Re: Re: [PATCH] [MIPS] Fix PR target/91769

[Paul Hua]

Hi:

The testsuite has a typo in "dg-final scan-assembler", s/mthc1/mtc1/.


On Fri, Oct 4, 2019 at 7:21 PM Dragan Mladjenovic
 wrote:
>
> On 01.10.2019. 21:37, Jeff Law wrote:
> > On 9/25/19 1:16 AM, Dragan Mladjenovic wrote:
> >> From: "Dragan Mladjenovic" 
> >>
> >> This fixes the issue by checking that addr's base reg is not part of dest
> >> multiword reg instead just checking the first reg of dest.
> >>
> >> gcc/ChangeLog:
> >>
> >> 2019-09-25  Dragan Mladjenovic  
> >>
> >>  PR target/91769
> >>  * config/mips/mips.c (mips_split_move): Use reg_overlap_mentioned_p
> >>  instead of REGNO equality check on addr.reg.
> >>
> >> gcc/testsuite/ChangeLog:
> >>
> >> 2019-09-25  Dragan Mladjenovic  
> >>
> >>  PR target/91769
> >>  * gcc.target/mips/pr91769.c: New test.
> > OK.  This would seem fine to backport to gcc-9 as well.  I don't think
> > gcc-8 had this code.
>
> Committed on trunk as r276525.
> Committed on gcc-9-branch as r276570 along with the r273174 as r276569.
>
> Best regards,
> Dragan
>
diff --git a/gcc/testsuite/gcc.target/mips/pr91769.c b/gcc/testsuite/gcc.target/mips/pr91769.c
index c9ad70d7f75..a1785d186d6 100644
--- a/gcc/testsuite/gcc.target/mips/pr91769.c
+++ b/gcc/testsuite/gcc.target/mips/pr91769.c
@@ -16,4 +16,4 @@ foo (void)
 }
 
 /* { dg-final { scan-assembler-not "lw\t\\\$4,0\\(\\\$5\\)\n\tlw\t\\\$5,4\\(\\\$5\\)\n\tldc1\t\\\$.*,0\\(\\\$5\\)" } } */
-/* { dg-final { scan-assembler "lw\t\\\$4,0\\(\\\$5\\)\n\tlw\t\\\$5,4\\(\\\$5\\)\n\tmtc1\t\\\$4,\\\$.*\n\tmthc1\t\\\$5,\\\$.*" } } */
+/* { dg-final { scan-assembler "lw\t\\\$4,0\\(\\\$5\\)\n\tlw\t\\\$5,4\\(\\\$5\\)\n\tmtc1\t\\\$4,\\\$.*\n\tmtc1\t\\\$5,\\\$.*" } } */

Re: [EXTERNAL]Re: Re: [PATCH] [MIPS] Fix PR target/91769

[Paul Hua]

Hi,

Thanks for explain that.
Add isa_rev=2 and -mfpxx to dg-options fix the fallout.

On Sun, Oct 6, 2019 at 8:03 PM Dragan Mladjenovic
 wrote:
>
>
>
> On 06.10.2019. 08:43, Paul Hua wrote:
> > Hi:
> >
> > The testsuite has a typo in "dg-final scan-assembler", s/mthc1/mtc1/.
> >
>
>
> Hi,
>
> I think I know what is happening here. My testing setup defaults to
> -mfpxx and yours probably to -mfp32. I should have probably tightened
> the test up to require R2 isa as well.
> Does adding isa_rev=2 and -mfpxx to dg-options fix the fallout form this
> test? I cannot check it right now, but I can send the fix for this
> tomorrow. Sorry for the inconvenience.
>
> Best regards,
> Dragan

Re: [PATCH][Middle-end]patch for fixing PR 86519

[Paul Hua]

Hi Qing:

>
> the change has been committed as:
> https://gcc.gnu.org/viewcvs/gcc?view=revision&revision=263563 
> <https://gcc.gnu.org/viewcvs/gcc?view=revision&revision=263563>
>
> Qing
>

The strcmpopt_6.c test still fails on mips64el target.

gcc.dg/strcmpopt_6.c: memcmp found 4 times
FAIL: gcc.dg/strcmpopt_6.c scan-assembler-times memcmp 2


The mips asm output have ".reloc" info.

-
ld  $5,%got_page(.LC0)($28)
ld  $25,%call16(memcmp)($28)
li  $6,3# 0x3
sd  $31,8($sp)
.reloc  1f,R_MIPS_JALR,memcmp
1:  jalr$25
daddiu  $5,$5,%got_ofst(.LC0)


scan-assembler find "4" times.

Thanks
Paul Hua

Re: [PATCH][Middle-end]patch for fixing PR 86519

[Paul Hua]

Hi, Qing,

The cfarm machine gcc23 can build mips64el successful, configure with
"../configure --prefix=/opt/gcc-9 MISSING=texinfo MAKEINFO=missing
--target=mips64el-linux-gnu --enable-languages=c,c++
On Tue, Aug 21, 2018 at 7:02 AM Qing Zhao  wrote:
>
> Hi, Paul,
>
> I was trying to repeat this issue on a mips machine today, but failed…
>
> the only mips machines I can access are those in gcc compile farm, I chose 
> gcc22, but failed to build GCC on this machine.
>
> do you know any other machine in gcc compile farm that can repeat this issue?
>
> thanks a lot.
>
> Qing
> > On Aug 17, 2018, at 10:43 PM, Paul Hua  wrote:
> >
> > Hi Qing:
> >
> >>
> >> the change has been committed as:
> >> https://gcc.gnu.org/viewcvs/gcc?view=revision&revision=263563 
> >> <https://gcc.gnu.org/viewcvs/gcc?view=revision&revision=263563>
> >>
> >> Qing
> >>
> >
> > The strcmpopt_6.c test still fails on mips64el target.
> >
> > gcc.dg/strcmpopt_6.c: memcmp found 4 times
> > FAIL: gcc.dg/strcmpopt_6.c scan-assembler-times memcmp 2
> >
> >
> > The mips asm output have ".reloc" info.
> >
> > -
> >ld  $5,%got_page(.LC0)($28)
> >ld  $25,%call16(memcmp)($28)
> >li  $6,3# 0x3
> >sd  $31,8($sp)
> >        .reloc  1f,R_MIPS_JALR,memcmp
> > 1:  jalr$25
> >daddiu  $5,$5,%got_ofst(.LC0)
> > 
> >
> > scan-assembler find "4" times.
> >
> > Thanks
> > Paul Hua
>

Re: [PATCH][Middle-end]patch for fixing PR 86519

[Paul Hua]

On Wed, Aug 22, 2018 at 2:15 AM Qing Zhao  wrote:
>
>
> > On Aug 21, 2018, at 8:07 AM, Paul Hua  wrote:
> >
> > Hi, Qing,
> >
> > The cfarm machine gcc23 can build mips64el successful, configure with
> > "../configure --prefix=/opt/gcc-9 MISSING=texinfo MAKEINFO=missing
> > --target=mips64el-linux-gnu --enable-languages=c,c++
>
> I got the same failure message on gcc23 as gcc22, even with the above 
> configure:
>
> /usr/bin/ld: failed to merge target specific data of file 
> /usr/lib32/libc.a(mremap.o)
> /usr/bin/ld: /usr/lib32/libc.a(libc-lowlevellock.o): ABI is incompatible with 
> that of the selected emulation
>
> not sure what’s the problem?
>

I just build all-gcc and make check.

./configure xxx
make all-gcc -j 2
make check-gcc RUNTESTFLAGS="dg.exp=strcmpopt_6.c"

It's enough to reproduce the regression.

Here is a mips port patch.

diff --git a/gcc/testsuite/gcc.dg/strcmpopt_6.c
b/gcc/testsuite/gcc.dg/strcmpopt_6.c
index 4c6de02824f..fa0ff9d1171 100644
--- a/gcc/testsuite/gcc.dg/strcmpopt_6.c
+++ b/gcc/testsuite/gcc.dg/strcmpopt_6.c
@@ -33,4 +33,5 @@ int main (void)

 }

-/* { dg-final { scan-assembler-times "memcmp" 2 } } */
+/* { dg-final { scan-assembler-times "memcmp" 2 { target { !
mips*-*-* } } } } */
+/* { dg-final { scan-assembler-times "memcmp" 4 { target { mips*-*-* } } } } */

Paul Hua

[PATCH 0/6] [MIPS] Reorganize the loongson march and extensions instructions set

[Paul Hua]

Hi:

This series patches reorganize the Loongson -march=xxx and Loongson
extensions instructions set.  For long time, the Loongson extensions
instructions set puts under -march=loongson3a option.  We can't
disable one of them when we need.

The patch (1) split Loongson  MultiMedia extensions Instructions (MMI)
from loongson3a, add -mloongson-mmi/-mno-loongson-mmi option for
enable/disable them.

The patch (2) split Loongson EXTensions (EXT) instructions from
loongson3a, add -mloongson-ext/-mno-loongson-ext option for
enable/disable them.

The patch (3) add Loongson EXTensions R2 (EXT2) instructions support,
add -mloongson-ext2/-mno-loongson-ext2 option for enable/disable them.

The patch (4) add Loongson 3A1000 processor support.  The gs464 is a
codename of 3A1000 microarchitecture.  Rename -march=loongson3a to
-march=gs464, Keep -march=loongson3a as an alias of -march=gs464 for
compatibility.

The patch (5) add Loongson 3A2000/3A3000 processor support.  Include
Loongson MMI, EXT, EXT2 instructions set.

The patch (6) add Loongson 2K1000 processor support. Include Loongson
MMI, EXT, EXT2 and msa instructions set.

The binutils patch has been upstreamed.

There are six patches in this set, as follows.
1) 0001-MIPS-Add-support-for-loongson-mmi-instructions.patch
2) 0002-MIPS-Add-support-for-Loongson-EXT-istructions.patch
3) 0003-MIPS-Add-support-for-Loongson-EXT2-istructions.patch
4) 0004-MIPS-Add-support-for-Loongson-3A1000-proccessor.patch
5) 0005-MIPS-Add-support-for-Loongson-3A2000-3A3000-proccess.patch
6) 0006-MIPS-Add-support-for-Loongson-2K1000-proccessor.patch

All patchs test under mips64el-linux-gnu no new regressions.

Ok for commit ?

Thanks,
Paul Hua

[PATCH 3/6] [MIPS] Add Loongson EXTensions R2 (EXT2) instructions support

[Paul Hua]

From 2871889515b9c7cc1af7bc93fe9e645b3adcd623 Mon Sep 17 00:00:00 2001
From: Chenghua Xu 
Date: Fri, 31 Aug 2018 11:55:48 +0800
Subject: [PATCH 3/6] [MIPS] Add support for Loongson EXT2 istructions.

gcc/
	* config/mips/mips.h (TARGET_CPU_CPP_BUILTINS): Define
	__mips_loongson_ext2, __mips_loongson_ext_rev=2.
	(ISA_HAS_CTZ_CTO): New, ture if TARGET_LOONGSON_EXT2.
	(ASM_SPEC): Add mloongson-ext2 and mno-loongson-ext2.
	* config/mips/mips.md: Add ctz to "define_attr "type"".
	(define_insn "ctz2"): New insn pattern.
	(define_insn "prefetch"): Include TARGET_LOONGSON_EXT2.
	* config/mips/mips.opt: Add -mloongson-ext2 option.

gcc/testsuite/
	* gcc.target/mips/loongson-ctz.c: New test.
	* gcc.target/mips/loongson-dctz.c: Likewise.
	* gcc.target/mips/mips.exp (mips_option_groups): Add
	-mloongson-ext2 option.
---
 gcc/config/mips/mips.h|   12 +
 gcc/config/mips/mips.md   |   31 +
 gcc/config/mips/mips.opt  |4 +++
 gcc/testsuite/gcc.target/mips/loongson-ctz.c  |   11 +
 gcc/testsuite/gcc.target/mips/loongson-dctz.c |   11 +
 gcc/testsuite/gcc.target/mips/mips.exp|1 +
 6 files changed, 65 insertions(+), 5 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/mips/loongson-ctz.c
 create mode 100644 gcc/testsuite/gcc.target/mips/loongson-dctz.c

diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h
index e0e78ba..b75646d 100644
--- a/gcc/config/mips/mips.h
+++ b/gcc/config/mips/mips.h
@@ -600,8 +600,16 @@ struct mips_cpu_info {
   if (TARGET_LOONGSON_EXT)		\
 	{\
 	  builtin_define ("__mips_loongson_ext");			\
+	  if (TARGET_LOONGSON_EXT2)	\
+	{\
+	  builtin_define ("__mips_loongson_ext2");			\
+	  builtin_define ("__mips_loongson_ext_rev=2");		\
+	}\
+	  else\
+	  builtin_define ("__mips_loongson_ext_rev=1");		\
 	}\
 	\
+	\
   /* Historical Octeon macro.  */	\
   if (TARGET_OCTEON)		\
 	builtin_define ("__OCTEON__");	\
@@ -1117,6 +1125,9 @@ struct mips_cpu_info {
 /* ISA has count leading zeroes/ones instruction (not implemented).  */
 #define ISA_HAS_CLZ_CLO		(mips_isa_rev >= 1 && !TARGET_MIPS16)
 
+/* ISA has count tailing zeroes/ones instruction (not implemented).  */
+#define ISA_HAS_CTZ_CTO		(TARGET_LOONGSON_EXT2)
+
 /* ISA has three operand multiply instructions that put
the high part in an accumulator: mulhi or mulhiu.  */
 #define ISA_HAS_MULHI		((TARGET_MIPS5400			 \
@@ -1362,6 +1373,7 @@ struct mips_cpu_info {
 %{mmsa} %{mno-msa} \
 %{mloongson-mmi} %{mno-loongson-mmi} \
 %{mloongson-ext} %{mno-loongson-ext} \
+%{mloongson-ext2} %{mno-loongson-ext2} \
 %{msmartmips} %{mno-smartmips} \
 %{mmt} %{mno-mt} \
 %{mfix-rm7000} %{mno-fix-rm7000} \
diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md
index 4b7a627..c8128d4 100644
--- a/gcc/config/mips/mips.md
+++ b/gcc/config/mips/mips.md
@@ -335,6 +335,7 @@
 ;; slt		set less than instructions
 ;; signext  sign extend instructions
 ;; clz		the clz and clo instructions
+;; ctz		the ctz and cto instructions
 ;; pop		the pop instruction
 ;; trap		trap if instructions
 ;; imul		integer multiply 2 operands
@@ -375,7 +376,7 @@
 (define_attr "type"
   "unknown,branch,jump,call,load,fpload,fpidxload,store,fpstore,fpidxstore,
prefetch,prefetchx,condmove,mtc,mfc,mthi,mtlo,mfhi,mflo,const,arith,logical,
-   shift,slt,signext,clz,pop,trap,imul,imul3,imul3nc,imadd,idiv,idiv3,move,
+   shift,slt,signext,clz,ctz,pop,trap,imul,imul3,imul3nc,imadd,idiv,idiv3,move,
fmove,fadd,fmul,fmadd,fdiv,frdiv,frdiv1,frdiv2,fabs,fneg,fcmp,fcvt,fsqrt,
frsqrt,frsqrt1,frsqrt2,dspmac,dspmacsat,accext,accmod,dspalu,dspalusat,
multi,atomic,syncloop,nop,ghost,multimem,
@@ -3149,6 +3150,23 @@
 ;;
 ;;  ...
 ;;
+;;  Count tailing zeroes.
+;;
+;;  ...
+;;
+
+(define_insn "ctz2"
+  [(set (match_operand:GPR 0 "register_operand" "=d")
+	(ctz:GPR (match_operand:GPR 1 "register_operand" "d")))]
+  "ISA_HAS_CTZ_CTO"
+  "ctz\t%0,%1"
+  [(set_attr "type" "ctz")
+   (set_attr "mode" "")])
+
+
+;;
+;;  ...
+;;
 ;;  Count number of set bits.
 ;;
 ;;  ...
@@ -7136,13 +7154,16 @@
 	 (match_operand 2 "const_int_operand" "n"))]
   "ISA_HAS_PREFETCH && TARGET_EXPLICIT_RELOCS"
 {
-  if (TARGET_LOONGSON_2EF || TARGET_LOONGSON_EXT)
+  if (TARGET_LOONGSON_2EF || TARGET_LOONGSON_EXT || TARGET_LOONGSON_EXT2)
 {
-  /* Loongson 2[ef] and Loongson 3a use load to $0 for prefetching.  */
+  /* Loongson ext2 implementation pref insnstructions.  */
+  if (TARGET_LOONGSON_EXT2)
+	return "pref\t%1, %a0";
+  /* Loongson 2[ef] and Loongson ext use load to $0 for prefetching.  */
   if (TARGET_64BIT)
-return "ld\t$0,%a0";
+	return "ld\t$0,%a0";
   else
-return "lw\t$0,%a0";
+	return "lw\t$0,%a0";
 }
   operands[1] = mips_prefetch_cookie (operands[

[PATCH 4/6] [MIPS] Add Loongson 3A1000 processor support.

[Paul Hua]

From 133e21aa8cd7a6f533840bf8255f8edd27543bb3 Mon Sep 17 00:00:00 2001
From: Chenghua Xu 
Date: Fri, 31 Aug 2018 14:08:01 +0800
Subject: [PATCH 4/6] [MIPS] Add support for Loongson 3A1000 proccessor.

gcc/
	* config/mips/loongson3a.md: Rename to ...
	* config/mips/gs464.md: ... here.
	* config/mips/mips-cpus.def: Define gs464; Add loongson3a
	as an alias of gs464 processor.
	* config/mips/mips-tables.opt: Regenerate.
	* config/mips/mips.c (mips_issue_rate): Use PROCESSOR_GS464
	instead of ROCESSOR_LOONGSON_3A.
	(mips_multipass_dfa_lookahead): Use TUNE_GS464 instread of
	TUNE_LOONGSON_3A.
	(mips_option_override): Enable MMI and EXT for gs464.
	* config/mips/mips.h: Rename TARGET_LOONGSON_3A to TARGET_GS464;
	Rename TUNE_LOONGSON_3A to TUNE_GS464.
	(MIPS_ISA_LEVEL_SPEC): Infer mips64r2 from gs464.
	(ISA_HAS_ODD_SPREG, ISA_AVOID_DIV_HILO, ISA_HAS_FUSED_MADD4,
	ISA_HAS_UNFUSED_MADD4): Use TARGET_GS464 instead of
	TARGET_LOONGSON_3A.
	* config/mips/mips.md: Include gs464.md instead of loongson3a.md.
	(processor): Add gs464;
	* doc/invoke.texi: Add gs464 to supported architectures.
---
 gcc/config/mips/gs464.md|  137 +++
 gcc/config/mips/loongson3a.md   |  137 ---
 gcc/config/mips/mips-cpus.def   |3 +-
 gcc/config/mips/mips-tables.opt |   19 +++--
 gcc/config/mips/mips.c  |   16 +++--
 gcc/config/mips/mips.h  |   15 ++--
 gcc/config/mips/mips.md |4 +-
 gcc/doc/invoke.texi |2 +-
 8 files changed, 170 insertions(+), 163 deletions(-)
 create mode 100644 gcc/config/mips/gs464.md
 delete mode 100644 gcc/config/mips/loongson3a.md

diff --git a/gcc/config/mips/gs464.md b/gcc/config/mips/gs464.md
new file mode 100644
index 000..82efb66
--- /dev/null
+++ b/gcc/config/mips/gs464.md
@@ -0,0 +1,137 @@
+;; Pipeline model for Loongson gs464 cores.
+
+;; Copyright (C) 2011-2018 Free Software Foundation, Inc.
+;;
+;; This file is part of GCC.
+;;
+;; GCC is free software; you can redistribute it and/or modify it
+;; under the terms of the GNU General Public License as published
+;; by the Free Software Foundation; either version 3, or (at your
+;; option) any later version.
+;;
+;; GCC is distributed in the hope that it will be useful, but WITHOUT
+;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+;; License for more details.
+;;
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3.  If not see
+;; .
+
+;; Uncomment the following line to output automata for debugging.
+;; (automata_option "v")
+
+;; Automaton for integer instructions.
+(define_automaton "gs464_a_alu")
+
+;; Automaton for floating-point instructions.
+(define_automaton "gs464_a_falu")
+
+;; Automaton for memory operations.
+(define_automaton "gs464_a_mem")
+
+;; Describe the resources.
+
+(define_cpu_unit "gs464_alu1" "gs464_a_alu")
+(define_cpu_unit "gs464_alu2" "gs464_a_alu")
+(define_cpu_unit "gs464_mem" "gs464_a_mem")
+(define_cpu_unit "gs464_falu1" "gs464_a_falu")
+(define_cpu_unit "gs464_falu2" "gs464_a_falu")
+
+;; Describe instruction reservations.
+
+(define_insn_reservation "gs464_arith" 1
+  (and (eq_attr "cpu" "gs464")
+   (eq_attr "type" "arith,clz,const,logical,
+			move,nop,shift,signext,slt"))
+  "gs464_alu1 | gs464_alu2")
+
+(define_insn_reservation "gs464_branch" 1
+  (and (eq_attr "cpu" "gs464")
+   (eq_attr "type" "branch,jump,call,condmove,trap"))
+  "gs464_alu1")
+
+(define_insn_reservation "gs464_mfhilo" 1
+  (and (eq_attr "cpu" "gs464")
+   (eq_attr "type" "mfhi,mflo,mthi,mtlo"))
+  "gs464_alu2")
+
+;; Operation imul3nc is fully pipelined.
+(define_insn_reservation "gs464_imul3nc" 5
+  (and (eq_attr "cpu" "gs464")
+   (eq_attr "type" "imul3nc"))
+  "gs464_alu2")
+
+(define_insn_reservation "gs464_imul" 7
+  (and (eq_attr "cpu" "gs464")
+   (eq_attr "type" "imul,imadd"))
+  "gs464_alu2 * 7")
+
+(define_insn_reservation "gs464_idiv_si" 12
+  (and (eq_attr "cpu" "gs464")
+   (and (eq_attr "type" "idiv")
+	(eq_attr "mode" "SI")))
+  "gs464_alu2 * 12")
+
+(define_insn_reservation "gs464_idiv_di" 25
+  (and (eq_attr "cpu" "gs464")
+   (and (eq_attr "type" "idiv")
+	(eq_attr "mode" "DI")))
+  "gs464_alu2 * 25")
+
+(define_insn_reservation "gs464_load" 3
+  (and (eq_attr "cpu" "gs464")
+   (eq_attr "type" "load"))
+  "gs464_mem")
+
+(define_insn_reservation "gs464_fpload" 4
+  (and (eq_attr "cpu" "gs464")
+   (eq_attr "type" "load,mfc,mtc"))
+  "gs464_mem")
+
+(define_insn_reservation "gs464_prefetch" 0
+  (and (eq_attr "cpu" "gs464")
+   (eq_attr "type" "prefetch,prefetchx"))
+  "gs464_mem")
+
+(define_insn_reservation "gs464_store" 0
+  (and (eq_attr "cpu" "gs464")
+   (eq_attr "type" "store,fpstore,fpidxstore"))
+  "gs464_mem")
+
+;; All the fp operations can be executed in FALU1.  Only

[PATCH 5/6] [MIPS] Add Loongson 3A2000/3A3000 processor support

[Paul Hua]

From 7c7599e473ef5a0e34c7ce192770eaaab7aa2efe Mon Sep 17 00:00:00 2001
From: Chenghua Xu 
Date: Mon, 3 Sep 2018 19:45:15 +0800
Subject: [PATCH 5/6] [MIPS] Add support for Loongson 3A2000/3A3000 proccessor.

gcc/
	* config/mips/gs464e.md: New.
	* config/mips/mips-cpus.def: Define gs464e.
	* config/mips/mips-tables.opt: Regenerate.
	* config/mips/mips.c (mips_rtx_cost_data): Add DEFAULT_COSTS for
	gs464e.
	(mips_issue_rate): Add support for gs464e.
	(mips_multipass_dfa_lookahead): Likewise.
	(mips_option_override): Enable MMI, EXT and EXT2 for gs464e.
	* config/mips/mips.h: Define TARGET_GS464E and TUNE_GS464E.
	(MIPS_ISA_LEVEL_SPEC): Infer mips64r2 from gs464e.
	* config/mips/mips.md: Include gs464e.md.
	(processor): Add gs464e.
	* doc/invoke.texi: Add gs464e to supported architectures.
---
 gcc/config/mips/gs464e.md   |  137 +++
 gcc/config/mips/mips-cpus.def   |1 +
 gcc/config/mips/mips-tables.opt |   19 +++--
 gcc/config/mips/mips.c  |   22 +--
 gcc/config/mips/mips.h  |4 +-
 gcc/config/mips/mips.md |2 +
 gcc/doc/invoke.texi |2 +-
 7 files changed, 172 insertions(+), 15 deletions(-)
 create mode 100644 gcc/config/mips/gs464e.md

diff --git a/gcc/config/mips/gs464e.md b/gcc/config/mips/gs464e.md
new file mode 100644
index 000..e2ef37d
--- /dev/null
+++ b/gcc/config/mips/gs464e.md
@@ -0,0 +1,137 @@
+;; Pipeline model for Loongson gs464e cores.
+
+;; Copyright (C) 2011-2018 Free Software Foundation, Inc.
+;;
+;; This file is part of GCC.
+;;
+;; GCC is free software; you can redistribute it and/or modify it
+;; under the terms of the GNU General Public License as published
+;; by the Free Software Foundation; either version 3, or (at your
+;; option) any later version.
+;;
+;; GCC is distributed in the hope that it will be useful, but WITHOUT
+;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+;; License for more details.
+;;
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3.  If not see
+;; .
+
+;; Uncomment the following line to output automata for debugging.
+;; (automata_option "v")
+
+;; Automaton for integer instructions.
+(define_automaton "gs464e_a_alu")
+
+;; Automaton for floating-point instructions.
+(define_automaton "gs464e_a_falu")
+
+;; Automaton for memory operations.
+(define_automaton "gs464e_a_mem")
+
+;; Describe the resources.
+
+(define_cpu_unit "gs464e_alu1" "gs464e_a_alu")
+(define_cpu_unit "gs464e_alu2" "gs464e_a_alu")
+(define_cpu_unit "gs464e_mem1" "gs464e_a_mem")
+(define_cpu_unit "gs464e_mem2" "gs464e_a_mem")
+(define_cpu_unit "gs464e_falu1" "gs464e_a_falu")
+(define_cpu_unit "gs464e_falu2" "gs464e_a_falu")
+
+;; Describe instruction reservations.
+
+(define_insn_reservation "gs464e_arith" 1
+  (and (eq_attr "cpu" "gs464e")
+   (eq_attr "type" "arith,clz,const,logical,
+			move,nop,shift,signext,slt"))
+  "gs464e_alu1 | gs464e_alu2")
+
+(define_insn_reservation "gs464e_branch" 1
+  (and (eq_attr "cpu" "gs464e")
+   (eq_attr "type" "branch,jump,call,condmove,trap"))
+  "gs464e_alu1 | gs464e_alu2")
+
+(define_insn_reservation "gs464e_mfhilo" 1
+  (and (eq_attr "cpu" "gs464e")
+   (eq_attr "type" "mfhi,mflo,mthi,mtlo"))
+  "gs464e_alu1 | gs464e_alu2")
+
+;; Operation imul3nc is fully pipelined.
+(define_insn_reservation "gs464e_imul3nc" 5
+  (and (eq_attr "cpu" "gs464e")
+   (eq_attr "type" "imul3nc"))
+  "gs464e_alu1 | gs464e_alu2")
+
+(define_insn_reservation "gs464e_imul" 7
+  (and (eq_attr "cpu" "gs464e")
+   (eq_attr "type" "imul,imadd"))
+  "gs464e_alu1 | gs464e_alu2")
+
+(define_insn_reservation "gs464e_idiv_si" 12
+  (and (eq_attr "cpu" "gs464e")
+   (and (eq_attr "type" "idiv")
+	(eq_attr "mode" "SI")))
+  "gs464e_alu1 | gs464e_alu2")
+
+(define_insn_reservation "gs464e_idiv_di" 25
+  (and (eq_attr "cpu" "gs464e")
+   (and (eq_attr "type" "idiv")
+	(eq_attr "mode" "DI")))
+  "gs464e_alu1 | gs464e_alu2")
+
+(define_insn_reservation "gs464e_load" 4
+  (and (eq_attr "cpu" "gs464e")
+   (eq_attr "type" "load"))
+  "gs464e_mem1 | gs464e_mem2")
+
+(define_insn_reservation "gs464e_fpload" 5
+  (and (eq_attr "cpu" "gs464e")
+   (eq_attr "type" "load,mfc,mtc"))
+  "gs464e_mem1 | gs464e_mem2")
+
+(define_insn_reservation "gs464e_prefetch" 0
+  (and (eq_attr "cpu" "gs464e")
+   (eq_attr "type" "prefetch,prefetchx"))
+  "gs464e_mem1 | gs464e_mem2")
+
+(define_insn_reservation "gs464e_store" 0
+  (and (eq_attr "cpu" "gs464e")
+   (eq_attr "type" "store,fpstore,fpidxstore"))
+  "gs464e_mem1 | gs464e_mem2")
+
+(define_insn_reservation "gs464e_fadd" 4
+  (and (eq_attr "cpu" "gs464e")
+   (eq_attr "type" "fadd,fmul,fmadd"))
+  "gs464e_falu1 | gs464e_falu2")
+
+(define_insn_reservation "gs464e_fcmp" 2
+  (and (eq_attr "cpu" "gs464e")
+   (eq_attr "type" "

[PATCH 6/6] [MIPS] Add Loongson 2K1000 processor support

[Paul Hua]

From a33230a02948e614e9c5c3a310cf9bdd0968aefc Mon Sep 17 00:00:00 2001
From: Chenghua Xu 
Date: Mon, 3 Sep 2018 20:01:54 +0800
Subject: [PATCH 6/6] [MIPS] Add support for Loongson 2K1000 proccessor.

gcc/
	* config/mips/gs264e.md: New.
	* config/mips/mips-cpus.def: Define gs264e.
	* config/mips/mips-tables.opt: Regenerate.
	* config/mips/mips.c (mips_rtx_cost_data): Add DEFAULT_COSTS for
	gs264e.
	(mips_issue_rate): Add support for gs264e.
	(mips_multipass_dfa_lookahead): Likewise.
	(mips_option_override): Enable MMI, EXT, EXT2 and MSA for gs264e.
	* config/mips/mips.h: Define TARGET_GS264E and TUNE_GS264E.
	(MIPS_ISA_LEVEL_SPEC): Infer mips64r2 from gs464e.
	* config/mips/mips.md: Include gs264e.md.
	(processor): Add gs264e.
	* config/mips/mips.opt (MSA): Use Mask instead of Var.
	* doc/invoke.texi: Add gs264e to supported architectures.
---
 gcc/config/mips/gs264e.md   |  133 +++
 gcc/config/mips/mips-cpus.def   |1 +
 gcc/config/mips/mips-tables.opt |   19 +++---
 gcc/config/mips/mips.c  |   29 ++---
 gcc/config/mips/mips.h  |6 +-
 gcc/config/mips/mips.md |2 +
 gcc/config/mips/mips.opt|2 +-
 gcc/doc/invoke.texi |1 +
 8 files changed, 174 insertions(+), 19 deletions(-)
 create mode 100644 gcc/config/mips/gs264e.md

diff --git a/gcc/config/mips/gs264e.md b/gcc/config/mips/gs264e.md
new file mode 100644
index 000..9b30bb5
--- /dev/null
+++ b/gcc/config/mips/gs264e.md
@@ -0,0 +1,133 @@
+;; Pipeline model for Loongson gs264e cores.
+
+;; Copyright (C) 2011-2018 Free Software Foundation, Inc.
+;;
+;; This file is part of GCC.
+;;
+;; GCC is free software; you can redistribute it and/or modify it
+;; under the terms of the GNU General Public License as published
+;; by the Free Software Foundation; either version 3, or (at your
+;; option) any later version.
+;;
+;; GCC is distributed in the hope that it will be useful, but WITHOUT
+;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+;; License for more details.
+;;
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3.  If not see
+;; .
+
+;; Uncomment the following line to output automata for debugging.
+;; (automata_option "v")
+
+;; Automaton for integer instructions.
+(define_automaton "gs264e_a_alu")
+
+;; Automaton for floating-point instructions.
+(define_automaton "gs264e_a_falu")
+
+;; Automaton for memory operations.
+(define_automaton "gs264e_a_mem")
+
+;; Describe the resources.
+
+(define_cpu_unit "gs264e_alu1" "gs264e_a_alu")
+(define_cpu_unit "gs264e_mem1" "gs264e_a_mem")
+(define_cpu_unit "gs264e_falu1" "gs264e_a_falu")
+
+;; Describe instruction reservations.
+
+(define_insn_reservation "gs264e_arith" 1
+  (and (eq_attr "cpu" "gs264e")
+   (eq_attr "type" "arith,clz,const,logical,
+			move,nop,shift,signext,slt"))
+  "gs264e_alu1")
+
+(define_insn_reservation "gs264e_branch" 1
+  (and (eq_attr "cpu" "gs264e")
+   (eq_attr "type" "branch,jump,call,condmove,trap"))
+  "gs264e_alu1")
+
+(define_insn_reservation "gs264e_mfhilo" 1
+  (and (eq_attr "cpu" "gs264e")
+   (eq_attr "type" "mfhi,mflo,mthi,mtlo"))
+  "gs264e_alu1")
+
+;; Operation imul3nc is fully pipelined.
+(define_insn_reservation "gs264e_imul3nc" 7
+  (and (eq_attr "cpu" "gs264e")
+   (eq_attr "type" "imul3nc"))
+  "gs264e_alu1")
+
+(define_insn_reservation "gs264e_imul" 7
+  (and (eq_attr "cpu" "gs264e")
+   (eq_attr "type" "imul,imadd"))
+  "gs264e_alu1")
+
+(define_insn_reservation "gs264e_idiv_si" 12
+  (and (eq_attr "cpu" "gs264e")
+   (and (eq_attr "type" "idiv")
+	(eq_attr "mode" "SI")))
+  "gs264e_alu1")
+
+(define_insn_reservation "gs264e_idiv_di" 25
+  (and (eq_attr "cpu" "gs264e")
+   (and (eq_attr "type" "idiv")
+	(eq_attr "mode" "DI")))
+  "gs264e_alu1")
+
+(define_insn_reservation "gs264e_load" 4
+  (and (eq_attr "cpu" "gs264e")
+   (eq_attr "type" "load"))
+  "gs264e_mem1")
+
+(define_insn_reservation "gs264e_fpload" 4
+  (and (eq_attr "cpu" "gs264e")
+   (eq_attr "type" "load,mfc,mtc"))
+  "gs264e_mem1")
+
+(define_insn_reservation "gs264e_prefetch" 0
+  (and (eq_attr "cpu" "gs264e")
+   (eq_attr "type" "prefetch,prefetchx"))
+  "gs264e_mem1")
+
+(define_insn_reservation "gs264e_store" 0
+  (and (eq_attr "cpu" "gs264e")
+   (eq_attr "type" "store,fpstore,fpidxstore"))
+  "gs264e_mem1")
+
+(define_insn_reservation "gs264e_fadd" 4
+  (and (eq_attr "cpu" "gs264e")
+   (eq_attr "type" "fadd,fmul,fmadd"))
+  "gs264e_falu1")
+
+(define_insn_reservation "gs264e_fcmp" 2
+  (and (eq_attr "cpu" "gs264e")
+   (eq_attr "type" "fabs,fcmp,fmove,fneg"))
+  "gs264e_falu1")
+
+(define_insn_reservation "gs264e_fcvt" 4
+  (and (eq_attr "cpu" "gs264e")
+   (eq_attr "type" "fcvt"))
+  "gs264e_falu1")
+
+(define_insn_reservation "gs264e_fdiv_sf"

[PATCH 1/6] [MIPS] Split Loongson EXTensions (EXT) instructions from loongson3a

[Paul Hua]

From fbe1d77d63f6224126ff4cdfef439182265b1682 Mon Sep 17 00:00:00 2001
From: Chenghua Xu 
Date: Fri, 31 Aug 2018 11:52:33 +0800
Subject: [PATCH 2/6] [MIPS] Add support for Loongson EXT istructions.

gcc/
	* config/mips/mips.c (mips_option_override): Default enable
	Loongson EXT on Loongson 3a target.
	* config/mips/mips.h (TARGET_CPU_CPP_BUILTINS): Add
	__mips_loongson_ext.
	(ASM_SPEC): Add mloongson-ext and mno-loongson-ext.
	* config/mips/mips.md (mul3, mul3_mul3_nohilo,
	div3, mod3, prefetch): Use TARGET_LOONGSON_EXT
	instead of TARGET_LOONGSON_3A.
	* config/mips/mips.opt: Add -mloongson-ext option.

gcc/testsuite/
	* gcc.target/mips/mips.exp (mips_option_groups): Add
	-mloongson-ext option.
---
 gcc/config/mips/mips.c |5 +
 gcc/config/mips/mips.h |7 +++
 gcc/config/mips/mips.md|   16 
 gcc/config/mips/mips.opt   |4 
 gcc/testsuite/gcc.target/mips/mips.exp |1 +
 5 files changed, 25 insertions(+), 8 deletions(-)

diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
index a804f70..019a6dc 100644
--- a/gcc/config/mips/mips.c
+++ b/gcc/config/mips/mips.c
@@ -20178,6 +20178,11 @@ mips_option_override (void)
 	  || (strcmp (mips_arch_info->name, "loongson3a") == 0)))
 target_flags |= MASK_LOONGSON_MMI;
 
+  /* Default to enable Loongson EXT on Longson 3a target.  */
+  if ((target_flags_explicit & MASK_LOONGSON_EXT) == 0
+  && (strcmp (mips_arch_info->name, "loongson3a") == 0))
+target_flags |= MASK_LOONGSON_EXT;
+
   /* .eh_frame addresses should be the same width as a C pointer.
  Most MIPS ABIs support only one pointer size, so the assembler
  will usually know exactly how big an .eh_frame address is.
diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h
index 3563c1d..e0e78ba 100644
--- a/gcc/config/mips/mips.h
+++ b/gcc/config/mips/mips.h
@@ -596,6 +596,12 @@ struct mips_cpu_info {
 	  builtin_define ("__mips_loongson_mmi");			\
 	}\
 	\
+  /* Whether Loongson EXT modes are enabled.  */			\
+  if (TARGET_LOONGSON_EXT)		\
+	{\
+	  builtin_define ("__mips_loongson_ext");			\
+	}\
+	\
   /* Historical Octeon macro.  */	\
   if (TARGET_OCTEON)		\
 	builtin_define ("__OCTEON__");	\
@@ -1355,6 +1361,7 @@ struct mips_cpu_info {
 %{mginv} %{mno-ginv} \
 %{mmsa} %{mno-msa} \
 %{mloongson-mmi} %{mno-loongson-mmi} \
+%{mloongson-ext} %{mno-loongson-ext} \
 %{msmartmips} %{mno-smartmips} \
 %{mmt} %{mno-mt} \
 %{mfix-rm7000} %{mno-fix-rm7000} \
diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md
index a88c1c5..4b7a627 100644
--- a/gcc/config/mips/mips.md
+++ b/gcc/config/mips/mips.md
@@ -1599,7 +1599,7 @@
 {
   rtx lo;
 
-  if (TARGET_LOONGSON_2EF || TARGET_LOONGSON_3A || ISA_HAS_R6MUL)
+  if (TARGET_LOONGSON_2EF || TARGET_LOONGSON_EXT || ISA_HAS_R6MUL)
 emit_insn (gen_mul3_mul3_nohilo (operands[0], operands[1],
 	   operands[2]));
   else if (ISA_HAS_MUL3)
@@ -1622,11 +1622,11 @@
   [(set (match_operand:GPR 0 "register_operand" "=d")
 (mult:GPR (match_operand:GPR 1 "register_operand" "d")
   (match_operand:GPR 2 "register_operand" "d")))]
-  "TARGET_LOONGSON_2EF || TARGET_LOONGSON_3A || ISA_HAS_R6MUL"
+  "TARGET_LOONGSON_2EF || TARGET_LOONGSON_EXT || ISA_HAS_R6MUL"
 {
   if (TARGET_LOONGSON_2EF)
 return "multu.g\t%0,%1,%2";
-  else if (TARGET_LOONGSON_3A)
+  else if (TARGET_LOONGSON_EXT)
 return "gsmultu\t%0,%1,%2";
   else
 return "mul\t%0,%1,%2";
@@ -3016,11 +3016,11 @@
   [(set (match_operand:GPR 0 "register_operand" "=&d")
 	(any_div:GPR (match_operand:GPR 1 "register_operand" "d")
 		 (match_operand:GPR 2 "register_operand" "d")))]
-  "TARGET_LOONGSON_2EF || TARGET_LOONGSON_3A || ISA_HAS_R6DIV"
+  "TARGET_LOONGSON_2EF || TARGET_LOONGSON_EXT || ISA_HAS_R6DIV"
   {
 if (TARGET_LOONGSON_2EF)
   return mips_output_division ("div.g\t%0,%1,%2", operands);
-else if (TARGET_LOONGSON_3A)
+else if (TARGET_LOONGSON_EXT)
   return mips_output_division ("gsdiv\t%0,%1,%2", operands);
 else
   return mips_output_division ("div\t%0,%1,%2", operands);
@@ -3032,11 +3032,11 @@
   [(set (match_operand:GPR 0 "register_operand" "=&d")
 	(any_mod:GPR (match_operand:GPR 1 "register_operand" "d")
 		 (match_operand:GPR 2 "register_operand" "d")))]
-  "TARGET_LOONGSON_2EF || TARGET_LOONGSON_3A || ISA_HAS_R6DIV"
+  "TARGET_LOONGSON_2EF || TARGET_LOONGSON_EXT || ISA_HAS_R6DIV"
   {
 if (TARGET_LOONGSON_2EF)
   return mips_output_division ("mod.g\t%0,%1,%2", operands);
-else if (TARGET_LOONGSON_3A)
+else if (TARGET_LOONGSON_EXT)
   return mips_output_division ("gsmod\t%0,%1,%2", operands);
 else
   return mips_output_division ("mod\t%0,%1,%2", operands);
@@ -7136,7 +7136,7 @@
 	 (match_operand 2 "const_int_operand" "n"))]
   "ISA_HAS_PREFETCH && TARGET_EXPLICIT_RELOCS"
 {
-  if (TARGET_LOONGSON_2EF || TARGET_L

Re: [PATCH 2/6] [MIPS] Split Loongson EXTensions (EXT) instructions from loongson3a

[Paul Hua]

sorry, it's should be [PATCH 2/6] not [PATCH 1/6] .

On Mon, Sep 3, 2018 at 8:30 PM Paul Hua  wrote:
>
>

Re: [PATCH v2 2/6] [MIPS] Split Loongson EXTensions (EXT) instructions from loongson3a

[Paul Hua]

On Mon, Sep 3, 2018 at 8:37 PM Paul Hua  wrote:
>
> sorry, it's should be [PATCH 2/6] not [PATCH 1/6] .
>
> On Mon, Sep 3, 2018 at 8:30 PM Paul Hua  wrote:
> >
> >

Hi:

The v2 patch add:
* gcc/doc/invoke.texi (-mloongson-ext): Document.

Thanks
Paul Hua
From e71973c5446ba529171f5934b92c3dc33842c612 Mon Sep 17 00:00:00 2001
From: Chenghua Xu 
Date: Fri, 31 Aug 2018 11:52:33 +0800
Subject: [PATCH 2/6] [MIPS] Add support for Loongson EXT istructions.

gcc/
	* config/mips/mips.c (mips_option_override): Default enable
	Loongson EXT on Loongson 3a target.
	* config/mips/mips.h (TARGET_CPU_CPP_BUILTINS): Add
	__mips_loongson_ext.
	(ASM_SPEC): Add mloongson-ext and mno-loongson-ext.
	* config/mips/mips.md (mul3, mul3_mul3_nohilo,
	div3, mod3, prefetch): Use TARGET_LOONGSON_EXT
	instead of TARGET_LOONGSON_3A.
	* config/mips/mips.opt (-mloongson-ext): Add option.
	* gcc/doc/invoke.texi (-mloongson-ext): Document.

gcc/testsuite/
	* gcc.target/mips/mips.exp (mips_option_groups): Add
	-mloongson-ext option.
---
 gcc/config/mips/mips.c |5 +
 gcc/config/mips/mips.h |7 +++
 gcc/config/mips/mips.md|   16 
 gcc/config/mips/mips.opt   |4 
 gcc/doc/invoke.texi|7 +++
 gcc/testsuite/gcc.target/mips/mips.exp |1 +
 6 files changed, 32 insertions(+), 8 deletions(-)

diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
index a804f70..019a6dc 100644
--- a/gcc/config/mips/mips.c
+++ b/gcc/config/mips/mips.c
@@ -20178,6 +20178,11 @@ mips_option_override (void)
 	  || (strcmp (mips_arch_info->name, "loongson3a") == 0)))
 target_flags |= MASK_LOONGSON_MMI;
 
+  /* Default to enable Loongson EXT on Longson 3a target.  */
+  if ((target_flags_explicit & MASK_LOONGSON_EXT) == 0
+  && (strcmp (mips_arch_info->name, "loongson3a") == 0))
+target_flags |= MASK_LOONGSON_EXT;
+
   /* .eh_frame addresses should be the same width as a C pointer.
  Most MIPS ABIs support only one pointer size, so the assembler
  will usually know exactly how big an .eh_frame address is.
diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h
index 3563c1d..e0e78ba 100644
--- a/gcc/config/mips/mips.h
+++ b/gcc/config/mips/mips.h
@@ -596,6 +596,12 @@ struct mips_cpu_info {
 	  builtin_define ("__mips_loongson_mmi");			\
 	}\
 	\
+  /* Whether Loongson EXT modes are enabled.  */			\
+  if (TARGET_LOONGSON_EXT)		\
+	{\
+	  builtin_define ("__mips_loongson_ext");			\
+	}\
+	\
   /* Historical Octeon macro.  */	\
   if (TARGET_OCTEON)		\
 	builtin_define ("__OCTEON__");	\
@@ -1355,6 +1361,7 @@ struct mips_cpu_info {
 %{mginv} %{mno-ginv} \
 %{mmsa} %{mno-msa} \
 %{mloongson-mmi} %{mno-loongson-mmi} \
+%{mloongson-ext} %{mno-loongson-ext} \
 %{msmartmips} %{mno-smartmips} \
 %{mmt} %{mno-mt} \
 %{mfix-rm7000} %{mno-fix-rm7000} \
diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md
index a88c1c5..4b7a627 100644
--- a/gcc/config/mips/mips.md
+++ b/gcc/config/mips/mips.md
@@ -1599,7 +1599,7 @@
 {
   rtx lo;
 
-  if (TARGET_LOONGSON_2EF || TARGET_LOONGSON_3A || ISA_HAS_R6MUL)
+  if (TARGET_LOONGSON_2EF || TARGET_LOONGSON_EXT || ISA_HAS_R6MUL)
 emit_insn (gen_mul3_mul3_nohilo (operands[0], operands[1],
 	   operands[2]));
   else if (ISA_HAS_MUL3)
@@ -1622,11 +1622,11 @@
   [(set (match_operand:GPR 0 "register_operand" "=d")
 (mult:GPR (match_operand:GPR 1 "register_operand" "d")
   (match_operand:GPR 2 "register_operand" "d")))]
-  "TARGET_LOONGSON_2EF || TARGET_LOONGSON_3A || ISA_HAS_R6MUL"
+  "TARGET_LOONGSON_2EF || TARGET_LOONGSON_EXT || ISA_HAS_R6MUL"
 {
   if (TARGET_LOONGSON_2EF)
 return "multu.g\t%0,%1,%2";
-  else if (TARGET_LOONGSON_3A)
+  else if (TARGET_LOONGSON_EXT)
 return "gsmultu\t%0,%1,%2";
   else
 return "mul\t%0,%1,%2";
@@ -3016,11 +3016,11 @@
   [(set (match_operand:GPR 0 "register_operand" "=&d")
 	(any_div:GPR (match_operand:GPR 1 "register_operand" "d")
 		 (match_operand:GPR 2 "register_operand" "d")))]
-  "TARGET_LOONGSON_2EF || TARGET_LOONGSON_3A || ISA_HAS_R6DIV"
+  "TARGET_LOONGSON_2EF || TARGET_LOONGSON_EXT || ISA_HAS_R6DIV"
   {
 if (TARGET_LOONGSON_2EF)
   return mips_output_division ("div.g\t%0,%1,%2", operands);
-else if (TARGET_LOONGSON_3A)
+else if (TARGET_LOONGSON_EXT)
   return mips_output_division ("gsdiv\t%0,%1,%2", operands);
 else
   return mips_output_division ("div\t%0,%1,%2", operands);
@@ -3032,11 +3032,11 @@
   [(set (match_operand:GPR 0 "register_operand" "=&d"

Re: [PATCH v2 3/6] [MIPS] Add Loongson EXTensions R2 (EXT2) instructions support

[Paul Hua]

On Mon, Sep 3, 2018 at 8:32 PM Paul Hua  wrote:
>
>
Hi:

The v2 patch add:
* gcc/doc/invoke.texi (-mloongson-ext2): Document.

Thanks
Paul Hua
From 6c20a2a9a61058ee7d97d0d01238514ed96b60fd Mon Sep 17 00:00:00 2001
From: Chenghua Xu 
Date: Fri, 31 Aug 2018 11:55:48 +0800
Subject: [PATCH 3/6] [MIPS] Add support for Loongson EXT2 istructions.

gcc/
	* config/mips/mips.h (TARGET_CPU_CPP_BUILTINS): Define
	__mips_loongson_ext2, __mips_loongson_ext_rev=2.
	(ISA_HAS_CTZ_CTO): New, ture if TARGET_LOONGSON_EXT2.
	(ASM_SPEC): Add mloongson-ext2 and mno-loongson-ext2.
	* config/mips/mips.md: Add ctz to "define_attr "type"".
	(define_insn "ctz2"): New insn pattern.
	(define_insn "prefetch"): Include TARGET_LOONGSON_EXT2.
	* config/mips/mips.opt (-mloongson-ext2): Add option.
	* gcc/doc/invoke.texi (-mloongson-ext2): Document.

gcc/testsuite/
	* gcc.target/mips/loongson-ctz.c: New test.
	* gcc.target/mips/loongson-dctz.c: Likewise.
	* gcc.target/mips/mips.exp (mips_option_groups): Add
	-mloongson-ext2 option.
---
 gcc/config/mips/mips.h|   12 +
 gcc/config/mips/mips.md   |   31 +
 gcc/config/mips/mips.opt  |4 +++
 gcc/doc/invoke.texi   |7 +
 gcc/testsuite/gcc.target/mips/loongson-ctz.c  |   11 +
 gcc/testsuite/gcc.target/mips/loongson-dctz.c |   11 +
 gcc/testsuite/gcc.target/mips/mips.exp|1 +
 7 files changed, 72 insertions(+), 5 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/mips/loongson-ctz.c
 create mode 100644 gcc/testsuite/gcc.target/mips/loongson-dctz.c

diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h
index e0e78ba..b75646d 100644
--- a/gcc/config/mips/mips.h
+++ b/gcc/config/mips/mips.h
@@ -600,8 +600,16 @@ struct mips_cpu_info {
   if (TARGET_LOONGSON_EXT)		\
 	{\
 	  builtin_define ("__mips_loongson_ext");			\
+	  if (TARGET_LOONGSON_EXT2)	\
+	{\
+	  builtin_define ("__mips_loongson_ext2");			\
+	  builtin_define ("__mips_loongson_ext_rev=2");		\
+	}\
+	  else\
+	  builtin_define ("__mips_loongson_ext_rev=1");		\
 	}\
 	\
+	\
   /* Historical Octeon macro.  */	\
   if (TARGET_OCTEON)		\
 	builtin_define ("__OCTEON__");	\
@@ -1117,6 +1125,9 @@ struct mips_cpu_info {
 /* ISA has count leading zeroes/ones instruction (not implemented).  */
 #define ISA_HAS_CLZ_CLO		(mips_isa_rev >= 1 && !TARGET_MIPS16)
 
+/* ISA has count tailing zeroes/ones instruction (not implemented).  */
+#define ISA_HAS_CTZ_CTO		(TARGET_LOONGSON_EXT2)
+
 /* ISA has three operand multiply instructions that put
the high part in an accumulator: mulhi or mulhiu.  */
 #define ISA_HAS_MULHI		((TARGET_MIPS5400			 \
@@ -1362,6 +1373,7 @@ struct mips_cpu_info {
 %{mmsa} %{mno-msa} \
 %{mloongson-mmi} %{mno-loongson-mmi} \
 %{mloongson-ext} %{mno-loongson-ext} \
+%{mloongson-ext2} %{mno-loongson-ext2} \
 %{msmartmips} %{mno-smartmips} \
 %{mmt} %{mno-mt} \
 %{mfix-rm7000} %{mno-fix-rm7000} \
diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md
index 4b7a627..c8128d4 100644
--- a/gcc/config/mips/mips.md
+++ b/gcc/config/mips/mips.md
@@ -335,6 +335,7 @@
 ;; slt		set less than instructions
 ;; signext  sign extend instructions
 ;; clz		the clz and clo instructions
+;; ctz		the ctz and cto instructions
 ;; pop		the pop instruction
 ;; trap		trap if instructions
 ;; imul		integer multiply 2 operands
@@ -375,7 +376,7 @@
 (define_attr "type"
   "unknown,branch,jump,call,load,fpload,fpidxload,store,fpstore,fpidxstore,
prefetch,prefetchx,condmove,mtc,mfc,mthi,mtlo,mfhi,mflo,const,arith,logical,
-   shift,slt,signext,clz,pop,trap,imul,imul3,imul3nc,imadd,idiv,idiv3,move,
+   shift,slt,signext,clz,ctz,pop,trap,imul,imul3,imul3nc,imadd,idiv,idiv3,move,
fmove,fadd,fmul,fmadd,fdiv,frdiv,frdiv1,frdiv2,fabs,fneg,fcmp,fcvt,fsqrt,
frsqrt,frsqrt1,frsqrt2,dspmac,dspmacsat,accext,accmod,dspalu,dspalusat,
multi,atomic,syncloop,nop,ghost,multimem,
@@ -3149,6 +3150,23 @@
 ;;
 ;;  ...
 ;;
+;;  Count tailing zeroes.
+;;
+;;  ...
+;;
+
+(define_insn "ctz2"
+  [(set (match_operand:GPR 0 "register_operand" "=d")
+	(ctz:GPR (match_operand:GPR 1 "register_operand" "d")))]
+  "ISA_HAS_CTZ_CTO"
+  "ctz\t%0,%1"
+  [(set_attr "type" "ctz")
+   (set_attr "mode" "")])
+
+
+;;
+;;  ...
+;;
 ;;  Count number of set bits.
 ;;
 ;;  ...
@@ -7136,13 +7154,16 @@
 	 (match_operand 2 "const_int_operand" "n"))]
   "ISA_HAS_PREFETCH && TARGET_EXPLICIT_RELOCS"
 {
-  if (TARGET_LOONGSON_2EF || TARGET_LOONGSON_EXT)
+  if (TARGET_LOONGSON_2EF || 

Re: [PATCH 0/6] [MIPS] Reorganize the loongson march and extensions instructions set

[Paul Hua]

Hi Joseph,

On Tue, Sep 4, 2018 at 12:21 AM Joseph Myers  wrote:
>
> Each patch adding a new command-line option needs to add documentation of
> that option to invoke.texi.  As far as I can see the patches document new
> CPU names but not new options.

Thanks for catch that, The v2 patch added.


> --
> Joseph S. Myers
> jos...@codesourcery.com

Re: [PATCH v2 1/6] [MIPS] Split Loongson (MMI) from loongson3a

[Paul Hua]

Hi Terry,

Thanks for your comments.
>
> For the new files, I think the copyright year should be just 2018.
>
The loongson-mmi.md is a renamed file from loongson.md, I think the
copyright year should be include the old file.

But in gs464e.md and gs264e.md, the copyright years will be just 2018,
I will update.

Paul

[PATCH,Testsuite] Check split_stack is ok for target in tree-prof/split-1.c

[Paul Hua]

Hi:

tree-prof/split-1.c use -fsplit-stack in dg-options but not check is
ok for target.
This patch add "dg-require-effective-target split_stack"  for it.

Ok for commit ?


Paul.


ChangeLog
2017-06-11  Chenghua Xu 

* gcc.dg/tree-prof/split-1.c: Require split_stack support.
diff --git a/gcc/testsuite/gcc.dg/tree-prof/split-1.c b/gcc/testsuite/gcc.dg/tree-prof/split-1.c
index a42fccf..4b90b63 100644
--- a/gcc/testsuite/gcc.dg/tree-prof/split-1.c
+++ b/gcc/testsuite/gcc.dg/tree-prof/split-1.c
@@ -1,6 +1,7 @@
 /* Test case that we don't get a link-time error when using
-fsplit-stack with -freorder-blocks-and-partition.  */
 /* { dg-require-effective-target freorder } */
+/* { dg-require-effective-target split_stack } */
 /* { dg-options "-O2 -fsplit-stack" } */
 
 extern unsigned int sleep (unsigned int);

Re: [PATCH] Fix new split-1.c testcase

[Paul Hua]

>
> [ Paul Hua sent a patch adding split_stack already, it was OKed, but
> it is not committed yet, fwiw ].
>

I saw this, so not commit my patch.

Paul.

Re: [PATCH] Enhance dump_probability function.

[Paul Hua]

New "ERROR: (DejaGnu)" on mips64el target.

my DejaGnu version is 1.5.1.

1)
make check-gcc RUNTESTFLAGS="tree-ssa.exp=builtin-sprintf-2.c"
...
ERROR: (DejaGnu) proc "^:\\" does not exist.
The error code is TCL LOOKUP COMMAND ^:\\
The info on the error is:
invalid command name "^:\"
while executing
"::tcl_unknown ^:\\"
("uplevel" body line 1)
invoked from within
"uplevel 1 ::tcl_unknown $args"
...

2)
make check-gcc RUNTESTFLAGS="tree-ssa.exp=vrp101.c"
...
ERROR: (DejaGnu) proc "^:\\" does not exist.
The error code is TCL LOOKUP COMMAND ^:\\
The info on the error is:
invalid command name "^:\"
while executing
"::tcl_unknown ^:\\"
("uplevel" body line 1)
invoked from within
"uplevel 1 ::tcl_unknown $args"
...

I don't known how to debug this, any advice ?

Paul.


On Tue, Jun 13, 2017 at 4:14 PM, Martin Liška  wrote:
> Hi.
>
> This is pre-approved patch that displays edge counts in dump files:
>
> ...
>   _85 = _83 + _84;
>   len_86 = SQRT (_85);
>   if (_85 u>= 0.0)
> goto ; [99.00%] [count: 778568]
>   else
> goto ; [1.00%] [count: 7864]
>
>[0.01%] [count: 7864]:
>   sqrt (_85);
> ...
>
> That makes it possible to understand why a profile mismatch happens.
> Patch can bootstrap on ppc64le-redhat-linux and survives regression tests.
>
> Martin
>
> gcc/ChangeLog:
>
> 2017-06-12  Martin Liska  
>
> * gimple-pretty-print.c (dump_probability): Add new argument.
> (dump_edge_probability): Dump both probability and count.
> (dump_gimple_label): Likewise.
> (dump_gimple_bb_header): Likewise.
>
> gcc/testsuite/ChangeLog:
>
> 2017-06-12  Martin Liska  
>
> * gcc.dg/tree-ssa/builtin-sprintf-2.c: Adjust scanned pattern.
> * gcc.dg/tree-ssa/dump-2.c: Likewise.
> * gcc.dg/tree-ssa/vrp101.c: Likewise.
> ---
>  gcc/gimple-pretty-print.c | 22 ++
>  gcc/testsuite/gcc.dg/tree-ssa/builtin-sprintf-2.c |  4 ++--
>  gcc/testsuite/gcc.dg/tree-ssa/dump-2.c|  2 +-
>  gcc/testsuite/gcc.dg/tree-ssa/vrp101.c|  2 +-
>  4 files changed, 18 insertions(+), 12 deletions(-)
>
>

[PATCH,MIPS] Fix pr86067 ICE: scal-to-vec1.c:86:1: error: unrecognizable insn with -march=loongson3a

[Paul Hua]

Hi:

The gcc.c-torture/execute/scal-to-vec1.c  trigger a gcc ICE bug.

It's a mistake in define_expand vec_setv4hi in loongson.md file.

375 (define_expand "vec_setv4hi"
376   [(set (match_operand:V4HI 0 "register_operand" "=f")
377 (unspec:V4HI [(match_operand:V4HI 1 "register_operand" "f")
378   (match_operand:HI 2 "register_operand" "f")
379   (match_operand:SI 3 "const_0_to_3_operand" "")]
380  UNSPEC_LOONGSON_PINSRH))]
381   "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS"
382 {
383   rtx ext = gen_reg_rtx (SImode);
384   emit_move_insn (ext, gen_lowpart (SImode, operands[1]));
385   operands[1] = ext;
386 })

The line 384 gen_lowpart the operands[1], should be gen_lowpart
operands[2], cause the operands[2] are HImode.


The attached patch fixed this bug.

Bootstrapped and reg-tested on mips64el-unknown-linux-gnu.
Ok for commit ?


---
2018-03-24  Chenghua Xu 

PR c/target 86076
* gcc/config/mips/loongson.md (vec_setv4hi): Gen_lowpart  for operands[2]
  instead of operands[1].
diff --git a/gcc/config/mips/loongson.md b/gcc/config/mips/loongson.md
index 38912ac..14794d3 100644
--- a/gcc/config/mips/loongson.md
+++ b/gcc/config/mips/loongson.md
@@ -381,8 +381,8 @@
   "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS"
 {
   rtx ext = gen_reg_rtx (SImode);
-  emit_move_insn (ext, gen_lowpart (SImode, operands[1]));
-  operands[1] = ext;
+  emit_move_insn (ext, gen_lowpart (SImode, operands[2]));
+  operands[2] = ext;
 })
 
 ;; Multiply and add packed integers.

Re: [PATCH,MIPS] Fix pr86067 ICE: scal-to-vec1.c:86:1: error: unrecognizable insn with -march=loongson3a

[Paul Hua]

Thanks for your comments, commited as r261538.

Paul Hua

On Tue, Jun 12, 2018 at 8:09 PM, Matthew Fortune  wrote:
> Paul Hua  writes:
>> The gcc.c-torture/execute/scal-to-vec1.c  trigger a gcc ICE bug.
>>
>> It's a mistake in define_expand vec_setv4hi in loongson.md file.
>>
>> 375 (define_expand "vec_setv4hi"
>> 376   [(set (match_operand:V4HI 0 "register_operand" "=f")
>> 377 (unspec:V4HI [(match_operand:V4HI 1 "register_operand" "f")
>> 378   (match_operand:HI 2 "register_operand" "f")
>> 379   (match_operand:SI 3 "const_0_to_3_operand"
>> "")]
>> 380  UNSPEC_LOONGSON_PINSRH))]
>> 381   "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS"
>> 382 {
>> 383   rtx ext = gen_reg_rtx (SImode);
>> 384   emit_move_insn (ext, gen_lowpart (SImode, operands[1]));
>> 385   operands[1] = ext;
>> 386 })
>>
>> The line 384 gen_lowpart the operands[1], should be gen_lowpart
>> operands[2], cause the operands[2] are HImode.
>>
>>
>> The attached patch fixed this bug.
>>
>> Bootstrapped and reg-tested on mips64el-unknown-linux-gnu.
>> Ok for commit ?
>>
>>
>> ---
>
> Hi Paul,
>
> This looks good, just one issue with the changelog entry. The entry
> would go in the gcc/ChangeLog file and the path is then relative to
> the gcc/ directory. The PR should be referenced as target/:
>
> 2018-03-24  Chenghua Xu 
>
> PR target/86076
> * config/mips/loongson.md (vec_setv4hi): Gen_lowpart for
> operands[2] instead of operands[1].
>
> OK to commit, thanks for finding and fixing. This has been broken
> since 2011!
>
> Matthew
>

Re: [PATCH] Fix -fcompare-debug failure on pr84146.c (PR target/84146)

[Paul Hua]

Hi Jakub:

It's introduce a regression on mips target.
see https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84623.

Paul hua


On Thu, Feb 8, 2018 at 6:36 AM, Jakub Jelinek  wrote:
> Hi!
>
> Unfortunately, seems my rest_of_insert_endbranch fix doesn't fix
> -fcompare-debug on the testcase, when adding the endbr after the setjmp
> call with no note in between, we add it into the same bb as the setjmp call,
> while when adding it with -g with NOTE_INSN_CALL_ARG_LOCATION, which is
> already outside of the bb, we add it outside of bb.
>
> This patch fixes it by removing lots of code:
>  22 files changed, 50 insertions(+), 205 deletions(-)
> instead of sticking the call arg location info into a separate note that
> is required to be adjacent to the call and thus requires lots of special
> cases everywhere we emit it as a REG_CALL_ARG_LOCATION note in REG_NOTES
> directly on the call.
> All we need to ensure is that we remove that reg note before emitting
> -fcompare-debug final insns dump, and need to unshare the rtl in there
> (apparently rtl sharing verification ignores
> NOTE_INSN_{CALL_ARG,VAR}_LOCATION notes, but of course not REG_NOTES).
>
> Bootstrapped/regtested on x86_64-linux and i686-linux, ok for trunk?
>
> 2018-02-07  Jakub Jelinek  
>
> PR target/84146
> * reg-notes.def (REG_CALL_ARG_LOCATION): New reg note.
> * insn-notes.def (NOTE_INSN_CALL_ARG_LOCATION): Remove.
> * var-tracking.c (emit_note_insn_var_location): Remove all references
> to NOTE_INSN_CALL_ARG_LOCATION.
> (emit_notes_in_bb): Emit arguments as REG_CALL_ARG_LOCATION note on
> the CALL_INSN rather than separate NOTE_INSN_CALL_ARG_LOCATION note.
> Use copy_rtx_if_shared.
> * dwarf2out.c (gen_subprogram_die): Use XEXP with 0 instead of
> NOTE_VAR_LOCATION on ca_loc->call_arg_loc_note.
> (dwarf2out_var_location): Remove handling of
> NOTE_INSN_CALL_ARG_LOCATION, instead handle REG_CALL_ARG_LOCATION note
> on call_insn.
> * final.c (final_scan_insn): Remove all references to
> NOTE_INSN_CALL_ARG_LOCATION.
> (rest_of_clean_state): Likewise.  Remove REG_CALL_ARG_LOCATION notes
> before dumping final insns.
> * except.c (emit_note_eh_region_end): Remove all references to
> NOTE_INSN_CALL_ARG_LOCATION.
> * config/alpha/alpha.c (alpha_pad_function_end): Likewise.
> * config/c6x/c6x.c (c6x_gen_bundles): Likewise.
> * config/arc/arc.c (hwloop_optimize): Likewise.
> * config/arm/arm.c (create_fix_barrier): Likewise.
> * config/s390/s390.c (s390_chunkify_start): Likewise.
> * config/sh/sh.c (find_barrier): Likewise.
> * config/i386/i386.c (rest_of_insert_endbranch,
> ix86_seh_fixup_eh_fallthru): Likewise.
> * config/xtensa/xtensa.c (hwloop_optimize): Likewise.
> * config/iq2000/iq2000.c (final_prescan_insn): Likewise.
> * config/frv/frv.c (frv_function_prologue): Likewise.
> * emit-rtl.c (try_split): Likewise.  Copy over REG_CALL_ARG_LOCATION
> reg note.
> (note_outside_basic_block_p): Remove all references to
> NOTE_INSN_CALL_ARG_LOCATION.
> * gengtype.c (adjust_field_rtx_def): Likewise.
> * print-rtl.c (rtx_writer::print_rtx_operand_code_0, print_insn):
> Likewise.
> * jump.c (cleanup_barriers, delete_related_insns): Likewise.
> * cfgrtl.c (force_nonfallthru_and_redirect): Likewise.
>
> * gcc.target/i386/pr84146.c: Add -fcompare-debug to dg-options.
>
> --- gcc/reg-notes.def.jj2018-01-03 10:19:55.239533971 +0100
> +++ gcc/reg-notes.def   2018-02-07 16:40:03.800915206 +0100
> @@ -239,3 +239,6 @@ REG_NOTE (CALL_DECL)
> when a called function has a 'notrack' attribute.  This note is used by 
> the
> compiler when the option -fcf-protection=branch is specified.  */
>  REG_NOTE (CALL_NOCF_CHECK)
> +
> +/* The values passed to callee, for debuginfo purposes.  */
> +REG_NOTE (CALL_ARG_LOCATION)
> --- gcc/insn-notes.def.jj   2018-01-03 10:19:55.669534040 +0100
> +++ gcc/insn-notes.def  2018-02-07 16:40:03.800915206 +0100
> @@ -65,9 +65,6 @@ INSN_NOTE (EH_REGION_END)
>  /* The location of a variable.  */
>  INSN_NOTE (VAR_LOCATION)
>
> -/* The values passed to callee.  */
> -INSN_NOTE (CALL_ARG_LOCATION)
> -
>  /* The beginning of a statement.  */
>  INSN_NOTE (BEGIN_STMT)
>
> --- gcc/var-tracking.c.jj   2018-02-07 13:11:26.950985542 +0100
> +++ gcc/var-tracking.c  2018-02-07 16:44:10.810478942 +0100
> @@ -8860,14 +8860,12 @@ emit_note_insn_var_location (variable **
>/* Make sure that the call related notes com

Re: Patch ping (Re: [PATCH PR82965/PR83991]Fix invalid profile count in vectorization peeling)

[Paul Hua]

It's looks fixed
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=82965#c12  on mips64el.

Thanks.

On Mon, Feb 26, 2018 at 8:02 PM, Bin.Cheng  wrote:
> Ping^2
>
> Thanks,
> bin
>
> On Mon, Feb 19, 2018 at 5:14 PM, Jakub Jelinek  wrote:
>> Hi!
>>
>> Honza, do you think you could have a look at this P1 fix?
>>
>> Thanks.
>>
>> On Wed, Jan 31, 2018 at 10:03:51AM +, Bin Cheng wrote:
>>> Hi,
>>> This patch fixes invalid profile count information in vectorization peeling.
>>> Current implementation is a bit confusing for me since it tries to compute
>>> an overall probability based on scaling probability and change of estimated
>>> niters.  This patch does it in two steps.  Firstly it does the scaling, then
>>> it adjusts to new estimated niters by simply adjusting loop's latch count
>>> information; scaling the loop's count information by the proportion
>>> new_estimated_niters/old_estimate_niters.  Of course we have to adjust loop
>>> latch's count information back after scaling.
>>>
>>> Bootstrap and test on x86_64 and AArch64.  gcc.dg/vect/pr79347.c is fixed
>>> for both PR82965 and PR83991.  Is this OK?
>>>
>>> Thanks,
>>> bin
>>>
>>> 2018-01-30  Bin Cheng  
>>>
>>>   PR tree-optimization/82965
>>>   PR tree-optimization/83991
>>>   * cfgloopmanip.c (scale_loop_profile): Further scale loop's profile
>>>   information if the loop was predicted to iterate too many times.
>>
>>> diff --git a/gcc/cfgloopmanip.c b/gcc/cfgloopmanip.c
>>> index b9b76d8..1f560b8 100644
>>> --- a/gcc/cfgloopmanip.c
>>> +++ b/gcc/cfgloopmanip.c
>>> @@ -509,7 +509,7 @@ scale_loop_profile (struct loop *loop, 
>>> profile_probability p,
>>>   gcov_type iteration_bound)
>>>  {
>>>gcov_type iterations = expected_loop_iterations_unbounded (loop);
>>> -  edge e;
>>> +  edge e, preheader_e;
>>>edge_iterator ei;
>>>
>>>if (dump_file && (dump_flags & TDF_DETAILS))
>>> @@ -521,77 +521,66 @@ scale_loop_profile (struct loop *loop, 
>>> profile_probability p,
>>>  (int)iteration_bound, (int)iterations);
>>>  }
>>>
>>> +  /* Scale the probabilities.  */
>>> +  scale_loop_frequencies (loop, p);
>>> +
>>>/* See if loop is predicted to iterate too many times.  */
>>> -  if (iteration_bound && iterations > 0
>>> -  && p.apply (iterations) > iteration_bound)
>>> +  if (iteration_bound == 0 || iterations <= 0
>>> +  || p.apply (iterations) <= iteration_bound)
>>> +return;
>>> +
>>> +  e = single_exit (loop);
>>> +  preheader_e = loop_preheader_edge (loop);
>>> +  profile_count count_in = preheader_e->count ();
>>> +  if (e && preheader_e
>>> +  && count_in > profile_count::zero ()
>>> +  && loop->header->count.initialized_p ())
>>>  {
>>> -  /* Fixing loop profile for different trip count is not trivial; the 
>>> exit
>>> -  probabilities has to be updated to match and frequencies propagated 
>>> down
>>> -  to the loop body.
>>> -
>>> -  We fully update only the simple case of loop with single exit that is
>>> -  either from the latch or BB just before latch and leads from BB with
>>> -  simple conditional jump.   This is OK for use in vectorizer.  */
>>> -  e = single_exit (loop);
>>> -  if (e)
>>> - {
>>> -   edge other_e;
>>> -   profile_count count_delta;
>>> +  edge other_e;
>>> +  profile_count count_delta;
>>>
>>> -  FOR_EACH_EDGE (other_e, ei, e->src->succs)
>>> - if (!(other_e->flags & (EDGE_ABNORMAL | EDGE_FAKE))
>>> - && e != other_e)
>>> -   break;
>>> +  FOR_EACH_EDGE (other_e, ei, e->src->succs)
>>> + if (!(other_e->flags & (EDGE_ABNORMAL | EDGE_FAKE))
>>> + && e != other_e)
>>> +   break;
>>>
>>> -   /* Probability of exit must be 1/iterations.  */
>>> -   count_delta = e->count ();
>>> -   e->probability = profile_probability::always ()
>>> +  /* Probability of exit must be 1/iterations.  */
>>> +  count_delta = e->count ();
>>> +  e->probability = profile_probability::always ()
>>>   .apply_scale (1, iteration_bound);
>>> -   other_e->probability = e->probability.invert ();
>>> -   count_delta -= e->count ();
>>> -
>>> -   /* If latch exists, change its count, since we changed
>>> -  probability of exit.  Theoretically we should update everything 
>>> from
>>> -  source of exit edge to latch, but for vectorizer this is enough. 
>>>  */
>>> -   if (loop->latch
>>> -   && loop->latch != e->src)
>>> - {
>>> -   loop->latch->count += count_delta;
>>> - }
>>> - }
>>> +  other_e->probability = e->probability.invert ();
>>>
>>>/* Roughly speaking we want to reduce the loop body profile by the
>>>difference of loop iterations.  We however can do better if
>>>we look at the actual profile, if it is available.  */
>>> -  p = p.apply_scale (iteration_bound, iterations);
>>> -
>>> -  if (loop->header->

Re: Patch ping (Re: [PATCH PR82965/PR83991]Fix invalid profile count in vectorization peeling)

[Paul Hua]

On Fri, Mar 9, 2018 at 10:51 PM, Bin.Cheng  wrote:
> On Fri, Mar 9, 2018 at 10:25 AM, Paul Hua  wrote:
>> It's looks fixed
>> https://gcc.gnu.org/bugzilla/show_bug.cgi?id=82965#c12  on mips64el.
> Hmm, is it fixed? or is it exposed now on mips64el?  I read the latter
> from the comment.

It is fixed, Bootstrap and test passed on mips64el.

Thanks,

Paul Hua

> I think the issue is like explained, but haven't dug into when/why it
> is triggered in vect_peeling only for some targets.
> Honza asked couple questions about my patch offline, I will revisit
> the patch, see how to address
> his concern.
>
> Thanks,
> bin
>>
>> Thanks.
>>
>> On Mon, Feb 26, 2018 at 8:02 PM, Bin.Cheng  wrote:
>>> Ping^2
>>>
>>> Thanks,
>>> bin
>>>
>>> On Mon, Feb 19, 2018 at 5:14 PM, Jakub Jelinek  wrote:
>>>> Hi!
>>>>
>>>> Honza, do you think you could have a look at this P1 fix?
>>>>
>>>> Thanks.
>>>>
>>>> On Wed, Jan 31, 2018 at 10:03:51AM +, Bin Cheng wrote:
>>>>> Hi,
>>>>> This patch fixes invalid profile count information in vectorization 
>>>>> peeling.
>>>>> Current implementation is a bit confusing for me since it tries to compute
>>>>> an overall probability based on scaling probability and change of 
>>>>> estimated
>>>>> niters.  This patch does it in two steps.  Firstly it does the scaling, 
>>>>> then
>>>>> it adjusts to new estimated niters by simply adjusting loop's latch count
>>>>> information; scaling the loop's count information by the proportion
>>>>> new_estimated_niters/old_estimate_niters.  Of course we have to adjust 
>>>>> loop
>>>>> latch's count information back after scaling.
>>>>>
>>>>> Bootstrap and test on x86_64 and AArch64.  gcc.dg/vect/pr79347.c is fixed
>>>>> for both PR82965 and PR83991.  Is this OK?
>>>>>
>>>>> Thanks,
>>>>> bin
>>>>>
>>>>> 2018-01-30  Bin Cheng  
>>>>>
>>>>>   PR tree-optimization/82965
>>>>>   PR tree-optimization/83991
>>>>>   * cfgloopmanip.c (scale_loop_profile): Further scale loop's profile
>>>>>   information if the loop was predicted to iterate too many times.
>>>>
>>>>> diff --git a/gcc/cfgloopmanip.c b/gcc/cfgloopmanip.c
>>>>> index b9b76d8..1f560b8 100644
>>>>> --- a/gcc/cfgloopmanip.c
>>>>> +++ b/gcc/cfgloopmanip.c
>>>>> @@ -509,7 +509,7 @@ scale_loop_profile (struct loop *loop, 
>>>>> profile_probability p,
>>>>>   gcov_type iteration_bound)
>>>>>  {
>>>>>gcov_type iterations = expected_loop_iterations_unbounded (loop);
>>>>> -  edge e;
>>>>> +  edge e, preheader_e;
>>>>>edge_iterator ei;
>>>>>
>>>>>if (dump_file && (dump_flags & TDF_DETAILS))
>>>>> @@ -521,77 +521,66 @@ scale_loop_profile (struct loop *loop, 
>>>>> profile_probability p,
>>>>>  (int)iteration_bound, (int)iterations);
>>>>>  }
>>>>>
>>>>> +  /* Scale the probabilities.  */
>>>>> +  scale_loop_frequencies (loop, p);
>>>>> +
>>>>>/* See if loop is predicted to iterate too many times.  */
>>>>> -  if (iteration_bound && iterations > 0
>>>>> -  && p.apply (iterations) > iteration_bound)
>>>>> +  if (iteration_bound == 0 || iterations <= 0
>>>>> +  || p.apply (iterations) <= iteration_bound)
>>>>> +return;
>>>>> +
>>>>> +  e = single_exit (loop);
>>>>> +  preheader_e = loop_preheader_edge (loop);
>>>>> +  profile_count count_in = preheader_e->count ();
>>>>> +  if (e && preheader_e
>>>>> +  && count_in > profile_count::zero ()
>>>>> +  && loop->header->count.initialized_p ())
>>>>>  {
>>>>> -  /* Fixing loop profile for different trip count is not trivial; 
>>>>> the exit
>>>>> -  probabilities has to be updated to match and frequencies 
>>>>> propagated down
>>>>> -  to the loop body.
>&g

[PATCH/testsuite] Skip vect-strided-shift-1.c on MIPS with -mpaired-single option.

[Paul Hua]

Hi:

The vect-strided-shift-1.c test fails on MIPS target.

FAIL: gcc.dg/vect/vect-strided-shift-1.c  -mpaired-single
scan-tree-dump-times vect "vectorized 1 loops in function" 1 (found 0
times)
FAIL: gcc.dg/vect/vect-strided-shift-1.c -flto -ffat-lto-objects
-mpaired-single  scan-tree-dump-times vect "vectorized 1 loops in
function" 1 (found 0 times)

Because the MIPS paired single insns only support for float
operations, not suite for this test.
added dg-skip-if directives on it for skip -mpaired-single option.

Ok for commit ?

Paul Hua

ChangeLog entries:

gcc/testsuite/ChangeLog

2018-03-14  Chenghua Xu 

* gcc.dg/vect/vect-strided-shift-1.c: Add dg-skip-if for
MIPS with -mpaired-single directives.
diff --git a/gcc/testsuite/gcc.dg/vect/vect-strided-shift-1.c b/gcc/testsuite/gcc.dg/vect/vect-strided-shift-1.c
index b1ce2ec..dcae9c2 100644
--- a/gcc/testsuite/gcc.dg/vect/vect-strided-shift-1.c
+++ b/gcc/testsuite/gcc.dg/vect/vect-strided-shift-1.c
@@ -1,3 +1,4 @@
+/* { dg-skip-if "Skip for mips -mpaired-single" { mips*-*-* } { "-mpaired-single" } } */
 /* PR tree-optimization/65963.  */
 #include "tree-vect.h"
 

Re: [PATCH] MIPS/GCC: Mark text contents as code or data

[Paul Hua]

I noticed that data-sym-pool.c fails on -O0 flags.

-O0 output :
-cut--
frob:
.frame  $17,8,$31   # vars= 0, regs= 1/0, args= 0, gp= 0
.mask   0x0002,0
.fmask  0x,0
addiu   $sp,-8
sd  $17,0($sp)
move$17,$sp
lw  $2,$L4
move$sp,$17
ld  $17,0($sp)
addiu   $sp,8
jr  $31
.type   __pool_frob_3, @object
__pool_frob_3:
.align  2
$L3:
.word   __gnu_local_gp
$L4:
.word   305419896
.type   __pend_frob_3, @function
__pend_frob_3:
.insn
.endfrob
.size   frob, .-frob
.ident  "GCC: (gcc trunk r258495 mips64el o32 n32 n64) 8.0.1
20180313 (experimental)"
-end--

Is it expected ? maybe we should add skip-if  -O0 flags.

Paul Hua


On Thu, Nov 17, 2016 at 1:15 AM, Maciej W. Rozycki  wrote:
> On Tue, 15 Nov 2016, Matthew Fortune wrote:
>
>> I'm a little concerned the expected output tests may be fragile over
>> time but let's wait and see.
>
>  Indeed, but I'd rather see false negatives than false positives or no
> coverage at all.  And I hope the pieces of expected assembly quoted will
> help telling any false negatives and actual regressions apart very easily.
>
>> OK to commit.
>
>  Applied now, thanks for your review.
>
>   Maciej

Re: [committed] Fix ICE for missing header fix-it hints with overlarge #line directives (PR c/84852)

[Paul Hua]

Hi:

The fixits-pr84852-1.c fails on mips64el target.

FAIL: gcc.dg/fixits-pr84852-1.c (test for excess errors)
FAIL: gcc.dg/fixits-pr84852-1.c dg-regexp 25 not found:
".*fixits-pr84852.c:-812156810:25:"

see this patch:

diff --git a/gcc/testsuite/gcc.dg/fixits-pr84852-1.c
b/gcc/testsuite/gcc.dg/fixits-pr84852-1.c
index ed88434..98087ab 100644
--- a/gcc/testsuite/gcc.dg/fixits-pr84852-1.c
+++ b/gcc/testsuite/gcc.dg/fixits-pr84852-1.c
@@ -22,4 +22,4 @@ int foo (void) { return strlen(""); }
 #endif

 /* We need this, to consume a stray line marker for the bogus line.  */
-/* { dg-regexp ".*fixits-pr84852.c:-812156810:25:" } */
+/* { dg-regexp ".*fixits-pr84852-1.c:-812156810:25:" } */

Thanks.

On Wed, Mar 14, 2018 at 10:10 PM, David Malcolm  wrote:
> PR c/84852 reports an ICE inside diagnostic_show_locus when printing
> a diagnostic for a source file with a #line >= 2^31:
>
>   #line 77
>   int foo (void) { return strlen(""); }
>
> where we're attempting to print a fix-it hint at the top of the file
> and underline the "strlen" (two "line spans").
>
> The
>   #line 77
> won't fix within the 32-bit linenum_type, and is truncated from
>   0x1cf977871
> to
>0xcf977871
> i.e. 3482810481 in decimal.
>
> Such a #line is reported by -pedantic and -pedantic-errors, but we
> shouldn't ICE.
>
> The ICE is an assertion failure within layout::calculate_line_spans,
> where the line spans have not been properly sorted.
>
> The layout_ranges are stored as int, rather than linenum_type,
> giving line -812156815 for the error, and line 1 for the fix-it hint.
>
> However, line_span uses linenum_type rather than int.
>
> line_span::comparator compares these values as int, and hence
> decides that (linenum_type)3482810481 aka (int)-812156815 is less
> than line 1.
>
> This leads to this assertion failing in layout::calculate_line_spans:
>
> 1105  gcc_assert (next->m_first_line >= current->m_first_line);
>
> since it isn't the case that 1 >= 3482810481.
>
> The underlying problem is the mix of types for storing line numbers:
> in parts of libcpp and diagnostic-show-locus.c we use linenum_type;
> in other places (including libcpp's expanded_location) we use int.
>
> I looked at using linenum_type throughout, but doing so turned into
> a large patch, so this patch fixes the ICE in a less invasive way
> by merely using linenum_type more consistently just within
> diagnostic-show-locus.c, and fixing line_span::comparator to properly
> handle line numbers (and line number differences) >= 2^31, by using
> a new helper function for linenum_type differences, computing the
> difference using long long, and using the sign of the difference
> (as the difference might not fit in the "int" return type imposed
> by qsort).
>
> (The new testcases assume the host's "unsigned int" is 32 bits; is
> there anything we support where that isn't the case?)
>
> I can self-approve the libcpp, diagnostic-show-locus.c and input.c
> changes.
>
> As part of the selftests, I needed to add ASSERT_GT and ASSERT_LT
> to selftest.h; I'm treating those parts of the patch as "obvious".
>
> Successfully bootstrapped and regression-tested on x86_64-pc-linux-gnu;
> adds 14 PASS results to gcc.sum.
>
> Committed to trunk as r258526.
>
> gcc/ChangeLog:
> PR c/84852
> * diagnostic-show-locus.c (class layout_point): Convert m_line
> from int to linenum_type.
> (line_span::comparator): Use linenum "compare" function when
> comparing line numbers.
> (test_line_span): New function.
> (layout_range::contains_point): Convert param "row" from int to
> linenum_type.
> (layout_range::intersects_line_p): Likewise.
> (layout::will_show_line_p): Likewise.
> (layout::print_source_line): Likewise.
> (layout::should_print_annotation_line_p): Likewise.
> (layout::print_annotation_line): Likewise.
> (layout::print_leading_fixits): Likewise.
> (layout::annotation_line_showed_range_p): Likewise.
> (struct line_corrections): Likewise for field m_row.
> (line_corrections::line_corrections): Likewise for param "row".
> (layout::print_trailing_fixits): Likewise.
> (layout::get_state_at_point): Likewise.
> (layout::get_x_bound_for_row): Likewise.
> (layout::print_line): Likewise.
> (diagnostic_show_locus): Likewise for locals "last_line" and
> "row".
> (selftest::diagnostic_show_locus_c_tests): Call test_line_span.
> * input.c (selftest::test_linenum_comparisons): New function.
> (selftest::input_c_tests): Call it.
> * selftest.c (selftest::test_assertions): Test ASSERT_GT,
> ASSERT_GT_AT, ASSERT_LT, and ASSERT_LT_AT.
> * selftest.h (ASSERT_GT): New macro.
> (ASSERT_GT_AT): New macro.
> (ASSERT_LT): New macro.
> (ASSERT_LT_AT): New macro.
>
> gcc/testsuite/ChangeLog:
> PR c/84852
> * gcc.dg/fixits

[PATCH,Testsuite,MIPS] Fixing fix-r4000-n.c failure started with r255348

[Paul Hua]

Hi:

The fix-r4000-n.c test fails after r255348, cause the r255348 does not print
 "[length = NN]" but "[c=NN l=NN]".

The asm for fix-r4000-1.c.
before r255348:
...
 mult$4,$5# 10   mulsi3_r4000[length = 8]
 mflo$2
...
after r255348:
...
 mult$4,$5# 10   [c=40 l=8]  mulsi3_r4000
 mflo$2
...

So changes those tests for match new print styles.

The changes in patch for fix-r4000-1.c
 -/* { dg-final { scan-assembler-times "[concat
{\tmult\t\$[45],\$[45][^\n]+mulsi3_r4000[^\n]+\n\tmflo\t\$2\n}]" 2 } }
*/
+/* { dg-final { scan-assembler-times "[concat
{\tmult\t\$[45],\$[45][^\n]+mulsi3_r4000\n\tmflo\t\$2\n}]" 2 } } */


And also changes dg-final scan-assembler "mulditi3_r4000" instead of
"mulditi3" in fix-r4000-7.c.
changes dg-final scan-assembler "umulditi3_r4000" instead of
"umulditi3" in fix-r4000-8.c.

Thanks.
Paul Hua.

ChangeLog entries:

gcc/testsuite/ChangeLog

2018-03-24  Chenghua Xu 

* gcc.target/mips/fix-r4000-1.c: Delete "[^\n]" in dg-final.
* gcc.target/mips/fix-r4000-2.c: Likewise.
* gcc.target/mips/fix-r4000-3.c: Likewise.
* gcc.target/mips/fix-r4000-4.c: Likewise.
* gcc.target/mips/fix-r4000-5.c: Likewise.
* gcc.target/mips/fix-r4000-6.c: Likewise.
* gcc.target/mips/fix-r4000-7.c: Likewise.
* gcc.target/mips/fix-r4000-8.c: Likewise.
* gcc.target/mips/fix-r4000-9.c: Likewise.
* gcc.target/mips/fix-r4000-10.c: Likewise.
* gcc.target/mips/fix-r4000-7.c: Change dg-final
  "mulditi3_r4000" instead of "mulditi3".
* gcc.target/mips/fix-r4000-8.c: Change dg-final
  "umulditi3_r4000" instead of "umulditi3".
diff --git a/gcc/testsuite/gcc.target/mips/fix-r4000-1.c b/gcc/testsuite/gcc.target/mips/fix-r4000-1.c
index 5c812f25600..36062b0f6da 100644
--- a/gcc/testsuite/gcc.target/mips/fix-r4000-1.c
+++ b/gcc/testsuite/gcc.target/mips/fix-r4000-1.c
@@ -4,4 +4,4 @@ typedef int int32_t;
 typedef int uint32_t;
 NOMIPS16 int32_t foo (int32_t x, int32_t y) { return x * y; }
 NOMIPS16 uint32_t bar (uint32_t x, uint32_t y) { return x * y; }
-/* { dg-final { scan-assembler-times "[concat {\tmult\t\$[45],\$[45][^\n]+mulsi3_r4000[^\n]+\n\tmflo\t\$2\n}]" 2 } } */
+/* { dg-final { scan-assembler-times "[concat {\tmult\t\$[45],\$[45][^\n]+mulsi3_r4000\n\tmflo\t\$2\n}]" 2 } } */
diff --git a/gcc/testsuite/gcc.target/mips/fix-r4000-10.c b/gcc/testsuite/gcc.target/mips/fix-r4000-10.c
index 7227bc8c092..7345eb511be 100644
--- a/gcc/testsuite/gcc.target/mips/fix-r4000-10.c
+++ b/gcc/testsuite/gcc.target/mips/fix-r4000-10.c
@@ -6,4 +6,4 @@
 typedef unsigned long long uint64_t;
 typedef unsigned int uint128_t __attribute__((mode(TI)));
 NOMIPS16 uint128_t foo (uint64_t x, uint64_t y) { return (uint128_t) x * y; }
-/* { dg-final { scan-assembler "[concat {\tdmultu\t\$[45],\$[45][^\n]+umulditi3_r4000[^\n]+\n\tmflo\t\$2\n\tmfhi\t\$3\n}]" } } */
+/* { dg-final { scan-assembler "[concat {\tdmultu\t\$[45],\$[45][^\n]+umulditi3_r4000\n\tmflo\t\$2\n\tmfhi\t\$3\n}]" } } */
diff --git a/gcc/testsuite/gcc.target/mips/fix-r4000-2.c b/gcc/testsuite/gcc.target/mips/fix-r4000-2.c
index 0261b16b1c8..4290d5f7fab 100644
--- a/gcc/testsuite/gcc.target/mips/fix-r4000-2.c
+++ b/gcc/testsuite/gcc.target/mips/fix-r4000-2.c
@@ -6,4 +6,4 @@ typedef long long int64_t;
 NOMIPS16 int32_t foo (int32_t x, int32_t y) { return ((int64_t) x * y) >> 32; }
 /* ??? A highpart pattern would be a better choice, but we currently
don't use them.  */
-/* { dg-final { scan-assembler "[concat {\tmult\t\$[45],\$[45][^\n]+mulsidi3_32bit_r4000[^\n]+\n\tmflo\t\$3\n\tmfhi\t\$2\n}]" } } */
+/* { dg-final { scan-assembler "[concat {\tmult\t\$[45],\$[45][^\n]+mulsidi3_32bit_r4000\n\tmflo\t\$3\n\tmfhi\t\$2\n}]" } } */
diff --git a/gcc/testsuite/gcc.target/mips/fix-r4000-3.c b/gcc/testsuite/gcc.target/mips/fix-r4000-3.c
index 195a9d10ced..5bc8fc8ddd4 100644
--- a/gcc/testsuite/gcc.target/mips/fix-r4000-3.c
+++ b/gcc/testsuite/gcc.target/mips/fix-r4000-3.c
@@ -5,4 +5,4 @@ typedef unsigned long long uint64_t;
 NOMIPS16 uint32_t foo (uint32_t x, uint32_t y) { return ((uint64_t) x * y) >> 32; }
 /* ??? A highpart pattern would be a better choice, but we currently
don't use them.  */
-/* { dg-final { scan-assembler "[concat {\tmultu\t\$[45],\$[45][^\n]+umulsidi3_32bit_r4000[^\n]+\n\tmflo\t\$3\n\tmfhi\t\$2\n}]" } } */
+/* { dg-final { scan-assembler "[concat {\tmultu\t\$[45],\$[45][^\n]+umulsidi3_32bit_r4000\n\tmflo\t\$3\n\tmfhi\t\$2\n}]" } } */
diff --git a/gcc/testsuite/gcc.target/mips/fix-r4000-4.c b/gcc/testsuite/gcc.target/mips/fix-r4000-4.c
index 7a66182f524..4b655b5edf6 100644
--- a/gcc/testsuite/gcc.target/mips/fix-r4000-4.c
+++ b/gcc/testsuite/gcc.target/mips/fix-r4000-4.c
@@ -7,4 +7,4 @@
 typedef int int32_t;
 typedef lo

[PATCH,Testsuite,MIPS] Fixing umips-stroe16-2.c failure started with r255348

[Paul Hua]

Hi:

The umips-stroe16-2.c test fails after r255348, cause the r255348 does not print
 "[length = NN]" but "[c=NN l=NN]".

The asm for umips-stroe16-2.c.
before r255348:
...
 sb  $0,0($4) # 9*movqi_internal/6   [length = 2]
...
after r255348:
...
 sb  $0,0($4) # 9[c=4 l=2]  *movqi_internal/5
...

The patch changs:

  -/* { dg-final { scan-assembler
"\tsb\t\\\$0,0\\(\\\$\[0-9\]+\\)\[^\n\]*length = 2" } } */
 +/* { dg-final { scan-assembler
"\tsb\t\\\$0,0\\(\\\$\[0-9\]+\\)\[^\n\]*l=2" } } */

Thanks.
Paul Hua.

ChangeLog entries:

gcc/testsuite/ChangeLog

2018-03-24  Chenghua Xu 

* gcc.target/mips/umips-stroe16-2.c: Change "length = 2"
  to "l=2" in dg-final.
diff --git a/gcc/testsuite/gcc.target/mips/umips-store16-2.c b/gcc/testsuite/gcc.target/mips/umips-store16-2.c
index 0748edb5692..7fbd5e57305 100644
--- a/gcc/testsuite/gcc.target/mips/umips-store16-2.c
+++ b/gcc/testsuite/gcc.target/mips/umips-store16-2.c
@@ -17,6 +17,6 @@ f3 (unsigned int *ptr)
 {
   *ptr = 0;
 }
-/* { dg-final { scan-assembler "\tsb\t\\\$0,0\\(\\\$\[0-9\]+\\)\[^\n\]*length = 2" } } */
-/* { dg-final { scan-assembler "\tsh\t\\\$0,0\\(\\\$\[0-9\]+\\)\[^\n\]*length = 2" } } */
-/* { dg-final { scan-assembler "\tsw\t\\\$0,0\\(\\\$\[0-9\]+\\)\[^\n\]*length = 2" } } */
+/* { dg-final { scan-assembler "\tsb\t\\\$0,0\\(\\\$\[0-9\]+\\)\[^\n\]*l=2" } } */
+/* { dg-final { scan-assembler "\tsh\t\\\$0,0\\(\\\$\[0-9\]+\\)\[^\n\]*l=2" } } */
+/* { dg-final { scan-assembler "\tsw\t\\\$0,0\\(\\\$\[0-9\]+\\)\[^\n\]*l=2" } } */

[PATCH] Fix pr87156 ICE building libstdc++ for mips64

[Paul Hua]

Hi:

The bug pr87156 make MIPS target bootstrap fail a month ago. The
attached patch that posted under bugzilla by Jan Hubicka fixed the
bug.
Bootstrapped and reg-tested on mips64el-linux-gnu and x86_64-pc-linux-gnu.
Considering that Jan not very active, Is it OK for commits the patch
under Jan Hubicka behalf ?

Thanks

Paul Hua



-
2018-10-11  Jan Hubicka  

PR target/87156
* cgraphclones.c (cgraph_node::create_version_clone_with_body):
Set new_decl virtual flag to zero.
diff --git a/gcc/cgraphclones.c b/gcc/cgraphclones.c
index 2af45bd4fec..189cb31a5dc 100644
--- a/gcc/cgraphclones.c
+++ b/gcc/cgraphclones.c
@@ -968,6 +968,8 @@ cgraph_node::create_version_clone_with_body
   SET_DECL_ASSEMBLER_NAME (new_decl, DECL_NAME (new_decl));
   SET_DECL_RTL (new_decl, NULL);

+  DECL_VIRTUAL_P (new_decl) = 0;
+
   /* When the old decl was a con-/destructor make sure the clone isn't.  */
   DECL_STATIC_CONSTRUCTOR (new_decl) = 0;
   DECL_STATIC_DESTRUCTOR (new_decl) = 0;

[Patch,Testsuite][MIPS][Committed] Adjusted msa compare instructions clti to clei.

[Paul Hua]

Hi:

Recently gcc optimize msa compare code i<5 from clti_.df $wn,$wn,5
to clei_.df $wn,$wn,4.
This patch adjusted testsuite.

Committed as obviously.


gcc/testsuite/
2018-12-05  Chenghua Xu  

* gcc.target/mips/msa.c: Adjusted clti_.df $wn,$wn,5
to clei_.df $wn,$wn,4 in test31.
diff --git a/gcc/testsuite/gcc.target/mips/msa.c b/gcc/testsuite/gcc.target/mips/msa.c
index cdd5ca28dac..b741f35556f 100644
--- a/gcc/testsuite/gcc.target/mips/msa.c
+++ b/gcc/testsuite/gcc.target/mips/msa.c
@@ -330,14 +330,14 @@
 /* { dg-final { scan-assembler-times "test30_v8u16:.*ceqi.h.*test30_v8u16" 1 } } */
 /* { dg-final { scan-assembler-times "test30_v4u32:.*ceqi.w.*test30_v4u32" 1 } } */
 /* { dg-final { scan-assembler-times "test30_v2u64:.*ceqi.d.*test30_v2u64" 1 } } */
-/* { dg-final { scan-assembler-times "test31_s_v16i8:.*clti_s.b.*test31_s_v16i8" 1 } } */
-/* { dg-final { scan-assembler-times "test31_s_v8i16:.*clti_s.h.*test31_s_v8i16" 1 } } */
-/* { dg-final { scan-assembler-times "test31_s_v4i32:.*clti_s.w.*test31_s_v4i32" 1 } } */
-/* { dg-final { scan-assembler-times "test31_s_v2i64:.*clti_s.d.*test31_s_v2i64" 1 } } */
-/* { dg-final { scan-assembler-times "test31_u_v16u8:.*clti_u.b.*test31_u_v16u8" 1 } } */
-/* { dg-final { scan-assembler-times "test31_u_v8u16:.*clti_u.h.*test31_u_v8u16" 1 } } */
-/* { dg-final { scan-assembler-times "test31_u_v4u32:.*clti_u.w.*test31_u_v4u32" 1 } } */
-/* { dg-final { scan-assembler-times "test31_u_v2u64:.*clti_u.d.*test31_u_v2u64" 1 } } */
+/* { dg-final { scan-assembler-times "test31_s_v16i8:.*clei_s.b.*test31_s_v16i8" 1 } } */
+/* { dg-final { scan-assembler-times "test31_s_v8i16:.*clei_s.h.*test31_s_v8i16" 1 } } */
+/* { dg-final { scan-assembler-times "test31_s_v4i32:.*clei_s.w.*test31_s_v4i32" 1 } } */
+/* { dg-final { scan-assembler-times "test31_s_v2i64:.*clei_s.d.*test31_s_v2i64" 1 } } */
+/* { dg-final { scan-assembler-times "test31_u_v16u8:.*clei_u.b.*test31_u_v16u8" 1 } } */
+/* { dg-final { scan-assembler-times "test31_u_v8u16:.*clei_u.h.*test31_u_v8u16" 1 } } */
+/* { dg-final { scan-assembler-times "test31_u_v4u32:.*clei_u.w.*test31_u_v4u32" 1 } } */
+/* { dg-final { scan-assembler-times "test31_u_v2u64:.*clei_u.d.*test31_u_v2u64" 1 } } */
 /* { dg-final { scan-assembler-times "test32_s_v16i8:.*clei_s.b.*test32_s_v16i8" 1 } } */
 /* { dg-final { scan-assembler-times "test32_s_v8i16:.*clei_s.h.*test32_s_v8i16" 1 } } */
 /* { dg-final { scan-assembler-times "test32_s_v4i32:.*clei_s.w.*test32_s_v4i32" 1 } } */

[wwwdoc][Patch] Mention Loongson 3a1000 3a2000 3a3000 2k1000 support in gcc9

[Paul Hua]

Hi Gerald,

The attached patch mention Loongson 3a1000 3a2000 3a3000 2k1000 support in gcc9.

ok for commit?
Index: changes.html
===
RCS file: /cvs/gcc/wwwdocs/htdocs/gcc-9/changes.html,v
retrieving revision 1.30
diff -u -r1.30 changes.html
--- changes.html	3 Dec 2018 17:20:20 -	1.30
+++ changes.html	31 Dec 2018 10:21:32 -
@@ -214,6 +214,44 @@
   
 
 
+MIPS
+
+  
+The Loongson loongson-mmi and loongson-ext
+extension has now been splited from loongson3a:
+
+   loongson-mmi which contains 
+   the Loongson MultiMedia extension Instructions operations.
+   loongson-ext which contains 
+   the Loongson EXTension instructions.
+
+  
+The Loongson EXTension R2 instructions is now supported.
+
+   loongson-ext2 which contains the Loongson EXTension R2 instructions.
+
+Use -mxxx or -mno-xxx will enable or disable those extersions.
+for example: Using -mloongson-mmi/-mno-loongson-mmi 
+will enable/disable Loongson MultiMedia Instructions extensions.
+  
+Support has been added for the following processors
+(GCC identifiers in parentheses):
+
+	Loongson 3A1000 (gs464)
+	which default enable loongson-mmi, loongson-ext.
+	Loongson 3A2000/3A3000 (gs464e)
+	which default enable loongson-mmi, loongson-ext, loongson-ext2.
+	Loongson 2K1000 (gs264e)
+	which default enable loongson-ext, loongson-ext2, msa.
+
+The GCC identifiers can be used
+as arguments to the -mcpu or -mtune options,
+for example: -mcpu=gs464 or
+-mtune=gs464e or as arguments to the equivalent target
+attributes and pragmas.
+  
+
+
 
 
 

Re: [PATCH v4 4/6, Committed] [MIPS] Add Loongson 3A1000 processor support

[Paul Hua]

Hi Gerald,

patch send to here: https://gcc.gnu.org/ml/gcc-patches/2018-12/msg01785.html

thanks.



On Fri, Dec 28, 2018 at 12:50 AM Gerald Pfeifer  wrote:
>
> Hi Paul and Matthew,
>
> I believe it would be good to get this and other MIPS changes covered
> in the GCC 9 release notes at https://gcc.gnu.org/gcc-9/changes.html .
>
> Gerald
>
> PS: https://gcc.gnu.org/about.html has background how to go about this.

[PATCH v3 0/6] [MIPS] Reorganize the loongson march and extensions instructions set

[Paul Hua]

Hi:

The original version of patches were here:
https://gcc.gnu.org/ml/gcc-patches/2018-09/msg00099.html

This is a update version. please review, thanks.

This series patches reorganize the Loongson -march=xxx and Loongson
extensions instructions set.  For long time, the Loongson extensions
instructions set puts under -march=loongson3a option.  We can't
disable one of them when we need.

The patch (1) split Loongson  MultiMedia extensions Instructions (MMI)
from loongson3a, add -mloongson-mmi/-mno-loongson-mmi option for
enable/disable them.

The patch (2) split Loongson EXTensions (EXT) instructions from
loongson3a, add -mloongson-ext/-mno-loongson-ext option for
enable/disable them.

The patch (3) add Loongson EXTensions R2 (EXT2) instructions support,
add -mloongson-ext2/-mno-loongson-ext2 option for enable/disable them.

The patch (4) add Loongson 3A1000 processor support.  The gs464 is a
codename of 3A1000 microarchitecture.  Rename -march=loongson3a to
-march=gs464, Keep -march=loongson3a as an alias of -march=gs464 for
compatibility.

The patch (5) add Loongson 3A2000/3A3000 processor support.  Include
Loongson MMI, EXT, EXT2 instructions set.

The patch (6) add Loongson 2K1000 processor support. Include Loongson
MMI, EXT, EXT2 and MSA instructions set.

The binutils patch has been upstreamed.

There are six patches in this set, as follows.
1) 0001-MIPS-Add-support-for-loongson-mmi-instructions.patch
2) 0002-MIPS-Add-support-for-Loongson-EXT-istructions.patch
3) 0003-MIPS-Add-support-for-Loongson-EXT2-istructions.patch
4) 0004-MIPS-Add-support-for-Loongson-3A1000-proccessor.patch
5) 0005-MIPS-Add-support-for-Loongson-3A2000-3A3000-proccess.patch
6) 0006-MIPS-Add-support-for-Loongson-2K1000-proccessor.patch

All patchs test under mips64el-linux-gnu no new regressions.

Ok for commit ?

Thanks,
Paul Hua

[PATCH v3 2/6] [MIPS] Split Loongson EXTensions (EXT) instructions from loongson3a

[Paul Hua]

From 2e053c832497892c6b8b1b685aaf871d8fc4da76 Mon Sep 17 00:00:00 2001
From: Chenghua Xu 
Date: Fri, 31 Aug 2018 11:52:33 +0800
Subject: [PATCH 2/6] Add support for Loongson EXT istructions.

gcc/
	* config/mips/mips.c (mips_option_override): Default enable
	Loongson EXT on Loongson 3a target.
	* config/mips/mips.h (TARGET_CPU_CPP_BUILTINS): Add
	__mips_loongson_ext.
	(ASM_SPEC): Add mloongson-ext and mno-loongson-ext.
	* config/mips/mips.md (mul3, mul3_mul3_nohilo,
	div3, mod3, prefetch): Use TARGET_LOONGSON_EXT
	instead of TARGET_LOONGSON_3A.
	* config/mips/mips.opt (-mloongson-ext): Add option.
	* gcc/doc/invoke.texi (-mloongson-ext): Document.

gcc/testsuite/
	* gcc.target/mips/mips.exp (mips_option_groups): Add
	-mloongson-ext option.
---
 gcc/config/mips/mips.c |  5 +
 gcc/config/mips/mips.h |  7 +++
 gcc/config/mips/mips.md| 16 
 gcc/config/mips/mips.opt   |  4 
 gcc/doc/invoke.texi|  7 +++
 gcc/testsuite/gcc.target/mips/mips.exp |  1 +
 6 files changed, 32 insertions(+), 8 deletions(-)

diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
index a804f7030db..019a6dca752 100644
--- a/gcc/config/mips/mips.c
+++ b/gcc/config/mips/mips.c
@@ -20178,6 +20178,11 @@ mips_option_override (void)
 	  || (strcmp (mips_arch_info->name, "loongson3a") == 0)))
 target_flags |= MASK_LOONGSON_MMI;
 
+  /* Default to enable Loongson EXT on Longson 3a target.  */
+  if ((target_flags_explicit & MASK_LOONGSON_EXT) == 0
+  && (strcmp (mips_arch_info->name, "loongson3a") == 0))
+target_flags |= MASK_LOONGSON_EXT;
+
   /* .eh_frame addresses should be the same width as a C pointer.
  Most MIPS ABIs support only one pointer size, so the assembler
  will usually know exactly how big an .eh_frame address is.
diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h
index 3563c1d78fe..e0e78ba610e 100644
--- a/gcc/config/mips/mips.h
+++ b/gcc/config/mips/mips.h
@@ -596,6 +596,12 @@ struct mips_cpu_info {
 	  builtin_define ("__mips_loongson_mmi");			\
 	}\
 	\
+  /* Whether Loongson EXT modes are enabled.  */			\
+  if (TARGET_LOONGSON_EXT)		\
+	{\
+	  builtin_define ("__mips_loongson_ext");			\
+	}\
+	\
   /* Historical Octeon macro.  */	\
   if (TARGET_OCTEON)		\
 	builtin_define ("__OCTEON__");	\
@@ -1355,6 +1361,7 @@ struct mips_cpu_info {
 %{mginv} %{mno-ginv} \
 %{mmsa} %{mno-msa} \
 %{mloongson-mmi} %{mno-loongson-mmi} \
+%{mloongson-ext} %{mno-loongson-ext} \
 %{msmartmips} %{mno-smartmips} \
 %{mmt} %{mno-mt} \
 %{mfix-rm7000} %{mno-fix-rm7000} \
diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md
index a88c1c53134..4b7a627b7a6 100644
--- a/gcc/config/mips/mips.md
+++ b/gcc/config/mips/mips.md
@@ -1599,7 +1599,7 @@
 {
   rtx lo;
 
-  if (TARGET_LOONGSON_2EF || TARGET_LOONGSON_3A || ISA_HAS_R6MUL)
+  if (TARGET_LOONGSON_2EF || TARGET_LOONGSON_EXT || ISA_HAS_R6MUL)
 emit_insn (gen_mul3_mul3_nohilo (operands[0], operands[1],
 	   operands[2]));
   else if (ISA_HAS_MUL3)
@@ -1622,11 +1622,11 @@
   [(set (match_operand:GPR 0 "register_operand" "=d")
 (mult:GPR (match_operand:GPR 1 "register_operand" "d")
   (match_operand:GPR 2 "register_operand" "d")))]
-  "TARGET_LOONGSON_2EF || TARGET_LOONGSON_3A || ISA_HAS_R6MUL"
+  "TARGET_LOONGSON_2EF || TARGET_LOONGSON_EXT || ISA_HAS_R6MUL"
 {
   if (TARGET_LOONGSON_2EF)
 return "multu.g\t%0,%1,%2";
-  else if (TARGET_LOONGSON_3A)
+  else if (TARGET_LOONGSON_EXT)
 return "gsmultu\t%0,%1,%2";
   else
 return "mul\t%0,%1,%2";
@@ -3016,11 +3016,11 @@
   [(set (match_operand:GPR 0 "register_operand" "=&d")
 	(any_div:GPR (match_operand:GPR 1 "register_operand" "d")
 		 (match_operand:GPR 2 "register_operand" "d")))]
-  "TARGET_LOONGSON_2EF || TARGET_LOONGSON_3A || ISA_HAS_R6DIV"
+  "TARGET_LOONGSON_2EF || TARGET_LOONGSON_EXT || ISA_HAS_R6DIV"
   {
 if (TARGET_LOONGSON_2EF)
   return mips_output_division ("div.g\t%0,%1,%2", operands);
-else if (TARGET_LOONGSON_3A)
+else if (TARGET_LOONGSON_EXT)
   return mips_output_division ("gsdiv\t%0,%1,%2", operands);
 else
   return mips_output_division ("div\t%0,%1,%2", operands);
@@ -3032,11 +3032,11 @@
   [(set (match_operand:GPR 0 "register_operand" "=&d")
 	(any_mod:GPR (match_operand:GPR 1 "register_operand" "d")
 		 (match_operand:GPR 2 "register_operand" "d")))]
-  "TARGET_LOONGSON_2EF || TARGET_LOONGSON_3A || ISA_HAS_R6DIV"
+  "TARGET_LOONGSON_2EF || TARGET_LOONGSON_EXT || ISA_HAS_R6DIV"
   {
 if (TARGET_LOONGSON_2EF)
   return mips_output_division ("mod.g\t%0,%1,%2", operands);
-else if (TARGET_LOONGSON_3A)
+else if (TARGET_LOONGSON_EXT)
   return mips_output_division ("gsmod\t%0,%1,%2", operands);
 else
   return mips_output_division ("mod\t%0,%1,%2", operands);
@@ -7136,7 +7136,7 @@
 	 (match_operand 2 "co

[PATCH v3 1/6] [MIPS] Split Loongson (MMI) from loongson3a

[Paul Hua]

From e9d36eb4d4a841486ac82037497a2671481f8a27 Mon Sep 17 00:00:00 2001
From: Chenghua Xu 
Date: Sun, 14 Oct 2018 11:11:00 +0800
Subject: [PATCH 1/6] Add support for loongson mmi instructions.

gcc/
* config.gcc (extra_headers): Add loongson-mmiintrin.h.
* config/mips/loongson.md: Move to ...
* config/mips/loongson-mmi.md: here; Adjustment.
* config/mips/loongsson.h: Move to ...
State as deprecated. Include loongson-mmiintrin.h for back
compatibility and warning.
* config/mips/loongsson-mmiintrin.h: ... here.
* config/mips/mips.c (mips_hard_regno_mode_ok_uncached,
mips_vector_mode_supported_p, AVAIL_NON_MIPS16): Use
TARGET_LOONGSON_MMI instead of TARGET_LOONGSON_VECTORS.
(mips_option_override): Make sure MMI use hard float; Default
enable MMI on Loongson 2e/2f/3a.
(mips_shift_truncation_mask, mips_expand_vpc_loongson_even_odd,
mips_expand_vpc_loongson_pshufh, mips_expand_vpc_loongson_bcast,
mips_expand_vector_init): Use TARGET_LOONGSON_MMI instead of
TARGET_LOONGSON_VECTORS.
* gcc/config/mips/mips.h (TARGET_LOONGSON_VECTORS): Delete.
(TARGET_CPU_CPP_BUILTINS): Add __mips_loongson_mmi.
(SHIFT_COUNT_TRUNCATED): Use TARGET_LOONGSON_MMI instead of
TARGET_LOONGSON_VECTORS.
* gcc/config/mips/mips.md (MOVE64, MOVE128): Use
TARGET_LOONGSON_MMI instead of TARGET_LOONGSON_VECTORS.
(Loongson MMI patterns): Include loongson-mmi.md instead of
loongson.md.
* gcc/config/mips/mips.opt (-mloongson-mmi): New option.
* gcc/doc/invoke.texi (-mloongson-mmi): Document.

gcc/testsuite/
* gcc.target/mips/loongson-shift-count-truncated-1.c
(dg-options): Run under -mloongson-mmi option.
Include loongson-mmiintrin.h instead of loongson.h.
* gcc.target/mips/loongson-simd.c: Likewise.
* gcc.target/mips/mips.exp (mips_option_groups): Add
-mloongson-mmi option.
(mips-dg-init): Add -mloongson-mmi option.
* gcc.target/mips/umips-store16-1.c (dg-options): Add
forbid_cpu=loongson3a.
* lib/target-supports.exp: Rename check_mips_loongson_hw_available
to check_mips_loongson_mmi_hw_available.
Rename check_effective_target_mips_loongson_runtime to
check_effective_target_mips_loongson_mmi_runtime.
(check_effective_target_vect_int): Use mips_loongson_mmi instead
of mips_loongson when check et-is-effective-target.
(add_options_for_mips_loongson_mmi): New proc.
Rename check_effective_target_mips_loongson to
check_effective_target_mips_loongson_mmi.
(check_effective_target_vect_shift,
check_effective_target_whole_vector_shift,
check_effective_target_vect_no_int_min_max,
check_effective_target_vect_no_align,
check_effective_target_vect_short_mult,
check_vect_support_and_set_flags):Use mips_loongson_mmi instead
of mips_loongson when check et-is-effective-target.
---
 gcc/config.gcc |   2 +-
 gcc/config/mips/{loongson.md => loongson-mmi.md}   | 241 ---
 gcc/config/mips/loongson-mmiintrin.h   | 691 +
 gcc/config/mips/loongson.h | 669 +---
 gcc/config/mips/mips.c |  34 +-
 gcc/config/mips/mips.h |  21 +-
 gcc/config/mips/mips.md|  16 +-
 gcc/config/mips/mips.opt   |   4 +
 gcc/doc/invoke.texi|   7 +
 .../mips/loongson-shift-count-truncated-1.c|   6 +-
 gcc/testsuite/gcc.target/mips/loongson-simd.c  |   4 +-
 gcc/testsuite/gcc.target/mips/mips.exp |   7 +
 gcc/testsuite/gcc.target/mips/umips-store16-1.c|   2 +-
 gcc/testsuite/lib/target-supports.exp  |  47 +-
 14 files changed, 913 insertions(+), 838 deletions(-)
 rename gcc/config/mips/{loongson.md => loongson-mmi.md} (79%)
 create mode 100644 gcc/config/mips/loongson-mmiintrin.h

diff --git a/gcc/config.gcc b/gcc/config.gcc
index 8521f7d556e..7871700db13 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -441,7 +441,7 @@ microblaze*-*-*)
 ;;
 mips*-*-*)
 	cpu_type=mips
-	extra_headers="loongson.h msa.h"
+	extra_headers="loongson.h loongson-mmiintrin.h msa.h"
 	extra_objs="frame-header-opt.o"
 	extra_options="${extra_options} g.opt fused-madd.opt mips/mips-tables.opt"
 	;;
diff --git a/gcc/config/mips/loongson.md b/gcc/config/mips/loongson-mmi.md
similarity index 79%
rename from gcc/config/mips/loongson.md
rename to gcc/config/mips/loongson-mmi.md
index 14794d3671f..ad23f676581 100644
--- a/gcc/config/mips/loongson.md
+++ b/gcc/config/mips/loongson-mmi.md
@@ -1,5 +1,4 @@
-;; Machine description for Loongson-specific patterns, such as
-;; ST Microelectronics Loongson-2E/2F etc.
+;; Machine description for Loong

[PATCH v3 3/6] [MIPS] Add Loongson EXTensions R2 (EXT2) instructions support

[Paul Hua]

From 14eabf990f187631cacd47e02342941ddb1b04a0 Mon Sep 17 00:00:00 2001
From: Chenghua Xu 
Date: Fri, 31 Aug 2018 11:55:48 +0800
Subject: [PATCH 3/6] Add support for Loongson EXT2 istructions.

gcc/
	* config/mips/mips.h (TARGET_CPU_CPP_BUILTINS): Define
	__mips_loongson_ext2, __mips_loongson_ext_rev=2.
	(ISA_HAS_CTZ_CTO): New, ture if TARGET_LOONGSON_EXT2.
	(ASM_SPEC): Add mloongson-ext2 and mno-loongson-ext2.
	* config/mips/mips.md: Add ctz to "define_attr "type"".
	(define_insn "ctz2"): New insn pattern.
	(define_insn "prefetch"): Include TARGET_LOONGSON_EXT2.
	* config/mips/mips.opt (-mloongson-ext2): Add option.
	* gcc/doc/invoke.texi (-mloongson-ext2): Document.

gcc/testsuite/
	* gcc.target/mips/loongson-ctz.c: New test.
	* gcc.target/mips/loongson-dctz.c: Likewise.
	* gcc.target/mips/mips.exp (mips_option_groups): Add
	-mloongson-ext2 option.
---
 gcc/config/mips/mips.h| 12 +++
 gcc/config/mips/mips.md   | 31 ++-
 gcc/config/mips/mips.opt  |  4 
 gcc/doc/invoke.texi   |  7 ++
 gcc/testsuite/gcc.target/mips/loongson-ctz.c  | 11 ++
 gcc/testsuite/gcc.target/mips/loongson-dctz.c | 11 ++
 gcc/testsuite/gcc.target/mips/mips.exp|  1 +
 7 files changed, 72 insertions(+), 5 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/mips/loongson-ctz.c
 create mode 100644 gcc/testsuite/gcc.target/mips/loongson-dctz.c

diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h
index e0e78ba610e..b75646d66ce 100644
--- a/gcc/config/mips/mips.h
+++ b/gcc/config/mips/mips.h
@@ -600,8 +600,16 @@ struct mips_cpu_info {
   if (TARGET_LOONGSON_EXT)		\
 	{\
 	  builtin_define ("__mips_loongson_ext");			\
+	  if (TARGET_LOONGSON_EXT2)	\
+	{\
+	  builtin_define ("__mips_loongson_ext2");			\
+	  builtin_define ("__mips_loongson_ext_rev=2");		\
+	}\
+	  else\
+	  builtin_define ("__mips_loongson_ext_rev=1");		\
 	}\
 	\
+	\
   /* Historical Octeon macro.  */	\
   if (TARGET_OCTEON)		\
 	builtin_define ("__OCTEON__");	\
@@ -1117,6 +1125,9 @@ struct mips_cpu_info {
 /* ISA has count leading zeroes/ones instruction (not implemented).  */
 #define ISA_HAS_CLZ_CLO		(mips_isa_rev >= 1 && !TARGET_MIPS16)
 
+/* ISA has count tailing zeroes/ones instruction (not implemented).  */
+#define ISA_HAS_CTZ_CTO		(TARGET_LOONGSON_EXT2)
+
 /* ISA has three operand multiply instructions that put
the high part in an accumulator: mulhi or mulhiu.  */
 #define ISA_HAS_MULHI		((TARGET_MIPS5400			 \
@@ -1362,6 +1373,7 @@ struct mips_cpu_info {
 %{mmsa} %{mno-msa} \
 %{mloongson-mmi} %{mno-loongson-mmi} \
 %{mloongson-ext} %{mno-loongson-ext} \
+%{mloongson-ext2} %{mno-loongson-ext2} \
 %{msmartmips} %{mno-smartmips} \
 %{mmt} %{mno-mt} \
 %{mfix-rm7000} %{mno-fix-rm7000} \
diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md
index 4b7a627b7a6..c8128d4d530 100644
--- a/gcc/config/mips/mips.md
+++ b/gcc/config/mips/mips.md
@@ -335,6 +335,7 @@
 ;; slt		set less than instructions
 ;; signext  sign extend instructions
 ;; clz		the clz and clo instructions
+;; ctz		the ctz and cto instructions
 ;; pop		the pop instruction
 ;; trap		trap if instructions
 ;; imul		integer multiply 2 operands
@@ -375,7 +376,7 @@
 (define_attr "type"
   "unknown,branch,jump,call,load,fpload,fpidxload,store,fpstore,fpidxstore,
prefetch,prefetchx,condmove,mtc,mfc,mthi,mtlo,mfhi,mflo,const,arith,logical,
-   shift,slt,signext,clz,pop,trap,imul,imul3,imul3nc,imadd,idiv,idiv3,move,
+   shift,slt,signext,clz,ctz,pop,trap,imul,imul3,imul3nc,imadd,idiv,idiv3,move,
fmove,fadd,fmul,fmadd,fdiv,frdiv,frdiv1,frdiv2,fabs,fneg,fcmp,fcvt,fsqrt,
frsqrt,frsqrt1,frsqrt2,dspmac,dspmacsat,accext,accmod,dspalu,dspalusat,
multi,atomic,syncloop,nop,ghost,multimem,
@@ -3149,6 +3150,23 @@
 ;;
 ;;  ...
 ;;
+;;  Count tailing zeroes.
+;;
+;;  ...
+;;
+
+(define_insn "ctz2"
+  [(set (match_operand:GPR 0 "register_operand" "=d")
+	(ctz:GPR (match_operand:GPR 1 "register_operand" "d")))]
+  "ISA_HAS_CTZ_CTO"
+  "ctz\t%0,%1"
+  [(set_attr "type" "ctz")
+   (set_attr "mode" "")])
+
+
+;;
+;;  ...
+;;
 ;;  Count number of set bits.
 ;;
 ;;  ...
@@ -7136,13 +7154,16 @@
 	 (match_operand 2 "const_int_operand" "n"))]
   "ISA_HAS_PREFETCH && TARGET_EXPLICIT_RELOCS"
 {
-  if (TARGET_LOONGSON_2EF || TARGET_LOONGSON_EXT)
+  if (TARGET_LOONGSON_2EF || TARGET_LOONGSON_EXT || TARGET_LOONGSON_EXT2)
 {
-  /* Loongson 2[ef] and Loongson 3a use load to $0 for prefetching.  */
+  /* Loongson ext2 implementation pref insnstructions.  */
+  if (TARGET_LOONGSON_EXT2)
+	return "pref\t%1, %a0";
+  /* Loongson 2[ef] and Loongson ext use load to $0 for prefetching.  */
   if (TARGET_64BIT)
-return "ld\t$0,%a0";
+	return "ld\t$0,%a0";
   

[PATCH v3 4/6] [MIPS] Add Loongson 3A1000 processor support

[Paul Hua]

From ce950df0f918eb02d15c4287d21e3aecb43bf351 Mon Sep 17 00:00:00 2001
From: Chenghua Xu 
Date: Fri, 31 Aug 2018 14:08:01 +0800
Subject: [PATCH 4/6] Add support for Loongson 3A1000 proccessor.

gcc/
	* config/mips/loongson3a.md: Rename to ...
	* config/mips/gs464.md: ... here.
	* config/mips/mips-cpus.def: Define gs464; Add loongson3a
	as an alias of gs464 processor.
	* config/mips/mips-tables.opt: Regenerate.
	* config/mips/mips.c (mips_issue_rate): Use PROCESSOR_GS464
	instead of ROCESSOR_LOONGSON_3A.
	(mips_multipass_dfa_lookahead): Use TUNE_GS464 instread of
	TUNE_LOONGSON_3A.
	(mips_option_override): Enable MMI and EXT for gs464.
	* config/mips/mips.h: Rename TARGET_LOONGSON_3A to TARGET_GS464;
	Rename TUNE_LOONGSON_3A to TUNE_GS464.
	(MIPS_ISA_LEVEL_SPEC): Infer mips64r2 from gs464.
	(ISA_HAS_ODD_SPREG, ISA_AVOID_DIV_HILO, ISA_HAS_FUSED_MADD4,
	ISA_HAS_UNFUSED_MADD4): Use TARGET_GS464 instead of
	TARGET_LOONGSON_3A.
	* config/mips/mips.md: Include gs464.md instead of loongson3a.md.
	(processor): Add gs464;
	* doc/invoke.texi: Add gs464 to supported architectures.
---
 gcc/config/mips/gs464.md| 137 
 gcc/config/mips/loongson3a.md   | 137 
 gcc/config/mips/mips-cpus.def   |   3 +-
 gcc/config/mips/mips-tables.opt |  19 +++---
 gcc/config/mips/mips.c  |  16 +++--
 gcc/config/mips/mips.h  |  15 +++--
 gcc/config/mips/mips.md |   4 +-
 gcc/doc/invoke.texi |   2 +-
 8 files changed, 170 insertions(+), 163 deletions(-)
 create mode 100644 gcc/config/mips/gs464.md
 delete mode 100644 gcc/config/mips/loongson3a.md

diff --git a/gcc/config/mips/gs464.md b/gcc/config/mips/gs464.md
new file mode 100644
index 000..82efb66786f
--- /dev/null
+++ b/gcc/config/mips/gs464.md
@@ -0,0 +1,137 @@
+;; Pipeline model for Loongson gs464 cores.
+
+;; Copyright (C) 2011-2018 Free Software Foundation, Inc.
+;;
+;; This file is part of GCC.
+;;
+;; GCC is free software; you can redistribute it and/or modify it
+;; under the terms of the GNU General Public License as published
+;; by the Free Software Foundation; either version 3, or (at your
+;; option) any later version.
+;;
+;; GCC is distributed in the hope that it will be useful, but WITHOUT
+;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+;; License for more details.
+;;
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3.  If not see
+;; .
+
+;; Uncomment the following line to output automata for debugging.
+;; (automata_option "v")
+
+;; Automaton for integer instructions.
+(define_automaton "gs464_a_alu")
+
+;; Automaton for floating-point instructions.
+(define_automaton "gs464_a_falu")
+
+;; Automaton for memory operations.
+(define_automaton "gs464_a_mem")
+
+;; Describe the resources.
+
+(define_cpu_unit "gs464_alu1" "gs464_a_alu")
+(define_cpu_unit "gs464_alu2" "gs464_a_alu")
+(define_cpu_unit "gs464_mem" "gs464_a_mem")
+(define_cpu_unit "gs464_falu1" "gs464_a_falu")
+(define_cpu_unit "gs464_falu2" "gs464_a_falu")
+
+;; Describe instruction reservations.
+
+(define_insn_reservation "gs464_arith" 1
+  (and (eq_attr "cpu" "gs464")
+   (eq_attr "type" "arith,clz,const,logical,
+			move,nop,shift,signext,slt"))
+  "gs464_alu1 | gs464_alu2")
+
+(define_insn_reservation "gs464_branch" 1
+  (and (eq_attr "cpu" "gs464")
+   (eq_attr "type" "branch,jump,call,condmove,trap"))
+  "gs464_alu1")
+
+(define_insn_reservation "gs464_mfhilo" 1
+  (and (eq_attr "cpu" "gs464")
+   (eq_attr "type" "mfhi,mflo,mthi,mtlo"))
+  "gs464_alu2")
+
+;; Operation imul3nc is fully pipelined.
+(define_insn_reservation "gs464_imul3nc" 5
+  (and (eq_attr "cpu" "gs464")
+   (eq_attr "type" "imul3nc"))
+  "gs464_alu2")
+
+(define_insn_reservation "gs464_imul" 7
+  (and (eq_attr "cpu" "gs464")
+   (eq_attr "type" "imul,imadd"))
+  "gs464_alu2 * 7")
+
+(define_insn_reservation "gs464_idiv_si" 12
+  (and (eq_attr "cpu" "gs464")
+   (and (eq_attr "type" "idiv")
+	(eq_attr "mode" "SI")))
+  "gs464_alu2 * 12")
+
+(define_insn_reservation "gs464_idiv_di" 25
+  (and (eq_attr "cpu" "gs464")
+   (and (eq_attr "type" "idiv")
+	(eq_attr "mode" "DI")))
+  "gs464_alu2 * 25")
+
+(define_insn_reservation "gs464_load" 3
+  (and (eq_attr "cpu" "gs464")
+   (eq_attr "type" "load"))
+  "gs464_mem")
+
+(define_insn_reservation "gs464_fpload" 4
+  (and (eq_attr "cpu" "gs464")
+   (eq_attr "type" "load,mfc,mtc"))
+  "gs464_mem")
+
+(define_insn_reservation "gs464_prefetch" 0
+  (and (eq_attr "cpu" "gs464")
+   (eq_attr "type" "prefetch,prefetchx"))
+  "gs464_mem")
+
+(define_insn_reservation "gs464_store" 0
+  (and (eq_attr "cpu" "gs464")
+   (eq_attr "type" "store,fpstore,fpidxstore"))
+  "gs464_mem")
+
+;; All the fp operations can be executed in FALU1.  Only fp

[PATCH v3 5/6] [MIPS] Add Loongson 3A2000/3A3000 processor support

[Paul Hua]

From 55047aa22e40de2637fbab4b5e246dfc4ca191f8 Mon Sep 17 00:00:00 2001
From: Chenghua Xu 
Date: Mon, 3 Sep 2018 19:45:15 +0800
Subject: [PATCH 5/6] Add support for Loongson 3A2000/3A3000 proccessor.

gcc/
	* config/mips/gs464e.md: New.
	* config/mips/mips-cpus.def: Define gs464e.
	* config/mips/mips-tables.opt: Regenerate.
	* config/mips/mips.c (mips_rtx_cost_data): Add DEFAULT_COSTS for
	gs464e.
	(mips_issue_rate): Add support for gs464e.
	(mips_multipass_dfa_lookahead): Likewise.
	(mips_option_override): Enable MMI, EXT and EXT2 for gs464e.
	* config/mips/mips.h: Define TARGET_GS464E and TUNE_GS464E.
	(MIPS_ISA_LEVEL_SPEC): Infer mips64r2 from gs464e.
	(ISA_HAS_FUSED_MADD4): Enable for TARGET_GS464E.
	(ISA_HAS_UNFUSED_MADD4): Exclude TARGET_GS464E.
	* config/mips/mips.md: Include gs464e.md.
	(processor): Add gs464e.
	* doc/invoke.texi: Add gs464e to supported architectures.
---
 gcc/config/mips/gs464e.md   | 137 
 gcc/config/mips/mips-cpus.def   |   1 +
 gcc/config/mips/mips-tables.opt |  19 +++---
 gcc/config/mips/mips.c  |  22 +--
 gcc/config/mips/mips.h  |  10 ++-
 gcc/config/mips/mips.md |   2 +
 gcc/doc/invoke.texi |   2 +-
 7 files changed, 176 insertions(+), 17 deletions(-)
 create mode 100644 gcc/config/mips/gs464e.md

diff --git a/gcc/config/mips/gs464e.md b/gcc/config/mips/gs464e.md
new file mode 100644
index 000..60e0e6b0463
--- /dev/null
+++ b/gcc/config/mips/gs464e.md
@@ -0,0 +1,137 @@
+;; Pipeline model for Loongson gs464e cores.
+
+;; Copyright (C) 2018 Free Software Foundation, Inc.
+;;
+;; This file is part of GCC.
+;;
+;; GCC is free software; you can redistribute it and/or modify it
+;; under the terms of the GNU General Public License as published
+;; by the Free Software Foundation; either version 3, or (at your
+;; option) any later version.
+;;
+;; GCC is distributed in the hope that it will be useful, but WITHOUT
+;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+;; License for more details.
+;;
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3.  If not see
+;; .
+
+;; Uncomment the following line to output automata for debugging.
+;; (automata_option "v")
+
+;; Automaton for integer instructions.
+(define_automaton "gs464e_a_alu")
+
+;; Automaton for floating-point instructions.
+(define_automaton "gs464e_a_falu")
+
+;; Automaton for memory operations.
+(define_automaton "gs464e_a_mem")
+
+;; Describe the resources.
+
+(define_cpu_unit "gs464e_alu1" "gs464e_a_alu")
+(define_cpu_unit "gs464e_alu2" "gs464e_a_alu")
+(define_cpu_unit "gs464e_mem1" "gs464e_a_mem")
+(define_cpu_unit "gs464e_mem2" "gs464e_a_mem")
+(define_cpu_unit "gs464e_falu1" "gs464e_a_falu")
+(define_cpu_unit "gs464e_falu2" "gs464e_a_falu")
+
+;; Describe instruction reservations.
+
+(define_insn_reservation "gs464e_arith" 1
+  (and (eq_attr "cpu" "gs464e")
+   (eq_attr "type" "arith,clz,const,logical,
+			move,nop,shift,signext,slt"))
+  "gs464e_alu1 | gs464e_alu2")
+
+(define_insn_reservation "gs464e_branch" 1
+  (and (eq_attr "cpu" "gs464e")
+   (eq_attr "type" "branch,jump,call,condmove,trap"))
+  "gs464e_alu1 | gs464e_alu2")
+
+(define_insn_reservation "gs464e_mfhilo" 1
+  (and (eq_attr "cpu" "gs464e")
+   (eq_attr "type" "mfhi,mflo,mthi,mtlo"))
+  "gs464e_alu1 | gs464e_alu2")
+
+;; Operation imul3nc is fully pipelined.
+(define_insn_reservation "gs464e_imul3nc" 5
+  (and (eq_attr "cpu" "gs464e")
+   (eq_attr "type" "imul3nc"))
+  "gs464e_alu1 | gs464e_alu2")
+
+(define_insn_reservation "gs464e_imul" 7
+  (and (eq_attr "cpu" "gs464e")
+   (eq_attr "type" "imul,imadd"))
+  "gs464e_alu1 | gs464e_alu2")
+
+(define_insn_reservation "gs464e_idiv_si" 12
+  (and (eq_attr "cpu" "gs464e")
+   (and (eq_attr "type" "idiv")
+	(eq_attr "mode" "SI")))
+  "gs464e_alu1 | gs464e_alu2")
+
+(define_insn_reservation "gs464e_idiv_di" 25
+  (and (eq_attr "cpu" "gs464e")
+   (and (eq_attr "type" "idiv")
+	(eq_attr "mode" "DI")))
+  "gs464e_alu1 | gs464e_alu2")
+
+(define_insn_reservation "gs464e_load" 4
+  (and (eq_attr "cpu" "gs464e")
+   (eq_attr "type" "load"))
+  "gs464e_mem1 | gs464e_mem2")
+
+(define_insn_reservation "gs464e_fpload" 5
+  (and (eq_attr "cpu" "gs464e")
+   (eq_attr "type" "load,mfc,mtc"))
+  "gs464e_mem1 | gs464e_mem2")
+
+(define_insn_reservation "gs464e_prefetch" 0
+  (and (eq_attr "cpu" "gs464e")
+   (eq_attr "type" "prefetch,prefetchx"))
+  "gs464e_mem1 | gs464e_mem2")
+
+(define_insn_reservation "gs464e_store" 0
+  (and (eq_attr "cpu" "gs464e")
+   (eq_attr "type" "store,fpstore,fpidxstore"))
+  "gs464e_mem1 | gs464e_mem2")
+
+(define_insn_reservation "gs464e_fadd" 4
+  (and (eq_attr "cpu" "gs464e")
+   (eq_attr "type" "fadd,fmul,fmadd"))
+  "gs464e_falu1 | gs464e_falu2")
+
+(define_

[PATCH v3 6/6] [MIPS] Add Loongson 2K1000 processor support

[Paul Hua]

From 0df9c46bea628086ca2c4b5db24c28cec912d319 Mon Sep 17 00:00:00 2001
From: Chenghua Xu 
Date: Mon, 3 Sep 2018 20:01:54 +0800
Subject: [PATCH 6/6] Add support for Loongson 2K1000 proccessor.

gcc/
	* config/mips/gs264e.md: New.
	* config/mips/mips-cpus.def: Define gs264e.
	* config/mips/mips-tables.opt: Regenerate.
	* config/mips/mips.c (mips_rtx_cost_data): Add DEFAULT_COSTS for
	gs264e.
	(mips_issue_rate): Add support for gs264e.
	(mips_multipass_dfa_lookahead): Likewise.
	(mips_option_override): Enable MMI, EXT, EXT2 and MSA for gs264e.
	* config/mips/mips.h: Define TARGET_GS264E and TUNE_GS264E.
	(MIPS_ISA_LEVEL_SPEC): Infer mips64r2 from gs264e.
	(ISA_HAS_FUSED_MADD4): Enable for TARGET_GS264E.
	(ISA_HAS_UNFUSED_MADD4): Exclude TARGET_GS264E.
	* config/mips/mips.md: Include gs264e.md.
	(processor): Add gs264e.
	* config/mips/mips.opt (MSA): Use Mask instead of Var.
	* doc/invoke.texi: Add gs264e to supported architectures.
---
 gcc/config/mips/gs264e.md   | 133 
 gcc/config/mips/mips-cpus.def   |   1 +
 gcc/config/mips/mips-tables.opt |  19 +++---
 gcc/config/mips/mips.c  |  29 ++---
 gcc/config/mips/mips.h  |  12 ++--
 gcc/config/mips/mips.md |   2 +
 gcc/config/mips/mips.opt|   2 +-
 gcc/doc/invoke.texi |   1 +
 8 files changed, 178 insertions(+), 21 deletions(-)
 create mode 100644 gcc/config/mips/gs264e.md

diff --git a/gcc/config/mips/gs264e.md b/gcc/config/mips/gs264e.md
new file mode 100644
index 000..8f1f9e17e08
--- /dev/null
+++ b/gcc/config/mips/gs264e.md
@@ -0,0 +1,133 @@
+;; Pipeline model for Loongson gs264e cores.
+
+;; Copyright (C) 2018 Free Software Foundation, Inc.
+;;
+;; This file is part of GCC.
+;;
+;; GCC is free software; you can redistribute it and/or modify it
+;; under the terms of the GNU General Public License as published
+;; by the Free Software Foundation; either version 3, or (at your
+;; option) any later version.
+;;
+;; GCC is distributed in the hope that it will be useful, but WITHOUT
+;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+;; License for more details.
+;;
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3.  If not see
+;; .
+
+;; Uncomment the following line to output automata for debugging.
+;; (automata_option "v")
+
+;; Automaton for integer instructions.
+(define_automaton "gs264e_a_alu")
+
+;; Automaton for floating-point instructions.
+(define_automaton "gs264e_a_falu")
+
+;; Automaton for memory operations.
+(define_automaton "gs264e_a_mem")
+
+;; Describe the resources.
+
+(define_cpu_unit "gs264e_alu1" "gs264e_a_alu")
+(define_cpu_unit "gs264e_mem1" "gs264e_a_mem")
+(define_cpu_unit "gs264e_falu1" "gs264e_a_falu")
+
+;; Describe instruction reservations.
+
+(define_insn_reservation "gs264e_arith" 1
+  (and (eq_attr "cpu" "gs264e")
+   (eq_attr "type" "arith,clz,const,logical,
+			move,nop,shift,signext,slt"))
+  "gs264e_alu1")
+
+(define_insn_reservation "gs264e_branch" 1
+  (and (eq_attr "cpu" "gs264e")
+   (eq_attr "type" "branch,jump,call,condmove,trap"))
+  "gs264e_alu1")
+
+(define_insn_reservation "gs264e_mfhilo" 1
+  (and (eq_attr "cpu" "gs264e")
+   (eq_attr "type" "mfhi,mflo,mthi,mtlo"))
+  "gs264e_alu1")
+
+;; Operation imul3nc is fully pipelined.
+(define_insn_reservation "gs264e_imul3nc" 7
+  (and (eq_attr "cpu" "gs264e")
+   (eq_attr "type" "imul3nc"))
+  "gs264e_alu1")
+
+(define_insn_reservation "gs264e_imul" 7
+  (and (eq_attr "cpu" "gs264e")
+   (eq_attr "type" "imul,imadd"))
+  "gs264e_alu1")
+
+(define_insn_reservation "gs264e_idiv_si" 12
+  (and (eq_attr "cpu" "gs264e")
+   (and (eq_attr "type" "idiv")
+	(eq_attr "mode" "SI")))
+  "gs264e_alu1")
+
+(define_insn_reservation "gs264e_idiv_di" 25
+  (and (eq_attr "cpu" "gs264e")
+   (and (eq_attr "type" "idiv")
+	(eq_attr "mode" "DI")))
+  "gs264e_alu1")
+
+(define_insn_reservation "gs264e_load" 4
+  (and (eq_attr "cpu" "gs264e")
+   (eq_attr "type" "load"))
+  "gs264e_mem1")
+
+(define_insn_reservation "gs264e_fpload" 4
+  (and (eq_attr "cpu" "gs264e")
+   (eq_attr "type" "load,mfc,mtc"))
+  "gs264e_mem1")
+
+(define_insn_reservation "gs264e_prefetch" 0
+  (and (eq_attr "cpu" "gs264e")
+   (eq_attr "type" "prefetch,prefetchx"))
+  "gs264e_mem1")
+
+(define_insn_reservation "gs264e_store" 0
+  (and (eq_attr "cpu" "gs264e")
+   (eq_attr "type" "store,fpstore,fpidxstore"))
+  "gs264e_mem1")
+
+(define_insn_reservation "gs264e_fadd" 4
+  (and (eq_attr "cpu" "gs264e")
+   (eq_attr "type" "fadd,fmul,fmadd"))
+  "gs264e_falu1")
+
+(define_insn_reservation "gs264e_fcmp" 2
+  (and (eq_attr "cpu" "gs264e")
+   (eq_attr "type" "fabs,fcmp,fmove,fneg"))
+  "gs264e_falu1")
+
+(define_insn_reservation "gs264e_fcvt" 4
+  (and (eq_attr "cpu" "gs264e")
+ 

Ping Re: [PATCH v3 0/6] [MIPS] Reorganize the loongson march and extensions instructions set

[Paul Hua]

Ping?

I'd like check in those patches before stage3.

Thanks,

On Tue, Oct 16, 2018 at 10:49 AM Paul Hua  wrote:
>
> Hi:
>
> The original version of patches were here:
> https://gcc.gnu.org/ml/gcc-patches/2018-09/msg00099.html
>
> This is a update version. please review, thanks.
>
> This series patches reorganize the Loongson -march=xxx and Loongson
> extensions instructions set.  For long time, the Loongson extensions
> instructions set puts under -march=loongson3a option.  We can't
> disable one of them when we need.
>
> The patch (1) split Loongson  MultiMedia extensions Instructions (MMI)
> from loongson3a, add -mloongson-mmi/-mno-loongson-mmi option for
> enable/disable them.
>
> The patch (2) split Loongson EXTensions (EXT) instructions from
> loongson3a, add -mloongson-ext/-mno-loongson-ext option for
> enable/disable them.
>
> The patch (3) add Loongson EXTensions R2 (EXT2) instructions support,
> add -mloongson-ext2/-mno-loongson-ext2 option for enable/disable them.
>
> The patch (4) add Loongson 3A1000 processor support.  The gs464 is a
> codename of 3A1000 microarchitecture.  Rename -march=loongson3a to
> -march=gs464, Keep -march=loongson3a as an alias of -march=gs464 for
> compatibility.
>
> The patch (5) add Loongson 3A2000/3A3000 processor support.  Include
> Loongson MMI, EXT, EXT2 instructions set.
>
> The patch (6) add Loongson 2K1000 processor support. Include Loongson
> MMI, EXT, EXT2 and MSA instructions set.
>
> The binutils patch has been upstreamed.
>
> There are six patches in this set, as follows.
> 1) 0001-MIPS-Add-support-for-loongson-mmi-instructions.patch
> 2) 0002-MIPS-Add-support-for-Loongson-EXT-istructions.patch
> 3) 0003-MIPS-Add-support-for-Loongson-EXT2-istructions.patch
> 4) 0004-MIPS-Add-support-for-Loongson-3A1000-proccessor.patch
> 5) 0005-MIPS-Add-support-for-Loongson-3A2000-3A3000-proccess.patch
> 6) 0006-MIPS-Add-support-for-Loongson-2K1000-proccessor.patch
>
> All patchs test under mips64el-linux-gnu no new regressions.
>
> Ok for commit ?
>
> Thanks,
> Paul Hua

Ping^2 Re: [PATCH v3 0/6] [MIPS] Reorganize the loongson march and extensions instructions set

[Paul Hua]

Ping ?

On Fri, Oct 19, 2018 at 2:19 PM Paul Hua  wrote:
>
> Ping?
>
> I'd like check in those patches before stage3.
>
> Thanks,
>
> On Tue, Oct 16, 2018 at 10:49 AM Paul Hua  wrote:
> >
> > Hi:
> >
> > The original version of patches were here:
> > https://gcc.gnu.org/ml/gcc-patches/2018-09/msg00099.html
> >
> > This is a update version. please review, thanks.
> >
> > This series patches reorganize the Loongson -march=xxx and Loongson
> > extensions instructions set.  For long time, the Loongson extensions
> > instructions set puts under -march=loongson3a option.  We can't
> > disable one of them when we need.
> >
> > The patch (1) split Loongson  MultiMedia extensions Instructions (MMI)
> > from loongson3a, add -mloongson-mmi/-mno-loongson-mmi option for
> > enable/disable them.
> >
> > The patch (2) split Loongson EXTensions (EXT) instructions from
> > loongson3a, add -mloongson-ext/-mno-loongson-ext option for
> > enable/disable them.
> >
> > The patch (3) add Loongson EXTensions R2 (EXT2) instructions support,
> > add -mloongson-ext2/-mno-loongson-ext2 option for enable/disable them.
> >
> > The patch (4) add Loongson 3A1000 processor support.  The gs464 is a
> > codename of 3A1000 microarchitecture.  Rename -march=loongson3a to
> > -march=gs464, Keep -march=loongson3a as an alias of -march=gs464 for
> > compatibility.
> >
> > The patch (5) add Loongson 3A2000/3A3000 processor support.  Include
> > Loongson MMI, EXT, EXT2 instructions set.
> >
> > The patch (6) add Loongson 2K1000 processor support. Include Loongson
> > MMI, EXT, EXT2 and MSA instructions set.
> >
> > The binutils patch has been upstreamed.
> >
> > There are six patches in this set, as follows.
> > 1) 0001-MIPS-Add-support-for-loongson-mmi-instructions.patch
> > 2) 0002-MIPS-Add-support-for-Loongson-EXT-istructions.patch
> > 3) 0003-MIPS-Add-support-for-Loongson-EXT2-istructions.patch
> > 4) 0004-MIPS-Add-support-for-Loongson-3A1000-proccessor.patch
> > 5) 0005-MIPS-Add-support-for-Loongson-3A2000-3A3000-proccess.patch
> > 6) 0006-MIPS-Add-support-for-Loongson-2K1000-proccessor.patch
> >
> > All patchs test under mips64el-linux-gnu no new regressions.
> >
> > Ok for commit ?
> >
> > Thanks,
> > Paul Hua

Re: [PATCH] combine: Do not combine moves from hard registers

[Paul Hua]

Hi:
>
> I have noticed many regressions on arm and aarch64 between 265366 and
> 265408 (this commit is 265398).
>

There are many regressions on mips64el between 265378 and 265420.

r265378 testresults:
https://gcc.gnu.org/ml/gcc-testresults/2018-10/msg02935.html
r265420 testresults:
https://gcc.gnu.org/ml/gcc-testresults/2018-10/msg03065.html

 I bisected at least one to this commit on mips64el:
FAIL: gcc.c-torture/execute/builtins/memcpy-chk.c compilation,  -O1
(internal compiler error)
FAIL: gcc.c-torture/execute/builtins/memcpy-chk.c compilation,  -O2
(internal compiler error)
FAIL: gcc.c-torture/execute/builtins/memcpy-chk.c compilation,  -O2
-flto -fno-use-linker-plugin -flto-partition=none  (internal compiler
error)
FAIL: gcc.c-torture/execute/builtins/memcpy-chk.c compilation,  -O2
-flto -fuse-linker-plugin -fno-fat-lto-objects  (internal compiler
error)
FAIL: gcc.c-torture/execute/builtins/memcpy-chk.c compilation,  -O3
-fomit-frame-pointer -funroll-loops -fpeel-loops -ftracer
-finline-functions  (internal compiler error)
FAIL: gcc.c-torture/execute/builtins/memcpy-chk.c compilation,  -O3 -g
 (internal compiler error)
FAIL: gcc.c-torture/execute/builtins/memcpy-chk.c compilation,  -Og -g
 (internal compiler error)
FAIL: gcc.c-torture/execute/builtins/memcpy-chk.c compilation,  -Os
(internal compiler error)

I filed a bug at https://gcc.gnu.org/bugzilla/show_bug.cgi?id=87720.

Paul Hua

> I bisected at least one to this commit on aarch64:
> FAIL: gcc.dg/ira-shrinkwrap-prep-1.c scan-rtl-dump ira "Split
> live-range of register"
> The same test also regresses on arm.
>
> For a whole picture of all the regressions I noticed during these two
> commits, have a look at:
> http://people.linaro.org/~christophe.lyon/cross-validation/gcc/trunk/265408/report-build-info.html
>
> Christophe
>

Ping^3 Re: [PATCH v3 0/6] [MIPS] Reorganize the loongson march and extensions instructions set

[Paul Hua]

Ping ?

On Tue, Oct 23, 2018 at 9:16 AM Paul Hua  wrote:
>
> Ping ?
>
> On Fri, Oct 19, 2018 at 2:19 PM Paul Hua  wrote:
> >
> > Ping?
> >
> > I'd like check in those patches before stage3.
> >
> > Thanks,
> >
> > On Tue, Oct 16, 2018 at 10:49 AM Paul Hua  wrote:
> > >
> > > Hi:
> > >
> > > The original version of patches were here:
> > > https://gcc.gnu.org/ml/gcc-patches/2018-09/msg00099.html
> > >
> > > This is a update version. please review, thanks.
> > >
> > > This series patches reorganize the Loongson -march=xxx and Loongson
> > > extensions instructions set.  For long time, the Loongson extensions
> > > instructions set puts under -march=loongson3a option.  We can't
> > > disable one of them when we need.
> > >
> > > The patch (1) split Loongson  MultiMedia extensions Instructions (MMI)
> > > from loongson3a, add -mloongson-mmi/-mno-loongson-mmi option for
> > > enable/disable them.
> > >
> > > The patch (2) split Loongson EXTensions (EXT) instructions from
> > > loongson3a, add -mloongson-ext/-mno-loongson-ext option for
> > > enable/disable them.
> > >
> > > The patch (3) add Loongson EXTensions R2 (EXT2) instructions support,
> > > add -mloongson-ext2/-mno-loongson-ext2 option for enable/disable them.
> > >
> > > The patch (4) add Loongson 3A1000 processor support.  The gs464 is a
> > > codename of 3A1000 microarchitecture.  Rename -march=loongson3a to
> > > -march=gs464, Keep -march=loongson3a as an alias of -march=gs464 for
> > > compatibility.
> > >
> > > The patch (5) add Loongson 3A2000/3A3000 processor support.  Include
> > > Loongson MMI, EXT, EXT2 instructions set.
> > >
> > > The patch (6) add Loongson 2K1000 processor support. Include Loongson
> > > MMI, EXT, EXT2 and MSA instructions set.
> > >
> > > The binutils patch has been upstreamed.
> > >
> > > There are six patches in this set, as follows.
> > > 1) 0001-MIPS-Add-support-for-loongson-mmi-instructions.patch
> > > 2) 0002-MIPS-Add-support-for-Loongson-EXT-istructions.patch
> > > 3) 0003-MIPS-Add-support-for-Loongson-EXT2-istructions.patch
> > > 4) 0004-MIPS-Add-support-for-Loongson-3A1000-proccessor.patch
> > > 5) 0005-MIPS-Add-support-for-Loongson-3A2000-3A3000-proccess.patch
> > > 6) 0006-MIPS-Add-support-for-Loongson-2K1000-proccessor.patch
> > >
> > > All patchs test under mips64el-linux-gnu no new regressions.
> > >
> > > Ok for commit ?
> > >
> > > Thanks,
> > > Paul Hua

Ping^4 Re: [PATCH v3 0/6] [MIPS] Reorganize the loongson march and extensions instructions set

[Paul Hua]

Ping ?

On Fri, Oct 26, 2018 at 5:50 PM Paul Hua  wrote:
>
> Ping ?
>
> On Tue, Oct 23, 2018 at 9:16 AM Paul Hua  wrote:
> >
> > Ping ?
> >
> > On Fri, Oct 19, 2018 at 2:19 PM Paul Hua  wrote:
> > >
> > > Ping?
> > >
> > > I'd like check in those patches before stage3.
> > >
> > > Thanks,
> > >
> > > On Tue, Oct 16, 2018 at 10:49 AM Paul Hua  wrote:
> > > >
> > > > Hi:
> > > >
> > > > The original version of patches were here:
> > > > https://gcc.gnu.org/ml/gcc-patches/2018-09/msg00099.html
> > > >
> > > > This is a update version. please review, thanks.
> > > >
> > > > This series patches reorganize the Loongson -march=xxx and Loongson
> > > > extensions instructions set.  For long time, the Loongson extensions
> > > > instructions set puts under -march=loongson3a option.  We can't
> > > > disable one of them when we need.
> > > >
> > > > The patch (1) split Loongson  MultiMedia extensions Instructions (MMI)
> > > > from loongson3a, add -mloongson-mmi/-mno-loongson-mmi option for
> > > > enable/disable them.
> > > >
> > > > The patch (2) split Loongson EXTensions (EXT) instructions from
> > > > loongson3a, add -mloongson-ext/-mno-loongson-ext option for
> > > > enable/disable them.
> > > >
> > > > The patch (3) add Loongson EXTensions R2 (EXT2) instructions support,
> > > > add -mloongson-ext2/-mno-loongson-ext2 option for enable/disable them.
> > > >
> > > > The patch (4) add Loongson 3A1000 processor support.  The gs464 is a
> > > > codename of 3A1000 microarchitecture.  Rename -march=loongson3a to
> > > > -march=gs464, Keep -march=loongson3a as an alias of -march=gs464 for
> > > > compatibility.
> > > >
> > > > The patch (5) add Loongson 3A2000/3A3000 processor support.  Include
> > > > Loongson MMI, EXT, EXT2 instructions set.
> > > >
> > > > The patch (6) add Loongson 2K1000 processor support. Include Loongson
> > > > MMI, EXT, EXT2 and MSA instructions set.
> > > >
> > > > The binutils patch has been upstreamed.
> > > >
> > > > There are six patches in this set, as follows.
> > > > 1) 0001-MIPS-Add-support-for-loongson-mmi-instructions.patch
> > > > 2) 0002-MIPS-Add-support-for-Loongson-EXT-istructions.patch
> > > > 3) 0003-MIPS-Add-support-for-Loongson-EXT2-istructions.patch
> > > > 4) 0004-MIPS-Add-support-for-Loongson-3A1000-proccessor.patch
> > > > 5) 0005-MIPS-Add-support-for-Loongson-3A2000-3A3000-proccess.patch
> > > > 6) 0006-MIPS-Add-support-for-Loongson-2K1000-proccessor.patch
> > > >
> > > > All patchs test under mips64el-linux-gnu no new regressions.
> > > >
> > > > Ok for commit ?
> > > >
> > > > Thanks,
> > > > Paul Hua

Re: Notes on -mloongson-ext2

[Paul Hua]

Hi, Matthew:

Thanks for your review and suggestion.

> >}   \
> >\
> >+   \
>
> Remove excess new line.

Done.

> Also you have the EXT2 condition nested inside a check for EXT but you do
> not have any logic to ensure that use of EXT2 automatically enables EXT.
> Also you need logic to say that if a user explicitly says -mloongson-ext2
> -mno-loongson-ext then that is an error.

Done.

> >   /* Historical Octeon macro.  */  \
> >   if (TARGET_OCTEON)   \
> >builtin_define ("__OCTEON__");  \
>
> >diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md
> >index 4b7a627b7a6..c8128d4d530 100644
> >--- a/gcc/config/mips/mips.md
> >+++ b/gcc/config/mips/mips.md
> >@@ -335,6 +335,7 @@
> > ;; slt set less than instructions
> > ;; signext  sign extend instructions
> > ;; clz the clz and clo instructions
> >+;; ctz the ctz and cto instructions
>
> There is no need to add a new type here. These are for distinguishing
> between
> scheduling rules and I see no distinction being made in the schedulers. Just
> mark the new instructions as clz type.
> > ;; pop the pop instruction
> > ;; traptrap if instructions
> > ;; imulinteger multiply 2 operands
> >@@ -375,7 +376,7 @@
> > (define_attr "type"
> >
> "unknown,branch,jump,call,load,fpload,fpidxload,store,fpstore,fpidxstore,
> >
> prefetch,prefetchx,condmove,mtc,mfc,mthi,mtlo,mfhi,mflo,const,arith,logical,
> >-
> shift,slt,signext,clz,pop,trap,imul,imul3,imul3nc,imadd,idiv,idiv3,move,
> >+
> shift,slt,signext,clz,ctz,pop,trap,imul,imul3,imul3nc,imadd,idiv,idiv3,move,
>
> As above no need for this.

Done.

>
> >@@ -7136,13 +7154,16 @@
> > (match_operand 2 "const_int_operand" "n"))]
> >   "ISA_HAS_PREFETCH && TARGET_EXPLICIT_RELOCS"
> > {
> >-  if (TARGET_LOONGSON_2EF || TARGET_LOONGSON_EXT)
> >+  if (TARGET_LOONGSON_2EF || TARGET_LOONGSON_EXT || TARGET_LOONGSON_EXT2)
>
> This does not look correct. Is operand 1 really in the format you want for
> EXT2? Does it not need the appropriate MIPS prefetch value calculating like
> below for the non-loongson cores?

I made a mistake.  Loongson only implements perf hint=0 and hint=1, So
other case just
set to load or store. Updated patch.

> I suggest changing this to:
>
> if ((TARGET_LOONGSON_2EF || TARGET_LOONGSON_EXT)
> && !TARGET_LOONGSON_EXT2)
>
> And let the standard non-loongson code take care of the rest.
>
> > {
> >-  /* Loongson 2[ef] and Loongson 3a use load to $0 for prefetching.
> */
> >+  /* Loongson ext2 implementation pref insnstructions.  */
> >+  if (TARGET_LOONGSON_EXT2)
> >+   return "pref\t%1, %a0";
> >+  /* Loongson 2[ef] and Loongson ext use load to $0 for prefetching.
> */
> >   if (TARGET_64BIT)
> >-return "ld\t$0,%a0";
> >+   return "ld\t$0,%a0";
> >   else
> >-return "lw\t$0,%a0";
> >+   return "lw\t$0,%a0";
> > }
> >   operands[1] = mips_prefetch_cookie (operands[1], operands[2]);
> >   return "pref\t%1,%a0";
>
> This one needs resubmitting to check the updated logic.
> Thanks,
> Matthew
>

Thanks again.

Paul Hua
From 3bedc3c580e1cf570b5ad0717ffac985a84fbc40 Mon Sep 17 00:00:00 2001
From: Chenghua Xu 
Date: Fri, 31 Aug 2018 11:55:48 +0800
Subject: [PATCH] Add support for Loongson EXT2 istructions.

gcc/
	* config/mips/mips-protos.h
	(mips_loongson_ext2_prefetch_cookie): New prototype.
	* config/mips/mips.c (mips_loongson_ext2_prefetch_cookie): New.
	(mips_option_override): Enable TARGET_LOONGSON_EXT when
	TARGET_LOONGSON_EXT2 is true.
	* config/mips/mips.h (TARGET_CPU_CPP_BUILTINS): Define
	__mips_loongson_ext2, __mips_loongson_ext_rev=2.
	(ISA_HAS_CTZ_CTO): New, ture if TARGET_LOONGSON_EXT2.
	(ISA_HAS_PREFETCH): Include TARGET_LOONGSON_EXT and
	TARGET_LOONGSON_EXT2.
	(ASM_SPEC): Add mloongson-ext2 and mno-loongson-ext2.
	(define_insn "ctz2"): New insn pattern.
	(define_insn "prefetch"): Include TARGET_LOONGSON_EXT2.
	(define_insn "prefetch_indexed_"): Include
	TARGET_LOONGSON_EXT and TARGET_LOONGSON_EXT2.
	* config/mips/mips.opt (-mloongson-ext2): Add option.
	* gcc/doc/invoke.texi (-mloongso

[PATCH v3 1/6, Committed] [MIPS] Split Loongson (MMI) from loongson3a

[Paul Hua]

Hi, Matthew:

I committed the patch. Thanks for your review.

On Tue, Oct 16, 2018 at 10:50 AM Paul Hua  wrote:
>
>
From f0e4191439f1dd212b766ea80852aad1919e4887 Mon Sep 17 00:00:00 2001
From: Chenghua Xu 
Date: Mon, 5 Nov 2018 16:34:50 +0800
Subject: [PATCH 1/6] Add support for loongson mmi instructions.

gcc/
	* config.gcc (extra_headers): Add loongson-mmiintrin.h.
	* config/mips/loongson.md: Move to ...
	* config/mips/loongson-mmi.md: here; Adjustment.
	* config/mips/loongson.h: Move to ...
	State as deprecated. Include loongson-mmiintrin.h for back
	compatibility and warning.
	* config/mips/loongson-mmiintrin.h: ... here.
	* config/mips/mips.c (mips_hard_regno_mode_ok_uncached,
	mips_vector_mode_supported_p, AVAIL_NON_MIPS16): Use
	TARGET_LOONGSON_MMI instead of TARGET_LOONGSON_VECTORS.
	(mips_option_override): Make sure MMI use hard float;
	(mips_shift_truncation_mask, mips_expand_vpc_loongson_even_odd,
	mips_expand_vpc_loongson_pshufh, mips_expand_vpc_loongson_bcast,
	mips_expand_vector_init): Use TARGET_LOONGSON_MMI instead of
	TARGET_LOONGSON_VECTORS.
	* gcc/config/mips/mips.h (TARGET_LOONGSON_VECTORS): Delete.
	(TARGET_CPU_CPP_BUILTINS): Add __mips_loongson_mmi.
	(MIPS_ASE_DSP_SPEC, MIPS_ASE_LOONGSON_MMI_SPEC): New.
	(BASE_DRIVER_SELF_SPECS): march=loongson2e/2f/3a implies
	-mloongson-mmi.
	(SHIFT_COUNT_TRUNCATED): Use TARGET_LOONGSON_MMI instead of
	TARGET_LOONGSON_VECTORS.
	* gcc/config/mips/mips.md (MOVE64, MOVE128): Use
	TARGET_LOONGSON_MMI instead of TARGET_LOONGSON_VECTORS.
	(Loongson MMI patterns): Include loongson-mmi.md instead of
	loongson.md.
	* gcc/config/mips/mips.opt (-mloongson-mmi): New option.
	* gcc/doc/invoke.texi (-mloongson-mmi): Document.

gcc/testsuite/
	* gcc.target/mips/loongson-shift-count-truncated-1.c
	(dg-options): Run under -mloongson-mmi option.
	Include loongson-mmiintrin.h instead of loongson.h.
	* gcc.target/mips/loongson-simd.c: Likewise.
	* gcc.target/mips/mips.exp (mips_option_groups): Add
	-mloongson-mmi option.
	(mips-dg-options): Add mips_option_dependency options "-mips16" vs
	"-mno-loongson-mmi", "-mmicromips" vs "-mno-loongson-mmi",
	"-msoft-float" vs "-mno-loongson-mmi".
	(mips-dg-init): Add -mloongson-mmi option.
	* lib/target-supports.exp: Rename check_mips_loongson_hw_available
	to check_mips_loongson_mmi_hw_available.
	Rename check_effective_target_mips_loongson_runtime to
	check_effective_target_mips_loongson_mmi_runtime.
	(check_effective_target_vect_int): Use mips_loongson_mmi instead
	of mips_loongson when check et-is-effective-target.
	(add_options_for_mips_loongson_mmi): New proc.
	Rename check_effective_target_mips_loongson to
	check_effective_target_mips_loongson_mmi.
	(check_effective_target_vect_shift,
	check_effective_target_whole_vector_shift,
	check_effective_target_vect_no_int_min_max,
	check_effective_target_vect_no_align,
	check_effective_target_vect_short_mult,
	check_vect_support_and_set_flags):Use mips_loongson_mmi instead
	of mips_loongson when check et-is-effective-target.
---
 gcc/config.gcc|   2 +-
 .../mips/{loongson.md => loongson-mmi.md} | 155 ++--
 gcc/config/mips/loongson-mmiintrin.h  | 691 ++
 gcc/config/mips/loongson.h| 669 +
 gcc/config/mips/mips.c|  27 +-
 gcc/config/mips/mips.h|  36 +-
 gcc/config/mips/mips.md   |  16 +-
 gcc/config/mips/mips.opt  |   4 +
 gcc/doc/invoke.texi   |   7 +
 .../mips/loongson-shift-count-truncated-1.c   |   6 +-
 gcc/testsuite/gcc.target/mips/loongson-simd.c |   4 +-
 gcc/testsuite/gcc.target/mips/mips.exp|  10 +
 gcc/testsuite/lib/target-supports.exp |  47 +-
 13 files changed, 877 insertions(+), 797 deletions(-)
 rename gcc/config/mips/{loongson.md => loongson-mmi.md} (88%)
 create mode 100644 gcc/config/mips/loongson-mmiintrin.h

diff --git a/gcc/config.gcc b/gcc/config.gcc
index 5e5c328ed4c..e275a673836 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -458,7 +458,7 @@ microblaze*-*-*)
 mips*-*-*)
 	cpu_type=mips
 	d_target_objs="mips-d.o"
-	extra_headers="loongson.h msa.h"
+	extra_headers="loongson.h loongson-mmiintrin.h msa.h"
 	extra_objs="frame-header-opt.o"
 	extra_options="${extra_options} g.opt fused-madd.opt mips/mips-tables.opt"
 	;;
diff --git a/gcc/config/mips/loongson.md b/gcc/config/mips/loongson-mmi.md
similarity index 88%
rename from gcc/config/mips/loongson.md
rename to gcc/config/mips/loongson-mmi.md
index 14794d3671f..b126e625ed5 100644
--- a/gcc/config/mips/loongson.md
+++ b/gcc/config/mips/loongson-mmi.md
@@ -1,5 +1,4 @@
-;; Machine description for Loongson-specific patterns, such as
-;; ST Microelectronics Loongson-2E/2F etc.
+;; Machine description for Loongson MultiMedia extensions Instructions (MMI).
 ;; Copyright 

[PATCH v4 2/6, Committed] [MIPS] Split Loongson EXTensions (EXT) instructions from loongson3a

[Paul Hua]

On Tue, Oct 16, 2018 at 10:50 AM Paul Hua  wrote:
>
>
From b1dfcb228934e3cde90f408056192ed7faff4417 Mon Sep 17 00:00:00 2001
From: Chenghua Xu 
Date: Tue, 6 Nov 2018 17:04:36 +0800
Subject: [PATCH 2/6] Add support for Loongson EXT instructions.

gcc/
	* config/mips/mips.h (TARGET_CPU_CPP_BUILTINS): Add
	__mips_loongson_ext.
	(MIPS_ASE_LOONGSON_EXT_SPEC): New.
	(BASE_DRIVER_SELF_SPECS): march=loongson3a implies
	-mloongson-ext.
	(ASM_SPEC): Add mloongson-ext and mno-loongson-ext.
	* config/mips/mips.md (mul3, mul3_mul3_nohilo,
	div3, mod3, prefetch): Use TARGET_LOONGSON_EXT
	instead of TARGET_LOONGSON_3A.
	* config/mips/mips.opt (-mloongson-ext): Add option.
	* gcc/doc/invoke.texi (-mloongson-ext): Document.

gcc/testsuite/
	* gcc.target/mips/mips.exp (mips_option_groups): Add
	-mloongson-ext option.
	(mips-dg-options): Add mips_option_dependency options
	"-mmicromips" vs "-mno-loongson-ext",
---
 gcc/config/mips/mips.h | 14 +-
 gcc/config/mips/mips.md| 16 
 gcc/config/mips/mips.opt   |  4 
 gcc/doc/invoke.texi|  7 +++
 gcc/testsuite/gcc.target/mips/mips.exp |  2 ++
 5 files changed, 34 insertions(+), 9 deletions(-)

diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h
index 27c0222ee46..7237c8da8ac 100644
--- a/gcc/config/mips/mips.h
+++ b/gcc/config/mips/mips.h
@@ -596,6 +596,12 @@ struct mips_cpu_info {
 	  builtin_define ("__mips_loongson_mmi");			\
 	}\
 	\
+  /* Whether Loongson EXT modes are enabled.  */			\
+  if (TARGET_LOONGSON_EXT)		\
+	{\
+	  builtin_define ("__mips_loongson_ext");			\
+	}\
+	\
   /* Historical Octeon macro.  */	\
   if (TARGET_OCTEON)		\
 	builtin_define ("__OCTEON__");	\
@@ -881,7 +887,8 @@ struct mips_cpu_info {
 #define BASE_DRIVER_SELF_SPECS	\
   MIPS_ISA_NAN2008_SPEC,	\
   MIPS_ASE_DSP_SPEC, 		\
-  MIPS_ASE_LOONGSON_MMI_SPEC
+  MIPS_ASE_LOONGSON_MMI_SPEC,	\
+  MIPS_ASE_LOONGSON_EXT_SPEC
 
 #define MIPS_ASE_DSP_SPEC \
   "%{!mno-dsp: \
@@ -893,6 +900,10 @@ struct mips_cpu_info {
   "%{!mno-loongson-mmi:\
  %{march=loongson2e|march=loongson2f|march=loongson3a: -mloongson-mmi}}"
 
+#define MIPS_ASE_LOONGSON_EXT_SPEC		\
+  "%{!mno-loongson-ext:\
+ %{march=loongson3a: -mloongson-ext}}"
+
 #define DRIVER_SELF_SPECS \
   MIPS_ISA_LEVEL_SPEC,	  \
   BASE_DRIVER_SELF_SPECS
@@ -1367,6 +1378,7 @@ struct mips_cpu_info {
 %{mginv} %{mno-ginv} \
 %{mmsa} %{mno-msa} \
 %{mloongson-mmi} %{mno-loongson-mmi} \
+%{mloongson-ext} %{mno-loongson-ext} \
 %{msmartmips} %{mno-smartmips} \
 %{mmt} %{mno-mt} \
 %{mfix-rm7000} %{mno-fix-rm7000} \
diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md
index a88c1c53134..4b7a627b7a6 100644
--- a/gcc/config/mips/mips.md
+++ b/gcc/config/mips/mips.md
@@ -1599,7 +1599,7 @@
 {
   rtx lo;
 
-  if (TARGET_LOONGSON_2EF || TARGET_LOONGSON_3A || ISA_HAS_R6MUL)
+  if (TARGET_LOONGSON_2EF || TARGET_LOONGSON_EXT || ISA_HAS_R6MUL)
 emit_insn (gen_mul3_mul3_nohilo (operands[0], operands[1],
 	   operands[2]));
   else if (ISA_HAS_MUL3)
@@ -1622,11 +1622,11 @@
   [(set (match_operand:GPR 0 "register_operand" "=d")
 (mult:GPR (match_operand:GPR 1 "register_operand" "d")
   (match_operand:GPR 2 "register_operand" "d")))]
-  "TARGET_LOONGSON_2EF || TARGET_LOONGSON_3A || ISA_HAS_R6MUL"
+  "TARGET_LOONGSON_2EF || TARGET_LOONGSON_EXT || ISA_HAS_R6MUL"
 {
   if (TARGET_LOONGSON_2EF)
 return "multu.g\t%0,%1,%2";
-  else if (TARGET_LOONGSON_3A)
+  else if (TARGET_LOONGSON_EXT)
 return "gsmultu\t%0,%1,%2";
   else
 return "mul\t%0,%1,%2";
@@ -3016,11 +3016,11 @@
   [(set (match_operand:GPR 0 "register_operand" "=&d")
 	(any_div:GPR (match_operand:GPR 1 "register_operand" "d")
 		 (match_operand:GPR 2 "register_operand" "d")))]
-  "TARGET_LOONGSON_2EF || TARGET_LOONGSON_3A || ISA_HAS_R6DIV"
+  "TARGET_LOONGSON_2EF || TARGET_LOONGSON_EXT || ISA_HAS_R6DIV"
   {
 if (TARGET_LOONGSON_2EF)
   return mips_output_division ("div.g\t%0,%1,%2", operands);
-else if (TARGET_LOONGSON_3A)
+else if (TARGET_LOONGSON_EXT)
   return mips_output_division ("gsdiv\t%0,%1,%2", operands);
 else
   return mips_output_division ("div\t%0,%1,%2", operands);
@@ -3032,11 +3032,11 @@
   [(set (match_operand:GPR 0 "register_operand" "=&d")
 	(any_mod:GPR (match_operand:GPR 1 "register_operand" "d")
 		 (match_operand:GPR 2 "register_operand" "d")))]
-  "TARGET_LOONGSON_2EF || TARGET_LOONGSON_3A || ISA_HAS_R6DIV"
+  "TARGE

[PATCH v4 3/6,Committed] [MIPS] Add Loongson EXTensions R2 (EXT2) instructions support

[Paul Hua]

On Tue, Oct 16, 2018 at 10:50 AM Paul Hua  wrote:
>
>
From 73a4aac5034307cf7369bb70fa407709502fffbf Mon Sep 17 00:00:00 2001
From: Chenghua Xu 
Date: Fri, 31 Aug 2018 11:55:48 +0800
Subject: [PATCH 3/6] Add support for Loongson EXT2 instructions.

gcc/
	* config/mips/mips-protos.h
	(mips_loongson_ext2_prefetch_cookie): New prototype.
	* config/mips/mips.c (mips_loongson_ext2_prefetch_cookie): New.
	(mips_option_override): Enable TARGET_LOONGSON_EXT when
	TARGET_LOONGSON_EXT2 is true.
	* config/mips/mips.h (TARGET_CPU_CPP_BUILTINS): Define
	__mips_loongson_ext2, __mips_loongson_ext_rev=2.
	(ISA_HAS_CTZ_CTO): New, true if TARGET_LOONGSON_EXT2.
	(ISA_HAS_PREFETCH): Include TARGET_LOONGSON_EXT and
	TARGET_LOONGSON_EXT2.
	(ASM_SPEC): Add mloongson-ext2 and mno-loongson-ext2.
	(define_insn "ctz2"): New insn pattern.
	(define_insn "prefetch"): Include TARGET_LOONGSON_EXT2.
	(define_insn "prefetch_indexed_"): Include
	TARGET_LOONGSON_EXT and TARGET_LOONGSON_EXT2.
	* config/mips/mips.opt (-mloongson-ext2): Add option.
	* gcc/doc/invoke.texi (-mloongson-ext2): Document.

gcc/testsuite/
	* gcc.target/mips/loongson-ctz.c: New test.
	* gcc.target/mips/loongson-dctz.c: Likewise.
	* gcc.target/mips/mips.exp (mips_option_groups): Add
	-mloongson-ext2 option.
---
 gcc/config/mips/mips-protos.h |  1 +
 gcc/config/mips/mips.c| 28 +++
 gcc/config/mips/mips.h| 15 +-
 gcc/config/mips/mips.md   | 47 +--
 gcc/config/mips/mips.opt  |  4 ++
 gcc/doc/invoke.texi   |  7 +++
 gcc/testsuite/gcc.target/mips/loongson-ctz.c  | 11 +
 gcc/testsuite/gcc.target/mips/loongson-dctz.c | 11 +
 gcc/testsuite/gcc.target/mips/mips.exp|  1 +
 9 files changed, 120 insertions(+), 5 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/mips/loongson-ctz.c
 create mode 100644 gcc/testsuite/gcc.target/mips/loongson-dctz.c

diff --git a/gcc/config/mips/mips-protos.h b/gcc/config/mips/mips-protos.h
index 099120db7b4..7cde2424016 100644
--- a/gcc/config/mips/mips-protos.h
+++ b/gcc/config/mips/mips-protos.h
@@ -323,6 +323,7 @@ extern bool mips_linked_madd_p (rtx_insn *, rtx_insn *);
 extern bool mips_store_data_bypass_p (rtx_insn *, rtx_insn *);
 extern int mips_dspalu_bypass_p (rtx, rtx);
 extern rtx mips_prefetch_cookie (rtx, rtx);
+extern rtx mips_loongson_ext2_prefetch_cookie (rtx, rtx);
 
 extern const char *current_section_name (void);
 extern unsigned int current_section_flags (void);
diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
index b579c3c3a2a..1c2075044d0 100644
--- a/gcc/config/mips/mips.c
+++ b/gcc/config/mips/mips.c
@@ -15142,6 +15142,22 @@ mips_prefetch_cookie (rtx write, rtx locality)
   /* store_retained / load_retained.  */
   return GEN_INT (INTVAL (write) + 6);
 }
+
+/* Loongson EXT2 only implements perf hint=0 (prefetch for load) and hint=1
+   (prefetch for store), other hint just scale to hint = 0 and hint = 1.  */
+
+rtx
+mips_loongson_ext2_prefetch_cookie (rtx write, rtx locality)
+{
+  /* store.  */
+  if (INTVAL (write) == 1)
+return GEN_INT (INTVAL (write));
+
+  /* load.  */
+  if (INTVAL (write) == 0)
+return GEN_INT (INTVAL (write));
+}
+
 
 /* Flags that indicate when a built-in function is available.
 
@@ -20171,6 +20187,18 @@ mips_option_override (void)
   if (TARGET_LOONGSON_MMI &&  !TARGET_HARD_FLOAT_ABI)
 error ("%<-mloongson-mmi%> must be used with %<-mhard-float%>");
 
+  /* If TARGET_LOONGSON_EXT2, enable TARGET_LOONGSON_EXT.  */
+  if (TARGET_LOONGSON_EXT2)
+{
+  /* Make sure that when TARGET_LOONGSON_EXT2 is true, TARGET_LOONGSON_EXT
+	 is true.  If a user explicitly says -mloongson-ext2 -mno-loongson-ext
+	 then that is an error.  */
+  if (!TARGET_LOONGSON_EXT
+	  && !((target_flags_explicit & MASK_LOONGSON_EXT) == 0))
+	error ("%<-mloongson-ext2%> must be used with %<-mloongson-ext%>");
+  target_flags |= MASK_LOONGSON_EXT;
+}
+
   /* .eh_frame addresses should be the same width as a C pointer.
  Most MIPS ABIs support only one pointer size, so the assembler
  will usually know exactly how big an .eh_frame address is.
diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h
index 7237c8da8ac..beeb4bcf20d 100644
--- a/gcc/config/mips/mips.h
+++ b/gcc/config/mips/mips.h
@@ -600,6 +600,13 @@ struct mips_cpu_info {
   if (TARGET_LOONGSON_EXT)		\
 	{\
 	  builtin_define ("__mips_loongson_ext");			\
+	  if (TARGET_LOONGSON_EXT2)	\
+	{\
+	  builtin_define ("__mips_loongson_ext2");			\
+	  builtin_define ("__mips_loongson_ext_rev=2");		\
+	}\
+	  else\
+	  builtin_define ("__mips_loongson_ext_rev=1");		\
 	}\
 	\
   /* Historical Octeon macro.  */	\
@@

[PATCH v4 5/6,Committed] [MIPS] Add Loongson 3A2000/3A3000 processor support

[Paul Hua]

On Tue, Oct 16, 2018 at 10:50 AM Paul Hua  wrote:
>
>
From 51c914e8c2b2e4c7cc93718e563a8f55f0161ff9 Mon Sep 17 00:00:00 2001
From: Chenghua Xu 
Date: Wed, 7 Nov 2018 09:27:05 +0800
Subject: [PATCH 5/6] Add support for Loongson 3A2000/3A3000 processor.

gcc/
	* config/mips/gs464e.md: New.
	* config/mips/mips-cpus.def: Define gs464e.
	* config/mips/mips-tables.opt: Regenerate.
	* config/mips/mips.c (mips_rtx_cost_data): Add DEFAULT_COSTS for
	gs464e.
	(mips_issue_rate): Add support for gs464e.
	(mips_multipass_dfa_lookahead): Likewise.
	(mips_option_override): Enable MMI, EXT and EXT2 for gs464e.
	* config/mips/mips.h: Define TARGET_GS464E and TUNE_GS464E.
	(MIPS_ISA_LEVEL_SPEC): Infer mips64r2 from gs464e.
	(ISA_HAS_FUSED_MADD4): Enable for TARGET_GS464E.
	(ISA_HAS_UNFUSED_MADD4): Exclude TARGET_GS464E.
	* config/mips/mips.md: Include gs464e.md.
	(processor): Add gs464e.
	* doc/invoke.texi: Add gs464e to supported architectures.
---
 gcc/config/mips/gs464e.md   | 137 
 gcc/config/mips/mips-cpus.def   |   1 +
 gcc/config/mips/mips-tables.opt |  19 +++--
 gcc/config/mips/mips.c  |   6 +-
 gcc/config/mips/mips.h  |  13 ++-
 gcc/config/mips/mips.md |   2 +
 gcc/doc/invoke.texi |   1 +
 7 files changed, 166 insertions(+), 13 deletions(-)
 create mode 100644 gcc/config/mips/gs464e.md

diff --git a/gcc/config/mips/gs464e.md b/gcc/config/mips/gs464e.md
new file mode 100644
index 000..60e0e6b0463
--- /dev/null
+++ b/gcc/config/mips/gs464e.md
@@ -0,0 +1,137 @@
+;; Pipeline model for Loongson gs464e cores.
+
+;; Copyright (C) 2018 Free Software Foundation, Inc.
+;;
+;; This file is part of GCC.
+;;
+;; GCC is free software; you can redistribute it and/or modify it
+;; under the terms of the GNU General Public License as published
+;; by the Free Software Foundation; either version 3, or (at your
+;; option) any later version.
+;;
+;; GCC is distributed in the hope that it will be useful, but WITHOUT
+;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+;; License for more details.
+;;
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3.  If not see
+;; <http://www.gnu.org/licenses/>.
+
+;; Uncomment the following line to output automata for debugging.
+;; (automata_option "v")
+
+;; Automaton for integer instructions.
+(define_automaton "gs464e_a_alu")
+
+;; Automaton for floating-point instructions.
+(define_automaton "gs464e_a_falu")
+
+;; Automaton for memory operations.
+(define_automaton "gs464e_a_mem")
+
+;; Describe the resources.
+
+(define_cpu_unit "gs464e_alu1" "gs464e_a_alu")
+(define_cpu_unit "gs464e_alu2" "gs464e_a_alu")
+(define_cpu_unit "gs464e_mem1" "gs464e_a_mem")
+(define_cpu_unit "gs464e_mem2" "gs464e_a_mem")
+(define_cpu_unit "gs464e_falu1" "gs464e_a_falu")
+(define_cpu_unit "gs464e_falu2" "gs464e_a_falu")
+
+;; Describe instruction reservations.
+
+(define_insn_reservation "gs464e_arith" 1
+  (and (eq_attr "cpu" "gs464e")
+   (eq_attr "type" "arith,clz,const,logical,
+			move,nop,shift,signext,slt"))
+  "gs464e_alu1 | gs464e_alu2")
+
+(define_insn_reservation "gs464e_branch" 1
+  (and (eq_attr "cpu" "gs464e")
+   (eq_attr "type" "branch,jump,call,condmove,trap"))
+  "gs464e_alu1 | gs464e_alu2")
+
+(define_insn_reservation "gs464e_mfhilo" 1
+  (and (eq_attr "cpu" "gs464e")
+   (eq_attr "type" "mfhi,mflo,mthi,mtlo"))
+  "gs464e_alu1 | gs464e_alu2")
+
+;; Operation imul3nc is fully pipelined.
+(define_insn_reservation "gs464e_imul3nc" 5
+  (and (eq_attr "cpu" "gs464e")
+   (eq_attr "type" "imul3nc"))
+  "gs464e_alu1 | gs464e_alu2")
+
+(define_insn_reservation "gs464e_imul" 7
+  (and (eq_attr "cpu" "gs464e")
+   (eq_attr "type" "imul,imadd"))
+  "gs464e_alu1 | gs464e_alu2")
+
+(define_insn_reservation "gs464e_idiv_si" 12
+  (and (eq_attr "cpu" "gs464e")
+   (and (eq_attr "type" "idiv")
+	(eq_attr "mode" "SI")))
+  "gs464e_alu1 | gs464e_alu2")
+
+(define_insn_reservation "gs464e_idiv_di" 25
+  (and (eq_attr "cpu" "gs464e")
+   (and (eq_attr "type" "idiv")
+	(eq_attr "mode" "DI")))
+  "gs464e_alu1 | gs464e_alu2")
+
+(define_insn_reservation "gs464e_load" 4
+  (and (eq_attr "cpu" "gs464e&qu

[PATCH v4 4/6, Committed] [MIPS] Add Loongson 3A1000 processor support

[Paul Hua]

On Tue, Oct 16, 2018 at 10:50 AM Paul Hua  wrote:
>
>
From ef10d77f03e693299611e6b4eee2ae6375a5841d Mon Sep 17 00:00:00 2001
From: Chenghua Xu 
Date: Tue, 6 Nov 2018 21:12:46 +0800
Subject: [PATCH 4/6] Add support for Loongson 3A1000 processor.

gcc/
	* config/mips/loongson3a.md: Rename to ...
	* config/mips/gs464.md: ... here.
	* config/mips/mips-cpus.def: Define gs464; Add loongson3a
	as an alias of gs464 processor.
	* config/mips/mips-tables.opt: Regenerate.
	* config/mips/mips.c (mips_issue_rate): Use PROCESSOR_GS464
	instead of PROCESSOR_LOONGSON_3A.
	(mips_multipass_dfa_lookahead): Use TUNE_GS464 instead of
	TUNE_LOONGSON_3A.
	(mips_option_override): Enable MMI and EXT for gs464.
	* config/mips/mips.h: Rename TARGET_LOONGSON_3A to TARGET_GS464;
	Rename TUNE_LOONGSON_3A to TUNE_GS464.
	(MIPS_ISA_LEVEL_SPEC): Infer mips64r2 from gs464.
	(ISA_HAS_ODD_SPREG, ISA_AVOID_DIV_HILO, ISA_HAS_FUSED_MADD4,
	ISA_HAS_UNFUSED_MADD4): Use TARGET_GS464 instead of
	TARGET_LOONGSON_3A.
	* config/mips/mips.md: Include gs464.md instead of loongson3a.md.
	(processor): Add gs464;
	* doc/invoke.texi: Add gs464 to supported architectures.
---
 gcc/config/mips/gs464.md| 137 
 gcc/config/mips/loongson3a.md   | 137 
 gcc/config/mips/mips-cpus.def   |   3 +-
 gcc/config/mips/mips-tables.opt |  19 +++--
 gcc/config/mips/mips.c  |   6 +-
 gcc/config/mips/mips.h  |  17 ++--
 gcc/config/mips/mips.md |   4 +-
 gcc/doc/invoke.texi |   2 +-
 8 files changed, 165 insertions(+), 160 deletions(-)
 create mode 100644 gcc/config/mips/gs464.md
 delete mode 100644 gcc/config/mips/loongson3a.md

diff --git a/gcc/config/mips/gs464.md b/gcc/config/mips/gs464.md
new file mode 100644
index 000..82efb66786f
--- /dev/null
+++ b/gcc/config/mips/gs464.md
@@ -0,0 +1,137 @@
+;; Pipeline model for Loongson gs464 cores.
+
+;; Copyright (C) 2011-2018 Free Software Foundation, Inc.
+;;
+;; This file is part of GCC.
+;;
+;; GCC is free software; you can redistribute it and/or modify it
+;; under the terms of the GNU General Public License as published
+;; by the Free Software Foundation; either version 3, or (at your
+;; option) any later version.
+;;
+;; GCC is distributed in the hope that it will be useful, but WITHOUT
+;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+;; License for more details.
+;;
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3.  If not see
+;; <http://www.gnu.org/licenses/>.
+
+;; Uncomment the following line to output automata for debugging.
+;; (automata_option "v")
+
+;; Automaton for integer instructions.
+(define_automaton "gs464_a_alu")
+
+;; Automaton for floating-point instructions.
+(define_automaton "gs464_a_falu")
+
+;; Automaton for memory operations.
+(define_automaton "gs464_a_mem")
+
+;; Describe the resources.
+
+(define_cpu_unit "gs464_alu1" "gs464_a_alu")
+(define_cpu_unit "gs464_alu2" "gs464_a_alu")
+(define_cpu_unit "gs464_mem" "gs464_a_mem")
+(define_cpu_unit "gs464_falu1" "gs464_a_falu")
+(define_cpu_unit "gs464_falu2" "gs464_a_falu")
+
+;; Describe instruction reservations.
+
+(define_insn_reservation "gs464_arith" 1
+  (and (eq_attr "cpu" "gs464")
+   (eq_attr "type" "arith,clz,const,logical,
+			move,nop,shift,signext,slt"))
+  "gs464_alu1 | gs464_alu2")
+
+(define_insn_reservation "gs464_branch" 1
+  (and (eq_attr "cpu" "gs464")
+   (eq_attr "type" "branch,jump,call,condmove,trap"))
+  "gs464_alu1")
+
+(define_insn_reservation "gs464_mfhilo" 1
+  (and (eq_attr "cpu" "gs464")
+   (eq_attr "type" "mfhi,mflo,mthi,mtlo"))
+  "gs464_alu2")
+
+;; Operation imul3nc is fully pipelined.
+(define_insn_reservation "gs464_imul3nc" 5
+  (and (eq_attr "cpu" "gs464")
+   (eq_attr "type" "imul3nc"))
+  "gs464_alu2")
+
+(define_insn_reservation "gs464_imul" 7
+  (and (eq_attr "cpu" "gs464")
+   (eq_attr "type" "imul,imadd"))
+  "gs464_alu2 * 7")
+
+(define_insn_reservation "gs464_idiv_si" 12
+  (and (eq_attr "cpu" "gs464")
+   (and (eq_attr "type" "idiv")
+	(eq_attr "mode" "SI")))
+  "gs464_alu2 * 12")
+
+(define_insn_reservation "gs464_idiv_di" 25
+  (and (eq_attr "cpu" "gs464")
+   (and (eq_attr "type" "idiv")
+	(eq_attr "mode" "DI"

[PATCH v4 6/6,Committed] [MIPS] Add Loongson 2K1000 processor support

[Paul Hua]

On Tue, Oct 16, 2018 at 10:50 AM Paul Hua  wrote:
>
>
From 7ab0637b28b22bdb00e021692ceb8372855c8a87 Mon Sep 17 00:00:00 2001
From: Chenghua Xu 
Date: Wed, 7 Nov 2018 09:38:09 +0800
Subject: [PATCH 6/6] Add support for Loongson 2K1000 processor.

gcc/
	* config/mips/gs264e.md: New.
	* config/mips/mips-cpus.def: Define gs264e.
	* config/mips/mips-tables.opt: Regenerate.
	* config/mips/mips.c (mips_rtx_cost_data): Add DEFAULT_COSTS for
	gs264e.
	(mips_issue_rate): Add support for gs264e.
	(mips_multipass_dfa_lookahead): Likewise.
	* config/mips/mips.h: Define TARGET_GS264E and TUNE_GS264E.
	(MIPS_ISA_LEVEL_SPEC): Infer mips64r2 from gs264e.
	(MIPS_ASE_MSA_SPEC): New.
	(BASE_DRIVER_SELF_SPECS): march=gs264e implies -mmsa.
	(ISA_HAS_FUSED_MADD4): Enable for TARGET_GS264E.
	(ISA_HAS_UNFUSED_MADD4): Exclude TARGET_GS264E.
	* config/mips/mips.md: Include gs264e.md.
	(processor): Add gs264e.
	* config/mips/mips.opt (MSA): Use Mask instead of Var.
	* doc/invoke.texi: Add gs264e to supported architectures.
---
 gcc/config/mips/gs264e.md   | 133 
 gcc/config/mips/mips-cpus.def   |   1 +
 gcc/config/mips/mips-tables.opt |  19 +++--
 gcc/config/mips/mips.c  |   6 +-
 gcc/config/mips/mips.h  |  23 --
 gcc/config/mips/mips.md |   2 +
 gcc/config/mips/mips.opt|   2 +-
 gcc/doc/invoke.texi |   2 +-
 8 files changed, 171 insertions(+), 17 deletions(-)
 create mode 100644 gcc/config/mips/gs264e.md

diff --git a/gcc/config/mips/gs264e.md b/gcc/config/mips/gs264e.md
new file mode 100644
index 000..8f1f9e17e08
--- /dev/null
+++ b/gcc/config/mips/gs264e.md
@@ -0,0 +1,133 @@
+;; Pipeline model for Loongson gs264e cores.
+
+;; Copyright (C) 2018 Free Software Foundation, Inc.
+;;
+;; This file is part of GCC.
+;;
+;; GCC is free software; you can redistribute it and/or modify it
+;; under the terms of the GNU General Public License as published
+;; by the Free Software Foundation; either version 3, or (at your
+;; option) any later version.
+;;
+;; GCC is distributed in the hope that it will be useful, but WITHOUT
+;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+;; License for more details.
+;;
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3.  If not see
+;; <http://www.gnu.org/licenses/>.
+
+;; Uncomment the following line to output automata for debugging.
+;; (automata_option "v")
+
+;; Automaton for integer instructions.
+(define_automaton "gs264e_a_alu")
+
+;; Automaton for floating-point instructions.
+(define_automaton "gs264e_a_falu")
+
+;; Automaton for memory operations.
+(define_automaton "gs264e_a_mem")
+
+;; Describe the resources.
+
+(define_cpu_unit "gs264e_alu1" "gs264e_a_alu")
+(define_cpu_unit "gs264e_mem1" "gs264e_a_mem")
+(define_cpu_unit "gs264e_falu1" "gs264e_a_falu")
+
+;; Describe instruction reservations.
+
+(define_insn_reservation "gs264e_arith" 1
+  (and (eq_attr "cpu" "gs264e")
+   (eq_attr "type" "arith,clz,const,logical,
+			move,nop,shift,signext,slt"))
+  "gs264e_alu1")
+
+(define_insn_reservation "gs264e_branch" 1
+  (and (eq_attr "cpu" "gs264e")
+   (eq_attr "type" "branch,jump,call,condmove,trap"))
+  "gs264e_alu1")
+
+(define_insn_reservation "gs264e_mfhilo" 1
+  (and (eq_attr "cpu" "gs264e")
+   (eq_attr "type" "mfhi,mflo,mthi,mtlo"))
+  "gs264e_alu1")
+
+;; Operation imul3nc is fully pipelined.
+(define_insn_reservation "gs264e_imul3nc" 7
+  (and (eq_attr "cpu" "gs264e")
+   (eq_attr "type" "imul3nc"))
+  "gs264e_alu1")
+
+(define_insn_reservation "gs264e_imul" 7
+  (and (eq_attr "cpu" "gs264e")
+   (eq_attr "type" "imul,imadd"))
+  "gs264e_alu1")
+
+(define_insn_reservation "gs264e_idiv_si" 12
+  (and (eq_attr "cpu" "gs264e")
+   (and (eq_attr "type" "idiv")
+	(eq_attr "mode" "SI")))
+  "gs264e_alu1")
+
+(define_insn_reservation "gs264e_idiv_di" 25
+  (and (eq_attr "cpu" "gs264e")
+   (and (eq_attr "type" "idiv")
+	(eq_attr "mode" "DI")))
+  "gs264e_alu1")
+
+(define_insn_reservation "gs264e_load" 4
+  (and (eq_attr "cpu" "gs264e")
+   (eq_attr "type" "load"))
+  "gs264e_mem1")
+
+(define_insn_reservation "gs264e_fpload" 4
+  (and (eq_attr "cpu" "gs264e")
+   

Re: [PATCH v4 3/6,Committed] [MIPS] Add Loongson EXTensions R2 (EXT2) instructions support

[Paul Hua]

sorry, i commits a wrong version patch. Fix the typo and bad logical
by commits attached patch.
On Wed, Nov 7, 2018 at 5:14 PM Paul Hua  wrote:
>
> On Tue, Oct 16, 2018 at 10:50 AM Paul Hua  wrote:
> >
> >
From 16a357d8f844e4bdc45bf385e98b8dc6c0723720 Mon Sep 17 00:00:00 2001
From: Chenghua Xu 
Date: Wed, 7 Nov 2018 18:15:03 +0800
Subject: [PATCH] Fix some typo and brain twister logical.

gcc/
	* config/mips/mips.c: Fix typo in documentation of
	mips_loongson_ext2_prefetch_cookie.
	(mips_option_override): fix brain twister logical.
	* config/mips/mips.h: Fix typo in documentation of
	ISA_HAS_CTZ_CTO and define pattern.
	* config/mips/mips.md (prefetch): Hoist EXT2 above
	the 2EF/EXT block.
	(prefetch_indexed): Hoist EXT2 above the EXT block.

gcc/testsuite/
	* gcc.target/mips/loongson-ctz.c: Fix typo.
	* gcc.target/mips/loongson-dctz.c: Fix typo.
---
 gcc/config/mips/mips.c|  4 +--
 gcc/config/mips/mips.h|  2 +-
 gcc/config/mips/mips.md   | 34 +--
 gcc/testsuite/gcc.target/mips/loongson-ctz.c  |  2 +-
 gcc/testsuite/gcc.target/mips/loongson-dctz.c |  2 +-
 5 files changed, 22 insertions(+), 22 deletions(-)

diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
index 2b83e4ec679..d78e2056ec2 100644
--- a/gcc/config/mips/mips.c
+++ b/gcc/config/mips/mips.c
@@ -15151,7 +15151,7 @@ mips_prefetch_cookie (rtx write, rtx locality)
   return GEN_INT (INTVAL (write) + 6);
 }
 
-/* Loongson EXT2 only implements perf hint=0 (prefetch for load) and hint=1
+/* Loongson EXT2 only implements pref hint=0 (prefetch for load) and hint=1
(prefetch for store), other hint just scale to hint = 0 and hint = 1.  */
 
 rtx
@@ -20202,7 +20202,7 @@ mips_option_override (void)
 	 is true.  If a user explicitly says -mloongson-ext2 -mno-loongson-ext
 	 then that is an error.  */
   if (!TARGET_LOONGSON_EXT
-	  && !((target_flags_explicit & MASK_LOONGSON_EXT) == 0))
+	  && (target_flags_explicit & MASK_LOONGSON_EXT) != 0)
 	error ("%<-mloongson-ext2%> must be used with %<-mloongson-ext%>");
   target_flags |= MASK_LOONGSON_EXT;
 }
diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h
index 0a92cf6788a..11ca364d752 100644
--- a/gcc/config/mips/mips.h
+++ b/gcc/config/mips/mips.h
@@ -1158,7 +1158,7 @@ struct mips_cpu_info {
 /* ISA has count leading zeroes/ones instruction (not implemented).  */
 #define ISA_HAS_CLZ_CLO		(mips_isa_rev >= 1 && !TARGET_MIPS16)
 
-/* ISA has count tailing zeroes/ones instruction.  */
+/* ISA has count trailing zeroes/ones instruction.  */
 #define ISA_HAS_CTZ_CTO		(TARGET_LOONGSON_EXT2)
 
 /* ISA has three operand multiply instructions that put
diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md
index 9e222dc0df0..0cb0cb80bcd 100644
--- a/gcc/config/mips/mips.md
+++ b/gcc/config/mips/mips.md
@@ -3153,7 +3153,7 @@
 ;;
 ;;  ...
 ;;
-;;  Count tailing zeroes.
+;;  Count trailing zeroes.
 ;;
 ;;  ...
 ;;
@@ -7157,21 +7157,21 @@
 	 (match_operand 2 "const_int_operand" "n"))]
   "ISA_HAS_PREFETCH && TARGET_EXPLICIT_RELOCS"
 {
-  if (TARGET_LOONGSON_2EF || TARGET_LOONGSON_EXT || TARGET_LOONGSON_EXT2)
+  if (TARGET_LOONGSON_2EF || TARGET_LOONGSON_EXT)
 {
-  /* Loongson ext2 implementation pref insnstructions.  */
-  if (TARGET_LOONGSON_EXT2)
-	{
-  	  operands[1] = mips_loongson_ext2_prefetch_cookie (operands[1],
-			operands[2]);
-	  return "pref\t%1, %a0";
-	}
   /* Loongson 2[ef] and Loongson ext use load to $0 for prefetching.  */
   if (TARGET_64BIT)
 	return "ld\t$0,%a0";
   else
 	return "lw\t$0,%a0";
 }
+  /* Loongson ext2 implementation pref instructions.  */
+  if (TARGET_LOONGSON_EXT2)
+{
+  operands[1] = mips_loongson_ext2_prefetch_cookie (operands[1],
+			operands[2]);
+  return "pref\t%1, %a0";
+}
   operands[1] = mips_prefetch_cookie (operands[1], operands[2]);
   return "pref\t%1,%a0";
 }
@@ -7184,21 +7184,21 @@
 	 (match_operand 3 "const_int_operand" "n"))]
   "ISA_HAS_PREFETCHX && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
 {
-  if (TARGET_LOONGSON_EXT || TARGET_LOONGSON_EXT2)
+  if (TARGET_LOONGSON_EXT)
 {
-  /* Loongson ext2 implementation pref insnstructions.  */
-  if (TARGET_LOONGSON_EXT2)
-	{
-  	  operands[2] = mips_loongson_ext2_prefetch_cookie (operands[2],
-			operands[3]);
-	  return "prefx\t%2,%1(%0)";
-	}
   /* Loongson Loongson ext use index load to $0 for prefetching.  */
   if (TARGET_64BIT)
 	return "gsldx\t$0,0(%0,%1)";
   else
 	return "gslwx\t$0,0(%0,%1)";
 }
+  /* Loongson ext2 implementation pref instructions.  */
+  if (TARGET_LOONGSON_EXT2)
+{
+  operands[2] = mips_loongson_

Re: [PATCH v3 1/6, Committed] [MIPS] Split Loongson (MMI) from loongson3a

[Paul Hua]

On Wed, Nov 7, 2018 at 5:12 PM Paul Hua  wrote:
>
> Hi, Matthew:
>
> I committed the patch. Thanks for your review.
>

After committed this patch some test failure under
with-arch=mips64r2(i only test under -with-arch=loongson3a).

  664 FAIL: gcc.target/mips/insn-casesi.c   -O0  (test for excess
errors)
  665 FAIL: gcc.target/mips/insn-casesi.c   -O1  (test for excess
errors)
  666 FAIL: gcc.target/mips/insn-casesi.c   -O2  (test for excess
errors)
  667 FAIL: gcc.target/mips/insn-casesi.c   -O2 -flto
-fno-use-linker-plugin -flto-partition=none  (test for excess errors)
  668 FAIL: gcc.target/mips/insn-casesi.c   -O2 -flto
-fuse-linker-plugin -fno-fat-lto-objects  (test for excess errors)
  669 FAIL: gcc.target/mips/insn-casesi.c   -O3 -g  (test for excess
errors)
  670 FAIL: gcc.target/mips/insn-casesi.c   -Os  (test for excess errors)

The error message is " /usr/bin/as: unrecognized option '-mno-loongson-mmi' "

Those error come from follow options.
>   mips_option_dependency options "-mips16" "-mno-loongson-mmi"
>   mips_option_dependency options "-mmicromips" "-mno-loongson-mmi"
>   mips_option_dependency options "-msoft-float" "-mno-loongson-mmi"
>   mips_option_dependency options "-mmicromips" "-mno-loongson-ext"

We should add those dependency only config with
--with-arch=loongson3a/gs464/gs464e/gs246e.
I committed the attached patch as obvious.

Paul Hua
From 11a0bec83b3a0f2765d35b6aa84263016836f86e Mon Sep 17 00:00:00 2001
From: Chenghua Xu 
Date: Thu, 8 Nov 2018 15:01:35 +0800
Subject: [PATCH] Add mips option dependency only config with loongson target.

gcc/testsuite/
	* gcc.target/mips/mips.exp (mips-dg-options):
	Add mips_option_dependency msoft-float vs no-mmi and
	mips16/micromips vs no-mmi/ext/ext2 only gcc
	config with Loongson target.
---
 gcc/testsuite/gcc.target/mips/mips.exp | 17 +
 1 file changed, 13 insertions(+), 4 deletions(-)

diff --git a/gcc/testsuite/gcc.target/mips/mips.exp b/gcc/testsuite/gcc.target/mips/mips.exp
index e70d416d0dd..002cc280e30 100644
--- a/gcc/testsuite/gcc.target/mips/mips.exp
+++ b/gcc/testsuite/gcc.target/mips/mips.exp
@@ -1054,10 +1054,19 @@ proc mips-dg-options { args } {
 mips_option_dependency options "-mno-plt" "addressing=unknown"
 mips_option_dependency options "-mabicalls" "-G0"
 mips_option_dependency options "-mno-gpopt" "-mexplicit-relocs"
-mips_option_dependency options "-mips16" "-mno-loongson-mmi"
-mips_option_dependency options "-mmicromips" "-mno-loongson-mmi"
-mips_option_dependency options "-msoft-float" "-mno-loongson-mmi"
-mips_option_dependency options "-mmicromips" "-mno-loongson-ext"
+
+if { [check_configured_with "with-arch=loongson3a"] 
+	 || [check_configured_with "with-arch=gs464"]
+	 || [check_configured_with "with-arch=gs464e"]
+	 || [check_configured_with "with-arch=gs264e"] } {
+	mips_option_dependency options "-msoft-float" "-mno-loongson-mmi"
+	mips_option_dependency options "-mips16" "-mno-loongson-mmi"
+	mips_option_dependency options "-mips16" "-mno-loongson-ext"
+	mips_option_dependency options "-mips16" "-mno-loongson-ext2"
+	mips_option_dependency options "-mmicromips" "-mno-loongson-mmi"
+	mips_option_dependency options "-mmicromips" "-mno-loongson-ext"
+	mips_option_dependency options "-mmicromips" "-mno-loongson-ext2"
+}
 
 # Work out information about the current ABI.
 set abi_test_option_p [mips_test_option_p options abi]
-- 
2.18.0

[PATCH] [MIPS] GCC: Fix Loongson3 LLSC Errata

[Paul Hua]

In some older Loongson3 processors there is a LL/SC errata that can
cause the CPU to deadlock occasionally.  The details are very
complicated. We find a way to work around this errata by a) adding a
sync before ll/lld instruction, b) adding a sync
before branch target that between ll and sc. The assembler do the jobs
'a', gcc do the jobs 'b'.

This patch also add a configure options
--with-mips-fix-loongson3-llsc=[yes|no] to enable fix-loongson3-llsc
by config.
From 16f0fd9e32d2098637dc0eb3e576444c48c43f22 Mon Sep 17 00:00:00 2001
From: Chenghua Xu 
Date: Fri, 30 Nov 2018 19:57:38 +0800
Subject: [PATCH] [MIPS][GCC]  Fix Loongson3 LLSC Errata.

gcc/
	* config.gcc (supported_defaults): Add fix-loongson3-llsc
	(with_fix_loongson3_llsc): Add validation.
	(all_defaults): Add fix-loongson3-llsc.
	* config/mips/mips.c (mips_process_sync_loop): Add sync before
	branch target that between ll and sc.
	* config/mips/mips.h (OPTION_DEFAULT_SPECS): Add a default for
	fix-loongson3-llsc.
	gcc/config/mips/mips.opt: New option.
	* doc/install.texi (--with-fix-loongson3-llsc):Document the new
	option.
	* doc/invoke.texi (-mfix-loongson3-llsc):Document the new option.

gcc/testsuite/
	* gcc.target/mips/fix-loongson3-llsc.c: New test.
	* gcc.target/mips/mips.exp (option): Add fix-loongson3-llsc.
---
 gcc/config.gcc| 19 +--
 gcc/config/mips/mips.c| 13 +++--
 gcc/config/mips/mips.h|  4 +++-
 gcc/config/mips/mips.opt  |  4 
 gcc/doc/install.texi  |  4 
 gcc/doc/invoke.texi   |  8 
 .../gcc.target/mips/fix-loongson3-llsc.c  | 10 ++
 gcc/testsuite/gcc.target/mips/mips.exp|  1 +
 8 files changed, 58 insertions(+), 5 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/mips/fix-loongson3-llsc.c

diff --git a/gcc/config.gcc b/gcc/config.gcc
index f6162ed496e..9887b43dc87 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -4323,7 +4323,7 @@ case "${target}" in
 		;;
 
 	mips*-*-*)
-		supported_defaults="abi arch arch_32 arch_64 float fpu nan fp_32 odd_spreg_32 tune tune_32 tune_64 divide llsc mips-plt synci lxc1-sxc1 madd4"
+		supported_defaults="abi arch arch_32 arch_64 float fpu nan fp_32 odd_spreg_32 tune tune_32 tune_64 divide llsc mips-plt synci lxc1-sxc1 madd4 fix-loongson3-llsc"
 
 		case ${with_float} in
 		"" | soft | hard)
@@ -4476,6 +4476,21 @@ case "${target}" in
 			exit 1
 			;;
 		esac
+
+		case ${with_fix_loongson3_llsc} in
+		yes)
+			with_fix_loongson3_llsc=fix-loongson3-llsc
+			;;
+		no)
+			with_fix_loongson3_llsc=no-fix-loongson3-llsc
+			;;
+		"")
+			;;
+		*)
+			echo "Unknown fix-loongson3-llsc type used in --with-fix-loongson3-llsc" 1>&2
+			exit 1
+			;;
+		esac
 		;;
 
 	nds32*-*-*)
@@ -4995,7 +5010,7 @@ case ${target} in
 esac
 
 t=
-all_defaults="abi cpu cpu_32 cpu_64 arch arch_32 arch_64 tune tune_32 tune_64 schedule float mode fpu nan fp_32 odd_spreg_32 divide llsc mips-plt synci tls lxc1-sxc1 madd4"
+all_defaults="abi cpu cpu_32 cpu_64 arch arch_32 arch_64 tune tune_32 tune_64 schedule float mode fpu nan fp_32 odd_spreg_32 divide llsc mips-plt synci tls lxc1-sxc1 madd4 fix-loongson3-llsc"
 for option in $all_defaults
 do
 	eval "val=\$with_"`echo $option | sed s/-/_/g`
diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
index 55b44078518..717f3d03292 100644
--- a/gcc/config/mips/mips.c
+++ b/gcc/config/mips/mips.c
@@ -14127,7 +14127,7 @@ mips_process_sync_loop (rtx_insn *insn, rtx *operands)
   mips_multi_start ();
 
   /* Output the release side of the memory barrier.  */
-  if (need_atomic_barrier_p (model, true))
+  if (need_atomic_barrier_p (model, true) && !FIX_LOONGSON3_LLSC)
 {
   if (required_oldval == 0 && TARGET_OCTEON)
 	{
@@ -14148,6 +14148,10 @@ mips_process_sync_loop (rtx_insn *insn, rtx *operands)
   /* Output the branch-back label.  */
   mips_multi_add_label ("1:");
 
+  /* Loongson3 target need sync before ll/lld.  */
+  if (need_atomic_barrier_p (model,  true) && FIX_LOONGSON3_LLSC)
+mips_multi_add_insn ("sync", NULL);
+
   /* OLDVAL = *MEM.  */
   mips_multi_add_insn (is_64bit_p ? "lld\t%0,%1" : "ll\t%0,%1",
 		   oldval, mem, NULL);
@@ -14257,13 +14261,18 @@ mips_process_sync_loop (rtx_insn *insn, rtx *operands)
 mips_multi_add_insn ("li\t%0,1", cmp, NULL);
 
   /* Output the acquire side of the memory barrier.  */
-  if (TARGET_SYNC_AFTER_SC && need_atomic_barrier_p (model, false))
+  if (TARGET_SYNC_AFTER_SC && need_atomic_barrier_p (model, false)
+  && !FIX_LOONGSON3_LLSC)
 mips_multi_add_insn ("sync", NULL);
 
   /* Output the exit label, if needed.  */
   if (required_oldval)
 mips_multi_add_label ("2:");
 
+  /* Loongson3 need a sync before branch target that between ll and sc.  */
+  if (FIX_LOONGSON3_LLSC)
+mips_multi_add_insn ("sync", NULL);
+
 #undef READ_OPERAND
 }
 
diff --git a/gcc/config/mips/mips.h b/gcc/config/

[MIPS][Testsuite] specify msa-fmadd.c abis

[Paul Hua]

Hi,

The msa-fmadd.c fails on abi=64, the attached patch fixed by specify the abis.

spawn -ignore SIGHUP
/home/xuchenghua/GCC/test/gcc-r272929_obj/gcc/xgcc
-B/home/xuchenghua/GCC/test/gcc-r272929_obj/gcc/
/home/xuchenghua/GCC/gcc_git_trunk/gcc/testsuite/gcc.target/mips/msa-fmadd.c
-fno-diagnostics-show-caret -fno-diagnostics-show-line-numbers
-fdiagnostics-color=never -O1 -DNOMIPS16=__attribute__((nomips16))
-DNOMICROMIPS=__attribute__((nomicromips))
-DNOCOMPRESSION=__attribute__((nocompression)) -EL -mhard-float
-mdouble-float -mfp64 -mno-mips16 -modd-spreg -mmsa
-flax-vector-conversions -ffat-lto-objects -fno-ident -S -o
msa-fmadd.s^M
/home/xuchenghua/GCC/gcc_git_trunk/gcc/testsuite/gcc.target/mips/msa-fmadd.c:11:16:
warning: call-clobbered register used for global register variable^M
/home/xuchenghua/GCC/gcc_git_trunk/gcc/testsuite/gcc.target/mips/msa-fmadd.c:12:16:
warning: call-clobbered register used for global register variable^M
FAIL: gcc.target/mips/msa-fmadd.c   -O1  (test for excess errors)
Excess errors:
/home/xuchenghua/GCC/gcc_git_trunk/gcc/testsuite/gcc.target/mips/msa-fmadd.c:11:16:
warning: call-clobbered register used for global register variable
/home/xuchenghua/GCC/gcc_git_trunk/gcc/testsuite/gcc.target/mips/msa-fmadd.c:12:16:
warning: call-clobbered register used for global register variable


Ok for commit ?
From 912581f71ad37b415aec06d23210109e1c778296 Mon Sep 17 00:00:00 2001
From: Chenghua Xu 
Date: Mon, 17 Jun 2019 14:36:37 +0800
Subject: [PATCH] [MIPS][Testsuite] specify msa-fmadd.c abis.

gcc/testsuite/

	* gcc.target/mips/mips-fmadd.c: Rename to ...
	* gcc.target/mips/mips-fmadd-o32.c: ... Here; add abi=32.
	* gcc.target/mips/mips-fmadd-n64.c: New.
---
 gcc/testsuite/gcc.target/mips/msa-fmadd-n64.c  | 101 +
 .../mips/{msa-fmadd.c => msa-fmadd-o32.c}  |   2 +-
 2 files changed, 102 insertions(+), 1 deletion(-)
 create mode 100644 gcc/testsuite/gcc.target/mips/msa-fmadd-n64.c
 rename gcc/testsuite/gcc.target/mips/{msa-fmadd.c => msa-fmadd-o32.c} (96%)

diff --git a/gcc/testsuite/gcc.target/mips/msa-fmadd-n64.c b/gcc/testsuite/gcc.target/mips/msa-fmadd-n64.c
new file mode 100644
index 000..199b366512c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/mips/msa-fmadd-n64.c
@@ -0,0 +1,101 @@
+/* { dg-do compile } */
+/* { dg-options "-mabi=64 -mfp64 -mhard-float -mmsa -EL -flax-vector-conversions" } */
+/* { dg-skip-if "uses global registers" { *-*-* } { "-O0" } { "" } } */
+
+typedef int v4i32 __attribute__ ((vector_size(16)));
+typedef float v4f32 __attribute__ ((vector_size(16)));
+typedef double v2f64 __attribute__ ((vector_size(16)));
+
+/* Test that MSA FMADD-like intrinsics do not use first operand for multiplication.  */
+
+register v4i32 a __asm__("$f24");
+register v4i32 b __asm__("$f25");
+register v4f32 c __asm__("$f26");
+register v4f32 d __asm__("$f27");
+register v2f64 e __asm__("$f28");
+register v2f64 f __asm__("$f29");
+
+void
+maddv_b_msa (void)
+{
+  a = __builtin_msa_maddv_b (a, b, b);
+}
+/* { dg-final { scan-assembler "maddv\\\.b\t\\\$w24,\\\$w25,\\\$w25" } }  */
+
+void
+maddv_h_msa (void)
+{
+  a = __builtin_msa_maddv_h (a, b, b);
+}
+/* { dg-final { scan-assembler "maddv\\\.h\t\\\$w24,\\\$w25,\\\$w25" } }  */
+
+void
+maddv_w_msa (void)
+{
+  a = __builtin_msa_maddv_w (a, b, b);
+}
+/* { dg-final { scan-assembler "maddv\\\.w\t\\\$w24,\\\$w25,\\\$w25" } }  */
+
+void
+maddv_d_msa (void)
+{
+  a = __builtin_msa_maddv_d (a, b, b);
+}
+/* { dg-final { scan-assembler "maddv\\\.d\t\\\$w24,\\\$w25,\\\$w25" } }  */
+
+void
+msubv_b_msa (void)
+{
+  a = __builtin_msa_msubv_b (a, b, b);
+}
+/* { dg-final { scan-assembler "msubv\\\.b\t\\\$w24,\\\$w25,\\\$w25" } }  */
+
+void
+msubv_h_msa (void)
+{
+  a = __builtin_msa_msubv_h (a, b, b);
+}
+/* { dg-final { scan-assembler "msubv\\\.h\t\\\$w24,\\\$w25,\\\$w25" } }  */
+
+void
+msubv_w_msa (void)
+{
+  a = __builtin_msa_msubv_w (a, b, b);
+}
+/* { dg-final { scan-assembler "msubv\\\.w\t\\\$w24,\\\$w25,\\\$w25" } }  */
+
+void
+msubv_d_msa (void)
+{
+  a = __builtin_msa_msubv_d (a, b, b);
+}
+/* { dg-final { scan-assembler "msubv\\\.d\t\\\$w24,\\\$w25,\\\$w25" } }  */
+
+void
+fmadd_w_msa (void)
+{
+  c = __builtin_msa_fmadd_w (c, d, d);
+}
+/* { dg-final { scan-assembler "fmadd\\\.w\t\\\$w26,\\\$w27,\\\$w27" } }  */
+
+void
+fmadd_d_msa (void)
+{
+  e = __builtin_msa_fmadd_d (e, f, f);
+}
+/* { dg-final { scan-assembler "fmadd\\\.d\t\\\$w28,\\\$w29,\\\$w29" } }  */
+
+void
+fmsub_w_msa (void)
+{
+  c = __builtin_msa_fmsub_w (c, d, d);
+}
+/* { dg-final { scan-assembler "fmsub\\\.w\t\\\$w26,\\\$w27,\\\$w27" } }  */
+
+void
+fmsub_d_msa (void)
+{
+  e = __builtin_msa_fmsub_d (e, f, f);
+}
+/* { dg-final { scan-assembler "fmsub\\\.d\t\\\$w28,\\\$w29,\\\$w29" } }  */
+
diff --git a/gcc/testsuite/gcc.target/mips/msa-fmadd.c b/gcc/testsuite/gcc.target/mips/msa-fmadd-o32.c
similarity index 96%
rename from gcc/testsuite/gcc.target/mips/msa-fmadd.c
rename to gcc/testsuite/gcc.target/mips/msa-fma

Re: [wwwdoc][Patch] Mention Loongson 3a1000 3a2000 3a3000 2k1000 support in gcc9

[Paul Hua]

Hi,
This is a updated version, Ok for commit?


On Thu, Jan 17, 2019 at 10:05 AM Paul Hua  wrote:
>
> Hi Gerald,
>
> Updated version, please review.
>
> Thanks.
>
> On Mon, Jan 14, 2019 at 7:46 AM Gerald Pfeifer  wrote:
> >
> > Hi Paul,
> >
> > On Mon, 31 Dec 2018, Paul Hua wrote:
> > > The attached patch mention Loongson 3a1000 3a2000 3a3000 2k1000 support
> > > in gcc9.
> >
> > thanks for putting this together.  Only a couple of editorial changes:
> >
> > Index: changes.html
> > ===
> > +  
> > +The Loongson loongson-mmi and loongson-ext
> > +extension has now been splited from loongson3a:
> >
> > "...extensions have been split..."
> >
> > +
> > +   loongson-mmi which contains
> > +   the Loongson MultiMedia extension Instructions operations.
> > +   loongson-ext which contains
> > +   the Loongson EXTension instructions.
> >
> > Here I'd omit omit the two instances of "which"
> >
> > +The Loongson EXTension R2 instructions is now supported.
> >
> > "is" -> "are"
> >
> > +Use -mxxx or -mno-xxx will enable or disable those extersions.
> >
> > Since it's only two options, how about listing both of them?
> >
> > "extersion" -> "extension"
> >
> > +for example: Using 
> > -mloongson-mmi/-mno-loongson-mmi
> > +will enable/disable Loongson MultiMedia Instructions extensions.
> >
> > "...the Loongson MultiMedia Instructions extension."
> >
> > +   which default enable loongson-mmi, 
> > loongson-ext.
> >
> > "which enables ... by default"  (also in the following two items)
> >
> >
> > Please look into those comments and then simply post the updated patch
> > as you're committing it.
> >
> > Gerald
Index: htdocs/gcc-9/changes.html
===
RCS file: /cvs/gcc/wwwdocs/htdocs/gcc-9/changes.html,v
retrieving revision 1.57
diff -r1.57 changes.html
822,823c822,859
< 
< 
---
> MIPS
> 
>   
> The Loongson loongson-mmi and loongson-ext
> extensions have been split from loongson3a:
> 
>loongson-mmi contains
>the Loongson MMI (MultiMedia extensions Instructions).
>loongson-ext contains 
>the Loongson EXT (EXTensions instructions).
> 
>   
> The Loongson EXT2 (EXTensions R2 instructions) are now supported.
> 
>loongson-ext2 which contains the Loongson EXT2 instructions.
> 
> Use -m[no-]loongson-mmi -m[no-]loongson-ext -m[no-]loongson-ext2
> will enable or disable those extensions,
> for example: Using -mloongson-mmi/-mno-loongson-mmi 
> will enable/disable the Loongson MultiMedia Instructions extensions.
>   
> Support has been added for the following processors
> (GCC identifiers in parentheses):
> 
> 	Loongson 3A1000 (gs464)
> 	which enables loongson-mmi, loongson-ext by default.
> 	Loongson 3A2000/3A3000 (gs464e)
> 	which enables loongson-mmi, loongson-ext, loongson-ext2 by default.
> 	Loongson 2K1000 (gs264e)
> 	which enables loongson-ext, loongson-ext2, msa by default.
> 
> The GCC identifiers can be used
> as arguments to the -mcpu or -mtune options,
> for example: -mcpu=gs464 or
> -mtune=gs464e or as arguments to the equivalent target
> attributes and pragmas.
>   
> 

[PATCH][MIPS] Fix pr89623 Can't build mips-wrs-vxworks cross-compiler

[Paul Hua]

Hi,

The MIPS target  run out of Mask in mips.opt, we are stage4, this
patch retrieve loongson-ext that haven't used yet for now. In next
stage1, I will rewrite those part use HOST_WIDE_INT or same thing like
that.

Ok for commit ?

2019-04-04  Chenghua Xu  

gcc/
PR target/89623
* config/mips/mips.opt (LOONGSON_EXT2): Use Var instead of Mask.
From a7671686bb820a6be896e6c75f5d2dd23dc1441f Mon Sep 17 00:00:00 2001
From: Chenghua Xu 
Date: Thu, 4 Apr 2019 16:11:50 +0800
Subject: [PATCH] [MIPS] Set loongson-ext2 options to Var instead of Mask.

2019-04-04  Chenghua Xu  

gcc/
PR target/89623
* config/mips/mips.opt (LOONGSON_EXT2): Use Var instead of Mask.
---
 gcc/config/mips/mips.opt | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/config/mips/mips.opt b/gcc/config/mips/mips.opt
index f3702c4..817a482 100644
--- a/gcc/config/mips/mips.opt
+++ b/gcc/config/mips/mips.opt
@@ -473,5 +473,5 @@ Target Report Mask(LOONGSON_EXT)
 Use Loongson EXTension (EXT) instructions.
 
 mloongson-ext2
-Target Report Mask(LOONGSON_EXT2)
+Target Report Var(TARGET_LOONGSON_EXT2)
 Use Loongson EXTension R2 (EXT2) instructions.
-- 
1.8.3.1

[PATCH] [MIPS] Fix PR/target 90357 20080502-1.c -O0 start with r269880

[Paul Hua]

The attached patch fix pr90357, bootstraped and regressed test on
mips64el-linux-gnu target.
Ok for commit ?
From a3db8763ee8460a5f63c567d58624a985f9924ce Mon Sep 17 00:00:00 2001
From: Chenghua Xu 
Date: Mon, 6 May 2019 16:14:56 +0800
Subject: [PATCH] [PATCH,MIPS] Skip forward src into next insn when the SRC reg
 is dead.

	PR target/90357
	gcc/
	* config/mips/mips.c (mips_split_move): Skip forward SRC into
	next insn when the SRC reg is dead.
---
 gcc/config/mips/mips.c | 13 -
 1 file changed, 12 insertions(+), 1 deletion(-)

diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
index 1de33b2..89fc073 100644
--- a/gcc/config/mips/mips.c
+++ b/gcc/config/mips/mips.c
@@ -4849,6 +4849,7 @@ mips_split_move (rtx dest, rtx src, enum mips_split_type split_type, rtx insn_)
  can forward SRC for DEST.  This is most useful if the next insn is a
  simple store.   */
   rtx_insn *insn = (rtx_insn *)insn_;
+  struct mips_address_info addr;
   if (insn)
 {
   rtx_insn *next = next_nonnote_nondebug_insn_bb (insn);
@@ -4856,7 +4857,17 @@ mips_split_move (rtx dest, rtx src, enum mips_split_type split_type, rtx insn_)
 	{
 	  rtx set = single_set (next);
 	  if (set && SET_SRC (set) == dest)
-	validate_change (next, &SET_SRC (set), src, false);
+	{
+	  if (MEM_P (src))
+		{
+		  rtx tmp = XEXP (src, 0);
+		  mips_classify_address (&addr, tmp, GET_MODE (tmp), true);
+		  if (REGNO (addr.reg) != REGNO (dest))
+		validate_change (next, &SET_SRC (set), src, false);
+		}
+	  else
+		validate_change (next, &SET_SRC (set), src, false);
+	}
 	}
 }
 }
-- 
1.8.3.1

Re: [PATCH] [MIPS] Fix PR/target 90357 20080502-1.c -O0 start with r269880

[Paul Hua]

ping ?

On Mon, May 6, 2019 at 4:34 PM Paul Hua  wrote:
>
> The attached patch fix pr90357, bootstraped and regressed test on
> mips64el-linux-gnu target.
> Ok for commit ?

Re: [wwwdoc][Patch] Mention Loongson 3a1000 3a2000 3a3000 2k1000 support in gcc9

[Paul Hua]

ping?

On Mon, Dec 31, 2018 at 6:27 PM Paul Hua  wrote:
>
> Hi Gerald,
>
> The attached patch mention Loongson 3a1000 3a2000 3a3000 2k1000 support in 
> gcc9.
>
> ok for commit?

Re: [wwwdoc][Patch] Mention Loongson 3a1000 3a2000 3a3000 2k1000 support in gcc9

[Paul Hua]

Hi Gerald,

Updated version, please review.

Thanks.

On Mon, Jan 14, 2019 at 7:46 AM Gerald Pfeifer  wrote:
>
> Hi Paul,
>
> On Mon, 31 Dec 2018, Paul Hua wrote:
> > The attached patch mention Loongson 3a1000 3a2000 3a3000 2k1000 support
> > in gcc9.
>
> thanks for putting this together.  Only a couple of editorial changes:
>
> Index: changes.html
> ===
> +  
> +The Loongson loongson-mmi and loongson-ext
> +extension has now been splited from loongson3a:
>
> "...extensions have been split..."
>
> +
> +   loongson-mmi which contains
> +   the Loongson MultiMedia extension Instructions operations.
> +   loongson-ext which contains
> +   the Loongson EXTension instructions.
>
> Here I'd omit omit the two instances of "which"
>
> +The Loongson EXTension R2 instructions is now supported.
>
> "is" -> "are"
>
> +Use -mxxx or -mno-xxx will enable or disable those extersions.
>
> Since it's only two options, how about listing both of them?
>
> "extersion" -> "extension"
>
> +for example: Using 
> -mloongson-mmi/-mno-loongson-mmi
> +will enable/disable Loongson MultiMedia Instructions extensions.
>
> "...the Loongson MultiMedia Instructions extension."
>
> +   which default enable loongson-mmi, 
> loongson-ext.
>
> "which enables ... by default"  (also in the following two items)
>
>
> Please look into those comments and then simply post the updated patch
> as you're committing it.
>
> Gerald
Index: changes.html
===
RCS file: /cvs/gcc/wwwdocs/htdocs/gcc-9/changes.html,v
retrieving revision 1.35
diff -u -r1.35 changes.html
--- changes.html	15 Jan 2019 13:17:49 -	1.35
+++ changes.html	17 Jan 2019 02:03:20 -
@@ -261,6 +261,45 @@
   
 
 
+MIPS
+
+  
+The Loongson loongson-mmi and loongson-ext
+extensions have been split from loongson3a:
+
+   loongson-mmi contains
+   the Loongson MultiMedia extension Instructions operations.
+   loongson-ext contains 
+   the Loongson EXTension instructions.
+
+  
+The Loongson EXTension R2 instructions are now supported.
+
+   loongson-ext2 which contains the Loongson EXTension R2 instructions.
+
+Use -m[no-]loongson-mmi -m[no-]loongson-ext -m[no-]loongson-ext2
+will enable or disable those extensions,
+for example: Using -mloongson-mmi/-mno-loongson-mmi 
+will enable/disable the Loongson MultiMedia Instructions extensions.
+  
+Support has been added for the following processors
+(GCC identifiers in parentheses):
+
+	Loongson 3A1000 (gs464)
+	which enables loongson-mmi, loongson-ext by default.
+	Loongson 3A2000/3A3000 (gs464e)
+	which enables loongson-mmi, loongson-ext, loongson-ext2 by default.
+	Loongson 2K1000 (gs264e)
+	which enables loongson-ext, loongson-ext2, msa by default.
+
+The GCC identifiers can be used
+as arguments to the -mcpu or -mtune options,
+for example: -mcpu=gs464 or
+-mtune=gs464e or as arguments to the equivalent target
+attributes and pragmas.
+  
+
+
 
 
 

Re: [PATCH][Testsuite] Fix mips dsp testsuite mistakes

[Paul Hua]

I am wrong, I lost the sta16() in mips dsp manual.

Re: Ping on MIPS specific patch adds `short_call` synonym for `near` attribute

[Paul Hua]

Hi, Simon:

I would like to testing your patch on mips64el target. but your patch
can't apply to current trunk.

error likes:
--cut---
xuchenghua@fc21-2k4w:61: gcc_git_trunk $ patch -p0 <
add_short_call_attribute.patch
patching file gcc/config/mips/mips.c
Hunk #1 FAILED at 598.
Hunk #2 FAILED at 1171.
2 out of 2 hunks FAILED -- saving rejects to file gcc/config/mips/mips.c.rej
patching file gcc/doc/extend.texi
patching file gcc/testsuite/gcc.target/mips/near-far-1.c
patching file gcc/testsuite/gcc.target/mips/near-far-2.c
patching file gcc/testsuite/gcc.target/mips/near-far-3.c
patching file gcc/testsuite/gcc.target/mips/near-far-4.c
patch:  malformed patch at line 159:
"\t(j(|al|als)|b(|al)c)\tnormal_func\n" } } */
--

Could you give a new patch?

Thanks,

Paul Hua.

On Thu, Sep 7, 2017 at 7:22 PM, Simon Atanasyan  wrote:
> This is a ping for a small MIPS specific patch adds `short_call`
> synonym for existing `near` attribute. The patch has not been approved
> or commented on.
>
> Add 'short_call' attribute for MIPS targets.
> https://gcc.gnu.org/ml/gcc-patches/2017-08/msg01280.html
>
> --
> Simon Atanasyan

Re: Ping on MIPS specific patch adds `short_call` synonym for `near` attribute

[Paul Hua]

bootstrap and regtested on mips64el-unknown-linux-gnu.


On Sat, Sep 9, 2017 at 2:34 PM, Simon Atanasyan  wrote:
> Hi Paul,
>
> Probably the patch in the original message is broken somehow. Anyway I
> attach updated patch to this mail.
>
> $ svn up
> Updating '.':
> At revision 251918.
> $ patch -p0 < ~/add_short_call_attribute.patch
> patching file gcc/config/mips/mips.c
> patching file gcc/doc/extend.texi
> patching file gcc/testsuite/gcc.target/mips/near-far-1.c
> patching file gcc/testsuite/gcc.target/mips/near-far-2.c
> patching file gcc/testsuite/gcc.target/mips/near-far-3.c
> patching file gcc/testsuite/gcc.target/mips/near-far-4.c
>
> On Sat, Sep 09, 2017 at 11:26:57AM +0800, Paul Hua wrote:
>> I would like to testing your patch on mips64el target. but your patch
>> can't apply to current trunk.
>>
>> On Thu, Sep 7, 2017 at 7:22 PM, Simon Atanasyan  wrote:
>> > This is a ping for a small MIPS specific patch adds `short_call`
>> > synonym for existing `near` attribute. The patch has not been approved
>> > or commented on.
>> >
>> > Add 'short_call' attribute for MIPS targets.
>> > https://gcc.gnu.org/ml/gcc-patches/2017-08/msg01280.html
>
> --
> Simon Atanasyan

Re: Fix minor reorg.c bug affecting MIPS targets

[Paul Hua]

Hi:

There are new failures between r248067 and r248036 on
mips64el-unknown-linux-gnu.

  ERROR: gcc.target/mips/reorgbug-1.c   -O0 : Unrecognised option: -O2
for " dg-options 1 "-O2 -msoft-float -mips2" "
  UNRESOLVED: gcc.target/mips/reorgbug-1.c   -O0 : Unrecognised
option: -O2 for " dg-options 1 "-O2 -msoft-float -mips2" "
  ERROR: gcc.target/mips/reorgbug-1.c   -O1 : Unrecognised option: -O2
for " dg-options 1 "-O2 -msoft-float -mips2" "
  UNRESOLVED: gcc.target/mips/reorgbug-1.c   -O1 : Unrecognised
option: -O2 for " dg-options 1 "-O2 -msoft-float -mips2" "
  ERROR: gcc.target/mips/reorgbug-1.c   -O2 -flto
-fno-use-linker-plugin -flto-partition=none : Unrecognised option: -O2
for " dg-options 1 "-O2 -msoft-float -mips2" "
  UNRESOLVED: gcc.target/mips/reorgbug-1.c   -O2 -flto
-fno-use-linker-plugin -flto-partition=none : Unrecognised option: -O2
for " dg-options 1 "-O2 -msoft-float -mips2" "
  ERROR: gcc.target/mips/reorgbug-1.c   -O2 -flto -fuse-linker-plugin
-fno-fat-lto-objects : Unrecognised option: -O2 for " dg-options 1
"-O2 -msoft-float -mips2" "
  UNRESOLVED: gcc.target/mips/reorgbug-1.c   -O2 -flto
-fuse-linker-plugin -fno-fat-lto-objects : Unrecognised option: -O2
for " dg-options 1 "-O2 -msoft-float -mips2" "
  ERROR: gcc.target/mips/reorgbug-1.c   -O2 : Unrecognised option: -O2
for " dg-options 1 "-O2 -msoft-float -mips2" "
  UNRESOLVED: gcc.target/mips/reorgbug-1.c   -O2 : Unrecognised
option: -O2 for " dg-options 1 "-O2 -msoft-float -mips2" "
  ERROR: gcc.target/mips/reorgbug-1.c   -O3 -g : Unrecognised option:
-O2 for " dg-options 1 "-O2 -msoft-float -mips2" "
  UNRESOLVED: gcc.target/mips/reorgbug-1.c   -O3 -g : Unrecognised
option: -O2 for " dg-options 1 "-O2 -msoft-float -mips2" "
  ERROR: gcc.target/mips/reorgbug-1.c   -Os : Unrecognised option: -O2
for " dg-options 1 "-O2 -msoft-float -mips2" "
  UNRESOLVED: gcc.target/mips/reorgbug-1.c   -Os : Unrecognised
option: -O2 for " dg-options 1 "-O2 -msoft-float -mips2" "

I don't know why?  just delete the "-O2" options in dg-options,  then
the test passed.

diff --git a/gcc/testsuite/gcc.target/mips/reorgbug-1.c
b/gcc/testsuite/gcc.target/mips/reorgbug-1.c
index b820a2b..9537d21 100644
--- a/gcc/testsuite/gcc.target/mips/reorgbug-1.c
+++ b/gcc/testsuite/gcc.target/mips/reorgbug-1.c
@@ -1,4 +1,4 @@
-/* { dg-options "-O2 -msoft-float -mips2" } */
+/* { dg-options "-msoft-float -mips2" } */

 typedef long int __int32_t;
 typedef long unsigned int __uint32_t;

config info:Compiler version: 8.0.0 20170515 (experimental) (gcc trunk
r248067 mips64el o32 n32 n64)
Platform: mips64el-unknown-linux-gnu
configure flags: --prefix=/home/xuchenghua/toolchain/gcc-trunk-r248067
--enable-bootstrap --enable-shared --enable-threads=posix
--enable-checking=release --enable-multilib--with-system-zlib
--enable-__cxa_atexit --disable-libunwind-exceptions
--enable-gnu-unique-object --enable-linker-build-id
--enable-languages=c,c++,fortran --enable-plugin
--enable-initfini-array --disable-libgcj --with-arch=mips64r2
--with-abi=64 --with-multilib-list=32,n32,64
--enable-gnu-indirect-function --with-long-double-128
--build=mips64el-unknown-linux --target=mips64el-unknown-linux
--with-pkgversion='gcc trunk r248067 mips64el o32 n32 n64'
--disable-werror


paul

On Tue, May 16, 2017 at 1:22 AM, Jeff Law  wrote:
>
>
> There's a subtle bug in reorg.c's relax_delay_slots that my tester tripped
> this weekend.  Not sure what changed code generation wise as the affected
> port built just fine last week.  But it is what is is.
>
>
>
> Assume before this code we've set TARGET_LABEL to the code_label associated
> with DELAY_JUMP_INSN (which is what we want)...
>
>
>
>  /* If the first insn at TARGET_LABEL is redundant with a previous
>  insn, redirect the jump to the following insn and process again.
>  We use next_real_insn instead of next_active_insn so we
>  don't skip USE-markers, or we'll end up with incorrect
>  liveness info.  */
>
> [ ... ]
>
>  /* Similarly, if it is an unconditional jump with one insn in its
>  delay list and that insn is redundant, thread the jump.  */
>   rtx_sequence *trial_seq =
> trial ? dyn_cast  (PATTERN (trial)) : NULL;
>   if (trial_seq
>   && trial_seq->len () == 2
>   && JUMP_P (trial_seq->insn (0))
>   && simplejump_or_return_p (trial_seq->insn (0))
>   && redundant_insn (trial_seq->insn (1), insn, vNULL))
> {
>   target_label = JUMP_LABEL (trial_seq->insn (0));
>   if (ANY_RETURN_P (target_label))
> target_label = find_end_label (target_label);
>
>   if (target_label
>   && redirect_with_delay_slots_safe_p (delay_jump_insn,
>target_label, insn))
> {
>   update_block (trial_seq->insn (1), insn);
>   reorg_redirect_jump (delay_jump_insn, target_label);
>   next = insn;
>   cont

Re: Fix minor reorg.c bug affecting MIPS targets

[Paul Hua]

Hi:

commited as r248137.

Thanks,
paul.

On Wed, May 17, 2017 at 2:46 AM, Toma Tabacu  wrote:
> From: Jeff Law
>> On 05/16/2017 10:01 AM, Toma Tabacu wrote:
>>> Hello Paul,
>>>
>>> You're seeing this problem because mips.exp can't handle -O* in dg-options.
>>> The other tests in gcc.target/mips use a dg-skip-if to skip for -O0 and -O1 
>>> instead of having -O2 in dg-options.
>>> This is supposed to ensure that the tests are run for as many optimization 
>>> levels as possible.
>>>
>>> I believe that Matthew can confirm this.
>> Feel free to remove the -O2.  The most important bits are -mips2 and
>> -msoft-float.  If nobody does it shortly, I'll take care of it myself.
>>
>>jeff
>
> Sorry, I won't be able to commit the fix until tomorrow.
> Thanks for taking care of this issue, though.
>
> Regards,
> Toma Tabacu

Re: Ipa function summary pass

[Paul Hua]

Hi,
On mips64el target:
New Fail:
FAIL: gfortran.dg/pr48636.f90   -O   scan-ipa-dump fnsummary "inline
hints: loop_iterations"

Paul

On Wed, May 24, 2017 at 4:47 PM, Christophe Lyon
 wrote:
> Hi,
>
> On 23 May 2017 at 18:23, Jan Hubicka  wrote:
>> Hi,
>> this patch finishes the breakup of ipa-inline and function analysis.
>> The analysis is now done by separate pass and I will work on cleaning
>> up the interfaces now.
>>
>> Honza
>>
>> * cgraphunit.c (symbol_table::process_new_functions): Update.
>> * ipa-fnsummary.c (pass_data_inline_parameters): Remove.
>> (inline_generate_summary): Rename to ...
>> (ipa_fn_summary_generate): ... this one.
>> (inline_read_summary): Rename to ...
>> (ipa_fn_summary_read): ... this one.
>> (inline_write_summary): Rename to ...
>> (ipa_fn_summary_write): ... this one.
>> (inline_free_summary): Rename to ...
>> (ipa_free_fn_summary): ... this one.
>> (pass_data_local_fn_summary, pass_local_fn_summary,
>> make_pass_local_fn_summary, pass_data_ipa_free_fn_summary,
>> pass_ipa_free_fn_summary, make_pass_ipa_free_fn_summary,
>> pass_data_ipa_fn_summary, pass_ipa_fn_summary,
>> make_pass_ipa_fn_summary): New.
>> * ipa-fnsummary.h (inline_generate_summary, inline_read_summary,
>> inline_write_summary, inline_free_summary): Remove.
>> (ipa_free_fn_summary) : New.
>> * ipa-inline.c (ipa_inline): Update.
>> (pass_ipa_inline): Do not generate summaries.
>> * ipa.c (pass_data_ipa_free_fn_summary, pass_ipa_free_fn_summary):
>> Remove.
>> * passes.def: Replace pass_inline_parameters by pass_local_fn_summary
>> and add pass_ipa_fn_summary.
>> * tree-pass.h (make_pass_ipa_fn_summary, make_pass_local_fn_summary):
>> New.
>> (make_pass_inline_parameters): Remove.
>>
>> * lto.c (do_whole_program_analysis): Replace inline_free_summary
>> by ipa_free_fn_summary.
>>
>> * gcc.dg/ipa/ctor-empty-1.c: Update template.
>> * gcc.dg/ipa/inline-5.c: Likewise.
>> * gfortran.dg/pr48636.f90: Likewise.
>> Index: cgraphunit.c
>> ===
>> --- cgraphunit.c(revision 248365)
>> +++ cgraphunit.c(working copy)
>> @@ -339,7 +339,7 @@ symbol_table::process_new_functions (voi
>>  and splitting.  This is redundant for functions added late.
>>  Just throw away whatever it did.  */
>>   if (!summaried_computed)
>> -   inline_free_summary ();
>> +   ipa_free_fn_summary ();
>> }
>>   else if (ipa_fn_summaries != NULL)
>> compute_fn_summary (node, true);
>> Index: ipa-fnsummary.c
>> ===
>> --- ipa-fnsummary.c (revision 248366)
>> +++ ipa-fnsummary.c (working copy)
>> @@ -2504,46 +2504,6 @@ compute_fn_summary_for_current (void)
>>return 0;
>>  }
>>
>> -namespace {
>> -
>> -const pass_data pass_data_inline_parameters =
>> -{
>> -  GIMPLE_PASS, /* type */
>> -  "inline_param", /* name */
>> -  OPTGROUP_INLINE, /* optinfo_flags */
>> -  TV_INLINE_PARAMETERS, /* tv_id */
>> -  0, /* properties_required */
>> -  0, /* properties_provided */
>> -  0, /* properties_destroyed */
>> -  0, /* todo_flags_start */
>> -  0, /* todo_flags_finish */
>> -};
>> -
>> -class pass_inline_parameters : public gimple_opt_pass
>> -{
>> -public:
>> -  pass_inline_parameters (gcc::context *ctxt)
>> -: gimple_opt_pass (pass_data_inline_parameters, ctxt)
>> -  {}
>> -
>> -  /* opt_pass methods: */
>> -  opt_pass * clone () { return new pass_inline_parameters (m_ctxt); }
>> -  virtual unsigned int execute (function *)
>> -{
>> -  return compute_fn_summary_for_current ();
>> -}
>> -
>> -}; // class pass_inline_parameters
>> -
>> -} // anon namespace
>> -
>> -gimple_opt_pass *
>> -make_pass_inline_parameters (gcc::context *ctxt)
>> -{
>> -  return new pass_inline_parameters (ctxt);
>> -}
>> -
>> -
>>  /* Estimate benefit devirtualizing indirect edge IE, provided KNOWN_VALS,
>> KNOWN_CONTEXTS and KNOWN_AGGS.  */
>>
>> @@ -3207,8 +3167,8 @@ ipa_fn_summary_t::insert (struct cgraph_
>>
>>  /* Note function body size.  */
>>
>> -void
>> -inline_generate_summary (void)
>> +static void
>> +ipa_fn_summary_generate (void)
>>  {
>>struct cgraph_node *node;
>>
>> @@ -3226,7 +3186,7 @@ inline_generate_summary (void)
>>ipa_fn_summaries->enable_insertion_hook ();
>>
>>ipa_register_cgraph_hooks ();
>> -  inline_free_summary ();
>> +  ipa_free_fn_summary ();
>>
>>FOR_EACH_DEFINED_FUNCTION (node)
>>  if (!node->alias)
>> @@ -3358,8 +3318,8 @@ inline_read_section (struct lto_file_dec
>> and inliner, so when ipa-cp is active, we don't need to write them
>> twice.  */
>>
>> -void
>> -inline_read_summary (void)
>> +static voi

[testsuite]MIPS remove duplicate div-x test

[Paul Hua]

Hi,

There are duplicate testcase in gcc.target/mips dir.

div-5.c same as div-9.c.
div-6.c same as div-10.c.
div-7.c same as div-11.c.
div-8.c same as div-12.c.

Is this deliberate?

Otherwise, the attached patch fixing this.


Paul.

***ChangeLog***

2017-06-01Chenghua Xu 

Remove duplicate div-x testcase.
* gcc.target/mips/div-9.c: Delete.
* gcc.target/mips/div-10.c: Ditto.
* gcc.target/mips/div-11.c: Ditto.
* gcc.target/mips/div-12.c: Ditto.
diff --git a/gcc/testsuite/gcc.target/mips/div-10.c b/gcc/testsuite/gcc.target/mips/div-10.c
deleted file mode 100644
index fb8953d..000
--- a/gcc/testsuite/gcc.target/mips/div-10.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-options "-mgp64 (-mips16)" } */
-/* { dg-final { scan-assembler "\tdivu\t" } } */
-/* { dg-final { scan-assembler "\tmflo\t" } } */
-/* { dg-final { scan-assembler-not "\tmfhi\t" } } */
-
-typedef unsigned int SI __attribute__((mode(SI)));
-
-MIPS16 SI
-f (SI x, SI y)
-{
-  return x / y;
-}
diff --git a/gcc/testsuite/gcc.target/mips/div-11.c b/gcc/testsuite/gcc.target/mips/div-11.c
deleted file mode 100644
index ff12929..000
--- a/gcc/testsuite/gcc.target/mips/div-11.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-options "-mgp64 (-mips16)" } */
-/* { dg-final { scan-assembler "\tdiv\t" } } */
-/* { dg-final { scan-assembler-not "\tmflo\t" } } */
-/* { dg-final { scan-assembler "\tmfhi\t" } } */
-
-typedef int SI __attribute__((mode(SI)));
-
-MIPS16 SI
-f (SI x, SI y)
-{
-  return x % y;
-}
diff --git a/gcc/testsuite/gcc.target/mips/div-12.c b/gcc/testsuite/gcc.target/mips/div-12.c
deleted file mode 100644
index 57866ce..000
--- a/gcc/testsuite/gcc.target/mips/div-12.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-options "-mgp64 (-mips16)" } */
-/* { dg-final { scan-assembler "\tdivu\t" } } */
-/* { dg-final { scan-assembler-not "\tmflo\t" } } */
-/* { dg-final { scan-assembler "\tmfhi\t" } } */
-
-typedef unsigned int SI __attribute__((mode(SI)));
-
-MIPS16 SI
-f (SI x, SI y)
-{
-  return x % y;
-}
diff --git a/gcc/testsuite/gcc.target/mips/div-9.c b/gcc/testsuite/gcc.target/mips/div-9.c
deleted file mode 100644
index 294cc7f..000
--- a/gcc/testsuite/gcc.target/mips/div-9.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-options "-mgp64 (-mips16)" } */
-/* { dg-final { scan-assembler "\tdiv\t" } } */
-/* { dg-final { scan-assembler "\tmflo\t" } } */
-/* { dg-final { scan-assembler-not "\tmfhi\t" } } */
-
-typedef int SI __attribute__((mode(SI)));
-
-MIPS16 SI
-f (SI x, SI y)
-{
-  return x / y;
-}

Re: [testsuite]MIPS remove duplicate div-x test

[Paul Hua]

cc: Matthew.

ping.

On Thu, Jun 1, 2017 at 3:35 PM, Paul Hua  wrote:
> Hi,
>
> There are duplicate testcase in gcc.target/mips dir.
>
> div-5.c same as div-9.c.
> div-6.c same as div-10.c.
> div-7.c same as div-11.c.
> div-8.c same as div-12.c.
>
> Is this deliberate?
>
> Otherwise, the attached patch fixing this.
>
>
> Paul.
>
> ***ChangeLog***
>
> 2017-06-01Chenghua Xu 
>
> Remove duplicate div-x testcase.
> * gcc.target/mips/div-9.c: Delete.
> * gcc.target/mips/div-10.c: Ditto.
> * gcc.target/mips/div-11.c: Ditto.
> * gcc.target/mips/div-12.c: Ditto.

Re: [testsuite]MIPS remove duplicate div-x test

[Paul Hua]

Commited as r248868.

Thanks.
Paul.

On Mon, Jun 5, 2017 at 4:41 AM, Matthew Fortune
 wrote:
> Hi Paul,
>
> Paul Hua  writes:
>> cc: Matthew.
>>
>> ping.
>
> Sorry a little slow on the reply.
>
>> On Thu, Jun 1, 2017 at 3:35 PM, Paul Hua  wrote:
>> > Hi,
>> >
>> > There are duplicate testcase in gcc.target/mips dir.
>> >
>> > div-5.c same as div-9.c.
>> > div-6.c same as div-10.c.
>> > div-7.c same as div-11.c.
>> > div-8.c same as div-12.c.
>> >
>> > Is this deliberate?
>
> I see no evidence of this being deliberate and has been like this since
> the original commit.
>
>> > Otherwise, the attached patch fixing this.
>> >
>> >
>> > Paul.
>> >
>> > ***ChangeLog***
>> >
>> > 2017-06-01Chenghua Xu 
>> >
>> > Remove duplicate div-x testcase.
>
> These kind of comments don't tend to go in a changelog.
>
>> > * gcc.target/mips/div-9.c: Delete.
>
> You could say "Delete duplicate test" here if you want though.
>
>> > * gcc.target/mips/div-10.c: Ditto.
>> > * gcc.target/mips/div-11.c: Ditto.
>> > * gcc.target/mips/div-12.c: Ditto.
>
> Otherwise OK. I can't remember if you have write access let me know
> if you need it committing. Thanks for finding this.
>
> Matthew

Re: [PATCH, gcc/MIPS] Add options to disable/enable madd.fmt/msub.fmt instructions

[Paul Hua]

Hi,

> +On MIPS targets, set the @option{-mno-unfused-madd4} option by default.
> +On some platform, like Loongson 3A/3B 1000/2000/3000, madd.fmt/msub.fmt is
> +broken, which may which may generate wrong calculator result.

The Loongson 3A/3B 1000/2000/3000 madd.fmt/msub.fmt are fused madd instructions.
Can you try this patch:
https://gcc.gnu.org/ml/gcc-patches/2016-11/msg00255.html .

Is this patch testing on trunk? I build the trunk failure for a long time.

Re: [Patch ,gcc/MIPS] add an build-time/runtime option to disable madd.fmt

[Paul Hua]

On aarch64 target the result are 1.332268e-17.
On x86 with fma target the result are also 1.332268e-17.

so, I don't think the Loongson's madd.fmt/msub.fmt is incorrect.

We should do something for usage of fused madd, the all things has
been tested an fedora21 remix for loongson(1).

1, gcc：add loongson to the list of targets with a fused implementation.
2, glibc：__fma() function，we should use madd.fmt like aarch64.
see patch: 
http://www.loongnix.org/cgit/glibc-2.20/commit/?id=14023742e6ef571b61439d0d7bb7939e663fe624
3, kernel: the emulation  when a float exception taken.

(1),http://www.loongnix.org/index.php/Loongnix-20161130%E7%89%88%E6%9C%AC%E5%9C%A8Fedora21_remix%E7%B3%BB%E7%BB%9F%E4%B8%8A%E5%8F%91%E5%B8%83

Thanks,
Paul

On Fri, Dec 23, 2016 at 12:38 AM, Yunqiang Su  wrote:
>
>> 在 2016年12月23日，00:18，Richard Sandiford  写道：
>>
>> Yunqiang Su  writes:
 在 2016年12月22日，23:48，Yunqiang Su  写道：

>
> 在 2016年12月22日，23:31，Richard Sandiford
>  写道：
>
> Matthew Fortune  writes:
>> Sandra Loosemore  writes:
>>> On 12/21/2016 11:54 AM, Yunqiang Su wrote:
 By this patch, I add a build-time option ` 
 --with-unfused-madd4=yes/no',
 and runtime option -m(no-)unfused-madd4,
 to disable generate madd.fmt instructions.
>>>
>>> Your patch also needs a documentation change so that the new
>>> command-line option is listed in the GCC manual with other MIPS target
>>> options.
>>
>> Any opinions on option names to control this? Is it best to target
>> the specific
>> feature that is non-compliant on loongson or apply a general 
>> -mfix-loongson
>> type option?
>>
>> I'm not sure I have a strong opinion either way but there do seem to be
>> multiple possible variants.
>
> Wasn't sure from this thread whether Loongson simply had a fused
> implementation (without intermediate rounding) or whether the
> instructions gave numerically incorrect results for some inputs.

 I test to define ISA_HAS_FUSED_MADD4 true and
 define ISA_HAS_UNFUSED_MADD4 false, and try to build a test case.
 With ISA_HAS_FUSED_MADD4, the result is about 1e-17,
 and with ISA_HAS_UNFUSED_MADD4, the result is about 1e-17,
 both of the are incorrect (the expect value is 0).

 The test case is

 #include 

 double a = 0.6;
 double b = 0.4;
 double c = 0.6;
 double d = 0.4;

 int main(void)
 {
   double x = a * b - c * d;
   printf("%le\n", x);
   return 0;
 }


> It sounds from a later thread like it's generating incorrect results,
> is that right?  If so, then FWIW I agree an -mfix option would be more
> consistent.  E.g. one of the -mfix-vr4120 errata was an incorrect
> integer division result and one of the -mfix-sb1 errata was an incorrect
> single-precision float division result.  The latter case could have been
> handled by an option to disable DIV.S and DIV.PS, but the -mfix option
> gave more control.
>
> If instead the problem is that the instructions are fused then that's
> also what the original MIPS 4 parts did, so maybe an option to control
> fusedness would make sense.

 The result to thread it fused or unfused, is different, while neither of 
 them
 is correct.
>>>
>>> ohh, the result are same, and neither is correct.
>>> both of them are 1.332268e-17.
>>
>> That's the expected result for an implementation in which the subtraction
>> is fused with the first multiplication without intermediate rounding.
>> The second 0.4 * 0.6 isn't exactly representable and rounds down, to a
>> value slightly less than 0.24.  Then the fused operation subtracts this
>> value from the exact result of the first 0.4 * 0.6 (0.24), giving a
>> value slightly greater than 0.
>
> I see. But I think 1.332268e-17 is too big than expected.
> 1-e17 for double is totally unacceptable.
>
>>
>> I see Paul Hua's patch does add Loongson to the list of targets
>> with a fused implementation (should have checked earlier, sorry).
>> So I think after that patch we would do the right thing.  (In particular,
>> -ffp-contract=off would then disable the fusing.)
>
> will -ffp-contract=off disable some other optimization?
> If so, I don’t think that will be an ideal choice for distributions, like 
> Debian.
>
>>
>> Thanks,
>> Richard
>

[PATCH,gcc/MIPS] Make loongson3a use fused madd.d

[Paul Hua]

Hi,

Loongson3a has 4 operand fused madd instrcution. This patch set
loongson3a use fused madd.d.



ChangeLog :

*** gcc/ChangeLog ***

2016-11-03 Chenghua Xu 

config/mips/
* mips.h: Set loongson3a use fused madd.d.


Tested on loongson3a.


PS: I will soon submit some patches, how can i get a copyright assignment.
diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h
index 81862a9..5076a2b 100644
--- a/gcc/config/mips/mips.h
+++ b/gcc/config/mips/mips.h
@@ -1056,11 +1056,11 @@ struct mips_cpu_info {
 
 /* ISA has 4 operand fused madd instructions of the form
'd = [+-] (a * b [+-] c)'.  */
-#define ISA_HAS_FUSED_MADD4	TARGET_MIPS8000
+#define ISA_HAS_FUSED_MADD4	(TARGET_MIPS8000 || TARGET_LOONGSON_3A)
 
 /* ISA has 4 operand unfused madd instructions of the form
'd = [+-] (a * b [+-] c)'.  */
-#define ISA_HAS_UNFUSED_MADD4	(ISA_HAS_FP4 && !TARGET_MIPS8000)
+#define ISA_HAS_UNFUSED_MADD4	(ISA_HAS_FP4 && !TARGET_MIPS8000 && !TARGET_LOONGSON_3A)
 
 /* ISA has 3 operand r6 fused madd instructions of the form
'c = c [+-] (a * b)'.  */

Re: [PATCH,gcc/MIPS] Make loongson3a use fused madd.d

[Paul Hua]

Hi Matthew,

Thanks for your comments, update the patch.

*** gcc/ChangeLog ***

2016-11-03 Chenghua Xu 

* config/mips/mips.h (ISA_HAS_FUSED_MADD4): Enable for
TARGET_LOONGSON_3A.
(ISA_HAS_UNFUSED_MADD4): Exclude TARGET_LOONGSON_3A.

Thanks,
Paul

On Thu, Nov 3, 2016 at 6:31 PM, Matthew Fortune
 wrote:
> Paul Hua  writes:
>> Loongson3a has 4 operand fused madd instrcution. This patch set
>> loongson3a use fused madd.d.
>
> Hi Paul,
>
> Thanks for the fix. I was vaguely aware that this was wrong for
> loongson-3a but never confirmed it.
>
> I suspect this change is mechanical enough that it can bypass
> copyright assignment but I'd need a global maintainer to comment.
>
> I've sent you copyright assignment paperwork separately.
>
> Two comments on the patch:
>
>> ChangeLog :
>>
>> *** gcc/ChangeLog ***
>>
>> 2016-11-03 Chenghua Xu 
>>
>> config/mips/
>> * mips.h: Set loongson3a use fused madd.d.
>
> The changelog needs to reference what was changed rather than the
> effect of the change:
>
> * config/mips/mips.h (ISA_HAS_FUSED_MADD4): Enable for
> TARGET_LOONGSON_3A.
> (ISA_HAS_UNFUSED_MADD4): Exclude TARGET_LOONGSON_3A.
>
>
>>diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h
>>index 81862a9..5076a2b 100644
>>--- a/gcc/config/mips/mips.h
>>+++ b/gcc/config/mips/mips.h
>>@@ -1056,11 +1056,11 @@ struct mips_cpu_info {
>>
>> /* ISA has 4 operand fused madd instructions of the form
>>'d = [+-] (a * b [+-] c)'.  */
>>-#define ISA_HAS_FUSED_MADD4   TARGET_MIPS8000
>>+#define ISA_HAS_FUSED_MADD4   (TARGET_MIPS8000 || TARGET_LOONGSON_3A)
>>
>> /* ISA has 4 operand unfused madd instructions of the form
>>'d = [+-] (a * b [+-] c)'.  */
>>-#define ISA_HAS_UNFUSED_MADD4 (ISA_HAS_FP4 && !TARGET_MIPS8000)
>>+#define ISA_HAS_UNFUSED_MADD4 (ISA_HAS_FP4 && !TARGET_MIPS8000 && 
>>!TARGET_LOONGSON_3A)
>
> Please split this line and move && !TARGET_LOONGSON_3A to the next line
> under ISA_HAS_FP4.
>
>>
>> /* ISA has 3 operand r6 fused madd instructions of the form
>>'c = c [+-] (a * b)'.  */
>
> Thanks,
> Matthew
>
diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h
index 81862a9..2a7a3f2 100644
--- a/gcc/config/mips/mips.h
+++ b/gcc/config/mips/mips.h
@@ -1056,11 +1056,13 @@ struct mips_cpu_info {
 
 /* ISA has 4 operand fused madd instructions of the form
'd = [+-] (a * b [+-] c)'.  */
-#define ISA_HAS_FUSED_MADD4	TARGET_MIPS8000
+#define ISA_HAS_FUSED_MADD4	(TARGET_MIPS8000 || TARGET_LOONGSON_3A)
 
 /* ISA has 4 operand unfused madd instructions of the form
'd = [+-] (a * b [+-] c)'.  */
-#define ISA_HAS_UNFUSED_MADD4	(ISA_HAS_FP4 && !TARGET_MIPS8000)
+#define ISA_HAS_UNFUSED_MADD4	(ISA_HAS_FP4\
+ && !TARGET_MIPS8000			\
+ && !TARGET_LOONGSON_3A)
 
 /* ISA has 3 operand r6 fused madd instructions of the form
'c = c [+-] (a * b)'.  */

Re: [PATCH,gcc/MIPS] Make loongson3a use fused madd.d

[Paul Hua]

Hi:

I get the copyright assignment, it's ok for commit.
but recently, The gcc mainline trunk are fail to building on
mips64el-unknown-linux,
the bug https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78660 show the problem.

Thanks,
Paul

On Thu, Nov 17, 2016 at 7:14 PM, Matthew Fortune
 wrote:
> Hi Jeff,
>
> Am I OK to accept this change without copyright assignment from Paul?
>
> The change is small and there is no other way it could be implemented
> anyway if I had someone write it from scratch.
>
> Thanks,
> Matthew
>
>> -----Original Message-
>> From: Paul Hua [mailto:paul.hua...@gmail.com]
>> Sent: 17 November 2016 03:01
>> To: Matthew Fortune
>> Cc: gcc-patches@gcc.gnu.org; catherine_mo...@mentor.com
>> Subject: Re: [PATCH,gcc/MIPS] Make loongson3a use fused madd.d
>>
>> ping...
>>
>> On Thu, Nov 3, 2016 at 7:58 PM, Paul Hua  wrote:
>> > Hi Matthew,
>> >
>> > Thanks for your comments, update the patch.
>> >
>> > *** gcc/ChangeLog ***
>> >
>> > 2016-11-03 Chenghua Xu 
>> >
>> > * config/mips/mips.h (ISA_HAS_FUSED_MADD4): Enable for
>> > TARGET_LOONGSON_3A.
>> > (ISA_HAS_UNFUSED_MADD4): Exclude TARGET_LOONGSON_3A.
>> >
>> > Thanks,
>> > Paul
>> >
>> > On Thu, Nov 3, 2016 at 6:31 PM, Matthew Fortune
>> >  wrote:
>> >> Paul Hua  writes:
>> >>> Loongson3a has 4 operand fused madd instrcution. This patch set
>> >>> loongson3a use fused madd.d.
>> >>
>> >> Hi Paul,
>> >>
>> >> Thanks for the fix. I was vaguely aware that this was wrong for
>> >> loongson-3a but never confirmed it.
>> >>
>> >> I suspect this change is mechanical enough that it can bypass
>> >> copyright assignment but I'd need a global maintainer to comment.
>> >>
>> >> I've sent you copyright assignment paperwork separately.
>> >>
>> >> Two comments on the patch:
>> >>
>> >>> ChangeLog :
>> >>>
>> >>> *** gcc/ChangeLog ***
>> >>>
>> >>> 2016-11-03 Chenghua Xu 
>> >>>
>> >>> config/mips/
>> >>> * mips.h: Set loongson3a use fused madd.d.
>> >>
>> >> The changelog needs to reference what was changed rather than the
>> >> effect of the change:
>> >>
>> >> * config/mips/mips.h (ISA_HAS_FUSED_MADD4): Enable for
>> >> TARGET_LOONGSON_3A.
>> >> (ISA_HAS_UNFUSED_MADD4): Exclude TARGET_LOONGSON_3A.
>> >>
>> >>
>> >>>diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h index
>> >>>81862a9..5076a2b 100644
>> >>>--- a/gcc/config/mips/mips.h
>> >>>+++ b/gcc/config/mips/mips.h
>> >>>@@ -1056,11 +1056,11 @@ struct mips_cpu_info {
>> >>>
>> >>> /* ISA has 4 operand fused madd instructions of the form
>> >>>'d = [+-] (a * b [+-] c)'.  */
>> >>>-#define ISA_HAS_FUSED_MADD4   TARGET_MIPS8000
>> >>>+#define ISA_HAS_FUSED_MADD4   (TARGET_MIPS8000 ||
>> TARGET_LOONGSON_3A)
>> >>>
>> >>> /* ISA has 4 operand unfused madd instructions of the form
>> >>>'d = [+-] (a * b [+-] c)'.  */
>> >>>-#define ISA_HAS_UNFUSED_MADD4 (ISA_HAS_FP4 && !TARGET_MIPS8000)
>> >>>+#define ISA_HAS_UNFUSED_MADD4 (ISA_HAS_FP4 && !TARGET_MIPS8000 &&
>> >>>+!TARGET_LOONGSON_3A)
>> >>
>> >> Please split this line and move && !TARGET_LOONGSON_3A to the next
>> >> line under ISA_HAS_FP4.
>> >>
>> >>>
>> >>> /* ISA has 3 operand r6 fused madd instructions of the form
>> >>>'c = c [+-] (a * b)'.  */
>> >>
>> >> Thanks,
>> >> Matthew
>> >>

[PATCH][COMMITTED] Add myself to MAINTAINERS (Write After Approval).

[Paul Hua]

Hi all,

I committed the attached patch, adding myself to the Write After Approval.
committed as r243789.

thanks,
paul
Index: ChangeLog
===
--- ChangeLog	(revision 243788)
+++ ChangeLog	(revision 243789)
@@ -1,3 +1,7 @@
+2016-12-19  Chenghua Xu  
+
+	* MAINTAINERS (Write After Approval): Add myself.
+
 2016-12-01  Ma Jiang  
 
 	* config/acx.m4: Change "tail +16c" to "tail -c +17".
Index: MAINTAINERS
===
--- MAINTAINERS	(revision 243788)
+++ MAINTAINERS	(revision 243789)
@@ -626,6 +626,7 @@
 Chung-Ju Wu	
 Le-Chun Wu	
 Mingjie Xing	
+Chenghua Xu	
 Canqun Yang	
 Fei Yang	
 Jeffrey Yasskin	

[PATCH][Testsuite] Fix mips dsp testsuite mistakes

[Paul Hua]

Hi,

There are some mistakes in mips dsp testsuite.

This patch fixing it.

Ok to commit?


[mips] Fix mips dsp testsuite mistake.

gcc/testsuite/gcc.target/mips/
*mips32-dsp-run.c: Fix mistake.

Index: gcc/testsuite/ChangeLog
===
--- gcc/testsuite/ChangeLog (revision 236553)
+++ gcc/testsuite/ChangeLog (working copy)
@@ -1,3 +1,7 @@
+2016-05-21  Chenghua Xu  
+
+   * gcc.target/mips/mips32-dsp-run.c: Fix mistake.
+
 2016-05-20  Martin Sebor  

PR c/71115
Index: gcc/testsuite/gcc.target/mips/mips32-dsp-run.c
===
--- gcc/testsuite/gcc.target/mips/mips32-dsp-run.c  (revision 236553)
+++ gcc/testsuite/gcc.target/mips/mips32-dsp-run.c  (working copy)
@@ -394,7 +394,7 @@ NOMIPS16 void test_MIPS_DSP ()

   v2q15_a = (v2q15) {0x1234, 0x5678};
   i32_b = 1;
-  v2q15_s = (v2q15) {0x2468, 0x7fff};
+  v2q15_s = (v2q15) {0x2468, 0xacf0};
   v2q15_r = __builtin_mips_shll_s_ph (v2q15_a, i32_b);
   r = (int) v2q15_r;
   s = (int) v2q15_s;
@@ -409,7 +409,7 @@ NOMIPS16 void test_MIPS_DSP ()

   q31_a = 0x7000;
   i32_b = 1;
-  q31_s = 0x7fff;
+  q31_s = 0xe000;
   q31_r = __builtin_mips_shll_s_w (q31_a, i32_b);
   if (q31_r != q31_s)
 abort ();
@@ -961,9 +961,9 @@ NOMIPS16 void test_MIPS_DSP ()
 abort ();
 #endif

-  i32_a = 0x1357a468;
+  i32_a = 0x13572468;
   __builtin_mips_wrdsp (i32_a, 63);
-  i32_s = 0x03572428;
+  i32_s = 0x13572468;
   i32_r = __builtin_mips_rddsp (63);
   if (i32_r != i32_s)
 abort ();



Regards,
Chenghua

Re: [PATCH,gcc/MIPS] Make loongson3a use fused madd.d

[Paul Hua]

ping...

On Thu, Nov 3, 2016 at 7:58 PM, Paul Hua  wrote:
> Hi Matthew,
>
> Thanks for your comments, update the patch.
>
> *** gcc/ChangeLog ***
>
> 2016-11-03 Chenghua Xu 
>
> * config/mips/mips.h (ISA_HAS_FUSED_MADD4): Enable for
> TARGET_LOONGSON_3A.
> (ISA_HAS_UNFUSED_MADD4): Exclude TARGET_LOONGSON_3A.
>
> Thanks,
> Paul
>
> On Thu, Nov 3, 2016 at 6:31 PM, Matthew Fortune
>  wrote:
>> Paul Hua  writes:
>>> Loongson3a has 4 operand fused madd instrcution. This patch set
>>> loongson3a use fused madd.d.
>>
>> Hi Paul,
>>
>> Thanks for the fix. I was vaguely aware that this was wrong for
>> loongson-3a but never confirmed it.
>>
>> I suspect this change is mechanical enough that it can bypass
>> copyright assignment but I'd need a global maintainer to comment.
>>
>> I've sent you copyright assignment paperwork separately.
>>
>> Two comments on the patch:
>>
>>> ChangeLog :
>>>
>>> *** gcc/ChangeLog ***
>>>
>>> 2016-11-03 Chenghua Xu 
>>>
>>> config/mips/
>>> * mips.h: Set loongson3a use fused madd.d.
>>
>> The changelog needs to reference what was changed rather than the
>> effect of the change:
>>
>> * config/mips/mips.h (ISA_HAS_FUSED_MADD4): Enable for
>> TARGET_LOONGSON_3A.
>> (ISA_HAS_UNFUSED_MADD4): Exclude TARGET_LOONGSON_3A.
>>
>>
>>>diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h
>>>index 81862a9..5076a2b 100644
>>>--- a/gcc/config/mips/mips.h
>>>+++ b/gcc/config/mips/mips.h
>>>@@ -1056,11 +1056,11 @@ struct mips_cpu_info {
>>>
>>> /* ISA has 4 operand fused madd instructions of the form
>>>'d = [+-] (a * b [+-] c)'.  */
>>>-#define ISA_HAS_FUSED_MADD4   TARGET_MIPS8000
>>>+#define ISA_HAS_FUSED_MADD4   (TARGET_MIPS8000 || TARGET_LOONGSON_3A)
>>>
>>> /* ISA has 4 operand unfused madd instructions of the form
>>>'d = [+-] (a * b [+-] c)'.  */
>>>-#define ISA_HAS_UNFUSED_MADD4 (ISA_HAS_FP4 && !TARGET_MIPS8000)
>>>+#define ISA_HAS_UNFUSED_MADD4 (ISA_HAS_FP4 && !TARGET_MIPS8000 && 
>>>!TARGET_LOONGSON_3A)
>>
>> Please split this line and move && !TARGET_LOONGSON_3A to the next line
>> under ISA_HAS_FP4.
>>
>>>
>>> /* ISA has 3 operand r6 fused madd instructions of the form
>>>'c = c [+-] (a * b)'.  */
>>
>> Thanks,
>> Matthew
>>

Re: [PATCH v8 00/12] Add LoongArch support.

[Paul Hua via Gcc-patches]

>
> And based on the history of RISC-V port
> (https://gcc.gnu.org/pipermail/gcc/2017-January/222595.html) the process
> for a new port seems:
>
> 1. Get a permission from the Steering Committee.
> 2. Add one or two port maintainers into MAINTAINERS file.
> 3. Now the technical reviewing of the patch series just begin.
>

Hi Ruoyao,
Thanks for your advice.  But I don't know how to contact the GCC
Steering Committee.

Hi David,
Any suggestions?

Re: [PATCH v8 00/12] Add LoongArch support.

[Paul Hua via Gcc-patches]

> > And based on the history of RISC-V port
> > (https://gcc.gnu.org/pipermail/gcc/2017-January/222595.html) the process
> > for a new port seems:
> >
> > 1. Get a permission from the Steering Committee.
> > 2. Add one or two port maintainers into MAINTAINERS file.
> > 3. Now the technical reviewing of the patch series just begin.
> >
>
> Hi Ruoyao,
> Thanks for your advice.  But I don't know how to contact the GCC
> Steering Committee.
>
> Hi David,
> Any suggestions?
Sorry, CCed David Edelsohn.

Ping for [PATCH v6 00/12] Add LoongArch support.

[Paul Hua via Gcc-patches]

ping ?

On Fri, Jan 28, 2022 at 9:50 PM chenglulu  wrote:
>
> The LoongArch architecture (LoongArch) is an Instruction Set
> Architecture (ISA) that has a Reduced Instruction Set Computer (RISC)
> style.
> The documents are on
> https://loongson.github.io/LoongArch-Documentation/README-EN.html
>
> The ELF ABI Documents are on:
> https://loongson.github.io/LoongArch-Documentation/LoongArch-ELF-ABI-EN.html
>
> The binutils has been merged into trunk:
> https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=560b3fe208255ae909b4b1c88ba9c28b09043307
>
> Note: We split -mabi= into -mabi=lp64d/f/s, the new options not support by 
> upstream binutils yet,
> this GCC port requires the following patch applied to binutils to build.
> https://github.com/loongson/binutils-gdb/commit/aacb0bf860f02aa5a7dcb76dd0e392bf871c7586
> (will be submitted to upstream after gcc side comfirmed)
>
> We have compiled more than 300 CLFS packages with this compiler.
> The CLFS are currently used on Cfarm machines gcc400 and gcc401.
>
>
> changelog:
>
> v1 -> v2
> 1. Split patch set.
> 2. Change some code style.
> 3. Add -mabi=lp64d/f/s options.
> 4. Change GLIBC_DYNAMIC_LINKER_LP64 name.
>
> v2 -> v3
> 1. Change some code style.
> 2. Bug fix.
>
> v3 -> v4
> 1. Change some code style.
> 2. Bug fix.
> 3. Delete some builtin macros.
>
> v4 -> v5
> 1. delete wrong insn zero_extendsidi2_internal.
> 2. Adjust some build options.
> 3. Change some .c files to .cc.
>
> v5 -> v6
> 1. Fix compilation issues. The generated files *.opt and *.h
>are generated to $(objdir).
>
>
> chenglulu (12):
>   LoongArch Port: Regenerate configure
>   LoongArch Port: gcc build
>   LoongArch Port: Regenerate gcc/configure.
>   LoongArch Port: Machine Decsription files.
>   LoongArch Port: Machine description C files and .h files.
>   LoongArch Port: Builtin functions.
>   LoongArch Port: Builtin macros.
>   LoongArch Port: libgcc
>   LoongArch Port: Regenerate libgcc/configure.
>   LoongArch Port: libgomp
>   LoongArch Port: gcc/testsuite
>   LoongArch Port: Add doc.
>
>  config/picflag.m4 |3 +
>  configure |   10 +-
>  configure.ac  |   10 +-
>  contrib/config-list.mk|5 +-
>  contrib/gcc_update|2 +
>  .../config/loongarch/loongarch-common.cc  |   73 +
>  gcc/config.gcc|  410 +-
>  gcc/config/host-linux.cc  |2 +
>  gcc/config/loongarch/constraints.md   |  212 +
>  gcc/config/loongarch/generic.md   |  132 +
>  gcc/config/loongarch/genopts/genstr.sh|   91 +
>  .../loongarch/genopts/loongarch-strings   |   58 +
>  gcc/config/loongarch/genopts/loongarch.opt.in |  189 +
>  gcc/config/loongarch/gnu-user.h   |   84 +
>  gcc/config/loongarch/la464.md |  132 +
>  gcc/config/loongarch/larchintrin.h|  413 ++
>  gcc/config/loongarch/linux.h  |   50 +
>  gcc/config/loongarch/loongarch-builtins.cc|  511 ++
>  gcc/config/loongarch/loongarch-c.cc   |  109 +
>  gcc/config/loongarch/loongarch-cpu.cc |  206 +
>  gcc/config/loongarch/loongarch-cpu.h  |   30 +
>  gcc/config/loongarch/loongarch-def.c  |  164 +
>  gcc/config/loongarch/loongarch-def.h  |  151 +
>  gcc/config/loongarch/loongarch-driver.cc  |  187 +
>  gcc/config/loongarch/loongarch-driver.h   |   69 +
>  gcc/config/loongarch/loongarch-ftypes.def |  106 +
>  gcc/config/loongarch/loongarch-modes.def  |   29 +
>  gcc/config/loongarch/loongarch-opts.cc|  580 ++
>  gcc/config/loongarch/loongarch-opts.h |   86 +
>  gcc/config/loongarch/loongarch-protos.h   |  241 +
>  gcc/config/loongarch/loongarch-str.h  |   57 +
>  gcc/config/loongarch/loongarch-tune.h |   72 +
>  gcc/config/loongarch/loongarch.cc | 6330 +
>  gcc/config/loongarch/loongarch.h  | 1271 
>  gcc/config/loongarch/loongarch.md | 3702 ++
>  gcc/config/loongarch/loongarch.opt|  189 +
>  gcc/config/loongarch/predicates.md|  553 ++
>  gcc/config/loongarch/sync.md  |  574 ++
>  gcc/config/loongarch/t-linux  |   53 +
>  gcc/config/loongarch/t-loongarch  |   68 +
>  gcc/configure |   66 +-
>  gcc/configure.ac  |   33 +-
>  gcc/doc/install.texi  |   47 +-
>  gcc/doc/invoke.texi   |  201 +
>  gcc/doc/md.texi   |   55 +
>  gcc/testsuite/g++.dg/cpp0x/constexpr-rom.C|2 +-
>  gcc/testsuite/g++.old-deja/g++.abi/ptrmem.C   |2 +-
>  gcc/testsuite/g++.old-deja/g++.pt/ptrmem6.C   |2 +-
>  gcc/testsuite/gcc.dg/20020312-2.c |2 +
>  gcc/testsuite/gcc.dg/loop-8.c |2 +-
>

Ping ?: [PATCH v7 00/12] Add LoongArch support.

[Paul Hua via Gcc-patches]

ping?

On Sat, Feb 12, 2022 at 11:12 AM  wrote:
>
> From: Chenghua Xu 
>
> Hi, all:
>
> This is the v7 version of LoongArch Port. Please review.
>
> We know it is stage4, I think it is ok for a new prot.
> The kernel side upstream waiting for a approval by gcc side,
> if it is blocked by stage4, a approval for GCC13 will be appreciation.
>
>
> The LoongArch architecture (LoongArch) is an Instruction Set
> Architecture (ISA) that has a Reduced Instruction Set Computer (RISC)
> style.
> The documents are on
> https://loongson.github.io/LoongArch-Documentation/README-EN.html
>
> The ELF ABI Documents are on:
> https://loongson.github.io/LoongArch-Documentation/LoongArch-ELF-ABI-EN.html
>
> The binutils has been merged into trunk:
> https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=560b3fe208255ae909b4b1c88ba9c28b09043307
>
> Note: We split -mabi= into -mabi=lp64d/f/s, the new options not support by 
> upstream binutils yet,
> this GCC port requires the following patch applied to binutils to build.
> https://github.com/loongson/binutils-gdb/commit/aacb0bf860f02aa5a7dcb76dd0e392bf871c7586
> (will be submitted to upstream after gcc side comfirmed)
>
> We have compiled more than 300 CLFS packages with this compiler.
> The CLFS are currently used on Cfarm machines gcc400 and gcc401.
>
> Changelog:
>
> v1 -> v2
> 1. Split patch set.
> 2. Change some code style.
> 3. Add -mabi=lp64d/f/s options.
> 4. Change GLIBC_DYNAMIC_LINKER_LP64 name.
>
> v2 -> v3
> 1. Change some code style.
> 2. Bug fix.
>
> v3 -> v4
> 1. Change some code style.
> 2. Bug fix.
> 3. Delete some builtin macros.
>
> v4 -> v5
> 1. delete wrong insn zero_extendsidi2_internal.
> 2. Adjust some build options.
> 3. Change some .c files to .cc.
>
> v5 -> v6
> 1. Fix compilation issues. The generated files *.opt and *.h
>are generated to $(objdir).
>
> v6 -> v7
> 1. Bug fix.
> 2. Change some code style.
>
> chenglulu (12):
>   LoongArch Port: Regenerate configure
>   LoongArch Port: gcc build
>   LoongArch Port: Regenerate gcc/configure.
>   LoongArch Port: Machine description files.
>   LoongArch Port: Machine description C files and .h files.
>   LoongArch Port: Builtin functions.
>   LoongArch Port: Builtin macros.
>   LoongArch Port: libgcc
>   LoongArch Port: Regenerate libgcc/configure.
>   LoongArch Port: libgomp
>   LoongArch Port: gcc/testsuite
>   LoongArch Port: Add doc.
>
>  config/picflag.m4 |3 +
>  configure |   10 +-
>  configure.ac  |   10 +-
>  contrib/config-list.mk|5 +-
>  contrib/gcc_update|2 +
>  .../config/loongarch/loongarch-common.cc  |   73 +
>  gcc/config.gcc|  410 +-
>  gcc/config/host-linux.cc  |2 +
>  gcc/config/loongarch/constraints.md   |  212 +
>  gcc/config/loongarch/generic.md   |  132 +
>  gcc/config/loongarch/genopts/genstr.sh|   91 +
>  .../loongarch/genopts/loongarch-strings   |   58 +
>  gcc/config/loongarch/genopts/loongarch.opt.in |  189 +
>  gcc/config/loongarch/gnu-user.h   |   84 +
>  gcc/config/loongarch/la464.md |  132 +
>  gcc/config/loongarch/larchintrin.h|  413 ++
>  gcc/config/loongarch/linux.h  |   50 +
>  gcc/config/loongarch/loongarch-builtins.cc|  511 ++
>  gcc/config/loongarch/loongarch-c.cc   |  109 +
>  gcc/config/loongarch/loongarch-cpu.cc |  206 +
>  gcc/config/loongarch/loongarch-cpu.h  |   30 +
>  gcc/config/loongarch/loongarch-def.c  |  164 +
>  gcc/config/loongarch/loongarch-def.h  |  151 +
>  gcc/config/loongarch/loongarch-driver.cc  |  187 +
>  gcc/config/loongarch/loongarch-driver.h   |   69 +
>  gcc/config/loongarch/loongarch-ftypes.def |  106 +
>  gcc/config/loongarch/loongarch-modes.def  |   29 +
>  gcc/config/loongarch/loongarch-opts.cc|  580 ++
>  gcc/config/loongarch/loongarch-opts.h |   86 +
>  gcc/config/loongarch/loongarch-protos.h   |  241 +
>  gcc/config/loongarch/loongarch-str.h  |   57 +
>  gcc/config/loongarch/loongarch-tune.h |   72 +
>  gcc/config/loongarch/loongarch.cc | 6318 +
>  gcc/config/loongarch/loongarch.h  | 1271 
>  gcc/config/loongarch/loongarch.md | 3702 ++
>  gcc/config/loongarch/loongarch.opt|  189 +
>  gcc/config/loongarch/predicates.md|  531 ++
>  gcc/config/loongarch/sync.md  |  574 ++
>  gcc/config/loongarch/t-linux  |   53 +
>  gcc/config/loongarch/t-loongarch  |   68 +
>  gcc/configure |   66 +-
>  gcc/configure.ac  |   33 +-
>  gcc/doc/install.texi  |   47 +-
>  gcc/doc/invoke.texi   |  201 +
>  gcc/doc/md.tex

Re: [PATCH v6 11/12] LoongArch Port: gcc/testsuite

[Paul Hua via Gcc-patches]

Hi Mike,

Thanks for your review.

On Wed, Feb 16, 2022 at 12:30 PM Mike Stump via Gcc-patches
 wrote:
>
> On Jan 28, 2022, at 5:49 AM, chenglulu  wrote:
> >
> > gcc/testsuite/
> >
> >* g++.dg/cpp0x/constexpr-rom.C: Add build options for LoongArch.
> >* g++.old-deja/g++.abi/ptrmem.C: Add LoongArch support.
> >* g++.old-deja/g++.pt/ptrmem6.C: xfail for LoongArch.
> >* gcc.dg/20020312-2.c: Add LoongArch support.
> >* gcc.dg/loop-8.c: Skip on LoongArch.
> >* gcc.dg/torture/stackalign/builtin-apply-2.c: Likewise.
> >* gcc.dg/tree-ssa/ssa-fre-3.c: Likewise.
> >* go.test/go-test.exp: Define the LoongArch target.
> >* lib/target-supports.exp: Like wise.
> >* gcc.target/loongarch/loongarch.exp: New file.
> >* gcc.target/loongarch/tst-asm-const.c: Like wise.
>
> Ok.

Re: [PATCH][MIPS] PR target/77510 Reduce size of MIPS core automaton

[Paul Hua via Gcc-patches]

> > This patch reduce reservation of model do not more than 10 cycles. The
> > memory of genautomata down to 1GB.
>
> How bad is the memory consumption before this change?
>

almost 2.4GB.
see bugzilla comment #4.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=77510#c4

Re: PING: [PATCH] mips: check MSA support for vector modes [PR100760, PR100761, PR100762]

[Paul Hua via Gcc-patches]

Looks good to me,  but I have no right to approve.



On Wed, Jun 30, 2021 at 9:17 PM Xi Ruoyao  wrote:
>
> Ping patch:
> https://gcc.gnu.org/pipermail/gcc-patches/2021-June/573213.html
>
> Status update: bootstrapped with BOOT_CFLAGS="-O3 -mmsa -mloongson-mmi"
> (it failed without the patch), and regtested on mips64el-linux-gnu with
> no new regression.
>
> On Sat, 2021-06-19 at 15:34 +0800, Xi Ruoyao wrote:
> > Check if the vector mode is really supported by MSA in certain cases,
> > instead of testing ISA_HAS_MSA.  Simply testing ISA_HAS_MSA can cause
> > ICE when MSA is enabled besides other MIPS SIMD extensions (notably,
> > Loongson MMI).
> >
> > Bootstrapped and tested on mips64el-linux-gnu.  OK to commit?
> >
> > gcc/
> >
> > * config/mips/mips.c (mips_const_insns): Use
> > MSA_SUPPORTED_MODE_P
> > instead of ISA_HAS_MSA.
> > (mips_expand_vec_unpack): Likewise.
> > (mips_expand_vector_init): Likewise.
> >
> > gcc/testsuite/
> >
> > * testsuite/gcc.target/mips/pr100760.c: New test.
> > * testsuite/gcc.target/mips/pr100761.c: New test.
> > * testsuite/gcc.target/mips/pr100762.c: New test.
> --
> Xi Ruoyao 
>

[PATCH] MIPS: Fix __builtin_longjmp (PR 64242)

[Paul Hua via Gcc-patches]

>From 589dbe8a1c2397bfafefa4e84abe5ec6e6798928 Mon Sep 17 00:00:00 2001
From: Andrew Pinski 
Date: Wed, 12 Feb 2020 11:42:57 +
Subject: [PATCH] MIPS: Fix __builtin_longjmp (PR 64242)

The problem here is mips has its own builtin_longjmp
pattern and it was not fixed when expand_builtin_longjmp
was fixed.  We need to read the new fp and gp before
restoring the stack as the buffer might be a local
variable.

Change-Id: I3416568e260e6bde3ad5cc470fb4f2ecfa207f05
Signed-off-by: Andrew Pinski 

This patch from Andrew, I bootstrapped and tested on mips64el-linux-gnu.

OK for master ?

gcc/ChangeLog:

PR middle-end/64242
* config/mips/mips.md (builtin_longjmp): Restore the frame pointer
   and stack pointer and gp.
From 589dbe8a1c2397bfafefa4e84abe5ec6e6798928 Mon Sep 17 00:00:00 2001
From: Andrew Pinski 
Date: Wed, 12 Feb 2020 11:42:57 +
Subject: [PATCH] MIPS: Fix __builtin_longjmp (PR 64242)

The problem here is mips has its own builtin_longjmp
pattern and it was not fixed when expand_builtin_longjmp
was fixed.  We need to read the new fp and gp before
restoring the stack as the buffer might be a local
variable.

Change-Id: I3416568e260e6bde3ad5cc470fb4f2ecfa207f05
Signed-off-by: Andrew Pinski 
---
 gcc/config/mips/mips.md | 12 +++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md
index dd9fdd1418d..8bafbe82bd3 100644
--- a/gcc/config/mips/mips.md
+++ b/gcc/config/mips/mips.md
@@ -6601,9 +6601,19 @@
 
   /* This bit is similar to expand_builtin_longjmp except that it
  restores $gp as well.  */
-  mips_emit_move (hard_frame_pointer_rtx, fp);
   mips_emit_move (pv, lab);
+  /* Restore the frame pointer and stack pointer and gp.  We must use a
+ temporary since the setjmp buffer may be a local.  */
+  fp = copy_to_reg (fp);
+  gpv = copy_to_reg (gpv);
   emit_stack_restore (SAVE_NONLOCAL, stack);
+
+  /* Ensure the frame pointer move is not optimized.  */
+  emit_insn (gen_blockage ());
+  emit_clobber (hard_frame_pointer_rtx);
+  emit_clobber (frame_pointer_rtx);
+  emit_clobber (gp);
+  mips_emit_move (hard_frame_pointer_rtx, fp);
   mips_emit_move (gp, gpv);
   emit_use (hard_frame_pointer_rtx);
   emit_use (stack_pointer_rtx);
-- 
2.17.1

Re: [PATCH] MIPS: Fix __builtin_longjmp (PR 64242)

[Paul Hua via Gcc-patches]

ping?

On Sun, Jul 12, 2020 at 2:27 PM Paul Hua  wrote:
>
> From 589dbe8a1c2397bfafefa4e84abe5ec6e6798928 Mon Sep 17 00:00:00 2001
> From: Andrew Pinski 
> Date: Wed, 12 Feb 2020 11:42:57 +
> Subject: [PATCH] MIPS: Fix __builtin_longjmp (PR 64242)
>
> The problem here is mips has its own builtin_longjmp
> pattern and it was not fixed when expand_builtin_longjmp
> was fixed.  We need to read the new fp and gp before
> restoring the stack as the buffer might be a local
> variable.
>
> Change-Id: I3416568e260e6bde3ad5cc470fb4f2ecfa207f05
> Signed-off-by: Andrew Pinski 
>
> This patch from Andrew, I bootstrapped and tested on mips64el-linux-gnu.
>
> OK for master ?
>
> gcc/ChangeLog:
>
> PR middle-end/64242
> * config/mips/mips.md (builtin_longjmp): Restore the frame pointer
>and stack pointer and gp.

Re: [PATCH v3 06/12] LoongArch Port: Builtin macros.

[Paul Hua via Gcc-patches]

Hi Joseph,

Thanks for your suggestion, Those macros can be removed, we will send
the v4 version soon.

Are there any problems in this series of patches?

In other words, What conditions are required for LoongArch back-end merged?

By the way, We are preparing the LoongArch machine to send to Cfarm for testing.

On Tue, Dec 14, 2021 at 8:13 AM Joseph Myers  wrote:
>
> On Fri, 10 Dec 2021, Chenghua Xu wrote:
>
> > +  /* Macros dependent on the C dialect.  */
> > +  if (preprocessing_asm_p ())
> > +{
> > +  builtin_define_std ("LANGUAGE_ASSEMBLY");
> > +  builtin_define ("_LANGUAGE_ASSEMBLY");
> > +}
> > +  else if (c_dialect_cxx ())
> > +{
> > +  builtin_define ("_LANGUAGE_C_PLUS_PLUS");
> > +  builtin_define ("__LANGUAGE_C_PLUS_PLUS");
> > +  builtin_define ("__LANGUAGE_C_PLUS_PLUS__");
> > +}
> > +  else
> > +{
> > +  builtin_define_std ("LANGUAGE_C");
> > +  builtin_define ("_LANGUAGE_C");
> > +}
> > +  if (c_dialect_objc ())
> > +{
> > +  builtin_define ("_LANGUAGE_OBJECTIVE_C");
> > +  builtin_define ("__LANGUAGE_OBJECTIVE_C");
> > +  /* Bizarre, but retained for backwards compatibility.  */
> > +  builtin_define_std ("LANGUAGE_C");
> > +  builtin_define ("_LANGUAGE_C");
> > +}
> > +}
>
> I think all of this should be removed.  It's a new architecture, there
> should be no need for any such macros for things that are not
> architecture-specific.  In general, be careful to remove anything in the
> port that is actually about the peculiarities of what was once done for
> compatibility with existing software for an old architecture (MIPS?) that
> you modelled the port on and that is not considered best practice for a
> new architecture where you can make a fresh start.
>
> --
> Joseph S. Myers
> jos...@codesourcery.com

Re: [PATCH v3 06/12] LoongArch Port: Builtin macros.

[Paul Hua via Gcc-patches]

Hi Ruoyao,
Thank you for your attention.

> GCC 12 development cycle is at stage 3 (general bugfixing) now.  So a
> new port have to wait until stage 1 of GCC 13 begins (in mid 2022, I
> guess).
I know it is stage3, but we are a new target, it's ok for GCC 12.

Re: [PATCH v4 00/12] Add LoongArch support.

[Paul Hua via Gcc-patches]

Hi all,

Ping?

By the way, the LoongArch machine is already connected to the Cfarm
and will be announced soon.
You can login through ssh.
ssh -l your-cfarm-user-name -p 25469 114.242.206.180


On Fri, Dec 24, 2021 at 5:28 PM chenglulu  wrote:
>
> The LoongArch architecture (LoongArch) is an Instruction Set
> Architecture (ISA) that has a Reduced Instruction Set Computer (RISC)
> style.
> The documents are on
> https://loongson.github.io/LoongArch-Documentation/README-EN.html
>
> The ELF ABI Documents are on:
> https://loongson.github.io/LoongArch-Documentation/LoongArch-ELF-ABI-EN.html
>
> The binutils has been merged into trunk:
> https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=560b3fe208255ae909b4b1c88ba9c28b09043307
>
> Note: We split -mabi= into -mabi=lp64d/f/s, the new options not support by 
> upstream binutils yet,
> this GCC port requires the following patch applied to binutils to build.
> https://github.com/loongson/binutils-gdb/commit/aacb0bf860f02aa5a7dcb76dd0e392bf871c7586
> (will be submitted to upstream after gcc side comfirmed)
>
>
> changelog:
>
> v1 -> v2
> 1. Split patch set.
> 2. Change some code style.
> 3. Add -mabi=lp64d/f/s options.
> 4. Change GLIBC_DYNAMIC_LINKER_LP64 name.
>
> v2 -> v3
> 1. Change some code style.
> 2. Bug fix.
>
> v3 -> v4
> 1. Change some code style.
> 2. Bug fix.
> 3. Delete some builtin macros.
>
> Add LoongArch support.
>
> chenglulu (12):
>   LoongArch Port: Regenerate configure
>   LoongArch Port: gcc build
>   LoongArch Port: Regenerate gcc/configure.
>   LoongArch Port: Machine Decsription files.
>   LoongArch Port: Machine description C files and .h files.
>   LoongArch Port: Builtin functions.
>   LoongArch Port: Builtin macros.
>   LoongArch Port: libgcc
>   LoongArch Port: Regenerate libgcc/configure.
>   LoongArch Port: libgomp
>   LoongArch Port: gcc/testsuite
>   LoongArch Port: Add doc.
>
>  config/picflag.m4 |3 +
>  configure |   10 +-
>  configure.ac  |   10 +-
>  contrib/config-list.mk|5 +-
>  .../config/loongarch/loongarch-common.c   |   63 +
>  gcc/config.gcc|  400 +-
>  gcc/config/host-linux.c   |2 +
>  gcc/config/loongarch/constraints.md   |  212 +
>  gcc/config/loongarch/generic.md   |  132 +
>  gcc/config/loongarch/genopts/genstr.sh|   91 +
>  .../loongarch/genopts/loongarch-strings   |   58 +
>  gcc/config/loongarch/genopts/loongarch.opt.in |  189 +
>  gcc/config/loongarch/gnu-user.h   |   78 +
>  gcc/config/loongarch/la464.md |  132 +
>  gcc/config/loongarch/larchintrin.h|  413 ++
>  gcc/config/loongarch/linux.h  |   50 +
>  gcc/config/loongarch/loongarch-builtins.c |  511 ++
>  gcc/config/loongarch/loongarch-c.c|  111 +
>  gcc/config/loongarch/loongarch-cpu.c  |  206 +
>  gcc/config/loongarch/loongarch-cpu.h  |   30 +
>  gcc/config/loongarch/loongarch-def.c  |  164 +
>  gcc/config/loongarch/loongarch-def.h  |  151 +
>  gcc/config/loongarch/loongarch-driver.c   |  187 +
>  gcc/config/loongarch/loongarch-driver.h   |   69 +
>  gcc/config/loongarch/loongarch-ftypes.def |  106 +
>  gcc/config/loongarch/loongarch-modes.def  |   29 +
>  gcc/config/loongarch/loongarch-opts.c |  582 ++
>  gcc/config/loongarch/loongarch-opts.h |   86 +
>  gcc/config/loongarch/loongarch-protos.h   |  242 +
>  gcc/config/loongarch/loongarch-str.h  |   57 +
>  gcc/config/loongarch/loongarch-tune.h |   72 +
>  gcc/config/loongarch/loongarch.c  | 6461 +
>  gcc/config/loongarch/loongarch.h  | 1291 
>  gcc/config/loongarch/loongarch.md | 3829 ++
>  gcc/config/loongarch/loongarch.opt|  189 +
>  gcc/config/loongarch/predicates.md|  553 ++
>  gcc/config/loongarch/sync.md  |  574 ++
>  gcc/config/loongarch/t-linux  |   53 +
>  gcc/config/loongarch/t-loongarch  |   59 +
>  gcc/configure |   85 +-
>  gcc/configure.ac  |   33 +-
>  gcc/doc/install.texi  |   47 +-
>  gcc/doc/invoke.texi   |  201 +
>  gcc/doc/md.texi   |   55 +
>  gcc/testsuite/g++.dg/cpp0x/constexpr-rom.C|2 +-
>  gcc/testsuite/g++.old-deja/g++.abi/ptrmem.C   |2 +-
>  gcc/testsuite/g++.old-deja/g++.pt/ptrmem6.C   |2 +-
>  gcc/testsuite/gcc.dg/20020312-2.c |2 +
>  gcc/testsuite/gcc.dg/loop-8.c |2 +-
>  .../torture/stackalign/builtin-apply-2.c  |2 +-
>  gcc/testsuite/gcc.dg/tree-ssa/ssa-fre-3.c |2 +-
>  .../gcc.target/loongarch/loongarch.exp|   40 +
>  .../gcc.target/loongarch/tst-asm-const.c