Re: [Patch, AArch64] Optimized implementation of vget_low_* in arm_neon.h.
On 20 August 2013 12:21, Tejas Belagod wrote: > Hi, > > This patch replaces all inline asm implementations of vget_low_* in > arm_neon.h with optimized implementations using other neon intrinsics. > > Tested with aarch64-none-elf. > > OK? This is OK. /Marcus
Re: [Patch,AArch64] Support SISD Shifts (SHL/USHR/SSHL/USHL/SSHR)
On 20 August 2013 16:04, Vidya Praveen wrote: >> 2013-08-20 Vidya Praveen >> >> * config/aarch64/aarch64.md (unspec): Add UNSPEC_SISD_SSHL, >> UNSPEC_SISD_USHL, UNSPEC_USHL_2S, UNSPEC_SSHL_2S, UNSPEC_SISD_NEG. >> (3_insn): Remove. >> (aarch64_ashl_sisd_or_int_3): New Pattern. >> (aarch64_lshr_sisd_or_int_3): Likewise. >> (aarch64_ashr_sisd_or_int_3): Likewise. >> (define_split for aarch64_lshr_sisd_or_int_di3): Likewise. >> (define_split for aarch64_lshr_sisd_or_int_si3): Likewise. >> (define_split for aarch64_ashr_sisd_or_int_di3): Likewise. >> (define_split for aarch64_ashr_sisd_or_int_si3): Likewise. >> (aarch64_sisd_ushl, aarch64_sisd_sshl): Likewise. >> (aarch64_ushl_2s, aarch64_sshl_2s, aarch64_sisd_neg_qi): Likewise. >> (ror3_insn): Likewise. >> * config/aarch64/predicates.md (aarch64_simd_register): New. >> >> gcc/testsuite/ChangeLog >> >> 2013-08-20 Vidya Praveen >> >> * gcc.target/aarch64/scalar_shift_1.c: New. >> OK /Marcus
Re: [RFC Patch, Aarch64] : Macros for profile code generation to enable gprof support
Hi Venkat,
On 3 August 2013 19:01, Venkataramanan Kumar
wrote:
> This patch adds macros to support gprof in Aarch64. The difference
> from the previous patch is that the compiler, while generating
> "mcount" routine for an instrumented function, also passes the return
> address as argument.
>
> The "mcount" routine in glibc will be modified as follows.
>
> (-Snip-)
> #define MCOUNT \
> -void __mcount (void)
> \
> +void __mcount (void* frompc)
>\
> {
> \
> - mcount_internal ((u_long) RETURN_ADDRESS (1), (u_long) RETURN_ADDRESS
> (0)); \
> + mcount_internal ((u_long) frompc, (u_long) RETURN_ADDRESS (0)); \
> }
> (-Snip-)
> If this is Ok I will send the patch to glibc as well.
> 2013-08-02 Venkataramanan Kumar
>
> * config/aarch64/aarch64.h (MCOUNT_NAME): Define.
>(NO_PROFILE_COUNTERS): Likewise.
>(PROFILE_HOOK): Likewise.
>(FUNCTION_PROFILER): Likewise.
> * config/aarch64/aarch64.c (aarch64_function_profiler): Remove.
>.
>
> regards,
> Venkat.
+ emit_library_call (fun, LCT_NORMAL, VOIDmode, 1,lr,Pmode); \
+}
GNU coding style requires spaces after the commas, but otherwise I
have no further comments on this patch. Post the glibc patch please.
Thanks
/Marcus
Re: [AArch64] Rewrite the vdup_lane intrinsics in C
On 9 August 2013 10:48, James Greenhalgh wrote: > --- > gcc/ > > 2013-08-09 James Greenhalgh > > * config/aarch64/aarch64-simd-builtins.def > (dup_lane_scalar): Remove. > * config/aarch64/aarch64-simd.md > (aarch64_simd_dup): Add 'w->w' alternative. > (aarch64_dup_lane): Allow for VALL. > (aarch64_dup_lane_scalar): Remove. > (aarch64_dup_lane_): New. > (aarch64_get_lane_signed): Add w->w altenative. > (aarch64_get_lane_unsigned): Likewise. > (aarch64_get_lane): Likewise. > * config/aarch64/aarch64.c (aarch64_evpc_dup): New. > (aarch64_expand_vec_perm_const_1): Use aarch64_evpc_dup. > * config/aarch64/iterators.md (VSWAP_WIDTH): New. > (VCON): Change container of V2SF. > (vswap_width_name): Likewise. > * config/aarch64/arm_neon.h > (__aarch64_vdup_lane_any): New. > (__aarch64_vdup_lane_<8,16,32,64>): Likewise. > (vdup_n_<8,16,32,64>): Convert to C implementation. > (vdup_lane_<8,16,32,64>): Likewise. > > gcc/testsuite/ > > 2013-08-09 James Greenhalgh > > * gcc.target/aarch64/scalar_intrinsics.c > (vdup_lane<8,16,32,64>): Force values to SIMD registers. OK /Marcus
Re: [PATCH, AArch64] Improve handling of constants destined for FP_REGS
On 4 September 2013 17:42, Ian Bolton wrote: > (This patch supercedes this one: > http://gcc.gnu.org/ml/gcc-patches/2013-07/msg01462.html) > 2013-09-04 Ian Bolton > > gcc/ > * config/aarch64/aarch64.c (aarch64_preferred_reload_class): > Return NO_REGS for immediate that can't be moved directly > into FP_REGS. > > testsuite/ > * gcc.target/aarch64/movdi_1.c: New test. Ok, thanks /Marcus
Re: [AArch64] Fix categorisation of the frecp* insns.
On 3 September 2013 12:30, James Greenhalgh wrote: > 2013-09-03 James Greenhalgh > > * config/aarch64/aarch64.md > (type): Remove frecpe, frecps, frecpx. > (aarch64_frecp): Move to aarch64-simd.md, > fix to be a TARGET_SIMD instruction. > (aarch64_frecps): Remove. > * config/aarch64/aarch64-simd.md > (aarch64_frecp): New, moved from aarch64.md > (aarch64_frecps): Handle all float/vector of float modes. OK /Marcus
Re: [PATCH, AArch64] support extension option 'crc' in -march and -mcpu
On 4 September 2013 15:47, Yufeng Zhang wrote: > gcc/ > > * config/aarch64/aarch64-option-extensions.def: Add > AARCH64_OPT_EXTENSION of 'crc'. > * config/aarch64/aarch64.h (AARCH64_FL_CRC): New define. > (AARCH64_ISA_CRC): Ditto. > * doc/invoke.texi (-march and -mcpu feature modifiers): Add > description of the CRC extension. OK /Marcus
Re: [Patch AArch64] Fix register constraints for lane intrinsics.
On 6 September 2013 09:18, James Greenhalgh wrote: > > Hi, > > Most of the vector-by-element instructions in AArch64 have the restriction > that, if the vector they are taking an element from has type "h" > then it must be in a register from the lower half of the vector register > set (i.e. v0-v15). While we have imposed that restriction in places, we > have not been consistent. > > Fix that. > > Tested with aarch64.exp with no regressions. > > OK for trunk? OK /Marcus
Re: [Patch, AArch64] Fix vdup_lane_* intrinsics' lane parameter.
On 5 September 2013 17:21, Tejas Belagod wrote: > > Hi, > > This patch fixes vdup_lane_* intrinsics in arm_neon.h to have the > correct lane parameter as opposed to the present '0'. > > Tested on aarch64-none-elf. OK for trunk? > > Thanks, > Tejas Belagod > ARM. > > Changelog: > > 2013-09-05 Tejas Belagod OK /Marcus
Re: [AArch64] Fix types of second parameter to qtbl/qtbx intrinsics
On 6 September 2013 11:45, James Greenhalgh wrote: > The signed variants of the qtbl and qtbx intrinsics currently > take an int8x<8,16> for their control vector parameter. > This should be a uint8x<8,16> parameter. > > Fixed as attached and checked against aarch64.exp on aarch64-none-elf > with no regressions. > > Is this OK to commit? This is OK. /Marcus
Re: [AArch64] Prevent generic pipeline description from dominating other pipeline descriptions.
On 10 September 2013 09:23, James Greenhalgh wrote: > 2013-09-10 James Greenhalgh > > * config/aarch64/aarch64.md (generic_sched): New. > * config/aarch64/aarch64-generic.md (load): Make conditional > on generic_sched attribute. > (nonload): Likewise. OK /Marcus
Re: [AArch64] Implement vcopy intrinsics.
On 13/09/13 19:39, James Greenhalgh wrote: Hi, This patch adds intrinsics for vcopy_lane_<8,16,32,64>. These are implemented in an optimal way using the vget_lane and vset_lane intrinsics and a combine pattern. I've added a testcase and run a full regression run for aarch64-none-elf. OK? Thanks, James OK /Marcus
Re: [AArch64] Implement vmul_lane_<16,32,64> intrinsics in C
On 13/09/13 19:28, James Greenhalgh wrote: Hi, This patch converts the vmul_lane_<16,32,64> intrinsics in arm_neon.h to a C implementation. OK /Marcus
Re: [AArch64] Improve arm_neon.h vml_lane handling.
On 13/09/13 19:31, James Greenhalgh wrote: Hi, This patch reimpliments the vml_lane and the fm intrinsics in C, and adds new combiner patterns to support this. OK /Marcus
Re: [AArch64] Fix parameters to vcvtx_high
On 06/09/13 16:06, James Greenhalgh wrote: gcc/ 2013-09-06 James Greenhalgh * config/aarch64/arm_neon.h (vcvtx_high_f32_f64): Fix parameters. OK /Marcus
Re: [PATCH][AARCH64]Replace gen_rtx_PLUS with plus_constant
On 20 September 2013 15:18, Renlin Li wrote: > 2013-09-20 Renlin Li > > * config/aarch64/aarch64.c (aarch64_expand_prologue): Use plus_constant. > (aarch64_expand_epilogue): Likewise. > (aarch64_legitimize_reload_address): Likewise. OK /Marcus
Re: [PATCH, AArch64] Fix the pointer-typed function argument expansion in aarch64_simd_expand_args
On 10 September 2013 18:12, Yufeng Zhang wrote: > gcc/ > > * config/aarch64/aarch64-builtins.c (aarch64_simd_expand_args): > Call aarch64_simd_expand_args to update op[argc]. OK /Marcus
Re: [patch, libgfortran, configure] Cross-compile support for libgfortran
On 4 June 2013 20:49, Steve Ellcey wrote: > This patch allows me to build libgfortran for a cross-compiling toolchain > using newlib. Currently the checks done by AC_CHECK_FUNCS_ONCE fail with > my toolchain because the compile/link fails due to the configure script not > using the needed linker script in the link command. The check for with_newlib > is how libjava deals with the problem and it fixes my build problems. > > My only concern is defining HAVE_STRTOLD, strtold exists in my newlib but > I am not sure if that is true for all newlib builds. I didn't see any > flags that I could easily use to check for long double support in the > libgfortran configure.ac, but it seems to assume that the type exists. > > OK to checkin? This patch breaks systems where long double is wider than double. The newlib implementation provides strtold for systems where double is as wide as long double but not on systems where long double is wider. I don;t see any issues with AC_CHECK_FUNC_ONCE when cross configuring aarch64 toolchains but I would have thought that fixing the link test issue you encountered would be preferable to hard coding assumptions in the configure script? Cheers /Marcus
[PATCH] Fix libgfortran cross compile configury w.r.t newlib
This patch:
http://gcc.gnu.org/ml/fortran/2013-06/msg00038.html
... breaks libgfortran configure against newlib.
The solution implemented hard wires an assumption in
libgfortran/configure.ac that newlib provides strtold(). This
assumption is not correct, newlib only provides an implementation of
strtold on systems where sizeof(long double) == sizeof(double). This
manifests as a regression when trying to build a cross aarch64 bare
metal toolchain with fortran enabled.
The attached patch tightens the condition introduced in the earlier
patch such that we continue to call AC_CHECK_FUNCS_ONCE unless we know
that link tests are not possible, in which case we fall back to the
existing broken assumption.
I'm in two minds about whether further sticky tape of this form is the
right approach or whether the original patch should be reverted until a
proper fix that does not regress the tree can be found.
Thoughts?
2013-09-26 Marcus Shawcroft
* configure.ac (AC_CHECK_FUNCS_ONCE): Make if statement
dependent on gcc_no_link.
Cheers
/Marcusdiff --git a/libgfortran/configure.ac b/libgfortran/configure.ac
index 4609eba..411ab38 100644
--- a/libgfortran/configure.ac
+++ b/libgfortran/configure.ac
@@ -261,7 +261,7 @@ GCC_HEADER_STDINT(gstdint.h)
AC_CHECK_MEMBERS([struct stat.st_blksize, struct stat.st_blocks, struct
stat.st_rdev])
# Check for library functions.
-if test "x${with_newlib}" = "xyes"; then
+if test "x${with_newlib}" = "xyes" -a "x${gcc_no_link}" = "xyes" ; then
# We are being configured with a cross compiler. AC_REPLACE_FUNCS
# may not work correctly, because the compiler may not be able to
# link executables.
Re: [RFC Patch, Aarch64] : Macros for profile code generation to enable gprof support
On 28 September 2013 11:57, Venkataramanan Kumar wrote: > 2013-10-28 Venkataramanan Kumar > >* config/aarch64/aarch64.h (MCOUNT_NAME): Define. >(NO_PROFILE_COUNTERS): Likewise. >(PROFILE_HOOK): Likewise. >(FUNCTION_PROFILER): Likewise. >* config/aarch64/aarch64.c (aarch64_function_profiler): Remove. OK, Thank you. /Marcus
Re: [ARM, AArch64] Make aarch64-common.c files more robust.
On 30 September 2013 09:52, James Greenhalgh wrote: > > Hi, > > aarch64-common.c. These functions expect a particular form You meant aarch-common.c here and in the title ;-) This is fine by me, but as a config/arm/ change needs OK from Ramana or Richard. /Marcus > 2013-09-30 James Greenhalgh > > * config/arm/aarch-common.c > (arm_early_load_addr_dep): Add sanity checking. > (arm_no_early_alu_shift_dep): Likewise. > (arm_no_early_alu_shift_value_dep): Likewise. > (arm_no_early_mul_dep): Likewise. > (arm_no_early_store_addr_dep): Likewise.
Re: [PATCH] Fix libgfortran cross compile configury w.r.t newlib
On 27/09/13 17:08, Steve Ellcey wrote:
On Thu, 2013-09-26 at 14:47 +0100, Marcus Shawcroft wrote:
I'm in two minds about whether further sticky tape of this form is the
right approach or whether the original patch should be reverted until a
proper fix that does not regress the tree can be found.
Thoughts?
2013-09-26 Marcus Shawcroft
* configure.ac (AC_CHECK_FUNCS_ONCE): Make if statement
dependent on gcc_no_link.
Cheers
/Marcus
Well, I thought this patch would work for me, but it does not. It looks
like gcc_no_link is set to 'no' on my target because, technically, I can
link even if I don't use a linker script. I just can't find any
functions.
% cat x.c
int main (void) { return 0; }
% mips-mti-elf-gcc x.c -o x
/local/home/sellcey/nightly/install-mips-mti-elf/lib/gcc/mips-mti-elf/4.9.0/../../../../mips-mti-elf/bin/ld:
warning: cannot find entry symbol __start; defaulting to 00400098
% echo $?
0
% cat y.c
int main (void) { exit (0); }
% install-mips-mti-elf/bin/mips-mti-elf-gcc y.c -o y
/local/home/sellcey/nightly/install-mips-mti-elf/lib/gcc/mips-mti-elf/4.9.0/../../../../mips-mti-elf/bin/ld:
warning: cannot find entry symbol __start; defaulting to 00400098
/tmp/ccdG78PN.o: In function `main':
y.c:(.text+0x14): undefined reference to `exit'
collect2: error: ld returned 1 exit status
ubuntu-sellcey % echo $?
1
In which case gating on gcc_no_link could be replaced with a test that
looks to see if we can link with the library. Perhaps looking for
exit() or some such that might reasonably be expected to be present.
For example:
AC_CHECK_FUNC(exit)
if test "x${with_newlib}" = "xyes" -a "x${ac_cv_func_exit}" = "xno"; then
/Marcus
Re: [PATCH][ARM]Replace gen_rtx_PLUS with plus_constant
On 30 September 2013 14:23, Renlin Li wrote: > OK for trunk? > > Kind regards, > Renlin Li > > gcc/ChangeLog: > > 2013-09-30 Renlin Li > > * config/arm/arm.c (arm_output_mi_thunk): Use plus_constant. OK /Marcus
Re: [PATCH][AARCH64]Replace gen_rtx_PLUS with plus_constant
On 30 September 2013 14:20, Renlin Li wrote: > gcc/ChangeLog: > > 2013-09-30 Renlin Li > > * config/aarch64/aarch64.c (aarch64_expand_prologue): Use plus_constant. > (aarch64_expand_epilogue): Likewise. OK /Marcus
[PATCH v2] Fix libgfortran cross compile configury w.r.t newlib
On 30/09/13 13:40, Marcus Shawcroft wrote:
Well, I thought this patch would work for me, but it does not. It looks
like gcc_no_link is set to 'no' on my target because, technically, I can
link even if I don't use a linker script. I just can't find any
functions.
In which case gating on gcc_no_link could be replaced with a test that
looks to see if we can link with the library. Perhaps looking for
exit() or some such that might reasonably be expected to be present.
For example:
AC_CHECK_FUNC(exit)
if test "x${with_newlib}" = "xyes" -a "x${ac_cv_func_exit}" = "xno"; then
/Marcus
Patch attached.
/Marcus
2013-10-01 Marcus Shawcroft
* configure.ac (AC_CHECK_FUNCS_ONCE): Add for exit() then make
existing AC_CHECK_FUNCS_ONCE dependent on outcome.
diff --git a/libgfortran/configure.ac b/libgfortran/configure.ac
index 4609eba..ac0c02f 100644
--- a/libgfortran/configure.ac
+++ b/libgfortran/configure.ac
@@ -261,7 +261,8 @@ GCC_HEADER_STDINT(gstdint.h)
AC_CHECK_MEMBERS([struct stat.st_blksize, struct stat.st_blocks, struct
stat.st_rdev])
# Check for library functions.
-if test "x${with_newlib}" = "xyes"; then
+AC_CHECK_FUNC(exit)
+if test "x${with_newlib}" = "xyes" -a "x${ac_cv_func_exit}" = "xno"; then
# We are being configured with a cross compiler. AC_REPLACE_FUNCS
# may not work correctly, because the compiler may not be able to
# link executables.
Re: [Patch,AArch64] Support SADDL/SSUBL/UADDL/USUBL
> 2013-09-30 Vidya Praveen > > * aarch64-simd.md > (aarch64_l2_internal): Rename to > ... > (aarch64_l_hi_internal): ... this; > Insert '\t' to output template. > (aarch64_l_lo_internal): New. > (aarch64_saddl2, aarch64_uaddl2): Modify to call > gen_aarch64_l_hi_internal() > instead. > (aarch64_ssubl2, aarch64_usubl2): Ditto. > > gcc/testsuite/ChangeLog: > > 2013-09-30 Vidya Praveen > > * gcc.target/aarch64/vect_saddl_1.c: New. OK /Marcus
Re: [PATCH, AARCH64] Added predefines for AArch64 code models
On 11/09/12 15:02, Chris Schlumberger-Socha wrote: This patch adds predefines for AArch64 code models. These code models are added as an effective target for the AArch64 platform. I've committed this patch to aarch64-trunk. /Marcus
Re: [PATCH] [AArch64] Refactor Advanced SIMD builtin initialisation.
On 05/10/12 16:52, James Greenhalgh wrote: Hi, This patch refactors the initialisation code for the Advanced SIMD builtins under the AArch64 target. The patch has been regression tested on aarch64-none-elf. OK for aarch64-branch? (If yes, someone will have to commit this for me as I do not have commit rights) Thanks, James Greenhalgh --- 2012-09-07 James Greenhalgh Tejas Belagod * config/aarch64/aarch64-builtins.c (aarch64_simd_builtin_type_bits): Rename to... (aarch64_simd_builtin_type_mode): ...this, make sequential. (aarch64_simd_builtin_datum): Refactor members where possible. (VAR1, VAR2, ..., VAR12): Update accordingly. (aarch64_simd_builtin_data): Update accordingly. (init_aarch64_simd_builtins): Refactor. (aarch64_simd_builtin_compare): Remove. (locate_simd_builtin_icode): Likewise. OK and backport to aarch64-4.7-branch please. /Marcus
Re: [PATCH] [AArch64] Add vcond, vcondu support.
On 09/10/12 12:08, James Greenhalgh wrote: Hi, This patch adds support for vcond and vcondu to the AArch64 backend. Tested with no regressions on aarch64-none-elf. OK for aarch64-branch? (If so, someone will have to commit for me, as I do not have commit rights.) Thanks James Greenhalgh --- 2012-09-11 James Greenhalgh Tejas Belagod * config/aarch64/aarch64-simd.md (aarch64_simd_bsl_internal): New pattern. (aarch64_simd_bsl): Likewise. (aarch64_vcond_internal): Likewise. (vcondu): Likewise. (vcond): Likewise. * config/aarch64/iterators.md (UNSPEC_BSL): Add to define_constants. OK /Marcus
[AARCH64] Fix ICE in aarch64_split_doubleword_move
I've just committed this patch to aarch64-trunk to resolve an ICE in
aarch64_split_doubleword_move when attempting to split v->v moves.
/Marcus
2012-10-16 Marcus Shawcroft
* config/aarch64/aarch64-protos.h (aarch64_split_doubleword_move):
Rename to aarch64_split_128bit_move.
(aarch64_split_128bit_move_p): New.
* config/aarch64/aarch64.c (aarch64_split_doubleword_move):
Rename to aarch64_split_128bit_move.
(aarch64_split_128bit_move_p): New.
* config/aarch64/aarch64.md: Adjust TImode move split.diff --git a/gcc/config/aarch64/aarch64-protos.h b/gcc/config/aarch64/aarch64-protos.h
index e6d35e4..712d2f6 100644
--- a/gcc/config/aarch64/aarch64-protos.h
+++ b/gcc/config/aarch64/aarch64-protos.h
@@ -245,7 +245,9 @@ void aarch64_simd_lane_bounds (rtx, HOST_WIDE_INT, HOST_WIDE_INT);
/* Emit code for reinterprets. */
void aarch64_simd_reinterpret (rtx, rtx);
-void aarch64_split_doubleword_move (rtx, rtx);
+void aarch64_split_128bit_move (rtx, rtx);
+
+bool aarch64_split_128bit_move_p (rtx, rtx);
#if defined (RTX_CODE)
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index a766b7e..b36be90 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -537,7 +537,7 @@ aarch64_emit_move (rtx dest, rtx src)
}
void
-aarch64_split_doubleword_move (rtx dst, rtx src)
+aarch64_split_128bit_move (rtx dst, rtx src)
{
rtx low_dst;
@@ -569,7 +569,7 @@ aarch64_split_doubleword_move (rtx dst, rtx src)
}
/* Fall through to r -> r cases. */
}
-
+
low_dst = gen_lowpart (word_mode, dst);
if (REG_P (low_dst)
&& reg_overlap_mentioned_p (low_dst, src))
@@ -586,6 +586,13 @@ aarch64_split_doubleword_move (rtx dst, rtx src)
}
}
+bool
+aarch64_split_128bit_move_p (rtx dst, rtx src)
+{
+ return (! REG_P (src)
+ || ! (FP_REGNUM_P (REGNO (dst)) && FP_REGNUM_P (REGNO (src;
+}
+
static rtx
aarch64_force_temporary (rtx x, rtx value)
{
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index 5c92a5b..1669726 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -947,10 +947,10 @@
(define_split
[(set (match_operand:TI 0 "register_operand" "")
(match_operand:TI 1 "aarch64_reg_or_imm" ""))]
- "reload_completed"
+ "reload_completed && aarch64_split_128bit_move_p (operands[0], operands[1])"
[(const_int 0)]
{
- aarch64_split_doubleword_move (operands[0], operands[1]);
+ aarch64_split_128bit_move (operands[0], operands[1]);
DONE;
})
--
1.7.12.rc0.22.gcdd159b
Re: [PATCH, AARCH64] Added predefines for AArch64 code models
On 15/10/12 11:03, Marcus Shawcroft wrote: On 11/09/12 15:02, Chris Schlumberger-Socha wrote: This patch adds predefines for AArch64 code models. These code models are added as an effective target for the AArch64 platform. I've committed this patch to aarch64-trunk. /Marcus .. and back ported to aarch64-4.7-branch, the patch applies cleanly and requires no modification. /Marcus
Re: [AARCH64] Fix ICE in aarch64_split_doubleword_move
On 16/10/12 16:10, Marcus Shawcroft wrote: I've just committed this patch to aarch64-trunk to resolve an ICE in aarch64_split_doubleword_move when attempting to split v->v moves. /Marcus 2012-10-16 Marcus Shawcroft * config/aarch64/aarch64-protos.h (aarch64_split_doubleword_move): Rename to aarch64_split_128bit_move. (aarch64_split_128bit_move_p): New. * config/aarch64/aarch64.c (aarch64_split_doubleword_move): Rename to aarch64_split_128bit_move. (aarch64_split_128bit_move_p): New. * config/aarch64/aarch64.md: Adjust TImode move split. and committed to aarch64-4.7-branch. /Marcus
[PATCH] [0/10] AArch64 Port
Folks, We would like to request the merge of aarch64-branch into trunk. This series of patches represents the delta from gcc trunk @r192445 to aarch64-branch @r192535. The patch set is broken down as follows: [1/10] gcc configury This patch contains the adjustments to top level gcc configury required to enable the AArch64 port. [2/10] gcc doc updates This patch contains the additions to the gcc/doc files to document the AArch64 port. [3/10] gcc AArch64 target new files This patch contains all of the new files for the target port itself, the patch does not modify any existing file. [4/10] gcc test suite adjustments This patch contains the adjustments to the existing test suite to support AArch64. [5/10] gcc AArch64 test suite new files This patch contains all of the new files added to the test suite for AArch64, the patch does not modify any existing file. [6/10] libatomic adjustments This patch adjusts the libatomic configury for AArch64. [7/10] libcpp adjustments This patch adjusts the libcpp configury for AArch64. [8/10] libgcc adjustments This patch provides the AArch64 libgcc port, it contains both the required configury adjustment to config.host and the new files introduced by the AArch64 port. [9/10] libgomp adjustments This patch adjusts the libgomp configury for AArch64. [10/10] libstdc adjustments This patch provides the AArch64 libstdc++-v3 port, it contains both the required configury adjustment to config.host and the new file introduced by the AArch64 port. In addition to these patches, the config.guess file will also need to be copied down from upstream, no patch provided. OK to commit? Thanks /Marcus
[PATCH] [1/10] AArch64 Port
This patch contains the adjustments to top level gcc configury required
to enable the AArch64 port.
Proposed ChangeLog:
* config.gcc: Add AArch64.
* configure.ac: Add AArch64 TLS support detection.
* configure: Regenerate.
diff --git a/gcc/config.gcc b/gcc/config.gcc
index
ed7474ad68c4ae7234072d508b697a9a2218d18d..75ca21756ebca80479d69c38ff8d3c4142d822f3
100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -310,6 +310,13 @@ m32c*-*-*)
tmake_file=m32c/t-m32c
target_has_targetm_common=no
;;
+aarch64*-*-*)
+ cpu_type=aarch64
+ need_64bit_hwint=yes
+ extra_headers="arm_neon.h"
+ extra_objs="aarch64-builtins.o"
+ target_has_targetm_common=yes
+ ;;
alpha*-*-*)
cpu_type=alpha
need_64bit_hwint=yes
@@ -796,6 +803,27 @@ case ${target} in
esac
case ${target} in
+aarch64*-*-elf)
+ tm_file="${tm_file} dbxelf.h elfos.h newlib-stdint.h"
+ tm_file="${tm_file} aarch64/aarch64-elf.h aarch64/aarch64-elf-raw.h"
+ tmake_file="${tmake_file} aarch64/t-aarch64"
+ use_gcc_stdint=wrap
+ case $target in
+ aarch64_be-*)
+ tm_defines="${tm_defines} TARGET_BIG_ENDIAN_DEFAULT=1"
+ ;;
+ esac
+ ;;
+aarch64*-*-linux*)
+ tm_file="${tm_file} dbxelf.h elfos.h gnu-user.h linux.h glibc-stdint.h"
+ tm_file="${tm_file} aarch64/aarch64-elf.h aarch64/aarch64-linux.h"
+ tmake_file="${tmake_file} aarch64/t-aarch64 aarch64/t-aarch64-linux"
+ case $target in
+ aarch64_be-*)
+ tm_defines="${tm_defines} TARGET_BIG_ENDIAN_DEFAULT=1"
+ ;;
+ esac
+ ;;
alpha*-*-linux*)
tm_file="elfos.h ${tm_file} alpha/elf.h alpha/linux.h alpha/linux-elf.h
glibc-stdint.h"
extra_options="${extra_options} alpha/elf.opt"
@@ -2995,6 +3023,92 @@ fi
supported_defaults=
case "${target}" in
+ aarch64*-*-*)
+ supported_defaults="cpu arch"
+ for which in cpu arch; do
+
+ eval "val=\$with_$which"
+ base_val=`echo $val | sed -e 's/\+.*//'`
+ ext_val=`echo $val | sed -e 's/[a-z0-9\-]\+//'`
+
+ if [ $which = arch ]; then
+ def=aarch64-arches.def
+ pattern=AARCH64_ARCH
+ else
+ def=aarch64-cores.def
+ pattern=AARCH64_CORE
+ fi
+
+ ext_mask=AARCH64_CPU_DEFAULT_FLAGS
+
+ # Find the base CPU or ARCH id in aarch64-cores.def or
+ # aarch64-arches.def
+ if [ x"$base_val" = x ] \
+ || grep "^$pattern(\"$base_val\"," \
+ ${srcdir}/config/aarch64/$def \
+ > /dev/null; then
+
+ if [ $which = arch ]; then
+ base_id=`grep "^$pattern(\"$base_val\"," \
+ ${srcdir}/config/aarch64/$def | \
+ sed -e 's/^[^,]*,[]*//' | \
+ sed -e 's/,.*$//'`
+ else
+ base_id=`grep "^$pattern(\"$base_val\"," \
+ ${srcdir}/config/aarch64/$def | \
+ sed -e 's/^[^,]*,[]*//' | \
+ sed -e 's/,.*$//'`
+ fi
+
+ while [ x"$ext_val" != x ]
+ do
+ ext_val=`echo $ext_val | sed -e 's/\+//'`
+ ext=`echo $ext_val | sed -e 's/\+.*//'`
+ base_ext=`echo $ext | sed -e 's/^no//'`
+
+ if [ x"$base_ext" = x ] \
+ || grep
"^AARCH64_OPT_EXTENSION(\"$base_ext\"," \
+
${srcdir}/config/aarch64/aarch64-option-extensions.def \
+ > /dev/null; then
+
+ ext_on=`grep
"^AARCH64_OPT_EXTENSION(\"$base_ext\"," \
+
${srcdir}/config/aarch64/aarch64-option-extensions.def | \
+ sed -e 's/^[^,]*,[ ]*//' | \
+ sed -e 's/,.*$//'`
+ ext_off=`grep
"^AARCH64_OPT_EXTENSION(\"$base_ext\"," \
+
${srcdir}/config/aarch64/aarch64-option-extensions.def | \
+ sed -e 's/^[^,]*,[ ]*[^,]*,[
]*//' | \
+ sed -e 's/,.*$//' | \
+ sed -e 's/).*$//'`
+
+ if [ $ext = $base_ext ]; then
+
[PATCH] [2/10] AArch64 Port
This patch contains the additions to the gcc/doc files to document
the AArch64 port.
Proposed ChangeLog:
* doc/invoke.texi (AArch64 Options): New.
* doc/md.texi (Machine Constraints): Add AArch64.
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index
a9a79343985bdc6bcd070453446a40e996199612..cb5de9e1993eabef512cbbcbe79de6588c6b666a
100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -467,6 +467,15 @@ Objective-C and Objective-C++ Dialects}.
@c Try and put the significant identifier (CPU or system) first,
@c so users have a clue at guessing where the ones they want will be.
+@emph{AArch64 Options}
+@gccoptlist{-mbig-endian -mlittle-endian @gol
+-mgeneral-regs-only @gol
+-mcmodel=tiny -mcmodel=small -mcmodel=large @gol
+-mstrict-align @gol
+-momit-leaf-frame-pointer -mno-omit-leaf-frame-pointer @gol
+-mtls-dialect=desc -mtls-dialect=traditional @gol
+-march=@var{name} -mcpu=@var{name} -mtune=@var{name}}
+
@emph{Adapteva Epiphany Options}
@gccoptlist{-mhalf-reg-file -mprefer-short-insn-regs @gol
-mbranch-cost=@var{num} -mcmove -mnops=@var{num} -msoft-cmpsf @gol
@@ -10611,6 +10620,7 @@ platform.
@c in Machine Dependent Options
@menu
+* AArch64 Options::
* Adapteva Epiphany Options::
* ARM Options::
* AVR Options::
@@ -10820,6 +10830,125 @@ purpose. The default is @option{-m1reg-
@end table
+@node AArch64 Options
+@subsection AArch64 Options
+@cindex AArch64 Options
+
+These options are defined for AArch64 implementations:
+
+@table @gcctabopt
+
+@item -mbig-endian
+@opindex mbig-endian
+Generate big-endian code. This is the default when GCC is configured for an
+@samp{aarch64_be-*-*} target.
+
+@item -mgeneral-regs-only
+@opindex mgeneral-regs-only
+Generate code which uses only the general registers.
+
+@item -mlittle-endian
+@opindex mlittle-endian
+Generate little-endian code. This is the default when GCC is configured for an
+@samp{aarch64-*-*} but not an @samp{aarch64_be-*-*} target.
+
+@item -mcmodel=tiny
+@opindex mcmodel=tiny
+Generate code for the tiny code model. The program and its statically defined
+symbols must be within 1GB of each other. Pointers are 64 bits. Programs can
+be statically or dynamically linked. This model is not fully implemented and
+mostly treated as "small".
+
+@item -mcmodel=small
+@opindex mcmodel=small
+Generate code for the small code model. The program and its statically defined
+symbols must be within 4GB of each other. Pointers are 64 bits. Programs can
+be statically or dynamically linked. This is the default code model.
+
+@item -mcmodel=large
+@opindex mcmodel=large
+Generate code for the large code model. This makes no assumptions about
+addresses and sizes of sections. Pointers are 64 bits. Programs can be
+statically linked only.
+
+@item -mstrict-align
+@opindex mstrict-align
+Do not assume that unaligned memory references will be handled by the system.
+
+@item -momit-leaf-frame-pointer
+@item -mno-omit-leaf-frame-pointer
+@opindex momit-leaf-frame-pointer
+@opindex mno-omit-leaf-frame-pointer
+Omit or keep the frame pointer in leaf functions. The former behaviour is the
+default.
+
+@item -mtls-dialect=desc
+@opindex mtls-dialect=desc
+Use TLS descriptors as the thread-local storage mechanism for dynamic accesses
+of TLS variables. This is the default.
+
+@item -mtls-dialect=traditional
+@opindex mtls-dialect=traditional
+Use traditional TLS as the thread-local storage mechanism for dynamic accesses
+of TLS variables.
+
+@item -march=@var{name}
+@opindex march
+Specify the name of the target architecture, optionally suffixed by one or
+more feature modifiers. This option has the form
+@option{-march=@var{arch}@r{@{}+@r{[}no@r{]}@var{feature}@r{@}*}}, where the
+only value for @var{arch} is @samp{armv8-a}. The possible values for
+@var{feature} are documented in the sub-section below.
+
+Where conflicting feature modifiers are specified, the right-most feature is
+used.
+
+GCC uses this name to determine what kind of instructions it can emit when
+generating assembly code. This option can be used in conjunction with or
+instead of the @option{-mcpu=} option.
+
+@item -mcpu=@var{name}
+@opindex mcpu
+Specify the name of the target processor, optionally suffixed by one or more
+feature modifiers. This option has the form
+@option{-mcpu=@var{cpu}@r{@{}+@r{[}no@r{]}@var{feature}@r{@}*}}, where the
+possible values for @var{cpu} are @samp{generic}, @samp{large}. The
+possible values for @var{feature} are documented in the sub-section
+below.
+
+Where conflicting feature modifiers are specified, the right-most feature is
+used.
+
+GCC uses this name to determine what kind of instructions it can emit when
+generating assembly code.
+
+@item -mtune=@var{name}
+@opindex mtune
+Specify the name of the processor to tune the performance for. The code will
+be tuned as if the target processor were of the type specified in this option,
+but still using instructions compatible with the targ
[PATCH] [6/10] AArch64 Port
This patch adjusts the libatomic configury for AArch64.
Proposed ChangeLog:
* configure.tgt: Mark libatomic unsupported.diff --git a/libatomic/configure.tgt b/libatomic/configure.tgt
index
847ac41ebed81efff601fcb966d76f35d228dda2..0caa0f42ff99766d1020acd8d966509d0f3447ce
100644
--- a/libatomic/configure.tgt
+++ b/libatomic/configure.tgt
@@ -95,6 +95,11 @@ fi
# Other system configury
case "${target}" in
+ aarch64*)
+ # This is currently not supported in AArch64.
+ UNSUPPORTED=1
+ ;;
+
arm*-*-linux*)
# OS support for atomic primitives.
config_path="${config_path} linux/arm posix"
[PATCH] [4/10] AArch64 Port
This patch contains the adjustments to the existing test suite to
support AArch64.
Proposed ChangeLog:
* lib/target-supports.exp
(check_profiling_available): Add AArch64.
(check_effective_target_vect_int): Likewise.
(check_effective_target_vect_shift): Likewise.
(check_effective_target_vect_float): Likewise.
(check_effective_target_vect_double): Likewise.
(check_effective_target_vect_widen_mult_qi_to_hi): Likewise.
(check_effective_target_vect_widen_mult_hi_to_si): Likewise.
(check_effective_target_vect_pack_trunc): Likewise.
(check_effective_target_vect_unpack): Likewise.
(check_effective_target_vect_hw_misalign): Likewise.
(check_effective_target_vect_short_mult): Likewise.
(check_effective_target_vect_int_mult): Likewise.
(check_effective_target_vect_stridedN): Likewise.
(check_effective_target_sync_int_long): Likewise.
(check_effective_target_sync_char_short): Likewise.
(check_vect_support_and_set_flags): Likewise.
(check_effective_target_aarch64_tiny): New.
(check_effective_target_aarch64_small): New.
(check_effective_target_aarch64_large): New.
* g++.dg/other/PR23205.C: Enable aarch64.
* g++.dg/other/pr23205-2.C: Likewise.
* g++.old-deja/g++.abi/ptrmem.C: Likewise.
* gcc.c-torture/execute/20101011-1.c: Likewise.
* gcc.dg/20020312-2.c: Likewise.
* gcc.dg/20040813-1.c: Likewise.
* gcc.dg/builtin-apply2.c: Likewise.
* gcc.dg/stack-usage-1.c: Likewise.
diff --git a/gcc/testsuite/g++.dg/abi/aarch64_guard1.C
b/gcc/testsuite/g++.dg/abi/aarch64_guard1.C
index ...af82ad2ec36998135e67a25f47d19b4e977fd8d2 100644
--- a/gcc/testsuite/g++.dg/abi/aarch64_guard1.C
+++ b/gcc/testsuite/g++.dg/abi/aarch64_guard1.C
@@ -0,0 +1,17 @@
+// Check that the initialization guard variable is an 8-byte aligned,
+// 8-byte doubleword and that only the least significant bit is used
+// for initialization guard variables.
+// { dg-do compile { target aarch64*-*-* } }
+// { dg-options "-O -fdump-tree-original" }
+
+int bar();
+
+int *foo ()
+{
+ static int x = bar ();
+ return &x;
+}
+
+// { dg-final { scan-assembler _ZGVZ3foovE1x,8,8 } }
+// { dg-final { scan-tree-dump "_ZGVZ3foovE1x & 1" "original" } }
+// { dg-final { cleanup-tree-dump "original" } }
diff --git a/gcc/testsuite/g++.dg/other/PR23205.C
b/gcc/testsuite/g++.dg/other/PR23205.C
index
a31fc1d773ddf0b21bdb219be2646c574923d7a5..e55710b40f0a0a69528ca4e27facff742ff2e4ad
100644
--- a/gcc/testsuite/g++.dg/other/PR23205.C
+++ b/gcc/testsuite/g++.dg/other/PR23205.C
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-skip-if "No stabs" { mmix-*-* *-*-aix* alpha*-*-* hppa*64*-*-*
ia64-*-* tile*-*-* *-*-vxworks } { "*" } { "" } } */
+/* { dg-skip-if "No stabs" { aarch64*-*-* mmix-*-* *-*-aix* alpha*-*-*
hppa*64*-*-* ia64-*-* tile*-*-* *-*-vxworks } { "*" } { "" } } */
/* { dg-options "-gstabs+ -fno-eliminate-unused-debug-types" } */
const int foobar = 4;
diff --git a/gcc/testsuite/g++.dg/other/pr23205-2.C
b/gcc/testsuite/g++.dg/other/pr23205-2.C
index
fbd16dfab5836e4f0ceb987cbf42271d3728c63f..607e5a2b4e433a0fec79d3fda4dc265f1f8a39ae
100644
--- a/gcc/testsuite/g++.dg/other/pr23205-2.C
+++ b/gcc/testsuite/g++.dg/other/pr23205-2.C
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-skip-if "No stabs" { mmix-*-* *-*-aix* alpha*-*-* hppa*64*-*-*
ia64-*-* tile*-*-* } { "*" } { "" } } */
+/* { dg-skip-if "No stabs" { aarch64*-*-* mmix-*-* *-*-aix* alpha*-*-*
hppa*64*-*-* ia64-*-* tile*-*-* } { "*" } { "" } } */
/* { dg-options "-gstabs+ -fno-eliminate-unused-debug-types
-ftoplevel-reorder" } */
const int foobar = 4;
diff --git a/gcc/testsuite/g++.old-deja/g++.abi/ptrmem.C
b/gcc/testsuite/g++.old-deja/g++.abi/ptrmem.C
index
077fa50840c978f9c0dda8c0e7071eda514395b5..341735879c59d517edb1fc49edfb78c6e2e01846
100644
--- a/gcc/testsuite/g++.old-deja/g++.abi/ptrmem.C
+++ b/gcc/testsuite/g++.old-deja/g++.abi/ptrmem.C
@@ -7,7 +7,7 @@
function. However, some platforms use all bits to encode a
function pointer. Such platforms use the lowest bit of the delta,
that is shifted left by one bit. */
-#if defined __MN10300__ || defined __SH5__ || defined __arm__ || defined
__thumb__ || defined __mips__
+#if defined __MN10300__ || defined __SH5__ || defined __arm__ || defined
__thumb__ || defined __mips__ || defined __aarch64__
#define ADJUST_PTRFN(func, virt) ((void (*)())(func))
#define ADJUST_DELTA(delta, virt) (((delta) << 1) + !!(virt))
#else
diff --git a/gcc/testsuite/gcc.c-torture/execute/20101011-1.c
b/gcc/testsuite/gcc.c-torture/execute/20101011-1.c
index
b98454e253ef074b6219a83f0f9473f9dbc0188d..76b9f068723994dd3f0543a9a4ece4538cb676de
100644
--- a/gcc/testsuite/gcc.c-torture/execute/20101011-1.c
+++ b/gcc/testsuite/gcc.c-torture/execute/20101011-1.c
@@ -12,6 +12,10 @@
#elif defined (__sh__)
/* On SH
[PATCH] [7/10] AArch64 Port
This patch adjusts the libcpp configury for AArch64. Proposed ChangeLog: * configure.ac: Enable AArch64. * configure: Regenerate.diff --git a/libcpp/configure.ac b/libcpp/configure.ac index 29bd8c5e6f1a7bddb628f415f3138dfeaa69a483..e62da06ce278f832084ff2080d694c99e24f8532 100644 --- a/libcpp/configure.ac +++ b/libcpp/configure.ac @@ -134,6 +134,7 @@ fi m4_changequote(,) case $target in + aarch64*-*-* | \ alpha*-*-* | \ arm*-*-*eabi* | \ arm*-*-symbianelf* | \ diff --git a/libcpp/configure b/libcpp/configure index 01e4462307f7ae6aa1b563133746fb45e41af74e..d33969b2b2d5f692ed39a78abd8a94c0385d071e 100755 --- a/libcpp/configure +++ b/libcpp/configure @@ -7096,6 +7096,7 @@ fi case $target in + aarch64*-*-* | \ alpha*-*-* | \ arm*-*-*eabi* | \ arm*-*-symbianelf* | \
[PATCH] [9/10] AArch64 Port
This patch adjusts the libgomp configury for AArch64.
Proposed ChangeLog:
* configure.tgt: Add AArch64.diff --git a/libgomp/configure.tgt b/libgomp/configure.tgt
index
d5a1480e4812634ae280238684cb2187b2c618f8..2eecc93a349f3afe9e0afbbc2e98194065873498
100644
--- a/libgomp/configure.tgt
+++ b/libgomp/configure.tgt
@@ -27,6 +27,10 @@ config_path="posix"
if test $enable_linux_futex = yes; then
case "${target}" in
+aarch64*-*-linux*)
+ config_path="linux posix"
+ ;;
+
alpha*-*-linux*)
config_path="linux/alpha linux posix"
;;
[PATCH] [10/10] AArch64 Port
This patch provides the AArch64 libstdc++-v3 port, it contains both the
required configury adjustment to config.host and the new file introduced
by the AArch64 port.
Proposed ChangeLog:
* config/cpu/aarch64/cxxabi_tweaks.h: New file.
* configure.host: Enable aarch64.diff --git a/libstdc++-v3/configure.host b/libstdc++-v3/configure.host
index
ed9e72109d41774c179190d9546b53d0dd4feef1..af5d3ffbff48eb82dd85ef55c290a3e5d2be9f89
100644
--- a/libstdc++-v3/configure.host
+++ b/libstdc++-v3/configure.host
@@ -99,6 +99,9 @@ error_constants_dir="os/generic"
# variants into the established source config/cpu/* sub-directories.
# THIS TABLE IS SORTED. KEEP IT THAT WAY.
case "${host_cpu}" in
+ aarch64*)
+try_cpu=aarch64
+;;
alpha*)
try_cpu=alpha
;;
diff --git a/libstdc++-v3/config/cpu/aarch64/cxxabi_tweaks.h
b/libstdc++-v3/config/cpu/aarch64/cxxabi_tweaks.h
index ...31a423f4fd56bffaead1d1f2b0057cdb80cda1fb 100644
--- a/libstdc++-v3/config/cpu/aarch64/cxxabi_tweaks.h
+++ b/libstdc++-v3/config/cpu/aarch64/cxxabi_tweaks.h
@@ -0,0 +1,60 @@
+// Control various target specific ABI tweaks. AArch64 version.
+
+// Copyright (C) 2004, 2006, 2008, 2009, 2011, 2012
+// Free Software Foundation, Inc.
+//
+// This file is part of the GNU ISO C++ Library. This library is free
+// software; you can redistribute it and/or modify it under the
+// terms of the GNU General Public License as published by the
+// Free Software Foundation; either version 3, or (at your option)
+// any later version.
+
+// This library is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+
+// Under Section 7 of GPL version 3, you are granted additional
+// permissions described in the GCC Runtime Library Exception, version
+// 3.1, as published by the Free Software Foundation.
+
+// You should have received a copy of the GNU General Public License and
+// a copy of the GCC Runtime Library Exception along with this program;
+// see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
+//
[PATCH] [8/10] AArch64 Port
This patch provides the AArch64 libgcc port, it contains both the
required configury adjustment to config.host and the new files
introduced by the AArch64 port.
Proposed ChangeLog:
* config.host (aarch64*-*-elf, aarch64*-*-linux*): New.
* config/aarch64/crti.S: New file.
* config/aarch64/crtn.S: New file.
* config/aarch64/linux-unwind.h: New file.
* config/aarch64/sfp-machine.h: New file.
* config/aarch64/sync-cache.c: New file.
* config/aarch64/t-aarch64: New file.
* config/aarch64/t-softfp: New file.diff --git a/libgcc/config.host b/libgcc/config.host
index
763f6c3a252223e149eb9b995679f455051bfe7a..96c93a4e6a04f63eb7ab629b822a55c19e6d5f97
100644
--- a/libgcc/config.host
+++ b/libgcc/config.host
@@ -83,6 +83,9 @@ m32c*-*-*)
cpu_type=m32c
tmake_file=t-fdpbit
;;
+aarch64*-*-*)
+ cpu_type=aarch64
+ ;;
alpha*-*-*)
cpu_type=alpha
;;
@@ -278,6 +281,16 @@ i[34567]86-*-mingw* | x86_64-*-mingw*)
esac
case ${host} in
+aarch64*-*-elf)
+ extra_parts="$extra_parts crtbegin.o crtend.o crti.o crtn.o"
+ tmake_file="${tmake_file} ${cpu_type}/t-aarch64"
+ tmake_file="${tmake_file} ${cpu_type}/t-softfp t-softfp"
+ ;;
+aarch64*-*-linux*)
+ md_unwind_header=aarch64/linux-unwind.h
+ tmake_file="${tmake_file} ${cpu_type}/t-aarch64"
+ tmake_file="${tmake_file} ${cpu_type}/t-softfp t-softfp"
+ ;;
alpha*-*-linux*)
tmake_file="${tmake_file} alpha/t-alpha alpha/t-ieee t-crtfm
alpha/t-linux"
extra_parts="$extra_parts crtfastmath.o"
diff --git a/libgcc/config/aarch64/crti.S b/libgcc/config/aarch64/crti.S
index ...49611303b023206cd9cd72511e49fe4aadca340c 100644
--- a/libgcc/config/aarch64/crti.S
+++ b/libgcc/config/aarch64/crti.S
@@ -0,0 +1,68 @@
+# Machine description for AArch64 architecture.
+# Copyright (C) 2009, 2010, 2011, 2012 Free Software Foundation, Inc.
+# Contributed by ARM Ltd.
+#
+# This file is free software; you can redistribute it and/or modify it
+# under the terms of the GNU General Public License as published by the
+# Free Software Foundation; either version 3, or (at your option) any
+# later version.
+#
+# This file is distributed in the hope that it will be useful, but
+# WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+# General Public License for more details.
+#
+# Under Section 7 of GPL version 3, you are granted additional
+# permissions described in the GCC Runtime Library Exception, version
+# 3.1, as published by the Free Software Foundation.
+#
+# You should have received a copy of the GNU General Public License and
+# a copy of the GCC Runtime Library Exception along with this program;
+# see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
+#
Re: [PATCH] [3/10] AArch64 Port
On 23/10/12 16:38, Jeff Law wrote: Given that you and Richard Earnshaw are the approved maintainers for the AAarch64 port, I'm going to give this an OK without diving into it. I'm going to assume you and Richard will iterate with anyone who does dive deeply into the port and has comments/suggestions. We will iterate as required with any further comments and suggestions raised. The one question in the back of my mind is whether or not this uses the new iterator support we discussed a few months ago? I can't recall if that was integrated into the trunk or not. The int-iterator support was accepted on trunk ~ 12th June. The AArch64 port does make extensive use of them. /Marcus
Re: [PATCH] [6/10] AArch64 Port
On 23/10/12 16:14, Jeff Law wrote: On 10/23/2012 03:42 AM, Marcus Shawcroft wrote: This patch adjusts the libatomic configury for AArch64. Proposed ChangeLog: * configure.tgt: Mark libatomic unsupported. This is good. Please install. Presumably at some point in the not too distant future, aarch support will be added to libatomic? jeff We have support for atomic optab coming real soon now at which point I think we can simply revert this patch. /Marcus
Re: [PATCH] [2/10] AArch64 Port
On 23/10/12 15:39, Joseph S. Myers wrote:
On Tue, 23 Oct 2012, Marcus Shawcroft wrote:
+@item -mcmodel=tiny
+@opindex mcmodel=tiny
+Generate code for the tiny code model. The program and its statically defined
+symbols must be within 1GB of each other. Pointers are 64 bits. Programs can
+be statically or dynamically linked. This model is not fully implemented and
+mostly treated as "small".
Say @samp{small} instead of using "" quotes in Texinfo sources.
Committed with this correction.
Thankyou
/Marcus
Re: [PATCH] [0/10] AArch64 Port
On 23/10/12 10:42, Marcus Shawcroft wrote: Folks, We would like to request the merge of aarch64-branch into trunk. All of the patches approved by Jeff and Jakub are now committed, with the documentation correction requested by Joseph. /Marcus
[PATCH, AArch64, COMMITTED]
Hi, This patch was actually written by Ian, I'm submitting it on his
behalf.
/Marcus
In draft revisions of the A64 ISA it was not possible to use SP on the
right hand side of a register + register add. This meant that we needed
two scratch registers when a large constant was being added to SP (one
to put SP into and one to put the large constant into).
Nowadays, that's perfectly fine, so we can remove the code in
aarch64_secondary_reload and the associated pattern that were there to
handle this case.
Regression tested on linux - no issues.
2013-10-03 Ian Bolton
* config/aarch64/aarch64.c (aarch64_secondary_reload): Remove
legacy code required for earlier version of ISA.
* config/aarch64/aarch64.md (reload_sp_immediate): Likewise.diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index 2c07ccf..5804115 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -4033,20 +4033,6 @@ aarch64_secondary_reload (bool in_p ATTRIBUTE_UNUSED,
rtx x,
enum machine_mode mode,
secondary_reload_info *sri)
{
- /* Address expressions of the form PLUS (SP, large_offset) need two
- scratch registers, one for the constant, and one for holding a
- copy of SP, since SP cannot be used on the RHS of an add-reg
- instruction. */
- if (mode == DImode
- && GET_CODE (x) == PLUS
- && XEXP (x, 0) == stack_pointer_rtx
- && CONST_INT_P (XEXP (x, 1))
- && !aarch64_uimm12_shift (INTVAL (XEXP (x, 1
-{
- sri->icode = CODE_FOR_reload_sp_immediate;
- return NO_REGS;
-}
-
/* Without the TARGET_SIMD instructions we cannot move a Q register
to a Q register directly. We need a scratch. */
if (REG_P (x) && (mode == TFmode || mode == TImode) && mode == GET_MODE (x)
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index 5312a79..27eea72 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -3799,38 +3799,6 @@
;; Reload support
;; ---
-;; Reload SP+imm where imm cannot be handled by a single ADD instruction.
-;; Must load imm into a scratch register and copy SP to the dest reg before
-;; adding, since SP cannot be used as a source register in an ADD
-;; instruction.
-(define_expand "reload_sp_immediate"
- [(parallel [(set (match_operand:DI 0 "register_operand" "=r")
- (match_operand:DI 1 "" ""))
-(clobber (match_operand:TI 2 "register_operand" "=&r"))])]
- ""
- {
-rtx sp = XEXP (operands[1], 0);
-rtx val = XEXP (operands[1], 1);
-unsigned regno = REGNO (operands[2]);
-rtx scratch = operands[1];
-gcc_assert (GET_CODE (operands[1]) == PLUS);
-gcc_assert (sp == stack_pointer_rtx);
-gcc_assert (CONST_INT_P (val));
-
-/* It is possible that one of the registers we got for operands[2]
- might coincide with that of operands[0] (which is why we made
- it TImode). Pick the other one to use as our scratch. */
-if (regno == REGNO (operands[0]))
- regno++;
-scratch = gen_rtx_REG (DImode, regno);
-
-emit_move_insn (scratch, val);
-emit_move_insn (operands[0], sp);
-emit_insn (gen_adddi3 (operands[0], operands[0], scratch));
-DONE;
- }
-)
-
(define_expand "aarch64_reload_mov"
[(set (match_operand:TX 0 "register_operand" "=w")
(match_operand:TX 1 "register_operand" "w"))
[PATCH] AArch64 fix PR58460
This fixes PR58460, the add and sub shifted register instruction forms
in AArch64 do not permit the stack register. This patch removes k
constraint from the relevant patterns and adds reduced form of the test
case.
Regression test aarch64-none-elf. Committed.
/Marcus
2013-10-03 Marcus Shawcroft
PR target/58460
* config/aarch64/aarch64.md (*adds_mul_imm_)
(*subs_mul_imm_)
(*add__, *add__si_uxtw,*add_mul_imm_)
(*sub__)
(*sub__si_uxtw,*sub_mul_imm_, *sub_mul_imm_si_uxtw):
Remove k constraint.
2013-10-03 Marcus Shawcroft
PR target/58460
* gcc.target/aarch64/pr58460.c: New file.diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index 830bbee..f3e004b 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -1365,7 +1365,7 @@
(plus:GPI (mult:GPI
(match_operand:GPI 1 "register_operand" "r")
(match_operand:QI 2 "aarch64_pwr_2_" "n"))
- (match_operand:GPI 3 "register_operand" "rk"))
+ (match_operand:GPI 3 "register_operand" "r"))
(const_int 0)))
(set (match_operand:GPI 0 "register_operand" "=r")
(plus:GPI (mult:GPI (match_dup 1) (match_dup 2))
@@ -1380,7 +1380,7 @@
(define_insn "*subs_mul_imm_"
[(set (reg:CC_NZ CC_REGNUM)
(compare:CC_NZ
-(minus:GPI (match_operand:GPI 1 "register_operand" "rk")
+(minus:GPI (match_operand:GPI 1 "register_operand" "r")
(mult:GPI
(match_operand:GPI 2 "register_operand" "r")
(match_operand:QI 3 "aarch64_pwr_2_" "n")))
@@ -1500,7 +1500,7 @@
)
(define_insn "*add__"
- [(set (match_operand:GPI 0 "register_operand" "=rk")
+ [(set (match_operand:GPI 0 "register_operand" "=r")
(plus:GPI (ASHIFT:GPI (match_operand:GPI 1 "register_operand" "r")
(match_operand:QI 2 "aarch64_shift_imm_"
"n"))
(match_operand:GPI 3 "register_operand" "r")))]
@@ -1513,7 +1513,7 @@
;; zero_extend version of above
(define_insn "*add__si_uxtw"
- [(set (match_operand:DI 0 "register_operand" "=rk")
+ [(set (match_operand:DI 0 "register_operand" "=r")
(zero_extend:DI
(plus:SI (ASHIFT:SI (match_operand:SI 1 "register_operand" "r")
(match_operand:QI 2 "aarch64_shift_imm_si" "n"))
@@ -1526,7 +1526,7 @@
)
(define_insn "*add_mul_imm_"
- [(set (match_operand:GPI 0 "register_operand" "=rk")
+ [(set (match_operand:GPI 0 "register_operand" "=r")
(plus:GPI (mult:GPI (match_operand:GPI 1 "register_operand" "r")
(match_operand:QI 2 "aarch64_pwr_2_" "n"))
(match_operand:GPI 3 "register_operand" "r")))]
@@ -1873,7 +1873,7 @@
)
(define_insn "*sub__"
- [(set (match_operand:GPI 0 "register_operand" "=rk")
+ [(set (match_operand:GPI 0 "register_operand" "=r")
(minus:GPI (match_operand:GPI 3 "register_operand" "r")
(ASHIFT:GPI
(match_operand:GPI 1 "register_operand" "r")
@@ -1887,7 +1887,7 @@
;; zero_extend version of above
(define_insn "*sub__si_uxtw"
- [(set (match_operand:DI 0 "register_operand" "=rk")
+ [(set (match_operand:DI 0 "register_operand" "=r")
(zero_extend:DI
(minus:SI (match_operand:SI 3 "register_operand" "r")
(ASHIFT:SI
@@ -1901,7 +1901,7 @@
)
(define_insn "*sub_mul_imm_"
- [(set (match_operand:GPI 0 "register_operand" "=rk")
+ [(set (match_operand:GPI 0 "register_operand" "=r")
(minus:GPI (match_operand:GPI 3 "register_operand" "r")
(mult:GPI
(match_operand:GPI 1 "register_operand" "r")
@@ -1915,7 +1915,7 @@
;; zero_extend version of above
(define_insn "*sub_mul_imm_si_uxtw"
- [(set (match_operand:DI 0 "register_operand" "=rk")
+ [(set (match_operand:DI 0 "register_operand" "=r")
(zero_extend:DI
(minus:SI (match_operand:SI 3 "register_operand" "r")
(mult:SI
diff --git a/gcc/testsuite/gcc.target/aarch64/pr58460.c
b/gcc/testsuite/gcc.target/aarch64/pr58460.c
new file mode 100644
index 000..a7e149a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/pr58460.c
@@ -0,0 +1,35 @@
+/* { dg-do run } */
+/* { dg-options "-O" } */
+extern unsigned long x1;
+
+char *
+f (char *a, char *b)
+{
+ return a;
+}
+
+int
+g (char *a)
+{
+ return 2;
+}
+
+void
+h (char *p[])
+{
+ char n[x1][512];
+ char *l = f (p[1], " ");
+ if (g (p[0]))
+n[0][0] = '\0';
+ while (l && *l)
+{
+}
+}
+
+unsigned long x1;
+
+int
+main ()
+{
+ return 0;
+}
Re: [PATCH] AArch64 fix PR58460
On 03/10/13 11:54, Marcus Shawcroft wrote: This fixes PR58460, the add and sub shifted register instruction forms in AArch64 do not permit the stack register. This patch removes k constraint from the relevant patterns and adds reduced form of the test case. Regression test aarch64-none-elf. Committed. /Marcus 2013-10-03 Marcus Shawcroft PR target/58460 * config/aarch64/aarch64.md (*adds_mul_imm_) (*subs_mul_imm_) (*add__, *add__si_uxtw,*add_mul_imm_) (*sub__) (*sub__si_uxtw,*sub_mul_imm_, *sub_mul_imm_si_uxtw): Remove k constraint. 2013-10-03 Marcus Shawcroft PR target/58460 * gcc.target/aarch64/pr58460.c: New file. I'll commit a backport of this to 4.8 tomorrow unless anyone objects Cheers /Marcus
Re: Enable building of libatomic on AArch64
On 3 October 2013 23:43, Michael Hudson-Doyle wrote: > Hi, > > As libatomic builds for and the tests pass on AArch64 (built on x86_64 > but tested on a foundation model, logs and summary: > > http://people.linaro.org/~mwhudson/libatomic.sum.txt > http://people.linaro.org/~mwhudson/runtest-log-v-2.txt > > ) this patch enables the build. > > Cheers, > mwh > (first time posting to this list, let me know if I'm doing it wrong) > > 2013-10-04 Michael Hudson-Doyle > > * configure.tgt: Add AArch64 support. > Hi, The patch looks fine to me. The ChangeLog entry should reflect the code that was removed rather than the functionality added. Perhaps: * configure.tgt (aarch64*): Remove. Did you investigate whether or not the 10 UNSUPPORTED results in the testsuite are sane? I think that 5 look legitimate since they require 128 bit sync ops. The other 5 look superficially like they should be supported on aarch64. We may just be missing aarch64 target supports wiring in check_effective_target_sync_long_long_runtime? /Marcus
Re: [PATCH v2] Fix libgfortran cross compile configury w.r.t newlib
On 1 October 2013 12:40, Marcus Shawcroft wrote: > Patch attached. > > /Marcus > > 2013-10-01 Marcus Shawcroft > > * configure.ac (AC_CHECK_FUNCS_ONCE): Add for exit() then make > existing AC_CHECK_FUNCS_ONCE dependent on outcome. Ping.
Re: [PATCH][AArch64] Vneg NEON intrinsics modified
On 8 October 2013 17:10, Alex Velenko wrote: > gcc/testsuite/ > > 2013-10-08 Alex Velenko > > * gcc.target/aarch64/vneg_f.c: New testcase. > * gcc.target/aarch64/vneg_s.c: New testcase. > > gcc/ > > 2013-10-08 Alex Velenko > > * config/aarch64/arm_neon.h (vneg_f32): Asm replaced with C. > (vneg_f64): New intrinsic. > (vneg_s8): Asm replaced with C. > (vneg_s16): Likewise. > (vneg_s32): Likewise. > (vneg_s64): New intrinsic. > (vnegq_f32): Asm replaced with C. > (vnegq_f64): Likewise. > (vnegq_s8): Likewise. > (vnegq_s16): Likewise. > (vnegq_s32): Likewise. > (vnegq_s64): Likewise. OK, and I committed this for you. /Marcus
Re: [PATCH][AARCH64] Vdiv NEON intrinsic
On 8 October 2013 17:25, Alex Velenko wrote: > gcc/testsuite/ > > 2013-09-10 Alex Velenko > > * gcc.target/aarch64/vdiv_f.c: New testcase. > > gcc/ > > 2013-09-10 Alex Velenko > > * config/aarch64/arm_neon.h (vdiv_f64): Added. OK. I fixed the date format for the proposed ChangeLog entry and committed for you. /Marcus
Re: [PATCH][AArch64] NEON vadd_f64 and vsub_f64 intrinsics modified
On 8 October 2013 17:35, Alex Velenko wrote: > 2013-10-08 Alex Velenko > > * gcc.target/aarch64/vadd_f64.c: New testcase. > * gcc.target/aarch64/vsub_f64.c: New testcase. > > gcc/ > > 2013-10-08 Alex Velenko > > * config/aarch64/arm_neon.h (vadd_f64): Implementation added. > (vsub_f64): Likewise. OK, committed. /Marcus
Re: [PATCH][AArch64] NEON vclz intrinsic modified
On 8 October 2013 17:45, Alex Velenko wrote: > > 2013-10-08 Alex Velenko > > * gcc.target/aarch64/vclz.c: New testcase. > > gcc/ > > 2013-10-08 Alex Velenko > > * config/aarch64/arm_neon.h (vclz_s8): Asm replaced with C > (vclz_s16): Likewise. > (vclz_s32): Likewise. > (vclzq_s8): Likewise. > (vclzq_s16): Likewise. > (vclzq_s32): Likewise. > (vclz_u8): Likewise. > (vclz_u16): Likewise. > (vclz_u32): Likewise. > (vclzq_u8): Likewise. > (vclzq_u16): Likewise. > (vclzq_u32): Likewise. > > * config/aarch64/aarch64.h (CLZ_DEFINED_VALUE_AT_ZERO): Macro > fixed for clz. > > * config/aarch64/aarch64-simd-builtins.def (VAR1 (UNOP, clz, 0, > v4si)): Replaced with iterator. OK, committed. /Marcus
[PATCH] Fix libstdc++/58659.cc test case.
The test case add here:
http://gcc.gnu.org/ml/gcc-patches/2013-10/msg00474.html
Introduced an unprototyped call to abort() resulting in failures due to
unexepected warnings in aarch64-none-elf cross testing.
Committed to trunk as obvious.
Cheers
/Marcus
2013-10-09 Marcus Shawcroft
* testsuite/20_util/shared_ptr/cons/58659.cc: Use
__builtin_abort().diff --git a/libstdc++-v3/testsuite/20_util/shared_ptr/cons/58659.cc b/libstdc++-v3/testsuite/20_util/shared_ptr/cons/58659.cc
index 5e7c730..1b823bc 100644
--- a/libstdc++-v3/testsuite/20_util/shared_ptr/cons/58659.cc
+++ b/libstdc++-v3/testsuite/20_util/shared_ptr/cons/58659.cc
@@ -48,7 +48,7 @@ namespace std
void deallocate(value_type* p, size_t n)
{
if (n != 1 || p != (void*)storage || !allocated)
- abort();
+ __builtin_abort();
allocated = false;
}
[PATCH] testsuite/29_atomics/atomic/cons/49445.cc missing dg-require-atomic-builtins
Hi,
The libstdc++-v3 testcase atomic/cons/49445.cc fails for a variety of
arm configurations that do not provide atomic builtins because the test
is not gated by dg-require-atomic-builtins
OK ?
/M
2013-10-10 Marcus Shawcroft
* testsuite/29_atomics/atomic/cons/49445.cc
(dg-require-atomic-builtins): Add.diff --git a/libstdc++-v3/testsuite/29_atomics/atomic/cons/49445.cc b/libstdc++-v3/testsuite/29_atomics/atomic/cons/49445.cc
index 793b58d..e45e777 100644
--- a/libstdc++-v3/testsuite/29_atomics/atomic/cons/49445.cc
+++ b/libstdc++-v3/testsuite/29_atomics/atomic/cons/49445.cc
@@ -1,3 +1,4 @@
+// { dg-require-atomic-builtins "" }
// { dg-options "-std=gnu++0x" }
// Copyright (C) 2012-2013 Free Software Foundation, Inc.
Re: [AArch64] Fix early-clobber operands to vtbx[1,3]
On 11 October 2013 17:45, James Greenhalgh wrote: > > Hi, > > The vtbx intrinsics are implemented in assembly without noting > that their tmp1 operand is early-clobber. This can, when the > wind blows the wrong way, result in us making a total mess of > the state of registers. > > Fix by marking the required operands as early-clobber. > > Regression tested against aarch64.exp with no problems. > > OK? OK, and back port to 4.8 please. /Marcus
Re: [PATCH v2] Fix libgfortran cross compile configury w.r.t newlib
On 1 October 2013 12:40, Marcus Shawcroft wrote:
> On 30/09/13 13:40, Marcus Shawcroft wrote:
>
>>> Well, I thought this patch would work for me, but it does not. It looks
>>> like gcc_no_link is set to 'no' on my target because, technically, I can
>>> link even if I don't use a linker script. I just can't find any
>>> functions.
>>>
>
>> In which case gating on gcc_no_link could be replaced with a test that
>> looks to see if we can link with the library. Perhaps looking for
>> exit() or some such that might reasonably be expected to be present.
>>
>> For example:
>>
>> AC_CHECK_FUNC(exit)
>> if test "x${with_newlib}" = "xyes" -a "x${ac_cv_func_exit}" = "xno"; then
>>
>> /Marcus
>>
>>
>>
>>
>
>
> Patch attached.
>
> /Marcus
>
> 2013-10-01 Marcus Shawcroft
>
> * configure.ac (AC_CHECK_FUNCS_ONCE): Add for exit() then make
> existing AC_CHECK_FUNCS_ONCE dependent on outcome.
Ping^2
/Marcus
[AArch64] Fix preferred_reload_class for regclass STACK_REG.
The existing AArch64 implementation of preferred_reload_class when
called with a destination regclass STACK_REG returns the wider register
class GENERAL_REG. This patch changes the behavior such that we only
return a narrower class (or NO_REGS) and never return a wider class.
I'll leave this on the list 24h before committing.
/Marcus
2013-10-16 Marcus Shawcroft
* config/aarch64/aarch64.c (aarch64_preferred_reload_class): Adjust
handling of STACK_REG.diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index da3962f..7fce7a0 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -4219,9 +4219,18 @@ aarch64_class_max_nregs (reg_class_t regclass, enum machine_mode mode)
static reg_class_t
aarch64_preferred_reload_class (rtx x, reg_class_t regclass)
{
- if (regclass == POINTER_REGS || regclass == STACK_REG)
+ if (regclass == POINTER_REGS)
return GENERAL_REGS;
+ if (regclass == STACK_REG)
+{
+ if (REG_P(x)
+ && reg_class_subset_p (REGNO_REG_CLASS (REGNO (x)), POINTER_REGS))
+ return regclass;
+
+ return NO_REGS;
+}
+
/* If it's an integer immediate that MOVI can't handle, then
FP_REGS is not an option, so we return NO_REGS instead. */
if (CONST_INT_P (x) && reg_class_subset_p (regclass, FP_REGS)
[AArch64] Classify FRAME_POINTER_REGNUM and ARG_POINTER_REGNUM as POINTER_REGS.
The existing aarch64 implementation of REGNO_REGCLASS classifies the soft frame and arg registers as CORE_REGS. However either could be eliminated against FP or SP, in case of the latter CORE_REGS is too narrow. This patch changes the classification to POINTER_REGS a superset of CORE_REGS that includes SP. Regressed aarch64-none-elf, committed. /Marcus 2013-10-16 Marcus Shawcroft * config/aarch64/aarch64.c (aarch64_regno_regclass): Classify FRAME_POINTER_REGNUM and ARG_POINTER_REGNUM as POINTER_REGS.diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index f6f587a..da3962f 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -3904,7 +3904,7 @@ aarch64_regno_regclass (unsigned regno) if (regno == FRAME_POINTER_REGNUM || regno == ARG_POINTER_REGNUM) -return CORE_REGS; +return POINTER_REGS; if (FP_REGNUM_P (regno)) return FP_LO_REGNUM_P (regno) ? FP_LO_REGS : FP_REGS;
Re: [AArch64] Fix output template for Scalar Neon->Neon register move.
On 16 October 2013 15:58, James Greenhalgh wrote: > > Hi, > > To move a scalar char/short/int around in the vector registers there > is no such instruction as: > dup v0, v0.h[0] > But there is: > dup h0, v0.h[0] > (Alternately there is dup v0.4h, v0.h[0], but I don't think that > is what we are aiming for). > > Fix the output template we are using to reflect this. > > aarch64.exp came back clean and the correct instruction form is > now generated. > > OK? OK /Marcus
Re: [RESEND] Enable building of libatomic on AArch64
On 17 October 2013 10:43, Michael Hudson-Doyle wrote: > Resending as the previous attempt went missing... > > 2013-10-04 Michael Hudson-Doyle > > * libatomic/configure.tgt (aarch64*): Remove code preventing > build. > > * gcc/testsuite/lib/target-supports.exp > (check_effective_target_sync_long_long): AArch64 supports > atomic operations on "long long". > (check_effective_target_sync_long_long_runtime): AArch64 can > execute atomic operations on "long long". > OK, and committed. /Marcus
[AArch64,PATCH] Adjust preferred_reload_class of SP+C
Hi,
This patch addresses an issue in reload triggered by the
gfortran.dg/loc_2.f90 regression test at -O3 with LRA disabled.
The patch is based on work done by Ian Bolton here at ARM which I've
dusted down and submitted.
Following SFP elimination and under heavy register pressure, reload
attempts the reload of SP+offset into a V register. The AArch64
instruction set does not support such an operation.
We considered two solutions to this issue:
1) Detect the SP+offset pattern in secondary reload and use an
intermediate X register.
2) Detect the SP+offset->V pattern inpreferred_reload_class and
return NO_REG before secondary reload gets involved.
The latter looks like a simpler and more intuitive solution to me than
the first. I also note that the i386 backend implementation of
preferred_reload_class contains equivalent code.
I intend to leave this patch on the list for a few days before
committing to give folks knowledgable on reload and the associated
target hooks the opportunity to comment.
Thanks
/Marcus
2013-10-17 Ian Bolton
Marcus Shawcroft
* config/aarch64/aarch64.c (aarch64_preferred_reload_class):
Special case reload SP+C into none GENERAL_REGS.diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index 7fce7a0..cc9ecdd 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -4237,6 +4237,24 @@ aarch64_preferred_reload_class (rtx x, reg_class_t regclass)
&& !aarch64_simd_imm_scalar_p (x, GET_MODE (x)))
return NO_REGS;
+ /* Register eliminiation can result in a request for
+ SP+constant->FP_REGS. We cannot support such operations which
+ use SP as source and an FP_REG as destination, so reject out
+ right now. */
+ if (! reg_class_subset_p (regclass, GENERAL_REGS) && GET_CODE (x) == PLUS)
+{
+ rtx lhs = XEXP (x, 0);
+
+ /* Look through a possible SUBREG introduced by ILP32. */
+ if (GET_CODE (lhs) == SUBREG)
+ lhs = SUBREG_REG (lhs);
+
+ gcc_assert (REG_P (lhs));
+ gcc_assert (reg_class_subset_p (REGNO_REG_CLASS (REGNO (lhs)),
+ POINTER_REGS));
+ return NO_REGS;
+}
+
return regclass;
}
Re: [PATCH][AArch64] Implement %c output template
On 17 October 2013 12:13, Kyrill Tkachov wrote: > [gcc/] > 2013-10-17 Kyrylo Tkachov > > * config/aarch64/aarch64.c (aarch64_print_operand): Handle 'c'. > > [gcc/testsuite] > 2013-10-17 Kyrylo Tkachov > > * gcc.target/aarch64/c-output-template.c: New testcase. > * gcc.target/aarch64/c-output-template-2.c: Likewise. > * gcc.target/aarch64/c-output-template-3.c: Likewise. OK /Marcus
Re: [AArch64] Fix types for vcvt_n intrinsics.
On 17 October 2013 17:27, James Greenhalgh wrote: > > Hi, > > I spotted that the types of arguments to these intrinsics are wrong, > which results in all sorts of fun issues! > > Fixed thusly, regression tested with aarch64.exp on aarch64-none-elf > with no issues. > > OK? > > Thanks, > James > > --- > 2013-10-17 James Greenhalgh > > * config/aarch64/arm_neon.h > (vcvt_n_<32,64>_<32,64>): Correct argument types. OK /Marcus
Re: [PATCH][AArch64] Get %c output template tests to pass for -fPIC
On 21 October 2013 09:41, Kyrill Tkachov wrote: > [gcc/testsuite] > 2013-10-21 Kyrylo Tkachov > > * gcc.target/aarch64/c-output-mod-2.c: Fix for -fPIC. > * gcc.target/aarch64/c-output-mod-3.c: Likewise. OK /Marcus
Re: [PATCH v2] Fix libgfortran cross compile configury w.r.t newlib
On 15 October 2013 22:35, Mike Stump wrote: > Would be nice for a build/config person to weigh in or to upgrade and make > bullet proof the system against such failures. My take, by default, the > compile line should do something useful, and that should be enough for > autoconf style tests to smell the library. Now, we can observe that Steve's > mips-mti-elf newlib port apparently violates that, but it is lost on me why > that is and why that is a good thing. Steve? Is there some reason why by > default, a suitable linker script can't be added by the compiler, or, if none > suitable, a stub one that isn't suitable in general, but, is complete enough > to allow autoconf to function normally? Steve, Can your build be fixed allowing us to back out: http://gcc.gnu.org/ml/fortran/2013-06/msg00038.html ? I'd really like to make some progress on this, while my proposed patch does resolve the regression introduced by the above patch I am concerned that this is going in the wrong direction and that we should, as Mike suggests above fix the build issue such that autoconf behaves, rather than attempting to hardwire configure details of newlib into libgfortran... /Marcus
Re: [Patch AArch64] Use software sqrt expansion always for -mlow-precision-recip-sqrt
On 11 January 2016 at 11:53, James Greenhalgh wrote: > > --- > 2015-12-10 James Greenhalgh > > * config/aarch64/aarch64.c (use_rsqrt_p): Always use software > reciprocal sqrt for -mlow-precision-recip-sqrt. > OK /Marcus
Re: [Patch AArch64] GCC 6 regression in vector performance. - Fix vector initialization to happen with lane load instructions.
On 20 January 2016 at 15:22, James Greenhalgh wrote: > gcc/ > > 2016-01-20 James Greenhalgh > Ramana Radhakrishnan > > * config/aarch64/aarch64.c (aarch64_expand_vector_init): Refactor, > always use lane loads to construct non-constant vectors. > > gcc/testsuite/ > > 2016-01-20 James Greenhalgh > Ramana Radhakrishnan > > * gcc.target/aarch64/vector_initialization_nostack.c: New. > OK /Marcus
Re: [Patch AArch64] Restrict 16-bit sqrdml{sa}h instructions to FP_LO_REGS
On 26 January 2016 at 16:04, James Greenhalgh wrote: > 2016-01-25 James Greenhalgh > > * config/aarch64/aarch64.md > (arch64_sqrdmlh_lane): Fix register > constraints for operand 3. > (aarch64_sqrdmlh_laneq): Likewise. > OK /Marcus
Re: [AArch64] Remove AARCH64_EXTRA_TUNE_RECIP_SQRT from Cortex-A57 tuning
On 11 January 2016 at 12:04, James Greenhalgh wrote: > 2015-12-11 James Greenhalgh > > * config/aarch64/aarch64.c (cortexa57_tunings): Remove > AARCH64_EXTRA_TUNE_RECIP_SQRT. > OK /Marcus
Re: [patch] introduce aarch64 as a Go architecture
On 1 December 2013 19:55, Michael Hudson-Doyle wrote: > Ian Lance Taylor writes: > >> I've gotten a patch from Michael Hudson-Doyle to set GOARCH to arm64 >> on an Aarch64 system (https://codereview.appspot.com/34830045/). > > Haha, go us. > >> I've gotten a patch from Matthias Klose to set GOARCH to aarch64 on >> such a system >> (http://gcc.gnu.org/ml/gcc-patches/2013-11/msg03765.html). >> >> I don't care one way or another myself, but we need to pick one. > > I don't care too much myself. AArch64 is more correct but arm64 is more > obvious. Also plan9/inferno will use arm64 IIUC. All the documentation relevant to this architecture uses the term "aarch64". How is arm64 obvious? /Marcus
Re: patch for elimination to SP when it is changed in RTL (PR57293)
On 2 December 2013 23:44, Vladimir Makarov wrote: > If somebody with the rights approves, I can commit it tomorrow. > > 2013-12-02 Vladimir Makarov > > * config/aarch64/aarch64.c (aarch64_frame_pointer_required): Check > LR_REGNUM. > (aarch64_can_eliminate): Don't check elimination source when > frame_pointer_requred is false. > This is fine with me, go ahead and commit it. Thanks /Marcus
Re: [PATCH/AARCH64 4/6] Implement the trap pattern
Hi On 3 December 2013 21:24, Andrew Pinski wrote: > +(define_insn "trap" > + [(trap_if (const_int 1) (const_int 8))] > + "" > + "brk #1000") Please add a type attribute to the pattern. The type attributes are now shared between arm and aarch64 backends.You should use the type value introduced by this patch: http://gcc.gnu.org/ml/gcc-patches/2013-12/msg00374.html OK with this change. Thanks /Marcus
Re: [PATCH/AARCH64 3/6] Fix up multi-lib options
On 3 December 2013 21:24, Andrew Pinski wrote: > * config/aarch64/t-aarch64 (MULTILIB_OPTIONS): Fix definition so > that options are conflicting ones. Looks fine to me, commit it. /Marcus
Re: [Patch, AArch64] [1/6] Implement support for Crypto -- Define TARGET_CRYPTO.
On 6 December 2013 17:35, Tejas Belagod wrote: > 2013-12-06 Tejas Belagod > > * config/aarch64/aarch64.h (TARGET_CRYPTO): New. > (__ARM_FEATURE_CRYPTO): Define if TARGET_CRYPTO is true. OK, but don;t apply until the rest of this patch series is approved. /Marcus
Re: [Patch, AArch64] [2/6] Implement support for Crypto -- Instruction types.
On 6 December 2013 17:35, Tejas Belagod wrote: > * config/arm/types.md (neon_mul_d_long, crypto_aes, crypto_sha1_xor, > crypto_sha1_fast, crypto_sha1_slow, crypto_sha256_fast, > crypto_sha256_slow): New. Looks ok to me, but get an ack from Ramana. Note that part of this patch duplicates the crypto* types from Kyrill's patch set also under review. Both sets look identical to me so whoever commits second will need to update their patch. /Marcus
Re: [Patch, AArch64] [3/6] Implement support for Crypto -- AES.
On 6 December 2013 17:36, Tejas Belagod wrote:
> * gcc.target/aarch64/aes.c: New.
Add _1 on the test case file name (see http://gcc.gnu.org/wiki/TestCaseWriting)
> diff --git a/gcc/config/aarch64/arm_neon.h b/gcc/config/aarch64/arm_neon.h
> index dc56170..9f35e09 100644
> --- a/gcc/config/aarch64/arm_neon.h
> +++ b/gcc/config/aarch64/arm_neon.h
> @@ -15793,6 +15793,42 @@ vaddvq_f64 (float64x2_t __a)
>return vgetq_lane_f64 (__t, __LANE0 (2));
> }
>
> +#ifdef __ARM_FEATURE_CRYPTO
> +
> +/* vaes */
> +
> +static __inline uint8x16_t
> +vaeseq_u8 (uint8x16_t data, uint8x16_t key)
> +{
> + return
> +(uint8x16_t) __builtin_aarch64_crypto_aesev16qi ((int8x16_t) data,
> +(int8x16_t) key);
James G fixed the infrastructure to allow properly typed builtins, see:
http://gcc.gnu.org/ml/gcc-patches/2013-11/msg02005.html
and
http://gcc.gnu.org/ml/gcc-patches/2013-11/msg02880.html
> @@ -959,3 +966,7 @@
> (UNSPEC_UZP1 "1") (UNSPEC_UZP2 "2")])
>
> (define_int_attr frecp_suffix [(UNSPEC_FRECPE "e") (UNSPEC_FRECPX "x")])
> +
> +(define_int_attr aes_op [(UNSPEC_AESE "e") (UNSPEC_AESD "d")])
> +(define_int_attr aesmc_op [(UNSPEC_AESMC "mc") (UNSPEC_AESIMC "imc")])
> +
Superflous trailing blank line.
> diff --git a/gcc/testsuite/gcc.target/aarch64/aes.c
> b/gcc/testsuite/gcc.target/aarch64/aes.c
> new file mode 100644
> index 000..82665fa
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/aes.c
> @@ -0,0 +1,40 @@
> +
> +/* { dg-do compile } */
> +/* { dg-options "-march=armv8-a+crypto" } */
> +
> +#include "arm_neon.h"
> +
> +uint8x16_t
> +test_vaeseq_u8 (uint8x16_t data, uint8x16_t key)
> +{
> + return vaeseq_u8 (data, key);
> +}
> +
> +/* { dg-final { scan-assembler "aese\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b" } }
Use scan-assembler-times 1 instead please.
Thanks
/Marcus
Re: [Patch, AArch64] [4/6] Implement support for Crypto -- SHA1.
Same comments as previous patch:
On 6 December 2013 17:36, Tejas Belagod wrote:
> testsuite/
> * gcc.target/aarch64/sha1.c: New.
Add _1 on the test case file name (see http://gcc.gnu.org/wiki/TestCaseWriting)
> +static __inline uint32x4_t
> +vsha1cq_u32 (uint32x4_t hash_abcd, uint32_t hash_e, uint32x4_t wk)
> +{
> + return
> +(uint32x4_t) __builtin_aarch64_crypto_sha1cv4si ((int32x4_t) hash_abcd,
> +(int32_t) hash_e,
> +(int32x4_t) wk);
> +}
James G fixed the infrastructure to allow properly typed builtins, see:
http://gcc.gnu.org/ml/gcc-patches/2013-11/msg02005.html
and
http://gcc.gnu.org/ml/gcc-patches/2013-11/msg02880.html
> +/* { dg-final { scan-assembler "sha1c\\tq" } } */
Use scan-assembler-times 1
Cheers
/Marcus
Re: [Patch, AArch64] [5/6] Implement support for Crypto -- SHA256.
On 6 December 2013 17:36, Tejas Belagod wrote: > > Hi, > > The attached patch implements support for crypto sha256. Same comments as previous crypto patch. /Marcus
Re: [PATCH/AARCH64 1/6] Fix size and pointer different types for ILP32.
On 3 December 2013 21:24, Andrew Pinski wrote:
>
> While compiling some programs, GCC and glibc (and newlib)'s definitions of
> size_t
> were not agreeing and causing format warnings to happen. The simple testcase
> for this is:
> #include
> #include
>
> int main(void)
> {
> ssize_t t = 0x1;
> printf("%zd\n", t);
> return 0;
> }
Hi Andrew,
The PCS IHI0056C defines SIZE_TYPE as 'unsigned long' for both ILP32
and LP64 and PTRDIFF_TYPE as "signed long" for both ILP32 and LP64.
This seems like a sane choice to me.
Trying to recreate the failure with the test fragment above doesn't
given a warning:
$ aarch64-none-elf-gcc -Wall -mabi=ilp32 test-size_t.c -specs=rdimon.specs
$ aarch64-none-linux-gnu-gcc -Wall -mabi=ilp32 test-size_t.c -c
$
..what am I doing differently to your test run?
Cheers
/Marcus
Re: [PATCH/AARCH64 6/6] Support ILP32 multi-lib
Hi,
On 10 December 2013 01:52, Andrew Pinski wrote:
> On Mon, Dec 9, 2013 at 12:12 PM, Yufeng Zhang wrote:
>> To be more explicit and consistent, the name of the ILP32 loader shall have
>> 'ilp32' instead of '32'. The extension field shall be appended to
>> 'aarch64', separated by '_', and we should probably add the big-endian name
>> at the same time. With the extension fields sorted alphabetically,
>> GLIBC_DYNAMIC_LINKER can be defined as:
>> "/lib/ld-linux-aarch64%{mbig-endian:_be}%{mabi=ilp32:_ilp32}.so.1"
> AS mentioned in another email I think _be is incorrect. I also think
There was recent discussion on this topic over here:
http://lists.linaro.org/pipermail/cross-distro/2013-November/000570.html
> aarch64 becomes redundant for _ilp32 and really it should be just:
> "/lib/ld-linux-%{mabi=ilp32:ilp32;:aarch64}.so.
Stick with: /lib/ld-linux-.so. as outlined in Yufeng's reply.
Cheers
/Marcus
Re: AARCH64 configure check for gas -mabi support
On 10/12/13 20:23, Kugan wrote: gcc/ +2013-12-11 Kugan Vivekanandarajah + * configure.ac: Add check for aarch64 assembler -mabi support. + * configure: Regenerate. + * config.in: Regenerate. + * config/aarch64/aarch64-elf.h (ASM_MABI_SPEC): New define. + (ASM_SPEC): Update to substitute -mabi with ASM_MABI_SPEC. + * config/aarch64/aarch64.h (aarch64_override_options): Issue error if + assembler does not support -mabi and option ilp32 is selected. + * doc/install.texi: Added note that building gcc 4.9 and after with pre + 2.24 binutils will not support -mabi=ilp32. + Kugan, Thanks for sorting this out. OK to commit. /Marcus
Re: [AArch64 2/3 big.LITTLE] Allow tuning parameters without unique tuning targets.
On 18 December 2013 12:23, James Greenhalgh wrote: > 2013-12-18 James Greenhalgh > > * config/aarch64/aarch64-cores.def: Add new column for > SCHEDULER_IDENT. > * config/aarch64/aarch64-opts.h (AARCH64_CORE): Handle > SCHEDULER_IDENT. > * config/aarch64/aarch64.c (AARCH64_CORE): Handle > SCHEDULER_IDENT. > (aarch64_parse_cpu): mcpu implies a default value for mtune. > * config/aarch64/aarch64.h (AARCH64_CORE): Handle > SCHEDULER_IDENT. OK /Marcus
Re: [AArch64 1/3 big.LITTLE] Driver rewriting of big.LITTLE names.
On 18 December 2013 12:23, James Greenhalgh wrote: > 2013-12-18 James Greenhalgh > > * common/config/aarch64/aarch64-common.c > (aarch64_rewrite_selected_cpu): New. > (aarch64_rewrite_mcpu): New. > * config/aarch64/aarch64-protos.h > (aarch64_rewrite_selected_cpu): New. > * config/aarch64/aarch64.h (BIG_LITTLE_SPEC): New. > (BIG_LITTLE_SPEC_FUNCTIONS): Likewise. > (ASM_CPU_SPEC): Likewise. > (EXTRA_SPEC_FUNCTIONS): Likewise. > (EXTRA_SPECS): Likewise. > (ASM_SPEC): Likewise. > * config/aarch64/aarch64.c (aarch64_start_file): Rewrite target > CPU name. OK /Marcus
Re: [AArch64 3/3 big.LITTLE] Add support for -mcpu=cortex-a57.cortex-a53
On 18 December 2013 12:23, James Greenhalgh wrote: > 2013-12-18 James Greenhalgh > > * config/aarch64/aarch64-cores.def: Add support for > -mcpu=cortex-a57.cortex-a53. > * config/aarch64/aarch64-tune.md: Regenerate. > * doc/invoke.texi: Document -mcpu=cortex-a57.cortex-a53. OK /Marcus
Re: [Patch, AArch64] [3/6] Implement support for Crypto -- AES.
On 18 December 2013 15:28, Tejas Belagod wrote: > 2013-12-18 Tejas Belagod > > > gcc/ > * config/aarch64/aarch64-simd-builtins.def: Update builtins table. > * config/aarch64/aarch64-builtins.c > (aarch64_types_binopu_qualifiers, > TYPES_BINOPU): New. > > * config/aarch64/aarch64-simd.md (aarch64_crypto_aesv16qi, > aarch64_crypto_aesv16qi): New. > * config/aarch64/arm_neon.h (vaeseq_u8, vaesdq_u8, vaesmcq_u8, > vaesimcq_u8): New. > * config/aarch64/iterators.md (UNSPEC_AESE, UNSPEC_AESD, > UNSPEC_AESMC, > UNSPEC_AESIMC): New. > (CRYPTO_AES, CRYPTO_AESMC): New int iterators. > (aes_op, aesmc_op): New int attributes. > > testsuite/ > * gcc.target/aarch64/aes_1.c: New. OK, Thanks /Marcus
Re: [Patch, AArch64] [4/6] Implement support for Crypto -- SHA1.
On 18 December 2013 15:28, Tejas Belagod wrote: > 2013-12-18 Tejas Belagod > > gcc/ > * config/aarch64/aarch64-simd-builtins.def: Update builtins table. > * config/aarch64/aarch64-builtins.c > (aarch64_types_ternopu_qualifiers, > TYPES_TERNOPU): New. > > * config/aarch64/aarch64-simd.md (aarch64_crypto_sha1hsi, > aarch64_crypto_sha1su1v4si, aarch64_crypto_sha1v4si, > aarch64_crypto_sha1su0v4si): New. > * config/aarch64/arm_neon.h (vsha1cq_u32, sha1mq_u32, vsha1pq_u32, > vsha1h_u32, vsha1su0q_u32, vsha1su1q_u32): New. > * config/aarch64/iterators.md (UNSPEC_SHA1, > UNSPEC_SHA1SU<01>): > New. > (CRYPTO_SHA1): New int iterator. > (sha1_op): New int attribute. > > testsuite/ > * gcc.target/aarch64/sha1_1.c: New. OK, thanks /Marcus
Re: [Patch, AArch64] [5/6] Implement support for Crypto -- SHA256.
On 18 December 2013 15:28, Tejas Belagod wrote: > 2013-12-18 Tejas Belagod > > > gcc/ > * config/aarch64/aarch64-simd-builtins.def: Update builtins table. > * config/aarch64/aarch64-simd.md > (aarch64_crypto_sha256hv4si, > aarch64_crypto_sha256su0v4si, aarch64_crypto_sha256su1v4si): New. > * config/aarch64/arm_neon.h (vsha256hq_u32, vsha256h2q_u32, > vsha256su0q_u32, vsha256su1q_u32): New. > * config/aarch64/iterators.md (UNSPEC_SHA256H<2>, > UNSPEC_SHA256SU<01>): > New. > (CRYPTO_SHA256): New int iterator. > (sha256_op): New int attribute. > > testsuite/ > * gcc.target/aarch64/sha256_1.c: New. OK /Marcus
Re: [Patch, AArch64] [6/6] Implement support for Crypto -- PMULL.64.
On 18 December 2013 15:28, Tejas Belagod wrote: >> 2013-12-06 Tejas Belagod >> >> gcc/ >> * config/aarch64/aarch64-builtins.c: Define builtin types for >> poly64_t >> poly128_t. >> * aarch64/aarch64-simd-builtins.def: Update builtins table. >> * config/aarch64/aarch64-simd.md (aarch64_crypto_pmulldi, >> aarch64_crypto_pmullv2di): New. >> * config/aarch64/aarch64.c (aarch64_simd_mangle_map): Update table >> for >> poly64x2_t mangler. >> * config/aarch64/arm_neon.h (poly64x2_t, poly64_t, poly128_t): >> Define. >> (vmull_p64, vmull_high_p64): New. >> * config/aarch64/iterators.md (UNSPEC_PMULL<2>): New. >> >> testsuite/ >> >> * gcc.target/aarch64/pmull.c: New. OK /Marcus
[AArch64] Define BE loader name.
Hi,
This patch defines the AArch64 BE loader name. Corresponding patches
for glibc and binutils have been posted on the relevant lists.
/Marcus
* config/aarch64/aarch64-linux.h (GLIBC_DYNAMIC_LINKER): Expand
loader
name using mbig-endian.
(LINUX_TARGET_LINK_SPEC): Pass linker -m flag.diff --git a/gcc/config/aarch64/aarch64-linux.h
b/gcc/config/aarch64/aarch64-linux.h
index 15272b8..a8f0771 100644
--- a/gcc/config/aarch64/aarch64-linux.h
+++ b/gcc/config/aarch64/aarch64-linux.h
@@ -21,7 +21,7 @@
#ifndef GCC_AARCH64_LINUX_H
#define GCC_AARCH64_LINUX_H
-#define GLIBC_DYNAMIC_LINKER "/lib/ld-linux-aarch64.so.1"
+#define GLIBC_DYNAMIC_LINKER "/lib/ld-linux-aarch64%{mbig-endian:_be}.so.1"
#define CPP_SPEC "%{pthread:-D_REENTRANT}"
@@ -32,7 +32,8 @@
%{rdynamic:-export-dynamic} \
-dynamic-linker " GNU_USER_DYNAMIC_LINKER " \
-X \
- %{mbig-endian:-EB} %{mlittle-endian:-EL}"
+ %{mbig-endian:-EB} %{mlittle-endian:-EL} \
+ -maarch64linux%{mbig-endian:b}"
#define LINK_SPEC LINUX_TARGET_LINK_SPEC
Re: [AArch64] big.LITTLE option rewriting bug
On 07/01/14 17:02, James Greenhalgh wrote: Ugh. Now we have two ASM_SPECs which try to handle -mcpu as input. One of them just returns the input, the other does the cpu rewriting we actually want, so we can end up with: gcc -mcpu=cortex-a57.cortex-a53 Getting passed through to the assembler as: as -mcpu=cortex-a57 -mcpu=cortex-a57.cortex-a53 Which is obviously broken. This patch removes the identity spec, the rewriting one will return identity for non-big.LITTLE names anyway. Checked with all the valid values of -mcpu to ensure that the right thing is passed through to the assembler. Also sanity checked with aarch64.exp. Ugh, and sorry, this was clumsy on my part. OK for trunk? Thanks, James --- gcc/ * config/aarch64/aarch64-elf.h (ASM_SPEC): Remove identity spec for -mcpu. OK /Marcus
Re: [PATCH, AArch64] Use llfloor and llceil for vcvtmd_s64_f64 and vcvtpd_s64_f64 in arm_neon.h
On 6 January 2014 12:30, Yufeng Zhang wrote: > This patch fixes the implementation of vcvtmd_s64_f64 and vcvtpd_s64_f64 in > arm_neon.h to use llfloor and llceil instead, which are ILP32-friendly. > > This patch will fix the following test failure in the ILP32 mode: > > FAIL: gcc.target/aarch64/vect-vcvt.c scan-assembler fcvtms\\tx[0-9]+, > d[0-9]+ > > OK for the trunk? OK, but we should wait for stage-1 now. Thanks /Marcus
Re: [PATCH/AARCH64] Fix register cost for moving to/from stack registers
On 15 January 2014 00:09, Andrew Pinski wrote: > ChangeLog: > * config/aarch64/aarch64.c (aarch64_register_move_cost): Correct cost > of moving from/to the STACK_REG register class. + /* Moving between GPR and stack cost is the same as GP2GP. */ Don't forget the double space after period. Otherwise, this is OK, thanks. /Marcus
Re: [AArch64][1/2] Mark GOT related MEM rtx as const to help RTL loop IV
On 7 July 2015 at 13:33, Jiong Wang wrote: > 2015-07-06 Jiong Wang > > gcc/ > * config/aarch64/aarch64.c (aarch64_load_symref_appropriately): Mark mem as > READONLY and NOTRAP for PIC symbol. > > gcc/testsuite/ > * gcc.target/aarch64/got_mem_hoist.c: New test. Looks, OK to me. Follow the guidance on the wiki here https://gcc.gnu.org/wiki/TestCaseWriting when naming new test cases and add _1 suffix. Otherwise OK. /Marcus
Re: [PATCH][AArch64][8/14] Implement TARGET_OPTION_VALID_ATTRIBUTE_P
On 21 July 2015 at 16:37, James Greenhalgh wrote:
> On Thu, Jul 16, 2015 at 04:20:59PM +0100, Kyrill Tkachov wrote:
>> +static bool
>> +aarch64_process_one_target_attr (char *arg_str, const char* pragma_or_attr)
>> +{
>> + bool ret;
>> + bool invert = false;
>> +
>> + int len = strlen (arg_str);
>> +
>> + if (len == 0)
>> +{
>> + error ("malformed target %s", pragma_or_attr);
>> + return false;
>> +}
>> +
>> + char *str_to_check = (char *) alloca (len + 1);
>
> Seems to go against your approach earlier in the patch series of XSTRDUP,
> it would be nice to stay consistent.
Agreed, we should be consistent. Each of the other instances of
alloca/xstrdup that I've seen in this patch series are actually
superflous, we simply copy the string, use it then bin it, better to
remove the dup completely.
In the choice between xstrdup() and alloca(), since alloca() is an
option, better to choose alloca() and remove the need for each of the
explicit free() calls in the exit paths. The alloca() route makes it
less likely that we accidentally introduce a space leak in the future.
Cheers
/Marcus
Re: [PATCH][AArch64] Fix LINUX_TARGET_LINK_SPEC to be consistent with ARM
On 22 July 2015 at 18:13, Szabolcs Nagy wrote:
> Same as
> https://gcc.gnu.org/ml/gcc-patches/2015-04/msg01387.html
> but for AArch64.
>
> -dynamic-linker is only passed to the linker if !static && !shared.
>
> -rdynamic handling is changed too to be consistent with arm:
> only pass -export-dynamic if !static.
>
> 2015-07-22 Szabolcs Nagy
>
> PR target/65711
> * config/aarch64/aarch64-linux.h (LINUX_TARGET_LINK_SPEC): Move
> -dynamic-linker within %{!static %{!shared, and -rdynamic within
> %{!static.
OK and I think we should backport this to 5 and 4.9
Cheers
/Marcus
Re: [PATCH][AArch64] elf toolchain does not pass -shared linker option
On 22 July 2015 at 18:22, Szabolcs Nagy wrote: > 2015-07-22 Szabolcs Nagy > > * config/aarch64/aarch64-elf-raw.h (LINK_SPEC): Handle -h, -static, > -shared, -symbolic, -rdynamic. OK, this should be back ported to 5 and 4.9 aswell. Thanks /Marcus
Re: [AArch64] Implement copysign[ds]f3
On 16 September 2015 at 08:40, James Greenhalgh wrote: > > Hi, > > This patch adds expanders for copysigndf3 and copysignsf3 to the AArch64 > backend. These use the BSL/BIT/BIF insn to save us from the default > expansion pattern. > > Bootstrapped on aarch64-none-linux-gnu with no issues, and checked > the performance to show a slight improvement to FP routines using > copysign or SIGN from fortran. > > OK? > > Thanks, > James > > --- > gcc/ > > 2015-09-16 James Greenhalgh > > * config/aarch64/aarch64.md (copysigndf3): New. > (copysignsf3): Likewise. > > gcc/testsuite/ > > 2015-09-16 James Greenhalgh > > * gcc.target/aarch64/copysign_1.c: New. > * gcc.target/aarch64/copysign_2.c: New. > OK /Marcus
Re: [PATCH] 2015-09-03 Benedikt Huber Philipp Tomsich
Hi,
Thanks for your work on this. There are a bunch of predominantly
style nits in line below. My none nit comments on this patch are:
This should be left turned off for all cores where we have not seen
benchmark numbers to indicate that this optimization is a benefit, we
can take patches for each core in the future once numbers are
available.
Given the absence of numbers for some of the cores and the significant
impact on one core this should remain disabled by default on generic.
We don't necessarily want a proliferation of user orientated tuning
options without good reason, instead the per core default tuning
behaviour should make the right choice per core, hence I think -mrecip
should be dropped. We already have the -moverride= mechanism to
provide a developer orientated mechanism to override the per core
tuning flag.
Further comments inline
Thanks
/Marcus
On 7 September 2015 at 11:40, Benedikt Huber
wrote:
--- a/gcc/config/aarch64/aarch64-tuning-flags.def
+++ b/gcc/config/aarch64/aarch64-tuning-flags.def
@@ -29,4 +29,5 @@
AARCH64_TUNE_ to give an enum name. */
AARCH64_EXTRA_TUNING_OPTION ("rename_fma_regs", RENAME_FMA_REGS)
+AARCH64_EXTRA_TUNING_OPTION ("mrecip_default_enabled", MRECIP_DEFAULT_ENABLED)
This name is exposed via the -moverride=tune= option, perhaps a
better name would be:
+AARCH64_EXTRA_TUNING_OPTION ("recip_sqrt", RECIP_SQRT)
> +/* Add builtins for reciprocal square root. */
> +void
> +aarch64_add_builtin_rsqrt (void)
> +{
> + tree fndecl = NULL;
> + tree ftype = NULL;
> +
> + tree V2SF_type_node = build_vector_type (float_type_node, 2);
> + tree V2DF_type_node = build_vector_type (double_type_node, 2);
> + tree V4SF_type_node = build_vector_type (float_type_node, 4);
> +
> + ftype = build_function_type_list (double_type_node, double_type_node,
> NULL_TREE);
Line length exceeds 80 characters.
> + fndecl = add_builtin_function ("__builtin_aarch64_rsqrt_df",
> +ftype, AARCH64_BUILTIN_RSQRT_DF, BUILT_IN_MD, NULL, NULL_TREE);
> + aarch64_builtin_decls[AARCH64_BUILTIN_RSQRT_DF] = fndecl;
> +
> + ftype = build_function_type_list (float_type_node, float_type_node,
> NULL_TREE);
Line length exceeds 80 characters.
> +/* Function to expand reciprocal square root builtins. */
> +static rtx
> +aarch64_expand_builtin_rsqrt (int fcode, tree exp, rtx target)
> +{
> + rtx pat;
> + tree arg0 = CALL_EXPR_ARG (exp, 0);
> + rtx op0 = expand_normal (arg0);
> +
> + enum insn_code c;
> +
> + switch (fcode)
> +{
> + case AARCH64_BUILTIN_RSQRT_DF:
> +c = CODE_FOR_rsqrt_df2; break;
Leading blocks of 8 spaces should be TAB's, likewise the rest of the patch.
> +/* Return builtin for reciprocal square root. */
> +tree
> +aarch64_builtin_rsqrt (unsigned int fn, bool md_fn)
Blank line between function comments and function, likewise through
the rest of the patch please.
> diff --git a/gcc/config/aarch64/aarch64-opts.h
> b/gcc/config/aarch64/aarch64-opts.h
> index bf6bb7b..f8e79cb 100644
> --- a/gcc/config/aarch64/aarch64-opts.h
> +++ b/gcc/config/aarch64/aarch64-opts.h
> @@ -73,4 +73,11 @@ enum aarch64_code_model {
>AARCH64_CMODEL_LARGE
> };
>
> +/* Each core can have -mrecip enabled or disabled by default. */
> +enum aarch64_mrecip {
{ on new line please.
> + AARCH64_MRECIP_OFF = 0,
> + AARCH64_MRECIP_ON,
> + AARCH64_MRECIP_DEFAULT,
Trailing , will give a "comma at end of enumerator list" warning every
time this file is included, drop the comma please.
> +/* Function to decide when to use
> + * reciprocal square root builtins. */
Drop the leading * on follow on comment lines, here and elsewhere in
the patch please.
> +/* Select reciprocal square root initial estimate
> + * insn depending on machine mode. */
> +rsqrte_type get_rsqrte_type (enum machine_mode mode)
New line between type and function name please, likewise for other
instance in this patch.
> + for (int i = 0; i < iterations; ++i)
> +{
> + rtx x1 = gen_reg_rtx (mode);
> + rtx x2 = gen_reg_rtx (mode);
> + rtx x3 = gen_reg_rtx (mode);
> + emit_set_insn (x2, gen_rtx_MULT (mode, x0, x0));
> +
> + emit_insn ((*get_rsqrts_type (mode)) (x3, xsrc, x2));
> +
> + emit_set_insn (x1, gen_rtx_MULT (mode, x0, x3));
> + x0 = x1;
> +}
> +
> + emit_move_insn (dst, x0);
> + return;
Superflous return, drop it please.
> +#undef TARGET_BUILTIN_RECIPROCAL
> +#define TARGET_BUILTIN_RECIPROCAL aarch64_builtin_reciprocal
> +
The rest of these TARGET_* defines are in alphabetical order, please
insert the new one in order.
> diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
> +
> +mlow-precision-recip-sqrt
> +Common Var(flag_mrecip_low_precision_sqrt) Optimization
> +Run fewer approximation steps to reduce latency and precision.
> diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
> +@item -mlow-precision-recip-sqrt
> +@item -mno-low-precision-recip-sqrt
> +@opindex -mlow-precision-recip-sqrt
> +@opindex -mn
