Re: [PINGv3][PATCH] Fix for PR 61561
Thank you. $ svn commit Sendinggcc/ChangeLog Sendinggcc/config/arm/thumb1.md Sendinggcc/config/arm/thumb2.md Transmitting file data ... Committed revision 213695. P.S. Minor nit was reg. tested. On 08/06/2014 06:44 PM, Richard Earnshaw wrote: On 06/08/14 15:14, Ramana Radhakrishnan wrote: This is OK thanks. Ramana Hmm, minor nit. (define_insn "*thumb1_movhi_insn" [(set (match_operand:HI 0 "nonimmediate_operand" "=l,l,m,*r,*h,l") - (match_operand:HI 1 "general_operand" "l,m,l,*h,*r,I"))] + (match_operand:HI 1 "general_operand" "lk,m,l,*h,*r,I"))] This would be better expressed as: [(set (match_operand:HI 0 "nonimmediate_operand" "=l,l,m,l*r,*h,l") (match_operand:HI 1 "general_operand" "l,m,l,k*h,*r,I"))] that is, to use the 4th alternative. That's because the use of SP in these operations does not clobber the flags. Similarly for the movqi pattern. R.
Re: [PINGv3][PATCH] Fix for PR 61561
--Marat On 08/07/2014 12:00 PM, Ramana Radhakrishnan wrote: On Thu, Aug 7, 2014 at 8:36 AM, Marat Zakirov wrote: Thank you. $ svn commit Sendinggcc/ChangeLog Sendinggcc/config/arm/thumb1.md Sendinggcc/config/arm/thumb2.md Transmitting file data ... Committed revision 213695. P.S. Minor nit was reg. tested. Another minor nit - please send the patch you committed to be archived on the mailing list. regards Ramana On 08/06/2014 06:44 PM, Richard Earnshaw wrote: On 06/08/14 15:14, Ramana Radhakrishnan wrote: This is OK thanks. Ramana Hmm, minor nit. (define_insn "*thumb1_movhi_insn" [(set (match_operand:HI 0 "nonimmediate_operand" "=l,l,m,*r,*h,l") - (match_operand:HI 1 "general_operand" "l,m,l,*h,*r,I"))] + (match_operand:HI 1 "general_operand" "lk,m,l,*h,*r,I"))] This would be better expressed as: [(set (match_operand:HI 0 "nonimmediate_operand" "=l,l,m,l*r,*h,l") (match_operand:HI 1 "general_operand" "l,m,l,k*h,*r,I"))] that is, to use the 4th alternative. That's because the use of SP in these operations does not clobber the flags. Similarly for the movqi pattern. R. gcc/ChangeLog: 2014-08-07 Marat Zakirov * config/arm/thumb1.md (*thumb1_movhi_insn): Handle stack pointer. (*thumb1_movqi_insn): Likewise. * config/arm/thumb2.md (*thumb2_movhi_insn): Likewise. diff --git a/gcc/config/arm/thumb1.md b/gcc/config/arm/thumb1.md index cd1adf4..fed741e 100644 --- a/gcc/config/arm/thumb1.md +++ b/gcc/config/arm/thumb1.md @@ -707,8 +707,8 @@ ) (define_insn "*thumb1_movhi_insn" - [(set (match_operand:HI 0 "nonimmediate_operand" "=l,l,m,*r,*h,l") - (match_operand:HI 1 "general_operand" "l,m,l,*h,*r,I"))] + [(set (match_operand:HI 0 "nonimmediate_operand" "=l,l,m,l*r,*h,l") + (match_operand:HI 1 "general_operand" "l,m,l,k*h,*r,I"))] "TARGET_THUMB1 && ( register_operand (operands[0], HImode) || register_operand (operands[1], HImode))" @@ -762,7 +762,7 @@ (define_insn "*thumb1_movqi_insn" [(set (match_operand:QI 0 "nonimmediate_operand" "=l,l,m,*r,*h,l") - (match_operand:QI 1 "general_operand" "l, m,l,*h,*r,I"))] + (match_operand:QI 1 "general_operand" "lk, m,l,*h,*r,I"))] "TARGET_THUMB1 && ( register_operand (operands[0], QImode) || register_operand (operands[1], QImode))" diff --git a/gcc/config/arm/thumb2.md b/gcc/config/arm/thumb2.md index 029a679..983b59d 100644 --- a/gcc/config/arm/thumb2.md +++ b/gcc/config/arm/thumb2.md @@ -318,7 +318,7 @@ ;; of the messiness associated with the ARM patterns. (define_insn "*thumb2_movhi_insn" [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,l,r,m,r") - (match_operand:HI 1 "general_operand" "r,I,Py,n,r,m"))] + (match_operand:HI 1 "general_operand" "rk,I,Py,n,r,m"))] "TARGET_THUMB2 && (register_operand (operands[0], HImode) || register_operand (operands[1], HImode))"
[PINGv2][PATCHv3] Fix vector tests on ARM platforms with disabled unaligned accesses
On 07/31/2014 04:08 PM, Marat Zakirov wrote:
On 07/24/2014 07:40 PM, Marat Zakirov wrote:
On 07/24/2014 04:27 PM, Marat Zakirov wrote:
On 07/23/2014 06:23 PM, Marat Zakirov wrote:
Hi there!
I made a patch which fixes regressions on ARM platforms with
disabled unaligned accesses. The problem is that
'arm_vect_no_misalign' predicate do not check 'unaligned_access'
global variable to determine whether unaligned access to vector are
allowed. This leads to spurious vect.exp test fails when GCC is
configured --with-specs=%{!munaligned-access:-mno-unaligned-access}.
Attached patch fixes ARM predicate and several tests to correctly
handle the issue.
The following targets were reg. tested for multiple targets (ARM,
Thumb-1, Thumb-2, x86, x86_64) with and without
-mno-unaligned-access. Analysis showed patch affects only vect.exp
tests so only vect.exp was tested.
For x86, x86_64, ARM without -mno-unaligned-access, Thumb-2
without -mno-unaligned-access and Thumb-1 no regressions occured.
For ARM/Thumb2 with -mno-unaligned-access patch fixed most of
failures but triggered some problems (see attached log) for current
vect.exp tests:
1) https://gcc.gnu.org/bugzilla/show_bug.cgi?id=61887
2) Some XPASS'es due to unexpected loop versioning (e.g.
gcc.dg/vect/pr33804.c).
3) After predicate fix some passing tests which require unaligned
vector support become NA (this was expected).
Here is new version of patch and regression log. On the current
trunk results are slightly different due to patches for Richard
Biener (no UNRESOLVED fails) but some PASS->XPASS regressions still
remain (see attachment):
PASS->XPASS: gcc.dg/vect/if-cvt-stores-vect-ifcvt-18.c
scan-tree-dump-times vect "vectorized 1 loops" 1
PASS->XPASS: gcc.dg/vect/pr33804.c -flto -ffat-lto-objects
scan-tree-dump-times vect "vectorized 1 loops" 1
etc.
These XPASS'es are due to code versioning: current GCC creates 2
versions of loop: aligned and misaligned. It's look like they are
slightly out of date at lest for ARM.
On 07/24/2014 06:50 PM, Ramana Radhakrishnan wrote:
This is redundant.
- || (defined(__ARMEL__) \
+ || (defined(__ARM_FEATURE_UNALIGNED) \
+ && defined(__ARMEL__) \
&& (!defined(__thumb__) || defined(__thumb2__)))
As is this line.
I think you can restrict the check to defined(__ARM_FEATURE_UNALIGNED)
&& defined(__ARMEL__)
__ARM_FEATURE_UNALIGNED should tell you whether unaligned access is
allowed or not, therefore you should no longer require any specific
"architectural" checks.
#error FOO
#endif
I'm not sure about the original intent of the tests right now.
Ramana
Thank you Ramana!
--Marat
gcc/testsuite/ChangeLog:
2014-07-23 Marat Zakirov
* gcc.dg/vect/vect-109.c: Skip predicate added.
* gcc.dg/vect/vect-93.c: Test check fixed.
* gcc.dg/vect/bb-slp-10.c: Likewise.
* lib/target-supports.exp (check_effective_target_arm_vect_no_misalign):
Check unaligned feature.
diff --git a/gcc/testsuite/gcc.dg/vect/bb-slp-10.c b/gcc/testsuite/gcc.dg/vect/bb-slp-10.c
index a1850ed..0090a4b 100644
--- a/gcc/testsuite/gcc.dg/vect/bb-slp-10.c
+++ b/gcc/testsuite/gcc.dg/vect/bb-slp-10.c
@@ -49,7 +49,7 @@ int main (void)
return 0;
}
-/* { dg-final { scan-tree-dump-times "unsupported alignment in basic block." 1 "slp2" { xfail vect_element_align } } } */
+/* { dg-final { scan-tree-dump "unsupported alignment in basic block." 1 "slp2" { xfail vect_element_align } } } */
/* { dg-final { scan-tree-dump-times "basic block vectorized" 1 "slp2" { target vect_element_align } } } */
/* { dg-final { cleanup-tree-dump "slp2" } } */
diff --git a/gcc/testsuite/gcc.dg/vect/vect-109.c b/gcc/testsuite/gcc.dg/vect/vect-109.c
index 854c970..c671175 100644
--- a/gcc/testsuite/gcc.dg/vect/vect-109.c
+++ b/gcc/testsuite/gcc.dg/vect/vect-109.c
@@ -1,3 +1,4 @@
+/* { dg-skip-if "" { vect_no_align } } */
/* { dg-require-effective-target vect_int } */
#include
diff --git a/gcc/testsuite/gcc.dg/vect/vect-93.c b/gcc/testsuite/gcc.dg/vect/vect-93.c
index 65403eb..1065a6e 100644
--- a/gcc/testsuite/gcc.dg/vect/vect-93.c
+++ b/gcc/testsuite/gcc.dg/vect/vect-93.c
@@ -79,7 +79,7 @@ int main (void)
/* { dg-final { scan-tree-dump-times "vectorized 2 loops" 1 "vect" { target vect_no_align } } } */
/* in main: */
-/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" { target vect_no_align } } } */
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_no_align } } } */
/* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 1 "vect" { xfail { vect_no_align } } } } */
/* { dg-final { clea
Re: [PINGv3][PATCH] Fix for PR 61561
Sorry ;( Will test&fix it. On 08/07/2014 12:50 PM, Richard Earnshaw wrote: On 08/06/2014 06:44 PM, Richard Earnshaw wrote: Similarly for the movqi pattern. You haven't updated the thumb1 QImode pattern in the same way. R. On 07/08/14 09:10, Marat Zakirov wrote: --Marat On 08/07/2014 12:00 PM, Ramana Radhakrishnan wrote: On Thu, Aug 7, 2014 at 8:36 AM, Marat Zakirov wrote: Thank you. $ svn commit Sendinggcc/ChangeLog Sendinggcc/config/arm/thumb1.md Sendinggcc/config/arm/thumb2.md./gcc/config/arm/thumb1.md Transmitting file data ... Committed revision 213695. P.S. Minor nit was reg. tested. Another minor nit - please send the patch you committed to be archived on the mailing list. regards Ramana On 08/06/2014 06:44 PM, Richard Earnshaw wrote: On 06/08/14 15:14, Ramana Radhakrishnan wrote: This is OK thanks. Ramana Hmm, minor nit. (define_insn "*thumb1_movhi_insn" [(set (match_operand:HI 0 "nonimmediate_operand" "=l,l,m,*r,*h,l") - (match_operand:HI 1 "general_operand" "l,m,l,*h,*r,I"))] + (match_operand:HI 1 "general_operand" "lk,m,l,*h,*r,I"))] This would be better expressed as: [(set (match_operand:HI 0 "nonimmediate_operand" "=l,l,m,l*r,*h,l") (match_operand:HI 1 "general_operand" "l,m,l,k*h,*r,I"))] that is, to use the 4th alternative. That's because the use of SP in these operations does not clobber the flags. Similarly for the movqi pattern. R. thumb2.diff gcc/ChangeLog: 2014-08-07 Marat Zakirov * config/arm/thumb1.md (*thumb1_movhi_insn): Handle stack pointer. (*thumb1_movqi_insn): Likewise. * config/arm/thumb2.md (*thumb2_movhi_insn): Likewise. diff --git a/gcc/config/arm/thumb1.md b/gcc/config/arm/thumb1.md index cd1adf4..fed741e 100644 --- a/gcc/config/arm/thumb1.md +++ b/gcc/config/arm/thumb1.md @@ -707,8 +707,8 @@ ) (define_insn "*thumb1_movhi_insn" - [(set (match_operand:HI 0 "nonimmediate_operand" "=l,l,m,*r,*h,l") - (match_operand:HI 1 "general_operand" "l,m,l,*h,*r,I"))] + [(set (match_operand:HI 0 "nonimmediate_operand" "=l,l,m,l*r,*h,l") + (match_operand:HI 1 "general_operand" "l,m,l,k*h,*r,I"))] "TARGET_THUMB1 && ( register_operand (operands[0], HImode) || register_operand (operands[1], HImode))" @@ -762,7 +762,7 @@ (define_insn "*thumb1_movqi_insn" [(set (match_operand:QI 0 "nonimmediate_operand" "=l,l,m,*r,*h,l") - (match_operand:QI 1 "general_operand" "l, m,l,*h,*r,I"))] + (match_operand:QI 1 "general_operand" "lk, m,l,*h,*r,I"))] "TARGET_THUMB1 && ( register_operand (operands[0], QImode) || register_operand (operands[1], QImode))" diff --git a/gcc/config/arm/thumb2.md b/gcc/config/arm/thumb2.md index 029a679..983b59d 100644 --- a/gcc/config/arm/thumb2.md +++ b/gcc/config/arm/thumb2.md @@ -318,7 +318,7 @@ ;; of the messiness associated with the ARM patterns. (define_insn "*thumb2_movhi_insn" [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,l,r,m,r") - (match_operand:HI 1 "general_operand" "r,I,Py,n,r,m"))] + (match_operand:HI 1 "general_operand" "rk,I,Py,n,r,m"))] "TARGET_THUMB2 && (register_operand (operands[0], HImode) || register_operand (operands[1], HImode))"
Re: [PINGv3][PATCH] Fix for PR 61561
Sendinggcc/ChangeLog Sendinggcc/config/arm/thumb1.md Transmitting file data .. Committed revision 213710. P.S. Sorry for inconvenience. On 08/07/2014 01:02 PM, Marat Zakirov wrote: Sorry ;( Will test&fix it. On 08/07/2014 12:50 PM, Richard Earnshaw wrote: On 08/06/2014 06:44 PM, Richard Earnshaw wrote: Similarly for the movqi pattern. You haven't updated the thumb1 QImode pattern in the same way. R. On 07/08/14 09:10, Marat Zakirov wrote: --Marat On 08/07/2014 12:00 PM, Ramana Radhakrishnan wrote: On Thu, Aug 7, 2014 at 8:36 AM, Marat Zakirov wrote: Thank you. $ svn commit Sendinggcc/ChangeLog Sendinggcc/config/arm/thumb1.md Sending gcc/config/arm/thumb2.md./gcc/config/arm/thumb1.md Transmitting file data ... Committed revision 213695. P.S. Minor nit was reg. tested. Another minor nit - please send the patch you committed to be archived on the mailing list. regards Ramana On 08/06/2014 06:44 PM, Richard Earnshaw wrote: On 06/08/14 15:14, Ramana Radhakrishnan wrote: This is OK thanks. Ramana Hmm, minor nit. (define_insn "*thumb1_movhi_insn" [(set (match_operand:HI 0 "nonimmediate_operand" "=l,l,m,*r,*h,l") - (match_operand:HI 1 "general_operand" "l,m,l,*h,*r,I"))] + (match_operand:HI 1 "general_operand" "lk,m,l,*h,*r,I"))] This would be better expressed as: [(set (match_operand:HI 0 "nonimmediate_operand" "=l,l,m,l*r,*h,l") (match_operand:HI 1 "general_operand" "l,m,l,k*h,*r,I"))] that is, to use the 4th alternative. That's because the use of SP in these operations does not clobber the flags. Similarly for the movqi pattern. R. thumb2.diff gcc/ChangeLog: 2014-08-07 Marat Zakirov * config/arm/thumb1.md (*thumb1_movhi_insn): Handle stack pointer. (*thumb1_movqi_insn): Likewise. * config/arm/thumb2.md (*thumb2_movhi_insn): Likewise. diff --git a/gcc/config/arm/thumb1.md b/gcc/config/arm/thumb1.md index cd1adf4..fed741e 100644 --- a/gcc/config/arm/thumb1.md +++ b/gcc/config/arm/thumb1.md @@ -707,8 +707,8 @@ ) (define_insn "*thumb1_movhi_insn" - [(set (match_operand:HI 0 "nonimmediate_operand" "=l,l,m,*r,*h,l") -(match_operand:HI 1 "general_operand" "l,m,l,*h,*r,I"))] + [(set (match_operand:HI 0 "nonimmediate_operand" "=l,l,m,l*r,*h,l") +(match_operand:HI 1 "general_operand" "l,m,l,k*h,*r,I"))] "TARGET_THUMB1 && ( register_operand (operands[0], HImode) || register_operand (operands[1], HImode))" @@ -762,7 +762,7 @@ (define_insn "*thumb1_movqi_insn" [(set (match_operand:QI 0 "nonimmediate_operand" "=l,l,m,*r,*h,l") -(match_operand:QI 1 "general_operand" "l, m,l,*h,*r,I"))] +(match_operand:QI 1 "general_operand" "lk, m,l,*h,*r,I"))] "TARGET_THUMB1 && ( register_operand (operands[0], QImode) || register_operand (operands[1], QImode))" diff --git a/gcc/config/arm/thumb2.md b/gcc/config/arm/thumb2.md index 029a679..983b59d 100644 --- a/gcc/config/arm/thumb2.md +++ b/gcc/config/arm/thumb2.md @@ -318,7 +318,7 @@ ;; of the messiness associated with the ARM patterns. (define_insn "*thumb2_movhi_insn" [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,l,r,m,r") -(match_operand:HI 1 "general_operand" "r,I,Py,n,r,m"))] +(match_operand:HI 1 "general_operand" "rk,I,Py,n,r,m"))] "TARGET_THUMB2 && (register_operand (operands[0], HImode) || register_operand (operands[1], HImode))" gcc/ChangeLog: 2014-08-07 Marat Zakirov * config/arm/thumb1.md (*thumb1_movqi_insn): Copy of thumb1_movhi_insn. --- gcc/config/arm/thumb1.md (revision 213695) +++ gcc/config/arm/thumb1.md (working copy) @@ -761,8 +761,8 @@ ) (define_insn "*thumb1_movqi_insn" - [(set (match_operand:QI 0 "nonimmediate_operand" "=l,l,m,*r,*h,l") - (match_operand:QI 1 "general_operand" "lk, m,l,*h,*r,I"))] + [(set (match_operand:QI 0 "nonimmediate_operand" "=l,l,m,l*r,*h,l") + (match_operand:QI 1 "general_operand" "l,m,l,k*h,*r,I"))] "TARGET_THUMB1 && ( register_operand (operands[0], QImode) || register_operand (operands[1], QImode))"
[PINGv3][PATCHv3] Fix vector tests on ARM platforms with disabled unaligned accesses
On 08/07/2014 12:52 PM, Marat Zakirov wrote:
On 07/31/2014 04:08 PM, Marat Zakirov wrote:
On 07/24/2014 07:40 PM, Marat Zakirov wrote:
On 07/24/2014 04:27 PM, Marat Zakirov wrote:
On 07/23/2014 06:23 PM, Marat Zakirov wrote:
Hi there!
I made a patch which fixes regressions on ARM platforms with
disabled unaligned accesses. The problem is that
'arm_vect_no_misalign' predicate do not check 'unaligned_access'
global variable to determine whether unaligned access to vector
are allowed. This leads to spurious vect.exp test fails when GCC
is configured
--with-specs=%{!munaligned-access:-mno-unaligned-access}.
Attached patch fixes ARM predicate and several tests to correctly
handle the issue.
The following targets were reg. tested for multiple targets (ARM,
Thumb-1, Thumb-2, x86, x86_64) with and without
-mno-unaligned-access. Analysis showed patch affects only
vect.exp tests so only vect.exp was tested.
For x86, x86_64, ARM without -mno-unaligned-access, Thumb-2
without -mno-unaligned-access and Thumb-1 no regressions occured.
For ARM/Thumb2 with -mno-unaligned-access patch fixed most of
failures but triggered some problems (see attached log) for
current vect.exp tests:
1) https://gcc.gnu.org/bugzilla/show_bug.cgi?id=61887
2) Some XPASS'es due to unexpected loop versioning (e.g.
gcc.dg/vect/pr33804.c).
3) After predicate fix some passing tests which require unaligned
vector support become NA (this was expected).
Here is new version of patch and regression log. On the current
trunk results are slightly different due to patches for Richard
Biener (no UNRESOLVED fails) but some PASS->XPASS regressions still
remain (see attachment):
PASS->XPASS: gcc.dg/vect/if-cvt-stores-vect-ifcvt-18.c
scan-tree-dump-times vect "vectorized 1 loops" 1
PASS->XPASS: gcc.dg/vect/pr33804.c -flto -ffat-lto-objects
scan-tree-dump-times vect "vectorized 1 loops" 1
etc.
These XPASS'es are due to code versioning: current GCC creates 2
versions of loop: aligned and misaligned. It's look like they are
slightly out of date at lest for ARM.
On 07/24/2014 06:50 PM, Ramana Radhakrishnan wrote:
This is redundant.
- || (defined(__ARMEL__) \
+ || (defined(__ARM_FEATURE_UNALIGNED) \
+ && defined(__ARMEL__) \
&& (!defined(__thumb__) || defined(__thumb2__)))
As is this line.
I think you can restrict the check to defined(__ARM_FEATURE_UNALIGNED)
&& defined(__ARMEL__)
__ARM_FEATURE_UNALIGNED should tell you whether unaligned access is
allowed or not, therefore you should no longer require any specific
"architectural" checks.
#error FOO
#endif
I'm not sure about the original intent of the tests right now.
Ramana
Thank you Ramana!
--Marat
gcc/testsuite/ChangeLog:
2014-07-23 Marat Zakirov
* gcc.dg/vect/vect-109.c: Skip predicate added.
* gcc.dg/vect/vect-93.c: Test check fixed.
* gcc.dg/vect/bb-slp-10.c: Likewise.
* lib/target-supports.exp (check_effective_target_arm_vect_no_misalign):
Check unaligned feature.
diff --git a/gcc/testsuite/gcc.dg/vect/bb-slp-10.c b/gcc/testsuite/gcc.dg/vect/bb-slp-10.c
index a1850ed..0090a4b 100644
--- a/gcc/testsuite/gcc.dg/vect/bb-slp-10.c
+++ b/gcc/testsuite/gcc.dg/vect/bb-slp-10.c
@@ -49,7 +49,7 @@ int main (void)
return 0;
}
-/* { dg-final { scan-tree-dump-times "unsupported alignment in basic block." 1 "slp2" { xfail vect_element_align } } } */
+/* { dg-final { scan-tree-dump "unsupported alignment in basic block." 1 "slp2" { xfail vect_element_align } } } */
/* { dg-final { scan-tree-dump-times "basic block vectorized" 1 "slp2" { target vect_element_align } } } */
/* { dg-final { cleanup-tree-dump "slp2" } } */
diff --git a/gcc/testsuite/gcc.dg/vect/vect-109.c b/gcc/testsuite/gcc.dg/vect/vect-109.c
index 854c970..c671175 100644
--- a/gcc/testsuite/gcc.dg/vect/vect-109.c
+++ b/gcc/testsuite/gcc.dg/vect/vect-109.c
@@ -1,3 +1,4 @@
+/* { dg-skip-if "" { vect_no_align } } */
/* { dg-require-effective-target vect_int } */
#include
diff --git a/gcc/testsuite/gcc.dg/vect/vect-93.c b/gcc/testsuite/gcc.dg/vect/vect-93.c
index 65403eb..1065a6e 100644
--- a/gcc/testsuite/gcc.dg/vect/vect-93.c
+++ b/gcc/testsuite/gcc.dg/vect/vect-93.c
@@ -79,7 +79,7 @@ int main (void)
/* { dg-final { scan-tree-dump-times "vectorized 2 loops" 1 "vect" { target vect_no_align } } } */
/* in main: */
-/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" { target vect_no_align } } } */
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_no_align } } } */
/* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 1 "vect" { xfail { vect_no_align } } } } */
/* {
[PATCH] Fix for PR 61875
Hi there!
I have a fix for https://gcc.gnu.org/bugzilla/show_bug.cgi?id=61875.
This situation occurs when somebody decides to build GCC with these
flags which are forbidden for libsanitizer. They get strange error (see
bug above) which I know how to fix but think that I should not. Instead
of it attached patch forces configure to fail when meet -fexceptions or
-frtti option in CXXFLAGS.
--Marat
libsanitizer/ChangeLog:
2014-08-18 Marat Zakirov
* configure.ac: Check -fexceptions and -frtti.
* configure: Regenerate.
diff --git a/libsanitizer/configure b/libsanitizer/configure
index 5e4840f..19261c6 100755
--- a/libsanitizer/configure
+++ b/libsanitizer/configure
@@ -648,18 +648,15 @@ am__fastdepCCAS_TRUE
CCASDEPMODE
CCASFLAGS
CCAS
-am__fastdepCXX_FALSE
-am__fastdepCXX_TRUE
-CXXDEPMODE
-ac_ct_CXX
-CXXFLAGS
-CXX
toolexeclibdir
toolexecdir
MAINT
MAINTAINER_MODE_FALSE
MAINTAINER_MODE_TRUE
multi_basedir
+am__fastdepCXX_FALSE
+am__fastdepCXX_TRUE
+CXXDEPMODE
am__fastdepCC_FALSE
am__fastdepCC_TRUE
CCDEPMODE
@@ -710,13 +707,16 @@ build
EGREP
GREP
CPP
+ac_ct_CC
+CFLAGS
+CC
OBJEXT
EXEEXT
-ac_ct_CC
+ac_ct_CXX
CPPFLAGS
LDFLAGS
-CFLAGS
-CC
+CXXFLAGS
+CXX
target_alias
host_alias
build_alias
@@ -772,15 +772,15 @@ enable_libtool_lock
ac_precious_vars='build_alias
host_alias
target_alias
-CC
-CFLAGS
+CXX
+CXXFLAGS
LDFLAGS
LIBS
CPPFLAGS
-CPP
-CXX
-CXXFLAGS
CCC
+CC
+CFLAGS
+CPP
CCAS
CCASFLAGS
CXXCPP'
@@ -1424,16 +1424,16 @@ Optional Packages:
--with-gnu-ld assume the C compiler uses GNU ld [default=no]
Some influential environment variables:
- CC C compiler command
- CFLAGS C compiler flags
+ CXX C++ compiler command
+ CXXFLAGSC++ compiler flags
LDFLAGS linker flags, e.g. -L if you have libraries in a
nonstandard directory
LIBSlibraries to pass to the linker, e.g. -l
CPPFLAGSC/C++/Objective C preprocessor flags, e.g. -I if
you have headers in a nonstandard directory
+ CC C compiler command
+ CFLAGS C compiler flags
CPP C preprocessor
- CXX C++ compiler command
- CXXFLAGSC++ compiler flags
CCASassembler compiler command (defaults to CC)
CCASFLAGS assembler compiler flags (defaults to CFLAGS)
CXXCPP C++ preprocessor
@@ -1518,6 +1518,44 @@ fi
## Autoconf initialization. ##
## ##
+# ac_fn_cxx_try_compile LINENO
+#
+# Try to compile conftest.$ac_ext, and return whether this succeeded.
+ac_fn_cxx_try_compile ()
+{
+ as_lineno=${as_lineno-"$1"} as_lineno_stack=as_lineno_stack=$as_lineno_stack
+ rm -f conftest.$ac_objext
+ if { { ac_try="$ac_compile"
+case "(($ac_try" in
+ *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;;
+ *) ac_try_echo=$ac_try;;
+esac
+eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\""
+$as_echo "$ac_try_echo"; } >&5
+ (eval "$ac_compile") 2>conftest.err
+ ac_status=$?
+ if test -s conftest.err; then
+grep -v '^ *+' conftest.err >conftest.er1
+cat conftest.er1 >&5
+mv -f conftest.er1 conftest.err
+ fi
+ $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5
+ test $ac_status = 0; } && {
+ test -z "$ac_cxx_werror_flag" ||
+ test ! -s conftest.err
+ } && test -s conftest.$ac_objext; then :
+ ac_retval=0
+else
+ $as_echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+ ac_retval=1
+fi
+ eval $as_lineno_stack; test "x$as_lineno_stack" = x && { as_lineno=; unset as_lineno;}
+ return $ac_retval
+
+} # ac_fn_cxx_try_compile
+
# ac_fn_c_try_compile LINENO
# --
# Try to compile conftest.$ac_ext, and return whether this succeeded.
@@ -1759,44 +1797,6 @@ $as_echo "$ac_res" >&6; }
} # ac_fn_c_check_header_compile
-# ac_fn_cxx_try_compile LINENO
-#
-# Try to compile conftest.$ac_ext, and return whether this succeeded.
-ac_fn_cxx_try_compile ()
-{
- as_lineno=${as_lineno-"$1"} as_lineno_stack=as_lineno_stack=$as_lineno_stack
- rm -f conftest.$ac_objext
- if { { ac_try="$ac_compile"
-case "(($ac_try" in
- *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;;
- *) ac_try_echo=$ac_try;;
-esac
-eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\""
-$as_echo "$ac_try_echo"; } >&5
- (eval "$ac_compile") 2>conftest.err
- ac_status=$?
- if test -s conftest.err; then
-grep -v '^ *+' conftest.err >conftest.er1
-cat conftest.er1 >&5
-mv -f conftest.er1 conftest.err
- fi
- $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5
- test $ac_status = 0; }
[PINGv4][PATCHv3] Fix vector tests on ARM platforms with disabled unaligned accesses
On 08/14/2014 05:40 PM, Marat Zakirov wrote:
On 08/07/2014 12:52 PM, Marat Zakirov wrote:
On 07/31/2014 04:08 PM, Marat Zakirov wrote:
On 07/24/2014 07:40 PM, Marat Zakirov wrote:
On 07/24/2014 04:27 PM, Marat Zakirov wrote:
On 07/23/2014 06:23 PM, Marat Zakirov wrote:
Hi there!
I made a patch which fixes regressions on ARM platforms with
disabled unaligned accesses. The problem is that
'arm_vect_no_misalign' predicate do not check 'unaligned_access'
global variable to determine whether unaligned access to vector
are allowed. This leads to spurious vect.exp test fails when GCC
is configured
--with-specs=%{!munaligned-access:-mno-unaligned-access}.
Attached patch fixes ARM predicate and several tests to correctly
handle the issue.
The following targets were reg. tested for multiple targets (ARM,
Thumb-1, Thumb-2, x86, x86_64) with and without
-mno-unaligned-access. Analysis showed patch affects only
vect.exp tests so only vect.exp was tested.
For x86, x86_64, ARM without -mno-unaligned-access, Thumb-2
without -mno-unaligned-access and Thumb-1 no regressions occured.
For ARM/Thumb2 with -mno-unaligned-access patch fixed most of
failures but triggered some problems (see attached log) for
current vect.exp tests:
1) https://gcc.gnu.org/bugzilla/show_bug.cgi?id=61887
2) Some XPASS'es due to unexpected loop versioning (e.g.
gcc.dg/vect/pr33804.c).
3) After predicate fix some passing tests which require unaligned
vector support become NA (this was expected).
Here is new version of patch and regression log. On the current
trunk results are slightly different due to patches for Richard
Biener (no UNRESOLVED fails) but some PASS->XPASS regressions
still remain (see attachment):
PASS->XPASS: gcc.dg/vect/if-cvt-stores-vect-ifcvt-18.c
scan-tree-dump-times vect "vectorized 1 loops" 1
PASS->XPASS: gcc.dg/vect/pr33804.c -flto -ffat-lto-objects
scan-tree-dump-times vect "vectorized 1 loops" 1
etc.
These XPASS'es are due to code versioning: current GCC creates 2
versions of loop: aligned and misaligned. It's look like they are
slightly out of date at lest for ARM.
On 07/24/2014 06:50 PM, Ramana Radhakrishnan wrote:
This is redundant.
- || (defined(__ARMEL__) \
+ || (defined(__ARM_FEATURE_UNALIGNED) \
+ && defined(__ARMEL__) \
&& (!defined(__thumb__) || defined(__thumb2__)))
As is this line.
I think you can restrict the check to
defined(__ARM_FEATURE_UNALIGNED)
&& defined(__ARMEL__)
__ARM_FEATURE_UNALIGNED should tell you whether unaligned access is
allowed or not, therefore you should no longer require any specific
"architectural" checks.
#error FOO
#endif
I'm not sure about the original intent of the tests right now.
Ramana
Thank you Ramana!
--Marat
gcc/testsuite/ChangeLog:
2014-07-23 Marat Zakirov
* gcc.dg/vect/vect-109.c: Skip predicate added.
* gcc.dg/vect/vect-93.c: Test check fixed.
* gcc.dg/vect/bb-slp-10.c: Likewise.
* lib/target-supports.exp (check_effective_target_arm_vect_no_misalign):
Check unaligned feature.
diff --git a/gcc/testsuite/gcc.dg/vect/bb-slp-10.c b/gcc/testsuite/gcc.dg/vect/bb-slp-10.c
index a1850ed..0090a4b 100644
--- a/gcc/testsuite/gcc.dg/vect/bb-slp-10.c
+++ b/gcc/testsuite/gcc.dg/vect/bb-slp-10.c
@@ -49,7 +49,7 @@ int main (void)
return 0;
}
-/* { dg-final { scan-tree-dump-times "unsupported alignment in basic block." 1 "slp2" { xfail vect_element_align } } } */
+/* { dg-final { scan-tree-dump "unsupported alignment in basic block." 1 "slp2" { xfail vect_element_align } } } */
/* { dg-final { scan-tree-dump-times "basic block vectorized" 1 "slp2" { target vect_element_align } } } */
/* { dg-final { cleanup-tree-dump "slp2" } } */
diff --git a/gcc/testsuite/gcc.dg/vect/vect-109.c b/gcc/testsuite/gcc.dg/vect/vect-109.c
index 854c970..c671175 100644
--- a/gcc/testsuite/gcc.dg/vect/vect-109.c
+++ b/gcc/testsuite/gcc.dg/vect/vect-109.c
@@ -1,3 +1,4 @@
+/* { dg-skip-if "" { vect_no_align } } */
/* { dg-require-effective-target vect_int } */
#include
diff --git a/gcc/testsuite/gcc.dg/vect/vect-93.c b/gcc/testsuite/gcc.dg/vect/vect-93.c
index 65403eb..1065a6e 100644
--- a/gcc/testsuite/gcc.dg/vect/vect-93.c
+++ b/gcc/testsuite/gcc.dg/vect/vect-93.c
@@ -79,7 +79,7 @@ int main (void)
/* { dg-final { scan-tree-dump-times "vectorized 2 loops" 1 "vect" { target vect_no_align } } } */
/* in main: */
-/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" { target vect_no_align } } } */
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_no_align } } } */
/* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 1 "vect
[PING][PATCH] Fix for PR 61875
On 08/18/2014 07:37 PM, Marat Zakirov wrote:
Hi there!
I have a fix for https://gcc.gnu.org/bugzilla/show_bug.cgi?id=61875.
This situation occurs when somebody decides to build GCC with
-fexeptions and -frtti which are forbidden for libsanitizer. They get
strange error (see bug above) which I know how to fix but think that I
should not. Instead of it attached patch forces configure to fail when
meet -fexceptions or -frtti option in CXXFLAGS.
--Marat
libsanitizer/ChangeLog:
2014-08-18 Marat Zakirov
* configure.ac: Check -fexceptions and -frtti.
* configure: Regenerate.
diff --git a/libsanitizer/configure b/libsanitizer/configure
index 5e4840f..19261c6 100755
--- a/libsanitizer/configure
+++ b/libsanitizer/configure
@@ -648,18 +648,15 @@ am__fastdepCCAS_TRUE
CCASDEPMODE
CCASFLAGS
CCAS
-am__fastdepCXX_FALSE
-am__fastdepCXX_TRUE
-CXXDEPMODE
-ac_ct_CXX
-CXXFLAGS
-CXX
toolexeclibdir
toolexecdir
MAINT
MAINTAINER_MODE_FALSE
MAINTAINER_MODE_TRUE
multi_basedir
+am__fastdepCXX_FALSE
+am__fastdepCXX_TRUE
+CXXDEPMODE
am__fastdepCC_FALSE
am__fastdepCC_TRUE
CCDEPMODE
@@ -710,13 +707,16 @@ build
EGREP
GREP
CPP
+ac_ct_CC
+CFLAGS
+CC
OBJEXT
EXEEXT
-ac_ct_CC
+ac_ct_CXX
CPPFLAGS
LDFLAGS
-CFLAGS
-CC
+CXXFLAGS
+CXX
target_alias
host_alias
build_alias
@@ -772,15 +772,15 @@ enable_libtool_lock
ac_precious_vars='build_alias
host_alias
target_alias
-CC
-CFLAGS
+CXX
+CXXFLAGS
LDFLAGS
LIBS
CPPFLAGS
-CPP
-CXX
-CXXFLAGS
CCC
+CC
+CFLAGS
+CPP
CCAS
CCASFLAGS
CXXCPP'
@@ -1424,16 +1424,16 @@ Optional Packages:
--with-gnu-ld assume the C compiler uses GNU ld [default=no]
Some influential environment variables:
- CC C compiler command
- CFLAGS C compiler flags
+ CXX C++ compiler command
+ CXXFLAGSC++ compiler flags
LDFLAGS linker flags, e.g. -L if you have libraries in a
nonstandard directory
LIBSlibraries to pass to the linker, e.g. -l
CPPFLAGSC/C++/Objective C preprocessor flags, e.g. -I if
you have headers in a nonstandard directory
+ CC C compiler command
+ CFLAGS C compiler flags
CPP C preprocessor
- CXX C++ compiler command
- CXXFLAGSC++ compiler flags
CCASassembler compiler command (defaults to CC)
CCASFLAGS assembler compiler flags (defaults to CFLAGS)
CXXCPP C++ preprocessor
@@ -1518,6 +1518,44 @@ fi
## Autoconf initialization. ##
## ##
+# ac_fn_cxx_try_compile LINENO
+#
+# Try to compile conftest.$ac_ext, and return whether this succeeded.
+ac_fn_cxx_try_compile ()
+{
+ as_lineno=${as_lineno-"$1"} as_lineno_stack=as_lineno_stack=$as_lineno_stack
+ rm -f conftest.$ac_objext
+ if { { ac_try="$ac_compile"
+case "(($ac_try" in
+ *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;;
+ *) ac_try_echo=$ac_try;;
+esac
+eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\""
+$as_echo "$ac_try_echo"; } >&5
+ (eval "$ac_compile") 2>conftest.err
+ ac_status=$?
+ if test -s conftest.err; then
+grep -v '^ *+' conftest.err >conftest.er1
+cat conftest.er1 >&5
+mv -f conftest.er1 conftest.err
+ fi
+ $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5
+ test $ac_status = 0; } && {
+ test -z "$ac_cxx_werror_flag" ||
+ test ! -s conftest.err
+ } && test -s conftest.$ac_objext; then :
+ ac_retval=0
+else
+ $as_echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+ ac_retval=1
+fi
+ eval $as_lineno_stack; test "x$as_lineno_stack" = x && { as_lineno=; unset as_lineno;}
+ return $ac_retval
+
+} # ac_fn_cxx_try_compile
+
# ac_fn_c_try_compile LINENO
# --
# Try to compile conftest.$ac_ext, and return whether this succeeded.
@@ -1759,44 +1797,6 @@ $as_echo "$ac_res" >&6; }
} # ac_fn_c_check_header_compile
-# ac_fn_cxx_try_compile LINENO
-#
-# Try to compile conftest.$ac_ext, and return whether this succeeded.
-ac_fn_cxx_try_compile ()
-{
- as_lineno=${as_lineno-"$1"} as_lineno_stack=as_lineno_stack=$as_lineno_stack
- rm -f conftest.$ac_objext
- if { { ac_try="$ac_compile"
-case "(($ac_try" in
- *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;;
- *) ac_try_echo=$ac_try;;
-esac
-eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\""
-$as_echo "$ac_try_echo"; } >&5
- (eval "$ac_compile") 2>conftest.err
- ac_status=$?
- if test -s conftest.err; then
-grep -v '^ *+' conftest.err >conftest.er1
-cat conftest.er1 >&5
-mv -f conftest.er1 conftest.err
- fi
- $as_echo "$as_me:${as_lineno-$LINENO}: \$?
[PINGv2][PATCH] Fix for PR 61875
On 08/26/2014 12:47 PM, Marat Zakirov wrote:
On 08/18/2014 07:37 PM, Marat Zakirov wrote:
Hi there!
I have a fix for https://gcc.gnu.org/bugzilla/show_bug.cgi?id=61875.
This situation occurs when somebody decides to build GCC with
-fexeptions and -frtti which are forbidden for libsanitizer. They get
strange error (see bug above) which I know how to fix but think that
I should not. Instead of it attached patch forces configure to fail
when meet -fexceptions or -frtti option in CXXFLAGS.
--Marat
libsanitizer/ChangeLog:
2014-08-18 Marat Zakirov
* configure.ac: Check -fexceptions and -frtti.
* configure: Regenerate.
diff --git a/libsanitizer/configure b/libsanitizer/configure
index 5e4840f..19261c6 100755
--- a/libsanitizer/configure
+++ b/libsanitizer/configure
@@ -648,18 +648,15 @@ am__fastdepCCAS_TRUE
CCASDEPMODE
CCASFLAGS
CCAS
-am__fastdepCXX_FALSE
-am__fastdepCXX_TRUE
-CXXDEPMODE
-ac_ct_CXX
-CXXFLAGS
-CXX
toolexeclibdir
toolexecdir
MAINT
MAINTAINER_MODE_FALSE
MAINTAINER_MODE_TRUE
multi_basedir
+am__fastdepCXX_FALSE
+am__fastdepCXX_TRUE
+CXXDEPMODE
am__fastdepCC_FALSE
am__fastdepCC_TRUE
CCDEPMODE
@@ -710,13 +707,16 @@ build
EGREP
GREP
CPP
+ac_ct_CC
+CFLAGS
+CC
OBJEXT
EXEEXT
-ac_ct_CC
+ac_ct_CXX
CPPFLAGS
LDFLAGS
-CFLAGS
-CC
+CXXFLAGS
+CXX
target_alias
host_alias
build_alias
@@ -772,15 +772,15 @@ enable_libtool_lock
ac_precious_vars='build_alias
host_alias
target_alias
-CC
-CFLAGS
+CXX
+CXXFLAGS
LDFLAGS
LIBS
CPPFLAGS
-CPP
-CXX
-CXXFLAGS
CCC
+CC
+CFLAGS
+CPP
CCAS
CCASFLAGS
CXXCPP'
@@ -1424,16 +1424,16 @@ Optional Packages:
--with-gnu-ld assume the C compiler uses GNU ld [default=no]
Some influential environment variables:
- CC C compiler command
- CFLAGS C compiler flags
+ CXX C++ compiler command
+ CXXFLAGSC++ compiler flags
LDFLAGS linker flags, e.g. -L if you have libraries in a
nonstandard directory
LIBSlibraries to pass to the linker, e.g. -l
CPPFLAGSC/C++/Objective C preprocessor flags, e.g. -I if
you have headers in a nonstandard directory
+ CC C compiler command
+ CFLAGS C compiler flags
CPP C preprocessor
- CXX C++ compiler command
- CXXFLAGSC++ compiler flags
CCASassembler compiler command (defaults to CC)
CCASFLAGS assembler compiler flags (defaults to CFLAGS)
CXXCPP C++ preprocessor
@@ -1518,6 +1518,44 @@ fi
## Autoconf initialization. ##
## ##
+# ac_fn_cxx_try_compile LINENO
+#
+# Try to compile conftest.$ac_ext, and return whether this succeeded.
+ac_fn_cxx_try_compile ()
+{
+ as_lineno=${as_lineno-"$1"} as_lineno_stack=as_lineno_stack=$as_lineno_stack
+ rm -f conftest.$ac_objext
+ if { { ac_try="$ac_compile"
+case "(($ac_try" in
+ *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;;
+ *) ac_try_echo=$ac_try;;
+esac
+eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\""
+$as_echo "$ac_try_echo"; } >&5
+ (eval "$ac_compile") 2>conftest.err
+ ac_status=$?
+ if test -s conftest.err; then
+grep -v '^ *+' conftest.err >conftest.er1
+cat conftest.er1 >&5
+mv -f conftest.er1 conftest.err
+ fi
+ $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5
+ test $ac_status = 0; } && {
+ test -z "$ac_cxx_werror_flag" ||
+ test ! -s conftest.err
+ } && test -s conftest.$ac_objext; then :
+ ac_retval=0
+else
+ $as_echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+ ac_retval=1
+fi
+ eval $as_lineno_stack; test "x$as_lineno_stack" = x && { as_lineno=; unset as_lineno;}
+ return $ac_retval
+
+} # ac_fn_cxx_try_compile
+
# ac_fn_c_try_compile LINENO
# --
# Try to compile conftest.$ac_ext, and return whether this succeeded.
@@ -1759,44 +1797,6 @@ $as_echo "$ac_res" >&6; }
} # ac_fn_c_check_header_compile
-# ac_fn_cxx_try_compile LINENO
-#
-# Try to compile conftest.$ac_ext, and return whether this succeeded.
-ac_fn_cxx_try_compile ()
-{
- as_lineno=${as_lineno-"$1"} as_lineno_stack=as_lineno_stack=$as_lineno_stack
- rm -f conftest.$ac_objext
- if { { ac_try="$ac_compile"
-case "(($ac_try" in
- *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;;
- *) ac_try_echo=$ac_try;;
-esac
-eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\""
-$as_echo "$ac_try_echo"; } >&5
- (eval "$ac_compile") 2>conftest.err
- ac_status=$?
- if test -s conftest.err; then
-grep -v '^ *+' conftest.err >conftest.er1
-cat conftest.er1 >&5
-mv -f conftest.er1 conftest.err
- fi
- $
Re: please verify my mail to community.
Hi all!
Here's a simple optimization patch for Asan. It stores alignment
information into ASAN_CHECK which is then extracted by sanopt to reduce
number of "and 0x7" instructions for sufficiently aligned accesses. I
checked it on linux kernel by comparing results of objdump -d -j .text
vmlinux | grep "and.*0x7," for optimized and regular cases. It
eliminates 12% of and 0x7's.
No regressions. Sanitized GCC was successfully Asan-bootstrapped. No
false positives were found in kernel.
--Marat
gcc/ChangeLog:
2014-09-02 Marat Zakirov
* asan.c (build_check_stmt): Alignment arg was added.
(asan_expand_check_ifn): Optimization for alignment >= 8.
gcc/testsuite/ChangeLog:
2014-09-02 Marat Zakirov
* c-c++-common/asan/red-align-1.c: New test.
* c-c++-common/asan/red-align-2.c: New test.
diff --git a/gcc/asan.c b/gcc/asan.c
index 58e7719..aed5ede 100644
--- a/gcc/asan.c
+++ b/gcc/asan.c
@@ -1639,9 +1639,11 @@ build_check_stmt (location_t loc, tree base, tree len,
if (end_instrumented)
flags |= ASAN_CHECK_END_INSTRUMENTED;
- g = gimple_build_call_internal (IFN_ASAN_CHECK, 3,
+ g = gimple_build_call_internal (IFN_ASAN_CHECK, 4,
build_int_cst (integer_type_node, flags),
- base, len);
+ base, len,
+ build_int_cst (integer_type_node,
+ align/BITS_PER_UNIT));
gimple_set_location (g, loc);
if (before_p)
gsi_insert_before (&gsi, g, GSI_SAME_STMT);
@@ -2434,6 +2436,7 @@ asan_expand_check_ifn (gimple_stmt_iterator *iter, bool use_calls)
tree base = gimple_call_arg (g, 1);
tree len = gimple_call_arg (g, 2);
+ HOST_WIDE_INT align = tree_to_shwi (gimple_call_arg (g, 3));
HOST_WIDE_INT size_in_bytes
= is_scalar_access && tree_fits_shwi_p (len) ? tree_to_shwi (len) : -1;
@@ -2547,7 +2550,10 @@ asan_expand_check_ifn (gimple_stmt_iterator *iter, bool use_calls)
gimple shadow_test = build_assign (NE_EXPR, shadow, 0);
gimple_seq seq = NULL;
gimple_seq_add_stmt (&seq, shadow_test);
- gimple_seq_add_stmt (&seq, build_assign (BIT_AND_EXPR, base_addr, 7));
+ /* Aligned (>= 8 bytes) access do not need & 7. */
+ if (align < 8)
+ gimple_seq_add_stmt (&seq, build_assign (BIT_AND_EXPR,
+ base_addr, 7));
gimple_seq_add_stmt (&seq, build_type_cast (shadow_type,
gimple_seq_last (seq)));
if (real_size_in_bytes > 1)
diff --git a/gcc/internal-fn.def b/gcc/internal-fn.def
index 7ae60f3..54ade9f 100644
--- a/gcc/internal-fn.def
+++ b/gcc/internal-fn.def
@@ -55,4 +55,4 @@ DEF_INTERNAL_FN (UBSAN_CHECK_SUB, ECF_CONST | ECF_LEAF | ECF_NOTHROW, NULL)
DEF_INTERNAL_FN (UBSAN_CHECK_MUL, ECF_CONST | ECF_LEAF | ECF_NOTHROW, NULL)
DEF_INTERNAL_FN (ABNORMAL_DISPATCHER, ECF_NORETURN, NULL)
DEF_INTERNAL_FN (BUILTIN_EXPECT, ECF_CONST | ECF_LEAF | ECF_NOTHROW, NULL)
-DEF_INTERNAL_FN (ASAN_CHECK, ECF_TM_PURE | ECF_LEAF | ECF_NOTHROW, ".W..")
+DEF_INTERNAL_FN (ASAN_CHECK, ECF_TM_PURE | ECF_LEAF | ECF_NOTHROW, ".W...")
diff --git a/gcc/testsuite/c-c++-common/asan/red-align-1.c b/gcc/testsuite/c-c++-common/asan/red-align-1.c
new file mode 100644
index 000..1edb3a2
--- /dev/null
+++ b/gcc/testsuite/c-c++-common/asan/red-align-1.c
@@ -0,0 +1,20 @@
+/* This tests aligment propagation to structure elem and
+ abcense of redudant & 7. */
+
+/* { dg-options "-fdump-tree-sanopt" } */
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-flto" } { "" } } */
+
+struct st {
+ int a;
+ int b;
+ int c;
+} __attribute__((aligned(16)));
+
+int foo (struct st * s_p)
+{
+ return s_p->a;
+}
+
+/* { dg-final { scan-tree-dump-times "& 7" 0 "sanopt" } } */
+/* { dg-final { cleanup-tree-dump "sanopt" } } */
diff --git a/gcc/testsuite/c-c++-common/asan/red-align-2.c b/gcc/testsuite/c-c++-common/asan/red-align-2.c
new file mode 100644
index 000..161fe3c
--- /dev/null
+++ b/gcc/testsuite/c-c++-common/asan/red-align-2.c
@@ -0,0 +1,20 @@
+/* This tests aligment propagation to structure elem and
+ abcense of redudant & 7. */
+
+/* { dg-options "-fdump-tree-sanopt" } */
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-flto" } { "" } } */
+
+struct st {
+ int a;
+ int b;
+ int c;
+} __attribute__((aligned(16)));
+
+int foo (struct st * s_p)
+{
+ return s_p->b;
+}
+
+/* { dg-final { scan-tree-dump-times "& 7" 1 "sanopt" } } */
+/* { dg-final { cleanup-tree-dump "sanopt" } } */
[PATCH] Asan optimization for aligned accesses.
Sorry for wrong subject!
On 09/02/2014 07:03 PM, Marat Zakirov wrote:
Hi all!
Here's a simple optimization patch for Asan. It stores alignment
information into ASAN_CHECK which is then extracted by sanopt to
reduce number of "and 0x7" instructions for sufficiently aligned
accesses. I checked it on linux kernel by comparing results of objdump
-d -j .text vmlinux | grep "and.*0x7," for optimized and regular
cases. It eliminates 12% of and 0x7's.
No regressions. Sanitized GCC was successfully Asan-bootstrapped. No
false positives were found in kernel.
--Marat
gcc/ChangeLog:
2014-09-02 Marat Zakirov
* asan.c (build_check_stmt): Alignment arg was added.
(asan_expand_check_ifn): Optimization for alignment >= 8.
gcc/testsuite/ChangeLog:
2014-09-02 Marat Zakirov
* c-c++-common/asan/red-align-1.c: New test.
* c-c++-common/asan/red-align-2.c: New test.
diff --git a/gcc/asan.c b/gcc/asan.c
index 58e7719..aed5ede 100644
--- a/gcc/asan.c
+++ b/gcc/asan.c
@@ -1639,9 +1639,11 @@ build_check_stmt (location_t loc, tree base, tree len,
if (end_instrumented)
flags |= ASAN_CHECK_END_INSTRUMENTED;
- g = gimple_build_call_internal (IFN_ASAN_CHECK, 3,
+ g = gimple_build_call_internal (IFN_ASAN_CHECK, 4,
build_int_cst (integer_type_node, flags),
- base, len);
+ base, len,
+ build_int_cst (integer_type_node,
+ align/BITS_PER_UNIT));
gimple_set_location (g, loc);
if (before_p)
gsi_insert_before (&gsi, g, GSI_SAME_STMT);
@@ -2434,6 +2436,7 @@ asan_expand_check_ifn (gimple_stmt_iterator *iter, bool use_calls)
tree base = gimple_call_arg (g, 1);
tree len = gimple_call_arg (g, 2);
+ HOST_WIDE_INT align = tree_to_shwi (gimple_call_arg (g, 3));
HOST_WIDE_INT size_in_bytes
= is_scalar_access && tree_fits_shwi_p (len) ? tree_to_shwi (len) : -1;
@@ -2547,7 +2550,10 @@ asan_expand_check_ifn (gimple_stmt_iterator *iter, bool use_calls)
gimple shadow_test = build_assign (NE_EXPR, shadow, 0);
gimple_seq seq = NULL;
gimple_seq_add_stmt (&seq, shadow_test);
- gimple_seq_add_stmt (&seq, build_assign (BIT_AND_EXPR, base_addr, 7));
+ /* Aligned (>= 8 bytes) access do not need & 7. */
+ if (align < 8)
+ gimple_seq_add_stmt (&seq, build_assign (BIT_AND_EXPR,
+ base_addr, 7));
gimple_seq_add_stmt (&seq, build_type_cast (shadow_type,
gimple_seq_last (seq)));
if (real_size_in_bytes > 1)
diff --git a/gcc/internal-fn.def b/gcc/internal-fn.def
index 7ae60f3..54ade9f 100644
--- a/gcc/internal-fn.def
+++ b/gcc/internal-fn.def
@@ -55,4 +55,4 @@ DEF_INTERNAL_FN (UBSAN_CHECK_SUB, ECF_CONST | ECF_LEAF | ECF_NOTHROW, NULL)
DEF_INTERNAL_FN (UBSAN_CHECK_MUL, ECF_CONST | ECF_LEAF | ECF_NOTHROW, NULL)
DEF_INTERNAL_FN (ABNORMAL_DISPATCHER, ECF_NORETURN, NULL)
DEF_INTERNAL_FN (BUILTIN_EXPECT, ECF_CONST | ECF_LEAF | ECF_NOTHROW, NULL)
-DEF_INTERNAL_FN (ASAN_CHECK, ECF_TM_PURE | ECF_LEAF | ECF_NOTHROW, ".W..")
+DEF_INTERNAL_FN (ASAN_CHECK, ECF_TM_PURE | ECF_LEAF | ECF_NOTHROW, ".W...")
diff --git a/gcc/testsuite/c-c++-common/asan/red-align-1.c b/gcc/testsuite/c-c++-common/asan/red-align-1.c
new file mode 100644
index 000..1edb3a2
--- /dev/null
+++ b/gcc/testsuite/c-c++-common/asan/red-align-1.c
@@ -0,0 +1,20 @@
+/* This tests aligment propagation to structure elem and
+ abcense of redudant & 7. */
+
+/* { dg-options "-fdump-tree-sanopt" } */
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-flto" } { "" } } */
+
+struct st {
+ int a;
+ int b;
+ int c;
+} __attribute__((aligned(16)));
+
+int foo (struct st * s_p)
+{
+ return s_p->a;
+}
+
+/* { dg-final { scan-tree-dump-times "& 7" 0 "sanopt" } } */
+/* { dg-final { cleanup-tree-dump "sanopt" } } */
diff --git a/gcc/testsuite/c-c++-common/asan/red-align-2.c b/gcc/testsuite/c-c++-common/asan/red-align-2.c
new file mode 100644
index 000..161fe3c
--- /dev/null
+++ b/gcc/testsuite/c-c++-common/asan/red-align-2.c
@@ -0,0 +1,20 @@
+/* This tests aligment propagation to structure elem and
+ abcense of redudant & 7. */
+
+/* { dg-options "-fdump-tree-sanopt" } */
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-flto" } { "" } } */
+
+struct st {
+ int a;
+ int b;
+ int c;
+} __attribute__((aligned(16)));
+
+int foo (struct st * s_p)
+{
+ return s_p->b;
+}
+
+/* { dg-final { scan-tree-dump-times "& 7" 1 "sanopt" } } */
+/* { dg-final { cleanup-tree-dump "sanopt" } } */
Re: [PINGv4][PATCHv3] Fix vector tests on ARM platforms with disabled unaligned accesses
On 09/04/2014 09:23 PM, Mike Stump wrote:
On Sep 4, 2014, at 4:14 AM, Ramana Radhakrishnan
wrote:
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -2293,8 +2293,8 @@ proc check_effective_target_arm_little_endian { } {
proc check_effective_target_arm_vect_no_misalign { } {
return [check_no_compiler_messages arm_vect_no_misalign assembly {
#if !defined(__arm__) \
- || (defined(__ARMEL__) \
- && (!defined(__thumb__) || defined(__thumb2__)))
+ || (defined(__ARM_FEATURE_UNALIGNED) \
+ && defined(__ARMEL__))
#error FOO
#endif
}]
Ok by me. But please wait for a testsuite maintainer to approve.
Ok.
Generally the port people that have been around for a while know what strikes
them as wrong or not and can just approve the patch directly. I suspect you
are one of those people. :-) If you have any doubts or concerns, you can
always raise them or ask for some help reviewing. Don’t worry, if I spot
something I don’t like after someone else says Ok, I will bring up the issue
for consideration. Even if I do, it doesn’t mean I object in anyway to the
first review.
Thank you all.
Committed revision 214956.
--Marat
gcc/testsuite/ChangeLog:
2014-07-23 Marat Zakirov
* gcc.dg/vect/vect-109.c: Skip predicate added.
* gcc.dg/vect/vect-93.c: Test check fixed.
* gcc.dg/vect/bb-slp-10.c: Likewise.
* lib/target-supports.exp (check_effective_target_arm_vect_no_misalign):
Check unaligned feature.
diff --git a/gcc/testsuite/gcc.dg/vect/bb-slp-10.c b/gcc/testsuite/gcc.dg/vect/bb-slp-10.c
index a1850ed..0090a4b 100644
--- a/gcc/testsuite/gcc.dg/vect/bb-slp-10.c
+++ b/gcc/testsuite/gcc.dg/vect/bb-slp-10.c
@@ -49,7 +49,7 @@ int main (void)
return 0;
}
-/* { dg-final { scan-tree-dump-times "unsupported alignment in basic block." 1 "slp2" { xfail vect_element_align } } } */
+/* { dg-final { scan-tree-dump "unsupported alignment in basic block." "slp2" { xfail vect_element_align } } } */
/* { dg-final { scan-tree-dump-times "basic block vectorized" 1 "slp2" { target vect_element_align } } } */
/* { dg-final { cleanup-tree-dump "slp2" } } */
diff --git a/gcc/testsuite/gcc.dg/vect/vect-109.c b/gcc/testsuite/gcc.dg/vect/vect-109.c
index 854c970..c671175 100644
--- a/gcc/testsuite/gcc.dg/vect/vect-109.c
+++ b/gcc/testsuite/gcc.dg/vect/vect-109.c
@@ -1,3 +1,4 @@
+/* { dg-skip-if "" { vect_no_align } } */
/* { dg-require-effective-target vect_int } */
#include
diff --git a/gcc/testsuite/gcc.dg/vect/vect-93.c b/gcc/testsuite/gcc.dg/vect/vect-93.c
index 65403eb..1065a6e 100644
--- a/gcc/testsuite/gcc.dg/vect/vect-93.c
+++ b/gcc/testsuite/gcc.dg/vect/vect-93.c
@@ -79,7 +79,7 @@ int main (void)
/* { dg-final { scan-tree-dump-times "vectorized 2 loops" 1 "vect" { target vect_no_align } } } */
/* in main: */
-/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" { target vect_no_align } } } */
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_no_align } } } */
/* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 1 "vect" { xfail { vect_no_align } } } } */
/* { dg-final { cleanup-tree-dump "vect" } } */
diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
index db65ebe..35076d2 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -2293,8 +2293,8 @@ proc check_effective_target_arm_little_endian { } {
proc check_effective_target_arm_vect_no_misalign { } {
return [check_no_compiler_messages arm_vect_no_misalign assembly {
#if !defined(__arm__) \
- || (defined(__ARMEL__) \
- && (!defined(__thumb__) || defined(__thumb2__)))
+ || (defined(__ARM_FEATURE_UNALIGNED) \
+ && defined(__ARMEL__))
#error FOO
#endif
}]
[PING v2][PATCH] Support for BIT_FIELD_REF in asan.c
On 10/03/2014 10:47 AM, Marat Zakirov wrote:
On 09/26/2014 12:55 PM, Marat Zakirov wrote:
Hi all!
Here's a patch which instruments byte-aligned BIT_FIELD_REFs. During
GCC asan-bootstrap and Linux kernel build I didn't find any cases
where BIT_FIELD_REF is not 8 bits aligned. But I do not have
sufficient confidence to replace current return if BIT_FIELD_REF is
misaligned to assert.
Ok to commit?
--Marat
gcc/ChangeLog:
2014-09-19 Marat Zakirov
* asan.c (instrument_derefs): BIT_FIELD_REF added.
gcc/testsuite/ChangeLog:
2014-09-19 Marat Zakirov
* c-c++-common/asan/bitfield-5.c: New test.
diff --git a/gcc/asan.c b/gcc/asan.c
index cf5de27..451af33 100644
--- a/gcc/asan.c
+++ b/gcc/asan.c
@@ -1705,6 +1705,7 @@ instrument_derefs (gimple_stmt_iterator *iter, tree t,
case INDIRECT_REF:
case MEM_REF:
case VAR_DECL:
+case BIT_FIELD_REF:
break;
/* FALLTHRU */
default:
diff --git a/gcc/testsuite/c-c++-common/asan/bitfield-5.c b/gcc/testsuite/c-c++-common/asan/bitfield-5.c
new file mode 100644
index 000..eb5e9e9
--- /dev/null
+++ b/gcc/testsuite/c-c++-common/asan/bitfield-5.c
@@ -0,0 +1,24 @@
+/* Check BIT_FIELD_REF. */
+
+/* { dg-do run } */
+/* { dg-shouldfail "asan" } */
+
+struct A
+{
+ int y : 20;
+ int x : 13;
+};
+
+int __attribute__ ((noinline, noclone))
+f (void *p) {
+ return ((struct A *)p)->x != 0;
+}
+
+int
+main ()
+{
+ int a = 0;
+ return f (&a);
+}
+
+/* { dg-output "ERROR: AddressSanitizer: stack-buffer-overflow" } */
[PATCH] Fix for PR 61422
Hi all, Here's a patch for PR 61422 (https://gcc.gnu.org/bugzilla/show_bug.cgi?id=61422). It fixes false positive on 16 byte access in ffmpeg standard library opus file NLSF_del_dec_quant.c. Reg. tested on x64. --Marat PR61422.diff Description: Binary data
[PATCH][PING] Fix for PR 61422
-Original Message- From: Marat Zakirov [mailto:m.zaki...@samsung.com] Sent: Friday, June 06, 2014 3:43 PM To: 'gcc-patches@gcc.gnu.org' Cc: 'Konstantin Serebryany'; 'Jakub Jelinek'; 'Slava Garbuzov'; Gribov Yury; 'Marat Zakirov' Subject: [PATCH] Fix for PR 61422 Hi all, Here's a patch for PR 61422 (https://gcc.gnu.org/bugzilla/show_bug.cgi?id=61422). It fixes false positive on 16 byte access in ffmpeg standard library opus file NLSF_del_dec_quant.c. Reg. tested on x64. --Marat PR61422.diff Description: Binary data
[PATCH] Fix for PR 61561
Hi all, Here's a patch for PR 61561 (https://gcc.gnu.org/bugzilla/show_bug.cgi?id=61561). It fixes ICE. Reg. tested on arm15. --Marat arm.md.diff.diff Description: Binary data
[PATCH] Fix for PR 61561
Hi all, Here's my new patch for PR 61561 (https://gcc.gnu.org/bugzilla/show_bug.cgi?id=61561). Which fixes ICE appeared due to QI/HI pattern lack in arm.md for stack pointer register. Reg. tested on arm-v7. --Marat arm.diff Description: Binary data
[PING][PATCH] Fix for PR 61561
This is a reminder message on fix for PR 61561 which is ICE while
compiling something which is valid* 'C' code.
(https://gcc.gnu.org/bugzilla/show_bug.cgi?id=61561).
Ramana, Richard, I am very appreciated for your attention and error
indication, your work made my patch simple and tiny. And I hope that
this patch will save somebody's time.
Additional info about the issue:
By adding constrain 'k' we want to make gcc work properly with stack
register in HI and QI mode. This is need because CSE an RTL phase in
some cases propagates sp register directly to HI/QI memory set. Next
reload an RTL phase trying to build HI/QI move sp into some general
purpose register which is fail due to pattern absence. You may ask who
needs part of sp register? Nevertheless it is legitimate operation and
there is simple example of practical usage. Imagine you put some local
variable 'a' into hash table which has < 256 bunches. In this case
'operator []' of some hash class may take QI from sp register which is
directly pointing on 'a'.
Patch was reg. tested on --build=x86_64-pc-linux-gnu
--host=x86_64-pc-linux-gnu --target=arm-v7a15v5r2-linux-gnueabi for
c,c++,fortran languages w/o bootstrap.
* According to 'C' Standard [ISO/IEC 9899:2011] 6.3.2.3
"Any pointer type may be converted to an integer type. Except as
previously specified, the result is implementation-defined". As we know
'char' and 'short' (also called 'short int') are both integers.
Thank for your attention.
Marat.
gcc/ChangeLog:
2014-06-30 Marat Zakirov
PR target/61561
* config/arm/arm.md (*movhi_insn_arch4): Handle stack pointer.
(*movhi_bytes): Likewise.
(*arm_movqi_insn): Likewise.
gcc/testsuite/ChangeLog:
2014-06-30 Marat Zakirov
PR target/61561
* gcc.dg/pr61561.c: New test.
diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index 42c12c8..99290dc 100644
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -6291,7 +6291,7 @@
;; Pattern to recognize insn generated default case above
(define_insn "*movhi_insn_arch4"
[(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r")
- (match_operand:HI 1 "general_operand" "rI,K,r,mi"))]
+ (match_operand:HI 1 "general_operand" "rIk,K,r,mi"))]
"TARGET_ARM
&& arm_arch4
&& (register_operand (operands[0], HImode)
@@ -6315,7 +6315,7 @@
(define_insn "*movhi_bytes"
[(set (match_operand:HI 0 "s_register_operand" "=r,r,r")
- (match_operand:HI 1 "arm_rhs_operand" "I,r,K"))]
+ (match_operand:HI 1 "arm_rhs_operand" "I,rk,K"))]
"TARGET_ARM"
"@
mov%?\\t%0, %1\\t%@ movhi
@@ -6430,7 +6430,7 @@
(define_insn "*arm_movqi_insn"
[(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,r,l,r,l,Uu,r,m")
- (match_operand:QI 1 "general_operand" "r,r,I,Py,K,Uu,l,m,r"))]
+ (match_operand:QI 1 "general_operand" "rk,rk,I,Py,K,Uu,l,m,r"))]
"TARGET_32BIT
&& ( register_operand (operands[0], QImode)
|| register_operand (operands[1], QImode))"
diff --git a/gcc/testsuite/gcc.dg/pr61561.c b/gcc/testsuite/gcc.dg/pr61561.c
new file mode 100644
index 000..0f4b716
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/pr61561.c
@@ -0,0 +1,15 @@
+/* PR c/61561. */
+/* { dg-do assemble } */
+/* { dg-options " -w -O2" } */
+
+int dummy (int a);
+
+char a;
+short b;
+
+void mmm (void)
+{
+ char dyn[dummy (3)];
+ a = (char)&dyn[0];
+ b = (short)&dyn[0];
+}
[PINGv6][PATCH] ASan on unaligned accesses
On 04/07/2015 03:22 PM, Jakub Jelinek wrote:
How are the automatic misaligned variables different from say heap
allocated ones, or global vars etc.?
No difference you are right Jakub. Shadow memory initialization for heap
values and globals of course also should be changed but it is a task for
libsanitizer not ASan for which I am sending patch. Fix for libsanitizer
to support unaligned heaps and globals will be committed by a separate
patch.
Well, a RTL solution I've tried at http://gcc.gnu.org/PR22141, but it gave
mixed results, so either it needs more cost tuning when it is desirable and
when it is not, or perhaps better do that still on GIMPLE instead, together
with trying to optimize bitfield accesses and other cases of adjacent
location accesses. But if we handle that on GIMPLE, it won't really affect
what asan RTL emitting code produces.
Jakub
I fixed the issue with 'movq' you were mentioned in a previous mail.
--Marat
gcc/ChangeLog:
2015-02-25 Marat Zakirov
* asan.c (asan_emit_stack_protection): Support for misalign accesses.
(asan_expand_check_ifn): Likewise.
* params.def: New option asan-catch-misaligned.
* params.h: New param ASAN_CATCH_MISALIGNED.
* doc/invoke.texi: New asan param description.
gcc/testsuite/ChangeLog:
2015-02-25 Marat Zakirov
* c-c++-common/asan/misalign-catch.c: New test.
diff --git a/gcc/asan.c b/gcc/asan.c
index 9e4a629..f9d052f 100644
--- a/gcc/asan.c
+++ b/gcc/asan.c
@@ -1050,7 +1050,6 @@ asan_emit_stack_protection (rtx base, rtx pbase, unsigned int alignb,
rtx_code_label *lab;
rtx_insn *insns;
char buf[30];
- unsigned char shadow_bytes[4];
HOST_WIDE_INT base_offset = offsets[length - 1];
HOST_WIDE_INT base_align_bias = 0, offset, prev_offset;
HOST_WIDE_INT asan_frame_size = offsets[0] - base_offset;
@@ -1059,6 +1058,8 @@ asan_emit_stack_protection (rtx base, rtx pbase, unsigned int alignb,
unsigned char cur_shadow_byte = ASAN_STACK_MAGIC_LEFT;
tree str_cst, decl, id;
int use_after_return_class = -1;
+ bool misalign = (flag_sanitize & SANITIZE_KERNEL_ADDRESS)
+ || ASAN_CATCH_MISALIGNED;
if (shadow_ptr_types[0] == NULL_TREE)
asan_init_shadow_ptr_types ();
@@ -1193,11 +1194,37 @@ asan_emit_stack_protection (rtx base, rtx pbase, unsigned int alignb,
if (STRICT_ALIGNMENT)
set_mem_align (shadow_mem, (GET_MODE_ALIGNMENT (SImode)));
prev_offset = base_offset;
+
+ vec shadow_mems;
+ vec shadow_bytes;
+
+ shadow_mems.create (0);
+ shadow_bytes.create (0);
+
for (l = length; l; l -= 2)
{
if (l == 2)
cur_shadow_byte = ASAN_STACK_MAGIC_RIGHT;
offset = offsets[l - 1];
+ if (l != length && misalign)
+ {
+ HOST_WIDE_INT aoff
+ = base_offset + ((offset - base_offset)
+ & ~(ASAN_RED_ZONE_SIZE - HOST_WIDE_INT_1))
+ - ASAN_RED_ZONE_SIZE;
+ if (aoff > prev_offset)
+ {
+ shadow_mem = adjust_address (shadow_mem, VOIDmode,
+ (aoff - prev_offset)
+ >> ASAN_SHADOW_SHIFT);
+ prev_offset = aoff;
+ shadow_bytes.safe_push (0);
+ shadow_bytes.safe_push (0);
+ shadow_bytes.safe_push (0);
+ shadow_bytes.safe_push (0);
+ shadow_mems.safe_push (shadow_mem);
+ }
+ }
if ((offset - base_offset) & (ASAN_RED_ZONE_SIZE - 1))
{
int i;
@@ -1212,13 +1239,13 @@ asan_emit_stack_protection (rtx base, rtx pbase, unsigned int alignb,
if (aoff < offset)
{
if (aoff < offset - (1 << ASAN_SHADOW_SHIFT) + 1)
- shadow_bytes[i] = 0;
+ shadow_bytes.safe_push (0);
else
- shadow_bytes[i] = offset - aoff;
+ shadow_bytes.safe_push (offset - aoff);
}
else
- shadow_bytes[i] = ASAN_STACK_MAGIC_PARTIAL;
- emit_move_insn (shadow_mem, asan_shadow_cst (shadow_bytes));
+ shadow_bytes.safe_push (ASAN_STACK_MAGIC_PARTIAL);
+ shadow_mems.safe_push (shadow_mem);
offset = aoff;
}
while (offset <= offsets[l - 2] - ASAN_RED_ZONE_SIZE)
@@ -1227,12 +1254,21 @@ asan_emit_stack_protection (rtx base, rtx pbase, unsigned int alignb,
(offset - prev_offset)
>> ASAN_SHADOW_SHIFT);
prev_offset = offset;
- memset (shadow_bytes, cur_shadow_byte, 4);
- emit_move_insn (shadow_mem, asan_shadow_cst (shadow_bytes));
+ shadow_bytes.safe_push (cur_shadow_byte);
+ shadow_bytes.safe_push (cur_shadow_byte);
+ shadow_bytes.safe_push (cur_shadow_byte);
+ shadow_bytes.safe_push (cur_shadow_byte);
+ shadow_mems.safe_push (shadow_mem);
offset += ASAN_RED_ZONE_SIZE;
}
cur_shadow_byte = ASAN_STACK_MAGIC_MIDDLE;
}
+ for (unsigned i = 0; misalign && i < shadow_bytes.length () - 1; i++)
+if (shadow_bytes[i] == 0 && shadow_bytes[i + 1] > 0)
+ shadow_bytes[i] = 8 + (shadow_bytes[i + 1] > 7 ? 0 : shadow_bytes[i + 1]);
+ for (unsigned i = 0; i < shadow_mems.length (); i++)
+emit_move_insn (shadow_mems[i], as
[PINGv7][PATCH] ASan on unaligned accesses
On 05/12/2015 02:16 PM, Marat Zakirov wrote:
On 04/07/2015 03:22 PM, Jakub Jelinek wrote:
How are the automatic misaligned variables different from say heap
allocated ones, or global vars etc.?
No difference you are right Jakub. Shadow memory initialization for
heap values and globals of course also should be changed but it is a
task for libsanitizer not ASan for which I am sending patch. Fix for
libsanitizer to support unaligned heaps and globals will be committed
by a separate patch.
Well, a RTL solution I've tried at http://gcc.gnu.org/PR22141, but it
gave
mixed results, so either it needs more cost tuning when it is
desirable and
when it is not, or perhaps better do that still on GIMPLE instead,
together
with trying to optimize bitfield accesses and other cases of adjacent
location accesses. But if we handle that on GIMPLE, it won't really
affect
what asan RTL emitting code produces.
Jakub
I fixed the issue with 'movq' you were mentioned in a previous mail.
--Marat
gcc/ChangeLog:
2015-02-25 Marat Zakirov
* asan.c (asan_emit_stack_protection): Support for misalign accesses.
(asan_expand_check_ifn): Likewise.
* params.def: New option asan-catch-misaligned.
* params.h: New param ASAN_CATCH_MISALIGNED.
* doc/invoke.texi: New asan param description.
gcc/testsuite/ChangeLog:
2015-02-25 Marat Zakirov
* c-c++-common/asan/misalign-catch.c: New test.
diff --git a/gcc/asan.c b/gcc/asan.c
index 9e4a629..f9d052f 100644
--- a/gcc/asan.c
+++ b/gcc/asan.c
@@ -1050,7 +1050,6 @@ asan_emit_stack_protection (rtx base, rtx pbase, unsigned int alignb,
rtx_code_label *lab;
rtx_insn *insns;
char buf[30];
- unsigned char shadow_bytes[4];
HOST_WIDE_INT base_offset = offsets[length - 1];
HOST_WIDE_INT base_align_bias = 0, offset, prev_offset;
HOST_WIDE_INT asan_frame_size = offsets[0] - base_offset;
@@ -1059,6 +1058,8 @@ asan_emit_stack_protection (rtx base, rtx pbase, unsigned int alignb,
unsigned char cur_shadow_byte = ASAN_STACK_MAGIC_LEFT;
tree str_cst, decl, id;
int use_after_return_class = -1;
+ bool misalign = (flag_sanitize & SANITIZE_KERNEL_ADDRESS)
+ || ASAN_CATCH_MISALIGNED;
if (shadow_ptr_types[0] == NULL_TREE)
asan_init_shadow_ptr_types ();
@@ -1193,11 +1194,37 @@ asan_emit_stack_protection (rtx base, rtx pbase, unsigned int alignb,
if (STRICT_ALIGNMENT)
set_mem_align (shadow_mem, (GET_MODE_ALIGNMENT (SImode)));
prev_offset = base_offset;
+
+ vec shadow_mems;
+ vec shadow_bytes;
+
+ shadow_mems.create (0);
+ shadow_bytes.create (0);
+
for (l = length; l; l -= 2)
{
if (l == 2)
cur_shadow_byte = ASAN_STACK_MAGIC_RIGHT;
offset = offsets[l - 1];
+ if (l != length && misalign)
+ {
+ HOST_WIDE_INT aoff
+ = base_offset + ((offset - base_offset)
+ & ~(ASAN_RED_ZONE_SIZE - HOST_WIDE_INT_1))
+ - ASAN_RED_ZONE_SIZE;
+ if (aoff > prev_offset)
+ {
+ shadow_mem = adjust_address (shadow_mem, VOIDmode,
+ (aoff - prev_offset)
+ >> ASAN_SHADOW_SHIFT);
+ prev_offset = aoff;
+ shadow_bytes.safe_push (0);
+ shadow_bytes.safe_push (0);
+ shadow_bytes.safe_push (0);
+ shadow_bytes.safe_push (0);
+ shadow_mems.safe_push (shadow_mem);
+ }
+ }
if ((offset - base_offset) & (ASAN_RED_ZONE_SIZE - 1))
{
int i;
@@ -1212,13 +1239,13 @@ asan_emit_stack_protection (rtx base, rtx pbase, unsigned int alignb,
if (aoff < offset)
{
if (aoff < offset - (1 << ASAN_SHADOW_SHIFT) + 1)
- shadow_bytes[i] = 0;
+ shadow_bytes.safe_push (0);
else
- shadow_bytes[i] = offset - aoff;
+ shadow_bytes.safe_push (offset - aoff);
}
else
- shadow_bytes[i] = ASAN_STACK_MAGIC_PARTIAL;
- emit_move_insn (shadow_mem, asan_shadow_cst (shadow_bytes));
+ shadow_bytes.safe_push (ASAN_STACK_MAGIC_PARTIAL);
+ shadow_mems.safe_push (shadow_mem);
offset = aoff;
}
while (offset <= offsets[l - 2] - ASAN_RED_ZONE_SIZE)
@@ -1227,12 +1254,21 @@ asan_emit_stack_protection (rtx base, rtx pbase, unsigned int alignb,
(offset - prev_offset)
>> ASAN_SHADOW_SHIFT);
prev_offset = offset;
- memset (shadow_bytes, cur_shadow_byte, 4);
- emit_move_insn (shadow_mem, asan_shadow_cst (shadow_bytes));
+ shadow_bytes.safe_push (cur_shadow_byte);
+ shadow_bytes.safe_push (cur_shadow_byte);
+ shadow_bytes.safe_push (cur_shadow_byte);
+ shadow_bytes.safe_push (cur_shadow_byte);
+ shadow_mems.safe_push (shadow_mem);
offset += ASAN_RED_ZONE_SIZE;
}
cur_shadow_byte = ASAN_STACK_MAGIC_MIDDLE;
}
+ for (unsigned i = 0; misalign && i < shadow_bytes.length () - 1; i++)
+if (shadow_bytes[i] == 0 && shadow_bytes[i + 1] > 0)
+ shadow_bytes[i] = 8 + (shadow_bytes[i + 1] > 7 ? 0 : shadow_bytes[i + 1]);
+ for (unsigned i = 0; i < sha
[PINGv8][PATCH] ASan on unaligned accesses
On 05/20/2015 10:01 AM, Marat Zakirov wrote:
On 05/12/2015 02:16 PM, Marat Zakirov wrote:
On 04/07/2015 03:22 PM, Jakub Jelinek wrote:
How are the automatic misaligned variables different from say heap
allocated ones, or global vars etc.?
No difference you are right Jakub. Shadow memory initialization for
heap values and globals of course also should be changed but it is a
task for libsanitizer not ASan for which I am sending patch. Fix for
libsanitizer to support unaligned heaps and globals will be committed
by a separate patch.
Well, a RTL solution I've tried at http://gcc.gnu.org/PR22141, but
it gave
mixed results, so either it needs more cost tuning when it is
desirable and
when it is not, or perhaps better do that still on GIMPLE instead,
together
with trying to optimize bitfield accesses and other cases of adjacent
location accesses. But if we handle that on GIMPLE, it won't really
affect
what asan RTL emitting code produces.
Jakub
I fixed the issue with 'movq' you were mentioned in a previous mail.
--Marat
gcc/ChangeLog:
2015-02-25 Marat Zakirov
* asan.c (asan_emit_stack_protection): Support for misalign accesses.
(asan_expand_check_ifn): Likewise.
* params.def: New option asan-catch-misaligned.
* params.h: New param ASAN_CATCH_MISALIGNED.
* doc/invoke.texi: New asan param description.
gcc/testsuite/ChangeLog:
2015-02-25 Marat Zakirov
* c-c++-common/asan/misalign-catch.c: New test.
diff --git a/gcc/asan.c b/gcc/asan.c
index 9e4a629..f9d052f 100644
--- a/gcc/asan.c
+++ b/gcc/asan.c
@@ -1050,7 +1050,6 @@ asan_emit_stack_protection (rtx base, rtx pbase, unsigned int alignb,
rtx_code_label *lab;
rtx_insn *insns;
char buf[30];
- unsigned char shadow_bytes[4];
HOST_WIDE_INT base_offset = offsets[length - 1];
HOST_WIDE_INT base_align_bias = 0, offset, prev_offset;
HOST_WIDE_INT asan_frame_size = offsets[0] - base_offset;
@@ -1059,6 +1058,8 @@ asan_emit_stack_protection (rtx base, rtx pbase, unsigned int alignb,
unsigned char cur_shadow_byte = ASAN_STACK_MAGIC_LEFT;
tree str_cst, decl, id;
int use_after_return_class = -1;
+ bool misalign = (flag_sanitize & SANITIZE_KERNEL_ADDRESS)
+ || ASAN_CATCH_MISALIGNED;
if (shadow_ptr_types[0] == NULL_TREE)
asan_init_shadow_ptr_types ();
@@ -1193,11 +1194,37 @@ asan_emit_stack_protection (rtx base, rtx pbase, unsigned int alignb,
if (STRICT_ALIGNMENT)
set_mem_align (shadow_mem, (GET_MODE_ALIGNMENT (SImode)));
prev_offset = base_offset;
+
+ vec shadow_mems;
+ vec shadow_bytes;
+
+ shadow_mems.create (0);
+ shadow_bytes.create (0);
+
for (l = length; l; l -= 2)
{
if (l == 2)
cur_shadow_byte = ASAN_STACK_MAGIC_RIGHT;
offset = offsets[l - 1];
+ if (l != length && misalign)
+ {
+ HOST_WIDE_INT aoff
+ = base_offset + ((offset - base_offset)
+ & ~(ASAN_RED_ZONE_SIZE - HOST_WIDE_INT_1))
+ - ASAN_RED_ZONE_SIZE;
+ if (aoff > prev_offset)
+ {
+ shadow_mem = adjust_address (shadow_mem, VOIDmode,
+ (aoff - prev_offset)
+ >> ASAN_SHADOW_SHIFT);
+ prev_offset = aoff;
+ shadow_bytes.safe_push (0);
+ shadow_bytes.safe_push (0);
+ shadow_bytes.safe_push (0);
+ shadow_bytes.safe_push (0);
+ shadow_mems.safe_push (shadow_mem);
+ }
+ }
if ((offset - base_offset) & (ASAN_RED_ZONE_SIZE - 1))
{
int i;
@@ -1212,13 +1239,13 @@ asan_emit_stack_protection (rtx base, rtx pbase, unsigned int alignb,
if (aoff < offset)
{
if (aoff < offset - (1 << ASAN_SHADOW_SHIFT) + 1)
- shadow_bytes[i] = 0;
+ shadow_bytes.safe_push (0);
else
- shadow_bytes[i] = offset - aoff;
+ shadow_bytes.safe_push (offset - aoff);
}
else
- shadow_bytes[i] = ASAN_STACK_MAGIC_PARTIAL;
- emit_move_insn (shadow_mem, asan_shadow_cst (shadow_bytes));
+ shadow_bytes.safe_push (ASAN_STACK_MAGIC_PARTIAL);
+ shadow_mems.safe_push (shadow_mem);
offset = aoff;
}
while (offset <= offsets[l - 2] - ASAN_RED_ZONE_SIZE)
@@ -1227,12 +1254,21 @@ asan_emit_stack_protection (rtx base, rtx pbase, unsigned int alignb,
(offset - prev_offset)
>> ASAN_SHADOW_SHIFT);
prev_offset = offset;
- memset (shadow_bytes, cur_shadow_byte, 4);
- emit_move_insn (shadow_mem, asan_shadow_cst (shadow_bytes));
+ shadow_bytes.safe_push (cur_shadow_byte);
+ shadow_bytes.safe_push (cur_shadow_byte);
+ shadow_bytes.safe_push (cur_shadow_byte);
+ shadow_bytes.safe_push (cur_shadow_byte);
+ shadow_mems.safe_push (shadow_mem);
offset += ASAN_RED_ZONE_SIZE;
}
cur_shadow_byte = ASAN_STACK_MAGIC_MIDDLE;
}
+ for (unsigned i = 0; misalign && i < shadow_bytes.length () - 1; i++)
+if (shadow_bytes[i] == 0 && shadow_bytes[i + 1] > 0)
+ shadow_bytes[i] = 8 + (shadow_bytes[i + 1] > 7 ? 0 : shadow_bytes[i +
[PINGv9][PATCH] ASan on unaligned accesses
On 05/26/2015 05:03 PM, Marat Zakirov wrote:
On 05/20/2015 10:01 AM, Marat Zakirov wrote:
On 05/12/2015 02:16 PM, Marat Zakirov wrote:
On 04/07/2015 03:22 PM, Jakub Jelinek wrote:
How are the automatic misaligned variables different from say heap
allocated ones, or global vars etc.?
No difference you are right Jakub. Shadow memory initialization for
heap values and globals of course also should be changed but it is a
task for libsanitizer not ASan for which I am sending patch. Fix for
libsanitizer to support unaligned heaps and globals will be
committed by a separate patch.
Well, a RTL solution I've tried at http://gcc.gnu.org/PR22141, but
it gave
mixed results, so either it needs more cost tuning when it is
desirable and
when it is not, or perhaps better do that still on GIMPLE instead,
together
with trying to optimize bitfield accesses and other cases of adjacent
location accesses. But if we handle that on GIMPLE, it won't
really affect
what asan RTL emitting code produces.
Jakub
I fixed the issue with 'movq' you were mentioned in a previous mail.
--Marat
gcc/ChangeLog:
2015-02-25 Marat Zakirov
* asan.c (asan_emit_stack_protection): Support for misalign accesses.
(asan_expand_check_ifn): Likewise.
* params.def: New option asan-catch-misaligned.
* params.h: New param ASAN_CATCH_MISALIGNED.
* doc/invoke.texi: New asan param description.
gcc/testsuite/ChangeLog:
2015-02-25 Marat Zakirov
* c-c++-common/asan/misalign-catch.c: New test.
diff --git a/gcc/asan.c b/gcc/asan.c
index 9e4a629..f9d052f 100644
--- a/gcc/asan.c
+++ b/gcc/asan.c
@@ -1050,7 +1050,6 @@ asan_emit_stack_protection (rtx base, rtx pbase, unsigned int alignb,
rtx_code_label *lab;
rtx_insn *insns;
char buf[30];
- unsigned char shadow_bytes[4];
HOST_WIDE_INT base_offset = offsets[length - 1];
HOST_WIDE_INT base_align_bias = 0, offset, prev_offset;
HOST_WIDE_INT asan_frame_size = offsets[0] - base_offset;
@@ -1059,6 +1058,8 @@ asan_emit_stack_protection (rtx base, rtx pbase, unsigned int alignb,
unsigned char cur_shadow_byte = ASAN_STACK_MAGIC_LEFT;
tree str_cst, decl, id;
int use_after_return_class = -1;
+ bool misalign = (flag_sanitize & SANITIZE_KERNEL_ADDRESS)
+ || ASAN_CATCH_MISALIGNED;
if (shadow_ptr_types[0] == NULL_TREE)
asan_init_shadow_ptr_types ();
@@ -1193,11 +1194,37 @@ asan_emit_stack_protection (rtx base, rtx pbase, unsigned int alignb,
if (STRICT_ALIGNMENT)
set_mem_align (shadow_mem, (GET_MODE_ALIGNMENT (SImode)));
prev_offset = base_offset;
+
+ vec shadow_mems;
+ vec shadow_bytes;
+
+ shadow_mems.create (0);
+ shadow_bytes.create (0);
+
for (l = length; l; l -= 2)
{
if (l == 2)
cur_shadow_byte = ASAN_STACK_MAGIC_RIGHT;
offset = offsets[l - 1];
+ if (l != length && misalign)
+ {
+ HOST_WIDE_INT aoff
+ = base_offset + ((offset - base_offset)
+ & ~(ASAN_RED_ZONE_SIZE - HOST_WIDE_INT_1))
+ - ASAN_RED_ZONE_SIZE;
+ if (aoff > prev_offset)
+ {
+ shadow_mem = adjust_address (shadow_mem, VOIDmode,
+ (aoff - prev_offset)
+ >> ASAN_SHADOW_SHIFT);
+ prev_offset = aoff;
+ shadow_bytes.safe_push (0);
+ shadow_bytes.safe_push (0);
+ shadow_bytes.safe_push (0);
+ shadow_bytes.safe_push (0);
+ shadow_mems.safe_push (shadow_mem);
+ }
+ }
if ((offset - base_offset) & (ASAN_RED_ZONE_SIZE - 1))
{
int i;
@@ -1212,13 +1239,13 @@ asan_emit_stack_protection (rtx base, rtx pbase, unsigned int alignb,
if (aoff < offset)
{
if (aoff < offset - (1 << ASAN_SHADOW_SHIFT) + 1)
- shadow_bytes[i] = 0;
+ shadow_bytes.safe_push (0);
else
- shadow_bytes[i] = offset - aoff;
+ shadow_bytes.safe_push (offset - aoff);
}
else
- shadow_bytes[i] = ASAN_STACK_MAGIC_PARTIAL;
- emit_move_insn (shadow_mem, asan_shadow_cst (shadow_bytes));
+ shadow_bytes.safe_push (ASAN_STACK_MAGIC_PARTIAL);
+ shadow_mems.safe_push (shadow_mem);
offset = aoff;
}
while (offset <= offsets[l - 2] - ASAN_RED_ZONE_SIZE)
@@ -1227,12 +1254,21 @@ asan_emit_stack_protection (rtx base, rtx pbase, unsigned int alignb,
(offset - prev_offset)
>> ASAN_SHADOW_SHIFT);
prev_offset = offset;
- memset (shadow_bytes, cur_shadow_byte, 4);
- emit_move_insn (shadow_mem, asan_shadow_cst (shadow_bytes));
+ shadow_bytes.safe_push (cur_shadow_byte);
+ shadow_bytes.safe_push (cur_shadow_byte);
+ shadow_bytes.safe_push (cur_shadow_byte);
+ shadow_bytes.safe_push (cur_shadow_byte);
+ shadow_mems.safe_push (shadow_mem);
offset += ASAN_RED_ZONE_SIZE;
}
cur_shadow_byte = ASAN_STACK_MAGIC_MIDDLE;
}
+ for (unsigned i = 0; misalign && i < shadow_bytes.length () - 1; i++)
+if (shadow_bytes[i] == 0 && shadow_bytes[i + 1] > 0)
+ shadow_bytes[i] = 8 + (shadow_bytes
[PATCH] Ignore alignment by option
Hi all!
Here is the patch which forces ASan to ignore alignment of memory
access. It increases ASan overhead but it's still useful because some
programs like linux kernel often cheat with alignment which may cause
false negatives.
--Marat
gcc/ChangeLog:
2014-11-14 Marat Zakirov
* asan.c (asan_expand_check_ifn): Ignore alignment by option.
* doc/invoke.texi: Document.
* params.def (asan-alignment-optimize): New.
* params.h: Likewise.
gcc/testsuite/ChangeLog:
2014-11-14 Marat Zakirov
* c-c++-common/asan/red-align-3.c: New test.
diff --git a/gcc/asan.c b/gcc/asan.c
index 79dede7..4f86088 100644
--- a/gcc/asan.c
+++ b/gcc/asan.c
@@ -2518,6 +2518,12 @@ asan_expand_check_ifn (gimple_stmt_iterator *iter, bool use_calls)
HOST_WIDE_INT size_in_bytes
= is_scalar_access && tree_fits_shwi_p (len) ? tree_to_shwi (len) : -1;
+
+ if (!ASAN_ALIGNMENT_OPTIMIZE && size_in_bytes > 1)
+{
+ size_in_bytes = -1;
+ align = 1;
+}
if (use_calls)
{
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 13270bc..8f43c06 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -10580,6 +10580,12 @@ is greater or equal to this number, use callbacks instead of inline checks.
E.g. to disable inline code use
@option{--param asan-instrumentation-with-call-threshold=0}.
+@item asan-alignment-optimize
+Enable asan optimization for aligned accesses.
+It is enabled by default when using @option{-fsanitize=address} option.
+To disable optimization for aligned accesses use
+@option{--param asan-alignment-optimize=0}.
+
@item chkp-max-ctor-size
Static constructors generated by Pointer Bounds Checker may become very
large and significantly increase compile time at optimization level
diff --git a/gcc/params.def b/gcc/params.def
index d2d2add..fbccf46 100644
--- a/gcc/params.def
+++ b/gcc/params.def
@@ -1114,6 +1114,11 @@ DEFPARAM (PARAM_ASAN_INSTRUMENTATION_WITH_CALL_THRESHOLD,
"in function becomes greater or equal to this number",
7000, 0, INT_MAX)
+DEFPARAM (PARAM_ASAN_ALIGNMENT_OPTIMIZE,
+ "asan-alignment-optimize",
+ "Enable asan optimization for aligned access",
+ 1, 0, 1)
+
DEFPARAM (PARAM_UNINIT_CONTROL_DEP_ATTEMPTS,
"uninit-control-dep-attempts",
"Maximum number of nested calls to search for control dependencies "
diff --git a/gcc/params.h b/gcc/params.h
index 4779e17..e2973d4 100644
--- a/gcc/params.h
+++ b/gcc/params.h
@@ -238,5 +238,7 @@ extern void init_param_values (int *params);
PARAM_VALUE (PARAM_ASAN_USE_AFTER_RETURN)
#define ASAN_INSTRUMENTATION_WITH_CALL_THRESHOLD \
PARAM_VALUE (PARAM_ASAN_INSTRUMENTATION_WITH_CALL_THRESHOLD)
+#define ASAN_ALIGNMENT_OPTIMIZE \
+ PARAM_VALUE (PARAM_ASAN_ALIGNMENT_OPTIMIZE)
#endif /* ! GCC_PARAMS_H */
diff --git a/gcc/testsuite/c-c++-common/asan/ignore_align.c b/gcc/testsuite/c-c++-common/asan/ignore_align.c
new file mode 100644
index 000..989958b
--- /dev/null
+++ b/gcc/testsuite/c-c++-common/asan/ignore_align.c
@@ -0,0 +1,34 @@
+/* { dg-options "-fdump-tree-sanopt --param asan-alignment-optimize=0" } */
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-flto" } { "" } } */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+void *memset (void *, int, __SIZE_TYPE__);
+#ifdef __cplusplus
+}
+#endif
+
+struct dummy {
+ int a;
+ int b;
+ int c;
+ int d;
+};
+
+volatile struct dummy * new_p;
+volatile struct dummy * old_p;
+
+void foo(void)
+{
+ *(volatile char *)(0x12);
+ *(volatile short int *)(0x12);
+ *(volatile unsigned int *)(0x12);
+ *(volatile unsigned long long *)(0x12);
+ *new_p = *old_p;
+}
+
+/* { dg-final { scan-tree-dump-times ">> 3" 11 "sanopt" } } */
+/* { dg-final { scan-tree-dump-times "& 7" 11 "sanopt" } } */
+/* { dg-final { cleanup-tree-dump "sanopt" } } */
[PING][PATCH] Ignore alignment by option
On 11/19/2014 06:01 PM, Marat Zakirov wrote:
Hi all!
Here is the patch which forces ASan to ignore alignment of memory
access. It increases ASan overhead but it's still useful because some
programs like linux kernel often cheat with alignment which may cause
false negatives.
--Marat
gcc/ChangeLog:
2014-11-14 Marat Zakirov
* asan.c (asan_expand_check_ifn): Ignore alignment by option.
* doc/invoke.texi: Document.
* params.def (asan-alignment-optimize): New.
* params.h: Likewise.
gcc/testsuite/ChangeLog:
2014-11-14 Marat Zakirov
* c-c++-common/asan/red-align-3.c: New test.
diff --git a/gcc/asan.c b/gcc/asan.c
index 79dede7..4f86088 100644
--- a/gcc/asan.c
+++ b/gcc/asan.c
@@ -2518,6 +2518,12 @@ asan_expand_check_ifn (gimple_stmt_iterator *iter, bool use_calls)
HOST_WIDE_INT size_in_bytes
= is_scalar_access && tree_fits_shwi_p (len) ? tree_to_shwi (len) : -1;
+
+ if (!ASAN_ALIGNMENT_OPTIMIZE && size_in_bytes > 1)
+{
+ size_in_bytes = -1;
+ align = 1;
+}
if (use_calls)
{
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 13270bc..8f43c06 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -10580,6 +10580,12 @@ is greater or equal to this number, use callbacks instead of inline checks.
E.g. to disable inline code use
@option{--param asan-instrumentation-with-call-threshold=0}.
+@item asan-alignment-optimize
+Enable asan optimization for aligned accesses.
+It is enabled by default when using @option{-fsanitize=address} option.
+To disable optimization for aligned accesses use
+@option{--param asan-alignment-optimize=0}.
+
@item chkp-max-ctor-size
Static constructors generated by Pointer Bounds Checker may become very
large and significantly increase compile time at optimization level
diff --git a/gcc/params.def b/gcc/params.def
index d2d2add..fbccf46 100644
--- a/gcc/params.def
+++ b/gcc/params.def
@@ -1114,6 +1114,11 @@ DEFPARAM (PARAM_ASAN_INSTRUMENTATION_WITH_CALL_THRESHOLD,
"in function becomes greater or equal to this number",
7000, 0, INT_MAX)
+DEFPARAM (PARAM_ASAN_ALIGNMENT_OPTIMIZE,
+ "asan-alignment-optimize",
+ "Enable asan optimization for aligned access",
+ 1, 0, 1)
+
DEFPARAM (PARAM_UNINIT_CONTROL_DEP_ATTEMPTS,
"uninit-control-dep-attempts",
"Maximum number of nested calls to search for control dependencies "
diff --git a/gcc/params.h b/gcc/params.h
index 4779e17..e2973d4 100644
--- a/gcc/params.h
+++ b/gcc/params.h
@@ -238,5 +238,7 @@ extern void init_param_values (int *params);
PARAM_VALUE (PARAM_ASAN_USE_AFTER_RETURN)
#define ASAN_INSTRUMENTATION_WITH_CALL_THRESHOLD \
PARAM_VALUE (PARAM_ASAN_INSTRUMENTATION_WITH_CALL_THRESHOLD)
+#define ASAN_ALIGNMENT_OPTIMIZE \
+ PARAM_VALUE (PARAM_ASAN_ALIGNMENT_OPTIMIZE)
#endif /* ! GCC_PARAMS_H */
diff --git a/gcc/testsuite/c-c++-common/asan/ignore_align.c b/gcc/testsuite/c-c++-common/asan/ignore_align.c
new file mode 100644
index 000..989958b
--- /dev/null
+++ b/gcc/testsuite/c-c++-common/asan/ignore_align.c
@@ -0,0 +1,34 @@
+/* { dg-options "-fdump-tree-sanopt --param asan-alignment-optimize=0" } */
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-flto" } { "" } } */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+void *memset (void *, int, __SIZE_TYPE__);
+#ifdef __cplusplus
+}
+#endif
+
+struct dummy {
+ int a;
+ int b;
+ int c;
+ int d;
+};
+
+volatile struct dummy * new_p;
+volatile struct dummy * old_p;
+
+void foo(void)
+{
+ *(volatile char *)(0x12);
+ *(volatile short int *)(0x12);
+ *(volatile unsigned int *)(0x12);
+ *(volatile unsigned long long *)(0x12);
+ *new_p = *old_p;
+}
+
+/* { dg-final { scan-tree-dump-times ">> 3" 11 "sanopt" } } */
+/* { dg-final { scan-tree-dump-times "& 7" 11 "sanopt" } } */
+/* { dg-final { cleanup-tree-dump "sanopt" } } */
Re: [PATCH] ASan phase place change
On 02/20/2015 03:07 PM, Jakub Jelinek wrote: On Fri, Feb 20, 2015 at 02:59:51PM +0300, Marat Zakirov wrote: Here is simple patch that moves asan phase just behind sanopt for all O0/O1/O2/O3 modes which gives +7% on x86 SPEC2006 (ref dataset). Regression testing and sanitized GCC bootstrapping were successfully done. This isn't a regression, so I think it isn't appropriate for stage 4. I bet the difference is mainly vectorization. I believe the right change is to teach the vectorizer about the ASAN_CHECK internal call instead. Jakub Jakub, I reproduced +28% for 433.milk with "-fno-tree-vectorize" on ref data. Are there some other GCC vectorization options? And why do you think that performance difference caused only by vectorization? As an example In llvm loop hoisting suffers from early asan phase http://lists.cs.uiuc.edu/pipermail/llvmdev/2011-December/046332.html. --Marat
[PING][PATCH] ASan phase place change
On 02/24/2015 03:49 PM, Marat Zakirov wrote:
On 02/20/2015 03:07 PM, Jakub Jelinek wrote:
On Fri, Feb 20, 2015 at 02:59:51PM +0300, Marat Zakirov wrote:
Here is simple patch that moves asan phase just behind sanopt for all
O0/O1/O2/O3 modes which gives +7% on x86 SPEC2006 (ref dataset).
Regression testing and sanitized GCC bootstrapping were successfully
done.
This isn't a regression, so I think it isn't appropriate for stage 4.
I bet the difference is mainly vectorization. I believe the right
change is to teach the vectorizer about the ASAN_CHECK internal call
instead.
Jakub
Jakub,
I reproduced +28% for 433.milk with "-fno-tree-vectorize" on ref data.
Are there some other GCC vectorization options? And why do you think
that performance difference caused only by vectorization? As an
example In llvm loop hoisting suffers from early asan phase
http://lists.cs.uiuc.edu/pipermail/llvmdev/2011-December/046332.html.
--Marat
gcc/ChangeLog:
2015-02-20 Marat Zakirov
* asan.c (make_pass_asan_O0): Pass remove.
* passes.def: Change place for ASan pass.
* tree-pass.h: Passes remove.
* tsan.c (make_pass_tsan_O0): Pass remove.
gcc/testsuite/ChangeLog:
2015-02-20 Marat Zakirov
* c-c++-common/asan/inc.c: Fix option.
diff --git a/gcc/asan.c b/gcc/asan.c
index b7c2b11..001d79e 100644
--- a/gcc/asan.c
+++ b/gcc/asan.c
@@ -2796,40 +2796,4 @@ make_pass_asan (gcc::context *ctxt)
return new pass_asan (ctxt);
}
-namespace {
-
-const pass_data pass_data_asan_O0 =
-{
- GIMPLE_PASS, /* type */
- "asan0", /* name */
- OPTGROUP_NONE, /* optinfo_flags */
- TV_NONE, /* tv_id */
- ( PROP_ssa | PROP_cfg | PROP_gimple_leh ), /* properties_required */
- 0, /* properties_provided */
- 0, /* properties_destroyed */
- 0, /* todo_flags_start */
- TODO_update_ssa, /* todo_flags_finish */
-};
-
-class pass_asan_O0 : public gimple_opt_pass
-{
-public:
- pass_asan_O0 (gcc::context *ctxt)
-: gimple_opt_pass (pass_data_asan_O0, ctxt)
- {}
-
- /* opt_pass methods: */
- virtual bool gate (function *) { return !optimize && gate_asan (); }
- virtual unsigned int execute (function *) { return asan_instrument (); }
-
-}; // class pass_asan_O0
-
-} // anon namespace
-
-gimple_opt_pass *
-make_pass_asan_O0 (gcc::context *ctxt)
-{
- return new pass_asan_O0 (ctxt);
-}
-
#include "gt-asan.h"
diff --git a/gcc/passes.def b/gcc/passes.def
index 2bc5dcd..398d8dc 100644
--- a/gcc/passes.def
+++ b/gcc/passes.def
@@ -214,8 +214,6 @@ along with GCC; see the file COPYING3. If not see
NEXT_PASS (pass_split_crit_edges);
NEXT_PASS (pass_pre);
NEXT_PASS (pass_sink_code);
- NEXT_PASS (pass_asan);
- NEXT_PASS (pass_tsan);
/* Pass group that runs when 1) enabled, 2) there are loops
in the function. Make sure to run pass_fix_loops before
to discover/remove loops before running the gate function
@@ -344,8 +342,8 @@ along with GCC; see the file COPYING3. If not see
NEXT_PASS (pass_vtable_verify);
NEXT_PASS (pass_lower_vector);
NEXT_PASS (pass_lower_complex_O0);
- NEXT_PASS (pass_asan_O0);
- NEXT_PASS (pass_tsan_O0);
+ NEXT_PASS (pass_asan);
+ NEXT_PASS (pass_tsan);
NEXT_PASS (pass_sanopt);
NEXT_PASS (pass_cleanup_eh);
NEXT_PASS (pass_lower_resx);
diff --git a/gcc/testsuite/c-c++-common/asan/inc.c b/gcc/testsuite/c-c++-common/asan/inc.c
index 36cc3d8..8c38150 100644
--- a/gcc/testsuite/c-c++-common/asan/inc.c
+++ b/gcc/testsuite/c-c++-common/asan/inc.c
@@ -1,4 +1,4 @@
-/* { dg-options "-fdump-tree-asan0" } */
+/* { dg-options "-fdump-tree-asan" } */
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "*" } { "-O0" } } */
@@ -16,6 +16,6 @@ main ()
return 0;
}
-/* { dg-final { scan-tree-dump-times "ASAN_" 1 "asan0" } } */
-/* { dg-final { scan-tree-dump "ASAN_CHECK \\(.*, 4\\);" "asan0" } } */
-/* { dg-final { cleanup-tree-dump "asan0" } } */
+/* { dg-final { scan-tree-dump-times "ASAN_" 1 "asan" } } */
+/* { dg-final { scan-tree-dump "ASAN_CHECK \\(.*, 4\\);" "asan" } } */
+/* { dg-final { cleanup-tree-dump "asan" } } */
diff --git a/gcc/tree-pass.h b/gcc/tree-pass.h
index b59ae7a..50cbf85 100644
--- a/gcc/tree-pass.h
+++ b/gcc/tree-pass.h
@@ -339,9 +339,7 @@ extern simple_ipa_opt_pass *make_pass_ipa_chkp_produce_thunks (gcc::context *ctx
extern gimple_opt_pass *make_pass_chkp (gcc::context *ctxt);
extern gimple_opt_pass *make_pass_chkp_opt (gcc::context *ctxt);
extern gimple_opt_pass *make_pass_asan (gcc::context *ctxt);
-extern gimple_opt_pass *make_pass_asan_O0 (gcc::context *ctxt);
extern gimple_opt_pass *make_pass_tsan (gcc::context *ctxt);
-extern gimple_opt_pass *make_pass_tsan_O0 (gcc::context *ctxt);
extern gimple_opt_pass *make_pass_lower_cf (gcc::context *ctxt);
extern gimple_opt_pass *make_pass_refactor_eh (gcc::co
[PATCH] ASan on unaligned accesses
Hi all!
Here is the patch which forces ASan to work on memory access without
proper alignment. it's useful because some programs like linux kernel
often cheat with alignment which may cause false negatives. This patch
needs additional support for proper work on unaligned accesses in global
data and heap. It will be implemented in libsanitizer by separate patch.
--Marat
gcc/ChangeLog:
2015-02-25 Marat Zakirov
* asan.c (asan_emit_stack_protection): Support for misalign accesses.
(asan_expand_check_ifn): Likewise.
* params.def: New option asan-catch-misaligned.
* params.h: New param ASAN_CATCH_MISALIGNED.
gcc/testsuite/ChangeLog:
2015-02-25 Marat Zakirov
* c-c++-common/asan/misalign-catch.c: New test.
diff --git a/gcc/asan.c b/gcc/asan.c
index b7c2b11..49d0da4 100644
--- a/gcc/asan.c
+++ b/gcc/asan.c
@@ -1050,7 +1050,6 @@ asan_emit_stack_protection (rtx base, rtx pbase, unsigned int alignb,
rtx_code_label *lab;
rtx_insn *insns;
char buf[30];
- unsigned char shadow_bytes[4];
HOST_WIDE_INT base_offset = offsets[length - 1];
HOST_WIDE_INT base_align_bias = 0, offset, prev_offset;
HOST_WIDE_INT asan_frame_size = offsets[0] - base_offset;
@@ -1059,6 +1058,7 @@ asan_emit_stack_protection (rtx base, rtx pbase, unsigned int alignb,
unsigned char cur_shadow_byte = ASAN_STACK_MAGIC_LEFT;
tree str_cst, decl, id;
int use_after_return_class = -1;
+ bool misalign = (flag_sanitize & SANITIZE_KERNEL_ADDRESS) || ASAN_CATCH_MISALIGNED;
if (shadow_ptr_types[0] == NULL_TREE)
asan_init_shadow_ptr_types ();
@@ -1193,11 +1193,37 @@ asan_emit_stack_protection (rtx base, rtx pbase, unsigned int alignb,
if (STRICT_ALIGNMENT)
set_mem_align (shadow_mem, (GET_MODE_ALIGNMENT (SImode)));
prev_offset = base_offset;
+
+ vec shadow_mems;
+ vec shadow_bytes;
+
+ shadow_mems.create(0);
+ shadow_bytes.create(0);
+
for (l = length; l; l -= 2)
{
if (l == 2)
cur_shadow_byte = ASAN_STACK_MAGIC_RIGHT;
offset = offsets[l - 1];
+ if (l != length && misalign)
+ {
+ HOST_WIDE_INT aoff
+ = base_offset + ((offset - base_offset)
+ & ~(ASAN_RED_ZONE_SIZE - HOST_WIDE_INT_1))
+ - ASAN_RED_ZONE_SIZE;
+ if (aoff > prev_offset)
+ {
+ shadow_mem = adjust_address (shadow_mem, VOIDmode,
+ (aoff - prev_offset)
+ >> ASAN_SHADOW_SHIFT);
+ prev_offset = aoff;
+ shadow_bytes.safe_push (0);
+ shadow_bytes.safe_push (0);
+ shadow_bytes.safe_push (0);
+ shadow_bytes.safe_push (0);
+ shadow_mems.safe_push (shadow_mem);
+ }
+ }
if ((offset - base_offset) & (ASAN_RED_ZONE_SIZE - 1))
{
int i;
@@ -1212,13 +1238,13 @@ asan_emit_stack_protection (rtx base, rtx pbase, unsigned int alignb,
if (aoff < offset)
{
if (aoff < offset - (1 << ASAN_SHADOW_SHIFT) + 1)
- shadow_bytes[i] = 0;
+ shadow_bytes.safe_push (0);
else
- shadow_bytes[i] = offset - aoff;
+ shadow_bytes.safe_push (offset - aoff);
}
else
- shadow_bytes[i] = ASAN_STACK_MAGIC_PARTIAL;
- emit_move_insn (shadow_mem, asan_shadow_cst (shadow_bytes));
+ shadow_bytes.safe_push (ASAN_STACK_MAGIC_PARTIAL);
+ shadow_mems.safe_push(shadow_mem);
offset = aoff;
}
while (offset <= offsets[l - 2] - ASAN_RED_ZONE_SIZE)
@@ -1227,12 +1253,21 @@ asan_emit_stack_protection (rtx base, rtx pbase, unsigned int alignb,
(offset - prev_offset)
>> ASAN_SHADOW_SHIFT);
prev_offset = offset;
- memset (shadow_bytes, cur_shadow_byte, 4);
- emit_move_insn (shadow_mem, asan_shadow_cst (shadow_bytes));
+ shadow_bytes.safe_push (cur_shadow_byte);
+ shadow_bytes.safe_push (cur_shadow_byte);
+ shadow_bytes.safe_push (cur_shadow_byte);
+ shadow_bytes.safe_push (cur_shadow_byte);
+ shadow_mems.safe_push(shadow_mem);
offset += ASAN_RED_ZONE_SIZE;
}
cur_shadow_byte = ASAN_STACK_MAGIC_MIDDLE;
}
+ for (unsigned i = 0; misalign && i < shadow_bytes.length () - 1; i++)
+if (shadow_bytes[i] == 0 && shadow_bytes[i + 1] > 0)
+ shadow_bytes[i] = 8 + (shadow_bytes[i + 1] > 7 ? 0 : shadow_bytes[i + 1]);
+ for (unsigned i = 0; i < shadow_mems.length (); i++)
+emit_move_insn (shadow_mems[i], asan_shadow_cst (&shadow_bytes[i * 4]));
+
do_pending_stack_adjust ();
/* Construct epilogue sequence. */
@@ -1285,34 +1320,8 @@ asan_emit_stack_protection (rtx base, rtx pbase, unsigned int alignb,
if (STRICT_ALIGNMENT)
set_mem_align (shadow_mem, (GET_MODE_ALIGNMENT (SImode)));
- prev_offset = base_offset;
- last_offset = base_offset;
- last_size = 0;
- for (l = length; l; l -= 2)
-{
- offset = base_offset + ((offsets[l - 1] - base_offset)
- & ~(ASAN_RED_ZONE_SIZE - HOST_WIDE_INT_1));
- if (last_offset + last_size != offset)
- {
- shadow_mem = adjust_address (shadow_mem, VOIDmode,
- (
[PATCH] optionally disable global check
Hi all!
Currently !ASAN_GLOBALS disables red-zones for global variables but
keeps their checks. This simple patch disables these checks too.
--Marat
gcc/ChangeLog:
2015-01-22 Marat Zakirov
* asan.c (instrument_derefs): asan-globals=0 disable instrumentation.
gcc/testsuite/ChangeLog:
2015-01-22 Marat Zakirov
* c-c++-common/asan/no-asan-check-glob.c: New test.
diff --git a/gcc/asan.c b/gcc/asan.c
index be28ede..c331f67 100644
--- a/gcc/asan.c
+++ b/gcc/asan.c
@@ -1809,6 +1809,8 @@ instrument_derefs (gimple_stmt_iterator *iter, tree t,
{
if (DECL_THREAD_LOCAL_P (inner))
return;
+ if (!ASAN_GLOBALS && is_global_var (inner))
+return;
if (!TREE_STATIC (inner))
{
/* Automatic vars in the current function will be always
diff --git a/gcc/testsuite/c-c++-common/asan/no-asan-check-glob.c b/gcc/testsuite/c-c++-common/asan/no-asan-check-glob.c
new file mode 100644
index 000..a1b1410
--- /dev/null
+++ b/gcc/testsuite/c-c++-common/asan/no-asan-check-glob.c
@@ -0,0 +1,13 @@
+/* { dg-options "--param asan-globals=0 -fdump-tree-asan" } */
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } { "*" } } */
+
+extern int a;
+
+int foo ()
+{
+ return a;
+}
+
+/* { dg-final { scan-tree-dump-times "ASAN_CHECK" 0 "asan1" } } */
+/* { dg-final { cleanup-tree-dump "asan1" } } */
[PINGv2][PATCH] ASan phase place change
On 03/03/2015 10:36 AM, Marat Zakirov wrote:
On 02/24/2015 03:49 PM, Marat Zakirov wrote:
On 02/20/2015 03:07 PM, Jakub Jelinek wrote:
On Fri, Feb 20, 2015 at 02:59:51PM +0300, Marat Zakirov wrote:
Here is simple patch that moves asan phase just behind sanopt for all
O0/O1/O2/O3 modes which gives +7% on x86 SPEC2006 (ref dataset).
Regression testing and sanitized GCC bootstrapping were
successfully done.
This isn't a regression, so I think it isn't appropriate for stage 4.
I bet the difference is mainly vectorization. I believe the right
change is to teach the vectorizer about the ASAN_CHECK internal call
instead.
Jakub
Jakub,
I reproduced +28% for 433.milk with "-fno-tree-vectorize" on ref
data. Are there some other GCC vectorization options? And why do you
think that performance difference caused only by vectorization? As an
example In llvm loop hoisting suffers from early asan phase
http://lists.cs.uiuc.edu/pipermail/llvmdev/2011-December/046332.html.
--Marat
gcc/ChangeLog:
2015-02-20 Marat Zakirov
* asan.c (make_pass_asan_O0): Pass remove.
* passes.def: Change place for ASan pass.
* tree-pass.h: Passes remove.
* tsan.c (make_pass_tsan_O0): Pass remove.
gcc/testsuite/ChangeLog:
2015-02-20 Marat Zakirov
* c-c++-common/asan/inc.c: Fix option.
diff --git a/gcc/asan.c b/gcc/asan.c
index b7c2b11..001d79e 100644
--- a/gcc/asan.c
+++ b/gcc/asan.c
@@ -2796,40 +2796,4 @@ make_pass_asan (gcc::context *ctxt)
return new pass_asan (ctxt);
}
-namespace {
-
-const pass_data pass_data_asan_O0 =
-{
- GIMPLE_PASS, /* type */
- "asan0", /* name */
- OPTGROUP_NONE, /* optinfo_flags */
- TV_NONE, /* tv_id */
- ( PROP_ssa | PROP_cfg | PROP_gimple_leh ), /* properties_required */
- 0, /* properties_provided */
- 0, /* properties_destroyed */
- 0, /* todo_flags_start */
- TODO_update_ssa, /* todo_flags_finish */
-};
-
-class pass_asan_O0 : public gimple_opt_pass
-{
-public:
- pass_asan_O0 (gcc::context *ctxt)
-: gimple_opt_pass (pass_data_asan_O0, ctxt)
- {}
-
- /* opt_pass methods: */
- virtual bool gate (function *) { return !optimize && gate_asan (); }
- virtual unsigned int execute (function *) { return asan_instrument (); }
-
-}; // class pass_asan_O0
-
-} // anon namespace
-
-gimple_opt_pass *
-make_pass_asan_O0 (gcc::context *ctxt)
-{
- return new pass_asan_O0 (ctxt);
-}
-
#include "gt-asan.h"
diff --git a/gcc/passes.def b/gcc/passes.def
index 2bc5dcd..398d8dc 100644
--- a/gcc/passes.def
+++ b/gcc/passes.def
@@ -214,8 +214,6 @@ along with GCC; see the file COPYING3. If not see
NEXT_PASS (pass_split_crit_edges);
NEXT_PASS (pass_pre);
NEXT_PASS (pass_sink_code);
- NEXT_PASS (pass_asan);
- NEXT_PASS (pass_tsan);
/* Pass group that runs when 1) enabled, 2) there are loops
in the function. Make sure to run pass_fix_loops before
to discover/remove loops before running the gate function
@@ -344,8 +342,8 @@ along with GCC; see the file COPYING3. If not see
NEXT_PASS (pass_vtable_verify);
NEXT_PASS (pass_lower_vector);
NEXT_PASS (pass_lower_complex_O0);
- NEXT_PASS (pass_asan_O0);
- NEXT_PASS (pass_tsan_O0);
+ NEXT_PASS (pass_asan);
+ NEXT_PASS (pass_tsan);
NEXT_PASS (pass_sanopt);
NEXT_PASS (pass_cleanup_eh);
NEXT_PASS (pass_lower_resx);
diff --git a/gcc/testsuite/c-c++-common/asan/inc.c b/gcc/testsuite/c-c++-common/asan/inc.c
index 36cc3d8..8c38150 100644
--- a/gcc/testsuite/c-c++-common/asan/inc.c
+++ b/gcc/testsuite/c-c++-common/asan/inc.c
@@ -1,4 +1,4 @@
-/* { dg-options "-fdump-tree-asan0" } */
+/* { dg-options "-fdump-tree-asan" } */
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "*" } { "-O0" } } */
@@ -16,6 +16,6 @@ main ()
return 0;
}
-/* { dg-final { scan-tree-dump-times "ASAN_" 1 "asan0" } } */
-/* { dg-final { scan-tree-dump "ASAN_CHECK \\(.*, 4\\);" "asan0" } } */
-/* { dg-final { cleanup-tree-dump "asan0" } } */
+/* { dg-final { scan-tree-dump-times "ASAN_" 1 "asan" } } */
+/* { dg-final { scan-tree-dump "ASAN_CHECK \\(.*, 4\\);" "asan" } } */
+/* { dg-final { cleanup-tree-dump "asan" } } */
diff --git a/gcc/tree-pass.h b/gcc/tree-pass.h
index b59ae7a..50cbf85 100644
--- a/gcc/tree-pass.h
+++ b/gcc/tree-pass.h
@@ -339,9 +339,7 @@ extern simple_ipa_opt_pass *make_pass_ipa_chkp_produce_thunks (gcc::context *ctx
extern gimple_opt_pass *make_pass_chkp (gcc::context *ctxt);
extern gimple_opt_pass *make_pass_chkp_opt (gcc::context *ctxt);
extern gimple_opt_pass *make_pass_asan (gcc::context *ctxt);
-extern gimple_opt_pass *make_pass_asan_O0 (gcc::context *ctxt);
extern gimple_opt_pass *make_pass_tsan (gcc::context *ctxt);
-extern gimple_opt_pass *make_pass_tsan_O0 (gcc::context *ctxt);
extern gimple_opt_pass *make_pass_lower_cf (gcc::context *ctxt);
ex
[PING][PATCH] ASan on unaligned accesses
On 03/04/2015 11:00 AM, Marat Zakirov wrote:
Hi all!
Here is the patch which forces ASan to work on memory access without
proper alignment. it's useful because some programs like linux kernel
often cheat with alignment which may cause false negatives. This patch
needs additional support for proper work on unaligned accesses in
global data and heap. It will be implemented in libsanitizer by
separate patch.
--Marat
gcc/ChangeLog:
2015-02-25 Marat Zakirov
* asan.c (asan_emit_stack_protection): Support for misalign accesses.
(asan_expand_check_ifn): Likewise.
* params.def: New option asan-catch-misaligned.
* params.h: New param ASAN_CATCH_MISALIGNED.
gcc/testsuite/ChangeLog:
2015-02-25 Marat Zakirov
* c-c++-common/asan/misalign-catch.c: New test.
diff --git a/gcc/asan.c b/gcc/asan.c
index b7c2b11..49d0da4 100644
--- a/gcc/asan.c
+++ b/gcc/asan.c
@@ -1050,7 +1050,6 @@ asan_emit_stack_protection (rtx base, rtx pbase, unsigned int alignb,
rtx_code_label *lab;
rtx_insn *insns;
char buf[30];
- unsigned char shadow_bytes[4];
HOST_WIDE_INT base_offset = offsets[length - 1];
HOST_WIDE_INT base_align_bias = 0, offset, prev_offset;
HOST_WIDE_INT asan_frame_size = offsets[0] - base_offset;
@@ -1059,6 +1058,7 @@ asan_emit_stack_protection (rtx base, rtx pbase, unsigned int alignb,
unsigned char cur_shadow_byte = ASAN_STACK_MAGIC_LEFT;
tree str_cst, decl, id;
int use_after_return_class = -1;
+ bool misalign = (flag_sanitize & SANITIZE_KERNEL_ADDRESS) || ASAN_CATCH_MISALIGNED;
if (shadow_ptr_types[0] == NULL_TREE)
asan_init_shadow_ptr_types ();
@@ -1193,11 +1193,37 @@ asan_emit_stack_protection (rtx base, rtx pbase, unsigned int alignb,
if (STRICT_ALIGNMENT)
set_mem_align (shadow_mem, (GET_MODE_ALIGNMENT (SImode)));
prev_offset = base_offset;
+
+ vec shadow_mems;
+ vec shadow_bytes;
+
+ shadow_mems.create(0);
+ shadow_bytes.create(0);
+
for (l = length; l; l -= 2)
{
if (l == 2)
cur_shadow_byte = ASAN_STACK_MAGIC_RIGHT;
offset = offsets[l - 1];
+ if (l != length && misalign)
+ {
+ HOST_WIDE_INT aoff
+ = base_offset + ((offset - base_offset)
+ & ~(ASAN_RED_ZONE_SIZE - HOST_WIDE_INT_1))
+ - ASAN_RED_ZONE_SIZE;
+ if (aoff > prev_offset)
+ {
+ shadow_mem = adjust_address (shadow_mem, VOIDmode,
+ (aoff - prev_offset)
+ >> ASAN_SHADOW_SHIFT);
+ prev_offset = aoff;
+ shadow_bytes.safe_push (0);
+ shadow_bytes.safe_push (0);
+ shadow_bytes.safe_push (0);
+ shadow_bytes.safe_push (0);
+ shadow_mems.safe_push (shadow_mem);
+ }
+ }
if ((offset - base_offset) & (ASAN_RED_ZONE_SIZE - 1))
{
int i;
@@ -1212,13 +1238,13 @@ asan_emit_stack_protection (rtx base, rtx pbase, unsigned int alignb,
if (aoff < offset)
{
if (aoff < offset - (1 << ASAN_SHADOW_SHIFT) + 1)
- shadow_bytes[i] = 0;
+ shadow_bytes.safe_push (0);
else
- shadow_bytes[i] = offset - aoff;
+ shadow_bytes.safe_push (offset - aoff);
}
else
- shadow_bytes[i] = ASAN_STACK_MAGIC_PARTIAL;
- emit_move_insn (shadow_mem, asan_shadow_cst (shadow_bytes));
+ shadow_bytes.safe_push (ASAN_STACK_MAGIC_PARTIAL);
+ shadow_mems.safe_push(shadow_mem);
offset = aoff;
}
while (offset <= offsets[l - 2] - ASAN_RED_ZONE_SIZE)
@@ -1227,12 +1253,21 @@ asan_emit_stack_protection (rtx base, rtx pbase, unsigned int alignb,
(offset - prev_offset)
>> ASAN_SHADOW_SHIFT);
prev_offset = offset;
- memset (shadow_bytes, cur_shadow_byte, 4);
- emit_move_insn (shadow_mem, asan_shadow_cst (shadow_bytes));
+ shadow_bytes.safe_push (cur_shadow_byte);
+ shadow_bytes.safe_push (cur_shadow_byte);
+ shadow_bytes.safe_push (cur_shadow_byte);
+ shadow_bytes.safe_push (cur_shadow_byte);
+ shadow_mems.safe_push(shadow_mem);
offset += ASAN_RED_ZONE_SIZE;
}
cur_shadow_byte = ASAN_STACK_MAGIC_MIDDLE;
}
+ for (unsigned i = 0; misalign && i < shadow_bytes.length () - 1; i++)
+if (shadow_bytes[i] == 0 && shadow_bytes[i + 1] > 0)
+ shadow_bytes[i] = 8 + (shadow_bytes[i + 1] > 7 ? 0 : shadow_bytes[i + 1]);
+ for (unsigned i = 0; i < shadow_mems.length (); i++)
+emit_move_insn (shadow_mems[i], asan_shadow_cst (&shadow_bytes[i * 4]));
+
do_pending_stack_adjust ();
/* Construct epilogue sequence. */
@@ -1285,34 +1320,8 @@ asan_emit_stack_protection (rtx base, rtx pbase, unsigned int alignb,
if (STRICT_ALIGNMENT)
set_mem_align (shadow_mem, (GET_MODE_ALIGNMENT (SImode)));
- prev_offset = base_offset;
- last_offset = base_offset;
- last_size = 0;
- for (l = length; l; l -= 2)
-{
- offset = base_offset + ((offsets[l - 1] - base_offset)
- & ~(ASAN_RED_ZONE_SIZE - HOST_WIDE_INT_1));
- if (last_offset + last_size != offset)
- {
-
[PINGv2][PATCH] ASan on unaligned accesses
On 03/04/2015 11:07 AM, Andrew Pinski wrote:
On Wed, Mar 4, 2015 at 12:00 AM, Marat Zakirov wrote:
Hi all!
Here is the patch which forces ASan to work on memory access without proper
alignment. it's useful because some programs like linux kernel often cheat
with alignment which may cause false negatives. This patch needs additional
support for proper work on unaligned accesses in global data and heap. It
will be implemented in libsanitizer by separate patch.
--Marat
gcc/ChangeLog:
2015-02-25 Marat Zakirov
* asan.c (asan_emit_stack_protection): Support for misalign
accesses.
(asan_expand_check_ifn): Likewise.
* params.def: New option asan-catch-misaligned.
* params.h: New param ASAN_CATCH_MISALIGNED.
Since this parameter can only be true or false, I think it should be a
normal option. Also you did not add documentation of the param.
Thanks,
Andrew
Fixed.
gcc/ChangeLog:
2015-03-12 Marat Zakirov
* asan.c (asan_emit_stack_protection): Support for misalign accesses.
(asan_expand_check_ifn): Likewise.
* common.opt: New flag -fasan-catch-misaligned.
* doc/invoke.texi: New flag description.
* opts.c (finish_options): Add check for new flag.
(common_handle_option): Switch on flag if SANITIZE_KERNEL_ADDRESS.
gcc/testsuite/ChangeLog:
2015-03-12 Marat Zakirov
* c-c++-common/asan/misalign-catch.c: New test.
diff --git a/gcc/asan.c b/gcc/asan.c
index 9e4a629..80bf2e8 100644
--- a/gcc/asan.c
+++ b/gcc/asan.c
@@ -1050,7 +1050,6 @@ asan_emit_stack_protection (rtx base, rtx pbase, unsigned int alignb,
rtx_code_label *lab;
rtx_insn *insns;
char buf[30];
- unsigned char shadow_bytes[4];
HOST_WIDE_INT base_offset = offsets[length - 1];
HOST_WIDE_INT base_align_bias = 0, offset, prev_offset;
HOST_WIDE_INT asan_frame_size = offsets[0] - base_offset;
@@ -1193,11 +1192,37 @@ asan_emit_stack_protection (rtx base, rtx pbase, unsigned int alignb,
if (STRICT_ALIGNMENT)
set_mem_align (shadow_mem, (GET_MODE_ALIGNMENT (SImode)));
prev_offset = base_offset;
+
+ vec shadow_mems;
+ vec shadow_bytes;
+
+ shadow_mems.create(0);
+ shadow_bytes.create(0);
+
for (l = length; l; l -= 2)
{
if (l == 2)
cur_shadow_byte = ASAN_STACK_MAGIC_RIGHT;
offset = offsets[l - 1];
+ if (l != length && flag_asan_catch_misaligned)
+ {
+ HOST_WIDE_INT aoff
+ = base_offset + ((offset - base_offset)
+ & ~(ASAN_RED_ZONE_SIZE - HOST_WIDE_INT_1))
+ - ASAN_RED_ZONE_SIZE;
+ if (aoff > prev_offset)
+ {
+ shadow_mem = adjust_address (shadow_mem, VOIDmode,
+ (aoff - prev_offset)
+ >> ASAN_SHADOW_SHIFT);
+ prev_offset = aoff;
+ shadow_bytes.safe_push (0);
+ shadow_bytes.safe_push (0);
+ shadow_bytes.safe_push (0);
+ shadow_bytes.safe_push (0);
+ shadow_mems.safe_push (shadow_mem);
+ }
+ }
if ((offset - base_offset) & (ASAN_RED_ZONE_SIZE - 1))
{
int i;
@@ -1212,13 +1237,13 @@ asan_emit_stack_protection (rtx base, rtx pbase, unsigned int alignb,
if (aoff < offset)
{
if (aoff < offset - (1 << ASAN_SHADOW_SHIFT) + 1)
- shadow_bytes[i] = 0;
+ shadow_bytes.safe_push (0);
else
- shadow_bytes[i] = offset - aoff;
+ shadow_bytes.safe_push (offset - aoff);
}
else
- shadow_bytes[i] = ASAN_STACK_MAGIC_PARTIAL;
- emit_move_insn (shadow_mem, asan_shadow_cst (shadow_bytes));
+ shadow_bytes.safe_push (ASAN_STACK_MAGIC_PARTIAL);
+ shadow_mems.safe_push(shadow_mem);
offset = aoff;
}
while (offset <= offsets[l - 2] - ASAN_RED_ZONE_SIZE)
@@ -1227,12 +1252,21 @@ asan_emit_stack_protection (rtx base, rtx pbase, unsigned int alignb,
(offset - prev_offset)
>> ASAN_SHADOW_SHIFT);
prev_offset = offset;
- memset (shadow_bytes, cur_shadow_byte, 4);
- emit_move_insn (shadow_mem, asan_shadow_cst (shadow_bytes));
+ shadow_bytes.safe_push (cur_shadow_byte);
+ shadow_bytes.safe_push (cur_shadow_byte);
+ shadow_bytes.safe_push (cur_shadow_byte);
+ shadow_bytes.safe_push (cur_shadow_byte);
+ shadow_mems.safe_push(shadow_mem);
offset += ASAN_RED_ZONE_SIZE;
}
cur_shadow_byte = ASAN_STACK_MAGIC_MIDDLE;
}
+ for (unsigned i = 0; flag_asan_catch_misaligned && i < shadow_bytes.length () - 1; i++)
+if (shadow_bytes[i] == 0 && shadow_bytes[i + 1] > 0)
+ shadow_bytes[i] = 8 + (shadow_bytes[i + 1] > 7 ? 0 : shadow_bytes[i + 1]);
+ for (unsigned i = 0; i < shadow_mems.length (); i++)
+emit_move_insn (shadow_mems[i], asan_shadow_cst (&shadow_bytes[i * 4]));
+
do_pending_stack_adjust ();
/* Construct epilogue sequence. */
@@ -1285,34 +1319,8 @@ asan_emit_stack_protection (rtx base, rtx pbase, unsigned int alignb,
if (STRICT_ALIGNMENT)
set_mem_align (shadow_mem, (GET_MODE_ALIGNMENT (SImode)));
- prev_offset = base_offset;
- last_offset =
[PINGv3][PATCH] ASan on unaligned accesses
On 03/19/2015 09:01 AM, Marat Zakirov wrote:
On 03/04/2015 11:07 AM, Andrew Pinski wrote:
On Wed, Mar 4, 2015 at 12:00 AM, Marat Zakirov
wrote:
Hi all!
Here is the patch which forces ASan to work on memory access without
proper
alignment. it's useful because some programs like linux kernel often
cheat
with alignment which may cause false negatives. This patch needs
additional
support for proper work on unaligned accesses in global data and
heap. It
will be implemented in libsanitizer by separate patch.
--Marat
gcc/ChangeLog:
2015-02-25 Marat Zakirov
* asan.c (asan_emit_stack_protection): Support for misalign
accesses.
(asan_expand_check_ifn): Likewise.
* params.def: New option asan-catch-misaligned.
* params.h: New param ASAN_CATCH_MISALIGNED.
Since this parameter can only be true or false, I think it should be a
normal option. Also you did not add documentation of the param.
Thanks,
Andrew
Fixed.
gcc/ChangeLog:
2015-03-12 Marat Zakirov
* asan.c (asan_emit_stack_protection): Support for misalign accesses.
(asan_expand_check_ifn): Likewise.
* common.opt: New flag -fasan-catch-misaligned.
* doc/invoke.texi: New flag description.
* opts.c (finish_options): Add check for new flag.
(common_handle_option): Switch on flag if SANITIZE_KERNEL_ADDRESS.
gcc/testsuite/ChangeLog:
2015-03-12 Marat Zakirov
* c-c++-common/asan/misalign-catch.c: New test.
diff --git a/gcc/asan.c b/gcc/asan.c
index 9e4a629..80bf2e8 100644
--- a/gcc/asan.c
+++ b/gcc/asan.c
@@ -1050,7 +1050,6 @@ asan_emit_stack_protection (rtx base, rtx pbase, unsigned int alignb,
rtx_code_label *lab;
rtx_insn *insns;
char buf[30];
- unsigned char shadow_bytes[4];
HOST_WIDE_INT base_offset = offsets[length - 1];
HOST_WIDE_INT base_align_bias = 0, offset, prev_offset;
HOST_WIDE_INT asan_frame_size = offsets[0] - base_offset;
@@ -1193,11 +1192,37 @@ asan_emit_stack_protection (rtx base, rtx pbase, unsigned int alignb,
if (STRICT_ALIGNMENT)
set_mem_align (shadow_mem, (GET_MODE_ALIGNMENT (SImode)));
prev_offset = base_offset;
+
+ vec shadow_mems;
+ vec shadow_bytes;
+
+ shadow_mems.create(0);
+ shadow_bytes.create(0);
+
for (l = length; l; l -= 2)
{
if (l == 2)
cur_shadow_byte = ASAN_STACK_MAGIC_RIGHT;
offset = offsets[l - 1];
+ if (l != length && flag_asan_catch_misaligned)
+ {
+ HOST_WIDE_INT aoff
+ = base_offset + ((offset - base_offset)
+ & ~(ASAN_RED_ZONE_SIZE - HOST_WIDE_INT_1))
+ - ASAN_RED_ZONE_SIZE;
+ if (aoff > prev_offset)
+ {
+ shadow_mem = adjust_address (shadow_mem, VOIDmode,
+ (aoff - prev_offset)
+ >> ASAN_SHADOW_SHIFT);
+ prev_offset = aoff;
+ shadow_bytes.safe_push (0);
+ shadow_bytes.safe_push (0);
+ shadow_bytes.safe_push (0);
+ shadow_bytes.safe_push (0);
+ shadow_mems.safe_push (shadow_mem);
+ }
+ }
if ((offset - base_offset) & (ASAN_RED_ZONE_SIZE - 1))
{
int i;
@@ -1212,13 +1237,13 @@ asan_emit_stack_protection (rtx base, rtx pbase, unsigned int alignb,
if (aoff < offset)
{
if (aoff < offset - (1 << ASAN_SHADOW_SHIFT) + 1)
- shadow_bytes[i] = 0;
+ shadow_bytes.safe_push (0);
else
- shadow_bytes[i] = offset - aoff;
+ shadow_bytes.safe_push (offset - aoff);
}
else
- shadow_bytes[i] = ASAN_STACK_MAGIC_PARTIAL;
- emit_move_insn (shadow_mem, asan_shadow_cst (shadow_bytes));
+ shadow_bytes.safe_push (ASAN_STACK_MAGIC_PARTIAL);
+ shadow_mems.safe_push(shadow_mem);
offset = aoff;
}
while (offset <= offsets[l - 2] - ASAN_RED_ZONE_SIZE)
@@ -1227,12 +1252,21 @@ asan_emit_stack_protection (rtx base, rtx pbase, unsigned int alignb,
(offset - prev_offset)
>> ASAN_SHADOW_SHIFT);
prev_offset = offset;
- memset (shadow_bytes, cur_shadow_byte, 4);
- emit_move_insn (shadow_mem, asan_shadow_cst (shadow_bytes));
+ shadow_bytes.safe_push (cur_shadow_byte);
+ shadow_bytes.safe_push (cur_shadow_byte);
+ shadow_bytes.safe_push (cur_shadow_byte);
+ shadow_bytes.safe_push (cur_shadow_byte);
+ shadow_mems.safe_push(shadow_mem);
offset += ASAN_RED_ZONE_SIZE;
}
cur_shadow_byte = ASAN_STACK_MAGIC_MIDDLE;
}
+ for (unsigned i = 0; flag_asan_catch_misaligned && i < shadow_bytes.length () - 1; i++)
+if (shadow_bytes[i] == 0 && shadow_bytes[i + 1] > 0)
+ shadow_bytes[i] = 8 + (shadow_bytes[i + 1] > 7 ? 0 : shadow_bytes[i + 1]);
+ for (unsigned i = 0; i < shadow_mems.length (); i++)
+emit_move_insn (shadow_mems[i], asan_shadow_cst (&shadow_bytes[i * 4]));
+
do_pending_stack_adjust ();
/* Construct epilogue sequence. */
@@ -1285,34 +1319,8 @@ asan_emit_stack_protection (rtx base, rtx pbase, unsigned int alignb,
if (STRICT_ALIGNMENT)
set_mem_align (shadow_mem, (GET_MODE_ALIGNMENT (SImode
[PINGv4][PATCH] ASan on unaligned accesses
On 03/26/2015 02:50 PM, Jakub Jelinek wrote:
On Thu, Mar 26, 2015 at 09:53:03AM +0300, Marat Zakirov wrote:
gcc/ChangeLog:
2015-03-12 Marat Zakirov
* asan.c (asan_emit_stack_protection): Support for misalign accesses.
(asan_expand_check_ifn): Likewise.
* common.opt: New flag -fasan-catch-misaligned.
* doc/invoke.texi: New flag description.
* opts.c (finish_options): Add check for new flag.
(common_handle_option): Switch on flag if SANITIZE_KERNEL_ADDRESS.
Well, as all the other asan options are done as params, handling one option
differently is just too inconsistent.
The reason we went with params was that it was expected most users wouldn't
really need to play with the knobs, and we didn't want to be stuck in
supporting those forever (params aren't supported from one version to
another, can be replaced, removed, added etc.).
So, I think this really should be a param at this point and perhaps for GCC
6 we can discuss if we want to change the params into normal options.
Jakub
Fixed.
gcc/ChangeLog:
2015-02-25 Marat Zakirov
* asan.c (asan_emit_stack_protection): Support for misalign accesses.
(asan_expand_check_ifn): Likewise.
* params.def: New option asan-catch-misaligned.
* params.h: New param ASAN_CATCH_MISALIGNED.
* doc/invoke.texi: New asan param description.
gcc/testsuite/ChangeLog:
2015-02-25 Marat Zakirov
* c-c++-common/asan/misalign-catch.c: New test.
diff --git a/gcc/asan.c b/gcc/asan.c
index 9e4a629..0ac1a11 100644
--- a/gcc/asan.c
+++ b/gcc/asan.c
@@ -1050,7 +1050,6 @@ asan_emit_stack_protection (rtx base, rtx pbase, unsigned int alignb,
rtx_code_label *lab;
rtx_insn *insns;
char buf[30];
- unsigned char shadow_bytes[4];
HOST_WIDE_INT base_offset = offsets[length - 1];
HOST_WIDE_INT base_align_bias = 0, offset, prev_offset;
HOST_WIDE_INT asan_frame_size = offsets[0] - base_offset;
@@ -1059,6 +1058,7 @@ asan_emit_stack_protection (rtx base, rtx pbase, unsigned int alignb,
unsigned char cur_shadow_byte = ASAN_STACK_MAGIC_LEFT;
tree str_cst, decl, id;
int use_after_return_class = -1;
+ bool misalign = (flag_sanitize & SANITIZE_KERNEL_ADDRESS) || ASAN_CATCH_MISALIGNED;
if (shadow_ptr_types[0] == NULL_TREE)
asan_init_shadow_ptr_types ();
@@ -1193,11 +1193,37 @@ asan_emit_stack_protection (rtx base, rtx pbase, unsigned int alignb,
if (STRICT_ALIGNMENT)
set_mem_align (shadow_mem, (GET_MODE_ALIGNMENT (SImode)));
prev_offset = base_offset;
+
+ vec shadow_mems;
+ vec shadow_bytes;
+
+ shadow_mems.create(0);
+ shadow_bytes.create(0);
+
for (l = length; l; l -= 2)
{
if (l == 2)
cur_shadow_byte = ASAN_STACK_MAGIC_RIGHT;
offset = offsets[l - 1];
+ if (l != length && misalign)
+ {
+ HOST_WIDE_INT aoff
+ = base_offset + ((offset - base_offset)
+ & ~(ASAN_RED_ZONE_SIZE - HOST_WIDE_INT_1))
+ - ASAN_RED_ZONE_SIZE;
+ if (aoff > prev_offset)
+ {
+ shadow_mem = adjust_address (shadow_mem, VOIDmode,
+ (aoff - prev_offset)
+ >> ASAN_SHADOW_SHIFT);
+ prev_offset = aoff;
+ shadow_bytes.safe_push (0);
+ shadow_bytes.safe_push (0);
+ shadow_bytes.safe_push (0);
+ shadow_bytes.safe_push (0);
+ shadow_mems.safe_push (shadow_mem);
+ }
+ }
if ((offset - base_offset) & (ASAN_RED_ZONE_SIZE - 1))
{
int i;
@@ -1212,13 +1238,13 @@ asan_emit_stack_protection (rtx base, rtx pbase, unsigned int alignb,
if (aoff < offset)
{
if (aoff < offset - (1 << ASAN_SHADOW_SHIFT) + 1)
- shadow_bytes[i] = 0;
+ shadow_bytes.safe_push (0);
else
- shadow_bytes[i] = offset - aoff;
+ shadow_bytes.safe_push (offset - aoff);
}
else
- shadow_bytes[i] = ASAN_STACK_MAGIC_PARTIAL;
- emit_move_insn (shadow_mem, asan_shadow_cst (shadow_bytes));
+ shadow_bytes.safe_push (ASAN_STACK_MAGIC_PARTIAL);
+ shadow_mems.safe_push(shadow_mem);
offset = aoff;
}
while (offset <= offsets[l - 2] - ASAN_RED_ZONE_SIZE)
@@ -1227,12 +1253,21 @@ asan_emit_stack_protection (rtx base, rtx pbase, unsigned int alignb,
(offset - prev_offset)
>> ASAN_SHADOW_SHIFT);
prev_offset = offset;
- memset (shadow_bytes, cur_shadow_byte, 4);
- emit_move_insn (shadow_mem, asan_shadow_cst (shadow_bytes));
+ shadow_bytes.safe_push (cur_shadow_byte);
+ shadow_bytes.safe_push (cur_shadow_byte);
+ shadow_bytes.safe_push (cur_shadow_byte);
+ shadow_bytes.safe_push (cur_shadow_byte);
+ shadow_mems.safe_push(shadow_mem);
offset += ASAN_RED_ZONE_SIZE;
}
cur_shadow_byte = ASAN_STACK_MAGIC_MIDDLE;
}
+ for (unsigned i = 0; misalign && i < shadow_bytes.length () - 1; i++)
+if (shadow_bytes[i] == 0 && shadow_bytes[i + 1] > 0)
+ shadow_bytes[i] = 8 + (shadow_bytes[i + 1] > 7 ? 0 : shadow_bytes[i + 1]);
[PINGv5][PATCH] ASan on unaligned accesses
Hi Jakub!
On 03/30/2015 08:42 PM, Jakub Jelinek wrote:
Can you please start by explaining the asan_emit_stack_protection
changes? What is the problem there, what do you want to achieve etc.?
Is it to support ABI violating stack pointer alignment, or something
different? If so, the compiler knows (or should be aware) what the
stack alignment is. The asan_expand_check_ifn change looks reasonable.
This patch is needed to support ASan on codes (like Linux kernel) which
do not care about compiler stack alignment - see example from the
attached patch:
long long *ptr;
__attribute__((noinline))
void foo () {
ptr = ((long long int *)(((char *)ptr) + 1));
*ptr = 1;
}
int main ()
{
long long int local[9];
ptr = (long long *)&local[8];
foo ();
return 0;
}
In this example current ASan won't find invalid memory write. Attached
patch (with new --param asan-catch-misaligned=1) resolves this problem.
Also, the changes regress code quality without the parameter, say on
the testcase you've added at -O2 -fsanitize=address (no param used),
on x86_64 the patch causes undesirable movl $0, 2147450880(%rbp) -
movq $0, 2147450892(%rbp) + movl $0, 2147450892(%rbp) + movl $0,
2147450896(%rbp) change.
Fixed in new patch. But I believe joining movs (2 movl to one movq)
is a x86 RTL job - not ASan.
--Marat
gcc/ChangeLog:
2015-02-25 Marat Zakirov
* asan.c (asan_emit_stack_protection): Support for misalign accesses.
(asan_expand_check_ifn): Likewise.
* params.def: New option asan-catch-misaligned.
* params.h: New param ASAN_CATCH_MISALIGNED.
* doc/invoke.texi: New asan param description.
gcc/testsuite/ChangeLog:
2015-02-25 Marat Zakirov
* c-c++-common/asan/misalign-catch.c: New test.
diff --git a/gcc/asan.c b/gcc/asan.c
index 9e4a629..7f60014 100644
--- a/gcc/asan.c
+++ b/gcc/asan.c
@@ -1050,7 +1050,6 @@ asan_emit_stack_protection (rtx base, rtx pbase, unsigned int alignb,
rtx_code_label *lab;
rtx_insn *insns;
char buf[30];
- unsigned char shadow_bytes[4];
HOST_WIDE_INT base_offset = offsets[length - 1];
HOST_WIDE_INT base_align_bias = 0, offset, prev_offset;
HOST_WIDE_INT asan_frame_size = offsets[0] - base_offset;
@@ -1059,6 +1058,8 @@ asan_emit_stack_protection (rtx base, rtx pbase, unsigned int alignb,
unsigned char cur_shadow_byte = ASAN_STACK_MAGIC_LEFT;
tree str_cst, decl, id;
int use_after_return_class = -1;
+ bool misalign = (flag_sanitize & SANITIZE_KERNEL_ADDRESS)
+ || ASAN_CATCH_MISALIGNED;
if (shadow_ptr_types[0] == NULL_TREE)
asan_init_shadow_ptr_types ();
@@ -1193,11 +1194,37 @@ asan_emit_stack_protection (rtx base, rtx pbase, unsigned int alignb,
if (STRICT_ALIGNMENT)
set_mem_align (shadow_mem, (GET_MODE_ALIGNMENT (SImode)));
prev_offset = base_offset;
+
+ vec shadow_mems;
+ vec shadow_bytes;
+
+ shadow_mems.create (0);
+ shadow_bytes.create (0);
+
for (l = length; l; l -= 2)
{
if (l == 2)
cur_shadow_byte = ASAN_STACK_MAGIC_RIGHT;
offset = offsets[l - 1];
+ if (l != length && misalign)
+ {
+ HOST_WIDE_INT aoff
+ = base_offset + ((offset - base_offset)
+ & ~(ASAN_RED_ZONE_SIZE - HOST_WIDE_INT_1))
+ - ASAN_RED_ZONE_SIZE;
+ if (aoff > prev_offset)
+ {
+ shadow_mem = adjust_address (shadow_mem, VOIDmode,
+ (aoff - prev_offset)
+ >> ASAN_SHADOW_SHIFT);
+ prev_offset = aoff;
+ shadow_bytes.safe_push (0);
+ shadow_bytes.safe_push (0);
+ shadow_bytes.safe_push (0);
+ shadow_bytes.safe_push (0);
+ shadow_mems.safe_push (shadow_mem);
+ }
+ }
if ((offset - base_offset) & (ASAN_RED_ZONE_SIZE - 1))
{
int i;
@@ -1212,13 +1239,13 @@ asan_emit_stack_protection (rtx base, rtx pbase, unsigned int alignb,
if (aoff < offset)
{
if (aoff < offset - (1 << ASAN_SHADOW_SHIFT) + 1)
- shadow_bytes[i] = 0;
+ shadow_bytes.safe_push (0);
else
- shadow_bytes[i] = offset - aoff;
+ shadow_bytes.safe_push (offset - aoff);
}
else
- shadow_bytes[i] = ASAN_STACK_MAGIC_PARTIAL;
- emit_move_insn (shadow_mem, asan_shadow_cst (shadow_bytes));
+ shadow_bytes.safe_push (ASAN_STACK_MAGIC_PARTIAL);
+ shadow_mems.safe_push (shadow_mem);
offset = aoff;
}
while (offset <= offsets[l - 2] - ASAN_RED_ZONE_SIZE)
@@ -1227,12 +1254,21 @@ asan_emit_stack_protection (rtx base, rtx pbase, unsigned int alignb,
(offset - prev_offset)
>> ASAN_SHADOW_SHIFT);
prev_offset = offset;
- memset (shadow_bytes, cur_shadow_byte, 4);
- emit_move_insn (shadow_mem, asan_shadow_cst (shadow_bytes));
+ shadow_bytes.safe_push (cur_shadow_byte);
+ shadow_bytes.safe_push (cur_shadow_byte);
+ shadow_bytes.safe_push (cur_shadow_byte);
+ shadow_bytes.safe_push (cur_shadow_byte);
+ shadow_mems.safe_push (shadow_mem);
offset += ASAN_RED_ZONE_SIZE;
}
cur_shadow_byte =
[PINGv10][PATCH] ASan on unaligned accesses
On 06/02/2015 04:11 PM, Marat Zakirov wrote:
On 05/26/2015 05:03 PM, Marat Zakirov wrote:
On 05/20/2015 10:01 AM, Marat Zakirov wrote:
On 05/12/2015 02:16 PM, Marat Zakirov wrote:
On 04/07/2015 03:22 PM, Jakub Jelinek wrote:
How are the automatic misaligned variables different from say heap
allocated ones, or global vars etc.?
No difference you are right Jakub. Shadow memory initialization for
heap values and globals of course also should be changed but it is
a task for libsanitizer not ASan for which I am sending patch. Fix
for libsanitizer to support unaligned heaps and globals will be
committed by a separate patch.
Well, a RTL solution I've tried at http://gcc.gnu.org/PR22141, but
it gave
mixed results, so either it needs more cost tuning when it is
desirable and
when it is not, or perhaps better do that still on GIMPLE instead,
together
with trying to optimize bitfield accesses and other cases of adjacent
location accesses. But if we handle that on GIMPLE, it won't
really affect
what asan RTL emitting code produces.
Jakub
I fixed the issue with 'movq' you were mentioned in a previous mail.
--Marat
gcc/ChangeLog:
2015-02-25 Marat Zakirov
* asan.c (asan_emit_stack_protection): Support for misalign accesses.
(asan_expand_check_ifn): Likewise.
* params.def: New option asan-catch-misaligned.
* params.h: New param ASAN_CATCH_MISALIGNED.
* doc/invoke.texi: New asan param description.
gcc/testsuite/ChangeLog:
2015-02-25 Marat Zakirov
* c-c++-common/asan/misalign-catch.c: New test.
diff --git a/gcc/asan.c b/gcc/asan.c
index 9e4a629..f9d052f 100644
--- a/gcc/asan.c
+++ b/gcc/asan.c
@@ -1050,7 +1050,6 @@ asan_emit_stack_protection (rtx base, rtx pbase, unsigned int alignb,
rtx_code_label *lab;
rtx_insn *insns;
char buf[30];
- unsigned char shadow_bytes[4];
HOST_WIDE_INT base_offset = offsets[length - 1];
HOST_WIDE_INT base_align_bias = 0, offset, prev_offset;
HOST_WIDE_INT asan_frame_size = offsets[0] - base_offset;
@@ -1059,6 +1058,8 @@ asan_emit_stack_protection (rtx base, rtx pbase, unsigned int alignb,
unsigned char cur_shadow_byte = ASAN_STACK_MAGIC_LEFT;
tree str_cst, decl, id;
int use_after_return_class = -1;
+ bool misalign = (flag_sanitize & SANITIZE_KERNEL_ADDRESS)
+ || ASAN_CATCH_MISALIGNED;
if (shadow_ptr_types[0] == NULL_TREE)
asan_init_shadow_ptr_types ();
@@ -1193,11 +1194,37 @@ asan_emit_stack_protection (rtx base, rtx pbase, unsigned int alignb,
if (STRICT_ALIGNMENT)
set_mem_align (shadow_mem, (GET_MODE_ALIGNMENT (SImode)));
prev_offset = base_offset;
+
+ vec shadow_mems;
+ vec shadow_bytes;
+
+ shadow_mems.create (0);
+ shadow_bytes.create (0);
+
for (l = length; l; l -= 2)
{
if (l == 2)
cur_shadow_byte = ASAN_STACK_MAGIC_RIGHT;
offset = offsets[l - 1];
+ if (l != length && misalign)
+ {
+ HOST_WIDE_INT aoff
+ = base_offset + ((offset - base_offset)
+ & ~(ASAN_RED_ZONE_SIZE - HOST_WIDE_INT_1))
+ - ASAN_RED_ZONE_SIZE;
+ if (aoff > prev_offset)
+ {
+ shadow_mem = adjust_address (shadow_mem, VOIDmode,
+ (aoff - prev_offset)
+ >> ASAN_SHADOW_SHIFT);
+ prev_offset = aoff;
+ shadow_bytes.safe_push (0);
+ shadow_bytes.safe_push (0);
+ shadow_bytes.safe_push (0);
+ shadow_bytes.safe_push (0);
+ shadow_mems.safe_push (shadow_mem);
+ }
+ }
if ((offset - base_offset) & (ASAN_RED_ZONE_SIZE - 1))
{
int i;
@@ -1212,13 +1239,13 @@ asan_emit_stack_protection (rtx base, rtx pbase, unsigned int alignb,
if (aoff < offset)
{
if (aoff < offset - (1 << ASAN_SHADOW_SHIFT) + 1)
- shadow_bytes[i] = 0;
+ shadow_bytes.safe_push (0);
else
- shadow_bytes[i] = offset - aoff;
+ shadow_bytes.safe_push (offset - aoff);
}
else
- shadow_bytes[i] = ASAN_STACK_MAGIC_PARTIAL;
- emit_move_insn (shadow_mem, asan_shadow_cst (shadow_bytes));
+ shadow_bytes.safe_push (ASAN_STACK_MAGIC_PARTIAL);
+ shadow_mems.safe_push (shadow_mem);
offset = aoff;
}
while (offset <= offsets[l - 2] - ASAN_RED_ZONE_SIZE)
@@ -1227,12 +1254,21 @@ asan_emit_stack_protection (rtx base, rtx pbase, unsigned int alignb,
(offset - prev_offset)
>> ASAN_SHADOW_SHIFT);
prev_offset = offset;
- memset (shadow_bytes, cur_shadow_byte, 4);
- emit_move_insn (shadow_mem, asan_shadow_cst (shadow_bytes));
+ shadow_bytes.safe_push (cur_shadow_byte);
+ shadow_bytes.safe_push (cur_shadow_byte);
+ shadow_bytes.safe_push (cur_shadow_byte);
+ shadow_bytes.safe_push (cur_shadow_byte);
+ shadow_mems.safe_push (shadow_mem);
offset += ASAN_RED_ZONE_SIZE;
}
cur_shadow_byte = ASAN_STACK_MAGIC_MIDDLE;
}
+ for (unsigned i = 0; misalign && i < shadow_bytes.length () - 1; i++)
+if (shadow_bytes[i] == 0 && shadow_bytes[i
[PATCH] ASan phase place change
Hi all!
Here is simple patch that moves asan phase just behind sanopt for all
O0/O1/O2/O3 modes which gives +7% on x86 SPEC2006 (ref dataset). Regression
testing and sanitized GCC bootstrapping were successfully done.
Performance data attached.
--Marat
PATCH REFPERCENT
400.perlbench1319 1334 1.14%
401.bzip27007182.57%
403.gcc 5866185.46%
429.mcf 43552119.77%
445.gobmk7207504.17%
456.hmmer8158160.12%
458.sjeng8909193.26%
462.libquantum 3273476.12%
464.h264ref 1353 1600 18.26%
471.omnetpp 738730-1.08%
473.astar5365441.49%
483.xalancbmk54461513.05%
410.bwaves 1939 1938 -0.05%
416.gamess 3201 3202 0.03%
433.milc 41954028.88%
434.zeusmp 1641 1641 0.00%
435.gromacs 9239381.63%
436.cactusADM2970 2973 0.10%
437.leslie3d 1564 1588 1.53%
444.namd 4844901.24%
447.dealII 59167614.38%
450.soplex 3203488.75%
453.povray 3223281.86%
459.GemsFDTD 1921 1950 1.51%
465.tonto1621 1641 1.23%
470.lbm 25233733.73%
482.sphinx3 65694343.75%
GEOMEAN7.07%
gcc/ChangeLog:
2015-02-20 Marat Zakirov
* asan.c (make_pass_asan_O0): Pass remove.
* passes.def: Change place for ASan pass.
* tree-pass.h: Passes remove.
* tsan.c (make_pass_tsan_O0): Pass remove.
gcc/testsuite/ChangeLog:
2015-02-20 Marat Zakirov
* c-c++-common/asan/inc.c: Fix option.
diff --git a/gcc/asan.c b/gcc/asan.c
index b7c2b11..001d79e 100644
--- a/gcc/asan.c
+++ b/gcc/asan.c
@@ -2796,40 +2796,4 @@ make_pass_asan (gcc::context *ctxt)
return new pass_asan (ctxt);
}
-namespace {
-
-const pass_data pass_data_asan_O0 =
-{
- GIMPLE_PASS, /* type */
- "asan0", /* name */
- OPTGROUP_NONE, /* optinfo_flags */
- TV_NONE, /* tv_id */
- ( PROP_ssa | PROP_cfg | PROP_gimple_leh ), /* properties_required */
- 0, /* properties_provided */
- 0, /* properties_destroyed */
- 0, /* todo_flags_start */
- TODO_update_ssa, /* todo_flags_finish */
-};
-
-class pass_asan_O0 : public gimple_opt_pass
-{
-public:
- pass_asan_O0 (gcc::context *ctxt)
-: gimple_opt_pass (pass_data_asan_O0, ctxt)
- {}
-
- /* opt_pass methods: */
- virtual bool gate (function *) { return !optimize && gate_asan (); }
- virtual unsigned int execute (function *) { return asan_instrument (); }
-
-}; // class pass_asan_O0
-
-} // anon namespace
-
-gimple_opt_pass *
-make_pass_asan_O0 (gcc::context *ctxt)
-{
- return new pass_asan_O0 (ctxt);
-}
-
#include "gt-asan.h"
diff --git a/gcc/passes.def b/gcc/passes.def
index 2bc5dcd..398d8dc 100644
--- a/gcc/passes.def
+++ b/gcc/passes.def
@@ -214,8 +214,6 @@ along with GCC; see the file COPYING3. If not see
NEXT_PASS (pass_split_crit_edges);
NEXT_PASS (pass_pre);
NEXT_PASS (pass_sink_code);
- NEXT_PASS (pass_asan);
- NEXT_PASS (pass_tsan);
/* Pass group that runs when 1) enabled, 2) there are loops
in the function. Make sure to run pass_fix_loops before
to discover/remove loops before running the gate function
@@ -344,8 +342,8 @@ along with GCC; see the file COPYING3. If not see
NEXT_PASS (pass_vtable_verify);
NEXT_PASS (pass_lower_vector);
NEXT_PASS (pass_lower_complex_O0);
- NEXT_PASS (pass_asan_O0);
- NEXT_PASS (pass_tsan_O0);
+ NEXT_PASS (pass_asan);
+ NEXT_PASS (pass_tsan);
NEXT_PASS (pass_sanopt);
NEXT_PASS (pass_cleanup_eh);
NEXT_PASS (pass_lower_resx);
diff --git a/gcc/testsuite/c-c++-common/asan/inc.c b/gcc/testsuite/c-c++-common/asan/inc.c
index 36cc3d8..8c38150 100644
--- a/gcc/testsuite/c-c++-common/asan/inc.c
+++ b/gcc/testsuite/c-c++-common/asan/inc.c
@@ -1,4 +1,4 @@
-/* { dg-options "-fdump-tree-asan0" } */
+/* { dg-options "-fdump-tree-asan" } */
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "*" } { "-O0" } } */
@@ -16,6 +16,6 @@ main ()
return 0;
}
-/* { dg-final { scan-tree-dump-times "ASAN_" 1 "asan0" } } */
-/* { dg-final { scan-tree-dump "ASAN_CHECK \\(.*, 4\\);" "asan0" } } */
-/* { dg-final { cleanup-tree-dump "asan0" } } */
+/* { dg-final { scan-tree-dump-times "ASAN_" 1 "asan" } } */
+/* { dg-final { scan-tree-dump "ASAN_
[PATCH] Fix for mklog
Hi all,
Current mklog in some cases do not checks whether function have real
changes or not. I fixed it by removing $doubtfunc and adding protection
against EOF.
Example:
diff --git a/gcc/cfg.c b/gcc/cfg.c
index 6070d9e..cb3dfd9 100644
--- a/gcc/cfg.c
+++ b/gcc/cfg.c
@@ -555,10 +555,10 @@ alloc_aux_for_block (basic_block bb, int size)
}
+void
+free_aux_for_edges (void)
+{
+ free_aux_for_edges (cfun);
+}
+
DEBUG_FUNCTION void
debug_bb (basic_block bb)
{
Current mklog output, function debug_bb is reported but it does not have
any changes within.
gcc/ChangeLog:
DATE
* cfg.c (free_aux_for_edges):
(debug_bb):
Patched mklog output:
gcc/ChangeLog:
DATE
* cfg.c (free_aux_for_edges):
Ok to commit?
--Marat
contrib/ChangeLog:
2014-11-05 Marat Zakirov
* mklog: Always doubt in functions.
Add EOF protection.
diff --git a/contrib/mklog b/contrib/mklog
index 6ed4c6e..8e3c6b6 100755
--- a/contrib/mklog
+++ b/contrib/mklog
@@ -108,10 +108,22 @@ sub remove_suffixes ($) {
return $filename;
}
+sub is_context_hunk_start {
+ return @_[0] =~ /^\*\*\*\*\*\** ([a-zA-Z0-9_].*)/;
+}
+
+sub is_unified_hunk_start {
+ return @_[0] =~ /^@@ .* @@ ([a-zA-Z0-9_].*)/;
+}
+
# Check if line is a top-level declaration.
# TODO: ignore preprocessor directives except maybe #define ?
sub is_top_level {
my ($function, $is_context_diff) = (@_);
+ if (is_unified_hunk_start ($function)
+ || is_context_hunk_start ($function)) {
+ return 1;
+ }
if ($is_context_diff) {
$function =~ s/^..//;
} else {
@@ -200,14 +212,10 @@ foreach (@diff_lines) {
$look_for_funs = 0;
}
-# Mark if we met doubtfully changed function.
-$doubtfunc = 0;
-if ($diff_lines[$line_idx] =~ /^@@ .* @@ ([a-zA-Z0-9_].*)/) {
- $doubtfunc = 1;
+if (is_unified_hunk_start ($diff_lines[$line_idx])) {
$is_context_diff = 0;
}
-elsif ($diff_lines[$line_idx] =~ /^\*\*\*\*\*\** ([a-zA-Z0-9_].*)/) {
- $doubtfunc = 1;
+elsif (is_context_hunk_start ($diff_lines[$line_idx])) {
$is_context_diff = 1;
}
@@ -222,7 +230,6 @@ foreach (@diff_lines) {
#
# The third pattern looks for the starts of functions or classes
# within a diff block both for context and unified diff files.
-
if ($look_for_funs
&& (/^\*\*\*\*\*\** ([a-zA-Z0-9_].*)/
|| /^@@ .* @@ ([a-zA-Z0-9_].*)/
@@ -249,19 +256,19 @@ foreach (@diff_lines) {
}
# Check is function really modified
$no_real_change = 0;
- if ($doubtfunc) {
- $idx = $line_idx;
+ $idx = $line_idx;
# Skip line info in context diffs.
- while ($is_context_diff && $diff_lines[$idx + 1] =~ /^[-\*]{3} [0-9]/) {
- ++$idx;
- }
+ while ($idx <= $#diff_lines && $is_context_diff
+ && $diff_lines[$idx + 1] =~ /^[-\*]{3} [0-9]/) {
+ ++$idx;
+ }
# Check all lines till the first change
# for the presence of really changed function
- do {
- ++$idx;
- $no_real_change = is_top_level ($diff_lines[$idx], $is_context_diff);
- } while (!$no_real_change && ($diff_lines[$idx] !~ /^[-+!]/))
- }
+ do {
+ ++$idx;
+ $no_real_change = $idx > $#diff_lines
+ || is_top_level ($diff_lines[$idx], $is_context_diff);
+ } while (!$no_real_change && ($diff_lines[$idx] !~ /^[-+!]/));
if ($fn && !$seen_names{$fn} && !$no_real_change) {
# If this is the first function in the file, we display it next
# to the filename, so we need an extra space before the opening
[PATCH] Fix for mklog
Hi all!
I found another issue of mklog.
Example:
--- a/gcc/asan.h
+++ b/gcc/asan.h
@@ -103,4 +103,14 @@ asan_intercepted_p (enum built_in_function fcode)
|| fcode == BUILT_IN_STRNCMP
|| fcode == BUILT_IN_STRNCPY;
}
+
+/* Convert LEN to HOST_WIDE_INT if possible.
+ Returns -1 otherwise. */
+
+static inline HOST_WIDE_INT
+maybe_tree_to_shwi (tree len)
+{
+ return tree_fits_shwi_p (len) ? tree_to_shwi (len) : -1;
+}
+
#endif /* TREE_ASAN */
mklog output:
gcc/ChangeLog:
DATE
* asan.h (asan_intercepted_p):
(maybe_tree_to_shwi):
Currently mklog finds some changes for asan_intercepted_p which are do
not exist.
Patched mklog output:
gcc/ChangeLog:
DATE
* asan.h (maybe_tree_to_shwi):
Attached patch make mklog to stop search for changes inside function
once '}' occur.
Ok, to commit?
--Marat
contrib/ChangeLog:
2014-11-06 Marat Zakirov
* mklog: Symbol '}' stops search for changes.
diff --git a/contrib/mklog b/contrib/mklog
index 6ed4c6e..7de485d 100755
--- a/contrib/mklog
+++ b/contrib/mklog
@@ -117,7 +117,7 @@ sub is_top_level {
} else {
$function =~ s/^.//;
}
- return $function && $function !~ /^[\s{}]/;
+ return $function && $function !~ /^[\s{]/;
}
# For every file in the .diff print all the function names in ChangeLog
[PATCH] Disable aggressive optimizations for sanitizer.
Hi!
I have a patch which disables -faggressive-loop-optimizations and
-fstrict-overflow when -fsanitize=undefined is switched on. Compiler
with aggressive optimizations may decrease quality of sanitization by
optimistically proposing something it actually should check.
Details are in https://gcc.gnu.org/ml/gcc/2014-11/msg00148.html
--Marat
gcc/ChangeLog:
2014-11-12 Marat Zakirov
* opts.c (finish_options): Disable aggressive opts for sanitizer.
(common_handle_option): Move code to finish_options.
gcc/testsuite/ChangeLog:
2014-11-12 Marat Zakirov
* c-c++-common/asan/aggressive-opts.c: New test.
diff --git a/gcc/opts.c b/gcc/opts.c
index 752cc84..db7768f 100644
--- a/gcc/opts.c
+++ b/gcc/opts.c
@@ -903,6 +903,19 @@ finish_options (struct gcc_options *opts, struct gcc_options *opts_set,
if (opts->x_flag_sanitize_recover & SANITIZE_LEAK)
error_at (loc, "-fsanitize-recover=leak is not supported");
+
+ /* When instrumenting the pointers, we don't want to remove
+ the null pointer checks. */
+ if (opts->x_flag_sanitize & (SANITIZE_NULL | SANITIZE_NONNULL_ATTRIBUTE
+| SANITIZE_RETURNS_NONNULL_ATTRIBUTE))
+opts->x_flag_delete_null_pointer_checks = 0;
+
+ /* Aggressive compiler optimizations may cause false negatives. */
+ if (opts->x_flag_sanitize)
+{
+ opts->x_flag_aggressive_loop_optimizations = 0;
+ opts->x_flag_strict_overflow = 0;
+}
}
#define LEFT_COLUMN 27
@@ -1621,12 +1634,6 @@ common_handle_option (struct gcc_options *opts,
if (code != OPT_fsanitize_)
break;
- /* When instrumenting the pointers, we don't want to remove
- the null pointer checks. */
- if (opts->x_flag_sanitize & (SANITIZE_NULL | SANITIZE_NONNULL_ATTRIBUTE
- | SANITIZE_RETURNS_NONNULL_ATTRIBUTE))
- opts->x_flag_delete_null_pointer_checks = 0;
-
/* Kernel ASan implies normal ASan but does not yet support
all features. */
if (opts->x_flag_sanitize & SANITIZE_KERNEL_ADDRESS)
diff --git a/gcc/testsuite/c-c++-common/asan/aggressive-opts.c b/gcc/testsuite/c-c++-common/asan/aggressive-opts.c
new file mode 100644
index 000..dfb2f0e
--- /dev/null
+++ b/gcc/testsuite/c-c++-common/asan/aggressive-opts.c
@@ -0,0 +1,28 @@
+/* { dg-options "-fdump-tree-asan" } */
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "*" } { "-O3" } } */
+
+int ext;
+
+int
+Perl_do_sv_dump()
+{
+int freq[10];
+int i;
+int max = 0;
+
+if (max < ext)
+ max = ext;
+
+for (i = 0; i <= max; i++)
+ if (freq[i])
+ ext = 0;
+
+if (i > 20)
+ return freq[i];
+else
+ return 0;
+}
+
+/* { dg-final { scan-tree-dump-times "ASAN_CHECK" 2 "asan1" } } */
+/* { dg-final { cleanup-tree-dump "asan" } } */
[PINGv2][PATCH] Ignore alignment by option
On 11/27/2014 05:14 PM, Marat Zakirov wrote:
On 11/19/2014 06:01 PM, Marat Zakirov wrote:
Hi all!
Here is the patch which forces ASan to ignore alignment of memory
access. It increases ASan overhead but it's still useful because some
programs like linux kernel often cheat with alignment which may cause
false negatives.
--Marat
gcc/ChangeLog:
2014-11-14 Marat Zakirov
* asan.c (asan_expand_check_ifn): Ignore alignment by option.
* doc/invoke.texi: Document.
* params.def (asan-alignment-optimize): New.
* params.h: Likewise.
gcc/testsuite/ChangeLog:
2014-11-14 Marat Zakirov
* c-c++-common/asan/red-align-3.c: New test.
diff --git a/gcc/asan.c b/gcc/asan.c
index 79dede7..4f86088 100644
--- a/gcc/asan.c
+++ b/gcc/asan.c
@@ -2518,6 +2518,12 @@ asan_expand_check_ifn (gimple_stmt_iterator *iter, bool use_calls)
HOST_WIDE_INT size_in_bytes
= is_scalar_access && tree_fits_shwi_p (len) ? tree_to_shwi (len) : -1;
+
+ if (!ASAN_ALIGNMENT_OPTIMIZE && size_in_bytes > 1)
+{
+ size_in_bytes = -1;
+ align = 1;
+}
if (use_calls)
{
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 13270bc..8f43c06 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -10580,6 +10580,12 @@ is greater or equal to this number, use callbacks instead of inline checks.
E.g. to disable inline code use
@option{--param asan-instrumentation-with-call-threshold=0}.
+@item asan-alignment-optimize
+Enable asan optimization for aligned accesses.
+It is enabled by default when using @option{-fsanitize=address} option.
+To disable optimization for aligned accesses use
+@option{--param asan-alignment-optimize=0}.
+
@item chkp-max-ctor-size
Static constructors generated by Pointer Bounds Checker may become very
large and significantly increase compile time at optimization level
diff --git a/gcc/params.def b/gcc/params.def
index d2d2add..fbccf46 100644
--- a/gcc/params.def
+++ b/gcc/params.def
@@ -1114,6 +1114,11 @@ DEFPARAM (PARAM_ASAN_INSTRUMENTATION_WITH_CALL_THRESHOLD,
"in function becomes greater or equal to this number",
7000, 0, INT_MAX)
+DEFPARAM (PARAM_ASAN_ALIGNMENT_OPTIMIZE,
+ "asan-alignment-optimize",
+ "Enable asan optimization for aligned access",
+ 1, 0, 1)
+
DEFPARAM (PARAM_UNINIT_CONTROL_DEP_ATTEMPTS,
"uninit-control-dep-attempts",
"Maximum number of nested calls to search for control dependencies "
diff --git a/gcc/params.h b/gcc/params.h
index 4779e17..e2973d4 100644
--- a/gcc/params.h
+++ b/gcc/params.h
@@ -238,5 +238,7 @@ extern void init_param_values (int *params);
PARAM_VALUE (PARAM_ASAN_USE_AFTER_RETURN)
#define ASAN_INSTRUMENTATION_WITH_CALL_THRESHOLD \
PARAM_VALUE (PARAM_ASAN_INSTRUMENTATION_WITH_CALL_THRESHOLD)
+#define ASAN_ALIGNMENT_OPTIMIZE \
+ PARAM_VALUE (PARAM_ASAN_ALIGNMENT_OPTIMIZE)
#endif /* ! GCC_PARAMS_H */
diff --git a/gcc/testsuite/c-c++-common/asan/ignore_align.c b/gcc/testsuite/c-c++-common/asan/ignore_align.c
new file mode 100644
index 000..989958b
--- /dev/null
+++ b/gcc/testsuite/c-c++-common/asan/ignore_align.c
@@ -0,0 +1,34 @@
+/* { dg-options "-fdump-tree-sanopt --param asan-alignment-optimize=0" } */
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-flto" } { "" } } */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+void *memset (void *, int, __SIZE_TYPE__);
+#ifdef __cplusplus
+}
+#endif
+
+struct dummy {
+ int a;
+ int b;
+ int c;
+ int d;
+};
+
+volatile struct dummy * new_p;
+volatile struct dummy * old_p;
+
+void foo(void)
+{
+ *(volatile char *)(0x12);
+ *(volatile short int *)(0x12);
+ *(volatile unsigned int *)(0x12);
+ *(volatile unsigned long long *)(0x12);
+ *new_p = *old_p;
+}
+
+/* { dg-final { scan-tree-dump-times ">> 3" 11 "sanopt" } } */
+/* { dg-final { scan-tree-dump-times "& 7" 11 "sanopt" } } */
+/* { dg-final { cleanup-tree-dump "sanopt" } } */
[PING][PATCH] Asan optimization for aligned accesses.
On 09/02/2014 07:09 PM, Marat Zakirov wrote:
Hi all!
Here's a simple optimization patch for Asan. It stores alignment
information into ASAN_CHECK which is then extracted by sanopt to
reduce number of "and 0x7" instructions for sufficiently aligned
accesses. I checked it on linux kernel by comparing results of
objdump -d -j .text vmlinux | grep "and.*0x7," for optimized and
regular cases. It eliminates 12% of and 0x7's.
No regressions. Sanitized GCC was successfully Asan-bootstrapped. No
false positives were found in kernel.
--Marat
gcc/ChangeLog:
2014-09-02 Marat Zakirov
* asan.c (build_check_stmt): Alignment arg was added.
(asan_expand_check_ifn): Optimization for alignment >= 8.
gcc/testsuite/ChangeLog:
2014-09-02 Marat Zakirov
* c-c++-common/asan/red-align-1.c: New test.
* c-c++-common/asan/red-align-2.c: New test.
diff --git a/gcc/asan.c b/gcc/asan.c
index 58e7719..aed5ede 100644
--- a/gcc/asan.c
+++ b/gcc/asan.c
@@ -1639,9 +1639,11 @@ build_check_stmt (location_t loc, tree base, tree len,
if (end_instrumented)
flags |= ASAN_CHECK_END_INSTRUMENTED;
- g = gimple_build_call_internal (IFN_ASAN_CHECK, 3,
+ g = gimple_build_call_internal (IFN_ASAN_CHECK, 4,
build_int_cst (integer_type_node, flags),
- base, len);
+ base, len,
+ build_int_cst (integer_type_node,
+ align/BITS_PER_UNIT));
gimple_set_location (g, loc);
if (before_p)
gsi_insert_before (&gsi, g, GSI_SAME_STMT);
@@ -2434,6 +2436,7 @@ asan_expand_check_ifn (gimple_stmt_iterator *iter, bool use_calls)
tree base = gimple_call_arg (g, 1);
tree len = gimple_call_arg (g, 2);
+ HOST_WIDE_INT align = tree_to_shwi (gimple_call_arg (g, 3));
HOST_WIDE_INT size_in_bytes
= is_scalar_access && tree_fits_shwi_p (len) ? tree_to_shwi (len) : -1;
@@ -2547,7 +2550,10 @@ asan_expand_check_ifn (gimple_stmt_iterator *iter, bool use_calls)
gimple shadow_test = build_assign (NE_EXPR, shadow, 0);
gimple_seq seq = NULL;
gimple_seq_add_stmt (&seq, shadow_test);
- gimple_seq_add_stmt (&seq, build_assign (BIT_AND_EXPR, base_addr, 7));
+ /* Aligned (>= 8 bytes) access do not need & 7. */
+ if (align < 8)
+ gimple_seq_add_stmt (&seq, build_assign (BIT_AND_EXPR,
+ base_addr, 7));
gimple_seq_add_stmt (&seq, build_type_cast (shadow_type,
gimple_seq_last (seq)));
if (real_size_in_bytes > 1)
diff --git a/gcc/internal-fn.def b/gcc/internal-fn.def
index 7ae60f3..54ade9f 100644
--- a/gcc/internal-fn.def
+++ b/gcc/internal-fn.def
@@ -55,4 +55,4 @@ DEF_INTERNAL_FN (UBSAN_CHECK_SUB, ECF_CONST | ECF_LEAF | ECF_NOTHROW, NULL)
DEF_INTERNAL_FN (UBSAN_CHECK_MUL, ECF_CONST | ECF_LEAF | ECF_NOTHROW, NULL)
DEF_INTERNAL_FN (ABNORMAL_DISPATCHER, ECF_NORETURN, NULL)
DEF_INTERNAL_FN (BUILTIN_EXPECT, ECF_CONST | ECF_LEAF | ECF_NOTHROW, NULL)
-DEF_INTERNAL_FN (ASAN_CHECK, ECF_TM_PURE | ECF_LEAF | ECF_NOTHROW, ".W..")
+DEF_INTERNAL_FN (ASAN_CHECK, ECF_TM_PURE | ECF_LEAF | ECF_NOTHROW, ".W...")
diff --git a/gcc/testsuite/c-c++-common/asan/red-align-1.c b/gcc/testsuite/c-c++-common/asan/red-align-1.c
new file mode 100644
index 000..1edb3a2
--- /dev/null
+++ b/gcc/testsuite/c-c++-common/asan/red-align-1.c
@@ -0,0 +1,20 @@
+/* This tests aligment propagation to structure elem and
+ abcense of redudant & 7. */
+
+/* { dg-options "-fdump-tree-sanopt" } */
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-flto" } { "" } } */
+
+struct st {
+ int a;
+ int b;
+ int c;
+} __attribute__((aligned(16)));
+
+int foo (struct st * s_p)
+{
+ return s_p->a;
+}
+
+/* { dg-final { scan-tree-dump-times "& 7" 0 "sanopt" } } */
+/* { dg-final { cleanup-tree-dump "sanopt" } } */
diff --git a/gcc/testsuite/c-c++-common/asan/red-align-2.c b/gcc/testsuite/c-c++-common/asan/red-align-2.c
new file mode 100644
index 000..161fe3c
--- /dev/null
+++ b/gcc/testsuite/c-c++-common/asan/red-align-2.c
@@ -0,0 +1,20 @@
+/* This tests aligment propagation to structure elem and
+ abcense of redudant & 7. */
+
+/* { dg-options "-fdump-tree-sanopt" } */
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-flto" } { "" } } */
+
+struct st {
+ int a;
+ int b;
+ int c;
+} __attribute__((aligned(16)));
+
+int foo (struct st * s_p)
+{
+ return s_p->b;
+}
+
+/* { dg-final { scan-tree-dump-times "& 7" 1 "sanopt" } } */
+/* { dg-final { cleanup-tree-dump "sanopt" } } */
[PINGv2][PATCH] Asan optimization for aligned accesses.
On 09/10/2014 04:30 PM, Marat Zakirov wrote:
On 09/02/2014 07:09 PM, Marat Zakirov wrote:
Hi all!
Here's a simple optimization patch for Asan. It stores alignment
information into ASAN_CHECK which is then extracted by sanopt to
reduce number of "and 0x7" instructions for sufficiently aligned
accesses. I checked it on linux kernel by comparing results of
objdump -d -j .text vmlinux | grep "and.*0x7," for optimized and
regular cases. It eliminates 12% of and 0x7's.
No regressions. Sanitized GCC was successfully Asan-bootstrapped. No
false positives were found in kernel.
--Marat
gcc/ChangeLog:
2014-09-02 Marat Zakirov
* asan.c (build_check_stmt): Alignment arg was added.
(asan_expand_check_ifn): Optimization for alignment >= 8.
gcc/testsuite/ChangeLog:
2014-09-02 Marat Zakirov
* c-c++-common/asan/red-align-1.c: New test.
* c-c++-common/asan/red-align-2.c: New test.
diff --git a/gcc/asan.c b/gcc/asan.c
index 58e7719..aed5ede 100644
--- a/gcc/asan.c
+++ b/gcc/asan.c
@@ -1639,9 +1639,11 @@ build_check_stmt (location_t loc, tree base, tree len,
if (end_instrumented)
flags |= ASAN_CHECK_END_INSTRUMENTED;
- g = gimple_build_call_internal (IFN_ASAN_CHECK, 3,
+ g = gimple_build_call_internal (IFN_ASAN_CHECK, 4,
build_int_cst (integer_type_node, flags),
- base, len);
+ base, len,
+ build_int_cst (integer_type_node,
+ align/BITS_PER_UNIT));
gimple_set_location (g, loc);
if (before_p)
gsi_insert_before (&gsi, g, GSI_SAME_STMT);
@@ -2434,6 +2436,7 @@ asan_expand_check_ifn (gimple_stmt_iterator *iter, bool use_calls)
tree base = gimple_call_arg (g, 1);
tree len = gimple_call_arg (g, 2);
+ HOST_WIDE_INT align = tree_to_shwi (gimple_call_arg (g, 3));
HOST_WIDE_INT size_in_bytes
= is_scalar_access && tree_fits_shwi_p (len) ? tree_to_shwi (len) : -1;
@@ -2547,7 +2550,10 @@ asan_expand_check_ifn (gimple_stmt_iterator *iter, bool use_calls)
gimple shadow_test = build_assign (NE_EXPR, shadow, 0);
gimple_seq seq = NULL;
gimple_seq_add_stmt (&seq, shadow_test);
- gimple_seq_add_stmt (&seq, build_assign (BIT_AND_EXPR, base_addr, 7));
+ /* Aligned (>= 8 bytes) access do not need & 7. */
+ if (align < 8)
+ gimple_seq_add_stmt (&seq, build_assign (BIT_AND_EXPR,
+ base_addr, 7));
gimple_seq_add_stmt (&seq, build_type_cast (shadow_type,
gimple_seq_last (seq)));
if (real_size_in_bytes > 1)
diff --git a/gcc/internal-fn.def b/gcc/internal-fn.def
index 7ae60f3..54ade9f 100644
--- a/gcc/internal-fn.def
+++ b/gcc/internal-fn.def
@@ -55,4 +55,4 @@ DEF_INTERNAL_FN (UBSAN_CHECK_SUB, ECF_CONST | ECF_LEAF | ECF_NOTHROW, NULL)
DEF_INTERNAL_FN (UBSAN_CHECK_MUL, ECF_CONST | ECF_LEAF | ECF_NOTHROW, NULL)
DEF_INTERNAL_FN (ABNORMAL_DISPATCHER, ECF_NORETURN, NULL)
DEF_INTERNAL_FN (BUILTIN_EXPECT, ECF_CONST | ECF_LEAF | ECF_NOTHROW, NULL)
-DEF_INTERNAL_FN (ASAN_CHECK, ECF_TM_PURE | ECF_LEAF | ECF_NOTHROW, ".W..")
+DEF_INTERNAL_FN (ASAN_CHECK, ECF_TM_PURE | ECF_LEAF | ECF_NOTHROW, ".W...")
diff --git a/gcc/testsuite/c-c++-common/asan/red-align-1.c b/gcc/testsuite/c-c++-common/asan/red-align-1.c
new file mode 100644
index 000..1edb3a2
--- /dev/null
+++ b/gcc/testsuite/c-c++-common/asan/red-align-1.c
@@ -0,0 +1,20 @@
+/* This tests aligment propagation to structure elem and
+ abcense of redudant & 7. */
+
+/* { dg-options "-fdump-tree-sanopt" } */
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-flto" } { "" } } */
+
+struct st {
+ int a;
+ int b;
+ int c;
+} __attribute__((aligned(16)));
+
+int foo (struct st * s_p)
+{
+ return s_p->a;
+}
+
+/* { dg-final { scan-tree-dump-times "& 7" 0 "sanopt" } } */
+/* { dg-final { cleanup-tree-dump "sanopt" } } */
diff --git a/gcc/testsuite/c-c++-common/asan/red-align-2.c b/gcc/testsuite/c-c++-common/asan/red-align-2.c
new file mode 100644
index 000..161fe3c
--- /dev/null
+++ b/gcc/testsuite/c-c++-common/asan/red-align-2.c
@@ -0,0 +1,20 @@
+/* This tests aligment propagation to structure elem and
+ abcense of redudant & 7. */
+
+/* { dg-options "-fdump-tree-sanopt" } */
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-flto" } { "" } } */
+
+struct st {
+ int a;
+ int b;
+ int c;
+} __attribute__((aligned(16)));
+
+int foo (struct st * s_p)
+{
+ return s_p->b;
+}
+
+/* { dg-final { scan-tree-dump-times "& 7" 1 "sanopt" } } */
+/* { dg-final { cleanup-tree-dump "sanopt" } } */
[PATCH] Support for BIT_FIELD_REF in asan.c
Hi all!
Here's a patch which instruments byte-aligned BIT_FIELD_REFs. During GCC
asan-bootstrap and Linux kernel build I didn't find any cases where
BIT_FIELD_REF is not 8 bits aligned. But I do not have sufficient
confidence to replace current return if BIT_FIELD_REF is misaligned to
assert.
Ok to commit?
--Marat
gcc/ChangeLog:
2014-09-19 Marat Zakirov
* asan.c (instrument_derefs): BIT_FIELD_REF added.
gcc/testsuite/ChangeLog:
2014-09-19 Marat Zakirov
* c-c++-common/asan/bitfield-5.c: New test.
diff --git a/gcc/asan.c b/gcc/asan.c
index cf5de27..451af33 100644
--- a/gcc/asan.c
+++ b/gcc/asan.c
@@ -1705,6 +1705,7 @@ instrument_derefs (gimple_stmt_iterator *iter, tree t,
case INDIRECT_REF:
case MEM_REF:
case VAR_DECL:
+case BIT_FIELD_REF:
break;
/* FALLTHRU */
default:
diff --git a/gcc/testsuite/c-c++-common/asan/bitfield-5.c b/gcc/testsuite/c-c++-common/asan/bitfield-5.c
new file mode 100644
index 000..eb5e9e9
--- /dev/null
+++ b/gcc/testsuite/c-c++-common/asan/bitfield-5.c
@@ -0,0 +1,24 @@
+/* Check BIT_FIELD_REF. */
+
+/* { dg-do run } */
+/* { dg-shouldfail "asan" } */
+
+struct A
+{
+ int y : 20;
+ int x : 13;
+};
+
+int __attribute__ ((noinline, noclone))
+f (void *p) {
+ return ((struct A *)p)->x != 0;
+}
+
+int
+main ()
+{
+ int a = 0;
+ return f (&a);
+}
+
+/* { dg-output "ERROR: AddressSanitizer: stack-buffer-overflow" } */
[PING][PATCH] Support for BIT_FIELD_REF in asan.c
On 09/26/2014 12:55 PM, Marat Zakirov wrote:
Hi all!
Here's a patch which instruments byte-aligned BIT_FIELD_REFs. During
GCC asan-bootstrap and Linux kernel build I didn't find any cases
where BIT_FIELD_REF is not 8 bits aligned. But I do not have
sufficient confidence to replace current return if BIT_FIELD_REF is
misaligned to assert.
Ok to commit?
--Marat
gcc/ChangeLog:
2014-09-19 Marat Zakirov
* asan.c (instrument_derefs): BIT_FIELD_REF added.
gcc/testsuite/ChangeLog:
2014-09-19 Marat Zakirov
* c-c++-common/asan/bitfield-5.c: New test.
diff --git a/gcc/asan.c b/gcc/asan.c
index cf5de27..451af33 100644
--- a/gcc/asan.c
+++ b/gcc/asan.c
@@ -1705,6 +1705,7 @@ instrument_derefs (gimple_stmt_iterator *iter, tree t,
case INDIRECT_REF:
case MEM_REF:
case VAR_DECL:
+case BIT_FIELD_REF:
break;
/* FALLTHRU */
default:
diff --git a/gcc/testsuite/c-c++-common/asan/bitfield-5.c b/gcc/testsuite/c-c++-common/asan/bitfield-5.c
new file mode 100644
index 000..eb5e9e9
--- /dev/null
+++ b/gcc/testsuite/c-c++-common/asan/bitfield-5.c
@@ -0,0 +1,24 @@
+/* Check BIT_FIELD_REF. */
+
+/* { dg-do run } */
+/* { dg-shouldfail "asan" } */
+
+struct A
+{
+ int y : 20;
+ int x : 13;
+};
+
+int __attribute__ ((noinline, noclone))
+f (void *p) {
+ return ((struct A *)p)->x != 0;
+}
+
+int
+main ()
+{
+ int a = 0;
+ return f (&a);
+}
+
+/* { dg-output "ERROR: AddressSanitizer: stack-buffer-overflow" } */
[PATCH] Inline asm asan instrumentation
Hi all,
Here's a patch for optional Asan instrumentation of inline assembly.
This version scans gimple for GIMPLE_ASMs and performs usual instrumentation
of arguments with memory constraints ("m", "o", etc.) with fixed size.
Instrumentation is turned off by default.
This was successfully bootstrapped and regtested on x64. I have also
instrumented and ran ffmpeg regression testsuite (it seems to have quite
some inline asm).
--Marat
InAsmAsan.diff
Description: Binary data
RE: [PATCH] Inline asm asan instrumentation
>> asm-struct-1.c test looks like a false positive though - the code does not
>> access any invalid memory, it only does a harmless pointer cast.
It is not. Because st1 have smaller size than st2:
struct st1 {
int a[110];
}
struct st2 {
int a[111];
};
And asm constrain was declared as:
: "=m" (*((struct st2 *)&s1)));
Test violate memory access constrain by cast (struct st2 *)&s1.
We check only constraints and by such a cast as we think user declare that he
want to access full st2 structure which have bigger size than st1.
-Original Message-
From: Evgeniy Stepanov [mailto:eugeni.stepa...@gmail.com]
Sent: Thursday, May 29, 2014 1:58 PM
To: Konstantin Serebryany
Cc: Marat Zakirov; GCC Patches; Konstantin Serebryany; Jakub Jelinek;
Viacheslav Garbuzov; Yuri Gribov; Marat Zakirov
Subject: Re: [PATCH] Inline asm asan instrumentation
Cool, we don't have this in LLVM-ASan, but we have plans to instrument inline
asm soon (not just constraints).
asm-struct-1.c test looks like a false positive though - the code does not
access any invalid memory, it only does a harmless pointer cast.
On Wed, May 28, 2014 at 10:36 PM, Konstantin Serebryany
wrote:
> On Wed, May 28, 2014 at 5:33 PM, Marat Zakirov wrote:
>> Hi all,
>>
>> Here's a patch for optional Asan instrumentation of inline assembly.
>>
>> This version scans gimple for GIMPLE_ASMs and performs usual
>> instrumentation of arguments with memory constraints ("m", "o", etc.) with
>> fixed size.
>>
>> Instrumentation is turned off by default.
>>
>> This was successfully bootstrapped and regtested on x64. I have also
>> instrumented and ran ffmpeg regression testsuite (it seems to have
>> quite some inline asm).
>>
>> --Marat
RE: [PATCH] Inline asm asan instrumentation
Actually I do not think that this is good idea to use constraints in a such
arbitrary way. By setting constraints user takes responsibility on himself.
So even if full inline asm support will be done one day, I do think that
checking memory constraints will be still exist.
It is the same situation as with compiler warnings - sometimes they are
bothering but if you think you do not need them - just do not use them.
-Original Message-
From: Jakub Jelinek [mailto:ja...@redhat.com]
Sent: Thursday, May 29, 2014 2:09 PM
To: Marat Zakirov
Cc: gcc-patches@gcc.gnu.org; 'Konstantin Serebryany'; 'Viacheslav Garbuzov';
'Yuri Gribov'; 'Marat Zakirov'
Subject: Re: [PATCH] Inline asm asan instrumentation
On Wed, May 28, 2014 at 05:33:44PM +0400, Marat Zakirov wrote:
> Here's a patch for optional Asan instrumentation of inline assembly.
>
> This version scans gimple for GIMPLE_ASMs and performs usual
> instrumentation of arguments with memory constraints ("m", "o", etc.) with
fixed size.
That doesn't look right to me. The fact that some region appears in "m"
doesn't mean the inline asm actually accesses it, it could not touch it at
all, or only some part of it.
If you look e.g. at Linux kernel headers, you'll see lots of struct
__large_struct { unsigned long buf[100]; }; #define __m(x) (*(struct
__large_struct __user *)(x)) ...
"m" (__m(addr))
and similar cases, if Asan wants to check that the whole 100*sizeof(long)
region is accessible, it could often just have false positives, because the
inline asm really accesses just some small part of it.
Jakub
[PING v2][PATCH] Fix for PR 61561
Original Message
Subject:[PING][PATCH] Fix for PR 61561
Date: Mon, 30 Jun 2014 19:21:49 +0400
From: Marat Zakirov
To: gcc-patches@gcc.gnu.org
CC: Ramana Radhakrishnan , Richard
Earnshaw , Kyrill Tkachov
, Slava Garbuzov , Yuri
Gribov , mara...@gmail.com
This is a reminder message on fix for PR 61561 which is ICE while
compiling something which is valid* 'C' code.
(https://gcc.gnu.org/bugzilla/show_bug.cgi?id=61561).
Ramana, Richard, I am very appreciated for your attention and error
indication, your work made my patch simple and tiny. And I hope that
this patch will save somebody's time.
Additional info about the issue:
By adding constrain 'k' we want to make gcc work properly with stack
register in HI and QI mode. This is need because CSE an RTL phase in
some cases propagates sp register directly to HI/QI memory set. Next
reload an RTL phase trying to build HI/QI move sp into some general
purpose register which is fail due to pattern absence. You may ask who
needs part of sp register? Nevertheless it is legitimate operation and
there is simple example of practical usage. Imagine you put some local
variable 'a' into hash table which has < 256 bunches. In this case
'operator []' of some hash class may take QI from sp register which is
directly pointing on 'a'.
Patch was reg. tested on --build=x86_64-pc-linux-gnu
--host=x86_64-pc-linux-gnu --target=arm-v7a15v5r2-linux-gnueabi for
c,c++,fortran languages w/o bootstrap.
* According to 'C' Standard [ISO/IEC 9899:2011] 6.3.2.3
"Any pointer type may be converted to an integer type. Except as
previously specified, the result is implementation-defined". As we know
'char' and 'short' (also called 'short int') are both integers.
Thank for your attention.
Marat.
gcc/ChangeLog:
2014-06-30 Marat Zakirov
PR target/61561
* config/arm/arm.md (*movhi_insn_arch4): Handle stack pointer.
(*movhi_bytes): Likewise.
(*arm_movqi_insn): Likewise.
gcc/testsuite/ChangeLog:
2014-06-30 Marat Zakirov
PR target/61561
* gcc.dg/pr61561.c: New test.
diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index 42c12c8..99290dc 100644
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -6291,7 +6291,7 @@
;; Pattern to recognize insn generated default case above
(define_insn "*movhi_insn_arch4"
[(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r")
- (match_operand:HI 1 "general_operand" "rI,K,r,mi"))]
+ (match_operand:HI 1 "general_operand" "rIk,K,r,mi"))]
"TARGET_ARM
&& arm_arch4
&& (register_operand (operands[0], HImode)
@@ -6315,7 +6315,7 @@
(define_insn "*movhi_bytes"
[(set (match_operand:HI 0 "s_register_operand" "=r,r,r")
- (match_operand:HI 1 "arm_rhs_operand" "I,r,K"))]
+ (match_operand:HI 1 "arm_rhs_operand" "I,rk,K"))]
"TARGET_ARM"
"@
mov%?\\t%0, %1\\t%@ movhi
@@ -6430,7 +6430,7 @@
(define_insn "*arm_movqi_insn"
[(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,r,l,r,l,Uu,r,m")
- (match_operand:QI 1 "general_operand" "r,r,I,Py,K,Uu,l,m,r"))]
+ (match_operand:QI 1 "general_operand" "rk,rk,I,Py,K,Uu,l,m,r"))]
"TARGET_32BIT
&& ( register_operand (operands[0], QImode)
|| register_operand (operands[1], QImode))"
diff --git a/gcc/testsuite/gcc.dg/pr61561.c b/gcc/testsuite/gcc.dg/pr61561.c
new file mode 100644
index 000..0f4b716
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/pr61561.c
@@ -0,0 +1,15 @@
+/* PR c/61561. */
+/* { dg-do assemble } */
+/* { dg-options " -w -O2" } */
+
+int dummy (int a);
+
+char a;
+short b;
+
+void mmm (void)
+{
+ char dyn[dummy (3)];
+ a = (char)&dyn[0];
+ b = (short)&dyn[0];
+}
Fwd: Re: [PING][PATCH] Fix for PR 61561
Thank to you all. Committed revision 212450. --Marat Original Message Subject:Re: [PING][PATCH] Fix for PR 61561 Date: Thu, 10 Jul 2014 14:01:24 +0100 From: Ramana Radhakrishnan To: Marat Zakirov , "gcc-patches@gcc.gnu.org" CC: Richard Earnshaw , Kyrylo Tkachov , Slava Garbuzov , Yuri Gribov , "mara...@gmail.com" On 30/06/14 16:21, Marat Zakirov wrote: Thank for your attention. This is OK for trunk - Sorry about the delayed response. Ramana Marat.
Re: [PING][PATCH] Fix for PR 61561
Unfortunately, I didn't reproduce the issue... Could you please provide full info? Including gcc trunk version, configure line, failed test command line. Thank you. --Marat On 07/11/2014 11:19 PM, Christophe Lyon wrote: The new testcase causes an ICE when the compile is configured --with-thumb or when forcing -mthumb. Christophe. On 11 July 2014 11:08, Marat Zakirov wrote: Thank to you all. Committed revision 212450. --Marat Original Message Subject:Re: [PING][PATCH] Fix for PR 61561 Date: Thu, 10 Jul 2014 14:01:24 +0100 From: Ramana Radhakrishnan To: Marat Zakirov , "gcc-patches@gcc.gnu.org" CC: Richard Earnshaw , Kyrylo Tkachov , Slava Garbuzov , Yuri Gribov , "mara...@gmail.com" On 30/06/14 16:21, Marat Zakirov wrote: Thank for your attention. This is OK for trunk - Sorry about the delayed response. Ramana Marat.
Re: [PING][PATCH] Fix for PR 61561
Christophe, Please look at a new patch. Draft tests are OK. I'll ask your commit approval when full regression (ARM/thumb1/thumb2) tests are done. Thank for your attention. --Marat On 07/11/2014 11:19 PM, Christophe Lyon wrote: The new testcase causes an ICE when the compile is configured --with-thumb or when forcing -mthumb. Christophe. On 11 July 2014 11:08, Marat Zakirov wrote: Thank to you all. Committed revision 212450. --Marat Original Message Subject:Re: [PING][PATCH] Fix for PR 61561 Date: Thu, 10 Jul 2014 14:01:24 +0100 From: Ramana Radhakrishnan To: Marat Zakirov , "gcc-patches@gcc.gnu.org" CC: Richard Earnshaw , Kyrylo Tkachov , Slava Garbuzov , Yuri Gribov , "mara...@gmail.com" On 30/06/14 16:21, Marat Zakirov wrote: Thank for your attention. This is OK for trunk - Sorry about the delayed response. Ramana Marat. gcc/ChangeLog: 2014-07-16 Marat Zakirov * config/arm/thumb1.md: Handle stack pointer. * config/arm/thumb2.md: Ditto. diff --git a/gcc/config/arm/thumb1.md b/gcc/config/arm/thumb1.md index c044fd5..47b5cbd 100644 --- a/gcc/config/arm/thumb1.md +++ b/gcc/config/arm/thumb1.md @@ -708,7 +708,7 @@ (define_insn "*thumb1_movhi_insn" [(set (match_operand:HI 0 "nonimmediate_operand" "=l,l,m,*r,*h,l") - (match_operand:HI 1 "general_operand" "l,m,l,*h,*r,I"))] + (match_operand:HI 1 "general_operand" "lk,m,l,*h,*r,I"))] "TARGET_THUMB1 && ( register_operand (operands[0], HImode) || register_operand (operands[1], HImode))" @@ -762,7 +762,7 @@ (define_insn "*thumb1_movqi_insn" [(set (match_operand:QI 0 "nonimmediate_operand" "=l,l,m,*r,*h,l") - (match_operand:QI 1 "general_operand" "l, m,l,*h,*r,I"))] + (match_operand:QI 1 "general_operand" "lk, m,l,*h,*r,I"))] "TARGET_THUMB1 && ( register_operand (operands[0], QImode) || register_operand (operands[1], QImode))" diff --git a/gcc/config/arm/thumb2.md b/gcc/config/arm/thumb2.md index 6ea0810..7228069 100644 --- a/gcc/config/arm/thumb2.md +++ b/gcc/config/arm/thumb2.md @@ -318,7 +318,7 @@ ;; of the messiness associated with the ARM patterns. (define_insn "*thumb2_movhi_insn" [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,l,r,m,r") - (match_operand:HI 1 "general_operand" "r,I,Py,n,r,m"))] + (match_operand:HI 1 "general_operand" "rk,I,Py,n,r,m"))] "TARGET_THUMB2 && (register_operand (operands[0], HImode) || register_operand (operands[1], HImode))"
Re: [PING][PATCH] Fix for PR 61561
On 07/16/2014 01:32 PM, Kyrill Tkachov wrote: On 16/07/14 10:22, Marat Zakirov wrote: Christophe, Please look at a new patch. Draft tests are OK. I'll ask your commit approval when full regression (ARM/thumb1/thumb2) tests are done. Hi Marat, I was about to propose the thumb2.md hunk myself, but I'll defer to the arm maintainers to comment on the other parts. Also, in the ChangeLog it is helpful to specify which patterns are being affected, so in your case it would be something like: * config/arm/thumb1.md (*thumb1_movhi_insn): Handle stack pointer. (*thumb1_movqi_insn): Likewise. * config/arm/thumb2.md (*thumb2_movhi_insn): Ditto. Kyrill Christophe, Kirill, finally I've finished regression testing. Please check if my patch is OK for trunk. The following configures were used: configure --build=x86_64-pc-linux-gnu --host=x86_64-pc-linux-gnu --target=arm-linux-gnueabi --with-interwork --enable-long-long --enable-languages=c,c++,fortran --enable-shared --with-gnu-as --with-gnu-ld --with-arch=$ARCH --with-mode=$MODE Thumb-1 $ARCH=armv4t $MODE=thumb Thumb-2 $ARCH=armv7 $MODE=thumb ARM $ARCH=armv7-a $MODE=arm No regressions detected, test pr61561.c passed in all cases. Thank you all. --Marat gcc/ChangeLog: 2014-07-16 Marat Zakirov * config/arm/thumb1.md (*thumb1_movhi_insn): Handle stack pointer. (*thumb1_movqi_insn): Likewise. * config/arm/thumb2.md (*thumb2_movhi_insn): Likewise. diff --git a/gcc/config/arm/thumb1.md b/gcc/config/arm/thumb1.md index c044fd5..47b5cbd 100644 --- a/gcc/config/arm/thumb1.md +++ b/gcc/config/arm/thumb1.md @@ -708,7 +708,7 @@ (define_insn "*thumb1_movhi_insn" [(set (match_operand:HI 0 "nonimmediate_operand" "=l,l,m,*r,*h,l") - (match_operand:HI 1 "general_operand" "l,m,l,*h,*r,I"))] + (match_operand:HI 1 "general_operand" "lk,m,l,*h,*r,I"))] "TARGET_THUMB1 && ( register_operand (operands[0], HImode) || register_operand (operands[1], HImode))" @@ -762,7 +762,7 @@ (define_insn "*thumb1_movqi_insn" [(set (match_operand:QI 0 "nonimmediate_operand" "=l,l,m,*r,*h,l") - (match_operand:QI 1 "general_operand" "l, m,l,*h,*r,I"))] + (match_operand:QI 1 "general_operand" "lk, m,l,*h,*r,I"))] "TARGET_THUMB1 && ( register_operand (operands[0], QImode) || register_operand (operands[1], QImode))" diff --git a/gcc/config/arm/thumb2.md b/gcc/config/arm/thumb2.md index 6ea0810..7228069 100644 --- a/gcc/config/arm/thumb2.md +++ b/gcc/config/arm/thumb2.md @@ -318,7 +318,7 @@ ;; of the messiness associated with the ARM patterns. (define_insn "*thumb2_movhi_insn" [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,l,r,m,r") - (match_operand:HI 1 "general_operand" "r,I,Py,n,r,m"))] + (match_operand:HI 1 "general_operand" "rk,I,Py,n,r,m"))] "TARGET_THUMB2 && (register_operand (operands[0], HImode) || register_operand (operands[1], HImode))"
[PING][PATCH] Fix for PR 61561
Hi all! This is a friendly reminder message. On 07/17/2014 03:22 PM, Marat Zakirov wrote: On 07/16/2014 01:32 PM, Kyrill Tkachov wrote: On 16/07/14 10:22, Marat Zakirov wrote: Christophe, Please look at a new patch. Draft tests are OK. I'll ask your commit approval when full regression (ARM/thumb1/thumb2) tests are done. Hi Marat, I was about to propose the thumb2.md hunk myself, but I'll defer to the arm maintainers to comment on the other parts. Also, in the ChangeLog it is helpful to specify which patterns are being affected, so in your case it would be something like: * config/arm/thumb1.md (*thumb1_movhi_insn): Handle stack pointer. (*thumb1_movqi_insn): Likewise. * config/arm/thumb2.md (*thumb2_movhi_insn): Ditto. Kyrill Christophe, Kirill, finally I've finished regression testing. Please check if my patch is OK for trunk. The following configures were used: configure --build=x86_64-pc-linux-gnu --host=x86_64-pc-linux-gnu --target=arm-linux-gnueabi --with-interwork --enable-long-long --enable-languages=c,c++,fortran --enable-shared --with-gnu-as --with-gnu-ld --with-arch=$ARCH --with-mode=$MODE Thumb-1 $ARCH=armv4t $MODE=thumb Thumb-2 $ARCH=armv7 $MODE=thumb ARM $ARCH=armv7-a $MODE=arm No regressions detected, test pr61561.c passed in all cases. Thank you all. --Marat gcc/ChangeLog: 2014-07-16 Marat Zakirov * config/arm/thumb1.md (*thumb1_movhi_insn): Handle stack pointer. (*thumb1_movqi_insn): Likewise. * config/arm/thumb2.md (*thumb2_movhi_insn): Likewise. diff --git a/gcc/config/arm/thumb1.md b/gcc/config/arm/thumb1.md index c044fd5..47b5cbd 100644 --- a/gcc/config/arm/thumb1.md +++ b/gcc/config/arm/thumb1.md @@ -708,7 +708,7 @@ (define_insn "*thumb1_movhi_insn" [(set (match_operand:HI 0 "nonimmediate_operand" "=l,l,m,*r,*h,l") - (match_operand:HI 1 "general_operand" "l,m,l,*h,*r,I"))] + (match_operand:HI 1 "general_operand" "lk,m,l,*h,*r,I"))] "TARGET_THUMB1 && ( register_operand (operands[0], HImode) || register_operand (operands[1], HImode))" @@ -762,7 +762,7 @@ (define_insn "*thumb1_movqi_insn" [(set (match_operand:QI 0 "nonimmediate_operand" "=l,l,m,*r,*h,l") - (match_operand:QI 1 "general_operand" "l, m,l,*h,*r,I"))] + (match_operand:QI 1 "general_operand" "lk, m,l,*h,*r,I"))] "TARGET_THUMB1 && ( register_operand (operands[0], QImode) || register_operand (operands[1], QImode))" diff --git a/gcc/config/arm/thumb2.md b/gcc/config/arm/thumb2.md index 6ea0810..7228069 100644 --- a/gcc/config/arm/thumb2.md +++ b/gcc/config/arm/thumb2.md @@ -318,7 +318,7 @@ ;; of the messiness associated with the ARM patterns. (define_insn "*thumb2_movhi_insn" [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,l,r,m,r") - (match_operand:HI 1 "general_operand" "r,I,Py,n,r,m"))] + (match_operand:HI 1 "general_operand" "rk,I,Py,n,r,m"))] "TARGET_THUMB2 && (register_operand (operands[0], HImode) || register_operand (operands[1], HImode))"
[PATCH] Fix vector tests on ARM platforms with disabled unaligned accesses
Hi there!
I made a patch which fixes regressions on ARM platforms with disabled
unaligned accesses. The problem is that 'arm_vect_no_misalign' predicate
do not check 'unaligned_access' global variable to determine whether
unaligned access to vector are allowed. This leads to spurious vect.exp
test fails when GCC is configured
--with-specs=%{!munaligned-access:-mno-unaligned-access}.
Attached patch fixes ARM predicate and several tests to correctly handle
the issue.
The following targets were reg. tested for multiple targets (ARM,
Thumb-1, Thumb-2, x86, x86_64) with and without -mno-unaligned-access.
Analysis showed patch affects only vect.exp tests so only vect.exp was
tested.
For x86, x86_64, ARM without -mno-unaligned-access, Thumb-2 without
-mno-unaligned-access and Thumb-1 no regressions occured. For
ARM/Thumb2 with -mno-unaligned-access patch fixed most of failures but
triggered some problems (see attached log) for current vect.exp tests:
1) https://gcc.gnu.org/bugzilla/show_bug.cgi?id=61887
2) Some XPASS'es due to unexpected loop versioning (e.g.
gcc.dg/vect/pr33804.c).
3) After predicate fix some passing tests which require unaligned vector
support become NA (this was expected).
P.S.
Here used configurations:
ARM_BASE = configure --build=x86_64-pc-linux-gnu
--host=x86_64-pc-linux-gnu --target=arm-linux-gnueabi --with-interwork
--enable-long-long --enable-languages=c,c++,fortran --enable-shared
--with-gnu-as --with-gnu-ld
ARM
$ARM_BASE --with-mode=arm --with-arch=armv7-a
ARM with -mno-unaligned-access option
$ARM_BASE --with-mode=arm --with-arch=armv7-a
--with-specs=%{!munaligned-access:-mno-unaligned-access}
Thumb-2
$ARM_BASE --with-mode=thumb --with-arch=armv7-a
Thumb-2 with -mno-unaligned-access
$ARM_BASE --with-mode=thumb --with-arch=armv7-a
--with-specs=%{!munaligned-access:-mno-unaligned-access}
Thumb-1
$ARM_BASE --with-mode=thumb --with-arch=armv4t
Thumb-1 with -mno-unaligned-access
$ARM_BASE --with-mode=thumb --with-arch=armv4t
--with-specs=%{!munaligned-access:-mno-unaligned-access}
x86
configure --enable-languages=c,c++,fortran
--Marat
gcc/testsuite/ChangeLog:
2014-07-23 Marat Zakirov
* gcc.dg/vect/vect-109.c: Predicate added.
* gcc.dg/vect/vect-93.c: Test check fixed.
* lib/target-supports.exp (check_effective_target_arm_vect_no_misalign):
Check unaligned feature.
diff --git a/gcc/testsuite/gcc.dg/vect/vect-109.c b/gcc/testsuite/gcc.dg/vect/vect-109.c
index 854c970..fb87e2c 100644
--- a/gcc/testsuite/gcc.dg/vect/vect-109.c
+++ b/gcc/testsuite/gcc.dg/vect/vect-109.c
@@ -1,4 +1,4 @@
-/* { dg-require-effective-target vect_int } */
+/* { dg-require-effective-target { vect_int && {! vect_no_align } } } */
#include
#include "tree-vect.h"
diff --git a/gcc/testsuite/gcc.dg/vect/vect-93.c b/gcc/testsuite/gcc.dg/vect/vect-93.c
index 65403eb..1065a6e 100644
--- a/gcc/testsuite/gcc.dg/vect/vect-93.c
+++ b/gcc/testsuite/gcc.dg/vect/vect-93.c
@@ -79,7 +79,7 @@ int main (void)
/* { dg-final { scan-tree-dump-times "vectorized 2 loops" 1 "vect" { target vect_no_align } } } */
/* in main: */
-/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" { target vect_no_align } } } */
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_no_align } } } */
/* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 1 "vect" { xfail { vect_no_align } } } } */
/* { dg-final { cleanup-tree-dump "vect" } } */
diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
index 5290a55..190483c 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -2293,7 +2293,8 @@ proc check_effective_target_arm_little_endian { } {
proc check_effective_target_arm_vect_no_misalign { } {
return [check_no_compiler_messages arm_vect_no_misalign assembly {
#if !defined(__arm__) \
- || (defined(__ARMEL__) \
+ || (defined(__ARM_FEATURE_UNALIGNED) \
+ && defined(__ARMEL__) \
&& (!defined(__thumb__) || defined(__thumb2__)))
#error FOO
#endif
dg-cmp-results.sh: Verbosity is 2, Variant is ""
Older log file: ./gcc/testsuite/gcc/gcc.sum
Test Run By mzakirov on Tue Jul 22 12:12:27 2014
Target is arm-v7a15v5r2-linux-gnueabi
Host is x86_64-pc-linux-gnu
Newer log file: /home/mzakirov/proj/gcc_unalign//build.arm.cortex-a15/obj/gcc_final/./gcc/testsuite/gcc/gcc.sum
Test Run By mzakirov on Tue Jul 22 12:22:35 2014
Target is arm-v7a15v5r2-linux-gnueabi
Host is x86_64-pc-linux-gnu
UNRESOLVED->NA: gcc.dg/vect/bb-slp-10.c -flto scan-tree-dump-times slp "basic block vectorized using SLP" 1
UNRESOLVED->NA: gcc.dg/vect/bb-slp-10.c scan-tree-dump-times slp "basic block vectorized using SLP" 1
UNRESOLVED->NA: gcc.dg/vect/bb-slp-24.c -flto
[PATCHv2] Fix vector tests on ARM platforms with disabled unaligned accesses
On 07/23/2014 06:23 PM, Marat Zakirov wrote:
Hi there!
I made a patch which fixes regressions on ARM platforms with disabled
unaligned accesses. The problem is that 'arm_vect_no_misalign'
predicate do not check 'unaligned_access' global variable to determine
whether unaligned access to vector are allowed. This leads to spurious
vect.exp test fails when GCC is configured
--with-specs=%{!munaligned-access:-mno-unaligned-access}.
Attached patch fixes ARM predicate and several tests to correctly
handle the issue.
The following targets were reg. tested for multiple targets (ARM,
Thumb-1, Thumb-2, x86, x86_64) with and without
-mno-unaligned-access. Analysis showed patch affects only vect.exp
tests so only vect.exp was tested.
For x86, x86_64, ARM without -mno-unaligned-access, Thumb-2 without
-mno-unaligned-access and Thumb-1 no regressions occured. For
ARM/Thumb2 with -mno-unaligned-access patch fixed most of failures but
triggered some problems (see attached log) for current vect.exp tests:
1) https://gcc.gnu.org/bugzilla/show_bug.cgi?id=61887
2) Some XPASS'es due to unexpected loop versioning (e.g.
gcc.dg/vect/pr33804.c).
3) After predicate fix some passing tests which require unaligned
vector support become NA (this was expected).
Here is new version of patch and regression log. On the current trunk
results are slightly different due to patches for Richard Biener (no
UNRESOLVED fails) but some PASS->XPASS regressions still remain (see
attachment):
PASS->XPASS: gcc.dg/vect/if-cvt-stores-vect-ifcvt-18.c
scan-tree-dump-times vect "vectorized 1 loops" 1
PASS->XPASS: gcc.dg/vect/pr33804.c -flto -ffat-lto-objects
scan-tree-dump-times vect "vectorized 1 loops" 1
etc.
These XPASS'es are due to code versioning: current GCC creates 2
versions of loop: aligned and misaligned. It's look like they are
slightly out of date at lest for ARM.
gcc/testsuite/ChangeLog:
2014-07-23 Marat Zakirov
* gcc.dg/vect/vect-109.c: Skip predicate added.
* gcc.dg/vect/vect-93.c: Test check fixed.
* gcc.dg/vect/bb-slp-10.c: Likewise.
* lib/target-supports.exp (check_effective_target_arm_vect_no_misalign):
Check unaligned feature.
diff --git a/gcc/testsuite/gcc.dg/vect/bb-slp-10.c b/gcc/testsuite/gcc.dg/vect/bb-slp-10.c
index a1850ed..0090a4b 100644
--- a/gcc/testsuite/gcc.dg/vect/bb-slp-10.c
+++ b/gcc/testsuite/gcc.dg/vect/bb-slp-10.c
@@ -49,7 +49,7 @@ int main (void)
return 0;
}
-/* { dg-final { scan-tree-dump-times "unsupported alignment in basic block." 1 "slp2" { xfail vect_element_align } } } */
+/* { dg-final { scan-tree-dump "unsupported alignment in basic block." 1 "slp2" { xfail vect_element_align } } } */
/* { dg-final { scan-tree-dump-times "basic block vectorized" 1 "slp2" { target vect_element_align } } } */
/* { dg-final { cleanup-tree-dump "slp2" } } */
diff --git a/gcc/testsuite/gcc.dg/vect/vect-109.c b/gcc/testsuite/gcc.dg/vect/vect-109.c
index 854c970..c671175 100644
--- a/gcc/testsuite/gcc.dg/vect/vect-109.c
+++ b/gcc/testsuite/gcc.dg/vect/vect-109.c
@@ -1,3 +1,4 @@
+/* { dg-skip-if "" { vect_no_align } } */
/* { dg-require-effective-target vect_int } */
#include
diff --git a/gcc/testsuite/gcc.dg/vect/vect-93.c b/gcc/testsuite/gcc.dg/vect/vect-93.c
index 65403eb..1065a6e 100644
--- a/gcc/testsuite/gcc.dg/vect/vect-93.c
+++ b/gcc/testsuite/gcc.dg/vect/vect-93.c
@@ -79,7 +79,7 @@ int main (void)
/* { dg-final { scan-tree-dump-times "vectorized 2 loops" 1 "vect" { target vect_no_align } } } */
/* in main: */
-/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" { target vect_no_align } } } */
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_no_align } } } */
/* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 1 "vect" { xfail { vect_no_align } } } } */
/* { dg-final { cleanup-tree-dump "vect" } } */
diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
index db65ebe..42251e8 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -2293,7 +2293,8 @@ proc check_effective_target_arm_little_endian { } {
proc check_effective_target_arm_vect_no_misalign { } {
return [check_no_compiler_messages arm_vect_no_misalign assembly {
#if !defined(__arm__) \
- || (defined(__ARMEL__) \
+ || (defined(__ARM_FEATURE_UNALIGNED) \
+ && defined(__ARMEL__) \
&& (!defined(__thumb__) || defined(__thumb2__)))
#error FOO
#endif
dg-cmp-results.sh: Verbosity is 2, Variant is "target-sim"
Older log file: ./gcc/testsuite/gcc/gcc.sum
Test Run By mzakirov on Thu Jul 24 11:47:42 2014
Target is arm-v7a15v5r2-linux-gnueabi
Host is x86_64-pc-l
[PATCHv3] Fix vector tests on ARM platforms with disabled unaligned accesses
On 07/24/2014 04:27 PM, Marat Zakirov wrote:
On 07/23/2014 06:23 PM, Marat Zakirov wrote:
Hi there!
I made a patch which fixes regressions on ARM platforms with disabled
unaligned accesses. The problem is that 'arm_vect_no_misalign'
predicate do not check 'unaligned_access' global variable to
determine whether unaligned access to vector are allowed. This leads
to spurious vect.exp test fails when GCC is configured
--with-specs=%{!munaligned-access:-mno-unaligned-access}.
Attached patch fixes ARM predicate and several tests to correctly
handle the issue.
The following targets were reg. tested for multiple targets (ARM,
Thumb-1, Thumb-2, x86, x86_64) with and without
-mno-unaligned-access. Analysis showed patch affects only vect.exp
tests so only vect.exp was tested.
For x86, x86_64, ARM without -mno-unaligned-access, Thumb-2 without
-mno-unaligned-access and Thumb-1 no regressions occured. For
ARM/Thumb2 with -mno-unaligned-access patch fixed most of failures
but triggered some problems (see attached log) for current vect.exp
tests:
1) https://gcc.gnu.org/bugzilla/show_bug.cgi?id=61887
2) Some XPASS'es due to unexpected loop versioning (e.g.
gcc.dg/vect/pr33804.c).
3) After predicate fix some passing tests which require unaligned
vector support become NA (this was expected).
Here is new version of patch and regression log. On the current trunk
results are slightly different due to patches for Richard Biener (no
UNRESOLVED fails) but some PASS->XPASS regressions still remain (see
attachment):
PASS->XPASS: gcc.dg/vect/if-cvt-stores-vect-ifcvt-18.c
scan-tree-dump-times vect "vectorized 1 loops" 1
PASS->XPASS: gcc.dg/vect/pr33804.c -flto -ffat-lto-objects
scan-tree-dump-times vect "vectorized 1 loops" 1
etc.
These XPASS'es are due to code versioning: current GCC creates 2
versions of loop: aligned and misaligned. It's look like they are
slightly out of date at lest for ARM.
On 07/24/2014 06:50 PM, Ramana Radhakrishnan wrote:
This is redundant.
- || (defined(__ARMEL__) \
+ || (defined(__ARM_FEATURE_UNALIGNED) \
+ && defined(__ARMEL__) \
&& (!defined(__thumb__) || defined(__thumb2__)))
As is this line.
I think you can restrict the check to defined(__ARM_FEATURE_UNALIGNED)
&& defined(__ARMEL__)
__ARM_FEATURE_UNALIGNED should tell you whether unaligned access is
allowed or not, therefore you should no longer require any specific
"architectural" checks.
#error FOO
#endif
I'm not sure about the original intent of the tests right now.
Ramana
Thank you Ramana!
--Marat
dg-cmp-results.sh: Verbosity is 2, Variant is "target-sim"
Older log file: ./gcc/testsuite/gcc/gcc.sum
Test Run By mzakirov on Thu Jul 24 11:47:42 2014
Target is arm-v7a15v5r2-linux-gnueabi
Host is x86_64-pc-linux-gnu
Newer log file: /home/mzakirov/proj/gcc_unalign/build.arm.cortex-a15/obj/gcc_final/./gcc/testsuite/gcc/gcc.sum
Test Run By mzakirov on Thu Jul 24 19:17:05 2014
Target is arm-v7a15v5r2-linux-gnueabi
Host is x86_64-pc-linux-gnu
NA->PASS: gcc.dg/vect/bb-slp-10.c -flto -ffat-lto-objects scan-tree-dump slp2 "unsupported alignment in basic block."
FAIL->NA: gcc.dg/vect/bb-slp-10.c -flto -ffat-lto-objects scan-tree-dump-times slp2 "basic block vectorized" 1
XFAIL->NA: gcc.dg/vect/bb-slp-10.c -flto -ffat-lto-objects scan-tree-dump-times slp2 "unsupported alignment in basic block." 1
NA->PASS: gcc.dg/vect/bb-slp-10.c scan-tree-dump slp2 "unsupported alignment in basic block."
FAIL->NA: gcc.dg/vect/bb-slp-10.c scan-tree-dump-times slp2 "basic block vectorized" 1
XFAIL->NA: gcc.dg/vect/bb-slp-10.c scan-tree-dump-times slp2 "unsupported alignment in basic block." 1
FAIL->NA: gcc.dg/vect/bb-slp-24.c -flto -ffat-lto-objects scan-tree-dump-times slp1 "basic block vectorized" 1
FAIL->NA: gcc.dg/vect/bb-slp-24.c scan-tree-dump-times slp1 "basic block vectorized" 1
FAIL->NA: gcc.dg/vect/bb-slp-25.c -flto -ffat-lto-objects scan-tree-dump-times slp1 "basic block vectorized" 1
FAIL->NA: gcc.dg/vect/bb-slp-25.c scan-tree-dump-times slp1 "basic block vectorized" 1
FAIL->NA: gcc.dg/vect/bb-slp-29.c -flto -ffat-lto-objects scan-tree-dump-times slp1 "basic block vectorized" 1
FAIL->NA: gcc.dg/vect/bb-slp-29.c scan-tree-dump-times slp1 "basic block vectorized" 1
FAIL->XFAIL: gcc.dg/vect/bb-slp-32.c -flto -ffat-lto-objects scan-tree-dump slp2 "vectorization is not profitable"
FAIL->XFAIL: gcc.dg/vect/bb-slp-32.c scan-tree-dump slp2 "vectorization is not profitable"
FAIL->XFAIL: gcc.dg/vect/bb-slp-9.c -flto -ffat-lto-objects scan-tree-dump-times slp2 "basic block vectorized" 1
FAIL->XFAIL: gcc.dg/vect/bb-slp-9.c s
[PINGv2][PATCH] Fix for PR 61561
On 07/23/2014 05:33 PM, Marat Zakirov wrote: Hi all! This is a friendly reminder message. On 07/17/2014 03:22 PM, Marat Zakirov wrote: On 07/16/2014 01:32 PM, Kyrill Tkachov wrote: On 16/07/14 10:22, Marat Zakirov wrote: Christophe, Please look at a new patch. Draft tests are OK. I'll ask your commit approval when full regression (ARM/thumb1/thumb2) tests are done. Hi Marat, I was about to propose the thumb2.md hunk myself, but I'll defer to the arm maintainers to comment on the other parts. Also, in the ChangeLog it is helpful to specify which patterns are being affected, so in your case it would be something like: * config/arm/thumb1.md (*thumb1_movhi_insn): Handle stack pointer. (*thumb1_movqi_insn): Likewise. * config/arm/thumb2.md (*thumb2_movhi_insn): Ditto. Kyrill Christophe, Kirill, finally I've finished regression testing. Please check if my patch is OK for trunk. The following configures were used: configure --build=x86_64-pc-linux-gnu --host=x86_64-pc-linux-gnu --target=arm-linux-gnueabi --with-interwork --enable-long-long --enable-languages=c,c++,fortran --enable-shared --with-gnu-as --with-gnu-ld --with-arch=$ARCH --with-mode=$MODE Thumb-1 $ARCH=armv4t $MODE=thumb Thumb-2 $ARCH=armv7 $MODE=thumb ARM $ARCH=armv7-a $MODE=arm No regressions detected, test pr61561.c passed in all cases. Thank you all. --Marat gcc/ChangeLog: 2014-07-16 Marat Zakirov * config/arm/thumb1.md (*thumb1_movhi_insn): Handle stack pointer. (*thumb1_movqi_insn): Likewise. * config/arm/thumb2.md (*thumb2_movhi_insn): Likewise. diff --git a/gcc/config/arm/thumb1.md b/gcc/config/arm/thumb1.md index c044fd5..47b5cbd 100644 --- a/gcc/config/arm/thumb1.md +++ b/gcc/config/arm/thumb1.md @@ -708,7 +708,7 @@ (define_insn "*thumb1_movhi_insn" [(set (match_operand:HI 0 "nonimmediate_operand" "=l,l,m,*r,*h,l") - (match_operand:HI 1 "general_operand" "l,m,l,*h,*r,I"))] + (match_operand:HI 1 "general_operand" "lk,m,l,*h,*r,I"))] "TARGET_THUMB1 && ( register_operand (operands[0], HImode) || register_operand (operands[1], HImode))" @@ -762,7 +762,7 @@ (define_insn "*thumb1_movqi_insn" [(set (match_operand:QI 0 "nonimmediate_operand" "=l,l,m,*r,*h,l") - (match_operand:QI 1 "general_operand" "l, m,l,*h,*r,I"))] + (match_operand:QI 1 "general_operand" "lk, m,l,*h,*r,I"))] "TARGET_THUMB1 && ( register_operand (operands[0], QImode) || register_operand (operands[1], QImode))" diff --git a/gcc/config/arm/thumb2.md b/gcc/config/arm/thumb2.md index 6ea0810..7228069 100644 --- a/gcc/config/arm/thumb2.md +++ b/gcc/config/arm/thumb2.md @@ -318,7 +318,7 @@ ;; of the messiness associated with the ARM patterns. (define_insn "*thumb2_movhi_insn" [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,l,r,m,r") - (match_operand:HI 1 "general_operand" "r,I,Py,n,r,m"))] + (match_operand:HI 1 "general_operand" "rk,I,Py,n,r,m"))] "TARGET_THUMB2 && (register_operand (operands[0], HImode) || register_operand (operands[1], HImode))"
[PING][PATCHv3] Fix vector tests on ARM platforms with disabled unaligned accesses
On 07/24/2014 07:40 PM, Marat Zakirov wrote:
On 07/24/2014 04:27 PM, Marat Zakirov wrote:
On 07/23/2014 06:23 PM, Marat Zakirov wrote:
Hi there!
I made a patch which fixes regressions on ARM platforms with
disabled unaligned accesses. The problem is that
'arm_vect_no_misalign' predicate do not check 'unaligned_access'
global variable to determine whether unaligned access to vector are
allowed. This leads to spurious vect.exp test fails when GCC is
configured --with-specs=%{!munaligned-access:-mno-unaligned-access}.
Attached patch fixes ARM predicate and several tests to correctly
handle the issue.
The following targets were reg. tested for multiple targets (ARM,
Thumb-1, Thumb-2, x86, x86_64) with and without
-mno-unaligned-access. Analysis showed patch affects only vect.exp
tests so only vect.exp was tested.
For x86, x86_64, ARM without -mno-unaligned-access, Thumb-2 without
-mno-unaligned-access and Thumb-1 no regressions occured. For
ARM/Thumb2 with -mno-unaligned-access patch fixed most of failures
but triggered some problems (see attached log) for current vect.exp
tests:
1) https://gcc.gnu.org/bugzilla/show_bug.cgi?id=61887
2) Some XPASS'es due to unexpected loop versioning (e.g.
gcc.dg/vect/pr33804.c).
3) After predicate fix some passing tests which require unaligned
vector support become NA (this was expected).
Here is new version of patch and regression log. On the current trunk
results are slightly different due to patches for Richard Biener (no
UNRESOLVED fails) but some PASS->XPASS regressions still remain (see
attachment):
PASS->XPASS: gcc.dg/vect/if-cvt-stores-vect-ifcvt-18.c
scan-tree-dump-times vect "vectorized 1 loops" 1
PASS->XPASS: gcc.dg/vect/pr33804.c -flto -ffat-lto-objects
scan-tree-dump-times vect "vectorized 1 loops" 1
etc.
These XPASS'es are due to code versioning: current GCC creates 2
versions of loop: aligned and misaligned. It's look like they are
slightly out of date at lest for ARM.
On 07/24/2014 06:50 PM, Ramana Radhakrishnan wrote:
This is redundant.
- || (defined(__ARMEL__) \
+ || (defined(__ARM_FEATURE_UNALIGNED) \
+ && defined(__ARMEL__) \
&& (!defined(__thumb__) || defined(__thumb2__)))
As is this line.
I think you can restrict the check to defined(__ARM_FEATURE_UNALIGNED)
&& defined(__ARMEL__)
__ARM_FEATURE_UNALIGNED should tell you whether unaligned access is
allowed or not, therefore you should no longer require any specific
"architectural" checks.
#error FOO
#endif
I'm not sure about the original intent of the tests right now.
Ramana
Thank you Ramana!
--Marat
gcc/testsuite/ChangeLog:
2014-07-23 Marat Zakirov
* gcc.dg/vect/vect-109.c: Skip predicate added.
* gcc.dg/vect/vect-93.c: Test check fixed.
* gcc.dg/vect/bb-slp-10.c: Likewise.
* lib/target-supports.exp (check_effective_target_arm_vect_no_misalign):
Check unaligned feature.
diff --git a/gcc/testsuite/gcc.dg/vect/bb-slp-10.c b/gcc/testsuite/gcc.dg/vect/bb-slp-10.c
index a1850ed..0090a4b 100644
--- a/gcc/testsuite/gcc.dg/vect/bb-slp-10.c
+++ b/gcc/testsuite/gcc.dg/vect/bb-slp-10.c
@@ -49,7 +49,7 @@ int main (void)
return 0;
}
-/* { dg-final { scan-tree-dump-times "unsupported alignment in basic block." 1 "slp2" { xfail vect_element_align } } } */
+/* { dg-final { scan-tree-dump "unsupported alignment in basic block." 1 "slp2" { xfail vect_element_align } } } */
/* { dg-final { scan-tree-dump-times "basic block vectorized" 1 "slp2" { target vect_element_align } } } */
/* { dg-final { cleanup-tree-dump "slp2" } } */
diff --git a/gcc/testsuite/gcc.dg/vect/vect-109.c b/gcc/testsuite/gcc.dg/vect/vect-109.c
index 854c970..c671175 100644
--- a/gcc/testsuite/gcc.dg/vect/vect-109.c
+++ b/gcc/testsuite/gcc.dg/vect/vect-109.c
@@ -1,3 +1,4 @@
+/* { dg-skip-if "" { vect_no_align } } */
/* { dg-require-effective-target vect_int } */
#include
diff --git a/gcc/testsuite/gcc.dg/vect/vect-93.c b/gcc/testsuite/gcc.dg/vect/vect-93.c
index 65403eb..1065a6e 100644
--- a/gcc/testsuite/gcc.dg/vect/vect-93.c
+++ b/gcc/testsuite/gcc.dg/vect/vect-93.c
@@ -79,7 +79,7 @@ int main (void)
/* { dg-final { scan-tree-dump-times "vectorized 2 loops" 1 "vect" { target vect_no_align } } } */
/* in main: */
-/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" { target vect_no_align } } } */
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_no_align } } } */
/* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 1 "vect" { xfail { vect_no_align } } } } */
/* { dg-final { cleanup-tree-dump "vect" } } */
diff --git a/gc
[PINGv3][PATCH] Fix for PR 61561
On 07/30/2014 04:56 PM, Marat Zakirov wrote: On 07/23/2014 05:33 PM, Marat Zakirov wrote: Hi all! This is a friendly reminder message. On 07/17/2014 03:22 PM, Marat Zakirov wrote: On 07/16/2014 01:32 PM, Kyrill Tkachov wrote: On 16/07/14 10:22, Marat Zakirov wrote: Christophe, Please look at a new patch. Draft tests are OK. I'll ask your commit approval when full regression (ARM/thumb1/thumb2) tests are done. Hi Marat, I was about to propose the thumb2.md hunk myself, but I'll defer to the arm maintainers to comment on the other parts. Also, in the ChangeLog it is helpful to specify which patterns are being affected, so in your case it would be something like: * config/arm/thumb1.md (*thumb1_movhi_insn): Handle stack pointer. (*thumb1_movqi_insn): Likewise. * config/arm/thumb2.md (*thumb2_movhi_insn): Ditto. Kyrill Christophe, Kirill, finally I've finished regression testing. Please check if my patch is OK for trunk. The following configures were used: configure --build=x86_64-pc-linux-gnu --host=x86_64-pc-linux-gnu --target=arm-linux-gnueabi --with-interwork --enable-long-long --enable-languages=c,c++,fortran --enable-shared --with-gnu-as --with-gnu-ld --with-arch=$ARCH --with-mode=$MODE Thumb-1 $ARCH=armv4t $MODE=thumb Thumb-2 $ARCH=armv7 $MODE=thumb ARM $ARCH=armv7-a $MODE=arm No regressions detected, test pr61561.c passed in all cases. Thank you all. --Marat gcc/ChangeLog: 2014-07-16 Marat Zakirov * config/arm/thumb1.md (*thumb1_movhi_insn): Handle stack pointer. (*thumb1_movqi_insn): Likewise. * config/arm/thumb2.md (*thumb2_movhi_insn): Likewise. diff --git a/gcc/config/arm/thumb1.md b/gcc/config/arm/thumb1.md index c044fd5..47b5cbd 100644 --- a/gcc/config/arm/thumb1.md +++ b/gcc/config/arm/thumb1.md @@ -708,7 +708,7 @@ (define_insn "*thumb1_movhi_insn" [(set (match_operand:HI 0 "nonimmediate_operand" "=l,l,m,*r,*h,l") - (match_operand:HI 1 "general_operand" "l,m,l,*h,*r,I"))] + (match_operand:HI 1 "general_operand" "lk,m,l,*h,*r,I"))] "TARGET_THUMB1 && ( register_operand (operands[0], HImode) || register_operand (operands[1], HImode))" @@ -762,7 +762,7 @@ (define_insn "*thumb1_movqi_insn" [(set (match_operand:QI 0 "nonimmediate_operand" "=l,l,m,*r,*h,l") - (match_operand:QI 1 "general_operand" "l, m,l,*h,*r,I"))] + (match_operand:QI 1 "general_operand" "lk, m,l,*h,*r,I"))] "TARGET_THUMB1 && ( register_operand (operands[0], QImode) || register_operand (operands[1], QImode))" diff --git a/gcc/config/arm/thumb2.md b/gcc/config/arm/thumb2.md index 6ea0810..7228069 100644 --- a/gcc/config/arm/thumb2.md +++ b/gcc/config/arm/thumb2.md @@ -318,7 +318,7 @@ ;; of the messiness associated with the ARM patterns. (define_insn "*thumb2_movhi_insn" [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,l,r,m,r") - (match_operand:HI 1 "general_operand" "r,I,Py,n,r,m"))] + (match_operand:HI 1 "general_operand" "rk,I,Py,n,r,m"))] "TARGET_THUMB2 && (register_operand (operands[0], HImode) || register_operand (operands[1], HImode))"
