[PATCH 1/7 v2] RISC-V: Add basic XAndes vendor extension support.

[Kuan-Lin Chen]

This patch add basic support for the following XAndes ISA extensions:

XANDESPERF
XANDESBFHCVT
XANDESVBFHCVT
XANDESVSINTLOAD
XANDESVPACKFPH
XANDESVDOT

gcc/ChangeLog:

* config/riscv/riscv-ext.def: Include riscv-ext-andes.def.
* config/riscv/riscv-ext.opt (riscv_xandes_subext): New variable.
(XANDESPERF) : New mask.
(XANDESBFHCVT): Ditto.
(XANDESVBFHCVT): Ditto.
(XANDESVSINTLOAD): Ditto.
(XANDESVPACKFPH): Ditto.
(XANDESVDOT): Ditto.
* config/riscv/t-riscv: Add riscv-ext-andes.def.
* doc/riscv-ext.texi: Regenerated.
* config/riscv/riscv-ext-andes.def: New file.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/xandes-predef-1.c: New test.
* gcc.target/riscv/xandes-predef-2.c: New test.
* gcc.target/riscv/xandes-predef-3.c: New test.
* gcc.target/riscv/xandes-predef-4.c: New test.
* gcc.target/riscv/xandes-predef-5.c: New test.
* gcc.target/riscv/xandes-predef-6.c: New test.

Co-author: Lino Hsing-Yu Peng (linop...@andestech.com),
   Kai Kai-Yi Weng (kaiw...@andestech.com).
---
 gcc/config/riscv/riscv-ext-andes.def  | 100 ++
 gcc/config/riscv/riscv-ext.def|   1 +
 gcc/config/riscv/riscv-ext.opt|  15 +++
 gcc/config/riscv/t-riscv  |   3 +-
 gcc/doc/riscv-ext.texi|  24 +
 .../gcc.target/riscv/xandes-predef-1.c|  14 +++
 .../gcc.target/riscv/xandes-predef-2.c|  14 +++
 .../gcc.target/riscv/xandes-predef-3.c|  14 +++
 .../gcc.target/riscv/xandes-predef-4.c|  14 +++
 .../gcc.target/riscv/xandes-predef-5.c|  14 +++
 .../gcc.target/riscv/xandes-predef-6.c|  14 +++
 11 files changed, 226 insertions(+), 1 deletion(-)
 create mode 100644 gcc/config/riscv/riscv-ext-andes.def
 create mode 100644 gcc/testsuite/gcc.target/riscv/xandes-predef-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/xandes-predef-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/xandes-predef-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/xandes-predef-4.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/xandes-predef-5.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/xandes-predef-6.c

diff --git a/gcc/config/riscv/riscv-ext-andes.def 
b/gcc/config/riscv/riscv-ext-andes.def
new file mode 100644
index ..4226e3ed86fe
--- /dev/null
+++ b/gcc/config/riscv/riscv-ext-andes.def
@@ -0,0 +1,100 @@
+/* Andes extension definition file for RISC-V.
+   Copyright (C) 2025 Free Software Foundation, Inc.
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 3, or (at your option)
+any later version.
+
+GCC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GCC; see the file COPYING3.  If not see
+.
+
+Please run `make riscv-regen` in build folder to make sure updated anything.
+
+Format of DEFINE_RISCV_EXT, please refer to riscv-ext.def.  */
+
+DEFINE_RISCV_EXT(
+  /* NAME */ xandesperf,
+  /* UPPERCASE_NAME */ XANDESPERF,
+  /* FULL_NAME */ "Andes performace extension",
+  /* DESC */ "",
+  /* URL */ ,
+  /* DEP_EXTS */ ({}),
+  /* SUPPORTED_VERSIONS */ ({{5, 0}}),
+  /* FLAG_GROUP */ xandes,
+  /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED,
+  /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED,
+  /* EXTRA_EXTENSION_FLAGS */ 0)
+
+DEFINE_RISCV_EXT(
+  /* NAME */ xandesbfhcvt,
+  /* UPPERCASE_NAME */ XANDESBFHCVT,
+  /* FULL_NAME */ "Andes bfloat16 conversion extension",
+  /* DESC */ "",
+  /* URL */ ,
+  /* DEP_EXTS */ ({}),
+  /* SUPPORTED_VERSIONS */ ({{5, 0}}),
+  /* FLAG_GROUP */ xandes,
+  /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED,
+  /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED,
+  /* EXTRA_EXTENSION_FLAGS */ 0)
+
+DEFINE_RISCV_EXT(
+  /* NAME */ xandesvbfhcvt,
+  /* UPPERCASE_NAME */ XANDESVBFHCVT,
+  /* FULL_NAME */ "Andes vector bfloat16 conversion extension",
+  /* DESC */ "",
+  /* URL */ ,
+  /* DEP_EXTS */ ({}),
+  /* SUPPORTED_VERSIONS */ ({{5, 0}}),
+  /* FLAG_GROUP */ xandes,
+  /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED,
+  /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED,
+  /* EXTRA_EXTENSION_FLAGS */ 0)
+
+DEFINE_RISCV_EXT(
+  /* NAME */ xandesvsintload,
+  /* UPPERCASE_NAME */ XANDESVSINTLOAD,
+  /* FULL_NAME */ "Andes vector INT4 load extension",
+  /* DESC */ "",
+  /* URL */ ,
+  /* DEP_EXTS */ ({}),
+  /* SUPPORTED_VERSIONS */ ({{5, 0}}),
+  /* FLAG_GROUP */ xandes,
+  /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED,
+  /* BITMASK_BIT_POSITION*/ BITMASK_NO

[PATCH 0/7 v2] Add Xandes vender extension support.

[Kuan-Lin Chen]

Changes since v1:
[PATCH 1/7]
Replaced "UPPERCAE_NAME" with "UPPERCASE_NAME".

[PATCH 2/7]
Renamed predicates
  - extract_loc_imm_si → unsigned_5_bit_integer_operand
  - extract_loc_imm_di → unsigned_6_bit_integer_operand
Replaced with existing predicates
  - Used const_int6_operand in place of extract_loc_imm_di
  - Defined const_int5_operand to replace extract_loc_imm_si
Branch handling updates
  - Added support for long-branch handling
  - Removed the length attribute from nds_branch_imms7 and 
nds_branch_on_bit
-Cost adjustments
  - For nds_branch_on_bit, set the combine-phase ZERO_EXTRACT cost to 
zero as intended
define_insn_and_splits condition fixes
  - Retained the built-in behavior where a split condition beginning with && is 
ANDed with the main condition
  - Reverted unnecessary changes to the split condition logic and simplified it 
back to the original form

[PATCH 6/7]
Removed "nds_vfpmad" temporarily before uploading Andes pipeline model.

Thanks for your review.


Kuan-Lin Chen (7):
  RISC-V: Add basic XAndes vendor extension support.
  RISC-V: Add support for the XAndesperf ISA extension.
  RISC-V: Add support for the XAndesbfhcvt ISA extension.
  RISC-V: Add support for the XAndesvbfhcvt ISA extension.
  RISC-V: Add support for the XAndesvsintload ISA extension.
  RISC-V: Add support for the XAndesvpackfph ISA extension.
  RISC-V: Add support for the XAndesvdot ISA extension.

 gcc/common/config/riscv/riscv-common.cc   |   3 +
 gcc/config.gcc|   4 +-
 .../riscv/andes-vector-builtins-bases.cc  | 189 +++
 .../riscv/andes-vector-builtins-bases.h   |  42 ++
 .../riscv/andes-vector-builtins-functions.def |  65 +++
 gcc/config/riscv/andes-vector.md  | 163 ++
 gcc/config/riscv/andes.def|  14 +
 gcc/config/riscv/andes.md | 469 ++
 gcc/config/riscv/andes_vector.h   |  32 ++
 gcc/config/riscv/constraints.md   |  10 +
 gcc/config/riscv/genrvv-type-indexer.cc   |   6 +-
 gcc/config/riscv/iterators.md |  12 +
 gcc/config/riscv/predicates.md|  42 ++
 gcc/config/riscv/riscv-builtins.cc|  10 +
 gcc/config/riscv/riscv-ext-andes.def  | 100 
 gcc/config/riscv/riscv-ext.def|   1 +
 gcc/config/riscv/riscv-ext.opt|  15 +
 gcc/config/riscv/riscv-ftypes.def |   3 +
 .../riscv/riscv-vector-builtins-types.def |  44 ++
 gcc/config/riscv/riscv-vector-builtins.cc | 103 
 gcc/config/riscv/riscv-vector-builtins.def|   4 +
 gcc/config/riscv/riscv-vector-builtins.h  |  20 +
 gcc/config/riscv/riscv.cc |  32 ++
 gcc/config/riscv/riscv.md |  17 +-
 gcc/config/riscv/t-riscv  |  18 +-
 gcc/config/riscv/vector-iterators.md  |  38 +-
 gcc/config/riscv/vector.md|   1 +
 gcc/doc/riscv-ext.texi|  24 +
 gcc/testsuite/gcc.target/riscv/rvv/rvv.exp|  12 +
 .../riscv/rvv/xandesvector/nds_vfwcvt.c   |  37 ++
 .../non-policy/non-overloaded/nds_vd4dots.c   | 132 +
 .../non-policy/non-overloaded/nds_vd4dotsu.c  | 132 +
 .../non-policy/non-overloaded/nds_vd4dotu.c   | 132 +
 .../non-policy/non-overloaded/nds_vfpmadb.c   | 103 
 .../non-policy/non-overloaded/nds_vfpmadt.c   | 103 
 .../non-policy/non-overloaded/nds_vln8.c  |  62 +++
 .../non-policy/overloaded/nds_vd4dots.c   | 132 +
 .../non-policy/overloaded/nds_vd4dotsu.c  | 132 +
 .../non-policy/overloaded/nds_vd4dotu.c   | 133 +
 .../non-policy/overloaded/nds_vfpmadb.c   | 103 
 .../non-policy/overloaded/nds_vfpmadt.c   | 103 
 .../non-policy/overloaded/nds_vln8.c  |  34 ++
 .../policy/non-overloaded/nds_vd4dots.c   | 258 ++
 .../policy/non-overloaded/nds_vd4dotsu.c  | 258 ++
 .../policy/non-overloaded/nds_vd4dotu.c   | 258 ++
 .../policy/non-overloaded/nds_vfpmadb.c   | 199 
 .../policy/non-overloaded/nds_vfpmadt.c   | 199 
 .../policy/non-overloaded/nds_vln8.c  | 118 +
 .../policy/overloaded/nds_vd4dots.c   | 258 ++
 .../policy/overloaded/nds_vd4dotsu.c  | 258 ++
 .../policy/overloaded/nds_vd4dotu.c   | 258 ++
 .../policy/overloaded/nds_vfpmadb.c   | 199 
 .../policy/overloaded/nds_vfpmadt.c   | 199 
 .../xandesvector/policy/overloaded/nds_vln8.c | 118 +
 .../gcc.target/riscv/xandes-predef-1.c|  14 +
 .../gcc.target/riscv/xandes-predef-2.c|  14 +
 .../gcc.target/riscv/xandes-predef-3.c|  14 +
 .../gcc.target/riscv/xandes-predef-4.c|  14 +
 .../gcc.target/riscv/xandes-predef-5.c|  14 +
 .../gcc.target/riscv/xandes-predef-6.c|  14 +
 .../gcc.target/riscv/xandesbfhcvt-1.c |  11 +

[PATCH 3/7 v2] RISC-V: Add support for the XAndesbfhcvt ISA extension.

[Kuan-Lin Chen]

This extension defines instructions to perform scalar floating-point
conversion between the BFLOAT16 floating-point data and the IEEE-754
32-bit single-precision floating-point (SP) data in a scalar
floating point register.

gcc/ChangeLog:

* config/riscv/andes.def: Add nds_fcvt_s_bf16 and nds_fcvt_bf16_s.
* config/riscv/andes.md (riscv_nds_fcvt_bf16_s): New pattern.
(riscv_nds_fcvt_s_bf16): New pattern.
* config/riscv/riscv-builtins.cc: New AVAIL andesbfhcvt.
Add new define RISCV_ATYPE_BF and RISCV_ATYPE_SF.
* config/riscv/riscv-ftypes.def: New DEF_RISCV_FTYPE.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/xandesbfhcvt-1.c: New test.
* gcc.target/riscv/xandesbfhcvt-2.c: New test.
---
 gcc/config/riscv/andes.def|  4 +++
 gcc/config/riscv/andes.md | 26 +++
 gcc/config/riscv/riscv-builtins.cc|  3 +++
 gcc/config/riscv/riscv-ftypes.def |  2 ++
 .../gcc.target/riscv/xandesbfhcvt-1.c | 11 
 .../gcc.target/riscv/xandesbfhcvt-2.c | 11 
 6 files changed, 57 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/xandesbfhcvt-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/xandesbfhcvt-2.c

diff --git a/gcc/config/riscv/andes.def b/gcc/config/riscv/andes.def
index b864ae712c1d..5b5fb76bfe0e 100644
--- a/gcc/config/riscv/andes.def
+++ b/gcc/config/riscv/andes.def
@@ -8,3 +8,7 @@ RISCV_BUILTIN (nds_ffmismsi, "nds_ffmism", 
RISCV_BUILTIN_DIRECT, RISCV_LONG_FTYP
 RISCV_BUILTIN (nds_ffmismdi, "nds_ffmism", RISCV_BUILTIN_DIRECT, 
RISCV_LONG_FTYPE_ULONG_ULONG, andesperf64),
 RISCV_BUILTIN (nds_flmismsi, "nds_flmism", RISCV_BUILTIN_DIRECT, 
RISCV_LONG_FTYPE_ULONG_ULONG, andesperf32),
 RISCV_BUILTIN (nds_flmismdi, "nds_flmism", RISCV_BUILTIN_DIRECT, 
RISCV_LONG_FTYPE_ULONG_ULONG, andesperf64),
+
+/* Andes Scalar BFLOAT16 Conversion Extension */
+RISCV_BUILTIN (nds_fcvt_s_bf16, "nds_fcvt_s_bf16", RISCV_BUILTIN_DIRECT, 
RISCV_SF_FTYPE_BF, andesbfhcvt),
+RISCV_BUILTIN (nds_fcvt_bf16_s, "nds_fcvt_bf16_s", RISCV_BUILTIN_DIRECT, 
RISCV_BF_FTYPE_SF, andesbfhcvt),
diff --git a/gcc/config/riscv/andes.md b/gcc/config/riscv/andes.md
index 51f61e58e244..22aa5e5150d5 100644
--- a/gcc/config/riscv/andes.md
+++ b/gcc/config/riscv/andes.md
@@ -441,3 +441,29 @@
   "nds.flmism\t%0, %z1, %z2"
   [(set_attr "mode" "")
(set_attr "type" "arith")])
+
+;;
+;;  
+;;
+;;Bfloat16
+;;
+;;  
+;;
+
+(define_insn "riscv_nds_fcvt_bf16_s"
+  [(set (match_operand:BF   0 "register_operand" "=f")
+   (float_truncate:BF
+ (match_operand:SF 1 "register_operand" " f")))]
+  "TARGET_XANDESBFHCVT"
+  "nds.fcvt.bf16.s\t%0,%1"
+  [(set_attr "type" "fcvt")
+   (set_attr "mode" "BF")])
+
+(define_insn "riscv_nds_fcvt_s_bf16"
+  [(set (match_operand:SF   0 "register_operand" "=f")
+   (float_extend:SF
+ (match_operand:BF 1 "register_operand" " f")))]
+  "TARGET_XANDESBFHCVT"
+  "nds.fcvt.s.bf16\t%0,%1"
+  [(set_attr "type" "fcvt")
+   (set_attr "mode" "SF")])
diff --git a/gcc/config/riscv/riscv-builtins.cc 
b/gcc/config/riscv/riscv-builtins.cc
index 8b081e240be4..799c7a4ccd13 100644
--- a/gcc/config/riscv/riscv-builtins.cc
+++ b/gcc/config/riscv/riscv-builtins.cc
@@ -140,6 +140,7 @@ AVAIL (cvsimd, TARGET_XCVSIMD && !TARGET_64BIT)
 /* ANDES AVAIL.  */
 AVAIL (andesperf32, !TARGET_64BIT && TARGET_XANDESPERF)
 AVAIL (andesperf64, TARGET_64BIT && TARGET_XANDESPERF)
+AVAIL (andesbfhcvt, TARGET_XANDESBFHCVT)
 
 /* Construct a riscv_builtin_description from the given arguments.
 
@@ -199,6 +200,8 @@ AVAIL (andesperf64, TARGET_64BIT && TARGET_XANDESPERF)
 #define RISCV_ATYPE_INT_PTR integer_ptr_type_node
 #define RISCV_ATYPE_ULONG long_unsigned_type_node
 #define RISCV_ATYPE_LONG long_integer_type_node
+#define RISCV_ATYPE_BF bfloat16_type_node
+#define RISCV_ATYPE_SF float_type_node
 
 /* RISCV_FTYPE_ATYPESN takes N RISCV_FTYPES-like type codes and lists
their associated RISCV_ATYPEs.  */
diff --git a/gcc/config/riscv/riscv-ftypes.def 
b/gcc/config/riscv/riscv-ftypes.def
index fd1314d9d975..f50a37a581a6 100644
--- a/gcc/config/riscv/riscv-ftypes.def
+++ b/gcc/config/riscv/riscv-ftypes.def
@@ -37,6 +37,8 @@ DEF_RISCV_FTYPE (1, (USI, UQI))
 DEF_RISCV_FTYPE (1, (USI, UHI))
 DEF_RISCV_FTYPE (1, (SI, QI))
 DEF_RISCV_FTYPE (1, (SI, HI))
+DEF_RISCV_FTYPE (1, (BF, SF))
+DEF_RISCV_FTYPE (1, (SF, BF))
 DEF_RISCV_FTYPE (2, (USI, UQI, UQI))
 DEF_RISCV_FTYPE (2, (USI, USI, UHI))
 DEF_RISCV_FTYPE (2, (USI, USI, QI))
diff --git a/gcc/testsuite/gcc.target/riscv/xandesbfhcvt-1.c 
b/gcc/testsuite/gcc.target/riscv/xandesbfhcvt-1.c
new file mode 100644
index ..b174b6ef5053
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/xandesbfhcvt-1.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_xandesbfhcvt" { target { rv32 } } } */
+/* { dg-options "-march=rv64gc_xandesbfhcvt" { target { rv64 } } } */

[PATCH 7/7 v2] RISC-V: Add support for the XAndesvdot ISA extension.

[Kuan-Lin Chen]

This extension defines vector instructions to calculae of the signed/unsigned
dot product of four SEW/4-bit data and accumulate the result into a SEWbit
element for all elements in a vector register.

gcc/ChangeLog:

* config/riscv/andes-vector-builtins-bases.cc (nds_vd4dot): New class.
(class nds_vd4dotsu): New class.
* config/riscv/andes-vector-builtins-bases.h: New def.
* config/riscv/andes-vector-builtins-functions.def (nds_vd4dots): Ditto.
(nds_vd4dotsu): Ditto.
(nds_vd4dotu): Ditto.
* config/riscv/andes-vector.md
(@pred_nds_vd4dot): New pattern.
(@pred_nds_vd4dotsu): New pattern.
* config/riscv/genrvv-type-indexer.cc (main): Modify sew of QUAD_FIX,
QUAD_FIX_SIGNED and QUAD_FIX_UNSIGNED.
* config/riscv/riscv-vector-builtins.cc
(qexti__ops): New operand information.
(qexti_su__ops): New operand information.
(qextu__ops): New operand information.
* config/riscv/riscv-vector-builtins.h (XANDESVDOT_EXT): New def.
(required_ext_to_isa_name): Add case XANDESVDOT_EXT.
(required_extensions_specified): Ditto.
(struct function_group_info): Ditto.
* config/riscv/vector-iterators.md (NDS_QUAD_FIX): New iterator.

gcc/testsuite/ChangeLog:

* 
gcc.target/riscv/rvv/xandesvector/non-policy/non-overloaded/nds_vd4dots.c: New 
test.
* 
gcc.target/riscv/rvv/xandesvector/non-policy/non-overloaded/nds_vd4dotsu.c: New 
test.
* 
gcc.target/riscv/rvv/xandesvector/non-policy/non-overloaded/nds_vd4dotu.c: New 
test.
* 
gcc.target/riscv/rvv/xandesvector/non-policy/overloaded/nds_vd4dots.c: New test.
* 
gcc.target/riscv/rvv/xandesvector/non-policy/overloaded/nds_vd4dotsu.c: New 
test.
* 
gcc.target/riscv/rvv/xandesvector/non-policy/overloaded/nds_vd4dotu.c: New test.
* 
gcc.target/riscv/rvv/xandesvector/policy/non-overloaded/nds_vd4dots.c: New test.
* 
gcc.target/riscv/rvv/xandesvector/policy/non-overloaded/nds_vd4dotsu.c: New 
test.
* 
gcc.target/riscv/rvv/xandesvector/policy/non-overloaded/nds_vd4dotu.c: New test.
* gcc.target/riscv/rvv/xandesvector/policy/overloaded/nds_vd4dots.c: 
New test.
* gcc.target/riscv/rvv/xandesvector/policy/overloaded/nds_vd4dotsu.c: 
New test.
* gcc.target/riscv/rvv/xandesvector/policy/overloaded/nds_vd4dotu.c: 
New test.
---
 .../riscv/andes-vector-builtins-bases.cc  |  33 +++
 .../riscv/andes-vector-builtins-bases.h   |   3 +
 .../riscv/andes-vector-builtins-functions.def |   7 +
 gcc/config/riscv/andes-vector.md  |  53 
 gcc/config/riscv/genrvv-type-indexer.cc   |   6 +-
 gcc/config/riscv/riscv-vector-builtins.cc |  31 +++
 gcc/config/riscv/riscv-vector-builtins.h  |   5 +
 gcc/config/riscv/vector-iterators.md  |  13 +
 .../non-policy/non-overloaded/nds_vd4dots.c   | 132 +
 .../non-policy/non-overloaded/nds_vd4dotsu.c  | 132 +
 .../non-policy/non-overloaded/nds_vd4dotu.c   | 132 +
 .../non-policy/overloaded/nds_vd4dots.c   | 132 +
 .../non-policy/overloaded/nds_vd4dotsu.c  | 132 +
 .../non-policy/overloaded/nds_vd4dotu.c   | 133 +
 .../policy/non-overloaded/nds_vd4dots.c   | 258 ++
 .../policy/non-overloaded/nds_vd4dotsu.c  | 258 ++
 .../policy/non-overloaded/nds_vd4dotu.c   | 258 ++
 .../policy/overloaded/nds_vd4dots.c   | 258 ++
 .../policy/overloaded/nds_vd4dotsu.c  | 258 ++
 .../policy/overloaded/nds_vd4dotu.c   | 258 ++
 20 files changed, 2489 insertions(+), 3 deletions(-)
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/xandesvector/non-policy/non-overloaded/nds_vd4dots.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/xandesvector/non-policy/non-overloaded/nds_vd4dotsu.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/xandesvector/non-policy/non-overloaded/nds_vd4dotu.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/xandesvector/non-policy/overloaded/nds_vd4dots.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/xandesvector/non-policy/overloaded/nds_vd4dotsu.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/xandesvector/non-policy/overloaded/nds_vd4dotu.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/xandesvector/policy/non-overloaded/nds_vd4dots.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/xandesvector/policy/non-overloaded/nds_vd4dotsu.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/xandesvector/policy/non-overloaded/nds_vd4dotu.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/xandesvector/policy/overloaded/nds_vd4dots.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/xandesvector/policy/overloaded/nds_vd4dotsu.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/xandesvector/policy/overloade

[PATCH 2/7 v2] RISC-V: Add support for the XAndesperf ISA extension.

[Kuan-Lin Chen]

This patch adds support for the XAndesperf ISA extension.
The 32-bit AndeStar V5 extension includes branch instructions,
load effective address instructions, and string processing
instructions for performance improvement.
New INSN patterns are added into the new file andes.md
as a seprated vender extension.

gcc/ChangeLog:

* config/riscv/constraints.md (Ou07): New constraint.
(ads_Bext): New constraint.
* config/riscv/iterators.md (ANYLE32): New iterator.
(sizen): New iterator.
(sh_limit): New iterator.
(sh_bit): New iterator.
* config/riscv/predicates.md (ads_branch_bbcs_operand): New predicate.
(ads_branch_bimm_operand): New predicate.
(ads_imm_extract_operand): New predicate.
(ads_extract_size_imm_si): New predicate.
(ads_extract_size_imm_di): New predicate.
(const_int5_operand): New predicate.
* config/riscv/riscv-builtins.cc:
Add new AVAIL andesperf32 and andesperf64.
Add new define RISCV_ATYPE_ULONG and RISCV_ATYPE_LONG.
* config/riscv/riscv-ftypes.def: New DEF_RISCV_FTYPE.
* config/riscv/riscv.cc
(riscv_extend_cost): Cost for pattern 'bfo'.
(riscv_rtx_costs): Cost for XAndesperf extension.
* config/riscv/riscv.md: Add support for XAndesperf to patterns
zero_extendsidi2_internal, zero_extendhi2, extendsidi2_internal,
extend2, 3
and branch_on_bit.
* config/riscv/vector-iterators.md
 (sz): Add sign_extract and zero_extract.
* config/riscv/andes.def: New file for vender Andes.
* config/riscv/andes.md: New file for vender Andes.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/xandesperf-1.c: New test.
* gcc.target/riscv/xandesperf-10.c: New test.
* gcc.target/riscv/xandesperf-2.c: New test.
* gcc.target/riscv/xandesperf-3.c: New test.
* gcc.target/riscv/xandesperf-4.c: New test.
* gcc.target/riscv/xandesperf-5.c: New test.
* gcc.target/riscv/xandesperf-6.c: New test.
* gcc.target/riscv/xandesperf-7.c: New test.
* gcc.target/riscv/xandesperf-8.c: New test.
* gcc.target/riscv/xandesperf-9.c: New test.
---
 gcc/config/riscv/andes.def|  10 +
 gcc/config/riscv/andes.md | 443 ++
 gcc/config/riscv/constraints.md   |  10 +
 gcc/config/riscv/iterators.md |  12 +
 gcc/config/riscv/predicates.md|  42 ++
 gcc/config/riscv/riscv-builtins.cc|   7 +
 gcc/config/riscv/riscv-ftypes.def |   1 +
 gcc/config/riscv/riscv.cc |  32 ++
 gcc/config/riscv/riscv.md |  17 +-
 gcc/config/riscv/vector-iterators.md  |   2 +-
 gcc/testsuite/gcc.target/riscv/xandesperf-1.c |  13 +
 .../gcc.target/riscv/xandesperf-10.c  |  32 ++
 gcc/testsuite/gcc.target/riscv/xandesperf-2.c |  13 +
 gcc/testsuite/gcc.target/riscv/xandesperf-3.c |  11 +
 gcc/testsuite/gcc.target/riscv/xandesperf-4.c |  11 +
 gcc/testsuite/gcc.target/riscv/xandesperf-5.c |  11 +
 gcc/testsuite/gcc.target/riscv/xandesperf-6.c |  18 +
 gcc/testsuite/gcc.target/riscv/xandesperf-7.c |  22 +
 gcc/testsuite/gcc.target/riscv/xandesperf-8.c |  26 +
 gcc/testsuite/gcc.target/riscv/xandesperf-9.c |  31 ++
 20 files changed, 757 insertions(+), 7 deletions(-)
 create mode 100644 gcc/config/riscv/andes.def
 create mode 100644 gcc/config/riscv/andes.md
 create mode 100644 gcc/testsuite/gcc.target/riscv/xandesperf-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/xandesperf-10.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/xandesperf-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/xandesperf-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/xandesperf-4.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/xandesperf-5.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/xandesperf-6.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/xandesperf-7.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/xandesperf-8.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/xandesperf-9.c

diff --git a/gcc/config/riscv/andes.def b/gcc/config/riscv/andes.def
new file mode 100644
index ..b864ae712c1d
--- /dev/null
+++ b/gcc/config/riscv/andes.def
@@ -0,0 +1,10 @@
+// XANDESPERF
+/* Andes Performance Extension */
+RISCV_BUILTIN (nds_ffbsi, "nds_ffb", RISCV_BUILTIN_DIRECT, 
RISCV_LONG_FTYPE_ULONG_ULONG, andesperf32),
+RISCV_BUILTIN (nds_ffbdi, "nds_ffb", RISCV_BUILTIN_DIRECT, 
RISCV_LONG_FTYPE_ULONG_ULONG, andesperf64),
+RISCV_BUILTIN (nds_ffzmismsi, "nds_ffzmism", RISCV_BUILTIN_DIRECT, 
RISCV_LONG_FTYPE_ULONG_ULONG, andesperf32),
+RISCV_BUILTIN (nds_ffzmismdi, "nds_ffzmism", RISCV_BUILTIN_DIRECT, 
RISCV_LONG_FTYPE_ULONG_ULONG, andesperf64),
+RISCV_BUILTIN (nds_ffmismsi, "nds_ffmism", RISCV_BUILTIN_DIRECT, 
RISCV_LONG_FTYPE_ULONG_ULONG, andesperf32),
+RISCV_BUILTIN (nds_ffmismdi, "nds_ffmism", RISCV_

[PATCH 4/7 v2] RISC-V: Add support for the XAndesvbfhcvt ISA extension.

[Kuan-Lin Chen]

This patch add support for XAndesvbfhcvt ISA extension.
This extension defines instructions to perform vector floating-point
conversion between the BFLOAT16 floating-point data and the IEEE-754 32-bit
single-precision floating-point (SP) data in a vector register.

gcc/ChangeLog:

* common/config/riscv/riscv-common.cc:
Turn on VECTOR_ELEN_BF_16 for XAndesvbfhcvt.
* config.gcc: Add extra_objs andes-vector-builtins-bases.o
and extra_headers andes_vector.h.
* config/riscv/riscv-vector-builtins.cc
(f32_to_bf16_nf_w_ops): New operand information.
(f32_to_bf16_nf_w_ops): New operand information.
(DEF_RVV_FUNCTION): New def.
* config/riscv/riscv-vector-builtins.def (bf16_s): Ditto.
(s_bf16): Ditto.
* config/riscv/riscv-vector-builtins.h (enum required_ext): Ditto.
(required_ext_to_isa_name): Add case XANDESVBFHCVT_EXT.
(required_extensions_specified): Ditto.
* config/riscv/t-riscv: Add andes-vector-builtins-functions.def,
andes-vector-builtins-bases.h and andes-vector-builtins-bases.o.
* config/riscv/vector-iterators.md (NDS_VWEXTBF): New iterator.
(NDS_V_DOUBLE_TRUNC_BF): New attr.
* config/riscv/andes-vector-builtins-bases.cc: New file.
* config/riscv/andes-vector-builtins-bases.h: New file.
* config/riscv/andes-vector-builtins-functions.def: New file.
* config/riscv/andes_vector.h: New file.
* config/riscv/andes_vector.md: New file.
* config/riscv/vector.md: Include andes_vector.md.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/rvv.exp:
* gcc.target/riscv/rvv/xandesvector/nds_vfwcvt.c: New test.
---
 gcc/common/config/riscv/riscv-common.cc   |   2 +
 gcc/config.gcc|   4 +-
 .../riscv/andes-vector-builtins-bases.cc  | 103 ++
 .../riscv/andes-vector-builtins-bases.h   |  33 ++
 .../riscv/andes-vector-builtins-functions.def |  45 
 gcc/config/riscv/andes-vector.md  |  51 +
 gcc/config/riscv/andes_vector.h   |  32 ++
 gcc/config/riscv/riscv-vector-builtins.cc |  21 
 gcc/config/riscv/riscv-vector-builtins.def|   2 +
 gcc/config/riscv/riscv-vector-builtins.h  |   5 +
 gcc/config/riscv/t-riscv  |  15 +++
 gcc/config/riscv/vector-iterators.md  |  13 +++
 gcc/config/riscv/vector.md|   1 +
 gcc/testsuite/gcc.target/riscv/rvv/rvv.exp|   2 +
 .../riscv/rvv/xandesvector/nds_vfwcvt.c   |  37 +++
 15 files changed, 364 insertions(+), 2 deletions(-)
 create mode 100644 gcc/config/riscv/andes-vector-builtins-bases.cc
 create mode 100644 gcc/config/riscv/andes-vector-builtins-bases.h
 create mode 100644 gcc/config/riscv/andes-vector-builtins-functions.def
 create mode 100644 gcc/config/riscv/andes-vector.md
 create mode 100644 gcc/config/riscv/andes_vector.h
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xandesvector/nds_vfwcvt.c

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index 82037a334528..2e20eee87902 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -1528,6 +1528,8 @@ static const riscv_extra_ext_flag_table_t 
riscv_extra_ext_flag_table[] =
   RISCV_EXT_FLAG_ENTRY ("xtheadvector",  x_riscv_isa_flags, MASK_FULL_V),
   RISCV_EXT_FLAG_ENTRY ("xtheadvector",  x_riscv_isa_flags, MASK_VECTOR),
 
+  RISCV_EXT_FLAG_ENTRY ("xandesvbfhcvt", x_riscv_vector_elen_flags, 
MASK_VECTOR_ELEN_BF_16),
+
   {NULL, NULL, NULL, 0}
 };
 
diff --git a/gcc/config.gcc b/gcc/config.gcc
index 8ed111392bb4..45a17fbb452b 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -549,10 +549,10 @@ riscv*)
cpu_type=riscv
extra_objs="riscv-builtins.o riscv-c.o riscv-sr.o 
riscv-shorten-memrefs.o riscv-selftests.o riscv-string.o"
extra_objs="${extra_objs} riscv-v.o riscv-vsetvl.o riscv-vector-costs.o 
riscv-avlprop.o riscv-vect-permconst.o"
-   extra_objs="${extra_objs} riscv-vector-builtins.o 
riscv-vector-builtins-shapes.o riscv-vector-builtins-bases.o 
sifive-vector-builtins-bases.o"
+   extra_objs="${extra_objs} riscv-vector-builtins.o 
riscv-vector-builtins-shapes.o riscv-vector-builtins-bases.o 
sifive-vector-builtins-bases.o andes-vector-builtins-bases.o"
extra_objs="${extra_objs} thead.o riscv-target-attr.o riscv-zicfilp.o"
d_target_objs="riscv-d.o"
-   extra_headers="riscv_vector.h riscv_crypto.h riscv_bitmanip.h 
riscv_th_vector.h sifive_vector.h"
+   extra_headers="riscv_vector.h riscv_crypto.h riscv_bitmanip.h 
riscv_th_vector.h sifive_vector.h andes_vector.h"
target_gtfiles="$target_gtfiles 
\$(srcdir)/config/riscv/riscv-vector-builtins.cc"
target_gtfiles="$target_gtfiles 
\$(srcdir)/config/riscv/riscv-vector-builtins.h"
extra_options="${extra_options} riscv/riscv-ext.opt"
diff 

[PATCH 5/7 v2] RISC-V: Add support for the XAndesvsintload ISA extension.

[Kuan-Lin Chen]

This extension defines vector load instructions to move sign-extended or
zero-extended INT4 data into 8-bit vector register elements.

gcc/ChangeLog:

* config/riscv/andes-vector-builtins-bases.cc
(nds_nibbleload): New class.
* config/riscv/andes-vector-builtins-bases.h (nds_vln8): New def.
(nds_vlnu8): Ditto.
* config/riscv/andes-vector-builtins-functions.def (nds_vln8): Ditto.
(nds_vlnu8): Ditto.
* config/riscv/andes.md (@pred_intload_mov): New pattern.
* config/riscv/riscv-vector-builtins-types.def (DEF_RVV_Q_OPS): New def.
(DEF_RVV_QU_OPS): Ditto.
* config/riscv/riscv-vector-builtins.cc
(q_v_void_const_ptr_ops): New operand information.
(qu_v_void_const_ptr_ops): Ditto.
* config/riscv/riscv-vector-builtins.def (void_const_ptr): New def.
* config/riscv/riscv-vector-builtins.h (enum required_ext): Ditto.
(required_ext_to_isa_name): Add case XANDESVSINTLOAD_EXT.
(required_extensions_specified): Ditto.
* config/riscv/vector-iterators.md (NDS_QVI): New iterator.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/rvv.exp: Add regression for xandesvector.
* 
gcc.target/riscv/rvv/xandesvector/non-policy/non-overloaded/nds_vln8.c: New 
test.
* gcc.target/riscv/rvv/xandesvector/non-policy/overloaded/nds_vln8.c: 
New test.
* gcc.target/riscv/rvv/xandesvector/policy/non-overloaded/nds_vln8.c: 
New test.
* gcc.target/riscv/rvv/xandesvector/policy/overloaded/nds_vln8.c: New 
test.
---
 .../riscv/andes-vector-builtins-bases.cc  |  30 -
 .../riscv/andes-vector-builtins-bases.h   |   2 +
 .../riscv/andes-vector-builtins-functions.def |   5 +
 gcc/config/riscv/andes-vector.md  |  27 
 .../riscv/riscv-vector-builtins-types.def |  30 +
 gcc/config/riscv/riscv-vector-builtins.cc |  32 +
 gcc/config/riscv/riscv-vector-builtins.def|   1 +
 gcc/config/riscv/riscv-vector-builtins.h  |   5 +
 gcc/config/riscv/vector-iterators.md  |   5 +
 gcc/testsuite/gcc.target/riscv/rvv/rvv.exp|  10 ++
 .../non-policy/non-overloaded/nds_vln8.c  |  62 +
 .../non-policy/overloaded/nds_vln8.c  |  34 +
 .../policy/non-overloaded/nds_vln8.c  | 118 ++
 .../xandesvector/policy/overloaded/nds_vln8.c | 118 ++
 14 files changed, 478 insertions(+), 1 deletion(-)
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/xandesvector/non-policy/non-overloaded/nds_vln8.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/xandesvector/non-policy/overloaded/nds_vln8.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/xandesvector/policy/non-overloaded/nds_vln8.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/xandesvector/policy/overloaded/nds_vln8.c

diff --git a/gcc/config/riscv/andes-vector-builtins-bases.cc 
b/gcc/config/riscv/andes-vector-builtins-bases.cc
index 69e16fd94543..2c19f32225b9 100644
--- a/gcc/config/riscv/andes-vector-builtins-bases.cc
+++ b/gcc/config/riscv/andes-vector-builtins-bases.cc
@@ -89,8 +89,35 @@ public:
   }
 };
 
+/* Implements Andes vln8.v/vln8.v.  */
+template 
+class nds_nibbleload : public function_base
+{
+public:
+  unsigned int call_properties (const function_instance &) const override
+  {
+return CP_READ_MEMORY;
+  }
+
+  bool can_be_overloaded_p (enum predication_type_index pred) const override
+  {
+return pred != PRED_TYPE_none;
+  }
+
+  rtx expand (function_expander &e) const override
+  {
+if (SIGN)
+  return e.use_contiguous_load_insn (
+   code_for_pred_intload_mov (SIGN_EXTEND, e.vector_mode ()));
+return e.use_contiguous_load_insn (
+  code_for_pred_intload_mov (ZERO_EXTEND, e.vector_mode ()));
+  }
+};
+
 static CONSTEXPR const nds_vfwcvt nds_vfwcvt_obj;
 static CONSTEXPR const nds_vfncvt nds_vfncvt_obj;
+static CONSTEXPR const nds_nibbleload nds_vln8_obj;
+static CONSTEXPR const nds_nibbleload nds_vlnu8_obj;
 
 /* Declare the function base NAME, pointing it to an instance
of class _obj.  */
@@ -99,5 +126,6 @@ static CONSTEXPR const nds_vfncvt nds_vfncvt_obj;
 
 BASE (nds_vfwcvt)
 BASE (nds_vfncvt)
-
+BASE (nds_vln8)
+BASE (nds_vlnu8)
 } // end namespace riscv_vector
diff --git a/gcc/config/riscv/andes-vector-builtins-bases.h 
b/gcc/config/riscv/andes-vector-builtins-bases.h
index 7d11761d8f6e..d983b44d2e9d 100644
--- a/gcc/config/riscv/andes-vector-builtins-bases.h
+++ b/gcc/config/riscv/andes-vector-builtins-bases.h
@@ -26,6 +26,8 @@ namespace riscv_vector {
 namespace bases {
 extern const function_base *const nds_vfwcvt;
 extern const function_base *const nds_vfncvt;
+extern const function_base *const nds_vln8;
+extern const function_base *const nds_vlnu8;
 }
 
 } // end namespace riscv_vector
diff --git a/gcc/config/riscv/andes-vector-builtins-functions.def 
b/gcc/config/riscv/andes-vector-builtins-functions.def
index 989db8c71bab..ebb0de3217ea 100644
--- a

[PATCH 6/7 v2] RISC-V: Add support for the XAndesvpackfph ISA extension.

[Kuan-Lin Chen]

This extension defines vector instructions to extract a pair of FP16 data from
a floating-point register. Multiply the top FP16 data with the FP16 elements
and add the result with the bottom FP16 data.

gcc/ChangeLog:

* common/config/riscv/riscv-common.cc:
Turn on VECTOR_ELEN_FP_16 for XAndesvpackfph.
* config/riscv/andes-vector-builtins-bases.cc (nds_vfpmad): New class.
* config/riscv/andes-vector-builtins-bases.h: New def.
* config/riscv/andes-vector-builtins-functions.def (nds_vfpmadt): Ditto.
(nds_vfpmadb): Ditto.
(nds_vfpmadt_frm): Ditto.
(nds_vfpmadb_frm): Ditto.
* config/riscv/andes-vector.md (@pred_nds_vfpmad):
New pattern.
* config/riscv/riscv-vector-builtins-types.def
(DEF_RVV_F16_OPS): New def.
* config/riscv/riscv-vector-builtins.cc (f16_ops): Ditto
* config/riscv/riscv-vector-builtins.def (float32_type_node): Ditto.
* config/riscv/riscv-vector-builtins.h (XANDESVPACKFPH_EXT): Ditto.
(required_ext_to_isa_name): Add case XANDESVPACKFPH_EXT.
(required_extensions_specified): Ditto.
* config/riscv/vector-iterators.md (VHF): New iterator.

gcc/testsuite/ChangeLog:

* 
gcc.target/riscv/rvv/xandesvector/non-policy/non-overloaded/nds_vfpmadb.c: New 
test.
* 
gcc.target/riscv/rvv/xandesvector/non-policy/non-overloaded/nds_vfpmadt.c: New 
test.
* 
gcc.target/riscv/rvv/xandesvector/non-policy/overloaded/nds_vfpmadb.c: New test.
* 
gcc.target/riscv/rvv/xandesvector/non-policy/overloaded/nds_vfpmadt.c: New test.
* 
gcc.target/riscv/rvv/xandesvector/policy/non-overloaded/nds_vfpmadb.c: New test.
* 
gcc.target/riscv/rvv/xandesvector/policy/non-overloaded/nds_vfpmadt.c: New test.
* gcc.target/riscv/rvv/xandesvector/policy/overloaded/nds_vfpmadb.c: 
New test.
* gcc.target/riscv/rvv/xandesvector/policy/overloaded/nds_vfpmadt.c: 
New test.
---
 gcc/common/config/riscv/riscv-common.cc   |   3 +-
 .../riscv/andes-vector-builtins-bases.cc  |  25 +++
 .../riscv/andes-vector-builtins-bases.h   |   4 +
 .../riscv/andes-vector-builtins-functions.def |   8 +
 gcc/config/riscv/andes-vector.md  |  32 +++
 .../riscv/riscv-vector-builtins-types.def |  14 ++
 gcc/config/riscv/riscv-vector-builtins.cc |  19 ++
 gcc/config/riscv/riscv-vector-builtins.def|   1 +
 gcc/config/riscv/riscv-vector-builtins.h  |   5 +
 gcc/config/riscv/vector-iterators.md  |   5 +
 .../non-policy/non-overloaded/nds_vfpmadb.c   | 103 +
 .../non-policy/non-overloaded/nds_vfpmadt.c   | 103 +
 .../non-policy/overloaded/nds_vfpmadb.c   | 103 +
 .../non-policy/overloaded/nds_vfpmadt.c   | 103 +
 .../policy/non-overloaded/nds_vfpmadb.c   | 199 ++
 .../policy/non-overloaded/nds_vfpmadt.c   | 199 ++
 .../policy/overloaded/nds_vfpmadb.c   | 199 ++
 .../policy/overloaded/nds_vfpmadt.c   | 199 ++
 18 files changed, 1323 insertions(+), 1 deletion(-)
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/xandesvector/non-policy/non-overloaded/nds_vfpmadb.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/xandesvector/non-policy/non-overloaded/nds_vfpmadt.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/xandesvector/non-policy/overloaded/nds_vfpmadb.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/xandesvector/non-policy/overloaded/nds_vfpmadt.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/xandesvector/policy/non-overloaded/nds_vfpmadb.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/xandesvector/policy/non-overloaded/nds_vfpmadt.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/xandesvector/policy/overloaded/nds_vfpmadb.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/xandesvector/policy/overloaded/nds_vfpmadt.c

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index 2e20eee87902..85783989afbc 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -1528,7 +1528,8 @@ static const riscv_extra_ext_flag_table_t 
riscv_extra_ext_flag_table[] =
   RISCV_EXT_FLAG_ENTRY ("xtheadvector",  x_riscv_isa_flags, MASK_FULL_V),
   RISCV_EXT_FLAG_ENTRY ("xtheadvector",  x_riscv_isa_flags, MASK_VECTOR),
 
-  RISCV_EXT_FLAG_ENTRY ("xandesvbfhcvt", x_riscv_vector_elen_flags, 
MASK_VECTOR_ELEN_BF_16),
+  RISCV_EXT_FLAG_ENTRY ("xandesvbfhcvt",  x_riscv_vector_elen_flags, 
MASK_VECTOR_ELEN_BF_16),
+  RISCV_EXT_FLAG_ENTRY ("xandesvpackfph", x_riscv_vector_elen_flags, 
MASK_VECTOR_ELEN_FP_16),
 
   {NULL, NULL, NULL, 0}
 };
diff --git a/gcc/config/riscv/andes-vector-builtins-bases.cc 
b/gcc/config/riscv/andes-vector-builtins-bases.cc
index 2c19f32225b9..1bf8b9dc088e 100644
--- a/gcc/config/riscv/andes-vector-builtins-bases.cc
+++ b/gcc/config/riscv/andes-vec