[PATCH v1] rs6000: Restore opaque overload variant for correct diagnostics
Hi All,
The following patch has been bootstrapped and regtested on powerpc64le-linux.
After r12-5752-gd08236359eb229, a new bif infrastructure was introduced
which stopped using opaque vector types (e.g. opaque_V4SI_type_node)
for overloaded built-in functions, which led to incorrect and
misleading diagnostics when argument types didn’t exactly match.
This patch reinstates the opaque overload variant for entries with
multiple arguments where at least one is a vector, inserting it
at the beginning of each stanza. This helps recover the intended
fallback behavior and ensures clearer, type-generic error reporting.
2025-05-23 Kishan Parmar
gcc:
PR target/104930
* config/rs6000/rs6000-c.cc (altivec_resolve_overloaded_builtin):
Skip the first overload entry during iteration if it uses opaque type
parameters.
* config/rs6000/rs6000-gen-builtins.cc
(maybe_generate_opaque_variant): New function.
(parse_first_ovld_entry): New function.
(parse_ovld_stanza): call parse_first_ovld_entry.
---
gcc/config/rs6000/rs6000-c.cc| 9 +-
gcc/config/rs6000/rs6000-gen-builtins.cc | 180 ++-
2 files changed, 187 insertions(+), 2 deletions(-)
diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc
index d3b0a566821..6217d585b40 100644
--- a/gcc/config/rs6000/rs6000-c.cc
+++ b/gcc/config/rs6000/rs6000-c.cc
@@ -1972,7 +1972,14 @@ altivec_resolve_overloaded_builtin (location_t loc, tree
fndecl,
arg_i++)
{
tree parmtype = TREE_VALUE (nextparm);
- if (!rs6000_builtin_type_compatible (types[arg_i], parmtype))
+ /* Since we only need opaque vector type for the default
+prototype which is the same as the first instance, we
+only expect to see it in the first instance. */
+ gcc_assert (instance ==
rs6000_overload_info[adj_fcode].first_instance
+ || parmtype != opaque_V4SI_type_node);
+ if ((instance == rs6000_overload_info[adj_fcode].first_instance
+ && parmtype == opaque_V4SI_type_node)
+ || !rs6000_builtin_type_compatible (types[arg_i], parmtype))
{
mismatch = true;
break;
diff --git a/gcc/config/rs6000/rs6000-gen-builtins.cc
b/gcc/config/rs6000/rs6000-gen-builtins.cc
index f77087e0452..d442b93138e 100644
--- a/gcc/config/rs6000/rs6000-gen-builtins.cc
+++ b/gcc/config/rs6000/rs6000-gen-builtins.cc
@@ -353,6 +353,7 @@ struct typeinfo
char isunsigned;
char isbool;
char ispixel;
+ char isopaque;
char ispointer;
basetype base;
restriction restr;
@@ -579,6 +580,7 @@ static typemap type_map[] =
{ "v4sf", "V4SF" },
{ "v4si", "V4SI" },
{ "v8hi", "V8HI" },
+{ "vop4si","opaque_V4SI" },
{ "vp8hi", "pixel_V8HI" },
};
@@ -1058,6 +1060,7 @@ match_type (typeinfo *typedata, int voidok)
vd vector double
v256__vector_pair
v512__vector_quad
+ vop vector opaque
For simplicity, We don't support "short int" and "long long int".
We don't currently support a of "_Float16". "signed"
@@ -1496,6 +1499,12 @@ complete_vector_type (typeinfo *typeptr, char *buf, int
*bufi)
*bufi += 4;
return;
}
+ else if (typeptr->isopaque)
+{
+ memcpy (&buf[*bufi], "op4si", 5);
+ *bufi += 5;
+ return;
+}
switch (typeptr->base)
{
case BT_CHAR:
@@ -1661,7 +1670,8 @@ construct_fntype_id (prototype *protoptr)
buf[bufi++] = '_';
if (argptr->info.isconst
&& argptr->info.base == BT_INT
- && !argptr->info.ispointer)
+ && !argptr->info.ispointer
+ && !argptr->info.isopaque)
{
buf[bufi++] = 'c';
buf[bufi++] = 'i';
@@ -1969,6 +1979,168 @@ create_bif_order (void)
rbt_inorder_callback (&bifo_rbt, bifo_rbt.rbt_root, set_bif_order);
}
+/* Attempt to generate an opaque variant if needed and valid. */
+static void
+maybe_generate_opaque_variant (ovlddata* entry)
+{
+ /* If no vector arg, no need to create opaque variant. */
+ bool has_vector_arg = false;
+ for (typelist* arg = entry->proto.args; arg; arg = arg->next)
+{
+ if (arg->info.isvector)
+ {
+ has_vector_arg = true;
+ break;
+ }
+}
+
+ if (!has_vector_arg || entry->proto.nargs <= 1)
+return;
+
+ /* Construct the opaque variant. */
+ ovlddata* opaque_entry = &ovlds[curr_ovld];
+ memcpy (opaque_entry, entry, sizeof (*entry));
+
+ /* Deep-co
[COMMITTED] MAINTAINERS: Add myself to write after approval
2025-05-22 Kishan Parmar * MAINTAINERS: Add myself to write after approval. --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index 8993d176c22..ac7e4de112e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -717,6 +717,7 @@ Maxim Ostapenko chefmax Jeevitha Palanisamy jeevitha Patrick Palka ppalka Seongbae Park spark +Kishan Parmar kishan Srinath Parvathanenisripar01 Devang Pateldpatel Andris Pavenis andris -- 2.43.5
[PATCH v1] rs6000: Restore opaque overload variant for correct diagnostics
Hi All,
The following patch has been bootstrapped and regtested on powerpc64le-linux.
After r12-5752-gd08236359eb229, a new bif infrastructure was introduced
which stopped using opaque vector types (e.g. opaque_V4SI_type_node)
for overloaded built-in functions, which led to incorrect and
misleading diagnostics when argument types didn’t exactly match.
This patch reinstates the opaque overload variant for entries with
multiple arguments where at least one is a vector, inserting it
at the beginning of each stanza. This helps recover the intended
fallback behavior and ensures clearer, type-generic error reporting.
2025-05-23 Kishan Parmar
gcc:
PR target/104930
* config/rs6000/rs6000-c.cc (altivec_resolve_overloaded_builtin):
Skip the first overload entry during iteration if it uses opaque type
parameters.
* config/rs6000/rs6000-gen-builtins.cc
(maybe_generate_opaque_variant): New function.
(parse_first_ovld_entry): New function.
(parse_ovld_stanza): call parse_first_ovld_entry.
---
gcc/config/rs6000/rs6000-c.cc| 9 +-
gcc/config/rs6000/rs6000-gen-builtins.cc | 180 ++-
2 files changed, 187 insertions(+), 2 deletions(-)
diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc
index d3b0a566821..6217d585b40 100644
--- a/gcc/config/rs6000/rs6000-c.cc
+++ b/gcc/config/rs6000/rs6000-c.cc
@@ -1972,7 +1972,14 @@ altivec_resolve_overloaded_builtin (location_t loc, tree
fndecl,
arg_i++)
{
tree parmtype = TREE_VALUE (nextparm);
- if (!rs6000_builtin_type_compatible (types[arg_i], parmtype))
+ /* Since we only need opaque vector type for the default
+prototype which is the same as the first instance, we
+only expect to see it in the first instance. */
+ gcc_assert (instance ==
rs6000_overload_info[adj_fcode].first_instance
+ || parmtype != opaque_V4SI_type_node);
+ if ((instance == rs6000_overload_info[adj_fcode].first_instance
+ && parmtype == opaque_V4SI_type_node)
+ || !rs6000_builtin_type_compatible (types[arg_i], parmtype))
{
mismatch = true;
break;
diff --git a/gcc/config/rs6000/rs6000-gen-builtins.cc
b/gcc/config/rs6000/rs6000-gen-builtins.cc
index f77087e0452..d442b93138e 100644
--- a/gcc/config/rs6000/rs6000-gen-builtins.cc
+++ b/gcc/config/rs6000/rs6000-gen-builtins.cc
@@ -353,6 +353,7 @@ struct typeinfo
char isunsigned;
char isbool;
char ispixel;
+ char isopaque;
char ispointer;
basetype base;
restriction restr;
@@ -579,6 +580,7 @@ static typemap type_map[] =
{ "v4sf", "V4SF" },
{ "v4si", "V4SI" },
{ "v8hi", "V8HI" },
+{ "vop4si","opaque_V4SI" },
{ "vp8hi", "pixel_V8HI" },
};
@@ -1058,6 +1060,7 @@ match_type (typeinfo *typedata, int voidok)
vd vector double
v256__vector_pair
v512__vector_quad
+ vop vector opaque
For simplicity, We don't support "short int" and "long long int".
We don't currently support a of "_Float16". "signed"
@@ -1496,6 +1499,12 @@ complete_vector_type (typeinfo *typeptr, char *buf, int
*bufi)
*bufi += 4;
return;
}
+ else if (typeptr->isopaque)
+{
+ memcpy (&buf[*bufi], "op4si", 5);
+ *bufi += 5;
+ return;
+}
switch (typeptr->base)
{
case BT_CHAR:
@@ -1661,7 +1670,8 @@ construct_fntype_id (prototype *protoptr)
buf[bufi++] = '_';
if (argptr->info.isconst
&& argptr->info.base == BT_INT
- && !argptr->info.ispointer)
+ && !argptr->info.ispointer
+ && !argptr->info.isopaque)
{
buf[bufi++] = 'c';
buf[bufi++] = 'i';
@@ -1969,6 +1979,168 @@ create_bif_order (void)
rbt_inorder_callback (&bifo_rbt, bifo_rbt.rbt_root, set_bif_order);
}
+/* Attempt to generate an opaque variant if needed and valid. */
+static void
+maybe_generate_opaque_variant (ovlddata* entry)
+{
+ /* If no vector arg, no need to create opaque variant. */
+ bool has_vector_arg = false;
+ for (typelist* arg = entry->proto.args; arg; arg = arg->next)
+{
+ if (arg->info.isvector)
+ {
+ has_vector_arg = true;
+ break;
+ }
+}
+
+ if (!has_vector_arg || entry->proto.nargs <= 1)
+return;
+
+ /* Construct the opaque variant. */
+ ovlddata* opaque_entry = &ovlds[curr_ovld];
+ memcpy (opaque_entry, entry, sizeof (*entry));
+
+ /* Deep-co
[PATCH v1] rs6000: Fix UBSAN runtime errors for powerpc64le-unknown-linux-gnu
Hi All,
The following patch has been bootstrapped and regtested on powerpc64le-linux.
While building GCC with --with-build-config=bootstrap-ubsan on
powerpc64le-unknown-linux-gnu, multiple UBSAN runtime errors were
encountered in rs6000.cc and rs6000.md due to undefined behavior
involving left shifts on negative values and shift exponents equal to
or exceeding the type width.
The issue was in bit pattern recognition code
(in can_be_rotated_to_negative_lis and can_be_built_by_li_and_rldic),
where signed values were shifted without handling negative inputs or
guarding against shift counts equal to the type width, causing UB.
The fix ensures shifts and rotations are done unsigned HOST_WIDE_INT,
and casting back only where needed (like for arithmetic right shifts)
with proper guards to prevent shift-by-64.
2025-06-26 Kishan Parmar
gcc:
PR target/118890
* config/rs6000/rs6000.cc (can_be_rotated_to_negative_lis):
Avoid left shift of negative value and guard shift count.
(can_be_built_by_li_and_rldic): Likewise.
(rs6000_emit_set_long_const): Likewise.
* config/rs6000/rs6000.md : Avoid signed overflow.
---
gcc/config/rs6000/rs6000.cc | 24 ++--
gcc/config/rs6000/rs6000.md | 4 +++-
2 files changed, 17 insertions(+), 11 deletions(-)
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 7ee26e52b13..e7e30fa95ba 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -10309,15 +10309,18 @@ can_be_rotated_to_negative_lis (HOST_WIDE_INT c, int
*rot)
/* case b. xx0..01..1xx: some of 15 x's (and some of 16 0's) are
rotated over the highest bit. */
- int pos_one = clz_hwi ((c << 16) >> 16);
- middle_zeros = ctz_hwi (c >> (HOST_BITS_PER_WIDE_INT - pos_one));
- int middle_ones = clz_hwi (~(c << pos_one));
- if (middle_zeros >= 16 && middle_ones >= 33)
+ unsigned HOST_WIDE_INT uc = (unsigned HOST_WIDE_INT)c;
+ int pos_one = clz_hwi ((HOST_WIDE_INT)(uc << 16) >> 16);
+ if (pos_one != 0)
{
- *rot = pos_one;
- return true;
+ middle_zeros = ctz_hwi (c >> (HOST_BITS_PER_WIDE_INT - pos_one));
+ int middle_ones = clz_hwi (~(uc << pos_one));
+ if (middle_zeros >= 16 && middle_ones >= 33)
+ {
+ *rot = pos_one;
+ return true;
+ }
}
-
return false;
}
@@ -10434,7 +10437,7 @@ can_be_built_by_li_and_rldic (HOST_WIDE_INT c, int
*shift, HOST_WIDE_INT *mask)
if (lz >= HOST_BITS_PER_WIDE_INT)
return false;
- int middle_ones = clz_hwi (~(c << lz));
+ int middle_ones = clz_hwi (~(((unsigned HOST_WIDE_INT)c) << lz));
if (tz + lz + middle_ones >= ones
&& (tz - lz) < HOST_BITS_PER_WIDE_INT
&& tz < HOST_BITS_PER_WIDE_INT)
@@ -10468,7 +10471,7 @@ can_be_built_by_li_and_rldic (HOST_WIDE_INT c, int
*shift, HOST_WIDE_INT *mask)
if (!IN_RANGE (pos_first_1, 1, HOST_BITS_PER_WIDE_INT-1))
return false;
- middle_ones = clz_hwi (~c << pos_first_1);
+ middle_ones = clz_hwi ((~(unsigned HOST_WIDE_INT)c) << pos_first_1);
middle_zeros = ctz_hwi (c >> (HOST_BITS_PER_WIDE_INT - pos_first_1));
if (pos_first_1 < HOST_BITS_PER_WIDE_INT
&& middle_ones + middle_zeros < HOST_BITS_PER_WIDE_INT
@@ -10570,7 +10573,8 @@ rs6000_emit_set_long_const (rtx dest, HOST_WIDE_INT c,
int *num_insns)
{
/* li/lis; rldicX */
unsigned HOST_WIDE_INT imm = (c | ~mask);
- imm = (imm >> shift) | (imm << (HOST_BITS_PER_WIDE_INT - shift));
+ if (shift != 0)
+ imm = (imm >> shift) | (imm << (HOST_BITS_PER_WIDE_INT - shift));
count_or_emit_insn (temp, GEN_INT (imm));
if (shift != 0)
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 9c718ca2a22..8fc079a4297 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -1971,7 +1971,9 @@
{
HOST_WIDE_INT val = INTVAL (operands[2]);
HOST_WIDE_INT low = sext_hwi (val, 16);
- HOST_WIDE_INT rest = trunc_int_for_mode (val - low, mode);
+ /* Avoid signed overflow by computing difference in unsigned domain. */
+ unsigned HOST_WIDE_INT urest = (unsigned HOST_WIDE_INT)val - (unsigned
HOST_WIDE_INT)low;
+ HOST_WIDE_INT rest = trunc_int_for_mode (urest, mode);
operands[4] = GEN_INT (low);
if (mode == SImode || satisfies_constraint_L (GEN_INT (rest)))
--
2.43.5
Re: [PATCH v1] rs6000: Restore opaque overload variant for correct diagnostics
Ping!
please review.
Thanks & Regards
Kishan
On 05/06/25 12:36 pm, Kishan Parmar wrote:
> Hi All,
>
> The following patch has been bootstrapped and regtested on powerpc64le-linux.
>
> After r12-5752-gd08236359eb229, a new bif infrastructure was introduced
> which stopped using opaque vector types (e.g. opaque_V4SI_type_node)
> for overloaded built-in functions, which led to incorrect and
> misleading diagnostics when argument types didn’t exactly match.
>
> This patch reinstates the opaque overload variant for entries with
> multiple arguments where at least one is a vector, inserting it
> at the beginning of each stanza. This helps recover the intended
> fallback behavior and ensures clearer, type-generic error reporting.
>
> 2025-05-23 Kishan Parmar
>
> gcc:
> PR target/104930
> * config/rs6000/rs6000-c.cc (altivec_resolve_overloaded_builtin):
> Skip the first overload entry during iteration if it uses opaque type
> parameters.
> * config/rs6000/rs6000-gen-builtins.cc
> (maybe_generate_opaque_variant): New function.
> (parse_first_ovld_entry): New function.
> (parse_ovld_stanza): call parse_first_ovld_entry.
> ---
> gcc/config/rs6000/rs6000-c.cc| 9 +-
> gcc/config/rs6000/rs6000-gen-builtins.cc | 180 ++-
> 2 files changed, 187 insertions(+), 2 deletions(-)
>
> diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc
> index d3b0a566821..6217d585b40 100644
> --- a/gcc/config/rs6000/rs6000-c.cc
> +++ b/gcc/config/rs6000/rs6000-c.cc
> @@ -1972,7 +1972,14 @@ altivec_resolve_overloaded_builtin (location_t loc,
> tree fndecl,
> arg_i++)
> {
> tree parmtype = TREE_VALUE (nextparm);
> - if (!rs6000_builtin_type_compatible (types[arg_i], parmtype))
> + /* Since we only need opaque vector type for the default
> + prototype which is the same as the first instance, we
> + only expect to see it in the first instance. */
> + gcc_assert (instance ==
> rs6000_overload_info[adj_fcode].first_instance
> + || parmtype != opaque_V4SI_type_node);
> + if ((instance == rs6000_overload_info[adj_fcode].first_instance
> +&& parmtype == opaque_V4SI_type_node)
> + || !rs6000_builtin_type_compatible (types[arg_i], parmtype))
> {
> mismatch = true;
> break;
> diff --git a/gcc/config/rs6000/rs6000-gen-builtins.cc
> b/gcc/config/rs6000/rs6000-gen-builtins.cc
> index f77087e0452..d442b93138e 100644
> --- a/gcc/config/rs6000/rs6000-gen-builtins.cc
> +++ b/gcc/config/rs6000/rs6000-gen-builtins.cc
> @@ -353,6 +353,7 @@ struct typeinfo
>char isunsigned;
>char isbool;
>char ispixel;
> + char isopaque;
>char ispointer;
>basetype base;
>restriction restr;
> @@ -579,6 +580,7 @@ static typemap type_map[] =
> { "v4sf","V4SF" },
> { "v4si","V4SI" },
> { "v8hi","V8HI" },
> +{ "vop4si", "opaque_V4SI" },
> { "vp8hi", "pixel_V8HI" },
>};
>
> @@ -1058,6 +1060,7 @@ match_type (typeinfo *typedata, int voidok)
> vdvector double
> v256 __vector_pair
> v512 __vector_quad
> + vop vector opaque
>
> For simplicity, We don't support "short int" and "long long int".
> We don't currently support a of "_Float16". "signed"
> @@ -1496,6 +1499,12 @@ complete_vector_type (typeinfo *typeptr, char *buf,
> int *bufi)
>*bufi += 4;
>return;
> }
> + else if (typeptr->isopaque)
> +{
> + memcpy (&buf[*bufi], "op4si", 5);
> + *bufi += 5;
> + return;
> +}
>switch (typeptr->base)
> {
> case BT_CHAR:
> @@ -1661,7 +1670,8 @@ construct_fntype_id (prototype *protoptr)
> buf[bufi++] = '_';
> if (argptr->info.isconst
> && argptr->info.base == BT_INT
> - && !argptr->info.ispointer)
> + && !argptr->info.ispointer
> + && !argptr->info.isopaque)
> {
> buf[bufi++] = 'c';
> buf[bufi++] = 'i';
> @@ -1969,6 +1979,168 @@ create_bif_order (void)
>rbt_inorder_callback (&bifo_rbt, bifo_rbt.rbt_root, set_bif_order);
> }
>
> +/* Attempt to generate an opaque variant if n
Re: [PATCH v1] rs6000: Fix UBSAN runtime errors for powerpc64le-unknown-linux-gnu
Ping!
Please review.
Thanks & Regards,
Kishan
On 26/06/25 1:26 pm, Kishan Parmar wrote:
> Hi All,
>
> The following patch has been bootstrapped and regtested on powerpc64le-linux.
>
> While building GCC with --with-build-config=bootstrap-ubsan on
> powerpc64le-unknown-linux-gnu, multiple UBSAN runtime errors were
> encountered in rs6000.cc and rs6000.md due to undefined behavior
> involving left shifts on negative values and shift exponents equal to
> or exceeding the type width.
>
> The issue was in bit pattern recognition code
> (in can_be_rotated_to_negative_lis and can_be_built_by_li_and_rldic),
> where signed values were shifted without handling negative inputs or
> guarding against shift counts equal to the type width, causing UB.
> The fix ensures shifts and rotations are done unsigned HOST_WIDE_INT,
> and casting back only where needed (like for arithmetic right shifts)
> with proper guards to prevent shift-by-64.
>
> 2025-06-26 Kishan Parmar
>
> gcc:
> PR target/118890
> * config/rs6000/rs6000.cc (can_be_rotated_to_negative_lis):
> Avoid left shift of negative value and guard shift count.
> (can_be_built_by_li_and_rldic): Likewise.
> (rs6000_emit_set_long_const): Likewise.
> * config/rs6000/rs6000.md : Avoid signed overflow.
> ---
> gcc/config/rs6000/rs6000.cc | 24 ++--
> gcc/config/rs6000/rs6000.md | 4 +++-
> 2 files changed, 17 insertions(+), 11 deletions(-)
>
> diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
> index 7ee26e52b13..e7e30fa95ba 100644
> --- a/gcc/config/rs6000/rs6000.cc
> +++ b/gcc/config/rs6000/rs6000.cc
> @@ -10309,15 +10309,18 @@ can_be_rotated_to_negative_lis (HOST_WIDE_INT c,
> int *rot)
>
>/* case b. xx0..01..1xx: some of 15 x's (and some of 16 0's) are
> rotated over the highest bit. */
> - int pos_one = clz_hwi ((c << 16) >> 16);
> - middle_zeros = ctz_hwi (c >> (HOST_BITS_PER_WIDE_INT - pos_one));
> - int middle_ones = clz_hwi (~(c << pos_one));
> - if (middle_zeros >= 16 && middle_ones >= 33)
> + unsigned HOST_WIDE_INT uc = (unsigned HOST_WIDE_INT)c;
> + int pos_one = clz_hwi ((HOST_WIDE_INT)(uc << 16) >> 16);
> + if (pos_one != 0)
> {
> - *rot = pos_one;
> - return true;
> + middle_zeros = ctz_hwi (c >> (HOST_BITS_PER_WIDE_INT - pos_one));
> + int middle_ones = clz_hwi (~(uc << pos_one));
> + if (middle_zeros >= 16 && middle_ones >= 33)
> + {
> + *rot = pos_one;
> + return true;
> + }
> }
> -
>return false;
> }
>
> @@ -10434,7 +10437,7 @@ can_be_built_by_li_and_rldic (HOST_WIDE_INT c, int
> *shift, HOST_WIDE_INT *mask)
>if (lz >= HOST_BITS_PER_WIDE_INT)
> return false;
>
> - int middle_ones = clz_hwi (~(c << lz));
> + int middle_ones = clz_hwi (~(((unsigned HOST_WIDE_INT)c) << lz));
>if (tz + lz + middle_ones >= ones
>&& (tz - lz) < HOST_BITS_PER_WIDE_INT
>&& tz < HOST_BITS_PER_WIDE_INT)
> @@ -10468,7 +10471,7 @@ can_be_built_by_li_and_rldic (HOST_WIDE_INT c, int
> *shift, HOST_WIDE_INT *mask)
>if (!IN_RANGE (pos_first_1, 1, HOST_BITS_PER_WIDE_INT-1))
> return false;
>
> - middle_ones = clz_hwi (~c << pos_first_1);
> + middle_ones = clz_hwi ((~(unsigned HOST_WIDE_INT)c) << pos_first_1);
>middle_zeros = ctz_hwi (c >> (HOST_BITS_PER_WIDE_INT - pos_first_1));
>if (pos_first_1 < HOST_BITS_PER_WIDE_INT
>&& middle_ones + middle_zeros < HOST_BITS_PER_WIDE_INT
> @@ -10570,7 +10573,8 @@ rs6000_emit_set_long_const (rtx dest, HOST_WIDE_INT
> c, int *num_insns)
> {
>/* li/lis; rldicX */
>unsigned HOST_WIDE_INT imm = (c | ~mask);
> - imm = (imm >> shift) | (imm << (HOST_BITS_PER_WIDE_INT - shift));
> + if (shift != 0)
> + imm = (imm >> shift) | (imm << (HOST_BITS_PER_WIDE_INT - shift));
>
>count_or_emit_insn (temp, GEN_INT (imm));
>if (shift != 0)
> diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
> index 9c718ca2a22..8fc079a4297 100644
> --- a/gcc/config/rs6000/rs6000.md
> +++ b/gcc/config/rs6000/rs6000.md
> @@ -1971,7 +1971,9 @@
> {
>HOST_WIDE_INT val = INTVAL (operands[2]);
>HOST_WIDE_INT low = sext_hwi (val, 16);
> - HOST_WIDE_INT rest = trunc_int_for_mode (val - low, mode);
> + /* Avoid signed overflow by computing difference in unsigned domain. */
> + unsigned HOST_WIDE_INT urest = (unsigned HOST_WIDE_INT)val - (unsigned
> HOST_WIDE_INT)low;
> + HOST_WIDE_INT rest = trunc_int_for_mode (urest, mode);
>
>operands[4] = GEN_INT (low);
>if (mode == SImode || satisfies_constraint_L (GEN_INT (rest)))
[PATCH] rs6000: Backport r15-2928-gbf891fcabca7a5 to gcc-14
I would like to backport patch r15-2928-gbf891fcabca7a5 which is
available from GCC-15.
In general, if -mcpu=power9, float128 hardware is available, but in the
case the user explicitly does -mno-float128-hardware or runs on a machine
that doesn't enable float128 by default (i.e. big endian Linux and AIX),
you don't want these insns to be generated.
Applyig r15-2928-gbf891fcabca7a5 causes 3 hunks and below is the rejected diff,
Because three patterns modified by the patch, "isinf2", "*xststdc_"
and xststdc_ are not present in the GCC 14 source code. As these patterns
were introduced to the master branch after the GCC 14 release.
--- gcc/config/rs6000/vsx.md
+++ gcc/config/rs6000/vsx.md
@@ -5353,18 +5353,20 @@
(match_dup 4)))
(set (match_operand:SI 0 "register_operand" "=r")
(eq:SI (match_dup 3)
(const_int 0)))]
- "TARGET_P9_VECTOR"
+ "TARGET_P9_VECTOR
+ && (!FLOAT128_IEEE_P (mode) || TARGET_FLOAT128_HW)"
{
operands[3] = gen_reg_rtx (CCFPmode);
operands[4] = CONST0_RTX (SImode);
})
(define_expand "isinf2"
[(use (match_operand:SI 0 "gpc_reg_operand"))
(use (match_operand:IEEE_FP 1 ""))]
- "TARGET_HARD_FLOAT && TARGET_P9_VECTOR"
+ "TARGET_P9_VECTOR
+ && (!FLOAT128_IEEE_P (mode) || TARGET_FLOAT128_HW)"
{
int mask = VSX_TEST_DATA_CLASS_POS_INF | VSX_TEST_DATA_CLASS_NEG_INF;
emit_insn (gen_xststdc_ (operands[0], operands[1], GEN_INT (mask)));
DONE;
@@ -5445,9 +5447,10 @@
[(match_operand:IEEE_FP 1 "" "")
(match_operand:SI 2 "u7bit_cint_operand" "n")]
UNSPEC_VSX_STSTDC)
(const_int 0)))]
- "TARGET_P9_VECTOR"
+ "TARGET_P9_VECTOR
+ && (!FLOAT128_IEEE_P (mode) || TARGET_FLOAT128_HW)"
"xststdcp %0,%1,%2"
[(set_attr "type" "fpcompare")])
;; VSX Vector Extract Exponent Double and Single Precision
I’ve just resolved the conflicts and Bootstrapped/regtested on 14 branch on
Powerpc64 BE/LE and it does not cause any regressions. Updated patch is below.
Ok for 14 branch?
Kishan
commit bf891fcabca7a59ce71e85c8f2eea2bfabbffe59
Author: Haochen Gui
Date: Thu Aug 15 13:45:35 2024 +0800
rs6000: Add TARGET_FLOAT128_HW guard for quad-precision insns
gcc/
* config/rs6000/rs6000.md (floatti2, floatunsti2,
fix_truncti2): Add guard TARGET_FLOAT128_HW.
* config/rs6000/vsx.md (xsxexpqp__,
xsxsigqp__, xsiexpqpf_,
xsiexpqp__, xscmpexpqp__,
*xscmpexpqp, xststdcnegqp_): Replace guard TARGET_P9_VECTOR
with TARGET_FLOAT128_HW.
gcc/testsuite/
* gcc.target/powerpc/float128-cmp2-runnable.c: Replace
ppc_float128_sw with ppc_float128_hw and remove p9vector_hw.
---
gcc/config/rs6000/rs6000.md| 6 +++---
gcc/config/rs6000/vsx.md | 14 +++---
.../gcc.target/powerpc/float128-cmp2-runnable.c| 3 +--
3 files changed, 11 insertions(+), 12 deletions(-)
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 74b87f926d7..bbbd7041a19 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -6897,7 +6897,7 @@
(define_insn "floatti2"
[(set (match_operand:IEEE128 0 "vsx_register_operand" "=v")
(float:IEEE128 (match_operand:TI 1 "vsx_register_operand" "v")))]
- "TARGET_POWER10"
+ "TARGET_POWER10 && TARGET_FLOAT128_HW"
{
return "xscvsqqp %0,%1";
}
@@ -6906,7 +6906,7 @@
(define_insn "floatunsti2"
[(set (match_operand:IEEE128 0 "vsx_register_operand" "=v")
(unsigned_float:IEEE128 (match_operand:TI 1 "vsx_register_operand"
"v")))]
- "TARGET_POWER10"
+ "TARGET_POWER10 && TARGET_FLOAT128_HW"
{
return "xscvuqqp %0,%1";
}
@@ -6915,7 +6915,7 @@
(define_insn "fix_truncti2"
[(set (match_operand:TI 0 "vsx_register_operand" "=v")
(fix:TI (match_operand:IEEE128 1 "vsx_register_operand" "v")))]
- "TARGET_POWER10"
+ "TARGET_POWER10 && TARGET_FLOAT128_HW"
{
return "xscvqpsqz %0,%1";
}
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 7a9c19ac903..8665ee7f6df 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -5132,7 +5132,7 @@
(unspec:V2DI_DI
[(match_operand:IEEE128 1 "altivec_register_operand" "v")]
UNSPEC_VSX_SXEXPDP))]
- "TARGET_P9_VECTOR"
+ "TARGET_FLOAT128_HW"
"xsxexpqp %0,%1"
[(set_attr "type" "vecmove")])
@@ -5151,7 +5151,7 @@
(unspec:VEC_TI [(match_operand:IEEE128 1
"altivec_register_operand" "v")]
UNSPEC_VSX_SXSIG))]
- "TARGET_P9_VECTOR"
+ "TARGET_FLOAT128_HW"
"xsxsigqp %0,%1"
[(set_attr "type" "vecmove")])
@@ -5171,7 +5171,7 @@
[(match_operand:IEEE128 1 "altivec_register_operand" "v")
(match_operand:DI 2 "altivec_register_operand" "v")]
UNSPEC_VSX_SIEXPQP))]
- "TARGET_P9_VECTOR"
+ "TARGET_FLOAT128_HW"
"xsiexpqp %0,%1,%2"
[(set_attr "type" "vecmove")])
@@ -5183,7 +5183,7 @@
(match_operand:V2DI_DI 2
Re: [PATCH] rs6000: Backport r15-2928-gbf891fcabca7a5 to gcc-14
On 18/07/25 2:09 am, Segher Boessenkool wrote: > So, how do you resolve it in this backport, simply leaving out those > hunks? > > If so: okay for 14. You don't want to backport further, right? More > stuff becomes missing :-) Yes, We need to ignore those patterns in this backport! Thanks, Kishan
