[PATCH] riscv: Fix incorrect gnu property alignment on rv32

[Jesse Huang]

Codegen is incorrectly emitting a ".p2align 3" that coerces the
alignment of the .note.gnu.property section from 4 to 8 on rv32.
---
 gcc/config/riscv/riscv.cc  |  2 +-
 gcc/testsuite/gcc.target/riscv/gnu-property-rv32.c | 12 
 gcc/testsuite/gcc.target/riscv/gnu-property-rv64.c | 12 
 3 files changed, 25 insertions(+), 1 deletion(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/gnu-property-rv32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/gnu-property-rv64.c

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 38f3ae7cd84..d3656a7a430 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -10382,7 +10382,7 @@ riscv_file_end ()
   fprintf (asm_out_file, "1:\n");
 
   /* pr_type.  */
-  fprintf (asm_out_file, "\t.p2align\t3\n");
+  fprintf (asm_out_file, "\t.p2align\t%u\n", p2align);
   fprintf (asm_out_file, "2:\n");
   fprintf (asm_out_file, "\t.long\t0xc000\n");
   /* pr_datasz.  */
diff --git a/gcc/testsuite/gcc.target/riscv/gnu-property-rv32.c 
b/gcc/testsuite/gcc.target/riscv/gnu-property-rv32.c
new file mode 100644
index 000..d0c01d8cb99
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/gnu-property-rv32.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32g_zicfiss -fcf-protection=return -mabi=ilp32d " { 
target { rv32 } } } */
+/* { dg-options "-march=rv32gc_zicfiss -fcf-protection=return -mabi=ilp32d " { 
target { rv32 } } } */
+/* { dg-options "-march=rv32g_zicfilp -fcf-protection=branch -mabi=ilp32d " { 
target { rv32 } } } */
+/* { dg-options "-march=rv32gc_zicfilp -fcf-protection=branch -mabi=ilp32d " { 
target { rv32 } } } */
+/* { dg-options "-march=rv32g_zicfiss_zicfilp -fcf-protection=full 
-mabi=ilp32d " { target { rv32 } } } */
+/* { dg-options "-march=rv32gc_zicfiss_zicfilp -fcf-protection=full 
-mabi=ilp32d " { target { rv32 } } } */
+
+void foo() {}
+
+/* { dg-final { scan-assembler-times ".p2align\t2" 3 } } */
+/* { dg-final { scan-assembler-not ".p2align\t3" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/gnu-property-rv64.c 
b/gcc/testsuite/gcc.target/riscv/gnu-property-rv64.c
new file mode 100644
index 000..25847ba410a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/gnu-property-rv64.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64g_zicfiss -fcf-protection=return -mabi=lp64d " { 
target { rv64 } } } */
+/* { dg-options "-march=rv64gc_zicfiss -fcf-protection=return -mabi=lp64d " { 
target { rv64 } } } */
+/* { dg-options "-march=rv64g_zicfilp -fcf-protection=branch -mabi=lp64d " { 
target { rv64 } } } */
+/* { dg-options "-march=rv64gc_zicfilp -fcf-protection=branch -mabi=lp64d " { 
target { rv64 } } } */
+/* { dg-options "-march=rv64g_zicfiss_zicfilp -fcf-protection=full -mabi=lp64d 
" { target { rv64 } } } */
+/* { dg-options "-march=rv64gc_zicfiss_zicfilp -fcf-protection=full 
-mabi=lp64d " { target { rv64 } } } */
+
+void foo() {}
+
+/* { dg-final { scan-assembler-times ".p2align\t3" 3 } } */
+/* { dg-final { scan-assembler-not ".p2align\t2" } } */
-- 
2.39.3

[PATCH v2] riscv: Fix incorrect gnu property alignment on rv32

[Jesse Huang]

Codegen is incorrectly emitting a ".p2align 3" that coerces the
alignment of the .note.gnu.property section from 4 to 8 on rv32.

2025-04-11  Jesse Huang  

gcc/ChangeLog

* config/riscv/riscv.cc (riscv_file_end): Fix .p2align value.

gcc/testsuite/ChangeLog

* gcc.target/riscv/gnu-property-align-rv32.c: New file.
* gcc.target/riscv/gnu-property-align-rv64.c: New file.
---
 gcc/config/riscv/riscv.cc| 2 +-
 gcc/testsuite/gcc.target/riscv/gnu-property-align-rv32.c | 7 +++
 gcc/testsuite/gcc.target/riscv/gnu-property-align-rv64.c | 7 +++
 3 files changed, 15 insertions(+), 1 deletion(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/gnu-property-align-rv32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/gnu-property-align-rv64.c

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 38f3ae7cd84..d3656a7a430 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -10382,7 +10382,7 @@ riscv_file_end ()
   fprintf (asm_out_file, "1:\n");
 
   /* pr_type.  */
-  fprintf (asm_out_file, "\t.p2align\t3\n");
+  fprintf (asm_out_file, "\t.p2align\t%u\n", p2align);
   fprintf (asm_out_file, "2:\n");
   fprintf (asm_out_file, "\t.long\t0xc000\n");
   /* pr_datasz.  */
diff --git a/gcc/testsuite/gcc.target/riscv/gnu-property-align-rv32.c 
b/gcc/testsuite/gcc.target/riscv/gnu-property-align-rv32.c
new file mode 100644
index 000..4f48cff33da
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/gnu-property-align-rv32.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32g_zicfiss -fcf-protection=return -mabi=ilp32d " } 
*/
+
+void foo() {}
+
+/* { dg-final { scan-assembler-times ".p2align\t2" 3 } } */
+/* { dg-final { scan-assembler-not ".p2align\t3" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/gnu-property-align-rv64.c 
b/gcc/testsuite/gcc.target/riscv/gnu-property-align-rv64.c
new file mode 100644
index 000..1bfd1271826
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/gnu-property-align-rv64.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64g_zicfiss -fcf-protection=return -mabi=lp64d " } */
+
+void foo() {}
+
+/* { dg-final { scan-assembler-times ".p2align\t3" 3 } } */
+/* { dg-final { scan-assembler-not ".p2align\t2" } } */
-- 
2.39.3