[PATCH] Add --disable-tm-clone-registry libgcc configure option.

[ilia . diachkov]

Hello,

This patch adds libgcc configuration option to disable TM clone 
registry. This option helps to reduce code size for embedded targets 
which do not need transactional memory support.


Tested on x86_64 and riscv64-unknown-elf-gcc, the last is with the 
option enabled.


If the change is Ok with you, please commit it since I have no write 
access to gcc repository.


Best regards,
Ilia.

libgcc/ChangeLog:

* Makefile.in: Add @use_tm_clone_registry@.
* configure: Regenerate.
* configure.ac: Add --disable-tm-clone-registry option.

gcc/ChangeLog:

* doc/install.texi: Document --disable-tm-clone-registry.

diff --git a/gcc/doc/install.texi b/gcc/doc/install.texi
index 29d0470..1a0e8c7 100644
--- a/gcc/doc/install.texi
+++ b/gcc/doc/install.texi
@@ -1284,6 +1284,11 @@ assumptions made by the configure test are incorrect.
 Specify that the target does not support TLS.
 This is an alias for @option{--enable-tls=no}.
 
+@item --disable-tm-clone-registry
+Disable TM clone registry in libgcc. It is enabled in libgcc by default.
+This option helps to reduce code size for embedded targets which do
+not use transactional memory.
+
 @item --with-cpu=@var{cpu}
 @itemx --with-cpu-32=@var{cpu}
 @itemx --with-cpu-64=@var{cpu}
diff --git a/libgcc/Makefile.in b/libgcc/Makefile.in
index fb77881..189f9ff 100644
--- a/libgcc/Makefile.in
+++ b/libgcc/Makefile.in
@@ -259,6 +259,8 @@ PICFLAG = @PICFLAG@
 
 CET_FLAGS = @CET_FLAGS@
 
+USE_TM_CLONE_REGISTRY = @use_tm_clone_registry@
+
 # Defined in libgcc2.c, included only in the static library.
 LIB2FUNCS_ST = _eprintf __gcc_bcmp
 
@@ -299,7 +301,7 @@ CRTSTUFF_CFLAGS = -O2 $(GCC_CFLAGS) $(INCLUDES) $(MULTILIB_CFLAGS) -g0 \
   $(NO_PIE_CFLAGS) -finhibit-size-directive -fno-inline -fno-exceptions \
   -fno-zero-initialized-in-bss -fno-toplevel-reorder -fno-tree-vectorize \
   -fbuilding-libgcc -fno-stack-protector $(FORCE_EXPLICIT_EH_REGISTRY) \
-  $(INHIBIT_LIBC_CFLAGS)
+  $(INHIBIT_LIBC_CFLAGS) $(USE_TM_CLONE_REGISTRY)
 
 # Extra flags to use when compiling crt{begin,end}.o.
 CRTSTUFF_T_CFLAGS =
diff --git a/libgcc/configure.ac b/libgcc/configure.ac
index 5f11455..b1b90d2 100644
--- a/libgcc/configure.ac
+++ b/libgcc/configure.ac
@@ -261,6 +261,16 @@ fi
 ])
 AC_SUBST([force_explicit_eh_registry])
 
+AC_ARG_ENABLE([tm-clone-registry],
+[  --disable-tm-clone-registrydisable TM clone registry],
+[
+use_tm_clone_registry=
+if test "$enable_tm_clone_registry" = no; then
+  use_tm_clone_registry=-DUSE_TM_CLONE_REGISTRY=0
+fi
+])
+AC_SUBST([use_tm_clone_registry])
+
 AC_LIB_PROG_LD_GNU
 
 AC_MSG_CHECKING([for thread model used by GCC])

[PATCH] RISC-V: Add -malign-data= option.

[Ilia Diachkov]

Hello,

This patch adds new machine specific option -malign-data={word,abi} to 
RISC-V port. The option switches alignment of  global variables and 
constants of array/record/union types. The default value 
(-malign-data=word) keeps existing way of alignment computation. Another 
option value (-malign-data=abi) makes data natural alignment. It avoids 
extra spaces between data to reduce code size. The measured code size 
reduction is about 0.4% at -Os on EEMBC automotive 1.1 tests and 
SPEC2006 C/C++ benchmarks. The patch was tested in riscv-gnu-toolchain 
by dejagnu.


Please check the patch into the trunk.

Best regards,
Ilia.

gcc/
* config/riscv/riscv-opts.h (struct riscv_align_data): Added.
	* config/riscv/riscv.c (riscv_constant_alignment): Use 
riscv_align_data_type.

* config/riscv/riscv.h (DATA_ALIGNMENT): Use riscv_align_data_type.
(LOCAL_ALIGNMENT): Set to old DATA_ALIGNMENT value.
* config/riscv/riscv.opt (malign-data): New.
* doc/invoke.texi (RISC-V Options): Document -malign-data=.From c183fbefb9b7b53eb066cbfdaa907b6087271029 Mon Sep 17 00:00:00 2001
From: Ilia Diachkov 
Date: Wed, 26 Jun 2019 01:33:20 +0300
Subject: [PATCH] RISC-V: Add -malign-data= option.

---
 gcc/config/riscv/riscv-opts.h |  5 +
 gcc/config/riscv/riscv.c  |  3 ++-
 gcc/config/riscv/riscv.h  | 10 +++---
 gcc/config/riscv/riscv.opt| 14 ++
 gcc/doc/invoke.texi   | 10 +-
 5 files changed, 37 insertions(+), 5 deletions(-)

diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index f3031f2..c1f7fa1 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -46,4 +46,9 @@ enum riscv_microarchitecture_type {
 };
 extern enum riscv_microarchitecture_type riscv_microarchitecture;
 
+enum riscv_align_data {
+  riscv_align_data_type_word,
+  riscv_align_data_type_abi
+};
+
 #endif /* ! GCC_RISCV_OPTS_H */
diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c
index d61455f..08418ce 100644
--- a/gcc/config/riscv/riscv.c
+++ b/gcc/config/riscv/riscv.c
@@ -4904,7 +4904,8 @@ riscv_can_change_mode_class (machine_mode, machine_mode, reg_class_t rclass)
 static HOST_WIDE_INT
 riscv_constant_alignment (const_tree exp, HOST_WIDE_INT align)
 {
-  if (TREE_CODE (exp) == STRING_CST || TREE_CODE (exp) == CONSTRUCTOR)
+  if ((TREE_CODE (exp) == STRING_CST || TREE_CODE (exp) == CONSTRUCTOR)
+  && (riscv_align_data_type == riscv_align_data_type_word))
 return MAX (align, BITS_PER_WORD);
   return align;
 }
diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
index 8856cee..bace9d9 100644
--- a/gcc/config/riscv/riscv.h
+++ b/gcc/config/riscv/riscv.h
@@ -181,7 +181,8 @@ along with GCC; see the file COPYING3.  If not see
that copy constants to character arrays can be done inline.  */
 
 #define DATA_ALIGNMENT(TYPE, ALIGN)	\
-  ALIGN) < BITS_PER_WORD)		\
+  (((riscv_align_data_type == riscv_align_data_type_word)		\
+&& ((ALIGN) < BITS_PER_WORD)	\
 && (TREE_CODE (TYPE) == ARRAY_TYPE	\
 	|| TREE_CODE (TYPE) == UNION_TYPE\
 	|| TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
@@ -190,8 +191,11 @@ along with GCC; see the file COPYING3.  If not see
character arrays to be word-aligned so that `strcpy' calls that copy
constants to character arrays can be done inline, and 'strcmp' can be
optimised to use word loads. */
-#define LOCAL_ALIGNMENT(TYPE, ALIGN) \
-  DATA_ALIGNMENT (TYPE, ALIGN)
+#define LOCAL_ALIGNMENT(TYPE, ALIGN)	\
+  ALIGN) < BITS_PER_WORD)		\
+&& (TREE_CODE (TYPE) == ARRAY_TYPE	\
+	|| TREE_CODE (TYPE) == UNION_TYPE\
+	|| TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
 
 /* Define if operations between registers always perform the operation
on the full register even if a narrower mode is specified.  */
diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
index 3b25f9a..a9b8ab5 100644
--- a/gcc/config/riscv/riscv.opt
+++ b/gcc/config/riscv/riscv.opt
@@ -131,3 +131,17 @@ Mask(RVE)
 mriscv-attribute
 Target Report Var(riscv_emit_attribute_p) Init(-1)
 Emit RISC-V ELF attribute.
+
+malign-data=
+Target RejectNegative Joined Var(riscv_align_data_type) Enum(riscv_align_data) Init(riscv_align_data_type_word)
+Use the given data alignment.
+
+Enum
+Name(riscv_align_data) Type(enum riscv_align_data)
+Known data alignment choices (for use with the -malign-data= option):
+
+EnumValue
+Enum(riscv_align_data) String(word) Value(riscv_align_data_type_word)
+
+EnumValue
+Enum(riscv_align_data) String(abi) Value(riscv_align_data_type_abi)
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 50e50e3..55c08b3 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -1059,7 +1059,8 @@ See RS/6000 and PowerPC Options.
 -mcmodel=medlow  -mcmodel=medany @gol
 -mexplicit-relocs  -mno-explicit-relocs @gol
 -mrelax  

Re: [PATCH] RISC-V: Add -malign-data= option.

[Ilia Diachkov]

Hmm, may I suggest use "natural" rather than "abi" and 32bit or 64bit
rather than "word"; it is not obvious what abi means and it is not
obvious what word means here; it could be either 32bit or 64bit
depending on the option.


It's actually worse: in RISC-V "word" always means 32-bit 
(BITS_PER_WORD is a
GCC name).  "natural" seems like a good term for the "align to the size 
of the
type".  The RISC-V term for "the width of an integer register" is 
"xlen", so I

think that's a good bet for the other option.


Also my other suggestion is create a new macro where you pass
riscv_align_data_type == riscv_align_data_type_word for the "(ALIGN) <
BITS_PER_WORD) " check to reduce the code duplication.


Thanks, Andrew and Palmer. I have updated the patch (see attached) by 
new option values "natural" and "xlen". Also I have added macro 
RISCV_EXPAND_ALIGNMENT similar to one implemented in ARM.


Additionally, has this been tested with "-mstrict-align"?  The 
generated code
can be awful, but if it's not correct then we should throw an error on 
that

combination.


I have tested the new option with -mstrict-align and found no influence 
on each other. Indeed, -malign-data=xlen with -mstrict-align works in 
the same way as you run the current gcc with -mstrict-align. What about 
-malign-data=natural with -mstrict-align, I have tested it by dejagnu 
with modified target_board which additionally passes 
-malign-data=natural (the first run) and -malign-data=natural with 
-mstrict-align (the second run). Both runs shown the same result.


Best regards,
Ilia.

gcc/
* config/riscv/riscv-opts.h (struct riscv_align_data): Added.
	* config/riscv/riscv.c (riscv_constant_alignment): Use 
riscv_align_data_type.

* config/riscv/riscv.h (RISCV_EXPAND_ALIGNMENT): Added.
(DATA_ALIGNMENT): Use RISCV_EXPAND_ALIGNMENT.
(LOCAL_ALIGNMENT): Use RISCV_EXPAND_ALIGNMENT.
* config/riscv/riscv.opt (malign-data): New.
* doc/invoke.texi (RISC-V Options): Document -malign-data=.

---
 gcc/config/riscv/riscv-opts.h |  5 +
 gcc/config/riscv/riscv.c  |  3 ++-
 gcc/config/riscv/riscv.h  | 17 +++--
 gcc/config/riscv/riscv.opt| 14 ++
 gcc/doc/invoke.texi   | 10 +-
 5 files changed, 41 insertions(+), 8 deletions(-)

diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index f3031f2..d00fbe2 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -46,4 +46,9 @@ enum riscv_microarchitecture_type {
 };
 extern enum riscv_microarchitecture_type riscv_microarchitecture;
 
+enum riscv_align_data {
+  riscv_align_data_type_xlen,
+  riscv_align_data_type_natural
+};
+
 #endif /* ! GCC_RISCV_OPTS_H */
diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c
index d61455f..bc457803 100644
--- a/gcc/config/riscv/riscv.c
+++ b/gcc/config/riscv/riscv.c
@@ -4904,7 +4904,8 @@ riscv_can_change_mode_class (machine_mode, machine_mode, reg_class_t rclass)
 static HOST_WIDE_INT
 riscv_constant_alignment (const_tree exp, HOST_WIDE_INT align)
 {
-  if (TREE_CODE (exp) == STRING_CST || TREE_CODE (exp) == CONSTRUCTOR)
+  if ((TREE_CODE (exp) == STRING_CST || TREE_CODE (exp) == CONSTRUCTOR)
+  && (riscv_align_data_type == riscv_align_data_type_xlen))
 return MAX (align, BITS_PER_WORD);
   return align;
 }
diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
index 8856cee..2e27e83 100644
--- a/gcc/config/riscv/riscv.h
+++ b/gcc/config/riscv/riscv.h
@@ -168,6 +168,13 @@ along with GCC; see the file COPYING3.  If not see
mode that should actually be used.  We allow pairs of registers.  */
 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_64BIT ? TImode : DImode)
 
+/* DATA_ALIGNMENT and LOCAL_ALIGNMENT common definition.  */
+#define RISCV_EXPAND_ALIGNMENT(COND, TYPE, ALIGN)			\
+  (((COND) && ((ALIGN) < BITS_PER_WORD)	\
+&& (TREE_CODE (TYPE) == ARRAY_TYPE	\
+	|| TREE_CODE (TYPE) == UNION_TYPE\
+	|| TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
+
 /* If defined, a C expression to compute the alignment for a static
variable.  TYPE is the data type, and ALIGN is the alignment that
the object would ordinarily have.  The value of this macro is used
@@ -180,18 +187,16 @@ along with GCC; see the file COPYING3.  If not see
cause character arrays to be word-aligned so that `strcpy' calls
that copy constants to character arrays can be done inline.  */
 
-#define DATA_ALIGNMENT(TYPE, ALIGN)	\
-  ALIGN) < BITS_PER_WORD)		\
-&& (TREE_CODE (TYPE) == ARRAY_TYPE	\
-	|| TREE_CODE (TYPE) == UNION_TYPE\
-	|| TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
+#define DATA_ALIGNMENT(TYPE, ALIGN)		\
+  RISCV_EXPAND_ALIGNMENT (riscv_align_data_type == riscv_align_data_type_xlen,	\
+			  TYPE, ALIGN)
 
 /* We need this for the same reason as DATA_ALIGNMENT, namely to cause
character arrays to be word-aligned so that `strcpy' ca

Ping: [PATCH] RISC-V: Add -malign-data= option.

[Ilia Diachkov]

Hello,

There are two weeks gone since the end of the patch discussion but no 
one has neither objected nor approved it. Please take a look to it and 
approve. Also please commit it since I have no write access.


The updated version of the patch was attached to my message 
https://gcc.gnu.org/ml/gcc-patches/2019-06/msg01689.html


The updated patch description:

This patch adds new machine specific option -malign-data={xlen,natural} 
to RISC-V port. The option switches alignment of global variables and 
constants of array/record/union types. The default value 
(-malign-data=xlen) keeps existing way of alignment computation. Another 
option value (-malign-data=natural) makes data natural alignment. It 
avoids extra spaces between data to reduce code size. The measured code 
size reduction is about 0.4% at -Os on EEMBC automotive 1.1 tests and 
SPEC2006 C/C++ benchmarks. The patch was tested in riscv-gnu-toolchain 
by dejagnu. Also I have tested the new option with -mstrict-align and 
found no influence on each other.


Best regards,
Ilia.

Ping^2: [PATCH] RISC-V: Add -malign-data= option.

[Ilia Diachkov]

Ping: https://gcc.gnu.org/ml/gcc-patches/2019-06/msg01609.html

Andrew, Palmer,

I think all issues was fixed in 
https://gcc.gnu.org/ml/gcc-patches/2019-06/msg01689.html . Do you have 
any concerns about the patch?


Best regards,
Ilia.