[committed] MAINTAINERS: Add myself to DCO section
I would like to add myself to DCO section for some contributions. commit 088a51a0abb5497cac32055bf373fa6039b924f8 Author: Chung-Ju Wu Date: Wed, 16 Mar 2022 03:20:00 + MAINTAINERS: Add myself to DCO section ChangeLog: * MAINTAINERS: Add myself to DCO section. Committed to trunk. --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index ccb79f5d2f4..54d55f01e99 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -725,3 +725,4 @@ Edward Smith-Rowland Petter Tomner Martin Uecker Jonathan Wakely +Chung-Ju Wu
[PATCH 1/3][ARM] STAR-MC1 CPU Support - arm: Add star-mc1 core
Hi, STAR-MC1 is an embedded processor with armv8m architecture. Majorly it is designed to meet the requirements of AIoT application performance, power consumption and security. Early this month, star-mc1 is supported by the latest releases of MDK and CMSIS. For the completeness of Arm ecosystem, it would be great if we can have star-mc1 support in official GCC as well. Attached is the patch to support star-mc1 cpu in GCC: * Fundamental of -mcpu=star-mc1 option - Based on latest upstream commit: https://gcc.gnu.org/g:3dff965cae6709a5fd1b7b05c51c3c8aba786961 - Add star-mc1 cpu in arm-cpus.in and regenerate necessary implementation * Include VLLDM bugfix - CVE-2021-35465 also affects star-mc1 configuration [1] - We apply quirk_vlldm strategy for star-mc1 cpu Successfully bootstrapped and tested on arm-none-eabi. Is it OK for trunk? [1] https://www.cve.org/CVERecord?id=CVE-2021-35465 Regards, jasonwucjFrom 3405d35f4a6a6abd7808e2c62ce2d1dbd2e2cb14 Mon Sep 17 00:00:00 2001 From: Chung-Ju Wu Date: Thu, 26 May 2022 02:58:16 + Subject: [PATCH 1/3] arm: Add star-mc1 core Signed-off-by: Chung-Ju Wu gcc/ChangeLog: * config/arm/arm-cpus.in: Add star-mc1 core. * config/arm/arm-tables.opt: Regenerate. * config/arm/arm-tune.md: Regenerate. --- gcc/config/arm/arm-cpus.in| 10 ++ gcc/config/arm/arm-tables.opt | 3 +++ gcc/config/arm/arm-tune.md| 4 ++-- 3 files changed, 15 insertions(+), 2 deletions(-) diff --git a/gcc/config/arm/arm-cpus.in b/gcc/config/arm/arm-cpus.in index 0d3082b569f..5a63bc548e5 100644 --- a/gcc/config/arm/arm-cpus.in +++ b/gcc/config/arm/arm-cpus.in @@ -1638,6 +1638,16 @@ begin cpu cortex-m55 vendor 41 end cpu cortex-m55 +begin cpu star-mc1 + cname starmc1 + tune flags LDSCHED + architecture armv8-m.main+dsp+fp + option nofp remove ALL_FP + option nodsp remove armv7em + isa quirk_no_asmcpu quirk_vlldm + costs v7m +end cpu star-mc1 + # V8 R-profile implementations. begin cpu cortex-r52 cname cortexr52 diff --git a/gcc/config/arm/arm-tables.opt b/gcc/config/arm/arm-tables.opt index ef0cc5ef0c8..e6461abcc57 100644 --- a/gcc/config/arm/arm-tables.opt +++ b/gcc/config/arm/arm-tables.opt @@ -282,6 +282,9 @@ Enum(processor_type) String(cortex-m35p) Value( TARGET_CPU_cortexm35p) EnumValue Enum(processor_type) String(cortex-m55) Value( TARGET_CPU_cortexm55) +EnumValue +Enum(processor_type) String(star-mc1) Value( TARGET_CPU_starmc1) + EnumValue Enum(processor_type) String(cortex-r52) Value( TARGET_CPU_cortexr52) diff --git a/gcc/config/arm/arm-tune.md b/gcc/config/arm/arm-tune.md index 34225536042..abc290edd09 100644 --- a/gcc/config/arm/arm-tune.md +++ b/gcc/config/arm/arm-tune.md @@ -49,6 +49,6 @@ cortexa710,cortexx1,neoversen1, cortexa75cortexa55,cortexa76cortexa55,neoversev1, neoversen2,cortexm23,cortexm33, - cortexm35p,cortexm55,cortexr52, - cortexr52plus" + cortexm35p,cortexm55,starmc1, + cortexr52,cortexr52plus" (const (symbol_ref "((enum attr_tune) arm_tune)"))) -- 2.31.1
[PATCH 2/3][ARM] STAR-MC1 CPU Support - arm: Add individual star-mc1 cost tables and cost functions
Hi,
Attached is the patch to provide star-mc1 specific cost functions and tables.
Given these individual implementation, developers are able to make
their own adjustment to fine-tune star-mc1 performance without affecting
other cpu configurations.
Bootstrapped and tested on arm-none-eabi.
Is it OK for trunk?
Regards,
jasonwucjFrom e9081bb6d7fc1521036dbceec59ba2eae532c04c Mon Sep 17 00:00:00 2001
From: Chung-Ju Wu
Date: Thu, 26 May 2022 03:47:23 +
Subject: [PATCH 2/3] arm: Add individual star-mc1 cost tables and cost
functions
Signed-off-by: Chung-Ju Wu
gcc/ChangeLog:
* config/arm/arm-cpus.in (star-mc1): Use star_mc1 costs.
* config/arm/arm.cc (arm_star_mc1_branch_cost): New function.
(star_mc1_extra_costs): New struct.
(arm_star_mc1_tune): New struct.
---
gcc/config/arm/arm-cpus.in | 2 +-
gcc/config/arm/arm.cc | 139 +
2 files changed, 140 insertions(+), 1 deletion(-)
diff --git a/gcc/config/arm/arm-cpus.in b/gcc/config/arm/arm-cpus.in
index 5a63bc548e5..6a346e4a93d 100644
--- a/gcc/config/arm/arm-cpus.in
+++ b/gcc/config/arm/arm-cpus.in
@@ -1645,7 +1645,7 @@ begin cpu star-mc1
option nofp remove ALL_FP
option nodsp remove armv7em
isa quirk_no_asmcpu quirk_vlldm
- costs v7m
+ costs star_mc1
end cpu star-mc1
# V8 R-profile implementations.
diff --git a/gcc/config/arm/arm.cc b/gcc/config/arm/arm.cc
index 70c2d50f0cc..c8f96f92a59 100644
--- a/gcc/config/arm/arm.cc
+++ b/gcc/config/arm/arm.cc
@@ -295,6 +295,7 @@ static int arm_default_branch_cost (bool, bool);
static int arm_cortex_a5_branch_cost (bool, bool);
static int arm_cortex_m_branch_cost (bool, bool);
static int arm_cortex_m7_branch_cost (bool, bool);
+static int arm_star_mc1_branch_cost (bool, bool);
static bool arm_vectorize_vec_perm_const (machine_mode, rtx, rtx, rtx,
const vec_perm_indices &);
@@ -1847,6 +1848,113 @@ const struct cpu_cost_table v7m_extra_costs =
}
};
+const struct cpu_cost_table star_mc1_extra_costs =
+{
+ /* ALU */
+ {
+0, /* arith. */
+0, /* logical. */
+0, /* shift. */
+0, /* shift_reg. */
+0, /* arith_shift. */
+COSTS_N_INSNS (1), /* arith_shift_reg. */
+0, /* log_shift. */
+COSTS_N_INSNS (1), /* log_shift_reg. */
+0, /* extend. */
+COSTS_N_INSNS (1), /* extend_arith. */
+0, /* bfi. */
+0, /* bfx. */
+0, /* clz. */
+0, /* rev. */
+COSTS_N_INSNS (1), /* non_exec. */
+false /* non_exec_costs_exec. */
+ },
+ {
+/* MULT SImode */
+{
+ COSTS_N_INSNS (1), /* simple. */
+ COSTS_N_INSNS (1), /* flag_setting. */
+ COSTS_N_INSNS (2), /* extend. */
+ COSTS_N_INSNS (1), /* add. */
+ COSTS_N_INSNS (3), /* extend_add. */
+ COSTS_N_INSNS (8)/* idiv. */
+},
+/* MULT DImode */
+{
+ 0, /* simple (N/A). */
+ 0, /* flag_setting (N/A). */
+ COSTS_N_INSNS (2), /* extend. */
+ 0, /* add (N/A). */
+ COSTS_N_INSNS (3), /* extend_add. */
+ 0/* idiv (N/A). */
+}
+ },
+ /* LD/ST */
+ {
+COSTS_N_INSNS (2), /* load. */
+0, /* load_sign_extend. */
+COSTS_N_INSNS (3), /* ldrd. */
+COSTS_N_INSNS (2), /* ldm_1st. */
+1, /* ldm_regs_per_insn_1st. */
+1, /* ldm_regs_per_insn_subsequent. */
+COSTS_N_INSNS (2), /* loadf. */
+COSTS_N_INSNS (3), /* loadd. */
+COSTS_N_INSNS (1), /* load_unaligned. */
+COSTS_N_INSNS (2), /* store. */
+COSTS_N_INSNS (3), /* strd. */
+COSTS_N_INSNS (2), /* stm_1st. */
+1, /* stm_regs_per_insn_1st. */
+1, /* stm_regs_per_insn_subsequent. */
+COSTS_N_INSNS (2), /* storef. */
+COSTS_N_INSNS (3), /* stored. */
+COSTS_N_INSNS (1), /* store_unaligned. */
+COSTS_N_INSNS (1), /* loadv. */
+COSTS_N_INSNS (1) /* storev. */
+ },
+ {
+/* FP SFmode */
+{
+ COSTS_N_INSNS (7), /* div. */
+ COSTS_N_INSNS (2), /* mult. */
+ COSTS_N_INSNS (5), /* mult_addsub. */
+ COSTS_N_INSNS (3), /* fma. */
+ COSTS_N_INSNS (1), /* addsub. */
+ 0, /* fpconst. */
+ 0, /* neg. */
+ 0, /* compare. */
+ 0, /* widen. */
+ 0, /* narrow. */
+ 0, /* toint. */
+ 0, /* fromint. */
+ 0/* roundint. */
+},
+/* FP DFmode */
+{
+
[PATCH 3/3][ARM] STAR-MC1 CPU Support - docs: Add star-mc1 core
Hi,
This is the patch to add star-mc1 in the Arm -mtune and
-mfix-cmse-cve-2021-35465 sections of gcc invoke.texi documentation.
Is it OK for trunk?
Regards,
jasonwucjFrom b3bd24d842b6284f2b893caa658975d9d746be73 Mon Sep 17 00:00:00 2001
From: Chung-Ju Wu
Date: Thu, 26 May 2022 05:15:13 +
Subject: [PATCH 3/3] docs: Add star-mc1 core
Signed-off-by: Chung-Ju Wu
gcc/ChangeLog:
* doc/invoke.text: Add star-mc1 core.
---
gcc/doc/invoke.texi | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 71098d86313..ac889e6e2b4 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -21181,7 +21181,8 @@ Permissible names are: @samp{arm7tdmi},
@samp{arm7tdmi-s}, @samp{arm710t},
@samp{cortex-m0plus.small-multiply}, @samp{exynos-m1}, @samp{marvell-pj4},
@samp{neoverse-n1}, @samp{neoverse-n2}, @samp{neoverse-v1}, @samp{xscale},
@samp{iwmmxt}, @samp{iwmmxt2}, @samp{ep9312}, @samp{fa526}, @samp{fa626},
-@samp{fa606te}, @samp{fa626te}, @samp{fmp626}, @samp{fa726te}, @samp{xgene1}.
+@samp{fa606te}, @samp{fa626te}, @samp{fmp626}, @samp{fa726te}, @samp{star-mc1},
+@samp{xgene1}.
Additionally, this option can specify that GCC should tune the performance
of the code for a big.LITTLE system. Permissible names are:
@@ -21587,8 +21588,9 @@ Development Tools Engineering Specification", which can
be found on
Mitigate against a potential security issue with the @code{VLLDM} instruction
in some M-profile devices when using CMSE (CVE-2021-365465). This option is
enabled by default when the option @option{-mcpu=} is used with
-@code{cortex-m33}, @code{cortex-m35p} or @code{cortex-m55}. The option
-@option{-mno-fix-cmse-cve-2021-35465} can be used to disable the mitigation.
+@code{cortex-m33}, @code{cortex-m35p}, @code{cortex-m55} or @code{star-mc1}.
+The option @option{-mno-fix-cmse-cve-2021-35465} can be used to disable
+the mitigation.
@item -mstack-protector-guard=@var{guard}
@itemx -mstack-protector-guard-offset=@var{offset}
--
2.31.1
Re: [PATCH 2/3][ARM] STAR-MC1 CPU Support - arm: Add individual star-mc1 cost tables and cost functions
Hi Kyrylo, On 2022/06/06 22:18 UTC+8, Kyrylo Tkachov wrote: I'd rather not duplicate those structures and functions in the master branch, as they provide a maintenance burden to the community. If some tuning parameters need to be modified in the future for better performance we can create star-mc1-specific structures on demand then. Thus, I think we don't want this patch. Thanks, Kyrill Thanks for the comment. Indeed, considering the maintenance burden to community, having those duplicate structures in the master branch is not a good idea. I am planning to contribute the star-mc1 pipeline machine description in the future. Maybe it would be better to propose new star-mc1 specific structure along with pipeline implementation then. Thanks for the review. I won't apply this 2/3 patch. Regards, jasonwucj
Re: [PATCH 1/3][ARM] STAR-MC1 CPU Support - arm: Add star-mc1 core
Hi Kyrylo, On 2022/06/06 22:10 UTC+8, Kyrylo Tkachov wrote: Successfully bootstrapped and tested on arm-none-eabi. Is it OK for trunk? This is okay (together with the documentation additions in 3/3) Thanks for the patch, Thanks for the approval. The patches 1/3 and 3/3 have been merged into one single patch and committed as: https://gcc.gnu.org/g:ef5cc6bbb60b0ccbc10fb76b697ae02f28af18c0 Regards, jasonwucj
[PATCH][wwwdocs] gcc-13: add arm star-mc1 cpu
Hi, Recently we added arm star-mc1 cpu support to upstream: https://gcc.gnu.org/pipermail/gcc-patches/2022-June/596379.html It would be great if we can describe it on gcc-13 changes.html as well. Attached is the patch for gcc-wwwdocs repository. Is it OK? Regards, jasonwucjFrom 379e1b67b92becaf1dc152ba1b5eaf617eaf3972 Mon Sep 17 00:00:00 2001 From: Chung-Ju Wu Date: Thu, 16 Jun 2022 02:37:36 + Subject: [PATCH] gcc-13: Add arm star-mc1 cpu support --- htdocs/gcc-13/changes.html | 7 ++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/htdocs/gcc-13/changes.html b/htdocs/gcc-13/changes.html index a262087f..90e979b0 100644 --- a/htdocs/gcc-13/changes.html +++ b/htdocs/gcc-13/changes.html @@ -109,7 +109,12 @@ a work-in-progress. - +arm + + The STAR-MC1 CPU is now supported through the star-mc1 + argument to the -mcpu and -mtune options. + + -- 2.31.1
Re: [PATCH][wwwdocs] gcc-13: add arm star-mc1 cpu
On 2022/06/16 23:23 UTC+8, Gerald Pfeifer wrote: On Thu, 16 Jun 2022, Chung-Ju Wu wrote: Recently we added arm star-mc1 cpu support to upstream: https://gcc.gnu.org/pipermail/gcc-patches/2022-June/596379.html It would be great if we can describe it on gcc-13 changes.html as well. Attached is the patch for gcc-wwwdocs repository. Looks good to me (from the wwwdocs side), thank you! Gerald Hi Gerald, Thanks for the approval! Committed as: fbc3a3692fa2bc85cd252d114f801da202f3ed35 Hi Kyrylo, If there requires any other adjustment on description, just let me know and I will make further changes accordingly. Thanks. Regards, jasonwucj
