[PATCH 3/12 V2] arm: Add option -mbranch-protection

[Andrea Corallo via Gcc-patches]

Richard Earnshaw  writes:

[...]

> +@item
> +-mbranch-protection=@var{none}|@var{standard}|@var{pac-ret}[+@var{leaf}][+@var{bti}]|@var{bti}[+@var{pac-ret}[+@var{leaf}]]
> +@opindex mbranch-protection
> +Enable branch protection features (armv8.1-m.main only).
> +@samp{none} generate code without branch protection or return address
> +signing.
> +@samp{standard[+@var{leaf}]} generate code with all branch protection
> +features enabled at their standard level.
> +@samp{pac-ret[+@var{leaf}]} generate code with return address signing
> +set to its standard level, which is to sign all functions that save
> +the return address to memory.
> +@samp{leaf} When return address signing is enabled, also sign leaf
> +functions even if they do not write the return address to memory.
> ++@samp{bti} Add landing-pad instructions at the permitted targets of
> +indirect branch instructions.
> +
> +If the @samp{+pacbti} architecture extension is not enabled, then all
> +branch protection and return address signing operations are
> +constrained to use only the instructions defined in the
> +architectural-NOP space. The generated code will remain
> +backwards-compatible with earlier versions of the architecture, but
> +the additional security can be enabled at run time on processors that
> +support the @samp{PACBTI} extension.
> +
> +Branch target enforcement using BTI can only be enabled at runtime if
> +all code in the application has been compiled with at least
> +@samp{-mbranch-protection=bti}.
> +
> +The default is to generate code without branch protection or return
> +address signing.
>
> This needs to make it clear that -mbranch-protection != none is only
> supported on armv8-m.main or later.
>
> R.

Hi Richard,

thanks for reviewing, please find attached the respinned patch.

Ok for trunk (when the rest of the series will be approved)?

Best Regards

  Andrea

gcc/ChangeLog:

* config/arm/arm.c (arm_configure_build_target): Parse and validate
-mbranch-protection option and initialize appropriate data structures.
* config/arm/arm.opt (-mbranch-protection): New option.
* doc/invoke.texi (Arm Options): Document it.

Co-Authored-By: Tejas Belagod  
Co-Authored-By: Richard Earnshaw 

diff --git a/gcc/config/arm/arm.cc b/gcc/config/arm/arm.cc
index 60f3eae82a4..0068817b0f2 100644
--- a/gcc/config/arm/arm.cc
+++ b/gcc/config/arm/arm.cc
@@ -3263,6 +3263,17 @@ arm_configure_build_target (struct arm_build_target 
*target,
   tune_opts = strchr (opts->x_arm_tune_string, '+');
 }
 
+  if (opts->x_arm_branch_protection_string)
+{
+  aarch_validate_mbranch_protection (opts->x_arm_branch_protection_string);
+
+  if (aarch_ra_sign_key != AARCH_KEY_A)
+   {
+ warning (0, "invalid key type for %<-mbranch-protection=%>");
+ aarch_ra_sign_key = AARCH_KEY_A;
+   }
+}
+
   if (arm_selected_arch)
 {
   arm_initialize_isa (target->isa, arm_selected_arch->common.isa_bits);
diff --git a/gcc/config/arm/arm.opt b/gcc/config/arm/arm.opt
index f54ec8356c3..d292e23ea11 100644
--- a/gcc/config/arm/arm.opt
+++ b/gcc/config/arm/arm.opt
@@ -323,6 +323,10 @@ mbranch-cost=
 Target RejectNegative Joined UInteger Var(arm_branch_cost) Init(-1)
 Cost to assume for a branch insn.
 
+mbranch-protection=
+Target RejectNegative Joined Var(arm_branch_protection_string) Save
+Use branch-protection features.
+
 mgeneral-regs-only
 Target RejectNegative Mask(GENERAL_REGS_ONLY) Save
 Generate code which uses the core registers only (r0-r14).
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 079e34ed98c..a2be3446594 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -825,7 +825,9 @@ Objective-C and Objective-C++ Dialects}.
 -mcmse @gol
 -mfix-cmse-cve-2021-35465 @gol
 -mstack-protector-guard=@var{guard} 
-mstack-protector-guard-offset=@var{offset} @gol
--mfdpic}
+-mfdpic @gol
+-mbranch-protection=@var{none}|@var{standard}|@var{pac-ret}[+@var{leaf}]
+[+@var{bti}]|@var{bti}[+@var{pac-ret}[+@var{leaf}]]}
 
 @emph{AVR Options}
 @gccoptlist{-mmcu=@var{mcu}  -mabsdata  -maccumulate-args @gol
@@ -21521,6 +21523,40 @@ The opposite @option{-mno-fdpic} option is useful (and 
required) to
 build the Linux kernel using the same (@code{arm-*-uclinuxfdpiceabi})
 toolchain as the one used to build the userland programs.
 
+@item
+-mbranch-protection=@var{none}|@var{standard}|@var{pac-ret}[+@var{leaf}][+@var{bti}]|@var{bti}[+@var{pac-ret}[+@var{leaf}]]
+@opindex mbranch-protection
+Enable branch protection features (armv8.1-m.main only).
+@samp{none} generate code without branch protection or return address
+signing.
+@samp{standard[+@var{leaf}]} generate code with all branch protection
+features enabled at their standard level.
+@samp{pac-ret[+@var{leaf}]} generate code with return address signing
+set to its standard level, which is to sign all functions that save
+the return address to memory.
+@samp{leaf} When return address signing is enabled, also sign leaf
+functions ev

Re: [PATCH 4/12] arm: Add testsuite library support for PACBTI target

[Andrea Corallo via Gcc-patches]

Richard Earnshaw  writes:

> On 01/07/2022 14:03, Richard Earnshaw via Gcc-patches wrote:
>> On 28/04/2022 10:40, Andrea Corallo via Gcc-patches wrote:
>>> Add targeting-checking entities for PACBTI in testsuite
>>> framework.
>>>
>>> Pre-approved with the requested changes here
>>> <https://gcc.gnu.org/pipermail/gcc-patches/2021-December/586331.html>.
>>>
>>> gcc/testsuite/ChangeLog:
>>>
>>> * testsuite/lib/target-supports.exp:
>>> (check_effective_target_arm_pacbti_hw): New.
>>> * doc/sourcebuild.texi: Document arm_pacbti_hw.
>>>
>>> Co-Authored-By: Tejas Belagod  
>>>
>> +proc check_effective_target_arm_pacbti_hw {} {
>> +    return [check_runtime arm_pacbti_hw_available {
>> +    __attribute__ ((naked)) int
>> +    main (void)
>> +    {
>> +  asm ("pac r12, lr, sp");
>> So the armv8-m Arm ARM says that this instruction is in the NOP
>> space and that it is undefined if we aren't armv8-m.main or higher.
>> +  asm ("mov r0, #0");
>> +  asm ("autg r12, lr, sp");
>> This isn't in the nop space, but the Arm ARM says it is
>> unpredictable if the extension isn't present.  Unfortunately, that
>> means this isn't a particularly reliable way of detecting that the
>> PACBTI feature is present.
>> However, I can't think off hand of more reliable way of testing this
>> since reading the feature register ID_ISAR5 is not possible when in
>> unprivileged mode.
>> So I think we'll have to live with this.
>> +  asm ("bx lr");
>> +    }
>> +    } ""]
>> OK.
>> 
>
> Or perhaps not. The test does not try to add the right options to
> enable PAC/BTI if those aren't in the default selection for the
> current testsuite run.
>
> Perhaps we also need some additional tests to work out what
> architecture options to add (if any) to ensure the test will at least
> assemble.

Hi Richard,
thanks for reviewing.

Wouldn't be sufficient for that to have this test compiled with
-march=armv8-m.main?

BR

  Andrea

[PATCH 5/12 V2] arm: Implement target feature macros for PACBTI

[Andrea Corallo via Gcc-patches]

Richard Earnshaw  writes:

> On 28/04/2022 10:42, Andrea Corallo via Gcc-patches wrote:
>> This patch implements target feature macros when PACBTI is enabled
>> through the -march option or -mbranch-protection.  The target feature
>> macros __ARM_FEATURE_PAC_DEFAULT and __ARM_FEATURE_BTI_DEFAULT are
>> specified in ARM ACLE
>> <https://developer.arm.com/documentation/101028/0012/5--Feature-test-macros?lang=en>
>> __ARM_FEATURE_PAUTH and __ARM_FEATURE_BTI are specified in the
>> pull-request <https://github.com/ARM-software/acle/pull/55>.
>> Approved here
>> <https://gcc.gnu.org/pipermail/gcc-patches/2021-December/586334.html>.
>> gcc/ChangeLog:
>>  * config/arm/arm-c.c (arm_cpu_builtins): Define
>>  __ARM_FEATURE_BTI_DEFAULT, __ARM_FEATURE_PAC_DEFAULT,
>>  __ARM_FEATURE_PAUTH and __ARM_FEATURE_BTI.
>
> This bit is OK.
>
>> gcc/testsuite/ChangeLog:
>>  * gcc.target/arm/acle/pacbti-m-predef-2.c: New test.
>>  * gcc.target/arm/acle/pacbti-m-predef-4.c: New test.
>>  * gcc.target/arm/acle/pacbti-m-predef-5.c: New test.
>> 
>
> These are all execution tests.  I think we also need some compile-only
> tests so that we get better coverage when the target does not directly
> support PACBTI.
>
> We also need some tests for the defines when targetting armv8-m.main
> and some tests for checking __ARM_FEATURE_BTI and __ARM_FEATURE_PAC
> (the tests here check only the '..._DEFAULT' macros.

Hi Richard & all,

please find attached the updated version of this patch.

Best Regards

  Andrea

gcc/ChangeLog:

* config/arm/arm-c.c (arm_cpu_builtins): Define
__ARM_FEATURE_BTI_DEFAULT, __ARM_FEATURE_PAC_DEFAULT,
__ARM_FEATURE_PAUTH and __ARM_FEATURE_BTI.

gcc/testsuite/ChangeLog:

* gcc.target/arm/acle/pacbti-m-predef-2.c: New test.
* gcc.target/arm/acle/pacbti-m-predef-4.c: Likewise.
* gcc.target/arm/acle/pacbti-m-predef-5.c: Likewise.
* gcc.target/arm/acle/pacbti-m-predef-8.c: Likewise.
* gcc.target/arm/acle/pacbti-m-predef-9.c: Likewise.
* gcc.target/arm/acle/pacbti-m-predef-10.c: Likewise.
* gcc.target/arm/acle/pacbti-m-predef-11.c: Likewise.
* gcc.target/arm/acle/pacbti-m-predef-12.c: Likewise.

>From d1897ca2db828d214a6591ab34f29cf42ebd2fb6 Mon Sep 17 00:00:00 2001
From: Andrea Corallo 
Date: Mon, 6 Dec 2021 11:39:59 +0100
Subject: [PATCH] [PATCH 5/12] arm: Implement target feature macros for PACBTI

This patch implements target feature macros when PACBTI is enabled
through the -march option or -mbranch-protection.  The target feature
macros __ARM_FEATURE_PAC_DEFAULT and __ARM_FEATURE_BTI_DEFAULT are
specified in ARM ACLE
<https://developer.arm.com/documentation/101028/0012/5--Feature-test-macros?lang=en>
__ARM_FEATURE_PAUTH and __ARM_FEATURE_BTI are specified in the
pull-request <https://github.com/ARM-software/acle/pull/55>.

Approved here
<https://gcc.gnu.org/pipermail/gcc-patches/2021-December/586334.html>.

gcc/ChangeLog:

* config/arm/arm-c.c (arm_cpu_builtins): Define
__ARM_FEATURE_BTI_DEFAULT, __ARM_FEATURE_PAC_DEFAULT,
__ARM_FEATURE_PAUTH and __ARM_FEATURE_BTI.

gcc/testsuite/ChangeLog:

* gcc.target/arm/acle/pacbti-m-predef-2.c: New test.
* gcc.target/arm/acle/pacbti-m-predef-4.c: Likewise.
* gcc.target/arm/acle/pacbti-m-predef-5.c: Likewise.
* gcc.target/arm/acle/pacbti-m-predef-8.c: Likewise.
* gcc.target/arm/acle/pacbti-m-predef-9.c: Likewise.
* gcc.target/arm/acle/pacbti-m-predef-10.c: Likewise.
* gcc.target/arm/acle/pacbti-m-predef-11.c: Likewise.
* gcc.target/arm/acle/pacbti-m-predef-12.c: Likewise.

Co-Authored-By: Tejas Belagod  
---
 gcc/config/arm/arm-c.cc   | 18 ++
 .../gcc.target/arm/acle/pacbti-m-predef-10.c  | 10 
 .../gcc.target/arm/acle/pacbti-m-predef-11.c  | 10 
 .../gcc.target/arm/acle/pacbti-m-predef-12.c  | 10 
 .../gcc.target/arm/acle/pacbti-m-predef-2.c   | 24 +++
 .../gcc.target/arm/acle/pacbti-m-predef-4.c   | 21 
 .../gcc.target/arm/acle/pacbti-m-predef-5.c   | 24 +++
 .../gcc.target/arm/acle/pacbti-m-predef-8.c   | 11 +
 .../gcc.target/arm/acle/pacbti-m-predef-9.c   | 10 
 9 files changed, 138 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-10.c
 create mode 100644 gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-11.c
 create mode 100644 gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-12.c
 create mode 100644 gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-2.c
 create mode 100644 gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-4.c
 create mode 100644 gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-5.c
 create mode 100644 gcc/testsuit

[PATCH 7/12 V2] arm: Emit build attributes for PACBTI target feature

[Andrea Corallo via Gcc-patches]

Richard Earnshaw  writes:

> On 28/04/2022 10:45, Andrea Corallo via Gcc-patches wrote:
>> This patch emits assembler directives for PACBTI build attributes as
>> defined by the
>> ABI.
>> <https://github.com/ARM-software/abi-aa/releases/download/2021Q1/addenda32.pdf>
>> gcc/ChangeLog:
>>  * config/arm/arm.c (arm_file_start): Emit EABI attributes for
>>  Tag_PAC_extension, Tag_BTI_extension, TAG_BTI_use, TAG_PACRET_use.
>
> This bit is OK.
>
>> gcc/testsuite/ChangeLog:
>>  * gcc.target/arm/acle/pacbti-m-predef-1.c: New test.
>>  * gcc.target/arm/acle/pacbti-m-predef-3: Likewise.
>>  * gcc.target/arm/acle/pacbti-m-predef-6.c: Likewise.
>>  * gcc.target/arm/acle/pacbti-m-predef-7.c: Likewise.
>
> These tests contain directives like:
>
> +/* { dg-additional-options " -mbranch-protection=pac-ret+bti
> --save-temps" } */
>
> But they don't check that the architecture permits this (it has to be
> armv8-m.main or later).

Hi Richard & all,

please find attached the updated patch.

BR

 Andrea

>From 7d66e00bf62c8624d03e0173be8b8631d7435c38 Mon Sep 17 00:00:00 2001
From: Andrea Corallo 
Date: Mon, 6 Dec 2021 11:42:24 +0100
Subject: [PATCH] [PATCH 7/12] arm: Emit build attributes for PACBTI target
 feature

This patch emits assembler directives for PACBTI build attributes as
defined by the
ABI.

<https://github.com/ARM-software/abi-aa/releases/download/2021Q1/addenda32.pdf>

gcc/ChangeLog:

* config/arm/arm.c (arm_file_start): Emit EABI attributes for
Tag_PAC_extension, Tag_BTI_extension, TAG_BTI_use, TAG_PACRET_use.

gcc/testsuite/ChangeLog:

* gcc.target/arm/acle/pacbti-m-predef-1.c: New test.
* gcc.target/arm/acle/pacbti-m-predef-3: Likewise.
* gcc.target/arm/acle/pacbti-m-predef-6.c: Likewise.
* gcc.target/arm/acle/pacbti-m-predef-7.c: Likewise.

Co-Authored-By: Tejas Belagod  
---
 gcc/config/arm/arm.cc  | 18 ++
 .../gcc.target/arm/acle/pacbti-m-predef-1.c| 16 
 .../gcc.target/arm/acle/pacbti-m-predef-3.c| 16 
 .../gcc.target/arm/acle/pacbti-m-predef-6.c| 15 +++
 .../gcc.target/arm/acle/pacbti-m-predef-7.c| 16 
 5 files changed, 81 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-1.c
 create mode 100644 gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-3.c
 create mode 100644 gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-6.c
 create mode 100644 gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-7.c

diff --git a/gcc/config/arm/arm.cc b/gcc/config/arm/arm.cc
index 0068817b0f2..ceec14f84b6 100644
--- a/gcc/config/arm/arm.cc
+++ b/gcc/config/arm/arm.cc
@@ -28349,6 +28349,8 @@ static void
 arm_file_start (void)
 {
   int val;
+  bool pac = (aarch_ra_sign_scope != AARCH_FUNCTION_NONE);
+  bool bti = (aarch_enable_bti == 1);
 
   arm_print_asm_arch_directives
 (asm_out_file, TREE_TARGET_OPTION (target_option_default_node));
@@ -28419,6 +28421,22 @@ arm_file_start (void)
arm_emit_eabi_attribute ("Tag_ABI_FP_16bit_format", 38,
 (int) arm_fp16_format);
 
+  if (TARGET_HAVE_PACBTI)
+   {
+ arm_emit_eabi_attribute ("Tag_PAC_extension", 50, 2);
+ arm_emit_eabi_attribute ("Tag_BTI_extension", 52, 2);
+   }
+  else if (pac || bti)
+   {
+ arm_emit_eabi_attribute ("Tag_PAC_extension", 50, 1);
+ arm_emit_eabi_attribute ("Tag_BTI_extension", 52, 1);
+   }
+
+  if (bti)
+arm_emit_eabi_attribute ("TAG_BTI_use", 74, 1);
+  if (pac)
+   arm_emit_eabi_attribute ("TAG_PACRET_use", 76, 1);
+
   if (arm_lang_output_object_attributes_hook)
arm_lang_output_object_attributes_hook();
 }
diff --git a/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-1.c 
b/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-1.c
new file mode 100644
index 000..d3ef58fcf9d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-1.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=armv8.1-m.main 
-mbranch-protection=pac-ret+bti --save-temps" } */
+
+#if !defined (__ARM_FEATURE_BTI_DEFAULT)
+#error "Feature test macro __ARM_FEATURE_BTI_DEFAULT should be defined."
+#endif
+
+#if !defined (__ARM_FEATURE_PAC_DEFAULT)
+#error "Feature test macro __ARM_FEATURE_PAC_DEFAULT should be defined."
+#endif
+
+/* { dg-final { scan-assembler-not "\.arch_extension pacbti" } } */
+/* { dg-final { scan-assembler "\.eabi_attribute 50, 1" } } */
+/* { dg-final { scan-assembler "\.eabi_attribute 52, 1" } } */
+/* { dg-final { scan-assembler "\.eabi_attribute 74, 1" } } */
+/* { dg-final { scan-assembler

[PATCH 8/12 V3] arm: Introduce multilibs for PACBTI target feature

[Andrea Corallo via Gcc-patches]

Richard Earnshaw  writes:

[...]

>> The documentation mentions -mbranch-protection=standard+leaf, so
>> you're missing a mapping for that.
>> OK with that change.
>> R.
>
> Oh, and please add some tests to gcc/testsuite/gcc.target/arm/multilib.exp
>
> R.

Hi Richard,

thanks, here the updated patch.

PS I've also added three mlibarch -> march matches that were missing.

BR

  Andrea

>From bbd0efb375c08981be7632319b24830196429e9b Mon Sep 17 00:00:00 2001
From: Andrea Corallo 
Date: Mon, 6 Dec 2021 11:42:59 +0100
Subject: [PATCH] [PATCH 8/12] arm: Introduce multilibs for PACBTI target
 feature

This patch add the following new multilibs.

thumb/v8.1-m.main+pacbti/mbranch-protection/nofp
thumb/v8.1-m.main+pacbti+dp/mbranch-protection/soft
thumb/v8.1-m.main+pacbti+dp/mbranch-protection/hard
thumb/v8.1-m.main+pacbti+fp/mbranch-protection/soft
thumb/v8.1-m.main+pacbti+fp/mbranch-protection/hard
thumb/v8.1-m.main+pacbti+mve/mbranch-protection/hard

Triggering the following compiler flags:

-mthumb -march=armv8.1-m.main+pacbti -mbranch-protection=standard 
-mfloat-abi=soft
-mthumb -march=armv8.1-m.main+pacbti+fp -mbranch-protection=standard 
-mfloat-abi=softfp
-mthumb -march=armv8.1-m.main+pacbti+fp -mbranch-protection=standard 
-mfloat-abi=hard
-mthumb -march=armv8.1-m.main+pacbti+fp.dp -mbranch-protection=standard 
-mfloat-abi=softfp
-mthumb -march=armv8.1-m.main+pacbti+fp.dp -mbranch-protection=standard 
-mfloat-abi=hard
-mthumb -march=armv8.1-m.main+pacbti+mve -mbranch-protection=standard 
-mfloat-abi=hard

gcc/

* config/arm/t-rmprofile: Add multilib rules for march +pacbti
  and mbranch-protection.

gcc/testsuite/

* gcc.target/arm/multilib.exp: Add pacbti related entries.
---
 gcc/config/arm/t-rmprofile| 29 +--
 gcc/testsuite/gcc.target/arm/multilib.exp |  6 +
 2 files changed, 33 insertions(+), 2 deletions(-)

diff --git a/gcc/config/arm/t-rmprofile b/gcc/config/arm/t-rmprofile
index eb321e832f1..c50bf4b3557 100644
--- a/gcc/config/arm/t-rmprofile
+++ b/gcc/config/arm/t-rmprofile
@@ -27,8 +27,11 @@
 
 # Arch and FPU variants to build libraries with
 
-MULTI_ARCH_OPTS_RM = 
march=armv6s-m/march=armv7-m/march=armv7e-m/march=armv7e-m+fp/march=armv7e-m+fp.dp/march=armv8-m.base/march=armv8-m.main/march=armv8-m.main+fp/march=armv8-m.main+fp.dp/march=armv8.1-m.main+mve
-MULTI_ARCH_DIRS_RM = v6-m v7-m v7e-m v7e-m+fp v7e-m+dp v8-m.base v8-m.main 
v8-m.main+fp v8-m.main+dp v8.1-m.main+mve
+MULTI_ARCH_OPTS_RM = 
march=armv6s-m/march=armv7-m/march=armv7e-m/march=armv7e-m+fp/march=armv7e-m+fp.dp/march=armv8-m.base/march=armv8-m.main/march=armv8-m.main+fp/march=armv8-m.main+fp.dp/march=armv8.1-m.main+mve/march=armv8.1-m.main+pacbti/march=armv8.1-m.main+pacbti+fp/march=armv8.1-m.main+pacbti+fp.dp/march=armv8.1-m.main+pacbti+mve
+MULTI_ARCH_DIRS_RM = v6-m v7-m v7e-m v7e-m+fp v7e-m+dp v8-m.base v8-m.main 
v8-m.main+fp v8-m.main+dp v8.1-m.main+mve v8.1-m.main+pacbti 
v8.1-m.main+pacbti+fp v8.1-m.main+pacbti+dp v8.1-m.main+pacbti+mve
+
+MULTI_ARCH_OPTS_RM += mbranch-protection=standard
+MULTI_ARCH_DIRS_RM += mbranch-protection
 
 # Base M-profile (no fp)
 MULTILIB_REQUIRED  += mthumb/march=armv6s-m/mfloat-abi=soft
@@ -50,6 +53,14 @@ MULTILIB_REQUIRED+= 
mthumb/march=armv8-m.main+fp.dp/mfloat-abi=hard
 MULTILIB_REQUIRED  += mthumb/march=armv8-m.main+fp.dp/mfloat-abi=softfp
 MULTILIB_REQUIRED  += mthumb/march=armv8.1-m.main+mve/mfloat-abi=hard
 
+MULTILIB_REQUIRED  += 
mthumb/march=armv8.1-m.main+pacbti/mbranch-protection=standard/mfloat-abi=soft
+MULTILIB_REQUIRED  += 
mthumb/march=armv8.1-m.main+pacbti+fp/mbranch-protection=standard/mfloat-abi=softfp
+MULTILIB_REQUIRED  += 
mthumb/march=armv8.1-m.main+pacbti+fp/mbranch-protection=standard/mfloat-abi=hard
+MULTILIB_REQUIRED  += 
mthumb/march=armv8.1-m.main+pacbti+fp.dp/mbranch-protection=standard/mfloat-abi=softfp
+MULTILIB_REQUIRED  += 
mthumb/march=armv8.1-m.main+pacbti+fp.dp/mbranch-protection=standard/mfloat-abi=hard
+MULTILIB_REQUIRED  += 
mthumb/march=armv8.1-m.main+pacbti+mve/mbranch-protection=standard/mfloat-abi=hard
+
+
 # Arch Matches
 MULTILIB_MATCHES   += march?armv6s-m=march?armv6-m
 
@@ -87,9 +98,23 @@ MULTILIB_MATCHES += $(foreach FP, $(v8_1m_sp_variants), \
 MULTILIB_MATCHES += $(foreach FP, $(v8_1m_dp_variants), \
 
march?armv8-m.main+fp.dp=mlibarch?armv8.1-m.main$(FP))
 
+# Map all mbranch-protection values other than 'none' to 'standard'.
+MULTILIB_MATCHES   += mbranch-protection?standard=mbranch-protection?bti
+MULTILIB_MATCHES   += 
mbranch-protection?standard=mbranch-protection?pac-ret
+MULTILIB_MATCHES   += 
mbranch-protection?standard=mbranch-protection?pac-ret+leaf
+MULTILIB_MATCHES   += 
mbranch-protection?standard=mbranch-protection?pac-ret+bti
+MULTILIB_MATCHES   += 
mbranch-protection?standard=mbranch-protection?pac-ret+leaf+bti
+MULTILIB_MATCHES   += 
mbranch-pro

[PATCH 9/12 V2] arm: Make libgcc bti compatible

[Andrea Corallo via Gcc-patches]

Richard Earnshaw  writes:

> On 28/04/2022 10:48, Andrea Corallo via Gcc-patches wrote:
>> This change add bti instructions at the beginning of arm specific
>> libgcc hand written assembly routines.
>> 2022-03-31  Andrea Corallo  
>>  * libgcc/config/arm/crti.S (FUNC_START): Add bti instruction
>> if
>>  necessary.
>>  * libgcc/config/arm/lib1funcs.S (THUMB_FUNC_START, FUNC_START):
>>  Likewise.
>> 
>
> +#if defined(__ARM_FEATURE_BTI)
>
> Wouldn't it be better to use __ARM_FEATURE_BTI_DEFAULT?  That way we
> only get BTI instructions in multilib variants that have asked for
> BTI.
>
> R.

Hi Richard,

good point, yes I think so.

Please find attached the updated patch.

BR

  Andrea

>From 6975c9ddbc8a4b790a765589c6fd07fea92173e5 Mon Sep 17 00:00:00 2001
From: Andrea Corallo 
Date: Tue, 8 Feb 2022 10:58:31 +0100
Subject: [PATCH] [PATCH 9/12] arm: Make libgcc bti compatible

This change add bti instructions at the beginning of arm specific
libgcc hand written assembly routines.

2022-03-31  Andrea Corallo  

* libgcc/config/arm/crti.S (FUNC_START): Add bti instruction if
necessary.
* libgcc/config/arm/lib1funcs.S (THUMB_FUNC_START, FUNC_START):
Likewise.
---
 libgcc/config/arm/crti.S  | 4 +++-
 libgcc/config/arm/lib1funcs.S | 6 ++
 2 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/libgcc/config/arm/crti.S b/libgcc/config/arm/crti.S
index 0192972a7e6..4098353af1c 100644
--- a/libgcc/config/arm/crti.S
+++ b/libgcc/config/arm/crti.S
@@ -51,7 +51,9 @@
 .macro FUNC_START
 #ifdef __thumb__
.thumb
-   
+#if defined(__ARM_FEATURE_BTI_DEFAULT)
+   bti
+#endif
push{r3, r4, r5, r6, r7, lr}
 #else
.arm
diff --git a/libgcc/config/arm/lib1funcs.S b/libgcc/config/arm/lib1funcs.S
index 8c39c9f20a2..de98edcc300 100644
--- a/libgcc/config/arm/lib1funcs.S
+++ b/libgcc/config/arm/lib1funcs.S
@@ -345,6 +345,9 @@ LSYM(Ldiv0):
TYPE(\name)
.thumb_func
 SYM (\name):
+#if defined(__ARM_FEATURE_BTI_DEFAULT)
+   bti
+#endif
 .endm
 
 /* Function start macros.  Variants for ARM and Thumb.  */
@@ -372,6 +375,9 @@ SYM (\name):
THUMB_FUNC
THUMB_SYNTAX
 SYM (__\name):
+#if defined(__ARM_FEATURE_BTI_DEFAULT)
+   bti
+#endif
 .endm
 
 .macro ARM_SYM_START name
-- 
2.25.1

[PATCH 5/12 V3] arm: Implement target feature macros for PACBTI

[Andrea Corallo via Gcc-patches]

Hi Richard,

thanks for reviewing.

Richard Earnshaw  writes:

[...]

> diff --git a/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-10.c
> b/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-10.c
> new file mode 100644
> index 000..311cf572dd9
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-10.c
> @@ -0,0 +1,10 @@
> +/* { dg-do compile } */
> +/* { dg-additional-options " -mbranch-protection=bti+pac-ret" } */
>
> This is not enough.  For example, if the testsuite is being run with
> "-march=armv6-m" as the testrun options, we'll get an error that will
> cause a test failure.  You need to run a pre-test rule that validates
> that adding -mbranch-protection is safe.

Right, please find attached the updated patch, it should fix this and
the mentioned spacing issue.

BR

  Andrea

>From d5e0c5c0c4a3a07eb6a65c7626f474a0dbd4f8db Mon Sep 17 00:00:00 2001
From: Andrea Corallo 
Date: Mon, 6 Dec 2021 11:39:59 +0100
Subject: [PATCH] [PATCH 5/12] arm: Implement target feature macros for PACBTI

This patch implements target feature macros when PACBTI is enabled
through the -march option or -mbranch-protection.  The target feature
macros __ARM_FEATURE_PAC_DEFAULT and __ARM_FEATURE_BTI_DEFAULT are
specified in ARM ACLE

__ARM_FEATURE_PAUTH and __ARM_FEATURE_BTI are specified in the
pull-request .

Approved here
.

gcc/

* config/arm/arm-c.c (arm_cpu_builtins): Define
__ARM_FEATURE_BTI_DEFAULT, __ARM_FEATURE_PAC_DEFAULT,
__ARM_FEATURE_PAUTH and __ARM_FEATURE_BTI.

gcc/testsuite/

* lib/target-supports.exp
(check_effective_target_mbranch_protection_ok): New function.
* gcc.target/arm/acle/pacbti-m-predef-2.c: New test.
* gcc.target/arm/acle/pacbti-m-predef-4.c: Likewise.
* gcc.target/arm/acle/pacbti-m-predef-5.c: Likewise.
* gcc.target/arm/acle/pacbti-m-predef-8.c: Likewise.
* gcc.target/arm/acle/pacbti-m-predef-9.c: Likewise.
* gcc.target/arm/acle/pacbti-m-predef-10.c: Likewise.
* gcc.target/arm/acle/pacbti-m-predef-11.c: Likewise.
* gcc.target/arm/acle/pacbti-m-predef-12.c: Likewise.

Co-Authored-By: Tejas Belagod  
---
 gcc/config/arm/arm-c.cc   | 18 +++
 .../gcc.target/arm/acle/pacbti-m-predef-10.c  | 11 +
 .../gcc.target/arm/acle/pacbti-m-predef-11.c  | 11 +
 .../gcc.target/arm/acle/pacbti-m-predef-12.c  | 11 +
 .../gcc.target/arm/acle/pacbti-m-predef-2.c   | 23 +++
 .../gcc.target/arm/acle/pacbti-m-predef-4.c   | 20 
 .../gcc.target/arm/acle/pacbti-m-predef-5.c   | 23 +++
 .../gcc.target/arm/acle/pacbti-m-predef-8.c   | 11 +
 .../gcc.target/arm/acle/pacbti-m-predef-9.c   | 10 
 gcc/testsuite/lib/target-supports.exp | 10 
 10 files changed, 148 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-10.c
 create mode 100644 gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-11.c
 create mode 100644 gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-12.c
 create mode 100644 gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-2.c
 create mode 100644 gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-4.c
 create mode 100644 gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-5.c
 create mode 100644 gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-8.c
 create mode 100644 gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-9.c

diff --git a/gcc/config/arm/arm-c.cc b/gcc/config/arm/arm-c.cc
index a8697b8c62f..190099b2c37 100644
--- a/gcc/config/arm/arm-c.cc
+++ b/gcc/config/arm/arm-c.cc
@@ -212,6 +212,24 @@ arm_cpu_builtins (struct cpp_reader* pfile)
   def_or_undef_macro (pfile, "__ARM_FEATURE_COMPLEX", TARGET_COMPLEX);
   def_or_undef_macro (pfile, "__ARM_32BIT_STATE", TARGET_32BIT);
 
+  def_or_undef_macro (pfile, "__ARM_FEATURE_PAUTH", TARGET_HAVE_PACBTI);
+  def_or_undef_macro (pfile, "__ARM_FEATURE_BTI", TARGET_HAVE_PACBTI);
+  def_or_undef_macro (pfile, "__ARM_FEATURE_BTI_DEFAULT",
+ aarch_enable_bti == 1);
+
+  cpp_undef (pfile, "__ARM_FEATURE_PAC_DEFAULT");
+  if (aarch_ra_sign_scope != AARCH_FUNCTION_NONE)
+  {
+unsigned int pac = 1;
+
+gcc_assert (aarch_ra_sign_key == AARCH_KEY_A);
+
+if (aarch_ra_sign_scope == AARCH_FUNCTION_ALL)
+  pac |= 0x4;
+
+builtin_define_with_int_value ("__ARM_FEATURE_PAC_DEFAULT", pac);
+  }
+
   cpp_undef (pfile, "__ARM_FEATURE_MVE");
   if (TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT)
 {
diff --git a/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-10.c 
b/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-10.c
new file mode 100644
index 000..4fcc96f3eb4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-10.c
@@ -0,0 +1,11 @@
+/* {

[PATCH 5/12 V4] arm: Implement target feature macros for PACBTI

[Andrea Corallo via Gcc-patches]

Andrea Corallo via Gcc-patches  writes:

> Hi Richard,
>
> thanks for reviewing.
>
> Richard Earnshaw  writes:
>
> [...]
>
>> diff --git a/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-10.c
>> b/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-10.c
>> new file mode 100644
>> index 000..311cf572dd9
>> --- /dev/null
>> +++ b/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-10.c
>> @@ -0,0 +1,10 @@
>> +/* { dg-do compile } */
>> +/* { dg-additional-options " -mbranch-protection=bti+pac-ret" } */
>>
>> This is not enough.  For example, if the testsuite is being run with
>> "-march=armv6-m" as the testrun options, we'll get an error that will
>> cause a test failure.  You need to run a pre-test rule that validates
>> that adding -mbranch-protection is safe.
>
> Right, please find attached the updated patch, it should fix this and
> the mentioned spacing issue.

Scratch that, I think the attached is better.

Sorry for the noise.

  Andrea

>From 0238ad4a53b78b8458ed254d0cb226457b6a76de Mon Sep 17 00:00:00 2001
From: Andrea Corallo 
Date: Mon, 6 Dec 2021 11:39:59 +0100
Subject: [PATCH] [PATCH 5/12] arm: Implement target feature macros for PACBTI

This patch implements target feature macros when PACBTI is enabled
through the -march option or -mbranch-protection.  The target feature
macros __ARM_FEATURE_PAC_DEFAULT and __ARM_FEATURE_BTI_DEFAULT are
specified in ARM ACLE
<https://developer.arm.com/documentation/101028/0012/5--Feature-test-macros?lang=en>
__ARM_FEATURE_PAUTH and __ARM_FEATURE_BTI are specified in the
pull-request <https://github.com/ARM-software/acle/pull/55>.

Approved here
<https://gcc.gnu.org/pipermail/gcc-patches/2021-December/586334.html>.

gcc/

* config/arm/arm-c.c (arm_cpu_builtins): Define
__ARM_FEATURE_BTI_DEFAULT, __ARM_FEATURE_PAC_DEFAULT,
__ARM_FEATURE_PAUTH and __ARM_FEATURE_BTI.

gcc/testsuite/

* lib/target-supports.exp
(check_effective_target_mbranch_protection_ok): New function.
* gcc.target/arm/acle/pacbti-m-predef-2.c: New test.
* gcc.target/arm/acle/pacbti-m-predef-4.c: Likewise.
* gcc.target/arm/acle/pacbti-m-predef-5.c: Likewise.
* gcc.target/arm/acle/pacbti-m-predef-8.c: Likewise.
* gcc.target/arm/acle/pacbti-m-predef-9.c: Likewise.
* gcc.target/arm/acle/pacbti-m-predef-10.c: Likewise.
* gcc.target/arm/acle/pacbti-m-predef-11.c: Likewise.
* gcc.target/arm/acle/pacbti-m-predef-12.c: Likewise.

Co-Authored-By: Tejas Belagod  
---
 gcc/config/arm/arm-c.cc   | 18 +++
 .../gcc.target/arm/acle/pacbti-m-predef-10.c  | 11 +
 .../gcc.target/arm/acle/pacbti-m-predef-11.c  | 11 +
 .../gcc.target/arm/acle/pacbti-m-predef-12.c  | 11 +
 .../gcc.target/arm/acle/pacbti-m-predef-2.c   | 23 +++
 .../gcc.target/arm/acle/pacbti-m-predef-4.c   | 20 
 .../gcc.target/arm/acle/pacbti-m-predef-5.c   | 23 +++
 .../gcc.target/arm/acle/pacbti-m-predef-8.c   | 12 ++
 .../gcc.target/arm/acle/pacbti-m-predef-9.c   | 11 +
 gcc/testsuite/lib/target-supports.exp | 10 
 10 files changed, 150 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-10.c
 create mode 100644 gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-11.c
 create mode 100644 gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-12.c
 create mode 100644 gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-2.c
 create mode 100644 gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-4.c
 create mode 100644 gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-5.c
 create mode 100644 gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-8.c
 create mode 100644 gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-9.c

diff --git a/gcc/config/arm/arm-c.cc b/gcc/config/arm/arm-c.cc
index a8697b8c62f..190099b2c37 100644
--- a/gcc/config/arm/arm-c.cc
+++ b/gcc/config/arm/arm-c.cc
@@ -212,6 +212,24 @@ arm_cpu_builtins (struct cpp_reader* pfile)
   def_or_undef_macro (pfile, "__ARM_FEATURE_COMPLEX", TARGET_COMPLEX);
   def_or_undef_macro (pfile, "__ARM_32BIT_STATE", TARGET_32BIT);
 
+  def_or_undef_macro (pfile, "__ARM_FEATURE_PAUTH", TARGET_HAVE_PACBTI);
+  def_or_undef_macro (pfile, "__ARM_FEATURE_BTI", TARGET_HAVE_PACBTI);
+  def_or_undef_macro (pfile, "__ARM_FEATURE_BTI_DEFAULT",
+ aarch_enable_bti == 1);
+
+  cpp_undef (pfile, "__ARM_FEATURE_PAC_DEFAULT");
+  if (aarch_ra_sign_scope != AARCH_FUNCTION_NONE)
+  {
+unsigned int pac = 1;
+
+gcc_assert (aarch_ra_sign_key == AARCH_KEY_A);
+
+if (aarch_ra_sign_scope == AARCH_FUNCTION_ALL)
+  pac |= 0x4;
+
+builtin_define_with_int_value ("__ARM_FEATURE_PAC_DEFAULT", pac);
+  }
+

[PATCH 7/12 V2] arm: Emit build attributes for PACBTI target feature

[Andrea Corallo via Gcc-patches]

Richard Earnshaw  writes:

> On 28/04/2022 10:45, Andrea Corallo via Gcc-patches wrote:
>> This patch emits assembler directives for PACBTI build attributes as
>> defined by the
>> ABI.
>> <https://github.com/ARM-software/abi-aa/releases/download/2021Q1/addenda32.pdf>
>> gcc/ChangeLog:
>>  * config/arm/arm.c (arm_file_start): Emit EABI attributes for
>>  Tag_PAC_extension, Tag_BTI_extension, TAG_BTI_use, TAG_PACRET_use.
>
> This bit is OK.
>
>> gcc/testsuite/ChangeLog:
>>  * gcc.target/arm/acle/pacbti-m-predef-1.c: New test.
>>  * gcc.target/arm/acle/pacbti-m-predef-3: Likewise.
>>  * gcc.target/arm/acle/pacbti-m-predef-6.c: Likewise.
>>  * gcc.target/arm/acle/pacbti-m-predef-7.c: Likewise.
>
> These tests contain directives like:
>
> +/* { dg-additional-options " -mbranch-protection=pac-ret+bti
> --save-temps" } */
>
> But they don't check that the architecture permits this (it has to be
> armv8-m.main or later).

Hi Richard,

please find attached the respinned version of the patch.

BR

  Andrea

>From b89ac2dc737593a290345cb96c5d9b048e731bf4 Mon Sep 17 00:00:00 2001
From: Andrea Corallo 
Date: Mon, 6 Dec 2021 11:42:24 +0100
Subject: [PATCH] [PATCH 7/12] arm: Emit build attributes for PACBTI target
 feature

This patch emits assembler directives for PACBTI build attributes as
defined by the
ABI.

<https://github.com/ARM-software/abi-aa/releases/download/2021Q1/addenda32.pdf>

gcc/ChangeLog:

* config/arm/arm.c (arm_file_start): Emit EABI attributes for
Tag_PAC_extension, Tag_BTI_extension, TAG_BTI_use, TAG_PACRET_use.

gcc/testsuite/ChangeLog:

* gcc.target/arm/acle/pacbti-m-predef-1.c: New test.
* gcc.target/arm/acle/pacbti-m-predef-3: Likewise.
* gcc.target/arm/acle/pacbti-m-predef-6.c: Likewise.
* gcc.target/arm/acle/pacbti-m-predef-7.c: Likewise.

Co-Authored-By: Tejas Belagod  
---
 gcc/config/arm/arm.cc  | 18 ++
 .../gcc.target/arm/acle/pacbti-m-predef-1.c| 17 +
 .../gcc.target/arm/acle/pacbti-m-predef-3.c| 17 +
 .../gcc.target/arm/acle/pacbti-m-predef-6.c| 16 
 .../gcc.target/arm/acle/pacbti-m-predef-7.c| 17 +
 5 files changed, 85 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-1.c
 create mode 100644 gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-3.c
 create mode 100644 gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-6.c
 create mode 100644 gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-7.c

diff --git a/gcc/config/arm/arm.cc b/gcc/config/arm/arm.cc
index 0068817b0f2..ceec14f84b6 100644
--- a/gcc/config/arm/arm.cc
+++ b/gcc/config/arm/arm.cc
@@ -28349,6 +28349,8 @@ static void
 arm_file_start (void)
 {
   int val;
+  bool pac = (aarch_ra_sign_scope != AARCH_FUNCTION_NONE);
+  bool bti = (aarch_enable_bti == 1);
 
   arm_print_asm_arch_directives
 (asm_out_file, TREE_TARGET_OPTION (target_option_default_node));
@@ -28419,6 +28421,22 @@ arm_file_start (void)
arm_emit_eabi_attribute ("Tag_ABI_FP_16bit_format", 38,
 (int) arm_fp16_format);
 
+  if (TARGET_HAVE_PACBTI)
+   {
+ arm_emit_eabi_attribute ("Tag_PAC_extension", 50, 2);
+ arm_emit_eabi_attribute ("Tag_BTI_extension", 52, 2);
+   }
+  else if (pac || bti)
+   {
+ arm_emit_eabi_attribute ("Tag_PAC_extension", 50, 1);
+ arm_emit_eabi_attribute ("Tag_BTI_extension", 52, 1);
+   }
+
+  if (bti)
+arm_emit_eabi_attribute ("TAG_BTI_use", 74, 1);
+  if (pac)
+   arm_emit_eabi_attribute ("TAG_PACRET_use", 76, 1);
+
   if (arm_lang_output_object_attributes_hook)
arm_lang_output_object_attributes_hook();
 }
diff --git a/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-1.c 
b/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-1.c
new file mode 100644
index 000..225b44de80a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-1.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target mbranch_protection_ok } */
+/* { dg-additional-options "-march=armv8.1-m.main 
-mbranch-protection=pac-ret+bti --save-temps" } */
+
+#if !defined (__ARM_FEATURE_BTI_DEFAULT)
+#error "Feature test macro __ARM_FEATURE_BTI_DEFAULT should be defined."
+#endif
+
+#if !defined (__ARM_FEATURE_PAC_DEFAULT)
+#error "Feature test macro __ARM_FEATURE_PAC_DEFAULT should be defined."
+#endif
+
+/* { dg-final { scan-assembler-not "\.arch_extension pacbti" } } */
+/* { dg-final { scan-assembler "\.eabi_attribute 50, 1" } } */
+/* { dg-final { scan-assembler "\.eabi_attribute 52, 1" } } */
+/* { dg-final { scan-

Re: [PATCH 9/12 V2] arm: Make libgcc bti compatible

[Andrea Corallo via Gcc-patches]

Richard Earnshaw  writes:

> On 21/07/2022 10:17, Andrea Corallo via Gcc-patches wrote:
>> Richard Earnshaw  writes:
>> 
>>> On 28/04/2022 10:48, Andrea Corallo via Gcc-patches wrote:
>>>> This change add bti instructions at the beginning of arm specific
>>>> libgcc hand written assembly routines.
>>>> 2022-03-31  Andrea Corallo  
>>>>* libgcc/config/arm/crti.S (FUNC_START): Add bti instruction
>>>> if
>>>>necessary.
>>>>* libgcc/config/arm/lib1funcs.S (THUMB_FUNC_START, FUNC_START):
>>>>Likewise.
>>>>
>>>
>>> +#if defined(__ARM_FEATURE_BTI)
>>>
>>> Wouldn't it be better to use __ARM_FEATURE_BTI_DEFAULT?  That way we
>>> only get BTI instructions in multilib variants that have asked for
>>> BTI.
>>>
>>> R.
>> Hi Richard,
>> good point, yes I think so.
>> Please find attached the updated patch.
>> BR
>>Andrea
>> 
>
> I've been pondering this patch.  The way it is implemented would put a
> BTI instruction at the start of every assembler routine in libgcc.
> But the vast majority of functions in libgcc cannot have their address
> taken, so a BTI isn't needed (BTI is only needed when an indirect jump
> could be used).  So I wonder if we really need to do this so
> aggressively?
>
> Perhaps a better approach would be to define a macro (eg MAYBEBTI)
> which expands a BTI if the compilation requires it and nothing
> otherwise), and then manually insert that in any functions that really
> need this (if any).

I guess the main downside of this approach would be the maintanace
burden, we'll have to remember forever that every time an asm function
is called by function pointer we have to add the bti landing pad
manually, otherwise this will be broken when pacbti enabled. WDYT?

If we want to go this way I'll start reworking the patch in this
direction (tho this might not be trivial).

BR

  Andrea

Re: [PATCH 10/12 V2] arm: Implement cortex-M return signing address codegen

[Andrea Corallo via Gcc-patches]

Richard Earnshaw  writes:

[...]

> +(define_insn "pac_nop"
> +  [(set (reg:SI IP_REGNUM)
> + (unspec:SI [(reg:SI SP_REGNUM) (reg:SI LR_REGNUM)]
> +   UNSPEC_PAC_NOP))]
> +  "TARGET_THUMB2"
> +  "pac\t%|ip, %|lr, %|sp"
> +  [(set_attr "length" "2")])
>
> This pattern is missing a type.

Which type do you think is missing?

> The length is also incorrect as the
> instruction is 32-bits (4 bytes).

Ack.

> Similarly for the other
> instructions below.  Also, you need to mark them as incompatible with
> conditional execution (they're constrained-unpredictable in IT
> blocks).

I guess this would translate in setting it with '(set_attr "predicable" "no")'

But isn't this already the default?

Thanks

  Andrea

Re: [PATCH] [arm] complete vmsr/vmrs blank and case adjustments

[Andrea Corallo via Gcc-patches]

Alexandre Oliva  writes:

> Back in September last year, some of the vmsr and vmrs patterns had an
> extraneous blank removed, and the case of register names lowered, but
> another instance remained, and so did a few testcases.

[...]

Hi Alexandre,

I'm not approver but LGTM, thanks for fixing this.

  Andrea

Re: [PATCH] [PR104882] [arm] require mve hw for mve run test

[Andrea Corallo via Gcc-patches]

Alexandre Oliva via Gcc-patches  writes:

> The pr104882.c test is an execution test, but arm_v8_1m_mve_ok only
> tests for compile-time support.  Add a requirement for mve hardware.
>
> Regstrapped on x86_64-linux-gnu.
> Tested on arm-vxworks7 (gcc-12) and arm-eabi (trunk).  Ok to install?
>
> for  gcc/testsuite/ChangeLog
>
>   PR target/104882
>   * gcc.target/arm/simd/pr104882.c: Require mve hardware.
> ---
>  gcc/testsuite/gcc.target/arm/simd/pr104882.c |1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/gcc/testsuite/gcc.target/arm/simd/pr104882.c 
> b/gcc/testsuite/gcc.target/arm/simd/pr104882.c
> index ae9709af42f22..1ea7a14836f54 100644
> --- a/gcc/testsuite/gcc.target/arm/simd/pr104882.c
> +++ b/gcc/testsuite/gcc.target/arm/simd/pr104882.c
> @@ -1,4 +1,5 @@
>  /* { dg-do run } */
> +/* { dg-require-effective-target arm_mve_hw } */
>  /* { dg-require-effective-target arm_v8_1m_mve_ok } */
>  /* { dg-add-options arm_v8_1m_mve } */
>  /* { dg-additional-options "-O2" } */

Hi Alexandre,

no approver here but LGTM, thanks.

  Andrea

Re: [PATCH] arm: [testuiste] fix ivopts.c target test [PR96372]

[Andrea Corallo via Gcc-patches]

Kyrylo Tkachov  writes:

[...]

> Ah ok, then it's fine to be consistent.
> The patch is ok.
> Thanks,
> Kyrill

Thanks, into master as 0568f801eff

  Andrea

[PATCH] arm: Low overhead loop handle long range branches [PR98931]

[Andrea Corallo via Gcc-patches]

Hi all,

this is to fix PR98931 where the LE (loop end, Armv8.1-M low overhead
loops) instruction cannot cover sufficently long branches.

In this case we emit as an alternative:

subslr, #1
bne label

arm-none-eabi regtested, arm-none-linux-gnueabihf boostrapped.

Okay for trunk?

Regards

  Andrea
  
>From c8216ed1313d670e79b28141dadd644e698c83cf Mon Sep 17 00:00:00 2001
From: Andrea Corallo 
Date: Wed, 3 Feb 2021 15:21:54 +0100
Subject: [PATCH] arm: Low overhead loop handle long range branches [PR98931]

gcc/ChangeLog

2021-02-05  Andrea Corallo  

* config/arm/thumb2.md: Generate alternative sequence to
handle long range branches.

gcc/testsuite/Changelog

2021-02-08  Andrea Corallo  

 * gcc.target/arm/pr98931.c: New testcase.
---
 gcc/config/arm/thumb2.md   | 13 -
 gcc/testsuite/gcc.target/arm/pr98931.c | 17 +
 2 files changed, 29 insertions(+), 1 deletion(-)
 create mode 100644 gcc/testsuite/gcc.target/arm/pr98931.c

diff --git a/gcc/config/arm/thumb2.md b/gcc/config/arm/thumb2.md
index bd53bf320de..2646926d3c1 100644
--- a/gcc/config/arm/thumb2.md
+++ b/gcc/config/arm/thumb2.md
@@ -1719,7 +1719,18 @@
   (set (reg:SI LR_REGNUM)
(plus:SI (reg:SI LR_REGNUM) (const_int -1)))])]
   "TARGET_32BIT && TARGET_HAVE_LOB"
-  "le\t%|lr, %l0")
+  "*
+  if (get_attr_length (insn) == 4)
+return \"le\\t%|lr, %l0\";
+  else
+return \"subs\\t%|lr, #1\;bne\\t%l0\";
+  "
+  [(set (attr "length")
+(if_then_else
+(lt (minus (pc) (match_dup 0)) (const_int 1024))
+   (const_int 4)
+   (const_int 6)))
+   (set_attr "type" "branch")])
 
 (define_expand "doloop_begin"
   [(match_operand 0 "" "")
diff --git a/gcc/testsuite/gcc.target/arm/pr98931.c 
b/gcc/testsuite/gcc.target/arm/pr98931.c
new file mode 100644
index 000..313876a3912
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/pr98931.c
@@ -0,0 +1,17 @@
+/* { dg-do assemble } */
+/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-marm" 
"-mcpu=*" } } */
+/* { dg-options "-march=armv8.1-m.main -O3 
--param=max-completely-peeled-insns=1300 --save-temps" } */
+
+extern long long a[][20][26][26][22];
+
+void
+foo ()
+{
+  for (short d = 0; d + 1; d++)
+for (unsigned e = 0; e < 25; e += 4)
+  for (unsigned f = 0; f < 25; f += 4)
+for (int g = 0; g < 21; g += 4)
+  a[4][d][e][f][g] = 0;
+}
+
+/* { dg-final { scan-assembler-not {le\slr,\s\S*} } } */
-- 
2.20.1

Re: [PATCH v2] arm: Low overhead loop handle long range branches [PR98931]

[Andrea Corallo via Gcc-patches]

Jakub Jelinek  writes:

> On Tue, Feb 09, 2021 at 03:09:43PM +0100, Jakub Jelinek via Gcc-patches wrote:
>> >"TARGET_32BIT && TARGET_HAVE_LOB"
>> > -  "le\t%|lr, %l0")
>> > +  "*
>> > +  if (get_attr_length (insn) == 4)
>> > +return \"le\\t%|lr, %l0\";
>> > +  else
>> > +return \"subs\\t%|lr, #1\;bne\\t%l0\";
>> > +  "
>> 
>> Why not
>> {
>>   if (get_attr_length (insn) == 4)
>> return "le\t%|lr, %l0";
>>   else
>> return "subs\t%|lr, #1;bne\t%l0";
>> }
>> instead?  Seems the arm backend uses "*..." more than the more modern {},
>> but one needs to backslash prefix a lot which makes it less readable?
>
> Where "more modern" is introduced 19.5 years ago ;)
>
>   Jakub

I guess we really like traditions :)

Attached second version addressing this.

Thanks

  Andrea

>From 7434e9519929affe8bcb7f4df2a775612cba0b18 Mon Sep 17 00:00:00 2001
From: Andrea Corallo 
Date: Wed, 3 Feb 2021 15:21:54 +0100
Subject: [PATCH] arm: Low overhead loop handle long range branches [PR98931]

gcc/ChangeLog

2021-02-05  Andrea Corallo  

* config/arm/thumb2.md: Generate alternative sequence to
handle long range branches.

gcc/testsuite/Changelog

2021-02-08  Andrea Corallo  

 * gcc.target/arm/pr98931.c: New testcase.
---
 gcc/config/arm/thumb2.md   | 13 -
 gcc/testsuite/gcc.target/arm/pr98931.c | 17 +
 2 files changed, 29 insertions(+), 1 deletion(-)
 create mode 100644 gcc/testsuite/gcc.target/arm/pr98931.c

diff --git a/gcc/config/arm/thumb2.md b/gcc/config/arm/thumb2.md
index bd53bf320de..a032448654a 100644
--- a/gcc/config/arm/thumb2.md
+++ b/gcc/config/arm/thumb2.md
@@ -1719,7 +1719,18 @@
   (set (reg:SI LR_REGNUM)
(plus:SI (reg:SI LR_REGNUM) (const_int -1)))])]
   "TARGET_32BIT && TARGET_HAVE_LOB"
-  "le\t%|lr, %l0")
+  {
+if (get_attr_length (insn) == 4)
+  return "le\t%|lr, %l0";
+else
+  return "subs\t%|lr, #1;bne\t%l0";
+  }
+  [(set (attr "length")
+(if_then_else
+(lt (minus (pc) (match_dup 0)) (const_int 1024))
+   (const_int 4)
+   (const_int 6)))
+   (set_attr "type" "branch")])
 
 (define_expand "doloop_begin"
   [(match_operand 0 "" "")
diff --git a/gcc/testsuite/gcc.target/arm/pr98931.c 
b/gcc/testsuite/gcc.target/arm/pr98931.c
new file mode 100644
index 000..313876a3912
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/pr98931.c
@@ -0,0 +1,17 @@
+/* { dg-do assemble } */
+/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-marm" 
"-mcpu=*" } } */
+/* { dg-options "-march=armv8.1-m.main -O3 
--param=max-completely-peeled-insns=1300 --save-temps" } */
+
+extern long long a[][20][26][26][22];
+
+void
+foo ()
+{
+  for (short d = 0; d + 1; d++)
+for (unsigned e = 0; e < 25; e += 4)
+  for (unsigned f = 0; f < 25; f += 4)
+for (int g = 0; g < 21; g += 4)
+  a[4][d][e][f][g] = 0;
+}
+
+/* { dg-final { scan-assembler-not {le\slr,\s\S*} } } */
-- 
2.20.1

Re: [PATCH v2] arm: Low overhead loop handle long range branches [PR98931]

[Andrea Corallo via Gcc-patches]

"Richard Earnshaw (lists)"  writes:

> On 09/02/2021 16:27, Andrea Corallo via Gcc-patches wrote:
>> Jakub Jelinek  writes:
>> 
>>> On Tue, Feb 09, 2021 at 03:09:43PM +0100, Jakub Jelinek via Gcc-patches 
>>> wrote:
>>>>>"TARGET_32BIT && TARGET_HAVE_LOB"
>>>>> -  "le\t%|lr, %l0")
>>>>> +  "*
>>>>> +  if (get_attr_length (insn) == 4)
>>>>> +return \"le\\t%|lr, %l0\";
>>>>> +  else
>>>>> +return \"subs\\t%|lr, #1\;bne\\t%l0\";
>>>>> +  "
>>>>
>>>> Why not
>>>> {
>>>>   if (get_attr_length (insn) == 4)
>>>> return "le\t%|lr, %l0";
>>>>   else
>>>> return "subs\t%|lr, #1;bne\t%l0";
>>>> }
>>>> instead?  Seems the arm backend uses "*..." more than the more modern {},
>>>> but one needs to backslash prefix a lot which makes it less readable?
>>>
>>> Where "more modern" is introduced 19.5 years ago ;)
>>>
>>> Jakub
>> 
>> I guess we really like traditions :)
>> 
>> Attached second version addressing this.
>> 
>> Thanks
>> 
>>   Andrea
>> 
>
> You're missing a clobber of the condition codes in the RTL.  This wasn't
> needed before, but is now.
>
> R.

Hi Richard,

thanks for reviewing, I guess this is going to be a good learning moment
for me.

What we originally expand is:

(insn 2396 2360 2397 3 (parallel [
(set (reg:CC_NZ 100 cc)
(compare:CC_NZ (plus:SI (reg:SI 14 lr)
(const_int -1 [0x]))
(const_int 0 [0])))
(set (reg:SI 14 lr)
(plus:SI (reg:SI 14 lr)
(const_int -1 [0x])))
]) "p1.c":4:21 -1
 (nil))
(jump_insn 2397 2396 2365 3 (set (pc)
(if_then_else (ne (reg:CC_NZ 100 cc)
(const_int 0 [0]))
(label_ref:SI 2361)
(pc))) "p1.c":4:21 273 {arm_cond_branch}
 (expr_list:REG_DEAD (reg:CC_NZ 100 cc)
(int_list:REG_BR_PROB 1062895996 (nil)))
 -> 2361)

Combine recognizing cc:CC_NZ as a dead reg and rewriting the two insns
as:

(jump_insn 2397 2396 2365 3 (parallel [
(set (pc)
(if_then_else (ne (reg:SI 14 lr)
(const_int 1 [0x1]))
(label_ref:SI 2361)
(pc)))
(set (reg:SI 14 lr)
(plus:SI (reg:SI 14 lr)
(const_int -1 [0x])))
]) "p1.c":4:21 1047 {*doloop_end_internal}
 (int_list:REG_BR_PROB 1062895996 (nil))
 -> 2361)

I originally thought that because the write of reg:CC_NZ is explicit in
the first pattern we expand this was sufficient, but I now understand
I'm wrong and combine should produce a pattern still expressing this.
Now the question is how to do that.

If I add the clobber '(clobber (reg:CC CC_REGNUM))' inside the parallel
of *doloop_end_internal as last element of the vector we ICE in
'add_clobbers' called during combine, apparently 'add_clobbers' does not
handle the insn_code_number.

If I add it as second element of the parallel combine is not combining
the two insns.

If I place the clobber outside the parallel as a second element of the
insn vector combine is crashing in 'recog_for_combine_1'.

So the question is probably: where should the clobber be positioned
canonically to have this working?

Thanks!

  Andrea

[PATCH v3] arm: Low overhead loop handle long range branches [PR98931]

[Andrea Corallo via Gcc-patches]

Andrea Corallo via Gcc-patches  writes:

> "Richard Earnshaw (lists)"  writes:
>
>> On 09/02/2021 16:27, Andrea Corallo via Gcc-patches wrote:
>>> Jakub Jelinek  writes:
>>> 
>>>> On Tue, Feb 09, 2021 at 03:09:43PM +0100, Jakub Jelinek via Gcc-patches 
>>>> wrote:
>>>>>>"TARGET_32BIT && TARGET_HAVE_LOB"
>>>>>> -  "le\t%|lr, %l0")
>>>>>> +  "*
>>>>>> +  if (get_attr_length (insn) == 4)
>>>>>> +return \"le\\t%|lr, %l0\";
>>>>>> +  else
>>>>>> +return \"subs\\t%|lr, #1\;bne\\t%l0\";
>>>>>> +  "
>>>>>
>>>>> Why not
>>>>> {
>>>>>   if (get_attr_length (insn) == 4)
>>>>> return "le\t%|lr, %l0";
>>>>>   else
>>>>> return "subs\t%|lr, #1;bne\t%l0";
>>>>> }
>>>>> instead?  Seems the arm backend uses "*..." more than the more modern {},
>>>>> but one needs to backslash prefix a lot which makes it less readable?
>>>>
>>>> Where "more modern" is introduced 19.5 years ago ;)
>>>>
>>>>Jakub
>>> 
>>> I guess we really like traditions :)
>>> 
>>> Attached second version addressing this.
>>> 
>>> Thanks
>>> 
>>>   Andrea
>>> 
>>
>> You're missing a clobber of the condition codes in the RTL.  This wasn't
>> needed before, but is now.
>>
>> R.
>
> Hi Richard,
>
> thanks for reviewing, I guess this is going to be a good learning moment
> for me.
>
> What we originally expand is:
>
> (insn 2396 2360 2397 3 (parallel [
> (set (reg:CC_NZ 100 cc)
> (compare:CC_NZ (plus:SI (reg:SI 14 lr)
> (const_int -1 [0x]))
> (const_int 0 [0])))
> (set (reg:SI 14 lr)
> (plus:SI (reg:SI 14 lr)
> (const_int -1 [0x])))
> ]) "p1.c":4:21 -1
>  (nil))
> (jump_insn 2397 2396 2365 3 (set (pc)
> (if_then_else (ne (reg:CC_NZ 100 cc)
> (const_int 0 [0]))
> (label_ref:SI 2361)
> (pc))) "p1.c":4:21 273 {arm_cond_branch}
>  (expr_list:REG_DEAD (reg:CC_NZ 100 cc)
> (int_list:REG_BR_PROB 1062895996 (nil)))
>  -> 2361)
>
> Combine recognizing cc:CC_NZ as a dead reg and rewriting the two insns
> as:
>
> (jump_insn 2397 2396 2365 3 (parallel [
> (set (pc)
> (if_then_else (ne (reg:SI 14 lr)
> (const_int 1 [0x1]))
> (label_ref:SI 2361)
> (pc)))
> (set (reg:SI 14 lr)
> (plus:SI (reg:SI 14 lr)
> (const_int -1 [0x])))
> ]) "p1.c":4:21 1047 {*doloop_end_internal}
>  (int_list:REG_BR_PROB 1062895996 (nil))
>  -> 2361)
>
> I originally thought that because the write of reg:CC_NZ is explicit in
> the first pattern we expand this was sufficient, but I now understand
> I'm wrong and combine should produce a pattern still expressing this.
> Now the question is how to do that.
>
> If I add the clobber '(clobber (reg:CC CC_REGNUM))' inside the parallel
> of *doloop_end_internal as last element of the vector we ICE in
> 'add_clobbers' called during combine, apparently 'add_clobbers' does not
> handle the insn_code_number.
>
> If I add it as second element of the parallel combine is not combining
> the two insns.
>
> If I place the clobber outside the parallel as a second element of the
> insn vector combine is crashing in 'recog_for_combine_1'.
>
> So the question is probably: where should the clobber be positioned
> canonically to have this working?
>
> Thanks!
>
>   Andrea

Righ, I've been explained by a knowledgeable colleague that the
'parallel' is implicit in the 'define_insn' and there's no need to
express it (interestgly this is confusing the code generating
'add_clobbers').

The attached patch rewrites the pattern as such and adds the missing
clobber.

Tests are running, okay for trunk when done with these?

Regards

  Andrea

>From c822f9374f1c16a0f863ca521fd87a350b616db4 Mon Sep 17 00:00:00 2001
From: Andrea Corallo 
Date: Wed, 3 Feb 2021 15:21:54 +0100
Subject: [PATCH] arm: Low overhead loop handle long range branches [PR98931]

gcc

Re: [PATCH v3] arm: Low overhead loop handle long range branches [PR98931]

[Andrea Corallo via Gcc-patches]

"Richard Earnshaw (lists)"  writes:

[...]

> +  [(set (attr "length")
> +(if_then_else
> +(lt (minus (pc) (match_dup 0)) (const_int 1024))
> + (const_int 4)
> + (const_int 6)))
> +   (set_attr "type" "branch")])
>
> Shouldn't that be using "ltu" rather than "lt", so that if, for some
> reason, the branch has been retargeted to come after the branch, then
> the test will still fail and we'll get the comparison variant back.

Right good point

> Otherwise OK.
>
> R.

Installed into trunk with the suggestion as 38c5703449c.

Thanks!

  Andrea

Re: [committed] jit: fix ICE on BUILT_IN_TRAP [PR99126]

[Andrea Corallo via Gcc-patches]

David Malcolm via Gcc-patches  writes:

> I tried several approaches to fixing this; this seemed the
> least invasive.

Hi Dave,

thanks for fixing this.

I do have a trivial question: are we guaranteed that the middle-end will
not try to add any build-in other than a trap?

Regards

  Andrea

Re: [committed] jit: fix ICE on BUILT_IN_TRAP [PR99126]

[Andrea Corallo via Gcc-patches]

Andrea Corallo via Gcc-patches  writes:

> David Malcolm via Gcc-patches  writes:
>
>> I tried several approaches to fixing this; this seemed the
>> least invasive.
>
> Hi Dave,
>
> thanks for fixing this.
>
> I do have a trivial question: are we guaranteed that the middle-end will
> not try to add any build-in other than a trap?

Ah also, shouldn't the fix be also back-ported?

Thanks

  Andrea

Re: [PATCH PR96375] arm: Fix testcase selection for Low Overhead Loop tests

[Andrea Corallo via Gcc-patches]

Andrea Corallo  writes:

> Hi all,
>
> I'd like to submit the following patch to fix PR96375 ([11 regression]
> arm/lob[2-5].c fail on some configurations).
>
> It fix the observed regression making sure -mthumb is always used and
> allowing Low Overhead Loop tests to be executed only on cortex-M profile
> targets.
>
> Does not introduce regressions in my testing and fix the reported one
> according to Christophe (in Cc).
>
> Okay for trunk?
>
> Thanks
>
>   Andrea
>
> 2020-07-31  Andrea Corallo  
>
>   * gcc.target/arm/lob1.c: Fix missing flag.
>   * gcc.target/arm/lob2.c: Likewise.
>   * gcc.target/arm/lob3.c: Likewise.
>   * gcc.target/arm/lob4.c: Likewise.
>   * gcc.target/arm/lob5.c: Likewise.
>   * gcc.target/arm/lob6.c: Likewise.
>   * lib/target-supports.exp
>   (check_effective_target_arm_v8_1_lob_ok): Return 1 only for
>   cortex-m targets, add '-mthumb' flag.

I really forgot to ping this patch (I'm reattaching it for convenience).

It still applies cleanly so... ping :)

>From 7056cfbde6ccf43eaf8651af2b4a09a31c9276de Mon Sep 17 00:00:00 2001
From: Andrea Corallo 
Date: Fri, 31 Jul 2020 14:52:24 +0100
Subject: [PATCH] arm: Fix testcase selection for Low Overhead Loop tests
 [PR96375]

gcc/testsuite/ChangeLog

2020-07-31  Andrea Corallo  

* gcc.target/arm/lob1.c: Fix missing flag.
* gcc.target/arm/lob2.c: Likewise.
* gcc.target/arm/lob3.c: Likewise.
* gcc.target/arm/lob4.c: Likewise.
* gcc.target/arm/lob5.c: Likewise.
* gcc.target/arm/lob6.c: Likewise.
* lib/target-supports.exp
(check_effective_target_arm_v8_1_lob_ok): Return 1 only for
cortex-m targets, add '-mthumb' flag.
---
 gcc/testsuite/gcc.target/arm/lob1.c   | 2 +-
 gcc/testsuite/gcc.target/arm/lob2.c   | 2 +-
 gcc/testsuite/gcc.target/arm/lob3.c   | 2 +-
 gcc/testsuite/gcc.target/arm/lob4.c   | 2 +-
 gcc/testsuite/gcc.target/arm/lob5.c   | 2 +-
 gcc/testsuite/gcc.target/arm/lob6.c   | 2 +-
 gcc/testsuite/lib/target-supports.exp | 4 ++--
 7 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/gcc/testsuite/gcc.target/arm/lob1.c 
b/gcc/testsuite/gcc.target/arm/lob1.c
index b92dc551d50..ba5c82cd55c 100644
--- a/gcc/testsuite/gcc.target/arm/lob1.c
+++ b/gcc/testsuite/gcc.target/arm/lob1.c
@@ -3,7 +3,7 @@
 /* { dg-do run } */
 /* { dg-require-effective-target arm_v8_1_lob_ok } */
 /* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-marm" 
"-mcpu=*" } } */
-/* { dg-options "-march=armv8.1-m.main -O3 --save-temps" } */
+/* { dg-options "-march=armv8.1-m.main -mthumb -O3 --save-temps" } */
 #include 
 #include "lob.h"
 
diff --git a/gcc/testsuite/gcc.target/arm/lob2.c 
b/gcc/testsuite/gcc.target/arm/lob2.c
index 1fe9a9d82bb..fdeb2686f51 100644
--- a/gcc/testsuite/gcc.target/arm/lob2.c
+++ b/gcc/testsuite/gcc.target/arm/lob2.c
@@ -2,7 +2,7 @@
if a non-inlineable function call takes place inside the loop.  */
 /* { dg-do compile } */
 /* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-marm" 
"-mcpu=*" } } */
-/* { dg-options "-march=armv8.1-m.main -O3 --save-temps" } */
+/* { dg-options "-march=armv8.1-m.main -mthumb -O3 --save-temps" } */
 #include 
 #include "lob.h"
 
diff --git a/gcc/testsuite/gcc.target/arm/lob3.c 
b/gcc/testsuite/gcc.target/arm/lob3.c
index 17cba007ccb..70314ea84b3 100644
--- a/gcc/testsuite/gcc.target/arm/lob3.c
+++ b/gcc/testsuite/gcc.target/arm/lob3.c
@@ -2,7 +2,7 @@
if causes VFP emulation library calls to happen inside the loop.  */
 /* { dg-do compile } */
 /* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-marm" 
"-mcpu=*" } } */
-/* { dg-options "-march=armv8.1-m.main -O3 --save-temps -mfloat-abi=soft" } */
+/* { dg-options "-march=armv8.1-m.main -mthumb -O3 --save-temps 
-mfloat-abi=soft" } */
 /* { dg-require-effective-target arm_softfloat } */
 #include 
 #include "lob.h"
diff --git a/gcc/testsuite/gcc.target/arm/lob4.c 
b/gcc/testsuite/gcc.target/arm/lob4.c
index 444a2c7b4bf..792f352d682 100644
--- a/gcc/testsuite/gcc.target/arm/lob4.c
+++ b/gcc/testsuite/gcc.target/arm/lob4.c
@@ -2,7 +2,7 @@
if LR is modified within the loop.  */
 /* { dg-do compile } */
 /* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-marm" 
"-mcpu=*" } } */
-/* { dg-options "-march=armv8.1-m.main -O3 --save-temps -mfloat-abi=soft" } */
+/* { dg-options "-march=armv8.1-m.main -mthumb -O3 --save-temps 
-mfloat-abi=soft" } */
 /* { dg-require-effective-target arm_softfloat } */
 #include 
 #include "lob.h"
diff --git a/gcc/testsuite/gcc.target/arm/lob5.c 
b/gcc/testsuite/gcc.target/arm/lob5.c
index c4f46e41532..1a6adf1e28e 100644
--- a/gcc/testsuite/gcc.target/arm/lob5.c
+++ b/gcc/testsuite/gcc.target/arm/lob5.c
@@ -3,7 +3,7 @@
therefore is not optimizable.  Outer loops are not optimized.  */
 /* { dg-do compile } */
 /* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-marm" 
"-mcpu=*" } } */
-/* { dg-options "-march=armv8.1-m.main -O3 -

Re: [PATCH PR96375] arm: Fix testcase selection for Low Overhead Loop tests

[Andrea Corallo via Gcc-patches]

Kyrylo Tkachov  writes:

>> -Original Message-
>> From: Andrea Corallo 
>> Sent: 01 October 2020 15:36
>> To: gcc-patches@gcc.gnu.org
>> Cc: Richard Earnshaw ; Kyrylo Tkachov
>> ; Christophe Lyon 
>> Subject: Re: [PATCH PR96375] arm: Fix testcase selection for Low Overhead
>> Loop tests
>> 
>> Andrea Corallo  writes:
>> 
>> > Hi all,
>> >
>> > I'd like to submit the following patch to fix PR96375 ([11 regression]
>> > arm/lob[2-5].c fail on some configurations).
>> >
>> > It fix the observed regression making sure -mthumb is always used and
>> > allowing Low Overhead Loop tests to be executed only on cortex-M profile
>> > targets.
>> >
>> > Does not introduce regressions in my testing and fix the reported one
>> > according to Christophe (in Cc).
>> >
>> > Okay for trunk?
>
> Ok.
> Thanks,
> Kyrill

Hi Kyrill,

Installed as 968ec08efef.

Thanks!

  Andrea

[PATCH 10/15 V2] arm: Implement cortex-M return signing address codegen

[Andrea Corallo via Gcc-patches]

Hi all,

this patch enables address return signature and verification based on
Armv8.1-M Pointer Authentication [1].

To sign the return address, we use the PAC R12, LR, SP instruction
upon function entry.  This is signing LR using SP and storing the
result in R12.  R12 will be pushed into the stack.

During function epilogue R12 will be popped and AUT R12, LR, SP will
be used to verify that the content of LR is still valid before return.

Here an example of PAC instrumented function prologue and epilogue:

void foo (void);

int main()
{
  foo ();
  return 0;
}

Compiled with '-march=armv8.1-m.main -mbranch-protection=pac-ret
-mthumb' translates into:

main:
pac ip, lr, sp
push{r3, r7, ip, lr}
add r7, sp, #0
bl  foo
movsr3, #0
mov r0, r3
pop {r3, r7, ip, lr}
aut ip, lr, sp
bx  lr

The patch also takes care of generating a PACBTI instruction in place
of the sequence BTI+PAC when Branch Target Identification is enabled
contextually.

Ex. the previous example compiled with '-march=armv8.1-m.main
-mbranch-protection=pac-ret+bti -mthumb' translates into:

main:
pacbti  ip, lr, sp
push{r3, r7, ip, lr}
add r7, sp, #0
bl  foo
movsr3, #0
mov r0, r3
pop {r3, r7, ip, lr}
aut ip, lr, sp
bx  lr

As part of previous upstream suggestions a test for varargs has been
added and '-mtpcs-frame' is deemed being incompatible with this return
signing address feature being introduced.

[1] 


gcc/Changelog

2021-11-03  Andrea Corallo  

* config/arm/arm.c: (arm_compute_frame_layout)
(arm_expand_prologue, thumb2_expand_return, arm_expand_epilogue)
(arm_conditional_register_usage): Update for pac codegen.
(arm_current_function_pac_enabled_p): New function.
* config/arm/arm.md (pac_ip_lr_sp, pacbti_ip_lr_sp, aut_ip_lr_sp):
Add new patterns.
* config/arm/unspecs.md (UNSPEC_PAC_IP_LR_SP)
(UNSPEC_PACBTI_IP_LR_SP, UNSPEC_AUT_IP_LR_SP): Add unspecs.

gcc/testsuite/Changelog

2021-11-03  Andrea Corallo  

* gcc.target/arm/pac.h : New file.
* gcc.target/arm/pac-1.c : New test case.
* gcc.target/arm/pac-2.c : Likewise.
* gcc.target/arm/pac-3.c : Likewise.
* gcc.target/arm/pac-4.c : Likewise.
* gcc.target/arm/pac-5.c : Likewise.
* gcc.target/arm/pac-6.c : Likewise.
* gcc.target/arm/pac-7.c : Likewise.
* gcc.target/arm/pac-8.c : Likewise.

diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h
index cff7ff1da2a..84764bf27ce 100644
--- a/gcc/config/arm/arm-protos.h
+++ b/gcc/config/arm/arm-protos.h
@@ -379,6 +379,7 @@ extern int vfp3_const_double_for_bits (rtx);
 extern void arm_emit_coreregs_64bit_shift (enum rtx_code, rtx, rtx, rtx, rtx,
   rtx);
 extern bool arm_fusion_enabled_p (tune_params::fuse_ops);
+extern bool arm_current_function_pac_enabled_p (void);
 extern bool arm_valid_symbolic_address_p (rtx);
 extern bool arm_validize_comparison (rtx *, rtx *, rtx *);
 extern bool arm_expand_vector_compare (rtx, rtx_code, rtx, rtx, bool);
diff --git a/gcc/config/arm/arm.cc b/gcc/config/arm/arm.cc
index a5cf4225aa2..0ba9c0b9960 100644
--- a/gcc/config/arm/arm.cc
+++ b/gcc/config/arm/arm.cc
@@ -3209,6 +3209,9 @@ arm_option_override_internal (struct gcc_options *opts,
   arm_stack_protector_guard_offset = offs;
 }
 
+  if (arm_current_function_pac_enabled_p () && !(arm_arch7 && arm_arch_cmse))
+error ("This architecture does not support branch protection 
instructions");
+
 #ifdef SUBTARGET_OVERRIDE_INTERNAL_OPTIONS
   SUBTARGET_OVERRIDE_INTERNAL_OPTIONS;
 #endif
@@ -21139,6 +21142,9 @@ arm_compute_save_core_reg_mask (void)
 
   save_reg_mask |= arm_compute_save_reg0_reg12_mask ();
 
+  if (arm_current_function_pac_enabled_p ())
+save_reg_mask |= 1 << IP_REGNUM;
+
   /* Decide if we need to save the link register.
  Interrupt routines have their own banked link register,
  so they never need to save it.
@@ -23362,6 +23368,12 @@ output_probe_stack_range (rtx reg1, rtx reg2)
   return "";
 }
 
+static bool
+aarch_bti_enabled ()
+{
+  return false;
+}
+
 /* Generate the prologue instructions for entry into an ARM or Thumb-2
function.  */
 void
@@ -23440,12 +23452,13 @@ arm_expand_prologue (void)
 
   /* The static chain register is the same as the IP register.  If it is
  clobbered when creating the frame, we need to save and restore it.  */
-  clobber_ip = IS_NESTED (func_type)
-  && ((TARGET_APCS_FRAME && frame_pointer_needed && TARGET_ARM)
-  || ((flag_stack_check == STATIC_BUILTIN_STACK_CHECK
-   || flag_stack_

[PING][PATCH 0/15] arm: Enables return address verification and branch target identification on Cortex-M

[Andrea Corallo via Gcc-patches]

Hi all,

ping^2 for patches 9/15 7/15 11/15 12/15 and 10/15 V2 of this series.

  Andrea

Re: [PATCH 9/15] arm: Set again stack pointer as CFA reg when popping if necessary

[Andrea Corallo via Gcc-patches]

Kyrylo Tkachov  writes:

> Hi Andrea,
>
>> -Original Message-
>> From: Gcc-patches > bounces+kyrylo.tkachov=arm@gcc.gnu.org> On Behalf Of Andrea
>> Corallo via Gcc-patches
>> Sent: Friday, August 12, 2022 4:34 PM
>> To: Andrea Corallo via Gcc-patches 
>> Cc: Richard Earnshaw ; nd 
>> Subject: [PATCH 9/15] arm: Set again stack pointer as CFA reg when popping
>> if necessary
>> 
>> Hi all,
>> 
>> this patch enables 'arm_emit_multi_reg_pop' to set again the stack
>> pointer as CFA reg when popping if this is necessary.
>> 
>
> From what I can tell from similar functions this is correct, but could you 
> elaborate on why this change is needed for my understanding please?
> Thanks,
> Kyrill

Hi Kyrill,

sure, if the frame pointer was set, than it is the current CFA register.
If we request to adjust the current CFA register offset indicating it
being SP (while it's actually FP) that is indeed not correct and the
incoherence we will be detected by an assertion in the dwarf emission
machinery.

Best Regards

  Andrea

[PATCH] Don't ICE running selftests if errors were raised [PR99723]

[Andrea Corallo via Gcc-patches]

Hi all

this is to address PR 99723.

In the PR GCC crashes as the initialization of common trees is not
performed as no compilation is happening, this is because we raise an
error earlier while processing the arch flags.

This patch changes the code to execute selftests only if no errors
where raised before.

Bootstrapped on aarch64, okay for trunk?

Best Regards

  Andrea

2022-09-27  Andrea Corallo  

* toplev.cc (toplev::main): Don't run self tests in case of
previous error.
---
 gcc/toplev.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/toplev.cc b/gcc/toplev.cc
index 924871fa9a8..b53a78bbaf1 100644
--- a/gcc/toplev.cc
+++ b/gcc/toplev.cc
@@ -2276,7 +2276,7 @@ toplev::main (int argc, char **argv)
start_timevars ();
   do_compile (no_backend);
 
-  if (flag_self_test)
+  if (flag_self_test && !seen_error ())
{
  if (no_backend)
error_at (UNKNOWN_LOCATION, "self-tests incompatible with %<-E%>");
-- 
2.25.1

[PATCH] arm: Define __ARM_FEATURE_AES and __ARM_FEATURE_SHA2 when march +crypto is selected

[Andrea Corallo via Gcc-patches]

Hi all,

this patch fixes the missing definition of __ARM_FEATURE_AES and
__ARM_FEATURE_SHA2 when AES SHA1 & SHA2 crypto instructions are
available [1] (read when march +crypto is selected).

Okay for master?

Thanks

  Andrea

[1] 

/gcc/ChangeLog

2022-09-14  Andrea Corallo  

* config/arm/arm-c.cc (arm_cpu_builtins): Define
__ARM_FEATURE_AES and __ARM_FEATURE_SHA2.

gcc/testsuite/ChangeLog

2022-09-14  Andrea Corallo  

* gcc.target/arm/attr-crypto.c: Update test.
---
 gcc/config/arm/arm-c.cc| 2 ++
 gcc/testsuite/gcc.target/arm/attr-crypto.c | 8 
 2 files changed, 10 insertions(+)

diff --git a/gcc/config/arm/arm-c.cc b/gcc/config/arm/arm-c.cc
index a8697b8c62f..86c56bf2680 100644
--- a/gcc/config/arm/arm-c.cc
+++ b/gcc/config/arm/arm-c.cc
@@ -202,6 +202,8 @@ arm_cpu_builtins (struct cpp_reader* pfile)
   def_or_undef_macro (pfile, "__ARM_FEATURE_QBIT", TARGET_ARM_QBIT);
   def_or_undef_macro (pfile, "__ARM_FEATURE_SAT", TARGET_ARM_SAT);
   def_or_undef_macro (pfile, "__ARM_FEATURE_CRYPTO", TARGET_CRYPTO);
+  def_or_undef_macro (pfile, "__ARM_FEATURE_AES", TARGET_CRYPTO);
+  def_or_undef_macro (pfile, "__ARM_FEATURE_SHA2", TARGET_CRYPTO);
 
   def_or_undef_macro (pfile, "__ARM_FEATURE_UNALIGNED", unaligned_access);
 
diff --git a/gcc/testsuite/gcc.target/arm/attr-crypto.c 
b/gcc/testsuite/gcc.target/arm/attr-crypto.c
index cbd13a757d8..05e458f36b6 100644
--- a/gcc/testsuite/gcc.target/arm/attr-crypto.c
+++ b/gcc/testsuite/gcc.target/arm/attr-crypto.c
@@ -16,6 +16,14 @@
 #error __ARM_FEATURE_CRYPTO not defined.
 #endif
 
+#ifndef __ARM_FEATURE_AES
+#error __ARM_FEATURE_AES not defined.
+#endif
+
+#ifndef __ARM_FEATURE_SHA2
+#error __ARM_FEATURE_SHA2 not defined.
+#endif
+
 #ifndef __ARM_NEON
 #error __ARM_NEON not defined.
 #endif
-- 
2.25.1

Re: [PATCH] arm: Define __ARM_FEATURE_AES and __ARM_FEATURE_SHA2 when march +crypto is selected

[Andrea Corallo via Gcc-patches]

Kyrylo Tkachov  writes:

> Hi Andrea,
>
>> -Original Message-
>> From: Andrea Corallo 
>> Sent: Wednesday, September 28, 2022 1:19 PM
>> To: gcc-patches@gcc.gnu.org
>> Cc: Kyrylo Tkachov ; Richard Earnshaw
>> ; Andrea Corallo 
>> Subject: [PATCH] arm: Define __ARM_FEATURE_AES and
>> __ARM_FEATURE_SHA2 when march +crypto is selected
>> 
>> Hi all,
>> 
>> this patch fixes the missing definition of __ARM_FEATURE_AES and
>> __ARM_FEATURE_SHA2 when AES SHA1 & SHA2 crypto instructions are
>> available [1] (read when march +crypto is selected).
>> 
>> Okay for master?
>
> Ok.
> Thanks,
> Kyrill

Into trunk as 5e9c4ed903c.

Thanks!

  Andrea

[PATCH 12/15 V2] arm: implement bti injection

[Andrea Corallo via Gcc-patches]

Kyrylo Tkachov  writes:

> Hi Andrea,

[...]

> diff --git a/gcc/config/arm/aarch-bti-insert.cc 
> b/gcc/config/arm/aarch-bti-insert.cc
> index 2d1d2e334a9..8f045c247bf 100644
> --- a/gcc/config/arm/aarch-bti-insert.cc
> +++ b/gcc/config/arm/aarch-bti-insert.cc
> @@ -41,6 +41,7 @@
>  #include "cfgrtl.h"
>  #include "tree-pass.h"
>  #include "cgraph.h"
> +#include "diagnostic-core.h"
>
> This change doesn't seem to match what's in the ChangeLog and doesn't make 
> sense to me.

Change removed thanks.

> @@ -32985,6 +32979,58 @@ arm_current_function_pac_enabled_p (void)
>   && !crtl->is_leaf);
>  }
>
> +/* Return TRUE if Branch Target Identification Mechanism is enabled.  */
> +bool
> +aarch_bti_enabled (void)
> +{
> +  return aarch_enable_bti == 1;
> +}
> +
> +/* Check if INSN is a BTI J insn.  */
> +bool
> +aarch_bti_j_insn_p (rtx_insn *insn)
> +{
> +  if (!insn || !INSN_P (insn))
> +return false;
> +
> +  rtx pat = PATTERN (insn);
> +  return GET_CODE (pat) == UNSPEC_VOLATILE && XINT (pat, 1) == 
> UNSPEC_BTI_NOP;
> +}
> +
> +/* Check if X (or any sub-rtx of X) is a PACIASP/PACIBSP instruction.  */
>
> The arm instructions are not PACIASP/PACIBSP.
> This comment should be rewritten.

This hunk belongs to aarch64.cc so it's aarch64 specific.

> +bool
> +aarch_pac_insn_p (rtx x)
> +{
>
> ..
>
> +rtx
> +aarch_gen_bti_c (void)
> +{
> +  return gen_bti_nop ();
> +}
> +
> +rtx
> +aarch_gen_bti_j (void)
> +{
> +  return gen_bti_nop ();
> +}
> +
>
> A reader may be confused for why we have a bti_c and bti_j function that have 
> identical functionality.
> Please add function comments explaining the situation.

Done

> diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
> index 92269a7819a..90c8c1d66f5 100644
> --- a/gcc/config/arm/arm.md
> +++ b/gcc/config/arm/arm.md
> @@ -12913,6 +12913,13 @@
>"aut\t%|ip, %|lr, %|sp"
>[(set_attr "length" "4")])
>
> +(define_insn "bti_nop"
> +  [(unspec_volatile [(const_int 0)] UNSPEC_BTI_NOP)]
> +  "arm_arch7 && arm_arch_cmse"
>
> That seems like a copy-paste mistake. CMSE has nothing to do with this 
> functionality?

This is because we don't have arm_arch8m_main, but this is equivalent to
arm_arch7 && arm_arch_cmse.  IIUC it wasn't added becasue armv8-m is
basically just armv7-m + cmse.

Any other preferred way to express this?

> +  "bti"
> +  [(set_attr "length" "4")
>
> The length of instructions in the arm backend is 4 by default, this set_attr 
> can be omitted
>
> +   (set_attr "type" "mov_reg")])
> +
> Probably better to use the "nop" attribute here?

Done

Thanks for reviewing, please find attached the updated version.

  Andrea

>From 42f81b763c3a347f3452cd6ead056748d2830135 Mon Sep 17 00:00:00 2001
From: Andrea Corallo 
Date: Thu, 7 Apr 2022 11:51:56 +0200
Subject: [PATCH] [PATCH 12/15] arm: implement bti injection

Hi all,

this patch enables Branch Target Identification Armv8.1-M Mechanism
[1].

This is achieved by using the bti pass made common with Aarch64.

The pass iterates through the instructions and adds the necessary BTI
instructions at the beginning of every function and at every landing
pads targeted by indirect jumps.

Best Regards

  Andrea

[1]


gcc/ChangeLog

2022-04-07  Andrea Corallo  

* config.gcc (arm*-*-*): Add 'aarch-bti-insert.o' object.
* config/arm/arm-protos.h: Update.
* config/arm/arm.cc (aarch_bti_enabled, aarch_bti_j_insn_p)
(aarch_pac_insn_p, aarch_gen_bti_c, aarch_gen_bti_j): New
functions.
* config/arm/arm.md (bti_nop): New insn.
* config/arm/t-arm (PASSES_EXTRA): Add 'arm-passes.def'.
(aarch-bti-insert.o): New target.
* config/arm/unspecs.md (UNSPEC_BTI_NOP): New unspec.
* config/arm/aarch-bti-insert.cc (rest_of_insert_bti): Update
to verify arch compatibility.
* config/arm/arm-passes.def: New file.

gcc/testsuite/ChangeLog

2022-04-07  Andrea Corallo  

* gcc.target/arm/bti-1.c: New testcase.
* gcc.target/arm/bti-2.c: Likewise.
---
 gcc/config.gcc   |  2 +-
 gcc/config/arm/arm-passes.def| 21 ++
 gcc/config/arm/arm-protos.h  |  2 +
 gcc/config/arm/arm.cc| 61 +---
 gcc/config/arm/arm.md|  6 +++
 gcc/config/arm/t-arm | 10 +
 gcc/config/arm/unspecs.md|  1 +
 gcc/testsuite/gcc.target/arm/bti-1.c | 12 ++
 gcc/testsuite/gcc.target/arm/bti-2.c | 58 ++
 9 files changed, 166 insertions(+), 7 deletions(-)
 create mode 100644 gcc/config/arm/arm-passes.def
 create mode 100644 gcc/testsuite/gcc.target/arm/bti-1.c
 create mode 100644 gcc/testsuite/gcc.target/arm/bti-2.c

diff --git a/gcc/config.gcc b/gcc/config.gcc
index 2021bdf9d2f..004e1dfa8d8 100644
--- a/gcc/config.gcc
+++ b/gcc/config

Re: [PATCH] Don't ICE running selftests if errors were raised [PR99723]

[Andrea Corallo via Gcc-patches]

Jeff Law via Gcc-patches  writes:

> On 9/27/22 09:12, Andrea Corallo via Gcc-patches wrote:
>> Hi all
>>
>> this is to address PR 99723.
>>
>> In the PR GCC crashes as the initialization of common trees is not
>> performed as no compilation is happening, this is because we raise an
>> error earlier while processing the arch flags.
>>
>> This patch changes the code to execute selftests only if no errors
>> where raised before.
>>
>> Bootstrapped on aarch64, okay for trunk?
>>
>> Best Regards
>>
>>Andrea
>>
>> 2022-09-27  Andrea Corallo  
>>
>>  * toplev.cc (toplev::main): Don't run self tests in case of
>>  previous error.
>
> OK

Into trunk as 248c8aeebc4.

Thanks

  Andrea

Re: [PATCH][pushed] jit: Initialize function::m_blocks in ctor

[Andrea Corallo via Gcc-patches]

Martin Liška  writes:

> This resolves the problem reported here:
> https://mail.gnu.org/archive/html/bug-gnu-emacs/2021-11/msg00606.html
> https://bugzilla.opensuse.org/show_bug.cgi?id=1192951
>
> I'm going to push it as obvious.
>
> Martin

Hi Martin,

thanks for the fix!

Question: that piece of code is there since 2014, should we back-port
the fix as well?

Best Regards

  Andrea

Re: [PATCH] [1/2] arm: Implement cortex-M return signing address codegen

[Andrea Corallo via Gcc-patches]

Andrea Corallo via Gcc-patches  writes:

> Hi all,
>
> this patch enables address return signature and verification based on
> Armv8.1-M Pointer Authentication [1].
>
> To sign the return address, we use the PAC R12, LR, SP instruction
> upon function entry.  This is signing LR using SP and storing the
> result in R12.  R12 will be pushed into the stack.
>
> During function epilogue R12 will be popped and AUT R12, LR, SP will
> be used to verify that the content of LR is still valid before return.
>
> Here an example of PAC instrumented function prologue and epilogue:
>
> pac r12, lr, sp
> push{r3, r7, lr}
> push{r12}
> sub sp, sp, #4
> [...] function body
> add sp, sp, #4
> pop {r12}
> pop {r3, r7, lr}
> aut r12, lr, sp
> bx  lr
>
> The patch also takes care of generating a PACBTI instruction in place
> of the sequence BTI+PAC when Branch Target Identification is enabled
> contextually.
>
> These two patches apply on top of Tejas series posted here [2].
>
> Regressioned and arm-linux-gnu aarch64-linux-gnu bootstraped.
>
> Best Regards
>
>   Andrea
>
> [1] 
> <https://community.arm.com/developer/ip-products/processors/b/processors-ip-blog/posts/armv8-1-m-pointer-authentication-and-branch-target-identification-extension>
> [2] <https://gcc.gnu.org/pipermail/gcc-patches/2021-October/581176.html>

Ping

Best Regards

  Andrea

Re: [PATCH][pushed] jit: Initialize function::m_blocks in ctor

[Andrea Corallo via Gcc-patches]

Martin Liška  writes:

[...]

>> Question: that piece of code is there since 2014, should we
>> back-port
>> the fix as well?
>
> I've just pushed to to all active code streams (master, 
> releases/gcc-{9,10,11}).

Wonderful, thanks again.

  Andrea

Re: [Patch 1/8, Arm, AArch64, GCC] Refactor mbranch-protection option parsing and make it common to AArch32 and AArch64 backends. [Was RE: [Patch 2/7, Arm, GCC] Add option -mbranch-protection.]

[Andrea Corallo via Gcc-patches]

Tejas Belagod via Gcc-patches  writes:

> Ping for this series.
>
> Thanks,
> Tejas.

Hi all,

pinging this series.

BR

  Andrea

Re: [Patch 1/8, Arm, AArch64, GCC] Refactor mbranch-protection option parsing and make it common to AArch32 and AArch64 backends. [Was RE: [Patch 2/7, Arm, GCC] Add option -mbranch-protection.]

[Andrea Corallo via Gcc-patches]

Richard Earnshaw  writes:

> On 30/11/2021 11:11, Andrea Corallo via Gcc-patches wrote:
>> Tejas Belagod via Gcc-patches  writes:
>> 
>>> Ping for this series.
>>>
>>> Thanks,
>>> Tejas.
>> Hi all,
>> pinging this series.
>> BR
>>Andrea
>> 

Hi Richard,

thanks for reviewing.

> It would be easier to find the 'series' if the messages were properly
> threaded together...


Feel free to let me know if you want me to ping the other patches as
well so they all pops up.

Thanks

  Andrea

Re: [Patch 3/8, Arm, GCC] Add option -mbranch-protection. [Was RE: [Patch 2/7, Arm, GCC] Add option -mbranch-protection.]

[Andrea Corallo via Gcc-patches]

Richard Earnshaw via Gcc-patches  writes:

[...]

>> Thanks for the reviews.
>> Add -mbranch-protection option.  This option enables the
>> code-generation of
>> pointer signing and authentication instructions in function prologues and
>> epilogues.
>> 2021-10-25  Tejas Belagod  
>> gcc/ChangeLog:
>>  * config/arm/arm.c (arm_configure_build_target): Parse and
>> validate
>>  -mbranch-protection option and initialize appropriate data structures.
>>  * config/arm/arm.opt: New option -mbranch-protection.
>
> .../arm.opt (-mbranch-protection) : New option.
>
>>  * doc/invoke.texi: Document -mbranch-protection.
>
> .../invoke.texi (Arm Options): Document it.
>
>> Tested the following configurations, OK for trunk?
>> -mthumb/-march=armv8.1-m.main+pacbti/-mfloat-abi=soft
>> -marm/-march=armv7-a/-mfpu=vfpv3-d16/-mfloat-abi=softfp
>> mcmodel=small and tiny
>> aarch64-none-linux-gnu native test and bootstrap
>> 
>
> +@item
> -mbranch-protection=@var{none}|@var{standard}|@var{pac-ret}[+@var{leaf}][+@var{bti}]|@var{bti}[+@var{pac-ret}[+@var{leaf}]]
> +@opindex mbranch-protection
> +Select the branch protection features to use.
> +@samp{none} is the default and turns off all types of branch protection.
> +@samp{standard} turns on all types of branch protection features.  If
> a feature
> +has additional tuning options, then @samp{standard} sets it to its standard
> +level.
> +@samp{pac-ret[+@var{leaf}]} turns on return address signing to its standard
> +level: signing functions that save the return address to memory (non-leaf
> +functions will practically always do this).  The optional argument
> @samp{leaf}
> +can be used to extend the signing to include leaf functions.
> +@samp{bti} turns on branch target identification mechanism.
>
> This doesn't really use the right documentation style.  Closer would be:

[...]

Hi Richard,

thanks for reviewing, here is the updated patch.

Best Regards

  Andrea

>From 3383a1e265b7b695c5d6ce6115ad66eed2a4cb48 Mon Sep 17 00:00:00 2001
From: Andrea Corallo 
Date: Mon, 6 Dec 2021 11:39:03 +0100
Subject: [PATCH] Add option -mbranch-protection.

Add -mbranch-protection option.  This option enables the
code-generation of pointer signing and authentication instructions in
function prologues and epilogues.

gcc/ChangeLog:

* config/arm/arm.c (arm_configure_build_target): Parse and validate
-mbranch-protection option and initialize appropriate data structures.
* config/arm/arm.opt (-mbranch-protection): New option.
* doc/invoke.texi (Arm Options): Document it.

Co-Authored-By: Tejas Belagod  
Co-Authored-By: Richard Earnshaw 
---
 gcc/config/arm/arm.c   | 11 +++
 gcc/config/arm/arm.opt |  4 
 gcc/doc/invoke.texi| 35 +--
 3 files changed, 48 insertions(+), 2 deletions(-)

diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 96186b8ad02..ee22acddee5 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -3237,6 +3237,17 @@ arm_configure_build_target (struct arm_build_target 
*target,
   tune_opts = strchr (opts->x_arm_tune_string, '+');
 }
 
+  if (opts->x_arm_branch_protection_string)
+{
+  aarch_validate_mbranch_protection (opts->x_arm_branch_protection_string);
+
+  if (aarch_ra_sign_key != AARCH_KEY_A)
+   {
+ warning (0, "invalid key type for %<-mbranch-protection=%>");
+ aarch_ra_sign_key = AARCH_KEY_A;
+   }
+}
+
   if (arm_selected_arch)
 {
   arm_initialize_isa (target->isa, arm_selected_arch->common.isa_bits);
diff --git a/gcc/config/arm/arm.opt b/gcc/config/arm/arm.opt
index 5c5b4f3ae06..4f2754c3e84 100644
--- a/gcc/config/arm/arm.opt
+++ b/gcc/config/arm/arm.opt
@@ -313,6 +313,10 @@ mbranch-cost=
 Target RejectNegative Joined UInteger Var(arm_branch_cost) Init(-1)
 Cost to assume for a branch insn.
 
+mbranch-protection=
+Target RejectNegative Joined Var(arm_branch_protection_string) Save
+Use branch-protection features.
+
 mgeneral-regs-only
 Target RejectNegative Mask(GENERAL_REGS_ONLY) Save
 Generate code which uses the core registers only (r0-r14).
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 3257df5596d..a808c6bb599 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -820,7 +820,9 @@ Objective-C and Objective-C++ Dialects}.
 -mpure-code @gol
 -mcmse @gol
 -mfix-cmse-cve-2021-35465 @gol
--mfdpic}
+-mfdpic @gol
+-mbranch-protection=@var{none}|@var{standard}|@var{pac-ret}[+@var{leaf}]
+[+@var{bti}]|@var{bti}[+@var{pac-ret}[+@var{leaf}]]}
 
 @emph{AVR Options}
 @gccoptlist{-mmcu=@var{mcu}  -mabsdata  -maccumulate-args @gol
@@ -21187,7 +21189,36 @@ The opposite @option{-mno-fdpic} option is useful (and 
required) to
 build the Linux kernel using the same (@code{arm-*-uclinuxfdpiceabi})
 toolchain as the one used to build the userland programs.
 
-@end table
+@item
+-mbranch-protection=@var{none}|@var{standard}|@var{pac-ret}[+@var{leaf}][+@var{bti}]|@var{bti}[+@var{pac-ret}[+@var{leaf}]]

Re: [PATCH] [1/2] arm: Implement cortex-M return signing address codegen

[Andrea Corallo via Gcc-patches]

Andrea Corallo via Gcc-patches  writes:

> Andrea Corallo via Gcc-patches  writes:
>
>> Hi all,
>>
>> this patch enables address return signature and verification based on
>> Armv8.1-M Pointer Authentication [1].
>>
>> To sign the return address, we use the PAC R12, LR, SP instruction
>> upon function entry.  This is signing LR using SP and storing the
>> result in R12.  R12 will be pushed into the stack.
>>
>> During function epilogue R12 will be popped and AUT R12, LR, SP will
>> be used to verify that the content of LR is still valid before return.
>>
>> Here an example of PAC instrumented function prologue and epilogue:
>>
>> pac r12, lr, sp
>> push{r3, r7, lr}
>> push{r12}
>> sub sp, sp, #4
>> [...] function body
>> add sp, sp, #4
>> pop {r12}
>> pop {r3, r7, lr}
>> aut r12, lr, sp
>> bx  lr
>>
>> The patch also takes care of generating a PACBTI instruction in place
>> of the sequence BTI+PAC when Branch Target Identification is enabled
>> contextually.
>>
>> These two patches apply on top of Tejas series posted here [2].
>>
>> Regressioned and arm-linux-gnu aarch64-linux-gnu bootstraped.
>>
>> Best Regards
>>
>>   Andrea
>>
>> [1] 
>> <https://community.arm.com/developer/ip-products/processors/b/processors-ip-blog/posts/armv8-1-m-pointer-authentication-and-branch-target-identification-extension>
>> [2] <https://gcc.gnu.org/pipermail/gcc-patches/2021-October/581176.html>
>
> Ping
>
> Best Regards
>
>   Andrea

Hi all,

pinging this and 2/2.

Thanks

  Andrea

[Patch 6/8 V2] Arm: Add pointer authentication for stack-unwinding runtime.

[Andrea Corallo via Gcc-patches]

Richard Earnshaw via Gcc-patches  writes:

> On 28/10/2021 12:43, Tejas Belagod via Gcc-patches wrote:
>> 
>>> -Original Message-
>>> From: Gcc-patches >> bounces+belagod=gcc.gnu@gcc.gnu.org> On Behalf Of Tejas Belagod via
>>> Gcc-patches
>>> Sent: Friday, October 8, 2021 1:18 PM
>>> To: gcc-patches@gcc.gnu.org
>>> Subject: [Patch 5/7, Arm. GCC] Add pointer authentication for stack-
>>> unwinding runtime.
>>>
>>> Hi,
>>>
>>> This patch adds authentication for when the stack is unwound when an
>>> exception is taken.  All the changes here are done to the runtime code in
>>> libgcc's unwinder code for Arm target. All the changes are guarded under
>>> defined (__ARM_FEATURE_PAC_DEFAULT) and activates only if the +pacbti
>>> feature is switched on for the architecture. This means that switching on 
>>> the
>>> target feature via -march or -mcpu is sufficient and -mbranch-protection
>>> need not be enabled. This ensures that the unwinder is authenticated only if
>>> the PACBTI instructions are available in the non-NOP space as it uses AUTG.
>>> Just generating PAC/AUT instructions using -mbranch-protection will not
>>> enable authentication on the unwinder.
>>>
>>> Tested on arm-none-eabi. OK for trunk?
>>>
>>> 2021-10-04  Tejas Belagod  
>>>
>>> gcc/ChangeLog:
>>>
>>> * ginclude/unwind-arm-common.h (_Unwind_VRS_RegClass):
>>> Introduce
>>> new pseudo register class _UVRSC_PAC.
>>> * libgcc/config/arm/pr-support.c (__gnu_unwind_execute): Decode
>>> exception opcode (0xb4) for saving RA_AUTH_CODE and
>>> authenticate
>>> with AUTG if found.
>>> * libgcc/config/arm/unwind-arm.c (struct pseudo_regs): New.
>>> (phase1_vrs): Introduce new field to store pseudo-reg state.
>>> (phase2_vrs): Likewise.
>>> (_Unwind_VRS_Get): Load pseudo register state from virtual reg set.
>>> (_Unwind_VRS_Set): Store pseudo register state to virtual reg set.
>>> (_Unwind_VRS_Pop): Load pseudo register value from stack into
>>> VRS.
>> Rebased and respin based on reviews for previous patches.
>> This patch adds authentication for when the stack is unwound when
>> an exception is taken.  All the changes here are done to the runtime
>> code in libgcc's unwinder code for Arm target. All the changes are
>> guarded under defined (__ARM_FEATURE_PAUTH) and activates only
>> if the +pacbti feature is switched on for the architecture. This means
>> that switching on the target feature via -march or -mcpu is sufficient
>> and -mbranch-protection need not be enabled. This ensures that the
>> unwinder is authenticated only if the PACBTI instructions are available
>> in the non-NOP space as it uses AUTG. Just generating PAC/AUT instructions
>> using -mbranch-protection will not enable authentication on the unwinder.
>> 2021-10-25  Tejas Belagod  
>> gcc/ChangeLog:
>>  * ginclude/unwind-arm-common.h (_Unwind_VRS_RegClass):
>> Introduce
>>  new pseudo register class _UVRSC_PAC.
>>  * libgcc/config/arm/pr-support.c (__gnu_unwind_execute): Decode
>>  exception opcode (0xb4) for saving RA_AUTH_CODE and authenticate
>>  with AUTG if found.
>>  * libgcc/config/arm/unwind-arm.c (struct pseudo_regs): New.
>>  (phase1_vrs): Introduce new field to store pseudo-reg state.
>>  (phase2_vrs): Likewise.
>>  (_Unwind_VRS_Get): Load pseudo register state from virtual reg set.
>>  (_Unwind_VRS_Set): Store pseudo register state to virtual reg set.
>>  (_Unwind_VRS_Pop): Load pseudo register value from stack into VRS.
>> Tested the following configurations, OK for trunk?
>> -mthumb/-march=armv8.1-m.main+pacbti/-mfloat-abi=soft
>> -marm/-march=armv7-a/-mfpu=vfpv3-d16/-mfloat-abi=softfp
>> mcmodel=small and tiny
>> aarch64-none-linux-gnu native test and bootstrap
>> Thanks,
>> Tejas.
>>

> I'd like to try to get rid of most of the ifdefs from this patch; at
> least, it shouldn't be using the ACLE PAUTH feature.  The unwinder
> should be able to cope with any unwind sequence thrown at it.
>
> Things are a little more complicated for pointer authentication,
> though, because some operations in the main code constructing the
> frame may be using architectural NOP instructions, while the unwinder
> cannot do the validation using only the architectural NOPs.
>
> So we need a fall-back: if the unwinder is built without the PAUTH
> feature it needs to unwind the pauth frames without the additional
> validation (but it still needs to be able to handle them).
>
> So the only remaining question is whether the additional support
> should only be enabled for M-profile targets, or whether we should
> just put this code into all builds of the unwinder.  I'm not sure I
> have a complete answer to that.  My inclination is to put it in
> unconditionally - we haven't had conditionals for any other optional
> architecture feature before.  If something similar is added for
> A/R-profiles, then either we will share the code exactly, or we'll end
> up with a different unwind code to use as a sui

Re: [Patch 8/8, Arm, GCC] Introduce multilibs for PACBTI target feature. [Was RE: [Patch 7/7, Arm, GCC] Introduce multilibs for PACBTI target feature.]

[Andrea Corallo via Gcc-patches]

Richard Earnshaw via Gcc-patches  writes:

> On 28/10/2021 12:43, Tejas Belagod via Gcc-patches wrote:
>> 
>>> -Original Message-
>>> From: Gcc-patches >> bounces+belagod=gcc.gnu@gcc.gnu.org> On Behalf Of Tejas Belagod via
>>> Gcc-patches
>>> Sent: Friday, October 8, 2021 1:19 PM
>>> To: gcc-patches@gcc.gnu.org
>>> Subject: [Patch 7/7, Arm, GCC] Introduce multilibs for PACBTI target 
>>> feature.
>>>
>>> Hi,
>>>
>>> This patch adds a multilib for pacbti target feature.
>>>
>>> Tested on arm-none-eabi. OK for trunk?
>>>
>>> 2021-10-04  Tejas Belagod  
>>>
>>> gcc/ChangeLog:
>>>
>>> * config/arm/t-rmprofile: Add multilib rules for +pacbti.
>> This patch adds a multilib for pacbti target feature.
>> 2021-10-04  Tejas Belagod  
>> gcc/ChangeLog:
>>  * config/arm/t-rmprofile: Add multilib rules for +pacbti.
>> Tested the following configurations, OK for trunk?
>> -mthumb/-march=armv8.1-m.main+pacbti/-mfloat-abi=soft
>> -marm/-march=armv7-a/-mfpu=vfpv3-d16/-mfloat-abi=softfp
>> mcmodel=small and tiny
>> aarch64-none-linux-gnu native test and bootstrap
>> Thanks,
>> Tejas.
>> 

Hi Richard,

> I can't decide whether this is too much, or too little.  But it
> doesn't feel right as it is.
>
> Ideally we don't want yet another multilib.  It would be better to
> have one of the existing multilib variants made pac/bti safe.
>
> And secondly, what about the hand-written assembler files in libgcc?
> Don't they need updating to be PAC/BTI safe?

I agree with you, this patch is missing at least bti landing pads in the
hand-written assembler files in libgcc.

> Also, does this even do what you intend it to do?  It adds the PAC/BTI
> architectural feature, but it doesn't actually enable PAC/BTI in the
> generated code.

Good point, I'll fix this too in the upcoming respin.

Thanks for reviewing.

BR

  Andrea

Re: [Patch 6/8 V2] Arm: Add pointer authentication for stack-unwinding runtime.

[Andrea Corallo via Gcc-patches]

Richard Earnshaw  writes:

> On 09/12/2021 17:36, Andrea Corallo via Gcc-patches wrote:
>> Richard Earnshaw via Gcc-patches  writes:
>> 
>>> On 28/10/2021 12:43, Tejas Belagod via Gcc-patches wrote:
>>>>
>>>>> -Original Message-
>>>>> From: Gcc-patches >>>> bounces+belagod=gcc.gnu@gcc.gnu.org> On Behalf Of Tejas Belagod via
>>>>> Gcc-patches
>>>>> Sent: Friday, October 8, 2021 1:18 PM
>>>>> To: gcc-patches@gcc.gnu.org
>>>>> Subject: [Patch 5/7, Arm. GCC] Add pointer authentication for stack-
>>>>> unwinding runtime.
>>>>>
>>>>> Hi,
>>>>>
>>>>> This patch adds authentication for when the stack is unwound when an
>>>>> exception is taken.  All the changes here are done to the runtime code in
>>>>> libgcc's unwinder code for Arm target. All the changes are guarded under
>>>>> defined (__ARM_FEATURE_PAC_DEFAULT) and activates only if the +pacbti
>>>>> feature is switched on for the architecture. This means that switching on 
>>>>> the
>>>>> target feature via -march or -mcpu is sufficient and -mbranch-protection
>>>>> need not be enabled. This ensures that the unwinder is authenticated only 
>>>>> if
>>>>> the PACBTI instructions are available in the non-NOP space as it uses 
>>>>> AUTG.
>>>>> Just generating PAC/AUT instructions using -mbranch-protection will not
>>>>> enable authentication on the unwinder.
>>>>>
>>>>> Tested on arm-none-eabi. OK for trunk?
>>>>>
>>>>> 2021-10-04  Tejas Belagod  
>>>>>
>>>>> gcc/ChangeLog:
>>>>>
>>>>>   * ginclude/unwind-arm-common.h (_Unwind_VRS_RegClass):
>>>>> Introduce
>>>>>   new pseudo register class _UVRSC_PAC.
>>>>>   * libgcc/config/arm/pr-support.c (__gnu_unwind_execute): Decode
>>>>>   exception opcode (0xb4) for saving RA_AUTH_CODE and
>>>>> authenticate
>>>>>   with AUTG if found.
>>>>>   * libgcc/config/arm/unwind-arm.c (struct pseudo_regs): New.
>>>>>   (phase1_vrs): Introduce new field to store pseudo-reg state.
>>>>>   (phase2_vrs): Likewise.
>>>>>   (_Unwind_VRS_Get): Load pseudo register state from virtual reg set.
>>>>>   (_Unwind_VRS_Set): Store pseudo register state to virtual reg set.
>>>>>   (_Unwind_VRS_Pop): Load pseudo register value from stack into
>>>>> VRS.
>>>> Rebased and respin based on reviews for previous patches.
>>>> This patch adds authentication for when the stack is unwound when
>>>> an exception is taken.  All the changes here are done to the runtime
>>>> code in libgcc's unwinder code for Arm target. All the changes are
>>>> guarded under defined (__ARM_FEATURE_PAUTH) and activates only
>>>> if the +pacbti feature is switched on for the architecture. This means
>>>> that switching on the target feature via -march or -mcpu is sufficient
>>>> and -mbranch-protection need not be enabled. This ensures that the
>>>> unwinder is authenticated only if the PACBTI instructions are available
>>>> in the non-NOP space as it uses AUTG. Just generating PAC/AUT instructions
>>>> using -mbranch-protection will not enable authentication on the unwinder.
>>>> 2021-10-25  Tejas Belagod  
>>>> gcc/ChangeLog:
>>>>* ginclude/unwind-arm-common.h (_Unwind_VRS_RegClass):
>>>> Introduce
>>>>new pseudo register class _UVRSC_PAC.
>>>>* libgcc/config/arm/pr-support.c (__gnu_unwind_execute): Decode
>>>>exception opcode (0xb4) for saving RA_AUTH_CODE and authenticate
>>>>with AUTG if found.
>>>>* libgcc/config/arm/unwind-arm.c (struct pseudo_regs): New.
>>>>(phase1_vrs): Introduce new field to store pseudo-reg state.
>>>>(phase2_vrs): Likewise.
>>>>(_Unwind_VRS_Get): Load pseudo register state from virtual reg set.
>>>>(_Unwind_VRS_Set): Store pseudo register state to virtual reg set.
>>>>(_Unwind_VRS_Pop): Load pseudo register value from stack into VRS.
>>>> Tested the following configurations, OK for trunk?
>>>> -mthumb/-march=armv8.1-m.main+pacbti/-mfloat-abi=soft
>>>> -marm/-march=armv7-a/-mfpu=vfpv3-d16/-mfloat-abi=softfp
>>>> mcmodel=small and tiny
&g

Re: [Patch 7/8 V2] Arm: Emit build attributes for PACBTI target feature.

[Andrea Corallo via Gcc-patches]

Richard Earnshaw via Gcc-patches  writes:

> On 28/10/2021 12:43, Tejas Belagod via Gcc-patches wrote:
>> 
>>> -Original Message-
>>> From: Gcc-patches >> bounces+belagod=gcc.gnu@gcc.gnu.org> On Behalf Of Tejas Belagod via
>>> Gcc-patches
>>> Sent: Friday, October 8, 2021 1:19 PM
>>> To: gcc-patches@gcc.gnu.org
>>> Subject: [Patch 6/7, Arm, GCC] Emit build attributes for PACBTI target
>>> feature.
>>>
>>> Hi,
>>>
>>> This patch emits assembler directives for PACBTI build attributes as defined
>>> by the ABI. (https://github.com/ARM-software/abi-
>>> aa/releases/download/2021Q1/addenda32.pdf)
>>>
>>> Tested on arm-none-eabi.
>>>
>>> 2021-10-04  Tejas Belagod  
>>>
>>> gcc/ChangeLog:
>>>
>>> * config/arm/arm.c (arm_file_start): Emit EABI attributes for
>>> Tag_PAC_extension, Tag_BTI_extension, TAG_BTI_use,
>>> TAG_PACRET_use.
>>>
>>> gcc/testsuite/ChangeLog:
>>>
>>> * gcc.target/arm/acle/pacbti-m-predef-1.c: New test.
>>> * gcc.target/arm/acle/pacbti-m-predef-3: New test.
>>> * gcc.target/arm/acle/pacbti-m-predef-6.c: New test.
>> This patch emits assembler directives for PACBTI build attributes
>> as defined by the ABI.
>> https://github.com/ARM-software/abi-aa/releases/download/2021Q1/addenda32.pdf
>> 2021-10-25  Tejas Belagod  
>> gcc/ChangeLog:
>>  * config/arm/arm.c (arm_file_start): Emit EABI attributes for
>>  Tag_PAC_extension, Tag_BTI_extension, TAG_BTI_use, TAG_PACRET_use.
>> gcc/testsuite/ChangeLog:
>>  * gcc.target/arm/acle/pacbti-m-predef-1.c: New test.
>>  * gcc.target/arm/acle/pacbti-m-predef-3: New test.
>>  * gcc.target/arm/acle/pacbti-m-predef-6.c: New test.
>
> I'm not sure what the value of making these executable tests is.  It
> means that they can only be used when the test model has PAC/BTI
> available.  But they don't really test the PAC/BTI generation, so that
> seems rather pointless.
>
> Better, IMO to make them simple compile/scan-assembler tests that
> check the build attributes are correct.
>
> R.

Hi Richard,

agreed.  Please find attached the updated version of the patch.

Thanks for reviewing

  Andrea

>From 6e54ecc3e20a3af8f72a38e55f086a33490353a0 Mon Sep 17 00:00:00 2001
From: Andrea Corallo 
Date: Mon, 6 Dec 2021 11:42:24 +0100
Subject: [PATCH] Emit build attributes for PACBTI target feature.

gcc/ChangeLog:

* config/arm/arm.c (arm_file_start): Emit EABI attributes for
Tag_PAC_extension, Tag_BTI_extension, TAG_BTI_use, TAG_PACRET_use.

gcc/testsuite/ChangeLog:

* gcc.target/arm/acle/pacbti-m-predef-1.c: New test.
* gcc.target/arm/acle/pacbti-m-predef-3: Likewise.
* gcc.target/arm/acle/pacbti-m-predef-6.c: Likewise.
* gcc.target/arm/acle/pacbti-m-predef-7.c: Likewise.

Co-Authored-By: Tejas Belagod  
---
 gcc/config/arm/arm.c  | 20 +++
 .../gcc.target/arm/acle/pacbti-m-predef-1.c   | 16 +++
 .../gcc.target/arm/acle/pacbti-m-predef-3.c   | 16 +++
 .../gcc.target/arm/acle/pacbti-m-predef-6.c   | 15 ++
 .../gcc.target/arm/acle/pacbti-m-predef-7.c   | 16 +++
 5 files changed, 83 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-1.c
 create mode 100644 gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-3.c
 create mode 100644 gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-6.c
 create mode 100644 gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-7.c

diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index ee22acddee5..a493523fe30 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -28221,6 +28221,8 @@ static void
 arm_file_start (void)
 {
   int val;
+  bool pac = (aarch_ra_sign_scope != AARCH_FUNCTION_NONE);
+  bool bti = (aarch_enable_bti == 1);
 
   arm_print_asm_arch_directives
 (asm_out_file, TREE_TARGET_OPTION (target_option_default_node));
@@ -28291,6 +28293,24 @@ arm_file_start (void)
arm_emit_eabi_attribute ("Tag_ABI_FP_16bit_format", 38,
 (int) arm_fp16_format);
 
+  if (TARGET_HAVE_PACBTI)
+   {
+ arm_emit_eabi_attribute ("Tag_PAC_extension", 50, 2);
+ arm_emit_eabi_attribute ("Tag_BTI_extension", 52, 2);
+ arm_emit_eabi_attribute ("TAG_BTI_use", 74, bti);
+ arm_emit_eabi_attribute ("TAG_PACRET_use", 76, pac);
+   }
+  else
+   {
+ if (pac || bti)
+   {
+ arm_emit_eabi_attribute ("Tag_PAC_extension", 50, 1);
+ arm_emit_eabi_attribute ("Tag_BTI_extension", 52, 1);
+ arm_emit_eabi_attribute ("TAG_BTI_use", 74, bti);
+ arm_emit_eabi_attribute ("TAG_PACRET_use", 76, pac);
+   }
+   }
+
   if (arm_lang_output_object_attributes_hook)
arm_lang_output_object_attributes_hook();
 }
diff --git a/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-1.c 
b/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-1.c
new file mode 100644
index 000..75d3e00ef64
---

Re: [PING][PATCH 0/15] arm: Enables return address verification and branch target identification on Cortex-M

[Andrea Corallo via Gcc-patches]

Richard Earnshaw  writes:

> On 21/09/2022 09:07, Andrea Corallo via Gcc-patches wrote:
>> Hi all,
>> ping^2 for patches 9/15 7/15 11/15 12/15 and 10/15 V2 of this
>> series.
>>Andrea
>
> Subject says xx/15, but I only see 1-12 from you.
>
> R.

Yeah, at the time Srinath asked me to leave space for three more patches
to add to the series, but then he posted only 13/15 I guess squashing
the code in one patch.

  Andrea

Re: [PATCH 9/15] arm: Set again stack pointer as CFA reg when popping if necessary

[Andrea Corallo via Gcc-patches]

Richard Earnshaw  writes:

> On 27/09/2022 16:24, Kyrylo Tkachov via Gcc-patches wrote:
>> 
>>> -Original Message-
>>> From: Andrea Corallo 
>>> Sent: Tuesday, September 27, 2022 11:06 AM
>>> To: Kyrylo Tkachov 
>>> Cc: Andrea Corallo via Gcc-patches ; Richard
>>> Earnshaw ; nd 
>>> Subject: Re: [PATCH 9/15] arm: Set again stack pointer as CFA reg when
>>> popping if necessary
>>>
>>> Kyrylo Tkachov  writes:
>>>
>>>> Hi Andrea,
>>>>
>>>>> -----Original Message-
>>>>> From: Gcc-patches >>>> bounces+kyrylo.tkachov=arm@gcc.gnu.org> On Behalf Of Andrea
>>>>> Corallo via Gcc-patches
>>>>> Sent: Friday, August 12, 2022 4:34 PM
>>>>> To: Andrea Corallo via Gcc-patches 
>>>>> Cc: Richard Earnshaw ; nd 
>>>>> Subject: [PATCH 9/15] arm: Set again stack pointer as CFA reg when
>>> popping
>>>>> if necessary
>>>>>
>>>>> Hi all,
>>>>>
>>>>> this patch enables 'arm_emit_multi_reg_pop' to set again the stack
>>>>> pointer as CFA reg when popping if this is necessary.
>>>>>
>>>>
>>>>  From what I can tell from similar functions this is correct, but could you
>>> elaborate on why this change is needed for my understanding please?
>>>> Thanks,
>>>> Kyrill
>>>
>>> Hi Kyrill,
>>>
>>> sure, if the frame pointer was set, than it is the current CFA register.
>>> If we request to adjust the current CFA register offset indicating it
>>> being SP (while it's actually FP) that is indeed not correct and the
>>> incoherence we will be detected by an assertion in the dwarf emission
>>> machinery.
>> Thanks,  the patch is ok
>> Kyrill
>> 
>>>
>>> Best Regards
>>>
>>>Andrea
>
> Hmm, wait.  Why would a multi-reg pop be updating the stack pointer?

Hi Richard,

not sure I understand, isn't any pop updating SP by definition?

BR

  Andrea

Re: [PATCH 10/15 V2] arm: Implement cortex-M return signing address codegen

[Andrea Corallo via Gcc-patches]

Richard Earnshaw  writes:

> On 14/09/2022 15:20, Andrea Corallo via Gcc-patches wrote:
>> Hi all,
>> 
>> this patch enables address return signature and verification based on
>> Armv8.1-M Pointer Authentication [1].
>> 
>> To sign the return address, we use the PAC R12, LR, SP instruction
>> upon function entry.  This is signing LR using SP and storing the
>> result in R12.  R12 will be pushed into the stack.
>> 
>> During function epilogue R12 will be popped and AUT R12, LR, SP will
>> be used to verify that the content of LR is still valid before return.
>> 
>> Here an example of PAC instrumented function prologue and epilogue:
>> 
>> void foo (void);
>> 
>> int main()
>> {
>>foo ();
>>return 0;
>> }
>> 
>> Compiled with '-march=armv8.1-m.main -mbranch-protection=pac-ret
>> -mthumb' translates into:
>> 
>> main:
>>  pac ip, lr, sp
>>  push{r3, r7, ip, lr}
>>  add r7, sp, #0
>>  bl  foo
>>  movsr3, #0
>>  mov r0, r3
>>  pop {r3, r7, ip, lr}
>>  aut ip, lr, sp
>>  bx  lr
>> 
>> The patch also takes care of generating a PACBTI instruction in place
>> of the sequence BTI+PAC when Branch Target Identification is enabled
>> contextually.
>> 
>> Ex. the previous example compiled with '-march=armv8.1-m.main
>> -mbranch-protection=pac-ret+bti -mthumb' translates into:
>> 
>> main:
>>  pacbti  ip, lr, sp
>>  push{r3, r7, ip, lr}
>>  add r7, sp, #0
>>  bl  foo
>>  movsr3, #0
>>  mov r0, r3
>>  pop {r3, r7, ip, lr}
>>  aut ip, lr, sp
>>  bx  lr
>> 
>> As part of previous upstream suggestions a test for varargs has been
>> added and '-mtpcs-frame' is deemed being incompatible with this return
>> signing address feature being introduced.
>> 
>> [1] 
>> <https://community.arm.com/developer/ip-products/processors/b/processors-ip-blog/posts/armv8-1-m-pointer-authentication-and-branch-target-identification-extension>
>> 
>> gcc/Changelog
>> 
>> 2021-11-03  Andrea Corallo  
>> 
>>  * config/arm/arm.c: (arm_compute_frame_layout)
>>  (arm_expand_prologue, thumb2_expand_return, arm_expand_epilogue)
>>  (arm_conditional_register_usage): Update for pac codegen.
>>  (arm_current_function_pac_enabled_p): New function.
>>  * config/arm/arm.md (pac_ip_lr_sp, pacbti_ip_lr_sp, aut_ip_lr_sp):
>>  Add new patterns.
>>  * config/arm/unspecs.md (UNSPEC_PAC_IP_LR_SP)
>>  (UNSPEC_PACBTI_IP_LR_SP, UNSPEC_AUT_IP_LR_SP): Add unspecs.
>> 
>> gcc/testsuite/Changelog
>> 
>> 2021-11-03  Andrea Corallo  
>> 
>>  * gcc.target/arm/pac.h : New file.
>>  * gcc.target/arm/pac-1.c : New test case.
>>  * gcc.target/arm/pac-2.c : Likewise.
>>  * gcc.target/arm/pac-3.c : Likewise.
>>  * gcc.target/arm/pac-4.c : Likewise.
>>  * gcc.target/arm/pac-5.c : Likewise.
>>  * gcc.target/arm/pac-6.c : Likewise.
>>  * gcc.target/arm/pac-7.c : Likewise.
>>  * gcc.target/arm/pac-8.c : Likewise.
>> 
>
> +  if (arm_current_function_pac_enabled_p () && !(arm_arch7 && 
> arm_arch_cmse))
> +error ("This architecture does not support branch protection 
> instructions");
>
> This test feels wrong.  What does having cmse give us?  I suspect you 
> want a test that ensures we have at least v8-m.main so that the NOP 
> instructions are correctly defined as NOPs (or, in this case, PACBTI 
> instructions) rather than unpredictable; but if that's the case then I 
> think you really want to write the test that way here (perhaps in a 
> macro) and then move this test into that so that it becomes 
> self-documenting - but don't we have a v8-m.main test anyway?

Yep

> +   if (arm_current_function_pac_enabled_p ())
> + {
> +  gcc_assert (!(saved_regs_mask & (1 << PC_REGNUM)));
> +   arm_emit_multi_reg_pop (saved_regs_mask);
> +   emit_insn (gen_aut_nop ());
> +   emit_jump_insn (simple_return_rtx);
> + }
>
> The assert is using indents that are just spaces, but the other lines 
> use tabs.  Please use tabs everywhere rather than mixing like this.

Ack.

> +/* Return TRUE if return address signing mechanism is enabled.  */
> +bool
> +arm_current_function_pac_enabled_p (void)
> +{
> +  return aarch_ra_s

[PATCH 10/15 V3] arm: Implement cortex-M return signing address codegen

[Andrea Corallo via Gcc-patches]

Hi all,

the third iteration of this patch is attached addresing review comments.

Thanks

  Andrea

>From b42e28be75f374a4e1a5943c8c9002e07dbcc567 Mon Sep 17 00:00:00 2001
From: Andrea Corallo 
Date: Thu, 20 Jan 2022 15:36:23 +0100
Subject: [PATCH] [PATCH 10/15] arm: Implement cortex-M return signing address
 codegen

Hi all,

this patch enables address return signature and verification based on
Armv8.1-M Pointer Authentication [1].

To sign the return address, we use the PAC R12, LR, SP instruction
upon function entry.  This is signing LR using SP and storing the
result in R12.  R12 will be pushed into the stack.

During function epilogue R12 will be popped and AUT R12, LR, SP will
be used to verify that the content of LR is still valid before return.

Here an example of PAC instrumented function prologue and epilogue:

void foo (void);

int main()
{
  foo ();
  return 0;
}

Compiled with '-march=armv8.1-m.main -mbranch-protection=pac-ret
-mthumb' translates into:

main:
pac ip, lr, sp
push{r3, r7, ip, lr}
add r7, sp, #0
bl  foo
movsr3, #0
mov r0, r3
pop {r3, r7, ip, lr}
aut ip, lr, sp
bx  lr

The patch also takes care of generating a PACBTI instruction in place
of the sequence BTI+PAC when Branch Target Identification is enabled
contextually.

Ex. the previous example compiled with '-march=armv8.1-m.main
-mbranch-protection=pac-ret+bti -mthumb' translates into:

main:
pacbti  ip, lr, sp
push{r3, r7, ip, lr}
add r7, sp, #0
bl  foo
movsr3, #0
mov r0, r3
pop {r3, r7, ip, lr}
aut ip, lr, sp
bx  lr

As part of previous upstream suggestions a test for varargs has been
added and '-mtpcs-frame' is deemed being incompatible with this return
signing address feature being introduced.

[1] 


gcc/Changelog

2021-11-03  Andrea Corallo  

* config/arm/arm.h (arm_arch8m_main): Declare it.
* config/arm/arm.cc (arm_arch8m_main): Define it.
(arm_option_reconfigure_globals): Set arm_arch8m_main.
(arm_compute_frame_layout, arm_expand_prologue)
(thumb2_expand_return, arm_expand_epilogue)
(arm_conditional_register_usage): Update for pac codegen.
(arm_current_function_pac_enabled_p): New function.
* config/arm/arm.md (pac_ip_lr_sp, pacbti_ip_lr_sp, aut_ip_lr_sp):
Add new patterns.
* config/arm/unspecs.md (UNSPEC_PAC_IP_LR_SP)
(UNSPEC_PACBTI_IP_LR_SP, UNSPEC_AUT_IP_LR_SP): Add unspecs.

gcc/testsuite/Changelog

2021-11-03  Andrea Corallo  

* gcc.target/arm/pac.h : New file.
* gcc.target/arm/pac-1.c : New test case.
* gcc.target/arm/pac-2.c : Likewise.
* gcc.target/arm/pac-3.c : Likewise.
* gcc.target/arm/pac-4.c : Likewise.
* gcc.target/arm/pac-5.c : Likewise.
* gcc.target/arm/pac-6.c : Likewise.
* gcc.target/arm/pac-7.c : Likewise.
* gcc.target/arm/pac-8.c : Likewise.
---
 gcc/config/arm/arm-protos.h  |  1 +
 gcc/config/arm/arm.cc| 77 +++-
 gcc/config/arm/arm.h |  4 ++
 gcc/config/arm/arm.md| 23 +
 gcc/config/arm/unspecs.md|  3 ++
 gcc/testsuite/gcc.target/arm/pac-1.c | 12 +
 gcc/testsuite/gcc.target/arm/pac-2.c | 11 
 gcc/testsuite/gcc.target/arm/pac-3.c | 11 
 gcc/testsuite/gcc.target/arm/pac-4.c | 10 
 gcc/testsuite/gcc.target/arm/pac-5.c | 28 ++
 gcc/testsuite/gcc.target/arm/pac-6.c | 18 +++
 gcc/testsuite/gcc.target/arm/pac-7.c | 32 
 gcc/testsuite/gcc.target/arm/pac-8.c | 34 
 gcc/testsuite/gcc.target/arm/pac.h   | 17 ++
 14 files changed, 268 insertions(+), 13 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/arm/pac-1.c
 create mode 100644 gcc/testsuite/gcc.target/arm/pac-2.c
 create mode 100644 gcc/testsuite/gcc.target/arm/pac-3.c
 create mode 100644 gcc/testsuite/gcc.target/arm/pac-4.c
 create mode 100644 gcc/testsuite/gcc.target/arm/pac-5.c
 create mode 100644 gcc/testsuite/gcc.target/arm/pac-6.c
 create mode 100644 gcc/testsuite/gcc.target/arm/pac-7.c
 create mode 100644 gcc/testsuite/gcc.target/arm/pac-8.c
 create mode 100644 gcc/testsuite/gcc.target/arm/pac.h

diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h
index cff7ff1da2a..84764bf27ce 100644
--- a/gcc/config/arm/arm-protos.h
+++ b/gcc/config/arm/arm-protos.h
@@ -379,6 +379,7 @@ extern int vfp3_const_double_for_bits (rtx);
 extern void arm_emit_coreregs_64bit_shift (enum rtx_code, rtx, rtx, rtx, rtx,
   rtx);
 extern bool arm_fusion_enabled_p (tune_params::fuse_ops);
+extern bool arm_current_function_pac_enabled

[PATCH 12/15 V3] arm: implement bti injection

[Andrea Corallo via Gcc-patches]

Hi all,

please find attached the third iteration of this patch addresing review
comments.

Thanks

  Andrea

>From e3001bd662b84dafeca200b52fc644b7bf81c4af Mon Sep 17 00:00:00 2001
From: Andrea Corallo 
Date: Thu, 7 Apr 2022 11:51:56 +0200
Subject: [PATCH] [PATCH 12/15] arm: implement bti injection

Hi all,

this patch enables Branch Target Identification Armv8.1-M Mechanism
[1].

This is achieved by using the bti pass made common with Aarch64.

The pass iterates through the instructions and adds the necessary BTI
instructions at the beginning of every function and at every landing
pads targeted by indirect jumps.

Best Regards

  Andrea

[1]


gcc/ChangeLog

2022-04-07  Andrea Corallo  

* config.gcc (arm*-*-*): Add 'aarch-bti-insert.o' object.
* config/arm/arm-protos.h: Update.
* config/arm/arm.cc (aarch_bti_enabled, aarch_bti_j_insn_p)
(aarch_pac_insn_p, aarch_gen_bti_c, aarch_gen_bti_j): New
functions.
* config/arm/arm.md (bti_nop): New insn.
* config/arm/t-arm (PASSES_EXTRA): Add 'arm-passes.def'.
(aarch-bti-insert.o): New target.
* config/arm/unspecs.md (UNSPEC_BTI_NOP): New unspec.
* config/arm/aarch-bti-insert.cc (rest_of_insert_bti): Update
to verify arch compatibility.
* config/arm/arm-passes.def: New file.

gcc/testsuite/ChangeLog

2022-04-07  Andrea Corallo  

* gcc.target/arm/bti-1.c: New testcase.
* gcc.target/arm/bti-2.c: Likewise.
---
 gcc/config.gcc   |  2 +-
 gcc/config/arm/arm-passes.def| 21 ++
 gcc/config/arm/arm-protos.h  |  2 +
 gcc/config/arm/arm.cc| 61 +---
 gcc/config/arm/arm.md|  7 
 gcc/config/arm/t-arm | 10 +
 gcc/config/arm/unspecs.md|  1 +
 gcc/testsuite/gcc.target/arm/bti-1.c | 12 ++
 gcc/testsuite/gcc.target/arm/bti-2.c | 58 ++
 9 files changed, 167 insertions(+), 7 deletions(-)
 create mode 100644 gcc/config/arm/arm-passes.def
 create mode 100644 gcc/testsuite/gcc.target/arm/bti-1.c
 create mode 100644 gcc/testsuite/gcc.target/arm/bti-2.c

diff --git a/gcc/config.gcc b/gcc/config.gcc
index 2021bdf9d2f..004e1dfa8d8 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -353,7 +353,7 @@ arc*-*-*)
;;
 arm*-*-*)
cpu_type=arm
-   extra_objs="arm-builtins.o arm-mve-builtins.o aarch-common.o"
+   extra_objs="arm-builtins.o arm-mve-builtins.o aarch-common.o 
aarch-bti-insert.o"
extra_headers="mmintrin.h arm_neon.h arm_acle.h arm_fp16.h arm_cmse.h 
arm_bf16.h arm_mve_types.h arm_mve.h arm_cde.h"
target_type_format_char='%'
c_target_objs="arm-c.o"
diff --git a/gcc/config/arm/arm-passes.def b/gcc/config/arm/arm-passes.def
new file mode 100644
index 000..71d6b563640
--- /dev/null
+++ b/gcc/config/arm/arm-passes.def
@@ -0,0 +1,21 @@
+/* Arm-specific passes declarations.
+   Copyright (C) 2022 Free Software Foundation, Inc.
+   Contributed by Arm Ltd.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3, or (at your option)
+   any later version.
+
+   GCC is distributed in the hope that it will be useful, but
+   WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+   General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with GCC; see the file COPYING3.  If not see
+   .  */
+
+INSERT_PASS_BEFORE (pass_shorten_branches, 1, pass_insert_bti);
diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h
index 84764bf27ce..6befb6c4445 100644
--- a/gcc/config/arm/arm-protos.h
+++ b/gcc/config/arm/arm-protos.h
@@ -24,6 +24,8 @@
 
 #include "sbitmap.h"
 
+rtl_opt_pass *make_pass_insert_bti (gcc::context *ctxt);
+
 extern enum unwind_info_type arm_except_unwind_info (struct gcc_options *);
 extern int use_return_insn (int, rtx);
 extern bool use_simple_return_p (void);
diff --git a/gcc/config/arm/arm.cc b/gcc/config/arm/arm.cc
index fa0f9a61498..26d4c1502f2 100644
--- a/gcc/config/arm/arm.cc
+++ b/gcc/config/arm/arm.cc
@@ -23374,12 +23374,6 @@ output_probe_stack_range (rtx reg1, rtx reg2)
   return "";
 }
 
-static bool
-aarch_bti_enabled ()
-{
-  return false;
-}
-
 /* Generate the prologue instructions for entry into an ARM or Thumb-2
function.  */
 void
@@ -32992,6 +32986,61 @@ arm_current_function_pac_enabled_p (void)
   && !crtl->is_leaf));
 }
 
+/* Return TRUE if Branch Target Identification Mechanism is enabled.  */
+bool
+aarch_bti_enabled

[PATCH 0/15] arm: Enables return address verification and branch target identification on Cortex-M

[Andrea Corallo via Gcc-patches]

Hi all,

as I respinned few patches, dropped one and added another, I'm reposting
this series thant enables return address verification and branch target
identification based on Armv8.1-M Pointer Authentication and Branch
Target Identification Extension [1] for Arm Cortex-M.

This feature is controlled by the newly introduced '-mbranch-protection'
option, contextually the Armv8.1-M Mainline target feature '+pacbti' is
added.

Best Regards

  Andrea

[1] 

[PATCH 1/15] arm: Make mbranch-protection opts parsing common to AArch32/64

[Andrea Corallo via Gcc-patches]

Hi all,

This change refactors all the mbranch-protection option parsing code and
types to make it common to both AArch32 and AArch64 backends.

This change also pulls in some supporting types from AArch64 to make
it common (aarch_parse_opt_result).

The significant changes in this patch are the movement of all branch
protection parsing routines from aarch64.c to aarch-common.c and
supporting data types and static data structures.

This patch also pre-declares variables and types required in the
aarch32 back-end for moved variables for function sign scope and key
to prepare for the impending series of patches that support parsing
the feature mbranch-protection in the aarch32 back-end.

Approved here


gcc/ChangeLog:

* common/config/aarch64/aarch64-common.cc: Include aarch-common.h.
(all_architectures): Fix comment.
(aarch64_parse_extension): Rename return type, enum value names.
* config/aarch64/aarch64-c.cc (aarch64_update_cpp_builtins): Rename
factored out aarch_ra_sign_scope and aarch_ra_sign_key variables.
Also rename corresponding enum values.
* config/aarch64/aarch64-opts.h (aarch64_function_type): Factor
out aarch64_function_type and move it to common code as
aarch_function_type in aarch-common.h.
* config/aarch64/aarch64-protos.h: Include common types header,
move out types aarch64_parse_opt_result and aarch64_key_type to
aarch-common.h
* config/aarch64/aarch64.cc: Move mbranch-protection parsing types
and functions out into aarch-common.h and aarch-common.cc.  Fix up
all the name changes resulting from the move.
* config/aarch64/aarch64.md: Fix up aarch64_ra_sign_key type name change
and enum value.
* config/aarch64/aarch64.opt: Include aarch-common.h to import
type move.  Fix up name changes from factoring out common code and
data.
* config/arm/aarch-common-protos.h: Export factored out routines to both
backends.
* config/arm/aarch-common.cc: Include newly factored out types.  Move 
all
mbranch-protection code and data structures from aarch64.cc.
* config/arm/aarch-common.h: New header that declares types shared
between aarch32 and aarch64 backends.
* config/arm/arm-protos.h: Declare types and variables that are
made common to aarch64 and aarch32 backends - aarch_ra_sign_key,
aarch_ra_sign_scope and aarch_enable_bti.

Co-Authored-By: Tejas Belagod  

diff --git a/gcc/common/config/aarch64/aarch64-common.cc 
b/gcc/common/config/aarch64/aarch64-common.cc
index dfda5b8372a..70a5cf98b75 100644
--- a/gcc/common/config/aarch64/aarch64-common.cc
+++ b/gcc/common/config/aarch64/aarch64-common.cc
@@ -30,6 +30,7 @@
 #include "opts.h"
 #include "flags.h"
 #include "diagnostic.h"
+#include "config/arm/aarch-common.h"
 
 #ifdef  TARGET_BIG_ENDIAN_DEFAULT
 #undef  TARGET_DEFAULT_TARGET_FLAGS
@@ -192,11 +193,11 @@ static const struct arch_to_arch_name all_architectures[] 
=
 
 /* Parse the architecture extension string STR and update ISA_FLAGS
with the architecture features turned on or off.  Return a
-   aarch64_parse_opt_result describing the result.
+   aarch_parse_opt_result describing the result.
When the STR string contains an invalid extension,
a copy of the string is created and stored to INVALID_EXTENSION.  */
 
-enum aarch64_parse_opt_result
+enum aarch_parse_opt_result
 aarch64_parse_extension (const char *str, uint64_t *isa_flags,
 std::string *invalid_extension)
 {
@@ -229,7 +230,7 @@ aarch64_parse_extension (const char *str, uint64_t 
*isa_flags,
adding_ext = 1;
 
   if (len == 0)
-   return AARCH64_PARSE_MISSING_ARG;
+   return AARCH_PARSE_MISSING_ARG;
 
 
   /* Scan over the extensions table trying to find an exact match.  */
@@ -251,13 +252,13 @@ aarch64_parse_extension (const char *str, uint64_t 
*isa_flags,
  /* Extension not found in list.  */
  if (invalid_extension)
*invalid_extension = std::string (str, len);
- return AARCH64_PARSE_INVALID_FEATURE;
+ return AARCH_PARSE_INVALID_FEATURE;
}
 
   str = ext;
 };
 
-  return AARCH64_PARSE_OK;
+  return AARCH_PARSE_OK;
 }
 
 /* Append all architecture extension candidates to the CANDIDATES vector.  */
diff --git a/gcc/config/aarch64/aarch64-c.cc b/gcc/config/aarch64/aarch64-c.cc
index caf8e332ea0..b0c5a4fd6b6 100644
--- a/gcc/config/aarch64/aarch64-c.cc
+++ b/gcc/config/aarch64/aarch64-c.cc
@@ -183,14 +183,14 @@ aarch64_update_cpp_builtins (cpp_reader *pfile)
"__ARM_FEATURE_BTI_DEFAULT", pfile);
 
   cpp_undef (pfile, "__ARM_FEATURE_PAC_DEFAULT");
-  if (aarch64_ra_sign_scope != AARCH64_FUNCTION_NONE)
+  if (aarch_ra_sign_scope != AARCH_FUNCTION_NONE)
 {
   int v = 0;
-  if (aarch64_ra_sign_key == AA

[PATCH 2/15] arm: Add Armv8.1-M Mainline target feature +pacbti

[Andrea Corallo via Gcc-patches]

This patch adds the -march feature +pacbti to Armv8.1-M Mainline.
This feature enables pointer signing and authentication instructions
on M-class architectures.

Pre-approved here
.

gcc/Changelog:

* config/arm/arm.h (TARGET_HAVE_PACBTI): New macro.
* config/arm/arm-cpus.in (pacbti): New feature.
* doc/invoke.texi (Arm Options): Document it.

Co-Authored-By: Tejas Belagod  

diff --git a/gcc/config/arm/arm-cpus.in b/gcc/config/arm/arm-cpus.in
index 0d3082b569f..9502a34fa97 100644
--- a/gcc/config/arm/arm-cpus.in
+++ b/gcc/config/arm/arm-cpus.in
@@ -229,6 +229,10 @@ define feature cdecp5
 define feature cdecp6
 define feature cdecp7
 
+# M-profile control flow integrity extensions (PAC/AUT/BTI).
+# Optional from Armv8.1-M Mainline.
+define feature pacbti
+
 # Feature groups.  Conventionally all (or mostly) upper case.
 # ALL_FPU lists all the feature bits associated with the floating-point
 # unit; these will all be removed if the floating-point unit is disabled
@@ -743,6 +747,7 @@ begin arch armv8.1-m.main
  isa ARMv8_1m_main
 # fp => FPv5-sp-d16; fp.dp => FPv5-d16
  option dsp add armv7em
+ option pacbti add pacbti
  option fp add FPv5 fp16
  option fp.dp add FPv5 FP_DBL fp16
  option nofp remove ALL_FP
diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
index f479540812a..3495ab857ea 100644
--- a/gcc/config/arm/arm.h
+++ b/gcc/config/arm/arm.h
@@ -335,6 +335,12 @@ emission of floating point pcs attributes.  */
isa_bit_mve_float) \
   && !TARGET_GENERAL_REGS_ONLY)
 
+/* Non-zero if this target supports Armv8.1-M Mainline pointer-signing
+   extension.  */
+#define TARGET_HAVE_PACBTI (arm_arch8_1m_main \
+   && bitmap_bit_p (arm_active_target.isa, \
+isa_bit_pacbti))
+
 /* MVE have few common instructions as VFP, like VLDM alias VPOP, VLDR, VSTM
alia VPUSH, VSTR and VMOV, VMSR and VMRS.  In the same manner it updates few
registers such as FPCAR, FPCCR, FPDSCR, FPSCR, MVFR0, MVFR1 and MVFR2.  All
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 3936aef69d0..079e34ed98c 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -21002,6 +21002,9 @@ Disable the floating-point extension.
 @item +cdecp0, +cdecp1, ... , +cdecp7
 Enable the Custom Datapath Extension (CDE) on selected coprocessors according
 to the numbers given in the options in the range 0 to 7.
+
+@item +pacbti
+Enable the Pointer Authentication and Branch Target Identification Extension.
 @end table
 
 @item  armv8-m.main

[PATCH 3/15] arm: Add option -mbranch-protection

[Andrea Corallo via Gcc-patches]

Hi all,

this adds -mbranch-protection option.  This option enables the
code-generation of pointer signing and authentication instructions in
function prologues and epilogues.

gcc/ChangeLog:

* config/arm/arm.c (arm_configure_build_target): Parse and validate
-mbranch-protection option and initialize appropriate data structures.
* config/arm/arm.opt (-mbranch-protection): New option.
* doc/invoke.texi (Arm Options): Document it.

Co-Authored-By: Tejas Belagod  
Co-Authored-By: Richard Earnshaw 

Approved here 

diff --git a/gcc/config/arm/arm.cc b/gcc/config/arm/arm.cc
index 60f3eae82a4..0068817b0f2 100644
--- a/gcc/config/arm/arm.cc
+++ b/gcc/config/arm/arm.cc
@@ -3263,6 +3263,17 @@ arm_configure_build_target (struct arm_build_target 
*target,
   tune_opts = strchr (opts->x_arm_tune_string, '+');
 }
 
+  if (opts->x_arm_branch_protection_string)
+{
+  aarch_validate_mbranch_protection (opts->x_arm_branch_protection_string);
+
+  if (aarch_ra_sign_key != AARCH_KEY_A)
+   {
+ warning (0, "invalid key type for %<-mbranch-protection=%>");
+ aarch_ra_sign_key = AARCH_KEY_A;
+   }
+}
+
   if (arm_selected_arch)
 {
   arm_initialize_isa (target->isa, arm_selected_arch->common.isa_bits);
diff --git a/gcc/config/arm/arm.opt b/gcc/config/arm/arm.opt
index f54ec8356c3..d292e23ea11 100644
--- a/gcc/config/arm/arm.opt
+++ b/gcc/config/arm/arm.opt
@@ -323,6 +323,10 @@ mbranch-cost=
 Target RejectNegative Joined UInteger Var(arm_branch_cost) Init(-1)
 Cost to assume for a branch insn.
 
+mbranch-protection=
+Target RejectNegative Joined Var(arm_branch_protection_string) Save
+Use branch-protection features.
+
 mgeneral-regs-only
 Target RejectNegative Mask(GENERAL_REGS_ONLY) Save
 Generate code which uses the core registers only (r0-r14).
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 079e34ed98c..a2be3446594 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -825,7 +825,9 @@ Objective-C and Objective-C++ Dialects}.
 -mcmse @gol
 -mfix-cmse-cve-2021-35465 @gol
 -mstack-protector-guard=@var{guard} 
-mstack-protector-guard-offset=@var{offset} @gol
--mfdpic}
+-mfdpic @gol
+-mbranch-protection=@var{none}|@var{standard}|@var{pac-ret}[+@var{leaf}]
+[+@var{bti}]|@var{bti}[+@var{pac-ret}[+@var{leaf}]]}
 
 @emph{AVR Options}
 @gccoptlist{-mmcu=@var{mcu}  -mabsdata  -maccumulate-args @gol
@@ -21521,6 +21523,40 @@ The opposite @option{-mno-fdpic} option is useful (and 
required) to
 build the Linux kernel using the same (@code{arm-*-uclinuxfdpiceabi})
 toolchain as the one used to build the userland programs.
 
+@item
+-mbranch-protection=@var{none}|@var{standard}|@var{pac-ret}[+@var{leaf}][+@var{bti}]|@var{bti}[+@var{pac-ret}[+@var{leaf}]]
+@opindex mbranch-protection
+Enable branch protection features (armv8.1-m.main only).
+@samp{none} generate code without branch protection or return address
+signing.
+@samp{standard[+@var{leaf}]} generate code with all branch protection
+features enabled at their standard level.
+@samp{pac-ret[+@var{leaf}]} generate code with return address signing
+set to its standard level, which is to sign all functions that save
+the return address to memory.
+@samp{leaf} When return address signing is enabled, also sign leaf
+functions even if they do not write the return address to memory.
++@samp{bti} Add landing-pad instructions at the permitted targets of
+indirect branch instructions.
+
+If the @samp{+pacbti} architecture extension is not enabled, then all
+branch protection and return address signing operations are
+constrained to use only the instructions defined in the
+architectural-NOP space. The generated code will remain
+backwards-compatible with earlier versions of the architecture, but
+the additional security can be enabled at run time on processors that
+support the @samp{PACBTI} extension.
+
+Branch target enforcement using BTI can only be enabled at runtime if
+all code in the application has been compiled with at least
+@samp{-mbranch-protection=bti}.
+
+Any setting other than @samp{none} is supported only on armv8-m.main
+or later.
+
+The default is to generate code without branch protection or return
+address signing.
+
 @end table
 
 @node AVR Options

[PATCH 4/15] arm: Add testsuite library support for PACBTI target

[Andrea Corallo via Gcc-patches]

Hi all,

this adds targeting-checking entities for PACBTI in testsuite
framework.

Pre-approved with the requested changes here
.

gcc/testsuite/ChangeLog:

* testsuite/lib/target-supports.exp:
(check_effective_target_arm_pacbti_hw): New.
* doc/sourcebuild.texi: Document arm_pacbti_hw.

Co-Authored-By: Tejas Belagod  

diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi
index 613ac29967b..a3f60e9c0cb 100644
--- a/gcc/doc/sourcebuild.texi
+++ b/gcc/doc/sourcebuild.texi
@@ -2167,6 +2167,10 @@ ARM target supports options to generate instructions 
from ARMv8.1-M with
 the Custom Datapath Extension (CDE) and M-Profile Vector Extension (MVE).
 Some multilibs may be incompatible with these options.
 
+@item arm_pacbti_hw
+Test system supports executing Pointer Authentication and Branch Target
+Identification instructions.
+
 @item arm_prefer_ldrd_strd
 ARM target prefers @code{LDRD} and @code{STRD} instructions over
 @code{LDM} and @code{STM} instructions.
@@ -2256,6 +2260,12 @@ ARM target generates Thumb-2 code for @code{-mthumb} but 
does not
 support executing the Armv8.1-M Mainline Low Overhead Loop
 instructions @code{DLS} and @code{LE}.
 
+@item mbranch_protection_ok
+ARM target supporting @code{-mbranch-protection=standard}.
+
+@item arm_pacbti_hw
+Test system supports for executing non nop pacbti instructions.
+
 @end table
 
 @subsubsection AArch64-specific attributes
diff --git a/gcc/testsuite/lib/target-supports.exp 
b/gcc/testsuite/lib/target-supports.exp
index ff8edbd3e17..aa828bd3a07 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -5090,6 +5090,22 @@ proc check_effective_target_arm_cmse_clear_ok {} {
 } "-mcmse"];
 }
 
+# Return 1 if the target supports executing PACBTI instructions, 0
+# otherwise.
+
+proc check_effective_target_arm_pacbti_hw {} {
+return [check_runtime arm_pacbti_hw_available {
+   __attribute__ ((naked)) int
+   main (void)
+   {
+ asm ("pac r12, lr, sp");
+ asm ("mov r0, #0");
+ asm ("autg r12, lr, sp");
+ asm ("bx lr");
+   }
+} "-march=armv8.1-m.main+pacbti+fp -mbranch-protection=standard -mthumb 
-mfloat-abi=hard"]
+}
+
 # Return 1 if this compilation turns on string_ops_prefer_neon on.
 
 proc check_effective_target_arm_tune_string_ops_prefer_neon { } {

[PATCH 5/15] arm: Implement target feature macros for PACBTI

[Andrea Corallo via Gcc-patches]

This patch implements target feature macros when PACBTI is enabled
through the -march option or -mbranch-protection.  The target feature
macros __ARM_FEATURE_PAC_DEFAULT and __ARM_FEATURE_BTI_DEFAULT are
specified in ARM ACLE

__ARM_FEATURE_PAUTH and __ARM_FEATURE_BTI are specified in the
pull-request .

Approved here
.

gcc/

* config/arm/arm-c.c (arm_cpu_builtins): Define
__ARM_FEATURE_BTI_DEFAULT, __ARM_FEATURE_PAC_DEFAULT,
__ARM_FEATURE_PAUTH and __ARM_FEATURE_BTI.

gcc/testsuite/

* lib/target-supports.exp
(check_effective_target_mbranch_protection_ok): New function.
* gcc.target/arm/acle/pacbti-m-predef-2.c: New test.
* gcc.target/arm/acle/pacbti-m-predef-4.c: Likewise.
* gcc.target/arm/acle/pacbti-m-predef-5.c: Likewise.
* gcc.target/arm/acle/pacbti-m-predef-8.c: Likewise.
* gcc.target/arm/acle/pacbti-m-predef-9.c: Likewise.
* gcc.target/arm/acle/pacbti-m-predef-10.c: Likewise.
* gcc.target/arm/acle/pacbti-m-predef-11.c: Likewise.
* gcc.target/arm/acle/pacbti-m-predef-12.c: Likewise.

Co-Authored-By: Tejas Belagod  

diff --git a/gcc/config/arm/arm-c.cc b/gcc/config/arm/arm-c.cc
index a8697b8c62f..190099b2c37 100644
--- a/gcc/config/arm/arm-c.cc
+++ b/gcc/config/arm/arm-c.cc
@@ -212,6 +212,24 @@ arm_cpu_builtins (struct cpp_reader* pfile)
   def_or_undef_macro (pfile, "__ARM_FEATURE_COMPLEX", TARGET_COMPLEX);
   def_or_undef_macro (pfile, "__ARM_32BIT_STATE", TARGET_32BIT);
 
+  def_or_undef_macro (pfile, "__ARM_FEATURE_PAUTH", TARGET_HAVE_PACBTI);
+  def_or_undef_macro (pfile, "__ARM_FEATURE_BTI", TARGET_HAVE_PACBTI);
+  def_or_undef_macro (pfile, "__ARM_FEATURE_BTI_DEFAULT",
+ aarch_enable_bti == 1);
+
+  cpp_undef (pfile, "__ARM_FEATURE_PAC_DEFAULT");
+  if (aarch_ra_sign_scope != AARCH_FUNCTION_NONE)
+  {
+unsigned int pac = 1;
+
+gcc_assert (aarch_ra_sign_key == AARCH_KEY_A);
+
+if (aarch_ra_sign_scope == AARCH_FUNCTION_ALL)
+  pac |= 0x4;
+
+builtin_define_with_int_value ("__ARM_FEATURE_PAC_DEFAULT", pac);
+  }
+
   cpp_undef (pfile, "__ARM_FEATURE_MVE");
   if (TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT)
 {
diff --git a/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-10.c 
b/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-10.c
new file mode 100644
index 000..52d18238109
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-10.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target mbranch_protection_ok } */
+/* { dg-additional-options "-march=armv8.1-m.main+fp 
-mbranch-protection=bti+pac-ret -mfloat-abi=hard" } */
+
+#if (__ARM_FEATURE_BTI_DEFAULT != 1)
+#error "Feature test macro __ARM_FEATURE_BTI_DEFAULT should be defined to 1."
+#endif
+
+#if !defined (__ARM_FEATURE_PAC_DEFAULT)
+#error "Feature test macro __ARM_FEATURE_PAC_DEFAULT should be defined."
+#endif
diff --git a/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-11.c 
b/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-11.c
new file mode 100644
index 000..9f2711097ac
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-11.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-marm" 
"-mcpu=*" "-mfloat-abi=*" } } */
+/* { dg-options "-march=armv8.1-m.main+pacbti" } */
+
+#if (__ARM_FEATURE_BTI != 1)
+#error "Feature test macro __ARM_FEATURE_BTI_DEFAULT should be defined to 1."
+#endif
+
+#if (__ARM_FEATURE_PAUTH != 1)
+#error "Feature test macro __ARM_FEATURE__PAUTH should be defined to 1."
+#endif
diff --git a/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-12.c 
b/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-12.c
new file mode 100644
index 000..db40b17c3b0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-12.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-marm" 
"-mcpu=*" } } */
+/* { dg-options "-march=armv8-m.main+fp -mfloat-abi=softfp" } */
+
+#if defined (__ARM_FEATURE_BTI)
+#error "Feature test macro __ARM_FEATURE_BTI should not be defined."
+#endif
+
+#if defined (__ARM_FEATURE_PAUTH)
+#error "Feature test macro __ARM_FEATURE_PAUTH should not be defined."
+#endif
diff --git a/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-2.c 
b/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-2.c
new file mode 100644
index 000..cd418ce0c7f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-2.c
@@ -0,0 +1,24 @@
+/* { dg-do run } */
+/* { dg-require-effective-target mbranch_protection_ok } */
+/* { dg-require-effective-target arm_pacbti_hw } */
+/* { dg-options "-march=armv8.1-m.main+pacbti+fp 
-mbranch-protection=bti+pac-ret+leaf -mthumb -mfloa

[PATCH 6/15] arm: Add pointer authentication for stack-unwinding runtime

[Andrea Corallo via Gcc-patches]

Hi all,

this patch adds authentication for when the stack is unwound when an
exception is taken.  All the changes here are done to the runtime code
in libgcc's unwinder code for Arm target. All the changes are guarded
under defined (__ARM_FEATURE_PAC_DEFAULT) and activated only if the
+pacbti feature is switched on for the architecture. This means that
switching on the target feature via -march or -mcpu is sufficient and
-mbranch-protection need not be enabled. This ensures that the
unwinder is authenticated only if the PACBTI instructions are
available in the non-NOP space as it uses AUTG.  Just generating
PAC/AUT instructions using -mbranch-protection will not enable
authentication on the unwinder.

Arroved here:


gcc/ChangeLog:

* ginclude/unwind-arm-common.h (_Unwind_VRS_RegClass): Introduce
new pseudo register class _UVRSC_PAC.
* libgcc/config/arm/pr-support.c (__gnu_unwind_execute): Decode
exception opcode (0xb4) for saving RA_AUTH_CODE and authenticate
with AUTG if found.
* libgcc/config/arm/unwind-arm.c (struct pseudo_regs): New.
(phase1_vrs): Introduce new field to store pseudo-reg state.
(phase2_vrs): Likewise.
(_Unwind_VRS_Get): Load pseudo register state from virtual reg set.
(_Unwind_VRS_Set): Store pseudo register state to virtual reg set.
(_Unwind_VRS_Pop): Load pseudo register value from stack into VRS.

Co-Authored-By: Tejas Belagod  

diff --git a/gcc/ginclude/unwind-arm-common.h b/gcc/ginclude/unwind-arm-common.h
index d3831f6c60a..f26702e8c6c 100644
--- a/gcc/ginclude/unwind-arm-common.h
+++ b/gcc/ginclude/unwind-arm-common.h
@@ -127,7 +127,8 @@ extern "C" {
   _UVRSC_VFP = 1,   /* vfp */
   _UVRSC_FPA = 2,   /* fpa */
   _UVRSC_WMMXD = 3, /* Intel WMMX data register */
-  _UVRSC_WMMXC = 4  /* Intel WMMX control register */
+  _UVRSC_WMMXC = 4, /* Intel WMMX control register */
+  _UVRSC_PAC = 5/* Armv8.1-M Mainline PAC/AUTH pseudo-register */
 }
   _Unwind_VRS_RegClass;
 
diff --git a/libgcc/config/arm/pr-support.c b/libgcc/config/arm/pr-support.c
index 2de96c2a447..e48854587c6 100644
--- a/libgcc/config/arm/pr-support.c
+++ b/libgcc/config/arm/pr-support.c
@@ -106,6 +106,7 @@ __gnu_unwind_execute (_Unwind_Context * context, 
__gnu_unwind_state * uws)
 {
   _uw op;
   int set_pc;
+  int set_pac = 0;
   _uw reg;
 
   set_pc = 0;
@@ -114,6 +115,27 @@ __gnu_unwind_execute (_Unwind_Context * context, 
__gnu_unwind_state * uws)
   op = next_unwind_byte (uws);
   if (op == CODE_FINISH)
{
+ /* When we reach end, we have to authenticate R12 we just popped
+earlier.
+
+Note: while the check provides additional security against a
+corrupted unwind chain, it isn't essential for correct unwinding
+of an uncorrupted chain.  */
+#if defined(TARGET_HAVE_PACBTI)
+ if (set_pac)
+   {
+ _uw sp;
+ _uw lr;
+ _uw pac;
+ _Unwind_VRS_Get (context, _UVRSC_CORE, R_SP, _UVRSD_UINT32, &sp);
+ _Unwind_VRS_Get (context, _UVRSC_CORE, R_LR, _UVRSD_UINT32, &lr);
+ _Unwind_VRS_Get (context, _UVRSC_PAC, R_IP,
+  _UVRSD_UINT32, &pac);
+ __asm__ __volatile__
+   ("autg %0, %1, %2" : : "r"(pac), "r"(lr), "r"(sp) :);
+   }
+#endif
+
  /* If we haven't already set pc then copy it from lr.  */
  if (!set_pc)
{
@@ -227,6 +249,16 @@ __gnu_unwind_execute (_Unwind_Context * context, 
__gnu_unwind_state * uws)
return _URC_FAILURE;
  continue;
}
+ /* Pop PAC off the stack into VRS pseudo.pac.  */
+ if (op == 0xb4)
+   {
+ if (_Unwind_VRS_Pop (context, _UVRSC_PAC, 0, _UVRSD_UINT32)
+ != _UVRSR_OK)
+   return _URC_FAILURE;
+ set_pac = 1;
+ continue;
+   }
+
  if ((op & 0xfc) == 0xb4)  /* Obsolete FPA.  */
return _URC_FAILURE;
 
diff --git a/libgcc/config/arm/unwind-arm.c b/libgcc/config/arm/unwind-arm.c
index 386406564af..89f945d047e 100644
--- a/libgcc/config/arm/unwind-arm.c
+++ b/libgcc/config/arm/unwind-arm.c
@@ -64,6 +64,12 @@ struct wmmxc_regs
   _uw wc[4];
 };
 
+/*  Holds value of pseudo registers eg. PAC.  */
+struct pseudo_regs
+{
+  _uw pac;
+};
+
 /* The ABI specifies that the unwind routines may only use core registers,
except when actually manipulating coprocessor state.  This allows
us to write one implementation that works on all platforms by
@@ -78,6 +84,9 @@ typedef struct
   /* The first fields must be the same as a phase2_vrs.  */
   _uw demand_save_flags;
   struct core_regs core;
+  /* Armv8.1-M Mainline PAC/AUTH values.  This field should be in the same 
field
+ order as phase2_vrs.  */
+  struc

[PATCH 7/15] arm: Emit build attributes for PACBTI target feature

[Andrea Corallo via Gcc-patches]

This patch emits assembler directives for PACBTI build attributes as
defined by the
ABI.



gcc/ChangeLog:

* config/arm/arm.c (arm_file_start): Emit EABI attributes for
Tag_PAC_extension, Tag_BTI_extension, TAG_BTI_use, TAG_PACRET_use.

gcc/testsuite/ChangeLog:

* gcc.target/arm/acle/pacbti-m-predef-1.c: New test.
* gcc.target/arm/acle/pacbti-m-predef-3: Likewise.
* gcc.target/arm/acle/pacbti-m-predef-6.c: Likewise.
* gcc.target/arm/acle/pacbti-m-predef-7.c: Likewise.

Co-Authored-By: Tejas Belagod  

diff --git a/gcc/config/arm/arm.cc b/gcc/config/arm/arm.cc
index 0068817b0f2..ceec14f84b6 100644
--- a/gcc/config/arm/arm.cc
+++ b/gcc/config/arm/arm.cc
@@ -28349,6 +28349,8 @@ static void
 arm_file_start (void)
 {
   int val;
+  bool pac = (aarch_ra_sign_scope != AARCH_FUNCTION_NONE);
+  bool bti = (aarch_enable_bti == 1);
 
   arm_print_asm_arch_directives
 (asm_out_file, TREE_TARGET_OPTION (target_option_default_node));
@@ -28419,6 +28421,22 @@ arm_file_start (void)
arm_emit_eabi_attribute ("Tag_ABI_FP_16bit_format", 38,
 (int) arm_fp16_format);
 
+  if (TARGET_HAVE_PACBTI)
+   {
+ arm_emit_eabi_attribute ("Tag_PAC_extension", 50, 2);
+ arm_emit_eabi_attribute ("Tag_BTI_extension", 52, 2);
+   }
+  else if (pac || bti)
+   {
+ arm_emit_eabi_attribute ("Tag_PAC_extension", 50, 1);
+ arm_emit_eabi_attribute ("Tag_BTI_extension", 52, 1);
+   }
+
+  if (bti)
+arm_emit_eabi_attribute ("TAG_BTI_use", 74, 1);
+  if (pac)
+   arm_emit_eabi_attribute ("TAG_PACRET_use", 76, 1);
+
   if (arm_lang_output_object_attributes_hook)
arm_lang_output_object_attributes_hook();
 }
diff --git a/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-1.c 
b/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-1.c
new file mode 100644
index 000..122f7a762a7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-1.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target mbranch_protection_ok } */
+/* { dg-options "-march=armv8.1-m.main+fp -mbranch-protection=pac-ret+bti 
-mfloat-abi=hard --save-temps" } */
+
+#if !defined (__ARM_FEATURE_BTI_DEFAULT)
+#error "Feature test macro __ARM_FEATURE_BTI_DEFAULT should be defined."
+#endif
+
+#if !defined (__ARM_FEATURE_PAC_DEFAULT)
+#error "Feature test macro __ARM_FEATURE_PAC_DEFAULT should be defined."
+#endif
+
+/* { dg-final { scan-assembler-not "\.arch_extension pacbti" } } */
+/* { dg-final { scan-assembler "\.eabi_attribute 50, 1" } } */
+/* { dg-final { scan-assembler "\.eabi_attribute 52, 1" } } */
+/* { dg-final { scan-assembler "\.eabi_attribute 74, 1" } } */
+/* { dg-final { scan-assembler "\.eabi_attribute 76, 1" } } */
diff --git a/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-3.c 
b/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-3.c
new file mode 100644
index 000..b94f3447ad9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-3.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target mbranch_protection_ok } */
+/* { dg-options "-march=armv8.1-m.main+fp -mbranch-protection=pac-ret+leaf 
-mfloat-abi=hard --save-temps" } */
+
+#if defined (__ARM_FEATURE_BTI_DEFAULT)
+#error "Feature test macro __ARM_FEATURE_BTI_DEFAULT should be undefined."
+#endif
+
+#if !defined (__ARM_FEATURE_PAC_DEFAULT)
+#error "Feature test macro __ARM_FEATURE_PAC_DEFAULT should be defined."
+#endif
+
+/* { dg-final { scan-assembler-not "\.arch_extension pacbti" } } */
+/* { dg-final { scan-assembler "\.eabi_attribute 50, 1" } } */
+/* { dg-final { scan-assembler "\.eabi_attribute 52, 1" } } */
+/* { dg-final { scan-assembler-not "\.eabi_attribute 74" } } */
+/* { dg-final { scan-assembler "\.eabi_attribute 76, 1" } } */
diff --git a/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-6.c 
b/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-6.c
new file mode 100644
index 000..ed52afc83c5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-6.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target mbranch_protection_ok } */
+/* { dg-additional-options "-march=armv8.1-m.main+fp -mbranch-protection=bti 
-mfloat-abi=hard --save-temps" } */
+
+#if !defined (__ARM_FEATURE_BTI_DEFAULT)
+#error "Feature test macro __ARM_FEATURE_BTI_DEFAULT should be defined."
+#endif
+
+#if defined (__ARM_FEATURE_PAC_DEFAULT)
+#error "Feature test macro __ARM_FEATURE_PAC_DEFAULT should be undefined."
+#endif
+/* { dg-final { scan-assembler-not "\.arch_extension pacbti" } } */
+/* { dg-final { scan-assembler "\.eabi_attribute 50, 1" } } */
+/* { dg-final { scan-assembler "\.eabi_attribute 52, 1" } } */
+/* { dg-final { scan-assembler "\.eabi_attribute 74, 1" } } */
+/* { dg-final { scan-assembler-not "\.eabi_attribute 76" } } */
diff --git a/g

[PATCH 8/15] arm: Introduce multilibs for PACBTI target feature

[Andrea Corallo via Gcc-patches]

This patch add the following new multilibs.

thumb/v8.1-m.main+pacbti/mbranch-protection/nofp
thumb/v8.1-m.main+pacbti+dp/mbranch-protection/soft
thumb/v8.1-m.main+pacbti+dp/mbranch-protection/hard
thumb/v8.1-m.main+pacbti+fp/mbranch-protection/soft
thumb/v8.1-m.main+pacbti+fp/mbranch-protection/hard
thumb/v8.1-m.main+pacbti+mve/mbranch-protection/hard

Triggering the following compiler flags:

-mthumb -march=armv8.1-m.main+pacbti -mbranch-protection=standard 
-mfloat-abi=soft
-mthumb -march=armv8.1-m.main+pacbti+fp -mbranch-protection=standard 
-mfloat-abi=softfp
-mthumb -march=armv8.1-m.main+pacbti+fp -mbranch-protection=standard 
-mfloat-abi=hard
-mthumb -march=armv8.1-m.main+pacbti+fp.dp -mbranch-protection=standard 
-mfloat-abi=softfp
-mthumb -march=armv8.1-m.main+pacbti+fp.dp -mbranch-protection=standard 
-mfloat-abi=hard
-mthumb -march=armv8.1-m.main+pacbti+mve -mbranch-protection=standard 
-mfloat-abi=hard

Approved here:


gcc/

* config/arm/t-rmprofile: Add multilib rules for march +pacbti
  and mbranch-protection.

gcc/testsuite/

* gcc.target/arm/multilib.exp: Add pacbti related entries.

diff --git a/gcc/config/arm/t-rmprofile b/gcc/config/arm/t-rmprofile
index eb321e832f1..fe46a1efa1a 100644
--- a/gcc/config/arm/t-rmprofile
+++ b/gcc/config/arm/t-rmprofile
@@ -27,8 +27,11 @@
 
 # Arch and FPU variants to build libraries with
 
-MULTI_ARCH_OPTS_RM = 
march=armv6s-m/march=armv7-m/march=armv7e-m/march=armv7e-m+fp/march=armv7e-m+fp.dp/march=armv8-m.base/march=armv8-m.main/march=armv8-m.main+fp/march=armv8-m.main+fp.dp/march=armv8.1-m.main+mve
-MULTI_ARCH_DIRS_RM = v6-m v7-m v7e-m v7e-m+fp v7e-m+dp v8-m.base v8-m.main 
v8-m.main+fp v8-m.main+dp v8.1-m.main+mve
+MULTI_ARCH_OPTS_RM = 
march=armv6s-m/march=armv7-m/march=armv7e-m/march=armv7e-m+fp/march=armv7e-m+fp.dp/march=armv8-m.base/march=armv8-m.main/march=armv8-m.main+fp/march=armv8-m.main+fp.dp/march=armv8.1-m.main+mve/march=armv8.1-m.main+pacbti/march=armv8.1-m.main+pacbti+fp/march=armv8.1-m.main+pacbti+fp.dp/march=armv8.1-m.main+pacbti+mve
+MULTI_ARCH_DIRS_RM = v6-m v7-m v7e-m v7e-m+fp v7e-m+dp v8-m.base v8-m.main 
v8-m.main+fp v8-m.main+dp v8.1-m.main+mve v8.1-m.main+pacbti 
v8.1-m.main+pacbti+fp v8.1-m.main+pacbti+dp v8.1-m.main+pacbti+mve
+
+MULTI_ARCH_OPTS_RM += mbranch-protection=standard
+MULTI_ARCH_DIRS_RM += mbranch-protection
 
 # Base M-profile (no fp)
 MULTILIB_REQUIRED  += mthumb/march=armv6s-m/mfloat-abi=soft
@@ -50,6 +53,13 @@ MULTILIB_REQUIRED+= 
mthumb/march=armv8-m.main+fp.dp/mfloat-abi=hard
 MULTILIB_REQUIRED  += mthumb/march=armv8-m.main+fp.dp/mfloat-abi=softfp
 MULTILIB_REQUIRED  += mthumb/march=armv8.1-m.main+mve/mfloat-abi=hard
 
+MULTILIB_REQUIRED  += 
mthumb/march=armv8.1-m.main+pacbti/mbranch-protection=standard/mfloat-abi=soft
+MULTILIB_REQUIRED  += 
mthumb/march=armv8.1-m.main+pacbti+fp/mbranch-protection=standard/mfloat-abi=softfp
+MULTILIB_REQUIRED  += 
mthumb/march=armv8.1-m.main+pacbti+fp/mbranch-protection=standard/mfloat-abi=hard
+MULTILIB_REQUIRED  += 
mthumb/march=armv8.1-m.main+pacbti+fp.dp/mbranch-protection=standard/mfloat-abi=softfp
+MULTILIB_REQUIRED  += 
mthumb/march=armv8.1-m.main+pacbti+fp.dp/mbranch-protection=standard/mfloat-abi=hard
+MULTILIB_REQUIRED  += 
mthumb/march=armv8.1-m.main+pacbti+mve/mbranch-protection=standard/mfloat-abi=hard
+
 # Arch Matches
 MULTILIB_MATCHES   += march?armv6s-m=march?armv6-m
 
@@ -87,9 +97,23 @@ MULTILIB_MATCHES += $(foreach FP, $(v8_1m_sp_variants), \
 MULTILIB_MATCHES += $(foreach FP, $(v8_1m_dp_variants), \
 
march?armv8-m.main+fp.dp=mlibarch?armv8.1-m.main$(FP))
 
+# Map all mbranch-protection values other than 'none' to 'standard'.
+MULTILIB_MATCHES   += mbranch-protection?standard=mbranch-protection?bti
+MULTILIB_MATCHES   += 
mbranch-protection?standard=mbranch-protection?pac-ret
+MULTILIB_MATCHES   += 
mbranch-protection?standard=mbranch-protection?pac-ret+leaf
+MULTILIB_MATCHES   += 
mbranch-protection?standard=mbranch-protection?pac-ret+bti
+MULTILIB_MATCHES   += 
mbranch-protection?standard=mbranch-protection?pac-ret+leaf+bti
+MULTILIB_MATCHES   += 
mbranch-protection?standard=mbranch-protection?bti+pac-ret
+MULTILIB_MATCHES   += 
mbranch-protection?standard=mbranch-protection?bti+pac-ret+leaf
+MULTILIB_MATCHES   += 
mbranch-protection?standard=mbranch-protection?standard+leaf
+
 # For all the MULTILIB_REQUIRED for v8-m and above, add MULTILIB_MATCHES which
 # maps mlibarch with march for multilib linking.
 MULTILIB_MATCHES   += march?armv8-m.main=mlibarch?armv8-m.main
 MULTILIB_MATCHES   += march?armv8-m.main+fp=mlibarch?armv8-m.main+fp
 MULTILIB_MATCHES   += march?armv8-m.main+fp.dp=mlibarch?armv8-m.main+fp.dp
 MULTILIB_MATCHES   += march?armv8.1-m.main+mve=mlibarch?armv8.1-m.main+mve
+MULTILIB_MATCHES   += 
march?armv8.

[PATCH 9/15] arm: Set again stack pointer as CFA reg when popping if necessary

[Andrea Corallo via Gcc-patches]

Hi all,

this patch enables 'arm_emit_multi_reg_pop' to set again the stack
pointer as CFA reg when popping if this is necessary.

/gcc/

* config/arm/arm.cc (arm_emit_multi_reg_pop): If the frame pointer
was set define again the stack pointer as CFA reg when popping.

diff --git a/gcc/config/arm/arm.cc b/gcc/config/arm/arm.cc
index ceec14f84b6..a5cf4225aa2 100644
--- a/gcc/config/arm/arm.cc
+++ b/gcc/config/arm/arm.cc
@@ -22303,8 +22303,18 @@ arm_emit_multi_reg_pop (unsigned long saved_regs_mask)
 
   REG_NOTES (par) = dwarf;
   if (!return_in_pc)
-arm_add_cfa_adjust_cfa_note (par, UNITS_PER_WORD * num_regs,
-stack_pointer_rtx, stack_pointer_rtx);
+{
+  /* If the frame pointer was set define again the stack pointer
+ as CFA reg.  */
+  if (frame_pointer_needed)
+{
+  RTX_FRAME_RELATED_P (par) = 1;
+  add_reg_note (par, REG_CFA_DEF_CFA, stack_pointer_rtx);
+}
+  else
+arm_add_cfa_adjust_cfa_note (par, UNITS_PER_WORD * num_regs,
+ stack_pointer_rtx, stack_pointer_rtx);
+}
 }
 
 /* Generate and emit an insn pattern that we will recognize as a pop_multi

[PATCH 10/15] arm: Implement cortex-M return signing address codegen

[Andrea Corallo via Gcc-patches]

Hi all,

this patch enables address return signature and verification based on
Armv8.1-M Pointer Authentication [1].

To sign the return address, we use the PAC R12, LR, SP instruction
upon function entry.  This is signing LR using SP and storing the
result in R12.  R12 will be pushed into the stack.

During function epilogue R12 will be popped and AUT R12, LR, SP will
be used to verify that the content of LR is still valid before return.

Here an example of PAC instrumented function prologue and epilogue:

void foo (void);

int main()
{
  foo ();
  return 0;
}

Compiled with '-march=armv8.1-m.main -mbranch-protection=pac-ret
-mthumb' translates into:

main:
pac ip, lr, sp
push{r3, r7, ip, lr}
add r7, sp, #0
bl  foo
movsr3, #0
mov r0, r3
pop {r3, r7, ip, lr}
aut ip, lr, sp
bx  lr

The patch also takes care of generating a PACBTI instruction in place
of the sequence BTI+PAC when Branch Target Identification is enabled
contextually.

Ex. the previous example compiled with '-march=armv8.1-m.main
-mbranch-protection=pac-ret+bti -mthumb' translates into:

main:
pacbti  ip, lr, sp
push{r3, r7, ip, lr}
add r7, sp, #0
bl  foo
movsr3, #0
mov r0, r3
pop {r3, r7, ip, lr}
aut ip, lr, sp
bx  lr

As part of previous upstream suggestions a test for varargs has been
added and '-mtpcs-frame' is deemed being incompatible with this return
signing address feature being introduced.

[1] 


gcc/Changelog

2021-11-03  Andrea Corallo  

* config/arm/arm.c: (arm_compute_frame_layout)
(arm_expand_prologue, thumb2_expand_return, arm_expand_epilogue)
(arm_conditional_register_usage): Update for pac codegen.
(arm_current_function_pac_enabled_p): New function.
* config/arm/arm.md (pac_ip_lr_sp, pacbti_ip_lr_sp, aut_ip_lr_sp):
Add new patterns.
* config/arm/unspecs.md (UNSPEC_PAC_IP_LR_SP)
(UNSPEC_PACBTI_IP_LR_SP, UNSPEC_AUT_IP_LR_SP): Add unspecs.

gcc/testsuite/Changelog

2021-11-03  Andrea Corallo  

* gcc.target/arm/pac.h : New file.
* gcc.target/arm/pac-1.c : New test case.
* gcc.target/arm/pac-2.c : Likewise.
* gcc.target/arm/pac-3.c : Likewise.
* gcc.target/arm/pac-4.c : Likewise.
* gcc.target/arm/pac-5.c : Likewise.
* gcc.target/arm/pac-6.c : Likewise.
* gcc.target/arm/pac-7.c : Likewise.
* gcc.target/arm/pac-8.c : Likewise.

diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h
index cff7ff1da2a..84764bf27ce 100644
--- a/gcc/config/arm/arm-protos.h
+++ b/gcc/config/arm/arm-protos.h
@@ -379,6 +379,7 @@ extern int vfp3_const_double_for_bits (rtx);
 extern void arm_emit_coreregs_64bit_shift (enum rtx_code, rtx, rtx, rtx, rtx,
   rtx);
 extern bool arm_fusion_enabled_p (tune_params::fuse_ops);
+extern bool arm_current_function_pac_enabled_p (void);
 extern bool arm_valid_symbolic_address_p (rtx);
 extern bool arm_validize_comparison (rtx *, rtx *, rtx *);
 extern bool arm_expand_vector_compare (rtx, rtx_code, rtx, rtx, bool);
diff --git a/gcc/config/arm/arm.cc b/gcc/config/arm/arm.cc
index a5cf4225aa2..31c6bcdea55 100644
--- a/gcc/config/arm/arm.cc
+++ b/gcc/config/arm/arm.cc
@@ -3209,6 +3209,9 @@ arm_option_override_internal (struct gcc_options *opts,
   arm_stack_protector_guard_offset = offs;
 }
 
+  if (arm_current_function_pac_enabled_p () && !(arm_arch7 && arm_arch_cmse))
+error ("This architecture does not support branch protection 
instructions");
+
 #ifdef SUBTARGET_OVERRIDE_INTERNAL_OPTIONS
   SUBTARGET_OVERRIDE_INTERNAL_OPTIONS;
 #endif
@@ -21139,6 +21142,9 @@ arm_compute_save_core_reg_mask (void)
 
   save_reg_mask |= arm_compute_save_reg0_reg12_mask ();
 
+  if (arm_current_function_pac_enabled_p ())
+save_reg_mask |= 1 << IP_REGNUM;
+
   /* Decide if we need to save the link register.
  Interrupt routines have their own banked link register,
  so they never need to save it.
@@ -23362,6 +23368,12 @@ output_probe_stack_range (rtx reg1, rtx reg2)
   return "";
 }
 
+static bool
+aarch_bti_enabled ()
+{
+  return false;
+}
+
 /* Generate the prologue instructions for entry into an ARM or Thumb-2
function.  */
 void
@@ -23440,12 +23452,13 @@ arm_expand_prologue (void)
 
   /* The static chain register is the same as the IP register.  If it is
  clobbered when creating the frame, we need to save and restore it.  */
-  clobber_ip = IS_NESTED (func_type)
-  && ((TARGET_APCS_FRAME && frame_pointer_needed && TARGET_ARM)
-  || ((flag_stack_check == STATIC_BUILTIN_STACK_CHECK
-   || flag_stack_

[PATCH 11/15] aarch64: Make bti pass generic so it can be used by the arm backend

[Andrea Corallo via Gcc-patches]

Hi all,

this patch splits and restructures the aarch64 bti pass code in order
to have it usable by the arm backend as well.  These changes have no
functional impact.

The original patch was approved here:
.

After that Richard E. noted that was better to move the new pass
definition for arm in the following patch and so I did.

Best Regards

  Andrea

gcc/Changelog

* config.gcc (aarch64*-*-*): Rename 'aarch64-bti-insert.o' into
'aarch-bti-insert.o'.
* config/aarch64/aarch64-protos.h: Remove 'aarch64_bti_enabled'
proto.
* config/aarch64/aarch64.cc (aarch_bti_enabled): Rename.
(aarch_bti_j_insn_p, aarch_pac_insn_p): New functions.
(aarch64_output_mi_thunk)
(aarch64_print_patchable_function_entry)
(aarch64_file_end_indicate_exec_stack): Update renamed function
calls to renamed functions.
* config/aarch64/t-aarch64 (aarch-bti-insert.o): Update target.
* config/arm/aarch-bti-insert.cc: New file including and
generalizing code from aarch64-bti-insert.cc.
* config/arm/aarch-common-protos.h: Update.

diff --git a/gcc/config.gcc b/gcc/config.gcc
index 7b58e1314ff..2021bdf9d2f 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -329,7 +329,7 @@ aarch64*-*-*)
c_target_objs="aarch64-c.o"
cxx_target_objs="aarch64-c.o"
d_target_objs="aarch64-d.o"
-   extra_objs="aarch64-builtins.o aarch-common.o aarch64-sve-builtins.o 
aarch64-sve-builtins-shapes.o aarch64-sve-builtins-base.o 
aarch64-sve-builtins-sve2.o cortex-a57-fma-steering.o aarch64-speculation.o 
falkor-tag-collision-avoidance.o aarch64-bti-insert.o aarch64-cc-fusion.o"
+   extra_objs="aarch64-builtins.o aarch-common.o aarch64-sve-builtins.o 
aarch64-sve-builtins-shapes.o aarch64-sve-builtins-base.o 
aarch64-sve-builtins-sve2.o cortex-a57-fma-steering.o aarch64-speculation.o 
falkor-tag-collision-avoidance.o aarch-bti-insert.o aarch64-cc-fusion.o"
target_gtfiles="\$(srcdir)/config/aarch64/aarch64-builtins.cc 
\$(srcdir)/config/aarch64/aarch64-sve-builtins.h 
\$(srcdir)/config/aarch64/aarch64-sve-builtins.cc"
target_has_targetm_common=yes
;;
diff --git a/gcc/config/aarch64/aarch64-c.cc b/gcc/config/aarch64/aarch64-c.cc
index b0c5a4fd6b6..a9aad3abdc2 100644
--- a/gcc/config/aarch64/aarch64-c.cc
+++ b/gcc/config/aarch64/aarch64-c.cc
@@ -179,7 +179,7 @@ aarch64_update_cpp_builtins (cpp_reader *pfile)
   aarch64_def_or_undef (TARGET_RNG, "__ARM_FEATURE_RNG", pfile);
   aarch64_def_or_undef (TARGET_MEMTAG, "__ARM_FEATURE_MEMORY_TAGGING", pfile);
 
-  aarch64_def_or_undef (aarch64_bti_enabled (),
+  aarch64_def_or_undef (aarch_bti_enabled (),
"__ARM_FEATURE_BTI_DEFAULT", pfile);
 
   cpp_undef (pfile, "__ARM_FEATURE_PAC_DEFAULT");
diff --git a/gcc/config/aarch64/aarch64-protos.h 
b/gcc/config/aarch64/aarch64-protos.h
index fe2180e95ea..9fdf7f9cc9c 100644
--- a/gcc/config/aarch64/aarch64-protos.h
+++ b/gcc/config/aarch64/aarch64-protos.h
@@ -891,7 +891,6 @@ void aarch64_register_pragmas (void);
 void aarch64_relayout_simd_types (void);
 void aarch64_reset_previous_fndecl (void);
 bool aarch64_return_address_signing_enabled (void);
-bool aarch64_bti_enabled (void);
 void aarch64_save_restore_target_globals (tree);
 void aarch64_addti_scratch_regs (rtx, rtx, rtx *,
 rtx *, rtx *,
diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc
index eec743024c1..2f67f3872f6 100644
--- a/gcc/config/aarch64/aarch64.cc
+++ b/gcc/config/aarch64/aarch64.cc
@@ -8534,11 +8534,61 @@ aarch64_return_address_signing_enabled (void)
 
 /* Return TRUE if Branch Target Identification Mechanism is enabled.  */
 bool
-aarch64_bti_enabled (void)
+aarch_bti_enabled (void)
 {
   return (aarch_enable_bti == 1);
 }
 
+/* Check if INSN is a BTI J insn.  */
+bool
+aarch_bti_j_insn_p (rtx_insn *insn)
+{
+  if (!insn || !INSN_P (insn))
+return false;
+
+  rtx pat = PATTERN (insn);
+  return GET_CODE (pat) == UNSPEC_VOLATILE && XINT (pat, 1) == UNSPECV_BTI_J;
+}
+
+/* Check if X (or any sub-rtx of X) is a PACIASP/PACIBSP instruction.  */
+bool
+aarch_pac_insn_p (rtx x)
+{
+  if (!INSN_P (x))
+return false;
+
+  subrtx_var_iterator::array_type array;
+  FOR_EACH_SUBRTX_VAR (iter, array, PATTERN (x), ALL)
+{
+  rtx sub = *iter;
+  if (sub && GET_CODE (sub) == UNSPEC)
+   {
+ int unspec_val = XINT (sub, 1);
+ switch (unspec_val)
+   {
+   case UNSPEC_PACIASP:
+case UNSPEC_PACIBSP:
+ return true;
+
+   default:
+ return false;
+   }
+ iter.skip_subrtxes ();
+   }
+}
+  return false;
+}
+
+rtx aarch_gen_bti_c (void)
+{
+  return gen_bti_c ();
+}
+
+rtx aarch_gen_bti_j (void)
+{
+  return gen_bti_j ();
+}
+
 /* The caller is going to use ST1D or LD1D to save or restore an SVE
register i

[PATCH 12/15] arm: implement bti injection

[Andrea Corallo via Gcc-patches]

Hi all,

this patch enables Branch Target Identification Armv8.1-M Mechanism
[1].

This is achieved by using the bti pass made common with Aarch64.

The pass iterates through the instructions and adds the necessary BTI
instructions at the beginning of every function and at every landing
pads targeted by indirect jumps.

Best Regards

  Andrea

[1]


gcc/ChangeLog

2022-04-07  Andrea Corallo  

* config.gcc (arm*-*-*): Add 'aarch-bti-insert.o' object.
* config/arm/arm-protos.h: Update.
* config/arm/arm.cc (aarch_bti_enabled, aarch_bti_j_insn_p)
(aarch_pac_insn_p, aarch_gen_bti_c, aarch_gen_bti_j): New
functions.
* config/arm/arm.md (bti_nop): New insn.
* config/arm/t-arm (PASSES_EXTRA): Add 'arm-passes.def'.
(aarch-bti-insert.o): New target.
* config/arm/unspecs.md (UNSPEC_BTI_NOP): New unspec.
* config/arm/aarch-bti-insert.cc (rest_of_insert_bti): Update
to verify arch compatibility.
* config/arm/arm-passes.def: New file.

gcc/testsuite/ChangeLog

2022-04-07  Andrea Corallo  

* gcc.target/arm/bti-1.c: New testcase.
* gcc.target/arm/bti-2.c: Likewise.

diff --git a/gcc/config.gcc b/gcc/config.gcc
index 2021bdf9d2f..004e1dfa8d8 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -353,7 +353,7 @@ arc*-*-*)
;;
 arm*-*-*)
cpu_type=arm
-   extra_objs="arm-builtins.o arm-mve-builtins.o aarch-common.o"
+   extra_objs="arm-builtins.o arm-mve-builtins.o aarch-common.o 
aarch-bti-insert.o"
extra_headers="mmintrin.h arm_neon.h arm_acle.h arm_fp16.h arm_cmse.h 
arm_bf16.h arm_mve_types.h arm_mve.h arm_cde.h"
target_type_format_char='%'
c_target_objs="arm-c.o"
diff --git a/gcc/config/arm/aarch-bti-insert.cc 
b/gcc/config/arm/aarch-bti-insert.cc
index 2d1d2e334a9..8f045c247bf 100644
--- a/gcc/config/arm/aarch-bti-insert.cc
+++ b/gcc/config/arm/aarch-bti-insert.cc
@@ -41,6 +41,7 @@
 #include "cfgrtl.h"
 #include "tree-pass.h"
 #include "cgraph.h"
+#include "diagnostic-core.h"
 
 /* This pass enables the support for Branch Target Identification Mechanism for
Arm/AArch64.  This is a security feature introduced in ARMv8.5-A
diff --git a/gcc/config/arm/arm-passes.def b/gcc/config/arm/arm-passes.def
new file mode 100644
index 000..71d6b563640
--- /dev/null
+++ b/gcc/config/arm/arm-passes.def
@@ -0,0 +1,21 @@
+/* Arm-specific passes declarations.
+   Copyright (C) 2022 Free Software Foundation, Inc.
+   Contributed by Arm Ltd.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3, or (at your option)
+   any later version.
+
+   GCC is distributed in the hope that it will be useful, but
+   WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+   General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with GCC; see the file COPYING3.  If not see
+   .  */
+
+INSERT_PASS_BEFORE (pass_shorten_branches, 1, pass_insert_bti);
diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h
index 84764bf27ce..6befb6c4445 100644
--- a/gcc/config/arm/arm-protos.h
+++ b/gcc/config/arm/arm-protos.h
@@ -24,6 +24,8 @@
 
 #include "sbitmap.h"
 
+rtl_opt_pass *make_pass_insert_bti (gcc::context *ctxt);
+
 extern enum unwind_info_type arm_except_unwind_info (struct gcc_options *);
 extern int use_return_insn (int, rtx);
 extern bool use_simple_return_p (void);
diff --git a/gcc/config/arm/arm.cc b/gcc/config/arm/arm.cc
index 31c6bcdea55..de5a679c92a 100644
--- a/gcc/config/arm/arm.cc
+++ b/gcc/config/arm/arm.cc
@@ -23368,12 +23368,6 @@ output_probe_stack_range (rtx reg1, rtx reg2)
   return "";
 }
 
-static bool
-aarch_bti_enabled ()
-{
-  return false;
-}
-
 /* Generate the prologue instructions for entry into an ARM or Thumb-2
function.  */
 void
@@ -32985,6 +32979,58 @@ arm_current_function_pac_enabled_p (void)
&& !crtl->is_leaf);
 }
 
+/* Return TRUE if Branch Target Identification Mechanism is enabled.  */
+bool
+aarch_bti_enabled (void)
+{
+  return aarch_enable_bti == 1;
+}
+
+/* Check if INSN is a BTI J insn.  */
+bool
+aarch_bti_j_insn_p (rtx_insn *insn)
+{
+  if (!insn || !INSN_P (insn))
+return false;
+
+  rtx pat = PATTERN (insn);
+  return GET_CODE (pat) == UNSPEC_VOLATILE && XINT (pat, 1) == UNSPEC_BTI_NOP;
+}
+
+/* Check if X (or any sub-rtx of X) is a PACIASP/PACIBSP instruction.  */
+bool
+aarch_pac_insn_p (rtx x)
+{
+  if (!x || !INSN_P (x))
+return false;
+
+  rtx pat = PATTERN (x);
+
+  if (GET_CODE (pat) == SET)
+{
+  rtx tmp

Re: [PATCH 0/15] arm: Enables return address verification and branch target identification on Cortex-M

[Andrea Corallo via Gcc-patches]

Andrea Corallo via Gcc-patches  writes:

> Hi all,
>
> as I respinned few patches, dropped one and added another, I'm reposting
> this series thant enables return address verification and branch target
> identification based on Armv8.1-M Pointer Authentication and Branch
> Target Identification Extension [1] for Arm Cortex-M.
>
> This feature is controlled by the newly introduced '-mbranch-protection'
> option, contextually the Armv8.1-M Mainline target feature '+pacbti' is
> added.
>
> Best Regards
>
>   Andrea
>
> [1]
> <https://community.arm.com/developer/ip-products/processors/b/processors-ip-blog/posts/armv8-1-m-pointer-authentication-and-branch-target-identification-extension>

Hi all,

FYI I've pushed these rebased on gcc-12 in 'endors/ARM/arm-12-m-pacbti'.

Best Regards

  Andrea

[PATCH] contrib: Fix a typo in contrib/git-fetch-vendor.sh

[Andrea Corallo via Gcc-patches]

Hi all,

just commited this to fix a typo as obvious.

Bests

  Andrea

/contrib/ChangeLog:

* git-fetch-vendor.sh : Fix typo.

diff --git a/contrib/git-fetch-vendor.sh b/contrib/git-fetch-vendor.sh
index 15303629b5c..bbd52fb2055 100755
--- a/contrib/git-fetch-vendor.sh
+++ b/contrib/git-fetch-vendor.sh
@@ -14,7 +14,7 @@ enable_push=no
 upstream=`git config --get "gcc-config.upstream"`
 if [ x"$upstream" = x ]
 then
-echo "Config gcc-config.upstream not set, run 
contrib/gcc-git-customization"
+echo "Config gcc-config.upstream not set, run 
contrib/gcc-git-customization.sh"
 exit 1
 fi
 

Re: [PATCH V2] arm: add -static-pie support

[Andrea Corallo via Gcc-patches]

Lance Fredrickson via Gcc-patches  writes:

> Yes, this is a 1st submission.
> Yes, I guess I was going for DCO rules.
> I will look at running the test suite. Does this need to be done on
> the target? because my arm target is a measly dual core 1ghz embedded
> chip and low ram. Netgear R7000 router actually.

Hi Lance,

you should be able to use qemu to run arm-linux-gnueabihf binaries and
as a consequance the testsuite if you prefer.

BR

  Andrea

Re: [PATCH 9/15] arm: Set again stack pointer as CFA reg when popping if necessary

[Andrea Corallo via Gcc-patches]

Andrea Corallo via Gcc-patches  writes:

> Hi all,
>
> this patch enables 'arm_emit_multi_reg_pop' to set again the stack
> pointer as CFA reg when popping if this is necessary.
>
> /gcc/
>
>   * config/arm/arm.cc (arm_emit_multi_reg_pop): If the frame pointer
>   was set define again the stack pointer as CFA reg when popping.

Ping

  Andrea

Re: [PATCH 7/15] arm: Emit build attributes for PACBTI target feature

[Andrea Corallo via Gcc-patches]

Andrea Corallo via Gcc-patches  writes:

> This patch emits assembler directives for PACBTI build attributes as
> defined by the
> ABI.
>
> <https://github.com/ARM-software/abi-aa/releases/download/2021Q1/addenda32.pdf>
>
> gcc/ChangeLog:
>
>   * config/arm/arm.c (arm_file_start): Emit EABI attributes for
>   Tag_PAC_extension, Tag_BTI_extension, TAG_BTI_use, TAG_PACRET_use.
>
> gcc/testsuite/ChangeLog:
>
>   * gcc.target/arm/acle/pacbti-m-predef-1.c: New test.
>   * gcc.target/arm/acle/pacbti-m-predef-3: Likewise.
>   * gcc.target/arm/acle/pacbti-m-predef-6.c: Likewise.
>   * gcc.target/arm/acle/pacbti-m-predef-7.c: Likewise.
>
> Co-Authored-By: Tejas Belagod  

Ping

  Andrea

Re: [PATCH 10/15] arm: Implement cortex-M return signing address codegen

[Andrea Corallo via Gcc-patches]

Ping

  Andrea

Re: [PATCH 11/15] aarch64: Make bti pass generic so it can be used by the arm backend

[Andrea Corallo via Gcc-patches]

Andrea Corallo via Gcc-patches  writes:

> Hi all,
>
> this patch splits and restructures the aarch64 bti pass code in order
> to have it usable by the arm backend as well.  These changes have no
> functional impact.
>
> The original patch was approved here:
> <https://gcc.gnu.org/pipermail/gcc-patches/2022-May/594172.html>.
>
> After that Richard E. noted that was better to move the new pass
> definition for arm in the following patch and so I did.

Ping

  Andrea

Re: [PATCH 12/15] arm: implement bti injection

[Andrea Corallo via Gcc-patches]

Andrea Corallo via Gcc-patches  writes:

> Hi all,
>
> this patch enables Branch Target Identification Armv8.1-M Mechanism
> [1].
>
> This is achieved by using the bti pass made common with Aarch64.
>
> The pass iterates through the instructions and adds the necessary BTI
> instructions at the beginning of every function and at every landing
> pads targeted by indirect jumps.
>
> Best Regards
>
>   Andrea
>
> [1]
> <https://community.arm.com/developer/ip-products/processors/b/processors-ip-blog/posts/armv8-1-m-pointer-authentication-and-branch-target-identification-extension>
>
> gcc/ChangeLog
>
> 2022-04-07  Andrea Corallo  
>
>   * config.gcc (arm*-*-*): Add 'aarch-bti-insert.o' object.
>   * config/arm/arm-protos.h: Update.
>   * config/arm/arm.cc (aarch_bti_enabled, aarch_bti_j_insn_p)
>   (aarch_pac_insn_p, aarch_gen_bti_c, aarch_gen_bti_j): New
>   functions.
>   * config/arm/arm.md (bti_nop): New insn.
>   * config/arm/t-arm (PASSES_EXTRA): Add 'arm-passes.def'.
>   (aarch-bti-insert.o): New target.
>   * config/arm/unspecs.md (UNSPEC_BTI_NOP): New unspec.
>   * config/arm/aarch-bti-insert.cc (rest_of_insert_bti): Update
>   to verify arch compatibility.
>   * config/arm/arm-passes.def: New file.
>
> gcc/testsuite/ChangeLog
>
> 2022-04-07  Andrea Corallo  
>
>   * gcc.target/arm/bti-1.c: New testcase.
>   * gcc.target/arm/bti-2.c: Likewise.

Ping

  Andrea

[PATCH 0/12] arm: Enables return address verification and branch target identification on Cortex-M

[Andrea Corallo via Gcc-patches]

Hi all,

this series enables return address verification and branch target
identification based on Armv8.1-M Pointer Authentication and Branch
Target Identification Extension [1] for Arm Cortex-M.

This feature is controlled by the newly introduced '-mbranch-protection'
option, contextually the Armv8.1-M Mainline target feature '+pacbti' is
added.

Best Regards

  Andrea

[1] 

[PATCH 1/12] arm: Make mbranch-protection opts parsing common to AArch32/64

[Andrea Corallo via Gcc-patches]

Hi all,

This change refactors all the mbranch-protection option parsing code and
types to make it common to both AArch32 and AArch64 backends.

This change also pulls in some supporting types from AArch64 to make
it common (aarch_parse_opt_result).

The significant changes in this patch are the movement of all branch
protection parsing routines from aarch64.c to aarch-common.c and
supporting data types and static data structures.

This patch also pre-declares variables and types required in the
aarch32 back-end for moved variables for function sign scope and key
to prepare for the impending series of patches that support parsing
the feature mbranch-protection in the aarch32 back-end.

This patch implements the changes requested and was pre-approved here
.

gcc/ChangeLog:

* common/config/aarch64/aarch64-common.cc: Include aarch-common.h.
(all_architectures): Fix comment.
(aarch64_parse_extension): Rename return type, enum value names.
* config/aarch64/aarch64-c.cc (aarch64_update_cpp_builtins): Rename
factored out aarch_ra_sign_scope and aarch_ra_sign_key variables.
Also rename corresponding enum values.
* config/aarch64/aarch64-opts.h (aarch64_function_type): Factor
out aarch64_function_type and move it to common code as
aarch_function_type in aarch-common.h.
* config/aarch64/aarch64-protos.h: Include common types header,
move out types aarch64_parse_opt_result and aarch64_key_type to
aarch-common.h
* config/aarch64/aarch64.cc: Move mbranch-protection parsing types
and functions out into aarch-common.h and aarch-common.cc.  Fix up
all the name changes resulting from the move.
* config/aarch64/aarch64.md: Fix up aarch64_ra_sign_key type name change
and enum value.
* config/aarch64/aarch64.opt: Include aarch-common.h to import
type move.  Fix up name changes from factoring out common code and
data.
* config/arm/aarch-common-protos.h: Export factored out routines to both
backends.
* config/arm/aarch-common.cc: Include newly factored out types.  Move 
all
mbranch-protection code and data structures from aarch64.cc.
* config/arm/aarch-common.h: New header that declares types shared
between aarch32 and aarch64 backends.
* config/arm/arm-protos.h: Declare types and variables that are
made common to aarch64 and aarch32 backends - aarch_ra_sign_key,
aarch_ra_sign_scope and aarch_enable_bti.

Co-Authored-By: Tejas Belagod  

diff --git a/gcc/common/config/aarch64/aarch64-common.cc 
b/gcc/common/config/aarch64/aarch64-common.cc
index dfda5b8372a..70a5cf98b75 100644
--- a/gcc/common/config/aarch64/aarch64-common.cc
+++ b/gcc/common/config/aarch64/aarch64-common.cc
@@ -30,6 +30,7 @@
 #include "opts.h"
 #include "flags.h"
 #include "diagnostic.h"
+#include "config/arm/aarch-common.h"
 
 #ifdef  TARGET_BIG_ENDIAN_DEFAULT
 #undef  TARGET_DEFAULT_TARGET_FLAGS
@@ -192,11 +193,11 @@ static const struct arch_to_arch_name all_architectures[] 
=
 
 /* Parse the architecture extension string STR and update ISA_FLAGS
with the architecture features turned on or off.  Return a
-   aarch64_parse_opt_result describing the result.
+   aarch_parse_opt_result describing the result.
When the STR string contains an invalid extension,
a copy of the string is created and stored to INVALID_EXTENSION.  */
 
-enum aarch64_parse_opt_result
+enum aarch_parse_opt_result
 aarch64_parse_extension (const char *str, uint64_t *isa_flags,
 std::string *invalid_extension)
 {
@@ -229,7 +230,7 @@ aarch64_parse_extension (const char *str, uint64_t 
*isa_flags,
adding_ext = 1;
 
   if (len == 0)
-   return AARCH64_PARSE_MISSING_ARG;
+   return AARCH_PARSE_MISSING_ARG;
 
 
   /* Scan over the extensions table trying to find an exact match.  */
@@ -251,13 +252,13 @@ aarch64_parse_extension (const char *str, uint64_t 
*isa_flags,
  /* Extension not found in list.  */
  if (invalid_extension)
*invalid_extension = std::string (str, len);
- return AARCH64_PARSE_INVALID_FEATURE;
+ return AARCH_PARSE_INVALID_FEATURE;
}
 
   str = ext;
 };
 
-  return AARCH64_PARSE_OK;
+  return AARCH_PARSE_OK;
 }
 
 /* Append all architecture extension candidates to the CANDIDATES vector.  */
diff --git a/gcc/config/aarch64/aarch64-c.cc b/gcc/config/aarch64/aarch64-c.cc
index caf8e332ea0..b0c5a4fd6b6 100644
--- a/gcc/config/aarch64/aarch64-c.cc
+++ b/gcc/config/aarch64/aarch64-c.cc
@@ -183,14 +183,14 @@ aarch64_update_cpp_builtins (cpp_reader *pfile)
"__ARM_FEATURE_BTI_DEFAULT", pfile);
 
   cpp_undef (pfile, "__ARM_FEATURE_PAC_DEFAULT");
-  if (aarch64_ra_sign_scope != AARCH64_FUNCTION_NONE)
+  if (aarch_ra_sign_scope != AARCH_FUNCTION_NONE)

[PATCH 2/12] arm: Add Armv8.1-M Mainline target feature +pacbti

[Andrea Corallo via Gcc-patches]

This patch adds the -march feature +pacbti to Armv8.1-M Mainline.

This feature enables pointer signing and authentication instructions
on M-class architectures.

Pre-approved here
.

gcc/Changelog:

* config/arm/arm.h (TARGET_HAVE_PACBTI): New macro.
* config/arm/arm-cpus.in (pacbti): New feature.
* doc/invoke.texi (Arm Options): Document it.

Co-Authored-By: Tejas Belagod  

diff --git a/gcc/config/arm/arm-cpus.in b/gcc/config/arm/arm-cpus.in
index 0d3082b569f..6c1dffe56e3 100644
--- a/gcc/config/arm/arm-cpus.in
+++ b/gcc/config/arm/arm-cpus.in
@@ -229,6 +229,10 @@ define feature cdecp5
 define feature cdecp6
 define feature cdecp7
 
+# M-profile control flow integrity extensions (PAC/AUT/BTI).
+# Optional from Armv8.1-M Mainline.
+define feature pacbti
+
 # Feature groups.  Conventionally all (or mostly) upper case.
 # ALL_FPU lists all the feature bits associated with the floating-point
 # unit; these will all be removed if the floating-point unit is disabled
@@ -748,6 +752,7 @@ begin arch armv8.1-m.main
  option nofp remove ALL_FP
  option mve add MVE
  option mve.fp add MVE_FP
+ option pacbti add pacbti
  option cdecp0 add cdecp0
  option cdecp1 add cdecp1
  option cdecp2 add cdecp2
diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
index f479540812a..3495ab857ea 100644
--- a/gcc/config/arm/arm.h
+++ b/gcc/config/arm/arm.h
@@ -335,6 +335,12 @@ emission of floating point pcs attributes.  */
isa_bit_mve_float) \
   && !TARGET_GENERAL_REGS_ONLY)
 
+/* Non-zero if this target supports Armv8.1-M Mainline pointer-signing
+   extension.  */
+#define TARGET_HAVE_PACBTI (arm_arch8_1m_main \
+   && bitmap_bit_p (arm_active_target.isa, \
+isa_bit_pacbti))
+
 /* MVE have few common instructions as VFP, like VLDM alias VPOP, VLDR, VSTM
alia VPUSH, VSTR and VMOV, VMSR and VMRS.  In the same manner it updates few
registers such as FPCAR, FPCCR, FPDSCR, FPSCR, MVFR0, MVFR1 and MVFR2.  All
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 3936aef69d0..079e34ed98c 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -21002,6 +21002,9 @@ Disable the floating-point extension.
 @item +cdecp0, +cdecp1, ... , +cdecp7
 Enable the Custom Datapath Extension (CDE) on selected coprocessors according
 to the numbers given in the options in the range 0 to 7.
+
+@item +pacbti
+Enable the Pointer Authentication and Branch Target Identification Extension.
 @end table
 
 @item  armv8-m.main

[PATCH 3/12] arm: Add option -mbranch-protection

[Andrea Corallo via Gcc-patches]

[PATCH 3/12] arm: Add option -mbranch-protection

Add -mbranch-protection option.  This option enables the
code-generation of pointer signing and authentication instructions in
function prologues and epilogues.

gcc/ChangeLog:

* config/arm/arm.c (arm_configure_build_target): Parse and validate
-mbranch-protection option and initialize appropriate data structures.
* config/arm/arm.opt (-mbranch-protection): New option.
* doc/invoke.texi (Arm Options): Document it.

Co-Authored-By: Tejas Belagod  
Co-Authored-By: Richard Earnshaw 

diff --git a/gcc/config/arm/arm.cc b/gcc/config/arm/arm.cc
index 60f3eae82a4..0068817b0f2 100644
--- a/gcc/config/arm/arm.cc
+++ b/gcc/config/arm/arm.cc
@@ -3263,6 +3263,17 @@ arm_configure_build_target (struct arm_build_target 
*target,
   tune_opts = strchr (opts->x_arm_tune_string, '+');
 }
 
+  if (opts->x_arm_branch_protection_string)
+{
+  aarch_validate_mbranch_protection (opts->x_arm_branch_protection_string);
+
+  if (aarch_ra_sign_key != AARCH_KEY_A)
+   {
+ warning (0, "invalid key type for %<-mbranch-protection=%>");
+ aarch_ra_sign_key = AARCH_KEY_A;
+   }
+}
+
   if (arm_selected_arch)
 {
   arm_initialize_isa (target->isa, arm_selected_arch->common.isa_bits);
diff --git a/gcc/config/arm/arm.opt b/gcc/config/arm/arm.opt
index f54ec8356c3..d292e23ea11 100644
--- a/gcc/config/arm/arm.opt
+++ b/gcc/config/arm/arm.opt
@@ -323,6 +323,10 @@ mbranch-cost=
 Target RejectNegative Joined UInteger Var(arm_branch_cost) Init(-1)
 Cost to assume for a branch insn.
 
+mbranch-protection=
+Target RejectNegative Joined Var(arm_branch_protection_string) Save
+Use branch-protection features.
+
 mgeneral-regs-only
 Target RejectNegative Mask(GENERAL_REGS_ONLY) Save
 Generate code which uses the core registers only (r0-r14).
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 079e34ed98c..f6f724af26e 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -825,7 +825,9 @@ Objective-C and Objective-C++ Dialects}.
 -mcmse @gol
 -mfix-cmse-cve-2021-35465 @gol
 -mstack-protector-guard=@var{guard} 
-mstack-protector-guard-offset=@var{offset} @gol
--mfdpic}
+-mfdpic @gol
+-mbranch-protection=@var{none}|@var{standard}|@var{pac-ret}[+@var{leaf}]
+[+@var{bti}]|@var{bti}[+@var{pac-ret}[+@var{leaf}]]}
 
 @emph{AVR Options}
 @gccoptlist{-mmcu=@var{mcu}  -mabsdata  -maccumulate-args @gol
@@ -21521,6 +21523,37 @@ The opposite @option{-mno-fdpic} option is useful (and 
required) to
 build the Linux kernel using the same (@code{arm-*-uclinuxfdpiceabi})
 toolchain as the one used to build the userland programs.
 
+@item
+-mbranch-protection=@var{none}|@var{standard}|@var{pac-ret}[+@var{leaf}][+@var{bti}]|@var{bti}[+@var{pac-ret}[+@var{leaf}]]
+@opindex mbranch-protection
+Enable branch protection features (armv8.1-m.main only).
+@samp{none} generate code without branch protection or return address
+signing.
+@samp{standard[+@var{leaf}]} generate code with all branch protection
+features enabled at their standard level.
+@samp{pac-ret[+@var{leaf}]} generate code with return address signing
+set to its standard level, which is to sign all functions that save
+the return address to memory.
+@samp{leaf} When return address signing is enabled, also sign leaf
+functions even if they do not write the return address to memory.
++@samp{bti} Add landing-pad instructions at the permitted targets of
+indirect branch instructions.
+
+If the @samp{+pacbti} architecture extension is not enabled, then all
+branch protection and return address signing operations are
+constrained to use only the instructions defined in the
+architectural-NOP space. The generated code will remain
+backwards-compatible with earlier versions of the architecture, but
+the additional security can be enabled at run time on processors that
+support the @samp{PACBTI} extension.
+
+Branch target enforcement using BTI can only be enabled at runtime if
+all code in the application has been compiled with at least
+@samp{-mbranch-protection=bti}.
+
+The default is to generate code without branch protection or return
+address signing.
+
 @end table
 
 @node AVR Options

[PATCH 4/12] arm: Add testsuite library support for PACBTI target

[Andrea Corallo via Gcc-patches]

Add targeting-checking entities for PACBTI in testsuite
framework.

Pre-approved with the requested changes here
.

gcc/testsuite/ChangeLog:

* testsuite/lib/target-supports.exp:
(check_effective_target_arm_pacbti_hw): New.
* doc/sourcebuild.texi: Document arm_pacbti_hw.

Co-Authored-By: Tejas Belagod  

diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi
index 613ac29967b..e8cbd8e4aef 100644
--- a/gcc/doc/sourcebuild.texi
+++ b/gcc/doc/sourcebuild.texi
@@ -2167,6 +2167,10 @@ ARM target supports options to generate instructions 
from ARMv8.1-M with
 the Custom Datapath Extension (CDE) and M-Profile Vector Extension (MVE).
 Some multilibs may be incompatible with these options.
 
+@item arm_pacbti_hw
+Test system supports executing Pointer Authentication and Branch Target
+Identification instructions.
+
 @item arm_prefer_ldrd_strd
 ARM target prefers @code{LDRD} and @code{STRD} instructions over
 @code{LDM} and @code{STM} instructions.
diff --git a/gcc/testsuite/lib/target-supports.exp 
b/gcc/testsuite/lib/target-supports.exp
index ff8edbd3e17..df8ab037fb3 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -5090,6 +5090,22 @@ proc check_effective_target_arm_cmse_clear_ok {} {
 } "-mcmse"];
 }
 
+# Return 1 if the target supports executing PACBTI instructions, 0
+# otherwise.
+
+proc check_effective_target_arm_pacbti_hw {} {
+return [check_runtime arm_pacbti_hw_available {
+   __attribute__ ((naked)) int
+   main (void)
+   {
+ asm ("pac r12, lr, sp");
+ asm ("mov r0, #0");
+ asm ("autg r12, lr, sp");
+ asm ("bx lr");
+   }
+} ""]
+}
+
 # Return 1 if this compilation turns on string_ops_prefer_neon on.
 
 proc check_effective_target_arm_tune_string_ops_prefer_neon { } {

[PATCH 5/12] arm: Implement target feature macros for PACBTI

[Andrea Corallo via Gcc-patches]

This patch implements target feature macros when PACBTI is enabled
through the -march option or -mbranch-protection.  The target feature
macros __ARM_FEATURE_PAC_DEFAULT and __ARM_FEATURE_BTI_DEFAULT are
specified in ARM ACLE

__ARM_FEATURE_PAUTH and __ARM_FEATURE_BTI are specified in the
pull-request .

Approved here
.

gcc/ChangeLog:

* config/arm/arm-c.c (arm_cpu_builtins): Define
__ARM_FEATURE_BTI_DEFAULT, __ARM_FEATURE_PAC_DEFAULT,
__ARM_FEATURE_PAUTH and __ARM_FEATURE_BTI.

gcc/testsuite/ChangeLog:

* gcc.target/arm/acle/pacbti-m-predef-2.c: New test.
* gcc.target/arm/acle/pacbti-m-predef-4.c: New test.
* gcc.target/arm/acle/pacbti-m-predef-5.c: New test.

Co-Authored-By: Tejas Belagod  

diff --git a/gcc/config/arm/arm-c.cc b/gcc/config/arm/arm-c.cc
index a8697b8c62f..190099b2c37 100644
--- a/gcc/config/arm/arm-c.cc
+++ b/gcc/config/arm/arm-c.cc
@@ -212,6 +212,24 @@ arm_cpu_builtins (struct cpp_reader* pfile)
   def_or_undef_macro (pfile, "__ARM_FEATURE_COMPLEX", TARGET_COMPLEX);
   def_or_undef_macro (pfile, "__ARM_32BIT_STATE", TARGET_32BIT);
 
+  def_or_undef_macro (pfile, "__ARM_FEATURE_PAUTH", TARGET_HAVE_PACBTI);
+  def_or_undef_macro (pfile, "__ARM_FEATURE_BTI", TARGET_HAVE_PACBTI);
+  def_or_undef_macro (pfile, "__ARM_FEATURE_BTI_DEFAULT",
+ aarch_enable_bti == 1);
+
+  cpp_undef (pfile, "__ARM_FEATURE_PAC_DEFAULT");
+  if (aarch_ra_sign_scope != AARCH_FUNCTION_NONE)
+  {
+unsigned int pac = 1;
+
+gcc_assert (aarch_ra_sign_key == AARCH_KEY_A);
+
+if (aarch_ra_sign_scope == AARCH_FUNCTION_ALL)
+  pac |= 0x4;
+
+builtin_define_with_int_value ("__ARM_FEATURE_PAC_DEFAULT", pac);
+  }
+
   cpp_undef (pfile, "__ARM_FEATURE_MVE");
   if (TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT)
 {
diff --git a/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-2.c 
b/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-2.c
new file mode 100644
index 000..4394fd147d7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-2.c
@@ -0,0 +1,24 @@
+
+/* { dg-do run } */
+/* { dg-require-effective-target arm_pacbti_hw } */
+/* { dg-additional-options " -mbranch-protection=bti+pac-ret+leaf" } */
+
+#if !defined (__ARM_FEATURE_BTI_DEFAULT)
+#error "Feature test macro __ARM_FEATURE_BTI_DEFAULT should be defined."
+#endif
+
+#if !defined (__ARM_FEATURE_PAC_DEFAULT)
+#error "Feature test macro __ARM_FEATURE_PAC_DEFAULT should be defined."
+#endif
+
+int
+main()
+{
+  if (__ARM_FEATURE_BTI_DEFAULT != 1)
+__builtin_abort ();
+
+  if (__ARM_FEATURE_PAC_DEFAULT != 5)
+__builtin_abort ();
+
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-4.c 
b/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-4.c
new file mode 100644
index 000..90f0c724b9e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-4.c
@@ -0,0 +1,21 @@
+
+/* { dg-do run } */
+/* { dg-require-effective-target arm_pacbti_hw } */
+/* { dg-additional-options " -mbranch-protection=pac-ret" } */
+
+#if !defined (__ARM_FEATURE_PAC_DEFAULT)
+#error "Feature test macro __ARM_FEATURE_BTI_DEFAULT should be defined."
+#endif
+
+#if defined (__ARM_FEATURE_BTI_DEFAULT)
+#error "Feature test macro __ARM_FEATURE_BTI_DEFAULT should be undefined."
+#endif
+
+int
+main()
+{
+  if (__ARM_FEATURE_PAC_DEFAULT != 1)
+__builtin_abort ();
+
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-5.c 
b/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-5.c
new file mode 100644
index 000..c865809b8b0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-5.c
@@ -0,0 +1,24 @@
+
+/* { dg-do run } */
+/* { dg-require-effective-target arm_pacbti_hw } */
+/* { dg-additional-options " -mbranch-protection=bti+pac-ret" } */
+
+#if !defined (__ARM_FEATURE_BTI_DEFAULT)
+#error "Feature test macro __ARM_FEATURE_BTI_DEFAULT should be defined."
+#endif
+
+#if !defined (__ARM_FEATURE_PAC_DEFAULT)
+#error "Feature test macro __ARM_FEATURE_PAC_DEFAULT should be defined."
+#endif
+
+int
+main()
+{
+  if (__ARM_FEATURE_BTI_DEFAULT != 1)
+__builtin_abort ();
+
+  if (__ARM_FEATURE_PAC_DEFAULT != 1)
+__builtin_abort ();
+
+  return 0;
+}

[PATCH 6/12] arm: Add pointer authentication for stack-unwinding runtime

[Andrea Corallo via Gcc-patches]

This patch adds authentication for when the stack is unwound when an
exception is taken.  All the changes here are done to the runtime code
in libgcc's unwinder code for Arm target. All the changes are guarded
under defined (__ARM_FEATURE_PAC_DEFAULT) and activated only if the
+pacbti feature is switched on for the architecture. This means that
switching on the target feature via -march or -mcpu is sufficient and
-mbranch-protection need not be enabled. This ensures that the
unwinder is authenticated only if the PACBTI instructions are
available in the non-NOP space as it uses AUTG.  Just generating
PAC/AUT instructions using -mbranch-protection will not enable
authentication on the unwinder.

Pre-approved with the requested changes here
.

gcc/ChangeLog:

* ginclude/unwind-arm-common.h (_Unwind_VRS_RegClass): Introduce
new pseudo register class _UVRSC_PAC.
* libgcc/config/arm/pr-support.c (__gnu_unwind_execute): Decode
exception opcode (0xb4) for saving RA_AUTH_CODE and authenticate
with AUTG if found.
* libgcc/config/arm/unwind-arm.c (struct pseudo_regs): New.
(phase1_vrs): Introduce new field to store pseudo-reg state.
(phase2_vrs): Likewise.
(_Unwind_VRS_Get): Load pseudo register state from virtual reg set.
(_Unwind_VRS_Set): Store pseudo register state to virtual reg set.
(_Unwind_VRS_Pop): Load pseudo register value from stack into VRS.

Co-Authored-By: Tejas Belagod  

diff --git a/gcc/ginclude/unwind-arm-common.h b/gcc/ginclude/unwind-arm-common.h
index d3831f6c60a..f26702e8c6c 100644
--- a/gcc/ginclude/unwind-arm-common.h
+++ b/gcc/ginclude/unwind-arm-common.h
@@ -127,7 +127,8 @@ extern "C" {
   _UVRSC_VFP = 1,   /* vfp */
   _UVRSC_FPA = 2,   /* fpa */
   _UVRSC_WMMXD = 3, /* Intel WMMX data register */
-  _UVRSC_WMMXC = 4  /* Intel WMMX control register */
+  _UVRSC_WMMXC = 4, /* Intel WMMX control register */
+  _UVRSC_PAC = 5/* Armv8.1-M Mainline PAC/AUTH pseudo-register */
 }
   _Unwind_VRS_RegClass;
 
diff --git a/libgcc/config/arm/pr-support.c b/libgcc/config/arm/pr-support.c
index 2de96c2a447..e48854587c6 100644
--- a/libgcc/config/arm/pr-support.c
+++ b/libgcc/config/arm/pr-support.c
@@ -106,6 +106,7 @@ __gnu_unwind_execute (_Unwind_Context * context, 
__gnu_unwind_state * uws)
 {
   _uw op;
   int set_pc;
+  int set_pac = 0;
   _uw reg;
 
   set_pc = 0;
@@ -114,6 +115,27 @@ __gnu_unwind_execute (_Unwind_Context * context, 
__gnu_unwind_state * uws)
   op = next_unwind_byte (uws);
   if (op == CODE_FINISH)
{
+ /* When we reach end, we have to authenticate R12 we just popped
+earlier.
+
+Note: while the check provides additional security against a
+corrupted unwind chain, it isn't essential for correct unwinding
+of an uncorrupted chain.  */
+#if defined(TARGET_HAVE_PACBTI)
+ if (set_pac)
+   {
+ _uw sp;
+ _uw lr;
+ _uw pac;
+ _Unwind_VRS_Get (context, _UVRSC_CORE, R_SP, _UVRSD_UINT32, &sp);
+ _Unwind_VRS_Get (context, _UVRSC_CORE, R_LR, _UVRSD_UINT32, &lr);
+ _Unwind_VRS_Get (context, _UVRSC_PAC, R_IP,
+  _UVRSD_UINT32, &pac);
+ __asm__ __volatile__
+   ("autg %0, %1, %2" : : "r"(pac), "r"(lr), "r"(sp) :);
+   }
+#endif
+
  /* If we haven't already set pc then copy it from lr.  */
  if (!set_pc)
{
@@ -227,6 +249,16 @@ __gnu_unwind_execute (_Unwind_Context * context, 
__gnu_unwind_state * uws)
return _URC_FAILURE;
  continue;
}
+ /* Pop PAC off the stack into VRS pseudo.pac.  */
+ if (op == 0xb4)
+   {
+ if (_Unwind_VRS_Pop (context, _UVRSC_PAC, 0, _UVRSD_UINT32)
+ != _UVRSR_OK)
+   return _URC_FAILURE;
+ set_pac = 1;
+ continue;
+   }
+
  if ((op & 0xfc) == 0xb4)  /* Obsolete FPA.  */
return _URC_FAILURE;
 
diff --git a/libgcc/config/arm/unwind-arm.c b/libgcc/config/arm/unwind-arm.c
index 386406564af..89f945d047e 100644
--- a/libgcc/config/arm/unwind-arm.c
+++ b/libgcc/config/arm/unwind-arm.c
@@ -64,6 +64,12 @@ struct wmmxc_regs
   _uw wc[4];
 };
 
+/*  Holds value of pseudo registers eg. PAC.  */
+struct pseudo_regs
+{
+  _uw pac;
+};
+
 /* The ABI specifies that the unwind routines may only use core registers,
except when actually manipulating coprocessor state.  This allows
us to write one implementation that works on all platforms by
@@ -78,6 +84,9 @@ typedef struct
   /* The first fields must be the same as a phase2_vrs.  */
   _uw demand_save_flags;
   struct core_regs core;
+  /* Armv8.1-M Mainline PAC/AUTH values.  This field should be in the same 
field
+ order 

[PATCH 7/12] arm: Emit build attributes for PACBTI target feature

[Andrea Corallo via Gcc-patches]

This patch emits assembler directives for PACBTI build attributes as
defined by the
ABI.



gcc/ChangeLog:

* config/arm/arm.c (arm_file_start): Emit EABI attributes for
Tag_PAC_extension, Tag_BTI_extension, TAG_BTI_use, TAG_PACRET_use.

gcc/testsuite/ChangeLog:

* gcc.target/arm/acle/pacbti-m-predef-1.c: New test.
* gcc.target/arm/acle/pacbti-m-predef-3: Likewise.
* gcc.target/arm/acle/pacbti-m-predef-6.c: Likewise.
* gcc.target/arm/acle/pacbti-m-predef-7.c: Likewise.

Co-Authored-By: Tejas Belagod  

diff --git a/gcc/config/arm/arm.cc b/gcc/config/arm/arm.cc
index 0068817b0f2..ceec14f84b6 100644
--- a/gcc/config/arm/arm.cc
+++ b/gcc/config/arm/arm.cc
@@ -28349,6 +28349,8 @@ static void
 arm_file_start (void)
 {
   int val;
+  bool pac = (aarch_ra_sign_scope != AARCH_FUNCTION_NONE);
+  bool bti = (aarch_enable_bti == 1);
 
   arm_print_asm_arch_directives
 (asm_out_file, TREE_TARGET_OPTION (target_option_default_node));
@@ -28419,6 +28421,22 @@ arm_file_start (void)
arm_emit_eabi_attribute ("Tag_ABI_FP_16bit_format", 38,
 (int) arm_fp16_format);
 
+  if (TARGET_HAVE_PACBTI)
+   {
+ arm_emit_eabi_attribute ("Tag_PAC_extension", 50, 2);
+ arm_emit_eabi_attribute ("Tag_BTI_extension", 52, 2);
+   }
+  else if (pac || bti)
+   {
+ arm_emit_eabi_attribute ("Tag_PAC_extension", 50, 1);
+ arm_emit_eabi_attribute ("Tag_BTI_extension", 52, 1);
+   }
+
+  if (bti)
+arm_emit_eabi_attribute ("TAG_BTI_use", 74, 1);
+  if (pac)
+   arm_emit_eabi_attribute ("TAG_PACRET_use", 76, 1);
+
   if (arm_lang_output_object_attributes_hook)
arm_lang_output_object_attributes_hook();
 }
diff --git a/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-1.c 
b/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-1.c
new file mode 100644
index 000..75d3e00ef64
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-1.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-additional-options " -mbranch-protection=pac-ret+bti --save-temps" } */
+
+#if !defined (__ARM_FEATURE_BTI_DEFAULT)
+#error "Feature test macro __ARM_FEATURE_BTI_DEFAULT should be defined."
+#endif
+
+#if !defined (__ARM_FEATURE_PAC_DEFAULT)
+#error "Feature test macro __ARM_FEATURE_PAC_DEFAULT should be defined."
+#endif
+
+/* { dg-final { scan-assembler-not "\.arch_extension pacbti" } } */
+/* { dg-final { scan-assembler "\.eabi_attribute 50, 1" } } */
+/* { dg-final { scan-assembler "\.eabi_attribute 52, 1" } } */
+/* { dg-final { scan-assembler "\.eabi_attribute 74, 1" } } */
+/* { dg-final { scan-assembler "\.eabi_attribute 76, 1" } } */
diff --git a/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-3.c 
b/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-3.c
new file mode 100644
index 000..bf6c3ba90c9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-3.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-additional-options " -mbranch-protection=pac-ret+leaf --save-temps" } 
*/
+
+#if defined (__ARM_FEATURE_BTI_DEFAULT)
+#error "Feature test macro __ARM_FEATURE_BTI_DEFAULT should be undefined."
+#endif
+
+#if !defined (__ARM_FEATURE_PAC_DEFAULT)
+#error "Feature test macro __ARM_FEATURE_PAC_DEFAULT should be defined."
+#endif
+
+/* { dg-final { scan-assembler-not "\.arch_extension pacbti" } } */
+/* { dg-final { scan-assembler "\.eabi_attribute 50, 1" } } */
+/* { dg-final { scan-assembler "\.eabi_attribute 52, 1" } } */
+/* { dg-final { scan-assembler-not "\.eabi_attribute 74" } } */
+/* { dg-final { scan-assembler "\.eabi_attribute 76, 1" } } */
diff --git a/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-6.c 
b/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-6.c
new file mode 100644
index 000..82af11ee407
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-6.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-additional-options " -mbranch-protection=bti --save-temps" } */
+
+#if !defined (__ARM_FEATURE_BTI_DEFAULT)
+#error "Feature test macro __ARM_FEATURE_BTI_DEFAULT should be defined."
+#endif
+
+#if defined (__ARM_FEATURE_PAC_DEFAULT)
+#error "Feature test macro __ARM_FEATURE_PAC_DEFAULT should be undefined."
+#endif
+/* { dg-final { scan-assembler-not "\.arch_extension pacbti" } } */
+/* { dg-final { scan-assembler "\.eabi_attribute 50, 1" } } */
+/* { dg-final { scan-assembler "\.eabi_attribute 52, 1" } } */
+/* { dg-final { scan-assembler "\.eabi_attribute 74, 1" } } */
+/* { dg-final { scan-assembler-not "\.eabi_attribute 76" } } */
diff --git a/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-7.c 
b/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-7.c
new file mode 100644
index 000..48a40e64c11
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-7.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg

[PATCH 8/12] arm: Introduce multilibs for PACBTI target feature

[Andrea Corallo via Gcc-patches]

This patch add the following new multilibs.

thumb/v8.1-m.main+pacbti/mbranch-protection/nofp
thumb/v8.1-m.main+pacbti+dp/mbranch-protection/soft
thumb/v8.1-m.main+pacbti+dp/mbranch-protection/hard
thumb/v8.1-m.main+pacbti+fp/mbranch-protection/soft
thumb/v8.1-m.main+pacbti+fp/mbranch-protection/hard
thumb/v8.1-m.main+pacbti+mve/mbranch-protection/hard

Triggering the following compiler flags:

-mthumb -march=armv8.1-m.main+pacbti -mbranch-protection=standard 
-mfloat-abi=soft
-mthumb -march=armv8.1-m.main+pacbti+fp -mbranch-protection=standard 
-mfloat-abi=softfp
-mthumb -march=armv8.1-m.main+pacbti+fp -mbranch-protection=standard 
-mfloat-abi=hard
-mthumb -march=armv8.1-m.main+pacbti+fp.dp -mbranch-protection=standard 
-mfloat-abi=softfp
-mthumb -march=armv8.1-m.main+pacbti+fp.dp -mbranch-protection=standard 
-mfloat-abi=hard
-mthumb -march=armv8.1-m.main+pacbti+mve -mbranch-protection=standard 
-mfloat-abi=hard

gcc/ChangeLog:

* config/arm/t-rmprofile: Add multilib rules for +pacbti.

diff --git a/gcc/config/arm/t-rmprofile b/gcc/config/arm/t-rmprofile
index eb321e832f1..542ff874b2e 100644
--- a/gcc/config/arm/t-rmprofile
+++ b/gcc/config/arm/t-rmprofile
@@ -27,8 +27,11 @@
 
 # Arch and FPU variants to build libraries with
 
-MULTI_ARCH_OPTS_RM = 
march=armv6s-m/march=armv7-m/march=armv7e-m/march=armv7e-m+fp/march=armv7e-m+fp.dp/march=armv8-m.base/march=armv8-m.main/march=armv8-m.main+fp/march=armv8-m.main+fp.dp/march=armv8.1-m.main+mve
-MULTI_ARCH_DIRS_RM = v6-m v7-m v7e-m v7e-m+fp v7e-m+dp v8-m.base v8-m.main 
v8-m.main+fp v8-m.main+dp v8.1-m.main+mve
+MULTI_ARCH_OPTS_RM = 
march=armv6s-m/march=armv7-m/march=armv7e-m/march=armv7e-m+fp/march=armv7e-m+fp.dp/march=armv8-m.base/march=armv8-m.main/march=armv8-m.main+fp/march=armv8-m.main+fp.dp/march=armv8.1-m.main+mve/march=armv8.1-m.main+pacbti/march=armv8.1-m.main+pacbti+fp/march=armv8.1-m.main+pacbti+fp.dp/march=armv8.1-m.main+pacbti+mve
+MULTI_ARCH_DIRS_RM = v6-m v7-m v7e-m v7e-m+fp v7e-m+dp v8-m.base v8-m.main 
v8-m.main+fp v8-m.main+dp v8.1-m.main+mve v8.1-m.main+pacbti 
v8.1-m.main+pacbti+fp v8.1-m.main+pacbti+dp 8.1-m.main+pacbti+mve
+
+MULTI_ARCH_OPTS_RM += mbranch-protection=pac-ret+bti
+MULTI_ARCH_DIRS_RM += mbranch-protection
 
 # Base M-profile (no fp)
 MULTILIB_REQUIRED  += mthumb/march=armv6s-m/mfloat-abi=soft
@@ -50,6 +53,14 @@ MULTILIB_REQUIRED+= 
mthumb/march=armv8-m.main+fp.dp/mfloat-abi=hard
 MULTILIB_REQUIRED  += mthumb/march=armv8-m.main+fp.dp/mfloat-abi=softfp
 MULTILIB_REQUIRED  += mthumb/march=armv8.1-m.main+mve/mfloat-abi=hard
 
+MULTILIB_REQUIRED  += 
mthumb/march=armv8.1-m.main+pacbti/mbranch-protection=standard/mfloat-abi=soft
+MULTILIB_REQUIRED  += 
mthumb/march=armv8.1-m.main+pacbti+fp/mbranch-protection=standard/mfloat-abi=softfp
+MULTILIB_REQUIRED  += 
mthumb/march=armv8.1-m.main+pacbti+fp/mbranch-protection=standard/mfloat-abi=hard
+MULTILIB_REQUIRED  += 
mthumb/march=armv8.1-m.main+pacbti+fp.dp/mbranch-protection=standard/mfloat-abi=softfp
+MULTILIB_REQUIRED  += 
mthumb/march=armv8.1-m.main+pacbti+fp.dp/mbranch-protection=standard/mfloat-abi=hard
+MULTILIB_REQUIRED  += 
mthumb/march=armv8.1-m.main+pacbti+mve/mbranch-protection=standard/mfloat-abi=hard
+
+
 # Arch Matches
 MULTILIB_MATCHES   += march?armv6s-m=march?armv6-m
 
@@ -93,3 +104,4 @@ MULTILIB_MATCHES += 
march?armv8-m.main=mlibarch?armv8-m.main
 MULTILIB_MATCHES   += march?armv8-m.main+fp=mlibarch?armv8-m.main+fp
 MULTILIB_MATCHES   += march?armv8-m.main+fp.dp=mlibarch?armv8-m.main+fp.dp
 MULTILIB_MATCHES   += march?armv8.1-m.main+mve=mlibarch?armv8.1-m.main+mve
+MULTILIB_MATCHES   += 
march?armv8.1-m.main+pacbti=mlibarch?armv8.1-m.main+pacbti

[PATCH 9/12] arm: Make libgcc bti compatible

[Andrea Corallo via Gcc-patches]

This change add bti instructions at the beginning of arm specific
libgcc hand written assembly routines.

2022-03-31  Andrea Corallo  

* libgcc/config/arm/crti.S (FUNC_START): Add bti instruction if
necessary.
* libgcc/config/arm/lib1funcs.S (THUMB_FUNC_START, FUNC_START):
Likewise.

diff --git a/libgcc/config/arm/crti.S b/libgcc/config/arm/crti.S
index 0192972a7e6..bac2d87fbb9 100644
--- a/libgcc/config/arm/crti.S
+++ b/libgcc/config/arm/crti.S
@@ -51,7 +51,9 @@
 .macro FUNC_START
 #ifdef __thumb__
.thumb
-   
+#if defined(__ARM_FEATURE_BTI)
+   bti
+#endif
push{r3, r4, r5, r6, r7, lr}
 #else
.arm
diff --git a/libgcc/config/arm/lib1funcs.S b/libgcc/config/arm/lib1funcs.S
index 8c39c9f20a2..45dfb5da9ee 100644
--- a/libgcc/config/arm/lib1funcs.S
+++ b/libgcc/config/arm/lib1funcs.S
@@ -345,6 +345,9 @@ LSYM(Ldiv0):
TYPE(\name)
.thumb_func
 SYM (\name):
+#if defined(__ARM_FEATURE_BTI)
+   bti
+#endif
 .endm
 
 /* Function start macros.  Variants for ARM and Thumb.  */
@@ -372,6 +375,9 @@ SYM (\name):
THUMB_FUNC
THUMB_SYNTAX
 SYM (__\name):
+#if defined(__ARM_FEATURE_BTI)
+   bti
+#endif
 .endm
 
 .macro ARM_SYM_START name

[PATCH 10/12] arm: Implement cortex-M return signing address codegen

[Andrea Corallo via Gcc-patches]

Hi all,

this patch enables address return signature and verification based on
Armv8.1-M Pointer Authentication [1].

To sign the return address, we use the PAC R12, LR, SP instruction
upon function entry.  This is signing LR using SP and storing the
result in R12.  R12 will be pushed into the stack.

During function epilogue R12 will be popped and AUT R12, LR, SP will
be used to verify that the content of LR is still valid before return.

Here an example of PAC instrumented function prologue and epilogue:

void foo (void);

int main()
{
  foo ();
  return 0;
}

Compiled with '-march=armv8.1-m.main -mbranch-protection=pac-ret
-mthumb' translates into:

main:
pac ip, lr, sp
push{r3, r7, ip, lr}
add r7, sp, #0
bl  foo
movsr3, #0
mov r0, r3
pop {r3, r7, ip, lr}
aut ip, lr, sp
bx  lr

The patch also takes care of generating a PACBTI instruction in place
of the sequence BTI+PAC when Branch Target Identification is enabled
contextually.

Ex. the previous example compiled with '-march=armv8.1-m.main
-mbranch-protection=pac-ret+bti -mthumb' translates into:

main:
pacbti  ip, lr, sp
push{r3, r7, ip, lr}
add r7, sp, #0
bl  foo
movsr3, #0
mov r0, r3
pop {r3, r7, ip, lr}
aut ip, lr, sp
bx  lr

As part of previous upstream suggestions a test for varargs has been
added and '-mtpcs-frame' is deemed being incompatible with this return
signing address feature being introduced.

[1] 


gcc/Changelog

* config/arm/arm.c: (arm_compute_frame_layout)
(arm_expand_prologue, thumb2_expand_return, arm_expand_epilogue)
(arm_conditional_register_usage): Update for pac codegen.
(arm_current_function_pac_enabled_p): New function.
* config/arm/arm.md (pac_ip_lr_sp, pacbti_ip_lr_sp, aut_ip_lr_sp):
Add new patterns.
* config/arm/unspecs.md (UNSPEC_PAC_IP_LR_SP)
(UNSPEC_PACBTI_IP_LR_SP, UNSPEC_AUT_IP_LR_SP): Add unspecs.

gcc/testsuite/Changelog

* gcc.target/arm/pac.h : New file.
* gcc.target/arm/pac-1.c : New test case.
* gcc.target/arm/pac-2.c : Likewise.
* gcc.target/arm/pac-3.c : Likewise.
* gcc.target/arm/pac-4.c : Likewise.
* gcc.target/arm/pac-5.c : Likewise.
* gcc.target/arm/pac-6.c : Likewise.
* gcc.target/arm/pac-7.c : Likewise.
* gcc.target/arm/pac-8.c : Likewise.

diff --git a/gcc/config/arm/arm.cc b/gcc/config/arm/arm.cc
index ceec14f84b6..c91dae292c8 100644
--- a/gcc/config/arm/arm.cc
+++ b/gcc/config/arm/arm.cc
@@ -302,6 +302,7 @@ static bool arm_vectorize_vec_perm_const (machine_mode, 
rtx, rtx, rtx,
  const vec_perm_indices &);
 
 static bool aarch_macro_fusion_pair_p (rtx_insn*, rtx_insn*);
+static bool arm_current_function_pac_enabled_p (void);
 
 static int arm_builtin_vectorization_cost (enum vect_cost_for_stmt 
type_of_cost,
   tree vectype,
@@ -21139,6 +21140,14 @@ arm_compute_save_core_reg_mask (void)
 
   save_reg_mask |= arm_compute_save_reg0_reg12_mask ();
 
+  if (arm_current_function_pac_enabled_p ())
+{
+  if (TARGET_TPCS_FRAME
+ || (TARGET_TPCS_LEAF_FRAME && crtl->is_leaf))
+   error ("TPCS incompatible with return address signing.");
+  save_reg_mask |= 1 << IP_REGNUM;
+}
+
   /* Decide if we need to save the link register.
  Interrupt routines have their own banked link register,
  so they never need to save it.
@@ -22302,7 +22311,7 @@ arm_emit_multi_reg_pop (unsigned long saved_regs_mask)
 par = emit_insn (par);
 
   REG_NOTES (par) = dwarf;
-  if (!return_in_pc)
+  if (!return_in_pc && !frame_pointer_needed)
 arm_add_cfa_adjust_cfa_note (par, UNITS_PER_WORD * num_regs,
 stack_pointer_rtx, stack_pointer_rtx);
 }
@@ -23352,6 +23361,11 @@ output_probe_stack_range (rtx reg1, rtx reg2)
   return "";
 }
 
+static bool  aarch_bti_enabled ()
+{
+  return false;
+}
+
 /* Generate the prologue instructions for entry into an ARM or Thumb-2
function.  */
 void
@@ -23431,11 +23445,12 @@ arm_expand_prologue (void)
   /* The static chain register is the same as the IP register.  If it is
  clobbered when creating the frame, we need to save and restore it.  */
   clobber_ip = IS_NESTED (func_type)
-  && ((TARGET_APCS_FRAME && frame_pointer_needed && TARGET_ARM)
-  || ((flag_stack_check == STATIC_BUILTIN_STACK_CHECK
-   || flag_stack_clash_protection)
-  && !df_regs_ever_live_p (LR_REGNUM)
-  && arm_r3_live_at_start_p ()));
+&& (((TARGET_APCS_FRAME && frame_pointer_ne

[PATCH 11/12] aarch64: Make bti pass generic so it can be used by the arm backend

[Andrea Corallo via Gcc-patches]

Hi all,

this patch splits and restructures the aarch64 bti pass code in order
to have it usable by the arm backend as well.  These changes have no
functional impact.

Best Regards

  Andrea

gcc/Changelog

* config.gcc (aarch64*-*-*): Rename 'aarch64-bti-insert.o' into
'aarch-bti-insert.o'.
* config/aarch64/aarch64-protos.h: Remove 'aarch64_bti_enabled'
proto.
* config/aarch64/aarch64.cc (aarch_bti_enabled): Rename.
(aarch_bti_j_insn_p, aarch_pac_insn_p): New functions.
(aarch64_output_mi_thunk)
(aarch64_print_patchable_function_entry)
(aarch64_file_end_indicate_exec_stack): Update renamed function
calls to renamed functions.
* config/aarch64/t-aarch64 (aarch-bti-insert.o): Update target.
* config/arm/aarch-bti-insert.cc: New file including and
generalizing code from aarch64-bti-insert.cc.
* config/arm/aarch-common-protos.h: Update.
* config/arm/arm-passes.def: New file.

diff --git a/gcc/config.gcc b/gcc/config.gcc
index 7b58e1314ff..2021bdf9d2f 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -329,7 +329,7 @@ aarch64*-*-*)
c_target_objs="aarch64-c.o"
cxx_target_objs="aarch64-c.o"
d_target_objs="aarch64-d.o"
-   extra_objs="aarch64-builtins.o aarch-common.o aarch64-sve-builtins.o 
aarch64-sve-builtins-shapes.o aarch64-sve-builtins-base.o 
aarch64-sve-builtins-sve2.o cortex-a57-fma-steering.o aarch64-speculation.o 
falkor-tag-collision-avoidance.o aarch64-bti-insert.o aarch64-cc-fusion.o"
+   extra_objs="aarch64-builtins.o aarch-common.o aarch64-sve-builtins.o 
aarch64-sve-builtins-shapes.o aarch64-sve-builtins-base.o 
aarch64-sve-builtins-sve2.o cortex-a57-fma-steering.o aarch64-speculation.o 
falkor-tag-collision-avoidance.o aarch-bti-insert.o aarch64-cc-fusion.o"
target_gtfiles="\$(srcdir)/config/aarch64/aarch64-builtins.cc 
\$(srcdir)/config/aarch64/aarch64-sve-builtins.h 
\$(srcdir)/config/aarch64/aarch64-sve-builtins.cc"
target_has_targetm_common=yes
;;
diff --git a/gcc/config/aarch64/aarch64-c.cc b/gcc/config/aarch64/aarch64-c.cc
index b0c5a4fd6b6..a9aad3abdc2 100644
--- a/gcc/config/aarch64/aarch64-c.cc
+++ b/gcc/config/aarch64/aarch64-c.cc
@@ -179,7 +179,7 @@ aarch64_update_cpp_builtins (cpp_reader *pfile)
   aarch64_def_or_undef (TARGET_RNG, "__ARM_FEATURE_RNG", pfile);
   aarch64_def_or_undef (TARGET_MEMTAG, "__ARM_FEATURE_MEMORY_TAGGING", pfile);
 
-  aarch64_def_or_undef (aarch64_bti_enabled (),
+  aarch64_def_or_undef (aarch_bti_enabled (),
"__ARM_FEATURE_BTI_DEFAULT", pfile);
 
   cpp_undef (pfile, "__ARM_FEATURE_PAC_DEFAULT");
diff --git a/gcc/config/aarch64/aarch64-protos.h 
b/gcc/config/aarch64/aarch64-protos.h
index fe2180e95ea..9fdf7f9cc9c 100644
--- a/gcc/config/aarch64/aarch64-protos.h
+++ b/gcc/config/aarch64/aarch64-protos.h
@@ -891,7 +891,6 @@ void aarch64_register_pragmas (void);
 void aarch64_relayout_simd_types (void);
 void aarch64_reset_previous_fndecl (void);
 bool aarch64_return_address_signing_enabled (void);
-bool aarch64_bti_enabled (void);
 void aarch64_save_restore_target_globals (tree);
 void aarch64_addti_scratch_regs (rtx, rtx, rtx *,
 rtx *, rtx *,
diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc
index eec743024c1..2f67f3872f6 100644
--- a/gcc/config/aarch64/aarch64.cc
+++ b/gcc/config/aarch64/aarch64.cc
@@ -8534,11 +8534,61 @@ aarch64_return_address_signing_enabled (void)
 
 /* Return TRUE if Branch Target Identification Mechanism is enabled.  */
 bool
-aarch64_bti_enabled (void)
+aarch_bti_enabled (void)
 {
   return (aarch_enable_bti == 1);
 }
 
+/* Check if INSN is a BTI J insn.  */
+bool
+aarch_bti_j_insn_p (rtx_insn *insn)
+{
+  if (!insn || !INSN_P (insn))
+return false;
+
+  rtx pat = PATTERN (insn);
+  return GET_CODE (pat) == UNSPEC_VOLATILE && XINT (pat, 1) == UNSPECV_BTI_J;
+}
+
+/* Check if X (or any sub-rtx of X) is a PACIASP/PACIBSP instruction.  */
+bool
+aarch_pac_insn_p (rtx x)
+{
+  if (!INSN_P (x))
+return false;
+
+  subrtx_var_iterator::array_type array;
+  FOR_EACH_SUBRTX_VAR (iter, array, PATTERN (x), ALL)
+{
+  rtx sub = *iter;
+  if (sub && GET_CODE (sub) == UNSPEC)
+   {
+ int unspec_val = XINT (sub, 1);
+ switch (unspec_val)
+   {
+   case UNSPEC_PACIASP:
+case UNSPEC_PACIBSP:
+ return true;
+
+   default:
+ return false;
+   }
+ iter.skip_subrtxes ();
+   }
+}
+  return false;
+}
+
+rtx aarch_gen_bti_c (void)
+{
+  return gen_bti_c ();
+}
+
+rtx aarch_gen_bti_j (void)
+{
+  return gen_bti_j ();
+}
+
 /* The caller is going to use ST1D or LD1D to save or restore an SVE
register in mode MODE at BASE_RTX + OFFSET, where OFFSET is in
the range [1, 16] * GET_MODE_SIZE (MODE).  Prepare for this by:
@@ -9918,7 +9968,7 @@ aarch64_output_mi_thunk (FILE *file, 

[PATCH 12/12] arm: implement bti injection

[Andrea Corallo via Gcc-patches]

Hi all,

this patch enables Branch Target Identification Armv8.1-M Mechanism
[1].

This is achieved by using the bti pass made common with Aarch64.

The pass iterates through the instructions and adds the necessary BTI
instructions at the beginning of every function and at every landing
pads targeted by indirect jumps.

Best Regards

  Andrea

[1]


gcc/ChangeLog

* config.gcc (arm*-*-*): Add 'aarch-bti-insert.o' object.
* config/arm/arm-protos.h: Update.
* config/arm/arm.cc (aarch_bti_enabled, aarch_bti_j_insn_p)
(aarch_pac_insn_p, aarch_gen_bti_c, aarch_gen_bti_j): New
functions.
* config/arm/arm.md (bti_nop): New insn.
* config/arm/t-arm (PASSES_EXTRA): Add 'arm-passes.def'.
(aarch-bti-insert.o): New target.
* config/arm/unspecs.md (UNSPEC_BTI_NOP): New unspec.

gcc/testsuite/ChangeLog

* gcc.target/arm/bti-1.c: New testcase.
* gcc.target/arm/bti-2.c: Likewise.

diff --git a/gcc/config.gcc b/gcc/config.gcc
index 2021bdf9d2f..004e1dfa8d8 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -353,7 +353,7 @@ arc*-*-*)
;;
 arm*-*-*)
cpu_type=arm
-   extra_objs="arm-builtins.o arm-mve-builtins.o aarch-common.o"
+   extra_objs="arm-builtins.o arm-mve-builtins.o aarch-common.o 
aarch-bti-insert.o"
extra_headers="mmintrin.h arm_neon.h arm_acle.h arm_fp16.h arm_cmse.h 
arm_bf16.h arm_mve_types.h arm_mve.h arm_cde.h"
target_type_format_char='%'
c_target_objs="arm-c.o"
diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h
index cff7ff1da2a..da23e0a4735 100644
--- a/gcc/config/arm/arm-protos.h
+++ b/gcc/config/arm/arm-protos.h
@@ -24,6 +24,8 @@
 
 #include "sbitmap.h"
 
+rtl_opt_pass *make_pass_insert_bti (gcc::context *ctxt);
+
 extern enum unwind_info_type arm_except_unwind_info (struct gcc_options *);
 extern int use_return_insn (int, rtx);
 extern bool use_simple_return_p (void);
diff --git a/gcc/config/arm/arm.cc b/gcc/config/arm/arm.cc
index c91dae292c8..a2b720a6660 100644
--- a/gcc/config/arm/arm.cc
+++ b/gcc/config/arm/arm.cc
@@ -23361,11 +23361,6 @@ output_probe_stack_range (rtx reg1, rtx reg2)
   return "";
 }
 
-static bool  aarch_bti_enabled ()
-{
-  return false;
-}
-
 /* Generate the prologue instructions for entry into an ARM or Thumb-2
function.  */
 void
@@ -32981,6 +32976,56 @@ arm_current_function_pac_enabled_p (void)
&& !crtl->is_leaf);
 }
 
+/* Return TRUE if Branch Target Identification Mechanism is enabled.  */
+bool
+aarch_bti_enabled (void)
+{
+  return aarch_enable_bti == 1;
+}
+
+/* Check if INSN is a BTI J insn.  */
+bool
+aarch_bti_j_insn_p (rtx_insn *insn)
+{
+  if (!insn || !INSN_P (insn))
+return false;
+
+  rtx pat = PATTERN (insn);
+  return GET_CODE (pat) == UNSPEC_VOLATILE && XINT (pat, 1) == UNSPEC_BTI_NOP;
+}
+
+/* Check if X (or any sub-rtx of X) is a PACIASP/PACIBSP instruction.  */
+bool
+aarch_pac_insn_p (rtx x)
+{
+  if (!x || !INSN_P (x))
+return false;
+
+  rtx pat = PATTERN (x);
+
+  if (GET_CODE (pat) == SET)
+{
+  rtx tmp = XEXP (pat, 1);
+  if (tmp
+ && GET_CODE (tmp) == UNSPEC
+ && (XINT (tmp, 1) == UNSPEC_PAC_NOP
+ || XINT (tmp, 1) == UNSPEC_PACBTI_NOP))
+   return true;
+}
+
+  return false;
+}
+
+rtx aarch_gen_bti_c (void)
+{
+  return gen_bti_nop ();
+}
+
+rtx aarch_gen_bti_j (void)
+{
+  return gen_bti_nop ();
+}
+
 /* Implement TARGET_SCHED_CAN_SPECULATE_INSN.  Return true if INSN can be
scheduled for speculative execution.  Reject the long-running division
and square-root instructions.  */
diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index b480f76a876..2221bc68f35 100644
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -12913,6 +12913,12 @@
   "aut\t%|ip, %|lr, %|sp"
   [(set_attr "length" "2")])
 
+(define_insn "bti_nop"
+  [(unspec_volatile [(const_int 0)] UNSPEC_BTI_NOP)]
+  "TARGET_THUMB2"
+  "bti"
+  [(set_attr "type" "mov_reg")])
+
 ;; Vector bits common to IWMMXT, Neon and MVE
 (include "vec-common.md")
 ;; Load the Intel Wireless Multimedia Extension patterns
diff --git a/gcc/config/arm/t-arm b/gcc/config/arm/t-arm
index 041cc6ec045..683342cb528 100644
--- a/gcc/config/arm/t-arm
+++ b/gcc/config/arm/t-arm
@@ -175,3 +175,13 @@ arm-d.o: $(srcdir)/config/arm/arm-d.cc
 arm-common.o: arm-cpu-cdata.h
 
 driver-arm.o: arm-native.h
+
+PASSES_EXTRA += $(srcdir)/config/arm/arm-passes.def
+
+aarch-bti-insert.o: $(srcdir)/config/arm/aarch-bti-insert.cc \
+$(CONFIG_H) $(SYSTEM_H) $(TM_H) $(REGS_H) insn-config.h $(RTL_BASE_H) \
+dominance.h cfg.h cfganal.h $(BASIC_BLOCK_H) $(INSN_ATTR_H) $(RECOG_H) \
+output.h hash-map.h $(DF_H) $(OBSTACK_H) $(TARGET_H) $(RTL_H) \
+$(CONTEXT_H) $(TREE_PASS_H) regrename.h
+   $(COMPILER) -c $(ALL_COMPILERF

Re: [PATCH 2/x] arm: add vst1_lane_bf16 + vstq_lane_bf16 intrinsics

[Andrea Corallo via Gcc-patches]

Andrea Corallo via Gcc-patches  writes:

> Hi all,
>
> Second patch of the serie here adding vst1_lane_bf16, vst1q_lane_bf16
> bfloat16 related neon intrinsics.
>
> Please see refer to:
> ACLE <https://developer.arm.com/docs/101028/latest>
> ISA  <https://developer.arm.com/docs/ddi0596/latest>
>
> Regtested and bootstrapped.
>
> Okay for trunk?
>
>   Andrea
>   

Ping

Re: [PATCH 1/x] arm: Add vld1_lane_bf16 + vldq_lane_bf16 intrinsics

[Andrea Corallo via Gcc-patches]

Andrea Corallo via Gcc-patches  writes:

> Hi all,
>
> I'd like to submit the following patch implementing the bfloat16_t
> neon related load intrinsics: vld1_lane_bf16, vld1q_lane_bf16.
>
> Please see refer to:
> ACLE <https://developer.arm.com/docs/101028/latest>
> ISA  <https://developer.arm.com/docs/ddi0596/latest>
>
> Regtested and bootstrapped.
>
> Okay for trunk?
>
>   Andrea

Ping

[PATCH 3/x] arm: Add vld1_bf16 + vld1q_bf16 intrinsics

[Andrea Corallo via Gcc-patches]

Hi all,

Third patch of the serie here adding vld1_bf16, vld1q_bf16 bfloat16
related neon intrinsics.

Please see refer to:
ACLE 
ISA  

Regtested and bootstrapped.

Thanks!

  Andrea

gcc/ChangeLog

2020-10-29  Andrea Corallo  

* config/arm/arm-builtins.c (VAR14): Define macro.
* config/arm/arm_neon_builtins.def: Touch for:
__builtin_neon_vld1v4bf, __builtin_neon_vld1v8bf.
* config/arm/arm_neon.h (vld1_bf16, vld1q_bf16): Add intrinsics.

gcc/testsuite/ChangeLog

2020-10-29  Andrea Corallo  

* gcc.target/arm/simd/vld1_bf16_1.c: New test.

>From f6dd72dfb2f5b5970ad53da64febd8e709a1ff22 Mon Sep 17 00:00:00 2001
From: Andrea Corallo 
Date: Thu, 29 Oct 2020 13:56:17 +0100
Subject: [PATCH 3/6] arm: Add vld1_bf16 + vld1q_bf16 intrinsics

gcc/ChangeLog

2020-10-29  Andrea Corallo  

* config/arm/arm-builtins.c (VAR14): Define macro.
* config/arm/arm_neon_builtins.def: Touch for:
__builtin_neon_vld1v4bf, __builtin_neon_vld1v8bf.
* config/arm/arm_neon.h (vld1_bf16, vld1q_bf16): Add intrinsics.

gcc/testsuite/ChangeLog

2020-10-29  Andrea Corallo  

* gcc.target/arm/simd/vld1_bf16_1.c: New test.
---
 gcc/config/arm/arm-builtins.c |  3 ++
 gcc/config/arm/arm_neon.h | 14 +
 gcc/config/arm/arm_neon_builtins.def  |  5 ++--
 .../gcc.target/arm/simd/vld1_bf16_1.c | 29 +++
 4 files changed, 49 insertions(+), 2 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/arm/simd/vld1_bf16_1.c

diff --git a/gcc/config/arm/arm-builtins.c b/gcc/config/arm/arm-builtins.c
index 33e8015b140..6dc5df93216 100644
--- a/gcc/config/arm/arm-builtins.c
+++ b/gcc/config/arm/arm-builtins.c
@@ -946,6 +946,9 @@ typedef struct {
 #define VAR13(T, N, A, B, C, D, E, F, G, H, I, J, K, L, M) \
   VAR12 (T, N, A, B, C, D, E, F, G, H, I, J, K, L) \
   VAR1 (T, N, M)
+#define VAR14(T, N, A, B, C, D, E, F, G, H, I, J, K, L, M, O) \
+  VAR13 (T, N, A, B, C, D, E, F, G, H, I, J, K, L, M) \
+  VAR1 (T, N, O)
 
 /* The builtin data can be found in arm_neon_builtins.def, arm_vfp_builtins.def
and arm_acle_builtins.def.  The entries in arm_neon_builtins.def require
diff --git a/gcc/config/arm/arm_neon.h b/gcc/config/arm/arm_neon.h
index 432d77fb272..b77175eaa3e 100644
--- a/gcc/config/arm/arm_neon.h
+++ b/gcc/config/arm/arm_neon.h
@@ -19557,6 +19557,20 @@ vst4q_bf16 (bfloat16_t * __ptr, bfloat16x8x4_t __val)
   return __builtin_neon_vst4v8bf (__ptr, __bu.__o);
 }
 
+__extension__ extern __inline bfloat16x4_t
+__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+vld1_bf16 (bfloat16_t const * __ptr)
+{
+  return __builtin_neon_vld1v4bf (__ptr);
+}
+
+__extension__ extern __inline bfloat16x8_t
+__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+vld1q_bf16 (const bfloat16_t * __ptr)
+{
+  return __builtin_neon_vld1v8bf (__ptr);
+}
+
 __extension__ extern __inline bfloat16x4x2_t
 __attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
 vld2_bf16 (bfloat16_t const * __ptr)
diff --git a/gcc/config/arm/arm_neon_builtins.def 
b/gcc/config/arm/arm_neon_builtins.def
index 7a5dae0c4c0..07eda44cc58 100644
--- a/gcc/config/arm/arm_neon_builtins.def
+++ b/gcc/config/arm/arm_neon_builtins.def
@@ -310,8 +310,9 @@ VAR1 (TERNOP, vtbx1, v8qi)
 VAR1 (TERNOP, vtbx2, v8qi)
 VAR1 (TERNOP, vtbx3, v8qi)
 VAR1 (TERNOP, vtbx4, v8qi)
-VAR12 (LOAD1, vld1,
-v8qi, v4hi, v4hf, v2si, v2sf, di, v16qi, v8hi, v8hf, v4si, v4sf, v2di)
+VAR14 (LOAD1, vld1,
+v8qi, v4hi, v4hf, v2si, v2sf, di, v16qi, v8hi, v8hf, v4si, v4sf, v2di,
+v4bf, v8bf)
 VAR12 (LOAD1LANE, vld1_lane,
v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di, v4bf, v8bf)
 VAR10 (LOAD1, vld1_dup,
diff --git a/gcc/testsuite/gcc.target/arm/simd/vld1_bf16_1.c 
b/gcc/testsuite/gcc.target/arm/simd/vld1_bf16_1.c
new file mode 100644
index 000..b6b00dc03c2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/simd/vld1_bf16_1.c
@@ -0,0 +1,29 @@
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_v8_2a_bf16_neon_ok } */
+/* { dg-add-options arm_v8_2a_bf16_neon } */
+/* { dg-additional-options "-save-temps -O2 -mfloat-abi=hard" }  */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "arm_neon.h"
+
+/*
+**test_vld1_bf16:
+** vld1.16 {d0}, \[r0\]
+** bx  lr
+*/
+bfloat16x4_t
+test_vld1_bf16 (bfloat16_t const *p)
+{
+  return vld1_bf16 (p);
+}
+
+/*
+**test_vld1q_bf16:
+** vld1.16 {d0-d1}, \[r0\]
+** bx  lr
+*/
+bfloat16x8_t
+test_vld1q_bf16 (bfloat16_t const *p)
+{
+  return vld1q_bf16 (p);
+}
-- 
2.20.1

[PATCH 4/x] arm: Add vst1_bf16 + vst1q_bf16 intrinsics

[Andrea Corallo via Gcc-patches]

Hi all,

Forth patch of the serie here adding vst1_bf16, vst1q_bf16 bfloat16
related neon intrinsics.

Please see refer to:
ACLE 
ISA  

Regtested and bootstrapped.

Thanks!

  Andrea

gcc/ChangeLog

2020-10-29  Andrea Corallo  

* config/arm/arm_neon.h (vst1_bf16, vst1q_bf16): Add intrinsics.
* config/arm/arm_neon_builtins.def : Touch for:
__builtin_neon_vst1v4bf, __builtin_neon_vst1v8bf.

gcc/testsuite/ChangeLog

2020-10-29  Andrea Corallo  

* gcc.target/arm/simd/vst1_bf16_1.c: New test.

>From e7b261dcab943401bac777ed3149bd6c5e9b3599 Mon Sep 17 00:00:00 2001
From: Andrea Corallo 
Date: Thu, 29 Oct 2020 15:11:37 +0100
Subject: [PATCH 4/6] arm: Add vst1_bf16 + vst1q_bf16 intrinsics

gcc/ChangeLog

2020-10-29  Andrea Corallo  

* config/arm/arm_neon.h (vst1_bf16, vst1q_bf16): Add intrinsics.
* config/arm/arm_neon_builtins.def : Touch for:
__builtin_neon_vst1v4bf, __builtin_neon_vst1v8bf.

gcc/testsuite/ChangeLog

2020-10-29  Andrea Corallo  

* gcc.target/arm/simd/vst1_bf16_1.c: New test.
---
 gcc/config/arm/arm_neon.h | 14 +
 gcc/config/arm/arm_neon_builtins.def  |  5 ++--
 .../gcc.target/arm/simd/vst1_bf16_1.c | 29 +++
 3 files changed, 46 insertions(+), 2 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/arm/simd/vst1_bf16_1.c

diff --git a/gcc/config/arm/arm_neon.h b/gcc/config/arm/arm_neon.h
index b77175eaa3e..24aad3370f6 100644
--- a/gcc/config/arm/arm_neon.h
+++ b/gcc/config/arm/arm_neon.h
@@ -19509,6 +19509,20 @@ vbfmlaltq_laneq_f32 (float32x4_t __r, bfloat16x8_t 
__a, bfloat16x8_t __b,
   return __builtin_neon_vfmat_laneqv8bf (__r, __a, __b, __index);
 }
 
+__extension__ extern __inline void
+__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_bf16 (bfloat16_t * __a, bfloat16x4_t __b)
+{
+  __builtin_neon_vst1v4bf (__a, __b);
+}
+
+__extension__ extern __inline void
+__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+vst1q_bf16 (bfloat16_t * __a, bfloat16x8_t __b)
+{
+  __builtin_neon_vst1v8bf (__a, __b);
+}
+
 __extension__ extern __inline void
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 vst2_bf16 (bfloat16_t * __ptr, bfloat16x4x2_t __val)
diff --git a/gcc/config/arm/arm_neon_builtins.def 
b/gcc/config/arm/arm_neon_builtins.def
index 07eda44cc58..e3ab6281497 100644
--- a/gcc/config/arm/arm_neon_builtins.def
+++ b/gcc/config/arm/arm_neon_builtins.def
@@ -317,8 +317,9 @@ VAR12 (LOAD1LANE, vld1_lane,
v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di, v4bf, v8bf)
 VAR10 (LOAD1, vld1_dup,
v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di)
-VAR12 (STORE1, vst1,
-   v8qi, v4hi, v4hf, v2si, v2sf, di, v16qi, v8hi, v8hf, v4si, v4sf, v2di)
+VAR14 (STORE1, vst1,
+v8qi, v4hi, v4hf, v2si, v2sf, di, v16qi, v8hi, v8hf, v4si, v4sf, v2di,
+v4bf, v8bf)
 VAR14 (STORE1LANE, vst1_lane,
v8qi, v4hi, v4hf, v2si, v2sf, di, v16qi, v8hi, v8hf, v4si, v4sf, v2di, 
v4bf, v8bf)
 VAR13 (LOAD1, vld2,
diff --git a/gcc/testsuite/gcc.target/arm/simd/vst1_bf16_1.c 
b/gcc/testsuite/gcc.target/arm/simd/vst1_bf16_1.c
new file mode 100644
index 000..06fb58ecd79
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/simd/vst1_bf16_1.c
@@ -0,0 +1,29 @@
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_v8_2a_bf16_neon_ok } */
+/* { dg-add-options arm_v8_2a_bf16_neon } */
+/* { dg-additional-options "-save-temps -O2 -mfloat-abi=hard" }  */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "arm_neon.h"
+
+/*
+**test_vst1_bf16:
+** vst1.16 {d0}, \[r0\]
+** bx  lr
+*/
+void
+test_vst1_bf16 (bfloat16_t *a, bfloat16x4_t b)
+{
+  vst1_bf16 (a, b);
+}
+
+/*
+**test_vst1q_bf16:
+** vst1.16 {d0-d1}, \[r0\]
+** bx  lr
+*/
+void
+test_vst1q_bf16 (bfloat16_t *a, bfloat16x8_t b)
+{
+  vst1q_bf16 (a, b);
+}
-- 
2.20.1

[PATCH 5/x] arm: Add vldN_lane_bf16 + vldNq_lane_bf16 intrisics

[Andrea Corallo via Gcc-patches]

Hi all,

5th patch of the serie here adding vld2_lane_bf16, vld2q_lane_bf16,
vld3_lane_bf16, vld3q_lane_bf16, vld4_lane_bf16, vld4q_lane_bf16
related neon intrinsics.

Please see refer to:
ACLE 
ISA  

Regtested and bootstrapped.

Thanks!

  Andrea

gcc/ChangeLog

2020-10-29  Andrea Corallo  

* config/arm/arm_neon.h (vld2_lane_bf16, vld2q_lane_bf16)
(vld3_lane_bf16, vld3q_lane_bf16, vld4_lane_bf16)
(vld4q_lane_bf16): Add intrinsics.
* config/arm/arm_neon_builtins.def: Touch for:
__builtin_neon_vld2_lanev4bf, __builtin_neon_vld2_lanev8bf,
__builtin_neon_vld3_lanev4bf, __builtin_neon_vld3_lanev8bf,
__builtin_neon_vld4_lanev4bf, __builtin_neon_vld4_lanev8bf.
* config/arm/iterators.md (VQ_HS): Add V8BF to the iterator.

gcc/testsuite/ChangeLog

2020-10-29  Andrea Corallo  

* gcc.target/aarch64/advsimd-intrinsics/vld2_lane_bf16_indices_1.c:
Run it also for the arm backend.
* gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_bf16_indices_1.c:
Likewise.
* gcc.target/aarch64/advsimd-intrinsics/vld3_lane_bf16_indices_1.c:
Likewise.
* gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_bf16_indices_1.c:
Likewise.
* gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_bf16_indices_1.c:
Likewise.
* gcc.target/arm/simd/vldn_lane_bf16_1.c: New test.

>From eafe168906ac8c375a398ff72f9b8657c30fe8e7 Mon Sep 17 00:00:00 2001
From: Andrea Corallo 
Date: Mon, 26 Oct 2020 18:31:19 +0100
Subject: [PATCH 5/6] arm: Add vldN_lane_bf16 + vldNq_lane_bf16 intrisics

gcc/ChangeLog

2020-10-29  Andrea Corallo  

* config/arm/arm_neon.h (vld2_lane_bf16, vld2q_lane_bf16)
(vld3_lane_bf16, vld3q_lane_bf16, vld4_lane_bf16)
(vld4q_lane_bf16): Add intrinsics.
* config/arm/arm_neon_builtins.def: Touch for:
__builtin_neon_vld2_lanev4bf, __builtin_neon_vld2_lanev8bf,
__builtin_neon_vld3_lanev4bf, __builtin_neon_vld3_lanev8bf,
__builtin_neon_vld4_lanev4bf, __builtin_neon_vld4_lanev8bf.
* config/arm/iterators.md (VQ_HS): Add V8BF to the iterator.

gcc/testsuite/ChangeLog

2020-10-29  Andrea Corallo  

* gcc.target/aarch64/advsimd-intrinsics/vld2_lane_bf16_indices_1.c:
Run it also for the arm backend.
* gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_bf16_indices_1.c:
Likewise.
* gcc.target/aarch64/advsimd-intrinsics/vld3_lane_bf16_indices_1.c:
Likewise.
* gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_bf16_indices_1.c:
Likewise.
* gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_bf16_indices_1.c:
Likewise.
* gcc.target/arm/simd/vldn_lane_bf16_1.c: New test.
---
 gcc/config/arm/arm_neon.h | 62 
 gcc/config/arm/arm_neon_builtins.def  | 12 +--
 gcc/config/arm/iterators.md   |  2 +-
 .../vld2_lane_bf16_indices_1.c|  2 +-
 .../vld2q_lane_bf16_indices_1.c   |  2 +-
 .../vld3_lane_bf16_indices_1.c|  2 +-
 .../vld3q_lane_bf16_indices_1.c   |  2 +-
 .../vld4_lane_bf16_indices_1.c|  2 +-
 .../vld4q_lane_bf16_indices_1.c   |  2 +-
 .../gcc.target/arm/simd/vldn_lane_bf16_1.c| 73 +++
 10 files changed, 148 insertions(+), 13 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/arm/simd/vldn_lane_bf16_1.c

diff --git a/gcc/config/arm/arm_neon.h b/gcc/config/arm/arm_neon.h
index 24aad3370f6..4fee128ce8d 100644
--- a/gcc/config/arm/arm_neon.h
+++ b/gcc/config/arm/arm_neon.h
@@ -19721,6 +19721,68 @@ vst1q_lane_bf16 (bfloat16_t * __a, bfloat16x8_t __b, 
const int __c)
   __builtin_neon_vst1_lanev8bf (__a, __b, __c);
 }
 
+__extension__ extern __inline bfloat16x4x2_t
+__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+vld2_lane_bf16 (const bfloat16_t * __a, bfloat16x4x2_t __b, const int __c)
+{
+  union { bfloat16x4x2_t __i; __builtin_neon_ti __o; } __bu = { __b };
+  union { bfloat16x4x2_t __i; __builtin_neon_ti __o; } __rv;
+  __rv.__o = __builtin_neon_vld2_lanev4bf ( __a, __bu.__o, __c);
+  return __rv.__i;
+}
+
+__extension__ extern __inline bfloat16x8x2_t
+__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+vld2q_lane_bf16 (const bfloat16_t * __a, bfloat16x8x2_t __b, const int __c)
+{
+  union { bfloat16x8x2_t __i; __builtin_neon_oi __o; } __bu = { __b };
+  union { bfloat16x8x2_t __i; __builtin_neon_oi __o; } __rv;
+  __rv.__o = __builtin_neon_vld2_lanev8bf (__a, __bu.__o, __c);
+  return __rv.__i;
+}
+
+__extension__ extern __inline bfloat16x4x3_t
+__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+vld3_lane_bf16 (const bfloat16_t * __a, bfloat16x4x3_t __b, const int __c)
+{
+  union { bfloat16x4x3_t __i; __builtin_neon_ei __o; } __bu = { __b };
+  unio

[PATCH 6/x] arm: Add vstN_lane_bf16 + vstNq_lane_bf16 intrisics

[Andrea Corallo via Gcc-patches]

Hi all,

last patch for this the serie adding vst2_lane_bf16, vst2q_lane_bf16,
vst3_lane_bf16, vst3q_lane_bf16, vst4_lane_bf16, vst4q_lane_bf16
related neon intrinsics.

Please see refer to:
ACLE 
ISA  

Regtested and bootstrapped.

Thanks!

  Andrea

>From 47b1272f7d14d91f4e327501c1e1bad6ceeb4525 Mon Sep 17 00:00:00 2001
From: Andrea Corallo 
Date: Thu, 29 Oct 2020 11:20:23 +0100
Subject: [PATCH 6/6] arm: Add vstN_lane_bf16 + vstNq_lane_bf16 intrisics

gcc/ChangeLog

2020-10-29  Andrea Corallo  

* config/arm/arm_neon.h (vst2_lane_bf16, vst2q_lane_bf16)
(vst3_lane_bf16, vst3q_lane_bf16, vst4_lane_bf16)
(vst4q_lane_bf16): New intrinsics.
* config/arm/arm_neon_builtins.def: Touch it for:
__builtin_neon_vst2_lanev4bf, __builtin_neon_vst2_lanev8bf,
__builtin_neon_vst3_lanev4bf, __builtin_neon_vst3_lanev8bf,
__builtin_neon_vst4_lanev4bf,__builtin_neon_vst4_lanev8bf.

gcc/testsuite/ChangeLog

2020-10-29  Andrea Corallo  

* gcc.target/aarch64/advsimd-intrinsics/vst2_lane_bf16_indices_1.c:
Run it also for arm-*-*.
* gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_bf16_indices_1.c:
Likewise.
* gcc.target/aarch64/advsimd-intrinsics/vst3_lane_bf16_indices_1.c:
Likewise.
* gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_bf16_indices_1.c:
Likewise.
* gcc.target/aarch64/advsimd-intrinsics/vst4_lane_bf16_indices_1.c:
Likewise.
* gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_bf16_indices_1.c:
Likewise.
* gcc.target/arm/simd/vstn_lane_bf16_1.c: New test.
---
 gcc/config/arm/arm_neon.h | 48 
 gcc/config/arm/arm_neon_builtins.def  | 12 +--
 .../vst2_lane_bf16_indices_1.c|  2 +-
 .../vst2q_lane_bf16_indices_1.c   |  2 +-
 .../vst3_lane_bf16_indices_1.c|  2 +-
 .../vst3q_lane_bf16_indices_1.c   |  2 +-
 .../vst4_lane_bf16_indices_1.c|  2 +-
 .../vst4q_lane_bf16_indices_1.c   |  2 +-
 .../gcc.target/arm/simd/vstn_lane_bf16_1.c| 73 +++
 9 files changed, 133 insertions(+), 12 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/arm/simd/vstn_lane_bf16_1.c

diff --git a/gcc/config/arm/arm_neon.h b/gcc/config/arm/arm_neon.h
index 4fee128ce8d..9569e1a4c9c 100644
--- a/gcc/config/arm/arm_neon.h
+++ b/gcc/config/arm/arm_neon.h
@@ -19783,6 +19783,54 @@ vld4q_lane_bf16 (const bfloat16_t * __a, 
bfloat16x8x4_t __b, const int __c)
   return __rv.__i;
 }
 
+__extension__ extern __inline void
+__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+vst2_lane_bf16 (bfloat16_t * __a, bfloat16x4x2_t __b, const int __c)
+{
+  union { bfloat16x4x2_t __i; __builtin_neon_ti __o; } __bu = { __b };
+  __builtin_neon_vst2_lanev4bf (__a, __bu.__o, __c);
+}
+
+__extension__ extern __inline void
+__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+vst2q_lane_bf16 (bfloat16_t * __a, bfloat16x8x2_t __b, const int __c)
+{
+  union { bfloat16x8x2_t __i; __builtin_neon_oi __o; } __bu = { __b };
+  __builtin_neon_vst2_lanev8bf (__a, __bu.__o, __c);
+}
+
+__extension__ extern __inline void
+__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+vst3_lane_bf16 (bfloat16_t * __a, bfloat16x4x3_t __b, const int __c)
+{
+  union { bfloat16x4x3_t __i; __builtin_neon_ei __o; } __bu = { __b };
+  __builtin_neon_vst3_lanev4bf (__a, __bu.__o, __c);
+}
+
+__extension__ extern __inline void
+__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+vst3q_lane_bf16 (bfloat16_t * __a, bfloat16x8x3_t __b, const int __c)
+{
+  union { bfloat16x8x3_t __i; __builtin_neon_ci __o; } __bu = { __b };
+  __builtin_neon_vst3_lanev8bf (__a, __bu.__o, __c);
+}
+
+__extension__ extern __inline void
+__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+vst4_lane_bf16 (bfloat16_t * __a, bfloat16x4x4_t __b, const int __c)
+{
+  union { bfloat16x4x4_t __i; __builtin_neon_oi __o; } __bu = { __b };
+  __builtin_neon_vst4_lanev4bf (__a, __bu.__o, __c);
+}
+
+__extension__ extern __inline void
+__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+vst4q_lane_bf16 (bfloat16_t * __a, bfloat16x8x4_t __b, const int __c)
+{
+  union { bfloat16x8x4_t __i; __builtin_neon_xi __o; } __bu = { __b };
+  __builtin_neon_vst4_lanev8bf (__a, __bu.__o, __c);
+}
+
 #pragma GCC pop_options
 
 #ifdef __cplusplus
diff --git a/gcc/config/arm/arm_neon_builtins.def 
b/gcc/config/arm/arm_neon_builtins.def
index 1cb8c8c23b4..0ff0494b5da 100644
--- a/gcc/config/arm/arm_neon_builtins.def
+++ b/gcc/config/arm/arm_neon_builtins.def
@@ -329,8 +329,8 @@ VAR11 (LOAD1LANE, vld2_lane,
 VAR8 (LOAD1, vld2_dup, v8qi, v4hi, v4hf, v2si, v2sf, di, v4bf, v8bf)
 VAR13 (STORE1, vst2,
v8qi, v4hi, v4hf, v4bf, v2si, v2sf, di, v16qi, v8hi, v

Re: [PATCH 4/x] arm: Add vst1_bf16 + vst1q_bf16 intrinsics

[Andrea Corallo via Gcc-patches]

Kyrylo Tkachov  writes:
[...]
> I see this patch also has the hunk:
> diff --git a/gcc/config/arm/arm-builtins.c b/gcc/config/arm/arm-builtins.c
> index 33e8015b140..6dc5df93216 100644
> --- a/gcc/config/arm/arm-builtins.c
> +++ b/gcc/config/arm/arm-builtins.c
> @@ -946,6 +946,9 @@ typedef struct {
>  #define VAR13(T, N, A, B, C, D, E, F, G, H, I, J, K, L, M) \
>VAR12 (T, N, A, B, C, D, E, F, G, H, I, J, K, L) \
>VAR1 (T, N, M)
> +#define VAR14(T, N, A, B, C, D, E, F, G, H, I, J, K, L, M, O) \
> +  VAR13 (T, N, A, B, C, D, E, F, G, H, I, J, K, L, M) \
> +  VAR1 (T, N, O)
>  
>  /* The builtin data can be found in arm_neon_builtins.def, 
> arm_vfp_builtins.def
> and arm_acle_builtins.def.  The entries in arm_neon_builtins.def require
>
> That is a duplicate from a previous patch in the series and doesn't appear in 
> the ChangeLog here.
> I think it's in here by mistake?
> Otherwise ok.
> Thanks,
> Kyrill

Hi Kyrill,

thanks for reviewing this.

Unless I'm wrong I see this hunk present in 3/x but not in 4/x.

  Andrea

Re: [PATCH 6/x] arm: Add vstN_lane_bf16 + vstNq_lane_bf16 intrisics

[Andrea Corallo via Gcc-patches]

Kyrylo Tkachov  writes:

>> -Original Message-
>> From: Andrea Corallo 
>> Sent: 02 November 2020 09:04
>> To: gcc-patches@gcc.gnu.org
>> Cc: Kyrylo Tkachov ; Richard Earnshaw
>> ; nd 
>> Subject: [PATCH 6/x] arm: Add vstN_lane_bf16 + vstNq_lane_bf16 intrisics
>> 
>> Hi all,
>> 
>> last patch for this the serie adding vst2_lane_bf16, vst2q_lane_bf16,
>> vst3_lane_bf16, vst3q_lane_bf16, vst4_lane_bf16, vst4q_lane_bf16
>> related neon intrinsics.
>> 
>> Please see refer to:
>> ACLE 
>> ISA  
>> 
>> Regtested and bootstrapped.
>> 
>
> Ok.
> Thanks,
> Kyrill

Hi Kyrill,

I've installed into master this serie (implementing your suggestion for
3/x).

ed62f3668b5 arm: Add vstN_lane_bf16 + vstNq_lane_bf16 intrisics
1528f34341b arm: Add vldN_lane_bf16 + vldNq_lane_bf16 intrisics
6170a793b7f arm: Add vst1_bf16 + vst1q_bf16 intrinsics
890076673d4 arm: Add vld1_bf16 + vld1q_bf16 intrinsics
d65303b6994 arm: Add vst1_lane_bf16 + vstq_lane_bf16 intrinsics

I'll follow up for the backports if you are okay with that.

Thanks

  Andrea

Re: [PATCH V2] aarch64: Add vcopy(q)__lane(q)_bf16 intrinsics

[Andrea Corallo via Gcc-patches]

Andrea Corallo via Gcc-patches  writes:

> Richard Sandiford  writes:

[...]

>> OK with that change if it works (for trunk and for whichever
>> branches need it).
>>
>> Thanks,
>> Richard
>
> Hi Richard,
>
> I've applied the suggestions and have now installed it into master as
> 8eb8dcac6ed.  I'll follow up with the backports.
>
> Thanks!
>
>   Andrea


Hi all,

applied to releases/gcc-10 as b768eef488a.

  Andrea

Re: [PATCH V3] aarch64: Add vstN_lane_bf16 + vstNq_lane_bf16 intrinsics

[Andrea Corallo via Gcc-patches]

Andrea Corallo via Gcc-patches  writes:

> Andrea Corallo via Gcc-patches  writes:
> [...]
>
>> Hi all,
>>
>> third version of this patch following the suggestions got for its sister
>> patch <https://gcc.gnu.org/pipermail/gcc-patches/2020-October/557308.html>
>>
>> Regtested and bootstrapped.
>>
>> Okay for trunk and 10?
>>
>> Thanks!
>>
>>   Andrea
>
> Installed into master as 292c812a27c (okay given here
> <https://gcc.gnu.org/pipermail/gcc-patches/2020-October/557310.html>)
>
> Will follow-up for the backport.
>
>   Andrea


Hi all,

installed into releases/gcc-10 as 73be6bd1433.

  Andrea

Re: [PATCH V4] aarch64: Add bfloat16 vldN_lane_bf16 + vldNq_lane_bf16 intrisics

[Andrea Corallo via Gcc-patches]

Andrea Corallo via Gcc-patches  writes:

> Richard Sandiford  writes:
> [...]
>> OK for both.  Thanks for doing this.
>>
>> Richard
>
> Welcome, installed into master as 44e570d9fb0.
>
> Will follow-up for the backport.
>
> Thanks!
>
>   Andrea


Hi all,

installed into releases/gcc-10 as aa97379d802.

Bests

  Andrea

Re: [PATCH 1/x] arm: Add vld1_lane_bf16 + vldq_lane_bf16 intrinsics

[Andrea Corallo via Gcc-patches]

Christophe Lyon  writes:

> On Wed, 4 Nov 2020 at 14:29, Christophe Lyon  
> wrote:
>>
>> On Tue, 3 Nov 2020 at 11:27, Kyrylo Tkachov via Gcc-patches
>>  wrote:
>> >
>> > Hi Andrea,
>> >
>> > > -Original Message-
>> > > From: Andrea Corallo 
>> > > Sent: 26 October 2020 15:59
>> > > To: gcc-patches@gcc.gnu.org
>> > > Cc: Kyrylo Tkachov ; Richard Earnshaw
>> > > ; nd 
>> > > Subject: [PATCH 1/x] arm: Add vld1_lane_bf16 + vldq_lane_bf16 intrinsics
>> > >
>> > > Hi all,
>> > >
>> > > I'd like to submit the following patch implementing the bfloat16_t
>> > > neon related load intrinsics: vld1_lane_bf16, vld1q_lane_bf16.
>> > >
>> > > Please see refer to:
>> > > ACLE 
>> > > ISA  
>> > >
>> > > Regtested and bootstrapped.
>> > >
>> > > Okay for trunk?
>> >
>>
>> I think you need to add -mfloat-abi=hard to the dg-additional-options
>> otherwise vld1_lane_bf16_1.c
>> fails on targets with a soft float-abi default (eg arm-linux-gnueabi).
>>
>> See bf16_vldn_1.c.
>
> Actually that's not sufficient because in turn we get:
> /sysroot-arm-none-linux-gnueabi/usr/include/gnu/stubs.h:10:11: fatal
> error: gnu/stubs-hard.h: No such file or directory
>
> So you should check that -mfloat-abi=hard is supported.
>
> Ditto for the vst tests.
>

Hi Christophe,

thanks for catching this, I'll prepare a patch.

  Andrea

Re: [PATCH 1/x] arm: Add vld1_lane_bf16 + vldq_lane_bf16 intrinsics

[Andrea Corallo via Gcc-patches]

Christophe Lyon  writes:

> On Tue, 3 Nov 2020 at 11:27, Kyrylo Tkachov via Gcc-patches
>  wrote:
>>
>> Hi Andrea,
>>
>> > -Original Message-
>> > From: Andrea Corallo 
>> > Sent: 26 October 2020 15:59
>> > To: gcc-patches@gcc.gnu.org
>> > Cc: Kyrylo Tkachov ; Richard Earnshaw
>> > ; nd 
>> > Subject: [PATCH 1/x] arm: Add vld1_lane_bf16 + vldq_lane_bf16 intrinsics
>> >
>> > Hi all,
>> >
>> > I'd like to submit the following patch implementing the bfloat16_t
>> > neon related load intrinsics: vld1_lane_bf16, vld1q_lane_bf16.
>> >
>> > Please see refer to:
>> > ACLE 
>> > ISA  
>> >
>> > Regtested and bootstrapped.
>> >
>> > Okay for trunk?
>>
>
> I think you need to add -mfloat-abi=hard to the dg-additional-options
> otherwise vld1_lane_bf16_1.c
> fails on targets with a soft float-abi default (eg arm-linux-gnueabi).
>
> See bf16_vldn_1.c.
>
> BTW, why did you use a different naming scheme for the tests?
> (bf16_vldn_1.c vs vld1_lane_bf16_1.c)

Nothing special, it made more sense to me to use directly the name of
the intrinsic as it include already the bf16 information.  I believe we
have both schemas in the aarch64 & arm backends.  I've no problem with
renaming the tests if we feel is important.

  Andrea

[PATCH] arm: [testcase] Better narrow some bfloat16 testcase

[Andrea Corallo via Gcc-patches]

Christophe Lyon  writes:

[...]

>> I think you need to add -mfloat-abi=hard to the dg-additional-options
>> otherwise vld1_lane_bf16_1.c
>> fails on targets with a soft float-abi default (eg arm-linux-gnueabi).
>>
>> See bf16_vldn_1.c.
>
> Actually that's not sufficient because in turn we get:
> /sysroot-arm-none-linux-gnueabi/usr/include/gnu/stubs.h:10:11: fatal
> error: gnu/stubs-hard.h: No such file or directory
>
> So you should check that -mfloat-abi=hard is supported.
>
> Ditto for the vst tests.

Hi Christophe,

this patch should implement your suggestions.

On my arm-none-linux-gnueabi setup the tests were already skipped
as unsupported so if you could test and confirm this fixes the 
issue you see would be great.

Thanks!

  Andrea

>From d27e3f39fa2f348a4b8aa929bbb65808a09f1211 Mon Sep 17 00:00:00 2001
From: Andrea Corallo 
Date: Thu, 5 Nov 2020 08:57:03 +
Subject: [PATCH] arm: [testcase] Better narrow some bfloat16 testcase

2020-11-05  Andrea Corallo  

* gcc.target/arm/simd/vld1_lane_bf16_1.c: Add -mfloat-abi=hard
flag.
* gcc.target/arm/simd/vld1_lane_bf16_indices_1.c: Likewise.
* gcc.target/arm/simd/vld1q_lane_bf16_indices_1.c: Likewise.
* gcc.target/arm/simd/vst1_lane_bf16_1.c: Likewise.
* gcc.target/arm/simd/vst1_lane_bf16_indices_1.c: Likewise.
* gcc.target/arm/simd/vstq1_lane_bf16_indices_1.c: Likewise.
* lib/target-supports.exp
(check_effective_target_arm_v8_2a_bf16_neon_ok_nocache): Require
target to support -mfloat-abi=hard.
---
 gcc/testsuite/gcc.target/arm/simd/vld1_lane_bf16_1.c  | 2 +-
 gcc/testsuite/gcc.target/arm/simd/vld1_lane_bf16_indices_1.c  | 1 +
 gcc/testsuite/gcc.target/arm/simd/vld1q_lane_bf16_indices_1.c | 1 +
 gcc/testsuite/gcc.target/arm/simd/vst1_lane_bf16_1.c  | 2 +-
 gcc/testsuite/gcc.target/arm/simd/vst1_lane_bf16_indices_1.c  | 1 +
 gcc/testsuite/gcc.target/arm/simd/vstq1_lane_bf16_indices_1.c | 1 +
 gcc/testsuite/lib/target-supports.exp | 4 
 7 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/gcc/testsuite/gcc.target/arm/simd/vld1_lane_bf16_1.c 
b/gcc/testsuite/gcc.target/arm/simd/vld1_lane_bf16_1.c
index fa4e45b7217..64e1f394676 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vld1_lane_bf16_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vld1_lane_bf16_1.c
@@ -1,7 +1,7 @@
 /* { dg-do assemble } */
 /* { dg-require-effective-target arm_v8_2a_bf16_neon_ok } */
 /* { dg-add-options arm_v8_2a_bf16_neon } */
-/* { dg-additional-options "-O3 --save-temps" } */
+/* { dg-additional-options "-O3 --save-temps -mfloat-abi=hard" } */
 
 #include "arm_neon.h"
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vld1_lane_bf16_indices_1.c 
b/gcc/testsuite/gcc.target/arm/simd/vld1_lane_bf16_indices_1.c
index c83eb53234d..9e56c25974e 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vld1_lane_bf16_indices_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vld1_lane_bf16_indices_1.c
@@ -1,6 +1,7 @@
 /* { dg-do assemble } */
 /* { dg-require-effective-target arm_v8_2a_bf16_neon_ok } */
 /* { dg-add-options arm_v8_2a_bf16_neon } */
+/* { dg-additional-options "-mfloat-abi=hard" } */
 
 #include "arm_neon.h"
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vld1q_lane_bf16_indices_1.c 
b/gcc/testsuite/gcc.target/arm/simd/vld1q_lane_bf16_indices_1.c
index 8e21e61c9c0..c75d24db11b 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vld1q_lane_bf16_indices_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vld1q_lane_bf16_indices_1.c
@@ -1,6 +1,7 @@
 /* { dg-do assemble } */
 /* { dg-require-effective-target arm_v8_2a_bf16_neon_ok } */
 /* { dg-add-options arm_v8_2a_bf16_neon } */
+/* { dg-additional-options "-mfloat-abi=hard" } */
 
 #include "arm_neon.h"
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vst1_lane_bf16_1.c 
b/gcc/testsuite/gcc.target/arm/simd/vst1_lane_bf16_1.c
index e018ec6592f..77e8a3bd5eb 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vst1_lane_bf16_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vst1_lane_bf16_1.c
@@ -1,7 +1,7 @@
 /* { dg-do assemble } */
 /* { dg-require-effective-target arm_v8_2a_bf16_neon_ok } */
 /* { dg-add-options arm_v8_2a_bf16_neon } */
-/* { dg-additional-options "-O3 --save-temps" } */
+/* { dg-additional-options "-O3 --save-temps -mfloat-abi=hard" } */
 
 #include "arm_neon.h"
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vst1_lane_bf16_indices_1.c 
b/gcc/testsuite/gcc.target/arm/simd/vst1_lane_bf16_indices_1.c
index 39870dc054c..ba4017afd0c 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vst1_lane_bf16_indices_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vst1_lane_bf16_indices_1.c
@@ -1,6 +1,7 @@
 /* { dg-do assemble } */
 /* { dg-require-effective-target arm_v8_2a_bf16_neon_ok } */
 /* { dg-add-options arm_v8_2a_bf16_neon } */
+/* { dg-additional-options "-mfloat-abi=hard" } */
 
 #include "arm_neon.h"
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vstq1_lane_bf16_indices_1.c 
b/gcc/testsuite/gcc.target/arm/simd/vstq1_lane_bf16

Re: [PATCH] arm: [testcase] Better narrow some bfloat16 testcase

[Andrea Corallo via Gcc-patches]

Christophe Lyon  writes:

> On Thu, 5 Nov 2020 at 12:11, Andrea Corallo  wrote:
>>
>> Christophe Lyon  writes:
>>
>> [...]
>>
>> >> I think you need to add -mfloat-abi=hard to the dg-additional-options
>> >> otherwise vld1_lane_bf16_1.c
>> >> fails on targets with a soft float-abi default (eg arm-linux-gnueabi).
>> >>
>> >> See bf16_vldn_1.c.
>> >
>> > Actually that's not sufficient because in turn we get:
>> > /sysroot-arm-none-linux-gnueabi/usr/include/gnu/stubs.h:10:11: fatal
>> > error: gnu/stubs-hard.h: No such file or directory
>> >
>> > So you should check that -mfloat-abi=hard is supported.
>> >
>> > Ditto for the vst tests.
>>
>> Hi Christophe,
>>
>> this patch should implement your suggestions.
>>
>> On my arm-none-linux-gnueabi setup the tests were already skipped
>> as unsupported so if you could test and confirm this fixes the
>> issue you see would be great.
>
> Do you know why they are unsupported in your setup?

We probably have a different GCC configuration.  Could you share how
it's configured your?

>> diff --git a/gcc/testsuite/lib/target-supports.exp 
>> b/gcc/testsuite/lib/target-supports.exp
>> index 15f0649f8ae..2ab7e39756d 100644
>> --- a/gcc/testsuite/lib/target-supports.exp
>> +++ b/gcc/testsuite/lib/target-supports.exp
>> @@ -5213,6 +5213,10 @@ proc 
>> check_effective_target_arm_v8_2a_bf16_neon_ok_nocache { } {
>>  return 0;
>>  }
>>
>> +if { ! [check_effective_target_arm_hard_ok] } {
>> + return 0;
>> +}
>> +
>> foreach flags {"" "-mfloat-abi=hard -mfpu=neon-fp-armv8" 
>> "-mfloat-abi=softfp -mfpu=neon-fp-armv8" } {
>> if { [check_no_compiler_messages_nocache arm_v8_2a_bf16_neon_ok 
>> object {
>> #include 
>
> This seems strange since you would now exit early if
> check_effective_target_arm_hard_ok is false, so you'll never need the
> -mfloat-abi=softfp version of the flags.

So IIUC your suggestion would be to test with higher priority softfp and
in case we decide to go for hardfp make sure
check_effective_target_arm_hard_ok is satisfied.  Am I correct?

> BTW in general, I think softfp is tried before hard in the other
> similar effective targets, any reason the order is different here?

No idea.

Thanks

  Andrea

[PATCH V2] arm: [testcase] Better narrow some bfloat16 testcase

[Andrea Corallo via Gcc-patches]

Christophe Lyon  writes:

> On Thu, 5 Nov 2020 at 15:30, Andrea Corallo  wrote:
>>
>> Christophe Lyon  writes:
>>
>> > On Thu, 5 Nov 2020 at 12:11, Andrea Corallo  wrote:
>> >>
>> >> Christophe Lyon  writes:
>> >>
>> >> [...]
>> >>
>> >> >> I think you need to add -mfloat-abi=hard to the dg-additional-options
>> >> >> otherwise vld1_lane_bf16_1.c
>> >> >> fails on targets with a soft float-abi default (eg arm-linux-gnueabi).
>> >> >>
>> >> >> See bf16_vldn_1.c.
>> >> >
>> >> > Actually that's not sufficient because in turn we get:
>> >> > /sysroot-arm-none-linux-gnueabi/usr/include/gnu/stubs.h:10:11: fatal
>> >> > error: gnu/stubs-hard.h: No such file or directory
>> >> >
>> >> > So you should check that -mfloat-abi=hard is supported.
>> >> >
>> >> > Ditto for the vst tests.
>> >>
>> >> Hi Christophe,
>> >>
>> >> this patch should implement your suggestions.
>> >>
>> >> On my arm-none-linux-gnueabi setup the tests were already skipped
>> >> as unsupported so if you could test and confirm this fixes the
>> >> issue you see would be great.
>> >
>> > Do you know why they are unsupported in your setup?
>>
>> We probably have a different GCC configuration.  Could you share how
>> it's configured your?
>>
> Sure, for instance:
> --target=arm-none-linux-gnueabi --with-float=soft --with-mode=arm
> --with-cpu=cortex-a9

Thanks, I see now what was going on, my gas has no bf16 support so the
test was marked as unsupported.  Dunno why I assumed
check_no_compiler_messages_nocache wasn't testing the whole compilation
process.

>> >> diff --git a/gcc/testsuite/lib/target-supports.exp 
>> >> b/gcc/testsuite/lib/target-supports.exp
>> >> index 15f0649f8ae..2ab7e39756d 100644
>> >> --- a/gcc/testsuite/lib/target-supports.exp
>> >> +++ b/gcc/testsuite/lib/target-supports.exp
>> >> @@ -5213,6 +5213,10 @@ proc 
>> >> check_effective_target_arm_v8_2a_bf16_neon_ok_nocache { } {
>> >>  return 0;
>> >>  }
>> >>
>> >> +if { ! [check_effective_target_arm_hard_ok] } {
>> >> + return 0;
>> >> +}
>> >> +
>> >> foreach flags {"" "-mfloat-abi=hard -mfpu=neon-fp-armv8" 
>> >> "-mfloat-abi=softfp -mfpu=neon-fp-armv8" } {
>> >> if { [check_no_compiler_messages_nocache arm_v8_2a_bf16_neon_ok 
>> >> object {
>> >> #include 
>> >
>> > This seems strange since you would now exit early if
>> > check_effective_target_arm_hard_ok is false, so you'll never need the
>> > -mfloat-abi=softfp version of the flags.
>>
>> So IIUC your suggestion would be to test with higher priority softfp and
>> in case we decide to go for hardfp make sure
>> check_effective_target_arm_hard_ok is satisfied.  Am I correct?
>>
> ISTM that other tests that need hardfp check if it's supported in the
> test, not in other effective targets.
>
> For instance mve/intrinsics/mve_fpu1.c
>
> I can see that quite a few tests that use -mfloat-abi=hard do not
> check whether it's supported. Those I checked do not include
> arm_neon.h and thus do not end up with the gnu/stubs-hard.h error
> above.

I see thanks for the explaination.  The attached should do the job.

  Andrea

>From 1fc3854d1cb48840d7b8db9fcf7b2997a25f35f4 Mon Sep 17 00:00:00 2001
From: Andrea Corallo 
Date: Thu, 5 Nov 2020 08:57:03 +
Subject: [PATCH] arm: [testcase] Better narrow some bfloat16 testcase

2020-11-05  Andrea Corallo  

* gcc.target/arm/simd/vld1_lane_bf16_1.c: Require target to
support and add -mfloat-abi=hard flag.
* gcc.target/arm/simd/vld1_lane_bf16_indices_1.c: Likewise.
* gcc.target/arm/simd/vld1q_lane_bf16_indices_1.c: Likewise.
* gcc.target/arm/simd/vst1_lane_bf16_1.c: Likewise.
* gcc.target/arm/simd/vst1_lane_bf16_indices_1.c: Likewise.
* gcc.target/arm/simd/vstq1_lane_bf16_indices_1.c: Likewise.
---
 gcc/testsuite/gcc.target/arm/simd/vld1_lane_bf16_1.c  | 3 ++-
 gcc/testsuite/gcc.target/arm/simd/vld1_lane_bf16_indices_1.c  | 2 ++
 gcc/testsuite/gcc.target/arm/simd/vld1q_lane_bf16_indices_1.c | 2 ++
 gcc/testsuite/gcc.target/arm/simd/vst1_lane_bf16_1.c  | 3 ++-
 gcc/testsuite/gcc.target/arm/simd/vst1_lane_bf16_indices_1.c  | 2 ++
 gcc/testsuite/gcc.target/arm/simd/vstq1_lane_bf16_indices_1.c | 2 ++
 6 files changed, 12 insertions(+), 2 deletions(-)

diff --git a/gcc/testsuite/gcc.target/arm/simd/vld1_lane_bf16_1.c 
b/gcc/testsuite/gcc.target/arm/simd/vld1_lane_bf16_1.c
index fa4e45b7217..94fb38f32b8 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vld1_lane_bf16_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vld1_lane_bf16_1.c
@@ -1,7 +1,8 @@
 /* { dg-do assemble } */
 /* { dg-require-effective-target arm_v8_2a_bf16_neon_ok } */
+/* { dg-require-effective-target arm_hard_ok } */
 /* { dg-add-options arm_v8_2a_bf16_neon } */
-/* { dg-additional-options "-O3 --save-temps" } */
+/* { dg-additional-options "-O3 --save-temps -mfloat-abi=hard" } */
 
 #include "arm_neon.h"
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vld1_lane_bf16_indices_1.c 
b/gcc/testsuite/gcc.target/arm/simd/vld1_

[PATCH] aarch64: Do not alter force_reg returned register expanding fcmla

[Andrea Corallo via Gcc-patches]

Hi all,

this patch is to fix a force_reg returned rtx potentially modified in
`aarch64_general_expand_builtin`.

Bootstrapped and reg-tested on aarch64-none-linux-gnu.

Okay for trunk?

Thanks

  Andrea

2020-11-06  Andrea Corallo  

* config/aarch64/aarch64-builtins.c
(aarch64_expand_fcmla_builtin): Do not alter force_reg returned
register.

>From 203d9688cee6298a10f14a79e6ca58b2fadeafc9 Mon Sep 17 00:00:00 2001
From: Andrea Corallo 
Date: Fri, 6 Nov 2020 16:17:32 +
Subject: [PATCH] aarch64: Do not alter force_reg returned register expanding
 fcmla

2020-11-06  Andrea Corallo  

* config/aarch64/aarch64-builtins.c
(aarch64_expand_fcmla_builtin): Do not alter force_reg returned
register.
---
 gcc/config/aarch64/aarch64-builtins.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/gcc/config/aarch64/aarch64-builtins.c 
b/gcc/config/aarch64/aarch64-builtins.c
index 9d5e8c75c55..3a63107d6ff 100644
--- a/gcc/config/aarch64/aarch64-builtins.c
+++ b/gcc/config/aarch64/aarch64-builtins.c
@@ -1856,10 +1856,10 @@ aarch64_expand_fcmla_builtin (tree exp, rtx target, int 
fcode)
  only need to know the order in a V2mode.  */
   lane_idx = aarch64_endian_lane_rtx (V2DImode, lane);
 
-  if (!target)
+  if (!target
+  || !REG_P (target)
+  || GET_MODE (target) != d->mode)
 target = gen_reg_rtx (d->mode);
-  else
-target = force_reg (d->mode, target);
 
   rtx pat = NULL_RTX;
 
-- 
2.20.1

Re: [PATCH V2] arm: [testcase] Better narrow some bfloat16 testcase

[Andrea Corallo via Gcc-patches]

Christophe Lyon  writes:
[...]
> Yes, it works for me, thanks.

Super, happy to push it when I get the okay.

  Andrea

Re: [PATCH V2] arm: [testcase] Better narrow some bfloat16 testcase

[Andrea Corallo via Gcc-patches]

Kyrylo Tkachov  writes:

>> -Original Message-
>> From: Andrea Corallo 
>> Sent: 09 November 2020 10:05
>> To: Christophe Lyon 
>> Cc: Kyrylo Tkachov ; gcc-patches@gcc.gnu.org;
>> Richard Earnshaw ; nd 
>> Subject: Re: [PATCH V2] arm: [testcase] Better narrow some bfloat16
>> testcase
>> 
>> Christophe Lyon  writes:
>> [...]
>> > Yes, it works for me, thanks.
>> 
>> Super, happy to push it when I get the okay.
>
> It's okay.
> Thanks,
> Kyrill

Installed into master as 2d4fa1f79c7.

Thanks

  Andrea