Re: [PATCH 0/2] RISC-V: Add ldr/str instruction for T-HEAD.

[ALO via Gcc-patches]

Hi,
Ping.

— Jojo
在 2021年6月29日 +0800 PM4:11，Jojo R ，写道：
> T-HEAD extends some customized ISAs for Cores.
> The patches support ldr/str insns, it likes arm's LDR insn, the
> memory model is a base register indexed by (optionally scaled) register.

Re: [PATCH 0/2] RISC-V: Add ldr/str instruction for T-HEAD.

[ALO via Gcc-patches]

Hi,

Ping.

@Jim @kito

— Jojo
在 2021年7月9日 +0800 AM9:30，ALO ，写道：
> Hi,
>   Ping.
>
> — Jojo
> 在 2021年6月29日 +0800 PM4:11，Jojo R ，写道：
> > T-HEAD extends some customized ISAs for Cores.
> > The patches support ldr/str insns, it likes arm's LDR insn, the
> > memory model is a base register indexed by (optionally scaled) register.