Re: [PATCH] RISC-V: Allow all const_vec_duplicates as constants.

[Kito Cheng via Gcc-patches]

Lgtm

Robin Dapp  於 2023年5月26日 週五 22:10 寫道：

> Hi,
>
> as we can always broadcast an integer constant to a vector register
> allow them in riscv_const_insns.  We need as many instructions as
> it takes to generate the constant and one vmv.vx.
>
> Regards
>  Robin
>
> gcc/ChangeLog:
>
> * config/riscv/riscv.cc (riscv_const_insns): Allow
> const_vec_duplicates.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv32.c: Add vmv.v.x
> tests.
> * gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv64.c: Dito.
> * gcc.target/riscv/rvv/autovec/vmv-imm-run.c: Dito.
> * gcc.target/riscv/rvv/autovec/vmv-imm-rv32.c: Dito.
> * gcc.target/riscv/rvv/autovec/vmv-imm-rv64.c: Dito.
> * gcc.target/riscv/rvv/autovec/vmv-imm-template.h: Dito.
> ---
>  gcc/config/riscv/riscv.cc | 22 --
>  .../riscv/rvv/autovec/vmv-imm-fixed-rv32.c|  3 +-
>  .../riscv/rvv/autovec/vmv-imm-fixed-rv64.c|  3 +-
>  .../riscv/rvv/autovec/vmv-imm-run.c   |  8 ++
>  .../riscv/rvv/autovec/vmv-imm-rv32.c  |  3 +-
>  .../riscv/rvv/autovec/vmv-imm-rv64.c  |  3 +-
>  .../riscv/rvv/autovec/vmv-imm-template.h  | 74 ++-
>  7 files changed, 73 insertions(+), 43 deletions(-)
>
> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> index c2acab08b89..5e0b515fe7a 100644
> --- a/gcc/config/riscv/riscv.cc
> +++ b/gcc/config/riscv/riscv.cc
> @@ -1297,12 +1297,22 @@ riscv_const_insns (rtx x)
>   }
>   }
>
> -   /* Constants from -16 to 15 can be loaded with vmv.v.i.
> -  The Wc0, Wc1 constraints are already covered by the
> -  vi constraint so we do not need to check them here
> -  separately.  */
> -   if (satisfies_constraint_vi (x))
> - return 1;
> +   rtx elt;
> +   if (const_vec_duplicate_p (x, &elt))
> + {
> +   /* Constants from -16 to 15 can be loaded with vmv.v.i.
> +  The Wc0, Wc1 constraints are already covered by the
> +  vi constraint so we do not need to check them here
> +  separately.  */
> +   if (satisfies_constraint_vi (x))
> + return 1;
> +
> +   /* A const duplicate vector can always be broadcast from
> +  a general-purpose register.  This means we need as many
> +  insns as it takes to load the constant into the GPR
> +  and one vmv.v.x.  */
> +   return 1 + riscv_integer_cost (INTVAL (elt));
> + }
>
> /* TODO: We may support more const vector in the future.  */
> return x == CONST0_RTX (GET_MODE (x)) ? 1 : 0;
> diff --git
> a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv32.c
> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv32.c
> index 631ea3bf268..e8d017f7339 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv32.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv32.c
> @@ -3,4 +3,5 @@
>
>  #include "vmv-imm-template.h"
>
> -/* { dg-final { scan-assembler-times "vmv.v.i" 32 } } */
> +/* { dg-final { scan-assembler-times {vmv.v.i} 32 } } */
> +/* { dg-final { scan-assembler-times {vmv.v.x} 8 } } */
> diff --git
> a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv64.c
> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv64.c
> index 7ded6cc18d2..f85ad4117d3 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv64.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv64.c
> @@ -3,4 +3,5 @@
>
>  #include "vmv-imm-template.h"
>
> -/* { dg-final { scan-assembler-times "vmv.v.i" 32 } } */
> +/* { dg-final { scan-assembler-times {vmv.v.i} 32 } } */
> +/* { dg-final { scan-assembler-times {vmv.v.x} 8 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-run.c
> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-run.c
> index 22b1958af81..79099a37bdd 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-run.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-run.c
> @@ -53,4 +53,12 @@ int main ()
>TEST_POS(uint64_t, 13)
>TEST_POS(uint64_t, 14)
>TEST_POS(uint64_t, 15)
> +  TEST_POS(uint32_t, 16)
> +  TEST_POS(uint32_t, 123)
> +  TEST_POS(uint32_t, 255)
> +  TEST_POS(uint32_t, 999)
> +  TEST_POS(uint32_t, 32701)
> +  TEST_POS(uint32_t, 65535)
> +  TEST_POS(uint32_t, 65536)
> +  TEST_POS(uint32_t, 923423)
>  }
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-rv32.c
> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-rv32.c
> index c419256cd45..6843bc6018d 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-rv32.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-rv32.c
> @@ -3,4 +3,5 @@
>
>  #include "vmv-imm-template.h"
>
> -/* { dg-final { scan-assembler-times "vmv.v.i" 32 } } */
> +/* { dg-final { scan-assembler-times {vmv.v.i} 32 } } */
> +/* {

Re: [PATCH V2] RISC-V: Fix zero-scratch-regs-3.c fail

[Kito Cheng via Gcc-patches]

LGTM

 於 2023年5月26日 週五 08:46 寫道：

> From: Juzhe-Zhong 
>
> gcc/ChangeLog:
>
> * config/riscv/riscv.cc (vector_zero_call_used_regs): Add explict
> VL and drop VL in ops.
>
> ---
>  gcc/config/riscv/riscv.cc | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> index 09fc9e5d95e..b16c60df6a7 100644
> --- a/gcc/config/riscv/riscv.cc
> +++ b/gcc/config/riscv/riscv.cc
> @@ -7396,9 +7396,9 @@ vector_zero_call_used_regs (HARD_REG_SET
> need_zeroed_hardregs)
>   emitted_vlmax_vsetvl = true;
> }
>
> - rtx ops[] = {target, CONST0_RTX (mode), vl};
> + rtx ops[] = {target, CONST0_RTX (mode)};
>   riscv_vector::emit_vlmax_insn (code_for_pred_mov (mode),
> -riscv_vector::RVV_UNOP, ops);
> +riscv_vector::RVV_UNOP, ops, vl);
>
>   SET_HARD_REG_BIT (zeroed_hardregs, regno);
> }
> --
> 2.36.3
>
>

[PATCH] Refactor wi::bswap as a function (instead of a method).

[Roger Sayle]

This patch implements Richard Sandiford's suggestion from
https://gcc.gnu.org/pipermail/gcc-patches/2023-May/618215.html
that wi::bswap (and a new wi::bitreverse) should be functions,
and ideally only accessors are member functions.  This patch
implements the first step, moving/refactoring wi::bswap.

This patch has been tested on x86_64-pc-linux-gnu with make bootstrap
and make -k check, both with and without --target_board=unix{-m32}
with no new failures.  Ok for mainline?


2023-05-28  Roger Sayle  

gcc/ChangeLog
* fold-const-call.cc (fold_const_call_ss) :
Update call to wi::bswap.
* simplify-rtx.cc (simplify_const_unary_operation) :
Update call to wi::bswap.
* tree-ssa-ccp.cc (evaluate_stmt) :
Update calls to wi::bswap.

* wide-int.cc (wide_int_storage::bswap): Remove/rename to...
(wi::bswap_large): New function, with revised API.
* wide-int.h (wi::bswap): New (template) function prototype.
(wide_int_storage::bswap): Remove method.
(sext_large, zext_large): Consistent indentation/line wrapping.
(bswap_large): Prototype helper function containing implementation.
(wi::bswap): New template wrapper around bswap_large.


Thanks,
Roger
--

diff --git a/gcc/fold-const-call.cc b/gcc/fold-const-call.cc
index 340cb66..663eae2 100644
--- a/gcc/fold-const-call.cc
+++ b/gcc/fold-const-call.cc
@@ -1060,7 +1060,8 @@ fold_const_call_ss (wide_int *result, combined_fn fn, 
const wide_int_ref &arg,
 case CFN_BUILT_IN_BSWAP32:
 case CFN_BUILT_IN_BSWAP64:
 case CFN_BUILT_IN_BSWAP128:
-  *result = wide_int::from (arg, precision, TYPE_SIGN (arg_type)).bswap ();
+  *result = wi::bswap (wide_int::from (arg, precision,
+  TYPE_SIGN (arg_type)));
   return true;
 
 default:
diff --git a/gcc/simplify-rtx.cc b/gcc/simplify-rtx.cc
index d4aeebc..d93d632 100644
--- a/gcc/simplify-rtx.cc
+++ b/gcc/simplify-rtx.cc
@@ -2111,7 +2111,7 @@ simplify_const_unary_operation (enum rtx_code code, 
machine_mode mode,
  break;
 
case BSWAP:
- result = wide_int (op0).bswap ();
+ result = wi::bswap (op0);
  break;
 
case TRUNCATE:
diff --git a/gcc/tree-ssa-ccp.cc b/gcc/tree-ssa-ccp.cc
index 6fb371c..26d5e44 100644
--- a/gcc/tree-ssa-ccp.cc
+++ b/gcc/tree-ssa-ccp.cc
@@ -2401,11 +2401,12 @@ evaluate_stmt (gimple *stmt)
  wide_int wval = wi::to_wide (val.value);
  val.value
= wide_int_to_tree (type,
-   wide_int::from (wval, prec,
-   UNSIGNED).bswap ());
+   wi::bswap (wide_int::from (wval, prec,
+  UNSIGNED)));
  val.mask
-   = widest_int::from (wide_int::from (val.mask, prec,
-   UNSIGNED).bswap (),
+   = widest_int::from (wi::bswap (wide_int::from (val.mask,
+  prec,
+  UNSIGNED)),
UNSIGNED);
  if (wi::sext (val.mask, prec) != -1)
break;
diff --git a/gcc/wide-int.cc b/gcc/wide-int.cc
index c0987aa..1e4c046 100644
--- a/gcc/wide-int.cc
+++ b/gcc/wide-int.cc
@@ -731,16 +731,13 @@ wi::set_bit_large (HOST_WIDE_INT *val, const 
HOST_WIDE_INT *xval,
 }
 }
 
-/* bswap THIS.  */
-wide_int
-wide_int_storage::bswap () const
+/* Byte swap the integer represented by XVAL and LEN into VAL.  Return
+   the number of blocks in VAL.  Both XVAL and VAL have PRECISION bits.  */
+unsigned int
+wi::bswap_large (HOST_WIDE_INT *val, const HOST_WIDE_INT *xval,
+unsigned int len, unsigned int precision)
 {
-  wide_int result = wide_int::create (precision);
   unsigned int i, s;
-  unsigned int len = BLOCKS_NEEDED (precision);
-  unsigned int xlen = get_len ();
-  const HOST_WIDE_INT *xval = get_val ();
-  HOST_WIDE_INT *val = result.write_val ();
 
   /* This is not a well defined operation if the precision is not a
  multiple of 8.  */
@@ -758,7 +755,7 @@ wide_int_storage::bswap () const
   unsigned int block = s / HOST_BITS_PER_WIDE_INT;
   unsigned int offset = s & (HOST_BITS_PER_WIDE_INT - 1);
 
-  byte = (safe_uhwi (xval, xlen, block) >> offset) & 0xff;
+  byte = (safe_uhwi (xval, len, block) >> offset) & 0xff;
 
   block = d / HOST_BITS_PER_WIDE_INT;
   offset = d & (HOST_BITS_PER_WIDE_INT - 1);
@@ -766,8 +763,7 @@ wide_int_storage::bswap () const
   val[block] |= byte << offset;
 }
 
-  result.set_len (canonize (val, len, precision));
-  return result;
+  return canonize (val, len, precision);
 }
 
 /* Fill VAL with a mask where the lower WIDTH bits are ones

Re: [PATCH] c++: mangle noexcept-expr [PR70790]

[Jason Merrill via Gcc-patches]

On 5/19/23 15:10, Patrick Palka wrote:

On Fri, 19 May 2023, Patrick Palka wrote:


This implements noexcept-expr mangling (and demangling) as per the
Itanium ABI.

Bootstrapped and regtested on x86_64-pc-linux-gnu, does this
look OK for trunk?

PR c++/70790

gcc/cp/ChangeLog:

* mangle.cc (write_expression): Handle NOEXCEPT_EXPR.

libiberty/ChangeLog:

* cp-demangle.c (cplus_demangle_operators): Add the noexcept
operator.


Oops, we should also make sure we print parens around the operand of
noexcept.  Otherwise we'd demangle the mangling of e.g.

   void f(A)

instead as

   void f(A)

Fixed in the following patch:

-- >8 --

Subject: [PATCH] c++: mangle noexcept-expr [PR70790]

This implements noexcept-expr mangling (and demangling) as per the
Itanium ABI.

Bootstrapped and regtested on x86_64-pc-linux-gnu, does this
look OK for trunk?


OK.  Incidentally, this paragraph should go before the scissors line 
since we don't want it to be part of the git commit comment.



PR c++/70790

gcc/cp/ChangeLog:

* mangle.cc (write_expression): Handle NOEXCEPT_EXPR.

libiberty/ChangeLog:

* cp-demangle.c (cplus_demangle_operators): Add the noexcept
operator.
(d_print_comp_inner) : Always
print parens around the operand of noexcept too.
* testsuite/demangle-expected: Test noexcept operator
demangling.

gcc/testsuite/ChangeLog:

* g++.dg/abi/mangle78.C: New test.
---
  gcc/cp/mangle.cc  |  5 +
  gcc/testsuite/g++.dg/abi/mangle78.C   | 14 ++
  libiberty/cp-demangle.c   |  5 +++--
  libiberty/testsuite/demangle-expected |  3 +++
  4 files changed, 25 insertions(+), 2 deletions(-)
  create mode 100644 gcc/testsuite/g++.dg/abi/mangle78.C

diff --git a/gcc/cp/mangle.cc b/gcc/cp/mangle.cc
index 826c5e76c1d..7dab4e62bc9 100644
--- a/gcc/cp/mangle.cc
+++ b/gcc/cp/mangle.cc
@@ -3402,6 +3402,11 @@ write_expression (tree expr)
else
write_string ("tr");
  }
+  else if (code == NOEXCEPT_EXPR)
+{
+  write_string ("nx");
+  write_expression (TREE_OPERAND (expr, 0));
+}
else if (code == CONSTRUCTOR)
  {
bool braced_init = BRACE_ENCLOSED_INITIALIZER_P (expr);
diff --git a/gcc/testsuite/g++.dg/abi/mangle78.C 
b/gcc/testsuite/g++.dg/abi/mangle78.C
new file mode 100644
index 000..63c4d779e9f
--- /dev/null
+++ b/gcc/testsuite/g++.dg/abi/mangle78.C
@@ -0,0 +1,14 @@
+// PR c++/70790
+// { dg-do compile { target c++11 } }
+
+template
+struct A { };
+
+template
+void f(A);
+
+int main() {
+  f({});
+}
+
+// { dg-final { scan-assembler "_Z1fIiEv1AIXnxtlT_EEE" } }
diff --git a/libiberty/cp-demangle.c b/libiberty/cp-demangle.c
index f2b36bcad68..efada1c322b 100644
--- a/libiberty/cp-demangle.c
+++ b/libiberty/cp-demangle.c
@@ -1947,6 +1947,7 @@ const struct demangle_operator_info 
cplus_demangle_operators[] =
{ "ng", NL ("-"), 1 },
{ "nt", NL ("!"), 1 },
{ "nw", NL ("new"),   3 },
+  { "nx", NL ("noexcept"),  1 },
{ "oR", NL ("|="),2 },
{ "oo", NL ("||"),2 },
{ "or", NL ("|"), 2 },
@@ -5836,8 +5837,8 @@ d_print_comp_inner (struct d_print_info *dpi, int options,
if (code && !strcmp (code, "gs"))
  /* Avoid parens after '::'.  */
  d_print_comp (dpi, options, operand);
-   else if (code && !strcmp (code, "st"))
- /* Always print parens for sizeof (type).  */
+   else if (code && (!strcmp (code, "st") || !strcmp (code, "nx")))
+ /* Always print parens for sizeof (type) or noexcept(expr).  */
  {
d_append_char (dpi, '(');
d_print_comp (dpi, options, operand);
diff --git a/libiberty/testsuite/demangle-expected 
b/libiberty/testsuite/demangle-expected
index d9bc7ed4b1f..52dff883a18 100644
--- a/libiberty/testsuite/demangle-expected
+++ b/libiberty/testsuite/demangle-expected
@@ -1659,3 +1659,6 @@ auto f()::{lambda(X<$T0>*, 
X*)#1}::operator()(X*,
  
  _ZZN1XIiE1FEvENKUliE_clEi

  X::F()::{lambda(int)#1}::operator()(int) const
+
+_Z1fIiEv1AIXnxtlT_EEE
+void f(A)

Re: [PATCH V2] RISC-V: Add RVV FMA auto-vectorization support

[juzhe.zh...@rivai.ai]

Ping。Ok for trunk？



juzhe.zh...@rivai.ai
 
From: juzhe.zhong
Date: 2023-05-26 19:35
To: gcc-patches
CC: kito.cheng; palmer; rdapp.gcc; jeffreyalaw; kito.cheng; pan2.li; Juzhe-Zhong
Subject: [PATCH V2] RISC-V: Add RVV FMA auto-vectorization support
From: Juzhe-Zhong 
 
This patch support FMA auto-vectorization pattern.
1. Let's RA decide vmacc or vmadd.
2. Fix bug of vector.md which generate incorrect information to VSETVL
   PASS when testing ternop-3.c.
 
gcc/ChangeLog:
 
* config/riscv/autovec.md (fma4): New pattern.
(*fma): Ditto.
* config/riscv/riscv-protos.h (enum insn_type): New enum.
(emit_vlmax_ternary_insn): New function.
* config/riscv/riscv-v.cc (emit_vlmax_ternary_insn): Ditto.
* config/riscv/vector.md: Fix vimuladd instruction bug.
 
gcc/testsuite/ChangeLog:
 
* gcc.target/riscv/rvv/rvv.exp: Add ternary tests
* gcc.target/riscv/rvv/autovec/ternop/ternop-1.c: New test.
* gcc.target/riscv/rvv/autovec/ternop/ternop-2.c: New test.
* gcc.target/riscv/rvv/autovec/ternop/ternop-3.c: New test.
* gcc.target/riscv/rvv/autovec/ternop/ternop_run-1.c: New test.
* gcc.target/riscv/rvv/autovec/ternop/ternop_run-2.c: New test.
* gcc.target/riscv/rvv/autovec/ternop/ternop_run-3.c: New test.
 
---
gcc/config/riscv/autovec.md   |  65 +++
gcc/config/riscv/riscv-protos.h   |   2 +
gcc/config/riscv/riscv-v.cc   |  20 
gcc/config/riscv/vector.md|   2 +-
.../riscv/rvv/autovec/ternop/ternop-1.c   |  28 +
.../riscv/rvv/autovec/ternop/ternop-2.c   |  34 ++
.../riscv/rvv/autovec/ternop/ternop-3.c   |  33 ++
.../riscv/rvv/autovec/ternop/ternop_run-1.c   |  84 ++
.../riscv/rvv/autovec/ternop/ternop_run-2.c   | 104 ++
.../riscv/rvv/autovec/ternop/ternop_run-3.c   | 104 ++
gcc/testsuite/gcc.target/riscv/rvv/rvv.exp|   2 +
11 files changed, 477 insertions(+), 1 deletion(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-3.c
create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-1.c
create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-2.c
create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-3.c
 
diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index 7fe4d94de39..04825df1210 100644
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -373,3 +373,68 @@
 DONE;
   }
)
+
+;; =
+;; == Ternary arithmetic
+;; =
+
+;; -
+;;  [INT] VMACC and VMADD
+;; -
+;; Includes:
+;; - vmacc
+;; - vmadd
+;; -
+
+;; We can't expand FMA for the following reasons:
+;; 1. Before RA, we don't know which multiply-add instruction is the ideal one.
+;;The vmacc is the ideal instruction when operands[3] overlaps operands[0].
+;;The vmadd is the ideal instruction when operands[1|2] overlaps 
operands[0].
+;; 2. According to vector.md, the multiply-add patterns has 'merge' operand 
which
+;;is the operands[5]. Since operands[5] should overlap operands[0], this 
operand
+;;should be allocated the same regno as operands[1|2|3].
+;; 3. The 'merge' operand is always a real merge operand and we don't allow 
undefined
+;;operand.
+;; 4. The operation of FMA pattern needs VLMAX vsetlvi which needs a VL 
operand.
+;;
+;; In this situation, we design the codegen of FMA as follows:
+;; 1. clobber a scratch in the expand pattern of FMA.
+;; 2. Let's RA decide which input operand (operands[1|2|3]) overlap 
operands[0].
+;; 3. Generate instructions (vmacc or vmadd) according to the register 
allocation
+;;result after reload_completed.
+(define_expand "fma4"
+  [(parallel
+[(set (match_operand:VI 0 "register_operand" "=vr")
+   (plus:VI
+ (mult:VI
+   (match_operand:VI 1 "register_operand" " vr")
+   (match_operand:VI 2 "register_operand" " vr"))
+ (match_operand:VI 3 "register_operand"   " vr")))
+ (clobber (match_scratch:SI 4))])]
+  "TARGET_VECTOR"
+  {})
+
+(define_insn_and_split "*fma"
+  [(set (match_operand:VI 0 "register_operand" "=vr, vr, ?&vr")
+ (plus:VI
+   (mult:VI
+ (match_operand:VI 1 "register_operand" " %0, vr,   vr")
+ (match_operand:VI 2 "register_operand" " vr, vr,   vr"))
+   (match_operand:VI 3 "register_operand"   " vr,  0,   vr")))
+   (clobber (match_scratch:SI 4 "=r,r,r

Ping^^ [PATCH v3] Add condition coverage profiling

[Jørgen Kvalsvik via Gcc-patches]

On 11/04/2023 15:23, Jørgen Kvalsvik wrote:
> On 05/12/2022 10:40, Jørgen Kvalsvik wrote:
>> This patch adds support in gcc+gcov for modified condition/decision
>> coverage (MC/DC) with the -fprofile-conditions flag. MC/DC is a type of
>> test/code coverage and it is particularly important in the avation and
>> automotive industries for safety-critical applications. MC/DC it is
>> required for or recommended by:
>>
>> * DO-178C for the most critical software (Level A) in avionics
>> * IEC 61508 for SIL 4
>> * ISO 26262-6 for ASIL D
>>
>>  From the SQLite webpage:
>>
>> Two methods of measuring test coverage were described above:
>> "statement" and "branch" coverage. There are many other test
>> coverage metrics besides these two. Another popular metric is
>> "Modified Condition/Decision Coverage" or MC/DC. Wikipedia defines
>> MC/DC as follows:
>>
>> * Each decision tries every possible outcome.
>> * Each condition in a decision takes on every possible outcome.
>> * Each entry and exit point is invoked.
>> * Each condition in a decision is shown to independently affect
>>   the outcome of the decision.
>>
>> In the C programming language where && and || are "short-circuit"
>> operators, MC/DC and branch coverage are very nearly the same thing.
>> The primary difference is in boolean vector tests. One can test for
>> any of several bits in bit-vector and still obtain 100% branch test
>> coverage even though the second element of MC/DC - the requirement
>> that each condition in a decision take on every possible outcome -
>> might not be satisfied.
>>
>> https://sqlite.org/testing.html#mcdc
>>
>> Wahlen, Heimdahl, and De Silva "Efficient Test Coverage Measurement for
>> MC/DC" describes an algorithm for adding instrumentation by carrying
>> over information from the AST, but my algorithm analyses the the control
>> flow graph to instrument for coverage. This has the benefit of being
>> programming language independent and faithful to compiler decisions
>> and transformations, although I have only tested it on constructs in C
>> and C++, see testsuite/gcc.misc-tests and testsuite/g++.dg.
>>
>> Like Wahlen et al this implementation records coverage in fixed-size
>> bitsets which gcov knows how to interpret. This is very fast, but
>> introduces a limit on the number of terms in a single boolean
>> expression, the number of bits in a gcov_unsigned_type (which is
>> typedef'd to uint64_t), so for most practical purposes this would be
>> acceptable. This limitation is in the implementation and not the
>> algorithm, so support for more conditions can be added by also
>> introducing arbitrary-sized bitsets.
>>
>> For space overhead, the instrumentation needs two accumulators
>> (gcov_unsigned_type) per condition in the program which will be written
>> to the gcov file. In addition, every function gets a pair of local
>> accumulators, but these accmulators are reused between conditions in the
>> same function.
>>
>> For time overhead, there is a zeroing of the local accumulators for
>> every condition and one or two bitwise operation on every edge taken in
>> the an expression.
>>
>> In action it looks pretty similar to the branch coverage. The -g short
>> opt carries no significance, but was chosen because it was an available
>> option with the upper-case free too.
>>
>> gcov --conditions:
>>
>> 3:   17:void fn (int a, int b, int c, int d) {
>> 3:   18:if ((a && (b || c)) && d)
>> condition outcomes covered 3/8
>> condition  0 not covered (true false)
>> condition  1 not covered (true)
>> condition  2 not covered (true)
>> condition  3 not covered (true)
>> 1:   19:x = 1;
>> -:   20:else
>> 2:   21:x = 2;
>> 3:   22:}
>>
>> gcov --conditions --json-format:
>>
>> "conditions": [
>> {
>> "not_covered_false": [
>> 0
>> ],
>> "count": 8,
>> "covered": 3,
>> "not_covered_true": [
>> 0,
>> 1,
>> 2,
>> 3
>> ]
>> }
>> ],
>>
>> Some expressions, mostly those without else-blocks, are effectively
>> "rewritten" in the CFG construction making the algorithm unable to
>> distinguish them:
>>
>> and.c:
>>
>> if (a && b && c)
>> x = 1;
>>
>> ifs.c:
>>
>> if (a)
>> if (b)
>> if (c)
>> x = 1;
>>
>> gcc will build the same graph for both these programs, and gcov will
>> report boths as 3-term expressions. It is vital that it is not
>> interpreted the other way around (which is consistent with the shape of
>> the graph) because otherwise the masking would be wrong for the and.c
>> program which is a more severe error. While surprising, users would
>> probably expect some minor rewriting of semantically-identical
>> expressions.
>>
>> and.c

RE: [PATCH] RISC-V: Add ZVFHMIN extension to the -march= option

[Li, Pan2 via Gcc-patches]

Sorry for disturbing but please help to take this PATCH in front of the 
reviewing queue as it blocks the RVV FP16 intrinsic support. Thanks a lot.

Pan

-Original Message-
From: Li, Pan2  
Sent: Thursday, May 25, 2023 8:46 PM
To: gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@sifive.com; Li, Pan2 ; 
Wang, Yanzhang 
Subject: [PATCH] RISC-V: Add ZVFHMIN extension to the -march= option

From: Pan Li 

This patch would like to add new sub extension (aka ZVFHMIN) to the -march= 
option. To make it simple, only the sub extension itself is involved in this 
patch, and the underlying FP16 related RVV intrinsic API depends on the 
TARGET_ZVFHMIN.

You can locate more information about ZVFHMIN from below spec doc.

https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#zvfhmin-vector-extension-for-minimal-half-precision-floating-point

Signed-off-by: Pan Li 

gcc/ChangeLog:

* common/config/riscv/riscv-common.cc:
(riscv_implied_info): Add zvfhmin item.
(riscv_ext_version_table): Ditto.
(riscv_ext_flag_table): Ditto.
* config/riscv/riscv-opts.h (MASK_ZVFHMIN): New macro.
(TARGET_ZFHMIN): Align indent.
(TARGET_ZFH): Ditto.
(TARGET_ZVFHMIN): New macro.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/arch-20.c: New test.
* gcc.target/riscv/predef-26.c: New test.
---
 gcc/common/config/riscv/riscv-common.cc|  3 ++
 gcc/config/riscv/riscv-opts.h  |  6 ++-
 gcc/testsuite/gcc.target/riscv/arch-20.c   |  5 +++
 gcc/testsuite/gcc.target/riscv/predef-26.c | 51 ++
 4 files changed, 63 insertions(+), 2 deletions(-)  create mode 100644 
gcc/testsuite/gcc.target/riscv/arch-20.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/predef-26.c

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index c2ec74b9d92..72f2f8f2753 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -104,6 +104,7 @@ static const riscv_implied_info_t riscv_implied_info[] =
 
   {"zfh", "zfhmin"},
   {"zfhmin", "f"},
+  {"zvfhmin", "f"},
 
   {"zhinx", "zhinxmin"},
   {"zhinxmin", "zfinx"},
@@ -216,6 +217,7 @@ static const struct riscv_ext_version 
riscv_ext_version_table[] =
 
   {"zfh",   ISA_SPEC_CLASS_NONE, 1, 0},
   {"zfhmin",ISA_SPEC_CLASS_NONE, 1, 0},
+  {"zvfhmin",   ISA_SPEC_CLASS_NONE, 1, 0},
 
   {"zmmul", ISA_SPEC_CLASS_NONE, 1, 0},
 
@@ -1259,6 +1261,7 @@ static const riscv_ext_flag_table_t 
riscv_ext_flag_table[] =
 
   {"zfhmin",&gcc_options::x_riscv_zf_subext, MASK_ZFHMIN},
   {"zfh",   &gcc_options::x_riscv_zf_subext, MASK_ZFH},
+  {"zvfhmin",   &gcc_options::x_riscv_zf_subext, MASK_ZVFHMIN},
 
   {"zmmul", &gcc_options::x_riscv_zm_subext, MASK_ZMMUL},
 
diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h 
index 2a16402265a..f34ca993689 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -200,9 +200,11 @@ enum riscv_entity
 
 #define MASK_ZFHMIN   (1 << 0)
 #define MASK_ZFH  (1 << 1)
+#define MASK_ZVFHMIN  (1 << 2)
 
-#define TARGET_ZFHMIN ((riscv_zf_subext & MASK_ZFHMIN) != 0)
-#define TARGET_ZFH((riscv_zf_subext & MASK_ZFH) != 0)
+#define TARGET_ZFHMIN  ((riscv_zf_subext & MASK_ZFHMIN) != 0)
+#define TARGET_ZFH ((riscv_zf_subext & MASK_ZFH) != 0)
+#define TARGET_ZVFHMIN ((riscv_zf_subext & MASK_ZVFHMIN) != 0)
 
 #define MASK_ZMMUL  (1 << 0)
 #define TARGET_ZMMUL((riscv_zm_subext & MASK_ZMMUL) != 0)
diff --git a/gcc/testsuite/gcc.target/riscv/arch-20.c 
b/gcc/testsuite/gcc.target/riscv/arch-20.c
new file mode 100644
index 000..8f8da1ecd65
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/arch-20.c
@@ -0,0 +1,5 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=rv32gcv_zvfhmin -mabi=ilp32 
+-mcmodel=medlow" } */ int foo() { }
diff --git a/gcc/testsuite/gcc.target/riscv/predef-26.c 
b/gcc/testsuite/gcc.target/riscv/predef-26.c
new file mode 100644
index 000..285f64bd6c0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/predef-26.c
@@ -0,0 +1,51 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=rv64i_zvfhmin -mabi=lp64f -mcmodel=medlow 
+-misa-spec=20191213" } */
+
+int main () {
+
+#ifndef __riscv_arch_test
+#error "__riscv_arch_test"
+#endif
+
+#if __riscv_xlen != 64
+#error "__riscv_xlen"
+#endif
+
+#if !defined(__riscv_i)
+#error "__riscv_i"
+#endif
+
+#if !defined(__riscv_f)
+#error "__riscv_f"
+#endif
+
+#if !defined(__riscv_zvfhmin)
+#error "__riscv_zvfhmin"
+#endif
+
+#if defined(__riscv_v)
+#error "__riscv_v"
+#endif
+
+#if defined(__riscv_d)
+#error "__riscv_d"
+#endif
+
+#if defined(__riscv_c)
+#error "__riscv_c"
+#endif
+
+#if defined(__riscv_a)
+#error "__riscv_a"
+#endif
+
+#if defined(__riscv_zfh)
+#error "__riscv_zfh"
+#endif
+
+#if defined(__riscv_zfhmin)
+#error "__riscv_zfhmin"
+#endif
+
+  return 0;
+}
--
2.34.1

Re: [PATCH] RISC-V: Add ZVFHMIN extension to the -march= option

[Kito Cheng via Gcc-patches]

On Mon, May 29, 2023 at 9:32 AM Li, Pan2 via Gcc-patches
 wrote:
>
> Sorry for disturbing but please help to take this PATCH in front of the 
> reviewing queue as it blocks the RVV FP16 intrinsic support. Thanks a lot.
>
> Pan
>
> -Original Message-
> From: Li, Pan2 
> Sent: Thursday, May 25, 2023 8:46 PM
> To: gcc-patches@gcc.gnu.org
> Cc: juzhe.zh...@rivai.ai; kito.ch...@sifive.com; Li, Pan2 
> ; Wang, Yanzhang 
> Subject: [PATCH] RISC-V: Add ZVFHMIN extension to the -march= option
>
> From: Pan Li 
>
> This patch would like to add new sub extension (aka ZVFHMIN) to the -march= 
> option. To make it simple, only the sub extension itself is involved in this 
> patch, and the underlying FP16 related RVV intrinsic API depends on the 
> TARGET_ZVFHMIN.
>
> You can locate more information about ZVFHMIN from below spec doc.
>
> https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#zvfhmin-vector-extension-for-minimal-half-precision-floating-point
>
> Signed-off-by: Pan Li 
>
> gcc/ChangeLog:
>
> * common/config/riscv/riscv-common.cc:
> (riscv_implied_info): Add zvfhmin item.
> (riscv_ext_version_table): Ditto.
> (riscv_ext_flag_table): Ditto.
> * config/riscv/riscv-opts.h (MASK_ZVFHMIN): New macro.
> (TARGET_ZFHMIN): Align indent.
> (TARGET_ZFH): Ditto.
> (TARGET_ZVFHMIN): New macro.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/arch-20.c: New test.
> * gcc.target/riscv/predef-26.c: New test.
> ---
>  gcc/common/config/riscv/riscv-common.cc|  3 ++
>  gcc/config/riscv/riscv-opts.h  |  6 ++-
>  gcc/testsuite/gcc.target/riscv/arch-20.c   |  5 +++
>  gcc/testsuite/gcc.target/riscv/predef-26.c | 51 ++
>  4 files changed, 63 insertions(+), 2 deletions(-)  create mode 100644 
> gcc/testsuite/gcc.target/riscv/arch-20.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/predef-26.c
>
> diff --git a/gcc/common/config/riscv/riscv-common.cc 
> b/gcc/common/config/riscv/riscv-common.cc
> index c2ec74b9d92..72f2f8f2753 100644
> --- a/gcc/common/config/riscv/riscv-common.cc
> +++ b/gcc/common/config/riscv/riscv-common.cc
> @@ -104,6 +104,7 @@ static const riscv_implied_info_t riscv_implied_info[] =
>
>{"zfh", "zfhmin"},
>{"zfhmin", "f"},
> +  {"zvfhmin", "f"},

spec says: "The Zvfhmin extension depends on the Zve32f extension."
so this should be zve32f rather than f


>{"zhinx", "zhinxmin"},
>{"zhinxmin", "zfinx"},

Re: [PATCH] RISC-V: Eliminate the magic number in riscv-v.cc

[Kito Cheng via Gcc-patches]

LGTM

On Fri, May 26, 2023 at 2:32 PM Li, Pan2 via Gcc-patches
 wrote:
>
> Thanks Robin.
>
> Sorry for not mentioned that it depends on another patch 
> https://gcc.gnu.org/pipermail/gcc-patches/2023-May/619536.html, which is in 
> the reviewing queue.
>
> Yes, totally agree we can remove the comments for some parameters excepts the 
> Boolean ones, as well as the term data related. I can file another PATCH to 
> make it happen due to it is another thing besides magic number elimination.
>
> Pan
>
> -Original Message-
> From: Robin Dapp 
> Sent: Friday, May 26, 2023 2:24 PM
> To: Li, Pan2 ; gcc-patches@gcc.gnu.org
> Cc: rdapp@gmail.com; juzhe.zh...@rivai.ai; kito.ch...@sifive.com; Wang, 
> Yanzhang 
> Subject: Re: [PATCH] RISC-V: Eliminate the magic number in riscv-v.cc
>
> Hi,
>
> > This patch would like to remove the magic number in the riscv-v.cc,
> > and align the same value to one macro.
>
> > diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
> > index 458020ce0a1..20b589bf51b 100644
> > --- a/gcc/config/riscv/riscv-v.cc
> > +++ b/gcc/config/riscv/riscv-v.cc
> > @@ -351,13 +351,15 @@ emit_vlmax_insn (unsigned icode, int op_num, rtx
> > *ops, rtx vl)  {
> >machine_mode data_mode = GET_MODE (ops[0]);
> >machine_mode mask_mode = get_mask_mode (data_mode).require ();
> > -  /* We have a maximum of 11 operands for RVV instruction patterns 
> > according to
> > -   * vector.md.  */
> > -  insn_expander<11> e (/*OP_NUM*/ op_num, /*HAS_DEST_P*/ true,
> > -/*FULLY_UNMASKED_P*/ true,
> > -/*USE_REAL_MERGE_P*/ false, /*HAS_AVL_P*/ true,
> > -/*VLMAX_P*/ true,
> > -/*DEST_MODE*/ data_mode, /*MASK_MODE*/ mask_mode);
> > +  insn_expander e (/*OP_NUM*/ op_num,
> > +   /*HAS_DEST_P*/ true,
> > +   /*FULLY_UNMASKED_P*/ true,
> > +   /*USE_REAL_MERGE_P*/ false,
> > +   /*HAS_AVL_P*/ true,
> > +   /*VLMAX_P*/ true,
> > +   /*DEST_MODE*/ data_mode,
> > +   /*MASK_MODE*/ mask_mode);
>
> I don't see where RVV_INSN_OPERANDS_MAX is defined.  Maybe you missed to 
> include that hunk?
>
> Apart from that maybe you could also remove the comments for dest_mode, 
> mask_mode and op_num?  I think the general "custom" is to just add them for 
> bool arguments and name non-bool arguments descriptively.  Here that could 
> mean renaming data_mode to dest_mode where appropriate (usually data_mode is 
> used to distinguish between data mode and comparison mode in conditionals, 
> not in regular insns where everything is "data").
>
> Regards
>  Robin

Re: [PATCH V2] RISC-V: Fix incorrect VXRM configuration in mode switching for CALL and ASM

[Kito Cheng via Gcc-patches]

LGTM, thanks :)

On Thu, May 25, 2023 at 3:00 PM  wrote:
>
> From: Juzhe-Zhong 
>
> Currently mode switching incorrect codegen for the following case:
> void fn (void);
>
> void f (void * in, void *out, int32_t x, int n, int m)
> {
>   for (int i = 0; i < n; i++) {
> vint32m1_t v = __riscv_vle32_v_i32m1 (in + i, 4);
> vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in + 100 + i, 4);
> vint32m1_t v3 = __riscv_vaadd_vx_i32m1 (v2, 0, VXRM_RDN, 4);
> fn ();
> v3 = __riscv_vaadd_vx_i32m1 (v3, 3, VXRM_RDN, 4);
> __riscv_vse32_v_i32m1 (out + 100 + i, v3, 4);
>   }
> }
>
> Before this patch:
>
> Preheader:
>   ...
>   csrwi vxrm,2
> Loop Body:
>   ... (no cswri vxrm,2)
>   vaadd.vx
>   ...
>   vaadd.vx
>   ...
>
> This codegen is incorrect.
>
> After this patch:
>
> Preheader:
>   ...
>   csrwi vxrm,2
> Loop Body:
>   ...
>   vaadd.vx
>   ...
>   csrwi vxrm,2
>   ...
>   vaadd.vx
>   ...
>
> cross-compile build PASS and regression PASS
>
> Ok for trunk ?
>
> gcc/ChangeLog:
>
> * config/riscv/riscv.cc (global_state_unknown_p): New function.
> (riscv_mode_after): Fix incorrect VXM.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/base/vxrm-11.c: New test.
> * gcc.target/riscv/rvv/base/vxrm-12.c: New test.
>
> ---
>  gcc/config/riscv/riscv.cc | 29 ++-
>  .../gcc.target/riscv/rvv/base/vxrm-11.c   | 20 +
>  .../gcc.target/riscv/rvv/base/vxrm-12.c   | 18 
>  3 files changed, 66 insertions(+), 1 deletion(-)
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-11.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-12.c
>
> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> index 09fc9e5d95e..406c5469425 100644
> --- a/gcc/config/riscv/riscv.cc
> +++ b/gcc/config/riscv/riscv.cc
> @@ -7549,6 +7549,31 @@ riscv_mode_needed (int entity, rtx_insn *insn)
>  }
>  }
>
> +/* Return true if the VXRM/FRM status of the INSN is unknown.  */
> +static bool
> +global_state_unknown_p (rtx_insn *insn, unsigned int regno)
> +{
> +  struct df_insn_info *insn_info = DF_INSN_INFO_GET (insn);
> +  df_ref ref;
> +
> +  /* Return true if there is a definition of VXRM.  */
> +  for (ref = DF_INSN_INFO_DEFS (insn_info); ref; ref = DF_REF_NEXT_LOC (ref))
> +if (DF_REF_REGNO (ref) == regno)
> +  return true;
> +
> +  /* A CALL function may contain an instruction that modifies the VXRM,
> + return true in this situation.  */
> +  if (CALL_P (insn))
> +return true;
> +
> +  /* Return true for all assembly since users may hardcode a assembly
> + like this: asm volatile ("csrwi vxrm, 0").  */
> +  extract_insn (insn);
> +  if (recog_data.is_asm)
> +return true;
> +  return false;
> +}
> +
>  /* Return the mode that an insn results in.  */
>
>  static int
> @@ -7557,7 +7582,9 @@ riscv_mode_after (int entity, int mode, rtx_insn *insn)
>switch (entity)
>  {
>  case RISCV_VXRM:
> -  if (recog_memoized (insn) >= 0)
> +  if (global_state_unknown_p (insn, VXRM_REGNUM))
> +   return VXRM_MODE_NONE;
> +  else if (recog_memoized (insn) >= 0)
> return reg_mentioned_p (gen_rtx_REG (SImode, VXRM_REGNUM),
> PATTERN (insn))
>  ? get_attr_vxrm_mode (insn)
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-11.c 
> b/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-11.c
> new file mode 100644
> index 000..7f637a8b7f5
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-11.c
> @@ -0,0 +1,20 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */
> +
> +#include "riscv_vector.h"
> +
> +void fn (void);
> +
> +void f (void * in, void *out, int32_t x, int n, int m)
> +{
> +  for (int i = 0; i < n; i++) {
> +vint32m1_t v = __riscv_vle32_v_i32m1 (in + i, 4);
> +vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in + 100 + i, 4);
> +vint32m1_t v3 = __riscv_vaadd_vx_i32m1 (v2, 0, VXRM_RDN, 4);
> +fn ();
> +v3 = __riscv_vaadd_vx_i32m1 (v3, 3, VXRM_RDN, 4);
> +__riscv_vse32_v_i32m1 (out + 100 + i, v3, 4);
> +  }
> +}
> +
> +/* { dg-final { scan-assembler-times {csrwi\s+vxrm,\s*2} 2 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-12.c 
> b/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-12.c
> new file mode 100644
> index 000..c3ab509f106
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-12.c
> @@ -0,0 +1,18 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */
> +
> +#include "riscv_vector.h"
> +
> +void f (void * in, void *out, int32_t x, int n, int m)
> +{
> +  for (int i = 0; i < n; i++) {
> +vint32m1_t v = __riscv_vle32_v_i32m1 (in + i, 4);
> +vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in + 100 + i, 4);
> +vint32m1_t v3 = __riscv_vaadd_vx_i32m1 (v2, 0, VXRM_RDN, 4);
> +asm volatile ("csrwi\tvxrm,1");
> +v3 = __riscv_vaadd_

[PATCH v2] RISC-V: Add ZVFHMIN extension to the -march= option

[Pan Li via Gcc-patches]

From: Pan Li 

This patch would like to add new sub extension (aka ZVFHMIN) to the
-march= option. To make it simple, only the sub extension itself is
involved in this patch, and the underlying FP16 related RVV intrinsic
API depends on the TARGET_ZVFHMIN.

The Zvfhmin extension depends on the Zve32f extension. You can locate
more information about ZVFHMIN from below spec doc.

https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#zvfhmin-vector-extension-for-minimal-half-precision-floating-point

Signed-off-by: Pan Li 

gcc/ChangeLog:

* common/config/riscv/riscv-common.cc:
(riscv_implied_info): Add zvfhmin item.
(riscv_ext_version_table): Ditto.
(riscv_ext_flag_table): Ditto.
* config/riscv/riscv-opts.h (MASK_ZVFHMIN): New macro.
(TARGET_ZFHMIN): Align indent.
(TARGET_ZFH): Ditto.
(TARGET_ZVFHMIN): New macro.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/arch-20.c: New test.
* gcc.target/riscv/predef-26.c: New test.

Signed-off-by: Pan Li 
---
 gcc/common/config/riscv/riscv-common.cc|  3 ++
 gcc/config/riscv/riscv-opts.h  |  6 ++-
 gcc/testsuite/gcc.target/riscv/arch-20.c   |  5 +++
 gcc/testsuite/gcc.target/riscv/predef-26.c | 51 ++
 4 files changed, 63 insertions(+), 2 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/arch-20.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/predef-26.c

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index c2ec74b9d92..92edafb516d 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -104,6 +104,7 @@ static const riscv_implied_info_t riscv_implied_info[] =
 
   {"zfh", "zfhmin"},
   {"zfhmin", "f"},
+  {"zvfhmin", "zve32f"},
 
   {"zhinx", "zhinxmin"},
   {"zhinxmin", "zfinx"},
@@ -216,6 +217,7 @@ static const struct riscv_ext_version 
riscv_ext_version_table[] =
 
   {"zfh",   ISA_SPEC_CLASS_NONE, 1, 0},
   {"zfhmin",ISA_SPEC_CLASS_NONE, 1, 0},
+  {"zvfhmin",   ISA_SPEC_CLASS_NONE, 1, 0},
 
   {"zmmul", ISA_SPEC_CLASS_NONE, 1, 0},
 
@@ -1259,6 +1261,7 @@ static const riscv_ext_flag_table_t 
riscv_ext_flag_table[] =
 
   {"zfhmin",&gcc_options::x_riscv_zf_subext, MASK_ZFHMIN},
   {"zfh",   &gcc_options::x_riscv_zf_subext, MASK_ZFH},
+  {"zvfhmin",   &gcc_options::x_riscv_zf_subext, MASK_ZVFHMIN},
 
   {"zmmul", &gcc_options::x_riscv_zm_subext, MASK_ZMMUL},
 
diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index 2a16402265a..f34ca993689 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -200,9 +200,11 @@ enum riscv_entity
 
 #define MASK_ZFHMIN   (1 << 0)
 #define MASK_ZFH  (1 << 1)
+#define MASK_ZVFHMIN  (1 << 2)
 
-#define TARGET_ZFHMIN ((riscv_zf_subext & MASK_ZFHMIN) != 0)
-#define TARGET_ZFH((riscv_zf_subext & MASK_ZFH) != 0)
+#define TARGET_ZFHMIN  ((riscv_zf_subext & MASK_ZFHMIN) != 0)
+#define TARGET_ZFH ((riscv_zf_subext & MASK_ZFH) != 0)
+#define TARGET_ZVFHMIN ((riscv_zf_subext & MASK_ZVFHMIN) != 0)
 
 #define MASK_ZMMUL  (1 << 0)
 #define TARGET_ZMMUL((riscv_zm_subext & MASK_ZMMUL) != 0)
diff --git a/gcc/testsuite/gcc.target/riscv/arch-20.c 
b/gcc/testsuite/gcc.target/riscv/arch-20.c
new file mode 100644
index 000..8f8da1ecd65
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/arch-20.c
@@ -0,0 +1,5 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=rv32gcv_zvfhmin -mabi=ilp32 -mcmodel=medlow" } */
+int foo()
+{
+}
diff --git a/gcc/testsuite/gcc.target/riscv/predef-26.c 
b/gcc/testsuite/gcc.target/riscv/predef-26.c
new file mode 100644
index 000..285f64bd6c0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/predef-26.c
@@ -0,0 +1,51 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=rv64i_zvfhmin -mabi=lp64f -mcmodel=medlow 
-misa-spec=20191213" } */
+
+int main () {
+
+#ifndef __riscv_arch_test
+#error "__riscv_arch_test"
+#endif
+
+#if __riscv_xlen != 64
+#error "__riscv_xlen"
+#endif
+
+#if !defined(__riscv_i)
+#error "__riscv_i"
+#endif
+
+#if !defined(__riscv_f)
+#error "__riscv_f"
+#endif
+
+#if !defined(__riscv_zvfhmin)
+#error "__riscv_zvfhmin"
+#endif
+
+#if defined(__riscv_v)
+#error "__riscv_v"
+#endif
+
+#if defined(__riscv_d)
+#error "__riscv_d"
+#endif
+
+#if defined(__riscv_c)
+#error "__riscv_c"
+#endif
+
+#if defined(__riscv_a)
+#error "__riscv_a"
+#endif
+
+#if defined(__riscv_zfh)
+#error "__riscv_zfh"
+#endif
+
+#if defined(__riscv_zfhmin)
+#error "__riscv_zfhmin"
+#endif
+
+  return 0;
+}
-- 
2.34.1

RE: [PATCH] RISC-V: Add ZVFHMIN extension to the -march= option

[Li, Pan2 via Gcc-patches]

Thanks Kito, update the PATCH v2 for addressing comments.

https://gcc.gnu.org/pipermail/gcc-patches/2023-May/619868.html

Pan

-Original Message-
From: Kito Cheng  
Sent: Monday, May 29, 2023 10:18 AM
To: Li, Pan2 
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; kito.ch...@sifive.com; Wang, 
Yanzhang 
Subject: Re: [PATCH] RISC-V: Add ZVFHMIN extension to the -march= option

On Mon, May 29, 2023 at 9:32 AM Li, Pan2 via Gcc-patches 
 wrote:
>
> Sorry for disturbing but please help to take this PATCH in front of the 
> reviewing queue as it blocks the RVV FP16 intrinsic support. Thanks a lot.
>
> Pan
>
> -Original Message-
> From: Li, Pan2 
> Sent: Thursday, May 25, 2023 8:46 PM
> To: gcc-patches@gcc.gnu.org
> Cc: juzhe.zh...@rivai.ai; kito.ch...@sifive.com; Li, Pan2 
> ; Wang, Yanzhang 
> Subject: [PATCH] RISC-V: Add ZVFHMIN extension to the -march= option
>
> From: Pan Li 
>
> This patch would like to add new sub extension (aka ZVFHMIN) to the -march= 
> option. To make it simple, only the sub extension itself is involved in this 
> patch, and the underlying FP16 related RVV intrinsic API depends on the 
> TARGET_ZVFHMIN.
>
> You can locate more information about ZVFHMIN from below spec doc.
>
> https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#zvfhmin-
> vector-extension-for-minimal-half-precision-floating-point
>
> Signed-off-by: Pan Li 
>
> gcc/ChangeLog:
>
> * common/config/riscv/riscv-common.cc:
> (riscv_implied_info): Add zvfhmin item.
> (riscv_ext_version_table): Ditto.
> (riscv_ext_flag_table): Ditto.
> * config/riscv/riscv-opts.h (MASK_ZVFHMIN): New macro.
> (TARGET_ZFHMIN): Align indent.
> (TARGET_ZFH): Ditto.
> (TARGET_ZVFHMIN): New macro.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/arch-20.c: New test.
> * gcc.target/riscv/predef-26.c: New test.
> ---
>  gcc/common/config/riscv/riscv-common.cc|  3 ++
>  gcc/config/riscv/riscv-opts.h  |  6 ++-
>  gcc/testsuite/gcc.target/riscv/arch-20.c   |  5 +++
>  gcc/testsuite/gcc.target/riscv/predef-26.c | 51 
> ++
>  4 files changed, 63 insertions(+), 2 deletions(-)  create mode 100644 
> gcc/testsuite/gcc.target/riscv/arch-20.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/predef-26.c
>
> diff --git a/gcc/common/config/riscv/riscv-common.cc 
> b/gcc/common/config/riscv/riscv-common.cc
> index c2ec74b9d92..72f2f8f2753 100644
> --- a/gcc/common/config/riscv/riscv-common.cc
> +++ b/gcc/common/config/riscv/riscv-common.cc
> @@ -104,6 +104,7 @@ static const riscv_implied_info_t 
> riscv_implied_info[] =
>
>{"zfh", "zfhmin"},
>{"zfhmin", "f"},
> +  {"zvfhmin", "f"},

spec says: "The Zvfhmin extension depends on the Zve32f extension."
so this should be zve32f rather than f


>{"zhinx", "zhinxmin"},
>{"zhinxmin", "zfinx"},

Re: [PATCH v2] RISC-V: Add ZVFHMIN extension to the -march= option

[Kito Cheng via Gcc-patches]

LGTM

On Mon, May 29, 2023 at 10:24 AM Pan Li via Gcc-patches
 wrote:
>
> From: Pan Li 
>
> This patch would like to add new sub extension (aka ZVFHMIN) to the
> -march= option. To make it simple, only the sub extension itself is
> involved in this patch, and the underlying FP16 related RVV intrinsic
> API depends on the TARGET_ZVFHMIN.
>
> The Zvfhmin extension depends on the Zve32f extension. You can locate
> more information about ZVFHMIN from below spec doc.
>
> https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#zvfhmin-vector-extension-for-minimal-half-precision-floating-point
>
> Signed-off-by: Pan Li 
>
> gcc/ChangeLog:
>
> * common/config/riscv/riscv-common.cc:
> (riscv_implied_info): Add zvfhmin item.
> (riscv_ext_version_table): Ditto.
> (riscv_ext_flag_table): Ditto.
> * config/riscv/riscv-opts.h (MASK_ZVFHMIN): New macro.
> (TARGET_ZFHMIN): Align indent.
> (TARGET_ZFH): Ditto.
> (TARGET_ZVFHMIN): New macro.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/arch-20.c: New test.
> * gcc.target/riscv/predef-26.c: New test.
>
> Signed-off-by: Pan Li 
> ---
>  gcc/common/config/riscv/riscv-common.cc|  3 ++
>  gcc/config/riscv/riscv-opts.h  |  6 ++-
>  gcc/testsuite/gcc.target/riscv/arch-20.c   |  5 +++
>  gcc/testsuite/gcc.target/riscv/predef-26.c | 51 ++
>  4 files changed, 63 insertions(+), 2 deletions(-)
>  create mode 100644 gcc/testsuite/gcc.target/riscv/arch-20.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/predef-26.c
>
> diff --git a/gcc/common/config/riscv/riscv-common.cc 
> b/gcc/common/config/riscv/riscv-common.cc
> index c2ec74b9d92..92edafb516d 100644
> --- a/gcc/common/config/riscv/riscv-common.cc
> +++ b/gcc/common/config/riscv/riscv-common.cc
> @@ -104,6 +104,7 @@ static const riscv_implied_info_t riscv_implied_info[] =
>
>{"zfh", "zfhmin"},
>{"zfhmin", "f"},
> +  {"zvfhmin", "zve32f"},
>
>{"zhinx", "zhinxmin"},
>{"zhinxmin", "zfinx"},
> @@ -216,6 +217,7 @@ static const struct riscv_ext_version 
> riscv_ext_version_table[] =
>
>{"zfh",   ISA_SPEC_CLASS_NONE, 1, 0},
>{"zfhmin",ISA_SPEC_CLASS_NONE, 1, 0},
> +  {"zvfhmin",   ISA_SPEC_CLASS_NONE, 1, 0},
>
>{"zmmul", ISA_SPEC_CLASS_NONE, 1, 0},
>
> @@ -1259,6 +1261,7 @@ static const riscv_ext_flag_table_t 
> riscv_ext_flag_table[] =
>
>{"zfhmin",&gcc_options::x_riscv_zf_subext, MASK_ZFHMIN},
>{"zfh",   &gcc_options::x_riscv_zf_subext, MASK_ZFH},
> +  {"zvfhmin",   &gcc_options::x_riscv_zf_subext, MASK_ZVFHMIN},
>
>{"zmmul", &gcc_options::x_riscv_zm_subext, MASK_ZMMUL},
>
> diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
> index 2a16402265a..f34ca993689 100644
> --- a/gcc/config/riscv/riscv-opts.h
> +++ b/gcc/config/riscv/riscv-opts.h
> @@ -200,9 +200,11 @@ enum riscv_entity
>
>  #define MASK_ZFHMIN   (1 << 0)
>  #define MASK_ZFH  (1 << 1)
> +#define MASK_ZVFHMIN  (1 << 2)
>
> -#define TARGET_ZFHMIN ((riscv_zf_subext & MASK_ZFHMIN) != 0)
> -#define TARGET_ZFH((riscv_zf_subext & MASK_ZFH) != 0)
> +#define TARGET_ZFHMIN  ((riscv_zf_subext & MASK_ZFHMIN) != 0)
> +#define TARGET_ZFH ((riscv_zf_subext & MASK_ZFH) != 0)
> +#define TARGET_ZVFHMIN ((riscv_zf_subext & MASK_ZVFHMIN) != 0)
>
>  #define MASK_ZMMUL  (1 << 0)
>  #define TARGET_ZMMUL((riscv_zm_subext & MASK_ZMMUL) != 0)
> diff --git a/gcc/testsuite/gcc.target/riscv/arch-20.c 
> b/gcc/testsuite/gcc.target/riscv/arch-20.c
> new file mode 100644
> index 000..8f8da1ecd65
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/arch-20.c
> @@ -0,0 +1,5 @@
> +/* { dg-do compile } */
> +/* { dg-options "-O2 -march=rv32gcv_zvfhmin -mabi=ilp32 -mcmodel=medlow" } */
> +int foo()
> +{
> +}
> diff --git a/gcc/testsuite/gcc.target/riscv/predef-26.c 
> b/gcc/testsuite/gcc.target/riscv/predef-26.c
> new file mode 100644
> index 000..285f64bd6c0
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/predef-26.c
> @@ -0,0 +1,51 @@
> +/* { dg-do compile } */
> +/* { dg-options "-O2 -march=rv64i_zvfhmin -mabi=lp64f -mcmodel=medlow 
> -misa-spec=20191213" } */
> +
> +int main () {
> +
> +#ifndef __riscv_arch_test
> +#error "__riscv_arch_test"
> +#endif
> +
> +#if __riscv_xlen != 64
> +#error "__riscv_xlen"
> +#endif
> +
> +#if !defined(__riscv_i)
> +#error "__riscv_i"
> +#endif
> +
> +#if !defined(__riscv_f)
> +#error "__riscv_f"
> +#endif
> +
> +#if !defined(__riscv_zvfhmin)
> +#error "__riscv_zvfhmin"
> +#endif
> +
> +#if defined(__riscv_v)
> +#error "__riscv_v"
> +#endif
> +
> +#if defined(__riscv_d)
> +#error "__riscv_d"
> +#endif
> +
> +#if defined(__riscv_c)
> +#error "__riscv_c"
> +#endif
> +
> +#if defined(__riscv_a)
> +#error "__riscv_a"
> +#endif
> +
> +#if defined(__riscv_zfh)
> +#error "__riscv_zfh"
> +#endif
> +
> +#if defined(__riscv_zfhmin)
> +#error "__riscv_zfhmin"
> +#endif
> +
> +  return 0;
> +}
> --
> 2.34.1
>

RE: [PATCH v2] RISC-V: Add ZVFHMIN extension to the -march= option

[Li, Pan2 via Gcc-patches]

Committed, thanks Kito.

Pan

-Original Message-
From: Kito Cheng  
Sent: Monday, May 29, 2023 10:40 AM
To: Li, Pan2 
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; kito.ch...@sifive.com; Wang, 
Yanzhang 
Subject: Re: [PATCH v2] RISC-V: Add ZVFHMIN extension to the -march= option

LGTM

On Mon, May 29, 2023 at 10:24 AM Pan Li via Gcc-patches 
 wrote:
>
> From: Pan Li 
>
> This patch would like to add new sub extension (aka ZVFHMIN) to the 
> -march= option. To make it simple, only the sub extension itself is 
> involved in this patch, and the underlying FP16 related RVV intrinsic 
> API depends on the TARGET_ZVFHMIN.
>
> The Zvfhmin extension depends on the Zve32f extension. You can locate 
> more information about ZVFHMIN from below spec doc.
>
> https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#zvfhmin-
> vector-extension-for-minimal-half-precision-floating-point
>
> Signed-off-by: Pan Li 
>
> gcc/ChangeLog:
>
> * common/config/riscv/riscv-common.cc:
> (riscv_implied_info): Add zvfhmin item.
> (riscv_ext_version_table): Ditto.
> (riscv_ext_flag_table): Ditto.
> * config/riscv/riscv-opts.h (MASK_ZVFHMIN): New macro.
> (TARGET_ZFHMIN): Align indent.
> (TARGET_ZFH): Ditto.
> (TARGET_ZVFHMIN): New macro.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/arch-20.c: New test.
> * gcc.target/riscv/predef-26.c: New test.
>
> Signed-off-by: Pan Li 
> ---
>  gcc/common/config/riscv/riscv-common.cc|  3 ++
>  gcc/config/riscv/riscv-opts.h  |  6 ++-
>  gcc/testsuite/gcc.target/riscv/arch-20.c   |  5 +++
>  gcc/testsuite/gcc.target/riscv/predef-26.c | 51 
> ++
>  4 files changed, 63 insertions(+), 2 deletions(-)  create mode 100644 
> gcc/testsuite/gcc.target/riscv/arch-20.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/predef-26.c
>
> diff --git a/gcc/common/config/riscv/riscv-common.cc 
> b/gcc/common/config/riscv/riscv-common.cc
> index c2ec74b9d92..92edafb516d 100644
> --- a/gcc/common/config/riscv/riscv-common.cc
> +++ b/gcc/common/config/riscv/riscv-common.cc
> @@ -104,6 +104,7 @@ static const riscv_implied_info_t 
> riscv_implied_info[] =
>
>{"zfh", "zfhmin"},
>{"zfhmin", "f"},
> +  {"zvfhmin", "zve32f"},
>
>{"zhinx", "zhinxmin"},
>{"zhinxmin", "zfinx"},
> @@ -216,6 +217,7 @@ static const struct riscv_ext_version 
> riscv_ext_version_table[] =
>
>{"zfh",   ISA_SPEC_CLASS_NONE, 1, 0},
>{"zfhmin",ISA_SPEC_CLASS_NONE, 1, 0},
> +  {"zvfhmin",   ISA_SPEC_CLASS_NONE, 1, 0},
>
>{"zmmul", ISA_SPEC_CLASS_NONE, 1, 0},
>
> @@ -1259,6 +1261,7 @@ static const riscv_ext_flag_table_t 
> riscv_ext_flag_table[] =
>
>{"zfhmin",&gcc_options::x_riscv_zf_subext, MASK_ZFHMIN},
>{"zfh",   &gcc_options::x_riscv_zf_subext, MASK_ZFH},
> +  {"zvfhmin",   &gcc_options::x_riscv_zf_subext, MASK_ZVFHMIN},
>
>{"zmmul", &gcc_options::x_riscv_zm_subext, MASK_ZMMUL},
>
> diff --git a/gcc/config/riscv/riscv-opts.h 
> b/gcc/config/riscv/riscv-opts.h index 2a16402265a..f34ca993689 100644
> --- a/gcc/config/riscv/riscv-opts.h
> +++ b/gcc/config/riscv/riscv-opts.h
> @@ -200,9 +200,11 @@ enum riscv_entity
>
>  #define MASK_ZFHMIN   (1 << 0)
>  #define MASK_ZFH  (1 << 1)
> +#define MASK_ZVFHMIN  (1 << 2)
>
> -#define TARGET_ZFHMIN ((riscv_zf_subext & MASK_ZFHMIN) != 0)
> -#define TARGET_ZFH((riscv_zf_subext & MASK_ZFH) != 0)
> +#define TARGET_ZFHMIN  ((riscv_zf_subext & MASK_ZFHMIN) != 0)
> +#define TARGET_ZFH ((riscv_zf_subext & MASK_ZFH) != 0)
> +#define TARGET_ZVFHMIN ((riscv_zf_subext & MASK_ZVFHMIN) != 0)
>
>  #define MASK_ZMMUL  (1 << 0)
>  #define TARGET_ZMMUL((riscv_zm_subext & MASK_ZMMUL) != 0)
> diff --git a/gcc/testsuite/gcc.target/riscv/arch-20.c 
> b/gcc/testsuite/gcc.target/riscv/arch-20.c
> new file mode 100644
> index 000..8f8da1ecd65
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/arch-20.c
> @@ -0,0 +1,5 @@
> +/* { dg-do compile } */
> +/* { dg-options "-O2 -march=rv32gcv_zvfhmin -mabi=ilp32 
> +-mcmodel=medlow" } */ int foo() { }
> diff --git a/gcc/testsuite/gcc.target/riscv/predef-26.c 
> b/gcc/testsuite/gcc.target/riscv/predef-26.c
> new file mode 100644
> index 000..285f64bd6c0
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/predef-26.c
> @@ -0,0 +1,51 @@
> +/* { dg-do compile } */
> +/* { dg-options "-O2 -march=rv64i_zvfhmin -mabi=lp64f -mcmodel=medlow 
> +-misa-spec=20191213" } */
> +
> +int main () {
> +
> +#ifndef __riscv_arch_test
> +#error "__riscv_arch_test"
> +#endif
> +
> +#if __riscv_xlen != 64
> +#error "__riscv_xlen"
> +#endif
> +
> +#if !defined(__riscv_i)
> +#error "__riscv_i"
> +#endif
> +
> +#if !defined(__riscv_f)
> +#error "__riscv_f"
> +#endif
> +
> +#if !defined(__riscv_zvfhmin)
> +#error "__riscv_zvfhmin"
> +#endif
> +
> +#if defined(__riscv_v)
> +#error "__riscv_v"
> +#endif
> +
> +#if defined(__riscv_d)
> +#error "__riscv_d"
> +#endif
> +
> +#if defined(__ri

Re: [PATCH] RISC-V: Add the option "-mdisable-multilib-check" to avoid multilib checks breaking the compilation.

[Jin Ma via Gcc-patches]

> > When testing a extension, it is often necessary for a certain program not to
> > need some kind of extension, such as the bitmanip extension, to evaluate the
> > performance or codesize of the extension. However, the current multilib 
> > rules
> > will report an error when it is not a superset of the MULTILIB_REQUIRED 
> > list,
> > which will cause the program to be unable to link normally, thus failing to
> > achieve the expected purpose.
> 
>  Hmm, I have troubles understanding what is going on here.  What do you 
> refer to by saying: "it is not a superset of the MULTILIB_REQUIRED list"?

This is a new matching rule added by kito for the multilib of riscv:
https://github.com/gcc-mirror/gcc/commit/d72ca12b846a9f5c01674b280b1817876c77888f

>  There should be no problem with linking compiled modules together that 
> make use of different extensions, with the static linker figuring out the 
> combined set of extensions actually required at run time for the program 
> loader to consider, as long as the modules do not have contradicting 
> requirements, e.g. big vs little endianness or RV32 vs RV64.
> 
>  Can you give me a specific example (compilation options and multilibs 
> available) of a failure you refer to?

A simple example:
1. Use "--disable-multilib --with-abi =lp64d --with-arch 
=rv64imafdc_zba_zbb_zbc_zbs"
to build the toolchain".
2. Use the toolchain to test the impact of zba_zbb_zbc_zbs extensions on the
performance and codesize of some functions or files in the program.

In this case, I may need to use the command "-mabi=lp64d -march=rv64imafdc" for
the compilation of a specific .c file in the program, which will cause the link 
to
fail and throw the following error: "FATAL ERROR: Can't find suitable multilib 
set for
'-march=rv64imafdc'/'-mabi=lp64d'". This does not satisfy the purpose of the 
test.

I think this needs an option to turn off this check. Users sometimes, just as
gcc uses the default multilib when it does not match the appropriate multilib,
do not need the `security lock`, and should already understand the risks
of using this option.

>  Is this something that could be solved without resorting to a possibly 
> dangerous hack, by making use of MULTILIB_REUSE?

Regarding the use of MULTILIB_REUSE, I think kito's patch has already been 
explained
and is currently implemented according to the new rules.
https://github.com/gcc-mirror/gcc/commit/5ca9980fc86242505ffdaaf62bca1fd5db26550b

> 
>   Maciej

Thanks,
Jin

Re: [PATCH 1/1] [V2] [RISC-V] support cm.push cm.pop cm.popret in zcmp

[Kito Cheng via Gcc-patches]

Thanks for this patch, just few minor comment, I think this is pretty
close to accept :)

Could you reference JiaWei's match_parallel[1] to prevent adding bunch
of *_offset_operand and stack_push_up_to_*_operand?


[1] 
https://patchwork.sourceware.org/project/gcc/patch/20230406062118.47431-5-jia...@iscas.ac.cn/


> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> index 629e5e45cac..a0a2db1f594 100644
> --- a/gcc/config/riscv/riscv.cc
> +++ b/gcc/config/riscv/riscv.cc
> @@ -117,6 +117,14 @@ struct GTY(())  riscv_frame_info {
>/* How much the GPR save/restore routines adjust sp (or 0 if unused).  */
>unsigned save_libcall_adjustment;
>
> +  /* the minimum number of bytes, in multiples of 16-byte address increments,
> + required to cover the registers in a multi push & pop.  */
> +  unsigned multi_push_adj_base;
> +
> +  /* the number of additional 16-byte address increments allocated for the 
> stack frame
> + in a multi push & pop.  */
> +  unsigned multi_push_adj_addi;
> +
>/* Offsets of fixed-point and floating-point save areas from frame bottom 
> */
>poly_int64 gp_sp_offset;
>poly_int64 fp_sp_offset;
> @@ -413,6 +421,21 @@ static const struct riscv_tune_info 
> riscv_tune_info_table[] = {
>  #include "riscv-cores.def"
>  };
>
> +typedef enum
> +{
> +  SI_IDX = 0,
> +  DI_IDX,
> +  MAX_MODE_IDX = DI_IDX
> +} mode_idx;
> +

Didn't see any use in this version?

> @@ -5574,18 +5924,25 @@ riscv_expand_epilogue (int style)
>REG_NOTES (insn) = dwarf;
>  }
>
> -  if (use_restore_libcall)
> -frame->mask = 0; /* Temporarily fib for GPRs.  */
> +  if (use_restore_libcall || use_multi_pop)
> +frame->mask = 0; /* Temporarily fib that we need not save GPRs.  */
>
>/* If we need to restore registers, deallocate as much stack as
>   possible in the second step without going out of range.  */
> -  if ((frame->mask | frame->fmask) != 0)
> +  if (use_multi_pop)
> +{
> +  if (frame->fmask
> +  && known_gt (frame->total_size - multipop_size,
> +  frame->frame_pointer_offset))
> +step2 = riscv_first_stack_step (frame, frame->total_size - 
> multipop_size);
> +}
> +  else if ((frame->mask | frame->fmask) != 0)
>  step2 = riscv_first_stack_step (frame, frame->total_size - libcall_size);
>
> -  if (use_restore_libcall)
> +  if (use_restore_libcall || use_multi_pop)
>  frame->mask = mask; /* Undo the above fib.  */
>
> -  poly_int64 step1 = frame->total_size - step2 - libcall_size;
> +  poly_int64 step1 = frame->total_size - step2 - libcall_size - 
> multipop_size ;
>
>/* Set TARGET to BASE + STEP1.  */
>if (known_gt (step1, 0))
> @@ -5620,7 +5977,7 @@ riscv_expand_epilogue (int style)
>adjust));
>   rtx dwarf = NULL_RTX;
>   rtx cfa_adjust_rtx = gen_rtx_PLUS (Pmode, stack_pointer_rtx,
> -GEN_INT (step2));
> +GEN_INT (step2 + libcall_size + 
> multipop_size));

Why we need `+ libcall_size` here? or...why we don't need that before?

>
>   dwarf = alloc_reg_note (REG_CFA_DEF_CFA, cfa_adjust_rtx, dwarf);
>   RTX_FRAME_RELATED_P (insn) = 1;
> @@ -5635,15 +5992,15 @@ riscv_expand_epilogue (int style)
>epilogue_cfa_sp_offset = step2;
>  }
>
> -  if (use_restore_libcall)
> +  if (use_restore_libcall || use_multi_pop)
>  frame->mask = 0; /* Temporarily fib that we need not save GPRs.  */
>
>/* Restore the registers.  */
> -  riscv_for_each_saved_reg (frame->total_size - step2 - libcall_size,
> +  riscv_for_each_saved_reg (frame->total_size - step2 - libcall_size - 
> multipop_size,
> riscv_restore_reg,
> true, style == EXCEPTION_RETURN);
>
> -  if (use_restore_libcall)
> +  if (use_restore_libcall || use_multi_pop)
>frame->mask = mask; /* Undo the above fib.  */
>
>if (need_barrier_p)
> @@ -5657,14 +6014,30 @@ riscv_expand_epilogue (int style)
>
>rtx dwarf = NULL_RTX;
>rtx cfa_adjust_rtx = gen_rtx_PLUS (Pmode, stack_pointer_rtx,
> -const0_rtx);
> +GEN_INT (libcall_size + 
> multipop_size));

Same question for `libcall_size` part.

Re: [PATCH] tree: Fix up save_expr [PR52339]

[Jason Merrill via Gcc-patches]

On 5/13/23 06:58, Eric Botcazou wrote:

I think we really need Eric (as one who e.g. introduced the
DECL_INVARIANT_P apparently for this kind of stuff) to have a look at that
on the Ada side.


I have been investigating this for a few days and it's no small change for Ada
and probably for other languages with dynamic types.  SAVE_EXPRs are delicate
to handle because 1) they are TREE_SIDE_EFFECTS (it's explained in save_expr)
so out of TREE_READONLY && !TREE_SIDE_EFFECTS trees, you now get side effects
which then propagate to all parent nodes


Hmm, interesting point.  The C++ front-end often explicitly creates a 
temporary with a TARGET_EXPR rather than SAVE_EXPR, and then later 
refers to just the variable; this avoids spreading TREE_SIDE_EFFECTS 
around, though it wasn't done for that reason.



2) their placement is problematic in
conditional expressions, for example if you replace

   cond > 0 ? A : A + 1

with

   cond > 0 ? SAVE_EXPR (A) : SAVE_EXPR (A) + 1

then gimplification will, say, create the temporary and initialize it in the
first arm so, if at runtime you take the second arm, you'll read the temporary
uninitialized.


Absolutely, you shouldn't have the same SAVE_EXPR on two sides of a ?: 
without also evaluating it in the condition (or earlier).  But that's 
already true for cases that already aren't invariant, so I'm surprised 
that this change would cause new problems of this sort.



That's caught for scalar values by the SSA form (if your patch
is applied to a GCC 12 tree, you'll get ICEs in the ACATS testsuite because of
this through finalize_type_size -> variable_size -> save_expr, it is probably
mitigated/addressed in GCC 14 by 68e0063397ba820e71adc220b2da0581dce29ffa).
That's also why making gnat_invariant_expr return (some of) them does not look
really safe.

In addition to this, in Ada we have bounds of unconstrained arrays which are
both read-only and stored indirectly, i.e. you have an INDIRECT_REF in the
tree (it is marked TREE_THIS_NOTRAP because the bounds are always present),
and which obviously play a crucial role in loops running over the arrays.
This issue is responsible for the regressions in the gnat.dg testsuite.


We want to be able to treat such things as invariant somehow even if we 
can't do that for references to user data that might be changed by 
intervening code.


That is, indicate that we know that the _REF actually refers to a const 
variable or is otherwise known to be unchanging.


Perhaps that should be a new flag that tree_invariant_p can check 
instead of TREE_READONLY.


Jason

Re: [PATCH] RISC-V: Add the option "-mdisable-multilib-check" to avoid multilib checks breaking the compilation.

[Kito Cheng via Gcc-patches]

On Mon, May 29, 2023 at 10:53 AM Jin Ma  wrote:
>
> > > When testing a extension, it is often necessary for a certain program not 
> > > to
> > > need some kind of extension, such as the bitmanip extension, to evaluate 
> > > the
> > > performance or codesize of the extension. However, the current multilib 
> > > rules
> > > will report an error when it is not a superset of the MULTILIB_REQUIRED 
> > > list,
> > > which will cause the program to be unable to link normally, thus failing 
> > > to
> > > achieve the expected purpose.
> >
> >  Hmm, I have troubles understanding what is going on here.  What do you
> > refer to by saying: "it is not a superset of the MULTILIB_REQUIRED list"?
>
> This is a new matching rule added by kito for the multilib of riscv:
> https://github.com/gcc-mirror/gcc/commit/d72ca12b846a9f5c01674b280b1817876c77888f
>
> >  There should be no problem with linking compiled modules together that
> > make use of different extensions, with the static linker figuring out the
> > combined set of extensions actually required at run time for the program
> > loader to consider, as long as the modules do not have contradicting
> > requirements, e.g. big vs little endianness or RV32 vs RV64.
> >
> >  Can you give me a specific example (compilation options and multilibs
> > available) of a failure you refer to?
>
> A simple example:
> 1. Use "--disable-multilib --with-abi =lp64d --with-arch 
> =rv64imafdc_zba_zbb_zbc_zbs"
> to build the toolchain".
> 2. Use the toolchain to test the impact of zba_zbb_zbc_zbs extensions on the
> performance and codesize of some functions or files in the program.
>
> In this case, I may need to use the command "-mabi=lp64d -march=rv64imafdc" 
> for
> the compilation of a specific .c file in the program, which will cause the 
> link to
> fail and throw the following error: "FATAL ERROR: Can't find suitable 
> multilib set for
> '-march=rv64imafdc'/'-mabi=lp64d'". This does not satisfy the purpose of the 
> test.

I feel this case should be build with --with-arch =rv64imafdc and test
with -march=rv64imafdc and  -march=rv64imafdc_zba_zbb_zbc_zbs,
but anyway I am OK with option :P

>
> I think this needs an option to turn off this check. Users sometimes, just as
> gcc uses the default multilib when it does not match the appropriate multilib,
> do not need the `security lock`, and should already understand the risks
> of using this option.
>
> >  Is this something that could be solved without resorting to a possibly
> > dangerous hack, by making use of MULTILIB_REUSE?
>
> Regarding the use of MULTILIB_REUSE, I think kito's patch has already been 
> explained
> and is currently implemented according to the new rules.
> https://github.com/gcc-mirror/gcc/commit/5ca9980fc86242505ffdaaf62bca1fd5db26550b
>
> >
> >   Maciej
>
> Thanks,
> Jin

Re: [PATCH V2] RISC-V: Add RVV FMA auto-vectorization support

[Kito Cheng via Gcc-patches]

LGTM, but with one question.

On Fri, May 26, 2023 at 7:36 PM  wrote:
>
> From: Juzhe-Zhong 
>
> This patch support FMA auto-vectorization pattern.
> 1. Let's RA decide vmacc or vmadd.
> 2. Fix bug of vector.md which generate incorrect information to VSETVL
>PASS when testing ternop-3.c.

Does this bug also appear in GCC 13? or this is new bug introduced at trunk

Re: Re: [PATCH V2] RISC-V: Add RVV FMA auto-vectorization support

[juzhe.zh...@rivai.ai]

This is existing bug in GCC 13. I think I should split into 2 patches.



juzhe.zh...@rivai.ai
 
From: Kito Cheng
Date: 2023-05-29 11:17
To: juzhe.zhong
CC: gcc-patches; kito.cheng; palmer; rdapp.gcc; jeffreyalaw; pan2.li
Subject: Re: [PATCH V2] RISC-V: Add RVV FMA auto-vectorization support
LGTM, but with one question.
 
On Fri, May 26, 2023 at 7:36 PM  wrote:
>
> From: Juzhe-Zhong 
>
> This patch support FMA auto-vectorization pattern.
> 1. Let's RA decide vmacc or vmadd.
> 2. Fix bug of vector.md which generate incorrect information to VSETVL
>PASS when testing ternop-3.c.
 
Does this bug also appear in GCC 13? or this is new bug introduced at trunk
 

RE: [PATCH V2] RISC-V: Fix incorrect VXRM configuration in mode switching for CALL and ASM

[Li, Pan2 via Gcc-patches]

Committed, thanks Kito.

Pan

-Original Message-
From: Kito Cheng  
Sent: Monday, May 29, 2023 10:22 AM
To: juzhe.zh...@rivai.ai
Cc: gcc-patches@gcc.gnu.org; kito.ch...@sifive.com; pal...@dabbelt.com; 
pal...@rivosinc.com; jeffreya...@gmail.com; rdapp@gmail.com; Li, Pan2 

Subject: Re: [PATCH V2] RISC-V: Fix incorrect VXRM configuration in mode 
switching for CALL and ASM

LGTM, thanks :)

On Thu, May 25, 2023 at 3:00 PM  wrote:
>
> From: Juzhe-Zhong 
>
> Currently mode switching incorrect codegen for the following case:
> void fn (void);
>
> void f (void * in, void *out, int32_t x, int n, int m) {
>   for (int i = 0; i < n; i++) {
> vint32m1_t v = __riscv_vle32_v_i32m1 (in + i, 4);
> vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in + 100 + i, 4);
> vint32m1_t v3 = __riscv_vaadd_vx_i32m1 (v2, 0, VXRM_RDN, 4);
> fn ();
> v3 = __riscv_vaadd_vx_i32m1 (v3, 3, VXRM_RDN, 4);
> __riscv_vse32_v_i32m1 (out + 100 + i, v3, 4);
>   }
> }
>
> Before this patch:
>
> Preheader:
>   ...
>   csrwi vxrm,2
> Loop Body:
>   ... (no cswri vxrm,2)
>   vaadd.vx
>   ...
>   vaadd.vx
>   ...
>
> This codegen is incorrect.
>
> After this patch:
>
> Preheader:
>   ...
>   csrwi vxrm,2
> Loop Body:
>   ...
>   vaadd.vx
>   ...
>   csrwi vxrm,2
>   ...
>   vaadd.vx
>   ...
>
> cross-compile build PASS and regression PASS
>
> Ok for trunk ?
>
> gcc/ChangeLog:
>
> * config/riscv/riscv.cc (global_state_unknown_p): New function.
> (riscv_mode_after): Fix incorrect VXM.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/base/vxrm-11.c: New test.
> * gcc.target/riscv/rvv/base/vxrm-12.c: New test.
>
> ---
>  gcc/config/riscv/riscv.cc | 29 ++-
>  .../gcc.target/riscv/rvv/base/vxrm-11.c   | 20 +
>  .../gcc.target/riscv/rvv/base/vxrm-12.c   | 18 
>  3 files changed, 66 insertions(+), 1 deletion(-)  create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-11.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-12.c
>
> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc 
> index 09fc9e5d95e..406c5469425 100644
> --- a/gcc/config/riscv/riscv.cc
> +++ b/gcc/config/riscv/riscv.cc
> @@ -7549,6 +7549,31 @@ riscv_mode_needed (int entity, rtx_insn *insn)
>  }
>  }
>
> +/* Return true if the VXRM/FRM status of the INSN is unknown.  */ 
> +static bool global_state_unknown_p (rtx_insn *insn, unsigned int 
> +regno) {
> +  struct df_insn_info *insn_info = DF_INSN_INFO_GET (insn);
> +  df_ref ref;
> +
> +  /* Return true if there is a definition of VXRM.  */  for (ref = 
> + DF_INSN_INFO_DEFS (insn_info); ref; ref = DF_REF_NEXT_LOC (ref))
> +if (DF_REF_REGNO (ref) == regno)
> +  return true;
> +
> +  /* A CALL function may contain an instruction that modifies the VXRM,
> + return true in this situation.  */  if (CALL_P (insn))
> +return true;
> +
> +  /* Return true for all assembly since users may hardcode a assembly
> + like this: asm volatile ("csrwi vxrm, 0").  */
> +  extract_insn (insn);
> +  if (recog_data.is_asm)
> +return true;
> +  return false;
> +}
> +
>  /* Return the mode that an insn results in.  */
>
>  static int
> @@ -7557,7 +7582,9 @@ riscv_mode_after (int entity, int mode, rtx_insn *insn)
>switch (entity)
>  {
>  case RISCV_VXRM:
> -  if (recog_memoized (insn) >= 0)
> +  if (global_state_unknown_p (insn, VXRM_REGNUM))
> +   return VXRM_MODE_NONE;
> +  else if (recog_memoized (insn) >= 0)
> return reg_mentioned_p (gen_rtx_REG (SImode, VXRM_REGNUM),
> PATTERN (insn))
>  ? get_attr_vxrm_mode (insn) diff --git 
> a/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-11.c 
> b/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-11.c
> new file mode 100644
> index 000..7f637a8b7f5
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-11.c
> @@ -0,0 +1,20 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */
> +
> +#include "riscv_vector.h"
> +
> +void fn (void);
> +
> +void f (void * in, void *out, int32_t x, int n, int m) {
> +  for (int i = 0; i < n; i++) {
> +vint32m1_t v = __riscv_vle32_v_i32m1 (in + i, 4);
> +vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in + 100 + i, 4);
> +vint32m1_t v3 = __riscv_vaadd_vx_i32m1 (v2, 0, VXRM_RDN, 4);
> +fn ();
> +v3 = __riscv_vaadd_vx_i32m1 (v3, 3, VXRM_RDN, 4);
> +__riscv_vse32_v_i32m1 (out + 100 + i, v3, 4);
> +  }
> +}
> +
> +/* { dg-final { scan-assembler-times {csrwi\s+vxrm,\s*2} 2 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-12.c 
> b/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-12.c
> new file mode 100644
> index 000..c3ab509f106
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-12.c
> @@ -0,0 +1,18 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */
> +
> +#inclu

Re: [PATCH V2] [vect]Enhance NARROW FLOAT_EXPR vectorization by truncating integer to lower precision.

[Hongtao Liu via Gcc-patches]

ping.

On Mon, May 8, 2023 at 9:59 AM liuhongt  wrote:
>
> > > @@ -4799,7 +4800,8 @@ vect_create_vectorized_demotion_stmts (vec_info 
> > > *vinfo, vec *vec_oprnds,
> > >stmt_vec_info stmt_info,
> > >vec &vec_dsts,
> > >gimple_stmt_iterator *gsi,
> > > -  slp_tree slp_node, enum tree_code 
> > > code)
> > > +  slp_tree slp_node, enum tree_code 
> > > code,
> > > +  bool last_stmt_p)
> >
> > Can you please document this new parameter?
> >
> Changed.
>
> >
> > I understand what you are doing, but somehow it looks a bit awkward?
> > Maybe we should split the NARROW case into NARROW_SRC and NARROW_DST?
> > The case of narrowing the source because we know its range isn't a
> > good fit for the
> > flow.
> Changed.
>
> Here's updated patch.
> Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,}.
> Ok for trunk?
>
> Similar like WIDEN FLOAT_EXPR, when direct_optab is not existed, try
> intermediate integer type whenever gimple ranger can tell it's safe.
>
> .i.e.
> When there's no direct optab for vector long long -> vector float, but
> the value range of integer can be represented as int, try vector int
> -> vector float if availble.
>
> gcc/ChangeLog:
>
> PR tree-optimization/108804
> * tree-vect-patterns.cc (vect_get_range_info): Remove static.
> * tree-vect-stmts.cc (vect_create_vectorized_demotion_stmts):
> Add new parameter narrow_src_p.
> (vectorizable_conversion): Enhance NARROW FLOAT_EXPR
> vectorization by truncating to lower precision.
> * tree-vectorizer.h (vect_get_range_info): New declare.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/i386/pr108804.c: New test.
> ---
>  gcc/testsuite/gcc.target/i386/pr108804.c |  15 +++
>  gcc/tree-vect-patterns.cc|   2 +-
>  gcc/tree-vect-stmts.cc   | 135 +--
>  gcc/tree-vectorizer.h|   1 +
>  4 files changed, 121 insertions(+), 32 deletions(-)
>  create mode 100644 gcc/testsuite/gcc.target/i386/pr108804.c
>
> diff --git a/gcc/testsuite/gcc.target/i386/pr108804.c 
> b/gcc/testsuite/gcc.target/i386/pr108804.c
> new file mode 100644
> index 000..2a43c1e1848
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/pr108804.c
> @@ -0,0 +1,15 @@
> +/* { dg-do compile } */
> +/* { dg-options "-mavx2 -Ofast -fdump-tree-vect-details" } */
> +/* { dg-final { scan-tree-dump-times "vectorized \[1-3] loops" 1 "vect" } } 
> */
> +
> +typedef unsigned long long uint64_t;
> +uint64_t d[512];
> +float f[1024];
> +
> +void foo() {
> +for (int i=0; i<512; ++i) {
> +uint64_t k = d[i];
> +f[i]=(k & 0x3F30);
> +}
> +}
> +
> diff --git a/gcc/tree-vect-patterns.cc b/gcc/tree-vect-patterns.cc
> index a49b0953977..dd546b488a4 100644
> --- a/gcc/tree-vect-patterns.cc
> +++ b/gcc/tree-vect-patterns.cc
> @@ -61,7 +61,7 @@ along with GCC; see the file COPYING3.  If not see
>  /* Return true if we have a useful VR_RANGE range for VAR, storing it
> in *MIN_VALUE and *MAX_VALUE if so.  Note the range in the dump files.  */
>
> -static bool
> +bool
>  vect_get_range_info (tree var, wide_int *min_value, wide_int *max_value)
>  {
>value_range vr;
> diff --git a/gcc/tree-vect-stmts.cc b/gcc/tree-vect-stmts.cc
> index 6b7dbfd4a23..3da89a8402d 100644
> --- a/gcc/tree-vect-stmts.cc
> +++ b/gcc/tree-vect-stmts.cc
> @@ -51,6 +51,7 @@ along with GCC; see the file COPYING3.  If not see
>  #include "internal-fn.h"
>  #include "tree-vector-builder.h"
>  #include "vec-perm-indices.h"
> +#include "gimple-range.h"
>  #include "tree-ssa-loop-niter.h"
>  #include "gimple-fold.h"
>  #include "regs.h"
> @@ -4791,7 +4792,9 @@ vect_gen_widened_results_half (vec_info *vinfo, enum 
> tree_code code,
>
>  /* Create vectorized demotion statements for vector operands from VEC_OPRNDS.
> For multi-step conversions store the resulting vectors and call the 
> function
> -   recursively.  */
> +   recursively. When NARROW_SRC_P is true, there's still a conversion after
> +   narrowing, don't store the vectors in the SLP_NODE or in vector info of
> +   the scalar statement(or in STMT_VINFO_RELATED_STMT chain).  */
>
>  static void
>  vect_create_vectorized_demotion_stmts (vec_info *vinfo, vec 
> *vec_oprnds,
> @@ -4799,7 +4802,8 @@ vect_create_vectorized_demotion_stmts (vec_info *vinfo, 
> vec *vec_oprnds,
>stmt_vec_info stmt_info,
>vec &vec_dsts,
>gimple_stmt_iterator *gsi,
> -  slp_tree slp_node, enum tree_code code)
> +  slp_tree slp_node, enum tree_code code,
> +  bool narrow_src_p)
>  {
>uns

[PATCH] RISC-V: Remove redundant printf of abs-run.c

[juzhe . zhong]

From: Juzhe-Zhong 

Notice that this testcase cause unexpected fail:
FAIL: gcc.target/riscv/rvv/autovec/unop/abs-run.c (test for excess errors)
Excess errors:
/work/home/jzzhong/work/rvv-opensource/software/host/toolchain/gcc/riscv-gcc/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-run.c:22:7:
 warning: implicit declaration of function 'printf' 
[-Wimplicit-function-declaration]
/work/home/jzzhong/work/rvv-opensource/software/host/toolchain/gcc/riscv-gcc/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-run.c:22:7:
 warning: incompatible implicit declaration of built-in function 'printf' 
[-Wbuiltin-declaration-mismatch]
/work/home/jzzhong/work/rvv-opensource/software/host/toolchain/gcc/riscv-gcc/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-run.c:22:7:
 warning: incompatible implicit declaration of built-in function 'printf' 
[-Wbuiltin-declaration-mismatch]
/work/home/jzzhong/work/rvv-opensource/software/host/toolchain/gcc/riscv-gcc/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-run.c:22:7:
 warning: incompatible implicit declaration of built-in function 'printf' 
[-Wbuiltin-declaration-mismatch]
/work/home/jzzhong/work/rvv-opensource/software/host/toolchain/gcc/riscv-gcc/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-run.c:22:7:
 warning: incompatible implicit declaration of built-in function 'printf' 
[-Wbuiltin-declaration-mismatch]

spawn /work/home/jzzhong/work/rvv-opensource/output/sim/bin/spike 
--isa=RV64GCVZfh 
/work/home/jzzhong/work/rvv-opensource/output/sim/riscv64-rivai-elf/bin/pk 
./abs-run.exe^M
bbl loader^M^M
0 0 -64^M
1 63 -63^M
2 2 -62^M
3 61 -61^M
4 4 -60^M
5 59 -59^M
6 6 -58^M
7 57 -57^M
8 8 -56^M
9 55 -55^M
10 10 -54^M
11 53 -53^M
12 12 -52^M
13 51 -51^M

Remove printf since it's unnecessary.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/unop/abs-run.c: Remove redundant printf.

---
 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-run.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-run.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-run.c
index 7404dbe037e..d864b54229b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-run.c
@@ -19,7 +19,6 @@
   vabs_##TYPE (a##TYPE, a##TYPE, SZ);  \
   for (int i = 0; i < SZ; i++) \
 {  \
-  printf ("%d %d %d\n", i, a##TYPE[i], i - 64);\
   if (i & 1)   \
assert (a##TYPE[i] == abs (i - 64));\
   else \
-- 
2.36.3

Re: [PATCH] RISC-V: Remove redundant printf of abs-run.c

[Kito Cheng via Gcc-patches]

Ok

 於 2023年5月29日 週一 11:39 寫道：

> From: Juzhe-Zhong 
>
> Notice that this testcase cause unexpected fail:
> FAIL: gcc.target/riscv/rvv/autovec/unop/abs-run.c (test for excess errors)
> Excess errors:
> /work/home/jzzhong/work/rvv-opensource/software/host/toolchain/gcc/riscv-gcc/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-run.c:22:7:
> warning: implicit declaration of function 'printf'
> [-Wimplicit-function-declaration]
> /work/home/jzzhong/work/rvv-opensource/software/host/toolchain/gcc/riscv-gcc/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-run.c:22:7:
> warning: incompatible implicit declaration of built-in function 'printf'
> [-Wbuiltin-declaration-mismatch]
> /work/home/jzzhong/work/rvv-opensource/software/host/toolchain/gcc/riscv-gcc/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-run.c:22:7:
> warning: incompatible implicit declaration of built-in function 'printf'
> [-Wbuiltin-declaration-mismatch]
> /work/home/jzzhong/work/rvv-opensource/software/host/toolchain/gcc/riscv-gcc/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-run.c:22:7:
> warning: incompatible implicit declaration of built-in function 'printf'
> [-Wbuiltin-declaration-mismatch]
> /work/home/jzzhong/work/rvv-opensource/software/host/toolchain/gcc/riscv-gcc/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-run.c:22:7:
> warning: incompatible implicit declaration of built-in function 'printf'
> [-Wbuiltin-declaration-mismatch]
>
> spawn /work/home/jzzhong/work/rvv-opensource/output/sim/bin/spike
> --isa=RV64GCVZfh
> /work/home/jzzhong/work/rvv-opensource/output/sim/riscv64-rivai-elf/bin/pk
> ./abs-run.exe^M
> bbl loader^M^M
> 0 0 -64^M
> 1 63 -63^M
> 2 2 -62^M
> 3 61 -61^M
> 4 4 -60^M
> 5 59 -59^M
> 6 6 -58^M
> 7 57 -57^M
> 8 8 -56^M
> 9 55 -55^M
> 10 10 -54^M
> 11 53 -53^M
> 12 12 -52^M
> 13 51 -51^M
>
> Remove printf since it's unnecessary.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/autovec/unop/abs-run.c: Remove redundant
> printf.
>
> ---
>  gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-run.c | 1 -
>  1 file changed, 1 deletion(-)
>
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-run.c
> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-run.c
> index 7404dbe037e..d864b54229b 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-run.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-run.c
> @@ -19,7 +19,6 @@
>vabs_##TYPE (a##TYPE, a##TYPE, SZ);  \
>for (int i = 0; i < SZ; i++) \
>  {  \
> -  printf ("%d %d %d\n", i, a##TYPE[i], i - 64);\
>if (i & 1)   \
> assert (a##TYPE[i] == abs (i - 64));\
>else \
> --
> 2.36.3
>
>

Re: [PATCH] RISC-V: Add the option "-mdisable-multilib-check" to avoid multilib checks breaking the compilation.

[Jin Ma via Gcc-patches]

> > > > When testing a extension, it is often necessary for a certain program 
> > > > not to
> > > > need some kind of extension, such as the bitmanip extension, to 
> > > > evaluate the
> > > > performance or codesize of the extension. However, the current multilib 
> > > > rules
> > > > will report an error when it is not a superset of the MULTILIB_REQUIRED 
> > > > list,
> > > > which will cause the program to be unable to link normally, thus 
> > > > failing to
> > > > achieve the expected purpose.
> > >
> > >  Hmm, I have troubles understanding what is going on here.  What do you
> > > refer to by saying: "it is not a superset of the MULTILIB_REQUIRED list"?
> >
> > This is a new matching rule added by kito for the multilib of riscv:
> > https://github.com/gcc-mirror/gcc/commit/d72ca12b846a9f5c01674b280b1817876c77888f
> >
> > >  There should be no problem with linking compiled modules together that
> > > make use of different extensions, with the static linker figuring out the
> > > combined set of extensions actually required at run time for the program
> > > loader to consider, as long as the modules do not have contradicting
> > > requirements, e.g. big vs little endianness or RV32 vs RV64.
> > >
> > >  Can you give me a specific example (compilation options and multilibs
> > > available) of a failure you refer to?
> >
> > A simple example:
> > 1. Use "--disable-multilib --with-abi =lp64d --with-arch 
> > =rv64imafdc_zba_zbb_zbc_zbs"
> > to build the toolchain".
> > 2. Use the toolchain to test the impact of zba_zbb_zbc_zbs extensions on the
> > performance and codesize of some functions or files in the program.
> >
> > In this case, I may need to use the command "-mabi=lp64d -march=rv64imafdc" 
> > for
> > the compilation of a specific .c file in the program, which will cause the 
> > link to
> > fail and throw the following error: "FATAL ERROR: Can't find suitable 
> > multilib set for
> > '-march=rv64imafdc'/'-mabi=lp64d'". This does not satisfy the purpose of 
> > the test.
> 
> I feel this case should be build with --with-arch =rv64imafdc and test
> with -march=rv64imafdc and  -march=rv64imafdc_zba_zbb_zbc_zbs,
> but anyway I am OK with option :P

Yes, but with "--with-arch=rv64imafdc" building toolchains, the library will 
not contain
zba_zbb_zbc_zbs extensions, so how can we quickly and easily eliminate the 
impact of not
using zba_zbb_zbc_zbs extensions in a certain program on program performance 
and codesize?

Although-mno-multilib-check is unsafe, it is useful during the development and 
testing phases.

> 
> >
> > I think this needs an option to turn off this check. Users sometimes, just 
> > as
> > gcc uses the default multilib when it does not match the appropriate 
> > multilib,
> > do not need the `security lock`, and should already understand the risks
> > of using this option.
> >
> > >  Is this something that could be solved without resorting to a possibly
> > > dangerous hack, by making use of MULTILIB_REUSE?
> >
> > Regarding the use of MULTILIB_REUSE, I think kito's patch has already been 
> > explained
> > and is currently implemented according to the new rules.
> > https://github.com/gcc-mirror/gcc/commit/5ca9980fc86242505ffdaaf62bca1fd5db26550b
> >
> > >
> > >   Maciej
> >
> > Thanks,
> > Jin

[PATCH] RISC-V: Add floating-point to integer conversion RVV auto-vectorization support

[juzhe . zhong]

From: Juzhe-Zhong 

Even though we can't support floating-point operations which are depending
on FRM yet, (for example vfadd support is blocked) since the RVV intrinsic doc 
is not updated
and we can't support mode switching for this.

We can support floating-point to integer conversion now since it's not 
depending on FRM and
we don't need mode switching support for this ('rtz' conversions independent 
FRM).

gcc/ChangeLog:

* config/riscv/autovec.md (2): New pattern.
* config/riscv/iterators.md: New attribute.
* config/riscv/vector-iterators.md: New attribute.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-run.c: New test.
* gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-rv32gcv.c: New 
test.
* gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-rv64gcv.c: New 
test.
* gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-template.h: New 
test.

---
 gcc/config/riscv/autovec.md   | 23 
 gcc/config/riscv/iterators.md |  4 +-
 gcc/config/riscv/vector-iterators.md  |  5 ++
 .../rvv/autovec/conversions/vfcvt_rtz-run.c   | 52 +++
 .../autovec/conversions/vfcvt_rtz-rv32gcv.c   |  6 +++
 .../autovec/conversions/vfcvt_rtz-rv64gcv.c   |  6 +++
 .../autovec/conversions/vfcvt_rtz-template.h  | 15 ++
 7 files changed, 110 insertions(+), 1 deletion(-)
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-run.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-rv32gcv.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-rv64gcv.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-template.h

diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index b24867ae4d0..3989ffb26ee 100644
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -478,6 +478,29 @@
   DONE;
 })
 
+;; =
+;; == Conversions
+;; =
+
+;; -
+;;  [INT<-FP] Conversions
+;; -
+;; Includes:
+;; - vfcvt.rtz.xu.f.v
+;; - vfcvt.rtz.x.f.v
+;; -
+
+(define_expand "2"
+  [(set (match_operand: 0 "register_operand")
+   (any_fix:
+ (match_operand:VF 1 "register_operand")))]
+  "TARGET_VECTOR"
+{
+  insn_code icode = code_for_pred (, mode);
+  riscv_vector::emit_vlmax_insn (icode, riscv_vector::RVV_UNOP, operands);
+  DONE;
+})
+
 ;; =
 ;; == Unary arithmetic
 ;; =
diff --git a/gcc/config/riscv/iterators.md b/gcc/config/riscv/iterators.md
index 8afe98e4410..d374a10810c 100644
--- a/gcc/config/riscv/iterators.md
+++ b/gcc/config/riscv/iterators.md
@@ -225,7 +225,9 @@
 (ss_minus "sssub")
 (us_minus "ussub")
 (sign_extend "extend")
-(zero_extend "zero_extend")])
+(zero_extend "zero_extend")
+(fix "fix_trunc")
+(unsigned_fix "fixuns_trunc")])
 
 ;;  code attributes
 (define_code_attr or_optab [(ior "ior")
diff --git a/gcc/config/riscv/vector-iterators.md 
b/gcc/config/riscv/vector-iterators.md
index 70fb5b80b1b..937ec3c7f67 100644
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -1208,6 +1208,11 @@
   (VNx1DF "VNx1DI") (VNx2DF "VNx2DI") (VNx4DF "VNx4DI") (VNx8DF "VNx8DI") 
(VNx16DF "VNx16DI")
 ])
 
+(define_mode_attr vconvert [
+  (VNx1SF "vnx1si") (VNx2SF "vnx2si") (VNx4SF "vnx4si") (VNx8SF "vnx8si") 
(VNx16SF "vnx16si") (VNx32SF "vnx32si")
+  (VNx1DF "vnx1di") (VNx2DF "vnx2di") (VNx4DF "vnx4di") (VNx8DF "vnx8di") 
(VNx16DF "vnx16di")
+])
+
 (define_mode_attr VNCONVERT [
   (VNx1SF "VNx1HI") (VNx2SF "VNx2HI") (VNx4SF "VNx4HI") (VNx8SF "VNx8HI") 
(VNx16SF "VNx16HI") (VNx32SF "VNx32HI")
   (VNx1DI "VNx1SF") (VNx2DI "VNx2SF") (VNx4DI "VNx4SF") (VNx8DI "VNx8SF") 
(VNx16DI "VNx16SF")
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-run.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-run.c
new file mode 100644
index 000..b81814893dd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-run.c
@@ -0,0 +1,52 @@
+/* { dg-do run { target { riscv_vector } } } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model 
--param=riscv-autovec-preference=scalable" } */
+
+#include "vfcvt_rtz-template.h"
+
+#define RUN(TYPE1, TYPE2, NUM)   

[RFC] light expander sra for parameters and returns

[Jiufu Guo via Gcc-patches]

Hi,

Previously, I was investigating some struct parameters and returns related
PRs 69143/65421/108073.

Investigating the issues case by case, and drafting patches for each of
them one by one. This would help us to enhance code incrementally.
While, this way, patches would interact with each other and implement
different codes for similar issues (because of the different paths in
gimple/rtl).  We may have a common fix for those issues.

We know a few other related PRs(such as meta-bug PR101926) exist. For those
PRs in different targets with different symptoms (and also different root
cause), I would expect a method could help some of them, but it may
be hard to handle all of them in one fix.

With investigation and check discussion for the issues, I remember a
suggestion from Richard: it would be nice to perform some SRA-like analysis
for the accesses on the structs (parameter/returns).
https://gcc.gnu.org/pipermail/gcc-patches/2022-November/605117.html
This may be a 'fairly common method' for those issues. With this idea,
I drafted a patch as below in this mail.

I also thought about directly using tree-sra.cc, e.g. enhance it and rerun it
at the end of GIMPLE passes. While since some issues are introduced inside
the expander, so below patch also co-works with other parts of the expander.
And since we already have tree-sra in gimple pass, we only need to take more
care on parameter and return in this patch: other decls could be handled
well in tree-sra.

The steps of this patch are:
1. Collect struct type parameters and returns, and then scan the function to
get the accesses on them. And figure out the accesses which would be profitable
to be scalarized (using registers of the parameter/return ). Now, reading on
parameter and writing on returns are checked in the current patch.
2. When/after the scalar registers are determined/expanded for the return or
parameters, compute the corresponding scalar register(s) for each accesses of
the return/parameter, and prepare the scalar RTLs for those accesses.
3. When using/expanding the accesses expression, leverage the computed/prepared
scalars directly.

This patch is tested on ppc64 both LE and BE.
To continue, I would ask for comments and suggestions first. And then I would
update/enhance accordingly.  Thanks in advance!
   

BR,
Jeff (Jiufu)


---
 gcc/cfgexpand.cc | 567 ++-
 gcc/expr.cc  |  15 +-
 gcc/function.cc  |  26 +-
 gcc/opts.cc  |   8 +-
 gcc/testsuite/g++.target/powerpc/pr102024.C  |   2 +-
 gcc/testsuite/gcc.target/powerpc/pr108073.c  |  29 +
 gcc/testsuite/gcc.target/powerpc/pr65421-1.c |   6 +
 gcc/testsuite/gcc.target/powerpc/pr65421-2.c |  32 ++
 8 files changed, 675 insertions(+), 10 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/powerpc/pr108073.c
 create mode 100644 gcc/testsuite/gcc.target/powerpc/pr65421-1.c
 create mode 100644 gcc/testsuite/gcc.target/powerpc/pr65421-2.c

diff --git a/gcc/cfgexpand.cc b/gcc/cfgexpand.cc
index 85a93a547c0..95c29b6b6fe 100644
--- a/gcc/cfgexpand.cc
+++ b/gcc/cfgexpand.cc
@@ -97,6 +97,564 @@ static bool defer_stack_allocation (tree, bool);
 
 static void record_alignment_for_reg_var (unsigned int);
 
+/* For light SRA in expander about paramaters and returns.  */
+namespace {
+
+struct access
+{
+  /* Each accessing on the aggragate is about OFFSET/SIZE and BASE.  */
+  HOST_WIDE_INT offset;
+  HOST_WIDE_INT size;
+  tree base;
+  bool writing;
+
+  /* The context expression of this access.  */
+  tree expr;
+
+  /* The rtx for the access: link to incoming/returning register(s).  */
+  rtx rtx_val;
+};
+
+typedef struct access *access_p;
+
+/* Expr (tree) -> Acess (access_p) map.  */
+static hash_map *expr_access_vec;
+
+/* Base (tree) -> Vector (vec *) map.  */
+static hash_map > *base_access_vec;
+
+/* Return a vector of pointers to accesses for the variable given in BASE or
+ NULL if there is none.  */
+
+static vec *
+get_base_access_vector (tree base)
+{
+  return base_access_vec->get (base);
+}
+
+/* Remove DECL from candidates for SRA.  */
+static void
+disqualify_candidate (tree decl)
+{
+  decl = get_base_address (decl);
+  base_access_vec->remove (decl);
+}
+
+/* Create and insert access for EXPR. Return created access, or NULL if it is
+   not possible.  */
+static struct access *
+create_access (tree expr, bool write)
+{
+  poly_int64 poffset, psize, pmax_size;
+  bool reverse;
+
+  tree base
+= get_ref_base_and_extent (expr, &poffset, &psize, &pmax_size, &reverse);
+
+  if (!DECL_P (base))
+return NULL;
+
+  vec *access_vec = get_base_access_vector (base);
+  if (!access_vec)
+return NULL;
+
+  /* TODO: support reverse. */
+  if (reverse)
+{
+  disqualify_candidate (expr);
+  return NULL;
+}
+
+  HOST_WIDE_INT offset, size, max_size;
+  if (!poffset.is_constant (&offset) || !psize.is_constant (&size)
+  || !pmax_size.is_

Re: [PATCH] RISC-V: Fix VSETVL PASS ICE on SLP auto-vectorization

[juzhe.zh...@rivai.ai]

This patch is fixing VSETVL PASS bug. Ok for trunk ?



juzhe.zh...@rivai.ai
 
From: juzhe.zhong
Date: 2023-05-26 11:01
To: gcc-patches
CC: kito.cheng; kito.cheng; palmer; palmer; jeffreyalaw; rdapp.gcc; pan2.li; 
Juzhe-Zhong
Subject: [PATCH] RISC-V: Fix VSETVL PASS ICE on SLP auto-vectorization
From: Juzhe-Zhong 
 
Fix bug reported here:
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109974
 
PR target/109974
 
gcc/ChangeLog:
 
* config/riscv/riscv-vsetvl.cc (source_equal_p): Fix ICE.
 
gcc/testsuite/ChangeLog:
 
* gcc.target/riscv/rvv/vsetvl/pr109974.c: New test.
 
---
gcc/config/riscv/riscv-vsetvl.cc  | 30 ++-
.../gcc.target/riscv/rvv/vsetvl/pr109974.c| 17 +++
2 files changed, 46 insertions(+), 1 deletion(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109974.c
 
diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc
index 9847d649d1d..fe55f4ccd30 100644
--- a/gcc/config/riscv/riscv-vsetvl.cc
+++ b/gcc/config/riscv/riscv-vsetvl.cc
@@ -1138,7 +1138,35 @@ source_equal_p (insn_info *insn1, insn_info *insn2)
 return false;
   if (!rtx_equal_p (SET_SRC (single_set1), SET_SRC (single_set2)))
 return false;
-  gcc_assert (insn1->uses ().size () == insn2->uses ().size ());
+  /* RTL_SSA uses include REG_NOTE. Consider this following case:
+
+ insn1 RTL:
+ (insn 41 39 42 4 (set (reg:DI 26 s10 [orig:159 loop_len_46 ] [159])
+   (umin:DI (reg:DI 15 a5 [orig:201 _149 ] [201])
+ (reg:DI 14 a4 [276]))) 408 {*umindi3}
+ (expr_list:REG_EQUAL (umin:DI (reg:DI 15 a5 [orig:201 _149 ] [201])
+ (const_int 2 [0x2]))
+ (nil)))
+ The RTL_SSA uses of this instruction has 2 uses:
+ 1. (reg:DI 15 a5 [orig:201 _149 ] [201]) - twice.
+ 2. (reg:DI 14 a4 [276]) - once.
+
+ insn2 RTL:
+ (insn 38 353 351 4 (set (reg:DI 27 s11 [orig:160 loop_len_47 ] [160])
+   (umin:DI (reg:DI 15 a5 [orig:199 _146 ] [199])
+ (reg:DI 14 a4 [276]))) 408 {*umindi3}
+ (expr_list:REG_EQUAL (umin:DI (reg:DI 28 t3 [orig:200 ivtmp_147 ] [200])
+ (const_int 2 [0x2]))
+ (nil)))
+  The RTL_SSA uses of this instruction has 3 uses:
+ 1. (reg:DI 15 a5 [orig:199 _146 ] [199]) - once
+ 2. (reg:DI 14 a4 [276]) - once
+ 3. (reg:DI 28 t3 [orig:200 ivtmp_147 ] [200]) - once
+
+  Return false when insn1->uses ().size () != insn2->uses ().size ()
+  */
+  if (insn1->uses ().size () != insn2->uses ().size ())
+return false;
   for (size_t i = 0; i < insn1->uses ().size (); i++)
 if (insn1->uses ()[i] != insn2->uses ()[i])
   return false;
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109974.c 
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109974.c
new file mode 100644
index 000..06a8562ebab
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109974.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv_zbb -mabi=ilp32d --param 
riscv-autovec-preference=fixed-vlmax -O3" } */
+
+#include 
+
+void
+func (int8_t *__restrict x, int64_t *__restrict y, int n)
+{
+  for (int i = 0, j = 0; i < n; i++, j +=2 )
+  {
+x[i + 0] += 1;
+y[j + 0] += 1;
+y[j + 1] += 2;
+  }
+}
+
+/* { dg-final { scan-assembler {vsetvli} { target { no-opts "-O0" no-opts 
"-O1" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts "-funroll-loops" } } } } 
*/
-- 
2.36.3
 

Re: [PATCH] RISC-V: Fix VSETVL PASS ICE on SLP auto-vectorization

[Kito Cheng via Gcc-patches]

Ok, and just make sure this only appear for trunk, right?

juzhe.zh...@rivai.ai 於 2023年5月29日 週一，12:19寫道：

> This patch is fixing VSETVL PASS bug. Ok for trunk ?
>
>
>
> juzhe.zh...@rivai.ai
>
> From: juzhe.zhong
> Date: 2023-05-26 11:01
> To: gcc-patches
> CC: kito.cheng; kito.cheng; palmer; palmer; jeffreyalaw; rdapp.gcc;
> pan2.li; Juzhe-Zhong
> Subject: [PATCH] RISC-V: Fix VSETVL PASS ICE on SLP auto-vectorization
> From: Juzhe-Zhong 
>
> Fix bug reported here:
> https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109974
>
> PR target/109974
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-vsetvl.cc (source_equal_p): Fix ICE.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/vsetvl/pr109974.c: New test.
>
> ---
> gcc/config/riscv/riscv-vsetvl.cc  | 30 ++-
> .../gcc.target/riscv/rvv/vsetvl/pr109974.c| 17 +++
> 2 files changed, 46 insertions(+), 1 deletion(-)
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109974.c
>
> diff --git a/gcc/config/riscv/riscv-vsetvl.cc
> b/gcc/config/riscv/riscv-vsetvl.cc
> index 9847d649d1d..fe55f4ccd30 100644
> --- a/gcc/config/riscv/riscv-vsetvl.cc
> +++ b/gcc/config/riscv/riscv-vsetvl.cc
> @@ -1138,7 +1138,35 @@ source_equal_p (insn_info *insn1, insn_info *insn2)
>  return false;
>if (!rtx_equal_p (SET_SRC (single_set1), SET_SRC (single_set2)))
>  return false;
> -  gcc_assert (insn1->uses ().size () == insn2->uses ().size ());
> +  /* RTL_SSA uses include REG_NOTE. Consider this following case:
> +
> + insn1 RTL:
> + (insn 41 39 42 4 (set (reg:DI 26 s10 [orig:159 loop_len_46 ] [159])
> +   (umin:DI (reg:DI 15 a5 [orig:201 _149 ] [201])
> + (reg:DI 14 a4 [276]))) 408 {*umindi3}
> + (expr_list:REG_EQUAL (umin:DI (reg:DI 15 a5 [orig:201 _149 ] [201])
> + (const_int 2 [0x2]))
> + (nil)))
> + The RTL_SSA uses of this instruction has 2 uses:
> + 1. (reg:DI 15 a5 [orig:201 _149 ] [201]) - twice.
> + 2. (reg:DI 14 a4 [276]) - once.
> +
> + insn2 RTL:
> + (insn 38 353 351 4 (set (reg:DI 27 s11 [orig:160 loop_len_47 ] [160])
> +   (umin:DI (reg:DI 15 a5 [orig:199 _146 ] [199])
> + (reg:DI 14 a4 [276]))) 408 {*umindi3}
> + (expr_list:REG_EQUAL (umin:DI (reg:DI 28 t3 [orig:200 ivtmp_147 ] [200])
> + (const_int 2 [0x2]))
> + (nil)))
> +  The RTL_SSA uses of this instruction has 3 uses:
> + 1. (reg:DI 15 a5 [orig:199 _146 ] [199]) - once
> + 2. (reg:DI 14 a4 [276]) - once
> + 3. (reg:DI 28 t3 [orig:200 ivtmp_147 ] [200]) - once
> +
> +  Return false when insn1->uses ().size () != insn2->uses ().size ()
> +  */
> +  if (insn1->uses ().size () != insn2->uses ().size ())
> +return false;
>for (size_t i = 0; i < insn1->uses ().size (); i++)
>  if (insn1->uses ()[i] != insn2->uses ()[i])
>return false;
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109974.c
> b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109974.c
> new file mode 100644
> index 000..06a8562ebab
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109974.c
> @@ -0,0 +1,17 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv_zbb -mabi=ilp32d --param
> riscv-autovec-preference=fixed-vlmax -O3" } */
> +
> +#include 
> +
> +void
> +func (int8_t *__restrict x, int64_t *__restrict y, int n)
> +{
> +  for (int i = 0, j = 0; i < n; i++, j +=2 )
> +  {
> +x[i + 0] += 1;
> +y[j + 0] += 1;
> +y[j + 1] += 2;
> +  }
> +}
> +
> +/* { dg-final { scan-assembler {vsetvli} { target { no-opts "-O0" no-opts
> "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts "-funroll-loops" } }
> } } */
> --
> 2.36.3
>
>

[PATCH V2] RISC-V: Add floating-point to integer conversion RVV auto-vectorization support

[juzhe . zhong]

From: Juzhe-Zhong 

Even though we can't support floating-point operations which are depending
on FRM yet, (for example vfadd support is blocked) since the RVV intrinsic doc 
is not updated
and we can't support mode switching for this.

We can support floating-point to integer conversion now since it's not 
depending on FRM and
we don't need mode switching support for this ('rtz' conversions independent 
FRM).

gcc/ChangeLog:

* config/riscv/autovec.md (2): New pattern.
* config/riscv/iterators.md: New attribute.
* config/riscv/vector-iterators.md: New attribute.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-run.c: New test.
* gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-rv32gcv.c: New 
test.
* gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-rv64gcv.c: New 
test.
* gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-template.h: New 
test.

---
 gcc/config/riscv/autovec.md   | 23 
 gcc/config/riscv/iterators.md |  4 +-
 gcc/config/riscv/vector-iterators.md  |  5 ++
 .../rvv/autovec/conversions/vfcvt_rtz-run.c   | 52 +++
 .../autovec/conversions/vfcvt_rtz-rv32gcv.c   |  6 +++
 .../autovec/conversions/vfcvt_rtz-rv64gcv.c   |  6 +++
 .../autovec/conversions/vfcvt_rtz-template.h  | 15 ++
 7 files changed, 110 insertions(+), 1 deletion(-)
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-run.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-rv32gcv.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-rv64gcv.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-template.h

diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index b24867ae4d0..3989ffb26ee 100644
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -478,6 +478,29 @@
   DONE;
 })
 
+;; =
+;; == Conversions
+;; =
+
+;; -
+;;  [INT<-FP] Conversions
+;; -
+;; Includes:
+;; - vfcvt.rtz.xu.f.v
+;; - vfcvt.rtz.x.f.v
+;; -
+
+(define_expand "2"
+  [(set (match_operand: 0 "register_operand")
+   (any_fix:
+ (match_operand:VF 1 "register_operand")))]
+  "TARGET_VECTOR"
+{
+  insn_code icode = code_for_pred (, mode);
+  riscv_vector::emit_vlmax_insn (icode, riscv_vector::RVV_UNOP, operands);
+  DONE;
+})
+
 ;; =
 ;; == Unary arithmetic
 ;; =
diff --git a/gcc/config/riscv/iterators.md b/gcc/config/riscv/iterators.md
index 8afe98e4410..d374a10810c 100644
--- a/gcc/config/riscv/iterators.md
+++ b/gcc/config/riscv/iterators.md
@@ -225,7 +225,9 @@
 (ss_minus "sssub")
 (us_minus "ussub")
 (sign_extend "extend")
-(zero_extend "zero_extend")])
+(zero_extend "zero_extend")
+(fix "fix_trunc")
+(unsigned_fix "fixuns_trunc")])
 
 ;;  code attributes
 (define_code_attr or_optab [(ior "ior")
diff --git a/gcc/config/riscv/vector-iterators.md 
b/gcc/config/riscv/vector-iterators.md
index 70fb5b80b1b..937ec3c7f67 100644
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -1208,6 +1208,11 @@
   (VNx1DF "VNx1DI") (VNx2DF "VNx2DI") (VNx4DF "VNx4DI") (VNx8DF "VNx8DI") 
(VNx16DF "VNx16DI")
 ])
 
+(define_mode_attr vconvert [
+  (VNx1SF "vnx1si") (VNx2SF "vnx2si") (VNx4SF "vnx4si") (VNx8SF "vnx8si") 
(VNx16SF "vnx16si") (VNx32SF "vnx32si")
+  (VNx1DF "vnx1di") (VNx2DF "vnx2di") (VNx4DF "vnx4di") (VNx8DF "vnx8di") 
(VNx16DF "vnx16di")
+])
+
 (define_mode_attr VNCONVERT [
   (VNx1SF "VNx1HI") (VNx2SF "VNx2HI") (VNx4SF "VNx4HI") (VNx8SF "VNx8HI") 
(VNx16SF "VNx16HI") (VNx32SF "VNx32HI")
   (VNx1DI "VNx1SF") (VNx2DI "VNx2SF") (VNx4DI "VNx4SF") (VNx8DI "VNx8SF") 
(VNx16DI "VNx16SF")
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-run.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-run.c
new file mode 100644
index 000..05f8d911ad7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-run.c
@@ -0,0 +1,52 @@
+/* { dg-do run { target { riscv_vector } } } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model 
--param=riscv-autovec-preference=scalable" } */
+
+#include "vfcvt_rtz-template.h"
+
+#define RUN(TYPE1, TYPE2, NUM)   

RE: Re: [PATCH V2] RISC-V: Add RVV FMA auto-vectorization support

[Li, Pan2 via Gcc-patches]

Committed with 2 patches, thanks Kito.

Pan

From: juzhe.zh...@rivai.ai 
Sent: Monday, May 29, 2023 11:19 AM
To: kito.cheng 
Cc: gcc-patches ; Kito.cheng ; 
palmer ; Robin Dapp ; jeffreyalaw 
; Li, Pan2 
Subject: Re: Re: [PATCH V2] RISC-V: Add RVV FMA auto-vectorization support

This is existing bug in GCC 13. I think I should split into 2 patches.


juzhe.zh...@rivai.ai

From: Kito Cheng
Date: 2023-05-29 11:17
To: juzhe.zhong
CC: gcc-patches; 
kito.cheng; palmer; 
rdapp.gcc; 
jeffreyalaw; pan2.li
Subject: Re: [PATCH V2] RISC-V: Add RVV FMA auto-vectorization support
LGTM, but with one question.

On Fri, May 26, 2023 at 7:36 PM 
mailto:juzhe.zh...@rivai.ai>> wrote:
>
> From: Juzhe-Zhong mailto:juzhe.zh...@rivai.ai>>
>
> This patch support FMA auto-vectorization pattern.
> 1. Let's RA decide vmacc or vmadd.
> 2. Fix bug of vector.md which generate incorrect information to VSETVL
>PASS when testing ternop-3.c.

Does this bug also appear in GCC 13? or this is new bug introduced at trunk

RE: [PATCH] RISC-V: Remove redundant printf of abs-run.c

[Li, Pan2 via Gcc-patches]

Committed, thanks Kito.

Pan

-Original Message-
From: Gcc-patches  On Behalf 
Of Kito Cheng via Gcc-patches
Sent: Monday, May 29, 2023 11:43 AM
To: 钟居哲 
Cc: GCC Patches ; Kito Cheng ; 
Palmer Dabbelt ; Palmer Dabbelt ; Jeff 
Law ; Robin Dapp 
Subject: Re: [PATCH] RISC-V: Remove redundant printf of abs-run.c

Ok

 於 2023年5月29日 週一 11:39 寫道：

> From: Juzhe-Zhong 
>
> Notice that this testcase cause unexpected fail:
> FAIL: gcc.target/riscv/rvv/autovec/unop/abs-run.c (test for excess 
> errors) Excess errors:
> /work/home/jzzhong/work/rvv-opensource/software/host/toolchain/gcc/riscv-gcc/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-run.c:22:7:
> warning: implicit declaration of function 'printf'
> [-Wimplicit-function-declaration]
> /work/home/jzzhong/work/rvv-opensource/software/host/toolchain/gcc/riscv-gcc/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-run.c:22:7:
> warning: incompatible implicit declaration of built-in function 'printf'
> [-Wbuiltin-declaration-mismatch]
> /work/home/jzzhong/work/rvv-opensource/software/host/toolchain/gcc/riscv-gcc/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-run.c:22:7:
> warning: incompatible implicit declaration of built-in function 'printf'
> [-Wbuiltin-declaration-mismatch]
> /work/home/jzzhong/work/rvv-opensource/software/host/toolchain/gcc/riscv-gcc/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-run.c:22:7:
> warning: incompatible implicit declaration of built-in function 'printf'
> [-Wbuiltin-declaration-mismatch]
> /work/home/jzzhong/work/rvv-opensource/software/host/toolchain/gcc/riscv-gcc/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-run.c:22:7:
> warning: incompatible implicit declaration of built-in function 'printf'
> [-Wbuiltin-declaration-mismatch]
>
> spawn /work/home/jzzhong/work/rvv-opensource/output/sim/bin/spike
> --isa=RV64GCVZfh
> /work/home/jzzhong/work/rvv-opensource/output/sim/riscv64-rivai-elf/bi
> n/pk
> ./abs-run.exe^M
> bbl loader^M^M
> 0 0 -64^M
> 1 63 -63^M
> 2 2 -62^M
> 3 61 -61^M
> 4 4 -60^M
> 5 59 -59^M
> 6 6 -58^M
> 7 57 -57^M
> 8 8 -56^M
> 9 55 -55^M
> 10 10 -54^M
> 11 53 -53^M
> 12 12 -52^M
> 13 51 -51^M
>
> Remove printf since it's unnecessary.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/autovec/unop/abs-run.c: Remove 
> redundant printf.
>
> ---
>  gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-run.c | 1 -
>  1 file changed, 1 deletion(-)
>
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-run.c
> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-run.c
> index 7404dbe037e..d864b54229b 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-run.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-run.c
> @@ -19,7 +19,6 @@
>vabs_##TYPE (a##TYPE, a##TYPE, SZ);  \
>for (int i = 0; i < SZ; i++) \
>  {  \
> -  printf ("%d %d %d\n", i, a##TYPE[i], i - 64);\
>if (i & 1)   \
> assert (a##TYPE[i] == abs (i - 64));\
>else \
> --
> 2.36.3
>
>

[committed 1/2] RISC-V: Fix ternary instruction attribute bug

[Pan Li via Gcc-patches]

From: Juzhe-Zhong 

Fix bug of vector.md which generate incorrect information to
VSETVL PASS when testing FMA auto vectorization ternop-3.c.

Signed-off-by: Juzhe-Zhong 

gcc/ChangeLog:

* config/riscv/vector.md: Fix vimuladd instruction bug.
---
 gcc/config/riscv/vector.md | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 15f66efaa48..cd696da5d89 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -388,7 +388,7 @@ (define_attr "avl_type" ""
 (symbol_ref "INTVAL (operands[7])"))
 
 (eq_attr "type" "vldux,vldox,vialu,vshift,viminmax,vimul,vidiv,vsalu,\
- viwalu,viwmul,vnshift,vimuladd,vaalu,vsmul,vsshift,\
+ viwalu,viwmul,vnshift,vaalu,vsmul,vsshift,\
  
vnclip,vicmp,vfalu,vfmul,vfminmax,vfdiv,vfwalu,vfwmul,\
  vfsgnj,vfcmp,vfmuladd,vslideup,vslidedown,vislide1up,\
  
vislide1down,vfslide1up,vfslide1down,vgather,viwmuladd,vfwmuladd,\
-- 
2.34.1

[committed 2/2] RISC-V: Add RVV FMA auto-vectorization support

[Pan Li via Gcc-patches]

From: Juzhe-Zhong 

This patch support FMA auto-vectorization pattern. Let's RA decide
vmacc or vmadd.

Signed-off-by: Juzhe-Zhong 

gcc/ChangeLog:

* config/riscv/autovec.md (fma4): New pattern.
(*fma): Ditto.
* config/riscv/riscv-protos.h (enum insn_type): New enum.
(emit_vlmax_ternary_insn): New function.
* config/riscv/riscv-v.cc (emit_vlmax_ternary_insn): Ditto.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/rvv.exp: Add ternary tests
* gcc.target/riscv/rvv/autovec/ternop/ternop-1.c: New test.
* gcc.target/riscv/rvv/autovec/ternop/ternop-2.c: New test.
* gcc.target/riscv/rvv/autovec/ternop/ternop-3.c: New test.
* gcc.target/riscv/rvv/autovec/ternop/ternop_run-1.c: New test.
* gcc.target/riscv/rvv/autovec/ternop/ternop_run-2.c: New test.
* gcc.target/riscv/rvv/autovec/ternop/ternop_run-3.c: New test.
---
 gcc/config/riscv/autovec.md   |  65 +++
 gcc/config/riscv/riscv-protos.h   |   2 +
 gcc/config/riscv/riscv-v.cc   |  20 
 .../riscv/rvv/autovec/ternop/ternop-1.c   |  28 +
 .../riscv/rvv/autovec/ternop/ternop-2.c   |  34 ++
 .../riscv/rvv/autovec/ternop/ternop-3.c   |  33 ++
 .../riscv/rvv/autovec/ternop/ternop_run-1.c   |  84 ++
 .../riscv/rvv/autovec/ternop/ternop_run-2.c   | 104 ++
 .../riscv/rvv/autovec/ternop/ternop_run-3.c   | 104 ++
 gcc/testsuite/gcc.target/riscv/rvv/rvv.exp|   2 +
 10 files changed, 476 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-3.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-1.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-2.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-3.c

diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index b24867ae4d0..0314e7587d0 100644
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -518,3 +518,68 @@ (define_expand "abs2"
   riscv_vector::RVV_UNOP_MU, ops);
   DONE;
 })
+
+;; =
+;; == Ternary arithmetic
+;; =
+
+;; -
+;;  [INT] VMACC and VMADD
+;; -
+;; Includes:
+;; - vmacc
+;; - vmadd
+;; -
+
+;; We can't expand FMA for the following reasons:
+;; 1. Before RA, we don't know which multiply-add instruction is the ideal one.
+;;The vmacc is the ideal instruction when operands[3] overlaps operands[0].
+;;The vmadd is the ideal instruction when operands[1|2] overlaps 
operands[0].
+;; 2. According to vector.md, the multiply-add patterns has 'merge' operand 
which
+;;is the operands[5]. Since operands[5] should overlap operands[0], this 
operand
+;;should be allocated the same regno as operands[1|2|3].
+;; 3. The 'merge' operand is always a real merge operand and we don't allow 
undefined
+;;operand.
+;; 4. The operation of FMA pattern needs VLMAX vsetlvi which needs a VL 
operand.
+;;
+;; In this situation, we design the codegen of FMA as follows:
+;; 1. clobber a scratch in the expand pattern of FMA.
+;; 2. Let's RA decide which input operand (operands[1|2|3]) overlap 
operands[0].
+;; 3. Generate instructions (vmacc or vmadd) according to the register 
allocation
+;;result after reload_completed.
+(define_expand "fma4"
+  [(parallel
+[(set (match_operand:VI 0 "register_operand" "=vr")
+ (plus:VI
+   (mult:VI
+ (match_operand:VI 1 "register_operand" " vr")
+ (match_operand:VI 2 "register_operand" " vr"))
+   (match_operand:VI 3 "register_operand"   " vr")))
+ (clobber (match_scratch:SI 4))])]
+  "TARGET_VECTOR"
+  {})
+
+(define_insn_and_split "*fma"
+  [(set (match_operand:VI 0 "register_operand" "=vr, vr, ?&vr")
+   (plus:VI
+ (mult:VI
+   (match_operand:VI 1 "register_operand" " %0, vr,   vr")
+   (match_operand:VI 2 "register_operand" " vr, vr,   vr"))
+ (match_operand:VI 3 "register_operand"   " vr,  0,   vr")))
+   (clobber (match_scratch:SI 4 "=r,r,r"))]
+  "TARGET_VECTOR"
+  "#"
+  "&& reload_completed"
+  [(const_int 0)]
+  {
+PUT_MODE (operands[4], Pmode);
+riscv_vector::emit_vlmax_vsetvl (mode, operands[4]);
+if (which_alternative == 2)
+  emit_insn (gen_rtx_SET (operands[0], operands[3]));
+rtx ops[] = {operands[0], ope

RE: [PATCH] RISC-V: Eliminate the magic number in riscv-v.cc

[Li, Pan2 via Gcc-patches]

Thanks Kito, will commit this after the vec_init repeated sequence patch.

Pan

-Original Message-
From: Kito Cheng  
Sent: Monday, May 29, 2023 10:20 AM
To: Li, Pan2 
Cc: Robin Dapp ; gcc-patches@gcc.gnu.org; 
juzhe.zh...@rivai.ai; kito.ch...@sifive.com; Wang, Yanzhang 

Subject: Re: [PATCH] RISC-V: Eliminate the magic number in riscv-v.cc

LGTM

On Fri, May 26, 2023 at 2:32 PM Li, Pan2 via Gcc-patches 
 wrote:
>
> Thanks Robin.
>
> Sorry for not mentioned that it depends on another patch 
> https://gcc.gnu.org/pipermail/gcc-patches/2023-May/619536.html, which is in 
> the reviewing queue.
>
> Yes, totally agree we can remove the comments for some parameters excepts the 
> Boolean ones, as well as the term data related. I can file another PATCH to 
> make it happen due to it is another thing besides magic number elimination.
>
> Pan
>
> -Original Message-
> From: Robin Dapp 
> Sent: Friday, May 26, 2023 2:24 PM
> To: Li, Pan2 ; gcc-patches@gcc.gnu.org
> Cc: rdapp@gmail.com; juzhe.zh...@rivai.ai; kito.ch...@sifive.com; 
> Wang, Yanzhang 
> Subject: Re: [PATCH] RISC-V: Eliminate the magic number in riscv-v.cc
>
> Hi,
>
> > This patch would like to remove the magic number in the riscv-v.cc, 
> > and align the same value to one macro.
>
> > diff --git a/gcc/config/riscv/riscv-v.cc 
> > b/gcc/config/riscv/riscv-v.cc index 458020ce0a1..20b589bf51b 100644
> > --- a/gcc/config/riscv/riscv-v.cc
> > +++ b/gcc/config/riscv/riscv-v.cc
> > @@ -351,13 +351,15 @@ emit_vlmax_insn (unsigned icode, int op_num, 
> > rtx *ops, rtx vl)  {
> >machine_mode data_mode = GET_MODE (ops[0]);
> >machine_mode mask_mode = get_mask_mode (data_mode).require ();
> > -  /* We have a maximum of 11 operands for RVV instruction patterns 
> > according to
> > -   * vector.md.  */
> > -  insn_expander<11> e (/*OP_NUM*/ op_num, /*HAS_DEST_P*/ true,
> > -/*FULLY_UNMASKED_P*/ true,
> > -/*USE_REAL_MERGE_P*/ false, /*HAS_AVL_P*/ true,
> > -/*VLMAX_P*/ true,
> > -/*DEST_MODE*/ data_mode, /*MASK_MODE*/ mask_mode);
> > +  insn_expander e (/*OP_NUM*/ op_num,
> > +   /*HAS_DEST_P*/ true,
> > +   /*FULLY_UNMASKED_P*/ true,
> > +   /*USE_REAL_MERGE_P*/ false,
> > +   /*HAS_AVL_P*/ true,
> > +   /*VLMAX_P*/ true,
> > +   /*DEST_MODE*/ data_mode,
> > +   /*MASK_MODE*/ mask_mode);
>
> I don't see where RVV_INSN_OPERANDS_MAX is defined.  Maybe you missed to 
> include that hunk?
>
> Apart from that maybe you could also remove the comments for dest_mode, 
> mask_mode and op_num?  I think the general "custom" is to just add them for 
> bool arguments and name non-bool arguments descriptively.  Here that could 
> mean renaming data_mode to dest_mode where appropriate (usually data_mode is 
> used to distinguish between data mode and comparison mode in conditionals, 
> not in regular insns where everything is "data").
>
> Regards
>  Robin

Re: Re: [PATCH] RISC-V: Fix VSETVL PASS ICE on SLP auto-vectorization

[juzhe.zh...@rivai.ai]

Yes.



juzhe.zh...@rivai.ai
 
From: Kito Cheng
Date: 2023-05-29 12:36
To: juzhe.zh...@rivai.ai
CC: Kito.cheng; Robin Dapp; gcc-patches; jeffreyalaw; palmer; palmer; pan2.li
Subject: Re: [PATCH] RISC-V: Fix VSETVL PASS ICE on SLP auto-vectorization
Ok, and just make sure this only appear for trunk, right?

juzhe.zh...@rivai.ai 於 2023年5月29日 週一，12:19寫道：
This patch is fixing VSETVL PASS bug. Ok for trunk ?



juzhe.zh...@rivai.ai

From: juzhe.zhong
Date: 2023-05-26 11:01
To: gcc-patches
CC: kito.cheng; kito.cheng; palmer; palmer; jeffreyalaw; rdapp.gcc; pan2.li; 
Juzhe-Zhong
Subject: [PATCH] RISC-V: Fix VSETVL PASS ICE on SLP auto-vectorization
From: Juzhe-Zhong 

Fix bug reported here:
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109974

PR target/109974

gcc/ChangeLog:

* config/riscv/riscv-vsetvl.cc (source_equal_p): Fix ICE.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/vsetvl/pr109974.c: New test.

---
gcc/config/riscv/riscv-vsetvl.cc  | 30 ++-
.../gcc.target/riscv/rvv/vsetvl/pr109974.c| 17 +++
2 files changed, 46 insertions(+), 1 deletion(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109974.c

diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc
index 9847d649d1d..fe55f4ccd30 100644
--- a/gcc/config/riscv/riscv-vsetvl.cc
+++ b/gcc/config/riscv/riscv-vsetvl.cc
@@ -1138,7 +1138,35 @@ source_equal_p (insn_info *insn1, insn_info *insn2)
 return false;
   if (!rtx_equal_p (SET_SRC (single_set1), SET_SRC (single_set2)))
 return false;
-  gcc_assert (insn1->uses ().size () == insn2->uses ().size ());
+  /* RTL_SSA uses include REG_NOTE. Consider this following case:
+
+ insn1 RTL:
+ (insn 41 39 42 4 (set (reg:DI 26 s10 [orig:159 loop_len_46 ] [159])
+   (umin:DI (reg:DI 15 a5 [orig:201 _149 ] [201])
+ (reg:DI 14 a4 [276]))) 408 {*umindi3}
+ (expr_list:REG_EQUAL (umin:DI (reg:DI 15 a5 [orig:201 _149 ] [201])
+ (const_int 2 [0x2]))
+ (nil)))
+ The RTL_SSA uses of this instruction has 2 uses:
+ 1. (reg:DI 15 a5 [orig:201 _149 ] [201]) - twice.
+ 2. (reg:DI 14 a4 [276]) - once.
+
+ insn2 RTL:
+ (insn 38 353 351 4 (set (reg:DI 27 s11 [orig:160 loop_len_47 ] [160])
+   (umin:DI (reg:DI 15 a5 [orig:199 _146 ] [199])
+ (reg:DI 14 a4 [276]))) 408 {*umindi3}
+ (expr_list:REG_EQUAL (umin:DI (reg:DI 28 t3 [orig:200 ivtmp_147 ] [200])
+ (const_int 2 [0x2]))
+ (nil)))
+  The RTL_SSA uses of this instruction has 3 uses:
+ 1. (reg:DI 15 a5 [orig:199 _146 ] [199]) - once
+ 2. (reg:DI 14 a4 [276]) - once
+ 3. (reg:DI 28 t3 [orig:200 ivtmp_147 ] [200]) - once
+
+  Return false when insn1->uses ().size () != insn2->uses ().size ()
+  */
+  if (insn1->uses ().size () != insn2->uses ().size ())
+return false;
   for (size_t i = 0; i < insn1->uses ().size (); i++)
 if (insn1->uses ()[i] != insn2->uses ()[i])
   return false;
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109974.c 
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109974.c
new file mode 100644
index 000..06a8562ebab
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109974.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv_zbb -mabi=ilp32d --param 
riscv-autovec-preference=fixed-vlmax -O3" } */
+
+#include 
+
+void
+func (int8_t *__restrict x, int64_t *__restrict y, int n)
+{
+  for (int i = 0, j = 0; i < n; i++, j +=2 )
+  {
+x[i + 0] += 1;
+y[j + 0] += 1;
+y[j + 1] += 2;
+  }
+}
+
+/* { dg-final { scan-assembler {vsetvli} { target { no-opts "-O0" no-opts 
"-O1" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts "-funroll-loops" } } } } 
*/
-- 
2.36.3

Re: [PATCH] LoongArch: Set 4 * (issue rate) as the default for -falign-functions and -falign-loops

[Xi Ruoyao via Gcc-patches]

On Tue, 2023-04-18 at 21:06 +0800, Lulu Cheng wrote:
> Hi, ruoyao:
> 
> Thank you so much for making this submission. But we are testing the 
> impact of these two alignment parameters
> 
> (also including -falign-jumps and -falign-lables ) on performance. So 
> before the result comes out, this patch will
> 
> not be merged into the main branch for the time being.

Hi!

Is there an estimate when the benchmark will be done?  If it will be
done soon I'll wait for the result before performing a full system
rebuild, otherwise I'll use my gut feeling to specify a -falign-
functions= value for the build :).

-- 
Xi Ruoyao 
School of Aerospace Science and Technology, Xidian University

RE: Re: [PATCH] RISC-V: Fix VSETVL PASS ICE on SLP auto-vectorization

[Li, Pan2 via Gcc-patches]

Committed, thanks Kito.

Pan

From: juzhe.zh...@rivai.ai 
Sent: Monday, May 29, 2023 2:02 PM
To: kito.cheng 
Cc: Kito.cheng ; Robin Dapp ; 
gcc-patches ; jeffreyalaw ; 
palmer ; palmer ; Li, Pan2 

Subject: Re: Re: [PATCH] RISC-V: Fix VSETVL PASS ICE on SLP auto-vectorization

Yes.


juzhe.zh...@rivai.ai

From: Kito Cheng
Date: 2023-05-29 12:36
To: juzhe.zh...@rivai.ai
CC: Kito.cheng; Robin 
Dapp; gcc-patches; 
jeffreyalaw; palmer; 
palmer; pan2.li
Subject: Re: [PATCH] RISC-V: Fix VSETVL PASS ICE on SLP auto-vectorization
Ok, and just make sure this only appear for trunk, right?

juzhe.zh...@rivai.ai 
mailto:juzhe.zh...@rivai.ai>>於 2023年5月29日 週一，12:19寫道：
This patch is fixing VSETVL PASS bug. Ok for trunk ?



juzhe.zh...@rivai.ai

From: juzhe.zhong
Date: 2023-05-26 11:01
To: gcc-patches
CC: kito.cheng; kito.cheng; palmer; palmer; jeffreyalaw; rdapp.gcc; 
pan2.li; Juzhe-Zhong
Subject: [PATCH] RISC-V: Fix VSETVL PASS ICE on SLP auto-vectorization
From: Juzhe-Zhong mailto:juzhe.zh...@rivai.ai>>

Fix bug reported here:
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109974

PR target/109974

gcc/ChangeLog:

* config/riscv/riscv-vsetvl.cc (source_equal_p): Fix ICE.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/vsetvl/pr109974.c: New test.

---
gcc/config/riscv/riscv-vsetvl.cc  | 30 ++-
.../gcc.target/riscv/rvv/vsetvl/pr109974.c| 17 +++
2 files changed, 46 insertions(+), 1 deletion(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109974.c

diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc
index 9847d649d1d..fe55f4ccd30 100644
--- a/gcc/config/riscv/riscv-vsetvl.cc
+++ b/gcc/config/riscv/riscv-vsetvl.cc
@@ -1138,7 +1138,35 @@ source_equal_p (insn_info *insn1, insn_info *insn2)
 return false;
   if (!rtx_equal_p (SET_SRC (single_set1), SET_SRC (single_set2)))
 return false;
-  gcc_assert (insn1->uses ().size () == insn2->uses ().size ());
+  /* RTL_SSA uses include REG_NOTE. Consider this following case:
+
+ insn1 RTL:
+ (insn 41 39 42 4 (set (reg:DI 26 s10 [orig:159 loop_len_46 ] [159])
+   (umin:DI (reg:DI 15 a5 [orig:201 _149 ] [201])
+ (reg:DI 14 a4 [276]))) 408 {*umindi3}
+ (expr_list:REG_EQUAL (umin:DI (reg:DI 15 a5 [orig:201 _149 ] [201])
+ (const_int 2 [0x2]))
+ (nil)))
+ The RTL_SSA uses of this instruction has 2 uses:
+ 1. (reg:DI 15 a5 [orig:201 _149 ] [201]) - twice.
+ 2. (reg:DI 14 a4 [276]) - once.
+
+ insn2 RTL:
+ (insn 38 353 351 4 (set (reg:DI 27 s11 [orig:160 loop_len_47 ] [160])
+   (umin:DI (reg:DI 15 a5 [orig:199 _146 ] [199])
+ (reg:DI 14 a4 [276]))) 408 {*umindi3}
+ (expr_list:REG_EQUAL (umin:DI (reg:DI 28 t3 [orig:200 ivtmp_147 ] [200])
+ (const_int 2 [0x2]))
+ (nil)))
+  The RTL_SSA uses of this instruction has 3 uses:
+ 1. (reg:DI 15 a5 [orig:199 _146 ] [199]) - once
+ 2. (reg:DI 14 a4 [276]) - once
+ 3. (reg:DI 28 t3 [orig:200 ivtmp_147 ] [200]) - once
+
+  Return false when insn1->uses ().size () != insn2->uses ().size ()
+  */
+  if (insn1->uses ().size () != insn2->uses ().size ())
+return false;
   for (size_t i = 0; i < insn1->uses ().size (); i++)
 if (insn1->uses ()[i] != insn2->uses ()[i])
   return false;
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109974.c 
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109974.c
new file mode 100644
index 000..06a8562ebab
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109974.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv_zbb -mabi=ilp32d --param 
riscv-autovec-preference=fixed-vlmax -O3" } */
+
+#include 
+
+void
+func (int8_t *__restrict x, int64_t *__restrict y, int n)
+{
+  for (int i = 0, j = 0; i < n; i++, j +=2 )
+  {
+x[i + 0] += 1;
+y[j + 0] += 1;
+y[j + 1] += 2;
+  }
+}
+
+/* { dg-final { scan-assembler {vsetvli} { target { no-opts "-O0" no-opts 
"-O1" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts "-funroll-loops" } } } } 
*/
--
2.36.3

[PATCH] RISC-V: Add RVV FNMA auto-vectorization support

[juzhe . zhong]

From: Juzhe-Zhong 

Like FMA, Add FNMA auto-vectorization support.

gcc/ChangeLog:

* config/riscv/autovec.md (fnma4): New pattern.
(*fnma): Ditto.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/ternop/ternop-4.c: New test.
* gcc.target/riscv/rvv/autovec/ternop/ternop-5.c: New test.
* gcc.target/riscv/rvv/autovec/ternop/ternop-6.c: New test.
* gcc.target/riscv/rvv/autovec/ternop/ternop_run-4.c: New test.
* gcc.target/riscv/rvv/autovec/ternop/ternop_run-5.c: New test.
* gcc.target/riscv/rvv/autovec/ternop/ternop_run-6.c: New test.

---
 gcc/config/riscv/autovec.md   |  45 
 .../riscv/rvv/autovec/ternop/ternop-4.c   |  28 +
 .../riscv/rvv/autovec/ternop/ternop-5.c   |  34 ++
 .../riscv/rvv/autovec/ternop/ternop-6.c   |  33 ++
 .../riscv/rvv/autovec/ternop/ternop_run-4.c   |  84 ++
 .../riscv/rvv/autovec/ternop/ternop_run-5.c   | 104 ++
 .../riscv/rvv/autovec/ternop/ternop_run-6.c   | 104 ++
 7 files changed, 432 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-4.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-5.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-6.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-4.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-5.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-6.c

diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index eff3e484fb4..20004a8af27 100644
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -606,3 +606,48 @@
   }
   [(set_attr "type" "vimuladd")
(set_attr "mode" "")])
+
+;; -
+;;  [INT] VMACC and VMADD
+;; -
+;; Includes:
+;; - vnmsac
+;; - vnmsub
+;; -
+
+(define_expand "fnma4"
+  [(parallel
+[(set (match_operand:VI 0 "register_operand" "=vr")
+ (minus:VI
+   (match_operand:VI 3 "register_operand"   " vr")
+   (mult:VI
+ (match_operand:VI 1 "register_operand" " vr")
+ (match_operand:VI 2 "register_operand" " vr"
+ (clobber (match_scratch:SI 4))])]
+  "TARGET_VECTOR"
+  {})
+
+(define_insn_and_split "*fnma"
+  [(set (match_operand:VI 0 "register_operand" "=vr, vr, ?&vr")
+   (minus:VI
+ (match_operand:VI 3 "register_operand"   " vr,  0,   vr")
+ (mult:VI
+   (match_operand:VI 1 "register_operand" " %0, vr,   vr")
+   (match_operand:VI 2 "register_operand" " vr, vr,   vr"
+   (clobber (match_scratch:SI 4 "=r,r,r"))]
+  "TARGET_VECTOR"
+  "#"
+  "&& reload_completed"
+  [(const_int 0)]
+  {
+PUT_MODE (operands[4], Pmode);
+riscv_vector::emit_vlmax_vsetvl (mode, operands[4]);
+if (which_alternative == 2)
+  emit_insn (gen_rtx_SET (operands[0], operands[3]));
+rtx ops[] = {operands[0], operands[1], operands[2], operands[3], 
operands[0]};
+riscv_vector::emit_vlmax_ternary_insn (code_for_pred_minus_mul 
(mode),
+  riscv_vector::RVV_TERNOP, ops, 
operands[4]);
+DONE;
+  }
+  [(set_attr "type" "vimuladd")
+   (set_attr "mode" "")])
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-4.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-4.c
new file mode 100644
index 000..22d11de89a1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-4.c
@@ -0,0 +1,28 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d 
--param=riscv-autovec-preference=scalable" } */
+
+#include 
+
+#define TEST_TYPE(TYPE)
\
+  __attribute__ ((noipa)) void ternop_##TYPE (TYPE *__restrict dst,
\
+ TYPE *__restrict a,  \
+ TYPE *__restrict b, int n)   \
+  {
\
+for (int i = 0; i < n; i++)
\
+  dst[i] += -(a[i] * b[i]);
\
+  }
+
+#define TEST_ALL() 
\
+  TEST_TYPE (int8_t)   
\
+  TEST_TYPE (uint8_t)  
\
+  TEST_TYPE (int16_t)  
\
+  TEST_TYPE (uint16_t) 
\
+  TEST_TYPE (int3

[PATCH V2] RISC-V: Add RVV FNMA auto-vectorization support

[juzhe . zhong]

From: Juzhe-Zhong 

Like FMA, Add FNMA (VNMSAC or VNMSUB) auto-vectorization support.

gcc/ChangeLog:

* config/riscv/autovec.md (fnma4): New pattern.
(*fnma): Ditto.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/ternop/ternop-4.c: New test.
* gcc.target/riscv/rvv/autovec/ternop/ternop-5.c: New test.
* gcc.target/riscv/rvv/autovec/ternop/ternop-6.c: New test.
* gcc.target/riscv/rvv/autovec/ternop/ternop_run-4.c: New test.
* gcc.target/riscv/rvv/autovec/ternop/ternop_run-5.c: New test.
* gcc.target/riscv/rvv/autovec/ternop/ternop_run-6.c: New test.

---
 gcc/config/riscv/autovec.md   |  45 
 .../riscv/rvv/autovec/ternop/ternop-4.c   |  28 +
 .../riscv/rvv/autovec/ternop/ternop-5.c   |  34 ++
 .../riscv/rvv/autovec/ternop/ternop-6.c   |  33 ++
 .../riscv/rvv/autovec/ternop/ternop_run-4.c   |  84 ++
 .../riscv/rvv/autovec/ternop/ternop_run-5.c   | 104 ++
 .../riscv/rvv/autovec/ternop/ternop_run-6.c   | 104 ++
 7 files changed, 432 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-4.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-5.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-6.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-4.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-5.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-6.c

diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index eff3e484fb4..a1028d71467 100644
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -606,3 +606,48 @@
   }
   [(set_attr "type" "vimuladd")
(set_attr "mode" "")])
+
+;; -
+;;  [INT] VNMSAC and VNMSUB
+;; -
+;; Includes:
+;; - vnmsac
+;; - vnmsub
+;; -
+
+(define_expand "fnma4"
+  [(parallel
+[(set (match_operand:VI 0 "register_operand" "=vr")
+ (minus:VI
+   (match_operand:VI 3 "register_operand"   " vr")
+   (mult:VI
+ (match_operand:VI 1 "register_operand" " vr")
+ (match_operand:VI 2 "register_operand" " vr"
+ (clobber (match_scratch:SI 4))])]
+  "TARGET_VECTOR"
+  {})
+
+(define_insn_and_split "*fnma"
+  [(set (match_operand:VI 0 "register_operand" "=vr, vr, ?&vr")
+   (minus:VI
+ (match_operand:VI 3 "register_operand"   " vr,  0,   vr")
+ (mult:VI
+   (match_operand:VI 1 "register_operand" " %0, vr,   vr")
+   (match_operand:VI 2 "register_operand" " vr, vr,   vr"
+   (clobber (match_scratch:SI 4 "=r,r,r"))]
+  "TARGET_VECTOR"
+  "#"
+  "&& reload_completed"
+  [(const_int 0)]
+  {
+PUT_MODE (operands[4], Pmode);
+riscv_vector::emit_vlmax_vsetvl (mode, operands[4]);
+if (which_alternative == 2)
+  emit_insn (gen_rtx_SET (operands[0], operands[3]));
+rtx ops[] = {operands[0], operands[1], operands[2], operands[3], 
operands[0]};
+riscv_vector::emit_vlmax_ternary_insn (code_for_pred_minus_mul 
(mode),
+  riscv_vector::RVV_TERNOP, ops, 
operands[4]);
+DONE;
+  }
+  [(set_attr "type" "vimuladd")
+   (set_attr "mode" "")])
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-4.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-4.c
new file mode 100644
index 000..22d11de89a1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-4.c
@@ -0,0 +1,28 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d 
--param=riscv-autovec-preference=scalable" } */
+
+#include 
+
+#define TEST_TYPE(TYPE)
\
+  __attribute__ ((noipa)) void ternop_##TYPE (TYPE *__restrict dst,
\
+ TYPE *__restrict a,  \
+ TYPE *__restrict b, int n)   \
+  {
\
+for (int i = 0; i < n; i++)
\
+  dst[i] += -(a[i] * b[i]);
\
+  }
+
+#define TEST_ALL() 
\
+  TEST_TYPE (int8_t)   
\
+  TEST_TYPE (uint8_t)  
\
+  TEST_TYPE (int16_t)  
\
+  TEST_TYPE (uint16_t)