[PATCH] testsuite: Require fgraphite effective target for pr106737.c test [PR106737]
On Thu, Aug 25, 2022 at 10:44:32AM +0200, Richard Biener via Gcc-patches wrote:
> * gcc.dg/autopar/pr106737.c: New testcase.
The test uses -floop-parallelize-all which emits a sorry when graphite
isn't configured in.
Fixed thusly, tested on x86_64-linux (where it PASSed for me before and
keeps PASSing) and on i686-linux (where it FAILed and now is UNSUPPORTED
as I don't have 32-bit libisl installed), committed to trunk as obvious.
2022-08-27 Jakub Jelinek
PR tree-optimization/106737
* gcc.dg/autopar/pr106737.c: Require fgraphite effective target.
--- gcc/testsuite/gcc.dg/autopar/pr106737.c.jj 2022-08-25 20:34:49.333893224
+0200
+++ gcc/testsuite/gcc.dg/autopar/pr106737.c 2022-08-27 09:22:07.141807077
+0200
@@ -1,4 +1,4 @@
-/* { dg-do compile } */
+/* { dg-do compile { target fgraphite } } */
/* { dg-options "-O -floop-parallelize-all -ftree-parallelize-loops=2
-fno-tree-dce" } */
void
Jakub
Re: [PATCH] x86: Handle V16BF in ix86_avx256_split_vector_move_misalign
On Fri, Aug 26, 2022 at 7:34 PM H.J. Lu wrote:
>
> Handle E_V16BFmode in ix86_avx256_split_vector_move_misalign and add
> V16BF to V_256H iterator.
>
> gcc/
>
> PR target/106748
> * config/i386/i386-expand.cc
> (ix86_avx256_split_vector_move_misalign): Handle E_V16BFmode.
> * config/i386/sse.md (V_256H): Add V16BF.
>
> gcc/testsuite/
>
> PR target/106748
> * gcc.target/i386/pr106748.c: New test.
OK.
Thanks,
Uros.
>
> ---
> gcc/config/i386/i386-expand.cc | 4
> gcc/config/i386/sse.md | 4 ++--
> gcc/testsuite/gcc.target/i386/pr106748.c | 20
> 3 files changed, 26 insertions(+), 2 deletions(-)
> create mode 100644 gcc/testsuite/gcc.target/i386/pr106748.c
>
> diff --git a/gcc/config/i386/i386-expand.cc b/gcc/config/i386/i386-expand.cc
> index 4b216308a18..836ebc82d67 100644
> --- a/gcc/config/i386/i386-expand.cc
> +++ b/gcc/config/i386/i386-expand.cc
> @@ -745,6 +745,10 @@ ix86_avx256_split_vector_move_misalign (rtx op0, rtx op1)
>extract = gen_avx_vextractf128v32qi;
>mode = V16QImode;
>break;
> +case E_V16BFmode:
> + extract = gen_avx_vextractf128v16bf;
> + mode = V8BFmode;
> + break;
> case E_V16HFmode:
>extract = gen_avx_vextractf128v16hf;
>mode = V8HFmode;
> diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
> index e6ab3c92dcf..259048481b6 100644
> --- a/gcc/config/i386/sse.md
> +++ b/gcc/config/i386/sse.md
> @@ -297,9 +297,9 @@ (define_mode_iterator V_128
> (define_mode_iterator V_256
>[V32QI V16HI V8SI V4DI V8SF V4DF])
>
> -;; All 256bit vector modes including HF vector mode
> +;; All 256bit vector modes including HF/BF vector modes
> (define_mode_iterator V_256H
> - [V32QI V16HI V8SI V4DI V8SF V4DF V16HF])
> + [V32QI V16HI V8SI V4DI V8SF V4DF V16HF V16BF])
>
> ;; All 128bit and 256bit vector modes
> (define_mode_iterator V_128_256
> diff --git a/gcc/testsuite/gcc.target/i386/pr106748.c
> b/gcc/testsuite/gcc.target/i386/pr106748.c
> new file mode 100644
> index 000..6388b1deb23
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/pr106748.c
> @@ -0,0 +1,20 @@
> +/* { dg-do compile } */
> +/* { dg-options "-O0 -mavx256-split-unaligned-store -mavx -fpack-struct" } */
> +
> +typedef __bf16 __m256bf16 __attribute__((__vector_size__(32)));
> +typedef struct {
> + __m256bf16 _m256bf16[1];
> +} YMM_T;
> +
> +struct {
> + YMM_T ymm0;
> +} fregs;
> +
> +__m256bf16 do_test_u3b_0_0;
> +int do_test_i;
> +
> +void
> +do_test()
> +{
> + (&fregs.ymm0)[do_test_i]._m256bf16[0] = do_test_u3b_0_0;
> +}
> --
> 2.37.2
>
[PATCH] RISC-V: Add RVV instructions classification
From: zhongjuzhe gcc/ChangeLog: * config/riscv/riscv.md: Add new type for vector instructions. --- gcc/config/riscv/riscv.md | 100 +- 1 file changed, 99 insertions(+), 1 deletion(-) diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index 30cd07dc6f5..ee3e7c53b78 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -195,10 +195,108 @@ ;; nop no operation ;; ghost an instruction that produces no real code ;; bitmanipbit manipulation instructions +;; Classification of RVV instructions which will be added to each RVV .md pattern and used by scheduler. +;; rdvlenb vector byte length vlenb csrr read +;; rdvlvector length vl csrr read +;; 7. Vector Loads and Stores +;; vldevector unit-stride load instructions +;; vstevector unit-stride store instructions +;; vldmvector unit-stride mask load instructions +;; vstmvector unit-stride mask store instructions +;; vldsvector strided load instructions +;; vstsvector strided store instructions +;; vldux vector unordered indexed load instructions +;; vldox vector ordered indexed load instructions +;; vstux vector unordered indexed store instructions +;; vstox vector ordered indexed store instructions +;; vldff vector unit-stride fault-only-first load instructions +;; vldrvector whole register load instructions +;; vstrvector whole register store instructions +;; 11. Vector integer arithmetic instructions +;; vialu vector single-width integer add and subtract and logical nstructions +;; viwalu vector widening integer add/subtract +;; vextvector integer extension +;; vicalu vector arithmetic with carry or borrow instructions +;; vshift vector single-width bit shift instructions +;; vnshift vector narrowing integer shift instructions +;; vicmp vector integer comparison/min/max instructions +;; vimul vector single-width integer multiply instructions +;; vidiv vector single-width integer divide instructions +;; viwmul vector widening integer multiply instructions +;; vimuladdvector single-width integer multiply-add instructions +;; viwmuladd vector widening integer multiply-add instructions +;; vimerge vector integer merge instructions +;; vimov vector integer move vector instructions +;; 12. Vector fixed-point arithmetic instructions +;; vsalu vector single-width saturating add and subtract and logical instructions +;; vaalu vector single-width averaging add and subtract and logical instructions +;; vsmul vector single-width fractional multiply with rounding and saturation instructions +;; vsshift vector single-width scaling shift instructions +;; vnclip vector narrowing fixed-point clip instructions +;; 13. Vector floating-point instructions +;; vfalu vector single-width floating-point add/subtract instructions +;; vfwalu vector widening floating-point add/subtract instructions +;; vfmul vector single-width floating-point multiply instructions +;; vfdiv vector single-width floating-point divide instructions +;; vfwmul vector widening floating-point multiply instructions +;; vfmuladdvector single-width floating-point multiply-add instructions +;; vfwmuladd vector widening floating-point multiply-add instructions +;; vfsqrt vector floating-point square-root instructions +;; vfrecp vector floating-point reciprocal square-root instructions +;; vfcmp vector floating-point comparison/min/max instructions +;; vfsgnj vector floating-point sign-injection instructions +;; vfclass vector floating-point classify instruction +;; vfmerge vector floating-point merge instruction +;; vfmov vector floating-point move instruction +;; vfcvtitof vector single-width integer to floating-point instruction +;; vfcvtftoi vector single-width floating-point to integer instruction +;; vfwcvtitof vector widening integer to floating-point instruction +;; vfwcvtftoi vector widening floating-point to integer instruction +;; vfwcvtftof vector widening floating-point to floating-point instruction +;; vfncvtitof vector narrowing integer to floating-point instruction +;; vfncvtftoi vector narrowing floating-point to integer instruction +;; vfncvtftof vector narrowing floating-point to floating-point instruction +;; 14. Vector reduction operations +;; vired vector single-width integer reduction instructions +;; viwred vector widening integer reduction instructions +;; vfred vector single-width floating-point un-ordered reduction instruction +;; vfredo vector single-width floating-point ordered reduction instruction +;; vfwred vector widening floating-point un-ordered reduction instruction +;; vfwredo vector widening floating-point ordered reduction instruction +;; 15. Vector mask instructio
[PATCH] RISC-V: Add RVV registers
From: zhongjuzhe
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_v_ext_vector_mode_p): New function.
(riscv_classify_address): Disallow PLUS/LO_SUM/CONST_INT address types
for RVV.
(riscv_address_insns): Add RVV modes condition.
(riscv_binary_cost): Ditto.
(riscv_rtx_costs): Adjust cost for RVV.
(riscv_secondary_memory_needed): Add RVV modes condition.
(riscv_hard_regno_nregs): Add RVV register allocation.
(riscv_hard_regno_mode_ok): Add RVV register allocation.
(riscv_class_max_nregs): Add RVV register allocation.
* config/riscv/riscv.h (DWARF_FRAME_REGNUM): Add VL/VTYPE and vector
registers in Dwarf.
(UNITS_PER_V_REG): New macro.
(FIRST_PSEUDO_REGISTER): Adjust first pseudo num for RVV.
(V_REG_FIRST): New macro.
(V_REG_LAST): Ditto.
(V_REG_NUM): Ditto.
(V_REG_P): Ditto.
(VL_REG_P): Ditto.
(VTYPE_REG_P): Ditto.
(RISCV_DWARF_VL): Ditto.
(RISCV_DWARF_VTYPE): Ditto.
(enum reg_class): Add RVV register types.
(REG_CLASS_CONTENTS): Add RVV register types.
* config/riscv/riscv.md: Add VL/VTYPE register number constants.
---
gcc/config/riscv/riscv.cc | 100 --
gcc/config/riscv/riscv.h | 90 --
gcc/config/riscv/riscv.md | 2 +
3 files changed, 173 insertions(+), 19 deletions(-)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 026c69ce40d..65d71544f47 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -279,7 +279,22 @@ const enum reg_class
riscv_regno_to_class[FIRST_PSEUDO_REGISTER] = {
FP_REGS, FP_REGS,FP_REGS,FP_REGS,
FP_REGS, FP_REGS,FP_REGS,FP_REGS,
FP_REGS, FP_REGS,FP_REGS,FP_REGS,
- FRAME_REGS, FRAME_REGS,
+ FRAME_REGS, FRAME_REGS, VL_REGS,VTYPE_REGS,
+ NO_REGS, NO_REGS,NO_REGS,NO_REGS,
+ NO_REGS, NO_REGS,NO_REGS,NO_REGS,
+ NO_REGS, NO_REGS,NO_REGS,NO_REGS,
+ NO_REGS, NO_REGS,NO_REGS,NO_REGS,
+ NO_REGS, NO_REGS,NO_REGS,NO_REGS,
+ NO_REGS, NO_REGS,NO_REGS,NO_REGS,
+ NO_REGS, NO_REGS,NO_REGS,NO_REGS,
+ VM_REGS, VD_REGS,VD_REGS,VD_REGS,
+ VD_REGS, VD_REGS,VD_REGS,VD_REGS,
+ VD_REGS, VD_REGS,VD_REGS,VD_REGS,
+ VD_REGS, VD_REGS,VD_REGS,VD_REGS,
+ VD_REGS, VD_REGS,VD_REGS,VD_REGS,
+ VD_REGS, VD_REGS,VD_REGS,VD_REGS,
+ VD_REGS, VD_REGS,VD_REGS,VD_REGS,
+ VD_REGS, VD_REGS,VD_REGS,VD_REGS,
};
/* Costs to use when optimizing for rocket. */
@@ -894,6 +909,14 @@ riscv_valid_lo_sum_p (enum riscv_symbol_type sym_type,
machine_mode mode,
return true;
}
+/* Return true if mode is the RVV mode. */
+
+static bool
+riscv_v_ext_vector_mode_p (machine_mode mode)
+{
+ return VECTOR_MODE_P (mode);
+}
+
/* Return true if X is a valid address for machine mode MODE. If it is,
fill in INFO appropriately. STRICT_P is true if REG_OK_STRICT is in
effect. */
@@ -912,6 +935,10 @@ riscv_classify_address (struct riscv_address_info *info,
rtx x,
return riscv_valid_base_register_p (info->reg, mode, strict_p);
case PLUS:
+ /* RVV load/store disallow any offset. */
+ if (riscv_v_ext_vector_mode_p (mode))
+ return false;
+
info->type = ADDRESS_REG;
info->reg = XEXP (x, 0);
info->offset = XEXP (x, 1);
@@ -919,6 +946,10 @@ riscv_classify_address (struct riscv_address_info *info,
rtx x,
&& riscv_valid_offset_p (info->offset, mode));
case LO_SUM:
+ /* RVV load/store disallow LO_SUM. */
+ if (riscv_v_ext_vector_mode_p (mode))
+ return false;
+
info->type = ADDRESS_LO_SUM;
info->reg = XEXP (x, 0);
info->offset = XEXP (x, 1);
@@ -937,6 +968,10 @@ riscv_classify_address (struct riscv_address_info *info,
rtx x,
&& riscv_valid_lo_sum_p (info->symbol_type, mode, info->offset));
case CONST_INT:
+ /* RVV load/store disallow CONST_INT. */
+ if (riscv_v_ext_vector_mode_p (mode))
+ return false;
+
/* Small-integer addresses don't occur very often, but they
are legitimate if x0 is a valid base register. */
info->type = ADDRESS_CONST_INT;
@@ -1022,7 +1057,7 @@ riscv_address_insns (rtx x, machine_mode mode, bool
might_split_p)
/* BLKmode is used for single unaligned loads and stores and should
not count as a multiword mode. */
- if (mode != BLKmode && might_split_p)
+ if (!riscv_v_ext_vector_mode_p (mode) && mode != BLKmode && might_split_p)
n += (GET_MODE_SIZE (mode).to_constant () + UNITS_PER_WORD - 1) /
UNITS_PER_WORD;
if (addr.type == ADDRESS_
[PATCH V3] Add warning options -W[no-]compare-distinct-pointer-types
GCC emits pedwarns unconditionally when comparing pointers of
different types, for example:
int xdp_context (struct xdp_md *xdp)
{
void *data = (void *)(long)xdp->data;
__u32 *metadata = (void *)(long)xdp->data_meta;
__u32 ret;
if (metadata + 1 > data)
return 0;
return 1;
}
/home/jemarch/foo.c: In function ‘xdp_context’:
/home/jemarch/foo.c:15:20: warning: comparison of distinct pointer types
lacks a cast
15 | if (metadata + 1 > data)
|^
LLVM supports an option -W[no-]compare-distinct-pointer-types that can
be used in order to enable or disable the emission of such warnings.
It is enabled by default.
This patch adds the same options to GCC.
Documentation and testsuite updated included.
Regtested in x86_64-linu-gnu.
No regressions observed.
gcc/ChangeLog:
PR c/106537
* doc/invoke.texi (Option Summary): Mention
-Wcompare-distinct-pointer-types under `Warning Options'.
(Warning Options): Document -Wcompare-distinct-pointer-types.
gcc/c-family/ChangeLog:
PR c/106537
* c.opt (Wcompare-distinct-pointer-types): New option.
gcc/c/ChangeLog:
PR c/106537
* c-typeck.cc (build_binary_op): Warning on comparing distinct
pointer types only when -Wcompare-distinct-pointer-types.
gcc/testsuite/ChangeLog:
PR c/106537
* gcc.c-torture/compile/pr106537-1.c: New test.
* gcc.c-torture/compile/pr106537-2.c: Likewise.
* gcc.c-torture/compile/pr106537-3.c: Likewise.
---
gcc/c-family/c.opt| 4
gcc/c/c-typeck.cc | 6 ++---
gcc/doc/invoke.texi | 6 +
.../gcc.c-torture/compile/pr106537-1.c| 23 +++
.../gcc.c-torture/compile/pr106537-2.c| 21 +
.../gcc.c-torture/compile/pr106537-3.c| 21 +
6 files changed, 78 insertions(+), 3 deletions(-)
create mode 100644 gcc/testsuite/gcc.c-torture/compile/pr106537-1.c
create mode 100644 gcc/testsuite/gcc.c-torture/compile/pr106537-2.c
create mode 100644 gcc/testsuite/gcc.c-torture/compile/pr106537-3.c
diff --git a/gcc/c-family/c.opt b/gcc/c-family/c.opt
index f776efd39d8..729b86c0287 100644
--- a/gcc/c-family/c.opt
+++ b/gcc/c-family/c.opt
@@ -1848,6 +1848,10 @@ Winvalid-imported-macros
C++ ObjC++ Var(warn_imported_macros) Warning
Warn about macros that have conflicting header units definitions.
+Wcompare-distinct-pointer-types
+C ObjC Var(warn_compare_distinct_pointer_types) Warning Init(1)
+Warn if pointers of distinct types are compared without a cast.
+
flang-info-include-translate
C++ Var(note_include_translate_yes)
Note #include directives translated to import declarations.
diff --git a/gcc/c/c-typeck.cc b/gcc/c/c-typeck.cc
index ee891ee33c2..dc7e8514c47 100644
--- a/gcc/c/c-typeck.cc
+++ b/gcc/c/c-typeck.cc
@@ -12422,7 +12422,7 @@ build_binary_op (location_t location, enum tree_code
code,
else
/* Avoid warning about the volatile ObjC EH puts on decls. */
if (!objc_ok)
- pedwarn (location, 0,
+ pedwarn (location, OPT_Wcompare_distinct_pointer_types,
"comparison of distinct pointer types lacks a cast");
if (result_type == NULL_TREE)
@@ -12562,8 +12562,8 @@ build_binary_op (location_t location, enum tree_code
code,
int qual = ENCODE_QUAL_ADDR_SPACE (as_common);
result_type = build_pointer_type
(build_qualified_type (void_type_node, qual));
- pedwarn (location, 0,
- "comparison of distinct pointer types lacks a cast");
+ pedwarn (location, OPT_Wcompare_distinct_pointer_types,
+ "comparison of distinct pointer types lacks a cast");
}
}
else if (code0 == POINTER_TYPE && null_pointer_constant_p (orig_op1))
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 6131bfa7acf..5ef9dbe4bbe 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -341,6 +341,7 @@ Objective-C and Objective-C++ Dialects}.
-Wcast-align -Wcast-align=strict -Wcast-function-type -Wcast-qual @gol
-Wchar-subscripts @gol
-Wclobbered -Wcomment @gol
+-Wcompare-distinct-pointer-types @gol
-Wconversion -Wno-coverage-mismatch -Wno-cpp @gol
-Wdangling-else -Wdangling-pointer -Wdangling-pointer=@var{n} @gol
-Wdate-time @gol
@@ -8648,6 +8649,11 @@ programs.
Warn for variables that might be changed by @code{longjmp} or
@code{vfork}. This warning is also enabled by @option{-Wextra}.
+@item -Wcompare-distinct-pointer-types
+@opindex Wcompare-distinct-pointer-types
+Warn if pointers of distinct types are compared without a cast. This
+warning is enabled by default.
+
@item -Wconversion
@opindex Wconversion
@opindex Wno-conversion
diff --git a/gcc/testsuite/gcc.
[PATCH] rs6000: Allow conversions of MMA pointer types [PR106017]
GCC incorrectly disables conversions between MMA pointer types, which
are allowed with clang. The original intent was to disable conversions
between MMA types and other other types, but pointer conversions should
have been allowed. The fix is to just remove the MMA pointer conversion
handling code altogether.
This passed bootstrap and regtesting on powerpc64le-linux with no regressions.
Ok for trunk and backports after some burn-in time?
Peter
gcc/
PR target/106017
* config/rs6000/rs6000.cc (rs6000_invalid_conversion): Remove handling
of MMA pointer conversions.
gcc/testsuite/
PR target/106017
* gcc.target/powerpc/pr106017.c: New test.
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index df491bee2ea..2f3146e56f8 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -28188,28 +28188,6 @@ rs6000_invalid_conversion (const_tree fromtype,
const_tree totype)
if (tomode == OOmode)
return N_("invalid conversion to type %<__vector_pair%>");
}
- else if (POINTER_TYPE_P (fromtype) && POINTER_TYPE_P (totype))
-{
- /* We really care about the modes of the base types. */
- frommode = TYPE_MODE (TREE_TYPE (fromtype));
- tomode = TYPE_MODE (TREE_TYPE (totype));
-
- /* Do not allow conversions to/from XOmode and OOmode pointer
-types, except to/from void pointers. */
- if (frommode != tomode
- && frommode != VOIDmode
- && tomode != VOIDmode)
- {
- if (frommode == XOmode)
- return N_("invalid conversion from type %<__vector_quad *%>");
- if (tomode == XOmode)
- return N_("invalid conversion to type %<__vector_quad *%>");
- if (frommode == OOmode)
- return N_("invalid conversion from type %<__vector_pair *%>");
- if (tomode == OOmode)
- return N_("invalid conversion to type %<__vector_pair *%>");
- }
-}
/* Conversion allowed. */
return NULL;
diff --git a/gcc/testsuite/gcc.target/powerpc/pr106017.c
b/gcc/testsuite/gcc.target/powerpc/pr106017.c
new file mode 100644
index 000..46d6c7a4a33
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr106017.c
@@ -0,0 +1,19 @@
+/* PR target/106017 */
+/* { dg-options "-O1 -mdejagnu-cpu=power10" } */
+/* { dg-require-effective-target power10_ok } */
+
+/* Make sure we do not flag any errors on the following test cases. */
+
+void takeacc(__vector_quad *);
+void
+foo (void)
+{
+ __vector_quad arr[4];
+ takeacc (arr);
+}
+
+unsigned char *
+bar (__vector_quad *a)
+{
+ return (unsigned char *)a;
+}
Re: [PATCH] rs6000: Allow conversions of MMA pointer types [PR106017]
Hi! On Sat, Aug 27, 2022 at 01:36:07PM -0500, Peter Bergner wrote: > GCC incorrectly disables conversions between MMA pointer types, which > are allowed with clang. The original intent was to disable conversions > between MMA types and other other types, but pointer conversions should > have been allowed. Such conversions are explicitly allowed in C, even (6.3.2.3/7). > The fix is to just remove the MMA pointer conversion > handling code altogether. Okay for trunk and all backports. Thanks! Segher
[committed] d: Merge upstream dmd 817610b16d, phobos b578dfad9
Hi, This patch merges the D front-end with upstream dmd 817610b16d, and standard library with phobos b578dfad9. D front-end changes: - Import latest bug fixes to mainline. Phobos changes: - Import latest bug fixes to mainline. - std.logger module has been moved out of experimental. - Removed std.experimental.typecons module. Bootstrapped and regression tested on x86_64-linux-gnu/-m32/-mx32, committed to mainline. Regards, Iain. --- gcc/d/ChangeLog: * dmd/MERGE: Merge upstream dmd 817610b16d. * d-ctfloat.cc (CTFloat::parse): Update for new front-end interface. * d-lang.cc (d_parse_file): Likewise. * expr.cc (ExprVisitor::visit (AssignExp *)): Remove handling of array assignments to non-trivial static and dynamic arrays. * runtime.def (ARRAYASSIGN): Remove. (ARRAYASSIGN_L): Remove. (ARRAYASSIGN_R): Remove. libphobos/ChangeLog: * libdruntime/MERGE: Merge upstream druntime 817610b16d. * libdruntime/Makefile.am (DRUNTIME_DSOURCES): Add core/internal/array/arrayassign.d. * libdruntime/Makefile.in: Regenerate. * src/MERGE: Merge upstream phobos b578dfad9. * src/Makefile.am (PHOBOS_DSOURCES): Remove std/experimental/typecons.d. Add std/logger package. * src/Makefile.in: Regenerate. --- gcc/d/d-ctfloat.cc|5 +- gcc/d/d-lang.cc |1 - gcc/d/dmd/MERGE |2 +- gcc/d/dmd/README.md | 282 +- gcc/d/dmd/astenums.d |1 - gcc/d/dmd/canthrow.d |4 +- gcc/d/dmd/common/README.md|8 +- gcc/d/dmd/common/outbuffer.d | 78 +- gcc/d/dmd/ctfeexpr.d | 20 +- gcc/d/dmd/declaration.d | 22 +- gcc/d/dmd/declaration.h |9 +- gcc/d/dmd/dimport.d | 11 +- gcc/d/dmd/dinterpret.d| 35 +- gcc/d/dmd/dmacro.d| 42 +- gcc/d/dmd/dmodule.d | 22 +- gcc/d/dmd/doc.d | 80 +- gcc/d/dmd/dsymbolsem.d| 162 +- gcc/d/dmd/dtemplate.d |9 +- gcc/d/dmd/escape.d| 185 +- gcc/d/dmd/expression.d|2 +- gcc/d/dmd/expressionsem.d | 95 +- gcc/d/dmd/func.d |2 - gcc/d/dmd/globals.d | 47 +- gcc/d/dmd/globals.h | 37 +- gcc/d/dmd/hdrgen.d| 16 +- gcc/d/dmd/id.d|3 + gcc/d/dmd/identifier.d|2 +- gcc/d/dmd/lexer.d |2 +- gcc/d/dmd/module.h|1 - gcc/d/dmd/mtype.d | 38 +- gcc/d/dmd/parse.d | 80 +- gcc/d/dmd/root/README.md | 44 +- gcc/d/dmd/root/array.d| 18 + gcc/d/dmd/root/ctfloat.d |2 +- gcc/d/dmd/root/ctfloat.h |2 +- gcc/d/dmd/semantic3.d |3 - gcc/d/dmd/traits.d|5 + gcc/d/dmd/typesem.d |5 + gcc/d/expr.cc | 30 +- gcc/d/runtime.def |9 +- .../gdc.test/compilable/aliasassign.d | 105 +- .../compilable/scope_infer_array_assign.d | 28 + gcc/testsuite/gdc.test/compilable/test21197.d | 25 + gcc/testsuite/gdc.test/compilable/uda.d |6 + .../gdc.test/fail_compilation/aliasassign2.d | 33 + .../gdc.test/fail_compilation/diag23295.d | 40 + .../gdc.test/fail_compilation/fail10968.d | 29 +- .../gdc.test/fail_compilation/fail14669.d |4 +- .../gdc.test/fail_compilation/ice8795.d |2 +- .../fail_compilation/imports/import15525.d|3 + .../gdc.test/fail_compilation/issue12652.d| 24 + .../gdc.test/fail_compilation/retscope6.d |2 + .../gdc.test/fail_compilation/shared.d| 11 + .../gdc.test/fail_compilation/test15525.d | 17 + .../gdc.test/fail_compilation/test17423.d |3 +- .../gdc.test/fail_compilation/test17764.d | 21 + .../gdc.test/fail_compilation/test20245.d | 19 +- .../gdc.test/fail_compilation/test20809.d | 44 + .../gdc.test/fail_compilation/test23073.d | 35 + .../gdc.test/fail_compilation/testsemi.d | 46 + gcc/testsuite/gdc.test/runnable/test20365.d | 21 + gcc/testsuite/gdc.test/runnable/test20809.d | 14 + libphobos/libdruntime/MERGE |2 +- libphobos/libdruntime/Makefile.am | 23 +- libphobos/libdruntime/M
Re: [PATCH] rs6000: Allow conversions of MMA pointer types [PR106017]
On 8/27/22 4:37 PM, Segher Boessenkool wrote: > Such conversions are explicitly allowed in C, even (6.3.2.3/7). Yeah, I think I just got a little carried away disabling them originally. :-( >> The fix is to just remove the MMA pointer conversion >> handling code altogether. > > Okay for trunk and all backports. Thanks! Ok, pushed to trunk. I'll backport after some burn-in. Thanks! Peter
