[PATCH] PR middle-end/80270: ICE in extract_bit_field_1
This patch fixes PR middle-end/80270, an ICE-on-valid regression, where
performing a bitfield extraction on a variable explicitly stored in a
hard register by the user causes a segmentation fault during RTL
expansion. Nearly identical source code without the "asm" qualifier
compiles fine. The point of divergence is in simplify_gen_subreg
which tries to avoid creating non-trivial SUBREGs of hard registers,
to avoid problems during register allocation. This suggests the
simple solution proposed here, to copy hard registers to a new pseudo
in extract_integral_bit_field, just before calling simplify_gen_subreg.
This patch has been tested on x86_64-pc-linux-gnu with make bootstrap
and make -k check with no new failures. Ok for mainline?
2022-02-27 Roger Sayle
gcc/ChangeLog
PR middle-end/80270
* expmed.cc (extract_integral_bit_field): If OP0 is a hard
register, copy it to a pseudo before calling simplify_gen_subreg.
gcc/testsuite/ChangeLog
* gcc.target/i386/pr80270.c: New test case.
Thanks in advance,
Roger
--
diff --git a/gcc/expmed.cc b/gcc/expmed.cc
index 80a16ce..b51450d 100644
--- a/gcc/expmed.cc
+++ b/gcc/expmed.cc
@@ -1975,6 +1975,14 @@ extract_integral_bit_field (rtx op0, opt_scalar_int_mode
op0_mode,
unsignedp, reverse);
return convert_extracted_bit_field (target, mode, tmode, unsignedp);
}
+ /* If OP0 is a hard register, copy it to a pseudo before calling
+simplify_gen_subreg. */
+ if (REG_P (op0) && HARD_REGISTER_P (op0))
+ {
+ rtx tmp = gen_reg_rtx (GET_MODE (op0));
+ emit_move_insn (tmp, op0);
+ op0 = tmp;
+ }
op0 = simplify_gen_subreg (word_mode, op0, op0_mode.require (),
bitnum / BITS_PER_WORD * UNITS_PER_WORD);
op0_mode = word_mode;
diff --git a/gcc/testsuite/gcc.target/i386/pr80270.c
b/gcc/testsuite/gcc.target/i386/pr80270.c
new file mode 100644
index 000..89e9c33
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr80270.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse" } */
+
+typedef int v8 __attribute__((vector_size(8)));
+struct S1 {
+ v8 s1f;
+};
+struct S2 {
+ struct S1 s2f1;
+ v8 s2f2;
+};
+
+extern void foo(int);
+
+void bar() {
+ int tmp, i = 3;
+ register struct S2 b asm("xmm0");
+ tmp = b.s2f1.s1f[i];
+ foo(tmp);
+}
+
New Swedish PO file for 'gcc' (version 12.1-b20220213)
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[COMMITTED] hpux: New include hack to fix declarations of _DINFINITY, _SINFINITY and _SQNAN
The declarations of _DINFINITY, _SINFINITY and _SQNAN need to be constant
expressions.
Committed to trunk.
Dave
---
2022-02-27 John David Anglin
fixincludes/ChangeLog:
* inclhack.def (hpux_math_constexpr): New hack.
* fixincl.x: Regenerate.
* tests/base/math.h: Update.
diff --git a/fixincludes/inclhack.def b/fixincludes/inclhack.def
index 8400d0c696b..7605ac89aa2 100644
--- a/fixincludes/inclhack.def
+++ b/fixincludes/inclhack.def
@@ -2282,6 +2282,24 @@ fix = {
" }\n";
};
+/*
+ * This hack fixes the declarations of _DINFINITY, _SINFINITY and _SQNAN.
+ */
+fix = {
+hackname = hpux_math_constexpr;
+mach = "*-hp-hpux11*";
+files = math.h;
+sed = "s@^[ \t]*extern[ \t]*const[ \t]*double[ \t]*_DINFINITY;"
+ "[ \t]*$@# define _DINFINITY (__builtin_inf ())@";
+sed = "s@^[ \t]*extern[ \t]*const[ \t]*float[ \t]*_SINFINITY;"
+ "[ \t]*$@#define _SINFINITY (__builtin_inff ())@";
+sed = "s@^[ \t]*extern[ \t]*const[ \t]*float[ \t]*_SQNAN;"
+ "[ \t]*$@#define _SQNAN (__builtin_nanf (\\\"\\\"))@";
+test_text = " extern const double _DINFINITY;\n"
+ " extern const float _SINFINITY;\n"
+ " extern const float _SQNAN;";
+};
+
/*
* Fix hpux 10.X missing ctype declarations 1
*/
diff --git a/fixincludes/tests/base/math.h b/fixincludes/tests/base/math.h
index 7525fd82ecf..29b67579748 100644
--- a/fixincludes/tests/base/math.h
+++ b/fixincludes/tests/base/math.h
@@ -57,6 +57,13 @@
#endif /* HPUX11_CPP_POW_INLINE_CHECK */
+#if defined( HPUX_MATH_CONSTEXPR_CHECK )
+# define _DINFINITY (__builtin_inf ())
+#define _SINFINITY (__builtin_inff ())
+#define _SQNAN (__builtin_nanf (""))
+#endif /* HPUX_MATH_CONSTEXPR_CHECK */
+
+
#if defined( HPUX11_FABSF_CHECK )
#ifdef _PA_RISC
#ifndef __cplusplus
signature.asc
Description: PGP signature
[pushed] c++: (*(fn))() [PR104618]
The patch for PR90451 deferred marking to the point of actual use; we missed
this one because of the parens.
Tested x86_64-pc-linux-gnu, applying to trunk.
PR c++/104618
gcc/cp/ChangeLog:
* typeck.cc (cp_build_addr_expr_1): Also
maybe_undo_parenthesized_ref.
gcc/testsuite/ChangeLog:
* g++.dg/overload/paren1.C: New test.
---
gcc/cp/typeck.cc | 6 +++---
gcc/testsuite/g++.dg/overload/paren1.C | 7 +++
2 files changed, 10 insertions(+), 3 deletions(-)
create mode 100644 gcc/testsuite/g++.dg/overload/paren1.C
diff --git a/gcc/cp/typeck.cc b/gcc/cp/typeck.cc
index f796337f73c..bddc83759ad 100644
--- a/gcc/cp/typeck.cc
+++ b/gcc/cp/typeck.cc
@@ -6884,9 +6884,9 @@ cp_build_addr_expr_1 (tree arg, bool strict_lvalue,
tsubst_flags_t complain)
so we can just form an ADDR_EXPR with the correct type. */
if (processing_template_decl || TREE_CODE (arg) != COMPONENT_REF)
{
- tree stripped_arg = tree_strip_any_location_wrapper (arg);
- if (TREE_CODE (stripped_arg) == FUNCTION_DECL
- && !mark_used (stripped_arg, complain) && !(complain & tf_error))
+ tree stripped_arg
+ = tree_strip_any_location_wrapper (maybe_undo_parenthesized_ref (arg));
+ if (!mark_single_function (stripped_arg, complain))
return error_mark_node;
val = build_address (arg);
if (TREE_CODE (arg) == OFFSET_REF)
diff --git a/gcc/testsuite/g++.dg/overload/paren1.C
b/gcc/testsuite/g++.dg/overload/paren1.C
new file mode 100644
index 000..21421ae8726
--- /dev/null
+++ b/gcc/testsuite/g++.dg/overload/paren1.C
@@ -0,0 +1,7 @@
+// PR c++/104618
+
+extern void gen_addsi3 (void);
+void output_stack_adjust ()
+{
+ (*(gen_addsi3)) ();
+}
base-commit: d1574a9b820f17adb9004255e2018967e9be063b
--
2.27.0
Re: [PATCH] AVX512F: Add helper enumeration for ternary logic intrinsics.
On Fri, Feb 25, 2022 at 4:44 PM Hongyu Wang via Gcc-patches
wrote:
>
> Hi,
>
> This patch intends to sync with llvm change in
> https://reviews.llvm.org/D120307 to add enumeration and truncate
This will be documented in intel intrinsic guide.
> imm to unsigned char, so users could use ~ on immediates.
>
> Bootstraped/regtested on x86_64-pc-linux-gnu{-m32,}.
> Ok for master?
Ok.
>
> gcc/ChangeLog:
>
> * config/i386/avx512fintrin.h (_MM_TERNLOG_ENUM): New enum.
> (_mm512_ternarylogic_epi64): Truncate imm to unsigned
> char to avoid error when using ~enum as parameter.
> (_mm512_mask_ternarylogic_epi64): Likewise.
> (_mm512_maskz_ternarylogic_epi64): Likewise.
> (_mm512_ternarylogic_epi32): Likewise.
> (_mm512_mask_ternarylogic_epi32): Likewise.
> (_mm512_maskz_ternarylogic_epi32): Likewise.
> * config/i386/avx512vlintrin.h (_mm256_ternarylogic_epi64):
> Adjust imm param type to unsigned char.
> (_mm256_mask_ternarylogic_epi64): Likewise.
> (_mm256_maskz_ternarylogic_epi64): Likewise.
> (_mm256_ternarylogic_epi32): Likewise.
> (_mm256_mask_ternarylogic_epi32): Likewise.
> (_mm256_maskz_ternarylogic_epi32): Likewise.
> (_mm_ternarylogic_epi64): Likewise.
> (_mm_mask_ternarylogic_epi64): Likewise.
> (_mm_maskz_ternarylogic_epi64): Likewise.
> (_mm_ternarylogic_epi32): Likewise.
> (_mm_mask_ternarylogic_epi32): Likewise.
> (_mm_maskz_ternarylogic_epi32): Likewise.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/i386/avx512f-vpternlogd-1.c: Use new enum.
> * gcc.target/i386/avx512f-vpternlogq-1.c: Likewise.
> * gcc.target/i386/avx512vl-vpternlogd-1.c: Likewise.
> * gcc.target/i386/avx512vl-vpternlogq-1.c: Likewise.
> * gcc.target/i386/testimm-10.c: Remove imm check for vpternlog
> insns since the imm has been truncated in intrinsic.
> ---
> gcc/config/i386/avx512fintrin.h | 132 ++---
> gcc/config/i386/avx512vlintrin.h | 278 +++---
> .../gcc.target/i386/avx512f-vpternlogd-1.c| 7 +-
> .../gcc.target/i386/avx512f-vpternlogq-1.c| 7 +-
> .../gcc.target/i386/avx512vl-vpternlogd-1.c | 13 +-
> .../gcc.target/i386/avx512vl-vpternlogq-1.c | 14 +-
> gcc/testsuite/gcc.target/i386/testimm-10.c| 7 -
> 7 files changed, 285 insertions(+), 173 deletions(-)
>
> diff --git a/gcc/config/i386/avx512fintrin.h b/gcc/config/i386/avx512fintrin.h
> index bc10c823c76..29511fd2831 100644
> --- a/gcc/config/i386/avx512fintrin.h
> +++ b/gcc/config/i386/avx512fintrin.h
> @@ -1639,16 +1639,27 @@ _mm_maskz_sub_round_ss (__mmask8 __U, __m128 __A,
> __m128 __B,
>
> #endif
>
> +/* Constant helper to represent the ternary logic operations among
> + vector A, B and C. */
> +typedef enum
> +{
> + _MM_TERNLOG_A = 0xF0,
> + _MM_TERNLOG_B = 0xCC,
> + _MM_TERNLOG_C = 0xAA
> +} _MM_TERNLOG_ENUM;
> +
> #ifdef __OPTIMIZE__
> extern __inline __m512i
> __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> _mm512_ternarylogic_epi64 (__m512i __A, __m512i __B, __m512i __C,
>const int __imm)
> {
> - return (__m512i) __builtin_ia32_pternlogq512_mask ((__v8di) __A,
> -(__v8di) __B,
> -(__v8di) __C, __imm,
> -(__mmask8) -1);
> + return (__m512i)
> +__builtin_ia32_pternlogq512_mask ((__v8di) __A,
> + (__v8di) __B,
> + (__v8di) __C,
> + (unsigned char) __imm,
> + (__mmask8) -1);
> }
>
> extern __inline __m512i
> @@ -1656,10 +1667,12 @@ __attribute__ ((__gnu_inline__, __always_inline__,
> __artificial__))
> _mm512_mask_ternarylogic_epi64 (__m512i __A, __mmask8 __U, __m512i __B,
> __m512i __C, const int __imm)
> {
> - return (__m512i) __builtin_ia32_pternlogq512_mask ((__v8di) __A,
> -(__v8di) __B,
> -(__v8di) __C, __imm,
> -(__mmask8) __U);
> + return (__m512i)
> +__builtin_ia32_pternlogq512_mask ((__v8di) __A,
> + (__v8di) __B,
> + (__v8di) __C,
> + (unsigned char) __imm,
> + (__mmask8) __U);
> }
>
> extern __inline __m512i
> @@ -1667,10 +1680,12 @@ __attribute__ ((__gnu_inline__, __always_inline__,
> __artificial__))
> _mm512_maskz_ternarylogic_epi64 (__mmask8 __U, __m512i __A, __m512i __B,
> __m512i __C, const int __imm)
> {
> - return (__m512i) __buil
Re: [PATCH v7 11/12] LoongArch Port: gcc/testsuite
Thanks, speculation barrier is not needed for loongarch. I have removed the warning. 在 2022/2/25 上午3:32, Xi Ruoyao 写道: On Sat, 2022-02-12 at 11:11 +0800, xucheng...@loongson.cn wrote: From: chenglulu 2022-02-12 Chenghua Xu Lulu Cheng gcc/testsuite/ spec-barrier tests fail with: ./testsuite/c-c++-common/spec-barrier-1.c:21:3: warning: this target does not define a speculation barrier; your program will still execute correctly, but incorrect speculation may not be restricted I'd seen some news saying your uarch has in-silicon defense for speculation related vulnerabilities. If this is true you can just make __builtin_speculation_safe_value a nop. Quote from gcc internal doc: If this pattern is not defined then the default expansion of '__builtin_speculation_safe_value' will emit a warning. You can suppress this warning by defining this pattern with a final condition of '0' (zero), which tells the compiler that a speculation barrier is not needed for this target.
[PATCH, rs6000] Correct match pattern in pr56605.c
Hi,
This patch corrects the match pattern in pr56605.c. The former pattern
is wrong and test case fails with GCC11. It should match following insn on
each subtarget after mode promotion is disabled. The patch need to be
backported to GCC11.
//gimple
_17 = (unsigned int) _20;
prolog_loop_niters.4_23 = _17 & 3;
//rtl
(insn 19 18 20 2 (parallel [
(set (reg:CC 208)
(compare:CC (and:SI (subreg:SI (reg:DI 207) 0)
(const_int 3 [0x3]))
(const_int 0 [0])))
(set (reg:SI 129 [ prolog_loop_niters.5 ])
(and:SI (subreg:SI (reg:DI 207) 0)
(const_int 3 [0x3])))
]) 197 {*andsi3_imm_mask_dot2}
Bootstrapped and tested on powerpc64-linux BE/LE and AIX with no regressions.
Is this okay for trunk and GCC11? Any recommendations? Thanks a lot.
ChangeLog
2022-02-28 Haochen Gui
gcc/testsuite/
PR target/102146
* gcc.target/powerpc/pr56605.c: Correct match pattern in combine pass.
patch.diff
diff --git a/gcc/testsuite/gcc.target/powerpc/pr56605.c
b/gcc/testsuite/gcc.target/powerpc/pr56605.c
index fdedbfc573d..231d808aa99 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr56605.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr56605.c
@@ -11,5 +11,5 @@ void foo (short* __restrict sb, int* __restrict ia)
ia[i] = (int) sb[i];
}
-/* { dg-final { scan-rtl-dump-times {\(compare:CC \((?:and|zero_extend):(?:DI)
\((?:sub)?reg:[SD]I} 1 "combine" } } */
+/* { dg-final { scan-rtl-dump-times {\(compare:CC \(and:SI \(subreg:SI
\(reg:DI} 1 "combine" } } */
[PATCH] rs6000/test: Adjust p9-vec-length-7 sensitive to unroll [PR103196]
Hi,
As PR103196 shows, p9-vec-length-full-7.c needs to be adjusted as the
complete unrolling can happen on some of its loops. This patch is to
use pragma "GCC unroll 0" to disable all possible loop unrollings.
Hope it can help the case not that fragile.
There are some other p9-vec-length* cases, I noticed that some of them
use either bigger or unknown loop iteration counts, and
"p9-vec-length-3*" have considered the effects of complete unrolling.
So I just leave them alone for now.
Tested on powerpc64-linux-gnu P8 and powerpc64le-linux-gnu P9 and P10.
Is it ok for trunk?
BR,
Kewen
-
PR testsuite/103196
gcc/testsuite/ChangeLog:
* gcc.target/powerpc/p9-vec-length-7.h: Add DO_PRAGMA macro.
* gcc.target/powerpc/p9-vec-length-epil-7.c: Use unroll pragma to
disable any unrollings.
* gcc.target/powerpc/p9-vec-length-full-7.c: Remove useless option.
* gcc.target/powerpc/p9-vec-length.h: Likewise.---
.../gcc.target/powerpc/p9-vec-length-7.h| 17 +++--
.../gcc.target/powerpc/p9-vec-length-epil-7.c | 2 +-
.../gcc.target/powerpc/p9-vec-length-full-7.c | 2 +-
.../gcc.target/powerpc/p9-vec-length.h | 2 ++
4 files changed, 15 insertions(+), 8 deletions(-)
diff --git a/gcc/testsuite/gcc.target/powerpc/p9-vec-length-7.h
b/gcc/testsuite/gcc.target/powerpc/p9-vec-length-7.h
index 4ef8f974a04..4f338565619 100644
--- a/gcc/testsuite/gcc.target/powerpc/p9-vec-length-7.h
+++ b/gcc/testsuite/gcc.target/powerpc/p9-vec-length-7.h
@@ -7,14 +7,19 @@
#define START 1
#define END 59
+/* Note that we use pragma unroll to disable any loop unrollings. */
+
#define test(TYPE)
\
- TYPE x_##TYPE[N] __attribute__((aligned(16)));
\
- void __attribute__((noinline, noclone)) test_npeel_##TYPE() {
\
+ TYPE x_##TYPE[N] __attribute__ ((aligned (16)));
\
+ void __attribute__ ((noinline, noclone)) test_npeel_##TYPE ()
\
+ {
\
TYPE v = 0;
\
-for (unsigned int i = START; i < END; i++) {
\
- x_##TYPE[i] = v;
\
- v += 1;
\
-}
\
+DO_PRAGMA (GCC unroll 0)
\
+for (unsigned int i = START; i < END; i++)
\
+ {
\
+ x_##TYPE[i] = v; \
+ v += 1;\
+ }
\
}
TEST_ALL (test)
diff --git a/gcc/testsuite/gcc.target/powerpc/p9-vec-length-epil-7.c
b/gcc/testsuite/gcc.target/powerpc/p9-vec-length-epil-7.c
index a27ee347ca1..859fedd5679 100644
--- a/gcc/testsuite/gcc.target/powerpc/p9-vec-length-epil-7.c
+++ b/gcc/testsuite/gcc.target/powerpc/p9-vec-length-epil-7.c
@@ -1,5 +1,5 @@
/* { dg-do compile { target { lp64 && powerpc_p9vector_ok } } } */
-/* { dg-options "-mdejagnu-cpu=power9 -O2 -ftree-vectorize
-fno-vect-cost-model -fno-unroll-loops -ffast-math" } */
+/* { dg-options "-mdejagnu-cpu=power9 -O2 -ftree-vectorize
-fno-vect-cost-model -ffast-math" } */
/* { dg-additional-options "--param=vect-partial-vector-usage=1" } */
diff --git a/gcc/testsuite/gcc.target/powerpc/p9-vec-length-full-7.c
b/gcc/testsuite/gcc.target/powerpc/p9-vec-length-full-7.c
index 89ff38443e7..5fe542bba20 100644
--- a/gcc/testsuite/gcc.target/powerpc/p9-vec-length-full-7.c
+++ b/gcc/testsuite/gcc.target/powerpc/p9-vec-length-full-7.c
@@ -1,5 +1,5 @@
/* { dg-do compile { target { lp64 && powerpc_p9vector_ok } } } */
-/* { dg-options "-mdejagnu-cpu=power9 -O2 -ftree-vectorize
-fno-vect-cost-model -fno-unroll-loops -ffast-math" } */
+/* { dg-options "-mdejagnu-cpu=power9 -O2 -ftree-vectorize
-fno-vect-cost-model -ffast-math" } */
/* { dg-additional-options "--param=vect-partial-vector-usage=2" } */
diff --git a/gcc/testsuite/gcc.target/powerpc/p9-vec-length.h
b/gcc/testsuite/gcc.target/powerpc/p9-vec-length.h
index 83418b0b641..7aefc9b308d 100644
--- a/gcc/testsuite/gcc.target/powerpc/p9-vec-length.h
+++ b/gcc/testsuite/gcc.target/powerpc/p9-vec-length.h
@@ -1,5 +1,7 @@
#include
+#define DO_PRAGMA(x) _Pragma (#x)
+
#define TEST_ALL(T)
\
T (int8_t)
\
T (uint8_t)
\
[PATCH] libatomic: Improve 16-byte atomics on Intel AVX [PR104688]
Hi! As mentioned in the PR, the latest Intel SDM has added: "Processors that enumerate support for Intel® AVX (by setting the feature flag CPUID.01H:ECX.AVX[bit 28]) guarantee that the 16-byte memory operations performed by the following instructions will always be carried out atomically: • MOVAPD, MOVAPS, and MOVDQA. • VMOVAPD, VMOVAPS, and VMOVDQA when encoded with VEX.128. • VMOVAPD, VMOVAPS, VMOVDQA32, and VMOVDQA64 when encoded with EVEX.128 and k0 (masking disabled). (Note that these instructions require the linear addresses of their memory operands to be 16-byte aligned.)" The following patch deals with it just on the libatomic library side so far, currently (since ~ 2017) we emit all the __atomic_* 16-byte builtins as library calls since and this is something that we can hopefully backport. The patch simply introduces yet another ifunc variant that takes priority over the pure CMPXCHG16B one, one that checks AVX and CMPXCHG16B bits and on non-Intel clears the AVX bit during detection for now (if AMD comes with the same guarantee, we could revert the config/x86/init.c hunk), which implements 16-byte atomic load as vmovdqa and 16-byte atomic store as vmovdqa followed by mfence. Bootstrapped/regtested on x86_64-linux and i686-linux, ok for trunk so far? 2022-02-28 Jakub Jelinek PR target/104688 * Makefile.am (IFUNC_OPTIONS): Change on x86_64 to -mcx16 -mcx16. (libatomic_la_LIBADD): Add $(addsuffix _16_2_.lo,$(SIZEOBJS)) for x86_64. * Makefile.in: Regenerated. * config/x86/host-config.h (IFUNC_COND_1): For x86_64 define to both AVX and CMPXCHG16B bits. (IFUNC_COND_2): Define. (IFUNC_NCOND): For x86_64 define to 2 * (N == 16). (MAYBE_HAVE_ATOMIC_CAS_16, MAYBE_HAVE_ATOMIC_EXCHANGE_16, MAYBE_HAVE_ATOMIC_LDST_16): Define to IFUNC_COND_2 rather than IFUNC_COND_1. (HAVE_ATOMIC_CAS_16): Redefine to 1 whenever IFUNC_ALT != 0. (HAVE_ATOMIC_LDST_16): Redefine to 1 whenever IFUNC_ALT == 1. (atomic_compare_exchange_n): Define whenever IFUNC_ALT != 0 on x86_64 for N == 16. (__atomic_load_n, __atomic_store_n): Redefine whenever IFUNC_ALT == 1 on x86_64 for N == 16. (atomic_load_n, atomic_store_n): New functions. * config/x86/init.c (__libat_feat1_init): On x86_64 clear bit_AVX if CPU vendor is not Intel. --- libatomic/Makefile.am.jj2022-01-11 23:11:23.597273193 +0100 +++ libatomic/Makefile.am 2022-02-25 17:25:16.298314196 +0100 @@ -138,8 +138,9 @@ IFUNC_OPTIONS= -march=i586 libatomic_la_LIBADD += $(addsuffix _8_1_.lo,$(SIZEOBJS)) endif if ARCH_X86_64 -IFUNC_OPTIONS = -mcx16 -libatomic_la_LIBADD += $(addsuffix _16_1_.lo,$(SIZEOBJS)) +IFUNC_OPTIONS = -mcx16 -mcx16 +libatomic_la_LIBADD += $(addsuffix _16_1_.lo,$(SIZEOBJS)) \ + $(addsuffix _16_2_.lo,$(SIZEOBJS)) endif endif --- libatomic/Makefile.in.jj2020-11-20 13:56:08.766230397 +0100 +++ libatomic/Makefile.in 2022-02-25 17:25:25.585185717 +0100 @@ -96,7 +96,9 @@ target_triplet = @target@ @ARCH_ARM_LINUX_TRUE@@HAVE_IFUNC_TRUE@ $(addsuffix \ @ARCH_ARM_LINUX_TRUE@@HAVE_IFUNC_TRUE@ _8_2_.lo,$(SIZEOBJS)) @ARCH_I386_TRUE@@HAVE_IFUNC_TRUE@am__append_3 = $(addsuffix _8_1_.lo,$(SIZEOBJS)) -@ARCH_X86_64_TRUE@@HAVE_IFUNC_TRUE@am__append_4 = $(addsuffix _16_1_.lo,$(SIZEOBJS)) +@ARCH_X86_64_TRUE@@HAVE_IFUNC_TRUE@am__append_4 = $(addsuffix _16_1_.lo,$(SIZEOBJS)) \ +@ARCH_X86_64_TRUE@@HAVE_IFUNC_TRUE@ $(addsuffix _16_2_.lo,$(SIZEOBJS)) + subdir = . ACLOCAL_M4 = $(top_srcdir)/aclocal.m4 am__aclocal_m4_deps = $(top_srcdir)/../config/acx.m4 \ @@ -435,7 +437,7 @@ libatomic_la_LIBADD = $(foreach s,$(SIZE @ARCH_AARCH64_LINUX_TRUE@@HAVE_IFUNC_TRUE@IFUNC_OPTIONS = -march=armv8-a+lse @ARCH_ARM_LINUX_TRUE@@HAVE_IFUNC_TRUE@IFUNC_OPTIONS = -march=armv7-a+fp -DHAVE_KERNEL64 @ARCH_I386_TRUE@@HAVE_IFUNC_TRUE@IFUNC_OPTIONS = -march=i586 -@ARCH_X86_64_TRUE@@HAVE_IFUNC_TRUE@IFUNC_OPTIONS = -mcx16 +@ARCH_X86_64_TRUE@@HAVE_IFUNC_TRUE@IFUNC_OPTIONS = -mcx16 -mcx16 libatomic_convenience_la_SOURCES = $(libatomic_la_SOURCES) libatomic_convenience_la_LIBADD = $(libatomic_la_LIBADD) MULTISRCTOP = --- libatomic/config/x86/host-config.h.jj 2022-01-11 23:11:23.598273179 +0100 +++ libatomic/config/x86/host-config.h 2022-02-25 17:22:08.732909052 +0100 @@ -55,31 +55,37 @@ load_feat1 (void) } #ifdef __x86_64__ -# define IFUNC_COND_1 (load_feat1 () & bit_CMPXCHG16B) +# define IFUNC_COND_1 ((load_feat1 () & (bit_AVX | bit_CMPXCHG16B)) \ +== (bit_AVX | bit_CMPXCHG16B)) +# define IFUNC_COND_2 (load_feat1 () & bit_CMPXCHG16B) #else # define IFUNC_COND_1 (load_feat1 () & bit_CMPXCHG8B) #endif #ifdef __x86_64__ -# define IFUNC_NCOND(N) (N == 16) +# define IFUNC_NCOND(N) (2 * (N == 16)) #else # define IFUNC_NCOND(N) (N == 8) #endif #ifdef __x86_64__ # undef MAYBE_HAVE_ATOMIC_CAS_16 -#
[PATCH] PR c++/84964: Middle-end patch to expand_call for ICE after sorry.
This patch resolves PR c++/84964 which is an ICE in the middle-end after
emitting a "sorry, unimplemented" message, and is a regression from
earlier releases of GCC. This issue is that after encountering a
function call requiring an unreasonable amount of stack space, the
code continues and falls foul of an assert checking that stack pointer
has been correctly updated. The fix is to (locally) consider aborted
function calls as "no return", which skips this downstream sanity check.
This patch has been tested on x86_64-pc-linux-gnu with make bootstrap
and make -k check with no new failures. Ok for mainline?
2022-02-28 Roger Sayle
gcc/ChangeLog
PR c++/84964
* calls.cc (expand_call): Ignore stack adjustments after sorry.
gcc/testsuite/ChangeLog
PR c++/84964
* g++.dg/pr84964.C: New test case.
Thanks in advance,
Roger
--
diff --git a/gcc/calls.cc b/gcc/calls.cc
index e64a937..d4ee015 100644
--- a/gcc/calls.cc
+++ b/gcc/calls.cc
@@ -3447,6 +3447,8 @@ expand_call (tree exp, rtx target, int ignore)
>= (1 << (HOST_BITS_PER_INT - 2)))
{
sorry ("passing too large argument on stack");
+ /* Don't worry about stack clean-up. */
+ flags |= ECF_NORETURN;
continue;
}
diff --git a/gcc/testsuite/g++.dg/pr84964.C b/gcc/testsuite/g++.dg/pr84964.C
new file mode 100644
index 000..1d0ff20
--- /dev/null
+++ b/gcc/testsuite/g++.dg/pr84964.C
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+struct a {
+ short b : -1ULL; // { dg-warning "exceeds its type" }
+};
+void c(...) { c(a()); } // { dg-message "sorry, unimplemented" }
+
