Re: [PATCH] Fortran: make IEEE_CLASS recognize signaling NaNs
ping > Le 2 janv. 2022 à 11:50, FX a écrit : > > Hi, > > This is the first part of a three-patch series to fix PR 82207 > (https://gcc.gnu.org/bugzilla/show_bug.cgi?id=82207), making gfortran handle > signaling NaNs. This part fixes the library code implementing IEEE_CLASS, by > using the issignaling macro (from TS 18661-1:2014) to check whether a NaN is > signalling. > > The patch comes with a testcase, conditional on issignaling support (which > will therefore run on glibc targets), which uses C built-ins to generate > signaling NaNs and checks in Fortran code that they are classified and behave > as expected. > > Once this is in, the next two parts are: > > - Add support for generating signaling NaNs in IEEE_VALUE, which is a longer > patch because it requires moving the IEEE_VALUE library code from Fortran to > C (but will be much more efficient and correct than the current > implementation). > - Provide a fallback implementation of issignaling on targets that don’t have > it. > > > Bootstrapped and regtested on x86_64-pc-gnu-linux. OK to commit? > > FX > 0001-Fortran-Allow-IEEE_CLASS-to-identify-signaling-NaNs.patch Description: Binary data
[PATCH] Fortran: Ignore KIND argument of a few more intrinsics. [PR103789]
Hello,
I was about to commit the attached patch, but pulling the latest master
brought me a broken bootstrap, so I can’t test it fully right now.
Anyway, it should be non-controversial, and Harald OK'ed a variant in the
PR already.
Bootstrap and regression test and commit pending.
MikaelFrom c1c17a43e172ebc28f2cd247f6e83c5fdbc6219f Mon Sep 17 00:00:00 2001
From: Mikael Morin
Date: Fri, 7 Jan 2022 22:34:59 +0100
Subject: [PATCH] Fortran: Ignore KIND argument of a few more intrinsics. [PR103789]
After PR97896 for which some code was added to ignore the KIND argument
of the INDEX intrinsics, and PR87711 for which that was extended to LEN_TRIM
as well, this propagates it further to MASKL, MASKR, SCAN and VERIFY.
PR fortran/103789
gcc/fortran/ChangeLog:
* trans-array.c (arg_evaluated_for_scalarization): Add MASKL, MASKR,
SCAN and VERIFY to the list of intrinsics whose KIND argument is to be
ignored.
gcc/testsuite/ChangeLog:
* gfortran.dg/maskl_1.f90: New test.
* gfortran.dg/maskr_1.f90: New test.
* gfortran.dg/scan_3.f90: New test.
* gfortran.dg/verify_3.f90: New test.
---
gcc/fortran/trans-array.c | 4
gcc/testsuite/gfortran.dg/maskl_1.f90 | 10 ++
gcc/testsuite/gfortran.dg/maskr_1.f90 | 10 ++
gcc/testsuite/gfortran.dg/scan_3.f90 | 11 +++
gcc/testsuite/gfortran.dg/verify_3.f90 | 11 +++
5 files changed, 46 insertions(+)
create mode 100644 gcc/testsuite/gfortran.dg/maskl_1.f90
create mode 100644 gcc/testsuite/gfortran.dg/maskr_1.f90
create mode 100644 gcc/testsuite/gfortran.dg/scan_3.f90
create mode 100644 gcc/testsuite/gfortran.dg/verify_3.f90
diff --git a/gcc/fortran/trans-array.c b/gcc/fortran/trans-array.c
index 29d08732e1b..a77f3318846 100644
--- a/gcc/fortran/trans-array.c
+++ b/gcc/fortran/trans-array.c
@@ -11500,6 +11500,10 @@ arg_evaluated_for_scalarization (gfc_intrinsic_sym *function,
{
case GFC_ISYM_INDEX:
case GFC_ISYM_LEN_TRIM:
+ case GFC_ISYM_MASKL:
+ case GFC_ISYM_MASKR:
+ case GFC_ISYM_SCAN:
+ case GFC_ISYM_VERIFY:
if (strcmp ("kind", gfc_dummy_arg_get_name (*dummy_arg)) == 0)
return false;
/* Fallthrough. */
diff --git a/gcc/testsuite/gfortran.dg/maskl_1.f90 b/gcc/testsuite/gfortran.dg/maskl_1.f90
new file mode 100644
index 000..9e25c2c9cdc
--- /dev/null
+++ b/gcc/testsuite/gfortran.dg/maskl_1.f90
@@ -0,0 +1,10 @@
+! { dg-do compile }
+!
+! PR fortran/103789
+! Check the absence of ICE when generating calls to MASKL with a KIND argument.
+
+program p
+ integer :: z(2), y(2)
+ y = [1, 13]
+ z = maskl(y, kind=4) + 1
+end program p
diff --git a/gcc/testsuite/gfortran.dg/maskr_1.f90 b/gcc/testsuite/gfortran.dg/maskr_1.f90
new file mode 100644
index 000..ebfd3dbba33
--- /dev/null
+++ b/gcc/testsuite/gfortran.dg/maskr_1.f90
@@ -0,0 +1,10 @@
+! { dg-do compile }
+!
+! PR fortran/103789
+! Check the absence of ICE when generating calls to MASKR with a KIND argument.
+
+program p
+ integer :: z(2), y(2)
+ y = [1, 13]
+ z = maskr(y, kind=4) + 1
+end program p
diff --git a/gcc/testsuite/gfortran.dg/scan_3.f90 b/gcc/testsuite/gfortran.dg/scan_3.f90
new file mode 100644
index 000..80262ae2167
--- /dev/null
+++ b/gcc/testsuite/gfortran.dg/scan_3.f90
@@ -0,0 +1,11 @@
+! { dg-do compile }
+!
+! PR fortran/103789
+! Check the absence of ICE when generating calls to SCAN with a KIND argument.
+
+program p
+ character(len=10) :: y(2)
+ integer :: z(2)
+ y = ['abc', 'def']
+ z = scan(y, 'e', kind=4) + 1
+end program p
diff --git a/gcc/testsuite/gfortran.dg/verify_3.f90 b/gcc/testsuite/gfortran.dg/verify_3.f90
new file mode 100644
index 000..f01e24e199e
--- /dev/null
+++ b/gcc/testsuite/gfortran.dg/verify_3.f90
@@ -0,0 +1,11 @@
+! { dg-do compile }
+!
+! PR fortran/103789
+! Check the absence of ICE when generating calls to VERIFY with a KIND argument.
+
+program p
+ character(len=10) :: y(2)
+ integer :: z(2)
+ y = ['abc', 'def']
+ z = verify(y, 'e', kind=4) + 1
+end program p
--
2.34.1
[power-ieee128, patch, committed] Implement CONVERT specifier
Hi,
I just pushed the attached patch to the branch. It works with the
attached test case for -mabi=ibmlongdouble and -mabi=ieeelongdouble.
The test case is not quite ready for inclusion in the test suite;
it still leaves its last data files behind, and it needs to be
dejagnuified and put with the right options into the right
directory. Not quite sure how to do this.
Still to do: the environment variables and -fconvert.
For the -fconvert option, I would like to see the same sort
of syntax as in the convert option, something like
-fconvert=r16_ieee,big-endian
but I do not know how to massage the *.opt files to accomplish
that.
Regarding specifying via environment variables: Next on
my agenda.
So, here's the patch.
Implement CONVERT specifier for OPEN.
This patch, based on Jakub's work, implements the CONVERT
specifier for the power-ieee128 brach. It allows specifying
the conversion as r16_ieee,big_endian and the other way around,
based on a table. Setting the conversion via environment
variable and via program option does not yet work.
gcc/ChangeLog:
* flag-types.h (enum gfc_convert): Add flags for
conversion.
gcc/fortran/ChangeLog:
* libgfortran.h (unit_convert): Add flags.
libgfortran/ChangeLog:
* Makefile.in: Regenerate.
* io/file_pos.c (unformatted_backspace): Mask off
R16 parts for convert.
* io/inquire.c (inquire_via_unit): Add cases for
R16 parts.
* io/open.c (st_open): Add cases for R16 conversion.
* io/transfer.c (unformatted_read): Adjust for R16 conversions.
(unformatted_write): Likewise.
(us_read): Mask of R16 bits.
(data_transfer_init): Likewiese.
(write_us_marker): Likewise.
! { dg-do run }
program tescht
implicit none
real (kind=16), parameter :: one_third = 3
call test_sanity
call test_sanity("r16_ieee")
call test_sanity("r16_ieee,big_endian")
call test_sanity("r16_ibm")
call test_sanity("big_endian,r16_ibm")
call test_ibm("r16_ibm")
call test_ibm("r16_ibm,swap")
call test_ibm("r16_ibm,big_endian")
call test_ibm("r16_ibm,little_endian")
call test_ibm("swap,r16_ibm")
call test_ibm("big_endian,r16_ibm")
call test_ibm("little_endian,r16_ibm")
contains
subroutine test_sanity(convert)
character(len=*), optional :: convert
real(kind=16) :: a, b, c, d
complex(kind=16) :: c1, c2
real(kind=16) :: arr(2)
complex(kind=16), dimension(10) :: c_arr
real(kind=16), dimension(10) :: a_arr, b_arr
integer :: i
if (present(convert)) then
open(10,file="dat",form="unformatted",convert=convert,status="replace")
else
open(10,file="dat",form="unformatted",status="replace")
end if
a = atan(1._16)*4
! Writing a single value and reading it back again
write (10) a
rewind (10)
read (10) b
if (abs(a-b) > 1e-30) stop 10
! Writing out a KIND=16 complex number and reading
! it back again
rewind(10)
c1 = cmplx(a, one_third,16)
rewind(10)
write (10) c1
rewind(10)
c2 = 0
read (10) c2
if (abs(c1 - c2) > 1e-10) stop 11
! Reading it back in as two reals
rewind(10)
read (10) c,d
if (abs(c-a) > 1e-30 .or. abs(d-one_third) > 1e-30) stop 12
! Reading it back as an array of two reals
rewind(10)
read (10) arr
if (abs(arr(1) - a) > 1e-30 .or. abs(arr(2) - one_third) > 1e-30) stop 13
close(10)
! Writing out a complex array
c_arr = [(1._16/(1._16+cmplx(0,i,16)),i=1,size(c_arr))]
rewind(10)
write (10) c_arr
rewind(10)
read (10) (a_arr(i), b_arr(i),i=1,10)
if (any (abs(real(c_arr)-a_arr) > 1e-30) .or. any(abs(aimag(c_arr)-b_arr) > 1e-30)) stop 14
end subroutine test_sanity
subroutine test_ibm(convert)
! Specific checks for writing and reading IBM long doubles as pairs
! of doubles.
character(len=*) :: convert
double precision:: x1, x2, x3, x4
real(kind=16) :: a, b, c
complex(kind=16) :: c1, c2
real(kind=16) :: rf(2)
a = atan(1._16)*4
open (10,file=convert // ".dat",status="replace",form ="unformatted",convert=convert)
! Writing a single value and reading it back again
write (10) a
rewind(10)
read (10) b
if (abs(a-b) > 1e-30) stop 1
return
! Writing out a KIND=16 value and reading it back again as a
! pair of doubles.
rewind(10)
read (10) x1, x2
b = real(x1,kind=16) + real(x2,kind=16)
if (abs(a-b) > 1e-30) stop 2
! Writing out a KIND=16 complex number and reading
! it back again
rewind (10)
c1 = cmplx(a, one_third,16)
write (10) c1
rewind (10)
read (10) c2
if (abs(c1 - c2) > 1e-10) stop 3
! Reading it back as a KIND=16 REAL array
rewind(10)
read (10) rf
if (abs(rf(1) - a) > 1e-30 .or. abs(rf(2) - one_third) > 1e-30) stop 4
! Reading it back as four double precision values
rewind (10)
read (10) x1, x2, x3, x4
b = real(x1,kind=16) + real(x2,ki
Re: [PATCH] Fortran: Ignore KIND argument of a few more intrinsics. [PR103789]
Le 09/01/2022 à 15:10, Mikael Morin a écrit : pulling the latest master brought me a broken bootstrap It was a user error (of course). Bootstrap and regression test and commit pending. Now tested and committed as r12-6386-gc1c17a43e172ebc28f2cd247f6e83c5fdbc6219f
Re: [PATCH] PR fortran/101762 - ICE on non-constant pointer initialization targets
Le 03/01/2022 à 20:45, Harald Anlauf via Fortran a écrit : Dear all, the initial-data-target for a pointer initialization can be either NULL() or a non-constant target. In the latter case subscripts of the target specification (or substring starting and ending points) must be constant expressions. The patch adds corresponding checks. I have verified that current Intel and Cray compilers generate similar errors for the testcase. Regtested on x86_64-pc-linux-gnu. OK for mainline? Hello, There is gfc_check_pointer_assign which does already various checks relating to pointer assignment, and those with is_init_expr == true could be tightened a bit. OK with your additional checks moved there. Thanks.
Re: [PATCH] Fortran: make IEEE_CLASS recognize signaling NaNs
Le 09/01/2022 à 11:52, FX via Fortran a écrit : ping Le 2 janv. 2022 à 11:50, FX a écrit : Hi, This is the first part of a three-patch series to fix PR 82207 (https://gcc.gnu.org/bugzilla/show_bug.cgi?id=82207), making gfortran handle signaling NaNs. This part fixes the library code implementing IEEE_CLASS, by using the issignaling macro (from TS 18661-1:2014) to check whether a NaN is signalling. The patch comes with a testcase, conditional on issignaling support (which will therefore run on glibc targets), which uses C built-ins to generate signaling NaNs and checks in Fortran code that they are classified and behave as expected. Once this is in, the next two parts are: - Add support for generating signaling NaNs in IEEE_VALUE, which is a longer patch because it requires moving the IEEE_VALUE library code from Fortran to C (but will be much more efficient and correct than the current implementation). - Provide a fallback implementation of issignaling on targets that don’t have it. Bootstrapped and regtested on x86_64-pc-gnu-linux. OK to commit? FX Hello, this is touching areas that I don’t know very much, but it looks reasonable, so without any other comment, please proceed. Thanks.
Re: [PATCH] PR fortran/103777 - ICE in gfc_simplify_maskl, at fortran/simplify.c:4918
Le 06/01/2022 à 22:44, Mikael Morin a écrit : Le 06/01/2022 à 20:50, Harald Anlauf a écrit : Did you find the time to try your version? Not yet. But I have not (yet) forgotten about this. I have looked at it, and it enables infinite mutual recursion between gfc_intrinsic_func_interface and gfc_simplify_expr, so it breaks heavily. I am still looking at it, but let’s proceed with your original patch for now. Thanks.
Re: [PATCH] PR fortran/101762 - ICE on non-constant pointer initialization targets
Hi Mikael,
Am 09.01.22 um 20:28 schrieb Mikael Morin:
Le 03/01/2022 à 20:45, Harald Anlauf via Fortran a écrit :
Dear all,
the initial-data-target for a pointer initialization can be either
NULL() or a non-constant target. In the latter case subscripts of
the target specification (or substring starting and ending points)
must be constant expressions. The patch adds corresponding checks.
I have verified that current Intel and Cray compilers generate similar
errors for the testcase.
Regtested on x86_64-pc-linux-gnu. OK for mainline?
Hello,
There is gfc_check_pointer_assign which does already various checks
relating to pointer assignment, and those with is_init_expr == true
could be tightened a bit.
agreed, this is a more appropriate location for this kind of checks.
OK with your additional checks moved there.
Thanks.
Done so and pushed as r12-6387, see attached updated patch.
Thanks for the review!
From 2e63128306ff93d8f53119137dd6c28b2defac94 Mon Sep 17 00:00:00 2001
From: Harald Anlauf
Date: Sun, 9 Jan 2022 22:08:14 +0100
Subject: [PATCH] Fortran: reject invalid non-constant pointer initialization
targets
gcc/fortran/ChangeLog:
PR fortran/101762
* expr.c (gfc_check_pointer_assign): For pointer initialization
targets, check that subscripts and substring indices in
specifications are constant expressions.
gcc/testsuite/ChangeLog:
PR fortran/101762
* gfortran.dg/pr101762.f90: New test.
---
gcc/fortran/expr.c | 34 ++
gcc/testsuite/gfortran.dg/pr101762.f90 | 23 +
2 files changed, 57 insertions(+)
create mode 100644 gcc/testsuite/gfortran.dg/pr101762.f90
diff --git a/gcc/fortran/expr.c b/gcc/fortran/expr.c
index 96a2cd70900..a87686d8217 100644
--- a/gcc/fortran/expr.c
+++ b/gcc/fortran/expr.c
@@ -4343,6 +4343,7 @@ gfc_check_pointer_assign (gfc_expr *lvalue, gfc_expr *rvalue,
{
gfc_symbol *sym;
bool target;
+ gfc_ref *ref;
if (gfc_is_size_zero_array (rvalue))
{
@@ -4372,6 +4373,39 @@ gfc_check_pointer_assign (gfc_expr *lvalue, gfc_expr *rvalue,
&rvalue->where);
return false;
}
+
+ for (ref = rvalue->ref; ref; ref = ref->next)
+ {
+ switch (ref->type)
+ {
+ case REF_ARRAY:
+ for (int n = 0; n < ref->u.ar.dimen; n++)
+ if (!gfc_is_constant_expr (ref->u.ar.start[n])
+ || !gfc_is_constant_expr (ref->u.ar.end[n])
+ || !gfc_is_constant_expr (ref->u.ar.stride[n]))
+ {
+ gfc_error ("Every subscript of target specification "
+ "at %L must be a constant expression",
+ &ref->u.ar.where);
+ return false;
+ }
+ break;
+
+ case REF_SUBSTRING:
+ if (!gfc_is_constant_expr (ref->u.ss.start)
+ || !gfc_is_constant_expr (ref->u.ss.end))
+ {
+ gfc_error ("Substring starting and ending points of target "
+ "specification at %L must be constant expressions",
+ &ref->u.ss.start->where);
+ return false;
+ }
+ break;
+
+ default:
+ break;
+ }
+ }
}
else
{
diff --git a/gcc/testsuite/gfortran.dg/pr101762.f90 b/gcc/testsuite/gfortran.dg/pr101762.f90
new file mode 100644
index 000..9ffd7540d81
--- /dev/null
+++ b/gcc/testsuite/gfortran.dg/pr101762.f90
@@ -0,0 +1,23 @@
+! { dg-do compile }
+! PR fortran/101762 - ICE on non-constant pointer initialization targets
+! Contributed by G.Steinmetz
+
+program p
+ integer, target :: a(3) = [7, 8, 9]
+ integer, pointer :: x=> a(3)
+ integer, pointer :: y=> a(n()) ! { dg-error "constant expression" }
+ integer, pointer :: z(:) => a(:n()) ! { dg-error "constant expression" }
+ character(7), target :: c= "abcdefg"
+ character(3), pointer :: c0 => c(2:4)
+ character(3), pointer :: c1 => c(m():) ! { dg-error "constant expression" }
+ character(3), pointer :: c2 => c(:m()) ! { dg-error "constant expression" }
+ print *, x, y
+contains
+ pure integer function k ()
+k = 2
+ end function k
+ subroutine s ()
+integer, pointer :: yy => a(k()) ! { dg-error "constant expression" }
+print *, yy
+ end subroutine s
+end
--
2.31.1
Re: [PATCH] PR fortran/103777 - ICE in gfc_simplify_maskl, at fortran/simplify.c:4918
Am 09.01.22 um 21:12 schrieb Mikael Morin: Le 06/01/2022 à 22:44, Mikael Morin a écrit : Le 06/01/2022 à 20:50, Harald Anlauf a écrit : Did you find the time to try your version? Not yet. But I have not (yet) forgotten about this. I have looked at it, and it enables infinite mutual recursion between gfc_intrinsic_func_interface and gfc_simplify_expr, so it breaks heavily. I am still looking at it, but let’s proceed with your original patch for now. OK, done so. It should not prevent a better solution later... Thanks. Thanks, Harald
PING^2: [PATCH] Add --enable-first-stage-cross configure option
Ping: [PATCH] Add --enable-first-stage-cross configure option
https://gcc.gnu.org/pipermail/gcc-patches/2021-July/575318.html
Add --enable-first-stage-cross configure option
Build static-only, C-only compiler that is sufficient to cross compile
glibc. This option disables various runtime libraries that require
libc to compile, turns on --with-newlib, --without-headers,
--disable-decimal-float, --disable-shared, --disable-threads, and sets
--enable-languages=c.
Rationale: current way of building first stage compiler of a cross
toolchain requires specifying a list of target libraries that are not
going to be compiled due to their dependency on target libc. This
list is not documented in gccinstall.texi and sometimes changes. To
simplify the procedure, it is better to maintain that list in the GCC
itself.
Usage example as a patch to glibc's scripts/build-many-libcs.py:
diff --git a/scripts/build-many-glibcs.py b/scripts/build-many-glibcs.py
index 580d25e8ee..3a6a7be76b 100755
--- a/scripts/build-many-glibcs.py
+++ b/scripts/build-many-glibcs.py
@@ -1446,17 +1446,7 @@ class Config(object):
# required to define inhibit_libc (to stop some parts of
# libgcc including libc headers); --without-headers is not
# sufficient.
-cfg_opts += ['--enable-languages=c', '--disable-shared',
- '--disable-threads',
- '--disable-libatomic',
- '--disable-decimal-float',
- '--disable-libffi',
- '--disable-libgomp',
- '--disable-libitm',
- '--disable-libmpx',
- '--disable-libquadmath',
- '--disable-libsanitizer',
- '--without-headers', '--with-newlib',
+cfg_opts += ['--enable-first-stage-cross',
'--with-glibc-version=%s' % self.ctx.glibc_version
]
cfg_opts += self.first_gcc_cfg
Bootstrapped/regtested on x86_64-pc-linux-gnu, and
tested with build-many-glibcs.py with the above patch.
OK for mainline?
ChangeLog:
* configure.ac: Add --enable-first-stage-cross.
* configure: Regenerate.
gcc/ChangeLog:
* doc/install.texi: Document --enable-first-stage-cross.
---
configure| 20
configure.ac | 15 +++
gcc/doc/install.texi | 7 +++
3 files changed, 42 insertions(+)
diff --git a/configure b/configure
index 9c2d7df1bb2..44f6ebcb947 100755
--- a/configure
+++ b/configure
@@ -794,6 +794,7 @@ ac_user_opts='
enable_option_checking
with_build_libsubdir
with_system_zlib
+enable_first_stage_cross
enable_as_accelerator_for
enable_offload_targets
enable_offload_defaulted
@@ -1522,6 +1523,9 @@ Optional Features:
--disable-option-checking ignore unrecognized --enable/--with options
--disable-FEATURE do not include FEATURE (same as --enable-FEATURE=no)
--enable-FEATURE[=ARG] include FEATURE [ARG=yes]
+ --enable-first-stage-cross
+ Build a static-only compiler that is sufficient to
+ build glibc.
--enable-as-accelerator-for=ARG
build as offload target compiler. Specify offload
host triple by ARG
@@ -2971,6 +2975,22 @@ case $is_cross_compiler in
no) skipdirs="${skipdirs} ${cross_only}" ;;
esac
+# Check whether --enable-first-stage-cross was given.
+if test "${enable_first_stage_cross+set}" = set; then :
+ enableval=$enable_first_stage_cross; ENABLE_FIRST_STAGE_CROSS=$enableval
+else
+ ENABLE_FIRST_STAGE_CROSS=no
+fi
+
+case "${ENABLE_FIRST_STAGE_CROSS}" in
+ yes)
+noconfigdirs="$noconfigdirs target-libatomic target-libquadmath
target-libgomp target-libssp"
+host_configargs="$host_configargs --disable-shared --disable-threads
--disable-decimal-float --without-headers --with-newlib"
+target_configargs="$target_configargs --disable-shared"
+enable_languages=c
+;;
+esac
+
# If both --with-headers and --with-libs are specified, default to
# --without-newlib.
if test x"${with_headers}" != x && test x"${with_headers}" != xno \
diff --git a/configure.ac b/configure.ac
index 68cc5cc31fe..84ae8210a72 100644
--- a/configure.ac
+++ b/configure.ac
@@ -268,6 +268,21 @@ case $is_cross_compiler in
no) skipdirs="${skipdirs} ${cross_only}" ;;
esac
+AC_ARG_ENABLE(first-stage-cross,
+[AS_HELP_STRING([--enable-first-stage-cross],
+ [Build a static-only compiler that is
+ sufficient to build glibc.])],
+ENABLE_FIRST_STAGE_CROSS=$enableval,
+ENABLE_FIRST_STAGE_CROSS=no)
+case "${ENABLE_FIRST_STAGE_CROSS}" in
+ yes)
+noconfigdirs="$noconfigdirs target-libatomic target-libquadmath
target-libgomp target-libssp"
+host_configargs="$host_configargs --disable-shared --disable-threads
--disable-decimal-float --without-h
Ping^1 [PATCH, rs6000] Fix ICE on expand bcd__ [PR100736]
Hi,
Gentle ping this:
https://gcc.gnu.org/pipermail/gcc-patches/2021-December/587253.html
Thanks
On 21/12/2021 下午 4:19, HAO CHEN GUI wrote:
> Hi,
> This patch fixes the ICE in PR100736. It adds a reverse condition
> comparison when the
> condition code can be reversed and finite-math-only is set.
>
> Bootstrapped and tested on powerpc64-linux BE and LE with no regressions.
> Is this okay for trunk?
> Any recommendations? Thanks a lot.
>
> ChangeLog
> 2021-12-20 Haochen Gui
>
> gcc/
> * config/rs6000/altivec.md (bcd_test_): Named.
> (bcd__): Reverse compare condition if
> finite-math-only is set.
> * config/rs6000/rs6000-protos.c (rs6000_reverse_compare): Defined.
> * config/rs6000/rs6000.c (rs6000_emit_sCOND): Refactored. Call
> rs6000_reverse_compare if the condition code can be reversed.
> (rs6000_reverse_compare): Implemented.
>
> gcc/testsuite/
> * gcc.target/powerpc/pr100736.h: New.
> * gcc.target/powerpc/pr100736.finite.c: New.
> * gcc.target/powerpc/pr100736.infinite.c: New.
>
>
> patch.diff
> diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
> index ef432112333..cc40edc5381 100644
> --- a/gcc/config/rs6000/altivec.md
> +++ b/gcc/config/rs6000/altivec.md
> @@ -4412,7 +4412,7 @@ (define_insn "bcd_"
> ;; UNORDERED test on an integer type (like V1TImode) is not defined. The
> type
> ;; probably should be one that can go in the VMX (Altivec) registers, so we
> ;; can't use DDmode or DFmode.
> -(define_insn "*bcd_test_"
> +(define_insn "bcd_test_"
>[(set (reg:CCFP CR6_REGNO)
> (compare:CCFP
>(unspec:V2DF [(match_operand:VBCD 1 "register_operand" "v")
> @@ -4539,6 +4539,18 @@ (define_expand "bcd__"
>"TARGET_P8_VECTOR"
> {
>operands[4] = CONST0_RTX (V2DFmode);
> + emit_insn (gen_bcd_test_ (operands[0], operands[1],
> +operands[2], operands[3],
> +operands[4]));
> + rtx cr6 = gen_rtx_REG (CCFPmode, CR6_REGNO);
> + rtx condition_rtx = gen_rtx_ (SImode, cr6, const0_rtx);
> + if (flag_finite_math_only)
> +{
> + condition_rtx = rs6000_reverse_compare (condition_rtx);
> + PUT_MODE (condition_rtx, SImode);
> +}
> + emit_insn (gen_rtx_SET (operands[0], condition_rtx));
> + DONE;
> })
>
> (define_insn "*bcdinvalid_"
> diff --git a/gcc/config/rs6000/rs6000-protos.h
> b/gcc/config/rs6000/rs6000-protos.h
> index 14f6b313105..9b93e26bec2 100644
> --- a/gcc/config/rs6000/rs6000-protos.h
> +++ b/gcc/config/rs6000/rs6000-protos.h
> @@ -114,6 +114,7 @@ extern enum rtx_code rs6000_reverse_condition
> (machine_mode,
> extern rtx rs6000_emit_eqne (machine_mode, rtx, rtx, rtx);
> extern rtx rs6000_emit_fp_cror (rtx_code, machine_mode, rtx);
> extern void rs6000_emit_sCOND (machine_mode, rtx[]);
> +extern rtx rs6000_reverse_compare (rtx);
> extern void rs6000_emit_cbranch (machine_mode, rtx[]);
> extern char * output_cbranch (rtx, const char *, int, rtx_insn *);
> extern const char * output_probe_stack_range (rtx, rtx, rtx);
> diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
> index 5e129986516..2f3dd311396 100644
> --- a/gcc/config/rs6000/rs6000.c
> +++ b/gcc/config/rs6000/rs6000.c
> @@ -15653,19 +15653,14 @@ rs6000_emit_fp_cror (rtx_code code, machine_mode
> mode, rtx x)
>return cc;
> }
>
> -void
> -rs6000_emit_sCOND (machine_mode mode, rtx operands[])
> +rtx
> +rs6000_reverse_compare (rtx condition_rtx)
> {
> - rtx condition_rtx = rs6000_generate_compare (operands[1], mode);
>rtx_code cond_code = GET_CODE (condition_rtx);
> -
> - if (FLOAT_MODE_P (mode) && HONOR_NANS (mode)
> - && !(FLOAT128_VECTOR_P (mode) && !TARGET_FLOAT128_HW))
> -;
> - else if (cond_code == NE
> -|| cond_code == GE || cond_code == LE
> -|| cond_code == GEU || cond_code == LEU
> -|| cond_code == ORDERED || cond_code == UNGE || cond_code == UNLE)
> + if (cond_code == NE
> + || cond_code == GE || cond_code == LE
> + || cond_code == GEU || cond_code == LEU
> + || cond_code == ORDERED || cond_code == UNGE || cond_code == UNLE)
> {
>rtx not_result = gen_reg_rtx (CCEQmode);
>rtx not_op, rev_cond_rtx;
> @@ -15679,6 +15674,19 @@ rs6000_emit_sCOND (machine_mode mode, rtx operands[])
>emit_insn (gen_rtx_SET (not_result, not_op));
>condition_rtx = gen_rtx_EQ (VOIDmode, not_result, const0_rtx);
> }
> + return condition_rtx;
> +}
> +
> +void
> +rs6000_emit_sCOND (machine_mode mode, rtx operands[])
> +{
> + rtx condition_rtx = rs6000_generate_compare (operands[1], mode);
> +
> + if (FLOAT_MODE_P (mode) && HONOR_NANS (mode)
> + && !(FLOAT128_VECTOR_P (mode) && !TARGET_FLOAT128_HW))
> + ;
> + else
> +condition_rtx = rs6000_reverse_compare (condition_rtx);
>
>machine_mode op_mode = GET_MODE (XEXP (operands[1], 0));
>if (op_mode == VOIDmode)
> diff --git a/gcc/te
Ping^1 [PATCH, rs6000] new split pattern for TI to V1TI move [PR103124]
Hi,
Gentle ping this:
https://gcc.gnu.org/pipermail/gcc-patches/2021-December/587051.html
Thanks
On 17/12/2021 上午 9:55, HAO CHEN GUI wrote:
> Hi,
>This patch defines a new split pattern for TI to V1TI move. The pattern
> concatenates two subreg:DI of
> a TI to a V2DI. With the pattern, the subreg pass can do register split for
> TI when there is a TI to V1TI
> move. The patch optimizes one unnecessary "mr" out on P9. The new test case
> illustrates it.
>
>Bootstrapped and tested on powerpc64-linux BE and LE with no regressions.
> Is this okay for trunk?
> Any recommendations? Thanks a lot.
>
> ChangeLog
> 2021-12-13 Haochen Gui
>
> gcc/
> * config/rs6000/vsx.md (split pattern for TI to V1TI move): Defined.
>
> gcc/testsuite/
> * gcc.target/powerpc/pr103124.c: New testcase.
>
>
> patch.diff
> diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
> index bf033e31c1c..52968eb4609 100644
> --- a/gcc/config/rs6000/vsx.md
> +++ b/gcc/config/rs6000/vsx.md
> @@ -6589,3 +6589,19 @@ (define_insn "xxeval"
> [(set_attr "type" "vecperm")
> (set_attr "prefixed" "yes")])
>
> +;; Construct V1TI by vsx_concat_v2di
> +(define_split
> + [(set (match_operand:V1TI 0 "vsx_register_operand")
> + (subreg:V1TI
> + (match_operand:TI 1 "int_reg_operand") 0 ))]
> + "TARGET_P9_VECTOR && !reload_completed"
> + [(const_int 0)]
> +{
> + rtx tmp1 = simplify_gen_subreg (DImode, operands[1], TImode, 0);
> + rtx tmp2 = simplify_gen_subreg (DImode, operands[1], TImode, 8);
> + rtx tmp3 = gen_reg_rtx (V2DImode);
> + emit_insn (gen_vsx_concat_v2di (tmp3, tmp1, tmp2));
> + rtx tmp4 = simplify_gen_subreg (V1TImode, tmp3, V2DImode, 0);
> + emit_move_insn (operands[0], tmp4);
> + DONE;
> +})
> diff --git a/gcc/testsuite/gcc.target/powerpc/pr103124.c
> b/gcc/testsuite/gcc.target/powerpc/pr103124.c
> new file mode 100644
> index 000..e9072d19b8e
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/powerpc/pr103124.c
> @@ -0,0 +1,12 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target powerpc_p9vector_ok } */
> +/* { dg-require-effective-target int128 } */
> +/* { dg-options "-O2 -mdejagnu-cpu=power9" } */
> +/* { dg-final { scan-assembler-not "\mmr\M" } } */
> +
> +vector __int128 add (long long a)
> +{
> + vector __int128 b;
> + b = (vector __int128) {a};
> + return b;
> +}
>
Ping^1 [PATCH] Modify combine pattern by a pseudo AND with its nonzero bits [PR93453]
Hi,
Gentle ping this:
https://gcc.gnu.org/pipermail/gcc-patches/2021-December/586304.html
Thanks
On 7/12/2021 下午 4:28, HAO CHEN GUI wrote:
> Hi,
> This patch modifies the combine pattern with a helper -
> change_pseudo_and_mask when recog fails.
> The helper converts a single pseudo to the pseudo AND with a mask if the
> outer operator is IOR/XOR/PLUS
> and the inner operator is ASHIFT/LSHIFTRT/AND. The conversion helps on shift
> + ior pattern.
>
> Not sure if the helper should be a target hook or not. Please advice.
>
> Bootstrapped and tested on powerpc64-linux BE and LE with no regressions.
> Is this okay for trunk?
> Any recommendations? Thanks a lot.
>
> ChangeLog
> 2021-12-07 Haochen Gui
>
> gcc/
> * combine.c (change_pseudo_and_mask): New.
> (recog_for_combine): If recog fails, try again with the pattern
> modified by change_pseudo_and_mask.
> * config/rs6000/rs6000.md (plus_ior_xor): Removed.
> (anonymous split pattern for plus_ior_xor): Likewise.
>
> gcc/testsuite/
> * gcc.target/powerpc/20050603-3.c: Modify dump check conditions.
> * gcc.target/powerpc/rlwimi-2.c: Likewise.
>
> patch.diff
> diff --git a/gcc/combine.c b/gcc/combine.c
> index 03e9a780919..53500e8c6a0 100644
> --- a/gcc/combine.c
> +++ b/gcc/combine.c
> @@ -11539,6 +11539,36 @@ change_zero_ext (rtx pat)
>return changed;
> }
>
> +/* When the outer code of set_src is IOR/XOR/PLUS and the inner code is
> + ASHIFT/LSHIFTRT/AND, convert a pseudo to psuedo AND with a mask if its
> + nonzero_bits is less than its mode mask. The nonzero_bits in other pass
> + doesn't return the same value as it does in combine pass. */
> +static bool
> +change_pseudo_and_mask (rtx pat)
> +{
> + rtx src = SET_SRC (pat);
> + if ((GET_CODE (src) == IOR
> + || GET_CODE (src) == XOR
> + || GET_CODE (src) == PLUS)
> + && (((GET_CODE (XEXP (src, 0)) == ASHIFT
> + || GET_CODE (XEXP (src, 0)) == LSHIFTRT
> + || GET_CODE (XEXP (src, 0)) == AND)
> +&& REG_P (XEXP (src, 1)
> +{
> + rtx *reg = &XEXP (SET_SRC (pat), 1);
> + machine_mode mode = GET_MODE (*reg);
> + unsigned HOST_WIDE_INT nonzero = nonzero_bits (*reg, mode);
> + if (nonzero < GET_MODE_MASK (mode))
> + {
> + rtx x = gen_rtx_AND (mode, *reg, GEN_INT (nonzero));
> + SUBST (*reg, x);
> + maybe_swap_commutative_operands (SET_SRC (pat));
> + return true;
> + }
> + }
> + return false;
> +}
> +
> /* Like recog, but we receive the address of a pointer to a new pattern.
> We try to match the rtx that the pointer points to.
> If that fails, we may try to modify or replace the pattern,
> @@ -11586,7 +11616,10 @@ recog_for_combine (rtx *pnewpat, rtx_insn *insn, rtx
> *pnotes)
> }
> }
>else
> - changed = change_zero_ext (pat);
> + {
> + changed = change_pseudo_and_mask (pat);
> + changed |= change_zero_ext (pat);
> + }
> }
>else if (GET_CODE (pat) == PARALLEL)
> {
> diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
> index 6bec2bddbde..5adbe9e9d27 100644
> --- a/gcc/config/rs6000/rs6000.md
> +++ b/gcc/config/rs6000/rs6000.md
> @@ -4149,24 +4149,6 @@ (define_insn "rotl3_insert_3"
> }
>[(set_attr "type" "insert")])
>
> -(define_code_iterator plus_ior_xor [plus ior xor])
> -
> -(define_split
> - [(set (match_operand:GPR 0 "gpc_reg_operand")
> - (plus_ior_xor:GPR (ashift:GPR (match_operand:GPR 1 "gpc_reg_operand")
> - (match_operand:SI 2 "const_int_operand"))
> - (match_operand:GPR 3 "gpc_reg_operand")))]
> - "nonzero_bits (operands[3], mode)
> - < HOST_WIDE_INT_1U << INTVAL (operands[2])"
> - [(set (match_dup 0)
> - (ior:GPR (and:GPR (match_dup 3)
> - (match_dup 4))
> - (ashift:GPR (match_dup 1)
> - (match_dup 2]
> -{
> - operands[4] = GEN_INT ((HOST_WIDE_INT_1U << INTVAL (operands[2])) - 1);
> -})
> -
> (define_insn "*rotl3_insert_4"
>[(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
> (ior:GPR (and:GPR (match_operand:GPR 3 "gpc_reg_operand" "0")
> diff --git a/gcc/testsuite/gcc.target/powerpc/20050603-3.c
> b/gcc/testsuite/gcc.target/powerpc/20050603-3.c
> index 4017d34f429..e628be11532 100644
> --- a/gcc/testsuite/gcc.target/powerpc/20050603-3.c
> +++ b/gcc/testsuite/gcc.target/powerpc/20050603-3.c
> @@ -12,7 +12,7 @@ void rotins (unsigned int x)
>b.y = (x<<12) | (x>>20);
> }
>
> -/* { dg-final { scan-assembler-not {\mrlwinm} } } */
> +/* { dg-final { scan-assembler-not {\mrlwinm} { target ilp32 } } } */
> /* { dg-final { scan-assembler-not {\mrldic} } } */
> /* { dg-final { scan-assembler-not {\mrot[lr]} } } */
> /* { dg-final { scan-assembler-not {\ms[lr][wd]} } } */
> diff --git a/gcc/testsuite/gcc.target/powerpc/rlwimi-2.c
> b/gcc/testsuite/gcc.target/powerpc/rlwimi-2.c
>
Ping: [PATCH] rs6000: Add split pattern to replace
Gentle ping, thanks.
On 2021/12/29 09:27, Xionghu Luo wrote:
> 7: r120:V4SI=const_vector
> 8: r121:V4SI=unspec[r120:V4SI,r120:V4SI,0xc] 260
>
> with r121:v4SI = r120:V4SI when r120 is a vector with same element.
>
> Bootstrapped and regtested pass on powerpc64le-linux-gnu {P10, P9}
> and powerpc64-linux-gnu {P8, P7}. OK for master?
>
> gcc/ChangeLog:
>
> * config/rs6000/altivec.md (sldoi_to_mov_): New.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/powerpc/sldoi_to_mov.c: New test.
> ---
> gcc/config/rs6000/altivec.md| 11 +++
> gcc/testsuite/gcc.target/powerpc/sldoi_to_mov.c | 15 +++
> 2 files changed, 26 insertions(+)
> create mode 100644 gcc/testsuite/gcc.target/powerpc/sldoi_to_mov.c
>
> diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
> index b2909857c34..25f86dbe828 100644
> --- a/gcc/config/rs6000/altivec.md
> +++ b/gcc/config/rs6000/altivec.md
> @@ -383,6 +383,17 @@ (define_split
> }
> })
>
> +(define_insn_and_split "sldoi_to_mov_"
> + [(set (match_operand:VM 0 "altivec_register_operand")
> + (unspec:VM [(match_operand:VM 1 "easy_vector_constant")
> + (match_dup 1)
> + (match_operand:VM 2 "u5bit_cint_operand")]
> + UNSPEC_VSLDOI))]
> + "VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode) && can_create_pseudo_p ()"
> + "#"
> + "&& 1"
> + [(set (match_dup 0) (match_dup 1))])
> +
> (define_insn "get_vrsave_internal"
>[(set (match_operand:SI 0 "register_operand" "=r")
> (unspec:SI [(reg:SI VRSAVE_REGNO)] UNSPEC_GET_VRSAVE))]
> diff --git a/gcc/testsuite/gcc.target/powerpc/sldoi_to_mov.c
> b/gcc/testsuite/gcc.target/powerpc/sldoi_to_mov.c
> new file mode 100644
> index 000..2053243c456
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/powerpc/sldoi_to_mov.c
> @@ -0,0 +1,15 @@
> +/* { dg-do compile } */
> +/* { dg-options "-O2" } */
> +
> +#include
> +vector signed int foo1 (vector signed int a) {
> +vector signed int b = {0};
> +return vec_sum2s(a, b);
> +}
> +
> +vector signed int foo2 (vector signed int a) {
> +vector signed int b = {0};
> +return vec_sld(b, b, 4);
> +}
> +
> +/* { dg-final { scan-assembler-times {\mvsldoi\M} 1 {target le} } } */
--
Thanks,
Xionghu
Ping: [PATCH] rs6000: powerpc suboptimal boolean test of contiguous bits [PR102239]
Ping, thanks.
On 2021/12/13 13:16, Xionghu Luo wrote:
> Add specialized version to combine two instructions from
>
> 9: {r123:CC=cmp(r124:DI&0x6,0);clobber scratch;}
>REG_DEAD r124:DI
> 10: pc={(r123:CC==0)?L15:pc}
> REG_DEAD r123:CC
>
> to:
>
> 10: {pc={(r123:DI&0x6==0)?L15:pc};clobber scratch;clobber %0:CC;}
>
> then split2 will split it to one rotate dot instruction (to save one
> rotate back instruction) as shifted result doesn't matter when comparing
> to 0 in CCEQmode.
>
> Bootstrapped and regression tested pass on Power 8/9/10, OK for master?
>
> gcc/ChangeLog:
>
> PR target/102239
> * config/rs6000/rs6000.md (*anddi3_insn_dot): New.
>
> gcc/testsuite/ChangeLog:
>
> PR target/102239
> * gcc.target/powerpc/pr102239.c: New test.
> ---
> gcc/config/rs6000/rs6000-protos.h | 1 +
> gcc/config/rs6000/rs6000.c | 7
> gcc/config/rs6000/rs6000.md | 38 +
> gcc/testsuite/gcc.target/powerpc/pr102239.c | 13 +++
> 4 files changed, 59 insertions(+)
> create mode 100644 gcc/testsuite/gcc.target/powerpc/pr102239.c
>
> diff --git a/gcc/config/rs6000/rs6000-protos.h
> b/gcc/config/rs6000/rs6000-protos.h
> index 14f6b313105..3644c524376 100644
> --- a/gcc/config/rs6000/rs6000-protos.h
> +++ b/gcc/config/rs6000/rs6000-protos.h
> @@ -73,6 +73,7 @@ extern int expand_block_move (rtx[], bool);
> extern bool expand_block_compare (rtx[]);
> extern bool expand_strn_compare (rtx[], int);
> extern bool rs6000_is_valid_mask (rtx, int *, int *, machine_mode);
> +extern bool rs6000_is_valid_rotate_dot_mask (rtx mask, machine_mode mode);
> extern bool rs6000_is_valid_and_mask (rtx, machine_mode);
> extern bool rs6000_is_valid_shift_mask (rtx, rtx, machine_mode);
> extern bool rs6000_is_valid_insert_mask (rtx, rtx, machine_mode);
> diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
> index 5e129986516..57a38cf954a 100644
> --- a/gcc/config/rs6000/rs6000.c
> +++ b/gcc/config/rs6000/rs6000.c
> @@ -11606,6 +11606,13 @@ rs6000_is_valid_mask (rtx mask, int *b, int *e,
> machine_mode mode)
>return true;
> }
>
> +bool
> +rs6000_is_valid_rotate_dot_mask (rtx mask, machine_mode mode)
> +{
> + int nb, ne;
> + return rs6000_is_valid_mask (mask, &nb, &ne, mode) && nb >= ne && ne > 0;
> +}
> +
> /* Return whether MASK (a CONST_INT) is a valid mask for any rlwinm, rldicl,
> or rldicr instruction, to implement an AND with it in mode MODE. */
>
> diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
> index 6bec2bddbde..014dc9612ea 100644
> --- a/gcc/config/rs6000/rs6000.md
> +++ b/gcc/config/rs6000/rs6000.md
> @@ -3762,6 +3762,44 @@ (define_insn_and_split "*and3_2insn_dot2"
> (set_attr "dot" "yes")
> (set_attr "length" "8,12")])
>
> +(define_insn_and_split "*anddi3_insn_dot"
> + [(set (pc)
> +(if_then_else (eq (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
> + (match_operand:DI 2 "const_int_operand" "n,n"))
> + (const_int 0))
> + (label_ref (match_operand 3 ""))
> + (pc)))
> + (clobber (match_scratch:DI 0 "=r,r"))
> + (clobber (reg:CC CR0_REGNO))]
> + "rs6000_is_valid_rotate_dot_mask (operands[2], DImode)
> + && TARGET_POWERPC64"
> + "#"
> + "&& reload_completed"
> + [(pc)]
> +{
> + int nb, ne;
> + if (rs6000_is_valid_mask (operands[2], &nb, &ne, DImode)
> + && nb >= ne
> + && ne > 0)
> + {
> + unsigned HOST_WIDE_INT val = INTVAL (operands[2]);
> + int shift = 63 - nb;
> + rtx tmp = gen_rtx_ASHIFT (DImode, operands[1], GEN_INT (shift));
> + tmp = gen_rtx_AND (DImode, tmp, GEN_INT (val << shift));
> + rtx cr0 = gen_rtx_REG (CCmode, CR0_REGNO);
> + rs6000_emit_dot_insn (operands[0], tmp, 1, cr0);
> + rtx loc_ref = gen_rtx_LABEL_REF (VOIDmode, operands[3]);
> + rtx cond = gen_rtx_EQ (CCEQmode, cr0, const0_rtx);
> + rtx ite = gen_rtx_IF_THEN_ELSE (VOIDmode, cond, loc_ref, pc_rtx);
> + emit_jump_insn (gen_rtx_SET (pc_rtx, ite));
> + DONE;
> + }
> + else
> + FAIL;
> +}
> + [(set_attr "type" "shift")
> + (set_attr "dot" "yes")
> + (set_attr "length" "8,12")])
>
> (define_expand "3"
>[(set (match_operand:SDI 0 "gpc_reg_operand")
> diff --git a/gcc/testsuite/gcc.target/powerpc/pr102239.c
> b/gcc/testsuite/gcc.target/powerpc/pr102239.c
> new file mode 100644
> index 000..1bafc9fe18e
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/powerpc/pr102239.c
> @@ -0,0 +1,13 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target lp64 } */
> +/* { dg-options "-O2" } */
> +
> +void foo(long arg)
> +{
> + if (arg & ((1UL << 33) | (1UL << 34)))
> +asm volatile("# if");
> + else
> +asm volatile("# else");
> +}
> +
> +/* { dg-final { scan-assembler-times "rldicr." 1 } } */
--
Thanks,
Xionghu
[PATCH] [i386] Remove register restriction on operands for andnot insn
Hi all,
This patch removes the register restriction on operands for andnot insn so that
it can be used from memory.
Regtested on x86_64-pc-linux-gnu. Ok for trunk?
BRs,
Haochen
gcc/ChangeLog:
PR target/53652
* config/i386/sse.md (*andnot3): Remove register restriction.
gcc/testsuite/ChangeLog:
PR target/53652
* gcc.target/i386/pr53652-1.c: New test.
---
gcc/config/i386/sse.md| 2 +-
gcc/testsuite/gcc.target/i386/pr53652-1.c | 16
2 files changed, 17 insertions(+), 1 deletion(-)
create mode 100644 gcc/testsuite/gcc.target/i386/pr53652-1.c
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 0997d9edf9d..4448b875d35 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -16630,7 +16630,7 @@
(define_insn "*andnot3"
[(set (match_operand:VI 0 "register_operand" "=x,x,v")
(and:VI
- (not:VI (match_operand:VI 1 "register_operand" "0,x,v"))
+ (not:VI (match_operand:VI 1 "vector_operand" "0,x,v"))
(match_operand:VI 2 "bcst_vector_operand" "xBm,xm,vmBr")))]
"TARGET_SSE"
{
diff --git a/gcc/testsuite/gcc.target/i386/pr53652-1.c
b/gcc/testsuite/gcc.target/i386/pr53652-1.c
new file mode 100644
index 000..bd07ee29f4d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr53652-1.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-final { scan-assembler-times "pandn\[ \\t\]" 2 } } */
+/* { dg-final { scan-assembler-not "vpternlogq\[ \\t\]" } } */
+
+typedef unsigned long long vec __attribute__((vector_size (16)));
+vec g;
+vec f1 (vec a, vec b)
+{
+ return ~a&b;
+}
+vec f2 (vec a, vec b)
+{
+ return ~g&b;
+}
+
--
2.18.1
Re: [PATCH] [i386] Remove register restriction on operands for andnot insn
On Mon, Jan 10, 2022 at 2:23 PM Haochen Jiang via Gcc-patches
wrote:
>
> Hi all,
>
> This patch removes the register restriction on operands for andnot insn so
> that it can be used from memory.
>
> Regtested on x86_64-pc-linux-gnu. Ok for trunk?
>
> BRs,
> Haochen
>
> gcc/ChangeLog:
>
> PR target/53652
> * config/i386/sse.md (*andnot3): Remove register restriction.
It should be "Extend predicate of operands[1] from register_operand to
vector_operand".
Similar for you commit message.
>
> gcc/testsuite/ChangeLog:
>
> PR target/53652
> * gcc.target/i386/pr53652-1.c: New test.
> ---
> gcc/config/i386/sse.md| 2 +-
> gcc/testsuite/gcc.target/i386/pr53652-1.c | 16
> 2 files changed, 17 insertions(+), 1 deletion(-)
> create mode 100644 gcc/testsuite/gcc.target/i386/pr53652-1.c
>
> diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
> index 0997d9edf9d..4448b875d35 100644
> --- a/gcc/config/i386/sse.md
> +++ b/gcc/config/i386/sse.md
> @@ -16630,7 +16630,7 @@
> (define_insn "*andnot3"
>[(set (match_operand:VI 0 "register_operand" "=x,x,v")
> (and:VI
> - (not:VI (match_operand:VI 1 "register_operand" "0,x,v"))
> + (not:VI (match_operand:VI 1 "vector_operand" "0,x,v"))
> (match_operand:VI 2 "bcst_vector_operand" "xBm,xm,vmBr")))]
>"TARGET_SSE"
> {
> diff --git a/gcc/testsuite/gcc.target/i386/pr53652-1.c
> b/gcc/testsuite/gcc.target/i386/pr53652-1.c
> new file mode 100644
> index 000..bd07ee29f4d
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/pr53652-1.c
> @@ -0,0 +1,16 @@
> +/* { dg-do compile } */
> +/* { dg-options "-O2 -msse2" } */
> +/* { dg-final { scan-assembler-times "pandn\[ \\t\]" 2 } } */
> +/* { dg-final { scan-assembler-not "vpternlogq\[ \\t\]" } } */
> +
> +typedef unsigned long long vec __attribute__((vector_size (16)));
> +vec g;
> +vec f1 (vec a, vec b)
> +{
> + return ~a&b;
> +}
> +vec f2 (vec a, vec b)
> +{
> + return ~g&b;
> +}
> +
> --
> 2.18.1
>
--
BR,
Hongtao
RE: [PATCH] [i386] Remove register restriction on operands for andnot insn
Hi Hongtao,
I have changed that message in this patch. Ok for trunk?
Thx,
Haochen
-Original Message-
From: Hongtao Liu
Sent: Monday, January 10, 2022 3:25 PM
To: Jiang, Haochen
Cc: GCC Patches ; Liu, Hongtao
Subject: Re: [PATCH] [i386] Remove register restriction on operands for andnot
insn
On Mon, Jan 10, 2022 at 2:23 PM Haochen Jiang via Gcc-patches
wrote:
>
> Hi all,
>
> This patch removes the register restriction on operands for andnot insn so
> that it can be used from memory.
>
> Regtested on x86_64-pc-linux-gnu. Ok for trunk?
>
> BRs,
> Haochen
>
> gcc/ChangeLog:
>
> PR target/53652
> * config/i386/sse.md (*andnot3): Remove register restriction.
It should be "Extend predicate of operands[1] from register_operand to
vector_operand".
Similar for you commit message.
>
> gcc/testsuite/ChangeLog:
>
> PR target/53652
> * gcc.target/i386/pr53652-1.c: New test.
> ---
> gcc/config/i386/sse.md| 2 +-
> gcc/testsuite/gcc.target/i386/pr53652-1.c | 16
> 2 files changed, 17 insertions(+), 1 deletion(-) create mode 100644
> gcc/testsuite/gcc.target/i386/pr53652-1.c
>
> diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index
> 0997d9edf9d..4448b875d35 100644
> --- a/gcc/config/i386/sse.md
> +++ b/gcc/config/i386/sse.md
> @@ -16630,7 +16630,7 @@
> (define_insn "*andnot3"
>[(set (match_operand:VI 0 "register_operand" "=x,x,v")
> (and:VI
> - (not:VI (match_operand:VI 1 "register_operand" "0,x,v"))
> + (not:VI (match_operand:VI 1 "vector_operand" "0,x,v"))
> (match_operand:VI 2 "bcst_vector_operand" "xBm,xm,vmBr")))]
>"TARGET_SSE"
> {
> diff --git a/gcc/testsuite/gcc.target/i386/pr53652-1.c
> b/gcc/testsuite/gcc.target/i386/pr53652-1.c
> new file mode 100644
> index 000..bd07ee29f4d
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/pr53652-1.c
> @@ -0,0 +1,16 @@
> +/* { dg-do compile } */
> +/* { dg-options "-O2 -msse2" } */
> +/* { dg-final { scan-assembler-times "pandn\[ \\t\]" 2 } } */
> +/* { dg-final { scan-assembler-not "vpternlogq\[ \\t\]" } } */
> +
> +typedef unsigned long long vec __attribute__((vector_size (16))); vec
> +g; vec f1 (vec a, vec b) {
> + return ~a&b;
> +}
> +vec f2 (vec a, vec b)
> +{
> + return ~g&b;
> +}
> +
> --
> 2.18.1
>
--
BR,
Hongtao
0001-i386-Extend-predicate-of-operands-1-from-register_op.patch
Description: 0001-i386-Extend-predicate-of-operands-1-from-register_op.patch
Re: [RFC][PATCH 3/N] lto-plugin: Port to C++
On Wed, Jan 5, 2022 at 2:28 PM Martin Liška wrote: > > Hello. > > I'm working on some changes that will be needed for support of ld.mold. > And I would like to have the plugin in C++. Having that, we can utilize basic > contains like std::vector (instead of xrealloc(foo, len + 1)...). > > I split the patch into 2 pieces where the second one is only result > of autoreconf and automake. > > Lightly tested with ld.bfd, ld.gold and lto.exp. With the linker plugin build by GCC using its libstdc++ statically(?) and for example gold (also a C++ application) built by another (GCC) system compiler there might be two different versioned libstdc++ in the process image after dlopening the plugin. Is the libstdc++ "copy" in the plugin sufficiently isolated to not cause problems here? Do we need to pay extra care as to the subset of the C++ standard library we can use (I'm thinking of parts initialized on load time like I/O)? That said, I'm not sure this is worth the trouble. Richard. > > Thoughts? > Thanks, > Martin
