Re: [PATCH] i386: Require TARGET_64BIT for any_mul_highpart peephole

[Uros Bizjak via Gcc-patches]

On Thu, Dec 23, 2021 at 11:21 PM H.J. Lu via Gcc-patches
 wrote:
>
> Restore i686 bootstrap by requiring TARGET_64BIT for any_mul_highpart
> peephole.
>
> PR bootstrap/103785
> * config/i386/i386.md: Require TARGET_64BIT for any_mul_highpart
> peephole.

I don't think this is correct. The patch uses SWI48, where DImode is
enabled only for TARGET_64BIT. The patch disables SImode peephole only
for 32bit targets, so if there is something wrong with the peephole,
it still remains buggy for 64bit targets. Either we remove problematic
peepholes to restore bootstrap or get a testcase and analyze the
problem to figure out the correct fix.

Uros.

> ---
>  gcc/config/i386/i386.md | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
> index 284b9507466..9d6786c5c2e 100644
> --- a/gcc/config/i386/i386.md
> +++ b/gcc/config/i386/i386.md
> @@ -8588,7 +8588,8 @@
>(any_mul_highpart:SWI48 (match_dup 2) (match_dup 0)))
>   (clobber (match_dup 2))
>   (clobber (reg:CC FLAGS_REG))])]
> -  "REGNO (operands[0]) != REGNO (operands[2])
> +  "TARGET_64BIT
> +   && REGNO (operands[0]) != REGNO (operands[2])
> && REGNO (operands[0]) != REGNO (operands[3])
> && (REGNO (operands[0]) == REGNO (operands[4])
> || peep2_reg_dead_p (3, operands[0]))"
> --
> 2.33.1
>

Re: [PATCH v2] ix86: Don't use the 'm' constraint for x86_64_general_operand

[Uros Bizjak via Gcc-patches]

On Thu, Dec 23, 2021 at 3:42 PM H.J. Lu  wrote:
>
> On Mon, Dec 20, 2021 at 2:22 PM H.J. Lu  wrote:
> >
> > On Mon, Dec 20, 2021 at 12:38 PM Jakub Jelinek  wrote:
> > >
> > > On Mon, Dec 20, 2021 at 11:44:08AM -0800, H.J. Lu wrote:
> > > > The problem is in
> > > >
> > > > (define_memory_constraint "TARGET_MEM_CONSTRAINT"
> > > >   "Matches any valid memory."
> > > >   (and (match_code "mem")
> > > >(match_test "memory_address_addr_space_p (GET_MODE (op), XEXP 
> > > > (op, 0),
> > > >  MEM_ADDR_SPACE 
> > > > (op))")))
> > > >
> > > > define_register_constraint allows LRA to convert the operand to the form
> > > > '(mem (reg X))', where X is a base register.  I am testing the v2 patch 
> > > > with
> > >
> > > If you mean replacing an immediate with a MEM containing that immediate,
> > > isn't that often the right thing though?
> > > I mean, if the register pressure is high and options are either spill some
> > > register, set it to immediate, use it in one instruction and then fill the
> > > spilled register (i.e. 2 memory loads), compared to a MEM use on the
> > > arithmetic instruction one MEM seems cheaper to me.  With -fPIC and the
> > > cst needing runtime relocation slightly less so of course.
> > >
> >
> > We will check the performance impact on SPEC CPU 2017.
> > Here is the v2 patch.  Liwei,  can you help collect SPEC CPU 2017
> > impact of the enclosed patch?  Thanks.
>
> We checked SPEC CPU 2017 performance with -O2 and -Ofast.
> There is no performance regression.   OK for master?

OK if there are no further comments from Jakub.

Thanks,
Uros.

> > > The code due to ivopts is trying to have something like
> > >   size_t a = (size_t) &tunable_list;
> > >   size_t b = 0xffa8 - a;
> > >   size_t c = x + b;
> > > and for that cst - &symbol one needs actually 2 registers, one to hold the
> > > constant and one to hold the (%rip) based address.
> > > (insn 790 789 791 111 (set (reg:DI 292)
> > > (const_int -88 [0xffa8])) "dl-tunables.c":304:15 76 
> > > {*movdi_internal}
> > >  (nil))
> > > (insn 791 790 792 111 (set (reg:DI 293)
> > > (symbol_ref:DI ("tunable_list") [flags 0x2]   > > 0x7f3460aa9cf0 tunable_list>)) "dl-tunables.c":304:15 76 {*movdi_internal}
> > >  (nil))
> > > (insn 792 791 793 111 (parallel [
> > > (set (reg:DI 291)
> > > (minus:DI (reg:DI 292)
> > > (reg:DI 293)))
> > > (clobber (reg:CC 17 flags))
> > > ]) "dl-tunables.c":304:15 299 {*subdi_1}
> > >  (nil))
> > > (insn 793 792 794 111 (parallel [
> > > (set (reg:DI 294)
> > > (plus:DI (reg:DI 291)
> > > (reg:DI 198 [ ivtmp.176 ])))
> > > (clobber (reg:CC 17 flags))
> > > ]) "dl-tunables.c":304:15 226 {*adddi_1}
> > >  (nil))
> > > It would be smarter to rewrite the above into a lea 
> > > 88+tunable_list(%rip), %temp1
> > > and use a subtraction instead of addition in the last insn above, or of
> > > course in the particular case even consider the following 2 instructions
> > > that do:
> > > (insn 794 793 795 111 (set (reg:DI 296)
> > > (symbol_ref:DI ("tunable_list") [flags 0x2]   > > 0x7f3460aa9cf0 tunable_list>)) "dl-tunables.c":304:15 76 {*movdi_internal}
> > >  (nil))
> > > (insn 795 794 796 111 (parallel [
> > > (set (reg:DI 295 [ cur ])
> > > (plus:DI (reg:DI 294)
> > > (reg:DI 296)))
> > > (clobber (reg:CC 17 flags))
> > > ]) "dl-tunables.c":304:15 226 {*adddi_1}
> > >  (nil))
> > > and find out that &tuneble_list - &tuneble_list is 0 and we don't need it 
> > > at
> > > all.  Guess we don't figure that out due to the cast of one of those
> > > addresses to size_t and the other one used in POINTER_PLUS_EXPR as normal
> > > pointer.
> > >
> > > Jakub
> > >
> >
> >
> > --
> > H.J.
>
> Thanks.
>
> --
> H.J.

[PATCH] [i386]Fix tdpbf16ps testcase

[Haochen Jiang via Gcc-patches]

Hi all,

This patch fix the testcase of amxbf16-dpbf16ps-2.c. Previously the type 
convert has some issue.

Ok for trunk?

BRs,
Haochen

gcc/testsuite/ChangeLog:

* gcc.target/i386/amx-check.h (check_float_tile_register):
New check function for float to prevent precision loss.
* gcc.target/i386/amxbf16-dpbf16ps-2.c: Correct the type convert
and byte offset. Use the new check function.
---
 gcc/testsuite/gcc.target/i386/amx-check.h | 23 --
 .../gcc.target/i386/amxbf16-dpbf16ps-2.c  | 30 ---
 2 files changed, 41 insertions(+), 12 deletions(-)

diff --git a/gcc/testsuite/gcc.target/i386/amx-check.h 
b/gcc/testsuite/gcc.target/i386/amx-check.h
index 03616ff0b8e..434b0e59703 100644
--- a/gcc/testsuite/gcc.target/i386/amx-check.h
+++ b/gcc/testsuite/gcc.target/i386/amx-check.h
@@ -139,8 +139,27 @@ int check_tile_register (__tile* ref, __tile* target)
 
   for (i = 0; i < rows; i++)
 for (j = 0; j < colsb; j++)
-   if (ref->buf[i * colsb + j] != target->buf[i * colsb + j])
-   return 0;
+  if (ref->buf[i * colsb + j] != target->buf[i * colsb + j])
+   return 0;
+
+  return 1;
+}
+
+/* Compare float tile register value with __tile variable */
+int check_float_tile_register (__tile* ref, __tile* target)
+{
+  /* Tile register should be stored from tmm to
+ memory and compare with emulation results. */
+  int rows = target->rows;
+  int colsb = target->colsb / 4;
+  int i, j;
+  uint32_t *ref_buf = (uint32_t *) ref->buf;
+  uint32_t *target_buf = (uint32_t *) target->buf;
+
+  for (i = 0; i < rows; i++)
+for (j = 0; j < colsb; j++)
+  if (abs(ref_buf[i * colsb + j] - target_buf[i * colsb + j]) > 1)
+   return 0;
 
   return 1;
 }
diff --git a/gcc/testsuite/gcc.target/i386/amxbf16-dpbf16ps-2.c 
b/gcc/testsuite/gcc.target/i386/amxbf16-dpbf16ps-2.c
index f7002ca5ea5..b00bc13ec78 100644
--- a/gcc/testsuite/gcc.target/i386/amxbf16-dpbf16ps-2.c
+++ b/gcc/testsuite/gcc.target/i386/amxbf16-dpbf16ps-2.c
@@ -12,15 +12,25 @@ void test_amx_bf16_dpbf16ps ();
 /* Transformation functions between bf16/float */
 static uint16_t make_bf16 (float f)
 {
-  uint32_t u = (uint32_t)f;
-  u = (u >> 16) & 0x;
-  return (uint16_t)u;
+  union
+  {
+float f;
+uint32_t u;
+  } fu;
+  fu.f = f;
+  fu.u = (fu.u >> 16) & 0x;
+  return (uint16_t) fu.u;
 }
 
 static float make_f32 (uint16_t bf)
 {
-  uint32_t u = (uint32_t)(bf << 16);
-  return (float)u;
+  union
+  {
+float f;
+uint32_t u;
+  } fu;
+  fu.u = (uint32_t) bf << 16;
+  return fu.f;
 }
 
 /* Init tile buffer with bf16 pairs */
@@ -54,10 +64,10 @@ void calc_matrix_dpbf16ps (__tile *dst, __tile *src1, 
__tile *src2)
for (t = 0; t < 2; t+=2)
  {
dst_buf[i * N + k] += 
- (make_f32(src1_buf[i * 4 * N + 4 * j + t]) *
- make_f32(src2_buf[j * 4 * K + 4 * k + t])) +
- (make_f32(src1_buf[i * 4 * N + 4 * j + t + 1]) *
- make_f32(src2_buf[j * 4 * K + 4 * k + t + 1]));
+ (make_f32(src1_buf[i * 2 * N + 2 * j + t]) *
+ make_f32(src2_buf[j * 2 * K + 2 * k + t])) +
+ (make_f32(src1_buf[i * 2 * N + 2 * j + t + 1]) *
+ make_f32(src2_buf[j * 2 * K + 2 * k + t + 1]));
  }
 
 }
@@ -80,6 +90,6 @@ void test_amx_bf16_dpbf16ps ()
   _tile_dpbf16ps (1, 2, 3);
   _tile_stored (1, dst_ref.buf, _STRIDE);
 
-  if (!check_tile_register (&dst_ref, &dst))
+  if (!check_float_tile_register (&dst_ref, &dst))
 abort();
 }
-- 
2.18.1

[PATCH v4 00/12] Add LoongArch support.

[chenglulu]

The LoongArch architecture (LoongArch) is an Instruction Set
Architecture (ISA) that has a Reduced Instruction Set Computer (RISC)
style.
The documents are on
https://loongson.github.io/LoongArch-Documentation/README-EN.html

The ELF ABI Documents are on:
https://loongson.github.io/LoongArch-Documentation/LoongArch-ELF-ABI-EN.html

The binutils has been merged into trunk:
https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=560b3fe208255ae909b4b1c88ba9c28b09043307

Note: We split -mabi= into -mabi=lp64d/f/s, the new options not support by 
upstream binutils yet, 
this GCC port requires the following patch applied to binutils to build.
https://github.com/loongson/binutils-gdb/commit/aacb0bf860f02aa5a7dcb76dd0e392bf871c7586
(will be submitted to upstream after gcc side comfirmed)


changelog:

v1 -> v2
1. Split patch set.
2. Change some code style.
3. Add -mabi=lp64d/f/s options.
4. Change GLIBC_DYNAMIC_LINKER_LP64 name.

v2 -> v3
1. Change some code style.
2. Bug fix.

v3 -> v4
1. Change some code style.
2. Bug fix.
3. Delete some builtin macros.

Add LoongArch support.

chenglulu (12):
  LoongArch Port: Regenerate configure
  LoongArch Port: gcc build
  LoongArch Port: Regenerate gcc/configure.
  LoongArch Port: Machine Decsription files.
  LoongArch Port: Machine description C files and .h files.
  LoongArch Port: Builtin functions.
  LoongArch Port: Builtin macros.
  LoongArch Port: libgcc
  LoongArch Port: Regenerate libgcc/configure.
  LoongArch Port: libgomp
  LoongArch Port: gcc/testsuite
  LoongArch Port: Add doc.

 config/picflag.m4 |3 +
 configure |   10 +-
 configure.ac  |   10 +-
 contrib/config-list.mk|5 +-
 .../config/loongarch/loongarch-common.c   |   63 +
 gcc/config.gcc|  400 +-
 gcc/config/host-linux.c   |2 +
 gcc/config/loongarch/constraints.md   |  212 +
 gcc/config/loongarch/generic.md   |  132 +
 gcc/config/loongarch/genopts/genstr.sh|   91 +
 .../loongarch/genopts/loongarch-strings   |   58 +
 gcc/config/loongarch/genopts/loongarch.opt.in |  189 +
 gcc/config/loongarch/gnu-user.h   |   78 +
 gcc/config/loongarch/la464.md |  132 +
 gcc/config/loongarch/larchintrin.h|  413 ++
 gcc/config/loongarch/linux.h  |   50 +
 gcc/config/loongarch/loongarch-builtins.c |  511 ++
 gcc/config/loongarch/loongarch-c.c|  111 +
 gcc/config/loongarch/loongarch-cpu.c  |  206 +
 gcc/config/loongarch/loongarch-cpu.h  |   30 +
 gcc/config/loongarch/loongarch-def.c  |  164 +
 gcc/config/loongarch/loongarch-def.h  |  151 +
 gcc/config/loongarch/loongarch-driver.c   |  187 +
 gcc/config/loongarch/loongarch-driver.h   |   69 +
 gcc/config/loongarch/loongarch-ftypes.def |  106 +
 gcc/config/loongarch/loongarch-modes.def  |   29 +
 gcc/config/loongarch/loongarch-opts.c |  582 ++
 gcc/config/loongarch/loongarch-opts.h |   86 +
 gcc/config/loongarch/loongarch-protos.h   |  242 +
 gcc/config/loongarch/loongarch-str.h  |   57 +
 gcc/config/loongarch/loongarch-tune.h |   72 +
 gcc/config/loongarch/loongarch.c  | 6461 +
 gcc/config/loongarch/loongarch.h  | 1291 
 gcc/config/loongarch/loongarch.md | 3829 ++
 gcc/config/loongarch/loongarch.opt|  189 +
 gcc/config/loongarch/predicates.md|  553 ++
 gcc/config/loongarch/sync.md  |  574 ++
 gcc/config/loongarch/t-linux  |   53 +
 gcc/config/loongarch/t-loongarch  |   59 +
 gcc/configure |   85 +-
 gcc/configure.ac  |   33 +-
 gcc/doc/install.texi  |   47 +-
 gcc/doc/invoke.texi   |  201 +
 gcc/doc/md.texi   |   55 +
 gcc/testsuite/g++.dg/cpp0x/constexpr-rom.C|2 +-
 gcc/testsuite/g++.old-deja/g++.abi/ptrmem.C   |2 +-
 gcc/testsuite/g++.old-deja/g++.pt/ptrmem6.C   |2 +-
 gcc/testsuite/gcc.dg/20020312-2.c |2 +
 gcc/testsuite/gcc.dg/loop-8.c |2 +-
 .../torture/stackalign/builtin-apply-2.c  |2 +-
 gcc/testsuite/gcc.dg/tree-ssa/ssa-fre-3.c |2 +-
 .../gcc.target/loongarch/loongarch.exp|   40 +
 .../gcc.target/loongarch/tst-asm-const.c  |   16 +
 gcc/testsuite/go.test/go-test.exp |3 +
 gcc/testsuite/lib/target-supports.exp |   14 +
 libgcc/config.host|   28 +-
 libgcc/config/loongarch/crtfastmath.c |   52 +
 libgcc/config/loongarch/crti.S|   43 +
 libgcc/config/loongarch/crtn.S|   39 +
 libgcc/config/loongarch/lib2funcs.c   |0
 libgcc/config/loongarch/linux-unwind.h  

[PATCH v4 01/12] LoongArch Port: Regenerate configure

[chenglulu]

* config/picflag.m4: Default add build option '-fpic' for LoongArch.
* configure: Add LoongArch tuples.
* configure.ac: Like wise.
---
 config/picflag.m4 |  3 +++
 configure | 10 +-
 configure.ac  | 10 +-
 3 files changed, 21 insertions(+), 2 deletions(-)

diff --git a/config/picflag.m4 b/config/picflag.m4
index 8b106f9af88..0aefcf619bf 100644
--- a/config/picflag.m4
+++ b/config/picflag.m4
@@ -44,6 +44,9 @@ case "${$2}" in
# sets the default TLS model and affects inlining.
$1=-fPIC
;;
+loongarch*-*-*)
+   $1=-fpic
+   ;;
 mips-sgi-irix6*)
# PIC is the default.
;;
diff --git a/configure b/configure
index 9c2d7df1bb2..87548f0da96 100755
--- a/configure
+++ b/configure
@@ -3060,7 +3060,7 @@ case "${ENABLE_GOLD}" in
   # Check for target supported by gold.
   case "${target}" in
 i?86-*-* | x86_64-*-* | sparc*-*-* | powerpc*-*-* | arm*-*-* \
-| aarch64*-*-* | tilegx*-*-* | mips*-*-* | s390*-*-*)
+| aarch64*-*-* | tilegx*-*-* | mips*-*-* | s390*-*-* | loongarch*-*-*)
  configdirs="$configdirs gold"
  if test x${ENABLE_GOLD} = xdefault; then
default_ld=gold
@@ -3646,6 +3646,9 @@ case "${target}" in
   i[3456789]86-*-*)
 libgloss_dir=i386
 ;;
+  loongarch*-*-*)
+libgloss_dir=loongarch
+;;
   m68hc11-*-*|m6811-*-*|m68hc12-*-*|m6812-*-*)
 libgloss_dir=m68hc11
 ;;
@@ -4030,6 +4033,11 @@ case "${target}" in
   wasm32-*-*)
 noconfigdirs="$noconfigdirs ld"
 ;;
+  loongarch*-*-linux*)
+;;
+  loongarch*-*-*)
+noconfigdirs="$noconfigdirs gprof"
+;;
 esac
 
 # If we aren't building newlib, then don't build libgloss, since libgloss
diff --git a/configure.ac b/configure.ac
index 68cc5cc31fe..55362afeeae 100644
--- a/configure.ac
+++ b/configure.ac
@@ -353,7 +353,7 @@ case "${ENABLE_GOLD}" in
   # Check for target supported by gold.
   case "${target}" in
 i?86-*-* | x86_64-*-* | sparc*-*-* | powerpc*-*-* | arm*-*-* \
-| aarch64*-*-* | tilegx*-*-* | mips*-*-* | s390*-*-*)
+| aarch64*-*-* | tilegx*-*-* | mips*-*-* | s390*-*-* | loongarch*-*-*)
  configdirs="$configdirs gold"
  if test x${ENABLE_GOLD} = xdefault; then
default_ld=gold
@@ -899,6 +899,9 @@ case "${target}" in
   i[[3456789]]86-*-*)
 libgloss_dir=i386
 ;;
+  loongarch*-*-*)
+libgloss_dir=loongarch
+;;
   m68hc11-*-*|m6811-*-*|m68hc12-*-*|m6812-*-*)
 libgloss_dir=m68hc11
 ;;
@@ -1283,6 +1286,11 @@ case "${target}" in
   wasm32-*-*)
 noconfigdirs="$noconfigdirs ld"
 ;;
+  loongarch*-*-linux*)
+;;
+  loongarch*-*-*)
+noconfigdirs="$noconfigdirs gprof"
+;;
 esac
 
 # If we aren't building newlib, then don't build libgloss, since libgloss
-- 
2.27.0

[PATCH v4 03/12] LoongArch Port: Regenerate gcc/configure.

[chenglulu]

---
 gcc/configure | 85 +++
 1 file changed, 79 insertions(+), 6 deletions(-)

diff --git a/gcc/configure b/gcc/configure
index 992a9d70092..999557a3b51 100755
--- a/gcc/configure
+++ b/gcc/configure
@@ -5352,7 +5352,26 @@ else
   GDC="$ac_cv_prog_GDC"
 fi
 
+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether the D compiler 
works" >&5
+$as_echo_n "checking whether the D compiler works... " >&6; }
+if ${acx_cv_d_compiler_works+:} false; then :
+  $as_echo_n "(cached) " >&6
+else
+  cat >conftest.d <&1 || echo failure`
+  if test x"$errors" = x && test -f conftest.$ac_objext; then
+acx_cv_d_compiler_works=yes
+  fi
+  rm -f conftest.*
+fi
+fi
+{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $acx_cv_d_compiler_works" >&5
+$as_echo "$acx_cv_d_compiler_works" >&6; }
+if test "x$GDC" != xno && test x$acx_cv_d_compiler_works != xno; then
   have_gdc=yes
 else
   have_gdc=no
@@ -5423,6 +5442,9 @@ case "${target}" in
# sets the default TLS model and affects inlining.
PICFLAG_FOR_TARGET=-fPIC
;;
+loongarch*-*-*)
+   PICFLAG_FOR_TARGET=-fpic
+   ;;
 mips-sgi-irix6*)
# PIC is the default.
;;
@@ -7865,6 +7887,9 @@ else
 mips*-*-*)
   enable_fixed_point=yes
   ;;
+loongarch*-*-*)
+  enable_fixed_point=yes
+  ;;
 *)
   { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: fixed-point is not 
supported for this target, ignored" >&5
 $as_echo "$as_me: WARNING: fixed-point is not supported for this target, 
ignored" >&2;}
@@ -19561,7 +19586,7 @@ else
   lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
   lt_status=$lt_dlunknown
   cat > conftest.$ac_ext <<_LT_EOF
-#line 19564 "configure"
+#line 19589 "configure"
 #include "confdefs.h"
 
 #if HAVE_DLFCN_H
@@ -19667,7 +19692,7 @@ else
   lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
   lt_status=$lt_dlunknown
   cat > conftest.$ac_ext <<_LT_EOF
-#line 19670 "configure"
+#line 19695 "configure"
 #include "confdefs.h"
 
 #if HAVE_DLFCN_H
@@ -25432,6 +25457,17 @@ foo:   data8   25
movlr24 = @tprel(foo#)'
tls_as_opt=--fatal-warnings
;;
+  loongarch*-*-*)
+conftest_s='
+   .section .tdata,"awT",@progbits
+x: .word 2
+   .text
+   la.tls.gd $a0,x
+   bl __tls_get_addr'
+   tls_first_major=0
+   tls_first_minor=0
+   tls_as_opt='--fatal-warnings'
+   ;;
   microblaze*-*-*)
 conftest_s='
.section .tdata,"awT",@progbits
@@ -28654,6 +28690,43 @@ $as_echo "#define HAVE_AS_MARCH_ZIFENCEI 1" 
>>confdefs.h
 fi
 
 ;;
+  loongarch*-*-*)
+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking assembler for 
.dtprelword support" >&5
+$as_echo_n "checking assembler for .dtprelword support... " >&6; }
+if ${gcc_cv_as_loongarch_dtprelword+:} false; then :
+  $as_echo_n "(cached) " >&6
+else
+  gcc_cv_as_loongarch_dtprelword=no
+  if test x$gcc_cv_as != x; then
+$as_echo '' > conftest.s
+if { ac_try='$gcc_cv_as $gcc_cv_as_flags 2,18,0 -o conftest.o conftest.s 
>&5'
+  { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_try\""; } >&5
+  (eval $ac_try) 2>&5
+  ac_status=$?
+  $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5
+  test $ac_status = 0; }; }
+then
+   .section .tdata,"awT",@progbits
+x:
+   .word 2
+   .text
+   .dtprelword x+0x8000
+else
+  echo "configure: failed program was" >&5
+  cat conftest.s >&5
+fi
+rm -f conftest.o conftest.s
+  fi
+fi
+{ $as_echo "$as_me:${as_lineno-$LINENO}: result: 
$gcc_cv_as_loongarch_dtprelword" >&5
+$as_echo "$gcc_cv_as_loongarch_dtprelword" >&6; }
+
+if test $gcc_cv_as_loongarch_dtprelword != yes; then
+
+$as_echo "#define HAVE_AS_DTPRELWORD 1" >>confdefs.h
+
+fi
+;;
 s390*-*-*)
 { $as_echo "$as_me:${as_lineno-$LINENO}: checking assembler for 
.gnu_attribute support" >&5
 $as_echo_n "checking assembler for .gnu_attribute support... " >&6; }
@@ -28817,11 +28890,11 @@ fi
 ;;
 esac
 
-# Mips and HP-UX need the GNU assembler.
+# Mips, LoongArch and HP-UX need the GNU assembler.
 # Linux on IA64 might be able to use the Intel assembler.
 
 case "$target" in
-  mips*-*-* | *-*-hpux* )
+  mips*-*-* | loongarch*-*-* | *-*-hpux* )
 if test x$gas_flag = xyes \
|| test x"$host" != x"$build" \
|| test ! -x "$gcc_cv_as" \
@@ -29258,8 +29331,8 @@ esac
 # ??? Once 2.11 is released, probably need to add first known working
 # version to the per-target configury.
 case "$cpu_type" in
-  aarch64 | alpha | arc | arm | avr | bfin | cris | csky | i386 | m32c | m68k \
-  | microblaze | mips | nds32 | nios2 | pa | riscv | rs6000 | score | sparc \
+  aarch64 | alpha | arc | arm | avr | bfin | cris | csky | i386 | loongarch | 
m32c \
+  | m68k | microblaze | mips | nds32 | nios2 | pa | riscv | rs6000 | score | 
sparc \
   | tilegx | tilepro | visium | xstormy16 | xtensa)
 insn="nop"
 ;;
-- 
2.27.0

[PATCH v4 07/12] LoongArch Port: Builtin macros.

[chenglulu]

gcc/

*config/loongarch/loongarch-c.c
---
 gcc/config/loongarch/loongarch-c.c | 111 +
 1 file changed, 111 insertions(+)
 create mode 100644 gcc/config/loongarch/loongarch-c.c

diff --git a/gcc/config/loongarch/loongarch-c.c 
b/gcc/config/loongarch/loongarch-c.c
new file mode 100644
index 000..b577b2f952c
--- /dev/null
+++ b/gcc/config/loongarch/loongarch-c.c
@@ -0,0 +1,111 @@
+/* LoongArch-specific code for C family languages.
+   Copyright (C) 2021 Free Software Foundation, Inc.
+   Contributed by Loongson Ltd.
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 3, or (at your option)
+any later version.
+
+GCC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GCC; see the file COPYING3.  If not see
+.  */
+
+#define IN_TARGET_CODE 1
+
+#include "config.h"
+#include "system.h"
+#include "coretypes.h"
+#include "tm.h"
+#include "c-family/c-common.h"
+#include "cpplib.h"
+
+#define preprocessing_asm_p() (cpp_get_options (pfile)->lang == CLK_ASM)
+#define builtin_define(TXT) cpp_define (pfile, TXT)
+#define builtin_assert(TXT) cpp_assert (pfile, TXT)
+
+/* Define preprocessor macros for the -march and -mtune options.
+   PREFIX is either _LOONGARCH_ARCH or _LOONGARCH_TUNE, INFO is
+   the selected processor.  If INFO's canonical name is "foo",
+   define PREFIX to be "foo", and define an additional macro
+   PREFIX_FOO.  */
+#define LARCH_CPP_SET_PROCESSOR(PREFIX, CPU_TYPE)  \
+  do   \
+{  \
+  char *macro, *p; \
+  int cpu_type = (CPU_TYPE);   \
+   \
+  macro = concat ((PREFIX), "_",   \
+ loongarch_cpu_strings[cpu_type], NULL);   \
+  for (p = macro; *p != 0; p++)\
+   *p = TOUPPER (*p);  \
+   \
+  builtin_define (macro);  \
+  builtin_define_with_value ((PREFIX), \
+loongarch_cpu_strings[cpu_type], 1);   \
+  free (macro);\
+}  \
+  while (0)
+
+/* TODO: what is the pfile technique ??? !!! */
+
+void
+loongarch_cpu_cpp_builtins (cpp_reader *pfile)
+{
+  builtin_assert ("machine=loongarch");
+  builtin_assert ("cpu=loongarch");
+  builtin_define ("__loongarch__");
+
+  LARCH_CPP_SET_PROCESSOR ("_LOONGARCH_ARCH", __ACTUAL_ARCH);
+  LARCH_CPP_SET_PROCESSOR ("_LOONGARCH_TUNE", __ACTUAL_TUNE);
+
+  /* Base architecture / ABI.  */
+  if (TARGET_64BIT)
+{
+  builtin_define ("__loongarch_grlen=64");
+  builtin_define ("__loongarch64");
+}
+
+  if (TARGET_ABI_LP64)
+{
+  builtin_define ("_ABILP64=3");
+  builtin_define ("_LOONGARCH_SIM=_ABILP64");
+  builtin_define ("__loongarch_lp64");
+}
+
+  /* These defines reflect the ABI in use, not whether the
+ FPU is directly accessible.  */
+  if (TARGET_DOUBLE_FLOAT_ABI)
+builtin_define ("__loongarch_double_float=1");
+  else if (TARGET_SINGLE_FLOAT_ABI)
+builtin_define ("__loongarch_single_float=1");
+
+  if (TARGET_DOUBLE_FLOAT_ABI || TARGET_SINGLE_FLOAT_ABI)
+builtin_define ("__loongarch_hard_float=1");
+  else
+builtin_define ("__loongarch_soft_float=1");
+
+
+  /* ISA Extensions.  */
+  if (TARGET_DOUBLE_FLOAT)
+builtin_define ("__loongarch_frlen=64");
+  else if (TARGET_SINGLE_FLOAT)
+builtin_define ("__loongarch_frlen=32");
+  else
+builtin_define ("__loongarch_frlen=0");
+
+  /* Native Data Sizes.  */
+  builtin_define_with_int_value ("_LOONGARCH_SZINT", INT_TYPE_SIZE);
+  builtin_define_with_int_value ("_LOONGARCH_SZLONG", LONG_TYPE_SIZE);
+  builtin_define_with_int_value ("_LOONGARCH_SZPTR", POINTER_SIZE);
+  builtin_define_with_int_value ("_LOONGARCH_FPSET", 32 / MAX_FPRS_PER_FMT);
+  builtin_define_with_int_value ("_LOONGARCH_SPFPSET", 32);
+
+}
-- 
2.27.0

[PATCH v4 09/12] LoongArch Port: Regenerate libgcc/configure.

[chenglulu]

---
 libgcc/configure | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/libgcc/configure b/libgcc/configure
index 4919a56f518..ce04c4f529f 100755
--- a/libgcc/configure
+++ b/libgcc/configure
@@ -2412,6 +2412,9 @@ case "${host}" in
# sets the default TLS model and affects inlining.
PICFLAG=-fPIC
;;
+loongarch*-*-*)
+   PICFLAG=-fpic
+   ;;
 mips-sgi-irix6*)
# PIC is the default.
;;
@@ -5066,7 +5069,7 @@ $as_echo "$libgcc_cv_cfi" >&6; }
 # word size rather than the address size.
 cat > conftest.c <

[PATCH v4 10/12] LoongArch Port: libgomp

[chenglulu]

libgomp/

* configure.tgt: Add LoongArch triplet.
---
 libgomp/configure.tgt | 4 
 1 file changed, 4 insertions(+)

diff --git a/libgomp/configure.tgt b/libgomp/configure.tgt
index d4f1e741b5a..2cd7272fcd8 100644
--- a/libgomp/configure.tgt
+++ b/libgomp/configure.tgt
@@ -56,6 +56,10 @@ if test x$enable_linux_futex = xyes; then
config_path="linux/ia64 linux posix"
;;
 
+loongarch*-*-linux*)
+   config_path="linux posix"
+   ;;
+
 mips*-*-linux*)
config_path="linux/mips linux posix"
;;
-- 
2.27.0

[PATCH v4 06/12] LoongArch Port: Builtin functions.

[chenglulu]

gcc/

* config/loongarch/larchintrin.h: New file.
* config/loongarch/loongarch-builtins.c: New file.
---
 gcc/config/loongarch/larchintrin.h| 413 +
 gcc/config/loongarch/loongarch-builtins.c | 511 ++
 2 files changed, 924 insertions(+)
 create mode 100644 gcc/config/loongarch/larchintrin.h
 create mode 100644 gcc/config/loongarch/loongarch-builtins.c

diff --git a/gcc/config/loongarch/larchintrin.h 
b/gcc/config/loongarch/larchintrin.h
new file mode 100644
index 000..fcf5043841d
--- /dev/null
+++ b/gcc/config/loongarch/larchintrin.h
@@ -0,0 +1,413 @@
+/* Intrinsics for LoongArch BASE operations.
+   Copyright (C) 2021 Free Software Foundation, Inc.
+   Contributed by Loongson Ltd.
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify it
+under the terms of the GNU General Public License as published
+by the Free Software Foundation; either version 3, or (at your
+option) any later version.
+
+GCC is distributed in the hope that it will be useful, but WITHOUT
+ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+License for more details.
+
+Under Section 7 of GPL version 3, you are granted additional
+permissions described in the GCC Runtime Library Exception, version
+3.1, as published by the Free Software Foundation.
+
+You should have received a copy of the GNU General Public License and
+a copy of the GCC Runtime Library Exception along with this program;
+see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+.  */
+
+#ifndef _GCC_LOONGARCH_BASE_INTRIN_H
+#define _GCC_LOONGARCH_BASE_INTRIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct drdtime
+{
+  unsigned long dvalue;
+  unsigned long dtimeid;
+} __drdtime_t;
+
+typedef struct rdtime
+{
+  unsigned int value;
+  unsigned int timeid;
+} __rdtime_t;
+
+#ifdef __loongarch64
+extern __inline __drdtime_t
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__builtin_loongarch_rdtime_d (void)
+{
+  __drdtime_t drdtime;
+  __asm__ volatile (
+"rdtime.d\t%[val],%[tid]\n\t"
+: [val]"=&r"(drdtime.dvalue),[tid]"=&r"(drdtime.dtimeid)
+:);
+  return drdtime;
+}
+#define __rdtime_d __builtin_loongarch_rdtime_d
+#endif
+
+extern __inline __rdtime_t
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__builtin_loongarch_rdtimeh_w (void)
+{
+  __rdtime_t rdtime;
+  __asm__ volatile (
+"rdtimeh.w\t%[val],%[tid]\n\t"
+: [val]"=&r"(rdtime.value),[tid]"=&r"(rdtime.timeid)
+:);
+  return rdtime;
+}
+#define __rdtimel_w __builtin_loongarch_rdtimel_w
+
+extern __inline __rdtime_t
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__builtin_loongarch_rdtimel_w (void)
+{
+  __rdtime_t rdtime;
+  __asm__ volatile (
+"rdtimel.w\t%[val],%[tid]\n\t"
+: [val]"=&r"(rdtime.value),[tid]"=&r"(rdtime.timeid)
+:);
+  return rdtime;
+}
+#define __rdtimeh_w __builtin_loongarch_rdtimeh_w
+
+/* Assembly instruction format:rj, fcsr.  */
+/* Data types in instruction templates:  USI, UQI.  */
+#define __movfcsr2gr(/*ui5*/ _1) __builtin_loongarch_movfcsr2gr ((_1));
+
+/* Assembly instruction format:0, fcsr, rj.  */
+/* Data types in instruction templates:  VOID, UQI, USI.  */
+#define __movgr2fcsr(/*ui5*/ _1, _2) \
+  __builtin_loongarch_movgr2fcsr ((unsigned short) _1, (unsigned int) _2);
+
+#if defined __loongarch64
+/* Assembly instruction format:ui5, rj, si12.  */
+/* Data types in instruction templates:  VOID, USI, UDI, SI.  */
+#define __dcacop(/*ui5*/ _1, /*unsigned long int*/ _2, /*si12*/ _3) \
+  ((void) __builtin_loongarch_dcacop ((_1), (unsigned long int) (_2), (_3)))
+#else
+#error "Don't support this ABI."
+#endif
+
+/* Assembly instruction format:rd, rj.  */
+/* Data types in instruction templates:  USI, USI.  */
+extern __inline unsigned int
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__cpucfg (unsigned int _1)
+{
+  return (unsigned int) __builtin_loongarch_cpucfg ((unsigned int) _1);
+}
+
+#ifdef __loongarch64
+/* Assembly instruction format:rd, rj.  */
+/* Data types in instruction templates:  DI, DI.  */
+extern __inline void
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__asrtle_d (long int _1, long int _2)
+{
+  __builtin_loongarch_asrtle_d ((long int) _1, (long int) _2);
+}
+
+/* Assembly instruction format:rd, rj.  */
+/* Data types in instruction templates:  DI, DI.  */
+extern __inline void
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__asrtgt_d (long int _1, long int _2)
+{
+  __builtin_loongarch_asrtgt_d ((long int) _1, (long int) _2);
+}
+#endif
+
+#if defined __loongarch64
+/* Assembly instruction format:rd, rj, ui5.  */
+/* Data types in instruction templates:  DI, DI, UQI.  */
+#define __dlddir(/*lon

[PATCH v4 02/12] LoongArch Port: gcc build

[chenglulu]

gcc/

* common/config/loongarch/loongarch-common.c: New file.
* config/loongarch/genopts/genstr.sh: New file.
* config/loongarch/genopts/loongarch-strings: New file.
* config/loongarch/genopts/loongarch.opt.in: New file.
* config/loongarch/gnu-user.h: New file.
* config/loongarch/linux.h: New file.
* config/loongarch/loongarch-cpu.c: New file.
* config/loongarch/loongarch-cpu.h: New file.
* config/loongarch/loongarch-driver.c: New file.
* config/loongarch/loongarch-driver.h: New file.
* config/loongarch/loongarch-opts.c: New file.
* config/loongarch/loongarch-opts.h: New file.
* config/loongarch/loongarch.opt: New file.
* config/loongarch/t-linux: New file.
* config/loongarch/t-loongarch: New file.
* config.gcc: Add LoongArch support.
* configure.ac: Add LoongArch support.
---
 .../config/loongarch/loongarch-common.c   |  63 ++
 gcc/config.gcc| 400 +++-
 gcc/config/loongarch/genopts/genstr.sh|  91 +++
 .../loongarch/genopts/loongarch-strings   |  58 ++
 gcc/config/loongarch/genopts/loongarch.opt.in | 189 ++
 gcc/config/loongarch/gnu-user.h   |  78 +++
 gcc/config/loongarch/linux.h  |  50 ++
 gcc/config/loongarch/loongarch-cpu.c  | 206 +++
 gcc/config/loongarch/loongarch-cpu.h  |  30 +
 gcc/config/loongarch/loongarch-def.c  | 164 +
 gcc/config/loongarch/loongarch-def.h  | 151 +
 gcc/config/loongarch/loongarch-driver.c   | 187 ++
 gcc/config/loongarch/loongarch-driver.h   |  69 +++
 gcc/config/loongarch/loongarch-opts.c | 582 ++
 gcc/config/loongarch/loongarch-opts.h |  86 +++
 gcc/config/loongarch/loongarch-str.h  |  57 ++
 gcc/config/loongarch/loongarch.opt| 189 ++
 gcc/config/loongarch/t-linux  |  53 ++
 gcc/config/loongarch/t-loongarch  |  59 ++
 gcc/configure.ac  |  33 +-
 20 files changed, 2790 insertions(+), 5 deletions(-)
 create mode 100644 gcc/common/config/loongarch/loongarch-common.c
 create mode 100755 gcc/config/loongarch/genopts/genstr.sh
 create mode 100644 gcc/config/loongarch/genopts/loongarch-strings
 create mode 100644 gcc/config/loongarch/genopts/loongarch.opt.in
 create mode 100644 gcc/config/loongarch/gnu-user.h
 create mode 100644 gcc/config/loongarch/linux.h
 create mode 100644 gcc/config/loongarch/loongarch-cpu.c
 create mode 100644 gcc/config/loongarch/loongarch-cpu.h
 create mode 100644 gcc/config/loongarch/loongarch-def.c
 create mode 100644 gcc/config/loongarch/loongarch-def.h
 create mode 100644 gcc/config/loongarch/loongarch-driver.c
 create mode 100644 gcc/config/loongarch/loongarch-driver.h
 create mode 100644 gcc/config/loongarch/loongarch-opts.c
 create mode 100644 gcc/config/loongarch/loongarch-opts.h
 create mode 100644 gcc/config/loongarch/loongarch-str.h
 create mode 100644 gcc/config/loongarch/loongarch.opt
 create mode 100644 gcc/config/loongarch/t-linux
 create mode 100644 gcc/config/loongarch/t-loongarch

diff --git a/gcc/common/config/loongarch/loongarch-common.c 
b/gcc/common/config/loongarch/loongarch-common.c
new file mode 100644
index 000..3f440aef1e7
--- /dev/null
+++ b/gcc/common/config/loongarch/loongarch-common.c
@@ -0,0 +1,63 @@
+/* Common hooks for LoongArch.
+   Copyright (C) 2021 Free Software Foundation, Inc.
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 3, or (at your option)
+any later version.
+
+GCC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GCC; see the file COPYING3.  If not see
+.  */
+
+#include "config.h"
+#include "system.h"
+#include "coretypes.h"
+#include "tm.h"
+#include "common/common-target.h"
+#include "common/common-target-def.h"
+#include "opts.h"
+#include "flags.h"
+#include "diagnostic-core.h"
+
+/* Implement TARGET_HANDLE_OPTION.  */
+
+static bool
+loongarch_handle_option (struct gcc_options *opts,
+struct gcc_options *opts_set ATTRIBUTE_UNUSED,
+const struct cl_decoded_option *decoded,
+location_t loc ATTRIBUTE_UNUSED)
+{
+  size_t code = decoded->opt_index;
+  int value = decoded->value;
+
+  switch (code)
+{
+case OPT_mmemcpy:
+  if (value)
+   {
+ if (opts->x_optimize_size)
+   opts->x_target_flags |= MASK_MEMCPY;
+   }
+  else
+   opts->x_target_flags &= ~MASK_MEMCPY;
+  

[PATCH v4 11/12] LoongArch Port: gcc/testsuite

[chenglulu]

gcc/testsuite/

* g++.dg/cpp0x/constexpr-rom.C: Add build options for LoongArch.
* g++.old-deja/g++.abi/ptrmem.C: Add LoongArch support.
* g++.old-deja/g++.pt/ptrmem6.C: xfail for LoongArch.
* gcc.dg/20020312-2.c: Add LoongArch support.
* gcc.dg/loop-8.c: Skip on LoongArch.
* gcc.dg/torture/stackalign/builtin-apply-2.c: Likewise.
* gcc.dg/tree-ssa/ssa-fre-3.c: Likewise.
* go.test/go-test.exp: Define the LoongArch target.
* lib/target-supports.exp: Like wise.
* gcc.target/loongarch/loongarch.exp: New file.
* gcc.target/loongarch/tst-asm-const.c: Like wise.
---
 gcc/testsuite/g++.dg/cpp0x/constexpr-rom.C|  2 +-
 gcc/testsuite/g++.old-deja/g++.abi/ptrmem.C   |  2 +-
 gcc/testsuite/g++.old-deja/g++.pt/ptrmem6.C   |  2 +-
 gcc/testsuite/gcc.dg/20020312-2.c |  2 +
 gcc/testsuite/gcc.dg/loop-8.c |  2 +-
 .../torture/stackalign/builtin-apply-2.c  |  2 +-
 gcc/testsuite/gcc.dg/tree-ssa/ssa-fre-3.c |  2 +-
 .../gcc.target/loongarch/loongarch.exp| 40 +++
 .../gcc.target/loongarch/tst-asm-const.c  | 16 
 gcc/testsuite/go.test/go-test.exp |  3 ++
 gcc/testsuite/lib/target-supports.exp | 14 +++
 11 files changed, 81 insertions(+), 6 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/loongarch/loongarch.exp
 create mode 100644 gcc/testsuite/gcc.target/loongarch/tst-asm-const.c

diff --git a/gcc/testsuite/g++.dg/cpp0x/constexpr-rom.C 
b/gcc/testsuite/g++.dg/cpp0x/constexpr-rom.C
index 2e0ef685f36..424979a604b 100644
--- a/gcc/testsuite/g++.dg/cpp0x/constexpr-rom.C
+++ b/gcc/testsuite/g++.dg/cpp0x/constexpr-rom.C
@@ -1,6 +1,6 @@
 // PR c++/49673: check that test_data goes into .rodata
 // { dg-do compile { target c++11 } }
-// { dg-additional-options -G0 { target { { alpha*-*-* frv*-*-* ia64-*-* 
lm32*-*-* m32r*-*-* microblaze*-*-* mips*-*-* nios2-*-* powerpc*-*-* 
rs6000*-*-* } && { ! { *-*-darwin* *-*-aix* alpha*-*-*vms* } } } } }
+// { dg-additional-options -G0 { target { { alpha*-*-* frv*-*-* ia64-*-* 
lm32*-*-* m32r*-*-* microblaze*-*-* mips*-*-* loongarch*-*-* nios2-*-* 
powerpc*-*-* rs6000*-*-* } && { ! { *-*-darwin* *-*-aix* alpha*-*-*vms* } } } } 
}
 // { dg-final { scan-assembler "\\.rdata" { target mips*-*-* } } }
 // { dg-final { scan-assembler "rodata" { target { { *-*-linux-gnu *-*-gnu* 
*-*-elf } && { ! { mips*-*-* riscv*-*-* } } } } } }
 
diff --git a/gcc/testsuite/g++.old-deja/g++.abi/ptrmem.C 
b/gcc/testsuite/g++.old-deja/g++.abi/ptrmem.C
index bda7960d8a2..f69000e9081 100644
--- a/gcc/testsuite/g++.old-deja/g++.abi/ptrmem.C
+++ b/gcc/testsuite/g++.old-deja/g++.abi/ptrmem.C
@@ -7,7 +7,7 @@
function.  However, some platforms use all bits to encode a
function pointer.  Such platforms use the lowest bit of the delta,
that is shifted left by one bit.  */
-#if defined __MN10300__ || defined __SH5__ || defined __arm__ || defined 
__thumb__ || defined __mips__ || defined __aarch64__ || defined __PRU__
+#if defined __MN10300__ || defined __SH5__ || defined __arm__ || defined 
__thumb__ || defined __mips__ || defined __aarch64__ || defined __PRU__ || 
defined __loongarch__
 #define ADJUST_PTRFN(func, virt) ((void (*)())(func))
 #define ADJUST_DELTA(delta, virt) (((delta) << 1) + !!(virt))
 #else
diff --git a/gcc/testsuite/g++.old-deja/g++.pt/ptrmem6.C 
b/gcc/testsuite/g++.old-deja/g++.pt/ptrmem6.C
index 9f4bbe43f89..8f8f7017ab7 100644
--- a/gcc/testsuite/g++.old-deja/g++.pt/ptrmem6.C
+++ b/gcc/testsuite/g++.old-deja/g++.pt/ptrmem6.C
@@ -25,7 +25,7 @@ int main() {
   h<&B::j>(); // { dg-error "" } 
   g<(void (A::*)()) &A::f>(); // { dg-error "" "" { xfail c++11 } }
   h<(int A::*) &A::i>(); // { dg-error "" "" { xfail c++11 } }
-  g<(void (A::*)()) &B::f>(); // { dg-error "" "" { xfail { c++11 && { 
aarch64*-*-* arm*-*-* mips*-*-* } } } }
+  g<(void (A::*)()) &B::f>(); // { dg-error "" "" { xfail { c++11 && { 
aarch64*-*-* arm*-*-* mips*-*-* loongarch*-*-* } } } }
   h<(int A::*) &B::j>(); // { dg-error "" } 
   g<(void (A::*)()) 0>(); // { dg-error "" "" { target { ! c++11 } } }
   h<(int A::*) 0>(); // { dg-error "" "" { target { ! c++11 } } }
diff --git a/gcc/testsuite/gcc.dg/20020312-2.c 
b/gcc/testsuite/gcc.dg/20020312-2.c
index 52c33d09b90..92bc150df0f 100644
--- a/gcc/testsuite/gcc.dg/20020312-2.c
+++ b/gcc/testsuite/gcc.dg/20020312-2.c
@@ -37,6 +37,8 @@ extern void abort (void);
 /* PIC register is r1, but is used even without -fpic.  */
 #elif defined(__lm32__)
 /* No pic register.  */
+#elif defined(__loongarch__)
+/* No pic register.  */
 #elif defined(__M32R__)
 /* No pic register.  */
 #elif defined(__m68k__)
diff --git a/gcc/testsuite/gcc.dg/loop-8.c b/gcc/testsuite/gcc.dg/loop-8.c
index a685fc25056..8e5f2087831 100644
--- a/gcc/testsuite/gcc.dg/loop-8.c
+++ b/gcc/testsuite/gcc.dg/loop-8.c
@@ -1,6 +1,6 @@
 /* { dg-do compile } */
 /* { dg-options "-O1 -fdump-rtl-loop2_invariant" } */
-/* { dg-skip

[PATCH v4 08/12] LoongArch Port: libgcc

[chenglulu]

libgcc/

* config/loongarch/crtfastmath.c: New file.
* config/loongarch/crti.S: Like wise.
* config/loongarch/crtn.S: Like wise.
* config/loongarch/lib2funcs.c: Like wise.
* config/loongarch/linux-unwind.h: Like wise.
* config/loongarch/sfp-machine.h: Like wise.
* config/loongarch/t-crtstuff: Like wise.
* config/loongarch/t-elf: Like wise.
* config/loongarch/t-loongarch: Like wise.
* config/loongarch/t-loongarch64: Like wise.
* config/loongarch/t-softfp-tf: Like wise.
* config.host: Add LoongArch tuples.
* configure.ac: Add LoongArch support.
---
 libgcc/config.host |  28 -
 libgcc/config/loongarch/crtfastmath.c  |  52 +
 libgcc/config/loongarch/crti.S |  43 +++
 libgcc/config/loongarch/crtn.S |  39 +++
 libgcc/config/loongarch/lib2funcs.c|   0
 libgcc/config/loongarch/linux-unwind.h |  80 +
 libgcc/config/loongarch/sfp-machine.h  | 152 +
 libgcc/config/loongarch/t-crtstuff |   2 +
 libgcc/config/loongarch/t-elf  |   3 +
 libgcc/config/loongarch/t-loongarch|   9 ++
 libgcc/config/loongarch/t-loongarch64  |   1 +
 libgcc/config/loongarch/t-softfp-tf|   3 +
 libgcc/configure.ac|   2 +-
 13 files changed, 412 insertions(+), 2 deletions(-)
 create mode 100644 libgcc/config/loongarch/crtfastmath.c
 create mode 100644 libgcc/config/loongarch/crti.S
 create mode 100644 libgcc/config/loongarch/crtn.S
 create mode 100644 libgcc/config/loongarch/lib2funcs.c
 create mode 100644 libgcc/config/loongarch/linux-unwind.h
 create mode 100644 libgcc/config/loongarch/sfp-machine.h
 create mode 100644 libgcc/config/loongarch/t-crtstuff
 create mode 100644 libgcc/config/loongarch/t-elf
 create mode 100644 libgcc/config/loongarch/t-loongarch
 create mode 100644 libgcc/config/loongarch/t-loongarch64
 create mode 100644 libgcc/config/loongarch/t-softfp-tf

diff --git a/libgcc/config.host b/libgcc/config.host
index ad0cdb284c7..7e9da09cb80 100644
--- a/libgcc/config.host
+++ b/libgcc/config.host
@@ -138,6 +138,22 @@ hppa*-*-*)
 lm32*-*-*)
cpu_type=lm32
;;
+loongarch*-*-*)
+   cpu_type=loongarch
+   tmake_file="loongarch/t-loongarch"
+   if test "${libgcc_cv_loongarch_hard_float}" = yes; then
+   tmake_file="${tmake_file} t-hardfp-sfdf t-hardfp"
+   else
+   tmake_file="${tmake_file} t-softfp-sfdf"
+   fi
+   if test "${ac_cv_sizeof_long_double}" = 16; then
+   tmake_file="${tmake_file} loongarch/t-softfp-tf"
+   fi
+   if test "${host_address}" = 64; then
+   tmake_file="${tmake_file} loongarch/t-loongarch64"
+   fi
+   tmake_file="${tmake_file} t-softfp"
+   ;;
 m32r*-*-*)
 cpu_type=m32r
 ;;
@@ -925,7 +941,17 @@ lm32-*-rtems*)
 lm32-*-uclinux*)
 extra_parts="$extra_parts crtbegin.o crtendS.o crtbeginT.o"
 tmake_file="lm32/t-lm32 lm32/t-uclinux t-libgcc-pic t-softfp-sfdf 
t-softfp"
-   ;;  
+   ;;
+loongarch*-*-linux*)
+   extra_parts="$extra_parts crtfastmath.o"
+   tmake_file="${tmake_file} t-crtfm"
+   case ${host} in
+ *)
+   tmake_file="${tmake_file} t-slibgcc-libgcc"
+   ;;
+   esac
+   md_unwind_header=loongarch/linux-unwind.h
+   ;;
 m32r-*-elf*)
tmake_file="$tmake_file m32r/t-m32r t-fdpbit"
extra_parts="$extra_parts crtinit.o crtfini.o"
diff --git a/libgcc/config/loongarch/crtfastmath.c 
b/libgcc/config/loongarch/crtfastmath.c
new file mode 100644
index 000..3523d531e2b
--- /dev/null
+++ b/libgcc/config/loongarch/crtfastmath.c
@@ -0,0 +1,52 @@
+/* Copyright (C) 2021 Free Software Foundation, Inc.
+   Contributed by Loongson Ltd.
+   Based on MIPS target for GNU compiler.
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify it
+under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 3, or (at your option)
+any later version.
+
+GCC is distributed in the hope that it will be useful, but WITHOUT
+ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+License for more details.
+
+Under Section 7 of GPL version 3, you are granted additional
+permissions described in the GCC Runtime Library Exception, version
+3.1, as published by the Free Software Foundation.
+
+You should have received a copy of the GNU General Public License
+and a copy of the GCC Runtime Library Exception along with this
+program; see the files COPYING3 and COPYING.RUNTIME respectively.
+If not, see .  */
+
+#ifdef __loongarch_hard_float
+
+/* Rounding control.  */
+#define _FPU_RC_NEAREST 0x000 /* RECOMMENDED.  */
+#define _FPU_RC_ZERO0x100
+#define _FPU_RC_UP  0x200
+#define _FPU_RC_DOWN 

[PATCH v4 12/12] LoongArch Port: Add doc.

[chenglulu]

* contrib/config-list.mk: Add LoongArch triplet.
* gcc/doc/install.texi: Add LoongArch options section.
* gcc/doc/invoke.texi: Add LoongArch options section.
* gcc/doc/md.texi: Add LoongArch options section.
---
 contrib/config-list.mk |   5 +-
 gcc/doc/install.texi   |  47 +-
 gcc/doc/invoke.texi| 201 +
 gcc/doc/md.texi|  55 +++
 4 files changed, 302 insertions(+), 6 deletions(-)

diff --git a/contrib/config-list.mk b/contrib/config-list.mk
index 3e1d1321861..ba6f12e4693 100644
--- a/contrib/config-list.mk
+++ b/contrib/config-list.mk
@@ -57,7 +57,10 @@ LIST = aarch64-elf aarch64-linux-gnu aarch64-rtems \
   i686-wrs-vxworksae \
   i686-cygwinOPT-enable-threads=yes i686-mingw32crt ia64-elf \
   ia64-freebsd6 ia64-linux ia64-hpux ia64-hp-vms iq2000-elf lm32-elf \
-  lm32-rtems lm32-uclinux m32c-rtems m32c-elf m32r-elf m32rle-elf \
+  lm32-rtems lm32-uclinux \
+  loongarch64-linux-gnu loongarch64-linux-gnuf64 \
+  loongarch64-linux-gnuf32 loongarch64-linux-gnusf \
+  m32c-rtems m32c-elf m32r-elf m32rle-elf \
   m68k-elf m68k-netbsdelf \
   m68k-uclinux m68k-linux m68k-rtems \
   mcore-elf microblaze-linux microblaze-elf \
diff --git a/gcc/doc/install.texi b/gcc/doc/install.texi
index 549da22aa16..4e0cf20347e 100644
--- a/gcc/doc/install.texi
+++ b/gcc/doc/install.texi
@@ -752,9 +752,9 @@ Here are the possible CPU types:
 @quotation
 aarch64, aarch64_be, alpha, alpha64, amdgcn, arc, arceb, arm, armeb, avr, bfin,
 bpf, cr16, cris, csky, epiphany, fido, fr30, frv, ft32, h8300, hppa, hppa2.0,
-hppa64, i486, i686, ia64, iq2000, lm32, m32c, m32r, m32rle, m68k, mcore,
-microblaze, microblazeel, mips, mips64, mips64el, mips64octeon, mips64orion,
-mips64vr, mipsel, mipsisa32, mipsisa32r2, mipsisa64, mipsisa64r2,
+hppa64, i486, i686, ia64, iq2000, lm32, loongarch64, m32c, m32r, m32rle, m68k,
+mcore, microblaze, microblazeel, mips, mips64, mips64el, mips64octeon,
+mips64orion, mips64vr, mipsel, mipsisa32, mipsisa32r2, mipsisa64, mipsisa64r2,
 mipsisa64r2el, mipsisa64sb1, mipsisa64sr71k, mipstx39, mmix, mn10300, moxie,
 msp430, nds32be, nds32le, nios2, nvptx, or1k, pdp11, powerpc, powerpc64,
 powerpc64le, powerpcle, pru, riscv32, riscv32be, riscv64, riscv64be, rl78, rx,
@@ -1171,8 +1171,9 @@ sysv, aix.
 @itemx --without-multilib-list
 Specify what multilibs to build.  @var{list} is a comma separated list of
 values, possibly consisting of a single value.  Currently only implemented
-for aarch64*-*-*, arm*-*-*, riscv*-*-*, sh*-*-* and x86-64-*-linux*.  The
-accepted values and meaning for each target is given below.
+for aarch64*-*-*, arm*-*-*, loongarch64-*-*, riscv*-*-*, sh*-*-* and
+x86-64-*-linux*.  The accepted values and meaning for each target is given
+below.
 
 @table @code
 @item aarch64*-*-*
@@ -1259,6 +1260,14 @@ profile.  The union of these options is considered when 
specifying both
 @code{-mfloat-abi=hard}
 @end multitable
 
+@item loongarch*-*-*
+@var{list} is a comma-separated list of the following ABI identifiers:
+@code{lp64d[/base]} @code{lp64f[/base]} @code{lp64d[/base]}, where the
+@code{/base} suffix may be omitted, to enable their respective run-time
+libraries.  If @var{list} is empty, @code{default}
+or @option{--with-multilib-list} is not specified, then the default ABI
+as specified by @option{--with-abi} or implied by @option{--target} is 
selected.
+
 @item riscv*-*-*
 @var{list} is a single ABI name.  The target architecture must be either
 @code{rv32gc} or @code{rv64gc}.  This will build a single multilib for the
@@ -4430,6 +4439,34 @@ This configuration is intended for embedded systems.
 Lattice Mico32 processor.
 This configuration is intended for embedded systems running uClinux.
 
+@html
+
+@end html
+@anchor{loongarch}
+@heading LoongArch
+LoongArch processor.
+The following LoongArch targets are available:
+@table @code
+@item loongarch64-linux-gnu*
+LoongArch processor running GNU/Linux.  This target triplet may be coupled
+with a small set of possible suffixes to identify their default ABI type:
+@table @code
+@item f64
+Uses @code{lp64d/base} ABI by default.
+@item f32
+Uses @code{lp64f/base} ABI by default.
+@item sf
+Uses @code{lp64s/base} ABI by default.
+@end table
+
+@item loongarch64-linux-gnu
+Same as @code{loongarch64-linux-gnuf64}, but may be used with
+@option{--with-abi=*} to configure the default ABI type.
+@end table
+
+More information about LoongArch can be found at
+@uref{https://github.com/loongson/LoongArch-Documentation}.
+
 @html
 
 @end html
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index ca621577432..2cf226604f7 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -991,6 +991,16 @@ Objective-C and Objective-C++ Dialects}.
 @gccoptlist{-mbarrel-shift-enabled  -mdivide-enabled  -mmultiply-enabled @gol
 -msign-extend-enabled  -muser-enabled}
 
+@emph{LoongArch Options}
+@gccoptlist{-march=@var{cpu-type}  -mtune=@var{cpu-type} 
-mabi=@var{bas

[PATCH v4] tree-optimization/101186 - extend FRE with "equivalence map" for condition prediction

[Di Zhao OS via Gcc-patches]

Here's a brief summary on the patch:

v4 (this version):
- In process_bb's condition-prediction code: update equivalence-heads if
  value-numbers have changed, otherwise some chances can be lost.

v3 (a few minor updates): 
- Simplify function record_equiv_from_prev_phi_1 by removing an argument.
- Fixed two small bugs that can lead to losing optimize opportunities.
- Link: https://gcc.gnu.org/pipermail/gcc-patches/2021-December/586687.html

v2:
- Use equivalence-heads (disjoint set) to represent temporary equivalences.
- Improved performance by reducing predicates-recording.
- The last version and some discussion:
  https://gcc.gnu.org/pipermail/gcc-patches/2021-December/586116.html
- Earlier discussion:
  https://gcc.gnu.org/pipermail/gcc-patches/2021-October/580688.html
- The patch:
  https://gcc.gnu.org/pipermail/gcc-patches/2021-September/579607.html

v1: 
- The initial patch (use a hashmap to store temporary equivalences):
  https://gcc.gnu.org/pipermail/gcc-patches/2021-June/573603.html
- Updates (fixed some code-style issue) and some explanation:
  https://gcc.gnu.org/pipermail/gcc-patches/2021-July/575531.html
- Reply from Richard:
  https://gcc.gnu.org/pipermail/gcc-patches/2021-July/576185.html

If the patch is considered, a following step I'm thinking is to
teach PRE pass with the temporary equivalences. Currently regression
test pr68619-4.c fails with the patch, because a variable's value
number turns to constant, and its equivalent's head is lost in the
AVAIL set. I think with this change, more partial redundancies can
be found.

Thanks,
Di Zhao

---

Extend FRE with temporary equivalences.

2021-12-24  Di Zhao  

gcc/ChangeLog:
PR tree-optimization/101186
* tree-ssa-sccvn.c (VN_INFO): remove assertions (there could be a
predicate already).
(dominated_by_p_w_unex): Moved upward.
(vn_nary_op_get_predicated_value): Moved upward.
(is_vn_valid_at_bb): Check if vn_pval is valid at BB.
(lookup_equiv_head): Lookup the "equivalence head" of given node.
(lookup_equiv_heads): Lookup the "equivalence head"s of given nodes.
(vn_tracking_edge): Extracted utility function.
(init_vn_nary_op_from_stmt): Insert and lookup by "equivalence head"s.
(vn_nary_op_insert_into): Insert new value at the front.
(vn_nary_op_insert_pieces_predicated_1): Insert as predicated values
from pieces.
(fold_const_from_equiv_heads): Fold N-ary expression of equiv-heads.
(push_new_nary_ref): Insert a back-reference to vn_nary_op_t.
(val_equiv_insert): Record temporary equivalence.
(vn_nary_op_insert_pieces_predicated): Record equivalences instead of
some predicates; insert back-refs.
(record_equiv_from_prev_phi_1): Record temporary equivalences generated
by PHI nodes.
(record_equiv_from_prev_phi): Given an outgoing edge of a conditional
expression taken, record equivalences generated by PHI nodes.
(visit_nary_op): Add lookup previous results of N-ary operations by
equivalences.
(insert_related_predicates_on_edge): Some predicates can be computed
from equivalences, no need to insert them.
(process_bb): Add lookup predicated values by equivalences.
(struct unwind_state): Unwind state of back-refs to vn_nary_op_t.
(do_unwind): Unwind the back-refs to vn_nary_op_t.
(do_rpo_vn): Update back-reference unwind state.
* tree-ssa-sccvn.h (struct nary_ref): hold a lists of references to the
nary map entries.

gcc/testsuite/ChangeLog:

* gcc.dg/tree-ssa/pr68619-2.c: Disable fre.
* gcc.dg/tree-ssa/pr71947-1.c: Disable fre.
* gcc.dg/tree-ssa/pr71947-2.c: Disable fre.
* gcc.dg/tree-ssa/pr71947-3.c: Disable fre.
* gcc.dg/tree-ssa/pr71947-5.c: Disable fre.
* gcc.dg/tree-ssa/pr71947-7.c: Disable fre.
* gcc.dg/tree-ssa/pr71947-8.c: Disable fre.
* gcc.dg/tree-ssa/pr71947-9.c: Disable fre.
* gcc.dg/tree-ssa/vrp03.c: Disable fre.
* gcc.dg/tree-ssa/ssa-fre-100.c: New test.
* gcc.dg/tree-ssa/ssa-fre-101.c: New test.
* gcc.dg/tree-ssa/ssa-fre-102.c: New test.
* gcc.dg/tree-ssa/ssa-pre-34.c: New test.


v4-tree-optimization-101186.patch
Description: v4-tree-optimization-101186.patch

Libbacktrace: Fix the use of newline in sed replacement

[FX via Gcc-patches]

Hi,

Libbacktrace fails to run “make check" on macOS (*-apple-darwin21), where the 
system make is GNU Make 3.81. But I think it would occur on all platforms that 
are not ELF and use make < 4. Running `make check` leads to this failure:

elf_32.c:144:26: error: extra tokens at end of #undef directive [-Werror]
  144 | #undef BACKTRACE_ELF_SIZE#define BACKTRACE_ELF_SIZE 32
  |  ^

where the invalid elf_32.c is generated by this command:

SEARCH='#error "Unknown BACKTRACE_ELF_SIZE"'; \
REPLACE='#undef BACKTRACE_ELF_SIZE\
#define BACKTRACE_ELF_SIZE'; \
/usr/bin/sed "s/^$SEARCH\$/$REPLACE 32/" \
/tmp/gcc-darwin-arm64/libbacktrace/elf.c \
> elf_32.c.tmp
mv elf_32.c.tmp elf_32.c

This tries to have a newline inside the REPLACE string, and pass it to sed. 
This fails with GNU Make < 4. And GCC requires "GNU make version 3.80 (or 
later)".

The portable solution is given in the autoconf manual: 
https://www.gnu.org/software/autoconf/manual/autoconf-2.69/html_node/Newlines-in-Make-Rules.html

Attached is a patch that fixes it. Tested on x86_64-apple-darwin21.
OK to commit?

FX



libbacktrace.patch
Description: Binary data

[pushed] Darwin: Define OBJECT_FORMAT_MACHO.

[Iain Sandoe via Gcc-patches]

There are places that we need to make different codegen depending
on the object format rather than on the arch.  We already have
definitions for ELF, COFF etc. this adds one for MACHO.

Tested on i686, powerpc, x86_64 and aarch64 Darwin.
pushed to master, thanks
Iain

Signed-off-by: Iain Sandoe 

gcc/ChangeLog:

* config/darwin.h (OBJECT_FORMAT_MACHO): New.
---
 gcc/config/darwin.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/gcc/config/darwin.h b/gcc/config/darwin.h
index 75b688ebf9e..c175eade887 100644
--- a/gcc/config/darwin.h
+++ b/gcc/config/darwin.h
@@ -43,6 +43,8 @@ see the files COPYING3 and COPYING.RUNTIME respectively.  If 
not, see
 #define DARWIN_X86 0
 #define DARWIN_PPC 0
 
+#define OBJECT_FORMAT_MACHO 1
+
 /* Suppress g++ attempt to link in the math library automatically. */
 #define MATH_LIBRARY ""
 
-- 
2.24.3 (Apple Git-128)

[pushed] Darwin: Check for that flag-reorder-and-partition.

[Iain Sandoe via Gcc-patches]

We were checking whether the flag had been set by the user, but not if
it was set to true.  Which means that the check fails in its intent when
the user puts -fno-reorder-and-partition.

Tested on i686, powerpc and x86_64-darwin. Pushed to master, thanks
Iain

Signed-off-by: Iain Sandoe 

gcc/ChangeLog:

* config/darwin.c (darwin_override_options): When checking for the
flag-reorder-and-partition case, also check that it is set on.
---
 gcc/config/darwin.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/gcc/config/darwin.c b/gcc/config/darwin.c
index 8ad5b26c980..e580319f761 100644
--- a/gcc/config/darwin.c
+++ b/gcc/config/darwin.c
@@ -3336,6 +3336,7 @@ darwin_override_options (void)
   (s)he knows why...  */
if (generating_for_darwin_version < 9
&& OPTION_SET_P (flag_reorder_blocks_and_partition)
+   && flag_reorder_blocks_and_partition
&& ((global_options.x_flag_exceptions   /* User, c++, java */
&& !OPTION_SET_P (flag_exceptions)) /* User specified... */
   || (global_options.x_flag_unwind_tables
-- 
2.24.3 (Apple Git-128)

Re: [pushed] Darwin: Check for that flag-reorder-and-partition.

[Andrew Pinski via Gcc-patches]

On Fri, Dec 24, 2021 at 2:47 AM Iain Sandoe via Gcc-patches
 wrote:
>
> We were checking whether the flag had been set by the user, but not if
> it was set to true.  Which means that the check fails in its intent when
> the user puts -fno-reorder-and-partition.
>
> Tested on i686, powerpc and x86_64-darwin. Pushed to master, thanks
> Iain
>
> Signed-off-by: Iain Sandoe 
>
> gcc/ChangeLog:
>
> * config/darwin.c (darwin_override_options): When checking for the
> flag-reorder-and-partition case, also check that it is set on.
> ---
>  gcc/config/darwin.c | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/gcc/config/darwin.c b/gcc/config/darwin.c
> index 8ad5b26c980..e580319f761 100644
> --- a/gcc/config/darwin.c
> +++ b/gcc/config/darwin.c
> @@ -3336,6 +3336,7 @@ darwin_override_options (void)
>(s)he knows why...  */

I see you already pushed this code, it might be a good idea to also
change (s)he to just they in the above comment too.

Thanks,
Andrew


> if (generating_for_darwin_version < 9
> && OPTION_SET_P (flag_reorder_blocks_and_partition)
> +   && flag_reorder_blocks_and_partition
> && ((global_options.x_flag_exceptions   /* User, c++, java */
> && !OPTION_SET_P (flag_exceptions)) /* User specified... 
> */
>|| (global_options.x_flag_unwind_tables
> --
> 2.24.3 (Apple Git-128)
>

[pushed] Darwin: Update rules for handling alignment of globals.

[Iain Sandoe via Gcc-patches]

The current rule was too strict and has not been required since Darwin11.

This relaxes the constraint to allow up to 2^28 alignment for non-common
entities.  Common is still restricted to a maximum aligment of 2^15.

When the host is an older version of Darwin ( earlier that 11 ) then the
existing constraint is still applied.  Note that this is a host constraint
not a target one (so that a compilation on 10.7 targeting 10.6 is allowed
to use a greater alignment than the tools on 10.6 support).  This matches
the behaviour of clang.

This showed up in testcases on the aarch64 branch, but is equally an issue
on both i686 and x86_64 for Darwin versions >= 11.  Tested on i686, powerpc
x86_64 and aarch64 darwin, pushed to master, thanks,
Iain

Signed-off-by: Iain Sandoe 

gcc/ChangeLog:

* config.gcc: Emit L2_MAX_OFILE_ALIGNMENT with suitable
values for the host.
* config/darwin.c (darwin_emit_common): Error for alignment
values > 32768.
* config/darwin.h (MAX_OFILE_ALIGNMENT): Rework to use the
configured L2_MAX_OFILE_ALIGNMENT.

gcc/testsuite/ChangeLog:

* gcc.dg/darwin-aligned-globals.c: New test.
* gcc.dg/darwin-comm-1.c: New test.
* gcc.dg/attr-aligned.c: Amend for new alignment values on
Darwin.
* gcc.target/i386/pr89261.c: Likewise.
---
 gcc/config.gcc| 14 +++
 gcc/config/darwin.c   | 17 +
 gcc/config/darwin.h   |  9 ---
 gcc/testsuite/gcc.dg/attr-aligned.c   |  8 +--
 gcc/testsuite/gcc.dg/darwin-aligned-globals.c | 24 +++
 gcc/testsuite/gcc.dg/darwin-comm-1.c  |  5 
 gcc/testsuite/gcc.target/i386/pr89261.c   |  3 ++-
 7 files changed, 68 insertions(+), 12 deletions(-)
 create mode 100644 gcc/testsuite/gcc.dg/darwin-aligned-globals.c
 create mode 100644 gcc/testsuite/gcc.dg/darwin-comm-1.c

diff --git a/gcc/config.gcc b/gcc/config.gcc
index bf1c7454e05..294f3123e38 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -677,6 +677,20 @@ case ${target} in
 macos_min=0
   fi
   def_ld64=85.2
+  # Tools hosted on earlier versions of Darwin constrained all object
+  # alignment to be 2^15 or smaller.  From Darwin11 (macOS 10.7) the
+  # alignment of non-common is allowed to be up to 2^28.  Note that the
+  # larger alignment is permitted when targeting 10.6 from 10.7 so that
+  # the constraint only need be applied per host (and only if the host
+  # is Darwin).
+  case ${host} in
+  *-*-darwin[4-9]* | *-*-darwin10*)
+  tm_defines="$tm_defines L2_MAX_OFILE_ALIGNMENT=15U"
+  ;;
+  *)
+  tm_defines="$tm_defines L2_MAX_OFILE_ALIGNMENT=28U"
+  ;;
+  esac
   case ${target} in
   # Darwin 4 to 19 correspond to macOS 10.0 to 10.15
   *-*-darwin[4-9]* | *-*-darwin1[0-9]*)
diff --git a/gcc/config/darwin.c b/gcc/config/darwin.c
index e580319f761..5045b68e8af 100644
--- a/gcc/config/darwin.c
+++ b/gcc/config/darwin.c
@@ -2558,7 +2558,6 @@ darwin_emit_common (FILE *fp, const char *name,
 rounded = (size + (align-1)) & ~(align-1);
 
   l2align = floor_log2 (align);
-  gcc_assert (l2align <= L2_MAX_OFILE_ALIGNMENT);
 
   in_section = comm_section;
   /* We mustn't allow multiple public symbols to share an address when using
@@ -2709,6 +2708,10 @@ darwin_asm_output_aligned_decl_common (FILE *fp, tree 
decl, const char *name,
 #ifdef DEBUG_DARWIN_MEM_ALLOCATORS
 fprintf (fp, "# adcom: %s (%d,%d) decl=0x0\n", name, (int)size, (int)align);
 #endif
+ /* Common variables are limited to a maximum alignment of 2^15.  */
+  if (align > 32768)
+   error_at (UNKNOWN_LOCATION, "common variables must have an alignment"
+ " of 32678 or less");
   darwin_emit_common (fp, name, size, align);
   return;
 }
@@ -2736,7 +2739,7 @@ fprintf (fp, "# adcom: %s (%lld,%d) ro %d cst %d stat %d 
com %d pub %d"
 }
 
   /* We shouldn't be messing with this if the decl has a section name.  */
-  gcc_assert (DECL_SECTION_NAME (decl) == NULL);
+  gcc_checking_assert (DECL_SECTION_NAME (decl) == NULL);
 
   /* We would rather not have to check this here - but it seems that we might
  be passed a decl that should be in coalesced space.  */
@@ -2765,10 +2768,16 @@ fprintf (fp, "# adcom: %s (%lld,%d) ro %d cst %d stat 
%d com %d pub %d"
 
   l2align = floor_log2 (align / BITS_PER_UNIT);
   /* Check we aren't asking for more aligment than the platform allows.  */
-  gcc_assert (l2align <= L2_MAX_OFILE_ALIGNMENT);
+  gcc_checking_assert (l2align <= L2_MAX_OFILE_ALIGNMENT);
 
   if (TREE_PUBLIC (decl) != 0)
-darwin_emit_common (fp, name, size, align);
+{
+  /* Common variables are limited to a maximum alignment of 2^15.  */
+  if (l2align > 15)
+   error_at (DECL_SOURCE_LOCATION (decl), "common variables must have"
+ " an alignment of 32678 or less");
+  darwin_emit_common (fp, name, size, a

Re: [pushed] Darwin: Check for that flag-reorder-and-partition.

[Iain Sandoe via Gcc-patches]

Hi Andrew,

> On 24 Dec 2021, at 10:51, Andrew Pinski  wrote:
> 
> On Fri, Dec 24, 2021 at 2:47 AM Iain Sandoe via Gcc-patches
>  wrote:
>> 
>> 

>> @@ -3336,6 +3336,7 @@ darwin_override_options (void)
>>   (s)he knows why...  */
> 
> I see you already pushed this code, it might be a good idea to also
> change (s)he to just they in the above comment too.

done as below, thanks,
Iain

[pushed] Darwin: Amend a comment to be more inclusive [NFC].

As per title.

Signed-off-by: Iain Sandoe 

gcc/ChangeLog:

* config/darwin.c (darwin_override_options): Make a comment
more inclusive.
---
 gcc/config/darwin.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/gcc/config/darwin.c b/gcc/config/darwin.c
index 5045b68e8af..c8e8b9d9f86 100644
--- a/gcc/config/darwin.c
+++ b/gcc/config/darwin.c
@@ -3339,10 +3339,10 @@ darwin_override_options (void)
 
/* Disable -freorder-blocks-and-partition when unwind tables are being
   emitted for Darwin < 9 (OSX 10.5).
-  The strategy is, "Unless the User has specifically set/unset an unwind
+  The strategy is, "Unless the user has specifically set/unset an unwind
   flag we will switch off -freorder-blocks-and-partition when unwind tables
-  will be generated".  If the User specifically sets flags... we assume
-  (s)he knows why...  */
+  will be generated".  If the user specifically sets flags, we have to
+  assume they know why.  */
if (generating_for_darwin_version < 9
&& OPTION_SET_P (flag_reorder_blocks_and_partition)
&& flag_reorder_blocks_and_partition
-- 
2.24.3 (Apple Git-128)

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[Aashu via Gcc-patches]

Hello (gcc-patches@gcc.gnu.org)

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designer & developer with 5+ years' experience. Do you need a great Website
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[PATCH] i386: Add V2SFmode DIV insn pattern [PR95046, PR103797]

[Uros Bizjak via Gcc-patches]

Use V4SFmode "DIVPS X,Y" with [y0, y1, 1.0f, 1.0f] as a divisor
to avoid division by zero.

2021-12-24  Uroš Bizjak  

gcc/ChangeLog:

PR target/95046
PR target/103797
* config/i386/mmx.md (divv2sf3): New instruction pattern.

gcc/testsuite/ChangeLog:

PR target/95046
PR target/103797
* gcc.target/i386/pr95046-1.c (test_div): Add.
(dg-options): Add -mno-recip.

Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}.

Pushed to master.

Uros.
diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md
index 6c5cbcfa52c..5a5755654c2 100644
--- a/gcc/config/i386/mmx.md
+++ b/gcc/config/i386/mmx.md
@@ -523,6 +523,26 @@
(set_attr "prefix" "*,orig,vex")
(set_attr "mode" "V2SF,V4SF,V4SF")])
 
+(define_expand "divv2sf3"
+  [(set (match_operand:V2SF 0 "register_operand")
+   (div:V2SF (match_operand:V2SF 1 "register_operand")
+ (match_operand:V2SF 2 "register_operand")))]
+  "TARGET_MMX_WITH_SSE"
+{
+  rtx op0 = lowpart_subreg (V4SFmode, operands[0],
+   GET_MODE (operands[0]));
+  rtx op1 = lowpart_subreg (V4SFmode, operands[1],
+   GET_MODE (operands[1]));
+  rtx op2 = gen_rtx_VEC_CONCAT (V4SFmode, operands[2],
+   force_reg (V2SFmode, CONST1_RTX (V2SFmode)));
+  rtx tmp = gen_reg_rtx (V4SFmode);
+
+  emit_insn (gen_rtx_SET (tmp, op2));
+
+  emit_insn (gen_divv4sf3 (op0, op1, tmp));
+  DONE;
+})
+
 (define_expand "mmx_v2sf3"
   [(set (match_operand:V2SF 0 "register_operand")
 (smaxmin:V2SF
diff --git a/gcc/testsuite/gcc.target/i386/pr95046-1.c 
b/gcc/testsuite/gcc.target/i386/pr95046-1.c
index bcc8bb5bfab..2a0e6db5fa5 100644
--- a/gcc/testsuite/gcc.target/i386/pr95046-1.c
+++ b/gcc/testsuite/gcc.target/i386/pr95046-1.c
@@ -1,6 +1,6 @@
 /* PR target/95046 */
 /* { dg-do compile { target { ! ia32 } } } */
-/* { dg-options "-O3 -ffast-math -msse2" } */
+/* { dg-options "-O3 -ffast-math -msse2 -mno-recip" } */
 
 
 float r[2], a[2], b[2];
@@ -32,6 +32,15 @@ test_mult (void)
 
 /* { dg-final { scan-assembler "\tv?mulps" } } */
 
+void
+test_div (void)
+{
+  for (int i = 0; i < 2; i++)
+r[i] = a[i] / b[i];
+}
+
+/* { dg-final { scan-assembler "\tv?divps" } } */
+
 void
 test_min (void)
 {

[r12-6113 Regression] FAIL: gfortran.dg/extract_recip_1.f -O scan-tree-dump-times optimized "rdiv_expr" 1 on Linux/x86_64

[sunil.k.pandey via Gcc-patches]

On Linux/x86_64,

8f921393e339090566c1589d81009caa954de90d is the first bad commit
commit 8f921393e339090566c1589d81009caa954de90d
Author: Uros Bizjak 
Date:   Fri Dec 24 17:09:36 2021 +0100

i386: Add V2SFmode DIV insn pattern [PR95046, PR103797]

caused

FAIL: gfortran.dg/extract_recip_1.f   -O   scan-tree-dump-times optimized 
"rdiv_expr" 1

with GCC configured with

../../gcc/configure 
--prefix=/local/skpandey/gccwork/toolwork/gcc-bisect-master/master/r12-6113/usr 
--enable-clocale=gnu --with-system-zlib --with-demangler-in-ld 
--with-fpmath=sse --enable-languages=c,c++,fortran --enable-cet --without-isl 
--enable-libmpx x86_64-linux --disable-bootstrap

To reproduce:

$ cd {build_dir}/gcc && make check 
RUNTESTFLAGS="dg.exp=gfortran.dg/extract_recip_1.f --target_board='unix{-m64}'"
$ cd {build_dir}/gcc && make check 
RUNTESTFLAGS="dg.exp=gfortran.dg/extract_recip_1.f --target_board='unix{-m64\ 
-march=cascadelake}'"

(Please do not reply to this email, for question about this report, contact me 
at skpgkp2 at gmail dot com)

[PATCH v2] i386: Check AX input in any_mul_highpart peepholes

[H.J. Lu via Gcc-patches]

When applying peephole optimization to transform

mov imm, %reg0
mov %reg1, %AX_REG
imul %reg0

to

mov imm, %AX_REG
imul %reg1

disable peephole optimization if reg1 == AX_REG as in

(set (reg:SI 1 dx [92])
 (const_int 714200473 [0x2a91d599]))
(set (reg:SI 0 ax [105])
 (reg:SI 0 ax [orig:89 k ] [89]))
(parallel [
  (set (reg:SI 1 dx [91])
   (smul_highpart:SI (reg:SI 0 ax [105]) (reg:SI 1 dx [92])))
   (clobber (reg:SI 0 ax [105]))
   (clobber (reg:CC 17 flags))
])

PR bootstrap/103785
* config/i386/i386.md: Swap operand order in comments and check
AX input in any_mul_highpart peepholes.
---
 gcc/config/i386/i386.md | 9 ++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 58b10643fcb..72e6486a92f 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -8552,7 +8552,7 @@
(set_attr "mode" "SI")])
 
 ;; Highpart multiplication peephole2s to tweak register allocation.
-;; mov %rdx,imm; mov %rax,%rdi; imulq %rdx  ->  mov %rax,imm; imulq %rdi
+;; mov imm,%rdx; mov %rdi,%rax; imulq %rdx  ->  mov imm,%rax; imulq %rdi
 (define_peephole2
   [(set (match_operand:SWI48 0 "general_reg_operand")
(match_operand:SWI48 1 "immediate_operand"))
@@ -8562,7 +8562,8 @@
   (any_mul_highpart:SWI48 (match_dup 2) (match_dup 0)))
  (clobber (match_dup 2))
  (clobber (reg:CC FLAGS_REG))])]
-  "REGNO (operands[0]) != REGNO (operands[2])
+  "REGNO (operands[3]) != AX_REG
+   && REGNO (operands[0]) != REGNO (operands[2])
&& REGNO (operands[0]) != REGNO (operands[3])
&& (REGNO (operands[0]) == REGNO (operands[4])
|| peep2_reg_dead_p (3, operands[0]))"
@@ -8582,7 +8583,9 @@
 (any_mul_highpart:SI (match_dup 2) (match_dup 0
  (clobber (match_dup 2))
  (clobber (reg:CC FLAGS_REG))])]
-  "REGNO (operands[0]) != REGNO (operands[2])
+  "REGNO (operands[3]) != AX_REG
+   && REGNO (operands[0]) != REGNO (operands[2])
+   && REGNO (operands[2]) != REGNO (operands[3])
&& REGNO (operands[0]) != REGNO (operands[3])
&& (REGNO (operands[0]) == REGNO (operands[4])
|| peep2_reg_dead_p (3, operands[0]))"
-- 
2.33.1

[PATCH v2 1/2] diagnostics: Honor #pragma GCC diagnostic in the preprocessor [PR53431]

[Lewis Hyatt via Gcc-patches]

Hello-

I would like please to follow up on this patch submitted for PR53431 here:
https://gcc.gnu.org/pipermail/gcc-patches/2021-December/586191.html

However, it was suggested on the PR that part of it could be split into a
separate simpler patch. I have now done that, and also made a few tweaks to
the first version at the same time, so may I please request that you review
this version 2 instead? This email contains the first smaller cleanup patch,
and the next email contains the main part of it. Thanks very much.

bootstrap and regtest were performed on x86-64 Linux, all tests look the same
before + after, plus the new passing testcases.

FAIL 112 112
PASS 528007 528042
UNSUPPORTED 14888 14888
UNTESTED 132 132
XFAIL 3238 3238
XPASS 17 17

-Lewis
From: Lewis Hyatt 
Date: Thu, 23 Dec 2021 17:03:04 -0500
Subject: [PATCH] c++: Minor cleanup in parser.c

The code to determine whether a given token starts a module directive is
currently repeated in 4 places in parser.c. I am about to submit a patch
that needs to add it in a 5th place, so since the code is not completely
trivial (needing to check for 3 different token types), it seems worthwhile
to factor this logic into its own function.

gcc/cp/ChangeLog:

* parser.c (cp_token_is_module_directive): New function
refactoring common code.
(cp_parser_skip_to_closing_parenthesis_1): Use the new function.
(cp_parser_skip_to_end_of_statement): Likewise.
(cp_parser_skip_to_end_of_block_or_statement): Likewise.
(cp_parser_declaration): Likewise.

diff --git a/gcc/cp/parser.c b/gcc/cp/parser.c
index 33fb40a5b59..9b7446655be 100644
--- a/gcc/cp/parser.c
+++ b/gcc/cp/parser.c
@@ -629,6 +629,16 @@ cp_lexer_alloc (void)
   return lexer;
 }
 
+/* Return TRUE if token is the start of a module declaration that will be
+   terminated by a CPP_PRAGMA_EOL token.  */
+static inline bool
+cp_token_is_module_directive (cp_token *token)
+{
+  return token->keyword == RID__EXPORT
+|| token->keyword == RID__MODULE
+|| token->keyword == RID__IMPORT;
+}
+
 /* Create a new main C++ lexer, the lexer that gets tokens from the
preprocessor.  */
 
@@ -3805,9 +3815,7 @@ cp_parser_skip_to_closing_parenthesis_1 (cp_parser 
*parser,
  break;
 
case CPP_KEYWORD:
- if (token->keyword != RID__EXPORT
- && token->keyword != RID__MODULE
- && token->keyword != RID__IMPORT)
+ if (!cp_token_is_module_directive (token))
break;
  /* FALLTHROUGH  */
 
@@ -3908,9 +3916,7 @@ cp_parser_skip_to_end_of_statement (cp_parser* parser)
  break;
 
case CPP_KEYWORD:
- if (token->keyword != RID__EXPORT
- && token->keyword != RID__MODULE
- && token->keyword != RID__IMPORT)
+ if (!cp_token_is_module_directive (token))
break;
  /* FALLTHROUGH  */
 
@@ -3997,9 +4003,7 @@ cp_parser_skip_to_end_of_block_or_statement (cp_parser* 
parser)
  break;
 
case CPP_KEYWORD:
- if (token->keyword != RID__EXPORT
- && token->keyword != RID__MODULE
- && token->keyword != RID__IMPORT)
+ if (!cp_token_is_module_directive (token))
break;
  /* FALLTHROUGH  */
 
@@ -14860,9 +14864,7 @@ cp_parser_declaration (cp_parser* parser, tree 
prefix_attrs)
   else
cp_parser_module_export (parser);
 }
-  else if (token1->keyword == RID__EXPORT
-  || token1->keyword == RID__IMPORT
-  || token1->keyword == RID__MODULE)
+  else if (cp_token_is_module_directive (token1))
 {
   bool exporting = token1->keyword == RID__EXPORT;
   cp_token *next = exporting ? token2 : token1;

[PATCH v2 2/2] diagnostics: Honor #pragma GCC diagnostic in the preprocessor [PR53431]

[Lewis Hyatt via Gcc-patches]

Hello-

Here is part 2/2 of the patch version 2 introduced here:
https://gcc.gnu.org/pipermail/gcc-patches/2021-December/587357.html
to resolve PR53431. Thank you!

-Lewis
>From 79dfa93ff94bbf492b396d1e6b3d06f1f95a6315 Mon Sep 17 00:00:00 2001
From: Lewis Hyatt 
Date: Sat, 4 Dec 2021 11:20:00 -0500
Subject: [PATCH] diagnostics: Honor #pragma GCC diagnostic in the preprocessor
 [PR53431]

As discussed on PR c++/53431, currently, "#pragma GCC diagnostic" does
not always take effect for diagnostics generated by libcpp. The reason
is that libcpp itself does not interpret this pragma and only sends it on
to the frontend, hence the pragma is only honored if the frontend
arranges for it. The C frontend does process the pragma immediately
(more or less) after seeing the token, so things work fine there. The PR
points out that it doesn't work for C++, because the C++ frontend
doesn't handle anything until it has read all the tokens from
libcpp. The underlying problem is not C++-specific, though, and for
instance, gcc -E has the same issue.

This commit fixes the PR by adding the concept of an early pragma handler that
can be registered by frontends, which gives them a chance to process
diagnostic pragmas from libcpp before it is too late for them to take
effect. The C++ and preprocess-only frontends are modified to use early
pragmas and correct the behavior.

gcc/c-family/ChangeLog:

PR c++/53431
* c-common.c (c_option_is_from_cpp_diagnostics): New function.
* c-common.h (c_option_is_from_cpp_diagnostics): Declare.
(c_pp_output_diagnostic_pragma): Declare.
* c-ppoutput.c (init_pp_output): Refactor logic about skipping pragmas
to...
(should_output_pragmas): ...here.  New function.
(class token_streamer): Added new member "skip_this_pragma".
(token_streamer::stream): Support printing early pragmas.
(do_line_change): Likewise.
(c_pp_output_diagnostic_pragma): New function.
* c-pragma.c (struct pragma_diagnostic_data): New helper class.
(pragma_diagnostic_lex_normal): New function. Moved logic for
interpreting GCC diagnostic pragmas here.
(pragma_diagnostic_lex_pp): New function for parsing diagnostic pragmas
directly from libcpp.
(handle_pragma_diagnostic): Refactor into helper function...
(handle_pragma_diagnostic_impl): ...here.  New function.
(handle_pragma_diagnostic_early): New function.
(handle_pragma_diagnostic_early_pp): New function.
(struct pragma_ns_name): Renamed to...
(struct pragma_pp_data): ...this.  Add new "early_handler" member.
(c_register_pragma_1): Support early pragmas in the preprocessor.
(c_register_pragma_with_early_handler): New function.
(c_register_pragma): Support the new early handlers in struct
internal_pragma_handler.
(c_register_pragma_with_data): Likewise.
(c_register_pragma_with_expansion): Likewise.
(c_register_pragma_with_expansion_and_data): Likewise.
(c_invoke_early_pragma_handler): New function.
(c_pp_invoke_early_pragma_handler): New function.
(init_pragma): Add early pragma support for diagnostic pragmas.
* c-pragma.h (struct internal_pragma_handler): Add new early handler
members.
(c_register_pragma_with_early_handler): Declare.
(c_invoke_early_pragma_handler): Declare.
(c_pp_invoke_early_pragma_handler): Declare.

gcc/cp/ChangeLog:

PR c++/53431
* parser.c (cp_parser_pragma_kind): Move earlier in the file.
(cp_lexer_handle_early_pragma): New function.
(cp_lexer_new_main): Support parsing and handling early pragmas.
(c_parse_file): Adapt to changes in cp_lexer_new_main.

gcc/testsuite/ChangeLog:

PR c++/53431
* c-c++-common/pragma-diag-11.c: New test.
* c-c++-common/pragma-diag-12.c: New test.
* c-c++-common/pragma-diag-13.c: New test.

diff --git a/gcc/c-family/c-common.c b/gcc/c-family/c-common.c
index a25d59fa77b..0a821e24b3c 100644
--- a/gcc/c-family/c-common.c
+++ b/gcc/c-family/c-common.c
@@ -6594,6 +6594,20 @@ c_option_controlling_cpp_diagnostic (enum 
cpp_warning_reason reason)
   return 0;
 }
 
+/* Return TRUE if the given option index corresponds to a diagnostic
+   issued by libcpp.  Linear search seems fine for now.  */
+bool
+c_option_is_from_cpp_diagnostics (int option_index)
+{
+  for (auto entry = cpp_reason_option_codes; entry->reason != CPP_W_NONE;
+   ++entry)
+{
+  if (entry->option_code == option_index)
+   return true;
+}
+  return false;
+}
+
 /* Callback from cpp_diagnostic for PFILE to print diagnostics from the
preprocessor.  The diagnostic is of type LEVEL, with REASON set
to the reason code if LEVEL is represents a warning, at location
diff --git a/gcc/c-family/c-common.h b/gcc/c-family/c-common.h
index c089fda12e4..287a792065b 100644
--- a/gcc/c-family/c-comm

Re: [PATCH] i386: Require TARGET_64BIT for any_mul_highpart peephole

[H.J. Lu via Gcc-patches]

On Fri, Dec 24, 2021 at 12:17 AM Uros Bizjak  wrote:
>
> On Thu, Dec 23, 2021 at 11:21 PM H.J. Lu via Gcc-patches
>  wrote:
> >
> > Restore i686 bootstrap by requiring TARGET_64BIT for any_mul_highpart
> > peephole.
> >
> > PR bootstrap/103785
> > * config/i386/i386.md: Require TARGET_64BIT for any_mul_highpart
> > peephole.
>
> I don't think this is correct. The patch uses SWI48, where DImode is
> enabled only for TARGET_64BIT. The patch disables SImode peephole only
> for 32bit targets, so if there is something wrong with the peephole,
> it still remains buggy for 64bit targets. Either we remove problematic
> peepholes to restore bootstrap or get a testcase and analyze the
> problem to figure out the correct fix.
>

I couldn't create a small testcase in C.   The problem is in

(set (reg:SI 1 dx [92])
 (const_int 714200473 [0x2a91d599]))
(set (reg:SI 0 ax [105])
 (reg:SI 0 ax [orig:89 k ] [89]))
(parallel [
  (set (reg:SI 1 dx [91])
   (smul_highpart:SI (reg:SI 0 ax [105]) (reg:SI 1 dx [92])))
   (clobber (reg:SI 0 ax [105]))
   (clobber (reg:CC 17 flags))
])

The v2 patch is posted at

https://gcc.gnu.org/pipermail/gcc-patches/2021-December/587356.html

-- 
H.J.

[PATCH v8] rtl: builtins: (not just) rs6000: Add builtins for fegetround, feclearexcept and feraiseexcept [PR94193]

[Raoni Fassina Firmino via Gcc-patches]

Changes since v7[7]:
  - Fixed an array indexing bug on fegeround testcase.
  - Fixed typos and spelling mistakes spread trouout the added comments.
  - Reworded header comment/description for fegetround expander.
  - Fixed changelog in the commit message.

After taking a look to add support for FE_INVALID I decided to not
include it in this patch. It is a little more nuanced case and it may be
the case that another type of treatment may be better suited for a case
that includes FE_INVALID, like a read-modify-write to FPSCR instead of
multiple mtfsb0/mtfsb1 instructions.

Tested on top of master (ef26c151c14a87177d46fd3d725e7f82e040e89f)
on the following plataforms with no regression:
  - powerpc64le-linux-gnu (Power 9)
  - powerpc64le-linux-gnu (Power 8)
  - powerpc64-linux-gnu (Power 9, with 32 and 64 bits tests)

Documentation changes tested on x86_64-redhat-linux.

==

I'm repeating the "changelog" from past versions here for convenience:

Changes since v6[6] and v5[5]:
  - Based this version on the v5 one.
  - Reworked all builtins back to the way they are in v5 and added the
following changes:
+ Added a test to target libc, only expanding with glibc as the
  target libc.
+ Updated all three expanders header comment to reflect the added
  behavior (fegetround got a full header as it had none).
+ Added extra documentation for the builtins on doc/extend.texi,
  similar to v6 version, but only the introductory paragraph,
  without a dedicated entry for each, since now they behavior and
  signature match the C99 ones.
  - Changed the description for the return operand in the RTL template
of the fegetround expander.  Using "(set )", the same way as
rs6000_mffsl expander (this change was taken from v6).
  - Updated the commit message mentioning the target libc restriction
and updated changelog.

Changes since v5[5]:
  - Reworked all builtins to accept the FE_* macros as parameters and
so be agnostic to libc implementations.  Largely based of
fpclassify.  To that end, there is some new files changed:
+ Change the argument list for the builtins declarations in
  builtins.def
+ Added new types in builtin-types.def to use in the buitins
  declarations.
+ Added extra documentation for the builtins on doc/extend.texi,
  similar to fpclassify.
  - Updated doc/md.texi documentation with the new optab behaviors.
  - Updated comments to the expanders and expand handlers to try to
explain whats is going on.
  - Changed the description for the return operand in the RTL template
of the fegetround expander.  Using "(set )", the same way as
rs6000_mffsl expander.
  - Updated testcases with helper macros with the new argument list.

Changes since v4[4]:
  - Fixed more spelling and code style.
  - Add more clarification on  comments for feraiseexcept and
feclearexcept expands;

Changes since v3[3]:
  - Fixed fegetround bug on powerpc64 (big endian) that Segher
spotted;

Changes since v2[2]:
  - Added documentation for the new optabs;
  - Remove use of non portable __builtin_clz;
  - Changed feclearexcept and feraiseexcept to accept all 4 valid
flags at the same time and added more test for that case;
  - Extended feclearexcept and feraiseexcept testcases to match
accepting multiple flags;
  - Fixed builtin-feclearexcept-feraiseexcept-2.c testcase comparison
after feclearexcept tests;
  - Updated commit message to reflect change in feclearexcept and
feraiseexcept from the glibc counterpart;
  - Fixed English spelling and typos;
  - Fixed code-style;
  - Changed subject line tag to make clear it is not just rs6000 code.

Changes since v1[1]:
  - Fixed English spelling;
  - Fixed code-style;
  - Changed match operand predicate in feclearexcept and feraiseexcept;
  - Changed testcase options;
  - Minor changes in test code to be C90 compatible;
  - Other minor changes suggested by Segher;
  - Changed subject line tag (not sure if I tagged correctly or should
include optabs: also)

[1] https://gcc.gnu.org/pipermail/gcc-patches/2020-August/552024.html
[2] https://gcc.gnu.org/pipermail/gcc-patches/2020-September/553297.html
[3] https://gcc.gnu.org/pipermail/gcc-patches/2020-October/557109.html
[4] https://gcc.gnu.org/pipermail/gcc-patches/2020-October/557349.html
[5] https://gcc.gnu.org/pipermail/gcc-patches/2020-November/557984.html
[6] https://gcc.gnu.org/pipermail/gcc-patches/2021-October/581837.html
[7] https://gcc.gnu.org/pipermail/gcc-patches/2021-November/585375.html

 8< 

This optimizations were originally in glibc, but was removed
and suggested that they were a good fit as gcc builtins[1].

feclearexcept and feraiseexcept were extended (in comparison to the
glibc version) to accept any combination of the accepted flags, not
limited to just one flag bit at a time anymore.

The builtin expanders needs knowledge of the target libc's FE_*
values, so they are limited to expand only to suitable libcs.