RE: [patch][x86] Split-up march icelake on march=icelake-server and march=icelake-client
Small fix. gcc/ * config.gcc (icelake-client, icelake-server): New. (icelake): Remove. * config/i386/i386.c (initial_ix86_tune_features): Extend to 64 bit. (initial_ix86_arch_features): Ditto. (PTA_SKYLAKE): Add SGX. (PTA_ICELAKE): Remove. (PTA_ICELAKE_CLIENT): New. (PTA_ICELAKE_SERVER): New. (ix86_option_override_internal): Split up icelake on icelake client and icelake server. (get_builtin_code_for_version): Ditto. (fold_builtin_cpu): Ditto. * config/i386/driver-i386.c (config/i386/driver-i386.c): Ditto. * config/i386/i386-c.c (ix86_target_macros_internal): Ditto * config/i386/i386.h (processor_type) Ditto. * doc/invoke.texi: Ditto. gcc/testsuite/ * g++.dg/ext/mv16.C: Split up icelake on icelake client and icelake-server. * gcc.target/i386/funcspec-56.inc: Ditto. libgcc/ * config/i386/cpuinfo.h (processor_subtypes): Split up icelake on icelake client and icelake-server. Thanks, Julia > -Original Message- > From: Koval, Julia > Sent: Tuesday, March 13, 2018 8:42 AM > To: Joseph Myers > Cc: 'GCC Patches' ; Uros Bizjak > > Subject: RE: [patch][x86] Split-up march icelake on march=icelake-server and > march=icelake-client > > Fixed invoke.texi. Here is the new version. > > gcc/ > * config.gcc (icelake-client, icelake-server): New. > (icelake): Remove. > * config/i386/i386.c (initial_ix86_tune_features): Extend to 64 bit. > (initial_ix86_arch_features): Ditto. > (ix86_option_override_internal): Split up icelake on icelake client and > icelake server. > (get_builtin_code_for_version): Ditto. > (fold_builtin_cpu): Ditto. > * config/i386/driver-i386.c (config/i386/driver-i386.c): Ditto. > * config/i386/i386-c.c (ix86_target_macros_internal): Ditto > * config/i386/i386.h (processor_type) Ditto. > * doc/invoke.texi: Ditto. > > gcc/testsuite/ > * g++.dg/ext/mv16.C: Split up icelake on icelake client and > icelake-server. > * gcc.target/i386/funcspec-56.inc: Ditto. > > libgcc/ > * config/i386/cpuinfo.h (processor_subtypes): Split up icelake on > icelake > client and icelake-server. > > Thanks, > Julia > > > -Original Message- > > From: Joseph Myers [mailto:jos...@codesourcery.com] > > Sent: Monday, March 12, 2018 10:21 PM > > To: Koval, Julia > > Cc: 'GCC Patches' ; Uros Bizjak > > > > Subject: Re: [patch][x86] Split-up march icelake on march=icelake-server and > > march=icelake-client > > > > On Mon, 12 Mar 2018, Koval, Julia wrote: > > > > > Hi, > > > This patch introduces separate client and server arch options instead of > > > -march=icelake. Ok for trunk? > > > > I don't see any invoke.texi updates here to document what these two > > options mean (including, presumably, different lists of features for > > them). > > > > -- > > Joseph S. Myers > > jos...@codesourcery.com 0001-icelake-client.patch Description: 0001-icelake-client.patch
RE: [x86,avx] Fix __builtin_cpu_supports for icelake and cannonlake isa
Gentle ping. > -Original Message- > From: Koval, Julia > Sent: Monday, February 12, 2018 10:57 AM > To: Kirill Yukhin > Cc: 'GCC Patches' > Subject: RE: [x86,avx] Fix __builtin_cpu_supports for icelake and cannonlake > isa > > Hi, > > There is no PR for this. This builtin was just missing for all new cpus. > > Thanks, > Julia > > > -Original Message- > > From: Kirill Yukhin [mailto:kirill.yuk...@gmail.com] > > Sent: Monday, February 12, 2018 7:19 AM > > To: Koval, Julia > > Cc: 'GCC Patches' > > Subject: Re: [x86,avx] Fix __builtin_cpu_supports for icelake and cannonlake > isa > > > > Hello Julia. > > > > On 15 Jan 08:28, Koval, Julia wrote: > > > Hi, > > > This patch fixes subj. Ok for trunk? > > > > > > gcc/ > > > * config/i386/i386.c (F_AVX512VBMI2, F_GFNI, F_VPCLMULQDQ, > > F_AVX512VNNI, > > > F_AVX512BITALG): New. > > > > > > gcc/testsuite/ > > > * gcc.target/i386/builtin_target.c (check_intel_cpu_model): Add > > cannonlake. > > > (check_features): Add avx512vbmi2, gfni, vpclmulqdq, avx512vnni, > > > avx512bitalg. > > > > > > libgcc/ > > > * config/i386/cpuinfo.c (get_available_features): Add > > FEATURE_AVX512VBMI2, > > > FEATURE_GFNI, FEATURE_VPCLMULQDQ, FEATURE_AVX512VNNI, > > FEATURE_AVX512BITALG. > > > * config/i386/cpuinfo.h (processor_features) Add > > FEATURE_AVX512VBMI2, > > > FEATURE_GFNI, FEATURE_VPCLMULQDQ, FEATURE_AVX512VNNI, > > FEATURE_AVX512BITALG. > > > > Could you pls mention, which problem does your patch fix? > > > > -- > > Thanks, K
Re: [PR84682] disregard address constraints on non-addresses
On Mar 12, 2018, "Bin.Cheng" wrote: > internal compiler error: in aarch64_classify_address, at > config/aarch64/aarch64.c:5678 > 0xfe3c29 aarch64_classify_address > /.../build/src/gcc/gcc/config/aarch64/aarch64.c:5677 > 0xfe8be8 aarch64_legitimate_address_hook_p > /.../build/src/gcc/gcc/config/aarch64/aarch64.c:5958 > 0xc0149e default_addr_space_legitimate_address_p(machine_mode, > rtx_def*, bool, unsigned char) > /.../build/src/gcc/gcc/targhooks.c:1476 > 0xb5b9f1 memory_address_addr_space_p(machine_mode, rtx_def*, unsigned char) > /.../build/src/gcc/gcc/recog.c:1334 > 0xb5d278 address_operand(rtx_def*, machine_mode) > /.../build/src/gcc/gcc/recog.c:1073 > 0xb5e186 asm_operand_ok(rtx_def*, char const*, char const**) > /.../build/src/gcc/gcc/recog.c:1816 > 0x73f440 expand_asm_stmt > /.../build/src/gcc/gcc/cfgexpand.c:3138 > 0x742d3c expand_gimple_stmt_1 > /.../build/src/gcc/gcc/cfgexpand.c:3621 > Not sure if it reveals latent bug or just inconsistent issue with > backend though. Possibly both, in a way. This triggers at expand, which is much earlier than the patch affects compilation; that call to address_operand was already there before. So the ICE was latent, but only in the sense that we didn't have tests that would have triggered it. Any asm stmt with a p constraint and a non-address operand (with another constraint to accept it) would have exercised this aarch64-specific ICE, and it would do so before hitting the machine-independent ICE that the patch fixed. aarch64_classify_address should probably return false instead of failing that assertion. When it comes to asm operands, there's no guarantee that you'll get something that even looks like an address, when you're part of the very code that's supposed to tell the rest of the compiler what a legitimate address should look like. -- Alexandre Oliva, freedom fighterhttp://FSFLA.org/~lxoliva/ You must be the change you wish to see in the world. -- Gandhi Be Free! -- http://FSFLA.org/ FSF Latin America board member Free Software Evangelist|Red Hat Brasil GNU Toolchain Engineer
Re: [AArch64] Add SVE mul_highpart patterns
On 8 February 2018 at 14:54, Richard Sandiford
wrote:
> One advantage of the new permute handling compared to the old way is
> that we can now easily take advantage of the vectoriser's divmod patterns
> for SVE.
>
> I realise we're in stage 4, but this is entirely SVE-specific.
>
> Tested on aarch64-linux-gnu and aarch64_be-elf. OK to install?
>
> Richard
>
Hi Richard,
>
> 2018-02-08 Richard Sandiford
>
> gcc/
> * config/aarch64/iterators.md (UNSPEC_SMUL_HIGHPART)
> (UNSPEC_UMUL_HIGHPART): New constants.
> (MUL_HIGHPART): New int iteraor.
> (su): Handle UNSPEC_SMUL_HIGHPART and UNSPEC_UMUL_HIGHPART.
> * config/aarch64/aarch64-sve.md (mul3_highpart): New
> define_expand.
> (*mul3_highpart): New define_insn.
>
> gcc/testsuite/
> * gcc.target/aarch64/sve/mul_highpart_1.c: New test.
> * gcc.target/aarch64/sve/mul_highpart_1_run.c: Likewise.
>
> Index: gcc/config/aarch64/iterators.md
> ===
> --- gcc/config/aarch64/iterators.md 2018-01-26 15:14:35.386171048 +
> +++ gcc/config/aarch64/iterators.md 2018-02-08 13:51:56.252511923 +
> @@ -438,6 +438,8 @@ (define_c_enum "unspec"
> UNSPEC_ANDF; Used in aarch64-sve.md.
> UNSPEC_IORF; Used in aarch64-sve.md.
> UNSPEC_XORF; Used in aarch64-sve.md.
> +UNSPEC_SMUL_HIGHPART ; Used in aarch64-sve.md.
> +UNSPEC_UMUL_HIGHPART ; Used in aarch64-sve.md.
> UNSPEC_COND_ADD; Used in aarch64-sve.md.
> UNSPEC_COND_SUB; Used in aarch64-sve.md.
> UNSPEC_COND_SMAX ; Used in aarch64-sve.md.
> @@ -1467,6 +1469,8 @@ (define_int_iterator UNPACK [UNSPEC_UNPA
>
> (define_int_iterator UNPACK_UNSIGNED [UNSPEC_UNPACKULO UNSPEC_UNPACKUHI])
>
> +(define_int_iterator MUL_HIGHPART [UNSPEC_SMUL_HIGHPART
> UNSPEC_UMUL_HIGHPART])
> +
> (define_int_iterator SVE_COND_INT_OP [UNSPEC_COND_ADD UNSPEC_COND_SUB
> UNSPEC_COND_SMAX UNSPEC_COND_UMAX
> UNSPEC_COND_SMIN UNSPEC_COND_UMIN
> @@ -1558,7 +1562,9 @@ (define_int_attr logicalf_op [(UNSPEC_AN
> (define_int_attr su [(UNSPEC_UNPACKSHI "s")
> (UNSPEC_UNPACKUHI "u")
> (UNSPEC_UNPACKSLO "s")
> -(UNSPEC_UNPACKULO "u")])
> +(UNSPEC_UNPACKULO "u")
> +(UNSPEC_SMUL_HIGHPART "s")
> +(UNSPEC_UMUL_HIGHPART "u")])
>
> (define_int_attr sur [(UNSPEC_SHADD "s") (UNSPEC_UHADD "u")
> (UNSPEC_SRHADD "sr") (UNSPEC_URHADD "ur")
> Index: gcc/config/aarch64/aarch64-sve.md
> ===
> --- gcc/config/aarch64/aarch64-sve.md 2018-02-01 11:04:16.723192040 +
> +++ gcc/config/aarch64/aarch64-sve.md 2018-02-08 13:51:56.252511923 +
> @@ -980,6 +980,34 @@ (define_insn "*msub3"
> mls\t%0., %1/m, %2., %3."
> )
>
> +;; Unpredicated highpart multiplication.
> +(define_expand "mul3_highpart"
> + [(set (match_operand:SVE_I 0 "register_operand")
> + (unspec:SVE_I
> + [(match_dup 3)
> + (unspec:SVE_I [(match_operand:SVE_I 1 "register_operand")
> + (match_operand:SVE_I 2 "register_operand")]
> +MUL_HIGHPART)]
> + UNSPEC_MERGE_PTRUE))]
> + "TARGET_SVE"
> + {
> +operands[3] = force_reg (mode, CONSTM1_RTX (mode));
> + }
> +)
> +
> +;; Predicated highpart multiplication.
> +(define_insn "*mul3_highpart"
> + [(set (match_operand:SVE_I 0 "register_operand" "=w")
> + (unspec:SVE_I
> + [(match_operand: 1 "register_operand" "Upl")
> + (unspec:SVE_I [(match_operand:SVE_I 2 "register_operand" "%0")
> + (match_operand:SVE_I 3 "register_operand" "w")]
> +MUL_HIGHPART)]
> + UNSPEC_MERGE_PTRUE))]
> + "TARGET_SVE"
> + "mulh\t%0., %1/m, %0., %3."
> +)
> +
> ;; Unpredicated NEG, NOT and POPCOUNT.
> (define_expand "2"
>[(set (match_operand:SVE_I 0 "register_operand")
> Index: gcc/testsuite/gcc.target/aarch64/sve/mul_highpart_1.c
> ===
> --- /dev/null 2018-02-08 11:17:10.862716283 +
> +++ gcc/testsuite/gcc.target/aarch64/sve/mul_highpart_1.c 2018-02-08
> 13:51:56.252511923 +
> @@ -0,0 +1,25 @@
> +/* { dg-do assemble { target aarch64_asm_sve_ok } } */
> +/* { dg-options "-O2 -ftree-vectorize -fno-vect-cost-model --save-temps" } */
> +
> +#include
> +
> +#define DEF_LOOP(TYPE) \
> +void __attribute__ ((noipa)) \
> +mod_##TYPE (TYPE *dst, TYPE *src, int count) \
> +{ \
> + for (int i = 0; i < count; ++i) \
> +dst[i] = src[i] % 17; \
> +}
> +
> +#define TEST_ALL(T) \
> + T (int32_t) \
> + T (uint32
Re: [PATCH] Fix -march=bdver1 ICE on int to float conversion (PR target/84844)
On Tue, Mar 13, 2018 at 9:30 PM, Jakub Jelinek wrote:
> Hi!
>
> As mentioned in bugzilla, when e.g. sel-sched queries (indirectly) before
> reload
> some attributes like get_attr_type that depend on alternatives, GCC attempts
> to constrain the operands in non-strict mode, which implies that if
> reg_class_for_constraint doesn't return NO_REGS, it is ok, otherwise the
> constraint needs to match (the actual code is more complex of course).
> The *float2_mixed pattern has different type
> attributes between different alternatives, uses nonimmediate_operand for the
> input and uses "m" constraint for it in all but one alternative; in that
> alternative it has "r" constraint for the input and "Yc" for output, which
> depending on tuning is either same as "v" or NO_REGS. So, on those tunings
> even in non-strict mode, if the input is a REG we fail to constrain the insn
> and ICE.
>
> The following patch fixes it by reverting the offending patch (as asked in
> the PR), even with the patch reverted the reported issue doesn't reproduce
> and in theory there is nothing wrong on emitting direct conversions even in
> these tunings in cold blocks, the hw supports it, just it is slow, but also
> smaller.
>
> Bootstrapped/regtested on x86_64-linux and i686-linux, ok for trunk?
>
> As mentioned in the PR, another alternative that works is adding another
> alternative next to that Yc <- r, e.g. !???*v <- r, which will allow the
> pre-reload attribute queries, but will very likely not be used otherwise.
>
> 2018-03-13 Jakub Jelinek
>
> PR target/84844
> Revert
> 2017-04-20 Uros Bizjak
>
> PR target/78090
> * config/i386/constraints.md (Yc): New register constraint.
> * config/i386/i386.md (*float2_mixed):
> Use Yc constraint for alternative 2 of operand 0. Remove
> preferred_for_speed attribute.
>
> * gcc.target/i386/pr84844.c: New test.
OK.
Perhaps some time in future, we should change all these inter-unit
constraints to use preferred_for_speed attribute. As with the attached
patch, these insn are not invalid instructions, so we can emit them in
certain cases (-Os), even for AMD targets. Conditional register
constraints made sense were
--- gcc/config/i386/constraints.md.jj 2018-02-26 20:49:57.299331387 +0100
> +++ gcc/config/i386/constraints.md 2018-03-13 13:47:22.285093035 +0100
> @@ -99,7 +99,6 @@ (define_register_constraint "w" "TARGET_
>
> ;; We use the Y prefix to denote any number of conditional register sets:
> ;; z First SSE register.
> -;; c SSE inter-unit conversions enabled
> ;; i SSE2 inter-unit moves to SSE register enabled
> ;; j SSE2 inter-unit moves from SSE register enabled
> ;; d any EVEX encodable SSE register for AVX512BW target or any SSE
> register
> @@ -124,10 +123,6 @@ (define_register_constraint "w" "TARGET_
> (define_register_constraint "Yz" "TARGET_SSE ? SSE_FIRST_REG : NO_REGS"
> "First SSE register (@code{%xmm0}).")
>
> -(define_register_constraint "Yc"
> - "TARGET_SSE && TARGET_INTER_UNIT_CONVERSIONS ? ALL_SSE_REGS : NO_REGS"
> - "@internal Any SSE register, when SSE and inter-unit conversions are
> enabled.")
> -
> (define_register_constraint "Yi"
> "TARGET_SSE2 && TARGET_INTER_UNIT_MOVES_TO_VEC ? ALL_SSE_REGS : NO_REGS"
> "@internal Any SSE register, when SSE2 and inter-unit moves to vector
> registers are enabled.")
> --- gcc/config/i386/i386.md.jj 2018-03-13 13:40:44.082903460 +0100
> +++ gcc/config/i386/i386.md 2018-03-13 13:47:22.284093034 +0100
> @@ -5325,7 +5325,7 @@ (define_expand "float })
>
> (define_insn "*float2_mixed"
> - [(set (match_operand:MODEF 0 "register_operand" "=f,Yc,v")
> + [(set (match_operand:MODEF 0 "register_operand" "=f,v,v")
> (float:MODEF
> (match_operand:SWI48 1 "nonimmediate_operand" "m,r,m")))]
>"SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH"
> @@ -5354,6 +5354,10 @@ (define_insn "*float && X87_ENABLE_FLOAT (mode,
> mode)")
> ]
> + (symbol_ref "true")))
> + (set (attr "preferred_for_speed")
> + (cond [(eq_attr "alternative" "1")
> + (symbol_ref "TARGET_INTER_UNIT_CONVERSIONS")]
> (symbol_ref "true")))])
>
> (define_insn "*float2_i387"
> --- gcc/testsuite/gcc.target/i386/pr84844.c.jj 2018-03-13 13:12:50.569130703
> +0100
> +++ gcc/testsuite/gcc.target/i386/pr84844.c 2018-03-13 12:21:04.553643164
> +0100
> @@ -0,0 +1,10 @@
> +/* PR target/84844 */
> +/* { dg-do compile } */
> +/* { dg-options "-march=bdver1 -O2 -fschedule-insns -fselective-scheduling"
> } */
> +
> +double
> +foo (int *x, int y, int z)
> +{
> + *x = y;
> + return z;
> +}
>
> Jakub
Re: [PATCH] Fix -march=bdver1 ICE on int to float conversion (PR target/84844)
On Wed, Mar 14, 2018 at 9:36 AM, Uros Bizjak wrote:
> On Tue, Mar 13, 2018 at 9:30 PM, Jakub Jelinek wrote:
>> Hi!
>>
>> As mentioned in bugzilla, when e.g. sel-sched queries (indirectly) before
>> reload
>> some attributes like get_attr_type that depend on alternatives, GCC attempts
>> to constrain the operands in non-strict mode, which implies that if
>> reg_class_for_constraint doesn't return NO_REGS, it is ok, otherwise the
>> constraint needs to match (the actual code is more complex of course).
>> The *float2_mixed pattern has different type
>> attributes between different alternatives, uses nonimmediate_operand for the
>> input and uses "m" constraint for it in all but one alternative; in that
>> alternative it has "r" constraint for the input and "Yc" for output, which
>> depending on tuning is either same as "v" or NO_REGS. So, on those tunings
>> even in non-strict mode, if the input is a REG we fail to constrain the insn
>> and ICE.
>>
>> The following patch fixes it by reverting the offending patch (as asked in
>> the PR), even with the patch reverted the reported issue doesn't reproduce
>> and in theory there is nothing wrong on emitting direct conversions even in
>> these tunings in cold blocks, the hw supports it, just it is slow, but also
>> smaller.
>>
>> Bootstrapped/regtested on x86_64-linux and i686-linux, ok for trunk?
>>
>> As mentioned in the PR, another alternative that works is adding another
>> alternative next to that Yc <- r, e.g. !???*v <- r, which will allow the
>> pre-reload attribute queries, but will very likely not be used otherwise.
>>
>> 2018-03-13 Jakub Jelinek
>>
>> PR target/84844
>> Revert
>> 2017-04-20 Uros Bizjak
>>
>> PR target/78090
>> * config/i386/constraints.md (Yc): New register constraint.
>> * config/i386/i386.md (*float2_mixed):
>> Use Yc constraint for alternative 2 of operand 0. Remove
>> preferred_for_speed attribute.
>>
>> * gcc.target/i386/pr84844.c: New test.
>
> OK.
>
> Perhaps some time in future, we should change all these inter-unit
> constraints to use preferred_for_speed attribute. As with the attached
> patch, these insn are not invalid instructions, so we can emit them in
> certain cases (-Os), even for AMD targets. Conditional register
> constraints made sense ...
... before preferred_for_... infrastructure was developed.
Uros.
>
> --- gcc/config/i386/constraints.md.jj 2018-02-26 20:49:57.299331387 +0100
>> +++ gcc/config/i386/constraints.md 2018-03-13 13:47:22.285093035 +0100
>> @@ -99,7 +99,6 @@ (define_register_constraint "w" "TARGET_
>>
>> ;; We use the Y prefix to denote any number of conditional register sets:
>> ;; z First SSE register.
>> -;; c SSE inter-unit conversions enabled
>> ;; i SSE2 inter-unit moves to SSE register enabled
>> ;; j SSE2 inter-unit moves from SSE register enabled
>> ;; d any EVEX encodable SSE register for AVX512BW target or any SSE
>> register
>> @@ -124,10 +123,6 @@ (define_register_constraint "w" "TARGET_
>> (define_register_constraint "Yz" "TARGET_SSE ? SSE_FIRST_REG : NO_REGS"
>> "First SSE register (@code{%xmm0}).")
>>
>> -(define_register_constraint "Yc"
>> - "TARGET_SSE && TARGET_INTER_UNIT_CONVERSIONS ? ALL_SSE_REGS : NO_REGS"
>> - "@internal Any SSE register, when SSE and inter-unit conversions are
>> enabled.")
>> -
>> (define_register_constraint "Yi"
>> "TARGET_SSE2 && TARGET_INTER_UNIT_MOVES_TO_VEC ? ALL_SSE_REGS : NO_REGS"
>> "@internal Any SSE register, when SSE2 and inter-unit moves to vector
>> registers are enabled.")
>> --- gcc/config/i386/i386.md.jj 2018-03-13 13:40:44.082903460 +0100
>> +++ gcc/config/i386/i386.md 2018-03-13 13:47:22.284093034 +0100
>> @@ -5325,7 +5325,7 @@ (define_expand "float> })
>>
>> (define_insn "*float2_mixed"
>> - [(set (match_operand:MODEF 0 "register_operand" "=f,Yc,v")
>> + [(set (match_operand:MODEF 0 "register_operand" "=f,v,v")
>> (float:MODEF
>> (match_operand:SWI48 1 "nonimmediate_operand" "m,r,m")))]
>>"SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH"
>> @@ -5354,6 +5354,10 @@ (define_insn "*float> && X87_ENABLE_FLOAT (mode,
>> mode)")
>> ]
>> + (symbol_ref "true")))
>> + (set (attr "preferred_for_speed")
>> + (cond [(eq_attr "alternative" "1")
>> + (symbol_ref "TARGET_INTER_UNIT_CONVERSIONS")]
>> (symbol_ref "true")))])
>>
>> (define_insn "*float2_i387"
>> --- gcc/testsuite/gcc.target/i386/pr84844.c.jj 2018-03-13
>> 13:12:50.569130703 +0100
>> +++ gcc/testsuite/gcc.target/i386/pr84844.c 2018-03-13
>> 12:21:04.553643164 +0100
>> @@ -0,0 +1,10 @@
>> +/* PR target/84844 */
>> +/* { dg-do compile } */
>> +/* { dg-options "-march=bdver1 -O2 -fschedule-insns -fselective-scheduling"
>> } */
>> +
>> +double
>> +foo (int *x, int y, int z)
>> +{
>> + *x = y;
>> + return z;
>> +}
>>
>>
[AARCH64 PATCH] Fix shift+rotate patterns with masking (PR target/84845)
Hi!
The following testcase ICEs on aarch64-linux, because combiner matches the
(insn 25 24 26 2 (set (reg:DI 114)
(rotatert:DI (reg:DI 115 [ d ])
(subreg:QI (neg:SI (and:SI (reg:SI 112)
(const_int 65535 [0x]))) 0))) "pr84845.c":8 664
{*aarch64_reg_di3_neg_mask2}
(expr_list:REG_DEAD (reg:SI 112)
(expr_list:REG_DEAD (reg:DI 115 [ d ])
(nil
pattern, but what we split it into doesn't recog, because there are just
patterns that use the same mode for the shift/rotate as for AND and use
proper
(match_operand 3 "const_int_operand" "n"))])))]
"(~INTVAL (operands[3]) & (GET_MODE_BITSIZE (mode) - 1)) == 0"
and then there is another pattern for the mixed DImode shift/rotate and
SImode mask, but that one uses for the mask instead
(match_operand 3 "aarch64_shift_imm_di" "Usd"))])))]
"((~INTVAL (operands[3]) & (GET_MODE_BITSIZE (DImode)-1)) == 0)"
which due to the predicate (and constraint) never matches.
The following patch fixes that bug (uses "const_int_operand" "n" like in
similar patterns), also fixes another bug in the *aarch64_reg_3_neg_mask2
splitter, where if it isn't split before reload it would emit invalid
negation (SImode negation from SImode input into DImode output).
And the last change is that I find these patterns to be misnamed, the most
important on these patterns is that they are shifts/rotates, but the names
of the pattern don't indicate that at all; some other patterns around do
indicate that with _ part, which the patch changes them to, and
one pattern has that part in inconsistent spot to the others.
Bootstrapped/regtested on aarch64-linux, ok for trunk?
2018-03-14 Jakub Jelinek
PR target/84845
* config/aarch64/aarch64.md (*aarch64_reg_3_neg_mask2): Rename
to ...
(*aarch64__reg_3_neg_mask2): ... this. If pseudos can't
be created, use lowpart_subreg of operands[0] rather than operands[0]
itself.
(*aarch64_reg_3_minus_mask): Rename to ...
(*aarch64_ashl_reg_3_minus_mask): ... this.
(*aarch64__reg_di3_mask2): Use const_int_operand predicate
and n constraint instead of aarch64_shift_imm_di and Usd.
(*aarch64_reg__minus3): Rename to ...
(*aarch64__reg_minus3): ... this.
* gcc.c-torture/compile/pr84845.c: New test.
--- gcc/config/aarch64/aarch64.md.jj2018-03-13 00:38:26.0 +0100
+++ gcc/config/aarch64/aarch64.md 2018-03-13 18:33:47.657719021 +0100
@@ -4262,7 +4262,7 @@ (define_insn "*aarch64__reg_3_neg_mask2"
+(define_insn_and_split "*aarch64__reg_3_neg_mask2"
[(set (match_operand:GPI 0 "register_operand" "=&r")
(SHIFT:GPI
(match_operand:GPI 1 "register_operand" "r")
@@ -4275,7 +4275,7 @@ (define_insn_and_split "*aarch64_reg_mode));
emit_insn (gen_negsi2 (tmp, operands[2]));
rtx and_op = gen_rtx_AND (SImode, tmp, operands[3]);
@@ -4286,7 +4286,7 @@ (define_insn_and_split "*aarch64_reg_3_minus_mask"
+(define_insn_and_split "*aarch64_ashl_reg_3_minus_mask"
[(set (match_operand:GPI 0 "register_operand" "=&r")
(ashift:GPI
(match_operand:GPI 1 "register_operand" "r")
@@ -4320,8 +4320,8 @@ (define_insn "*aarch64__reg_di3_m
(match_operand:DI 1 "register_operand" "r")
(match_operator 4 "subreg_lowpart_operator"
[(and:SI (match_operand:SI 2 "register_operand" "r")
-(match_operand 3 "aarch64_shift_imm_di" "Usd"))])))]
- "((~INTVAL (operands[3]) & (GET_MODE_BITSIZE (DImode)-1)) == 0)"
+ (match_operand 3 "const_int_operand" "n"))])))]
+ "((~INTVAL (operands[3]) & (GET_MODE_BITSIZE (DImode) - 1)) == 0)"
{
rtx xop[3];
xop[0] = operands[0];
@@ -4333,7 +4333,7 @@ (define_insn "*aarch64__reg_di3_m
[(set_attr "type" "shift_reg")]
)
-(define_insn_and_split "*aarch64_reg__minus3"
+(define_insn_and_split "*aarch64__reg_minus3"
[(set (match_operand:GPI 0 "register_operand" "=&r")
(ASHIFT:GPI
(match_operand:GPI 1 "register_operand" "r")
--- gcc/testsuite/gcc.c-torture/compile/pr84845.c.jj2018-03-13
18:42:46.841004726 +0100
+++ gcc/testsuite/gcc.c-torture/compile/pr84845.c 2018-03-13
18:42:16.491988632 +0100
@@ -0,0 +1,12 @@
+/* PR target/84845 */
+
+int a, b, c;
+unsigned long d;
+
+void
+foo (void)
+{
+ b = -1;
+ b <<= c >= 0;
+ d = d << (63 & (short)-b) | d >> (63 & -(short)-b);
+}
Jakub
Re: [PATCH] Fix ptr-overflow sanopt optimization (PR sanitizer/83392)
On Tue, 13 Mar 2018, Jakub Jelinek wrote:
> Hi!
>
> The sanopt maybe_optimize_ubsan_ptr_ifn optimization behaves differently
> on 32-bit and on 64-bit targets when using similar arguments maximum or
> minimum of ptrdiff_t or values close to it.
>
> The problem is that UHWI is 64-bit, regardless of whether addresses are
> 64-bit or 32-bit, so for 32-bit targets get_inner_reference returns
> NULL offset and all the offset is in pbitpos, while on 64-bit targets
> where such large offsets in bytes would fit into shwi, but in bits won't
> fit, we return INTEGER_CST offset and often 0 pbitpos.
>
> The following patch handles such offset, so that the sanopt behaves the
> same way, and adjusts the testcase (which really should have just 14
> matches, the 3 lines with comment changes are already covered by the
> overflow check on p = b - SMAX;).
>
> Bootstrapped/regtested on x86_64-linux and i686-linux, ok for trunk?
OK.
Thanks,
Richard.
> 2018-03-13 Jakub Jelinek
>
> PR sanitizer/83392
> * sanopt.c (maybe_optimize_ubsan_ptr_ifn): Handle also
> INTEGER_CST offset, add it together with bitpos / 8 and
> sign extend based on POINTER_SIZE.
>
> * c-c++-common/ubsan/ptr-overflow-sanitization-1.c: Adjust expected
> check count from 17 to 14.
>
> --- gcc/sanopt.c.jj 2018-03-02 00:15:54.670780980 +0100
> +++ gcc/sanopt.c 2018-03-13 16:54:49.905621373 +0100
> @@ -486,12 +486,17 @@ maybe_optimize_ubsan_ptr_ifn (sanopt_ctx
>HOST_WIDE_INT bitpos;
>base = get_inner_reference (base, &bitsize, &pbitpos, &offset, &mode,
> &unsignedp, &reversep, &volatilep);
> - if (offset == NULL_TREE
> + if ((offset == NULL_TREE || TREE_CODE (offset) == INTEGER_CST)
> && DECL_P (base)
> && pbitpos.is_constant (&bitpos))
> {
> gcc_assert (!DECL_REGISTER (base));
> - offset_int expr_offset = bitpos / BITS_PER_UNIT;
> + offset_int expr_offset;
> + if (offset)
> + expr_offset = wi::to_offset (offset) + bitpos / BITS_PER_UNIT;
> + else
> + expr_offset = bitpos / BITS_PER_UNIT;
> + expr_offset = wi::sext (expr_offset, POINTER_SIZE);
> offset_int total_offset = expr_offset + cur_offset;
> if (total_offset != wi::sext (total_offset, POINTER_SIZE))
> {
> @@ -511,7 +516,7 @@ maybe_optimize_ubsan_ptr_ifn (sanopt_ctx
> && (!is_global_var (base) || decl_binds_to_current_def_p (base)))
> {
> offset_int base_size = wi::to_offset (DECL_SIZE_UNIT (base));
> - if (bitpos >= 0
> + if (!wi::neg_p (expr_offset)
> && wi::les_p (total_offset, base_size))
> {
> if (!wi::neg_p (total_offset)
> @@ -532,7 +537,7 @@ maybe_optimize_ubsan_ptr_ifn (sanopt_ctx
>*/
>
> bool sign_cur_offset = !wi::neg_p (cur_offset);
> - bool sign_expr_offset = bitpos >= 0;
> + bool sign_expr_offset = !wi::neg_p (expr_offset);
>
> tree base_addr
> = build1 (ADDR_EXPR, build_pointer_type (TREE_TYPE (base)), base);
> --- gcc/testsuite/c-c++-common/ubsan/ptr-overflow-sanitization-1.c.jj
> 2017-10-11 22:37:52.798901780 +0200
> +++ gcc/testsuite/c-c++-common/ubsan/ptr-overflow-sanitization-1.c
> 2018-03-13 17:00:18.947808006 +0100
> @@ -25,9 +25,9 @@ void foo(void)
>p2 = p + 2;
>
>p = b - SMAX; /* pointer overflow check is needed */
> - p2 = p + (SMAX - 2); /* b - 2: pointer overflow check is needed */
> - p2 = p + (SMAX - 1); /* b - 1: pointer overflow check is needed */
> - p2 = p + SMAX; /* b: pointer overflow check is needed */
> + p2 = p + (SMAX - 2); /* b - 2: no need to check this */
> + p2 = p + (SMAX - 1); /* b - 1: no need to check this */
> + p2 = p + SMAX; /* b: no need to check this */
>p2++; /* b + 1 */
>
>p = c;
> @@ -75,4 +75,4 @@ void negative_to_negative (char *ptr)
>p2 += 5;
> }
>
> -/* { dg-final { scan-tree-dump-times "__ubsan_handle_pointer_overflow" 17
> "optimized" } } */
> +/* { dg-final { scan-tree-dump-times "__ubsan_handle_pointer_overflow" 14
> "optimized" } } */
>
> Jakub
>
>
--
Richard Biener
SUSE LINUX GmbH, GF: Felix Imendoerffer, Jane Smithard, Graham Norton, HRB
21284 (AG Nuernberg)
Re: [patch][x86] Split-up march icelake on march=icelake-server and march=icelake-client
On Wed, Mar 14, 2018 at 8:44 AM, Koval, Julia wrote: > Small fix. > > gcc/ > * config.gcc (icelake-client, icelake-server): New. > (icelake): Remove. > * config/i386/i386.c (initial_ix86_tune_features): Extend to 64 bit. > (initial_ix86_arch_features): Ditto. > (PTA_SKYLAKE): Add SGX. > (PTA_ICELAKE): Remove. > (PTA_ICELAKE_CLIENT): New. > (PTA_ICELAKE_SERVER): New. > (ix86_option_override_internal): Split up icelake on icelake client > and > icelake server. > (get_builtin_code_for_version): Ditto. > (fold_builtin_cpu): Ditto. > * config/i386/driver-i386.c (config/i386/driver-i386.c): Ditto. > * config/i386/i386-c.c (ix86_target_macros_internal): Ditto > * config/i386/i386.h (processor_type) Ditto. > * doc/invoke.texi: Ditto. > > gcc/testsuite/ > * g++.dg/ext/mv16.C: Split up icelake on icelake client and > icelake-server. > * gcc.target/i386/funcspec-56.inc: Ditto. > > libgcc/ > * config/i386/cpuinfo.h (processor_subtypes): Split up icelake on > icelake > client and icelake-server. OK. Thanks, Uros. > Thanks, > Julia > >> -Original Message- >> From: Koval, Julia >> Sent: Tuesday, March 13, 2018 8:42 AM >> To: Joseph Myers >> Cc: 'GCC Patches' ; Uros Bizjak >> >> Subject: RE: [patch][x86] Split-up march icelake on march=icelake-server and >> march=icelake-client >> >> Fixed invoke.texi. Here is the new version. >> >> gcc/ >> * config.gcc (icelake-client, icelake-server): New. >> (icelake): Remove. >> * config/i386/i386.c (initial_ix86_tune_features): Extend to 64 bit. >> (initial_ix86_arch_features): Ditto. >> (ix86_option_override_internal): Split up icelake on icelake client and >> icelake server. >> (get_builtin_code_for_version): Ditto. >> (fold_builtin_cpu): Ditto. >> * config/i386/driver-i386.c (config/i386/driver-i386.c): Ditto. >> * config/i386/i386-c.c (ix86_target_macros_internal): Ditto >> * config/i386/i386.h (processor_type) Ditto. >> * doc/invoke.texi: Ditto. >> >> gcc/testsuite/ >> * g++.dg/ext/mv16.C: Split up icelake on icelake client and >> icelake-server. >> * gcc.target/i386/funcspec-56.inc: Ditto. >> >> libgcc/ >> * config/i386/cpuinfo.h (processor_subtypes): Split up icelake on >> icelake >> client and icelake-server. >> >> Thanks, >> Julia >> >> > -Original Message- >> > From: Joseph Myers [mailto:jos...@codesourcery.com] >> > Sent: Monday, March 12, 2018 10:21 PM >> > To: Koval, Julia >> > Cc: 'GCC Patches' ; Uros Bizjak >> > >> > Subject: Re: [patch][x86] Split-up march icelake on march=icelake-server >> > and >> > march=icelake-client >> > >> > On Mon, 12 Mar 2018, Koval, Julia wrote: >> > >> > > Hi, >> > > This patch introduces separate client and server arch options instead of >> > > -march=icelake. Ok for trunk? >> > >> > I don't see any invoke.texi updates here to document what these two >> > options mean (including, presumably, different lists of features for >> > them). >> > >> > -- >> > Joseph S. Myers >> > jos...@codesourcery.com
Re: [PATCH] MIPS/GCC: Mark text contents as code or data
I noticed that data-sym-pool.c fails on -O0 flags. -O0 output : -cut-- frob: .frame $17,8,$31 # vars= 0, regs= 1/0, args= 0, gp= 0 .mask 0x0002,0 .fmask 0x,0 addiu $sp,-8 sd $17,0($sp) move$17,$sp lw $2,$L4 move$sp,$17 ld $17,0($sp) addiu $sp,8 jr $31 .type __pool_frob_3, @object __pool_frob_3: .align 2 $L3: .word __gnu_local_gp $L4: .word 305419896 .type __pend_frob_3, @function __pend_frob_3: .insn .endfrob .size frob, .-frob .ident "GCC: (gcc trunk r258495 mips64el o32 n32 n64) 8.0.1 20180313 (experimental)" -end-- Is it expected ? maybe we should add skip-if -O0 flags. Paul Hua On Thu, Nov 17, 2016 at 1:15 AM, Maciej W. Rozycki wrote: > On Tue, 15 Nov 2016, Matthew Fortune wrote: > >> I'm a little concerned the expected output tests may be fragile over >> time but let's wait and see. > > Indeed, but I'd rather see false negatives than false positives or no > coverage at all. And I hope the pieces of expected assembly quoted will > help telling any false negatives and actual regressions apart very easily. > >> OK to commit. > > Applied now, thanks for your review. > > Maciej
Re: [AArch64] Add SVE mul_highpart patterns
Christophe Lyon writes:
> On 8 February 2018 at 14:54, Richard Sandiford
> wrote:
>> Index: gcc/testsuite/gcc.target/aarch64/sve/mul_highpart_1_run.c
>> ===
>> --- /dev/null 2018-02-08 11:17:10.862716283 +
>> +++ gcc/testsuite/gcc.target/aarch64/sve/mul_highpart_1_run.c 2018-02-08
>> 13:51:56.253511883 +
>> @@ -0,0 +1,29 @@
>> +/* { dg-do run } */
> You forgot to include an effective target to prevent trying to run on
> non-SVE capable HW.
Oops, sorry about that. I had the fix in the tree I use for non-SVE
testing but forgot to update the commit tree. Applied as below.
> I suppose check_effective_target_aarch64_sve_hw would work, but I 'm
> not sure it's sufficient to prevent from compiling the test with old
> binutils non supporting sve: maybe you also need to add
> aarch64_asm_sve_ok as in the other testcase?
It should be OK. aarch64_sve_hw is supposed to imply aarch64_asm_sve_ok,
since it needs to both assemble and run SVE code.
Thanks,
Richard
2018-03-14 Richard Sandiford
gcc/testsuite/
* gcc.target/aarch64/sve/mul_highpart_1_run.c: Restrict to
aarch64_sve_hw.
Index: gcc/testsuite/gcc.target/aarch64/sve/mul_highpart_1_run.c
===
--- gcc/testsuite/gcc.target/aarch64/sve/mul_highpart_1_run.c 2018-03-13
15:11:55.402370138 +
+++ gcc/testsuite/gcc.target/aarch64/sve/mul_highpart_1_run.c 2018-03-14
09:06:36.946848641 +
@@ -1,4 +1,4 @@
-/* { dg-do run } */
+/* { dg-do run { target aarch64_sve_hw } } */
/* { dg-options "-O2 -ftree-vectorize -fno-vect-cost-model --save-temps" } */
#include "mul_highpart_1.c"
[PATCH] Fix tree statistics with -fmem-report.
Hi.
Current code that tracks memory statistics wrongly decremented a counter
based on t_kind, which is an enum value and thus a constant:
- tree_node_counts[(int) t_kind]--;
That's obviously a mistake.
May I install the patch after reg tests&bootstrap?
Thanks,
Martin
gcc/ChangeLog:
2018-03-14 Martin Liska
* tree.c (record_node_allocation_statistics): Use
get_stats_node_kind.
(get_stats_node_kind): New function extracted from
record_node_allocation_statistics.
(free_node): Use get_stats_node_kind.
---
gcc/tree.c | 94 +-
1 file changed, 38 insertions(+), 56 deletions(-)
diff --git a/gcc/tree.c b/gcc/tree.c
index 1e1a1be1f20..ce52f0af0b7 100644
--- a/gcc/tree.c
+++ b/gcc/tree.c
@@ -933,92 +933,68 @@ tree_size (const_tree node)
}
}
-/* Record interesting allocation statistics for a tree node with CODE
- and LENGTH. */
+/* Return tree node kind based on tree CODE. */
-static void
-record_node_allocation_statistics (enum tree_code code ATTRIBUTE_UNUSED,
- size_t length ATTRIBUTE_UNUSED)
+static tree_node_kind
+get_stats_node_kind (enum tree_code code)
{
enum tree_code_class type = TREE_CODE_CLASS (code);
- tree_node_kind kind;
-
- if (!GATHER_STATISTICS)
-return;
switch (type)
{
case tcc_declaration: /* A decl node */
- kind = d_kind;
- break;
-
+ return d_kind;
case tcc_type: /* a type node */
- kind = t_kind;
- break;
-
+ return t_kind;
case tcc_statement: /* an expression with side effects */
- kind = s_kind;
- break;
-
+ return s_kind;
case tcc_reference: /* a reference */
- kind = r_kind;
- break;
-
+ return r_kind;
case tcc_expression: /* an expression */
case tcc_comparison: /* a comparison expression */
case tcc_unary: /* a unary arithmetic expression */
case tcc_binary: /* a binary arithmetic expression */
- kind = e_kind;
- break;
-
+ return e_kind;
case tcc_constant: /* a constant */
- kind = c_kind;
- break;
-
+ return c_kind;
case tcc_exceptional: /* something random, like an identifier. */
switch (code)
{
case IDENTIFIER_NODE:
- kind = id_kind;
- break;
-
+ return id_kind;
case TREE_VEC:
- kind = vec_kind;
- break;
-
+ return vec_kind;
case TREE_BINFO:
- kind = binfo_kind;
- break;
-
+ return binfo_kind;
case SSA_NAME:
- kind = ssa_name_kind;
- break;
-
+ return ssa_name_kind;
case BLOCK:
- kind = b_kind;
- break;
-
+ return b_kind;
case CONSTRUCTOR:
- kind = constr_kind;
- break;
-
+ return constr_kind;
case OMP_CLAUSE:
- kind = omp_clause_kind;
- break;
-
+ return omp_clause_kind;
default:
- kind = x_kind;
- break;
+ return x_kind;
}
break;
-
case tcc_vl_exp:
- kind = e_kind;
- break;
-
+ return e_kind;
default:
gcc_unreachable ();
}
+}
+
+/* Record interesting allocation statistics for a tree node with CODE
+ and LENGTH. */
+
+static void
+record_node_allocation_statistics (enum tree_code code, size_t length)
+{
+ if (!GATHER_STATISTICS)
+return;
+
+ tree_node_kind kind = get_stats_node_kind (code);
tree_code_counts[(int) code]++;
tree_node_counts[(int) kind]++;
@@ -1157,9 +1133,15 @@ free_node (tree node)
enum tree_code code = TREE_CODE (node);
if (GATHER_STATISTICS)
{
+ enum tree_node_kind kind = get_stats_node_kind (code);
+
+ gcc_checking_assert (tree_code_counts[(int) TREE_CODE (node)] != 0);
+ gcc_checking_assert (tree_node_counts[(int) kind] != 0);
+ gcc_checking_assert (tree_node_sizes[(int) kind] >= tree_size (node));
+
tree_code_counts[(int) TREE_CODE (node)]--;
- tree_node_counts[(int) t_kind]--;
- tree_node_sizes[(int) t_kind] -= tree_size (node);
+ tree_node_counts[(int) kind]--;
+ tree_node_sizes[(int) kind] -= tree_size (node);
}
if (CODE_CONTAINS_STRUCT (code, TS_CONSTRUCTOR))
vec_free (CONSTRUCTOR_ELTS (node));
Re: [PATCH] Fix tree statistics with -fmem-report.
On Wed, Mar 14, 2018 at 10:51 AM, Martin Liška wrote: > Hi. > > Current code that tracks memory statistics wrongly decremented a counter > based on t_kind, which is an enum value and thus a constant: > > - tree_node_counts[(int) t_kind]--; > > That's obviously a mistake. > > May I install the patch after reg tests&bootstrap? Ok. Richard. > Thanks, > Martin > > gcc/ChangeLog: > > 2018-03-14 Martin Liska > > * tree.c (record_node_allocation_statistics): Use > get_stats_node_kind. > (get_stats_node_kind): New function extracted from > record_node_allocation_statistics. > (free_node): Use get_stats_node_kind. > --- > gcc/tree.c | 94 > +- > 1 file changed, 38 insertions(+), 56 deletions(-) > >
[PATCH][ARM][PR82989] Fix unexpected use of NEON instructions for shifts
Hi
This patch fixes PR82989 so that we avoid NEON instructions when
-mneon-for-64bits is not enabled. This is more of a short term fix for
the real deeper problem of making and early decision of choosing or
rejecting NEON instructions. There is now a new ticket PR84467 to deal
with the longer term solution.
(Please refer to the discussion in the bug report for more details).
Testing: Bootstrapped and regtested on arm-none-linux-gnueabihf and
added a new test case based on the test given on the bug report.
Ok for trunk and backports for gcc-7 and gcc-6 branches?
Sudi
*** gcc/ChangeLog ***
2018-03-14 Sudakshina Das
* config/arm/neon.md (ashldi3_neon): Update ?s for constraints
to favor GPR over NEON registers.
(di3_neon): Likewise.
*** gcc/testsuite/ChangeLog ***
2018-03-14 Sudakshina Das
* gcc.target/arm/pr82989.c: New test.
diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md
index 6a6f5d7..1646b21 100644
--- a/gcc/config/arm/neon.md
+++ b/gcc/config/arm/neon.md
@@ -1180,12 +1180,12 @@
)
(define_insn_and_split "ashldi3_neon"
- [(set (match_operand:DI 0 "s_register_operand" "= w, w,?&r,?r,?&r, ?w,w")
- (ashift:DI (match_operand:DI 1 "s_register_operand" " 0w, w, 0r, 0, r, 0w,w")
- (match_operand:SI 2 "general_operand""rUm, i, r, i, i,rUm,i")))
- (clobber (match_scratch:SI 3"= X, X,?&r, X, X, X,X"))
- (clobber (match_scratch:SI 4"= X, X,?&r, X, X, X,X"))
- (clobber (match_scratch:DI 5"=&w, X, X, X, X, &w,X"))
+ [(set (match_operand:DI 0 "s_register_operand" "= w, w, &r, r, &r, ?w,?w")
+ (ashift:DI (match_operand:DI 1 "s_register_operand" " 0w, w, 0r, 0, r, 0w, w")
+ (match_operand:SI 2 "general_operand""rUm, i, r, i, i,rUm, i")))
+ (clobber (match_scratch:SI 3"= X, X, &r, X, X, X, X"))
+ (clobber (match_scratch:SI 4"= X, X, &r, X, X, X, X"))
+ (clobber (match_scratch:DI 5"=&w, X, X, X, X, &w, X"))
(clobber (reg:CC_C CC_REGNUM))]
"TARGET_NEON"
"#"
@@ -1276,7 +1276,7 @@
;; ashrdi3_neon
;; lshrdi3_neon
(define_insn_and_split "di3_neon"
- [(set (match_operand:DI 0 "s_register_operand" "= w, w,?&r,?r,?&r,?w,?w")
+ [(set (match_operand:DI 0 "s_register_operand" "= w, w, &r, r, &r,?w,?w")
(RSHIFTS:DI (match_operand:DI 1 "s_register_operand" " 0w, w, 0r, 0, r,0w, w")
(match_operand:SI 2 "reg_or_int_operand" " r, i, r, i, i, r, i")))
(clobber (match_scratch:SI 3 "=2r, X, &r, X, X,2r, X"))
diff --git a/gcc/testsuite/gcc.target/arm/pr82989.c b/gcc/testsuite/gcc.target/arm/pr82989.c
new file mode 100644
index 000..1295ee6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/pr82989.c
@@ -0,0 +1,38 @@
+/* PR target/82989 */
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-skip-if "avoid conflicts with multilib options" { *-*-* } { "-mcpu=*" } { "-mcpu=cortex-a8" } } */
+/* { dg-skip-if "avoid conflicts with multilib options" { *-*-* } { "-mfpu=*" } { "-mfpu=neon" } } */
+/* { dg-skip-if "avoid conflicts with multilib options" { *-*-* } { "-mfloat-abi=*" } { "-mfloat-abi=hard" } } */
+/* { dg-options "-O2 -mcpu=cortex-a8 -mfpu=neon -mfloat-abi=hard" } */
+/* { dg-add-options arm_neon } */
+
+typedef unsigned long long uint64_t;
+
+void f_shr_imm (uint64_t *a )
+{
+ *a += *a >> 32;
+}
+/* { dg-final { scan-assembler-not "vshr*" } } */
+
+void f_shr_reg (uint64_t *a, uint64_t b)
+{
+ *a += *a >> b;
+}
+/* { dg-final { scan-assembler-not "vshl*" } } */
+/* Only 2 times for f_shr_reg. f_shr_imm should not have any. */
+/* { dg-final { scan-assembler-times {lsr\tr[0-9]+, r[0-9]+, r[0-9]} 2 } } */
+
+void f_shl_imm (uint64_t *a)
+{
+ *a += *a << 32;
+}
+/* { dg-final { scan-assembler-not "vshl*" } } */
+
+void f_shl_reg (uint64_t *a, uint64_t b)
+{
+ *a += *a << b;
+}
+/* { dg-final { scan-assembler-not "vshl*" } } */
+/* Only 2 times for f_shl_reg. f_shl_imm should not have any. */
+/* { dg-final { scan-assembler-times {lsl\tr[0-9]+, r[0-9]+, r[0-9]} 2 } } */
[PATCH] Revert assert in PRE
Bootstrapped on x86_64-unknown-linux-gnu, applied.
Richard.
2018-03-14 Richard Biener
* tree-ssa-pre.c (compute_antic_aux): Remove code that asserts
that the value-set of ANTIC_IN doesn't grow.
Revert
* tree-ssa-pre.c (struct bb_bitmap_sets): Add visited_with_visited_succs
member.
(BB_VISITED_WITH_VISITED_SUCCS): New define.
(compute_antic): Initialize BB_VISITED_WITH_VISITED_SUCCS.
Index: gcc/tree-ssa-pre.c
===
--- gcc/tree-ssa-pre.c (revision 258517)
+++ gcc/tree-ssa-pre.c (working copy)
@@ -484,10 +484,6 @@ typedef struct bb_bitmap_sets
/* True if we have visited this block during ANTIC calculation. */
unsigned int visited : 1;
- /* True if we have visited this block after all successors have been
- visited this way. */
- unsigned int visited_with_visited_succs : 1;
-
/* True when the block contains a call that might not return. */
unsigned int contains_may_not_return_call : 1;
} *bb_value_sets_t;
@@ -501,8 +497,6 @@ typedef struct bb_bitmap_sets
#define NEW_SETS(BB) ((bb_value_sets_t) ((BB)->aux))->new_sets
#define EXPR_DIES(BB) ((bb_value_sets_t) ((BB)->aux))->expr_dies
#define BB_VISITED(BB) ((bb_value_sets_t) ((BB)->aux))->visited
-#define BB_VISITED_WITH_VISITED_SUCCS(BB) \
-((bb_value_sets_t) ((BB)->aux))->visited_with_visited_succs
#define BB_MAY_NOTRETURN(BB) ((bb_value_sets_t)
((BB)->aux))->contains_may_not_return_call
#define BB_LIVE_VOP_ON_EXIT(BB) ((bb_value_sets_t) ((BB)->aux))->vop_on_exit
@@ -2047,8 +2041,6 @@ compute_antic_aux (basic_block block, bo
{
e = single_succ_edge (block);
gcc_assert (BB_VISITED (e->dest));
- BB_VISITED_WITH_VISITED_SUCCS (block)
- = BB_VISITED_WITH_VISITED_SUCCS (e->dest);
phi_translate_set (ANTIC_OUT, ANTIC_IN (e->dest), e);
}
/* If we have multiple successors, we take the intersection of all of
@@ -2059,7 +2051,6 @@ compute_antic_aux (basic_block block, bo
size_t i;
edge first = NULL;
- BB_VISITED_WITH_VISITED_SUCCS (block) = true;
auto_vec worklist (EDGE_COUNT (block->succs));
FOR_EACH_EDGE (e, ei, block->succs)
{
@@ -2078,8 +2069,6 @@ compute_antic_aux (basic_block block, bo
fprintf (dump_file, "ANTIC_IN is MAX on %d->%d\n",
e->src->index, e->dest->index);
}
- BB_VISITED_WITH_VISITED_SUCCS (block)
- &= BB_VISITED_WITH_VISITED_SUCCS (e->dest);
}
/* Of multiple successors we have to have visited one already
@@ -2184,19 +2173,7 @@ compute_antic_aux (basic_block block, bo
}
if (!bitmap_set_equal (old, ANTIC_IN (block)))
-{
- changed = true;
- /* After the initial value set computation the value set may
- only shrink during the iteration. */
- if (was_visited && BB_VISITED_WITH_VISITED_SUCCS (block) &&
flag_checking)
- {
- bitmap_iterator bi;
- unsigned int i;
- EXECUTE_IF_AND_COMPL_IN_BITMAP (&ANTIC_IN (block)->values,
- &old->values, 0, i, bi)
- gcc_unreachable ();
- }
-}
+changed = true;
maybe_dump_sets:
if (dump_file && (dump_flags & TDF_DETAILS))
@@ -2367,7 +2344,6 @@ compute_antic (void)
FOR_ALL_BB_FN (block, cfun)
{
BB_VISITED (block) = 0;
- BB_VISITED_WITH_VISITED_SUCCS (block) = 0;
FOR_EACH_EDGE (e, ei, block->preds)
if (e->flags & EDGE_ABNORMAL)
@@ -2384,7 +2360,6 @@ compute_antic (void)
/* At the exit block we anticipate nothing. */
BB_VISITED (EXIT_BLOCK_PTR_FOR_FN (cfun)) = 1;
- BB_VISITED_WITH_VISITED_SUCCS (EXIT_BLOCK_PTR_FOR_FN (cfun)) = 1;
/* For ANTIC computation we need a postorder that also guarantees that
a block with a single successor is visited after its successor.
Re: [PR84682] disregard address constraints on non-addresses
On Wed, Mar 14, 2018 at 8:03 AM, Alexandre Oliva wrote: > On Mar 12, 2018, "Bin.Cheng" wrote: > >> internal compiler error: in aarch64_classify_address, at >> config/aarch64/aarch64.c:5678 >> 0xfe3c29 aarch64_classify_address >> /.../build/src/gcc/gcc/config/aarch64/aarch64.c:5677 >> 0xfe8be8 aarch64_legitimate_address_hook_p >> /.../build/src/gcc/gcc/config/aarch64/aarch64.c:5958 >> 0xc0149e default_addr_space_legitimate_address_p(machine_mode, >> rtx_def*, bool, unsigned char) >> /.../build/src/gcc/gcc/targhooks.c:1476 >> 0xb5b9f1 memory_address_addr_space_p(machine_mode, rtx_def*, unsigned char) >> /.../build/src/gcc/gcc/recog.c:1334 >> 0xb5d278 address_operand(rtx_def*, machine_mode) >> /.../build/src/gcc/gcc/recog.c:1073 >> 0xb5e186 asm_operand_ok(rtx_def*, char const*, char const**) >> /.../build/src/gcc/gcc/recog.c:1816 >> 0x73f440 expand_asm_stmt >> /.../build/src/gcc/gcc/cfgexpand.c:3138 >> 0x742d3c expand_gimple_stmt_1 >> /.../build/src/gcc/gcc/cfgexpand.c:3621 > >> Not sure if it reveals latent bug or just inconsistent issue with >> backend though. > > Possibly both, in a way. This triggers at expand, which is much earlier > than the patch affects compilation; that call to address_operand was > already there before. So the ICE was latent, but only in the sense that > we didn't have tests that would have triggered it. Any asm stmt with a > p constraint and a non-address operand (with another constraint to > accept it) would have exercised this aarch64-specific ICE, and it would > do so before hitting the machine-independent ICE that the patch fixed. > > aarch64_classify_address should probably return false instead of failing > that assertion. When it comes to asm operands, there's no guarantee > that you'll get something that even looks like an address, when you're > part of the very code that's supposed to tell the rest of the compiler > what a legitimate address should look like. Yes, the assert imposes stronger condition on input, which it could simply return false indicating an invalid address. I will test a change to see if there is any fallout. Thanks, bin > > -- > Alexandre Oliva, freedom fighterhttp://FSFLA.org/~lxoliva/ > You must be the change you wish to see in the world. -- Gandhi > Be Free! -- http://FSFLA.org/ FSF Latin America board member > Free Software Evangelist|Red Hat Brasil GNU Toolchain Engineer
PING^2: [PATCH] Use dlsym to check if libdl is needed for plugin
On Wed, Feb 21, 2018 at 3:02 AM, H.J. Lu wrote: > On Wed, Oct 18, 2017 at 5:25 PM, H.J. Lu wrote: >> config/plugins.m4 has >> >> if test "$plugins" = "yes"; then >> AC_SEARCH_LIBS([dlopen], [dl]) >> fi >> >> Plugin uses dlsym, but libasan.so only intercepts dlopen, not dlsym: >> >> [hjl@gnu-tools-1 binutils-text]$ nm -D /lib64/libasan.so.4| grep " dl" >> 00038580 W dlclose >> U dl_iterate_phdr >> 0004dc50 W dlopen >> U dlsym >> U dlvsym >> [hjl@gnu-tools-1 binutils-text]$ >> >> Testing dlopen for libdl leads to false negative when -fsanitize=address >> is used. It results in link failure: >> >> ../bfd/.libs/libbfd.a(plugin.o): undefined reference to symbol >> 'dlsym@@GLIBC_2.16' >> >> dlsym should be used to check if libdl is needed for plugin. >> >> OK for master? >> >> H.J. >> --- >> bfd/ >> >> PR gas/22318 >> * configure: Regenerated. >> >> binutils/ >> >> PR gas/22318 >> * configure: Regenerated. >> >> config/ >> >> * plugins.m4 (AC_PLUGINS): Use dlsym to check if libdl is needed. >> >> gas/ >> >> PR gas/22318 >> * configure: Regenerated. >> >> gprof/ >> >> PR gas/22318 >> * configure: Regenerated. >> >> ld/ >> >> PR gas/22318 >> * configure: Regenerated. PING. -- H.J. From 8157f3e03107e77b8306d4ab1388a63548a13470 Mon Sep 17 00:00:00 2001 From: "H.J. Lu" Date: Wed, 18 Oct 2017 17:18:37 -0700 Subject: [PATCH] Use dlsym to check if libdl is needed for plugin config/plugins.m4 has if test "$plugins" = "yes"; then AC_SEARCH_LIBS([dlopen], [dl]) fi Plugin uses dlsym, but libasan.so only intercepts dlopen, not dlsym: [hjl@gnu-tools-1 binutils-text]$ nm -D /lib64/libasan.so.4| grep " dl" 00038580 W dlclose U dl_iterate_phdr 0004dc50 W dlopen U dlsym U dlvsym [hjl@gnu-tools-1 binutils-text]$ Testing dlopen for libdl leads to false negative when -fsanitize=address is used. It results in link failure: ../bfd/.libs/libbfd.a(plugin.o): undefined reference to symbol 'dlsym@@GLIBC_2.16' dlsym should be used to check if libdl is needed for plugin. * plugins.m4 (AC_PLUGINS): Use dlsym to check if libdl is needed. diff --git a/config/plugins.m4 b/config/plugins.m4 index 513c690e1b..c6acebc1ca 100644 --- a/config/plugins.m4 +++ b/config/plugins.m4 @@ -16,6 +16,6 @@ AC_DEFUN([AC_PLUGINS], [plugins=$maybe_plugins] ) if test "$plugins" = "yes"; then -AC_SEARCH_LIBS([dlopen], [dl]) +AC_SEARCH_LIBS([dlsym], [dl]) fi ])
RE: [patch][i386] Adding pconfig, wbnoinvd and wbinvd intrinsics
Hi, I have made changes to this patch. I attached a new version. 14.03. 2018 Olga Makhotina gcc/ * config/i386/sgxintrin.h (_enclv_u32): New intrinsic. (__enclv_bc, __enclv_cd, __enclv_generic): New definitions. (ERDINFO, ETRACKC, ELDBC, ELDUC): New leaves. gcc/testsuite/ * gcc.target/i386/sgx.c (_enclv_u32): Test new intrinsic. Is it ok for trunk? Thanks, Olga. -Original Message- From: Uros Bizjak [mailto:ubiz...@gmail.com] Sent: Sunday, March 4, 2018 8:23 PM To: Makhotina, Olga Cc: gcc-patches@gcc.gnu.org; Kirill Yukhin Subject: Re: [patch][i386] Adding pconfig, wbnoinvd and wbinvd intrinsics On Fri, Mar 2, 2018 at 3:15 PM, Makhotina, Olga wrote: > Hi, > > I have made changes to this patch. > I attached a new version. > > 02.03.2018 Olga Makhotina > > gcc/ > * common/config/i386/i386-common.c (OPTION_MASK_ISA_PCONFIG_SET, > OPTION_MASK_ISA_PCONFIG_UNSET, OPTION_MASK_ISA_WBNOINVD_SET, > OPTION_MASK_ISA_WBNOINVD_UNSET): New definitions. > (ix86_handle_option): Handle -mpconfig and -mwbnoinvd. > * config.gcc (pconfigintrin.h, wbnoinvdintrin.h) : Add headers. > * config/i386/cpuid.h (bit_PCONFIG, bit_WBNOINVD): New. > * config/i386/driver-i386.c (host_detect_local_cpu): Detect -mpconfig > and -mwbnoinvd. > * config/i386/i386-builtin.def (__builtin_ia32_wbnoinvd, > __builtin_ia32_wbinvd): New builtins. > (SPECIAL_ARGS2): New. > * config/i386/i386-c.c (__WBNOINVD__, __PCONFIG__): New. > (SPECIAL_ARGS2): New. > * config/i386/i386.c (ix86_target_string): Add -mpconfig and > -mwbnoinvd. > (ix86_valid_target_attribute_inner_p): Ditto. > (ix86_init_mmx_sse_builtins): Add special_args2. > * config/i386/i386.h (TARGET_PCONFIG, TARGET_PCONFIG_P, > TARGET_WBNOINVD, > TARGET_WBNOINVD_P): New. > * config/i386/i386.md (UNSPECV_WBINVD, UNSPECV_WBNOINVD): New. > (define_insn "wbinvd", define_insn "wbnoinvd"): New. > * config/i386/i386.opt: Add -mpconfig and -mwbnoinvd. > * config/i386/immintrin.h (_wbinvd): New intrinsic. > * config/i386/pconfigintrin.h: New file. > * config/i386/wbnoinvdintrin.h: Ditto. > * config/i386/x86intrin.h: Add headers pconfigintrin.h and > wbnoinvdintrin.h. > * doc/invoke.texi (-mpconfig, -mwbnoinvd): New. > > gcc/testsuite/ > * g++.dg/other/i386-2.C: Add -mpconfig and -mwbnoinvd. > * g++.dg/other/i386-3.C: Ditto. > * gcc.target/i386/sse-12.c: Ditto. > * gcc.target/i386/sse-13.c: Ditto. > * gcc.target/i386/sse-14.c: Ditto. > * gcc.target/i386/sse-23.c: Add pconfig and wbnoinvd. > * gcc.target/i386/wbinvd-1.c: New test. > * gcc.target/i386/wbnoinvd-1.c: Ditto. > * gcc.target/i386/pconfig-1.c: Ditto. > > Is it ok for trunk? OK. Thanks, Uros. 0001-enclv.patch Description: 0001-enclv.patch
Re: [PATCH] Prefer mempcpy to memcpy on x86_64 target (PR middle-end/81657).
On 03/13/2018 04:23 PM, Jakub Jelinek wrote:
> On Tue, Mar 13, 2018 at 04:19:21PM +0100, Martin Liška wrote:
>>> Yes, see e.g. TARGET_LIBC_HAS_FUNCTION target hook,
>>> where in particular linux_libc_has_function deals with various C libraries.
>>> Of course, in this case you need another target hook, that is dependent both
>>> on the target backend and C library.
>>>
>>> It would be nice to make the target hook a little bit more generic as well,
>>> e.g. pass it enum builtin_function and query if it is fast, slow or
>>> unknown, or even some kind of cost, where the caller could ask for cost of
>>> BUILT_IN_MEMCPY and BUILT_IN_MEMPCPY and decide based on the relative costs.
>>
>> Let me start with simple return enum value of FAST,SLOW,UNKNOWN. I've added
>> new hook
>> definition to gcc/config/gnu-user.h that will point to
>> gnu_libc_function_implementation.
>> I would like to implement the function in gcc/targhooks.c, but I don't know
>> how to
>> make ifdef according to target?
>
> Put there just the default implementation (everything is UNKNOWN?).
>
>> One another issue is that built_in_function is enum defined in tree.h. Thus
>> I'll replace the
>> callback argument with int, that will be casted. One last issue: am I right
>> that I'll have to define
>> TARGET_LIBC_FUNCTION_IMPLEMENTATION in each config file (similar to
>> no_c99_libc_has_function)?
>
> And define the i386/x86_64 glibc one in config/i386/*.h, check there
> OPTION_GLIBC and only in that case return something other than UNKNOWN.
>
> And redefine TARGET_LIBC_FUNCTION_IMPLEMENTATION only in that case.
>
> Jakub
>
Hi.
I'm sending V2 that can survive bootstrap and regression tests on both x86_64
and ppc64le.
Martin
>From 222c7c205a7afc144dc123d2b378a057dcf8816f Mon Sep 17 00:00:00 2001
From: marxin
Date: Wed, 14 Mar 2018 09:44:18 +0100
Subject: [PATCH] Introduce new libc_func_speed target hook (PR
middle-end/81657).
gcc/ChangeLog:
2018-03-14 Martin Liska
PR middle-end/81657
* builtins.c (expand_builtin_memory_copy_args): Handle situation
when libc library provides a fast mempcpy implementation/
* config/i386/i386-protos.h (gnu_libc_func_speed): New.
* config/i386/i386.c (enum libc_speed): Likewise.
(ix86_libc_func_speed): Likewise.
(TARGET_LIBC_FUNC_SPEED): Likewise.
* coretypes.h (enum libc_speed): Likewise.
* doc/tm.texi: Document new target hook.
* doc/tm.texi.in: Likewise.
* expr.c (emit_block_move_hints): Handle libc bail out argument.
* expr.h (emit_block_move_hints): Add new parameters.
* target.def: Add new hook.
* targhooks.c (enum libc_speed): New enum.
(default_libc_func_speed): Provide a default hook
implementation.
* targhooks.h (default_libc_func_speed): Likewise.
gcc/testsuite/ChangeLog:
2018-03-14 Martin Liska
* gcc.c-torture/execute/builtins/mempcpy.c (main_test): Adjust
to not use mempcpy.
* gcc.dg/string-opt-1.c: Adjust for i386 target.
---
gcc/builtins.c | 13 -
gcc/config/i386/i386-protos.h| 2 ++
gcc/config/i386/i386.c | 20
gcc/coretypes.h | 7 +++
gcc/doc/tm.texi | 4
gcc/doc/tm.texi.in | 1 +
gcc/expr.c | 16 +++-
gcc/expr.h | 4 +++-
gcc/target.def | 7 +++
gcc/targhooks.c | 6 ++
gcc/targhooks.h | 1 +
.../gcc.c-torture/execute/builtins/mempcpy.c | 2 +-
gcc/testsuite/gcc.dg/string-opt-1.c | 4 ++--
13 files changed, 81 insertions(+), 6 deletions(-)
diff --git a/gcc/builtins.c b/gcc/builtins.c
index 85affa74510..eb038dd45b3 100644
--- a/gcc/builtins.c
+++ b/gcc/builtins.c
@@ -3651,13 +3651,24 @@ expand_builtin_memory_copy_args (tree dest, tree src, tree len,
src_mem = get_memory_rtx (src, len);
set_mem_align (src_mem, src_align);
+ bool is_move_done;
+
/* Copy word part most expediently. */
+ bool bail_out_libcall = endp == 1
+&& targetm.libc_func_speed ((int)BUILT_IN_MEMPCPY) == FAST_SPEED;
dest_addr = emit_block_move_hints (dest_mem, src_mem, len_rtx,
CALL_EXPR_TAILCALL (exp)
&& (endp == 0 || target == const0_rtx)
? BLOCK_OP_TAILCALL : BLOCK_OP_NORMAL,
expected_align, expected_size,
- min_size, max_size, probable_max_size);
+ min_size, max_size, probable_max_size,
+ bail_out_libcall, &is_move_done);
+
+ /* Bail out when a mempcpy call would be expanded as libcall and when
+ we have a target that provides a fast implementation
+ of mempcpy routine. */
+ if (!is_move_done)
+return NULL_RTX;
if (dest_addr == 0)
{
diff --git a/gcc/config/i386/i386-protos.h b/gcc/confi
Re: [PATCH] Prefer mempcpy to memcpy on x86_64 target (PR middle-end/81657).
On Wed, Mar 14, 2018 at 5:54 AM, Martin Liška wrote: > On 03/13/2018 04:23 PM, Jakub Jelinek wrote: >> On Tue, Mar 13, 2018 at 04:19:21PM +0100, Martin Liška wrote: Yes, see e.g. TARGET_LIBC_HAS_FUNCTION target hook, where in particular linux_libc_has_function deals with various C libraries. Of course, in this case you need another target hook, that is dependent both on the target backend and C library. It would be nice to make the target hook a little bit more generic as well, e.g. pass it enum builtin_function and query if it is fast, slow or unknown, or even some kind of cost, where the caller could ask for cost of BUILT_IN_MEMCPY and BUILT_IN_MEMPCPY and decide based on the relative costs. >>> >>> Let me start with simple return enum value of FAST,SLOW,UNKNOWN. I've added >>> new hook >>> definition to gcc/config/gnu-user.h that will point to >>> gnu_libc_function_implementation. >>> I would like to implement the function in gcc/targhooks.c, but I don't know >>> how to >>> make ifdef according to target? >> >> Put there just the default implementation (everything is UNKNOWN?). >> >>> One another issue is that built_in_function is enum defined in tree.h. Thus >>> I'll replace the >>> callback argument with int, that will be casted. One last issue: am I right >>> that I'll have to define >>> TARGET_LIBC_FUNCTION_IMPLEMENTATION in each config file (similar to >>> no_c99_libc_has_function)? >> >> And define the i386/x86_64 glibc one in config/i386/*.h, check there >> OPTION_GLIBC and only in that case return something other than UNKNOWN. >> >> And redefine TARGET_LIBC_FUNCTION_IMPLEMENTATION only in that case. >> >> Jakub >> > > Hi. > > I'm sending V2 that can survive bootstrap and regression tests on both x86_64 > and ppc64le. > > Martin diff --git a/gcc/testsuite/gcc.c-torture/execute/builtins/mempcpy.c b/gcc/testsuite/gcc.c-torture/execute/builtins/mempcpy.c index d82e2232d7b..91e1c87f83f 100644 --- a/gcc/testsuite/gcc.c-torture/execute/builtins/mempcpy.c +++ b/gcc/testsuite/gcc.c-torture/execute/builtins/mempcpy.c @@ -62,7 +62,7 @@ main_test (void) mempcpy (p + 5, s3, 1); if (memcmp (p, "ABCDEFg", 8)) abort (); - mempcpy (p + 6, s1 + 1, l1); + memcpy (p + 6, s1 + 1, l1); if (memcmp (p, "ABCDEF2", 8)) abort (); } This is a mempcpy test. Why is mempcpy changed to memcpy? -- H.J.
Re: [PATCH] Prefer mempcpy to memcpy on x86_64 target (PR middle-end/81657).
On 03/14/2018 01:57 PM, H.J. Lu wrote: > On Wed, Mar 14, 2018 at 5:54 AM, Martin Liška wrote: >> On 03/13/2018 04:23 PM, Jakub Jelinek wrote: >>> On Tue, Mar 13, 2018 at 04:19:21PM +0100, Martin Liška wrote: > Yes, see e.g. TARGET_LIBC_HAS_FUNCTION target hook, > where in particular linux_libc_has_function deals with various C > libraries. > Of course, in this case you need another target hook, that is dependent > both > on the target backend and C library. > > It would be nice to make the target hook a little bit more generic as > well, > e.g. pass it enum builtin_function and query if it is fast, slow or > unknown, or even some kind of cost, where the caller could ask for cost of > BUILT_IN_MEMCPY and BUILT_IN_MEMPCPY and decide based on the relative > costs. Let me start with simple return enum value of FAST,SLOW,UNKNOWN. I've added new hook definition to gcc/config/gnu-user.h that will point to gnu_libc_function_implementation. I would like to implement the function in gcc/targhooks.c, but I don't know how to make ifdef according to target? >>> >>> Put there just the default implementation (everything is UNKNOWN?). >>> One another issue is that built_in_function is enum defined in tree.h. Thus I'll replace the callback argument with int, that will be casted. One last issue: am I right that I'll have to define TARGET_LIBC_FUNCTION_IMPLEMENTATION in each config file (similar to no_c99_libc_has_function)? >>> >>> And define the i386/x86_64 glibc one in config/i386/*.h, check there >>> OPTION_GLIBC and only in that case return something other than UNKNOWN. >>> >>> And redefine TARGET_LIBC_FUNCTION_IMPLEMENTATION only in that case. >>> >>> Jakub >>> >> >> Hi. >> >> I'm sending V2 that can survive bootstrap and regression tests on both >> x86_64 and ppc64le. >> >> Martin > > diff --git a/gcc/testsuite/gcc.c-torture/execute/builtins/mempcpy.c > b/gcc/testsuite/gcc.c-torture/execute/builtins/mempcpy.c > index d82e2232d7b..91e1c87f83f 100644 > --- a/gcc/testsuite/gcc.c-torture/execute/builtins/mempcpy.c > +++ b/gcc/testsuite/gcc.c-torture/execute/builtins/mempcpy.c > @@ -62,7 +62,7 @@ main_test (void) >mempcpy (p + 5, s3, 1); >if (memcmp (p, "ABCDEFg", 8)) > abort (); > - mempcpy (p + 6, s1 + 1, l1); > + memcpy (p + 6, s1 + 1, l1); >if (memcmp (p, "ABCDEF2", 8)) > abort (); > } > > This is a mempcpy test. Why is mempcpy changed to memcpy? > Because this mempcpy is not optimized out to memcpy and it then aborts. It's proper to leave here mempcpy I believe. Martin
Re: [PATCH] Prefer mempcpy to memcpy on x86_64 target (PR middle-end/81657).
On Wed, Mar 14, 2018 at 01:54:39PM +0100, Martin Liška wrote:
> --- a/gcc/builtins.c
> +++ b/gcc/builtins.c
> @@ -3651,13 +3651,24 @@ expand_builtin_memory_copy_args (tree dest, tree src,
> tree len,
>src_mem = get_memory_rtx (src, len);
>set_mem_align (src_mem, src_align);
>
> + bool is_move_done;
> +
>/* Copy word part most expediently. */
This comment supposedly belongs right above the emit_block_move_hints call.
> + bool bail_out_libcall = endp == 1
> +&& targetm.libc_func_speed ((int)BUILT_IN_MEMPCPY) == FAST_SPEED;
Formatting. && belongs below endp. So either:
bool bail_out_libcall
= (endp == 1
&& ...);
or
bool bail_out_libcall = false;
if (endp == 1
&& ...)
bail_out_libcall = true;
?
The variable is not named very well, shouldn't it be avoid_libcall or
something similar? Perhaps the variable should have a comment describing
what it is. Do you need separate argument for that bool and
is_move_done, rather than just the flag being that some pointer to bool is
non-NULL?
>dest_addr = emit_block_move_hints (dest_mem, src_mem, len_rtx,
>CALL_EXPR_TAILCALL (exp)
>&& (endp == 0 || target == const0_rtx)
>? BLOCK_OP_TAILCALL : BLOCK_OP_NORMAL,
>expected_align, expected_size,
> - min_size, max_size, probable_max_size);
> + min_size, max_size, probable_max_size,
> + bail_out_libcall, &is_move_done);
> +
> + /* Bail out when a mempcpy call would be expanded as libcall and when
> + we have a target that provides a fast implementation
> + of mempcpy routine. */
> + if (!is_move_done)
> +return NULL_RTX;
>
>if (dest_addr == 0)
> {
> --- a/gcc/config/i386/i386.c
> +++ b/gcc/config/i386/i386.c
> @@ -2733,6 +2733,23 @@ ix86_using_red_zone (void)
> && (!cfun->machine->has_local_indirect_jump
> || cfun->machine->indirect_branch_type == indirect_branch_keep));
> }
> +
Missing function comment here. For target hooks, usually there is a copy of
the target.def comment, perhaps with further details on why it is overridden
and what it does.
> --- a/gcc/coretypes.h
> +++ b/gcc/coretypes.h
> @@ -384,6 +384,13 @@ enum excess_precision_type
>EXCESS_PRECISION_TYPE_FAST
> };
>
Missing comment describing what it is, plus it the enumerators are too
generic, if it is libc_speed enum, perhaps LIBC_FAST_SPEED etc.?
> --- a/gcc/targhooks.c
> +++ b/gcc/targhooks.c
> @@ -1642,6 +1642,12 @@ no_c99_libc_has_function (enum function_class fn_class
> ATTRIBUTE_UNUSED)
>return false;
> }
>
Again, missing function comment.
> +enum libc_speed
> +default_libc_func_speed (int)
> +{
> + return UNKNOWN_SPEED;
> +}
> +
> --- a/gcc/testsuite/gcc.dg/string-opt-1.c
> +++ b/gcc/testsuite/gcc.dg/string-opt-1.c
> @@ -48,5 +48,5 @@ main (void)
>return 0;
> }
>
> -/* { dg-final { scan-assembler-not "\" } } */
> -/* { dg-final { scan-assembler "memcpy" } } */
> +/* { dg-final { scan-assembler-not "\" { target { i?86-*-*
> x86_64-*-* } } } } */
> +/* { dg-final { scan-assembler "memcpy" { target { ! { i?86-*-* x86_64-*-*
> } } } } } */
First of all, I don't really understand this, I'd expect both the
two old dg-final lines to be used as is for non-x86 targets and another two
for x86_64, and more importantly, the target hook is only for glibc, not for
musl/bionic etc., nor for non-linux, so you probably need some effective
target for it for whether it is glibc rather than musl/bionic, and use
...-*-linux* and ...-*-gnu* etc. rather than ...-*-*. Or tweak the dg-fianl
patterns so that it succeeds on both variants of the target hook, but then
does the test test anything at all?
Jakub
Re: [PATCH] Prefer mempcpy to memcpy on x86_64 target (PR middle-end/81657).
On Wed, Mar 14, 2018 at 02:08:07PM +0100, Martin Liška wrote: > > diff --git a/gcc/testsuite/gcc.c-torture/execute/builtins/mempcpy.c > > b/gcc/testsuite/gcc.c-torture/execute/builtins/mempcpy.c > > index d82e2232d7b..91e1c87f83f 100644 > > --- a/gcc/testsuite/gcc.c-torture/execute/builtins/mempcpy.c > > +++ b/gcc/testsuite/gcc.c-torture/execute/builtins/mempcpy.c > > @@ -62,7 +62,7 @@ main_test (void) > >mempcpy (p + 5, s3, 1); > >if (memcmp (p, "ABCDEFg", 8)) > > abort (); > > - mempcpy (p + 6, s1 + 1, l1); > > + memcpy (p + 6, s1 + 1, l1); > >if (memcmp (p, "ABCDEF2", 8)) > > abort (); > > } > > > > This is a mempcpy test. Why is mempcpy changed to memcpy? > > > > Because this mempcpy is not optimized out to memcpy and it then aborts. Why it isn't optimized to memcpy? If the lhs is unused, it always should be folded to memcpy, regardless of whether mempcpy is fast or not (I assume no target has slow memcpy and fast mempcpy). Jakub
[PATCH] combine: Don't make log_links for pc_rtx (PR84780 #c10)
distribute_links tries to place a log_link for whatever the destination of the modified instruction is. It shouldn't do that when that dest is pc_rtx, which isn't actually a register. Committing to trunk. Segher 2018-03-14 Segher Boessenkool * combine.c (distribute_links): Don't make a link based on pc_rtx. --- gcc/combine.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/gcc/combine.c b/gcc/combine.c index 0a447b9..eaebe65 100644 --- a/gcc/combine.c +++ b/gcc/combine.c @@ -14812,6 +14812,9 @@ distribute_links (struct insn_link *links) || GET_CODE (reg) == SUBREG) reg = XEXP (reg, 0); + if (reg == pc_rtx) + continue; + /* A LOG_LINK is defined as being placed on the first insn that uses a register and points to the insn that sets the register. Start searching at the next insn after the target of the link and stop -- 1.8.3.1
[PATCH] rs6000: Fix sanitizer frame unwind on 32-bit ABIs
This fixes more than half of our testcase failures on BE.
Committing.
Segher
2018-03-14 Segher Boessenkool
libsanitizer/
* sanitizer_common/sanitizer_stacktrace.cc
(BufferedStackTrace::FastUnwindStack): Use the correct frame offset
for PowerPC SYSV ABI.
---
libsanitizer/sanitizer_common/sanitizer_stacktrace.cc | 13 ++---
1 file changed, 10 insertions(+), 3 deletions(-)
diff --git a/libsanitizer/sanitizer_common/sanitizer_stacktrace.cc
b/libsanitizer/sanitizer_common/sanitizer_stacktrace.cc
index 83309d6..2de585c 100644
--- a/libsanitizer/sanitizer_common/sanitizer_stacktrace.cc
+++ b/libsanitizer/sanitizer_common/sanitizer_stacktrace.cc
@@ -78,14 +78,21 @@ void BufferedStackTrace::FastUnwindStack(uptr pc, uptr bp,
uptr stack_top,
IsAligned((uptr)frame, sizeof(*frame)) &&
size < max_depth) {
#ifdef __powerpc__
-// PowerPC ABIs specify that the return address is saved at offset
-// 16 of the *caller's* stack frame. Thus we must dereference the
-// back chain to find the caller frame before extracting it.
+// PowerPC ABIs specify that the return address is saved on the
+// *caller's* stack frame. Thus we must dereference the back chain
+// to find the caller frame before extracting it.
uhwptr *caller_frame = (uhwptr*)frame[0];
if (!IsValidFrame((uptr)caller_frame, stack_top, bottom) ||
!IsAligned((uptr)caller_frame, sizeof(uhwptr)))
break;
+// For most ABIs the offset where the return address is saved is two
+// register sizes. The exception is the SVR4 ABI, which uses an
+// offset of only one register size.
+#ifdef _CALL_SYSV
+uhwptr pc1 = caller_frame[1];
+#else
uhwptr pc1 = caller_frame[2];
+#endif
#elif defined(__s390__)
uhwptr pc1 = frame[14];
#else
--
1.8.3.1
Re: [PATCH] Prefer mempcpy to memcpy on x86_64 target (PR middle-end/81657).
On 03/14/2018 02:07 PM, Jakub Jelinek wrote:
> On Wed, Mar 14, 2018 at 01:54:39PM +0100, Martin Liška wrote:
>> --- a/gcc/builtins.c
>> +++ b/gcc/builtins.c
>> @@ -3651,13 +3651,24 @@ expand_builtin_memory_copy_args (tree dest, tree
>> src, tree len,
>>src_mem = get_memory_rtx (src, len);
>>set_mem_align (src_mem, src_align);
>>
>> + bool is_move_done;
>> +
>>/* Copy word part most expediently. */
>
> This comment supposedly belongs right above the emit_block_move_hints call.
>
>> + bool bail_out_libcall = endp == 1
>> +&& targetm.libc_func_speed ((int)BUILT_IN_MEMPCPY) == FAST_SPEED;
>
> Formatting. && belongs below endp. So either:
> bool bail_out_libcall
> = (endp == 1
>&& ...);
> or
> bool bail_out_libcall = false;
> if (endp == 1
> && ...)
> bail_out_libcall = true;
> ?
> The variable is not named very well, shouldn't it be avoid_libcall or
> something similar? Perhaps the variable should have a comment describing
> what it is. Do you need separate argument for that bool and
> is_move_done, rather than just the flag being that some pointer to bool is
> non-NULL?
Can you please explain me how to replace the 2 new arguments?
>
>>dest_addr = emit_block_move_hints (dest_mem, src_mem, len_rtx,
>> CALL_EXPR_TAILCALL (exp)
>> && (endp == 0 || target == const0_rtx)
>> ? BLOCK_OP_TAILCALL : BLOCK_OP_NORMAL,
>> expected_align, expected_size,
>> - min_size, max_size, probable_max_size);
>> + min_size, max_size, probable_max_size,
>> + bail_out_libcall, &is_move_done);
>> +
>> + /* Bail out when a mempcpy call would be expanded as libcall and when
>> + we have a target that provides a fast implementation
>> + of mempcpy routine. */
>> + if (!is_move_done)
>> +return NULL_RTX;
>>
>>if (dest_addr == 0)
>> {
>> --- a/gcc/config/i386/i386.c
>> +++ b/gcc/config/i386/i386.c
>> @@ -2733,6 +2733,23 @@ ix86_using_red_zone (void)
>>&& (!cfun->machine->has_local_indirect_jump
>>|| cfun->machine->indirect_branch_type == indirect_branch_keep));
>> }
>> +
>
> Missing function comment here. For target hooks, usually there is a copy of
> the target.def comment, perhaps with further details on why it is overridden
> and what it does.
>> --- a/gcc/coretypes.h
>> +++ b/gcc/coretypes.h
>> @@ -384,6 +384,13 @@ enum excess_precision_type
>>EXCESS_PRECISION_TYPE_FAST
>> };
>>
>
> Missing comment describing what it is, plus it the enumerators are too
> generic, if it is libc_speed enum, perhaps LIBC_FAST_SPEED etc.?
>> --- a/gcc/targhooks.c
>> +++ b/gcc/targhooks.c
>> @@ -1642,6 +1642,12 @@ no_c99_libc_has_function (enum function_class
>> fn_class ATTRIBUTE_UNUSED)
>>return false;
>> }
>>
>
> Again, missing function comment.
>
>> +enum libc_speed
>> +default_libc_func_speed (int)
>> +{
>> + return UNKNOWN_SPEED;
>> +}
>> +
>
>> --- a/gcc/testsuite/gcc.dg/string-opt-1.c
>> +++ b/gcc/testsuite/gcc.dg/string-opt-1.c
>> @@ -48,5 +48,5 @@ main (void)
>>return 0;
>> }
>>
>> -/* { dg-final { scan-assembler-not "\" } } */
>> -/* { dg-final { scan-assembler "memcpy" } } */
>> +/* { dg-final { scan-assembler-not "\" { target { i?86-*-*
>> x86_64-*-* } } } } */
>> +/* { dg-final { scan-assembler "memcpy" { target { ! { i?86-*-* x86_64-*-*
>> } } } } } */
>
> First of all, I don't really understand this, I'd expect both the
> two old dg-final lines to be used as is for non-x86 targets and another two
> for x86_64, and more importantly, the target hook is only for glibc, not for
> musl/bionic etc., nor for non-linux, so you probably need some effective
> target for it for whether it is glibc rather than musl/bionic, and use
> ...-*-linux* and ...-*-gnu* etc. rather than ...-*-*. Or tweak the dg-fianl
> patterns so that it succeeds on both variants of the target hook, but then
> does the test test anything at all?
I fixed that by preserving the old 2 old-finals and then I added a new for
x86_64 target.
Apart from the comment above I've fixed all nits and mempcpy is not used when
LHS == NULL.
Martin
>
> Jakub
>
>From 26979038ce9500015f957afd896146022a38490b Mon Sep 17 00:00:00 2001
From: marxin
Date: Wed, 14 Mar 2018 09:44:18 +0100
Subject: [PATCH] Introduce new libc_func_speed target hook (PR
middle-end/81657).
gcc/ChangeLog:
2018-03-14 Martin Liska
PR middle-end/81657
* builtins.c (expand_builtin_memory_copy_args): Handle situation
when libc library provides a fast mempcpy implementation/
* config/i386/i386-protos.h (gnu_libc_func_speed): New.
* config/i386/i386.c (enum libc_speed): Likewise.
(ix86_libc_func_speed): Likewise.
(TARGET_LIBC_FUNC_SPEED): Likewise.
* coretypes.h (enum libc_speed): Likewise.
* doc/tm.texi: Document new target hook.
* do
[committed] Fix ICE for missing header fix-it hints with overlarge #line directives (PR c/84852)
PR c/84852 reports an ICE inside diagnostic_show_locus when printing
a diagnostic for a source file with a #line >= 2^31:
#line 77
int foo (void) { return strlen(""); }
where we're attempting to print a fix-it hint at the top of the file
and underline the "strlen" (two "line spans").
The
#line 77
won't fix within the 32-bit linenum_type, and is truncated from
0x1cf977871
to
0xcf977871
i.e. 3482810481 in decimal.
Such a #line is reported by -pedantic and -pedantic-errors, but we
shouldn't ICE.
The ICE is an assertion failure within layout::calculate_line_spans,
where the line spans have not been properly sorted.
The layout_ranges are stored as int, rather than linenum_type,
giving line -812156815 for the error, and line 1 for the fix-it hint.
However, line_span uses linenum_type rather than int.
line_span::comparator compares these values as int, and hence
decides that (linenum_type)3482810481 aka (int)-812156815 is less
than line 1.
This leads to this assertion failing in layout::calculate_line_spans:
1105 gcc_assert (next->m_first_line >= current->m_first_line);
since it isn't the case that 1 >= 3482810481.
The underlying problem is the mix of types for storing line numbers:
in parts of libcpp and diagnostic-show-locus.c we use linenum_type;
in other places (including libcpp's expanded_location) we use int.
I looked at using linenum_type throughout, but doing so turned into
a large patch, so this patch fixes the ICE in a less invasive way
by merely using linenum_type more consistently just within
diagnostic-show-locus.c, and fixing line_span::comparator to properly
handle line numbers (and line number differences) >= 2^31, by using
a new helper function for linenum_type differences, computing the
difference using long long, and using the sign of the difference
(as the difference might not fit in the "int" return type imposed
by qsort).
(The new testcases assume the host's "unsigned int" is 32 bits; is
there anything we support where that isn't the case?)
I can self-approve the libcpp, diagnostic-show-locus.c and input.c
changes.
As part of the selftests, I needed to add ASSERT_GT and ASSERT_LT
to selftest.h; I'm treating those parts of the patch as "obvious".
Successfully bootstrapped and regression-tested on x86_64-pc-linux-gnu;
adds 14 PASS results to gcc.sum.
Committed to trunk as r258526.
gcc/ChangeLog:
PR c/84852
* diagnostic-show-locus.c (class layout_point): Convert m_line
from int to linenum_type.
(line_span::comparator): Use linenum "compare" function when
comparing line numbers.
(test_line_span): New function.
(layout_range::contains_point): Convert param "row" from int to
linenum_type.
(layout_range::intersects_line_p): Likewise.
(layout::will_show_line_p): Likewise.
(layout::print_source_line): Likewise.
(layout::should_print_annotation_line_p): Likewise.
(layout::print_annotation_line): Likewise.
(layout::print_leading_fixits): Likewise.
(layout::annotation_line_showed_range_p): Likewise.
(struct line_corrections): Likewise for field m_row.
(line_corrections::line_corrections): Likewise for param "row".
(layout::print_trailing_fixits): Likewise.
(layout::get_state_at_point): Likewise.
(layout::get_x_bound_for_row): Likewise.
(layout::print_line): Likewise.
(diagnostic_show_locus): Likewise for locals "last_line" and
"row".
(selftest::diagnostic_show_locus_c_tests): Call test_line_span.
* input.c (selftest::test_linenum_comparisons): New function.
(selftest::input_c_tests): Call it.
* selftest.c (selftest::test_assertions): Test ASSERT_GT,
ASSERT_GT_AT, ASSERT_LT, and ASSERT_LT_AT.
* selftest.h (ASSERT_GT): New macro.
(ASSERT_GT_AT): New macro.
(ASSERT_LT): New macro.
(ASSERT_LT_AT): New macro.
gcc/testsuite/ChangeLog:
PR c/84852
* gcc.dg/fixits-pr84852-1.c: New test.
* gcc.dg/fixits-pr84852-2.c: New test.
libcpp/ChangeLog:
* include/line-map.h (compare): New function on linenum_type.
---
gcc/diagnostic-show-locus.c | 105 ++--
gcc/input.c | 16 +
gcc/selftest.c | 4 ++
gcc/selftest.h | 38
gcc/testsuite/gcc.dg/fixits-pr84852-1.c | 25
gcc/testsuite/gcc.dg/fixits-pr84852-2.c | 25
libcpp/include/line-map.h | 12
7 files changed, 192 insertions(+), 33 deletions(-)
create mode 100644 gcc/testsuite/gcc.dg/fixits-pr84852-1.c
create mode 100644 gcc/testsuite/gcc.dg/fixits-pr84852-2.c
diff --git a/gcc/diagnostic-show-locus.c b/gcc/diagnostic-show-locus.c
index 5eee3cc..bdf608a 100644
--- a/gcc/diagnostic-show-locus.c
+++ b/gcc/diagnostic-show-locus.c
@@ -115,7 +115,7 @@ class layou
Re: [PATCH][AArch64][1/3] PR target/84164: Simplify subreg + redundant AND-immediate
On 14/03/18 14:07, Jakub Jelinek wrote: On Fri, Mar 02, 2018 at 10:34:22AM -0700, Jeff Law wrote: 2018-02-12 Kyrylo Tkachov PR target/84164 * simplify-rtx.c (simplify_truncation): Simplify truncation of masking operation. * config/aarch64/aarch64.md (*aarch64_reg_3_neg_mask2): Use simplify_gen_unary creating a SUBREG. (*aarch64_reg_3_minus_mask): Likewise. (*aarch64__reg_di3_mask2): Use const_int_operand predicate for operand 3. 2018-02-12 Kyrylo Tkachov PR target/84164 * gcc.c-torture/compile/pr84164.c: New test. Sorry. I suspect I dropped this from my inbox when it had the AArch64 marker -- I didn't realize it had a target independent component. The simplify-rtx bits are fine. The version in simplify_truncation is much better than the original in simplify_subreg (which I think needed to verify that you were looking at the lowpart before optimizing). Isn't that a stage1 material though? I fear given the amount of changes that needed to be done for it on i386.md that similar amount of work would be needed on many other targets, especially if they have less extensive testsuite coverage it might take a while to discover it. Perhaps, in which case your patch would be safer, or my subset of that posted at: https://gcc.gnu.org/ml/gcc-patches/2018-02/msg00102.html Maybe that would be preferable and we revisit this simplification for GCC 9? Thanks, Kyrill Jakub
Re: [PATCH v2] Fix bogus strncpy source length warning on source bound by constant
On Tue, Mar 13, 2018 at 7:22 PM, Siddhesh Poyarekar
wrote:
> Avoid issuing a bogus warning when the source of strncpy is bound by a
> constant known to be less than the minimum size of the destination.
>
> Changes from v1:
>
> - Use range-info instead of the MIN_EXPR hack
> - Get the minimum size of dst and check for NULL_TREE return
>
> The patch bootstraps successfully and introduces no new regressions in
> the testsuite.
>
> gcc/
>
> * tree-ssa-strlen.c (handle_builtin_stxncpy): Check bounds of
> source length if available.
>
> gcc/testsuite/
>
> * gcc.dg/builtin-stringop-chk-10.c: New test case.
> ---
> gcc/testsuite/gcc.dg/builtin-stringop-chk-10.c | 17 +
> gcc/tree-ssa-strlen.c | 15 +++
> 2 files changed, 32 insertions(+)
> create mode 100644 gcc/testsuite/gcc.dg/builtin-stringop-chk-10.c
>
> diff --git a/gcc/testsuite/gcc.dg/builtin-stringop-chk-10.c
> b/gcc/testsuite/gcc.dg/builtin-stringop-chk-10.c
> new file mode 100644
> index 000..13e4bd2f049
> --- /dev/null
> +++ b/gcc/testsuite/gcc.dg/builtin-stringop-chk-10.c
> @@ -0,0 +1,17 @@
> +/* Bogus -Wstringop-overflow on strncpy when size is based on strlen but is
> + bound by a constant.
> + { dg-do compile }
> + { dg-options "-O2 -Wstringop-overflow" } */
> +
> +char dst[1024];
> +
> +void
> +f1 (const char *src)
> +{
> + unsigned long limit = 512;
> + unsigned long len = __builtin_strlen (src); /* { dg-bogus "length
> computed here" } */
> + if (len > limit)
> +len = limit;
> +
> + __builtin_strncpy (dst, src, len); /* { dg-bogus "specified bound
> depends on the length of the source argument" } */
> +}
> diff --git a/gcc/tree-ssa-strlen.c b/gcc/tree-ssa-strlen.c
> index 72f6a17cd32..265f351ea85 100644
> --- a/gcc/tree-ssa-strlen.c
> +++ b/gcc/tree-ssa-strlen.c
> @@ -2125,6 +2125,21 @@ handle_builtin_stxncpy (built_in_function,
> gimple_stmt_iterator *gsi)
>return;
> }
>
> + /* Don't bother about the strlen (SRC) in the LEN computation if the range
> of
> + values for LEN ends up within dstsize. */
> + if (TREE_CODE (len) == SSA_NAME)
> +{
> + wide_int min, max;
> + enum value_range_type vr = get_range_info (len, &min, &max);
> + tree dstsize = compute_objsize (dst, 3);
> + if (vr == VR_RANGE && dstsize)
> + {
> + tree len_max = wide_int_to_tree (TREE_TYPE (dstsize), max);
> + if (tree_int_cst_lt (len_max, dstsize))
Instead of building a tree from max you should use
if (wi::to_widest (max) < wi::to_widest (wi::to_wide (dstsize)))
return;
given compute_objsize is somewhat confused about the type it returns
a widest_int compare is required.
Note I'm not too familiar with tree-ssa-strlen.c nor this part of the
warning code
so I'll not approve the patch but after fixing that it looks techincally ok.
Richard.
> + return;
> + }
> +}
> +
>/* Retrieve the strinfo data for the string S that LEN was computed
> from as some function F of strlen (S) (i.e., LEN need not be equal
> to strlen(S)). */
> --
> 2.14.3
>
Re: [PATCH,rs6000] Add vec_permxor support.
Segher:
I have addressed the following comments in the patch
> >
> > 2018-03-12 Carl Love
> >
> > * config/rs6000/rs6000-c.c: Add macro definitions for
> > ALTIVEC_BUILTIN_VEC_PERM.
>
> ALTIVEC_BUILTIN_VEC_PERMXOR.
Fixed typo.
>
> > * config/rs6000/altivec.md: Add define_insn for altivec-
> > vpermxor.
>
> altivec_vpermxor.
>
> Please write this like:
> (altivec_vpermxor): New define_expand.
Fixed.
>
> > Add UNSPEC_VNOR, define_insn altivec_vnor_v16qi3.
>
> There already is nor3 for BOOL_128 (so norv16qi3 for this).
>
> But you probably want to use one_cmpl2 instead (which ends up
> as
> *one_cmpl3_internal for BOOL_128, *one_cmplv16qi3_internal here
> (the "3" is a misnomer), the expander is one_cmplv16qi2).
Changed, removed the vnor definition I added.
>
> > --- /dev/null
> > +++ b/gcc/testsuite/gcc.target/powerpc/builtins-7-runnable.c
> > @@ -0,0 +1,112 @@
> > +/* { dg-do run { target { powerpc*-*-* && { lp64 && p8vector_hw }
> > } } } */
> > +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-
> > mcpu=*" } { "-mcpu=power8" } } */
> > +/* { dg-options "-mcpu=power8 -O2" } */
>
> Does this need lp64?
Nope, removed.
I have retested the patch on
powerpc64-unknown-linux-gnu (Power 8 BE)
powerpc64le-unknown-linux-gnu (Power 8 LE)
powerpc64le-unknown-linux-gnu (Power 9 LE)
The patch is below. Please let me know if it looks OK now. Thanks.
Carl Love
gcc/ChangeLog:
2018-03-14 Carl Love
* config/rs6000/rs6000-c.c: Add macro definitions for
ALTIVEC_BUILTIN_VEC_PERMXOR.
* config/rs6000/rs6000.h: Add #define for vec_permxor builtin.
* config/rs6000/rs6000-builtin.def: Add macro expansions for VPERMXOR.
* config/rs6000/altivec.md (altivec-vpermxor): New define expand.
Add UNSPEC_VNOR, define_insn altivec_vnor_v16qi3.
* config/rs6000/rs6000-p8swap.c (rtx_is_swappable_p): Add case
UNSPEC_VPERMXOR.
* config/doc/extend.texi: Add prototypes for vec_permxor.
gcc/testsuite/ChangeLog:
2018-03-13 Carl Love
* gcc.target/powerpc/builtins-7-runnable.c: Add tests for vec_permxor.
---
gcc/config/rs6000/altivec.h| 1 +
gcc/config/rs6000/altivec.md | 23 +
gcc/config/rs6000/rs6000-builtin.def | 3 +
gcc/config/rs6000/rs6000-c.c | 10 ++
gcc/config/rs6000/rs6000-p8swap.c | 1 +
gcc/doc/extend.texi| 6 ++
.../gcc.target/powerpc/builtins-7-runnable.c | 112 +
7 files changed, 156 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/powerpc/builtins-7-runnable.c
diff --git a/gcc/config/rs6000/altivec.h b/gcc/config/rs6000/altivec.h
index 1e495e6..5a34162 100644
--- a/gcc/config/rs6000/altivec.h
+++ b/gcc/config/rs6000/altivec.h
@@ -76,6 +76,7 @@
#define vec_vor vec_or
#define vec_vpkpx vec_packpx
#define vec_vperm vec_perm
+#define vec_permxor __builtin_vec_vpermxor
#define vec_vrefp vec_re
#define vec_vrfin vec_round
#define vec_vrsqrtefp vec_rsqrte
diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
index 2759f2d..646275c 100644
--- a/gcc/config/rs6000/altivec.md
+++ b/gcc/config/rs6000/altivec.md
@@ -3827,6 +3827,29 @@
DONE;
})
+(define_expand "altivec_vpermxor"
+ [(use (match_operand:V16QI 0 "register_operand"))
+ (use (match_operand:V16QI 1 "register_operand"))
+ (use (match_operand:V16QI 2 "register_operand"))
+ (use (match_operand:V16QI 3 "register_operand"))]
+ "TARGET_P8_VECTOR"
+{
+ if (!BYTES_BIG_ENDIAN)
+{
+ /* vpermxor indexes the bytes using Big Endian numbering. If LE,
+change indexing in operand[3] to BE index. */
+ rtx be_index = gen_reg_rtx (V16QImode);
+
+ emit_insn (gen_one_cmplv16qi2 (be_index, operands[3]));
+ emit_insn (gen_crypto_vpermxor_v16qi (operands[0], operands[1],
+ operands[2], be_index));
+}
+ else
+emit_insn (gen_crypto_vpermxor_v16qi (operands[0], operands[1],
+ operands[2], operands[3]));
+ DONE;
+})
+
(define_expand "altivec_negv4sf2"
[(use (match_operand:V4SF 0 "register_operand"))
(use (match_operand:V4SF 1 "register_operand"))]
diff --git a/gcc/config/rs6000/rs6000-builtin.def
b/gcc/config/rs6000/rs6000-builtin.def
index 9942d65..1efa8b6 100644
--- a/gcc/config/rs6000/rs6000-builtin.def
+++ b/gcc/config/rs6000/rs6000-builtin.def
@@ -2008,6 +2008,8 @@ BU_P8V_AV_P (VCMPEQUD_P, "vcmpequd_p", CONST,
vector_eq_v2di_p)
BU_P8V_AV_P (VCMPGTSD_P, "vcmpgtsd_p", CONST, vector_gt_v2di_p)
BU_P8V_AV_P (VCMPGTUD_P, "vcmpgtud_p", CONST, vector_gtu_v2di_p)
+BU_P8V_AV_3 (VPERMXOR, "vpermxor", CONST, altivec_vpermxor)
+
/* ISA 2.05 overloaded 2 argument functions. */
BU_P6
[PATCH ] PR 844422 Fix FCTID, FCTIW with -mcpu=power7
GCC Maintainers: The following patch fixes an ICE when compiling the test case gcc -mcpu=power7 builtin-fctid-fctiw-runnable.c The GCC compiler now gives a message "error: builtin function ‘__builtin_fctiw’ requires the ‘-mpower8-vector’ option" and exits without generating an internal error. The patch has been tested by compiling by hand as given above. The regression testing has also been done on powerpc64-unknown-linux-gnu (Power 8 BE) powerpc64le-unknown-linux-gnu (Power 8 LE) powerpc64le-unknown-linux-gnu (Power 9 LE) with no regressions. Let me know if the patch looks OK or not. Thanks. Carl Love - gcc/ChangeLog: 2018-03-13 Carl Love PR 84422 - ICE on various builtin test functions when compiled with -mcpu=power7. * config/rs6000/rs6000-builtin.def: Change macro expansion for FCTID, FCTIW to BU_P8V_MISC_1. --- gcc/config/rs6000/rs6000-builtin.def | 12 ++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/gcc/config/rs6000/rs6000-builtin.def b/gcc/config/rs6000/rs6000-builtin.def index 9942d65..6e6dab0 100644 --- a/gcc/config/rs6000/rs6000-builtin.def +++ b/gcc/config/rs6000/rs6000-builtin.def @@ -658,6 +658,14 @@ /* Miscellaneous builtins for instructions added in ISA 2.07. These instructions do require the ISA 2.07 vector support, but they aren't vector instructions. */ +#define BU_P8V_MISC_1(ENUM, NAME, ATTR, ICODE) \ + RS6000_BUILTIN_1 (MISC_BUILTIN_ ## ENUM, /* ENUM */ \ + "__builtin_" NAME, /* NAME */ \ + RS6000_BTM_P8_VECTOR, /* MASK */ \ + (RS6000_BTC_ ## ATTR/* ATTR */ \ +| RS6000_BTC_UNARY), \ + CODE_FOR_ ## ICODE) /* ICODE */ + #define BU_P8V_MISC_3(ENUM, NAME, ATTR, ICODE) \ RS6000_BUILTIN_3 (MISC_BUILTIN_ ## ENUM, /* ENUM */ \ "__builtin_" NAME, /* NAME */ \ @@ -1881,8 +1889,8 @@ BU_VSX_OVERLOAD_X (XST,"xst") BU_VSX_OVERLOAD_X (XST_BE, "xst_be") /* 1 argument builtins pre ISA 2.04. */ -BU_FP_MISC_1 (FCTID, "fctid",CONST, lrintdfdi2) -BU_FP_MISC_1 (FCTIW, "fctiw",CONST, lrintsfsi2) +BU_P8V_MISC_1 (FCTID, "fctid",CONST, lrintdfdi2) +BU_P8V_MISC_1 (FCTIW, "fctiw",CONST, lrintsfsi2) /* 2 argument CMPB instructions added in ISA 2.05. */ BU_P6_2 (CMPB_32,"cmpb_32",CONST, cmpbsi3) -- 2.7.4
[PATCH, rs6000] PR 84422 fix sse2-pmuludq-1.c with -mcpu=power7
GCC Maintainers:
The following patch fixes an ICE when compiling the test case
gcc -mcpu=power7 sse2-pmuludq-1.c
The GCC compiler now gives a message
"error: builtin function ‘__builtin_altivec_vmuleuw’ requires the
‘-mpower8-vector’ option"
and exits without generating an internal error.
The patch has been tested by compiling by hand as given above. The
regression testing has also been done on
powerpc64-unknown-linux-gnu (Power 8 BE)
powerpc64le-unknown-linux-gnu (Power 8 LE)
powerpc64le-unknown-linux-gnu (Power 9 LE)
with no regressions.
Let me know if the patch looks OK or not. Thanks.
Carl Love
--
gcc/ChangeLog:
2018-03-13 Carl Love
PR 84422 - ICE on various builtin test functions when compiled with
-mcpu=power7.
* config/rs6000/rs6000-builtin.def: Change expansion for
VMULE[SW|UW] to BU_P8V_AV_2.
* config/rs6000/rs6000.c: Change
ALTIVEC_BUILTIN_VMULE[SW|UW] to P8V_BUILTIN_VMULE[SW|UW].
Change ALTIVEC_BUILTIN_VMULO[SW|UW] to P8V_BUILTIN_VMULO[SW|UW].
* config/rs6000/rs6000-c.c: Change
ALTIVEC_BUILTIN_VMULE[SW|UW] to P8V_BUILTIN_VMULE[SW|UW].
Change ALTIVEC_BUILTIN_VMULO[SW|UW] to P8V_BUILTIN_VMULO[SW|UW].
---
gcc/config/rs6000/rs6000-builtin.def | 8
gcc/config/rs6000/rs6000-c.c | 16
gcc/config/rs6000/rs6000.c | 12 ++--
3 files changed, 18 insertions(+), 18 deletions(-)
diff --git a/gcc/config/rs6000/rs6000-builtin.def
b/gcc/config/rs6000/rs6000-builtin.def
index 6e6dab0..9925364 100644
--- a/gcc/config/rs6000/rs6000-builtin.def
+++ b/gcc/config/rs6000/rs6000-builtin.def
@@ -1094,14 +1094,14 @@ BU_ALTIVEC_2 (VMULEUB,"vmuleub",CONST,
vec_widen_umult_even_v16qi)
BU_ALTIVEC_2 (VMULESB, "vmulesb",CONST,
vec_widen_smult_even_v16qi)
BU_ALTIVEC_2 (VMULEUH, "vmuleuh",CONST,
vec_widen_umult_even_v8hi)
BU_ALTIVEC_2 (VMULESH, "vmulesh",CONST,
vec_widen_smult_even_v8hi)
-BU_ALTIVEC_2 (VMULEUW, "vmuleuw",CONST,
vec_widen_umult_even_v4si)
-BU_ALTIVEC_2 (VMULESW, "vmulesw",CONST,
vec_widen_smult_even_v4si)
+BU_P8V_AV_2 (VMULEUW,"vmuleuw",CONST,
vec_widen_umult_even_v4si)
+BU_P8V_AV_2 (VMULESW,"vmulesw",CONST,
vec_widen_smult_even_v4si)
BU_ALTIVEC_2 (VMULOUB, "vmuloub",CONST,
vec_widen_umult_odd_v16qi)
BU_ALTIVEC_2 (VMULOSB, "vmulosb",CONST,
vec_widen_smult_odd_v16qi)
BU_ALTIVEC_2 (VMULOUH, "vmulouh",CONST,
vec_widen_umult_odd_v8hi)
BU_ALTIVEC_2 (VMULOSH, "vmulosh",CONST,
vec_widen_smult_odd_v8hi)
-BU_ALTIVEC_2 (VMULOUW, "vmulouw",CONST,
vec_widen_umult_odd_v4si)
-BU_ALTIVEC_2 (VMULOSW, "vmulosw",CONST,
vec_widen_smult_odd_v4si)
+BU_P8V_AV_2 (VMULOUW,"vmulouw",CONST,
vec_widen_umult_odd_v4si)
+BU_P8V_AV_2 (VMULOSW,"vmulosw",CONST,
vec_widen_smult_odd_v4si)
BU_ALTIVEC_2 (VNOR, "vnor", CONST, norv4si3)
BU_ALTIVEC_2 (VOR, "vor",CONST, iorv4si3)
BU_ALTIVEC_2 (VPKUHUM, "vpkuhum",CONST, altivec_vpkuhum)
diff --git a/gcc/config/rs6000/rs6000-c.c b/gcc/config/rs6000/rs6000-c.c
index cc8e4e1..174ecb2 100644
--- a/gcc/config/rs6000/rs6000-c.c
+++ b/gcc/config/rs6000/rs6000-c.c
@@ -2231,9 +2231,9 @@ const struct altivec_builtin_types
altivec_overloaded_builtins[] = {
RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI,
RS6000_BTI_unsigned_V8HI, 0 },
{ ALTIVEC_BUILTIN_VEC_MULE, ALTIVEC_BUILTIN_VMULESH,
RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
- { ALTIVEC_BUILTIN_VEC_MULE, ALTIVEC_BUILTIN_VMULESW,
+ { ALTIVEC_BUILTIN_VEC_MULE, P8V_BUILTIN_VMULESW,
RS6000_BTI_V2DI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
- { ALTIVEC_BUILTIN_VEC_MULE, ALTIVEC_BUILTIN_VMULEUW,
+ { ALTIVEC_BUILTIN_VEC_MULE, P8V_BUILTIN_VMULEUW,
RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V4SI,
RS6000_BTI_unsigned_V4SI, 0 },
{ ALTIVEC_BUILTIN_VEC_VMULEUB, ALTIVEC_BUILTIN_VMULEUB,
@@ -2244,9 +2244,9 @@ const struct altivec_builtin_types
altivec_overloaded_builtins[] = {
RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI,
RS6000_BTI_unsigned_V8HI, 0 },
{ ALTIVEC_BUILTIN_VEC_VMULESH, ALTIVEC_BUILTIN_VMULESH,
RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
- { ALTIVEC_BUILTIN_VEC_VMULEUW, ALTIVEC_BUILTIN_VMULEUW,
+ { ALTIVEC_BUILTIN_VEC_VMULEUW, P8V_BUILTIN_VMULEUW,
RS6000_BTI_V2DI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
- { ALTIVEC_BUILTIN_VEC_VMULESW, ALTIVEC_BUILTIN_VMULESW,
+ { ALTIVEC_BUILTIN_VEC_VMULESW, P8V_BUILTIN_VMULESW,
RS6000_BTI_V2DI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
{ ALTIVEC_BUILTIN_VEC_MULO, ALTIVEC_BUILTIN_VMULOUB,
RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI,
RS6000_BTI_un
C++ PATCH to fix an ICE on invalid with OVERLOADs (PR c++/84854)
cxx_constant_value doesn't understand template codes, and neither it
understands OVERLOADs, so if we pass an OVERLOAD to it, we crash. Here
instantiate_non_dependent_expr got an OVERLOAD, but since it calls
is_nondependent_constant_expression which checks type_unknown_p, it left the
expression as it was. We can't use is_nondependent_constant_expression in
finish_if_stmt_cond because i_n_c_e checks is_constant_expression and that is
not suitable here; we'd miss diagnostics. So I did the following; I think we
should reject the testcase with an error.
Bootstrapped/regtested on x86_64-linux, ok for trunk?
2018-03-14 Marek Polacek
PR c++/84854
* semantics.c (finish_if_stmt_cond): Give error if the condition
is an overloaded function with no contextual type information.
* g++.dg/cpp1z/constexpr-if15.C: New test.
diff --git gcc/cp/semantics.c gcc/cp/semantics.c
index fdf37bea770..a056e9445e9 100644
--- gcc/cp/semantics.c
+++ gcc/cp/semantics.c
@@ -735,8 +735,16 @@ finish_if_stmt_cond (tree cond, tree if_stmt)
&& require_constant_expression (cond)
&& !value_dependent_expression_p (cond))
{
- cond = instantiate_non_dependent_expr (cond);
- cond = cxx_constant_value (cond, NULL_TREE);
+ if (type_unknown_p (cond))
+ {
+ cxx_incomplete_type_error (cond, TREE_TYPE (cond));
+ cond = error_mark_node;
+ }
+ else
+ {
+ cond = instantiate_non_dependent_expr (cond);
+ cond = cxx_constant_value (cond, NULL_TREE);
+ }
}
finish_cond (&IF_COND (if_stmt), cond);
add_stmt (if_stmt);
diff --git gcc/testsuite/g++.dg/cpp1z/constexpr-if15.C
gcc/testsuite/g++.dg/cpp1z/constexpr-if15.C
index e69de29bb2d..c819b3e3a07 100644
--- gcc/testsuite/g++.dg/cpp1z/constexpr-if15.C
+++ gcc/testsuite/g++.dg/cpp1z/constexpr-if15.C
@@ -0,0 +1,11 @@
+// PR c++/84854
+// { dg-options -std=c++17 }
+
+constexpr int foo () { return 1; }
+constexpr int foo (int) { return 2; }
+
+template
+void a()
+{
+ if constexpr(foo) { }; // { dg-error "overloaded function" }
+}
Marek
[PATCH] Document some arch-specific operand modifiers
Hi,
here's an attempt to document some of the inline asm operand modifiers
which make sense and which get used so that people can find what they
mean in the docs.
This is my first gcc patch so there might be clumsiness ahead. :)
Thanks,
Boris.
gcc/Changelog:
2018-03-14 Borislav Petkov
* gcc/doc/extend.texi: document some arch-specific asm operand modifiers
and sort entries.
* gcc/config/i386/i386.c: fix typo.
---
gcc/ChangeLog | 6
gcc/config/i386/i386.c | 2 +-
gcc/doc/extend.texi| 79 +-
3 files changed, 60 insertions(+), 27 deletions(-)
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 4d56c473e68b..c3d83a2fe15c 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2018-03-14 Borislav Petkov
+
+ * gcc/doc/extend.texi: document some arch-specific asm operand modifiers
+ and sort entries.
+ * gcc/config/i386/i386.c: fix typo.
+
2018-01-21 Bill Schmidt
David Edelsohn
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index 72d25ae4f722..da634afa1e08 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -17847,7 +17847,7 @@ print_reg (rtx x, int code, FILE *file)
F,f -- likewise, but for floating-point.
O -- if HAVE_AS_IX86_CMOV_SUN_SYNTAX, expand to "w.", "l." or "q.",
otherwise nothing
- R -- print embeded rounding and sae.
+ R -- print embedded rounding and sae.
r -- print only sae.
z -- print the opcode suffix for the size of the current operand.
Z -- likewise, with special suffixes for x87 instructions.
diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
index dce808f1eab1..321576bac292 100644
--- a/gcc/doc/extend.texi
+++ b/gcc/doc/extend.texi
@@ -9224,14 +9224,14 @@ top:
asm volatile goto ("some assembler instructions here"
: /* No outputs. */
- : "q" (iInt), "X" (sizeof(unsigned char) + 1)
+ : "q" (iInt), "X" (sizeof(unsigned char) + 1), "i" (42)
: /* No clobbers. */
: top);
@}
@end example
-With no modifiers, this is what the output from the operands would be for the
-@samp{att} and @samp{intel} dialects of assembler:
+With no modifiers, this is what the output from the operands would be
+for the @samp{att} and @samp{intel} dialects of assembler:
@multitable {Operand} {$.L2} {OFFSET FLAT:.L2}
@headitem Operand @tab @samp{att} @tab @samp{intel}
@@ -9241,55 +9241,82 @@ With no modifiers, this is what the output from the
operands would be for the
@item @code{%1}
@tab @code{$2}
@tab @code{2}
-@item @code{%2}
-@tab @code{$.L2}
-@tab @code{OFFSET FLAT:.L2}
+@item @code{%3}
+@tab @code{$.L3}
+@tab @code{OFFSET FLAT:.L3}
@end multitable
The table below shows the list of supported modifiers and their effects.
@multitable {Modifier} {Print the opcode suffix for the size of th} {Operand}
{@samp{att}} {@samp{intel}}
@headitem Modifier @tab Description @tab Operand @tab @samp{att} @tab
@samp{intel}
-@item @code{z}
-@tab Print the opcode suffix for the size of the current integer operand (one
of @code{b}/@code{w}/@code{l}/@code{q}).
-@tab @code{%z0}
-@tab @code{l}
-@tab
+@item @code{a}
+@tab Print an absolute memory reference.
+@tab @code{%A0}
+@tab @code{*%rax}
+@tab @code{rax}
@item @code{b}
@tab Print the QImode name of the register.
@tab @code{%b0}
@tab @code{%al}
@tab @code{al}
+@item @code{c}
+@tab Require a constant operand and print the constant expression with no
punctuation.
+@tab @code{%c1}
+@tab @code{2}
+@tab @code{2}
+@item @code{E}
+@tab Print the address in Double Integer (DImode) mode (8 bytes) when the
target is 64-bit.
+Otherwise mode is unspecified (VOIDmode).
+@tab @code{%E1}
+@tab @code{%(rax)}
+@tab @code{[rax]}
@item @code{h}
@tab Print the QImode name for a ``high'' register.
@tab @code{%h0}
@tab @code{%ah}
@tab @code{ah}
-@item @code{w}
-@tab Print the HImode name of the register.
-@tab @code{%w0}
-@tab @code{%ax}
-@tab @code{ax}
+@item @code{H}
+@tab Add 8 bytes to an offsettable memory reference. Useful when accessing the
+high 8 bytes of SSE values. For a memref in (%rax), it generates
+@tab @code{%H0}
+@tab @code{8(%rax)}
+@tab @code{8[rax]}
@item @code{k}
@tab Print the SImode name of the register.
@tab @code{%k0}
@tab @code{%eax}
@tab @code{eax}
+@item @code{l}
+@tab Print the label name with no punctuation.
+@tab @code{%l3}
+@tab @code{.L3}
+@tab @code{.L3}
+@item @code{p}
+@tab Print raw symbol name (without syntax-specific prefixes).
+@tab @code{%p2}
+@tab @code{42}
+@tab @code{42}
+@item @code{P}
+@tab If used for a function, print the PLT suffix and generate PIC code.
+For example, emit @code{foo@@PLT} instead of 'foo' for the function
+foo(). If used for a constant, drop all syntax-specific prefixes and
+issue the bare constant. See @code{p} above.
@item @code{q}
@tab Print the DImode name of the register.
@tab @code{%q0}
@tab @code{%rax}
@tab @code{rax}
-@item @code{l}
-@tab Print the label name w
Re: [PATCH,rs6000] Add vec_permxor support.
Hi! On Wed, Mar 14, 2018 at 08:17:42AM -0700, Carl Love wrote: > 2018-03-14 Carl Love > > * config/rs6000/rs6000-c.c: Add macro definitions for > ALTIVEC_BUILTIN_VEC_PERMXOR. > * config/rs6000/rs6000.h: Add #define for vec_permxor builtin. > * config/rs6000/rs6000-builtin.def: Add macro expansions for VPERMXOR. > * config/rs6000/altivec.md (altivec-vpermxor): New define expand. Underscore instead of dash? The changelog shoould mention the actual name of things... This helps grep and friends. > Add UNSPEC_VNOR, define_insn altivec_vnor_v16qi3. Delete this last line? > * config/rs6000/rs6000-p8swap.c (rtx_is_swappable_p): Add case > UNSPEC_VPERMXOR. > * config/doc/extend.texi: Add prototypes for vec_permxor. > > gcc/testsuite/ChangeLog: > > 2018-03-13 Carl Love > > * gcc.target/powerpc/builtins-7-runnable.c: Add tests for vec_permxor. This is a new file, the changelog should say that. Okay for trunk with that. Thanks! Segher
[PATCH] Add test-case (PR ipa/84805).
Hi.
This is a new test-case isolated from libreoffice.
Patch can bootstrap on ppc64le-redhat-linux and survives regression tests.
I'm going to install it.
Martin
gcc/testsuite/ChangeLog:
2018-03-14 Martin Liska
PR ipa/8480
* g++.dg/lto/pr84805_0.C: New test.
* g++.dg/lto/pr84805_1.C: New test.
* g++.dg/lto/pr84805_2.C: New test.
---
gcc/testsuite/g++.dg/lto/pr84805_0.C | 151 +++
gcc/testsuite/g++.dg/lto/pr84805_1.C | 15
gcc/testsuite/g++.dg/lto/pr84805_2.C | 131 ++
3 files changed, 297 insertions(+)
create mode 100644 gcc/testsuite/g++.dg/lto/pr84805_0.C
create mode 100644 gcc/testsuite/g++.dg/lto/pr84805_1.C
create mode 100644 gcc/testsuite/g++.dg/lto/pr84805_2.C
diff --git a/gcc/testsuite/g++.dg/lto/pr84805_0.C b/gcc/testsuite/g++.dg/lto/pr84805_0.C
new file mode 100644
index 000..c34c6340201
--- /dev/null
+++ b/gcc/testsuite/g++.dg/lto/pr84805_0.C
@@ -0,0 +1,151 @@
+// { dg-lto-do link }
+// { dg-lto-options {{-O2 -fPIC -shared -flto}} }
+
+template < typename _Tp, _Tp __v > struct integral_constant {
+ static constexpr _Tp value = __v;
+};
+typedef integral_constant< bool, false > false_type;
+struct __is_void_helper : false_type {};
+struct is_void : __is_void_helper {};
+template < typename > struct is_array : false_type {};
+namespace __gnu_cxx {
+enum _Lock_policy { _S_single, _S_mutex, _S_atomic };
+const _Lock_policy __default_lock_policy = _S_atomic;
+} namespace std {
+using __gnu_cxx::_Lock_policy;
+using __gnu_cxx::__default_lock_policy;
+template < _Lock_policy = __default_lock_policy > class _Sp_counted_base;
+template < typename, _Lock_policy = __default_lock_policy > class __shared_ptr;
+template < _Lock_policy > class __shared_count { _Sp_counted_base<> *_M_pi; };
+template < typename _Tp, _Lock_policy, bool = is_array< _Tp >::value,
+ bool = is_void::value >
+class __shared_ptr_access {};
+template < typename _Tp, _Lock_policy _Lp >
+class __shared_ptr : __shared_ptr_access< _Tp, _Lp > {
+ using element_type = _Tp;
+ element_type *_M_ptr;
+ __shared_count< _Lp > _M_refcount;
+};
+template < typename _Tp > class shared_ptr : __shared_ptr< _Tp > {};
+} typedef struct _rtl_String rtl_String;
+typedef struct _rtl_uString rtl_uString;
+namespace rtl {
+class OString {
+ rtl_String *pData;
+};
+} using rtl::OString;
+namespace rtl {
+class OUString {
+ rtl_uString *pData;
+};
+} using rtl::OUString;
+namespace tools {
+template < typename T > class SvRef {
+T *pObj;
+};
+} class SvRefBase {
+ unsigned nRefCount : 31;
+ unsigned bNoDelete : 1;
+
+protected:
+ virtual ~SvRefBase();
+};
+class ErrCode {
+ unsigned m_value;
+};
+class SvStream;
+class SfxMedium;
+struct strong_int {
+ unsigned short m_value;
+};
+typedef strong_int LanguageType;
+class SotObject : virtual SvRefBase {
+ unsigned short nOwnerLockCount;
+ bool bInClose;
+};
+class BaseStorage;
+class SotStorage : virtual SotObject {
+ BaseStorage *m_pOwnStg;
+ SvStream *m_pStorStm;
+ ErrCode m_nError;
+ OUString m_aName;
+ bool m_bIsRoot;
+ bool m_bDelStm;
+ OString m_aKey;
+ int m_nVersion;
+};
+class ScDocument;
+class ScAddress {
+ int nRow;
+ short nCol;
+ short nTab;
+};
+enum XclBiff {};
+enum XclOutput {};
+enum BiffTyp {};
+class SharedFormulaBuffer;
+class ExtNameBuff;
+class ExtSheetBuffer;
+class ExcelToSc;
+class XclImpColRowSettings;
+struct RootData {
+ BiffTyp eDateiTyp;
+ ExtSheetBuffer *pExtSheetBuff;
+ SharedFormulaBuffer *pShrfmlaBuff;
+ ExtNameBuff *pExtNameBuff;
+ ExcelToSc *pFmlaConverter;
+ XclImpColRowSettings *pColRowBuff;
+};
+class ScEditEngineDefaulter;
+class ScHeaderEditEngine;
+class EditEngine;
+class ScExtDocOptions;
+class XclFontPropSetHelper;
+class XclChPropSetHelper;
+class XclTracer;
+struct XclRootData { // { dg-lto-warning "8: type 'struct XclRootData' violates the C\\+\\+ One Definition Rule" }
+ typedef std::shared_ptr< ScEditEngineDefaulter > ScEEDefaulterRef;
+ typedef std::shared_ptr< ScHeaderEditEngine > ScHeaderEERef;
+ typedef std::shared_ptr< EditEngine > EditEngineRef;
+ typedef std::shared_ptr< XclFontPropSetHelper > XclFontPropSetHlpRef;
+ typedef std::shared_ptr< XclChPropSetHelper > XclChPropSetHlpRef;
+ typedef std::shared_ptr< ScExtDocOptions > ScExtDocOptRef;
+ typedef std::shared_ptr< XclTracer > XclTracerRef;
+ typedef std::shared_ptr< RootData > RootDataRef;
+ XclBiff meBiff;
+ XclOutput meOutput;
+ SfxMedium &mrMedium;
+ tools::SvRef< SotStorage > mxRootStrg;
+ ScDocument &mrDoc;
+ OUString maDocUrl;
+ OUString maBasePath;
+ OUString maUserName;
+ OUString maDefPassword;
+ unsigned short meTextEnc;
+ LanguageType meSysLang;
+ LanguageType meDocLang;
+ LanguageType meUILang;
+ short mnDefApiScript;
+ ScAddress maScMaxPos;
+ ScAddress maXclMaxPos;
+ ScAddress maMaxPos;
+ ScEEDefaulterRef mxEditEngine;
+ ScHeaderEERef mxHFEditEngine;
+ EditEngineRef mxDrawEditEng;
+ XclFontPropSetHlpRe
Re: [PATCH][AArch64][1/3] PR target/84164: Simplify subreg + redundant AND-immediate
On Fri, Mar 02, 2018 at 10:34:22AM -0700, Jeff Law wrote: > >>> 2018-02-12 Kyrylo Tkachov > >>> > >>> PR target/84164 > >>> * simplify-rtx.c (simplify_truncation): Simplify truncation of > >>> masking > >>> operation. > >>> * config/aarch64/aarch64.md (*aarch64_reg_3_neg_mask2): > >>> Use simplify_gen_unary creating a SUBREG. > >>> (*aarch64_reg_3_minus_mask): Likewise. > >>> (*aarch64__reg_di3_mask2): Use const_int_operand predicate > >>> for operand 3. > >>> > >>> 2018-02-12 Kyrylo Tkachov > >>> > >>> PR target/84164 > >>> * gcc.c-torture/compile/pr84164.c: New test. > Sorry. I suspect I dropped this from my inbox when it had the AArch64 > marker -- I didn't realize it had a target independent component. > > The simplify-rtx bits are fine. The version in simplify_truncation is > much better than the original in simplify_subreg (which I think needed > to verify that you were looking at the lowpart before optimizing). Isn't that a stage1 material though? I fear given the amount of changes that needed to be done for it on i386.md that similar amount of work would be needed on many other targets, especially if they have less extensive testsuite coverage it might take a while to discover it. Jakub
[PATCH][AARCH64] PR target/84521 Fix frame pointer corruption with -fomit-frame-pointer with __builtin_setjmp
Hi
This patch is another partial fix for PR 84521. This is adding a
definition to one of the target hooks used in the SJLJ implemetation so
that AArch64 defines the hard_frame_pointer_rtx as the
TARGET_BUILTIN_SETJMP_FRAME_VALUE. As pointed out by Wilco there is
still a lot more work to be done for these builtins in the future.
Testing: Bootstrapped and regtested on aarch64-none-linux-gnu and added
new test.
Is this ok for trunk?
Sudi
*** gcc/ChangeLog ***
2018-03-14 Sudakshina Das
* builtins.c (expand_builtin_setjmp_receiver): Update condition
to restore frame pointer.
* config/aarch64/aarch64.h (DONT_USE_BUILTIN_SETJMP): Update
comment.
* config/aarch64/aarch64.c (aarch64_builtin_setjmp_frame_value):
New.
(TARGET_BUILTIN_SETJMP_FRAME_VALUE): Define.
*** gcc/testsuite/ChangeLog ***
2018-03-14 Sudakshina Das
* gcc.c-torture/execute/pr84521.c: New test.
diff --git a/gcc/builtins.c b/gcc/builtins.c
index 85affa7..640f1a9 100644
--- a/gcc/builtins.c
+++ b/gcc/builtins.c
@@ -898,7 +898,8 @@ expand_builtin_setjmp_receiver (rtx receiver_label)
/* Now put in the code to restore the frame pointer, and argument
pointer, if needed. */
- if (! targetm.have_nonlocal_goto ())
+ if (! targetm.have_nonlocal_goto ()
+ && targetm.builtin_setjmp_frame_value () != hard_frame_pointer_rtx)
{
/* First adjust our frame pointer to its actual value. It was
previously set to the start of the virtual area corresponding to
diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h
index e3c52f6..7a21c14 100644
--- a/gcc/config/aarch64/aarch64.h
+++ b/gcc/config/aarch64/aarch64.h
@@ -474,7 +474,9 @@ extern unsigned aarch64_architecture_version;
#define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, R4_REGNUM)
#define EH_RETURN_HANDLER_RTX aarch64_eh_return_handler_rtx ()
-/* Don't use __builtin_setjmp until we've defined it. */
+/* Don't use __builtin_setjmp until we've defined it.
+ CAUTION: This macro is only used during exception unwinding.
+ Don't fall for its name. */
#undef DONT_USE_BUILTIN_SETJMP
#define DONT_USE_BUILTIN_SETJMP 1
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index e1fb87f..e7ac0fe 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -12128,6 +12128,13 @@ aarch64_expand_builtin_va_start (tree valist, rtx nextarg ATTRIBUTE_UNUSED)
expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
}
+/* Implement TARGET_BUILTIN_SETJMP_FRAME_VALUE. */
+static rtx
+aarch64_builtin_setjmp_frame_value (void)
+{
+ return hard_frame_pointer_rtx;
+}
+
/* Implement TARGET_GIMPLIFY_VA_ARG_EXPR. */
static tree
@@ -17505,6 +17512,9 @@ aarch64_run_selftests (void)
#undef TARGET_FOLD_BUILTIN
#define TARGET_FOLD_BUILTIN aarch64_fold_builtin
+#undef TARGET_BUILTIN_SETJMP_FRAME_VALUE
+#define TARGET_BUILTIN_SETJMP_FRAME_VALUE aarch64_builtin_setjmp_frame_value
+
#undef TARGET_FUNCTION_ARG
#define TARGET_FUNCTION_ARG aarch64_function_arg
diff --git a/gcc/testsuite/gcc.c-torture/execute/pr84521.c b/gcc/testsuite/gcc.c-torture/execute/pr84521.c
new file mode 100644
index 000..76b10d2
--- /dev/null
+++ b/gcc/testsuite/gcc.c-torture/execute/pr84521.c
@@ -0,0 +1,49 @@
+/* { dg-require-effective-target indirect_jumps } */
+
+#include
+
+jmp_buf buf;
+
+int uses_longjmp (void)
+{
+ __builtin_longjmp (buf, 1);
+}
+
+int gl;
+void after_longjmp (void)
+{
+ gl = 5;
+}
+
+int
+test_1 (int n)
+{
+ volatile int *p = alloca (n);
+ if (__builtin_setjmp (buf))
+{
+ after_longjmp ();
+}
+ else
+{
+ uses_longjmp ();
+}
+
+ return 0;
+}
+
+int __attribute__ ((optimize ("no-omit-frame-pointer")))
+test_2 (int n)
+{
+ int i;
+ int *ptr = (int *)__builtin_alloca (sizeof (int) * n);
+ for (i = 0; i < n; i++)
+ptr[i] = i;
+ test_1 (n);
+ return 0;
+}
+
+int main (int argc, const char **argv)
+{
+ __builtin_memset (&buf, 0xaf, sizeof (buf));
+ test_2 (100);
+}
Re: C++ PATCH to fix an ICE on invalid with OVERLOADs (PR c++/84854)
On Wed, Mar 14, 2018 at 11:59 AM, Marek Polacek wrote:
> cxx_constant_value doesn't understand template codes, and neither it
> understands OVERLOADs, so if we pass an OVERLOAD to it, we crash. Here
> instantiate_non_dependent_expr got an OVERLOAD, but since it calls
> is_nondependent_constant_expression which checks type_unknown_p, it left the
> expression as it was. We can't use is_nondependent_constant_expression in
> finish_if_stmt_cond because i_n_c_e checks is_constant_expression and that is
> not suitable here; we'd miss diagnostics. So I did the following; I think we
> should reject the testcase with an error.
>
> Bootstrapped/regtested on x86_64-linux, ok for trunk?
>
> 2018-03-14 Marek Polacek
>
> PR c++/84854
> * semantics.c (finish_if_stmt_cond): Give error if the condition
> is an overloaded function with no contextual type information.
>
> * g++.dg/cpp1z/constexpr-if15.C: New test.
>
> diff --git gcc/cp/semantics.c gcc/cp/semantics.c
> index fdf37bea770..a056e9445e9 100644
> --- gcc/cp/semantics.c
> +++ gcc/cp/semantics.c
> @@ -735,8 +735,16 @@ finish_if_stmt_cond (tree cond, tree if_stmt)
>&& require_constant_expression (cond)
>&& !value_dependent_expression_p (cond))
> {
> - cond = instantiate_non_dependent_expr (cond);
> - cond = cxx_constant_value (cond, NULL_TREE);
> + if (type_unknown_p (cond))
> + {
> + cxx_incomplete_type_error (cond, TREE_TYPE (cond));
> + cond = error_mark_node;
I think I'd prefer to skip this block when type_unknown_p, and leave
error handling up to the code shared with regular if.
Jason
Re: [x86,avx] Fix __builtin_cpu_supports for icelake and cannonlake isa
Hello Julia! > On 14 Mar 2018, at 10:48, Koval, Julia wrote: > > Gentle ping. Your patch is OK for main trunk. — Thanks, K >> -Original Message- >> From: Koval, Julia >> Sent: Monday, February 12, 2018 10:57 AM >> To: Kirill Yukhin >> Cc: 'GCC Patches' >> Subject: RE: [x86,avx] Fix __builtin_cpu_supports for icelake and cannonlake >> isa >> >> Hi, >> >> There is no PR for this. This builtin was just missing for all new cpus. >> >> Thanks, >> Julia >> >>> -Original Message- >>> From: Kirill Yukhin [mailto:kirill.yuk...@gmail.com] >>> Sent: Monday, February 12, 2018 7:19 AM >>> To: Koval, Julia >>> Cc: 'GCC Patches' >>> Subject: Re: [x86,avx] Fix __builtin_cpu_supports for icelake and cannonlake >> isa >>> >>> Hello Julia. >>> >>> On 15 Jan 08:28, Koval, Julia wrote: Hi, This patch fixes subj. Ok for trunk? gcc/ * config/i386/i386.c (F_AVX512VBMI2, F_GFNI, F_VPCLMULQDQ, >>> F_AVX512VNNI, F_AVX512BITALG): New. gcc/testsuite/ * gcc.target/i386/builtin_target.c (check_intel_cpu_model): Add >>> cannonlake. (check_features): Add avx512vbmi2, gfni, vpclmulqdq, avx512vnni, avx512bitalg. libgcc/ * config/i386/cpuinfo.c (get_available_features): Add >>> FEATURE_AVX512VBMI2, FEATURE_GFNI, FEATURE_VPCLMULQDQ, FEATURE_AVX512VNNI, >>> FEATURE_AVX512BITALG. * config/i386/cpuinfo.h (processor_features) Add >>> FEATURE_AVX512VBMI2, FEATURE_GFNI, FEATURE_VPCLMULQDQ, FEATURE_AVX512VNNI, >>> FEATURE_AVX512BITALG. >>> >>> Could you pls mention, which problem does your patch fix? >>> >>> -- >>> Thanks, K
C++ PATCH for c++/83916, C++17 ICE with template template parameters
In the wg21.link/P0522 change to template template parameter matching,
we ran into trouble with this testcase: when we try to form
TTC, we need to convert TA to TC, and try to tsubst TC to
produce the real desired type. But trying to look up TC in the args
for TTC fails, and indeed makes no sense. Even if we passed in more
args somehow, what we have in outer_args are args for A, not for C, so
that wouldn't help.
I dealt with this situation by recognizing that we are dealing with
multiple levels of template parms and only have a single level of
template args, so we can't possibly get the right answer, so we
shouldn't do any substitution.
Tested x86_64-pc-linux-gnu, applying to trunk.
commit 31437c878831d15bbccbd8a891a074aacfdeec10
Author: Jason Merrill
Date: Wed Mar 14 11:44:50 2018 -0400
PR c++/83916 - ICE with template template parameters.
* pt.c (convert_template_argument): Don't substitute into type of
non-type parameter if we don't have enough arg levels.
(unify): Likewise.
diff --git a/gcc/cp/pt.c b/gcc/cp/pt.c
index d720c33cf0a..14321816cde 100644
--- a/gcc/cp/pt.c
+++ b/gcc/cp/pt.c
@@ -7974,7 +7974,11 @@ convert_template_argument (tree parm,
{
tree t = TREE_TYPE (parm);
- if (tree a = type_uses_auto (t))
+ if (TEMPLATE_PARM_LEVEL (get_template_parm_index (parm))
+ > TMPL_ARGS_DEPTH (args))
+ /* We don't have enough levels of args to do any substitution. This
+ can happen in the context of -fnew-ttp-matching. */;
+ else if (tree a = type_uses_auto (t))
{
t = do_auto_deduction (t, arg, a, complain, adc_unify, args);
if (t == error_mark_node)
@@ -21224,14 +21228,22 @@ unify (tree tparms, tree targs, tree parm, tree arg, int strict,
template-parameter exactly, except that a template-argument
deduced from an array bound may be of any integral type.
The non-type parameter might use already deduced type parameters. */
- ++processing_template_decl;
- tparm = tsubst (TREE_TYPE (parm), targs, 0, NULL_TREE);
- --processing_template_decl;
- if (tree a = type_uses_auto (tparm))
+ tparm = TREE_TYPE (parm);
+ if (TEMPLATE_PARM_LEVEL (parm) > TMPL_ARGS_DEPTH (targs))
+ /* We don't have enough levels of args to do any substitution. This
+ can happen in the context of -fnew-ttp-matching. */;
+ else
{
- tparm = do_auto_deduction (tparm, arg, a, complain, adc_unify);
- if (tparm == error_mark_node)
- return 1;
+ ++processing_template_decl;
+ tparm = tsubst (tparm, targs, tf_none, NULL_TREE);
+ --processing_template_decl;
+
+ if (tree a = type_uses_auto (tparm))
+ {
+ tparm = do_auto_deduction (tparm, arg, a, complain, adc_unify);
+ if (tparm == error_mark_node)
+ return 1;
+ }
}
if (!TREE_TYPE (arg))
diff --git a/gcc/testsuite/g++.dg/template/ttp31.C b/gcc/testsuite/g++.dg/template/ttp31.C
new file mode 100644
index 000..ff3f1f5c3ac
--- /dev/null
+++ b/gcc/testsuite/g++.dg/template/ttp31.C
@@ -0,0 +1,10 @@
+// PR c++/83916
+// { dg-do compile { target c++11 } }
+
+template class TTA, TA... VA>
+struct A { };
+
+template class TTC, TC... VC>
+struct C : A { };
diff --git a/gcc/testsuite/g++.dg/template/ttp32.C b/gcc/testsuite/g++.dg/template/ttp32.C
new file mode 100644
index 000..a96a62d332f
--- /dev/null
+++ b/gcc/testsuite/g++.dg/template/ttp32.C
@@ -0,0 +1,10 @@
+// PR c++/83916
+// { dg-do compile { target c++17 } }
+
+template class TTA, TA... VA>
+struct A { };
+
+template class TTC, TC... VC>
+struct C : A { };
[PATCH v2, rs6000] Remove unused (and incorrect) code for internal store and load operations
Thank you for feedback and discussion regarding my first draft of this
patch with Segher Boessenkool and Bill Schmidt. This revision of the
patch differs from the first in the following regards:
1. I have also removed the vector_altivec_load_ and
vectore_altivec_store_ expansions from vector.md.
2. I have removed the unused rs6000_address_for_altivec function
from rs6000.c.
I have once again bootstrapped and regression tested on both little-
endian and big-endian targets. The remainder of this description is
borrowed from my initial submission of the patch.
While working to assure rs6000 documentation of built-in functions is
consistent with the implementation of built-in functions, I discovered
some apparent typographic errors in the definitions of the
ST_INTERNAL_4sf and ST_INTERNAL_2df built-in functions. As I endeavored
to fix these definitions and write test cases to prove that I had
properly fixed them, I discovered that these functions are no longer in
use.
This patch removes the unnecessary definitions and related back-end
functions. This has bootstrapped and tested without regressions on both
powerpc64le-unknown-linux (P8) and on powerpc-linux (P7 big-endian, with
both -m32 and -m64 target options).
Is this patch ok for trunk?
gcc/ChangeLog:
2018-03-14 Kelvin Nilsen
* config/rs6000/rs6000-builtin.def: Remove various BU_ALTIVEC_X
macro expansions for definition of ST_INTERNAL_ and
LD_INTERNAL_ builtins.
* config/rs6000/rs6000-protos.h (rs6000_address_for_altivec):
Remove prototype.
* config/rs6000/rs6000.c (altivec_expand_ld_builtin): Delete this
function.
(altivec_expand_st_builtin): Likewise.
(altivec_expand_builtin): Remove calls to deleted functions.
(rs6000_address_for_altivec): Delete this function.
* config/rs6000/vector.md: Remove expands for
vector_altivec_load_ and vector_altivec_store_.
Index: gcc/config/rs6000/rs6000-builtin.def
===
--- gcc/config/rs6000/rs6000-builtin.def(revision 258338)
+++ gcc/config/rs6000/rs6000-builtin.def(working copy)
@@ -1210,20 +1210,6 @@ BU_ALTIVEC_P (VCMPGTSB_P, "vcmpgtsb_p", CONST,
BU_ALTIVEC_P (VCMPGTUB_P, "vcmpgtub_p",CONST, vector_gtu_v16qi_p)
/* AltiVec builtins that are handled as special cases. */
-BU_ALTIVEC_X (ST_INTERNAL_4si, "st_internal_4si", MEM)
-BU_ALTIVEC_X (LD_INTERNAL_4si, "ld_internal_4si", MEM)
-BU_ALTIVEC_X (ST_INTERNAL_8hi, "st_internal_8hi", MEM)
-BU_ALTIVEC_X (LD_INTERNAL_8hi, "ld_internal_8hi", MEM)
-BU_ALTIVEC_X (ST_INTERNAL_16qi,"st_internal_16qi", MEM)
-BU_ALTIVEC_X (LD_INTERNAL_16qi,"ld_internal_16qi", MEM)
-BU_ALTIVEC_X (ST_INTERNAL_4sf, "st_internal_16qi", MEM)
-BU_ALTIVEC_X (LD_INTERNAL_4sf, "ld_internal_4sf", MEM)
-BU_ALTIVEC_X (ST_INTERNAL_2df, "st_internal_4sf", MEM)
-BU_ALTIVEC_X (LD_INTERNAL_2df, "ld_internal_2df", MEM)
-BU_ALTIVEC_X (ST_INTERNAL_2di, "st_internal_2di", MEM)
-BU_ALTIVEC_X (LD_INTERNAL_2di, "ld_internal_2di", MEM)
-BU_ALTIVEC_X (ST_INTERNAL_1ti, "st_internal_1ti", MEM)
-BU_ALTIVEC_X (LD_INTERNAL_1ti, "ld_internal_1ti", MEM)
BU_ALTIVEC_X (MTVSCR, "mtvscr", MISC)
BU_ALTIVEC_X (MFVSCR, "mfvscr", MISC)
BU_ALTIVEC_X (DSSALL, "dssall", MISC)
Index: gcc/config/rs6000/rs6000-protos.h
===
--- gcc/config/rs6000/rs6000-protos.h (revision 258338)
+++ gcc/config/rs6000/rs6000-protos.h (working copy)
@@ -162,7 +162,6 @@ extern void rs6000_emit_parity (rtx, rtx);
extern rtx rs6000_machopic_legitimize_pic_address (rtx, machine_mode,
rtx);
extern rtx rs6000_address_for_fpconvert (rtx);
-extern rtx rs6000_address_for_altivec (rtx);
extern rtx rs6000_allocate_stack_temp (machine_mode, bool, bool);
extern int rs6000_loop_align (rtx);
extern void rs6000_split_logical (rtx [], enum rtx_code, bool, bool, bool);
Index: gcc/config/rs6000/rs6000.c
===
--- gcc/config/rs6000/rs6000.c (revision 258338)
+++ gcc/config/rs6000/rs6000.c (working copy)
@@ -15183,127 +15183,7 @@ rs6000_expand_ternop_builtin (enum insn_code icode
return target;
}
-/* Expand the lvx builtins. */
-static rtx
-altivec_expand_ld_builtin (tree exp, rtx target, bool *expandedp)
-{
- tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
- unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
- tree arg0;
- machine_mode tmode, mode0;
- rtx pat, op0;
- enum insn_code icode;
- switch (fcode)
-{
-case ALTIVEC_BUILTIN_LD_INTERNAL_16qi:
- icode = CODE_FOR_vector_altivec_load_v16qi;
- break;
-case ALTIVEC_BUILTIN_LD_INTERNAL_8hi:
- icode = CODE_FOR_vector_altivec_load_v8hi;
- break;
-case ALTIVEC_BUILTIN_LD_INTERNAL_4si:
- icode = C
Re: RFA (make_dispatcher_decl): PATCH for c++/83911, ICE with multiversioned constructor
Ping On Fri, Mar 2, 2018 at 1:23 PM, Jason Merrill wrote: > As I mentioned in the PR, the problem here is that we're replacing a > constructor with a dispatcher function which doesn't look much like a > constructor. This patch adjusts make_dispatcher_decl to make it look > more like the functions it dispatches to, but other things are certain > to break for similar reasons down the road. A proper solution should > be more transparent, like thunks. > > Tested x86_64-pc-linux-gnu. Does this seem worth applying to fix the > regression?
Re: [PATCH] Add test-case (PR ipa/84805).
> Patch can bootstrap on ppc64le-redhat-linux and survives regression tests. Please make sure to test it on more platforms (see PR ipa/83983 for details). -- Eric Botcazou
Re: [PATCH, rs6000] PR 84422 fix sse2-pmuludq-1.c with -mcpu=power7
Hi Carl, On Wed, Mar 14, 2018 at 08:32:54AM -0700, Carl Love wrote: > 2018-03-13 Carl Love > > PR 84422 - ICE on various builtin test functions when compiled with > -mcpu=power7. This should be _exactly_ PR target/84422 (one such line per PR, and no blank line after it) so that bugzilla will automagically pick it up. > * config/rs6000/rs6000-builtin.def: Change expansion for > VMULE[SW|UW] to BU_P8V_AV_2. > * config/rs6000/rs6000.c: Change > ALTIVEC_BUILTIN_VMULE[SW|UW] to P8V_BUILTIN_VMULE[SW|UW]. > Change ALTIVEC_BUILTIN_VMULO[SW|UW] to P8V_BUILTIN_VMULO[SW|UW]. > * config/rs6000/rs6000-c.c: Change > ALTIVEC_BUILTIN_VMULE[SW|UW] to P8V_BUILTIN_VMULE[SW|UW]. > Change ALTIVEC_BUILTIN_VMULO[SW|UW] to P8V_BUILTIN_VMULO[SW|UW]. If you don't use the literal names it becomes very hard to grep for. The patch itself looks fine. Okay for trunk. Thanks! Segher
Enable string_view assertions
Hi
Following PR 78420 patch I realized that we can use similar
technique to have assertions in string_view implementations.
I also rename testsuite files expected to XFAIL as they should have
a trailing '_neg'. It fixes 4 XPASS when run in debug mode
Note that I also try to use a static_assert when
__builtin_constant_v return true but it is not constant enough. Could it
be a gcc issue ?
Tested under Linux x86_64 normal and debug modes.
Ok to commit ? Now ?
François
diff --git a/libstdc++-v3/include/experimental/string_view b/libstdc++-v3/include/experimental/string_view
index e42d5ac..97f9312 100644
--- a/libstdc++-v3/include/experimental/string_view
+++ b/libstdc++-v3/include/experimental/string_view
@@ -178,8 +178,9 @@ inline namespace fundamentals_v1
constexpr const _CharT&
operator[](size_type __pos) const
{
- // TODO: Assert to restore in a way compatible with the constexpr.
- // __glibcxx_assert(__pos < this->_M_len);
+ if (!__builtin_constant_p(__pos))
+ __glibcxx_assert(__pos < this->_M_len);
+
return *(this->_M_str + __pos);
}
@@ -198,16 +199,18 @@ inline namespace fundamentals_v1
constexpr const _CharT&
front() const
{
- // TODO: Assert to restore in a way compatible with the constexpr.
- // __glibcxx_assert(this->_M_len > 0);
+ if (!__builtin_constant_p(this->_M_len))
+ __glibcxx_assert(this->_M_len > 0);
+
return *this->_M_str;
}
constexpr const _CharT&
back() const
{
- // TODO: Assert to restore in a way compatible with the constexpr.
- // __glibcxx_assert(this->_M_len > 0);
+ if (!__builtin_constant_p(this->_M_len))
+ __glibcxx_assert(this->_M_len > 0);
+
return *(this->_M_str + this->_M_len - 1);
}
diff --git a/libstdc++-v3/include/std/string_view b/libstdc++-v3/include/std/string_view
index 9f39df8..22b168b 100644
--- a/libstdc++-v3/include/std/string_view
+++ b/libstdc++-v3/include/std/string_view
@@ -169,8 +169,9 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
constexpr const _CharT&
operator[](size_type __pos) const noexcept
{
- // TODO: Assert to restore in a way compatible with the constexpr.
- // __glibcxx_assert(__pos < this->_M_len);
+ if (!__builtin_constant_p(__pos))
+ __glibcxx_assert(__pos < this->_M_len);
+
return *(this->_M_str + __pos);
}
@@ -187,16 +188,18 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
constexpr const _CharT&
front() const noexcept
{
- // TODO: Assert to restore in a way compatible with the constexpr.
- // __glibcxx_assert(this->_M_len > 0);
+ if (!__builtin_constant_p(this->_M_len))
+ __glibcxx_assert(this->_M_len > 0);
+
return *this->_M_str;
}
constexpr const _CharT&
back() const noexcept
{
- // TODO: Assert to restore in a way compatible with the constexpr.
- // __glibcxx_assert(this->_M_len > 0);
+ if (!__builtin_constant_p(this->_M_len))
+ __glibcxx_assert(this->_M_len > 0);
+
return *(this->_M_str + this->_M_len - 1);
}
diff --git a/libstdc++-v3/testsuite/21_strings/basic_string_view/element_access/char/2.cc b/libstdc++-v3/testsuite/21_strings/basic_string_view/element_access/char/2.cc
deleted file mode 100644
index 4ee2b64..000
--- a/libstdc++-v3/testsuite/21_strings/basic_string_view/element_access/char/2.cc
+++ /dev/null
@@ -1,30 +0,0 @@
-// { dg-do run { xfail *-*-* } }
-// { dg-options "-std=gnu++17 -O0" }
-// { dg-require-debug-mode "" }
-
-// Copyright (C) 2013-2018 Free Software Foundation, Inc.
-//
-// This file is part of the GNU ISO C++ Library. This library is free
-// software; you can redistribute it and/or modify it under the
-// terms of the GNU General Public License as published by the
-// Free Software Foundation; either version 3, or (at your option)
-// any later version.
-
-// This library is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-// GNU General Public License for more details.
-
-// You should have received a copy of the GNU General Public License along
-// with this library; see the file COPYING3. If not see
-//
[PATCH, rs6000] Finish implementation of __builtin_atlivec_lvx_v1ti
During code review, it was discovered that the implementation of
__builtin_altivec_lvx_v1ti is not complete. The constant
ALTIVEC_BUILTINLVX_V1TI is introduced and is bound to the function
__builtin_altivec_lvx_v1ti. However, this function's implementation is
incomplete because there is no call to the def_builtin function for this
binding.
This patch provides the missing pieces to add support for this function.
Additionally, this patch introduces four new __int128-based prototypes
of the overloaded __builtin_vec_ld function. This is the function that
implements the vec_ld () macro expansion. A new test case has been
provided to exercise each of these prototypes.
This patch has been bootstrapped and tested without regressions on both
powerpc64le-unknown-linux (P8) and on powerpc-linux (P7 big-endian, with
both -m32 and -m64 target options).
Is this patch ok for trunk?
gcc/ChangeLog:
2018-03-14 Kelvin Nilsen
* config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Add
entries for V1TI variants of __builtin_altivec_ld builtin.
* config/rs6000/rs6000.c (altivec_expand_lv_builtin): Add test and
handling of V1TI variant of LVX icode pattern.
(altivec_expand_builtin): Add case for ALTIVEC_BUILTIN_LVX_V1TI.
(rs6000_gimple_fold_builtin): Likewise.
(altivec_init_builtins): Add code to define
__builtin_altivec_lvx_v1ti function.
* doc/extend.texi: Add four new prototypes for vec_ld.
gcc/testsuite/ChangeLog:
2018-03-14 Kelvin Nilsen
* gcc.target/powerpc/altivec-ld-1.c: New test.
Index: gcc/config/rs6000/rs6000-c.c
===
--- gcc/config/rs6000/rs6000-c.c(revision 258341)
+++ gcc/config/rs6000/rs6000-c.c(working copy)
@@ -1562,6 +1562,15 @@ const struct altivec_builtin_types altivec_overloa
{ VSX_BUILTIN_VEC_FLOATO, VSX_BUILTIN_UNS_FLOATO_V2DI,
RS6000_BTI_V4SF, RS6000_BTI_unsigned_V2DI, 0, 0 },
+ { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V1TI,
+RS6000_BTI_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_V1TI, 0 },
+ { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V1TI,
+RS6000_BTI_unsigned_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V1TI, 0 },
+ { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V1TI,
+RS6000_BTI_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_INTTI, 0 },
+ { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V1TI,
+RS6000_BTI_unsigned_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTTI, 0 },
+
{ ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DF,
RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF, 0 },
{ ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DI,
Index: gcc/config/rs6000/rs6000.c
===
--- gcc/config/rs6000/rs6000.c (revision 258341)
+++ gcc/config/rs6000/rs6000.c (working copy)
@@ -14452,6 +14452,7 @@ altivec_expand_lv_builtin (enum insn_code icode, t
LVXL and LVE*X expand to use UNSPECs to hide their special behavior,
so the raw address is fine. */
if (icode == CODE_FOR_altivec_lvx_v2df_2op
+ || icode == CODE_FOR_altivec_lvx_v1ti_2op
|| icode == CODE_FOR_altivec_lvx_v2di_2op
|| icode == CODE_FOR_altivec_lvx_v4sf_2op
|| icode == CODE_FOR_altivec_lvx_v4si_2op
@@ -15811,6 +15812,9 @@ altivec_expand_builtin (tree exp, rtx target, bool
case ALTIVEC_BUILTIN_LVX_V2DI:
return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v2di_2op,
exp, target, false);
+case ALTIVEC_BUILTIN_LVX_V1TI:
+ return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v1ti_2op,
+ exp, target, false);
case ALTIVEC_BUILTIN_LVX_V4SF:
return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v4sf_2op,
exp, target, false);
@@ -16542,6 +16546,7 @@ rs6000_gimple_fold_builtin (gimple_stmt_iterator *
case ALTIVEC_BUILTIN_LVX_V4SF:
case ALTIVEC_BUILTIN_LVX_V2DI:
case ALTIVEC_BUILTIN_LVX_V2DF:
+case ALTIVEC_BUILTIN_LVX_V1TI:
{
arg0 = gimple_call_arg (stmt, 0); // offset
arg1 = gimple_call_arg (stmt, 1); // address
@@ -17443,6 +17448,10 @@ altivec_init_builtins (void)
= build_function_type_list (V2DI_type_node,
long_integer_type_node, pcvoid_type_node,
NULL_TREE);
+ tree v1ti_ftype_long_pcvoid
+= build_function_type_list (V1TI_type_node,
+ long_integer_type_node, pcvoid_type_node,
+ NULL_TREE);
tree void_ftype_opaque_long_pvoid
= build_function_type_list (void_type_node,
@@ -17540,6 +17549,8 @@ altivec_init_builtins (void)
def_builtin ("__builtin_altivec_lvx", v4si_ftype_long_pcvoid,
ALTIVEC_BUILTIN_LVX);
def_builtin ("__builtin_altivec_lvx_v2df", v2df_ftype_long_pcvoid,
ALTIVEC_BUILTIN_LVX_V2DF);
+ def_builtin (
[PATCH] Fix emit_conditional_move (PR target/84860)
Hi!
prepare_cmp_insn in some cases changes both the passed in comparison and the
comparison mode, e.g. by promoting the arguments from SFmode to DFmode etc.
In emit_conditional_move we call this in a loop, for (pass = 0; pass < 2;
pass++)
and in each case construct comparison arguments as well as the comparison
passed to it from the original arguments (we have to after all, because when
not successful, we throw the whole insn sequence away), but use cmode which
the first iteration could have changed, on this testcase on powerpcspe with
-mcpu=8548 from SFmode to DFmode, so we ICE the second time, because the
arguments don't really match the comparison mode.
Fixed by passing it an address of a copy of the cmode parameter, so that the
second pass starts with the original cmode that matches the arguments again.
Bootstrapped/regtested on x86_64-linux and i686-linux, ok for trunk?
2018-03-14 Jakub Jelinek
PR target/84860
* optabs.c (emit_conditional_move): Pass address of cmode's copy
rather than address of cmode as last argument to prepare_cmp_insn.
* gcc.c-torture/compile/pr84860.c: New test.
--- gcc/optabs.c.jj 2018-02-09 19:11:29.0 +0100
+++ gcc/optabs.c2018-03-14 09:22:31.707873477 +0100
@@ -4345,9 +4345,10 @@ emit_conditional_move (rtx target, enum
save_pending_stack_adjust (&save);
last = get_last_insn ();
do_pending_stack_adjust ();
+ machine_mode cmpmode = cmode;
prepare_cmp_insn (XEXP (comparison, 0), XEXP (comparison, 1),
GET_CODE (comparison), NULL_RTX, unsignedp,
- OPTAB_WIDEN, &comparison, &cmode);
+ OPTAB_WIDEN, &comparison, &cmpmode);
if (comparison)
{
struct expand_operand ops[4];
--- gcc/testsuite/gcc.c-torture/compile/pr84860.c.jj2018-03-14
09:26:19.93506 +0100
+++ gcc/testsuite/gcc.c-torture/compile/pr84860.c 2018-03-14
09:26:44.854884590 +0100
@@ -0,0 +1,11 @@
+/* PR target/84860 */
+
+void
+foo (int x, int y)
+{
+ while (x < 1)
+{
+ x = y;
+ y = ((float)1 / 0) ? 2 : 0;
+}
+}
Jakub
[C++ PATCH] Fix up -Wdeprecated (PR c++/84222)
Hi!
As the following testcase shows, if we have a deprecated class, we warn
about any uses, including e.g. arguments of methods of that class (how can
one e.g. declare or define a copy ctor without warnings?).
The following patch changes it, so that we don't warn about deprecated uses
in methods of that deprecated class (warn about uses of other deprecated
classes of course). There is still one xfailed case where we warn about
template-id in the containing scope if the deprecated class is a template.
clang++ warns about the bar (const C &, const C &) function, both about
the parameters and about the use in the body (like g++) and doesn't warn
inside of (perhaps uninstantiated only) templates at all (which I think is
better that we do warn).
Bootstrapped/regtested on x86_64-linux and i686-linux, ok for trunk?
2018-03-14 Jakub Jelinek
PR c++/84222
* cp-tree.h (cp_warn_deprecated_use): Declare.
* tree.c (cp_warn_deprecated_use): New function.
* typeck2.c (build_functional_cast): Use it.
* decl.c (grokparms): Likewise.
(grokdeclarator): Likewise. Temporarily push nested class scope
around grokparms call for out of class member definitions.
* g++.dg/warn/deprecated.C (T::member3): Change dg-warning to dg-bogus.
* g++.dg/warn/deprecated-6.C (T::member3): Likewise.
* g++.dg/warn/deprecated-13.C: New test.
--- gcc/cp/cp-tree.h.jj 2018-03-11 17:48:36.360061435 +0100
+++ gcc/cp/cp-tree.h2018-03-14 11:49:58.924816419 +0100
@@ -7064,6 +7064,7 @@ extern tree cxx_copy_lang_qualifiers (c
extern void cxx_print_statistics (void);
extern bool maybe_warn_zero_as_null_pointer_constant (tree, location_t);
+extern void cp_warn_deprecated_use (tree);
/* in ptree.c */
extern void cxx_print_xnode(FILE *, tree, int);
--- gcc/cp/tree.c.jj2018-03-07 22:51:58.671478659 +0100
+++ gcc/cp/tree.c 2018-03-14 11:49:58.926816421 +0100
@@ -5347,6 +5347,19 @@ cp_tree_code_length (enum tree_code code
}
}
+/* Wrapper around warn_deprecated_use that doesn't warn for
+ current_class_type. */
+
+void
+cp_warn_deprecated_use (tree node)
+{
+ if (TYPE_P (node)
+ && current_class_type
+ && TYPE_MAIN_VARIANT (node) == current_class_type)
+return;
+ warn_deprecated_use (node, NULL_TREE);
+}
+
/* Implement -Wzero_as_null_pointer_constant. Return true if the
conditions for the warning hold, false otherwise. */
bool
--- gcc/cp/typeck2.c.jj 2018-03-02 00:15:54.096781050 +0100
+++ gcc/cp/typeck2.c2018-03-14 11:49:58.931816424 +0100
@@ -2057,7 +2057,7 @@ build_functional_cast (tree exp, tree pa
if (complain & tf_warning
&& TREE_DEPRECATED (type)
&& DECL_ARTIFICIAL (exp))
- warn_deprecated_use (type, NULL_TREE);
+ cp_warn_deprecated_use (type);
}
else
type = exp;
--- gcc/cp/decl.c.jj2018-03-14 09:44:55.744974946 +0100
+++ gcc/cp/decl.c 2018-03-14 12:18:08.094012453 +0100
@@ -10448,7 +10448,7 @@ grokdeclarator (const cp_declarator *dec
suppress reports of deprecated items. */
if (type && TREE_DEPRECATED (type)
&& deprecated_state != DEPRECATED_SUPPRESS)
-warn_deprecated_use (type, NULL_TREE);
+cp_warn_deprecated_use (type);
if (type && TREE_CODE (type) == TYPE_DECL)
{
typedef_decl = type;
@@ -10456,7 +10456,7 @@ grokdeclarator (const cp_declarator *dec
if (TREE_DEPRECATED (type)
&& DECL_ARTIFICIAL (typedef_decl)
&& deprecated_state != DEPRECATED_SUPPRESS)
- warn_deprecated_use (type, NULL_TREE);
+ cp_warn_deprecated_use (type);
}
/* No type at all: default to `int', and set DEFAULTED_INT
because it was not a user-defined typedef. */
@@ -11271,8 +11271,18 @@ grokdeclarator (const cp_declarator *dec
explicitp = 2;
}
- arg_types = grokparms (declarator->u.function.parameters,
- &parms);
+ tree pushed_scope = NULL_TREE;
+ if (funcdecl_p
+ && decl_context != FIELD
+ && inner_declarator->u.id.qualifying_scope
+ && CLASS_TYPE_P (inner_declarator->u.id.qualifying_scope))
+ pushed_scope
+ = push_scope (inner_declarator->u.id.qualifying_scope);
+
+ arg_types = grokparms (declarator->u.function.parameters, &parms);
+
+ if (pushed_scope)
+ pop_scope (pushed_scope);
if (inner_declarator
&& inner_declarator->kind == cdk_id
@@ -12799,7 +12809,7 @@ grokparms (tree parmlist, tree *parms)
{
tree deptype = type_is_deprecated (type);
if (deptype)
- warn_deprecated_use (deptype, NULL_TREE);
+ cp_warn_deprecated_use (deptype);
}
/* Top-level qualifiers on the parameters are
--- gcc/testsuite/g++.dg/warn/depr
[C PATCH] Reject shifts of float vectors by int count (PR c/84853)
Hi!
The change for better warnings on vector shifts unfortunately started
accepting even shifts of floating point vectors by int shift count, which is
something that shouldn't be supported and ICEs later on.
Fixed thusly, bootstrapped/regtested on x86_64-linux and i686-linux, ok for
trunk?
2018-03-14 Jakub Jelinek
PR c/84853
* c-typeck.c (build_binary_op) :
If code1 is INTEGER_TYPE, only allow code0 VECTOR_TYPE if it has
INTEGER_TYPE element type.
* gcc.dg/pr84853.c: New test.
--- gcc/c/c-typeck.c.jj 2018-03-13 21:32:00.441647458 +0100
+++ gcc/c/c-typeck.c2018-03-13 23:03:27.659789112 +0100
@@ -11350,7 +11350,8 @@ build_binary_op (location_t location, en
converted = 1;
}
else if ((code0 == INTEGER_TYPE || code0 == FIXED_POINT_TYPE
- || code0 == VECTOR_TYPE)
+ || (code0 == VECTOR_TYPE
+ && TREE_CODE (TREE_TYPE (type0)) == INTEGER_TYPE))
&& code1 == INTEGER_TYPE)
{
doing_shift = true;
@@ -11408,7 +11409,8 @@ build_binary_op (location_t location, en
converted = 1;
}
else if ((code0 == INTEGER_TYPE || code0 == FIXED_POINT_TYPE
- || code0 == VECTOR_TYPE)
+ || (code0 == VECTOR_TYPE
+ && TREE_CODE (TREE_TYPE (type0)) == INTEGER_TYPE))
&& code1 == INTEGER_TYPE)
{
doing_shift = true;
--- gcc/testsuite/gcc.dg/pr84853.c.jj 2018-03-13 23:07:05.910890067 +0100
+++ gcc/testsuite/gcc.dg/pr84853.c 2018-03-13 23:06:38.546877404 +0100
@@ -0,0 +1,19 @@
+/* PR c/84853 */
+/* { dg-do compile } */
+
+typedef float V __attribute__((__vector_size__ (16)));
+typedef int W __attribute__((__vector_size__ (16)));
+
+void
+foo (int x, V *y, V *z, W *w)
+{
+ *y = *y << x;/* { dg-error "invalid operands to binary <<" }
*/
+ *z = *z << *w; /* { dg-error "invalid operands to binary <<" } */
+}
+
+void
+bar (int x, V *y, V *z, W *w)
+{
+ *y = *y >> x;/* { dg-error "invalid operands to binary >>" }
*/
+ *z = *z >> *w; /* { dg-error "invalid operands to binary >>" } */
+}
Jakub
[C++ PATCH] Fix PLACEHOLDER_EXPR handling (PR c++/79937, PR c++/82410)
Hi!
The following patch is an attempt to fix PLACEHOLDER_EXPR handling.
As e.g.
struct Y
{
static Y bar (Y y) { return y; }
int i;
int n = bar (Y{2,i}).m + bar {Y{2,i,i}).n;
int m = i;
};
is rejected - one can't use incomplete ctors which would need NSDMIs
until the class is defined, I believe PLACEHOLDER_EXPRs can't be arbitrarily
intermixed, rather some CONSTRUCTORs into which we've added the NSDMI
expressions can contain PLACEHOLDER_EXPRs and other PLACEHOLDER_EXPRs can be
only found inside such CONSTRUCTORs added earlier.
So, this patch adds a new flag on CONSTRUCTORs, which acts as a barrier
boundary for replace_placeholders, where we replace just PLACEHOLDER_EXPRs
from the outermost expressions and don't dive into CONSTRUCTORs into which
we've added other PLACEHOLDER_EXPRs - those will be handled later on
separately, by cp_gimplify_init_expr calling replace_placeholders.
Bootstrapped/regtested on x86_64-linux and i686-linux, ok for trunk?
2018-03-14 Jakub Jelinek
PR c++/79937
PR c++/82410
* cp-tree.h (CONSTRUCTOR_PLACEHOLDER_BOUNDARY): Define.
(find_placeholder): Declare.
* tree.c (struct replace_placeholders_t): Add exp member.
(replace_placeholders_r): Don't walk into ctors with
CONSTRUCTOR_PLACEHOLDER_BOUNDARY flag set, unless they are equal to
d->exp.
(replace_placeholders): Initialize data.exp.
(find_placeholders_r, find_placeholders): New functions.
* typeck2.c (process_init_constructor_record,
process_init_constructor_union): Set CONSTRUCTOR_PLACEHOLDER_BOUNDARY
if adding NSDMI on which find_placeholder returns true.
* g++.dg/cpp1y/pr79937-1.C: New test.
* g++.dg/cpp1y/pr79937-2.C: New test.
* g++.dg/cpp1y/pr79937-3.C: New test.
* g++.dg/cpp1y/pr79937-4.C: New test.
* g++.dg/cpp1y/pr82410.C: New test.
--- gcc/cp/cp-tree.h.jj 2018-03-14 16:21:50.745925263 +0100
+++ gcc/cp/cp-tree.h2018-03-14 15:57:51.171323825 +0100
@@ -425,6 +425,7 @@ extern GTY(()) tree cp_global_trees[CPTI
DECL_VTABLE_OR_VTT_P (in VAR_DECL)
FUNCTION_RVALUE_QUALIFIED (in FUNCTION_TYPE, METHOD_TYPE)
CALL_EXPR_REVERSE_ARGS (in CALL_EXPR, AGGR_INIT_EXPR)
+ CONSTRUCTOR_PLACEHOLDER_BOUNDARY (in CONSTRUCTOR)
6: IDENTIFIER_REPO_CHOSEN (in IDENTIFIER_NODE)
DECL_CONSTRUCTION_VTABLE_P (in VAR_DECL)
TYPE_MARKED_P (in _TYPE)
@@ -4144,6 +4145,12 @@ more_aggr_init_expr_args_p (const aggr_i
#define CONSTRUCTOR_C99_COMPOUND_LITERAL(NODE) \
(TREE_LANG_FLAG_3 (CONSTRUCTOR_CHECK (NODE)))
+/* True if this CONSTRUCTOR contains PLACEHOLDER_EXPRs referencing the
+ CONSTRUCTOR's type not nested inside another CONSTRUCTOR marked with
+ CONSTRUCTOR_PLACEHOLDER_BOUNDARY. */
+#define CONSTRUCTOR_PLACEHOLDER_BOUNDARY(NODE) \
+ (TREE_LANG_FLAG_5 (CONSTRUCTOR_CHECK (NODE)))
+
#define DIRECT_LIST_INIT_P(NODE) \
(BRACE_ENCLOSED_INITIALIZER_P (NODE) && CONSTRUCTOR_IS_DIRECT_INIT (NODE))
@@ -7021,6 +7028,7 @@ extern tree array_type_nelts_top (tree)
extern tree break_out_target_exprs (tree);
extern tree build_ctor_subob_ref (tree, tree, tree);
extern tree replace_placeholders (tree, tree, bool * = NULL);
+extern bool find_placeholders (tree);
extern tree get_type_decl (tree);
extern tree decl_namespace_context (tree);
extern bool decl_anon_ns_mem_p (const_tree);
--- gcc/cp/tree.c.jj2018-03-14 11:49:58.926816421 +0100
+++ gcc/cp/tree.c 2018-03-14 16:24:29.036987505 +0100
@@ -3096,6 +3096,7 @@ build_ctor_subob_ref (tree index, tree t
struct replace_placeholders_t
{
tree obj;/* The object to be substituted for a PLACEHOLDER_EXPR. */
+ tree exp;/* The outermost exp. */
bool seen; /* Whether we've encountered a PLACEHOLDER_EXPR. */
hash_set *pset;/* To avoid walking same trees multiple times.
*/
};
@@ -3134,7 +3135,12 @@ replace_placeholders_r (tree* t, int* wa
{
constructor_elt *ce;
vec *v = CONSTRUCTOR_ELTS (*t);
- if (d->pset->add (*t))
+ /* Don't walk into CONSTRUCTOR_PLACEHOLDER_BOUNDARY ctors
+ other than the d->exp one, those have PLACEHOLDER_EXPRs
+ related to another object. */
+ if ((CONSTRUCTOR_PLACEHOLDER_BOUNDARY (*t)
+&& *t != d->exp)
+ || d->pset->add (*t))
{
*walk_subtrees = false;
return NULL_TREE;
@@ -3192,16 +3198,70 @@ replace_placeholders (tree exp, tree obj
return exp;
tree *tp = &exp;
- hash_set pset;
- replace_placeholders_t data = { obj, false, &pset };
+ /* Use exp instead of *(type *)&exp. */
+ while (TREE_CODE (exp) == INDIRECT_REF)
+{
+ tree t = TREE_OPERAND (exp, 0);
+ STRIP_NOPS (t);
+ if (TREE_CODE (t) == ADDR_EXPR
+ && (t = TREE_OPERAND (t, 0))
+ && same_type_ignoring_to
Re: Enable string_view assertions
(Resending from a different account, sorry for the duplicate).
On 14/03/18 22:12 +0100, François Dumont wrote:
> constexpr const _CharT&
> operator[](size_type __pos) const noexcept
> {
>- // TODO: Assert to restore in a way compatible with the constexpr.
>- // __glibcxx_assert(__pos < this->_M_len);
>+ if (!__builtin_constant_p(__pos))
>+__glibcxx_assert(__pos < this->_M_len);
This doesn't do the right thing, because it fails to assert when __pos
is known at compile-time:
const std::string_view sv;
sv[100];
This will only assert at -O0. As soon as optimization is enabled the
value is known inside the function, and __builtin_constant_p(__pos)
is true, and we don't do the range check.
We also don't do the check for constant expressions, when we should be
able to give a compilation error, not just ignore it!
Enabling the assertions at -O0 and outside constant expressions is
slightly better than never enabling them at all, but not good enough
to remove the "TODO" comments. Ideally we want out-of-range accesses
to be an error in constant expressions, and fail the runtime assertion
in non-constant expressions.
But using __builtin_constant_p to do the assertion conditionally
doesn't do that. In PR 78420 either branch is OK: when the comparison
is known at compile-time, do it directly, otherwise do it via casting.
Both give the same result.
Here you do "if the result is not known, check it at runtime,
otherwise don't check at all".
What we should do instead is declare a new member function like this:
static void
__out_of_range() __attribute__((__error__("Index out-of-range")));
Then we can refer to that in the cases where (__pos >= _M_len) is
known at compile-time:
constexpr const _CharT&
operator[](size_type __pos) const noexcept
{
if (__builtin_constant_p(__pos >= _M_len))
{
if (__pos >= _M_len)
__out_of_range();
}
else
__glibcxx_assert(__pos < this->_M_len);
return *(this->_M_str + __pos);
}
Now if we try an out-of-range access in a constant expression we get:
sv.cc:4:23: in 'constexpr' expansion of
's.std::basic_string_view::operator[](1)'
/home/jwakely/gcc/8/include/c++/8.0.1/string_view:181:22: error: call
to non-'constexpr' function 'static void
std::basic_string_view<_CharT, _Traits>::__out_of_range() [with _CharT
= char; _Traits = std::char_traits]'
__out_of_range();
~~^~
In a non-constant expression, with optimization it gives a
compile-time error because of the __error__ attribute:
In member function 'constexpr const _CharT&
std::basic_string_view<_CharT,
_Traits>::operator[](std::basic_string_view<_CharT,
_Traits>::size_type) const [with _CharT = char; _Traits =
std::char_traits]',
inlined from 'int main()' at sv.cc:9:6:
/home/jwakely/gcc/8/include/c++/8.0.1/string_view:181:22: error: call
to 'std::basic_string_view::__out_of_range' declared with
attribute error: Index out-of-range
__out_of_range();
~~^~
Finally, without optimization, you can get a run-time failure with
_GLIBCXX_ASSERTIONS:
/home/jwakely/gcc/8/include/c++/8.0.1/string_view:178: constexpr const
_CharT& std::basic_string_view<_CharT,
_Traits>::operator[](std::basic_string_view<_CharT,
_Traits>::size_type) const [with _CharT = char; _Traits =
std::char_traits; std::basic_string_view<_CharT,
_Traits>::size_type = long unsigned int]: Assertion '__pos <
this->_M_len' failed.
Aborted (core dumped)
Without _GLIBCXX_ASSERTIONS and without optimization the code compiles
and runs, with undefined behaviour.
This seems like the optimal set of checks (I've been working on doing
this in other types too, so we give compile-time errors when we can
prove the code has a bug).
>--- /dev/null
>+++
>b/libstdc++-v3/testsuite/21_strings/basic_string_view/element_access/char/2_neg.cc
>@@ -0,0 +1,30 @@
>+// { dg-do run { xfail *-*-* } }
>+// { dg-options "-std=gnu++17 -O0" }
>+// { dg-require-debug-mode "" }
Instead of requiring debug mode we could just define
_GLIBCXX_ASSERTIONS.
We should also add tests for the compile-time errors, both in and out
of constant expressions.
[RFC Patch], PowerPC memory support pre-gcc9, patch #1
I am starting to work on cleaning up the memory addressing support in the GCC 9 time frame. At the moment, I am working on upgrading the infrastructure to allow in the future to prevent splitting memory on 64-bit LE systems too early, rework the fusion support, and provide a pathway for future processor support. The first patch in the series moves most of the reg_addr structure from rs6000.c to rs6000-protos.h, so that in the next patch, we can start splitting some of the address code to other files. In addition to just moving the reg_addr stuff to be global, there are a few minor changes in this patch: 1) I was playing with making r12 be fixed with a new option (not in this set of patches), and I noticed it wasn't reflected in the -mdebug=reg debug dump, due to the debug dump being done before the conditional registers are setup. I made the debug dump set conditional registers. 2) I renamed some of the mode_suppports helper functions to be more consistent the instruction documentation (i.e. there are helper functions for normal d-form register+offset instructions, ds-form where the bottom 2 bits must be 0 and dq-form where the bottom 4 bits must be 0). I added optional arguments to the helper functions, so that secondary reload in the future can narrow down whether a particular register class has particular support. 3) I did a simplification in setting up the reg_addr address masks, where instead of 3 states which two set INDEXED and the other sets MULTIPLE register, it only has 1 place where it sets INDEXED. I have tested this with full bootstrap and make check on a little endian power8 with no regressions. Since we are in stage4 currently, I am not asking for permission to check it in, but if you have any comments on how you would like to see the eventual patches when stage1 opens up, let me know. It would be simpler to make the changes now, rather than when the number of patches have accumulated. The second patch that I will submit shortly will move the rs6000_output_move_128bit function to a new file (rs6000-output.c). The third patch that I will submit will be to move the movdi patterns to a separate function (rs6000_output_move_64bit) also in rs6000-output.c, so that in the future we can use C++ code to check on constraints, etc. I haven't written it yet, but the fourth patch is likely to similarly move DF and DD output templates to use the same function. One thing I plan to do for DF/DD is to structure the comments about the alternatives so that it is more readable, much like I've done for movdi, etc. I likely will remove the undocumented toc-fusion all together, and eventually rework the p8/p9 fusion support. 2018-03-14 Michael Meissner * config/rs6000/rs6000-protos.h (regno_or_subregno): Add declaration. (enum rs6000_reg_type): Move the basic reg_addr support from rs6000.c to rs6000-protos.h, except for the parts that store insn_code's for the register allocator to allow future patches to move parts of rs6000.c to other files. Change the bool flags to bit-fields. Add a flag to indicate the mode/reload register class uses DS-form (14-bit offset) addresses. (reg_class_to_reg_type): Likwise. (IS_STD_REG_TYPE): Likwise. (IS_FP_VECT_REG_TYPE): Likwise. (enum rs6000_reload_reg_type): Likwise. (struct rs6000_reg_addr): Likwise. (reg_addr): Likwise. (RELOAD_REG_*): Likewise. (mode_supports_pre_incdec_p): Move the mode supports helper functions to rs6000-protos.h. Add an optional argument to use a particular reload register class instead of RELOAD_REG_ANY. Rename mode_supports_vsx_dform_quad -> mode_supports_dq_form. Add mode_supports_ds_form for DS-form addresses. Add mode_supports_x_form for X-form (indexed) addresses. (mode_supports_pre_modify_p): Likewise. (mode_supports_d_form): Likewise. (mode_supports_ds_form): Likewise. (mode_supports_dq_form): Likewise. (mode_supports_x_form): Likewise. * config/rs6000/rs6000.c (enum rs6000_reg_type): Move basic reg_addr support to rs6000-protos.h. (IS_STD_REG_TYPE): Likewise. (IS_FP_VECT_REG_TYPE): Likewise. (enum rs6000_reload_reg_typ): Likewise. (reg_class_to_reg_type): Make global. (addr_mask_type): Move basic reg_addr support to rs6000-protos.h. (reg_addr): Make global. (RELOAD_REG_VALID): Move basic reg_addr support to rs6000-protos.h. (RELOAD_REG_*): Likewise. (struct rs6000_insn_functions): New structure that includes the parts of the old reg_addr structure that did not move to rs6000-protos.h because it contains insn codes. (rs6000_insns): Likewise. (mode_supports_pre_modify_p): Move to rs6000-prot
Re: PR libstdc++/78420 Make std::less etc. yield total order for pointers
Here's a very different patch. This gets rid of the __ptr_rel_ops and
just puts the special handling for pointers directly in the
std::less<_Tp*> etc. specializations. Then std::less uses
std::less for some pointer type P*. I've also added a ton of ugly
metaprogramming to detect the "if the call operator calls a built-in
operator comparing pointers" condition. The idea is borrowed from
Casey Carter and Eric Niebler's Ranges work, but basically it checks
if operator<(T,U) or T.operator<(U) can be called, and if not the
comparison must be using a built-in operator. If both T and U are
convertible to pointers (specifically, to const volatile void* which
is the most accepting of all pointers) then we assume we're using a
built-in operator comparing pointers, and delegate to std::less, which ensures a total order.
Tested powerpc64le-linux, committed to trunk. This fixes a regression,
but I'm not sure about backporting it yet, I haven't even tried
testing it on the branches.
commit 00c52c235b8dea85000f7b5e1dcff0526216a9a5
Author: Jonathan Wakely
Date: Wed Mar 14 19:12:21 2018 +
PR libstdc++/78420 Make std::less etc. yield total order for pointers
In order for std::less etc. to meet the total order requirements of
[comparisons] p2 we need to cast unrelated pointers to uintptr_t before
comparing them. Those casts aren't allowed in constant expressions, so
only cast when __builtin_constant_p says the result of the comparison is
not a compile-time constant (because the arguments are not constants, or
the result of the comparison is unspecified). When the result is
constant just compare the pointers directly without casting.
This ensures that the function can be called in constant expressions
with suitable arguments, but still yields a total order even for
otherwise unspecified pointer comparisons.
For std::less etc. add new overloads for pointers, which use
std::less> directly. Also change the generic
overloads to detect when the comparison would call a built-in relational
operator with pointer operands, and dispatch that case to the
corresponding specialization for void pointers.
PR libstdc++/78420
* include/bits/stl_function.h (greater<_Tp*>, less<_Tp*>)
(greater_equal<_Tp*>, less_equal<_Tp>*): Add partial specializations
to ensure total order for pointers.
(greater, less, greater_equal, less_equal):
Add operator() overloads for pointer arguments and make generic
overloads dispatch to new _S_cmp functions when comparisons would
use built-in operators for pointers.
* testsuite/20_util/function_objects/comparisons_pointer.cc: New.
diff --git a/libstdc++-v3/include/bits/stl_function.h
b/libstdc++-v3/include/bits/stl_function.h
index f5f98b25395..0affaf7da3a 100644
--- a/libstdc++-v3/include/bits/stl_function.h
+++ b/libstdc++-v3/include/bits/stl_function.h
@@ -406,14 +406,65 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
{ return __x <= __y; }
};
-#if __cplusplus > 201103L
+ // Partial specialization of std::greater for pointers.
+ template
+struct greater<_Tp*> : public binary_function<_Tp*, _Tp*, bool>
+{
+ _GLIBCXX14_CONSTEXPR bool
+ operator()(_Tp* __x, _Tp* __y) const _GLIBCXX_NOTHROW
+ {
+ if (__builtin_constant_p (__x > __y))
+ return __x > __y;
+ return (__UINTPTR_TYPE__)__x > (__UINTPTR_TYPE__)__y;
+ }
+};
+
+ // Partial specialization of std::less for pointers.
+ template
+struct less<_Tp*> : public binary_function<_Tp*, _Tp*, bool>
+{
+ _GLIBCXX14_CONSTEXPR bool
+ operator()(_Tp* __x, _Tp* __y) const _GLIBCXX_NOTHROW
+ {
+ if (__builtin_constant_p (__x < __y))
+ return __x < __y;
+ return (__UINTPTR_TYPE__)__x < (__UINTPTR_TYPE__)__y;
+ }
+};
+
+ // Partial specialization of std::greater_equal for pointers.
+ template
+struct greater_equal<_Tp*> : public binary_function<_Tp*, _Tp*, bool>
+{
+ _GLIBCXX14_CONSTEXPR bool
+ operator()(_Tp* __x, _Tp* __y) const _GLIBCXX_NOTHROW
+ {
+ if (__builtin_constant_p (__x >= __y))
+ return __x >= __y;
+ return (__UINTPTR_TYPE__)__x >= (__UINTPTR_TYPE__)__y;
+ }
+};
+
+ // Partial specialization of std::less_equal for pointers.
+ template
+struct less_equal<_Tp*> : public binary_function<_Tp*, _Tp*, bool>
+{
+ _GLIBCXX14_CONSTEXPR bool
+ operator()(_Tp* __x, _Tp* __y) const _GLIBCXX_NOTHROW
+ {
+ if (__builtin_constant_p (__x <= __y))
+ return __x <= __y;
+ return (__UINTPTR_TYPE__)__x <= (__UINTPTR_TYPE__)__y;
+ }
+};
+
+#if __cplusplus >= 201402L
/// One of the @link comparison_functors comparison functors@endlink.
template<>
struct equal_to
{
template
- _GLIBCXX14_CONSTEXPR
- auto
+ constexpr auto
operato
Re: Enable string_view assertions
On 14 March 2018 at 22:52, Jonathan Wakely wrote:
> (Resending from a different account, sorry for the duplicate).
>
> On 14/03/18 22:12 +0100, François Dumont wrote:
>> constexpr const _CharT&
>> operator[](size_type __pos) const noexcept
>> {
>>- // TODO: Assert to restore in a way compatible with the constexpr.
>>- // __glibcxx_assert(__pos < this->_M_len);
>>+ if (!__builtin_constant_p(__pos))
>>+__glibcxx_assert(__pos < this->_M_len);
>
> This doesn't do the right thing, because it fails to assert when __pos
> is known at compile-time:
>
> const std::string_view sv;
> sv[100];
>
> This will only assert at -O0. As soon as optimization is enabled the
> value is known inside the function, and __builtin_constant_p(__pos)
> is true, and we don't do the range check.
>
> We also don't do the check for constant expressions, when we should be
> able to give a compilation error, not just ignore it!
>
> Enabling the assertions at -O0 and outside constant expressions is
> slightly better than never enabling them at all, but not good enough
> to remove the "TODO" comments. Ideally we want out-of-range accesses
> to be an error in constant expressions, and fail the runtime assertion
> in non-constant expressions.
>
> But using __builtin_constant_p to do the assertion conditionally
> doesn't do that. In PR 78420 either branch is OK: when the comparison
> is known at compile-time, do it directly, otherwise do it via casting.
> Both give the same result.
>
> Here you do "if the result is not known, check it at runtime,
> otherwise don't check at all".
>
> What we should do instead is declare a new member function like this:
>
> static void
> __out_of_range() __attribute__((__error__("Index out-of-range")));
>
> Then we can refer to that in the cases where (__pos >= _M_len) is
> known at compile-time:
>
> constexpr const _CharT&
> operator[](size_type __pos) const noexcept
> {
> if (__builtin_constant_p(__pos >= _M_len))
> {
> if (__pos >= _M_len)
> __out_of_range();
> }
> else
> __glibcxx_assert(__pos < this->_M_len);
> return *(this->_M_str + __pos);
> }
>
> Now if we try an out-of-range access in a constant expression we get:
>
> sv.cc:4:23: in 'constexpr' expansion of
> 's.std::basic_string_view::operator[](1)'
> /home/jwakely/gcc/8/include/c++/8.0.1/string_view:181:22: error: call
> to non-'constexpr' function 'static void
> std::basic_string_view<_CharT, _Traits>::__out_of_range() [with _CharT
> = char; _Traits = std::char_traits]'
> __out_of_range();
> ~~^~
>
> In a non-constant expression, with optimization it gives a
> compile-time error because of the __error__ attribute:
>
> In member function 'constexpr const _CharT&
> std::basic_string_view<_CharT,
> _Traits>::operator[](std::basic_string_view<_CharT,
> _Traits>::size_type) const [with _CharT = char; _Traits =
> std::char_traits]',
> inlined from 'int main()' at sv.cc:9:6:
> /home/jwakely/gcc/8/include/c++/8.0.1/string_view:181:22: error: call
> to 'std::basic_string_view::__out_of_range' declared with
> attribute error: Index out-of-range
> __out_of_range();
> ~~^~
>
> Finally, without optimization, you can get a run-time failure with
> _GLIBCXX_ASSERTIONS:
>
> /home/jwakely/gcc/8/include/c++/8.0.1/string_view:178: constexpr const
> _CharT& std::basic_string_view<_CharT,
> _Traits>::operator[](std::basic_string_view<_CharT,
> _Traits>::size_type) const [with _CharT = char; _Traits =
> std::char_traits; std::basic_string_view<_CharT,
> _Traits>::size_type = long unsigned int]: Assertion '__pos <
> this->_M_len' failed.
> Aborted (core dumped)
>
> Without _GLIBCXX_ASSERTIONS and without optimization the code compiles
> and runs, with undefined behaviour.
>
> This seems like the optimal set of checks (I've been working on doing
> this in other types too, so we give compile-time errors when we can
> prove the code has a bug).
Here's one way to generalize this idea. We could potentially replace
most of the lightweight __glibcxx_assert checks with this, to get
zero-overhead static checking at compile-time whenever possible (even
in constexpr functions) and have optional run-time assertions for the
remaining cases.
diff --git a/libstdc++-v3/include/bits/c++config
b/libstdc++-v3/include/bits/c++config
index 1eb4679f67c..3342af3a4f0 100644
--- a/libstdc++-v3/include/bits/c++config
+++ b/libstdc++-v3/include/bits/c++config
@@ -462,6 +462,12 @@ namespace std
# define __glibcxx_assert(_Condition)
#endif
+#define __glibcxx_assert2(_Condition, _Action) \
+ do { \
+if (__builtin_constant_p((_Condition))) { if (!(_Condition)) _Action; \
+} else { __glibcxx_assert(_Condition); } \
+ } while (false)
+
// Macros for race detectors.
//
[committed] hppa: Fix handling of secondary reloads for floating-point loads and stores
In rare situations, pa_emit_move_sequence needs to handle a paradoxical SUBREG in a floating-point load or store. There is existing code to adjust the operand's address but we fail to emit the reload if we don't need to load the address to a register. We just fall through pa_emit_move_sequence and emit the original operand. This patch revises the handling of these reloads to always emit the reload with the adjusted operand. Tested on hppa-unknown-linux-gnu and hppa64-hp-hpux11.11. Committed to trunk. Dave -- John David Anglin dave.ang...@bell.net 2018-03-14 John David Anglin PR target/83451 * config/pa/pa.c (pa_emit_move_sequence): Always emit secondary reload insn for floating-point loads and stores. Index: config/pa/pa.c === --- config/pa/pa.c (revision 258420) +++ config/pa/pa.c (working copy) @@ -1750,9 +1750,7 @@ } else emit_move_insn (scratch_reg, XEXP (op1, 0)); - emit_insn (gen_rtx_SET (operand0, - replace_equiv_address (op1, scratch_reg))); - return 1; + op1 = replace_equiv_address (op1, scratch_reg); } } else if ((!INT14_OK_STRICT && symbolic_memory_operand (op1, VOIDmode)) @@ -1762,10 +1760,10 @@ /* Load memory address into SCRATCH_REG. */ scratch_reg = force_mode (word_mode, scratch_reg); emit_move_insn (scratch_reg, XEXP (op1, 0)); - emit_insn (gen_rtx_SET (operand0, - replace_equiv_address (op1, scratch_reg))); - return 1; + op1 = replace_equiv_address (op1, scratch_reg); } + emit_insn (gen_rtx_SET (operand0, op1)); + return 1; } else if (scratch_reg && FP_REG_P (operand1) @@ -1803,9 +1801,7 @@ } else emit_move_insn (scratch_reg, XEXP (op0, 0)); - emit_insn (gen_rtx_SET (replace_equiv_address (op0, scratch_reg), - operand1)); - return 1; + op0 = replace_equiv_address (op0, scratch_reg); } } else if ((!INT14_OK_STRICT && symbolic_memory_operand (op0, VOIDmode)) @@ -1815,10 +1811,10 @@ /* Load memory address into SCRATCH_REG. */ scratch_reg = force_mode (word_mode, scratch_reg); emit_move_insn (scratch_reg, XEXP (op0, 0)); - emit_insn (gen_rtx_SET (replace_equiv_address (op0, scratch_reg), - operand1)); - return 1; + op0 = replace_equiv_address (op0, scratch_reg); } + emit_insn (gen_rtx_SET (op0, operand1)); + return 1; } /* Handle secondary reloads for loads of FP registers from constant expressions by forcing the constant into memory. For the most part,
Re: Enable string_view assertions
On 14 March 2018 at 23:27, Jonathan Wakely wrote:
> Here's one way to generalize this idea. We could potentially replace
> most of the lightweight __glibcxx_assert checks with this, to get
> zero-overhead static checking at compile-time whenever possible (even
> in constexpr functions) and have optional run-time assertions for the
> remaining cases.
Thinking about this some more, we probably don't want to do this for
most __glibcxx_assert uses, because it's probably rare that we can
statically detect most errors in something like
std::vector::operator[]. I doubt we would catch many bugs that way, as
most bugs would involve non-constant indices and vectors that have
changed size dynamically at run-time.
It *might* be useful in vector::front, vector::back, string::front,
deque::front etc. to catch bugs where users do:
std::string s;
// ...
someFunction(&s.front(), s.size());
It seems most valuable in constexpr functions (where we definitely
expect constant arguments in many cases) and where run-time arguments
will typically be constants, like in the attached patch for atomic
objects.
diff --git a/libstdc++-v3/include/bits/atomic_base.h
b/libstdc++-v3/include/bits/atomic_base.h
index a1fadcd8056..0f6783d257c 100644
--- a/libstdc++-v3/include/bits/atomic_base.h
+++ b/libstdc++-v3/include/bits/atomic_base.h
@@ -186,9 +186,9 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
clear(memory_order __m = memory_order_seq_cst) noexcept
{
memory_order __b = __m & __memory_order_mask;
- __glibcxx_assert(__b != memory_order_consume);
- __glibcxx_assert(__b != memory_order_acquire);
- __glibcxx_assert(__b != memory_order_acq_rel);
+ __glibcxx_assert2(__b != memory_order_consume, __invalid_memory_order());
+ __glibcxx_assert2(__b != memory_order_acquire, __invalid_memory_order());
+ __glibcxx_assert2(__b != memory_order_acq_rel, __invalid_memory_order());
__atomic_clear (&_M_i, __m);
}
@@ -197,9 +197,9 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
clear(memory_order __m = memory_order_seq_cst) volatile noexcept
{
memory_order __b = __m & __memory_order_mask;
- __glibcxx_assert(__b != memory_order_consume);
- __glibcxx_assert(__b != memory_order_acquire);
- __glibcxx_assert(__b != memory_order_acq_rel);
+ __glibcxx_assert2(__b != memory_order_consume, __invalid_memory_order());
+ __glibcxx_assert2(__b != memory_order_acquire, __invalid_memory_order());
+ __glibcxx_assert2(__b != memory_order_acq_rel, __invalid_memory_order());
__atomic_clear (&_M_i, __m);
}
@@ -208,6 +208,10 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
static constexpr __atomic_flag_data_type
_S_init(bool __i)
{ return __i ? __GCC_ATOMIC_TEST_AND_SET_TRUEVAL : 0; }
+
+static void
+__invalid_memory_order()
+__attribute__((__error__("invalid memory order for atomic_flag::clear")));
};
@@ -367,9 +371,9 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
store(__int_type __i, memory_order __m = memory_order_seq_cst) noexcept
{
memory_order __b = __m & __memory_order_mask;
- __glibcxx_assert(__b != memory_order_acquire);
- __glibcxx_assert(__b != memory_order_acq_rel);
- __glibcxx_assert(__b != memory_order_consume);
+ __glibcxx_assert2(__b != memory_order_acquire, __invalid());
+ __glibcxx_assert2(__b != memory_order_acq_rel, __invalid());
+ __glibcxx_assert2(__b != memory_order_consume, __invalid());
__atomic_store_n(&_M_i, __i, __m);
}
@@ -379,9 +383,9 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
memory_order __m = memory_order_seq_cst) volatile noexcept
{
memory_order __b = __m & __memory_order_mask;
- __glibcxx_assert(__b != memory_order_acquire);
- __glibcxx_assert(__b != memory_order_acq_rel);
- __glibcxx_assert(__b != memory_order_consume);
+ __glibcxx_assert2(__b != memory_order_acquire, __invalid());
+ __glibcxx_assert2(__b != memory_order_acq_rel, __invalid());
+ __glibcxx_assert2(__b != memory_order_consume, __invalid());
__atomic_store_n(&_M_i, __i, __m);
}
@@ -390,8 +394,8 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
load(memory_order __m = memory_order_seq_cst) const noexcept
{
memory_order __b = __m & __memory_order_mask;
- __glibcxx_assert(__b != memory_order_release);
- __glibcxx_assert(__b != memory_order_acq_rel);
+ __glibcxx_assert2(__b != memory_order_release, __invalid());
+ __glibcxx_assert2(__b != memory_order_acq_rel, __invalid());
return __atomic_load_n(&_M_i, __m);
}
@@ -400,8 +404,8 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
load(memory_order __m = memory_order_seq_cst) const volatile noexcept
{
memory_order __b = __m & __memory_order_mask;
- __glibcxx_assert(__b != memory_order_release);
- __glibcxx_assert(__b != memory_order_acq_rel);
+ __glibcxx_assert2(__b != memory_order_release, __invalid(
Re: [C PATCH] Reject shifts of float vectors by int count (PR c/84853)
On Wed, 14 Mar 2018, Jakub Jelinek wrote: > Hi! > > The change for better warnings on vector shifts unfortunately started > accepting even shifts of floating point vectors by int shift count, which is > something that shouldn't be supported and ICEs later on. > > Fixed thusly, bootstrapped/regtested on x86_64-linux and i686-linux, ok for > trunk? OK. -- Joseph S. Myers jos...@codesourcery.com
Re: [C++ PATCH] Fix up -Wdeprecated (PR c++/84222)
On Wed, Mar 14, 2018 at 6:26 PM, Jakub Jelinek wrote:
> As the following testcase shows, if we have a deprecated class, we warn
> about any uses, including e.g. arguments of methods of that class (how can
> one e.g. declare or define a copy ctor without warnings?).
>
> The following patch changes it, so that we don't warn about deprecated uses
> in methods of that deprecated class (warn about uses of other deprecated
> classes of course). There is still one xfailed case where we warn about
> template-id in the containing scope if the deprecated class is a template.
>
> clang++ warns about the bar (const C &, const C &) function, both about
> the parameters and about the use in the body (like g++) and doesn't warn
> inside of (perhaps uninstantiated only) templates at all (which I think is
> better that we do warn).
>
> Bootstrapped/regtested on x86_64-linux and i686-linux, ok for trunk?
>
> 2018-03-14 Jakub Jelinek
>
> PR c++/84222
> * cp-tree.h (cp_warn_deprecated_use): Declare.
> * tree.c (cp_warn_deprecated_use): New function.
> * typeck2.c (build_functional_cast): Use it.
> * decl.c (grokparms): Likewise.
I like these.
> (grokdeclarator): Likewise. Temporarily push nested class scope
> around grokparms call for out of class member definitions.
>
> * g++.dg/warn/deprecated.C (T::member3): Change dg-warning to
> dg-bogus.
> * g++.dg/warn/deprecated-6.C (T::member3): Likewise.
> * g++.dg/warn/deprecated-13.C: New test.
>
> --- gcc/cp/cp-tree.h.jj 2018-03-11 17:48:36.360061435 +0100
> +++ gcc/cp/cp-tree.h2018-03-14 11:49:58.924816419 +0100
> @@ -7064,6 +7064,7 @@ extern tree cxx_copy_lang_qualifiers (c
>
> extern void cxx_print_statistics (void);
> extern bool maybe_warn_zero_as_null_pointer_constant (tree, location_t);
> +extern void cp_warn_deprecated_use (tree);
>
> /* in ptree.c */
> extern void cxx_print_xnode(FILE *, tree, int);
> --- gcc/cp/tree.c.jj2018-03-07 22:51:58.671478659 +0100
> +++ gcc/cp/tree.c 2018-03-14 11:49:58.926816421 +0100
> @@ -5347,6 +5347,19 @@ cp_tree_code_length (enum tree_code code
> }
> }
>
> +/* Wrapper around warn_deprecated_use that doesn't warn for
> + current_class_type. */
> +
> +void
> +cp_warn_deprecated_use (tree node)
> +{
> + if (TYPE_P (node)
> + && current_class_type
> + && TYPE_MAIN_VARIANT (node) == current_class_type)
> +return;
> + warn_deprecated_use (node, NULL_TREE);
> +}
> +
> /* Implement -Wzero_as_null_pointer_constant. Return true if the
> conditions for the warning hold, false otherwise. */
> bool
> --- gcc/cp/typeck2.c.jj 2018-03-02 00:15:54.096781050 +0100
> +++ gcc/cp/typeck2.c2018-03-14 11:49:58.931816424 +0100
> @@ -2057,7 +2057,7 @@ build_functional_cast (tree exp, tree pa
>if (complain & tf_warning
> && TREE_DEPRECATED (type)
> && DECL_ARTIFICIAL (exp))
> - warn_deprecated_use (type, NULL_TREE);
> + cp_warn_deprecated_use (type);
> }
>else
> type = exp;
> --- gcc/cp/decl.c.jj2018-03-14 09:44:55.744974946 +0100
> +++ gcc/cp/decl.c 2018-03-14 12:18:08.094012453 +0100
> @@ -10448,7 +10448,7 @@ grokdeclarator (const cp_declarator *dec
> suppress reports of deprecated items. */
>if (type && TREE_DEPRECATED (type)
>&& deprecated_state != DEPRECATED_SUPPRESS)
> -warn_deprecated_use (type, NULL_TREE);
> +cp_warn_deprecated_use (type);
>if (type && TREE_CODE (type) == TYPE_DECL)
> {
>typedef_decl = type;
> @@ -10456,7 +10456,7 @@ grokdeclarator (const cp_declarator *dec
>if (TREE_DEPRECATED (type)
> && DECL_ARTIFICIAL (typedef_decl)
> && deprecated_state != DEPRECATED_SUPPRESS)
> - warn_deprecated_use (type, NULL_TREE);
> + cp_warn_deprecated_use (type);
> }
>/* No type at all: default to `int', and set DEFAULTED_INT
> because it was not a user-defined typedef. */
> @@ -11271,8 +11271,18 @@ grokdeclarator (const cp_declarator *dec
> explicitp = 2;
> }
>
> - arg_types = grokparms (declarator->u.function.parameters,
> - &parms);
> + tree pushed_scope = NULL_TREE;
> + if (funcdecl_p
> + && decl_context != FIELD
> + && inner_declarator->u.id.qualifying_scope
> + && CLASS_TYPE_P (inner_declarator->u.id.qualifying_scope))
> + pushed_scope
> + = push_scope (inner_declarator->u.id.qualifying_scope);
Can't we use ctype here?
Jason
Re: [C++ PATCH] Fix PLACEHOLDER_EXPR handling (PR c++/79937, PR c++/82410)
On Wed, Mar 14, 2018 at 6:33 PM, Jakub Jelinek wrote:
> The following patch is an attempt to fix PLACEHOLDER_EXPR handling.
> As e.g.
> struct Y
> {
> static Y bar (Y y) { return y; }
> int i;
> int n = bar (Y{2,i}).m + bar {Y{2,i,i}).n;
> int m = i;
> };
> is rejected - one can't use incomplete ctors which would need NSDMIs
> until the class is defined, I believe PLACEHOLDER_EXPRs can't be arbitrarily
> intermixed, rather some CONSTRUCTORs into which we've added the NSDMI
> expressions can contain PLACEHOLDER_EXPRs and other PLACEHOLDER_EXPRs can be
> only found inside such CONSTRUCTORs added earlier.
>
> So, this patch adds a new flag on CONSTRUCTORs, which acts as a barrier
> boundary for replace_placeholders, where we replace just PLACEHOLDER_EXPRs
> from the outermost expressions and don't dive into CONSTRUCTORs into which
> we've added other PLACEHOLDER_EXPRs - those will be handled later on
> separately, by cp_gimplify_init_expr calling replace_placeholders.
>
> Bootstrapped/regtested on x86_64-linux and i686-linux, ok for trunk?
>
> 2018-03-14 Jakub Jelinek
>
> PR c++/79937
> PR c++/82410
> * cp-tree.h (CONSTRUCTOR_PLACEHOLDER_BOUNDARY): Define.
> (find_placeholder): Declare.
> * tree.c (struct replace_placeholders_t): Add exp member.
> (replace_placeholders_r): Don't walk into ctors with
> CONSTRUCTOR_PLACEHOLDER_BOUNDARY flag set, unless they are equal to
> d->exp.
> (replace_placeholders): Initialize data.exp.
> (find_placeholders_r, find_placeholders): New functions.
> * typeck2.c (process_init_constructor_record,
> process_init_constructor_union): Set CONSTRUCTOR_PLACEHOLDER_BOUNDARY
> if adding NSDMI on which find_placeholder returns true.
>
> * g++.dg/cpp1y/pr79937-1.C: New test.
> * g++.dg/cpp1y/pr79937-2.C: New test.
> * g++.dg/cpp1y/pr79937-3.C: New test.
> * g++.dg/cpp1y/pr79937-4.C: New test.
> * g++.dg/cpp1y/pr82410.C: New test.
>
> --- gcc/cp/cp-tree.h.jj 2018-03-14 16:21:50.745925263 +0100
> +++ gcc/cp/cp-tree.h2018-03-14 15:57:51.171323825 +0100
> @@ -425,6 +425,7 @@ extern GTY(()) tree cp_global_trees[CPTI
>DECL_VTABLE_OR_VTT_P (in VAR_DECL)
>FUNCTION_RVALUE_QUALIFIED (in FUNCTION_TYPE, METHOD_TYPE)
>CALL_EXPR_REVERSE_ARGS (in CALL_EXPR, AGGR_INIT_EXPR)
> + CONSTRUCTOR_PLACEHOLDER_BOUNDARY (in CONSTRUCTOR)
> 6: IDENTIFIER_REPO_CHOSEN (in IDENTIFIER_NODE)
>DECL_CONSTRUCTION_VTABLE_P (in VAR_DECL)
>TYPE_MARKED_P (in _TYPE)
> @@ -4144,6 +4145,12 @@ more_aggr_init_expr_args_p (const aggr_i
> #define CONSTRUCTOR_C99_COMPOUND_LITERAL(NODE) \
>(TREE_LANG_FLAG_3 (CONSTRUCTOR_CHECK (NODE)))
>
> +/* True if this CONSTRUCTOR contains PLACEHOLDER_EXPRs referencing the
> + CONSTRUCTOR's type not nested inside another CONSTRUCTOR marked with
> + CONSTRUCTOR_PLACEHOLDER_BOUNDARY. */
> +#define CONSTRUCTOR_PLACEHOLDER_BOUNDARY(NODE) \
> + (TREE_LANG_FLAG_5 (CONSTRUCTOR_CHECK (NODE)))
> +
> #define DIRECT_LIST_INIT_P(NODE) \
> (BRACE_ENCLOSED_INITIALIZER_P (NODE) && CONSTRUCTOR_IS_DIRECT_INIT (NODE))
>
> @@ -7021,6 +7028,7 @@ extern tree array_type_nelts_top (tree)
> extern tree break_out_target_exprs (tree);
> extern tree build_ctor_subob_ref (tree, tree, tree);
> extern tree replace_placeholders (tree, tree, bool * = NULL);
> +extern bool find_placeholders (tree);
> extern tree get_type_decl (tree);
> extern tree decl_namespace_context (tree);
> extern bool decl_anon_ns_mem_p (const_tree);
> --- gcc/cp/tree.c.jj2018-03-14 11:49:58.926816421 +0100
> +++ gcc/cp/tree.c 2018-03-14 16:24:29.036987505 +0100
> @@ -3096,6 +3096,7 @@ build_ctor_subob_ref (tree index, tree t
> struct replace_placeholders_t
> {
>tree obj;/* The object to be substituted for a PLACEHOLDER_EXPR.
> */
> + tree exp;/* The outermost exp. */
>bool seen; /* Whether we've encountered a PLACEHOLDER_EXPR. */
>hash_set *pset;/* To avoid walking same trees multiple
> times. */
> };
> @@ -3134,7 +3135,12 @@ replace_placeholders_r (tree* t, int* wa
>{
> constructor_elt *ce;
> vec *v = CONSTRUCTOR_ELTS (*t);
> - if (d->pset->add (*t))
> + /* Don't walk into CONSTRUCTOR_PLACEHOLDER_BOUNDARY ctors
> + other than the d->exp one, those have PLACEHOLDER_EXPRs
> + related to another object. */
> + if ((CONSTRUCTOR_PLACEHOLDER_BOUNDARY (*t)
> +&& *t != d->exp)
> + || d->pset->add (*t))
> {
> *walk_subtrees = false;
> return NULL_TREE;
> @@ -3192,16 +3198,70 @@ replace_placeholders (tree exp, tree obj
> return exp;
>
>tree *tp = &exp;
> - hash_set pset;
> - replace_placeholders_t data = { obj, false, &pset };
> + /* Use
[PATCH] PR fortran/69395 -- don't exceed max allowed array dimensions
The attachedi patch detects situations where the sum of
an array's rank and corank exceeds the maximum allowed
by the Standard. Regression tested on x86_64-*-freebsd.
2018-03-14 Steven G. Kargl
PR fortran/69395
* decl.c (merge_array_spec): Limit the merging to maximum allowed
dimensions, and issue error message if limit is exceeded.
2018-03-14 Steven G. Kargl
PR fortran/69395
* gfortran.dg/pr69395.f90
--
Steve
Index: gcc/fortran/decl.c
===
--- gcc/fortran/decl.c (revision 258537)
+++ gcc/fortran/decl.c (working copy)
@@ -804,7 +804,7 @@ cleanup:
static bool
merge_array_spec (gfc_array_spec *from, gfc_array_spec *to, bool copy)
{
- int i;
+ int i, j;
if ((from->type == AS_ASSUMED_RANK && to->corank)
|| (to->type == AS_ASSUMED_RANK && from->corank))
@@ -822,8 +822,14 @@ merge_array_spec (gfc_array_spec *from, gfc_array_spec
for (i = 0; i < to->corank; i++)
{
- to->lower[from->rank + i] = to->lower[i];
- to->upper[from->rank + i] = to->upper[i];
+ /* Do not exceed the limits on lower[] and upper[]. gfortran
+ cleans up elsewhere. */
+ j = from->rank + i;
+ if (j >= GFC_MAX_DIMENSIONS)
+ break;
+
+ to->lower[j] = to->lower[i];
+ to->upper[j] = to->upper[i];
}
for (i = 0; i < from->rank; i++)
{
@@ -846,19 +852,33 @@ merge_array_spec (gfc_array_spec *from, gfc_array_spec
for (i = 0; i < from->corank; i++)
{
+ /* Do not exceed the limits on lower[] and upper[]. gfortran
+ cleans up elsewhere. */
+ j = to->rank + i;
+ if (j >= GFC_MAX_DIMENSIONS)
+ break;
+
if (copy)
{
- to->lower[to->rank + i] = gfc_copy_expr (from->lower[i]);
- to->upper[to->rank + i] = gfc_copy_expr (from->upper[i]);
+ to->lower[j] = gfc_copy_expr (from->lower[i]);
+ to->upper[j] = gfc_copy_expr (from->upper[i]);
}
else
{
- to->lower[to->rank + i] = from->lower[i];
- to->upper[to->rank + i] = from->upper[i];
+ to->lower[j] = from->lower[i];
+ to->upper[j] = from->upper[i];
}
}
}
+ if (to->rank + to->corank >= GFC_MAX_DIMENSIONS)
+{
+ gfc_error ("Sum of array rank %d and corank %d at %C exceeds maximum "
+ "allowed dimensions of %d",
+ to->rank, to->corank, GFC_MAX_DIMENSIONS);
+ to->corank = GFC_MAX_DIMENSIONS - to->rank;
+ return false;
+}
return true;
}
Index: gcc/testsuite/gfortran.dg/pr69395.f90
===
--- gcc/testsuite/gfortran.dg/pr69395.f90 (nonexistent)
+++ gcc/testsuite/gfortran.dg/pr69395.f90 (working copy)
@@ -0,0 +1,5 @@
+! { dg-do compile }
+! { dg-options "-fcoarray=single" }
+program p
+real, dimension(1,2,1,2,1,2,1,2), codimension[1,2,1,2,1,2,1,*] :: z ! { dg-error "allowed dimensions" }
+end
Re: [committed] Fix ICE for missing header fix-it hints with overlarge #line directives (PR c/84852)
Hi:
The fixits-pr84852-1.c fails on mips64el target.
FAIL: gcc.dg/fixits-pr84852-1.c (test for excess errors)
FAIL: gcc.dg/fixits-pr84852-1.c dg-regexp 25 not found:
".*fixits-pr84852.c:-812156810:25:"
see this patch:
diff --git a/gcc/testsuite/gcc.dg/fixits-pr84852-1.c
b/gcc/testsuite/gcc.dg/fixits-pr84852-1.c
index ed88434..98087ab 100644
--- a/gcc/testsuite/gcc.dg/fixits-pr84852-1.c
+++ b/gcc/testsuite/gcc.dg/fixits-pr84852-1.c
@@ -22,4 +22,4 @@ int foo (void) { return strlen(""); }
#endif
/* We need this, to consume a stray line marker for the bogus line. */
-/* { dg-regexp ".*fixits-pr84852.c:-812156810:25:" } */
+/* { dg-regexp ".*fixits-pr84852-1.c:-812156810:25:" } */
Thanks.
On Wed, Mar 14, 2018 at 10:10 PM, David Malcolm wrote:
> PR c/84852 reports an ICE inside diagnostic_show_locus when printing
> a diagnostic for a source file with a #line >= 2^31:
>
> #line 77
> int foo (void) { return strlen(""); }
>
> where we're attempting to print a fix-it hint at the top of the file
> and underline the "strlen" (two "line spans").
>
> The
> #line 77
> won't fix within the 32-bit linenum_type, and is truncated from
> 0x1cf977871
> to
>0xcf977871
> i.e. 3482810481 in decimal.
>
> Such a #line is reported by -pedantic and -pedantic-errors, but we
> shouldn't ICE.
>
> The ICE is an assertion failure within layout::calculate_line_spans,
> where the line spans have not been properly sorted.
>
> The layout_ranges are stored as int, rather than linenum_type,
> giving line -812156815 for the error, and line 1 for the fix-it hint.
>
> However, line_span uses linenum_type rather than int.
>
> line_span::comparator compares these values as int, and hence
> decides that (linenum_type)3482810481 aka (int)-812156815 is less
> than line 1.
>
> This leads to this assertion failing in layout::calculate_line_spans:
>
> 1105 gcc_assert (next->m_first_line >= current->m_first_line);
>
> since it isn't the case that 1 >= 3482810481.
>
> The underlying problem is the mix of types for storing line numbers:
> in parts of libcpp and diagnostic-show-locus.c we use linenum_type;
> in other places (including libcpp's expanded_location) we use int.
>
> I looked at using linenum_type throughout, but doing so turned into
> a large patch, so this patch fixes the ICE in a less invasive way
> by merely using linenum_type more consistently just within
> diagnostic-show-locus.c, and fixing line_span::comparator to properly
> handle line numbers (and line number differences) >= 2^31, by using
> a new helper function for linenum_type differences, computing the
> difference using long long, and using the sign of the difference
> (as the difference might not fit in the "int" return type imposed
> by qsort).
>
> (The new testcases assume the host's "unsigned int" is 32 bits; is
> there anything we support where that isn't the case?)
>
> I can self-approve the libcpp, diagnostic-show-locus.c and input.c
> changes.
>
> As part of the selftests, I needed to add ASSERT_GT and ASSERT_LT
> to selftest.h; I'm treating those parts of the patch as "obvious".
>
> Successfully bootstrapped and regression-tested on x86_64-pc-linux-gnu;
> adds 14 PASS results to gcc.sum.
>
> Committed to trunk as r258526.
>
> gcc/ChangeLog:
> PR c/84852
> * diagnostic-show-locus.c (class layout_point): Convert m_line
> from int to linenum_type.
> (line_span::comparator): Use linenum "compare" function when
> comparing line numbers.
> (test_line_span): New function.
> (layout_range::contains_point): Convert param "row" from int to
> linenum_type.
> (layout_range::intersects_line_p): Likewise.
> (layout::will_show_line_p): Likewise.
> (layout::print_source_line): Likewise.
> (layout::should_print_annotation_line_p): Likewise.
> (layout::print_annotation_line): Likewise.
> (layout::print_leading_fixits): Likewise.
> (layout::annotation_line_showed_range_p): Likewise.
> (struct line_corrections): Likewise for field m_row.
> (line_corrections::line_corrections): Likewise for param "row".
> (layout::print_trailing_fixits): Likewise.
> (layout::get_state_at_point): Likewise.
> (layout::get_x_bound_for_row): Likewise.
> (layout::print_line): Likewise.
> (diagnostic_show_locus): Likewise for locals "last_line" and
> "row".
> (selftest::diagnostic_show_locus_c_tests): Call test_line_span.
> * input.c (selftest::test_linenum_comparisons): New function.
> (selftest::input_c_tests): Call it.
> * selftest.c (selftest::test_assertions): Test ASSERT_GT,
> ASSERT_GT_AT, ASSERT_LT, and ASSERT_LT_AT.
> * selftest.h (ASSERT_GT): New macro.
> (ASSERT_GT_AT): New macro.
> (ASSERT_LT): New macro.
> (ASSERT_LT_AT): New macro.
>
> gcc/testsuite/ChangeLog:
> PR c/84852
> * gcc.dg/fixits
Re: C++ PATCH for c++/81236, missed 'this' capture with template-id in generic lambda
On Tue, Aug 29, 2017 at 5:37 PM, Jason Merrill wrote:
> We could approach this by extending that change to all generic
> lambdas, and that might be appropriate for GCC 7, but it seems to me
> that this approach will just mean any problems with doing all the
> normal processing in a template will remain latent until someone
> happens to use them in a generic lambda; instead, this patch removes
> the template special case and fixes the normal code to work properly
> in templates.
I noticed today that this caused a regression on the attached
testcases, because we weren't updating the type of the BASELINK after
instantiating the auto function.
Tested x86_64-pc-linux-gnu, applying to trunk.
commit d1d91f146d88b9d7442cce1e03edca55693de139
Author: Jason Merrill
Date: Wed Mar 14 16:27:08 2018 -0400
PR c++/81236 - auto variable and auto function
* pt.c (tsubst_baselink): Update the type of the BASELINK after
mark_used.
diff --git a/gcc/cp/pt.c b/gcc/cp/pt.c
index 14321816cde..2ea5fc79a2c 100644
--- a/gcc/cp/pt.c
+++ b/gcc/cp/pt.c
@@ -14700,9 +14700,16 @@ tsubst_baselink (tree baselink, tree object_type,
/* If lookup found a single function, mark it as used at this point.
(If lookup found multiple functions the one selected later by
overload resolution will be marked as used at that point.) */
- if (!template_id_p && !really_overloaded_fn (fns)
- && !mark_used (OVL_FIRST (fns), complain) && !(complain & tf_error))
-return error_mark_node;
+ if (!template_id_p && !really_overloaded_fn (fns))
+{
+ tree fn = OVL_FIRST (fns);
+ bool ok = mark_used (fn, complain);
+ if (!ok && !(complain & tf_error))
+ return error_mark_node;
+ if (ok && BASELINK_P (baselink))
+ /* We might have instantiated an auto function. */
+ TREE_TYPE (baselink) = TREE_TYPE (fn);
+}
if (BASELINK_P (baselink))
{
diff --git a/gcc/testsuite/g++.dg/cpp1y/auto-fn48.C b/gcc/testsuite/g++.dg/cpp1y/auto-fn48.C
new file mode 100644
index 000..bf9448e793e
--- /dev/null
+++ b/gcc/testsuite/g++.dg/cpp1y/auto-fn48.C
@@ -0,0 +1,15 @@
+// { dg-do compile { target c++14 } }
+
+template struct A
+{
+ static auto fn() { }
+ static void f()
+ {
+auto x = fn;
+ }
+};
+
+int main()
+{
+ A::f();
+}
diff --git a/gcc/testsuite/g++.dg/cpp1y/auto-fn49.C b/gcc/testsuite/g++.dg/cpp1y/auto-fn49.C
new file mode 100644
index 000..d2e490604a7
--- /dev/null
+++ b/gcc/testsuite/g++.dg/cpp1y/auto-fn49.C
@@ -0,0 +1,12 @@
+// CWG issue 2335
+// { dg-do compile { target c++14 } }
+
+template struct partition_indices {
+ static auto compute_right () {}
+ static constexpr auto right = compute_right;
+};
+auto foo () -> partition_indices<>;
+void f() {
+ auto x = foo();
+ auto y = x.right;
+}
C++ PATCH for c++/84801, ICE with unexpanded pack in lambda
Tested x86_64-pc-linux-gnu, applying to trunk.
commit c977f3b7668e49eb8f8fd3fdabb6cc7a47e37adc
Author: Jason Merrill
Date: Wed Mar 14 23:29:39 2018 -0400
PR c++/84801 - ICE with unexpanded pack in lambda.
* pt.c (check_for_bare_parameter_packs): Don't return early for a
lambda in non-template context.
diff --git a/gcc/cp/pt.c b/gcc/cp/pt.c
index 2ea5fc79a2c..32af3a4822e 100644
--- a/gcc/cp/pt.c
+++ b/gcc/cp/pt.c
@@ -4043,7 +4043,8 @@ check_for_bare_parameter_packs (tree t)
return false;
/* A lambda might use a parameter pack from the containing context. */
- if (current_class_type && LAMBDA_TYPE_P (current_class_type))
+ if (current_class_type && LAMBDA_TYPE_P (current_class_type)
+ && CLASSTYPE_TEMPLATE_INFO (current_class_type))
return false;
if (TREE_CODE (t) == TYPE_DECL)
diff --git a/gcc/testsuite/g++.dg/cpp1y/lambda-generic-variadic15.C b/gcc/testsuite/g++.dg/cpp1y/lambda-generic-variadic15.C
new file mode 100644
index 000..1de72712643
--- /dev/null
+++ b/gcc/testsuite/g++.dg/cpp1y/lambda-generic-variadic15.C
@@ -0,0 +1,5 @@
+// PR c++/84801
+// { dg-do compile { target c++14 } }
+
+int v;
+int main() { [](auto... c) { v = c; }(1); } // { dg-error "not expanded" }
C++ PATCH for c++/84820, no error for invalid qualified-id
The problem here was that although cp_parser_declarator returned
cp_error_declarator, we then wrapped it in another declarator, hiding
the problem.
Tested x86_64-pc-linux-gnu, applying to trunk.
commit 44b23ac745e9f249ff3971fcb4021facbbf8741c
Author: Jason Merrill
Date: Thu Mar 15 00:14:04 2018 -0400
PR c++/84820 - no error for invalid qualified-id.
* parser.c (cp_parser_make_indirect_declarator): Don't wrap
cp_error_declarator.
diff --git a/gcc/cp/parser.c b/gcc/cp/parser.c
index 0a82f415196..119f6c078f7 100644
--- a/gcc/cp/parser.c
+++ b/gcc/cp/parser.c
@@ -3823,7 +3823,7 @@ cp_parser_make_indirect_declarator (enum tree_code code, tree class_type,
cp_declarator *target,
tree attributes)
{
- if (code == ERROR_MARK)
+ if (code == ERROR_MARK || target == cp_error_declarator)
return cp_error_declarator;
if (code == INDIRECT_REF)
diff --git a/gcc/testsuite/g++.dg/parse/error21.C b/gcc/testsuite/g++.dg/parse/error21.C
index 8c717d7e811..920a4909e15 100644
--- a/gcc/testsuite/g++.dg/parse/error21.C
+++ b/gcc/testsuite/g++.dg/parse/error21.C
@@ -8,6 +8,5 @@ void foo()
// Check that we do not complain about an unused
// compiler-generated variable.
A& = a; // { dg-error "6:expected unqualified-id before '=' token" "6" }
- // { dg-error "8:'a' was not declared in this scope" "8" { target *-*-* } .-1 }
}
diff --git a/gcc/testsuite/g++.dg/parse/qualified5.C b/gcc/testsuite/g++.dg/parse/qualified5.C
new file mode 100644
index 000..dff934e98b1
--- /dev/null
+++ b/gcc/testsuite/g++.dg/parse/qualified5.C
@@ -0,0 +1,13 @@
+// PR c++/84820
+
+struct A {};
+
+template struct B : A
+{
+ B()
+ {
+A(&A::foo); // { dg-error "foo" }
+ }
+};
+
+B<0> b;
Re: [PATCH v2] Fix bogus strncpy source length warning on source bound by constant
On Wednesday 14 March 2018 08:40 PM, Richard Biener wrote: > Instead of building a tree from max you should use > > if (wi::to_widest (max) < wi::to_widest (wi::to_wide (dstsize))) > return; > > given compute_objsize is somewhat confused about the type it returns > a widest_int compare is required. > > Note I'm not too familiar with tree-ssa-strlen.c nor this part of the > warning code > so I'll not approve the patch but after fixing that it looks techincally ok. Thanks, I'll post a fixed up version soon. Siddhesh
