RE: [Patch,tree-optimization]: Add new path Splitting pass on tree ssa representation

2015-12-25 Thread Ajit Kumar Agarwal 
Hello Jeff:

I am out on vacation till 3rd Jan 2016.
Is it okay If I respond on the below once I am back in office.

Thanks & Regards
Ajit

-Original Message-
From: Jeff Law [mailto:l...@redhat.com] 
Sent: Wednesday, December 23, 2015 12:06 PM
To: Ajit Kumar Agarwal; Richard Biener
Cc: GCC Patches; Vinod Kathail; Shail Aditya Gupta; Vidhumouli Hunsigida; 
Nagaraju Mekala
Subject: Re: [Patch,tree-optimization]: Add new path Splitting pass on tree ssa 
representation

On 12/11/2015 02:11 AM, Ajit Kumar Agarwal wrote:
>
> Mibench/EEMBC benchmarks (Target Microblaze)
>
> Automotive_qsort1(4.03%), Office_ispell(4.29%), Office_stringsearch1(3.5%). 
> Telecom_adpcm_d( 1.37%), ospfv2_lite(1.35%).
I'm having a real tough time reproducing any of these results.  In fact, I'm 
having a tough time seeing cases where path splitting even applies to the 
Mibench/EEMBC benchmarks mentioned above.

In the very few cases where split-paths might apply, the net resulting assembly 
code I get is the same with and without split-paths.

How consistent are these results?

What functions are being affected that in turn impact performance?

What options are you using to compile the benchmarks?  I'm trying with
-O2 -fsplit-paths and -O3 in my attempts to trigger the transformation so that 
I can look more closely at possible heuristics.

Is this with the standard microblaze-elf target?  Or with some other target?

jeff

Re: [PATCH, RFC, gfortran] Multi-threaded random number generator

2015-12-25 Thread Janne Blomqvist 
On Fri, Dec 25, 2015 at 2:39 AM, Damian Rouson
 wrote:
> Does this patch change the behavior of multi-image programs the run with one
> thread per image, where each image an MPI rank?   I assume the answer is no.

AFAICT, no. Or well, as I mentioned previously, the sequence of random
numbers is different since a different generator is used.

> Just checking to be sure.
>
> Also, I frequently use the init_random_seed subroutine from the gfortran
> online documentation
> (https://gcc.gnu.org/onlinedocs/gfortran/RANDOM_005fSEED.html).  Will that
> need any modification based on the current patch?  In my usual use case (one
> thread per image), I assume nothing changes there.

It should continue working, although if said part of the patch is
accepted, in the future it should suffice to just call random_seed
with no arguments instead of init_random_seed or something like that.

FWIW, F2015 contains a random_init intrinsic which offers a bit more
control how the generator is seeded for co-array programs.

>
> Damian
>
>
>
> On Dec 23, 2015, at 2:29 PM, Janne Blomqvist 
> wrote:
>
> Hi,
>
> the GFortran random number generator (RANDOM_NUMBER and RANDOM_SEED
> intrinsics) has a number of issues that the attached preliminary patch
> tries to address.
>
> - 64-bit integers are available on all targets GFortran supports, and
> the vast majority of users nowadays use targets with native 64-bit
> capability.  Thus by using a PRNG that uses and generates 64-bit
> values we can get a bit of speedup compared to the current 32-bit
> generator.
>
> - The current implementation is a single stream generator protected by
> a mutex. This means that if multiple threads are calling
> RANDOM_NUMBER
>
> 1) It's impossible to provide repeatable streams by using the same
> seed, since thread scheduling is not deterministic.
>
> 2) Performance is not only bound by the performance of a single
> thread, but can easily be a lot slower due to lock contention.
>
> I have been thinking about how one could make use of a multi-threaded
> PRNG given the limitations of the RANDOM_NUMBER & RANDOM_SEED API, and
> I have come up with something that I think is usable.
>
> The attached patch replaces the current KISS generator by the late
> George Marsaglia with the xorshift1024* generator, an enhanced version
> of Marsaglias xorshift generator. It's a quite nice generator, e.g. it
>
> - passes the TestU1 suite.
>
> - has a quite long period, 2**1024 - 1. So even if one generates
> multiple seeds randomly, it's exceedingly unlikely that the streams
> will alias in any realistic timeframe.
>
> - furthermore, allows a "jump" function to quickly jump forwards
> 2**512 bits in the stream, which is nice for creating multiple
> independent streams. Thus, with a total period of 2**1024, it allows
> up to 2**512 substreams each providing 2**512 bits before any
> aliasing.
>
> - Code is relatively simple, similar to KISS.
>
> Now, in order to be able to use separate streams for each thread given
> the Fortran standard API, the patch is implemented as follows. There
> is a master_state, which is initially statically initialized. The
> per-thread state is stored in a thread-local variable, and is
> initially uninitialized.
>
> - When RANDOM_NUMBER is called, a check is made to see whether the
> per-thread generator state is initialized. If not, the state is
> copied from the master_state, and the jump() function is called N
> times, where N equals how many streams have previously been
> generated from the master_state (the njumps variable). When the
> per-thread generator state is initialized, a random number is
> generated by reading and updating the per-thread generator state.
>
> - When RANDOM_SEED(PUT=) is called, the master_state is updated with
> the new seed, njumps is reset to zero, and the current thread
> generator state is copied from master_state. Thus any new streams
> that are subsequently created use the new seed, whereas other
> existing streams will continue using their existing states.
>
> - When RANDOM_SEED is called without arguments, the master_seed and
> current thread seed is set to random data read from the OS
> /dev/urandom device. Otherwise like above.
>
> While the above description might appear a bit convoluted, I think the
> end results for users is somewhat intuitive and it supports the common
> use cases
>
> - For a single-threaded program, or a multi-threaded program that
> takes care to call RANDOM_NUMER/RANDOM_SEED from one thread only,
> the end result is just like with the current implementation.
>
> - For a multi-threaded program that doesn't call RANDOM_SEED, each
> thread gets its own deterministic random stream with up to 2**512
> bits before any aliasing occurs.
>
> - In order to get random initial seeds on each invocation of the program,
> just
> call random_seed without arguments, either before calling
> random_number from any threads, or then in each thread.
>
> Note that the patch is preliminary, it works so one can

Re: [PATCH, RFC, gfortran] Multi-threaded random number generator

2015-12-25 Thread Janne Blomqvist 
On Thu, Dec 24, 2015 at 7:54 PM, Steve Kargl
 wrote:
> On Thu, Dec 24, 2015 at 04:53:30PM +0200, Janne Blomqvist wrote:
>> On Thu, Dec 24, 2015 at 1:18 AM, Steve Kargl
>>  wrote:
>> > Two questions.
>> >
>> > 1) Does the patch deal with PR 52879?
>>
>> To be honest, I haven't tested.  FWIW, the paper at
>>
>> http://vigna.di.unimi.it/ftp/papers/xorshift.pdf
>>
>> contains results of some experiments on how quickly the generator
>> escapes from a low-entropy state.
>>
>> (I think one issue behind PR 52879 is that part of the seed is only
>> used for generating real(8/16) and are  thus unused for real(4))
>
> Currently, we have 3 KISS generators with different seeds (of course).
> FX added a pass over the seeds to mix them.  See the scramble_seed()
> and unscramble_seed() functions.

Not particularly related to that PR specifically, I've been thinking a
bit about how one could detect low entropy seeds. Apparently there
isn't any really straightforward test one can do on a bunch of data to
estimate the entropy. What apparently is used is to compress the data,
and then the compression factor can be seen as some kind of entropy
estimate. Although I suspect for as little data as the random seed
this won't work that well.

A really simple ad-hoc method would be to just run
__builtin_popcountll() over the seed (i.e. count the number of
non-zero bits). Then if the result is below or above some threshold
(that is, the seed is mostly zeros or mostly ones) do, well,
something. E.g. print a warning to stderr, discard the provided seed
and read a new seed from /dev/urandom, or something like that? This
won't of course catch a seed with a bit pattern like 010101010101.. ,
but maybe it's still better than nothing?

>> > 2) Does it maintain the correspondence between a REAL(4) and
>> >REAL(8) stream if the same seeds are used?  For example,
>> >
>> > program foo
>> >integer, parameter :: seed(12) = [1, 12, 123, 1234, 12345, 123456, &
>> >&  654321, 54321, 4321, 321, 21, 1]
>> >real(4) x
>> >real(8) y
>> >call random_seed(put=seed)
>> >call random_number(x)
>> >call random_seed(put=seed)
>> >call random_number(y)
>> >print *, x, y
>> > end program foo
>> >
>> > %  gfc -o z r.f90 && ./z
>> >   0.181959510  0.18195952290401995
>>
>> No, it doesn't do this. Currently each thread only has a single set of
>> state variables (vs. 3 for the current). Additionally, for real(4), a
>> single 64-bit random value is used to create two real(4) variables,
>> but the performance advantage of this isn't huge compared to the naive
>> implementation of discarding half of the 64 random bits per call.
>> OTOH, it's not particularly hard to do this in user code if one wants
>> to, so is this feature really worth it?
>
> IHMO, this a nice feature to have.  One can easily test an algorithm
> in REAL(4), REAL(8), REAL(10), and REAL(16) where the high order bits
> all match to determine a suitable precision to use.  An obvious
> outcome is choosing a precision to balance performance vs accuracy.

Yes, I understand this. I just wonder whether it's useful enough that
it's worth doing by default and have everyone pay the cost (lower
performance for real(4), larger state, slower escape from a low
entropy state for real(16))? Alternatively, it's simple to have a
wrapper routine that calls the highest precision random_number for
testing, right?

>
> So, your mapping is
>
> PRNG stream: |--64-|--64-|  2 64-bit xorshift values.
> REAL(4): |--24--|--24--|--24--|--24--|  4 values (24-bit significand).
> REAL(8): |-53xx|-53xx|  2 values (53-bit significand).
>REAL(10): |--64-|--64-|  2 values (64-bit significand).
>REAL(16): |---113-|  1 value  (113-bit significand).
>
> The current mapping is
>
> PRNG stream: |--32--|--32--|--32--|--32--|  4 32-bit KISS values.
> REAL(4): |--24--|xx|xx|xx|  4 values (24-bit significand).
> REAL(8): |-53xx|x|  2 values (53-bit significand).
>REAL(10): |--64-|x|  2 values (64-bit significand).
>REAL(16): |---113-|  1 value  (113-bit significand).
>
> where x means unused bits.

Roughly, yes. Or well, there is some unused bits in the real(4)
generation. Note that none of the arandom_rX functions that convert
from uint{32,64}_t to realN are modified by the patch.

-- 
Janne Blomqvist

Re: [PATCH] Avoid ifcvt ICE on conditional return followed by trap (PR target/69015)

2015-12-25 Thread Eric Botcazou 
> This patch just disables that transformation, IMHO trading conditional
> return + unconditional trap with conditional trap + unconditional return
> isn't worth it.
> 
> Martin Sebor has kindly bootstrapped/regtested this on powerpc64le-linux,
> ok for trunk?
> 
> 2015-12-23  Jakub Jelinek  
> 
>   PR target/69015
>   * ifcvt.c (find_cond_trap): Give up if returnjump_p (jump).
> 
>   * gcc.dg/pr69015.c: New test.

OK, thanks.

-- 
Eric Botcazou

Re: [PATCH 1/2] [graphite] add more dumps on data dependence graph

2015-12-25 Thread Gerald Pfeifer 
Hi Sebastian,

On Mon, 14 Dec 2015, Sebastian Pop wrote:
>  gcc/graphite-dependences.c| 31 +++
>  gcc/graphite-poly.c   | 15 ++-
>  gcc/graphite-scop-detection.c | 21 -

on December 17th 2015, my nightly bootstrap (on i386-unknown-freebsd10.1,
but I don't think this is material) started to fail as follows:

  /scratch/tmp/gerald/gcc-HEAD/gcc/graphite-scop-detection.c:1892:17: 
  note: in instantiation of member function 'vec::safe_push'
  requested here
  scop->drs.safe_push (dr_info (dr, pbb));
^

>From what I can see, this code was added by your patch:

> @@ -1879,7 +1879,18 @@ gather_bbs::before_dom_children (basic_block bb)
>int i;
>data_reference_p dr;
>FOR_EACH_VEC_ELT (gbb->data_refs, i, dr)
> -scop->drs.safe_push (dr_info (dr, pbb));
> +{
> +  DEBUG_PRINT (dp << "Adding memory ";
> +if (dr->is_read)
> +  dp << "read: ";
> +else
> +  dp << "write: ";
> +print_generic_expr (dump_file, dr->ref, 0);
> +dp << "\nFrom stmt: ";
> +print_gimple_stmt (dump_file, dr->stmt, 0, 0));
> +
> +  scop->drs.safe_push (dr_info (dr, pbb));
> +}

The system in question has isl 0.15 installed.

Gerald

[PATCH][PR 67425] Fix docs for -frandom-seed

2015-12-25 Thread Yury Gribov 

Hi all,

this patch reverts invalid documentation change -frandom-seed which was 
introduced by myself in r216773 a year ago.


I've checked the generated man and the only test for -frandom-seed 
(gcc.dg/pr61868.c).


Ok for trunk?  I also want to backport to GCC5 branch.

-Yura
>From 23f8c38f593a18c5783949f7c2225b49685fedfc Mon Sep 17 00:00:00 2001
From: Yury Gribov 
Date: Fri, 25 Dec 2015 13:57:28 +0300
Subject: [PATCH] Fix docs for -frandom-seed to allow string arguments.

2015-12-25  Yury Gribov  

	PR driver/67425
	* common.opt (frandom-seed): Fix parameter name.
	* doc/invoke.texi (frandom-seed): Ditto.
---
 gcc/common.opt  | 2 +-
 gcc/doc/invoke.texi | 6 +++---
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/gcc/common.opt b/gcc/common.opt
index 23f394d..1f0daf0 100644
--- a/gcc/common.opt
+++ b/gcc/common.opt
@@ -1909,7 +1909,7 @@ Common Var(common_deferred_options) Defer
 
 frandom-seed=
 Common Joined RejectNegative Var(common_deferred_options) Defer
--frandom-seed=	Make compile reproducible using .
+-frandom-seed=	Make compile reproducible using .
 
 ; This switch causes the command line that was used to create an
 ; object file to be recorded into the object file.  The exact format
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 4e2cf8f..ff14f70 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -364,7 +364,7 @@ Objective-C and Objective-C++ Dialects}.
 -fmem-report -fpre-ipa-mem-report -fpost-ipa-mem-report -fprofile-arcs @gol
 -fopt-info @gol
 -fopt-info-@var{options}@r{[}=@var{file}@r{]} @gol
--frandom-seed=@var{number} -fsched-verbose=@var{n} @gol
+-frandom-seed=@var{string} -fsched-verbose=@var{n} @gol
 -fsel-sched-verbose -fsel-sched-dump-cfg -fsel-sched-pipelining-verbose @gol
 -fstack-usage  -ftest-coverage  -ftime-report -fvar-tracking @gol
 -fvar-tracking-assignments  -fvar-tracking-assignments-toggle @gol
@@ -7464,7 +7464,7 @@ the first option takes effect and the subsequent options are
 ignored. Thus only @file{vec.miss} is produced which contains
 dumps from the vectorizer about missed opportunities.
 
-@item -frandom-seed=@var{number}
+@item -frandom-seed=@var{string}
 @opindex frandom-seed
 This option provides a seed that GCC uses in place of
 random numbers in generating certain symbol names
@@ -7473,7 +7473,7 @@ place unique stamps in coverage data files and the object files that
 produce them.  You can use the @option{-frandom-seed} option to produce
 reproducibly identical object files.
 
-The @var{number} should be different for every file you compile.
+The @var{string} should be different for every file you compile.
 
 @item -fsched-verbose=@var{n}
 @opindex fsched-verbose
-- 
1.9.1

Re: [PATCH 5/5] Fix intransitive comparison in dr_group_sort_cmp

2015-12-25 Thread Yury Gribov 

On 12/19/2015 01:30 AM, Yuri Gribov wrote:

On Fri, Dec 18, 2015 at 11:20 PM, Yury Gribov  wrote:

On 12/17/2015 03:51 PM, Richard Biener wrote:


On Thu, 17 Dec 2015, Yury Gribov wrote:


On 12/17/2015 02:57 PM, Richard Biener wrote:


On Thu, 17 Dec 2015, Yury Gribov wrote:


That's an interesting one. The original comparison function assumes
that
operand_equal_p(a,b) is true iff compare_tree(a, b) == 0.
Unfortunately that's not true (functions are written by different
authors).

This causes subtle violation of transitiveness.

I believe removing operand_equal_p should preserve the intended
semantics
(same approach taken in another comparison function in this file -
comp_dr_with_seg_len_pair).

Cc-ing Cong Hou and Richard who are the authours.



I don't think the patch is good.  compare_tree really doesn't expect
equal elements (and it returning zero is bad or a bug).



Hm but that's how it's used in other comparator in this file
(comp_dr_with_seg_len_pair).



But for sure

switch (code)
  {
  /* For const values, we can just use hash values for comparisons.  */
  case INTEGER_CST:
  case REAL_CST:
  case FIXED_CST:
  case STRING_CST:
  case COMPLEX_CST:
  case VECTOR_CST:
{
  hashval_t h1 = iterative_hash_expr (t1, 0);
  hashval_t h2 = iterative_hash_expr (t2, 0);
  if (h1 != h2)
return h1 < h2 ? -1 : 1;
  break;
}

doesn't detect un-equality correctly (it assumes the hash is
collision-free).

Also note that operator== of dr_with_seg_len again also uses
operand_equal_p (plus compare_tree).

IMHO compare_tree should be cleaned up with respect to what
trees we expect here (no REAL_CSTs for example) and properly
do comparisons.


But it's also
"lazy" in that it will return 0 when it hopes a further disambiguation
inside dr_group_sort_cmp on a different field will eventually lead to
a non-zero compare_tree.

So eventually if compare_tree returns zero we have to fall back to the
final disambiguator using gimple_uid.

That said, I'd like to see the testcase where you observe an
intransitive comparison.



Let me dig my debugging logs (I'll send detailed repro tomorrow).


Added home address.


Richard,

I was doing my original testing on an older GCC (actually 4.9) and it
seems that this particular issue does not reproduce on current trunk.
But from what I can see the problem is still in the code which I'll
now try to explain.

Here's the problem that was detected by the tool:

(gdb) p dr_group_sort_cmp($dr1,$dr2)
$1 = -1
(gdb) p dr_group_sort_cmp($dr2,$dr3)
$2 = -1
(gdb) p dr_group_sort_cmp($dr1,$dr3)
$3 = 1

In other words, dr1 < dr2 and dr2 < dr3 but dr1 > dr3 (which is a
violation of transitivity axiom and will generally drive qsort mad).
Let's see why that happens.

Comparison starts at base addresses which are

(gdb) cal debug_generic_expr($ba1)
b_7(D) + (sizetype) i_69 * 4
(gdb) cal debug_generic_expr($ba2)
a_12(D) + (sizetype) ((long unsigned int) i_69 * 4)
(gdb) cal debug_generic_expr($ba3)
b_7(D) + (sizetype) ((long unsigned int) i_69 * 4)

Now here are results for operand_equals_p:

(gdb) cal operand_equal_p($ba1,$ba2,0)
$1 = 0
(gdb) cal operand_equal_p($ba2,$ba3,0)
$3 = 0

This means that to compare dr1 vs. dr2 and dr2 vs. dr3 we use compare_tree:

(gdb) cal compare_tree($ba1,$ba2)
$4 = -1
(gdb) cal compare_tree($ba2,$ba3)
$5 = -1

For dr1 vs. dr3 situation is more interesting. We continue with other checks
in dr_group_sort_cmp. Everything is equal:

(gdb) p dr_equal_offsets_p(*$dr1,*$dr3)
$7 = true
(gdb) p $dr1.is_read
$9 = false
(gdb) p $dr3.is_read
$11 = false
(gdb) cal 
operand_equal_p($dr1.ref.typed.type.type_common.size_unit,$dr3.ref.typed.type.type_common.size_unit,0)
$15 = 1
(gdb) cal operand_equal_p($dr1.innermost.step,$dr3.innermost.step,0)
$16 = 1

Until the very end where we compare initial values:

(gdb) cal tree_int_cst_compare($dr1.innermost.init,$dr3.innermost.init,0)
$18 = 1

I think the core reason is probably that pattern that's used here i.e.
   if(P(x,y))
 return cmp1(x,y);
   return cmp2(x,y);
will in general not be a valid total ordering even if cmp1 or cmp2 are.
(In our case P = operand_equals_p, cmp1 = compare_tree, cmp2 =
tree_int_cst_compare).

FTR I compiled the attached repro with 4.9.3 like this:
$ ./cc1plus -quiet -O2 -ftree-vectorize repro.i


Richard,

What's your call on this? Do you want a GCC6-relevant repro?

/Yura

[CilkPlus] fix issues when cilk_spawn is used with nontrivial expressions

2015-12-25 Thread Ryan Burn 
This patch fixes issues with cilk_spawn where bad diagnostics are
emitted for expressions invoking conversion operators or constructor
calls (PR69024, PR68997).

It also fixes an issue with a missing CLEANUP_POINT_EXPR that causes
an ICE when gimplifying code containing a temporary with a destructor
(PR69048)

Bootstrapped and regression tested on x86_64-linux

2015-12-25  Ryan Burn  

   PR cilkplus/69024, PR cilkplus/68997, PR cilkplus/PR69048
   * cilk.c (cilk_detect_spawn_and_unwrap): Use recursive function
find_spawn to search for the CILK_SPAWN_STMT.
 (cilk_ignorable_spawn_rhs_op): Also ignore COMPOUND_EXPR.
 (find_spawn): New.
 (is_conversion_operator_function_decl_p): New.
 (is_conversion_operator_call_p): New.
 (is_unary_constructor_aggr_init_p): New.
 (is_conversion_operator_aggr_init_p): New.
 (extract_free_variables): Don't extract the slot variable of
an AGGR_INIT_EXPR.
 (create_cilk_wrapper_body): Add CLEANUP_POINT_EXPR to the
spawn expression.

   * gcc/testsuite/g++.dg/cilk-plus/CK/pr68997.cc : New test.

   * gcc/testsuite/g++.dg/cilk-plus/CK/pr69024.cc : New test.

   * gcc/testsuite/g++.dg/cilk-plus/CK/pr69048.cc : New test.

   * gcc/testsuite/g++.dg/cilk-plus/CK/pr68001.cc : Removed check
depending on bad diagnostics.


cilk_spawn.patch
Description: Binary data

Re: [PATCH] Fix the remaining PR c++/24666 blockers (arrays decay to pointers too early)

2015-12-25 Thread Patrick Palka 
On Thu, Dec 24, 2015 at 9:41 PM, Jason Merrill  wrote:
> On 12/24/2015 12:57 PM, Patrick Palka wrote:
>>
>> So instead, this patch
>> takes the easier route and just adds preparatory logic to decay these
>> dependent array parameter types where necessary so that by the time
>> unify() is called it will be looking at two decayed T * types.  There
>> only seem to be three places where this needs to be done.
>
>
> Does it not make sense to do this in maybe_adjust_types_for_deduction?

That alone would not be sufficient because more_specialized_fn()
doesn't call maybe_adjust_types_for_deduction() beforehand, yet we
have to do the decaying there too (and on both types, not just one of
them).

And maybe_adjust_types_for_deduction() seems to operate on the
presumption that one type is the parameter type and one is the
argument type. But in more_specialized_fn() and in get_bindings() we
are really working with two parameter types and have to decay them
both. So sometimes we have to decay one of the types that are
eventually going to get passed to unify(), and other times we want to
decay both types that are going to get passed to unify().
maybe_adjust_types_for_deduction() seems to only expect the former
case.

Finally, maybe_adjust_types_for_deduction() is not called when
unifying a nested function declarator (because it is guarded by the
subr flag in unify_one_argument), so doing it there we would also
regress in the following test case:

void foo (int *);

template 
void bar (void (T[5]));

void
baz (void)
{
  bar (foo); // type of function foo will no longer unify with void
(T[5]) so deduction of type T now fails
}

Re: [PATCH 1/2] [graphite] add more dumps on data dependence graph

2015-12-25 Thread Sebastian Pop 
On Fri, Dec 25, 2015 at 4:40 AM, Gerald Pfeifer  wrote:
> Hi Sebastian,
>
> On Mon, 14 Dec 2015, Sebastian Pop wrote:
>>  gcc/graphite-dependences.c| 31 +++
>>  gcc/graphite-poly.c   | 15 ++-
>>  gcc/graphite-scop-detection.c | 21 -
>
> on December 17th 2015, my nightly bootstrap (on i386-unknown-freebsd10.1,
> but I don't think this is material) started to fail as follows:
>
>   /scratch/tmp/gerald/gcc-HEAD/gcc/graphite-scop-detection.c:1892:17:
>   note: in instantiation of member function 'vec vl_ptr>::safe_push'
>   requested here
>   scop->drs.safe_push (dr_info (dr, pbb));
> ^

I do not see what the error is.  Do you happen to have
the few lines with the error before this note?

>
> From what I can see, this code was added by your patch:
>
>> @@ -1879,7 +1879,18 @@ gather_bbs::before_dom_children (basic_block bb)
>>int i;
>>data_reference_p dr;
>>FOR_EACH_VEC_ELT (gbb->data_refs, i, dr)
>> -scop->drs.safe_push (dr_info (dr, pbb));
>> +{
>> +  DEBUG_PRINT (dp << "Adding memory ";
>> +if (dr->is_read)
>> +  dp << "read: ";
>> +else
>> +  dp << "write: ";
>> +print_generic_expr (dump_file, dr->ref, 0);
>> +dp << "\nFrom stmt: ";
>> +print_gimple_stmt (dump_file, dr->stmt, 0, 0));
>> +
>> +  scop->drs.safe_push (dr_info (dr, pbb));
>> +}

This code does not change the safe_push call.

Thanks Gerald for reporting this problem.
Sebastian

Re: [patch] Fix dynamic linker spec for FreeBSD powerpc64

2015-12-25 Thread Andreas Tobler 

On 22.12.15 20:18, Andreas Tobler wrote:

Hi all,

The attached patch fixes a problem you get if you build dynamic binaries
for a 32-bit powerpc target on a 64-bit powerpc host.

At the time I did this port I didn't fully understand all the scenarios
you might run into.

The issue is this, on all FreeBSD archs the interpreter is ld-elf.so.1.
On powerpc64 we have also an ld-elf32.so.1 for 32-bit binaries. In case
we run a 32-bit binary on a 64-bit host the RTLD reroutes the call to
this ld-elf32.so.1.

Up to now this rerouting didn't happen since gcc used the ld-elf32.so.1
instead. The binary runs fine on the 64-bit host since the RTLD finds a
ld-elf32.so.1.

But now when I take this binary to a 32-bit host I can't run it since
the RTLD does not find the ld-elf32.so.1.

The patch fixes this and simplifies the LINK_OS_FREEBSD_SPEC_DEF for
FreeBSD powerpc64.

If there are no major objections I'm going to apply this patch to trunk,
gcc-5 and gcc-49 branch in the next days. It is FreeBSD powerpc64 only
and it is a bug.


Applied on the mentioned branches.

Andreas



2015-12-22  Andreas Tobler  

* config/rs6000/freebsd64.h: Delete FREEBSD_DYNAMIC_LINKER32/64
defines. Use FBSD_DYNAMIC_LINKER instead.
Rename and simplify LINK_OS_FREEBSD_SPEC_DEF32/64 to
LINK_OS_FREEBSD_SPEC_DEF.

[RFC][PATCH, ARM 0/8] ARMv8-M Security Extensions

2015-12-25 Thread Thomas Preud'homme 
[Sending on behalf of Andre Vieira]

Hello,

This patch series aims at implementing an alpha status support for ARMv8-M's 
Security Extensions. It is only posted as RFC at this stage. You can find the 
specification of ARMV8-M Security Extensions in: ARM®v8-M Security Extensions: 
Requirements on Development Tools 
(http://infocenter.arm.com/help/topic/com.arm.doc.ecm0359818/index.html).

We currently:
- do not support passing arguments or returning on the stack for 
cmse_nonsecure_{call,entry} functions,
- do not guarantee padding bits are cleared for arguments or return variables 
of cmse_nonsecure_{call,entry} functions,
- only test Security Extensions for -mfpu=fpv5-d16 and fpv5-sp-d16 and only 
support single and double precision FPU's with d16.


Andre Vieira (8):
 Add support for ARMv8-M's Security Extensions flag and intrinsics
 Add RTL patterns for thumb1 push/pop
 Handling ARMv8-M Security Extension's cmse_nonsecure_entry attribute
 ARMv8-M Security Extension's cmse_nonsecure_entry: __acle_se label and bxns 
return
 ARMv8-M Security Extension's cmse_nonsecure_entry: clear registers
 Handling ARMv8-M Security Extension's cmse_nonsecure_call attribute
 ARMv8-M Security Extension's cmse_nonsecure_call: use __gnu_cmse_nonsecure_call
 Added support for ARMV8-M Security Extension cmse_nonsecure_caller intrinsic


Cheers,

Andre

[RFC][PATCH, ARM 1/8] Add support for ARMv8-M's Security Extensions flag and intrinsics

2015-12-25 Thread Thomas Preud'homme 
[Sending on behalf of Andre Vieira]

Hello,

This patch adds the support of the '-mcmse' option to enable ARMv8-M's Security 
Extensions and supports the following intrinsics:
cmse_TT
cmse_TT_fptr
cmse_TTT
cmse_TTT_fptr
cmse_TTA
cmse_TTA_fptr
cmse_TTAT
cmse_TTAT_fptr
cmse_check_address_range
cmse_check_pointed_object
cmse_is_nsfptr
cmse_nsfptr_create

It also defines the mandatory cmse_address_info struct and the 
__ARM_FEATURE_CMSE macro.
See Chapter 4, Sections 5.2, 5.3 and 5.6 of ARM®v8-M Security Extensions: 
Requirements on Development Tools 
(http://infocenter.arm.com/help/topic/com.arm.doc.ecm0359818/index.html).

*** gcc/ChangeLog ***
2015-10-27  Andre Vieira
Thomas Preud'homme  

* gcc/config.gcc (extra_headers): Added arm_cmse.h.
* gcc/config/arm/arm-arches.def (ARM_ARCH):
  (armv8-m): Add FL2_CMSE.
  (armv8-m.main): Likewise.
  (armv8-m.main+dsp): Likewise.
* gcc/config/arm/arm-c.c
  (arm_cpu_builtins): Added __ARM_FEATURE_CMSE macro.
* gcc/config/arm/arm-protos.h 
  (arm_is_constant_pool_ref): Define FL2_CMSE.
* gcc/config/arm.c (arm_arch_cmse): New.
  (arm_option_override): New error for unsupported cmse target.
* gcc/config/arm/arm.h (arm_arch_cmse): New.
* gcc/config/arm/arm.opt (mcmse): New.
* gcc/doc/invoke.texi (ARM Options): Add -mcmse.
* gcc/config/arm/arm_cmse.h: New file.
* libgcc/config/arm/cmse.c: Likewise.
* libgcc/config/arm/t-arm (HAVE_CMSE): New.


*** gcc/testsuite/ChangeLog ***
2015-10-27  Andre Vieira
Thomas Preud'homme  

* gcc.target/arm/cmse/cmse.exp: New.
* gcc.target/arm/cmse/cmse-1.c: New.
* gcc.target/arm/cmse/cmse-12.c: New.
* lib/target-supports.exp
  (check_effective_target_arm_cmse_ok): New.

We welcome any comments.

Cheers,

Andre

RE: [RFC][PATCH, ARM 1/8] Add support for ARMv8-M's Security Extensions flag and intrinsics

2015-12-25 Thread Thomas Preud'homme 
And even better, with the patch (see below ChangeLog entries)! Sigh...

> From: gcc-patches-ow...@gcc.gnu.org [mailto:gcc-patches-
> ow...@gcc.gnu.org] On Behalf Of Thomas Preud'homme
> Sent: Saturday, December 26, 2015 9:41 AM
> To: gcc-patches@gcc.gnu.org; Richard Earnshaw; Ramana Radhakrishnan;
> Kyrylo Tkachov
> Subject: [RFC][PATCH, ARM 1/8] Add support for ARMv8-M's Security
> Extensions flag and intrinsics
> 
> [Sending on behalf of Andre Vieira]
> 
> Hello,
> 
> This patch adds the support of the '-mcmse' option to enable ARMv8-M's
> Security Extensions and supports the following intrinsics:
> cmse_TT
> cmse_TT_fptr
> cmse_TTT
> cmse_TTT_fptr
> cmse_TTA
> cmse_TTA_fptr
> cmse_TTAT
> cmse_TTAT_fptr
> cmse_check_address_range
> cmse_check_pointed_object
> cmse_is_nsfptr
> cmse_nsfptr_create
> 
> It also defines the mandatory cmse_address_info struct and the
> __ARM_FEATURE_CMSE macro.
> See Chapter 4, Sections 5.2, 5.3 and 5.6 of ARM®v8-M Security
> Extensions: Requirements on Development Tools
> (http://infocenter.arm.com/help/topic/com.arm.doc.ecm0359818/index
> .html).
> 
> *** gcc/ChangeLog ***
> 2015-10-27  Andre Vieira
> Thomas Preud'homme  
> 
> * gcc/config.gcc (extra_headers): Added arm_cmse.h.
> * gcc/config/arm/arm-arches.def (ARM_ARCH):
>   (armv8-m): Add FL2_CMSE.
>   (armv8-m.main): Likewise.
>   (armv8-m.main+dsp): Likewise.
> * gcc/config/arm/arm-c.c
>   (arm_cpu_builtins): Added __ARM_FEATURE_CMSE macro.
> * gcc/config/arm/arm-protos.h
>   (arm_is_constant_pool_ref): Define FL2_CMSE.
> * gcc/config/arm.c (arm_arch_cmse): New.
>   (arm_option_override): New error for unsupported cmse target.
> * gcc/config/arm/arm.h (arm_arch_cmse): New.
> * gcc/config/arm/arm.opt (mcmse): New.
> * gcc/doc/invoke.texi (ARM Options): Add -mcmse.
> * gcc/config/arm/arm_cmse.h: New file.
> * libgcc/config/arm/cmse.c: Likewise.
> * libgcc/config/arm/t-arm (HAVE_CMSE): New.
> 
> 
> *** gcc/testsuite/ChangeLog ***
> 2015-10-27  Andre Vieira
> Thomas Preud'homme  
> 
> * gcc.target/arm/cmse/cmse.exp: New.
> * gcc.target/arm/cmse/cmse-1.c: New.
> * gcc.target/arm/cmse/cmse-12.c: New.
> * lib/target-supports.exp
>   (check_effective_target_arm_cmse_ok): New.

diff --git a/gcc/config.gcc b/gcc/config.gcc
index 
882e4134b4c883a5fe0f19996e54ac63769bada1..701082e82ee3da6c5bf00da799293c92af8624ff
 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -321,7 +321,7 @@ arc*-*-*)
 arm*-*-*)
cpu_type=arm
extra_objs="arm-builtins.o aarch-common.o"
-   extra_headers="mmintrin.h arm_neon.h arm_acle.h"
+   extra_headers="mmintrin.h arm_neon.h arm_acle.h arm_cmse.h"
target_type_format_char='%'
c_target_objs="arm-c.o"
cxx_target_objs="arm-c.o"
diff --git a/gcc/config/arm/arm-arches.def b/gcc/config/arm/arm-arches.def
index 
1d0301a3b9414127d387834584f3e42c225b6d3f..52518e64e07a1b085ae5ed1932b598e064258971
 100644
--- a/gcc/config/arm/arm-arches.def
+++ b/gcc/config/arm/arm-arches.def
@@ -58,11 +58,11 @@ ARM_ARCH("armv7e-m", cortexm4,  7EM,
ARM_FSET_MAKE_CPU1 (FL_CO_PROC |  FL_F
 ARM_ARCH("armv8-a", cortexa53,  8A,ARM_FSET_MAKE_CPU1 (FL_CO_PROC |
 FL_FOR_ARCH8A))
 ARM_ARCH("armv8-a+crc",cortexa53, 8A,   ARM_FSET_MAKE_CPU1 (FL_CO_PROC | 
FL_CRC32  | FL_FOR_ARCH8A))
 ARM_ARCH("armv8-m.base", cortexm0, 8M_BASE,
-ARM_FSET_MAKE_CPU1 ( FL_FOR_ARCH8M_BASE))
+ARM_FSET_MAKE (  FL_FOR_ARCH8M_BASE, FL2_CMSE))
 ARM_ARCH("armv8-m.main", cortexm7, 8M_MAIN,
-ARM_FSET_MAKE_CPU1(FL_CO_PROC |  FL_FOR_ARCH8M_MAIN))
+ARM_FSET_MAKE (FL_CO_PROC |  FL_FOR_ARCH8M_MAIN, FL2_CMSE))
 ARM_ARCH("armv8-m.main+dsp", cortexm7, 8M_MAIN,
-ARM_FSET_MAKE_CPU1(FL_CO_PROC | FL_ARCH7EM | FL_FOR_ARCH8M_MAIN))
+ARM_FSET_MAKE (FL_CO_PROC | FL_ARCH7EM | FL_FOR_ARCH8M_MAIN, FL2_CMSE))
 ARM_ARCH("iwmmxt",  iwmmxt, 5TE,   ARM_FSET_MAKE_CPU1 (FL_LDSCHED | 
FL_STRONG | FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT))
 ARM_ARCH("iwmmxt2", iwmmxt2,5TE,   ARM_FSET_MAKE_CPU1 (FL_LDSCHED | 
FL_STRONG | FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT | FL_IWMMXT2))
 
diff --git a/gcc/config/arm/arm-c.c b/gcc/config/arm/arm-c.c
index 
7dee28ec52df68f8c7a60fe66e1b049fed39c1c0..459ddbb1f41947cbeeb1a291ab7395843528e562
 100644
--- a/gcc/config/arm/arm-c.c
+++ b/gcc/config/arm/arm-c.c
@@ -73,6 +73,14 @@ arm_cpu_builtins (struct cpp_reader* pfile)
 
   def_or_undef_macro (pfile, "__ARM_32BIT_STATE", TARGET_32BIT); 
 
+  if (arm_arch8 && !arm_arch_notm)
+{
+  if (arm_arch_cmse && use_cmse)
+   builtin_define_with_int_value ("__ARM_FEATURE_CMSE", 3);
+  else
+   builtin_define ("__ARM_FEATURE_CMSE");
+}
+
   if (TARGET_ARM_FEATURE_LDREX)
 builtin_define_with

[RFC][PATCH , ARM 2/8] Add RTL patterns for thumb1 push/pop

2015-12-25 Thread Thomas Preud'homme 
[Sending on behalf of Andre Vieira]

Hello,

This patch adds RTL patterns for the push and pop instructions for thumb1. 
These are needed by subsequent patches in the series.

*** gcc/ChangeLog ***
2015-10-27  Andre Vieira
Thomas Preud'homme  

* gcc/config/arm/arm-ldmstm.nl (constr thumb): Enabled
  stackpointer to be written/read.
* gcc/config/arm/ldmstm.md: Regenerated.
* gcc/config/arm/thumb1.md (*thumb1_pop_single): New.
  (*thumb1_load_multiple_operation): New.
* gcc/config/arm/arm.c (thumb_pop): Fix of comment.


diff --git a/gcc/config/arm/arm-ldmstm.ml b/gcc/config/arm/arm-ldmstm.ml
index 
62982df594d5d4a1407df359e927c66986a9788c..f3ee741e93927d8d44a9eccec8970b46a8984216
 100644
--- a/gcc/config/arm/arm-ldmstm.ml
+++ b/gcc/config/arm/arm-ldmstm.ml
@@ -63,7 +63,7 @@ let rec final_offset addrmode nregs =
   | DB -> -4 * nregs
 
 let constr thumb =
-  if thumb then "l" else "rk"
+  if thumb then "lk" else "rk"
 
 let inout_constr op_type =
   match op_type with
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 
06a6184ee0c4ed1a7cec1de4c1786e297cc57872..2223101fbf96bceb4beb3a7d6cb04162481dc3bf
 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -23773,8 +23773,8 @@ thumb1_emit_multi_reg_push (unsigned long mask, 
unsigned long real_regs)
   return insn;
 }
 
-/* Emit code to push or pop registers to or from the stack.  F is the
-   assembly file.  MASK is the registers to pop.  */
+/* Emit code to pop registers from the stack.  F is the assembly file.
+   MASK is the registers to pop.  */
 static void
 thumb_pop (FILE *f, unsigned long mask)
 {
diff --git a/gcc/config/arm/ldmstm.md b/gcc/config/arm/ldmstm.md
index 
ebb09ab86e799f3606e0988980edf3cd0189272b..8c0472e07799bd9d08759e35b6b98f3536d3d013
 100644
--- a/gcc/config/arm/ldmstm.md
+++ b/gcc/config/arm/ldmstm.md
@@ -43,7 +43,7 @@
 (define_insn "*thumb_ldm4_ia"
   [(match_parallel 0 "load_multiple_operation"
 [(set (match_operand:SI 1 "low_register_operand" "")
-  (mem:SI (match_operand:SI 5 "s_register_operand" "l")))
+  (mem:SI (match_operand:SI 5 "s_register_operand" "lk")))
  (set (match_operand:SI 2 "low_register_operand" "")
   (mem:SI (plus:SI (match_dup 5)
   (const_int 4
@@ -80,7 +80,7 @@
 
 (define_insn "*thumb_ldm4_ia_update"
   [(match_parallel 0 "load_multiple_operation"
-[(set (match_operand:SI 5 "s_register_operand" "+&l")
+[(set (match_operand:SI 5 "s_register_operand" "+&lk")
   (plus:SI (match_dup 5) (const_int 16)))
  (set (match_operand:SI 1 "low_register_operand" "")
   (mem:SI (match_dup 5)))
@@ -133,7 +133,7 @@
 
 (define_insn "*thumb_stm4_ia_update"
   [(match_parallel 0 "store_multiple_operation"
-[(set (match_operand:SI 5 "s_register_operand" "+&l")
+[(set (match_operand:SI 5 "s_register_operand" "+&lk")
   (plus:SI (match_dup 5) (const_int 16)))
  (set (mem:SI (match_dup 5))
   (match_operand:SI 1 "low_register_operand" ""))
@@ -491,7 +491,7 @@
 (define_insn "*thumb_ldm3_ia"
   [(match_parallel 0 "load_multiple_operation"
 [(set (match_operand:SI 1 "low_register_operand" "")
-  (mem:SI (match_operand:SI 4 "s_register_operand" "l")))
+  (mem:SI (match_operand:SI 4 "s_register_operand" "lk")))
  (set (match_operand:SI 2 "low_register_operand" "")
   (mem:SI (plus:SI (match_dup 4)
   (const_int 4
@@ -522,7 +522,7 @@
 
 (define_insn "*thumb_ldm3_ia_update"
   [(match_parallel 0 "load_multiple_operation"
-[(set (match_operand:SI 4 "s_register_operand" "+&l")
+[(set (match_operand:SI 4 "s_register_operand" "+&lk")
   (plus:SI (match_dup 4) (const_int 12)))
  (set (match_operand:SI 1 "low_register_operand" "")
   (mem:SI (match_dup 4)))
@@ -568,7 +568,7 @@
 
 (define_insn "*thumb_stm3_ia_update"
   [(match_parallel 0 "store_multiple_operation"
-[(set (match_operand:SI 4 "s_register_operand" "+&l")
+[(set (match_operand:SI 4 "s_register_operand" "+&lk")
   (plus:SI (match_dup 4) (const_int 12)))
  (set (mem:SI (match_dup 4))
   (match_operand:SI 1 "low_register_operand" ""))
@@ -877,7 +877,7 @@
 (define_insn "*thumb_ldm2_ia"
   [(match_parallel 0 "load_multiple_operation"
 [(set (match_operand:SI 1 "low_register_operand" "")
-  (mem:SI (match_operand:SI 3 "s_register_operand" "l")))
+  (mem:SI (match_operand:SI 3 "s_register_operand" "lk")))
  (set (match_operand:SI 2 "low_register_operand" "")
   (mem:SI (plus:SI (match_dup 3)
   (const_int 4])]
@@ -902,7 +902,7 @@
 
 (define_insn "*thumb_ldm2_ia_update"
   [(match_parallel 0 "load_multiple_operation"
-[(set (match_operand:SI 3 "s_register_operand" "+&l")
+[(set (match_operand:SI 3 "s_register_operand" "+&lk")
   (plus:SI (match_dup 3) (const_int 8)))
  (set (match_operand:SI 1 "low_register_operand" "")

[RFC][PATCH, ARM 3/8] Handling ARMv8-M Security Extension's cmse_nonsecure_entry attribute

2015-12-25 Thread Thomas Preud'homme 
[Sending on behalf of Andre Vieira]

Hello,

This patch adds support for the ARMv8-M Security Extensions 
'cmse_nonsecure_entry' attribute. In this patch we implement the attribute 
handling and diagnosis around the attribute. See Section 5.4 of ARM®v8-M 
Security Extensions 
(http://infocenter.arm.com/help/topic/com.arm.doc.ecm0359818/index.html).

*** gcc/ChangeLog ***
2015-10-27  Andre Vieira
Thomas Preud'homme  

* gcc/config/arm/arm.c (arm_handle_cmse_nonsecure_entry): New.
  (arm_attribute_table): Added cmse_nonsecure_entry
  (arm_compute_func_type): Handle cmse_nonsecure_entry.
  (cmse_func_args_or_return_in_stack): New.
  (arm_handle_cmse_nonsecure_entry): New.
* gcc/config/arm/arm.h (ARM_FT_CMSE_ENTRY): New macro define.
  (IS_CMSE_ENTRY): Likewise.

*** gcc/testsuite/ChangeLog ***
2015-10-27  Andre Vieira
Thomas Preud'homme  

* gcc.target/arm/cmse/cmse-3.c: New.


diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
index 
cf6d9466fb79e4f8a2dbfe725c52d5be8ea24fd2..f12e3c93bbe24b10ed8eee6687161826773ef649
 100644
--- a/gcc/config/arm/arm.h
+++ b/gcc/config/arm/arm.h
@@ -1375,6 +1375,7 @@ enum reg_class
 #define ARM_FT_VOLATILE(1 << 4) /* Does not return.  */
 #define ARM_FT_NESTED  (1 << 5) /* Embedded inside another func.  */
 #define ARM_FT_STACKALIGN  (1 << 6) /* Called with misaligned stack.  */
+#define ARM_FT_CMSE_ENTRY  (1 << 7) /* ARMv8-M non-secure entry function.  
*/
 
 /* Some macros to test these flags.  */
 #define ARM_FUNC_TYPE(t)   (t & ARM_FT_TYPE_MASK)
@@ -1383,6 +1384,7 @@ enum reg_class
 #define IS_NAKED(t)(t & ARM_FT_NAKED)
 #define IS_NESTED(t)   (t & ARM_FT_NESTED)
 #define IS_STACKALIGN(t)   (t & ARM_FT_STACKALIGN)
+#define IS_CMSE_ENTRY(t)   (t & ARM_FT_CMSE_ENTRY)
 
 
 /* Structure used to hold the function stack frame layout.  Offsets are
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 
2223101fbf96bceb4beb3a7d6cb04162481dc3bf..5b9e51b10e91eee64e3383c1ed50269c3e6cf24c
 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -135,6 +135,7 @@ static tree arm_handle_isr_attribute (tree *, tree, tree, 
int, bool *);
 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
 static tree arm_handle_notshared_attribute (tree *, tree, tree, int, bool *);
 #endif
+static tree arm_handle_cmse_nonsecure_entry (tree *, tree, tree, int, bool *);
 static void arm_output_function_epilogue (FILE *, HOST_WIDE_INT);
 static void arm_output_function_prologue (FILE *, HOST_WIDE_INT);
 static int arm_comp_type_attributes (const_tree, const_tree);
@@ -343,6 +344,9 @@ static const struct attribute_spec arm_attribute_table[] =
   { "notshared",0, 0, false, true, false, arm_handle_notshared_attribute,
 false },
 #endif
+  /* ARMv8-M Security Extensions support.  */
+  { "cmse_nonsecure_entry", 0, 0, true, false, false,
+arm_handle_cmse_nonsecure_entry, false },
   { NULL,   0, 0, false, false, false, NULL, false }
 };
 

@@ -3562,6 +3566,9 @@ arm_compute_func_type (void)
   else
 type |= arm_isr_value (TREE_VALUE (a));
 
+  if (lookup_attribute ("cmse_nonsecure_entry", attr))
+type |= ARM_FT_CMSE_ENTRY;
+
   return type;
 }
 
@@ -6552,6 +6559,109 @@ arm_handle_notshared_attribute (tree *node,
 }
 #endif
 
+/* This function is used to check whether functions with attributes
+   cmse_nonsecure_call or cmse_nonsecure_entry use the stack to pass arguments
+   or return variables.  If the function does indeed use the stack this
+   function returns true and diagnoses this, otherwise it returns false.  */
+
+static bool
+cmse_func_args_or_return_in_stack (tree fndecl, tree name, tree fntype)
+{
+  function_args_iterator args_iter;
+  CUMULATIVE_ARGS args_so_far_v;
+  cumulative_args_t args_so_far;
+  bool first_param = true;
+  tree arg_type, prev_arg_type = NULL_TREE, ret_type;
+
+  /* Error out if any argument is passed on the stack.  */
+  arm_init_cumulative_args (&args_so_far_v, fntype, NULL_RTX, fndecl);
+  args_so_far = pack_cumulative_args (&args_so_far_v);
+  FOREACH_FUNCTION_ARGS (fntype, arg_type, args_iter)
+{
+  rtx arg_rtx;
+  machine_mode arg_mode = TYPE_MODE (arg_type);
+
+  prev_arg_type = arg_type;
+  if (VOID_TYPE_P (arg_type))
+   continue;
+
+  if (!first_param)
+   arm_function_arg_advance (args_so_far, arg_mode, arg_type, true);
+  arg_rtx = arm_function_arg (args_so_far, arg_mode, arg_type, true);
+  if (!arg_rtx
+ || arm_arg_partial_bytes (args_so_far, arg_mode, arg_type, true))
+   {
+ error ("%qE attribute not available to functions with arguments "
+"passed on the stack", name);
+ return true;
+   }
+  first_param = false;
+}
+
+  /* Error out for variadic functions since we cannot control how many
+ arguments will be passed and thus stack could be used.  stdarg_p ()

[RFC][PATCH, ARM 4/8] ARMv8-M Security Extension's cmse_nonsecure_entry: __acle_se label and bxns return

2015-12-25 Thread Thomas Preud'homme 
[Sending on behalf of Andre Vieira]

Hello,

This patch extends support for the ARMv8-M Security Extensions 
'cmse_nonsecure_entry' attribute in two ways:

1) Generate two labels for the function, the regular function name and one with 
the function's name appended to '__acle_se_', this will trigger the linker to 
create a secure gateway veneer for this entry function.
2) Return from cmse_nonsecure_entry marked functions using bxns.

See Section 5.4 of ARM®v8-M Security Extensions 
(http://infocenter.arm.com/help/topic/com.arm.doc.ecm0359818/index.html).


*** gcc/ChangeLog ***
2015-10-27  Andre Vieira
Thomas Preud'homme  

* gcc/config/arm/arm.c (use_return_insn): Change to return with  bxns
  when cmse_nonsecure_entry.
  (output_return_instruction): Likewise.
  (arm_output_function_prologue): Likewise.
  (thumb_pop): Likewise.
  (thumb_exit): Likewise.
  (arm_function_ok_for_sibcall): Disable sibcall for entry functions.
  (arm_asm_declare_function_name): New.
  (thumb1_cmse_nonsecure_entry_return): New.
* gcc/config/arm/arm-protos.h (arm_asm_declare_function_name): New.
* gcc/config/arm/elf.h (ASM_DECLARE_FUNCTION_NAME): Redefine to
  use arm_asm_declare_function_name.

*** gcc/testsuite/ChangeLog ***
2015-10-27  Andre Vieira
Thomas Preud'homme  

* gcc.target/arm/cmse/cmse-2.c: New.
* gcc.target/arm/cmse/cmse-4.c: New.


diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h
index 
85dca057d63544c672188db39b05a33b1be10915..9ee8c333046d9a5bb0487f7b710a5aff42d2
 100644
--- a/gcc/config/arm/arm-protos.h
+++ b/gcc/config/arm/arm-protos.h
@@ -31,6 +31,7 @@ extern int arm_volatile_func (void);
 extern void arm_expand_prologue (void);
 extern void arm_expand_epilogue (bool);
 extern void arm_declare_function_name (FILE *, const char *, tree);
+extern void arm_asm_declare_function_name (FILE *, const char *, tree);
 extern void thumb2_expand_return (bool);
 extern const char *arm_strip_name_encoding (const char *);
 extern void arm_asm_output_labelref (FILE *, const char *);
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 
5b9e51b10e91eee64e3383c1ed50269c3e6cf24c..e530b772e3cc053c16421a2a2861d815d53ebb01
 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -3795,6 +3795,11 @@ use_return_insn (int iscond, rtx sibling)
return 0;
 }
 
+  /* ARMv8-M nonsecure entry function need to use bxns to return and thus need
+ several instructions if anything needs to be popped.  */
+  if (saved_int_regs && IS_CMSE_ENTRY (func_type))
+return 0;
+
   /* If there are saved registers but the LR isn't saved, then we need
  two instructions for the return.  */
   if (saved_int_regs && !(saved_int_regs & (1 << LR_REGNUM)))
@@ -6820,6 +6825,11 @@ arm_function_ok_for_sibcall (tree decl, tree exp)
   if (IS_INTERRUPT (func_type))
 return false;
 
+  /* ARMv8-M non-secure entry functions need to return with bxns which is only
+ generated for entry functions themselves.  */
+  if (IS_CMSE_ENTRY (arm_current_func_type ()))
+return false;
+
   if (!VOID_TYPE_P (TREE_TYPE (DECL_RESULT (cfun->decl
 {
   /* Check that the return value locations are the same.  For
@@ -19607,6 +19617,7 @@ output_return_instruction (rtx operand, bool 
really_return, bool reverse,
 (e.g. interworking) then we can load the return address
 directly into the PC.  Otherwise we must load it into LR.  */
   if (really_return
+ && !IS_CMSE_ENTRY (func_type)
  && (IS_INTERRUPT (func_type) || !TARGET_INTERWORK))
return_reg = reg_names[PC_REGNUM];
   else
@@ -19742,8 +19753,12 @@ output_return_instruction (rtx operand, bool 
really_return, bool reverse,
  break;
 
default:
+ if (IS_CMSE_ENTRY (func_type))
+   {
+ snprintf (instr, sizeof (instr), "bxns%s\t%%|lr", conditional);
+   }
  /* Use bx if it's available.  */
- if (arm_arch5 || arm_arch4t)
+ else if (arm_arch5 || arm_arch4t)
sprintf (instr, "bx%s\t%%|lr", conditional);
  else
sprintf (instr, "mov%s\t%%|pc, %%|lr", conditional);
@@ -19756,6 +19771,42 @@ output_return_instruction (rtx operand, bool 
really_return, bool reverse,
   return "";
 }
 
+/* Output in FILE asm statements needed to declare the NAME of the function
+   defined by its DECL node.  */
+
+void
+arm_asm_declare_function_name (FILE *file, const char *name, tree decl)
+{
+  size_t cmse_name_len;
+  char *cmse_name = 0;
+  char cmse_prefix[] = "__acle_se_";
+
+  if (use_cmse && lookup_attribute ("cmse_nonsecure_entry",
+   DECL_ATTRIBUTES (decl)))
+{
+  cmse_name_len = sizeof (cmse_prefix) + strlen (name);
+  cmse_name = XALLOCAVEC (char, cmse_name_len);
+  snprintf (cmse_name, cmse_name_len, "%s%s", cmse_pr

[RFC][PATCH, ARM 5/8] ARMv8-M Security Extension's cmse_nonsecure_entry: clear registers

2015-12-25 Thread Thomas Preud'homme 
[Sending on behalf of Andre Vieira]

Hello,

This patch extends support for the ARMv8-M Security Extensions 
'cmse_nonsecure_entry' attribute to safeguard against leak of information 
through unbanked registers.

When returning from a nonsecure entry function we clear all caller-saved 
registers that are not used to pass return values, by writing either the LR, in 
case of general purpose registers, or the value 0, in case of FP registers. We 
use the LR to write to APSR and FPSCR too. We currently only support 32 FP 
registers as in we only clear D0-D7.
We currently do not support entry functions that pass arguments or return 
variables on the stack and we diagnose this. This patch relies on the existing 
code to make sure callee-saved registers used in cmse_nonsecure_entry functions 
are saved and restored thus retaining their nonsecure mode value, this should 
be happening already as it is required by AAPCS.


*** gcc/ChangeLog ***
2015-10-27  Andre Vieira
Thomas Preud'homme  

* gcc/config/arm/arm.c (output_return_instruction): Clear
  registers.
  (thumb2_expand_return): Likewise.
  (thumb1_expand_epilogue): Likewise.
  (arm_expand_epilogue): Likewise.
  (cmse_nonsecure_entry_clear_before_return): New.
* gcc/config/arm/arm.h (TARGET_DSP_ADD): New macro define.
* gcc/config/arm/thumb1.md (*epilogue_insns): Change length attribute.
* gcc/config/arm/thumb2.md (*thumb2_return): Likewise.

*** gcc/testsuite/ChangeLog ***
2015-10-27  Andre Vieira
Thomas Preud'homme  

* gcc.target/arm/cmse/cmse.exp: Test different multilibs separate.
* gcc.target/arm/cmse/baseline/cmse-2.c: Test that registers are 
cleared.
* gcc.target/arm/cmse/mainline/soft/cmse-5.c: New.
* gcc.target/arm/cmse/mainline/hard/cmse-5.c: New.
* gcc.target/arm/cmse/mainline/hard-sp/cmse-5.c: New.
* gcc.target/arm/cmse/mainline/softfp/cmse-5.c: New.
* gcc.target/arm/cmse/mainline/softfp-sp/cmse-5.c: New.


diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
index 
f12e3c93bbe24b10ed8eee6687161826773ef649..b06e0586a3da50f57645bda13629bc4dbd3d53b7
 100644
--- a/gcc/config/arm/arm.h
+++ b/gcc/config/arm/arm.h
@@ -230,6 +230,9 @@ extern void (*arm_lang_output_object_attributes_hook)(void);
 /* Integer SIMD instructions, and extend-accumulate instructions.  */
 #define TARGET_INT_SIMD \
   (TARGET_32BIT && arm_arch6 && (arm_arch_notm || arm_arch7em))
+/* Parallel addition and subtraction instructions.  */
+#define TARGET_DSP_ADD \
+  (TARGET_ARM_ARCH >= 6 && (arm_arch_notm || arm_arch7em))
 
 /* Should MOVW/MOVT be used in preference to a constant pool.  */
 #define TARGET_USE_MOVT \
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 
e530b772e3cc053c16421a2a2861d815d53ebb01..0700478ca38307f35d0cb01f83ea182802ba28fa
 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -19755,6 +19755,24 @@ output_return_instruction (rtx operand, bool 
really_return, bool reverse,
default:
  if (IS_CMSE_ENTRY (func_type))
{
+ char flags[12] = "APSR_nzcvq";
+ /* Check if we have to clear the 'GE bits' which is only used if
+parallel add and subtraction instructions are available.  */
+ if (TARGET_DSP_ADD)
+   {
+ /* If so also clear the ge flags.  */
+ flags[10] = 'g';
+ flags[11] = '\0';
+   }
+ snprintf (instr, sizeof (instr),  "msr%s\t%s, %%|lr", conditional,
+   flags);
+ output_asm_insn (instr, & operand);
+ if (TARGET_HARD_FLOAT && TARGET_VFP)
+   {
+ snprintf (instr, sizeof (instr), "vmsr%s\tfpscr, %%|lr",
+   conditional);
+ output_asm_insn (instr, & operand);
+   }
  snprintf (instr, sizeof (instr), "bxns%s\t%%|lr", conditional);
}
  /* Use bx if it's available.  */
@@ -23999,6 +24017,17 @@ thumb_pop (FILE *f, unsigned long mask)
 static void
 thumb1_cmse_nonsecure_entry_return (FILE *f, int reg_containing_return_addr)
 {
+  char flags[12] = "APSR_nzcvq";
+  /* Check if we have to clear the 'GE bits' which is only used if
+ parallel add and subtraction instructions are available.  */
+  if (TARGET_DSP_ADD)
+{
+  flags[10] = 'g';
+  flags[11] = '\0';
+}
+  asm_fprintf (f, "\tmsr\t%s, %r\n", flags, reg_containing_return_addr);
+  if (TARGET_HARD_FLOAT && TARGET_VFP)
+asm_fprintf (f, "\tvmsr\tfpscr, %r\n", reg_containing_return_addr);
   asm_fprintf (f, "\tbxns\t%r\n", reg_containing_return_addr);
 }
 
@@ -25140,6 +25169,139 @@ thumb1_expand_prologue (void)
 cfun->machine->lr_save_eliminated = 0;
 }
 
+/* Clear caller saved registers not used to pass return values and leaked
+   condition flags before exiting a cmse_nonsecure_e

[RFC][PATCH, ARM 6/8] Handling ARMv8-M Security Extension's cmse_nonsecure_call attribute

2015-12-25 Thread Thomas Preud'homme 
[Sending on behalf of Andre Vieira]

Hello,

This patch adds support for the ARMv8-M Security Extensions 
'cmse_nonsecure_call' attribute. This attribute may only be used for function 
types and when used in combination with the '-mcmse' compilation flag. See 
Section 5.5 of ARM®v8-M Security Extensions 
(http://infocenter.arm.com/help/topic/com.arm.doc.ecm0359818/index.html).

We currently do not support cmse_nonsecure_call functions that pass arguments 
or return variables on the stack and we diagnose this. 

*** gcc/ChangeLog ***
2015-10-27  Andre Vieira
Thomas Preud'homme  

* gcc/config/arm/arm.c (gimplify.h): New include.
  (arm_handle_cmse_nonsecure_call): New.
  (arm_attribute_table): Added cmse_nonsecure_call.

*** gcc/testsuite/ChangeLog ***
2015-10-27  Andre Vieira
Thomas Preud'homme  

* gcc.target/arm/cmse/cmse-3.c: Add tests.
* gcc.target/arm/cmse/cmse-4.c: Add tests.


diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 
0700478ca38307f35d0cb01f83ea182802ba28fa..4b4eea88cbec8e04d5b92210f0af2440ce6fb6e4
 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -61,6 +61,7 @@
 #include "builtins.h"
 #include "tm-constrs.h"
 #include "rtl-iter.h"
+#include "gimplify.h"
 
 /* This file should be included last.  */
 #include "target-def.h"
@@ -136,6 +137,7 @@ static tree arm_handle_isr_attribute (tree *, tree, tree, 
int, bool *);
 static tree arm_handle_notshared_attribute (tree *, tree, tree, int, bool *);
 #endif
 static tree arm_handle_cmse_nonsecure_entry (tree *, tree, tree, int, bool *);
+static tree arm_handle_cmse_nonsecure_call (tree *, tree, tree, int, bool *);
 static void arm_output_function_epilogue (FILE *, HOST_WIDE_INT);
 static void arm_output_function_prologue (FILE *, HOST_WIDE_INT);
 static int arm_comp_type_attributes (const_tree, const_tree);
@@ -347,6 +349,8 @@ static const struct attribute_spec arm_attribute_table[] =
   /* ARMv8-M Security Extensions support.  */
   { "cmse_nonsecure_entry", 0, 0, true, false, false,
 arm_handle_cmse_nonsecure_entry, false },
+  { "cmse_nonsecure_call", 0, 0, true, false, false,
+arm_handle_cmse_nonsecure_call, false },
   { NULL,   0, 0, false, false, false, NULL, false }
 };
 

@@ -6667,6 +6671,76 @@ arm_handle_cmse_nonsecure_entry (tree *node, tree name,
   return NULL_TREE;
 }
 
+
+/* Called upon detection of the use of the cmse_nonsecure_call attribute, this
+   function will check whether the attribute is allowed here and will add the
+   attribute to the function type tree or otherwise issue a diagnose.  The
+   reason we check this at declaration time is to only allow the use of the
+   attribute with declartions of function pointers and not function
+   declartions.  */
+
+static tree
+arm_handle_cmse_nonsecure_call (tree *node, tree name,
+tree /* args */,
+int /* flags */,
+bool *no_add_attrs)
+{
+  tree decl = NULL_TREE;
+  tree type, fntype, main_variant;
+
+  if (!use_cmse)
+{
+  *no_add_attrs = true;
+  return NULL_TREE;
+}
+
+  if (TREE_CODE (*node) == VAR_DECL || TREE_CODE (*node) == TYPE_DECL)
+{
+  decl = *node;
+  type = TREE_TYPE (decl);
+}
+
+  if (!decl
+  || (!(TREE_CODE (type) == POINTER_TYPE
+   && TREE_CODE (TREE_TYPE (type)) == FUNCTION_TYPE)
+ && TREE_CODE (type) != FUNCTION_TYPE))
+{
+   warning (OPT_Wattributes, "%qE attribute only applies to base type of a 
"
+"function pointer", name);
+   *no_add_attrs = true;
+   return NULL_TREE;
+}
+
+  /* type is either a function pointer, when the attribute is used on a 
function
+   * pointer, or a function type when used in a typedef.  */
+  if (TREE_CODE (type) == FUNCTION_TYPE)
+fntype = type;
+  else
+fntype = TREE_TYPE (type);
+
+  *no_add_attrs |= cmse_func_args_or_return_in_stack (NULL, name, fntype);
+
+  if (*no_add_attrs)
+return NULL_TREE;
+
+  /* Prevent tree's being shared among function types with and without
+ cmse_nonsecure_call attribute.  Do however make sure they keep the same
+ main_variant, this is required for correct DIE output.  */
+  main_variant = TYPE_MAIN_VARIANT (fntype);
+  fntype = build_distinct_type_copy (fntype);
+  TYPE_MAIN_VARIANT (fntype) = main_variant;
+  if (TREE_CODE (type) == FUNCTION_TYPE)
+TREE_TYPE (decl) = fntype;
+  else
+TREE_TYPE (type) = fntype;
+
+  /* Construct a type attribute and add it to the function type.  */
+  tree attrs = tree_cons (get_identifier ("cmse_nonsecure_call"), NULL_TREE,
+ TYPE_ATTRIBUTES (fntype));
+  TYPE_ATTRIBUTES (fntype) = attrs;
+  return NULL_TREE;
+}
+
 /* Return 0 if the attributes for two types are incompatible, 1 if they
are compatible, and 2 if they are nearly compatible (which causes a
warning to be generated).  */
diff --git a/

[RFC][PATCH, ARM 7/8] ARMv8-M Security Extension's cmse_nonsecure_call: use __gnu_cmse_nonsecure_call

2015-12-25 Thread Thomas Preud'homme 
[Sending on behalf of Andre Vieira]

Hello,

This patch extends support for the ARMv8-M Security Extensions 
'cmse_nonsecure_call' to use a new library function 
'__gnu_cmse_nonsecure_call'. This library function is responsible for (without 
using r0-r3 or d0-d7):
1) saving and clearing all callee-saved registers using the secure stack
2) clearing the LSB of the address passed in r4 and using blxns to 'jump' to it
3) clearing ASPR, including the 'ge bits' if DSP is enabled
4) clearing FPSCR if using non-soft float-abi
5) restoring callee-saved registers.

The decisions whether to include DSP 'ge bits' clearing and floating point 
registers (single/double precision) all depends on the multilib used.

See Section 5.5 of ARM®v8-M Security Extensions 
(http://infocenter.arm.com/help/topic/com.arm.doc.ecm0359818/index.html).

*** gcc/ChangeLog ***

*** gcc/ChangeLog ***
2015-10-27  Andre Vieira
Thomas Preud'homme  

* gcc/config/arm/arm.c (detect_cmse_nonsecure_call): New.
  (cmse_nonsecure_call_clear_caller_saved): New.
* gcc/config/arm/arm-protos.h (detect_cmse_nonsecure_call): New.
* gcc/config/arm/arm.md (call): Handle cmse_nonsecure_entry.
  (call_value): Likewise.
  (nonsecure_call_internal): New.
  (nonsecure_call_value_internal): New.
* gcc/config/arm/thumb1.md (*nonsecure_call_reg_thumb1_v5): New.
  (*nonsecure_call_value_reg_thumb1_v5): New.
* gcc/config/arm/thumb2.md (*nonsecure_call_reg_thumb2): New.
  (*nonsecure_call_value_reg_thumb2): New.
* gcc/config/arm/unspecs.md (UNSPEC_NONSECURE_MEM): New.
* libgcc/config/arm/cmse_nonsecure_call.S: New.
* libgcc/config/arm/t-arm: Compile cmse_nonsecure_call.S


*** gcc/testsuite/ChangeLog ***
2015-10-27  Andre Vieira
Thomas Preud'homme  

* gcc/testsuite/gcc.target/arm/cmse/baseline/cmse-11.c: New.
* gcc/testsuite/gcc.target/arm/cmse/baseline/cmse-13.c: New.
* gcc/testsuite/gcc.target/arm/cmse/baseline/cmse-6.c: New.
* gcc/testsuite/gcc.target/arm/cmse/mainline/hard-sp/cmse-13.c: New.
* gcc/testsuite/gcc.target/arm/cmse/mainline/hard-sp/cmse-7.c: New.
* gcc/testsuite/gcc.target/arm/cmse/mainline/hard-sp/cmse-8.c: New.
* gcc/testsuite/gcc.target/arm/cmse/mainline/hard/cmse-13.c: New.
* gcc/testsuite/gcc.target/arm/cmse/mainline/hard/cmse-7.c: New.
* gcc/testsuite/gcc.target/arm/cmse/mainline/hard/cmse-8.c: New.
* gcc/testsuite/gcc.target/arm/cmse/mainline/soft/cmse-13.c: New.
* gcc/testsuite/gcc.target/arm/cmse/mainline/soft/cmse-7.c: New.
* gcc/testsuite/gcc.target/arm/cmse/mainline/soft/cmse-8.c: New.
* gcc/testsuite/gcc.target/arm/cmse/mainline/softfp-sp/cmse-7.c: New.
* gcc/testsuite/gcc.target/arm/cmse/mainline/softfp-sp/cmse-8.c: New.
* gcc/testsuite/gcc.target/arm/cmse/mainline/softfp/cmse-13.c: New.
* gcc/testsuite/gcc.target/arm/cmse/mainline/softfp/cmse-7.c: New.
* gcc/testsuite/gcc.target/arm/cmse/mainline/softfp/cmse-8.c: New.


diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h
index 
9ee8c333046d9a5bb0487f7b710a5aff42d2..694ee02f534019a5fc9377757f3269dfe6ccfbc0
 100644
--- a/gcc/config/arm/arm-protos.h
+++ b/gcc/config/arm/arm-protos.h
@@ -132,6 +132,7 @@ extern int arm_const_double_inline_cost (rtx);
 extern bool arm_const_double_by_parts (rtx);
 extern bool arm_const_double_by_immediates (rtx);
 extern void arm_emit_call_insn (rtx, rtx, bool);
+bool detect_cmse_nonsecure_call (tree);
 extern const char *output_call (rtx *);
 void arm_emit_movpair (rtx, rtx);
 extern const char *output_mov_long_double_arm_from_arm (rtx *);
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 
4b4eea88cbec8e04d5b92210f0af2440ce6fb6e4..320f7b447501047a59ceef4f7ded2dadc2088664
 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -17403,6 +17403,129 @@ note_invalid_constants (rtx_insn *insn, HOST_WIDE_INT 
address, int do_pushes)
   return;
 }
 
+/* Saves callee saved registers, clears callee saved registers and caller saved
+   registers not used to pass arguments before a cmse_nonsecure_call.  And
+   restores the callee saved registers after.  */
+
+static void
+cmse_nonsecure_call_clear_caller_saved (void)
+{
+  basic_block bb;
+
+  FOR_EACH_BB_FN (bb, cfun)
+{
+  rtx_insn *insn;
+
+  FOR_BB_INSNS (bb, insn)
+   {
+ uint64_t to_clear_mask, float_mask;
+ rtx_insn *seq;
+ rtx pat, call, unspec, link, reg, cleared_reg, tmp;
+ unsigned int regno, maxregno;
+ rtx address;
+
+ if (!NONDEBUG_INSN_P (insn))
+   continue;
+
+ if (!CALL_P (insn))
+   continue;
+
+ pat = PATTERN (insn);
+ gcc_assert (GET_CODE (pat) == PARALLEL && XVECLEN (pat, 0) > 0);
+ call = XVECEXP (pat, 0, 0);
+
+ /* Get the real call RTX if the insn set

[RFC][PATCH, ARM 8/8] Added support for ARMV8-M Security Extension cmse_nonsecure_caller intrinsic

2015-12-25 Thread Thomas Preud'homme 
[Sending on behalf of Andre Vieira]

Hello,

This patch adds support ARMv8-M's Security Extension's cmse_nonsecure_caller 
intrinsic. This intrinsic is used to check whether an entry function was called 
from a non-secure state. 
See Section 5.4.3 of ARM®v8-M Security Extensions: Requirements on Development 
Tools (http://infocenter.arm.com/help/topic/com.arm.doc.ecm0359818/index.html) 
for further details.

*** gcc/ChangeLog ***
2015-10-27  Andre Vieira
Thomas Preud'homme  

* gcc/config/arm/arm-builtins.c (arm_builtins): Define
  ARM_BUILTIN_CMSE_NONSECURE_CALLER.
  (bdesc_2arg): Add line for cmse_nonsecure_caller.
  (arm_init_builtins): Init for cmse_nonsecure_caller.
  (arm_expand_builtin): Handle cmse_nonsecure_caller.
* gcc/config/arm/arm_cmse.h (cmse_nonsecure_caller): New.

*** gcc/testsuite/ChangeLog ***
2015-10-27  Andre Vieira
Thomas Preud'homme  

* gcc.target/arm/cmse/cmse-1.c: Added test for 
  cmse_nonsecure_caller.


diff --git a/gcc/config/arm/arm-builtins.c b/gcc/config/arm/arm-builtins.c
index 
11cd17d0b8f3c29ccbe16cb463a17d55ba0fa1e3..7934cf1d4d96c40255d3e93dc9902b4568014984
 100644
--- a/gcc/config/arm/arm-builtins.c
+++ b/gcc/config/arm/arm-builtins.c
@@ -515,6 +515,8 @@ enum arm_builtins
   ARM_BUILTIN_GET_FPSCR,
   ARM_BUILTIN_SET_FPSCR,
 
+  ARM_BUILTIN_CMSE_NONSECURE_CALLER,
+
 #undef CRYPTO1
 #undef CRYPTO2
 #undef CRYPTO3
@@ -1263,6 +1265,10 @@ static const struct builtin_description bdesc_2arg[] =
   FP_BUILTIN (set_fpscr, SET_FPSCR)
 #undef FP_BUILTIN
 
+  {ARM_FSET_MAKE_CPU2 (FL2_CMSE), CODE_FOR_andsi3,
+   "__builtin_arm_cmse_nonsecure_caller", ARM_BUILTIN_CMSE_NONSECURE_CALLER,
+   UNKNOWN, 0},
+
 #define CRC32_BUILTIN(L, U) \
   {ARM_FSET_EMPTY, CODE_FOR_##L, "__builtin_arm_"#L, \
ARM_BUILTIN_##U, UNKNOWN, 0},
@@ -1797,6 +1803,17 @@ arm_init_builtins (void)
= add_builtin_function ("__builtin_arm_stfscr", ftype_set_fpscr,
ARM_BUILTIN_SET_FPSCR, BUILT_IN_MD, NULL, 
NULL_TREE);
 }
+
+  if (arm_arch_cmse)
+{
+  tree ftype_cmse_nonsecure_caller
+   = build_function_type_list (unsigned_type_node, NULL);
+  arm_builtin_decls[ARM_BUILTIN_CMSE_NONSECURE_CALLER]
+   = add_builtin_function ("__builtin_arm_cmse_nonsecure_caller",
+   ftype_cmse_nonsecure_caller,
+   ARM_BUILTIN_CMSE_NONSECURE_CALLER, BUILT_IN_MD,
+   NULL, NULL_TREE);
+}
 }
 
 /* Return the ARM builtin for CODE.  */
@@ -2356,6 +2373,14 @@ arm_expand_builtin (tree exp,
   emit_insn (pat);
   return target;
 
+case ARM_BUILTIN_CMSE_NONSECURE_CALLER:
+  icode = CODE_FOR_andsi3;
+  target = gen_reg_rtx (SImode);
+  op0 = arm_return_addr (0, NULL_RTX);
+  pat = GEN_FCN (icode) (target, op0, const1_rtx);
+  emit_insn (pat);
+  return target;
+
 case ARM_BUILTIN_TEXTRMSB:
 case ARM_BUILTIN_TEXTRMUB:
 case ARM_BUILTIN_TEXTRMSH:
diff --git a/gcc/config/arm/arm_cmse.h b/gcc/config/arm/arm_cmse.h
index 
ab20a3ec46025f268a1e9bed895d27da9af7aab6..0bdff668d03d54e1acf2bdd3b5ff1bfb2b463bd8
 100644
--- a/gcc/config/arm/arm_cmse.h
+++ b/gcc/config/arm/arm_cmse.h
@@ -163,6 +163,13 @@ __attribute__ ((__always_inline__))
 cmse_TTAT (void *p)
 CMSE_TT_ASM (at)
 
+//TODO: diagnose use outside cmse_nonsecure_entry functions
+__extension__ static __inline int __attribute__ ((__always_inline__))
+cmse_nonsecure_caller (void)
+{
+  return __builtin_arm_cmse_nonsecure_caller ();
+}
+
 #define CMSE_AU_NONSECURE  2
 #define CMSE_MPU_NONSECURE 16
 #define CMSE_NONSECURE 18
diff --git a/gcc/testsuite/gcc.target/arm/cmse/cmse-1.c 
b/gcc/testsuite/gcc.target/arm/cmse/cmse-1.c
index 
1c3d4e9e934f4b1166d4d98383cf4ae8c3515117..ccecf396d3cda76536537b4d146bbb5f70589fd5
 100644
--- a/gcc/testsuite/gcc.target/arm/cmse/cmse-1.c
+++ b/gcc/testsuite/gcc.target/arm/cmse/cmse-1.c
@@ -66,3 +66,32 @@ int foo (char * p)
 /* { dg-final { scan-assembler-times "ttat " 2 } } */
 /* { dg-final { scan-assembler-times "bl.cmse_check_address_range" 7 } } */
 /* { dg-final { scan-assembler-not "cmse_check_pointed_object" } } */
+
+typedef int (*int_ret_funcptr_t) (void);
+typedef int __attribute__ ((cmse_nonsecure_call)) (*int_ret_nsfuncptr_t) 
(void);
+
+int __attribute__ ((cmse_nonsecure_entry))
+baz (void)
+{
+  return cmse_nonsecure_caller ();
+}
+
+int __attribute__ ((cmse_nonsecure_entry))
+qux (int_ret_funcptr_t int_ret_funcptr)
+{
+  int_ret_nsfuncptr_t int_ret_nsfunc_ptr;
+
+  if (cmse_is_nsfptr (int_ret_funcptr))
+{
+  int_ret_nsfunc_ptr = cmse_nsfptr_create (int_ret_funcptr);
+  return int_ret_nsfunc_ptr ();
+}
+  return 0;
+}
+/* { dg-final { scan-assembler "baz:" } } */
+/* { dg-final { scan-assembler "__acle_se_baz:" } } */
+/* { dg-final { scan-assembler-not "\tcmse_nonsecure_caller" } } */
+/* { dg-final { scan-rtl-dump "and.

Another C++11 experimental thing...

2015-12-25 Thread Ed Smith-Rowland 

I think we should change the language in the c++0x_warning.h:

Index: include/bits/c++0x_warning.h
===
--- include/bits/c++0x_warning.h(revision 231922)
+++ include/bits/c++0x_warning.h(working copy)
@@ -29,9 +29,9 @@
 #define _CXX0X_WARNING_H 1
 
 #if __cplusplus < 201103L
-#error This file requires compiler and library support for the \
-ISO C++ 2011 standard. This support is currently experimental, and must be \
-enabled with the -std=c++11 or -std=gnu++11 compiler options.
+#error This file requires compiler and library support \
+for the ISO C++ 2011 standard. This support must be enabled \
+with the -std=c++11 or -std=gnu++11 compiler options.
 #endif
 
 #endif

2015-12-26  Edward Smith-Rowland  <3dw...@verizon.net>
* include/bits/c++0x_warning.h Ramove experimental language.

Note new TR29124 Special math functions on the web pages.

2015-12-25 Thread Ed Smith-Rowland 

I can't get CVS to commit.

Could someone do this for me?

Index: ./htdocs/svn.html
===
RCS file: /cvs/gcc/wwwdocs/htdocs/svn.html,v
retrieving revision 1.206
diff -r1.206 svn.html
565a566,572
>   tr29124
>   This branch is for development of TR29124 Special math Functions,
> for the C++ runtime library
> See  href="http://www.open-std.org/jtc1/sc22/wg21/docs/papers/2010/n3060.pdf";>
> .  It is maintained by Ed Smith-Rowland
> 3dw...@verizon.net>.
>