[PATCH] Keep patch file permissions in mklog

[Tom de Vries]

Geoff,

Currently, mklog resets the permissions on a patch file:
...
$ touch tmp.patch
$ ls -la tmp.patch
-rw-rw-r-- 1 vries vries 0 mei 31 09:17 tmp.patch
$ ./contrib/mklog tmp.patch
$ ls -la tmp.patch
-rw--- 1 vries vries 59 mei 31 09:17 tmp.patch
$
...

This patch fixes that:
...
$ rm tmp.patch
$ touch tmp.patch
$ ls -la tmp.patch
-rw-rw-r-- 1 vries vries 0 mei 31 09:41 tmp.patch
$ ./contrib/mklog tmp.patch
$ ls -la tmp.patch
-rw-rw-r-- 1 vries vries 59 mei 31 09:41 tmp.patch
...

OK for trunk?

Thanks,
- Tom
2014-05-31  Tom de Vries  

	* mklog: Keep permissions on patch file.

diff --git a/contrib/mklog b/contrib/mklog
index fb489b0..d6f3556 100755
--- a/contrib/mklog
+++ b/contrib/mklog
@@ -264,7 +264,7 @@ foreach my $clname (keys %cl_entries) {
 }
 
 # Concatenate the ChangeLog template and the original .diff file.
-system ("cat $diff >>$temp && mv $temp $diff") == 0
+system ("cat $diff >>$temp && cat $temp >$diff && rm $temp") == 0
 or die "Could not add the ChangeLog entry to $diff";
 
 exit 0;
-- 
1.9.1

[PATCH 0/5] Cache recog_op_alt by insn code, take 2

[Richard Sandiford]

Sorry Jeff, while working on the follow-on LRA patch I came across
a couple of problems, so I need another round on this.

First of all, I mentioned doing a follow-on patch to make LRA and
recog use the same cache for operand_alternatives.  I hadn't realised
until I wrote that patch that there's a significant difference between
the LRA and recog_op_alt versions of the information: recog_op_alt
groups alternatives together by operand whereas LRA groups operands
together by alternative.  So in the cached flat array, recog_op_alt
uses [op * n_alternatives + alt] whereas LRA uses [alt * n_operands + nop].
The two could only share a cache if they used the same order.

I think the LRA ordering makes more sense.  Quite a few places are
only interested in alternative which_alternative, so grouping operands
together by alternative gives a natural subarray.  And there are places
in IRA (which uses recog_op_alt rather than the LRA information) where
the "for each alternative" loop is the outer one.

A second difference was that preprocess_constraints skips disabled
alternatives while LRA's setup_operand_alternative doesn't; LRA just
checks for disabled alternatives when walking the array instead.
That should make no difference in practice, but since the LRA approach
would also make it easier to precompute the array at build time,
I thought it would be a better way to go.  It also gives a cleaner
interface: we can have a preprocess_insn_constraints function that
takes a (define_insn-based) insn and returns the operand_alternative
information without any global state.

Also, it turns out that sel-sched.c, regcprop.c and regrename.c
modify the recog_op_alt structure as a convenient way of handling
matching constraints.  That obviously isn't a good idea if we want
other passes to reuse the data later.  I've fixed that and made the
types "const" so that new instances shouldn't creep in.

Also, I hadn't realised that a define_insn with no constraints
at all has 0 alternatives rather than 1.  Some passes nevertheless
unconditionally access the recog_op_alt information for alternative
which_alternative.

I could have fixed that by making n_alternatives always be >= 1
in the static insn table.  Several places do have fast paths for
n_alternatives == 0 though, so I thought it would be better to
handle the 0 alternative case in preprocess_constraints as well.
All it needs is a MIN (..., 1).

So the patch has now grown to 5 subpatches:

1. make recog_op_alt a flat array and order it in the same way as LRA
2. fix the places that modified recog_op_alt locally
3. don't handle the enabled attribute in preprocess_constraints and make
   sure all consumers check for disabled alternatives explicitly
4. the updated version of the original patch
5. get LRA to use the new cache too (the original follow-on patch)

Jeff Law  writes:
> On 05/20/14 02:19, Richard Sandiford wrote:
>> Following on from (and depending on) the last patch, process_constraints
>> also shows up high in the profile.  This patch caches the recog_op_alt
>> information by insn code too.  It also shrinks the size of the structure
>> from 1 pointer + 5 ints to 1 pointer + 2 ints:
>>
>> - no target should have more than 65536 register classes :-)
> That could probably be much lower if we needed more bits for other things.
>
>> - "reject" is based on a cost of 600 for '!', so 16 bits should be plenty
> OK.  Makes sense.
>
>
>> - "matched" and "matches" are operand numbers and so fit in 8 bits
> OK.  This could also be smaller, don't we have an upper limit of 32 (or 
> 30?) on the number of operands appearing in an insn.  It'd be a way to 
> get a few more bits if we need them someday.

Yeah, we could probably squeeze everything into a single int if we needed
to and if we were prepared to have non-byte-sized integer fields.
Going from 2 ints to 1 int wouldn't help LP64 hosts as things stand
though, since we have a pointer at the beginning of the struct.

Boostrapped & regression-tested on x86_64-linux-gnu.  Also tested by
building gcc.dg, g++.dg and gcc.c-torture for one target per config/
directory and making sure that there were no asm differences.

Thanks,
Richard

[PATCH 1/5] Flatten recog_op_alt and reorder entries

[Richard Sandiford]

As described in the covering note, this patch converts recog_op_alt
into a flat array and orders the entries in the same way as the
LRA cache.  Several places just want the information for alternative
which_alternative, so I added a convenience function for that.

Thanks,
Richard


gcc/
* recog.h (recog_op_alt): Convert to a flat array.
(which_op_alt): New function.
* recog.c (recog_op_alt): Convert to a flat array.
(preprocess_constraints): Update accordingly, grouping all
operands of the same alternative together, rather than the
other way around.
* ira-lives.c (check_and_make_def_conflict): Likewise.
(make_early_clobber_and_input_conflicts): Likewise.
* config/i386/i386.c (ix86_legitimate_combined_insn): Likewise.
* reg-stack.c (check_asm_stack_operands): Use which_op_alt.
(subst_asm_stack_regs): Likewise.
* regcprop.c (copyprop_hardreg_forward_1): Likewise.
* regrename.c (hide_operands, record_out_operands): Likewise.
(build_def_use): Likewise.
* sel-sched.c (get_reg_class): Likewise.
* config/arm/arm.c (note_invalid_constants): Likewise.

Index: gcc/recog.h
===
--- gcc/recog.h 2014-05-31 08:54:10.351219264 +0100
+++ gcc/recog.h 2014-05-31 08:57:21.608789337 +0100
@@ -256,9 +256,20 @@ struct recog_data_d
 
 extern struct recog_data_d recog_data;
 
-/* Contains a vector of operand_alternative structures for every operand.
-   Set up by preprocess_constraints.  */
-extern struct operand_alternative 
recog_op_alt[MAX_RECOG_OPERANDS][MAX_RECOG_ALTERNATIVES];
+extern struct operand_alternative recog_op_alt[MAX_RECOG_OPERANDS
+  * MAX_RECOG_ALTERNATIVES];
+
+/* Return a pointer to an array in which index OP describes the constraints
+   on operand OP of the current instruction alternative (which_alternative).
+   Only valid after calling preprocess_constraints and constrain_operands.  */
+
+inline static operand_alternative *
+which_op_alt ()
+{
+  gcc_checking_assert (IN_RANGE (which_alternative, 0,
+recog_data.n_alternatives - 1));
+  return &recog_op_alt[which_alternative * recog_data.n_operands];
+}
 
 /* A table defined in insn-output.c that give information about
each insn-code value.  */
Index: gcc/recog.c
===
--- gcc/recog.c 2014-05-31 08:54:10.351219264 +0100
+++ gcc/recog.c 2014-05-31 08:57:57.642085058 +0100
@@ -78,9 +78,11 @@ struct target_recog *this_target_recog =
 
 struct recog_data_d recog_data;
 
-/* Contains a vector of operand_alternative structures for every operand.
+/* Contains a vector of operand_alternative structures, such that
+   operand OP of alternative A is at index A * n_operands + OP.
Set up by preprocess_constraints.  */
-struct operand_alternative 
recog_op_alt[MAX_RECOG_OPERANDS][MAX_RECOG_ALTERNATIVES];
+struct operand_alternative recog_op_alt[MAX_RECOG_OPERANDS
+   * MAX_RECOG_ALTERNATIVES];
 
 /* On return from `constrain_operands', indicate which alternative
was satisfied.  */
@@ -2330,24 +2332,25 @@ preprocess_constraints (void)
 {
   int i;
 
-  for (i = 0; i < recog_data.n_operands; i++)
-memset (recog_op_alt[i], 0, (recog_data.n_alternatives
-* sizeof (struct operand_alternative)));
+  int n_operands = recog_data.n_operands;
+  int n_alternatives = recog_data.n_alternatives;
+  int n_entries = n_operands * n_alternatives;
+  memset (recog_op_alt, 0, n_entries * sizeof (struct operand_alternative));
 
-  for (i = 0; i < recog_data.n_operands; i++)
+  for (i = 0; i < n_operands; i++)
 {
   int j;
   struct operand_alternative *op_alt;
   const char *p = recog_data.constraints[i];
 
-  op_alt = recog_op_alt[i];
+  op_alt = recog_op_alt;
 
-  for (j = 0; j < recog_data.n_alternatives; j++)
+  for (j = 0; j < n_alternatives; j++, op_alt += n_operands)
{
- op_alt[j].cl = NO_REGS;
- op_alt[j].constraint = p;
- op_alt[j].matches = -1;
- op_alt[j].matched = -1;
+ op_alt[i].cl = NO_REGS;
+ op_alt[i].constraint = p;
+ op_alt[i].matches = -1;
+ op_alt[i].matched = -1;
 
  if (!TEST_BIT (recog_data.enabled_alternatives, j))
{
@@ -2357,7 +2360,7 @@ preprocess_constraints (void)
 
  if (*p == '\0' || *p == ',')
{
- op_alt[j].anything_ok = 1;
+ op_alt[i].anything_ok = 1;
  continue;
}
 
@@ -2385,77 +2388,77 @@ preprocess_constraints (void)
  break;
 
case '?':
- op_alt[j].reject += 6;
+ op_alt[i].reject += 6;
  break;
case '!':
- op_alt[j].reject += 600;
+ op

Re: [patch i386]: Expand sibling-tail-calls via accumulator register

[Kai Tietz]

Hmm,  this might cause by allowing CONST-memory-addresses.  This was
doubtful from the beginning.
It would be helpful to see here for the case a final rtl-dump.

Could you try if following patch (it is incomplete as it disregards
plus-expression) solves your bootstrap issue?

Regards,
Kai

Index: predicates.md
===
--- predicates.md   (Revision 211102)
+++ predicates.md   (Arbeitskopie)
@@ -74,6 +74,9 @@
 (define_predicate "sibcall_memory_operand"
   (match_operand 0 "memory_operand")
 {
+  op = XEXP (op, 0);
+  if (GET_CODE (op) == CONST)
+op = XEXP (op, 0);
   return CONSTANT_P (XEXP (op, 0));
 })

[PATCH 2/5] Don't modify recog_op_alt after preprocess_constraints

[Richard Sandiford]

Since the aim of this series is to cache the result of preprocess_constraints,
we need to make sure that passes don't modify the information afterwards.
This patch deals with the places that did.  Patch 4 will make the information
properly const.

Thanks,
Richard


gcc/
* recog.h (alternative_class): New function.
(which_op_alt): Return a const recog_op_alt.
* reg-stack.c (check_asm_stack_operands): Update type accordingly.
(subst_asm_stack_regs): Likewise.
* config/arm/arm.c (note_invalid_constants): Likewise.
* regcprop.c (copyprop_hardreg_forward_1): Likewise.  Don't modify
the operand_alternative; use alternative class instead.
* sel-sched.c (get_reg_class): Likewise.
* regrename.c (build_def_use): Likewise.
(hide_operands, restore_operands, record_out_operands): Update type
accordingly.

Index: gcc/recog.h
===
--- gcc/recog.h 2014-05-31 08:57:21.608789337 +0100
+++ gcc/recog.h 2014-05-31 09:02:35.956369716 +0100
@@ -79,6 +79,14 @@ struct operand_alternative
   unsigned int anything_ok:1;
 };
 
+/* Return the class for operand I of alternative ALT, taking matching
+   constraints into account.  */
+
+static inline enum reg_class
+alternative_class (const operand_alternative *alt, int i)
+{
+  return alt[i].matches >= 0 ? alt[alt[i].matches].cl : alt[i].cl;
+}
 
 extern void init_recog (void);
 extern void init_recog_no_volatile (void);
@@ -263,7 +271,7 @@ struct recog_data_d
on operand OP of the current instruction alternative (which_alternative).
Only valid after calling preprocess_constraints and constrain_operands.  */
 
-inline static operand_alternative *
+inline static const operand_alternative *
 which_op_alt ()
 {
   gcc_checking_assert (IN_RANGE (which_alternative, 0,
Index: gcc/reg-stack.c
===
--- gcc/reg-stack.c 2014-05-31 08:57:21.608789337 +0100
+++ gcc/reg-stack.c 2014-05-31 09:02:35.968369814 +0100
@@ -482,7 +482,7 @@ check_asm_stack_operands (rtx insn)
   PATTERN (insn) = gen_rtx_USE (VOIDmode, const0_rtx);
   return 0;
 }
-  operand_alternative *op_alt = which_op_alt ();
+  const operand_alternative *op_alt = which_op_alt ();
 
   /* Strip SUBREGs here to make the following code simpler.  */
   for (i = 0; i < recog_data.n_operands; i++)
@@ -2030,7 +2030,7 @@ subst_asm_stack_regs (rtx insn, stack_pt
   constrain_operands (1);
 
   preprocess_constraints ();
-  operand_alternative *op_alt = which_op_alt ();
+  const operand_alternative *op_alt = which_op_alt ();
 
   get_asm_operands_in_out (body, &n_outputs, &n_inputs);
 
Index: gcc/config/arm/arm.c
===
--- gcc/config/arm/arm.c2014-05-31 08:57:21.608789337 +0100
+++ gcc/config/arm/arm.c2014-05-31 09:02:35.966369798 +0100
@@ -16872,7 +16872,7 @@ note_invalid_constants (rtx insn, HOST_W
  this insn.  */
   preprocess_constraints ();
 
-  operand_alternative *op_alt = which_op_alt ();
+  const operand_alternative *op_alt = which_op_alt ();
   for (opno = 0; opno < recog_data.n_operands; opno++)
 {
   /* Things we need to fix can only occur in inputs.  */
Index: gcc/regcprop.c
===
--- gcc/regcprop.c  2014-05-31 08:57:21.608789337 +0100
+++ gcc/regcprop.c  2014-05-31 09:02:35.957369724 +0100
@@ -775,20 +775,17 @@ copyprop_hardreg_forward_1 (basic_block
   if (! constrain_operands (1))
fatal_insn_not_found (insn);
   preprocess_constraints ();
-  operand_alternative *op_alt = which_op_alt ();
+  const operand_alternative *op_alt = which_op_alt ();
   n_ops = recog_data.n_operands;
   is_asm = asm_noperands (PATTERN (insn)) >= 0;
 
-  /* Simplify the code below by rewriting things to reflect
-matching constraints.  Also promote OP_OUT to OP_INOUT
+  /* Simplify the code below by promoting OP_OUT to OP_INOUT
 in predicated instructions.  */
 
   predicated = GET_CODE (PATTERN (insn)) == COND_EXEC;
   for (i = 0; i < n_ops; ++i)
{
  int matches = op_alt[i].matches;
- if (matches >= 0)
-   op_alt[i].cl = op_alt[matches].cl;
  if (matches >= 0 || op_alt[i].matched >= 0
  || (predicated && recog_data.operand_type[i] == OP_OUT))
recog_data.operand_type[i] = OP_INOUT;
@@ -939,12 +936,14 @@ copyprop_hardreg_forward_1 (basic_block
  if (op_alt[i].is_address)
replaced[i]
  = replace_oldest_value_addr (recog_data.operand_loc[i],
-  op_alt[i].cl, VOIDmode,
-  ADDR_SPACE_GENERIC, insn, vd);
+  alternative_class (op_alt, i),
+

[PATCH 3/5] Make recog_op_alt consumers check the enabled attribute

[Richard Sandiford]

As described in the covering note, it seems better to put the onus of
checking the enabled attribute on the passes that are walking each
alternative, like LRA does for its internal subpasses.  That leads
to a nicer interface in patch 4 and would make it easier to precompute
the information at build time.  (The only thing preventing that now is
the subunion class.)

Thanks,
Richard


gcc/
* recog.c (preprocess_constraints): Don't skip disabled alternatives.
* ira-lives.c (check_and_make_def_conflict): Check for disabled
alternatives.
(make_early_clobber_and_input_conflicts): Likewise.
* config/i386/i386.c (ix86_legitimate_combined_insn): Likewise.

Index: gcc/recog.c
===
--- gcc/recog.c 2014-05-31 08:57:57.642085058 +0100
+++ gcc/recog.c 2014-05-31 09:07:21.669714878 +0100
@@ -2352,12 +2352,6 @@ preprocess_constraints (void)
  op_alt[i].matches = -1;
  op_alt[i].matched = -1;
 
- if (!TEST_BIT (recog_data.enabled_alternatives, j))
-   {
- p = skip_alternative (p);
- continue;
-   }
-
  if (*p == '\0' || *p == ',')
{
  op_alt[i].anything_ok = 1;
Index: gcc/ira-lives.c
===
--- gcc/ira-lives.c 2014-05-31 08:54:12.238234755 +0100
+++ gcc/ira-lives.c 2014-05-31 09:07:21.670714886 +0100
@@ -641,8 +641,11 @@ check_and_make_def_conflict (int alt, in
   /* If there's any alternative that allows USE to match DEF, do not
 record a conflict.  If that causes us to create an invalid
 instruction due to the earlyclobber, reload must fix it up.  */
+  alternative_mask enabled = recog_data.enabled_alternatives;
   for (alt1 = 0; alt1 < recog_data.n_alternatives; alt1++)
{
+ if (!TEST_BIT (enabled, alt1))
+   continue;
  operand_alternative *op_alt1 = &recog_op_alt[alt1 * n_operands];
  if (op_alt1[use].matches == def
  || (use < n_operands - 1
@@ -688,30 +691,32 @@ make_early_clobber_and_input_conflicts (
 
   int n_alternatives = recog_data.n_alternatives;
   int n_operands = recog_data.n_operands;
+  alternative_mask enabled = recog_data.enabled_alternatives;
   operand_alternative *op_alt = recog_op_alt;
   for (alt = 0; alt < n_alternatives; alt++, op_alt += n_operands)
-for (def = 0; def < n_operands; def++)
-  {
-   def_cl = NO_REGS;
-   if (op_alt[def].earlyclobber)
- {
-   if (op_alt[def].anything_ok)
- def_cl = ALL_REGS;
-   else
- def_cl = op_alt[def].cl;
-   check_and_make_def_conflict (alt, def, def_cl);
- }
-   if ((def_match = op_alt[def].matches) >= 0
-   && (op_alt[def_match].earlyclobber
-   || op_alt[def].earlyclobber))
- {
-   if (op_alt[def_match].anything_ok)
- def_cl = ALL_REGS;
-   else
- def_cl = op_alt[def_match].cl;
-   check_and_make_def_conflict (alt, def, def_cl);
- }
-  }
+if (TEST_BIT (enabled, alt))
+  for (def = 0; def < n_operands; def++)
+   {
+ def_cl = NO_REGS;
+ if (op_alt[def].earlyclobber)
+   {
+ if (op_alt[def].anything_ok)
+   def_cl = ALL_REGS;
+ else
+   def_cl = op_alt[def].cl;
+ check_and_make_def_conflict (alt, def, def_cl);
+   }
+ if ((def_match = op_alt[def].matches) >= 0
+ && (op_alt[def_match].earlyclobber
+ || op_alt[def].earlyclobber))
+   {
+ if (op_alt[def_match].anything_ok)
+   def_cl = ALL_REGS;
+ else
+   def_cl = op_alt[def_match].cl;
+ check_and_make_def_conflict (alt, def, def_cl);
+   }
+   }
 }
 
 /* Mark early clobber hard registers of the current INSN as live (if
Index: gcc/config/i386/i386.c
===
--- gcc/config/i386/i386.c  2014-05-31 08:54:12.236234739 +0100
+++ gcc/config/i386/i386.c  2014-05-31 09:07:21.682714985 +0100
@@ -5874,8 +5874,11 @@ ix86_legitimate_combined_insn (rtx insn)
  /* Operand has no constraints, anything is OK.  */
  win = !n_alternatives;
 
+ alternative_mask enabled = recog_data.enabled_alternatives;
  for (j = 0; j < n_alternatives; j++, op_alt += n_operands)
{
+ if (!TEST_BIT (enabled, j))
+   continue;
  if (op_alt[i].anything_ok
  || (op_alt[i].matches != -1
  && operands_match_p

[PATCH 4/5] Cache recog_op_alt by insn code: main patch

[Richard Sandiford]

This is the refreshed main patch.  I've rearranged the preprocess_constraints
code into three functions so that LRA can use it in patch 5.

Thanks,
Richard


gcc/
* recog.h (operand_alternative): Convert reg_class, reject,
matched and matches into bitfields.
(preprocess_constraints): New overload.
(preprocess_insn_constraints): New function.
(preprocess_constraints): Take the insn as parameter.
(recog_op_alt): Change into a pointer.
(target_recog): Add x_op_alt.
* recog.c (asm_op_alt): New variable.
(recog_op_alt): Change into a pointer.
(preprocess_constraints): New overload, replacing the old function
definition with one that doesn't use global state.
(preprocess_insn_constraints): New function.
(preprocess_constraints): Use them.  Take the insn as parameter.
Use asm_op_alt for asms.
(recog_init): Free existing x_op_alt entries.
* ira-lives.c (check_and_make_def_conflict): Make operand_alternative
pointer const.
(make_early_clobber_and_input_conflicts): Likewise.
(process_bb_node_lives): Pass the insn to process_constraints.
* reg-stack.c (check_asm_stack_operands): Likewise.
(subst_asm_stack_regs): Likewise.
* regcprop.c (copyprop_hardreg_forward_1): Likewise.
* regrename.c (build_def_use): Likewise.
* sched-deps.c (sched_analyze_insn): Likewise.
* sel-sched.c (get_reg_class, implicit_clobber_conflict_p): Likewise.
* config/arm/arm.c (xscale_sched_adjust_cost): Likewise.
(note_invalid_constants): Likewise.
* config/i386/i386.c (ix86_legitimate_combined_insn): Likewise.
(ix86_legitimate_combined_insn): Make operand_alternative pointer
const.

Index: gcc/recog.h
===
--- gcc/recog.h 2014-05-31 09:02:35.956369716 +0100
+++ gcc/recog.h 2014-05-31 09:10:16.596150618 +0100
@@ -46,18 +46,18 @@ struct operand_alternative
   const char *constraint;
 
   /* The register class valid for this alternative (possibly NO_REGS).  */
-  enum reg_class cl;
+  ENUM_BITFIELD (reg_class) cl : 16;
 
   /* "Badness" of this alternative, computed from number of '?' and '!'
  characters in the constraint string.  */
-  unsigned int reject;
+  unsigned int reject : 16;
 
   /* -1 if no matching constraint was found, or an operand number.  */
-  int matches;
+  int matches : 8;
   /* The same information, but reversed: -1 if this operand is not
  matched by any other, or the operand number of the operand that
  matches this one.  */
-  int matched;
+  int matched : 8;
 
   /* Nonzero if '&' was found in the constraint string.  */
   unsigned int earlyclobber:1;
@@ -77,6 +77,8 @@ struct operand_alternative
   /* Nonzero if 'X' was found in the constraint string, or if the constraint
  string for this alternative was empty.  */
   unsigned int anything_ok:1;
+
+  unsigned int unused : 8;
 };
 
 /* Return the class for operand I of alternative ALT, taking matching
@@ -142,7 +144,10 @@ extern void insn_extract (rtx);
 extern void extract_insn (rtx);
 extern void extract_constrain_insn_cached (rtx);
 extern void extract_insn_cached (rtx);
-extern void preprocess_constraints (void);
+extern void preprocess_constraints (int, int, const char **,
+   operand_alternative *);
+extern const operand_alternative *preprocess_insn_constraints (int);
+extern void preprocess_constraints (rtx);
 extern rtx peep2_next_insn (int);
 extern int peep2_regno_dead_p (int, int);
 extern int peep2_reg_dead_p (int, rtx);
@@ -264,8 +269,7 @@ struct recog_data_d
 
 extern struct recog_data_d recog_data;
 
-extern struct operand_alternative recog_op_alt[MAX_RECOG_OPERANDS
-  * MAX_RECOG_ALTERNATIVES];
+extern const operand_alternative *recog_op_alt;
 
 /* Return a pointer to an array in which index OP describes the constraints
on operand OP of the current instruction alternative (which_alternative).
@@ -396,6 +400,7 @@ struct insn_data_d
 struct target_recog {
   bool x_initialized;
   alternative_mask x_enabled_alternatives[LAST_INSN_CODE];
+  operand_alternative *x_op_alt[LAST_INSN_CODE];
 };
 
 extern struct target_recog default_target_recog;
Index: gcc/recog.c
===
--- gcc/recog.c 2014-05-31 09:07:21.669714878 +0100
+++ gcc/recog.c 2014-05-31 09:15:38.746800685 +0100
@@ -81,8 +81,11 @@ struct recog_data_d recog_data;
 /* Contains a vector of operand_alternative structures, such that
operand OP of alternative A is at index A * n_operands + OP.
Set up by preprocess_constraints.  */
-struct operand_alternative recog_op_alt[MAX_RECOG_OPERANDS
-   * MAX_RECOG_ALTERNATIVES];
+const operand_alternative *recog_op_alt;
+
+/* Used to provide recog_op_alt for asms.  */
+st

[PATCH 5/5] Reuse recog_op_alt cache in LRA

[Richard Sandiford]

The operand_alternative cache was LRA's only per-subtarget state
so a lot of this patch is removing the associated initialisation
and target_globals stuff.

I called the preprocess_constraints functions in lra_set_insn_recog_data
rather than setup_operand_alternative because lra_set_insn_recog_data
already has a local constraints array (needed for asms).
setup_operand_alternative is now only called in the uncached case.

Thanks,
Richard


gcc/
* lra-int.h (lra_static_insn_data): Make operand_alternative a
const pointer.
(target_lra_int, default_target_lra_int, this_target_lra_int)
(op_alt_data): Delete.
* lra.h (lra_init): Delete.
* lra.c (default_target_lra_int, this_target_lra_int): Delete.
(init_insn_code_data_once): Remove op_alt_data handling.
(finish_insn_code_data_once): Likewise.
(init_op_alt_data): Delete.
(get_static_insn_data): Initialize operand_alternative to null.
(free_insn_recog_data): Cast operand_alternative before freeing it.
(setup_operand_alternative): Take the operand_alternative as
parameter and assume it isn't already cached in the static
insn data.
(lra_set_insn_recog_data): Update accordingly.
(lra_init): Delete.
* ira.c (ira_init): Don't call lra_init.
* target-globals.h (this_target_lra_int): Declare.
(target_globals): Remove lra_int.
(restore_target_globals): Update accordingly.
* target-globals.c: Don't include lra-int.h.
(default_target_globals, save_target_globals): Remove lra_int.

Index: gcc/lra-int.h
===
--- gcc/lra-int.h   2014-05-31 08:54:08.894207303 +0100
+++ gcc/lra-int.h   2014-05-31 09:25:56.876885502 +0100
@@ -198,7 +198,7 @@ struct lra_static_insn_data
   /* Array [n_alternatives][n_operand] of static constraint info for
  given operand in given alternative.  This info can be changed if
  the target reg info is changed.  */
-  struct operand_alternative *operand_alternative;
+  const struct operand_alternative *operand_alternative;
 };
 
 /* LRA internal info about an insn (LRA internal insn
@@ -495,21 +495,3 @@ lra_assign_reg_val (int from, int to)
   lra_reg_info[to].val = lra_reg_info[from].val;
   lra_reg_info[to].offset = lra_reg_info[from].offset;
 }
-
-
-struct target_lra_int
-{
-  /* Map INSN_UID -> the operand alternative data (NULL if unknown).
- We assume that this data is valid until register info is changed
- because classes in the data can be changed.  */
-  struct operand_alternative *x_op_alt_data[LAST_INSN_CODE];
-};
-
-extern struct target_lra_int default_target_lra_int;
-#if SWITCHABLE_TARGET
-extern struct target_lra_int *this_target_lra_int;
-#else
-#define this_target_lra_int (&default_target_lra_int)
-#endif
-
-#define op_alt_data (this_target_lra_int->x_op_alt_data)
Index: gcc/lra.h
===
--- gcc/lra.h   2014-05-31 08:54:08.894207303 +0100
+++ gcc/lra.h   2014-05-31 09:25:56.951886120 +0100
@@ -36,5 +36,4 @@ extern rtx lra_create_new_reg (enum mach
 extern rtx lra_eliminate_regs (rtx, enum machine_mode, rtx);
 extern void lra (FILE *);
 extern void lra_init_once (void);
-extern void lra_init (void);
 extern void lra_finish_once (void);
Index: gcc/lra.c
===
--- gcc/lra.c   2014-05-31 08:54:08.894207303 +0100
+++ gcc/lra.c   2014-05-31 09:25:56.891885625 +0100
@@ -553,11 +553,6 @@ finish_insn_regs (void)
 /* This page contains code dealing LRA insn info (or in other words
LRA internal insn representation).  */
 
-struct target_lra_int default_target_lra_int;
-#if SWITCHABLE_TARGET
-struct target_lra_int *this_target_lra_int = &default_target_lra_int;
-#endif
-
 /* Map INSN_CODE -> the static insn data.  This info is valid during
all translation unit.  */
 struct lra_static_insn_data *insn_code_data[LAST_INSN_CODE];
@@ -599,7 +594,6 @@ static struct lra_static_insn_data debug
 init_insn_code_data_once (void)
 {
   memset (insn_code_data, 0, sizeof (insn_code_data));
-  memset (op_alt_data, 0, sizeof (op_alt_data));
 }
 
 /* Called once per compiler work to finalize some LRA data related to
@@ -613,25 +607,9 @@ finish_insn_code_data_once (void)
 {
   if (insn_code_data[i] != NULL)
free (insn_code_data[i]);
-  if (op_alt_data[i] != NULL)
-   free (op_alt_data[i]);
 }
 }
 
-/* Initialize LRA info about operands in insn alternatives.  */
-static void
-init_op_alt_data (void)
-{
- int i;
-
-  for (i = 0; i < LAST_INSN_CODE; i++)
-if (op_alt_data[i] != NULL)
-  {
-   free (op_alt_data[i]);
-   op_alt_data[i] = NULL;
-  }
-}
-
 /* Return static insn data, allocate and setup if necessary.  Although
dup_num is static data (it depends only on icode), to set it up we
need to extract insn first. So recog_dat

Re: [Patch ARM] PR 61154 - Define TARGET_SUPPORTS_WIDE_INT.

[Richard Sandiford]

Ramana Radhakrishnan  writes:
> Hi,
>
>   This is the simplest patch to fix PR61154 that came after the wide-int 
> merge. I've got a patch stack that tries to audit the use of GEN_INT vs 
> gen_int_mode and the use of CONST_DOUBLE with VOIDmode in the backend 
> but it's still not safe to go and TBH I'd like to deal with that 
> separately given the current state of brokenness in the tree.
>
> Tested with a bootstrap again today on top of 211072 and earlier 
> regression tests showed no regressions.
>
> Will apply once regression tests finish.
>
> regards
> Ramana
>
>   Ramana Radhakrishnan  
>
> * config/arm/arm.h (TARGET_SUPPORTS_WIDE_INT): Define.
> * config/arm/arm.md (movdi splitter): Replace const_double_operand
>   with immediate_operand.

Thanks for doing this!

Richard

Re: [patch, mips, tree] align microMIPS functions to 16 bits with -Os

[Richard Sandiford]

Sandra Loosemore  writes:
> On 05/28/2014 01:09 PM, Richard Sandiford wrote:
>> Sandra Loosemore  writes:
>>
>>> On 05/19/2014 01:38 PM, Sandra Loosemore wrote:

 2014-05-19  Iain Sandoe  
   Catherine Moore  
   Sandra Loosemore  

   gcc/
   * config/mips/mips.c (mips_set_current_function): Choose
   function alignment once the current mode is known.

   gcc/testsuite/
   * gcc.target/mips/umips-align-1.c: New.
   * gcc.target/mips/umips-align-2.c: New.
   * gcc.target/mips/umips-align-3.c: New.
   * gcc.target/mips/mips.exp: Add interlink-compressed to
   -mfoo/-mno-foo options.
>>>
>>> Ping?
>>>
>>> https://gcc.gnu.org/ml/gcc-patches/2014-05/msg01536.html
>>>
>>> -Sandra
>>
>> FAOD, I wasn't commenting because I still think it's the wrong place but
>> still don't have a specific counter-suggestion.  mips_set_current_function
>> is potentially called many times for the same function but setting the
>> alignment seems like something that should only happen once.  I think it
>> could potentially mean that alignment tests against the function address
>> could be optimised away based on the FUNCTION_BOUNDARY before
>> mips_set_current_function is called.
>>
>> As a strawman, maybe adding a new target hook to cgraph_create_node
>> would work?
>
> H, why there?

I just thought trying to trap it at cgraph hand-off time would be
late enough to know the ISA mode of the function but early enough
to catch inter-function references.

>> Hopefully that'll prompt someone to say how stupid that
>> idea is and say what the right way of doing it would be.
>
> If the implementation in the current patch is considered too stupid, I'd 
> rather spend my time implementing a plausibly correct version on my next 
> try instead of another stupid one.
>
> My best guess is that this belongs somewhere in stor-layout.c, but the 
> comments on layout_decl explicitly say FUNCTION_DECLs are not handled 
> there, and I am not so familiar with the code as to be able to identify 
> all the places where FUNCTION_DECLs ought to get their storage laid out 
> but are not currently having it done.  So that's probably a stupid idea, 
> too  :-(

I'll try asking on IRC next week.

Thanks,
Richard

Re: [patch i386]: Expand sibling-tail-calls via accumulator register

[Kai Tietz]

That patch won't help here.  My tests showing here a different
problem.  For -O2 or above this issue happens.

For -O2 the following code will be generated.
movl28(%esp), %eax
testl   %eax, %eax
je  L16
movl%ebp, 64(%esp)
addl$44, %esp
popl%ebx
popl%esi
popl%edi
popl%ebp
jmp *28(%esp)
Question here is why it tries to use memory-address here instead of
simply using eax-register, which is already loaded.

A small testcase for that is:

typedef void *ira_loop_tree_node_t;
#define NULL 0

extern int end (int);
extern int doo (int);

void
ira_traverse_loop_tree (bool bb_p, ira_loop_tree_node_t loop_node,
void (*preorder_func) (ira_loop_tree_node_t),
void (*postorder_func) (ira_loop_tree_node_t))
{
  int l, r = 0x1, h = 0, j = 0;

  if (preorder_func != NULL)
(*preorder_func) (loop_node);

  if (bb_p)
{
  for (l = 0; l < end (l); l++)
{
  r += doo (l);
  h += (l + 1) * 3;
  h %= (l + 1);
  r -= doo (h);
  j += (l + 1) * 7;
  j %= (l + 1);
  r += doo (j);
}
}

  if (postorder_func != NULL)
(*postorder_func) (loop_node);
}

Re: [PATCH, Fortan] fix initialization of flag_errno_math and flag_associative_math

[Dominique Dhumieres]

Hi Joost,

Why do you want -fno-math-errno to be the default for gfortran?
AFAICT such default is not documented and the flag works
(checked on your test gfortran.dg/errnocheck_1.f90).

For -fassociative-math, the manual says

For Fortran the option is automatically enabled when both -fno-signed-zeros and 
-fno-trapping-math are in effect.

and again AFAICT this is not working (checked on your test
gfortran.dg/associative_1.f90) while I see

  /* Fortran allows associative math - but we cannot reassociate if
 we want traps or signed zeros. Cf. also flag_protect_parens.  */
  if (flag_associative_math == -1)
flag_associative_math = (!flag_trapping_math && !flag_signed_zeros);

in gcc/fortran/options.c. Why this is not working is beyond my understanding,
but I am not sure that your fix is the right one.

Cheers,

Dominique

Re: [patch i386]: Expand sibling-tail-calls via accumulator register

[Kai Tietz]

Hello,

recent fallout about sibcall was caused by using 'm' constraint for
sibcalls.  By this wrongly combines happened on reload-pass.

ChangeLog

2014-05-31  Kai Tietz  

* constrains.md (define_constrain): New 'B' constraint.
* i386.md (sibcall_insn_operand): Use B instead of m constraint.

ChangeLog testsuite

2014-05-31  Kai Tietz  

* gcc.target/i386/sibcall-6.c: New test.

Bootstrapped i386-unknown-linux-gnu, x86_64-unknown-linux-gnu.  Ok for apply?

Regards,
Kai

Index: constraints.md
===
--- constraints.md(Revision 211089)
+++ constraints.md(Arbeitskopie)
@@ -18,7 +18,7 @@
 ;; .

 ;;; Unused letters:
-;;; B H
+;;;   H
 ;;;   h j

 ;; Integer register constraints.
@@ -151,6 +151,11 @@
   "@internal Constant call address operand."
   (match_operand 0 "constant_call_address_operand"))

+(define_constraint "B"
+  "@internal Sibcall memory operand."
+  (and (not (match_test "TARGET_X32"))
+   (match_operand 0 "sibcall_memory_operand")))
+
 (define_constraint "w"
   "@internal Call memory operand."
   (and (not (match_test "TARGET_X32"))
Index: i386.md
===
--- i386.md(Revision 211089)
+++ i386.md(Arbeitskopie)
@@ -11376,12 +11376,41 @@
   [(set_attr "type" "call")])

 (define_insn "*sibcall"
-  [(call (mem:QI (match_operand:W 0 "sibcall_insn_operand" "Uzm"))
+  [(call (mem:QI (match_operand:W 0 "sibcall_insn_operand" "UzB"))
  (match_operand 1))]
   "SIBLING_CALL_P (insn)"
   "* return ix86_output_call_insn (insn, operands[0]);"
   [(set_attr "type" "call")])

+; TODO
+(define_peephole2
+  [(set (match_operand:DI 0 "register_operand")
+(match_operand:DI 1 "memory_operand"))
+   (unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
+  "TARGET_64BIT"
+  [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)
+   (set (match_dup 0)
+(match_dup 1))])
+
+(define_peephole2
+  [(set (match_operand:SI 0 "register_operand")
+(match_operand:SI 1 "memory_operand"))
+   (unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
+  "!TARGET_64BIT"
+  [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)
+   (set (match_dup 0)
+(match_dup 1))])
+
+(define_peephole2
+  [(set (match_operand:DI 0 "register_operand")
+(match_operand:DI 1 "memory_operand"))
+   (call (mem:QI (match_operand:DI 2 "register_operand"))
+ (match_operand 3))]
+  "TARGET_64BIT  && REG_P (operands[0]) && 0
+&& REG_P (operands[2])
+&& REGNO (operands[0]) == REGNO (operands[2])"
+  [(call (mem:QI (match_dup 1)) (match_dup 1))])
+
 (define_expand "call_pop"
   [(parallel [(call (match_operand:QI 0)
 (match_operand:SI 1))
@@ -11406,7 +11435,7 @@
   [(set_attr "type" "call")])

 (define_insn "*sibcall_pop"
-  [(call (mem:QI (match_operand:SI 0 "sibcall_insn_operand" "Uzm"))
+  [(call (mem:QI (match_operand:SI 0 "sibcall_insn_operand" "UzB"))
  (match_operand 1))
(set (reg:SI SP_REG)
 (plus:SI (reg:SI SP_REG)
@@ -11451,7 +11480,7 @@

 (define_insn "*sibcall_value"
   [(set (match_operand 0)
-(call (mem:QI (match_operand:W 1 "sibcall_insn_operand" "Uzm"))
+(call (mem:QI (match_operand:W 1 "sibcall_insn_operand" "UzB"))
   (match_operand 2)))]
   "SIBLING_CALL_P (insn)"
   "* return ix86_output_call_insn (insn, operands[1]);"
@@ -11494,7 +11523,7 @@

 (define_insn "*sibcall_value_pop"
   [(set (match_operand 0)
-(call (mem:QI (match_operand:SI 1 "sibcall_insn_operand" "Uzm"))
+(call (mem:QI (match_operand:SI 1 "sibcall_insn_operand" "UzB"))
   (match_operand 2)))
(set (reg:SI SP_REG)
 (plus:SI (reg:SI SP_REG)
Index: gcc.target/i386/sibcall-6.c
===
--- gcc.target/i386/sibcall-6.c(Revision 0)
+++ gcc.target/i386/sibcall-6.c(Arbeitskopie)
@@ -0,0 +1,37 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target ia32 } */
+/* { dg-options "-O2" } */
+
+typedef void *ira_loop_tree_node_t;
+
+extern int end (int);
+extern int doo (int);
+
+void
+ira_traverse_loop_tree (int bb_p, ira_loop_tree_node_t loop_node,
+void (*preorder_func) (ira_loop_tree_node_t),
+void (*postorder_func) (ira_loop_tree_node_t))
+{
+  int l, r = 0x1, h = 0, j = 0;
+
+  if (preorder_func)
+(*preorder_func) (loop_node);
+
+  if (bb_p)
+{
+  for (l = 0; l < end (l); l++)
+{
+  r += doo (l);
+  h += (l + 1) * 3;
+  h %= (l + 1);
+  r -= doo (h);
+  j += (l + 1) * 7;
+  j %= (l + 1);
+  r += doo (j);
+}
+}
+
+  if (postorder_func != NULL)
+(*postorder_func) (loop_node);
+}
+/* { dg-final { scan-assembler "jmp[ \t]*.%eax" } } */

[PATCH] m68k: add missing early clobber in beq0_di, bne0_di patterns

[Andreas Schwab]

This is a wrong code bug that appeared in netcdf when compiling with gcc
4.8.  Due to difference in register allocation this doesn't trigger in
4.9 or trunk, but it is obvious that the bug is only dormant.  The issue
is that if the first operand matches "o" it may contain the same
register as operand 2 as part of the address.  Clearly the register
overlap checks only make sense if the first operand matches "d".  So for
an "o" operand we need to mark the scratch register as early clobber.

Bootstrapped on m68k-suse-linux and installed in trunk.

Andreas.

* config/m68k/m68k.md (beq0_di, bne0_di): Make the "o" constraint
a separate alternative where the scratch operand 2 is marked as
early clobber.
---
 gcc/config/m68k/m68k.md | 14 +++---
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/gcc/config/m68k/m68k.md b/gcc/config/m68k/m68k.md
index c4ebb0e..9729624 100644
--- a/gcc/config/m68k/m68k.md
+++ b/gcc/config/m68k/m68k.md
@@ -5961,15 +5961,15 @@
 
 (define_insn "beq0_di"
   [(set (pc)
-(if_then_else (eq (match_operand:DI 0 "general_operand" "d*ao,<>")
+(if_then_else (eq (match_operand:DI 0 "general_operand" "d*a,o,<>")
 (const_int 0))
-(label_ref (match_operand 1 "" ","))
+(label_ref (match_operand 1 "" ",,"))
 (pc)))
-   (clobber (match_scratch:SI 2 "=d,d"))]
+   (clobber (match_scratch:SI 2 "=d,&d,d"))]
   ""
 {
   CC_STATUS_INIT;
-  if (which_alternative == 1)
+  if (which_alternative == 2)
 return "move%.l %0,%2\;or%.l %0,%2\;jeq %l1";
   if ((cc_prev_status.value1
   && rtx_equal_p (cc_prev_status.value1, operands[0]))
@@ -6006,11 +6006,11 @@
 
 (define_insn "bne0_di"
   [(set (pc)
-(if_then_else (ne (match_operand:DI 0 "general_operand" "do,*a")
+(if_then_else (ne (match_operand:DI 0 "general_operand" "d,o,*a")
 (const_int 0))
-(label_ref (match_operand 1 "" ","))
+(label_ref (match_operand 1 "" ",,"))
 (pc)))
-   (clobber (match_scratch:SI 2 "=d,X"))]
+   (clobber (match_scratch:SI 2 "=d,&d,X"))]
   ""
 {
   if ((cc_prev_status.value1
-- 
2.0.0

-- 
Andreas Schwab, sch...@linux-m68k.org
GPG Key fingerprint = 58CA 54C7 6D53 942B 1756  01D3 44D5 214B 8276 4ED5
"And now for something completely different."

Re: [patch i386]: Expand sibling-tail-calls via accumulator register

[Kai Tietz]

In testcase a NULL escaped ...

ChangeLog testsuite

2014-05-31  Kai Tietz  

* gcc.target/i386/sibcall-6.c: New test.

Index: gcc.target/i386/sibcall-6.c
===
--- gcc.target/i386/sibcall-6.c(Revision 0)
+++ gcc.target/i386/sibcall-6.c(Arbeitskopie)
@@ -0,0 +1,37 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target ia32 } */
+/* { dg-options "-O2" } */
+
+typedef void *ira_loop_tree_node_t;
+
+extern int end (int);
+extern int doo (int);
+
+void
+ira_traverse_loop_tree (int bb_p, ira_loop_tree_node_t loop_node,
+void (*preorder_func) (ira_loop_tree_node_t),
+void (*postorder_func) (ira_loop_tree_node_t))
+{
+  int l, r = 0x1, h = 0, j = 0;
+
+  if (preorder_func)
+(*preorder_func) (loop_node);
+
+  if (bb_p)
+{
+  for (l = 0; l < end (l); l++)
+{
+  r += doo (l);
+  h += (l + 1) * 3;
+  h %= (l + 1);
+  r -= doo (h);
+  j += (l + 1) * 7;
+  j %= (l + 1);
+  r += doo (j);
+}
+}
+
+  if (postorder_func)
+(*postorder_func) (loop_node);
+}
+/* { dg-final { scan-assembler "jmp[ \t]*.%eax" } } */

[patch i386]: Fix sibcall failures caused by allowing constant memories

[Kai Tietz]

Hello,

I resend patch within new thread.
Recent fallout about sibcall was caused by using 'm' constraint for
sibcalls.  By this wrongly combines happened on reload-pass. That
patch introduces new constraint 'B' for sibcall_memory_operand.

ChangeLog

2014-05-31  Kai Tietz  

* constrains.md (define_constrain): New 'B' constraint.
* i386.md (sibcall_insn_operand): Use B instead of m constraint.

ChangeLog testsuite

2014-05-31  Kai Tietz  

* gcc.target/i386/sibcall-6.c: New test.

Bootstrapped i386-unknown-linux-gnu, x86_64-unknown-linux-gnu.  Ok for apply?

Regards,
Kai

Index: constraints.md
===
--- constraints.md(Revision 211089)
+++ constraints.md(Arbeitskopie)
@@ -18,7 +18,7 @@
 ;; .

 ;;; Unused letters:
-;;; B H
+;;;   H
 ;;;   h j

 ;; Integer register constraints.
@@ -151,6 +151,11 @@
   "@internal Constant call address operand."
   (match_operand 0 "constant_call_address_operand"))

+(define_constraint "B"
+  "@internal Sibcall memory operand."
+  (and (not (match_test "TARGET_X32"))
+   (match_operand 0 "sibcall_memory_operand")))
+
 (define_constraint "w"
   "@internal Call memory operand."
   (and (not (match_test "TARGET_X32"))
Index: i386.md
===
--- i386.md(Revision 211089)
+++ i386.md(Arbeitskopie)
@@ -11376,12 +11376,41 @@
   [(set_attr "type" "call")])

 (define_insn "*sibcall"
-  [(call (mem:QI (match_operand:W 0 "sibcall_insn_operand" "Uzm"))
+  [(call (mem:QI (match_operand:W 0 "sibcall_insn_operand" "UzB"))
  (match_operand 1))]
   "SIBLING_CALL_P (insn)"
   "* return ix86_output_call_insn (insn, operands[0]);"
@@ -11406,7 +11435,7 @@
   [(set_attr "type" "call")])

 (define_insn "*sibcall_pop"
-  [(call (mem:QI (match_operand:SI 0 "sibcall_insn_operand" "Uzm"))
+  [(call (mem:QI (match_operand:SI 0 "sibcall_insn_operand" "UzB"))
  (match_operand 1))
(set (reg:SI SP_REG)
 (plus:SI (reg:SI SP_REG)
@@ -11451,7 +11480,7 @@

 (define_insn "*sibcall_value"
   [(set (match_operand 0)
-(call (mem:QI (match_operand:W 1 "sibcall_insn_operand" "Uzm"))
+(call (mem:QI (match_operand:W 1 "sibcall_insn_operand" "UzB"))
   (match_operand 2)))]
   "SIBLING_CALL_P (insn)"
   "* return ix86_output_call_insn (insn, operands[1]);"
@@ -11494,7 +11523,7 @@

 (define_insn "*sibcall_value_pop"
   [(set (match_operand 0)
-(call (mem:QI (match_operand:SI 1 "sibcall_insn_operand" "Uzm"))
+(call (mem:QI (match_operand:SI 1 "sibcall_insn_operand" "UzB"))
   (match_operand 2)))
(set (reg:SI SP_REG)
 (plus:SI (reg:SI SP_REG)
Index: gcc.target/i386/sibcall-6.c
===
--- gcc.target/i386/sibcall-6.c(Revision 0)
+++ gcc.target/i386/sibcall-6.c(Arbeitskopie)
@@ -0,0 +1,37 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target ia32 } */
+/* { dg-options "-O2" } */
+
+typedef void *ira_loop_tree_node_t;
+
+extern int end (int);
+extern int doo (int);
+
+void
+ira_traverse_loop_tree (int bb_p, ira_loop_tree_node_t loop_node,
+void (*preorder_func) (ira_loop_tree_node_t),
+void (*postorder_func) (ira_loop_tree_node_t))
+{
+  int l, r = 0x1, h = 0, j = 0;
+
+  if (preorder_func)
+(*preorder_func) (loop_node);
+
+  if (bb_p)
+{
+  for (l = 0; l < end (l); l++)
+{
+  r += doo (l);
+  h += (l + 1) * 3;
+  h %= (l + 1);
+  r -= doo (h);
+  j += (l + 1) * 7;
+  j %= (l + 1);
+  r += doo (j);
+}
+}
+
+  if (postorder_func)
+(*postorder_func) (loop_node);
+}
+/* { dg-final { scan-assembler "jmp[ \t]*.%eax" } } */

Re: ipa-visibility TLC 2/n

[David Edelsohn]

This leads to bootstrap errors like:

In file included from
/tmp/20140531/powerpc-ibm-aix7.1.0.0/libstdc++-v3/include/backward/strstream:54:0,
 from
/nasfarm/edelsohn/src/src/libstdc++-v3/src/c++98/strstream.cc:44:
/tmp/20140531/powerpc-ibm-aix7.1.0.0/libstdc++-v3/include/istream: In
constructor 'std::istrstream::istrstream(char*)':
/tmp/20140531/powerpc-ibm-aix7.1.0.0/libstdc++-v3/include/istream:94:32:
internal compiler error: in place_block_symbol, at varasm.c:7067
   : _M_gcount(streamsize(0))
^

On Sat, May 31, 2014 at 3:42 AM, Richard Sandiford
 wrote:
> David Edelsohn  writes:
>> Honza,
>>
>> With the patch, I cannot bootstrap.
>
> I think it was meant to be:
>
>   place_block_symbol (target);
>
> rather than:
>
>   place_block_symbol (symbol);
>
> I.e. we need to place "target" before copying its offset.
>
> Thanks,
> Richard

Re: [patch i386]: Fix sibcall failures caused by allowing constant memories

[Dominique Dhumieres]

> I resend patch within new thread. ...

This patch fixes pr61377. Could it be committed ASAP?

TIA,

Dominique

Re: Eliminate write-only variables

[Sandra Loosemore]

On 05/20/2014 04:56 AM, Richard Biener wrote:

On Tue, May 20, 2014 at 6:29 AM, Jan Hubicka  wrote:

On 05/18/2014 08:45 PM, Sandra Loosemore wrote:

On 05/18/2014 02:59 PM, Jan Hubicka wrote:

For cases like local-statics-7 your approach can be "saved" by adding
simple IPA analysis
to look for static vars that are used only by one function and keeping
your DSE code active
for them, so we can still get rid of this special case assignments
during late compilation.
I am however not quite convinced it is worth the effort - do you have
some real world
cases where it helps?


Um, the well-known benchmark.  ;-)


I looked at the generated code for this benchmark and see that your
patch is indeed not getting rid of all the pointless static
variables, while ours is, so this is quite disappointing.  I'm
thinking now that we will still need to retain our patch at least
locally, although we'd really like to get it on trunk if possible.


Yours patch can really be improved by adding simple IPA analysis to work
out what variables are refernced by one function only instead of using
not-longer-that-relevant local static info.
As last IPA pass for each static variable with no address taken, look at all
references and see if they all come from one function or functions inlined to
it.


Here is another testcase vaguely based on the same kind of
signal-processing algorithm as the benchmark, but coded without
reference to it.  I have arm-none-eabi builds around for both 4.9.0
with our remove_local_statics patch applied, and trunk with your
patch.  With -O2, our optimization produces 23 instructions and gets
rid of all 3 statics, yours produces 33 and only gets rid of 1 of
them.

Of course it's lame to use static variables in this way, but OTOH
it's lame if GCC can't recognize them and optimize them away, too.

-Sandra




void
fir (int *coeffs, int coeff_length, int *input, int input_length, int *output)
{
   static int *coeffp;
   static int *inputp;
   static int *outputp;


Here inputp read is rmeoved only at 101.dceloop1 pass. That is really late.
coeffp is removed late, too.


   int i, c, acc;

   for (i = 0; i < input_length; i++)
 {
   coeffp = coeffs;
   inputp = input + i;
   outputp = output + i;
   acc = 0;
   for (c = 0; c < coeff_length; c++)
   {
 acc += *coeffp * *inputp;
 coeffp++;
 inputp--;
   }


It seems like AA can not work out the fact that inputp is unchanged until that
late.  Richi, any ideas?


Well, AA is perfectly fine - it's just that this boils down to a partial
redundancy problem.  The stores can be removed by DCE even with

Index: gcc/tree-ssa-dce.c
===
--- gcc/tree-ssa-dce.c  (revision 210635)
+++ gcc/tree-ssa-dce.c  (working copy)
@@ -278,10 +278,20 @@ mark_stmt_if_obviously_necessary (gimple
break;

  case GIMPLE_ASSIGN:
-  if (TREE_CODE (gimple_assign_lhs (stmt)) == SSA_NAME
- && TREE_CLOBBER_P (gimple_assign_rhs1 (stmt)))
-   return;
-  break;
+  {
+   tree lhs = gimple_assign_lhs (stmt);
+   if (TREE_CODE (lhs) == SSA_NAME
+   && TREE_CLOBBER_P (gimple_assign_rhs1 (stmt)))
+ return;
+   if (TREE_CODE (lhs) == VAR_DECL
+   && !TREE_ADDRESSABLE (lhs)
+   && TREE_STATIC (lhs)
+   && !TREE_PUBLIC (lhs) && !DECL_EXTERNAL (lhs)
+   /* ???  Make sure lhs is only refered to from cfun->decl.  */
+   && decl_function_context (lhs) == cfun->decl)
+ return;
+   break;
+  }

  default:
break;

but I don't have a good way of checking the ??? prerequesite
(even without taking its address the statics may be refered to
by a) inline copies, b) ipa-split function parts, c) nested functions).
I'm sure IPA references are not kept up-to-date.

The last reads go away with PRE at the expense of two
additional induction variables.

If we know that a static variable does not have its address taken
and is only refered to from a single function we can in theory
simply rewrite it into SSA form during early opts (before inlining
its body), for example by SRA.  That isn't even restricted to
function-local statics (for statics used in multiple functions but
not having address-taken we can do the same with doing
function entry / exit load / store).  I think that would be a much
better IPA enabled optimization than playing games with
looking at individual stmts.


FAOD, I'm not currently planning to work on this any more myself.  I 
understand Bernd's patch pretty well and could make some minor changes 
to clean it up if that's what it takes to get it approved, but it sounds 
like what's wanted is a completely different approach, again, and I 
don't have any confidence that I could implement something that wouldn't 
just get stuck in another round of "why don't you try X instead" or 
"maybe it would be better to do this in Y".  :-(


Richard, FWIW I think both of the object

Re: [PATCH] Do not build libsanitizer also for powerpc*-*-linux*

[Peter Bergner]

On Fri, 2014-05-30 at 15:49 +0200, Jakub Jelinek wrote:
> On Fri, May 30, 2014 at 08:09:22AM -0500, Peter Bergner wrote:
> > On Thu, 2014-05-29 at 14:07 -0500, Peter Bergner wrote:
> > > On Wed, 2014-05-28 at 09:36 +0200, Thomas Schwinge wrote:
> > > > This is being discussed in the thread at
> > > > .  Until that
> > > > has been resolved, I do agree to check in the following patch (and have
> > > > successfully tested it, but cannot formally approve it for commit; thus
> > > > copying the libsanitizer maintainers):
> > > 
> > > The re-enablement patch was submitted to the llvm mailing list here:
> > > 
> > >   
> > > http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20140526/219249.html
> > > 
> > > Once that is committed and merged into gcc, we can re-enable building
> > > libsanitizer for powerpc*-linux.
> > 
> > Ok, it was committed upstream as revision 209879.  Kostya, can we get
> > this merged into gcc trunk and powerpc*-linux re-enabled again?  Thanks.
> 
> I've cherry-picked the two upstream commits and after testing on
> x86_64-linux/i686-linux committed to trunk.

Great, thanks!  I bootstrapped and ran the asan testsuite.  I'm now seeing
lots of FAILs due to:

  ASan runtime does not come first in initial library list; you should either
  link runtime to your application or manually preload it with LD_PRELOAD.

...which Paolo mentioned in the other thread that he is hitting this too.
There was some discussion on what to do, but has there been a decision on
how to fix this yet?  Or is it fixed upstream and we just need to merge
that fix too?

Peter

Re: [patch i386]: Fix sibcall failures caused by allowing constant memories

[Jeff Law]

On 05/31/14 06:27, Kai Tietz wrote:

Hello,

I resend patch within new thread.
Recent fallout about sibcall was caused by using 'm' constraint for
sibcalls.  By this wrongly combines happened on reload-pass. That
patch introduces new constraint 'B' for sibcall_memory_operand.

ChangeLog

2014-05-31  Kai Tietz  

 * constrains.md (define_constrain): New 'B' constraint.
 * i386.md (sibcall_insn_operand): Use B instead of m constraint.

ChangeLog testsuite

2014-05-31  Kai Tietz  

 * gcc.target/i386/sibcall-6.c: New test.

Bootstrapped i386-unknown-linux-gnu, x86_64-unknown-linux-gnu.  Ok for apply?

OK.
Jeff

Re: [PATCH, PR 61160] IPA-CP and edges leading to thunks of clones

[Jan Hubicka]

> Hi,
> 
> PR 61160 is actually two problems, this patch deals with the one
> reported in comment one.  The underlying cause is that an IPA-CP test
> whether an edge is already leading to a clone does not look through
> thunks, which caused it to double count and doubly-redirect them.
> 
> Bootstrapped and tested on x86_64-linux, I will run the test on the
> 4.9 branch later.  OK for both if it passed everywhere?
> 
> Thanks,
> 
> Martin
> 
> 
> 2014-05-28  Martin Jambor  
> 
>   PR ipa/61160
>   * ipa-cp.c (cgraph_edge_brings_value_p): Handle edges leading to
>   thunks.
OK, thanks!
Honza

Re: ipa-visibility TLC 2/n

[Richard Sandiford]

David Edelsohn  writes:
> Honza,
>
> With the patch, I cannot bootstrap.

I think it was meant to be:

  place_block_symbol (target);

rather than:

  place_block_symbol (symbol);

I.e. we need to place "target" before copying its offset.

Thanks,
Richard