Re: [off list] Re: [PATCH] x86: use 'rep bsf' syntax when assembler supports it
On Sat, Jun 23, 2012 at 12:00 AM, Roland McGrath wrote: > Here is an alternative patch that just changes the configure test > controlling %; so it will elide the ; only for an assembler that > also accepts 'rep bsf', 'rep bsr', and 'rep ret', and just uses > %; for these cases too. You'll need to have built binutils from its trunk > within the last five minutes or so to have an assembler that passes the > test now. We found another one ... "rep nop" that implements "pause". It looks that this is really the last rep prefixed insn. With existing binutils, the use of ";" was mostly cosmetic, assembler checked that rep was indeed followed by a string instruction. Other than that, older binutils didn't care about the placement of ";". > gcc/ > 2012-06-22 Roland McGrath > > * configure.ac (HAVE_AS_IX86_REP_LOCK_PREFIX): Also require that the > assembler accept 'rep bsf ...', 'rep bsr ...', and 'rep ret'. > * configure: Regenerated. > * config/i386/i386.md (simple_return_internal_long): Use %; > (ctz2): Likewise. Based on the observation above, the patch is OK for mainline, but please also handle "rep nop" case. Thanks, Uros.
[PATCH, c-family]: Remove unused variables from c_common_write_pch
Hello!
2012-07-01 Uros Bizjak
* c-pch.c (c_common_write_pch): Remove unused variables.
Tested on x86_64-pc-linux-gnu, committed to mainline SVN.
Uros.
Index: c-pch.c
===
--- c-pch.c (revision 189099)
+++ c-pch.c (working copy)
@@ -169,9 +169,6 @@ pch_init (void)
void
c_common_write_pch (void)
{
- char *buf;
- long written;
-
timevar_push (TV_PCH_SAVE);
targetm.prepare_pch_save ();
Re: [patch] Move lowering of switches to bit tests to GIMPLE
On Sat, Jun 30, 2012 at 12:29 PM, Steven Bosscher wrote: > Hello, > > This patch moves the emit_case_bit_tests method of switch lowering > from 'expand' to a GIMPLE pass. > > Initially, I planned to move all switch lowering to something other > than a casesi or tablejump to GIMPLE, but this is more involved than I > anticipated. My plan was (and still is, but for later) to do the > switch lowering using a divide-and-conquer approach: Parts of a switch > may be best expanded as bit-tests, other parts maybe as a decision > tree, and yet others as casesi/tablejump (the code in stmt.c uses only > one of these approaches per GIMPLE_SWITCH). Also I wanted to use > profile information in the lowering decision making (using Freescale's > patch as a basis). But I need to come up with a way to handle the SJLJ > dispatch table issue. > > I'll continue to work on all of the above, and I hope I can finish > everything I planned to work on for GCC 4.8. > But to make sure I don't miss the GCC 4.8 stage1 deadline, I'm > proposing this for trunk now. > > Bootstrapped&tested on powerpc64-unknown-linux-gnu - several times in > fact, over the past few months. > Bootstrapped&tested on x86_64-unknown-linux-gnu. Also built&tested on > various powerpc64 X embedded targets. > > OK for trunk? This is ok. We have to think about the point in the pass pipeline where we want to do this (and the rest of) lowering. At the moment switch-conversion runs before profile-data is read and thus cannot do a very good job. I think lowering somewhere early after IPA optimizations (inlining and then constant propagation might affect the optimal lowering?) might be most sensible? Thanks for working on this, Richard. > Ciao! > Steven
Re: [Patch, Fortran] Handle C_F_POINTER with a noncontiguous SHAPE=
Hi Tobias, I am puzzled by the subject: the test gfortran.dg/c_f_pointer_shape_tests_5.f90 does not need the patch to succeed (at least after 4.5.3, it fails only for 4.4.6). Note that the similar test in http://gcc.gnu.org/ml/fortran/2012-04/msg00115.html fails because c_f_pointer(x, ptr, shape=myshape(::2)) try to set the shape [1,3,5] to a rank 2 pointer (note that this is not detected even with -fcheck=all, should I open a PR for it?). Otherwise I have regstraped trunk and fortran-dev with the patch without regression on trunk. On fortran-dev, as noticed, c_f_pointer_tests_3.f90 has to be adjusted and all the c_f_pointer_* failures are fixed, but c_f_pointer_tests.f90 (i.e., 4 failures out of 5, 15 to go). Cheers, Dominique
[PATCH, i386]: Use __builtin_ia32_pause some more
Hello!
gcc/
2012-07-01 Uros Bizjak
* config/i386/xmmintrin.h (_mm_sfence): Use __builtin_ia32_pause.
libgomp/
2012-07-01 Uros Bizjak
* config/linux/x86/futex.h (cpu_relax): Use __builtin_ia32_pause.
* testsuite/libgomp.c/sort-1.c (busy_wait): Ditto.
libitm/
2012-07-01 Uros Bizjak
* config/x86/target.h (cpu_relax): Use __builtin_ia32_pause.
Bootstrapped and regression tested on x86_64-pc-linux-gnu {,-m32}.
OK for mainline? The patch needs approval from libgomp and libitm maintainers.
Uros.
Index: libitm/config/x86/target.h
===
--- libitm/config/x86/target.h (revision 189100)
+++ libitm/config/x86/target.h (working copy)
@@ -63,7 +63,7 @@ typedef struct gtm_jmpbuf
static inline void
cpu_relax (void)
{
- __asm volatile ("rep; nop" : : : "memory");
+ __builtin_ia32_pause ();
}
} // namespace GTM
Index: gcc/config/i386/xmmintrin.h
===
--- gcc/config/i386/xmmintrin.h (revision 189100)
+++ gcc/config/i386/xmmintrin.h (working copy)
@@ -1225,7 +1225,7 @@ _mm_sfence (void)
extern __inline void __attribute__((__gnu_inline__, __always_inline__,
__artificial__))
_mm_pause (void)
{
- __asm__ __volatile__ ("rep; nop" : : );
+ __builtin_ia32_pause ();
}
/* Transpose the 4x4 matrix composed of row[0-3]. */
Index: libgomp/config/linux/x86/futex.h
===
--- libgomp/config/linux/x86/futex.h(revision 189100)
+++ libgomp/config/linux/x86/futex.h(working copy)
@@ -143,5 +143,5 @@ futex_wake (int *addr, int count)
static inline void
cpu_relax (void)
{
- __asm volatile ("rep; nop" : : : "memory");
+ __builtin_ia32_pause ();
}
Index: libgomp/testsuite/libgomp.c/sort-1.c
===
--- libgomp/testsuite/libgomp.c/sort-1.c(revision 189100)
+++ libgomp/testsuite/libgomp.c/sort-1.c(working copy)
@@ -100,7 +100,7 @@ static inline void
busy_wait (void)
{
#if defined __i386__ || defined __x86_64__
- __asm volatile ("rep; nop" : : : "memory");
+ __builtin_ia32_pause ();
#elif defined __ia64__
__asm volatile ("hint @pause" : : : "memory");
#elif defined __sparc__ && (defined __arch64__ || defined __sparc_v9__)
Re: [PATCH] Don't try to perform conditional_replacement on vectors (PR tree-optimization/53748)
Il 25/06/2012 16:44, Jakub Jelinek ha scritto: > Hi! > > On vectors, even when they satisfy > integer_zerop/integer_onep/integer_all_onesp, the routine doesn't > handle vector types and it is questionable if it would be a good > optimization for them anyway. I think it's not questionable at all, since creating such masks is exactly what vector comparison instructions do. But anyway that would be a separate patch. Thanks for the fix! Paolo
Re: [C++ Pubnames Patch] Anonymous namespaces enclosed in named namespaces. (issue6343052)
On Thu, Jun 28, 2012 at 12:50 PM, Sterling Augustine
wrote:
> The enclosed patch adds a fix for the pubnames anonymous namespaces contained
> within named namespaces, and adds an extensive test for the various pubnames.
>
> The bug is that when printing at verbosity level 1, and lang_decl_name sees a
> namespace decl in not in the global namespace, it prints the namespace's
> enclosing scopes--so far so good. However, the code I added earlier this month
> to handle anonymous namespaces also prints the enclosing scopes, so one would
> get foo::foo::(anonymous namespace) instead of foo::(anonymous namespace).
>
> The solution is to stop the added code from printing the enclosing scope,
> which
> is correct for both verbosity levels 0 and 1. Level 2 is handled elsewhere and
> so not relevant.
>
> I have formalized the tests I have been using to be sure pubnames are correct
> and include that in this patch. It is based on ccoutant's gdb_index_test.cc
> from
> the gold test suite.
>
> OK for mainline?
OK.
>
> Sterling
>
>
> gcc/cp/ChangeLog
>
> 2012-06-28 Sterling Augustine
>
> * error.c (lang_decl_name): Use TFF_UNQUALIFIED_NAME flag.
>
> gcc/testsuite/ChangeLog
>
> 2012-06-28 Sterling Augustine
>
> * g++.dg/debug/dwarf2/pubnames-2.C: New.
>
> Index: cp/error.c
> ===
> --- cp/error.c (revision 189025)
> +++ cp/error.c (working copy)
> @@ -2633,7 +2633,7 @@
> dump_function_name (decl, TFF_PLAIN_IDENTIFIER);
>else if ((DECL_NAME (decl) == NULL_TREE)
> && TREE_CODE (decl) == NAMESPACE_DECL)
> -dump_decl (decl, TFF_PLAIN_IDENTIFIER);
> +dump_decl (decl, TFF_PLAIN_IDENTIFIER | TFF_UNQUALIFIED_NAME);
>else
> dump_decl (DECL_NAME (decl), TFF_PLAIN_IDENTIFIER);
>
> Index: testsuite/g++.dg/debug/dwarf2/pubnames-2.C
> ===
> --- testsuite/g++.dg/debug/dwarf2/pubnames-2.C (revision 0)
> +++ testsuite/g++.dg/debug/dwarf2/pubnames-2.C (revision 0)
> @@ -0,0 +1,194 @@
> +// { dg-do compile }
> +// { dg-options "-gpubnames -gdwarf-4 -std=c++0x -dA" }
> +// { dg-final { scan-assembler ".section\t.debug_pubnames" } }
> +// { dg-final { scan-assembler "\"\\(anonymous namespace\\)0\"+\[
> \t\]+\[#;]+\[ \t\]+external name" } }
> +// { dg-final { scan-assembler "\"one0\"+\[ \t\]+\[#;]+\[ \t\]+external
> name" } }
> +// { dg-final { scan-assembler "\"one::G_A0\"+\[ \t\]+\[#;]+\[
> \t\]+external name" } }
> +// { dg-final { scan-assembler "\"one::G_B0\"+\[ \t\]+\[#;]+\[
> \t\]+external name" } }
> +// { dg-final { scan-assembler "\"one::G_C0\"+\[ \t\]+\[#;]+\[
> \t\]+external name" } }
> +// { dg-final { scan-assembler "\"one::\\(anonymous namespace\\)0\"+\[
> \t\]+\[#;]+\[ \t\]+external name" } }
> +// { dg-final { scan-assembler "\"two0\"+\[ \t\]+\[#;]+\[ \t\]+external
> name" } }
> +// { dg-final { scan-assembler "\"F_A0\"+\[ \t\]+\[#;]+\[ \t\]+external
> name" } }
> +// { dg-final { scan-assembler "\"F_B0\"+\[ \t\]+\[#;]+\[ \t\]+external
> name" } }
> +// { dg-final { scan-assembler "\"F_C0\"+\[ \t\]+\[#;]+\[ \t\]+external
> name" } }
> +// { dg-final { scan-assembler "\"inline_func_10\"+\[ \t\]+\[#;]+\[
> \t\]+external name" } }
> +// { dg-final { scan-assembler "\"one::c1::c10\"+\[ \t\]+\[#;]+\[
> \t\]+external name" } }
> +// { dg-final { scan-assembler "\"one::c1::~c10\"+\[ \t\]+\[#;]+\[
> \t\]+external name" } }
> +// { dg-final { scan-assembler "\"one::c1::val0\"+\[ \t\]+\[#;]+\[
> \t\]+external name" } }
> +// { dg-final { scan-assembler "\"check_enum0\"+\[ \t\]+\[#;]+\[
> \t\]+external name" } }
> +// { dg-final { scan-assembler "\"main0\"+\[ \t\]+\[#;]+\[ \t\]+external
> name" } }
> +// { dg-final { scan-assembler "\"two::c2::c20\"+\[ \t\]+\[#;]+\[
> \t\]+external name" } }
> +// { dg-final { scan-assembler "\"two::c2::c20\"+\[
> \t\]+\[#;]+\[ \t\]+external name" } }
> +// { dg-final { scan-assembler "\"two::c2::c20\"+\[
> \t\]+\[#;]+\[ \t\]+external name" } }
> +// { dg-final { scan-assembler "\"check0\"+\[ \t\]+\[#;]+\[
> \t\]+external name" } }
> +// { dg-final { scan-assembler "\"check \\>0\"+\[
> \t\]+\[#;]+\[ \t\]+external name" } }
> +// { dg-final { scan-assembler "\"check \\>0\"+\[
> \t\]+\[#;]+\[ \t\]+external name" } }
> +// { dg-final { scan-assembler "\"check \\>0\"+\[
> \t\]+\[#;]+\[ \t\]+external name" } }
> +// { dg-final { scan-assembler "\"two::c2::val0\"+\[ \t\]+\[#;]+\[
> \t\]+external name" } }
> +// { dg-final { scan-assembler "\"two::c2::val0\"+\[
> \t\]+\[#;]+\[ \t\]+external name" } }
> +// { dg-final { scan-assembler "\"two::c2::val0\"+\[
> \t\]+\[#;]+\[ \t\]+external name" } }
> +// { dg-final { scan-assembler
> "\"__static_initialization_and_destruction_00\"+\[ \t\]+\[#;]+\[
> \t\]+external name" } }
> +// { dg-final { scan-assembler "\"two::c2::~c20\"+\[ \t\]+\[
Re: [wwwdocs] Update coding conventions for C++
On Fri, Jun 29, 2012 at 1:17 PM, Lawrence Crowl wrote: > Resend, as I replied to a message that didn't have the usual suspects > on the cc line. > > On 6/27/12, Lawrence Crowl wrote: >> ..., does anyone object to removing the permission to use C++ >> streams? > > Having heard no objection, I removed the permission. This is an area where I think we should not be too prescriptive. Clearly, the diagnostics machinery will be used for anything diagnostics -- so whether IOStreams are allowed or not would not change that. On the other hand, I feel we should defer to maintainers' discretion in specific areas whether people are implementing dumping or other I/O facilities not related to diagnostics, since as I you correctly pointed out, there is an added value of flexiibility and expressivity. In summary: Instead of blanket ban, I would suggest that uses for C++ I/O streams be reserved for non-diagnostics purposes and left at the discretion of maintainers. > > The following patch is the current state of the changes. Since the > discussion appears to have died down, can I commit this patch?
Re: [wwwdocs] Update coding conventions for C++
On 06/29/2012 02:17 PM, Lawrence Crowl wrote: +RTTI anddynamic_cast + + +Run-time type information (RTTI) is permitted +when certain non-default--enable-checking options are enabled, +so as to allow checkers to report dynamic types. +However, by default, RTTI is not permitted +and the compiler must build cleanly with-fno-rtti. + As discussed, I would say that RTTI is currently not permitted but could be added later. For the rationale, I would say that disabling RTTI saves some space for classes with virtual functions when it isn't used, but could be enabled if it would be useful in some part of the compiler. And then remove the rest of the rationale. Jason
Re: [ARM Patch 1/n] PR53447: optimizations of 64bit ALU operation with constant
On Fri, Jun 29, 2012 at 9:57 PM, Ramana Radhakrishnan
wrote:
>
> On 29 June 2012 12:23, Carrot Wei wrote:
> > Hi
> >
> > So the following is updated patch. Tested on qemu with arm/thumb modes
>
> Assuming this testing was with and without neon ? Because the patterns
> changed are different whether you use Neon or not.
>
Now the patch has been tested with all combination of arm/thumb
neon/non-neon modes.
> > without regression.
>
> Can you add some tests for all 4 cases ? See comments inline below for
> some changes ?
>
New test cases added.
> Ok with those changes if no regressions for above mentioned testing.
>
> > Index: config/arm/arm.md
> > ===
> > --- config/arm/arm.md (revision 187751)
> > +++ config/arm/arm.md (working copy)
> > @@ -574,7 +574,7 @@
> > [(parallel
> > [(set (match_operand:DI 0 "s_register_operand" "")
> > (plus:DI (match_operand:DI 1 "s_register_operand" "")
> > - (match_operand:DI 2 "s_register_operand" "")))
> > + (match_operand:DI 2 "arm_adddi_operand" "")))
> > (clobber (reg:CC CC_REGNUM))])]
> > "TARGET_EITHER"
> > "
> > @@ -609,10 +609,10 @@
> > [(set_attr "length" "4")]
> > )
> >
> > -(define_insn_and_split "*arm_adddi3"
> > - [(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
> > - (plus:DI (match_operand:DI 1 "s_register_operand" "%0, 0")
> > - (match_operand:DI 2 "s_register_operand" "r, 0")))
> > +(define_insn_and_split "arm_adddi3"
> > + [(set (match_operand:DI 0 "s_register_operand"
> > "=&r,&r,&r,&r,&r")
> > + (plus:DI (match_operand:DI 1 "s_register_operand" "%0, 0, r, 0, r")
> > + (match_operand:DI 2 "arm_adddi_operand" "r, 0, r, Dd,
> > Dd")))
> > (clobber (reg:CC CC_REGNUM))]
> > "TARGET_32BIT && !(TARGET_HARD_FLOAT && TARGET_MAVERICK) && !TARGET_NEON"
> > "#"
> > @@ -630,8 +630,17 @@
> > operands[0] = gen_lowpart (SImode, operands[0]);
> > operands[4] = gen_highpart (SImode, operands[1]);
> > operands[1] = gen_lowpart (SImode, operands[1]);
> > - operands[5] = gen_highpart (SImode, operands[2]);
> > - operands[2] = gen_lowpart (SImode, operands[2]);
> > + if (GET_CODE (operands[2]) == CONST_INT)
> > + {
> > + HOST_WIDE_INT v = INTVAL (operands[2]);
> > + operands[5] = GEN_INT (ARM_SIGN_EXTEND ((v >> 32) & 0x));
> > + operands[2] = GEN_INT (ARM_SIGN_EXTEND (v & 0x));
> > + }
> > + else
> > + {
> > + operands[5] = gen_highpart (SImode, operands[2]);
> > + operands[2] = gen_lowpart (SImode, operands[2]);
> > + }
>
> Instead
>
>
> operands[5] = gen_highpart_mode (SImode, DImode, operands[2]);
> operands[2] = gen_lowpart (SImode, operands[2]);
>
> So you don't need a check there.
>
A good method.
>
>
> > }"
> > [(set_attr "conds" "clob")
> > (set_attr "length" "8")]
> > @@ -980,12 +989,14 @@
> > )
> >
> > (define_insn "*addsi3_carryin_"
> > - [(set (match_operand:SI 0 "s_register_operand" "=r")
> > - (plus:SI (plus:SI (match_operand:SI 1 "s_register_operand" "%r")
> > - (match_operand:SI 2 "arm_rhs_operand" "rI"))
> > + [(set (match_operand:SI 0 "s_register_operand" "=r,r")
> > + (plus:SI (plus:SI (match_operand:SI 1 "s_register_operand" "%r,r")
> > + (match_operand:SI 2 "arm_not_operand" "rI,K"))
> > (LTUGEU:SI (reg: CC_REGNUM) (const_int 0]
> > "TARGET_32BIT"
> > - "adc%?\\t%0, %1, %2"
> > + "@
> > + adc%?\\t%0, %1, %2
> > + sbc%?\\t%0, %1, #%B2"
> > [(set_attr "conds" "use")]
> > )
>
> Any reason why you didn't consider making these changes to the
> *addsi3_carryin_alt2 pattern ?
>
It's simply because of my ignorance.
thanks
Carrot
The actually committed patch is as following
2012-07-01 Wei Guozhi
PR target/53447
* gcc.target/arm/pr53447-1.c: New testcase.
* gcc.target/arm/pr53447-2.c: New testcase.
* gcc.target/arm/pr53447-3.c: New testcase.
* gcc.target/arm/pr53447-4.c: New testcase.
2012-07-01 Wei Guozhi
PR target/53447
* config/arm/arm-protos.h (const_ok_for_dimode_op): New prototype.
* config/arm/arm.c (const_ok_for_dimode_op): New function.
* config/arm/constraints.md (Dd): New constraint.
* config/arm/predicates.md (arm_adddi_operand): New predicate.
* config/arm/arm.md (adddi3): Extend it to handle constants.
(arm_adddi3): Likewise.
(addsi3_carryin_): Extend it to handle sbc case.
(addsi3_carryin_alt2_): Likewise.
* config/arm/neon.md (adddi3_neon): Extend it to handle constants.
Index: testsuite/gcc.target/arm/pr53447-1.c
===
--- testsuite/gcc.target/arm/pr53447-1.c(revision 0)
+++ testsuite/gcc.target/arm/pr53447-1.c(revision 0)
@@ -0,0
[wwwdocs] Buildstat update for 4.7
Latest results for 4.7.x -tgc Testresults for 4.7.1: alphaev68-unknown-linux-gnu i386-pc-solaris2.8 (2) i686-pc-linux-gnu (2) powerpc-apple-darwin8.11.0 x86_64-unknown-linux-gnu --- buildstat.html 2012-06-15 20:00:05.615216445 +0200 +++ /tmp/buildstat.out 2012-07-01 20:56:20.979614188 +0200 @@ -31,6 +31,14 @@ +alphaev68-unknown-linux-gnu + +Test results: +http://gcc.gnu.org/ml/gcc-testresults/2012-06/msg01281.html";>4.7.1 + + + + hppa2.0w-hp-hpux11.11 Test results: @@ -58,6 +66,8 @@ i386-pc-solaris2.8 Test results: +http://gcc.gnu.org/ml/gcc-testresults/2012-06/msg02064.html";>4.7.1, +http://gcc.gnu.org/ml/gcc-testresults/2012-06/msg01781.html";>4.7.1, http://gcc.gnu.org/ml/gcc-testresults/2012-05/msg00527.html";>4.7.0, http://gcc.gnu.org/ml/gcc-testresults/2012-03/msg02998.html";>4.7.0, http://gcc.gnu.org/ml/gcc-testresults/2012-03/msg02619.html";>4.7.0 @@ -89,9 +99,19 @@ +i686-pc-linux-gnu + +Test results: +http://gcc.gnu.org/ml/gcc-testresults/2012-06/msg01316.html";>4.7.1, +http://gcc.gnu.org/ml/gcc-testresults/2012-06/msg01315.html";>4.7.1 + + + + powerpc-apple-darwin8.11.0 Test results: +http://gcc.gnu.org/ml/gcc-testresults/2012-06/msg01566.html";>4.7.1, http://gcc.gnu.org/ml/gcc-testresults/2012-03/msg02890.html";>4.7.0 @@ -142,6 +162,7 @@ x86_64-unknown-linux-gnu Test results: +http://gcc.gnu.org/ml/gcc-testresults/2012-06/msg01675.html";>4.7.1, http://gcc.gnu.org/ml/gcc-testresults/2012-03/msg02853.html";>4.7.0, http://gcc.gnu.org/ml/gcc-testresults/2012-03/msg02514.html";>4.7.0
Re: [patch] Move lowering of switches to bit tests to GIMPLE
On Sun, Jul 1, 2012 at 11:58 AM, Richard Guenther wrote: >> OK for trunk? > > This is ok. Grrr, I now get regressions on both powerpc64 and x86_64 (although both still bootstrap). I'm withdrawing this patch until I've sorted out these new problems. Ciao! Steven
[SH] PR 51244 - Eliminate redundant movt and tst insns.
Hello,
The attached patch is the same patch as posted in the PR.
It eliminates redundant movt and tst insns, which started to appear a
while ago.
Tested against rev 189081 with
make -k check RUNTESTFLAGS="--target_board=sh-sim
\{-m2/-ml,-m2/-mb,-m2a/-mb,-m2a-single/-mb,-m4/-ml,-m4/-mb,
-m4-single/-ml,-m4-single/-mb,-m4a-single/-ml,-m4a-single/-mb}"
and no new failures.
Cheers,
Oleg
ChangeLog:
PR target/51244
* config/sh/predicates.md (t_reg_operand, negt_reg_operand): New
predicates.
* config/sh/sh-protos.h (get_t_reg_rtx): New prototype.
* config/sh/sh.c (get_t_reg_rtx): New function. Use it when
invoking gen_branch_true and gen_branch_false.
* config/sh/sh.md: Use get_t_reg_rtx when invoking
gen_branch_true and gen_branch_false.
(branch_true, branch_false): Use t_reg_operand predicate.
(*branch_true, *branch_false): Delete.
(movt): Use t_reg_operand predicate.
(*negnegt): Use negt_reg_operand predicate and fold little and
big endian variants.
(*movtt): Use t_reg_operand and fold little and big endian
variants.
(*movt_qi): Delete.
testsuite/ChangeLog:
PR target/51244
* gcc.target/sh/pr51244-1.c: Check that movt insn is not
generated.
Index: gcc/testsuite/gcc.target/sh/pr51244-1.c
===
--- gcc/testsuite/gcc.target/sh/pr51244-1.c (revision 189081)
+++ gcc/testsuite/gcc.target/sh/pr51244-1.c (working copy)
@@ -4,7 +4,7 @@
/* { dg-do compile { target "sh*-*-*" } } */
/* { dg-options "-O1 -mbranch-cost=2" } */
/* { dg-skip-if "" { "sh*-*-*" } { "-m5*"} { "" } } */
-/* { dg-final { scan-assembler-not "tst|negc|extu" } } */
+/* { dg-final { scan-assembler-not "movt|tst|negc|extu" } } */
int
testfunc_00 (int a, int b, int c, int d)
Index: gcc/config/sh/predicates.md
===
--- gcc/config/sh/predicates.md (revision 189081)
+++ gcc/config/sh/predicates.md (working copy)
@@ -898,3 +898,42 @@
(match_test "mode != HImode")
(match_test "TARGET_SH4A_ARCH"
+;; A predicate describing the T bit register in any form.
+(define_predicate "t_reg_operand"
+ (match_code "reg,subreg,sign_extend,zero_extend")
+{
+ switch (GET_CODE (op))
+{
+ case REG:
+ return REGNO (op) == T_REG;
+
+ case SUBREG:
+ return REGNO (SUBREG_REG (op)) == T_REG;
+
+ case ZERO_EXTEND:
+ case SIGN_EXTEND:
+ return GET_CODE (XEXP (op, 0)) == SUBREG
+ && REGNO (SUBREG_REG (XEXP (op, 0))) == T_REG;
+
+ default:
+ return 0;
+}
+})
+
+;; A predicate describing a negated T bit register.
+(define_predicate "negt_reg_operand"
+ (match_code "subreg,xor")
+{
+ switch (GET_CODE (op))
+{
+ case XOR:
+ return t_reg_operand (XEXP (op, 0), GET_MODE (XEXP (op, 0)))
+ && satisfies_constraint_M (XEXP (op, 1));
+
+ case SUBREG:
+ return negt_reg_operand (XEXP (op, 0), GET_MODE (XEXP (op, 0)));
+
+ default:
+ return 0;
+}
+})
Index: gcc/config/sh/sh-protos.h
===
--- gcc/config/sh/sh-protos.h (revision 189081)
+++ gcc/config/sh/sh-protos.h (working copy)
@@ -109,6 +109,7 @@
#endif /* RTX_CODE */
extern const char *output_jump_label_table (void);
+extern rtx get_t_reg_rtx (void);
extern rtx get_fpscr_rtx (void);
extern int sh_media_register_for_return (void);
extern void sh_expand_prologue (void);
Index: gcc/config/sh/sh.c
===
--- gcc/config/sh/sh.c (revision 189081)
+++ gcc/config/sh/sh.c (working copy)
@@ -1874,7 +1874,7 @@
void
expand_cbranchsi4 (rtx *operands, enum rtx_code comparison, int probability)
{
- rtx (*branch_expander) (rtx) = gen_branch_true;
+ rtx (*branch_expander) (rtx, rtx) = gen_branch_true;
rtx jump;
comparison = prepare_cbranch_operands (operands, SImode, comparison);
@@ -1888,7 +1888,7 @@
emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, T_REG),
gen_rtx_fmt_ee (comparison, SImode,
operands[1], operands[2])));
- jump = emit_jump_insn (branch_expander (operands[3]));
+ jump = emit_jump_insn (branch_expander (operands[3], get_t_reg_rtx ()));
if (probability >= 0)
add_reg_note (jump, REG_BR_PROB, GEN_INT (probability));
@@ -1941,7 +1941,7 @@
if (TARGET_CMPEQDI_T)
{
emit_insn (gen_cmpeqdi_t (operands[1], operands[2]));
- emit_jump_insn (gen_branch_true (operands[3]));
+ emit_jump_insn (gen_branch_true (operands[3], get_t_reg_rtx ()));
return true;
}
msw_skip = NE;
@@ -1969,7 +1969,7 @@
if (TARGET_CMPEQDI_T)
{
emit_insn (gen_cmpeqdi_t (operands[1], operands[2]));
- emit_jump_insn (gen_branch_false (operands[3]));
+ emit_jump_insn (gen_branch_false (operands[3], get_t_reg_rtx
Re: [SH] PR 51244 - Eliminate redundant movt and tst insns.
Oleg Endo wrote: > The attached patch is the same patch as posted in the PR. > It eliminates redundant movt and tst insns, which started to appear a > while ago. This patch is OK. Regards, kaz
