Re: PowerPC prologue and epilogue 6

[Alan Modra]

On Thu, May 31, 2012 at 10:41:26AM +0930, Alan Modra wrote:
> Looks like it is one I introduced.  gcc-4.6 uses r12 to save altivec
> regs, my new code tries to use r11.  Will fix.

Please try out this patch on Darwin.  Bootstrapped and regression
tested powerpc-linux.

gcc/
* config/rs6000/rs6000.c (ptr_regno_for_savres): Comment.
(rs6000_emit_prologue): Ensure register used for inline saves
of vector regs is not the static chain register.  Revise comment.
gcc/testsuite/
* gcc.target/powerpc/savres.c: Add -static to dg-options.
Check static chain in nested funcs.

Index: gcc/config/rs6000/rs6000.c
===
--- gcc/config/rs6000/rs6000.c  (revision 187999)
+++ gcc/config/rs6000/rs6000.c  (working copy)
@@ -19108,6 +19161,9 @@ rs6000_emit_stack_reset (rs6000_stack_t *info,
   return NULL_RTX;
 }
 
+/* Return the register number used as a pointer by out-of-line
+   save/restore functions.  */
+
 static inline unsigned
 ptr_regno_for_savres (int sel)
 {
@@ -19845,6 +19901,9 @@ rs6000_emit_prologue (void)
  int sel = SAVRES_SAVE | SAVRES_VR;
  unsigned ptr_regno = ptr_regno_for_savres (sel);
 
+ if (using_static_chain_p
+ && ptr_regno == STATIC_CHAIN_REGNUM)
+   ptr_regno = 12;
  if (REGNO (frame_reg_rtx) != ptr_regno)
START_USE (ptr_regno);
  ptr_reg = gen_rtx_REG (Pmode, ptr_regno);
@@ -19953,9 +20012,9 @@ rs6000_emit_prologue (void)
   int offset;
   int save_regno;
 
-  /* Get VRSAVE onto a GPR.  Note that ABI_V4 might be using r12
-as frame_reg_rtx and r11 as the static chain pointer for
-nested functions.  */
+  /* Get VRSAVE onto a GPR.  Note that ABI_V4 and ABI_DARWIN might
+be using r12 as frame_reg_rtx and r11 as the static chain
+pointer for nested functions.  */
   save_regno = 12;
   if (DEFAULT_ABI == ABI_AIX && !using_static_chain_p)
save_regno = 11;
Index: gcc/testsuite/gcc.target/powerpc/savres.c
===
--- gcc/testsuite/gcc.target/powerpc/savres.c   (revision 187999)
+++ gcc/testsuite/gcc.target/powerpc/savres.c   (working copy)
@@ -1,5 +1,5 @@
 /* { dg-do run } */
-/* { dg-options "-fno-inline -fomit-frame-pointer" } */
+/* { dg-options "-fno-inline -fomit-frame-pointer -static" } */
 
 /* -fno-inline -maltivec -m32/-m64 -mmultiple/no-multiple -Os/-O2.  */
 #ifndef NO_BODY
@@ -73,6 +73,7 @@ __attribute__ ((vector_size (16))) int val31 = {-3
 
 #else /* NO_BODY */
 /* For looking at prologue and epilogue code without distractions.  */
+#define abort()
 #define TRASH_ALL_CR
 #define TRASH_ALL_VR
 #define TRASH_ALL_FPR
@@ -458,7 +459,7 @@ void s_0 (void)
 void wb_all (void)
 {
   char b[10];
-  void nb_all (void)
+  char *nb_all (void)
   {
 char a[33000];
 TRASH_ALL_CR;
@@ -470,14 +471,16 @@ void wb_all (void)
 USE_ALL_FPR;
 USE_ALL_GPR;
 __asm __volatile ("#%0 %1" : "=m" (a), "=m" (b) : : "cr2", "cr3", "cr4", 
"v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", 
"v31", "fr14", "fr15", "fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", 
"fr23", "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31", "r14", 
"r15", "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", "r24", "r25", 
"r26", "r27", "r28", "r29", "r30", "r31");
+return b;
   }
-  nb_all();
+  if (nb_all() != b)
+abort ();
 }
 
 void wb_cvfr (void)
 {
   char b[10];
-  void nb_cvfr (void)
+  char *nb_cvfr (void)
   {
 char a[33000];
 TRASH_SOME_CR;
@@ -489,14 +492,16 @@ void wb_cvfr (void)
 USE_SOME_FPR;
 USE_SOME_GPR;
 __asm __volatile ("#%0 %1" : "=m" (a), "=m" (b) : : "cr2", "v26", "v27", 
"v31", "fr28", "fr31", "r30", "r31");
+return b;
   }
-  nb_cvfr ();
+  if (nb_cvfr () != b)
+abort ();
 }
 
 void wb_vfr (void)
 {
   char b[10];
-  void nb_vfr (void)
+  char *nb_vfr (void)
   {
 char a[33000];
 TRASH_SOME_VR;
@@ -506,14 +511,16 @@ void wb_vfr (void)
 USE_SOME_FPR;
 USE_SOME_GPR;
 __asm __volatile ("#%0 %1" : "=m" (a), "=m" (b) : : "v26", "v27", "v31", 
"fr28", "fr31", "r30", "r31");
+return b;
   }
-  nb_vfr ();
+  if (nb_vfr () != b)
+abort ();
 }
 
 void wb_cvf (void)
 {
   char b[10];
-  void nb_cvf (void)
+  char *nb_cvf (void)
   {
 char a[33000];
 TRASH_SOME_CR;
@@ -523,14 +530,16 @@ void wb_cvf (void)
 USE_SOME_VR;
 USE_SOME_FPR;
 __asm __volatile ("#%0 %1" : "=m" (a), "=m" (b) : : "cr2", "v26", "v27", 
"v31", "fr28", "fr31");
+return b;
   }
-  nb_cvf ();
+  if (nb_cvf () != b)
+abort ();
 }
 
 void wb_vf (void)
 {
   char b[10];
-  void nb_vf (void)
+  char *nb_vf (void)
   {
 char a[33000];
 TRASH_SOME_VR;
@@ -538,15 +547,17 @@ void wb_vf (void)
 USE_SOME_VR;
 USE_SOME_FPR;
 __asm __volatile ("#%0 %1" : "=m" (a), "=m" (b) : : "v26", "v27", "v31", 
"fr28", 

Re: [patch] Robustify get_ref_base_and_extent and friend

[Richard Guenther]

On Wed, May 30, 2012 at 7:14 PM, Eric Botcazou  wrote:
> Hi,
>
> we're having issues with get_ref_base_and_extent overflowing the offset and
> thus returning bogus big negative values on 32-bit hosts.  The attached patch
> converts it to double ints like get_inner_reference.  It also contains a small
> fix for build_user_friendly_ref_for_offset that can stop if a field has again
> too big an offset.
>
> Tested on x86_64-suse-linux and i586-suse-linux, OK for mainline?

Heh, I think I have a similar patch for the get_ref_base_and_extent issue
in my dev tree for almost three years ...

Ok!

Thanks,
Richard.

>
> 2012-05-30  Eric Botcazou  
>
>        * tree-dfa.c (get_ref_base_and_extent): Compute the offset using
>        double ints throughout.
>        * tree-sra.c (build_user_friendly_ref_for_offset) :
>        Check that the position of the field is representable as an integer.
>
>
> --
> Eric Botcazou

Re: [Patch, testsuite] fix failure in test gcc.dg/vect/slp-perm-8.c

[Richard Guenther]

On Wed, May 30, 2012 at 7:46 PM, Greta Yorsh  wrote:
> I'm attaching an updated version of the patch, addressing the comments from
> http://gcc.gnu.org/ml/gcc-patches/2012-04/msg01615.html
>
> This patch adds arm32 to targets that support vect_char_mult. In addition,
> the test is updated to prevent vectorization of the initialization loop. The
> expected number of vectorized loops is adjusted accordingly.
>
> No regression with check-gcc on qemu for arm-none-eabi cortex-a9 neon softfp
> arm/thumb.
>
> OK for trunk?

Ok.

Thanks,
Richard.

> Thanks,
> Greta
>
> ChangeLog
>
> gcc/testsuite
>
> 2012-05-30  Greta Yorsh  
>
>        * gcc.dg/vect/slp-perm-8.c (main): Prevent vectorization
>        of the initialization loop.
>        (dg-final): Adjust the expected number of vectorized loops
>        depending on vect_char_mult target selector.
>        * lib/target-supports.exp (check_effective_target_vect_char_mult):
> Add
>          arm32 to targets
>
>
>> -Original Message-
>> From: Richard Earnshaw [mailto:rearn...@arm.com]
>> Sent: 25 April 2012 17:30
>> To: Richard Guenther
>> Cc: Greta Yorsh; gcc-patches@gcc.gnu.org; mikest...@comcast.net;
>> r...@cebitec.uni-bielefeld.de
>> Subject: Re: [Patch, testsuite] fix failure in test gcc.dg/vect/slp-
>> perm-8.c
>>
>> On 25/04/12 15:31, Richard Guenther wrote:
>> > On Wed, Apr 25, 2012 at 4:27 PM, Greta Yorsh 
>> wrote:
>> >> Richard Guenther wrote:
>> >>> On Wed, Apr 25, 2012 at 3:34 PM, Greta Yorsh 
>> >>> wrote:
>>  Richard Guenther wrote:
>> > On Wed, Apr 25, 2012 at 1:51 PM, Greta Yorsh
>> 
>> > wrote:
>> >> The test gcc.dg/vect/slp-perm-8.c fails on arm-none-eabi with
>> neon
>> > enabled:
>> >> FAIL: gcc.dg/vect/slp-perm-8.c scan-tree-dump-times vect
>> >>> "vectorized
>> > 1
>> >> loops" 2
>> >>
>> >> The test expects 2 loops to be vectorized, while gcc
>> successfully
>> > vectorizes
>> >> 3 loops in this test using neon on arm. This patch adjusts the
>> > expected
>> >> output. Fixed test passes on qemu for arm and powerpc.
>> >>
>> >> OK for trunk?
>> >
>> > I think the proper fix is to instead of
>> >
>> >   for (i = 0; i < N; i++)
>> >     {
>> >       input[i] = i;
>> >       output[i] = 0;
>> >       if (input[i] > 256)
>> >         abort ();
>> >     }
>> >
>> > use
>> >
>> >   for (i = 0; i < N; i++)
>> >     {
>> >       input[i] = i;
>> >       output[i] = 0;
>> >       __asm__ volatile ("");
>> >     }
>> >
>> > to prevent vectorization of initialization loops.
>> 
>>  Actually, it looks like both arm and powerpc vectorize this
>> >>> initialization loop (line 31), because the control flow is hoisted
>> >>> outside the loop by previous optimizations. In addition, arm with
>> neon
>> >>> vectorizes the second loop (line 39), but powerpc does not:
>> 
>>  39: not vectorized: relevant stmt not supported: D.2163_8 = i_40 *
>> 9;
>> 
>>  If this is the expected behaviour for powerpc, then the patch I
>> >>> proposed is still needed to fix the test failure on arm. Also,
>> there
>> >>> would be no need to disable vectorization of the initialization
>> loop,
>> >>> right?
>> >>>
>> >>> Ah, I thought that was what changed.  Btw, the if () abort () tries
>> to
>> >>> disable
>> >>> vectorization but does not succeed in doing so.
>> >>>
>> >>> Richard.
>> >>
>> >> Here is an updated patch. It prevents vectorization of the
>> initialization
>> >> loop, as Richard suggested, and updates the expected number of
>> vectorized
>> >> loops accordingly. This patch assumes that the second loop in main
>> (line 39)
>> >> should only be vectorized on arm with neon.  The test passes for arm
>> and
>> >> powerpc.
>> >>
>> >> OK for trunk?
>> >
>> > If arm cannot handle 9 * i then the approrpiate condition would be
>> > vect_int_mult, not arm_neon_ok.
>> >
>>
>> The issue is that arm has (well, should be marked has having)
>> vect_char_mult.  The difference in count of vectorized loops is based
>> on
>> that.
>>
>> R.
>>
>> > Ok with that change.
>> >
>> > Richard.
>> >
>> >> Thank you,
>> >> Greta
>> >>
>> >> gcc/testsuite/ChangeLog
>> >>
>> >> 2012-04-25  Greta Yorsh  
>> >>
>> >>        * gcc.dg/vect/slp-perm-8.c (main): Prevent
>> >>        vectorization of initialization loop.
>> >>        (dg-final): Adjust the expected number of
>> >>        vectorized loops.
>> >>
>> >>
>> >>
>> >>
>> >
>>

Re: [patch] Fix many Makefile dependencies, round 2

[Richard Guenther]

On Wed, May 30, 2012 at 7:53 PM, Steven Bosscher  wrote:
> Hello,
>
> Here is the next round of fixes.  I think I need one or two more
> iterations before everything is fixed, but this already improves
> things a bit again.
>
> While working on this, I noticed that cfglayout.h was being included
> by many files, for symbols that are not specific to cfglayout. I'll
> fix that in another patch later this week.
>
> For this one: Bootstrapped on powerpc64-unknown-linux-gnu. OK for trunk?

Ok.

Thanks,
Richard.

> Ciao!
> Steven

Re: [cxx-conversion] Change check functions from templates to overloads. (issue6256075)

[Richard Guenther]

On Thu, May 31, 2012 at 5:49 AM, Lawrence Crowl  wrote:
> Change the check functions from templates to overloads.
>
> Add "set unwindonsignal on" to gdbinit.in to gracefully handle aborts
> in functions used from gdb.
>
> Tested on x86-64.

Thanks - that looks much better to me now.

Richard.

>
> Index: gcc/ChangeLog.cxx-conversion
>
> 2012-05-30   Lawrence Crowl  
>
>        * tree.h (tree_check): Change from template to const overload.
>        (tree_not_check): Likewise.
>        (tree_check2): Likewise.
>        (tree_not_check2): Likewise.
>        (tree_check3): Likewise.
>        (tree_not_check3): Likewise.
>        (tree_check4): Likewise.
>        (tree_not_check4): Likewise.
>        (tree_check5): Likewise.
>        (tree_not_check5): Likewise.
>        (contains_struct_check): Likewise.
>        (tree_class_check): Likewise.
>        (tree_range_check): Likewise.
>        (omp_clause_subcode_check): Likewise.
>        (omp_clause_range_check): Likewise.
>        (expr_check): Likewise.
>        (non_type_check): Likewise.
>        (tree_vec_elt_check): Likewise.
>        (omp_clause_elt_check): Likewise.
>        (tree_operand_check): Likewise.
>        (tree_operand_check_code): Likewise.
>        (tree_operand_length): Merge duplicate copy.
>        * gdbinit.in (set unwindonsignal on): New.
>
>
> Index: gcc/tree.h
> ===
> --- gcc/tree.h  (revision 187989)
> +++ gcc/tree.h  (working copy)
> @@ -3598,18 +3598,17 @@ union GTY ((ptr_alias (union lang_tree_n
>  };
>
>  #if defined ENABLE_TREE_CHECKING && (GCC_VERSION >= 2007)
> -template 
> -inline Tree
> -tree_check (Tree __t, const char *__f, int __l, const char *__g, tree_code 
> __c)
> +
> +inline tree
> +tree_check (tree __t, const char *__f, int __l, const char *__g, tree_code 
> __c)
>  {
>   if (TREE_CODE (__t) != __c)
>     tree_check_failed (__t, __f, __l, __g, __c, 0);
>   return __t;
>  }
>
> -template 
> -inline Tree
> -tree_not_check (Tree __t, const char *__f, int __l, const char *__g,
> +inline tree
> +tree_not_check (tree __t, const char *__f, int __l, const char *__g,
>                 enum tree_code __c)
>  {
>   if (TREE_CODE (__t) == __c)
> @@ -3617,9 +3616,8 @@ tree_not_check (Tree __t, const char *__
>   return __t;
>  }
>
> -template 
> -inline Tree
> -tree_check2 (Tree __t, const char *__f, int __l, const char *__g,
> +inline tree
> +tree_check2 (tree __t, const char *__f, int __l, const char *__g,
>              enum tree_code __c1, enum tree_code __c2)
>  {
>   if (TREE_CODE (__t) != __c1
> @@ -3628,9 +3626,8 @@ tree_check2 (Tree __t, const char *__f,
>   return __t;
>  }
>
> -template 
> -inline Tree
> -tree_not_check2 (Tree __t, const char *__f, int __l, const char *__g,
> +inline tree
> +tree_not_check2 (tree __t, const char *__f, int __l, const char *__g,
>                  enum tree_code __c1, enum tree_code __c2)
>  {
>   if (TREE_CODE (__t) == __c1
> @@ -3639,9 +3636,8 @@ tree_not_check2 (Tree __t, const char *_
>   return __t;
>  }
>
> -template 
> -inline Tree
> -tree_check3 (Tree __t, const char *__f, int __l, const char *__g,
> +inline tree
> +tree_check3 (tree __t, const char *__f, int __l, const char *__g,
>              enum tree_code __c1, enum tree_code __c2, enum tree_code __c3)
>  {
>   if (TREE_CODE (__t) != __c1
> @@ -3651,9 +3647,8 @@ tree_check3 (Tree __t, const char *__f,
>   return __t;
>  }
>
> -template 
> -inline Tree
> -tree_not_check3 (Tree __t, const char *__f, int __l, const char *__g,
> +inline tree
> +tree_not_check3 (tree __t, const char *__f, int __l, const char *__g,
>                  enum tree_code __c1, enum tree_code __c2, enum tree_code 
> __c3)
>  {
>   if (TREE_CODE (__t) == __c1
> @@ -3663,9 +3658,8 @@ tree_not_check3 (Tree __t, const char *_
>   return __t;
>  }
>
> -template 
> -inline Tree
> -tree_check4 (Tree __t, const char *__f, int __l, const char *__g,
> +inline tree
> +tree_check4 (tree __t, const char *__f, int __l, const char *__g,
>              enum tree_code __c1, enum tree_code __c2, enum tree_code __c3,
>              enum tree_code __c4)
>  {
> @@ -3677,9 +3671,8 @@ tree_check4 (Tree __t, const char *__f,
>   return __t;
>  }
>
> -template 
> -inline Tree
> -tree_not_check4 (Tree __t, const char *__f, int __l, const char *__g,
> +inline tree
> +tree_not_check4 (tree __t, const char *__f, int __l, const char *__g,
>                  enum tree_code __c1, enum tree_code __c2, enum tree_code 
> __c3,
>                  enum tree_code __c4)
>  {
> @@ -3691,9 +3684,8 @@ tree_not_check4 (Tree __t, const char *_
>   return __t;
>  }
>
> -template 
> -inline Tree
> -tree_check5 (Tree __t, const char *__f, int __l, const char *__g,
> +inline tree
> +tree_check5 (tree __t, const char *__f, int __l, const char *__g,
>              enum tree_code __c1, enum tree_code __c2, enum tree_code __c3,
>              enum tree_code __c4, enum tree_code __c5)
>  {
> @@ -3706,9 +3698,8 @@ tree_check5 (Tree __t, const c

[Patch, Fortran] PR53521 - Fix size == 0 handling with reallocate

[Tobias Burnus]

Dear all,

gfortran was producing the following code:

  res = realloc (mem, size)
  if (size == 0)
res = NULL;
  ...
  if (res != 0)
free (res)

The problem is that "realloc (..., 0)" does not have to produce a NULL 
pointer as result.



While in "valgrind" one only gets the warning that "0 bytes in  
blocks" where not freed, looking at "top", one sees an excessive use of 
memory.


That seems to cause crashes in CP2K. At least the valgrind issue is a 
GCC 4.3 to 4.8 regression.



Without the patch, gfortran produces:

  D.1888 = (integer(kind=4)[0] * restrict) __builtin_realloc ((void 
*) atmp.0.data, D.1887);

  if (D.1888 == 0B && D.1887 != 0)
{
  _gfortran_os_error (&"Allocation would exceed memory 
limit"[1]{lb: 1 sz: 1});

}
  if (D.1887 == 0)
{
  D.1888 = 0B;
}
  atmp.0.data = (void * restrict) D.1888;



I see two possibilities:


1) FIRST approach: manual freeing/NULL setting; that's the closed what 
is currently done. (Note: It calls free unconditionally; "free(0)" is 
optimized away by the middle end.
(Note: That requires an update of the "free" count in 
gfortran.dg/allocatable_function_4.f90)


  if (D.1887 == 0)
{
  __builtin_free ((void *) atmp.0.data);
  D.1888 = 0B;
}
  else
{
  D.1888 = (integer(kind=4)[0] * restrict) __builtin_realloc 
((void *) atmp.0.data, D.1887);

  if (D.1888 == 0B && D.1887 != 0)
{
  _gfortran_os_error (&"Allocation would exceed memory 
limit"[1]{lb: 1 sz: 1});

}
}
  atmp.0.data = (void * restrict) D.1888;



2) SECOND approach: Simply removing the NULL setting and just using the 
result which realloc returns; if not NULL, the free() will properly 
handle it.


  D.1888 = (integer(kind=4)[0] * restrict) __builtin_realloc ((void 
*) atmp.0.data, D.1887);

  if (D.1888 == 0B && D.1887 != 0)
{
  _gfortran_os_error (&"Allocation would exceed memory 
limit"[1]{lb: 1 sz: 1});

}
  atmp.0.data = (void * restrict) D.1888;



Both patches have been tested with Joost's example and the test suite.
Which version do you prefer? OK for the trunk?

I like the second version more. (And I would even consider to get rid of 
the os_error.)


Tobias
2012-05-31  Tobias Burnus  

	PR fortran/53521
	* trans.c (gfc_deallocate_scalar_with_status): Properly
	handle the case size == 0.

diff --git a/gcc/fortran/trans.c b/gcc/fortran/trans.c
index 5d6e6ef..d53112f 100644
--- a/gcc/fortran/trans.c
+++ b/gcc/fortran/trans.c
@@ -1126,20 +1126,24 @@ gfc_deallocate_scalar_with_status (tree pointer, tree status, bool can_fail,
 void *
 internal_realloc (void *mem, size_t size)
 {
+  if (size == 0)
+{
+  free (mem);
+  return NULL;
+}
+
   res = realloc (mem, size);
   if (!res && size != 0)
 _gfortran_os_error ("Allocation would exceed memory limit");
 
-  if (size == 0)
-return NULL;
-
   return res;
 }  */
 tree
 gfc_call_realloc (stmtblock_t * block, tree mem, tree size)
 {
-  tree msg, res, nonzero, zero, null_result, tmp;
+  tree msg, res, cond, null_result, tmp;
   tree type = TREE_TYPE (mem);
+  stmtblock_t nonzero, zero;
 
   size = gfc_evaluate_now (size, block);
 
@@ -1149,17 +1153,20 @@ gfc_call_realloc (stmtblock_t * block, tree mem, tree size)
   /* Create a variable to hold the result.  */
   res = gfc_create_var (type, NULL);
 
+  gfc_init_block (&nonzero);
+  gfc_init_block (&zero);
+
   /* Call realloc and check the result.  */
   tmp = build_call_expr_loc (input_location,
 			 builtin_decl_explicit (BUILT_IN_REALLOC), 2,
 			 fold_convert (pvoid_type_node, mem), size);
-  gfc_add_modify (block, res, fold_convert (type, tmp));
+  gfc_add_modify (&nonzero, res, fold_convert (type, tmp));
   null_result = fold_build2_loc (input_location, EQ_EXPR, boolean_type_node,
  res, build_int_cst (pvoid_type_node, 0));
-  nonzero = fold_build2_loc (input_location, NE_EXPR, boolean_type_node, size,
+  cond = fold_build2_loc (input_location, NE_EXPR, boolean_type_node, size,
 			 build_int_cst (size_type_node, 0));
   null_result = fold_build2_loc (input_location, TRUTH_AND_EXPR, boolean_type_node,
- null_result, nonzero);
+ null_result, cond);
   msg = gfc_build_addr_expr (pchar_type_node, gfc_build_localized_cstring_const
 			 ("Allocation would exceed memory limit"));
   tmp = fold_build3_loc (input_location, COND_EXPR, void_type_node,
@@ -1167,15 +1174,22 @@ gfc_call_realloc (stmtblock_t * block, tree mem, tree size)
 			 build_

Committed, CRIS: fix assembling for other ISA variant

[Hans-Peter Nilsson]

If you specified another ISA variant with e.g. -march=, that
option got through to the compiler proper and the assembler only
if it was -march=v32.  Now fixed, tested crisv32-elf and cris-elf.

gcc:
* config/cris/cris.h (CC1_SPEC): Pass through all -march=
and -mcpu= options.
(ASM_SPEC): Ditto, not just -march=v32, but translate non-v10,
non-v32 into --march=v0_v10.

gcc/testsuite:
* gcc.target/cris/asm-v8.S, gcc.target/cris/asm-v10.S,
gcc.target/cris/asm-other.S, gcc.target/cris/inasm-v8.c,
gcc.target/cris/inasm-v10.c, gcc.target/cris/inasm-other.c:
New tests.

--- gcc/config/cris/cris.h  Tue May 29 04:13:08 2012
+++ gcc/config/cris/cris.h  Thu May 31 04:28:11 2012
@@ -156,11 +156,13 @@ extern int cris_cpu_version;
 " -D__CRIS_arch_tune=" CRIS_DEFAULT_TUNE "}"\
  CRIS_ARCH_CPP_DEFAULT
 
-/* Override previous definitions (linux.h).  */
+/* Override previous definitions (../linux.h).  */
 #undef CC1_SPEC
 #define CC1_SPEC \
  "%{metrax4:-march=v3}\
   %{metrax100:-march=v8}\
+  %{march=*:-march=%*}\
+  %{mcpu=*:-mcpu=%*}\
   %(cc1_subtarget)"
 
 /* For the cris-*-elf subtarget.  */
@@ -190,7 +192,9 @@ extern int cris_cpu_version;
  MAYBE_AS_NO_MUL_BUG_ABORT \
  "%(asm_subtarget)\
  %{march=*:%{mcpu=*:%edo not specify both -march=... and -mcpu=...}}\
- %{march=v32:--march=v32} %{mcpu=v32:--march=v32}"
+ %{march=v0|mcpu=v0|march=v3|mcpu=v3|march=v8|mcpu=v8:--march=v0_v10}\
+ %{march=v10|mcpu=v10:--march=v10}\
+ %{march=v32|mcpu=v32:--march=v32}"
 
 /* For the cris-*-elf subtarget.  */
 #define CRIS_ASM_SUBTARGET_SPEC \
--- /dev/null   Tue Oct 29 15:57:07 2002
+++ gcc/testsuite/gcc.target/cris/asm-other.S   Thu May 31 03:47:27 2012
@@ -0,0 +1,15 @@
+/* { dg-do assemble } */
+/* { dg-options "-DOTHER_ISA=0 -march=v0" { target crisv32-*-* } } */
+/* { dg-options "-DOTHER_ISA=32 -march=v32" { target cris-*-* } } */
+
+/* Make sure we can assemble for the "other" variant, with the twist
+   that the gcc option -march=v0 isn't valid for the assembler.  */
+.text
+#if OTHER_ISA == 32
+   addoq 42,$r1,$acr
+#else
+0:
+   move.d [$r2=$r0+42],$r1
+   bwf 0b
+   nop
+#endif
--- /dev/null   Tue Oct 29 15:57:07 2002
+++ gcc/testsuite/gcc.target/cris/inasm-other.c Thu May 31 03:56:29 2012
@@ -0,0 +1,23 @@
+/* { dg-do assemble } */
+/* { dg-options "-DOTHER_ISA=0 -march=v0" { target crisv32-*-* } } */
+/* { dg-options "-DOTHER_ISA=32 -march=v32" { target cris-*-* } } */
+
+/* Make sure we can (generate code and) assemble for the "other"
+   variant, with the twist that the gcc option -march=v0 isn't
+   valid for the assembler.  We don't check that the generated code
+   is for the other variant; other tests cover that already, but they
+   don't *assemble* the result.  We can't trust the prologue and
+   epilogue to contain incompatible insns (they actually deliberately
+   don't, usually and it'd be brittle to tweak the function signature
+   to make it so), so we force some with inline asm.  */
+
+void f(void)
+{
+#if OTHER_ISA == 32
+  asm volatile ("addoq 42,$r11,$acr");
+#else
+  asm volatile ("0: move.d [$r12=$sp+42],$r10\n\t"
+   "bwf 0b\n\t"
+   "nop");
+#endif
+}
--- /dev/null   Tue Oct 29 15:57:07 2002
+++ gcc/testsuite/gcc.target/cris/inasm-v10.c   Thu May 31 04:22:03 2012
@@ -0,0 +1,6 @@
+/* { dg-do assemble } */
+/* { dg-options "-DOTHER_ISA=10 -march=v10" } */
+
+/* Check that -march=v10 is also recognized.  */
+
+#include "inasm-other.c"
--- /dev/null   Tue Oct 29 15:57:07 2002
+++ gcc/testsuite/gcc.target/cris/inasm-v8.cThu May 31 04:22:46 2012
@@ -0,0 +1,6 @@
+/* { dg-do assemble } */
+/* { dg-options "-DOTHER_ISA=8 -march=v8" } */
+
+/* Check that -march=v8 is also recognized.  */
+
+#include "inasm-other.c"
--- /dev/null   Tue Oct 29 15:57:07 2002
+++ gcc/testsuite/gcc.target/cris/asm-v10.S Thu May 31 04:22:03 2012
@@ -0,0 +1,6 @@
+/* { dg-do assemble } */
+/* { dg-options "-DOTHER_ISA=10 -march=v10" } */
+
+/* Check that -march=v10 is also recognized.  */
+
+#include "asm-other.S"
--- /dev/null   Tue Oct 29 15:57:07 2002
+++ gcc/testsuite/gcc.target/cris/asm-v8.S  Thu May 31 04:22:46 2012
@@ -0,0 +1,6 @@
+/* { dg-do assemble } */
+/* { dg-options "-DOTHER_ISA=8 -march=v8" } */
+
+/* Check that -march=v8 is also recognized.  */
+
+#include "asm-other.S"

brgds, H-P

Re: [Patch, Fortran] PR53521 - Fix size == 0 handling with reallocate

[Jakub Jelinek]

On Thu, May 31, 2012 at 11:28:20AM +0200, Tobias Burnus wrote:
> I see two possibilities:
> 
> 
> 1) FIRST approach: manual freeing/NULL setting; that's the closed
> what is currently done. (Note: It calls free unconditionally;
> "free(0)" is optimized away by the middle end.
> (Note: That requires an update of the "free" count in
> gfortran.dg/allocatable_function_4.f90)
> 
>   if (D.1887 == 0)
> {
>   __builtin_free ((void *) atmp.0.data);
>   D.1888 = 0B;
> }
>   else
> {
>   D.1888 = (integer(kind=4)[0] * restrict) __builtin_realloc
> ((void *) atmp.0.data, D.1887);
>   if (D.1888 == 0B && D.1887 != 0)

You wouldn't need to check D.1887 != 0 here, that check has been performed
earlier.

> 2) SECOND approach: Simply removing the NULL setting and just using
> the result which realloc returns; if not NULL, the free() will
> properly handle it.
> 
>   D.1888 = (integer(kind=4)[0] * restrict) __builtin_realloc
> ((void *) atmp.0.data, D.1887);
>   if (D.1888 == 0B && D.1887 != 0)
> {
>   _gfortran_os_error (&"Allocation would exceed memory
> limit"[1]{lb: 1 sz: 1});
> }
>   atmp.0.data = (void * restrict) D.1888;
> 

Yeah, POSIX says on realloc return value:
If size was equal to 0, either NULL or a pointer suitable to be passed to
free() is returned.  So, for POSIX compatible realloc implementation the
second approach should be fine.

> I like the second version more. (And I would even consider to get
> rid of the os_error.)

Without the os_error, you'd just crash silently on allocation failures?

Jakub

Re: [Patch,AVR]: Use tr instead of set to canonicalize line endings for cmp

[Georg-Johann Lay]

Richard Henderson wrote:

>> +# The avr-mmcu.texi we want to compare against / check into svn should
>> +# have unix-style line endings.  To make this work on MinGW, remove \r.
>> +# \r is not portable to Solaris tr, therefore we have a special case
>> +# for ASCII.  We use \r for other encodings like EBCDIC.
>>   s-avr-mmcu-texi: gen-avr-mmcu-texi$(build_exeext)
>> -$(RUN_GEN) ./$<  | sed -e 's:\r::g'>  avr-mmcu.texi
>> +$(RUN_GEN) ./$<  >  tmp-avr-mmcu.texi
>> +case `echo X|tr X '\101'` in \
>> +  A) tr -d '\015'<  tmp-avr-mmcu.texi>  tmp2-avr-mmcu.texi ;; \
>> +  *) tr -d '\r'<  tmp-avr-mmcu.texi>  tmp2-avr-mmcu.texi ;; \
>> +esac
> 
> Why not do this inside gen-avr-mmcu-texi.c instead?
> 
> Instead of writing to stdout, open the file to write, and open
> it in binary mode.  Seems much easier than fighting with conversion
> after the fact.

Here is an updated patch that prints to binary file.

Moreover, the rewritten gen-tool now sorts the MCUs alphabetically
and thus the texi output differs and must be regenerated.

However, this just solves 1/2 of the problem:
SVN identifies texi as text file and if checked out under, e.g.
Windows, SVN will adjust the line endings for Windows again.

If it's appropriate I would also set svn:mime-type to something
like application/foo but that seems bit odd.

Johann

* config/avr/gen-avr-mmcu-texi.c: Rewrite:
- Output to binary file instead of as to stdout.
- Take output file as command line parameter.
- Sort MCUs.
* config/avr/t-avr: Correct avr-mmcu.texi dependencies.
(gen-avr-mmcu-texi): Use libiberty.
(s-avr-mmcu-texi): Use new gen-avr-mmcu-texi interface.
* doc/avr-mmcu.texi: Regenerate.
Index: config/avr/gen-avr-mmcu-texi.c
===
--- config/avr/gen-avr-mmcu-texi.c	(revision 188005)
+++ config/avr/gen-avr-mmcu-texi.c	(working copy)
@@ -20,25 +20,62 @@
 
 #include "avr-devices.c"
 
-int main (void)
+static const char*
+mcu_name[sizeof avr_mcu_types / sizeof avr_mcu_types[0]];
+
+static int
+comparator (const void *va, const void *vb)
+{
+  const char* const *a = (const char* const*) va;
+  const char* const *b = (const char* const*) vb;
+
+  return strcmp (*a, *b);
+} 
+
+static void
+print_mcus (FILE *fout, size_t n_mcus)
+{
+  size_t i;
+
+  if (!n_mcus)
+return;
+
+  qsort (mcu_name, n_mcus, sizeof (char*), comparator);
+
+  fprintf (fout, "@*@var{mcu}@tie{}=");
+
+  for (i = 0; i < n_mcus; i++)
+fprintf (fout, " @code{%s}%s", mcu_name[i], i == n_mcus-1 ? ".\n\n" : ",");
+}
+
+int main (int argc, char *argv[])
 {
   enum avr_arch arch = 0;
-  unsigned i, first = 1;
+  FILE *fout;
+  size_t i, n_mcus = 0;
   const struct mcu_type_s *mcu;
 
-  printf ("@c Copyright (C) 2012 Free Software Foundation, Inc.\n");
-  printf ("@c This is part of the GCC manual.\n");
-  printf ("@c For copying conditions, see the file "
-  "gcc/doc/include/fdl.texi.\n\n");
-
-  printf ("@c This file is generated automatically using\n");
-  printf ("@c gcc/config/avr/gen-avr-mmcu-texi.c from:\n");
-  printf ("@cgcc/config/avr/avr-devices.c\n");
-  printf ("@cgcc/config/avr/avr-mcus.def\n\n");
+  if (argc != 2
+  /* Write the texi output as binary so that line endings are the same
+ so matter what host we are on.  This is used in cmp -s in t-avr.  */
+  || !(fout = fopen (argv[1], "wb")))
+{
+  fprintf (stderr, "\n%s: wrong usage\n", argv[0]);
+  return EXIT_FAILURE;
+}
 
-  printf ("@c Please do not edit manually.\n\n");
+  fprintf (fout,
+   "@c Copyright (C) 2012 Free Software Foundation, Inc.\n"
+   "@c This is part of the GCC manual.\n"
+   "@c For copying conditions, see the file "
+   "gcc/doc/include/fdl.texi.\n\n"
+   "@c This file is generated automatically using\n"
+   "@c gcc/config/avr/gen-avr-mmcu-texi.c from:\n"
+   "@cgcc/config/avr/avr-devices.c\n"
+   "@cgcc/config/avr/avr-mcus.def\n\n"
+   "@c Please do not edit manually.\n\n");
 
-  printf ("@table @code\n\n");
+  fprintf (fout, "@table @code\n\n");
 
   for (mcu = avr_mcu_types; mcu->name; mcu++)
 {
@@ -46,28 +83,25 @@ int main (void)
 {
   arch = mcu->arch;
 
+  /* Start a new architecture:  Flush the MCUs collected so far.  */
+
+  print_mcus (fout, n_mcus);
+  n_mcus = 0;
+
   for (i = 0; i < sizeof (avr_texinfo) / sizeof (*avr_texinfo); i++)
-{
-  if (arch == avr_texinfo[i].arch)
-{
-  if (mcu != avr_mcu_types)
-printf (".\n\n");
-  printf ("@item %s\n%s\n", mcu->name, avr_texinfo[i].texinfo);
-  printf ("@*@var{mcu}@tie{}=");
-  first = 1;
-  break;
-}
-}
+if (arch == av

[PATCH, GCC][AArch64] Use Enums for code models option selection

[Sofiane Naci]

Hi,

This patch re-factors code models option selection in the AArch64 port:

 . Renaming variables such as mem_model to cmodel, for better clarity.
 . Using the generic support for enumerated option arguments.
 . Fixing touched code layout and formatting issues.

Thanks
Sofiane

-

ChangeLog:

2012-05-31  Sofiane Naci 

[AArch64] Use Enums for code models option selection.

* config/aarch64/aarch64-elf-raw.h (AARCH64_DEFAULT_MEM_MODEL):
Delete.
* config/aarch64/aarch64-linux.h (AARCH64_DEFAULT_MEM_MODEL):
Delete.
* config/aarch64/aarch64-opts.h (enum aarch64_code_model): New.
* config/aarch64/aarch64-protos.h: Update comments.
* config/aarch64/aarch64.c: Update comments.
(aarch64_default_mem_model): Rename to aarch64_code_model.
(aarch64_expand_mov_immediate): Remove error message.
(aarch64_select_rtx_section): Remove assertion and update comment.
(aarch64_override_options): Move memory model initialization from
here.
(struct aarch64_mem_model): Delete.
(aarch64_memory_models[]): Delete.
(initialize_aarch64_memory_model): Rename to
initialize_aarch64_code_model
and update.
(aarch64_classify_symbol): Handle AARCH64_CMODEL_TINY and
AARCH64_CMODEL_TINY_PIC
* config/aarch64/aarch64.h
(enum aarch64_memory_model): Delete.
(aarch64_default_mem_model): Rename to aarch64_cmodel.
(HAS_LONG_COND_BRANCH): Update.
(HAS_LONG_UNCOND_BRANCH): Update.
* config/aarch64/aarch64.opt
(cmodel): New.
(mcmodel): Update.


aarch64-use-enums-for-cmodels.patch
Description: Binary data

Re: [Patch,AVR]: Use tr instead of set to canonicalize line endings for cmp

[Joerg Wunsch]

As Georg-Johann Lay wrote:

> If it's appropriate I would also set svn:mime-type to something
> like application/foo but that seems bit odd.

Rather set the svn:eol-style attribute to "LF" instead, I'd say.

But wait a moment, why not setting the svn:eol-style to "native", and
the generator utility to also use native line endings (fopen(...,
"w"))?  That way, Windows should be able to use CR-LF for both, Unix
just LF, and MacOS just CR.

-- 
cheers, J"org   .-.-.   --... ...--   -.. .  DL8DTL

http://www.sax.de/~joerg/NIC: JW11-RIPE
Never trust an operating system you don't have sources for. ;-)

[C++ Patch] PR 53524

[Paolo Carlini]

Hi,

when I fixed PR16603 (for 4.7.0) I didn't anticipate that we would warn 
more easily about mismatching enum types for user code using conditional 
expressions to define enumerators basing on other enumerators of the 
same open enum, like the testcase in this PR shows. Generally speaking, 
IMHO the warning is a bit pedantic, eg, the EDG front-end doesn't warn 
at all, thus it seems to me that a good thing to do, safe for 4.7.1 too, 
is giving the warning a unique name and moving it to -Wall.


Bootstrapped and tested x86_64-linux.

Thanks,
Paolo.


2012-05-31  Paolo Carlini  

PR c++/53524
* doc/invoke.texi (Wenum-mismatch): Document.

/cp
2012-05-31  Paolo Carlini  

PR c++/53524
* call.c (build_conditional_expr_1): Use OPT_Wenum_mismatch.

/c-family
2012-05-31  Paolo Carlini  

PR c++/53524
* c.opt (Wenum-mismatch): Add.

/testsuite
2012-05-31  Paolo Carlini  

PR c++/53524
* g++.dg/warn/Wenum-mismatch1.C: New.
* g++.dg/warn/Wenum-mismatch2.C: Likewise.
* g++.dg/warn/Wenum-mismatch3.C: Likewise.
* g++.old-deja/g++.other/cond5.C: Adjust.
Index: doc/invoke.texi
===
--- doc/invoke.texi (revision 188050)
+++ doc/invoke.texi (working copy)
@@ -198,8 +198,8 @@ in the following sections.
 -fno-default-inline  -fvisibility-inlines-hidden @gol
 -fvisibility-ms-compat @gol
 -Wabi  -Wconversion-null  -Wctor-dtor-privacy @gol
--Wdelete-non-virtual-dtor -Wliteral-suffix -Wnarrowing @gol
--Wnoexcept -Wnon-virtual-dtor  -Wreorder @gol
+-Wdelete-non-virtual-dtor  -Wenum-mismatch  -Wliteral-suffix @gol
+-Wnarrowing  -Wnoexcept  -Wnon-virtual-dtor  -Wreorder @gol
 -Weffc++  -Wstrict-null-sentinel @gol
 -Wno-non-template-friend  -Wold-style-cast @gol
 -Woverloaded-virtual  -Wno-pmf-conversions @gol
@@ -3084,6 +3084,7 @@ Options} and @ref{Objective-C and Objective-C++ Di
 -Wc++11-compat  @gol
 -Wchar-subscripts  @gol
 -Wenum-compare @r{(in C/Objc; this is on by default in C++)} @gol
+-Wenum-mismatch @r{(in C++)} @gol
 -Wimplicit-int @r{(C and Objective-C only)} @gol
 -Wimplicit-function-declaration @r{(C and Objective-C only)} @gol
 -Wcomment  @gol
@@ -4301,6 +4302,12 @@ Warn about a comparison between values of differen
 this warning is enabled by default.  In C this warning is enabled by
 @option{-Wall}.
 
+@item -Wenum-mismatch @r{(C++ and Objective-C++ only)}
+@opindex Wenum-mismatch
+@opindex Wno-enum-mismatch
+Warn about values of different enumerated types in conditional
+expressions.  This warning is enabled by @option{-Wall}.
+
 @item -Wjump-misses-init @r{(C, Objective-C only)}
 @opindex Wjump-misses-init
 @opindex Wno-jump-misses-init
Index: c-family/c.opt
===
--- c-family/c.opt  (revision 188053)
+++ c-family/c.opt  (working copy)
@@ -360,6 +360,10 @@ Wenum-compare
 C ObjC C++ ObjC++ Var(warn_enum_compare) Init(-1) Warning
 Warn about comparison of different enum types
 
+Wenum-mismatch
+C++ ObjC++ Var(warn_enum_mismatch) Warning LangEnabledBy(C++ ObjC++,Wall)
+Warn about enumeral mismatch in conditional expression
+
 Werror
 C ObjC C++ ObjC++
 ; Documented in common.opt
Index: testsuite/g++.old-deja/g++.other/cond5.C
===
--- testsuite/g++.old-deja/g++.other/cond5.C(revision 188050)
+++ testsuite/g++.old-deja/g++.other/cond5.C(working copy)
@@ -1,7 +1,7 @@
 // { dg-do assemble  }
-// { dg-options "-W -pedantic -ansi" }
+// { dg-options "-W -Wenum-mismatch -pedantic -ansi" }
 
-// Copyright (C) 1999, 2000 Free Software Foundation, Inc.
+// Copyright (C) 1999, 2000, 2012 Free Software Foundation, Inc.
 // Contributed by Nathan Sidwell 1 Sep 1999 
 // Derived from bug report from Gabriel Dos Reis
 // 
Index: testsuite/g++.dg/warn/Wenum-mismatch1.C
===
--- testsuite/g++.dg/warn/Wenum-mismatch1.C (revision 0)
+++ testsuite/g++.dg/warn/Wenum-mismatch1.C (revision 0)
@@ -0,0 +1,30 @@
+// PR c++/53524
+
+template < typename > struct PointerLikeTypeTraits {
+  enum { NumLowBitsAvailable };
+};
+
+class CodeGenInstruction;
+class CodeGenInstAlias;
+
+template < typename T>
+struct PointerIntPair {
+  enum { IntShift = T::NumLowBitsAvailable };
+};
+
+template < typename PT1, typename PT2 > struct PointerUnionUIntTraits {
+  enum {
+PT1BitsAv = PointerLikeTypeTraits < PT1 >::NumLowBitsAvailable,
+PT2BitsAv = PointerLikeTypeTraits < PT2 >::NumLowBitsAvailable,
+NumLowBitsAvailable = 0 ? PT1BitsAv : PT2BitsAv
+  };
+};
+
+template < typename PT1, typename PT2 > class PointerUnion {
+  typedef PointerIntPair < PointerUnionUIntTraits < PT1, PT2 > > ValTy;
+  ValTy Val;
+};
+
+struct ClassInfo {
+  PointerUnion < CodeGenInstruction *, CodeGenInstAlias * > DefRec;
+};
Index: testsuite/g++.dg/warn/Wenum-mismatch2.C
=

Re: [Patch,AVR]: Use tr instead of set to canonicalize line endings for cmp

[Georg-Johann Lay]

Joerg Wunsch wrote:
> As Georg-Johann Lay wrote:
> 
>> If it's appropriate I would also set svn:mime-type to something
>> like application/foo but that seems bit odd.
> 
> Rather set the svn:eol-style attribute to "LF" instead, I'd say.
> 
> But wait a moment, why not setting the svn:eol-style to "native", and
> the generator utility to also use native line endings (fopen(...,
> "w"))?  That way, Windows should be able to use CR-LF for both, Unix
> just LF, and MacOS just CR.

Thanks for pointing to eol-style. I didn't know that one.

So here is the next version of the patch, returning to printf again :-)

It also sets svn:eol-style to native; I actually don't know how the svn
server hooks are configured.

Ok to install?

Johann

* config/avr/t-avr: Correct avr-mmcu.texi dependencies.
(s-avr-mmcu-texi): Don't sed on gen-avr-mmcu-texi output.
* config/avr/gen-avr-mmcu-texi.c: Sort MCUs.
* doc/avr-mmcu.texi: Regenerate.



Index: config/avr/gen-avr-mmcu-texi.c
===
--- config/avr/gen-avr-mmcu-texi.c	(revision 188005)
+++ config/avr/gen-avr-mmcu-texi.c	(working copy)
@@ -20,10 +20,38 @@
 
 #include "avr-devices.c"
 
+static const char*
+mcu_name[sizeof avr_mcu_types / sizeof avr_mcu_types[0]];
+
+static int
+comparator (const void *va, const void *vb)
+{
+  const char* const *a = (const char* const*) va;
+  const char* const *b = (const char* const*) vb;
+
+  return strcmp (*a, *b);
+} 
+
+static void
+print_mcus (size_t n_mcus)
+{
+  size_t i;
+
+  if (!n_mcus)
+return;
+
+  qsort (mcu_name, n_mcus, sizeof (char*), comparator);
+
+  printf ("@*@var{mcu}@tie{}=");
+
+  for (i = 0; i < n_mcus; i++)
+printf (" @code{%s}%s", mcu_name[i], i == n_mcus-1 ? ".\n\n" : ",");
+}
+
 int main (void)
 {
   enum avr_arch arch = 0;
-  unsigned i, first = 1;
+  size_t i, n_mcus = 0;
   const struct mcu_type_s *mcu;
 
   printf ("@c Copyright (C) 2012 Free Software Foundation, Inc.\n");
@@ -46,27 +74,22 @@ int main (void)
 {
   arch = mcu->arch;
 
+  /* Start a new architecture:  Flush the MCUs collected so far.  */
+
+  print_mcus (n_mcus);
+  n_mcus = 0;
+
   for (i = 0; i < sizeof (avr_texinfo) / sizeof (*avr_texinfo); i++)
-{
-  if (arch == avr_texinfo[i].arch)
-{
-  if (mcu != avr_mcu_types)
-printf (".\n\n");
-  printf ("@item %s\n%s\n", mcu->name, avr_texinfo[i].texinfo);
-  printf ("@*@var{mcu}@tie{}=");
-  first = 1;
-  break;
-}
-}
+if (arch == avr_texinfo[i].arch)
+  printf ("@item %s\n%s\n", mcu->name, avr_texinfo[i].texinfo);
 }
   else if (arch == (enum avr_arch) mcu->arch)
 {
-  printf ("%s @code{%s}", first ? "" : ",", mcu->name);
-  first = 0;
+  mcu_name[n_mcus++] = mcu->name;
 }
 }
 
-  printf (".\n\n");
+  print_mcus (n_mcus);
   printf ("@end table\n");
 
   return EXIT_SUCCESS;
Index: config/avr/t-avr
===
--- config/avr/t-avr	(revision 188005)
+++ config/avr/t-avr	(working copy)
@@ -47,10 +47,18 @@ gen-avr-mmcu-texi$(build_exeext): $(srcd
   $(TM_H) $(AVR_MCUS) $(srcdir)/config/avr/avr-devices.c
 	$(CC) $(ALL_CFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) $< -o $@
 
-avr-devices.o: s-avr-mmcu-texi
+# Make sure that the -mmcu= documentation is in sync with the compiler.
+$(srcdir)/doc/avr-mmcu.texi: s-avr-mmcu-texi; @true
 
+# invoke.texi @includes avr-mmcu.texi.  Put this dependency here instead
+# of in the global Makefile so that developers of other backends are not
+# bothered with AVR stuff. 
+$(srcdir)/doc/invoke.texi: $(srcdir)/doc/avr-mmcu.texi
+
+# Ensure that device support is in sync with -mmcu= documentation.
 s-avr-mmcu-texi: gen-avr-mmcu-texi$(build_exeext)
-	$(RUN_GEN) ./$< | sed -e 's:\r::g' > avr-mmcu.texi
+	$(RUN_GEN) ./$< > tmp-avr-mmcu.texi
+	$(SHELL) $(srcdir)/../move-if-change tmp-avr-mmcu.texi avr-mmcu.texi
 	@if cmp -s $(srcdir)/doc/avr-mmcu.texi avr-mmcu.texi; then \
 	  $(STAMP) $@;		\
 	else			\
Index: doc/avr-mmcu.texi
===
--- doc/avr-mmcu.texi	(revision 187704)
+++ doc/avr-mmcu.texi	(working copy)
@@ -13,11 +13,11 @@
 
 @item avr2
 ``Classic'' devices with up to 8@tie{}KiB of program memory.
-@*@var{mcu}@tie{}= @code{at90s2313}, @code{at90s2323}, @code{at90s2333}, @code{at90s2343}, @code{attiny22}, @code{attiny26}, @code{at90s4414}, @code{at90s4433}, @code{at90s4434}, @code{at90s8515}, @code{at90c8534}, @code{at90s8535}.
+@*@var{mcu}@tie{}= @code{at90c8534}, @code{at90s2313}, @code{at90s2323}, @code{at90s2333}, @code{at90s2343}, @code{at90s4414}, @code{at90s4433}, @code{at90s4434}, @code{at90s8515}, @code{at90s8535}, @code{attiny22}, @code{attiny26}.
 
 @item avr

Re: [AARCH64] [PATCH 3/3] AArch64 Port

[Tejas Belagod]

Richard Sandiford wrote:

Tejas Belagod  writes:

Hi Richard,

Thanks for your comments. Some questions inline below.

Richard Sandiford wrote:

Marcus Shawcroft  writes:

This patch adds an implementation of integer iterators.

Nice.  A few comments from an onlooker (on top of what Stephen said).


+/* Since GCC does not construct a table of valid constants,
+   we have to accept any int as valid.  No cross-checking can
+   be done.  */
+static int
+find_int (const char *name)
+{
+  char *endptr;
+  int ret;
+
+  if (ISDIGIT (*name))
+{
+  ret = strtol (name, &endptr, 0);
+  gcc_assert (*endptr == '\0');

I think this should be an error rather than an assert.


+/* Stand-alone int iterator usage-checking function.  */
+static bool
+uses_int_iterator_p (rtx x, struct mapping *iterator, int opno)
+{
+  int i;
+  for (i=0; i < num_int_iterator_data; i++)
+if (int_iterator_data[i].iterator->group == iterator->group &&
+   int_iterator_data[i].iterator->index == iterator->index)

Formatting: && should be at the beginning of the second line.


+  {
+   /* Found an existing entry. Check if X is in its list.  */
+   struct int_iterator_mapping it = int_iterator_data[i];
+   int j;
+
+   for (j=0; j < it.num_rtx; j++)
+   {
+ if (it.rtxs[j].x == x && it.rtxs[j].opno == opno)
+   return true;
+   }

Formatting: redundant { ... }.

It might be easier to store a pointer to XEXP (x, opno) than storing
x and opno separately.


+  }
+  return false;
+}
+
 /* Map a code or mode attribute string P to the underlying string for
ITERATOR and VALUE.  */
 
@@ -341,7 +414,9 @@

   x = rtx_alloc (bellwether_code);
   memcpy (x, original, RTX_CODE_SIZE (bellwether_code));
 
-  /* Change the mode or code itself.  */

+  /* Change the mode or code itself.
+ For int iterators, apply_iterator () does nothing. This is
+ because we want to apply int iterators to operands below.  */

The way I imagined this working is that we'd just walk a list of
rtx * pointers for the current iterator and substitute the current
iterator value.  Then we'd take a deep copy of the rtx once all
iterators had been applied.  Checking every operand against the
substitution table seems a bit round-about.

I understand how this would work for mode and code iterators, but I'm a 
bit confused about how it would for int iterators.


Probably because of a typo, sorry.  I meant "int *" in the above.
At least, they'd be "int *" for int iterators and "rtx" for mode
and code iterators.



Thanks for the clarification.

Don't we have to 
traverse each operand to figure out which ones to substitute for an int 
iterator value? Also, when you say take a deep copy after all the 
iterators have been applied, do you mean code, mode and int iterators or 
do you mean values of a particular iterator? As I understand the current 
implementation, mode and code iterators use placeholder integral 
constants that are replaced with actual iterator values during the rtx 
traverse. If we take a deep copy after the replacement, won't we lose 
these placeholder codes?


If you don't convert codes and modes (and leave it to me), then you'd
probably need to apply all int interators first.  I expect it'd be easier
to convert modes and codes at the same time.


In the currect scheme, when multiple code/mode iterators are in an rtx pattern, 
they are expanded for each combination of iterator values in 
apply_iterator_traverse () and a repeated traversal of the expanded rtx's for 
each iterator achieves the 'cross-product' of rtx's for iterator value 
combinations. This allows for having the place-holder codes/modes in new rtx's 
that are shallow-copied and a subsequent traversal will eventually replace them 
with actual code/mode iterator values. Doing away with the placeholders means 
that we have to build a 'cross-product' of iterator values from a database of 
iterator values as used in a pattern and make an rtx copy(deep) corresponding to 
each element of the cross-product with the iterator value combinations 
substituted in. This is my understanding of the new implementation - am I on the 
right track?


Thanks,
Tejas.

Re: [PATCH][RFC] Extend memset recognition

[Richard Guenther]

On Wed, 30 May 2012, Richard Guenther wrote:

> 
> The patch below extents memset recognition to cover a few more
> non-byte-size store loops and all byte-size store loops.  This exposes
> issues with our builtins.exp testsuite which has custom memset
> routines like
> 
> void *
> my_memset (void *d, int c, size_t n)
> {
>   char *dst = (char *) d;
>   while (n--)
> *dst++ = c;
>   return (char *) d;
> }
> 
> Now, for LTO we have papered over similar issues by attaching
> the used attribute to the functions.  But the general question is - when
> can we be sure the function we are dealing with are not the actual
> implementation for the builtin call we want to generate?  A few
> things come to my mind:
> 
>  1) the function already calls the function we want to generate (well,
> it might be a tail-recursive memset implementation ...)
> 
>  2) the function availability is AVAIL_LOCAL
> 
>  3) ... ?
> 
> For sure 2) would work, but it would severely restrict the transform
> (do we care?).
> 
> We have a similar issue with sin/cos -> sincos transform and a
> trivial sincos implementation.
> 
> Any ideas?
> 
> Bootstrapped (with memset recognition enabled by default) and tested
> on x86_64-unknown-linux-gnu with the aforementioned issues.

The following fixes it by simply always adding 
-fno-tree-loop-distribute-patterns to builtins.exp.

Bootstrapped and tested on x86_64-unknown-linux-gnu.

If there are no further comments I'll go with the local advise from
Micha who says "who cares".

Thanks,
Richard.

2012-05-30  Richard Guenther  

PR tree-optimization/53081
* tree-data-ref.h (stores_zero_from_loop): Rename to ...
(stores_bytes_from_loop): ... this.
(stmt_with_adjacent_zero_store_dr_p): Rename to ...
(stmt_with_adjacent_byte_store_dr_p): ... this.
* tree-data-ref.c (stmt_with_adjacent_zero_store_dr_p): Rename to ...
(stmt_with_adjacent_byte_store_dr_p): ... this.  Handle all kinds
of byte-sized stores.
(stores_zero_from_loop): Rename to ...
(stores_bytes_from_loop): ... this.
* tree-loop-distribution.c (generate_memset_zero): Rename to ...
(generate_memset): ... this.  Handle all kinds of byte-sized
stores.
(generate_builtin): Adjust.
(can_generate_builtin): Likewise.
(tree_loop_distribution): Likewise.

* gcc.dg/tree-ssa/ldist-19.c: New testcase.
* gcc.c-torture/execute/builtins/builtins.exp: Always pass
-fno-tree-loop-distribute-patterns.

Index: gcc/tree-data-ref.h
===
*** gcc/tree-data-ref.h.orig2012-05-30 13:24:52.0 +0200
--- gcc/tree-data-ref.h 2012-05-30 13:24:56.128827666 +0200
*** index_in_loop_nest (int var, VEC (loop_p
*** 606,616 
  }
  
  void stores_from_loop (struct loop *, VEC (gimple, heap) **);
! void stores_zero_from_loop (struct loop *, VEC (gimple, heap) **);
  void remove_similar_memory_refs (VEC (gimple, heap) **);
  bool rdg_defs_used_in_other_loops_p (struct graph *, int);
  bool have_similar_memory_accesses (gimple, gimple);
! bool stmt_with_adjacent_zero_store_dr_p (gimple);
  
  /* Returns true when STRIDE is equal in absolute value to the size of
 the unit type of TYPE.  */
--- 606,616 
  }
  
  void stores_from_loop (struct loop *, VEC (gimple, heap) **);
! void stores_bytes_from_loop (struct loop *, VEC (gimple, heap) **);
  void remove_similar_memory_refs (VEC (gimple, heap) **);
  bool rdg_defs_used_in_other_loops_p (struct graph *, int);
  bool have_similar_memory_accesses (gimple, gimple);
! bool stmt_with_adjacent_byte_store_dr_p (gimple);
  
  /* Returns true when STRIDE is equal in absolute value to the size of
 the unit type of TYPE.  */
Index: gcc/tree-data-ref.c
===
*** gcc/tree-data-ref.c.orig2012-05-30 13:24:52.0 +0200
--- gcc/tree-data-ref.c 2012-05-30 13:24:56.141827666 +0200
*** stores_from_loop (struct loop *loop, VEC
*** 5248,5259 
free (bbs);
  }
  
! /* Returns true when the statement at STMT is of the form "A[i] = 0"
 that contains a data reference on its LHS with a stride of the same
!size as its unit type.  */
  
  bool
! stmt_with_adjacent_zero_store_dr_p (gimple stmt)
  {
tree lhs, rhs;
bool res;
--- 5248,5260 
free (bbs);
  }
  
! /* Returns true when the statement at STMT is of the form "A[i] = x"
 that contains a data reference on its LHS with a stride of the same
!size as its unit type that can be rewritten as a series of byte
!stores with the same value.  */
  
  bool
! stmt_with_adjacent_byte_store_dr_p (gimple stmt)
  {
tree lhs, rhs;
bool res;
*** stmt_with_adjacent_zero_store_dr_p (gimp
*** 5272,5278 
&& DECL_BIT_FIELD (TREE_OPERAND (lhs, 1)))
  return false;
  
!   if (!(integer_zerop (rhs) || real_zerop (rhs)))
  r

[PATCH] Fix PR48493

[Richard Guenther]

This fixes PR48493 by backporting a one-liner - we should not go
the movmisalign path for destinations that are not memory.

Bootstrapped and tested on x86_64-unknown-linux-gnu and on
mips by Andrew, installed.

Richard.

2012-05-31  Richard Guenther  

PR middle-end/48493
* expr.c (expand_assignment): Do not use movmisalign on
non-memory.

* gcc.dg/torture/pr48493.c: New testcase.

Index: gcc/expr.c
===
*** gcc/expr.c  (revision 188009)
--- gcc/expr.c  (working copy)
*** expand_assignment (tree to, tree from, b
*** 4593,4598 
--- 4593,4599 
if ((TREE_CODE (to) == MEM_REF
 || TREE_CODE (to) == TARGET_MEM_REF)
&& mode != BLKmode
+   && !mem_ref_refers_to_non_mem_p (to)
&& ((align = get_object_or_type_alignment (to))
  < GET_MODE_ALIGNMENT (mode))
&& ((icode = optab_handler (movmisalign_optab, mode))
Index: gcc/testsuite/gcc.dg/torture/pr48493.c
===
*** gcc/testsuite/gcc.dg/torture/pr48493.c  (revision 0)
--- gcc/testsuite/gcc.dg/torture/pr48493.c  (revision 0)
***
*** 0 
--- 1,18 
+ /* { dg-do compile } */
+ 
+ typedef long long T __attribute__((may_alias, aligned (1)));
+ 
+ struct S
+ {
+   _Complex float d __attribute__((aligned (8)));
+ };
+ 
+ void bar (struct S);
+ 
+ void
+ f1 (T x)
+ {
+   struct S s;
+   *(T *) ((char *) &s.d + 1) = x;
+   bar (s);
+ }

[PATCH] Fix MEM_REF offset calculation in dr_analyze_innermost

[Richard Guenther]

Pointed out by people working on targets with ptr-size != sizetype size.

Bootstrapped and tested on x86_64-unknown-linux-gnu, applied.

Richard.

2012-05-31  Richard Guenther  

* tree-data-ref.c (dr_analyze_innermost): Properly convert
the MEM_REF offset to sizetype.

Index: gcc/tree-data-ref.c
===
--- gcc/tree-data-ref.c (revision 188055)
+++ gcc/tree-data-ref.c (working copy)
@@ -755,13 +755,12 @@ dr_analyze_innermost (struct data_refere
 {
   if (!integer_zerop (TREE_OPERAND (base, 1)))
{
+ double_int moff = mem_ref_offset (base);
+ tree mofft = double_int_to_tree (sizetype, moff);
  if (!poffset)
-   {
- double_int moff = mem_ref_offset (base);
- poffset = double_int_to_tree (sizetype, moff);
-   }
+   poffset = mofft;
  else
-   poffset = size_binop (PLUS_EXPR, poffset, TREE_OPERAND (base, 1));
+   poffset = size_binop (PLUS_EXPR, poffset, mofft);
}
   base = TREE_OPERAND (base, 0);
 }

Re: [google/gcc-4_6] Adjust .xfail files for ARM & PowerPC64 (issue6255067)

[Diego Novillo]

On 12-05-31 02:27 , Doug Kwan wrote:


2012-05-30   Doug Kwan

* contrib/testsuite-management/powerpc64-grtev2-linux-gnu.xfail:
Mark TLS tests as flaky. These do not work well with QEMU.
Exempt g++.dg/cpp0x/variadic-value1.C like we did for x86.
* contrib/testsuite-management/arm-grtev2-linux-gnueabi.xfail:
Same.


OK.


Diego.

Re: Use C++ in COMPILER_FOR_BUILD if needed (issue6191056)

[Diego Novillo]

On 12-05-30 13:42 , DJ Delorie wrote:



  BUILD_CFLAGS= @BUILD_CFLAGS@ -DGENERATOR_FILE
+BUILD_CXXFLAGS = $(INTERNAL_CFLAGS) $(CXXFLAGS) -DGENERATOR_FILE


Why are these so different?

The rest seem OK


Ah, I missed adding BUILD_CXXFLAGS to configure.ac.  Thanks.

OK to commit this amended patch?

2012-05-31

* configure.ac (CXX_FOR_BUILD): Define and substitute.
(BUILD_CXXFLAGS): Define and substitute.
* Makefile.in (BUILD_CXXFLAGS): Define.
(CXX_FOR_BUILD): Define.
(COMPILER_FOR_BUILD): Set to CXX_FOR_BUILD if building with C++.
(LINKER_FOR_BUILD): Likewise.
(BUILD_COMPILERFLAGS): Set to BUILD_CXXFLAGS if building with C++.
(BUILD_LINKERFLAGS): Likewise.
* configure: Regenerate.

diff --git a/gcc/Makefile.in b/gcc/Makefile.in
index 7b61b71..502cde8 100644
--- a/gcc/Makefile.in
+++ b/gcc/Makefile.in
@@ -728,15 +728,27 @@ DIR = ../gcc

 # Native compiler for the build machine and its switches.
 CC_FOR_BUILD = @CC_FOR_BUILD@
+CXX_FOR_BUILD = @CXX_FOR_BUILD@
 BUILD_CFLAGS= @BUILD_CFLAGS@ -DGENERATOR_FILE
+BUILD_CXXFLAGS = @BUILD_CXXFLAGS@ -DGENERATOR_FILE

 # Native compiler that we use.  This may be C++ some day.
+ifneq ($(ENABLE_BUILD_WITH_CXX),yes)
 COMPILER_FOR_BUILD = $(CC_FOR_BUILD)
 BUILD_COMPILERFLAGS = $(BUILD_CFLAGS)
+else
+COMPILER_FOR_BUILD = $(CXX_FOR_BUILD)
+BUILD_COMPILERFLAGS = $(BUILD_CXXFLAGS)
+endif

 # Native linker that we use.
+ifneq ($(ENABLE_BUILD_WITH_CXX),yes)
 LINKER_FOR_BUILD = $(CC_FOR_BUILD)
 BUILD_LINKERFLAGS = $(BUILD_CFLAGS)
+else
+LINKER_FOR_BUILD = $(CXX_FOR_BUILD)
+BUILD_LINKERFLAGS = $(BUILD_CXXFLAGS)
+endif

 # Native linker and preprocessor flags.  For x-fragment overrides.
 BUILD_LDFLAGS=@BUILD_LDFLAGS@
diff --git a/gcc/configure.ac b/gcc/configure.ac
index a3a4038..0c55952 100644
--- a/gcc/configure.ac
+++ b/gcc/configure.ac
@@ -1848,7 +1848,9 @@ AC_SUBST(inhibit_libc)

 # These are the normal (build=host) settings:
 CC_FOR_BUILD='$(CC)'   AC_SUBST(CC_FOR_BUILD)
+CXX_FOR_BUILD='$(CXX)' AC_SUBST(CXX_FOR_BUILD)
 BUILD_CFLAGS='$(ALL_CFLAGS)'   AC_SUBST(BUILD_CFLAGS)
+BUILD_CXXFLAGS='$(ALL_CXXFLAGS)' AC_SUBST(BUILD_CXXFLAGS)
 BUILD_LDFLAGS='$(LDFLAGS)' AC_SUBST(BUILD_LDFLAGS)
 STMP_FIXINC=stmp-fixincAC_SUBST(STMP_FIXINC)

Re: PowerPC prologue and epilogue 6

[Dominique Dhumieres]

> Please try out this patch on Darwin.  Bootstrapped and regression
> tested powerpc-linux.

I have applied the patch to r188026 and updated the build.
As patched the test gcc.target/powerpc/savres.c now fails with

FAIL: gcc.target/powerpc/savres.c (test for excess errors)
Excess errors:
ld_classic: can't locate file for: -lcrt0.o

According Iain Sandoe

> -static is not applicable to Darwin (except for kernel code).
> to make the test non-pic - use "-mdynamic-no-pic" (Darwin-only).

Replacing -static with -mdynamic-no-pic makes the test to pass
(the final patch will require the suitable dg directives;-).

Thanks

Dominique

PS Clean bootstrap and full regtesting scheduled for the next week-end).

Re: [PATCH] Fix PR53501

[Eric Botcazou]

> This fixes PR53501, fold_plusminus_mult_expr does not expect that
> operands have a sign-conversion stripped.  So don't call it with
> such arguments.
>
> Bootstrap and regtest pending on x86_64-unknown-linux-gnu.
>
> Richard.
>
> 2012-05-30  Richard Guenther  
>
>   PR middle-end/53501
>   * fold-const.c (fold_binary_loc): Make sure to call
>   fold_plusminus_mult_expr with the original sign of operands.

This pessimizes size computations in Ada for 64-bit targets on the 4.7 branch.

For the attached testcase, we go from:

Representation information for unit t (spec)


for x'Object_Size use 17179869248;
for x'Value_Size use  ((#1 + 8) * 8) ;
for x'Alignment use 4;
for x use record
   m at  0 range  0 .. 30;
   s at  4 range  0 ..  ((#1 * 8))  - 1;
   r at bit offset (((#1 + 4) * 8))  size in bits = 31
   b at bit offset #1 + 7) * 8) + 7))  size in bits = 1
end record;

to

Representation information for unit t (spec)


for x'Object_Size use 17179869248;
for x'Value_Size use  (((#1 + 7) * 8) + 8) ;
for x'Alignment use 4;
for x use record
   m at  0 range  0 .. 30;
   s at  4 range  0 ..  ((#1 * 8))  - 1;
   r at bit offset (((#1 + 4) * 8))  size in bits = 31
   b at bit offset #1 + 7) * 8) + 7))  size in bits = 1
end record;

with -gnatR3 and I'm not sure to understand what the sign has to do here.

-- 
Eric Botcazou
package t is

type x (m : natural) is record
s : string (1 .. m);
r : natural;
b : boolean;
end record;
for x'alignment use 4;

pragma Pack (x);

end t;

Re: [PATCH] Fix PR53501

[Richard Guenther]

On Thu, 31 May 2012, Eric Botcazou wrote:

> > This fixes PR53501, fold_plusminus_mult_expr does not expect that
> > operands have a sign-conversion stripped.  So don't call it with
> > such arguments.
> >
> > Bootstrap and regtest pending on x86_64-unknown-linux-gnu.
> >
> > Richard.
> >
> > 2012-05-30  Richard Guenther  
> >
> > PR middle-end/53501
> > * fold-const.c (fold_binary_loc): Make sure to call
> > fold_plusminus_mult_expr with the original sign of operands.
> 
> This pessimizes size computations in Ada for 64-bit targets on the 4.7 branch.
> 
> For the attached testcase, we go from:
> 
> Representation information for unit t (spec)
> 
> 
> for x'Object_Size use 17179869248;
> for x'Value_Size use  ((#1 + 8) * 8) ;
> for x'Alignment use 4;
> for x use record
>m at  0 range  0 .. 30;
>s at  4 range  0 ..  ((#1 * 8))  - 1;
>r at bit offset (((#1 + 4) * 8))  size in bits = 31
>b at bit offset #1 + 7) * 8) + 7))  size in bits = 1
> end record;
> 
> to
> 
> Representation information for unit t (spec)
> 
> 
> for x'Object_Size use 17179869248;
> for x'Value_Size use  (((#1 + 7) * 8) + 8) ;
> for x'Alignment use 4;
> for x use record
>m at  0 range  0 .. 30;
>s at  4 range  0 ..  ((#1 * 8))  - 1;
>r at bit offset (((#1 + 4) * 8))  size in bits = 31
>b at bit offset #1 + 7) * 8) + 7))  size in bits = 1
> end record;
> 
> with -gnatR3 and I'm not sure to understand what the sign has to do here.

The issue is that fold_plusminus_mult re-writes the multiplication
from unsigned to signed for the failing testcase, introducing
undefined overflow.  Yes, it's possible to make fold_plusminus_mult
deal with the situation properly (you can always express the
computations in unsigned arithmetic if association simplifies it).
I just thought that's not appropriate for the branch, so the
simple wrong-code fix was better (the rest is on my TODO for trunk - if
you do not beat me to it).

Richard.

Re: [Patch, Fortran] PR53521 - Fix size == 0 handling with reallocate

[Janne Blomqvist]

On Thu, May 31, 2012 at 12:28 PM, Tobias Burnus  wrote:
> Dear all,
>
> gfortran was producing the following code:
>
>  res = realloc (mem, size)
>  if (size == 0)
>    res = NULL;
>  ...
>  if (res != 0)
>    free (res)
>
> The problem is that "realloc (..., 0)" does not have to produce a NULL
> pointer as result.
>
>
> While in "valgrind" one only gets the warning that "0 bytes in  blocks"
> where not freed, looking at "top", one sees an excessive use of memory.
>
> That seems to cause crashes in CP2K. At least the valgrind issue is a GCC
> 4.3 to 4.8 regression.
>
>
> Without the patch, gfortran produces:
> 
>      D.1888 = (integer(kind=4)[0] * restrict) __builtin_realloc ((void *)
> atmp.0.data, D.1887);
>      if (D.1888 == 0B && D.1887 != 0)
>        {
>          _gfortran_os_error (&"Allocation would exceed memory limit"[1]{lb:
> 1 sz: 1});
>        }
>      if (D.1887 == 0)
>        {
>          D.1888 = 0B;
>        }
>      atmp.0.data = (void * restrict) D.1888;
> 
>
>
> I see two possibilities:
>
>
> 1) FIRST approach: manual freeing/NULL setting; that's the closed what is
> currently done. (Note: It calls free unconditionally; "free(0)" is optimized
> away by the middle end.
> (Note: That requires an update of the "free" count in
> gfortran.dg/allocatable_function_4.f90)
> 
>      if (D.1887 == 0)
>        {
>          __builtin_free ((void *) atmp.0.data);
>          D.1888 = 0B;
>        }
>      else
>        {
>          D.1888 = (integer(kind=4)[0] * restrict) __builtin_realloc ((void
> *) atmp.0.data, D.1887);
>          if (D.1888 == 0B && D.1887 != 0)
>            {
>              _gfortran_os_error (&"Allocation would exceed memory
> limit"[1]{lb: 1 sz: 1});
>            }
>        }
>      atmp.0.data = (void * restrict) D.1888;
> 
>
>
> 2) SECOND approach: Simply removing the NULL setting and just using the
> result which realloc returns; if not NULL, the free() will properly handle
> it.
> 
>      D.1888 = (integer(kind=4)[0] * restrict) __builtin_realloc ((void *)
> atmp.0.data, D.1887);
>      if (D.1888 == 0B && D.1887 != 0)
>        {
>          _gfortran_os_error (&"Allocation would exceed memory limit"[1]{lb:
> 1 sz: 1});
>        }
>      atmp.0.data = (void * restrict) D.1888;
> 
>
>
> Both patches have been tested with Joost's example and the test suite.
> Which version do you prefer? OK for the trunk?
>
> I like the second version more. (And I would even consider to get rid of the
> os_error.)

I prefer the second approach as well, Ok for trunk.


-- 
Janne Blomqvist

Re: [PATCH][RFC] Extend memset recognition

[Michael Matz]

Hi,

On Thu, 31 May 2012, Richard Guenther wrote:

> > Bootstrapped (with memset recognition enabled by default) and tested 
> > on x86_64-unknown-linux-gnu with the aforementioned issues.
> 
> The following fixes it by simply always adding 
> -fno-tree-loop-distribute-patterns to builtins.exp.
> 
> Bootstrapped and tested on x86_64-unknown-linux-gnu.
> 
> If there are no further comments I'll go with the local advise from 
> Micha who says "who cares".

To be honest, the long version of "who cares" was rather:
M "well we could disallow generating calls to X in functions named X", 
  handling some easy cases;
R "but user could write my_memcpy, and use an alias to it named memcpy 
  from another unit";
M "so, he shouldn't do that, or disable such pattern recognition";
R "we could also only rewrite in AVAIL_LOCAL function";
M "huh, disables quite many things except for lto, ... my benchmarks ...";
R "hmm"
M "hmm"
...
M "who cares"

;)


Ciao,
Michael.

Re: [PATCH] Sparc longlong.h enhancements.

[Eric Botcazou]

> Eric, while looking at soft-fp code generated in glibc I noticed that
> for v9 on 32-bit we end up doing software multiplies and divides :-/
>
> I also noticed that the two-limb addition and subtraction could be
> done using a branchless sequence on 64-bit.
>
> Any objections?

None on principle, but...

>  #if ((defined (__sparc__) && defined (__arch64__)) || defined (__sparcv9))
> \ && W_TYPE_SIZE == 64
>  #define add_ss(sh, sl, ah, al, bh, bl)   \
> -  __asm__ ("addcc %r4,%5,%1\n\t" \
> -"add %r2,%3,%0\n\t"  \
> -"bcs,a,pn %%xcc, 1f\n\t" \
> -"add %0, 1, %0\n"\
> -"1:" \
> +  do {   
> \
> +UDItype __carry = 0; \
> +__asm__ ("addcc\t%r5,%6,%1\n\t"  \
> +  "add\t%r3,%4,%0\n\t"   \
> +  "movcs\t%%xcc, 1, %2\n\t"  \
> + "add\t%0, %2, %0"   
> \
>
>  : "=r" ((UDItype)(sh)),  \
>
> -  "=&r" ((UDItype)(sl))  \
> +  "=&r" ((UDItype)(sl)), \
> +  "=&r" (__carry)\
>
>  : "%rJ" ((UDItype)(ah)), \
>
>"rI" ((UDItype)(bh)),  \
>"%rJ" ((UDItype)(al)), \
> -  "rI" ((UDItype)(bl))   \
> -__CLOBBER_CC)
> +  "rI" ((UDItype)(bl)),  \
> +  "2" (__carry)  \
> +__CLOBBER_CC);   \
> +  } while (0)

If __carry is used as both source and destination for %2, why not use a single 
operand with the + modifier?

> -#define sub_ddmmss(sh, sl, ah, al, bh, bl)   \
> -  __asm__ ("subcc %r4,%5,%1\n\t" \
> -"sub %r2,%3,%0\n\t"  \
> -"bcs,a,pn %%xcc, 1f\n\t" \
> -"sub %0, 1, %0\n\t"  \
> -"1:" \
> +#define sub_ddmmss(sh, sl, ah, al, bh, bl)   \
> +  do {   
> \
> +UDItype __carry = 0; \
> +__asm__ ("subcc\t%r5,%6,%1\n\t"  \
> +  "sub\t%r3,%4,%0\n\t"   \
> +  "movcs\t%%xcc, 1, %2\n\t"  \
> + "add\t%0, %2, %0"   
> \
>
>  : "=r" ((UDItype)(sh)),  \
>
> -  "=&r" ((UDItype)(sl))  \
> -: "rJ" ((UDItype)(ah)),  \
> +  "=&r" ((UDItype)(sl)), \
> +  "=&r" (__carry)\
> +: "%rJ" ((UDItype)(ah)), \
>"rI" ((UDItype)(bh)),  \
> -  "rJ" ((UDItype)(al)),  \
> -  "rI" ((UDItype)(bl))   \
> -__CLOBBER_CC)
> +  "%rJ" ((UDItype)(al)), \
> +  "rI" ((UDItype)(bl)),  \
> +  "2" (__carry)  \
> +__CLOBBER_CC);   \
> +  } while (0)

Likewise.

-- 
Eric Botcazou

Re: PowerPC prologue and epilogue 6

[Alan Modra]

On Thu, May 31, 2012 at 02:16:32PM +0200, Dominique Dhumieres wrote:
> (the final patch will require the suitable dg directives;-).

This is really stretching my testsuite knowledge.  Maybe add

/* { dg-additional-options "-mdynamic-no-pic" { target *-*-darwin* } } */


-- 
Alan Modra
Australia Development Lab, IBM

PATCH: PR target/53539: Different __WCHAR_TYPE__/wchar_t for gcc -m32 on Linux/i386 and Linux/x86-64

[H.J. Lu]

Hi,

This patch makes __WCHAR_TYPE__/wchar_t the same for gcc -m32 on
Linux/i386 and Linux/x86-64.  OK for trunk?

Thanks.


H.J.

2012-05-31  H.J. Lu  

PR target/53539
* config/i386/gnu-user.h (WCHAR_TYPE): Use "int".
(WCHAR_TYPE_SIZE): Set to 32.

diff --git a/gcc/config/i386/gnu-user.h b/gcc/config/i386/gnu-user.h
index 9020be9..f88cbad 100644
--- a/gcc/config/i386/gnu-user.h
+++ b/gcc/config/i386/gnu-user.h
@@ -53,10 +53,10 @@ along with GCC; see the file COPYING3.  If not see
 #define PTRDIFF_TYPE "int"
   
 #undef WCHAR_TYPE
-#define WCHAR_TYPE "long int"
+#define WCHAR_TYPE "int"

 #undef WCHAR_TYPE_SIZE
-#define WCHAR_TYPE_SIZE BITS_PER_WORD
+#define WCHAR_TYPE_SIZE 32
 
 /* Provide a LINK_SPEC appropriate for GNU userspace.  Here we provide support
for the special GCC options -static and -shared, which allow us to

Re: PowerPC prologue and epilogue 6

[Dominique Dhumieres]

> This is really stretching my testsuite knowledge.  Maybe add
>
>/* { dg-additional-options "-mdynamic-no-pic" { target *-*-darwin* } } */

Using

/* { dg-options "-fno-inline -fomit-frame-pointer" } */
/* { dg-additional-options "-mdynamic-no-pic" { target *-*-darwin* } } */

works for me on powerpc-apple-darwin9, but I can't test it on nondarwin powerpc.

Dominique

[Patch, ARM][0/8] Epilogue in RTL: introduction (Sameera's patches, Part I)

[Greta Yorsh]

This sequence of patches adds support for epilogue generation in RTL.

This is the first part of Sameera's work on ARM prologue/epilogue. Sameera
Deshpande posted it for review in December 2011, having addressed all
previous comments: http://gcc.gnu.org/ml/gcc-patches/2011-12/msg00049.html.
The latest version hasn't been approved yet. Originally, it was split into
two patches:
[1/2]: Thumb2 epilogue in RTL
[2/2]: ARM epilogue in RTL
I rebased Sameera's patches, made small changes in the patterns and fixed
RTL epilogue generated for -mapcs-frame. To make reviewing easier, I split
the patches into smaller steps:
* Reorganization - already committed upstream.
* New insn and expand patterns - main functionality change.
* Cleanup of dead code.

Here is the list of patches:
 1-update-predicate.patch
 2-patterns.patch
 3-patterns-vfp.patch
 4-expand-epilog-apcs-frame.patch
 5-expand-epilog.patch
 6-simple-return.patch
 7-expand-thumb2-return.patch
 8-remove-dead-code.patch

Testing:
* Crossbuild for target arm-none-eabi with cpu cortex-a9 neon softfp and
tested in three configuration: -marm (default), -mthumb, -mapcs-frame. No
regression on qemu.
* Crossbuild for target arm-none-eabi thumb2 with cpu cortex-m3. No
regression on qemu.
* Crossbuild for target arm-none-eabi thumb1 with cpu arm7tdmi and
arm1136jf-s. No regression on qemu.
* Crossbuild for target arm-linux-gnueabi with cpu cortex-a9 with eglibc and
used this compiler to build AEL linux kernel. It boots successfully.
* Bootstrap the compiler on cortex-a8 successfully for
--languages=c,c++,fortran and used this compiler to build gdb. No regression
with check-gcc and check-gdb.

Notes:
* The patches are to be applied in the above order.
* The patches are not intended to be used individually.
* The patches have been tested only as a sequence.
* The patches have been tested on gcc from 20 March 2012 (fsf trunk r185582
of gcc-4.8 stage 1). The patches apply cleanly to current trunk (r188056).
* The patches have not been explicitly tested with any FPA variants (which
are deprecated in 4.7 and expected to become obsolete in 4.8).

Ok for trunk?

Thank you,
Greta

Re: PATCH: PR target/53539: Different __WCHAR_TYPE__/wchar_t for gcc -m32 on Linux/i386 and Linux/x86-64

[Jakub Jelinek]

On Thu, May 31, 2012 at 06:35:19AM -0700, H.J. Lu wrote:
> This patch makes __WCHAR_TYPE__/wchar_t the same for gcc -m32 on
> Linux/i386 and Linux/x86-64.  OK for trunk?

That looks wrong.  For Linux/i386, the 32-bit only compiler should be
the standard, rather than x86_64 -m32 if they differ.
So, IMHO you should keep gnu-user.h as is, and just use
#define WCHAR_TYPE (TARGET_64BIT ? "int" : "long int")
in gcc/config/i386/x86-64.h.

> 2012-05-31  H.J. Lu  
> 
>   PR target/53539
>   * config/i386/gnu-user.h (WCHAR_TYPE): Use "int".
>   (WCHAR_TYPE_SIZE): Set to 32.
> 
> diff --git a/gcc/config/i386/gnu-user.h b/gcc/config/i386/gnu-user.h
> index 9020be9..f88cbad 100644
> --- a/gcc/config/i386/gnu-user.h
> +++ b/gcc/config/i386/gnu-user.h
> @@ -53,10 +53,10 @@ along with GCC; see the file COPYING3.  If not see
>  #define PTRDIFF_TYPE "int"
>
>  #undef WCHAR_TYPE
> -#define WCHAR_TYPE "long int"
> +#define WCHAR_TYPE "int"
> 
>  #undef WCHAR_TYPE_SIZE
> -#define WCHAR_TYPE_SIZE BITS_PER_WORD
> +#define WCHAR_TYPE_SIZE 32
>  
>  /* Provide a LINK_SPEC appropriate for GNU userspace.  Here we provide 
> support
> for the special GCC options -static and -shared, which allow us to

Jakub

[Patch, ARM][1/8] Epilogue in RTL: update ldm_stm_operation_p

[Greta Yorsh]

This patch updates ldm_stm_operation_p to check for loads that if SP is in
the register list, then the base register is SP. It guarantees that SP is
reset correctly when an LDM instruction is interrupted. Otherwise, we might
end up with a corrupt stack. 

ChangeLog:

gcc

2012-05-31  Greta Yorsh  

* config/arm/arm.c (ldm_stm_operation_p): Require SP
  as base register for loads if SP is in the register list.diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index e3290e2..4717725 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -10247,6 +10247,12 @@ ldm_stm_operation_p (rtx op, bool load, enum 
machine_mode mode,
   if (!REG_P (addr))
 return false;
 
+  /* Don't allow SP to be loaded unless it is also the base register. It
+ guarantees that SP is reset correctly when an LDM instruction
+ is interruptted. Otherwise, we might end up with a corrupt stack.  */
+  if (load && (REGNO (reg) == SP_REGNUM) && (REGNO (addr) != SP_REGNUM))
+return false;
+
   for (; i < count; i++)
 {
   elt = XVECEXP (op, 0, i);
@@ -10270,6 +10276,10 @@ ldm_stm_operation_p (rtx op, bool load, enum 
machine_mode mode,
   || (consecutive
   && (REGNO (reg) !=
   (unsigned int) (first_regno + regs_per_val * (i - base
+  /* Don't allow SP to be loaded unless it is also the base register. 
It
+ guarantees that SP is reset correctly when an LDM instruction
+ is interrupted. Otherwise, we might end up with a corrupt stack.  
*/
+  || (load && (REGNO (reg) == SP_REGNUM) && (REGNO (addr) != 
SP_REGNUM))
   || !MEM_P (mem)
   || GET_MODE (mem) != mode
   || ((GET_CODE (XEXP (mem, 0)) != PLUS

[PATCH][1/n] loop distribution TLC

[Richard Guenther]

This applies some TLC to loop distribution mainly to make pattern
recognition more sane and not so costly.  This first patch revisits
the fix for PR45948 which turned out not effective later and
effectively fixed by another patch, too (see the ??? marker for
how that patch was overly conservative).  Thus this first patch
removes the original fix and re-instantiates a testcase that would
still ICE.  Conveniently it also removes a few callers of 
can_generate_builtin - which followups concentrate on.

Bootstrapped and tested on x86_64-unknown-linux-gnu, applied to trunk.

Richard.

2012-05-31  Richard Guenther  

* tree-loop-distribution.c (stmt_has_scalar_dependences_outside_loop):
Use FOR_EACH_SSA_DEF_OPERAND.
(generate_builtin): Adjust.
(stmt_generated_in_another_partition): Remove.
(add_scalar_computations_to_partition): Likewise.
(rdg_build_partitions): Do not call
add_scalar_computations_to_partition.

* gcc.dg/tree-ssa/ldist-pr45948-2.c: New testcase copy of
ldist-pr45948.c with disabled SCCP.

Index: gcc/tree-loop-distribution.c
===
*** gcc/tree-loop-distribution.c.orig   2012-05-31 14:51:19.0 +0200
--- gcc/tree-loop-distribution.c2012-05-31 15:44:52.007545525 +0200
*** ssa_name_has_uses_outside_loop_p (tree d
*** 80,111 
  }
  
  /* Returns true when STMT defines a scalar variable used after the
!loop.  */
  
  static bool
! stmt_has_scalar_dependences_outside_loop (gimple stmt)
  {
!   tree name;
  
!   switch (gimple_code (stmt))
! {
! case GIMPLE_CALL:
! case GIMPLE_ASSIGN:
!   name = gimple_get_lhs (stmt);
!   break;
! 
! case GIMPLE_PHI:
!   name = gimple_phi_result (stmt);
!   break;
! 
! default:
!   return false;
! }
  
!   return (name
! && TREE_CODE (name) == SSA_NAME
! && ssa_name_has_uses_outside_loop_p (name,
!  loop_containing_stmt (stmt)));
  }
  
  /* Update the PHI nodes of NEW_LOOP.  NEW_LOOP is a duplicate of
--- 80,98 
  }
  
  /* Returns true when STMT defines a scalar variable used after the
!loop LOOP.  */
  
  static bool
! stmt_has_scalar_dependences_outside_loop (loop_p loop, gimple stmt)
  {
!   def_operand_p def_p;
!   ssa_op_iter op_iter;
  
!   FOR_EACH_SSA_DEF_OPERAND (def_p, stmt, op_iter, SSA_OP_DEF)
! if (ssa_name_has_uses_outside_loop_p (DEF_FROM_PTR (def_p), loop))
!   return true;
  
!   return false;
  }
  
  /* Update the PHI nodes of NEW_LOOP.  NEW_LOOP is a duplicate of
*** generate_builtin (struct loop *loop, bit
*** 382,390 
  if (!bitmap_bit_p (partition, x++))
continue;
  
! /* If the stmt has uses outside of the loop fail.  */
! if (stmt_has_scalar_dependences_outside_loop (stmt))
!   goto end;
  
  if (is_gimple_assign (stmt)
  && !is_gimple_reg (gimple_assign_lhs (stmt)))
--- 369,384 
  if (!bitmap_bit_p (partition, x++))
continue;
  
! /* If the stmt has uses outside of the loop fail.
!???  If the stmt is generated in another partition that
!is not created as builtin we can ignore this.  */
! if (stmt_has_scalar_dependences_outside_loop (loop, stmt))
!   {
! if (dump_file && (dump_flags & TDF_DETAILS))
!   fprintf (dump_file, "not generating builtin, partition has "
!"scalar uses outside of the loop\n");
! goto end;
!   }
  
  if (is_gimple_assign (stmt)
  && !is_gimple_reg (gimple_assign_lhs (stmt)))
*** fuse_partitions_with_similar_memory_acce
*** 879,938 
  }
  }
  
- /* Returns true when STMT will be code generated in a partition of RDG
-different than PART and that will not be code generated as a
-builtin.  */
- 
- static bool
- stmt_generated_in_another_partition (struct graph *rdg, gimple stmt, int part,
-VEC (bitmap, heap) *partitions)
- {
-   int p;
-   bitmap pp;
-   unsigned i;
-   bitmap_iterator bi;
- 
-   FOR_EACH_VEC_ELT (bitmap, partitions, p, pp)
- if (p != part
-   && !can_generate_builtin (rdg, pp))
-   EXECUTE_IF_SET_IN_BITMAP (pp, 0, i, bi)
-   if (stmt == RDG_STMT (rdg, i))
- return true;
- 
-   return false;
- }
- 
- /* For each partition in PARTITIONS that will be code generated using
-a builtin, add its scalar computations used after the loop to
-PARTITION.  */
- 
- static void
- add_scalar_computations_to_partition (struct graph *rdg,
- VEC (bitmap, heap) *partitions,
- bitmap partition)
- {
-   int p;
-   bitmap pp;
-   unsigned i;
-   bitmap_iterator bi;
-   bitmap l = BITMAP_ALLOC (NULL);
-   bitmap pr = BITMAP_ALLOC (NULL);
-   bo

[Patch, ARM][2/8] Epilogue in RTL: new patterns for int regs

[Greta Yorsh]

This patch adds new define_insn patterns for epilogue with integer
registers.

The patterns can handle pop multiple with writeback and return (loading into
PC directly).
To handle return, the patterns use a new special predicate
pop_multiple_return, that uses ldm_stm_operation_p function from a previous
patch. To output assembly, the patterns use a new function
arm_output_multireg_pop.

This patch also adds a new function arm_emit_multi_reg_pop
that emits RTL that matches the new pop patterns for integer registers.
This is a helper function for epilogue expansion. It is used by a later
patch.

ChangeLog:

gcc

2012-05-31  Ian Bolton  
Sameera Deshpande  
Greta Yorsh  

* config/arm/arm.md (load_multiple_with_writeback) New define_insn.
(load_multiple, pop_multiple_with_writeback_and_return) Likewise.
(pop_multiple_with_return, ldr_with_return) Likewise.
* config/arm/predicates.md (pop_multiple_return) New special
predicate.
* config/arm/arm-protos.h (arm_output_multireg_pop) New declaration.
* config/arm/arm.c (arm_output_multireg_pop) New function.
(arm_emit_multi_reg_pop): New function.
(ldm_stm_operation_p): Check SP in the register list.
diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h
index 53c2aef..7b25e37 100644
--- a/gcc/config/arm/arm-protos.h
+++ b/gcc/config/arm/arm-protos.h
@@ -156,6 +156,7 @@ extern intarm_emit_vector_const (FILE *, rtx);
 extern void arm_emit_fp16_const (rtx c);
 extern const char * arm_output_load_gr (rtx *);
 extern const char *vfp_output_fstmd (rtx *);
+extern void arm_output_multireg_pop (rtx *, bool, rtx, bool, bool);
 extern void arm_set_return_address (rtx, rtx);
 extern int arm_eliminable_register (rtx);
 extern const char *arm_output_shift(rtx *, int);
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 4717725..9093801 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -13815,6 +13815,84 @@ vfp_output_fldmd (FILE * stream, unsigned int base, 
int reg, int count)
 }
 
 
+/* OPERANDS[0] is the entire list of insns that constitute pop,
+   OPERANDS[1] is the base register, RETURN_PC is true iff return insn
+   is in the list, UPDATE is true iff the list contains explicit
+   update of base register.
+ */
+void
+arm_output_multireg_pop (rtx *operands, bool return_pc, rtx cond, bool reverse,
+ bool update)
+{
+  int i;
+  char pattern[100];
+  int offset;
+  const char *conditional;
+  int num_saves = XVECLEN (operands[0], 0);
+  unsigned int regno;
+  unsigned int regno_base = REGNO (operands[1]);
+
+  offset = 0;
+  offset += update ? 1 : 0;
+  offset += return_pc ? 1 : 0;
+
+  /* Is the base register in the list? */
+  for (i = offset; i < num_saves; i++)
+{
+  regno = REGNO (XEXP (XVECEXP (operands[0], 0, i), 0));
+  /* If SP is in the list, then the base register must be SP. */
+  gcc_assert ((regno != SP_REGNUM) || (regno_base == SP_REGNUM));
+  /* If base register is in the list, there must be no explicit update.  */
+  if (regno == regno_base)
+gcc_assert (!update);
+}
+
+  conditional = reverse ? "%?%D0" : "%?%d0";
+  if ((regno_base == SP_REGNUM) && TARGET_UNIFIED_ASM)
+{
+  /* Output pop (not stmfd) because it has a shorter encoding. */
+  gcc_assert (update);
+  sprintf (pattern, "pop%s\t{", conditional);
+}
+  else
+{
+  /* Output ldmfd when the base register is SP, otherwise output ldmia.
+ It's just a convention, their semantics are identical.  */
+  if (regno_base == SP_REGNUM)
+sprintf (pattern, "ldm%sfd\t", conditional);
+  else if (TARGET_UNIFIED_ASM)
+sprintf (pattern, "ldmia%s\t", conditional);
+  else
+sprintf (pattern, "ldm%sia\t", conditional);
+
+  strcat (pattern, reg_names[regno_base]);
+  if (update)
+strcat (pattern, "!, {");
+  else
+strcat (pattern, ", {");
+}
+
+  /* Output the first destination register. */
+  strcat (pattern,
+  reg_names[REGNO (XEXP (XVECEXP (operands[0], 0, offset), 0))]);
+
+  /* Output the rest of the destination registers.  */
+  for (i = offset + 1; i < num_saves; i++)
+{
+  strcat (pattern, ", ");
+  strcat (pattern,
+  reg_names[REGNO (XEXP (XVECEXP (operands[0], 0, i), 0))]);
+}
+
+  strcat (pattern, "}");
+
+  if (IS_INTERRUPT (arm_current_func_type ()) && return_pc)
+strcat (pattern, "^");
+
+  output_asm_insn (pattern, &cond);
+}
+
+
 /* Output the assembly for a store multiple.  */
 
 const char *
@@ -16461,6 +16539,85 @@ emit_multi_reg_push (unsigned long mask)
   return par;
 }
 
+/* Generate and emit an insn pattern that we will recognize as a pop_multi.
+   SAVED_REGS_MASK shows which registers need to be restored.
+
+   Unfortunately, since this insn does not reflect very well the actual
+   semantics of the operation, we need to annotate the insn for the benefit
+   

[Patch, ARM][3/8] Epilogue in RTL: new patterns for vfp regs

[Greta Yorsh]

New define insn pattern for epilogue with floating point registers (DFmode)
and a new function that emits RTL for this pattern. This function is a
helper for epilogue extension. It is used by a later patch.

ChangeLog:

gcc

2012-05-31  Ian Bolton  
Sameera Deshpande  
Greta Yorsh  

* config/arm/arm.md (vfp_pop_multiple_with_writeback) New
define_insn.
* config/arm/predicates.md (pop_multiple_fp) New special predicate.
* config/arm/arm.c (arm_emit_vfp_multi_reg_pop): New function.diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 9093801..491ffea 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -16618,6 +16618,76 @@ arm_emit_multi_reg_pop (unsigned long saved_regs_mask)
   REG_NOTES (par) = dwarf;
 }
 
+/* Generate and emit an insn pattern that we will recognize as a pop_multi
+   of NUM_REGS consecutive VFP regs, starting at FIRST_REG.
+
+   Unfortunately, since this insn does not reflect very well the actual
+   semantics of the operation, we need to annotate the insn for the benefit
+   of DWARF2 frame unwind information.  */
+static void
+arm_emit_vfp_multi_reg_pop (int first_reg, int num_regs, rtx base_reg)
+{
+  int i, j;
+  rtx par;
+  rtx dwarf = NULL_RTX;
+  rtx tmp, reg;
+
+  gcc_assert (num_regs && num_regs <= 32);
+
+/* Workaround ARM10 VFPr1 bug.  */
+  if (num_regs == 2 && !arm_arch6)
+{
+  if (first_reg == 15)
+first_reg--;
+
+  num_regs++;
+}
+
+  /* We can emit at most 16 D-registers in a single pop_multi instruction, and
+ there could be up to 32 D-registers to restore.
+ If there are more than 16 D-registers, make two recursive calls,
+ each of which emits one pop_multi instruction.  */
+  if (num_regs > 16)
+{
+  arm_emit_vfp_multi_reg_pop (first_reg, 16, base_reg);
+  arm_emit_vfp_multi_reg_pop (first_reg + 16, num_regs - 16, base_reg);
+  return;
+}
+
+  /* The parallel needs to hold num_regs SETs
+ and one SET for the stack update.  */
+  par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (num_regs + 1));
+
+  /* Increment the stack pointer, based on there being
+ num_regs 8-byte registers to restore.  */
+  tmp = gen_rtx_SET (VOIDmode,
+ base_reg,
+ plus_constant (base_reg, 8 * num_regs));
+  RTX_FRAME_RELATED_P (tmp) = 1;
+  XVECEXP (par, 0, 0) = tmp;
+
+  /* Now show every reg that will be restored, using a SET for each.  */
+  for (j = 0, i=first_reg; j < num_regs; i += 2)
+{
+  reg = gen_rtx_REG (DFmode, i);
+
+  tmp = gen_rtx_SET (VOIDmode,
+ reg,
+ gen_frame_mem
+ (DFmode,
+  plus_constant (base_reg, 8 * j)));
+  RTX_FRAME_RELATED_P (tmp) = 1;
+  XVECEXP (par, 0, j + 1) = tmp;
+
+  dwarf = alloc_reg_note (REG_CFA_RESTORE, reg, dwarf);
+
+  j++;
+}
+
+  par = emit_insn (par);
+  REG_NOTES (par) = dwarf;
+}
+
 /* Calculate the size of the return value that is passed in registers.  */
 static unsigned
 arm_size_return_regs (void)
diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index 862ccf4..98387fa 100644
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -11042,6 +11042,41 @@
   [(set_attr "type" "load1")
(set_attr "predicable" "yes")]
 )
+;; Pop for floating point registers (as used in epilogue RTL)
+(define_insn "*vfp_pop_multiple_with_writeback"
+  [(match_parallel 0 "pop_multiple_fp"
+[(set (match_operand:SI 1 "s_register_operand" "+rk")
+  (plus:SI (match_dup 1)
+   (match_operand:SI 2 "const_int_operand" "I")))
+ (set (match_operand:DF 3 "arm_hard_register_operand" "")
+  (mem:DF (match_dup 1)))])]
+  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
+  "*
+  {
+int num_regs = XVECLEN (operands[0], 0);
+char pattern[100];
+rtx op_list[2];
+strcpy (pattern, \"fldmfdd\\t\");
+strcat (pattern, reg_names[REGNO (SET_DEST (XVECEXP (operands[0], 0, 
0)))]);
+strcat (pattern, \"!, {\");
+op_list[0] = XEXP (XVECEXP (operands[0], 0, 1), 0);
+strcat (pattern, \"%P0\");
+if ((num_regs - 1) > 1)
+  {
+strcat (pattern, \"-%P1\");
+op_list [1] = XEXP (XVECEXP (operands[0], 0, num_regs - 1), 0);
+  }
+
+strcat (pattern, \"}\");
+output_asm_insn (pattern, op_list);
+return \"\";
+  }
+  "
+  [(set_attr "type" "load4")
+   (set_attr "conds" "unconditional")
+   (set_attr "predicable" "no")]
+)
+
 ;; Special patterns for dealing with the constant pool
 
 (define_insn "align_4"
diff --git a/gcc/config/arm/predicates.md b/gcc/config/arm/predicates.md
index 24dd4ea..92114bd 100644
--- a/gcc/config/arm/predicates.md
+++ b/gcc/config/arm/predicates.md
@@ -401,6 +401,14 @@
  /*return_pc=*/true);
 })
 
+(define_special_predicate "pop_multiple_fp"
+  (match_code "parallel")
+{
+ return ldm_stm_operation_p (op, /*load=*/true, DFmode,

[Patch, ARM][4/8] Epilogue in RTL: expand epilogue for apcs frame

[Greta Yorsh]

Helper function for epilogue expansion. Emit RTL for APCS frame epilogue
(when -mapcs-frame command line option is specified).
This function is used by a later patch.

For APCS frame epilogue, the compiler currently generates LDM with SP as
both the base register
and one of the destination registers. For example:

@ APCS_FRAME epilogue
ldmfd   sp, {r4, fp, sp, pc}

@ non-APCS_FRAME epilogue
ldmfd sp!, {r4, fp, pc}

The use of SP in LDM register list is deprecated, but this patch does not
address the problem.

To generate the epilogue for APCS frame in RTL, this patch adds a new
alternative to arm_addsi2 insn in ARM mode only to generate "sub sp, fp,
#imm". Previously, there was no pattern to generate sub with SP as the
destination register and not SP as the operand register.


ChangeLog:

gcc

2012-05-31  Ian Bolton  
Sameera Deshpande  
Greta Yorsh  

* config/arm/arm.c (arm_expand_epilogue_apcs_frame): New function.
* config/arm/arm.md (arm_addsi3) Add an alternative.diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 491ffea..d6b4c2e 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -22896,6 +22896,232 @@ thumb1_expand_epilogue (void)
 emit_use (gen_rtx_REG (SImode, LR_REGNUM));
 }
 
+/* Epilogue code for APCS frame.  */
+static void
+arm_expand_epilogue_apcs_frame (bool really_return)
+{
+  unsigned long func_type;
+  unsigned long saved_regs_mask;
+  int num_regs = 0;
+  int i;
+  int floats_from_frame = 0;
+  arm_stack_offsets *offsets;
+
+  gcc_assert (TARGET_APCS_FRAME && frame_pointer_needed && TARGET_ARM);
+  func_type = arm_current_func_type ();
+
+  /* Get frame offsets for ARM.  */
+  offsets = arm_get_frame_offsets ();
+  saved_regs_mask = offsets->saved_regs_mask;
+
+  /* Find the offset of the floating-point save area in the frame.  */
+  floats_from_frame = offsets->saved_args - offsets->frame;
+
+  /* Compute how many core registers saved and how far away the floats are.  */
+  for (i = 0; i <= LAST_ARM_REGNUM; i++)
+if (saved_regs_mask & (1 << i))
+  {
+num_regs++;
+floats_from_frame += 4;
+  }
+
+  if (TARGET_HARD_FLOAT && TARGET_VFP)
+{
+  int start_reg;
+
+  /* The offset is from IP_REGNUM.  */
+  int saved_size = arm_get_vfp_saved_size ();
+  if (saved_size > 0)
+{
+  floats_from_frame += saved_size;
+  emit_insn (gen_addsi3 (gen_rtx_REG (SImode, IP_REGNUM),
+ hard_frame_pointer_rtx,
+ GEN_INT (-floats_from_frame)));
+}
+
+  /* Generate VFP register multi-pop.  */
+  start_reg = FIRST_VFP_REGNUM;
+
+  for (i = FIRST_VFP_REGNUM; i < LAST_VFP_REGNUM; i += 2)
+/* Look for a case where a reg does not need restoring.  */
+if ((!df_regs_ever_live_p (i) || call_used_regs[i])
+&& (!df_regs_ever_live_p (i + 1)
+|| call_used_regs[i + 1]))
+  {
+if (start_reg != i)
+  arm_emit_vfp_multi_reg_pop (start_reg,
+  (i - start_reg) / 2,
+  gen_rtx_REG (SImode,
+   IP_REGNUM));
+start_reg = i + 2;
+  }
+
+  /* Restore the remaining regs that we have discovered (or possibly
+ even all of them, if the conditional in the for loop never
+ fired).  */
+  if (start_reg != i)
+arm_emit_vfp_multi_reg_pop (start_reg,
+(i - start_reg) / 2,
+gen_rtx_REG (SImode, IP_REGNUM));
+}
+  else if (TARGET_FPA_EMU2)
+{
+  for (i = LAST_FPA_REGNUM; i >= FIRST_FPA_REGNUM; i--)
+if (df_regs_ever_live_p (i) && !call_used_regs[i])
+  {
+rtx addr;
+rtx insn;
+floats_from_frame += 12;
+addr = gen_rtx_MEM (XFmode,
+gen_rtx_PLUS (SImode,
+  hard_frame_pointer_rtx,
+  GEN_INT (- floats_from_frame)));
+set_mem_alias_set (addr, get_frame_alias_set ());
+insn = emit_insn (gen_rtx_SET (XFmode,
+   gen_rtx_REG (XFmode, i),
+   addr));
+REG_NOTES (insn) = alloc_reg_note (REG_CFA_RESTORE,
+   gen_rtx_REG (XFmode, i),
+   NULL_RTX);
+  }
+}
+  else
+{
+  int idx = 0;
+  rtx load_seq[4];
+  rtx dwarf = NULL_RTX;
+  rtx par;
+  rtx frame_mem;
+
+  for (i = LAST_FPA_REGNUM; i >= FIRST_FPA_REGNUM; i--)
+{
+  /* We can't unstack more than four registers at once.  */
+  if (idx == 4)
+{
+  par = emit_insn (gen_rtx_PAR

[Patch, ARM][5/8] Epilogue in RTL: expand

[Greta Yorsh]

The main function for epilogue RTL generation, used by expand epilogue
patterns.

ChangeLog:

gcc

2012-05-31  Ian Bolton  
Sameera Deshpande  
Greta Yorsh  

* config/arm/arm-protos.h (arm_expand_epilogue): New declaration.
* config/arm/arm.c (arm_expand_epilogue): New function.
* config/arm/arm.md (epilogue): Update condition and code.
(sibcall_epilogue): Likewise.
diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h
index 7b25e37..f61feef 100644
--- a/gcc/config/arm/arm-protos.h
+++ b/gcc/config/arm/arm-protos.h
@@ -30,6 +30,7 @@ extern void arm_load_pic_register (unsigned long);
 extern int arm_volatile_func (void);
 extern const char *arm_output_epilogue (rtx);
 extern void arm_expand_prologue (void);
+extern void arm_expand_epilogue (bool);
 extern const char *arm_strip_name_encoding (const char *);
 extern void arm_asm_output_labelref (FILE *, const char *);
 extern void thumb2_asm_output_opcode (FILE *);
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index d6b4c2e..c8642e2 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -23122,6 +23122,326 @@ arm_expand_epilogue_apcs_frame (bool really_return)
   emit_jump_insn (simple_return_rtx);
 }
 
+/* Generate RTL to represent ARM epilogue.  Really_return is true if the
+   function is not a sibcall.  */
+void
+arm_expand_epilogue (bool really_return)
+{
+  unsigned long func_type;
+  unsigned long saved_regs_mask;
+  int num_regs = 0;
+  int i;
+  int amount;
+  int floats_from_frame = 0;
+  arm_stack_offsets *offsets;
+
+  func_type = arm_current_func_type ();
+
+  /* Naked functions don't have epilogue.  Hence, generate return pattern, and
+ let output_return_instruction take care of instruction emition if any.  */
+  if (IS_NAKED (func_type)
+  || (IS_VOLATILE (func_type) && TARGET_ABORT_NORETURN))
+{
+  emit_jump_insn (simple_return_rtx);
+  return;
+}
+
+  /* If we are throwing an exception, then we really must be doing a
+ return, so we can't tail-call.  */
+  gcc_assert (!crtl->calls_eh_return || really_return);
+
+  if (TARGET_APCS_FRAME && frame_pointer_needed && TARGET_ARM)
+{
+  arm_expand_epilogue_apcs_frame (really_return);
+  return;
+}
+
+  /* Get frame offsets for ARM.  */
+  offsets = arm_get_frame_offsets ();
+  saved_regs_mask = offsets->saved_regs_mask;
+
+  /* Find offset of floating point register from frame pointer.
+ The initialization is done in this way to take care of frame pointer
+ and static-chain register, if stored.  */
+  floats_from_frame = offsets->saved_args - offsets->frame;
+  /* Compute how many registers saved and how far away the floats will be.  */
+  for (i = 0; i <= LAST_ARM_REGNUM; i++)
+if (saved_regs_mask & (1 << i))
+  {
+num_regs++;
+floats_from_frame += 4;
+  }
+
+  if (frame_pointer_needed)
+{
+  /* Restore stack pointer if necessary.  */
+  if (TARGET_ARM)
+{
+  /* In ARM mode, frame pointer points to first saved register.
+ Restore stack pointer to last saved register.  */
+  amount = offsets->frame - offsets->saved_regs;
+
+  /* Force out any pending memory operations that reference stacked 
data
+ before stack de-allocation occurs.  */
+  emit_insn (gen_blockage ());
+  emit_insn (gen_addsi3 (stack_pointer_rtx,
+ hard_frame_pointer_rtx,
+ GEN_INT (amount)));
+
+  /* Emit USE(stack_pointer_rtx) to ensure that stack adjustment is not
+ deleted.  */
+  emit_insn (gen_prologue_use (stack_pointer_rtx));
+}
+  else
+{
+  /* In Thumb-2 mode, the frame pointer points to the last saved
+ register.  */
+  amount = offsets->locals_base - offsets->saved_regs;
+  if (amount)
+emit_insn (gen_addsi3 (hard_frame_pointer_rtx,
+   hard_frame_pointer_rtx,
+   GEN_INT (amount)));
+
+  /* Force out any pending memory operations that reference stacked 
data
+ before stack de-allocation occurs.  */
+  emit_insn (gen_blockage ());
+  emit_insn (gen_movsi (stack_pointer_rtx, hard_frame_pointer_rtx));
+  /* Emit USE(stack_pointer_rtx) to ensure that stack adjustment is not
+ deleted.  */
+  emit_insn (gen_prologue_use (stack_pointer_rtx));
+}
+}
+  else
+{
+  /* Pop off outgoing args and local frame to adjust stack pointer to
+ last saved register.  */
+  amount = offsets->outgoing_args - offsets->saved_regs;
+  if (amount)
+{
+  /* Force out any pending memory operations that reference stacked 
data
+ before stack de-allocation occurs.  */
+  emit_insn (gen_blockage ());
+  emit_insn (gen_addsi3 (stack_pointe

[PATCH][2/n] loop distribution TLC

[Richard Guenther]

This abstracts the notion of a partition properly so we can add
more information to it in followup patches (and not re-compute
everything all the time).

Bootstrap and regtest running on x86_64-unknown-linux-gnu.

Richard.

2012-05-31  Richard Guenther  

* tree-loop-distribution.c (struct partition_s): New struct,
typedef and vector type.
(partition_alloc, partition_free): New functions.
(generate_loops_for_partition, generate_builtin,
generate_code_for_partition, rdg_flag_uses, rdg_flag_vertex,
rdg_flag_vertex_and_dependent, rdg_flag_loop_exits,
build_rdg_partition_for_component, can_generate_builtin,
similar_memory_accesses, fuse_partitions_with_similar_memory_accesses,
rdg_build_partitions, dump_rdg_partitions, debug_rdg_partitions,
number_of_rw_in_partition, partition_contains_all_rw,
ldist_gen): Use partition_t instead of bitmap.

Index: gcc/tree-loop-distribution.c
===
*** gcc/tree-loop-distribution.c.orig   2012-05-31 15:51:46.0 +0200
--- gcc/tree-loop-distribution.c2012-05-31 15:58:12.560517791 +0200
*** along with GCC; see the file COPYING3.
*** 52,57 
--- 52,85 
  #include "tree-scalar-evolution.h"
  #include "tree-pass.h"
  
+ typedef struct partition_s
+ {
+   bitmap stmts;
+ } *partition_t;
+ 
+ DEF_VEC_P (partition_t);
+ DEF_VEC_ALLOC_P (partition_t, heap);
+ 
+ /* Allocate and initialize a partition from BITMAP.  */
+ 
+ static partition_t
+ partition_alloc (bitmap stmts)
+ {
+   partition_t partition = XCNEW (struct partition_s);
+   partition->stmts = stmts ? stmts : BITMAP_ALLOC (NULL);
+   return partition;
+ }
+ 
+ /* Free PARTITION.  */
+ 
+ static void
+ partition_free (partition_t partition)
+ {
+   BITMAP_FREE (partition->stmts);
+   free (partition);
+ }
+ 
+ 
  /* If bit I is not set, it means that this node represents an
 operation that has already been performed, and that should not be
 performed again.  This is the subgraph of remaining important
*** create_bb_after_loop (struct loop *loop)
*** 192,198 
 the code gen succeeded. */
  
  static bool
! generate_loops_for_partition (struct loop *loop, bitmap partition, bool 
copy_p)
  {
unsigned i, x;
gimple_stmt_iterator bsi;
--- 220,227 
 the code gen succeeded. */
  
  static bool
! generate_loops_for_partition (struct loop *loop, partition_t partition,
! bool copy_p)
  {
unsigned i, x;
gimple_stmt_iterator bsi;
*** generate_loops_for_partition (struct loo
*** 219,225 
basic_block bb = bbs[i];
  
for (bsi = gsi_start_phis (bb); !gsi_end_p (bsi); gsi_next (&bsi))
! if (!bitmap_bit_p (partition, x++))
reset_debug_uses (gsi_stmt (bsi));
  
for (bsi = gsi_start_bb (bb); !gsi_end_p (bsi); gsi_next (&bsi))
--- 248,254 
basic_block bb = bbs[i];
  
for (bsi = gsi_start_phis (bb); !gsi_end_p (bsi); gsi_next (&bsi))
! if (!bitmap_bit_p (partition->stmts, x++))
reset_debug_uses (gsi_stmt (bsi));
  
for (bsi = gsi_start_bb (bb); !gsi_end_p (bsi); gsi_next (&bsi))
*** generate_loops_for_partition (struct loo
*** 227,233 
gimple stmt = gsi_stmt (bsi);
if (gimple_code (stmt) != GIMPLE_LABEL
&& !is_gimple_debug (stmt)
!   && !bitmap_bit_p (partition, x++))
  reset_debug_uses (stmt);
  }
}
--- 256,262 
gimple stmt = gsi_stmt (bsi);
if (gimple_code (stmt) != GIMPLE_LABEL
&& !is_gimple_debug (stmt)
!   && !bitmap_bit_p (partition->stmts, x++))
  reset_debug_uses (stmt);
  }
}
*** generate_loops_for_partition (struct loo
*** 237,243 
basic_block bb = bbs[i];
  
for (bsi = gsi_start_phis (bb); !gsi_end_p (bsi);)
!   if (!bitmap_bit_p (partition, x++))
  {
gimple phi = gsi_stmt (bsi);
if (!is_gimple_reg (gimple_phi_result (phi)))
--- 266,272 
basic_block bb = bbs[i];
  
for (bsi = gsi_start_phis (bb); !gsi_end_p (bsi);)
!   if (!bitmap_bit_p (partition->stmts, x++))
  {
gimple phi = gsi_stmt (bsi);
if (!is_gimple_reg (gimple_phi_result (phi)))
*** generate_loops_for_partition (struct loo
*** 252,258 
  gimple stmt = gsi_stmt (bsi);
  if (gimple_code (stmt) != GIMPLE_LABEL
  && !is_gimple_debug (stmt)
! && !bitmap_bit_p (partition, x++))
{
  unlink_stmt_vdef (stmt);
  gsi_remove (&bsi, true);
--- 281,287 
  gimple stmt = gsi_stmt (bsi);
  if (gimple_code (stmt) != GIMPLE_LABEL
  && !is_gimple_debug (stmt)
! && !bitmap_bit_p (partition->stmts, x++))

[Patch, ARM][6/8] Epilogue in RTL: simple return

[Greta Yorsh]

Add a new parameter to the function output_return_instruction to handle
simple cases of return when no epilogue needs to be printed out.

ChangeLog:

gcc

2012-05-31  Ian Bolton  
Sameera Deshpande  
Greta Yorsh  

* config/arm/arm-protos.h (output_return_instruction): New
parameter.
* config/arm/arm.c (output_return_instruction): New parameter.
* config/arm/arm.md (arm_simple_return): New pattern.
(arm_return, cond_return, cond_return_inverted): Add new arguments.
* config/arm/thumb2.md (thumb2_return): Update condition and code.
diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h
index f61feef..01cd794 100644
--- a/gcc/config/arm/arm-protos.h
+++ b/gcc/config/arm/arm-protos.h
@@ -148,7 +148,7 @@ extern int arm_address_offset_is_imm (rtx);
 extern const char *output_add_immediate (rtx *);
 extern const char *arithmetic_instr (rtx, int);
 extern void output_ascii_pseudo_op (FILE *, const unsigned char *, int);
-extern const char *output_return_instruction (rtx, int, int);
+extern const char *output_return_instruction (rtx, int, int, int);
 extern void arm_poke_function_name (FILE *, const char *);
 extern void arm_final_prescan_insn (rtx);
 extern int arm_debugger_arg_offset (int, rtx);
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index c8642e2..e7a74e0 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -15592,9 +15592,11 @@ arm_get_vfp_saved_size (void)
 
 
 /* Generate a function exit sequence.  If REALLY_RETURN is false, then do
-   everything bar the final return instruction.  */
+   everything bar the final return instruction.  If simple_return is true,
+   then do not output epilogue, because it has already been emitted in RTL.  */
 const char *
-output_return_instruction (rtx operand, int really_return, int reverse)
+output_return_instruction (rtx operand, int really_return, int reverse,
+   int simple_return)
 {
   char conditional[10];
   char instr[100];
@@ -15637,7 +15639,7 @@ output_return_instruction (rtx operand, int 
really_return, int reverse)
   offsets = arm_get_frame_offsets ();
   live_regs_mask = offsets->saved_regs_mask;
 
-  if (live_regs_mask)
+  if (!simple_return && live_regs_mask)
 {
   const char * return_reg;
 
@@ -15765,7 +15767,7 @@ output_return_instruction (rtx operand, int 
really_return, int reverse)
{
  /* The return has already been handled
 by loading the LR into the PC.  */
- really_return = 0;
+  return "";
}
 }
 
diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index d1c1894..867dcbe 100644
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -8597,7 +8597,7 @@
 arm_ccfsm_state += 2;
 return \"\";
   }
-return output_return_instruction (const_true_rtx, TRUE, FALSE);
+return output_return_instruction (const_true_rtx, TRUE, FALSE, FALSE);
   }"
   [(set_attr "type" "load1")
(set_attr "length" "12")
@@ -8618,7 +8618,7 @@
 arm_ccfsm_state += 2;
 return \"\";
   }
-return output_return_instruction (operands[0], TRUE, FALSE);
+return output_return_instruction (operands[0], TRUE, FALSE, FALSE);
   }"
   [(set_attr "conds" "use")
(set_attr "length" "12")
@@ -8639,13 +8639,30 @@
 arm_ccfsm_state += 2;
 return \"\";
   }
-return output_return_instruction (operands[0], TRUE, TRUE);
+return output_return_instruction (operands[0], TRUE, TRUE, FALSE);
   }"
   [(set_attr "conds" "use")
(set_attr "length" "12")
(set_attr "type" "load1")]
 )
 
+(define_insn "*arm_simple_return"
+  [(simple_return)]
+  "TARGET_ARM"
+  "*
+  {
+if (arm_ccfsm_state == 2)
+  {
+arm_ccfsm_state += 2;
+return \"\";
+  }
+return output_return_instruction (const_true_rtx, TRUE, FALSE, TRUE);
+  }"
+  [(set_attr "type" "branch")
+   (set_attr "length" "4")
+   (set_attr "predicable" "yes")]
+)
+
 ;; Generate a sequence of instructions to determine if the processor is
 ;; in 26-bit or 32-bit mode, and return the appropriate return address
 ;; mask.
diff --git a/gcc/config/arm/thumb2.md b/gcc/config/arm/thumb2.md
index 39a2138..b7a8423 100644
--- a/gcc/config/arm/thumb2.md
+++ b/gcc/config/arm/thumb2.md
@@ -635,17 +635,12 @@
(set_attr "length" "20")]
 )
 
-;; Note: this is not predicable, to avoid issues with linker-generated
-;; interworking stubs.
 (define_insn "*thumb2_return"
-  [(return)]
-  "TARGET_THUMB2 && USE_RETURN_INSN (FALSE)"
-  "*
-  {
-return output_return_instruction (const_true_rtx, TRUE, FALSE);
-  }"
-  [(set_attr "type" "load1")
-   (set_attr "length" "12")]
+  [(simple_return)]
+  "TARGET_THUMB2"
+  "* return output_return_instruction (const_true_rtx, TRUE, FALSE, TRUE);"
+  [(set_attr "type" "branch")
+   (set_attr "length" "4")]
 )
 
 (define_insn_and_split "thumb2_eh_return"

[Patch, ARM][7/8] Epilogue in RTL: expand thumb2 return

[Greta Yorsh]

Generate RTL for return in Thumb2 mode. Used by expand of return insn.

ChangeLog:

gcc

2012-05-31  Ian Bolton  
Sameera Deshpande  
Greta Yorsh  

* config/arm/arm-protos.h (thumb2_expand_return): New declaration.
* config/arm/arm.c (thumb2_expand_return): New function.
* config/arm/arm.md (return): Update condition and code.diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h
index 01cd794..2fef0f2 100644
--- a/gcc/config/arm/arm-protos.h
+++ b/gcc/config/arm/arm-protos.h
@@ -31,6 +31,7 @@ extern int arm_volatile_func (void);
 extern const char *arm_output_epilogue (rtx);
 extern void arm_expand_prologue (void);
 extern void arm_expand_epilogue (bool);
+extern void thumb2_expand_return (void);
 extern const char *arm_strip_name_encoding (const char *);
 extern void arm_asm_output_labelref (FILE *, const char *);
 extern void thumb2_asm_output_opcode (FILE *);
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index e7a74e0..8bc6dcc 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -22841,6 +22841,52 @@ thumb1_expand_prologue (void)
 cfun->machine->lr_save_eliminated = 0;
 }
 
+/* Generate pattern *pop_multiple_with_stack_update_and_return if single
+   POP instruction can be generated.  LR should be replaced by PC.  All
+   the checks required are already done by  USE_RETURN_INSN ().  Hence,
+   all we really need to check here is if single register is to be
+   returned, or multiple register return.  */
+void
+thumb2_expand_return (void)
+{
+  int i, num_regs;
+  unsigned long saved_regs_mask;
+  arm_stack_offsets *offsets;
+
+  offsets = arm_get_frame_offsets ();
+  saved_regs_mask = offsets->saved_regs_mask;
+
+  for (i = 0, num_regs = 0; i <= LAST_ARM_REGNUM; i++)
+if (saved_regs_mask & (1 << i))
+  num_regs++;
+
+  if (saved_regs_mask)
+{
+  if (num_regs == 1)
+{
+  rtx par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (2));
+  rtx reg = gen_rtx_REG (SImode, PC_REGNUM);
+  rtx addr = gen_rtx_MEM (SImode,
+  gen_rtx_POST_INC (SImode,
+stack_pointer_rtx));
+  set_mem_alias_set (addr, get_frame_alias_set ());
+  XVECEXP (par, 0, 0) = ret_rtx;
+  XVECEXP (par, 0, 1) = gen_rtx_SET (SImode, reg, addr);
+  RTX_FRAME_RELATED_P (XVECEXP (par, 0, 1)) = 1;
+  emit_jump_insn (par);
+}
+  else
+{
+  saved_regs_mask &= ~ (1 << LR_REGNUM);
+  saved_regs_mask |=   (1 << PC_REGNUM);
+  arm_emit_multi_reg_pop (saved_regs_mask);
+}
+}
+  else
+{
+  emit_jump_insn (simple_return_rtx);
+}
+}
 
 void
 thumb1_expand_epilogue (void)
diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index 867dcbe..387ca15 100644
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -8583,8 +8583,20 @@
 
 (define_expand "return"
   [(return)]
-  "TARGET_32BIT && USE_RETURN_INSN (FALSE)"
-  "")
+  "(TARGET_ARM || (TARGET_THUMB2
+   && ARM_FUNC_TYPE (arm_current_func_type ()) == ARM_FT_NORMAL
+   && !IS_STACKALIGN (arm_current_func_type (
+&& USE_RETURN_INSN (FALSE)"
+  "
+  {
+if (TARGET_THUMB2)
+  {
+thumb2_expand_return ();
+DONE;
+  }
+  }
+  "
+)
 
 ;; Often the return insn will be the same as loading from memory, so set attr
 (define_insn "*arm_return"

Re: PATCH: PR target/53539: Different __WCHAR_TYPE__/wchar_t for gcc -m32 on Linux/i386 and Linux/x86-64

[H.J. Lu]

On Thu, May 31, 2012 at 6:50 AM, Jakub Jelinek  wrote:
> On Thu, May 31, 2012 at 06:35:19AM -0700, H.J. Lu wrote:
>> This patch makes __WCHAR_TYPE__/wchar_t the same for gcc -m32 on
>> Linux/i386 and Linux/x86-64.  OK for trunk?
>
> That looks wrong.  For Linux/i386, the 32-bit only compiler should be
> the standard, rather than x86_64 -m32 if they differ.
> So, IMHO you should keep gnu-user.h as is, and just use
> #define WCHAR_TYPE (TARGET_64BIT ? "int" : "long int")
> in gcc/config/i386/x86-64.h.
>

You are right on Linux/i386.  But we should change config/i386/gnu-user64.h,
not x86-64.h since most of other i386 OSes use int for wchar.  Also we should
check TARGET_LP64 to keep x32 as close to i386 as possible.  OK for
trunk and 4.7?

Thanks.


-- 
H.J.

2012-05-31  H.J. Lu  

PR target/53539
* config/i386/gnu-user64.h (WCHAR_TYPE): Use "int" only for
TARGET_LP64.

diff --git a/gcc/config/i386/gnu-user64.h b/gcc/config/i386/gnu-user64.h
index 0e66d26..2941332 100644
--- a/gcc/config/i386/gnu-user64.h
+++ b/gcc/config/i386/gnu-user64.h
@@ -91,3 +91,6 @@ see the files COPYING3 and COPYING.RUNTIME respectively.  If n
ot, see
 #define TARGET_THREAD_SPLIT_STACK_OFFSET \
   (TARGET_64BIT ? (TARGET_X32 ? 0x40 : 0x70) : 0x30)
 #endif
+
+#undef WCHAR_TYPE
+#define WCHAR_TYPE (TARGET_LP64 ? "int" : "long int")

[Patch, ARM][8/8] Epilogue in RTL: remove dead code

[Greta Yorsh]

As a result of the previous changes, epilogue_insns pattern can only be
generated in Thumb1. After removing other cases in define_insn for
epilogue_insns, the function arm_output_epilogue becomes dead code and can
be eliminated, along with all its helper functions.


ChangeLog:

gcc

2012-05-31  Ian Bolton  
Sameera Deshpande  
Greta Yorsh  

* config/arm/arm-protos.h (arm_output_epilogue): Remove.
* config/arm/arm.c (print_multi_reg): Remove.
(vfp_output_fldmd): Likewise.
(arm_output_epilogue): Likewise.
* config/arm/arm.md (epilogue_insns): Update condition and code.diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h
index 34de513..b97773b 100644
--- a/gcc/config/arm/arm-protos.h
+++ b/gcc/config/arm/arm-protos.h
@@ -28,7 +28,6 @@ extern int use_return_insn (int, rtx);
 extern enum reg_class arm_regno_class (int);
 extern void arm_load_pic_register (unsigned long);
 extern int arm_volatile_func (void);
-extern const char *arm_output_epilogue (rtx);
 extern void arm_expand_prologue (void);
 extern void arm_expand_epilogue (bool);
 extern void thumb2_expand_return (void);
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 903517d..712e38f 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -13886,86 +13886,6 @@ fp_const_from_val (REAL_VALUE_TYPE *r)
   gcc_unreachable ();
 }
 
-/* Output the operands of a LDM/STM instruction to STREAM.
-   MASK is the ARM register set mask of which only bits 0-15 are important.
-   REG is the base register, either the frame pointer or the stack pointer,
-   INSTR is the possibly suffixed load or store instruction.
-   RFE is nonzero if the instruction should also copy spsr to cpsr.  */
-
-static void
-print_multi_reg (FILE *stream, const char *instr, unsigned reg,
-unsigned long mask, int rfe)
-{
-  unsigned i;
-  bool not_first = FALSE;
-
-  gcc_assert (!rfe || (mask & (1 << PC_REGNUM)));
-  fputc ('\t', stream);
-  asm_fprintf (stream, instr, reg);
-  fputc ('{', stream);
-
-  for (i = 0; i <= LAST_ARM_REGNUM; i++)
-if (mask & (1 << i))
-  {
-   if (not_first)
- fprintf (stream, ", ");
-
-   asm_fprintf (stream, "%r", i);
-   not_first = TRUE;
-  }
-
-  if (rfe)
-fprintf (stream, "}^\n");
-  else
-fprintf (stream, "}\n");
-}
-
-
-/* Output a FLDMD instruction to STREAM.
-   BASE if the register containing the address.
-   REG and COUNT specify the register range.
-   Extra registers may be added to avoid hardware bugs.
-
-   We output FLDMD even for ARMv5 VFP implementations.  Although
-   FLDMD is technically not supported until ARMv6, it is believed
-   that all VFP implementations support its use in this context.  */
-
-static void
-vfp_output_fldmd (FILE * stream, unsigned int base, int reg, int count)
-{
-  int i;
-
-  /* Workaround ARM10 VFPr1 bug.  */
-  if (count == 2 && !arm_arch6)
-{
-  if (reg == 15)
-   reg--;
-  count++;
-}
-
-  /* FLDMD may not load more than 16 doubleword registers at a time. Split the
- load into multiple parts if we have to handle more than 16 registers.  */
-  if (count > 16)
-{
-  vfp_output_fldmd (stream, base, reg, 16);
-  vfp_output_fldmd (stream, base, reg + 16, count - 16);
-  return;
-}
-
-  fputc ('\t', stream);
-  asm_fprintf (stream, "fldmfdd\t%r!, {", base);
-
-  for (i = reg; i < reg + count; i++)
-{
-  if (i > reg)
-   fputs (", ", stream);
-  asm_fprintf (stream, "d%d", i);
-}
-  fputs ("}\n", stream);
-
-}
-
-
 /* OPERANDS[0] is the entire list of insns that constitute pop,
OPERANDS[1] is the base register, RETURN_PC is true iff return insn
is in the list, UPDATE is true iff the list contains explicit
@@ -16061,451 +15981,6 @@ arm_output_function_prologue (FILE *f, HOST_WIDE_INT 
frame_size)
 
 }
 
-const char *
-arm_output_epilogue (rtx sibling)
-{
-  int reg;
-  unsigned long saved_regs_mask;
-  unsigned long func_type;
-  /* Floats_offset is the offset from the "virtual" frame.  In an APCS
- frame that is $fp + 4 for a non-variadic function.  */
-  int floats_offset = 0;
-  rtx operands[3];
-  FILE * f = asm_out_file;
-  unsigned int lrm_count = 0;
-  int really_return = (sibling == NULL);
-  int start_reg;
-  arm_stack_offsets *offsets;
-
-  /* If we have already generated the return instruction
- then it is futile to generate anything else.  */
-  if (use_return_insn (FALSE, sibling) &&
-  (cfun->machine->return_used_this_function != 0))
-return "";
-
-  func_type = arm_current_func_type ();
-
-  if (IS_NAKED (func_type))
-/* Naked functions don't have epilogues.  */
-return "";
-
-  if (IS_VOLATILE (func_type) && TARGET_ABORT_NORETURN)
-{
-  rtx op;
-
-  /* A volatile function should never return.  Call abort.  */
-  op = gen_rtx_SYMBOL_REF (Pmode, NEED_PLT_RELOC ? "abort(PLT)" : "abort");
-  assemble_external_libcall (op);
-  output_asm_

Re: [Patch,AVR]: Use tr instead of set to canonicalize line endings for cmp

[Richard Henderson]

On 05/31/2012 03:47 AM, Georg-Johann Lay wrote:

* config/avr/t-avr: Correct avr-mmcu.texi dependencies.
(s-avr-mmcu-texi): Don't sed on gen-avr-mmcu-texi output.
* config/avr/gen-avr-mmcu-texi.c: Sort MCUs.
* doc/avr-mmcu.texi: Regenerate.


Ok.

Thanks for your patience.


r~

[PATCH][3/n] loop distribution TLC

[Richard Guenther]

This re-organizes builtin detection and generation properly into
an analysis and transform phase (noting that when we fail late
we will generate wrong code at the moment - eventually non-fatal,
but at least it will have duplicate work in the left-over loop).

With this in place adding more kinds of builtins to detect should
not be any rocket science anymore.

Bootstrap and regtest pending on x86_64-unknown-linux-gnu.

Richard.

2012-05-31  Richard Guenther  

* tree-loop-distribution.c (enum partition_kind): New enum.
(struct partition_s): Add kind and main_stmt members.
(partition_alloc): Initialize kind to PKIND_NORMAL.
(partition_builtin_p): New function.
(copy_loop_before): Remove failure path and assert instead.
(generate_loops_for_partition): Likewise.
(generate_memset_zero): Fold into ...
(generate_memset_builtin): ... this.
(classify_partition): New function with code from
can_generate_builtin and generate_builtin.
(generate_builtin): Remove.
(can_generate_builtin): Likewise.
(fuse_partitions_with_similar_memory_accesses): Call
partition_builtin_p instead of can_generate_builtin.
(rdg_build_partitions): Do not call
fuse_partitions_with_similar_memory_accesses here...
(ldist_gen): ... but here after classifying all partitions.
Remove failure path of generate_code_for_partition.
(generate_code_for_partition): Generate code according
to partition classification.

Index: trunk/gcc/tree-loop-distribution.c
===
*** trunk.orig/gcc/tree-loop-distribution.c 2012-05-31 15:58:12.0 
+0200
--- trunk/gcc/tree-loop-distribution.c  2012-05-31 16:26:17.255459534 +0200
*** along with GCC; see the file COPYING3.
*** 52,60 
--- 52,65 
  #include "tree-scalar-evolution.h"
  #include "tree-pass.h"
  
+ enum partition_kind { PKIND_NORMAL, PKIND_MEMSET };
+ 
  typedef struct partition_s
  {
bitmap stmts;
+   enum partition_kind kind;
+   /* Main statement a kind != PKIND_NORMAL partition is about.  */
+   gimple main_stmt;
  } *partition_t;
  
  DEF_VEC_P (partition_t);
*** partition_alloc (bitmap stmts)
*** 67,72 
--- 72,78 
  {
partition_t partition = XCNEW (struct partition_s);
partition->stmts = stmts ? stmts : BITMAP_ALLOC (NULL);
+   partition->kind = PKIND_NORMAL;
return partition;
  }
  
*** partition_free (partition_t partition)
*** 79,84 
--- 85,97 
free (partition);
  }
  
+ /* Returns true if the partition can be generated as a builtin.  */
+ 
+ static bool
+ partition_builtin_p (partition_t partition)
+ {
+   return partition->kind != PKIND_NORMAL;
+ }
  
  /* If bit I is not set, it means that this node represents an
 operation that has already been performed, and that should not be
*** copy_loop_before (struct loop *loop)
*** 183,198 
struct loop *res;
edge preheader = loop_preheader_edge (loop);
  
-   if (!single_exit (loop))
- return NULL;
- 
initialize_original_copy_tables ();
res = slpeel_tree_duplicate_loop_to_edge_cfg (loop, preheader);
free_original_copy_tables ();
  
-   if (!res)
- return NULL;
- 
update_phis_for_loop_copy (loop, res);
rename_variables_in_loop (res);
  
--- 196,206 
struct loop *res;
edge preheader = loop_preheader_edge (loop);
  
initialize_original_copy_tables ();
res = slpeel_tree_duplicate_loop_to_edge_cfg (loop, preheader);
+   gcc_assert (res != NULL);
free_original_copy_tables ();
  
update_phis_for_loop_copy (loop, res);
rename_variables_in_loop (res);
  
*** create_bb_after_loop (struct loop *loop)
*** 216,225 
 copied when COPY_P is true.  All the statements not flagged in the
 PARTITION bitmap are removed from the loop or from its copy.  The
 statements are indexed in sequence inside a basic block, and the
!basic blocks of a loop are taken in dom order.  Returns true when
!the code gen succeeded. */
  
! static bool
  generate_loops_for_partition (struct loop *loop, partition_t partition,
  bool copy_p)
  {
--- 224,232 
 copied when COPY_P is true.  All the statements not flagged in the
 PARTITION bitmap are removed from the loop or from its copy.  The
 statements are indexed in sequence inside a basic block, and the
!basic blocks of a loop are taken in dom order.  */
  
! static void
  generate_loops_for_partition (struct loop *loop, partition_t partition,
  bool copy_p)
  {
*** generate_loops_for_partition (struct loo
*** 230,242 
if (copy_p)
  {
loop = copy_loop_before (loop);
create_preheader (loop, CP_SIMPLE_PREHEADERS);
create_bb_after_loop (loop);
  }
  
-   if (loop == NULL)
- return false;
- 
/*

Prevent double free in basic_string

[tlknv]

Hi All,
I would like to propose a patch to libstdc++-v3/include/bits/basic_string.h 
that solves the problem described in the bug 21334 ( 
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=21334 ).
Briefly:
Developers often use non constant methods begin(), end(), operator [], at() for 
constant operations.
Since developers don’t modify the string they don’t expect that these 
operations are considered as not constant/modifying operations and can lead to 
double free if not protected by some mutex/lock.
The problem is caused by a potential delay in _M_grab() between making a 
positive decision (!_M_is_leaked() && __alloc1 == __alloc2) and performing the 
corresponding action ( _M_refcopy() ). 
_CharT*
_M_grab(const _Alloc& __alloc1, const _Alloc& __alloc2)
{
 return (!_M_is_leaked() && __alloc1 == __alloc2)
 ? _M_refcopy() : _M_clone(__alloc1);
}
Assume that there is std::string s1;
Some thread t2 creates a “copy” of s1: std::string s2(s1);
Copy constructor calls _M_grab. Since _M_refcount == 0 _M_grab decided to call 
_M_refcopy(). At this moment some other thread t1 calls some non-constant 
method on s1, e.g. s1.begin(). begin() calls _M_leak .. _M_leak_hard .. 
_M_set_leaked which sets _M_refcount to -1. Then _M_refcopy() in t2 is going to 
increment _M_refcount making it 0. Thus each of two basic_string objects think 
that it owns the object and will eventually free the memory allocated for the 
string. Which will cause double free and likely crash of the process.

Thanks,
Boris
--- old/libstdc++-v3/include/bits/basic_string.h	2012-05-30 17:03:15.974035000 -0400
+++ new/libstdc++-v3/include/bits/basic_string.h	2012-05-31 09:09:43.514414000 -0400
@@ -224,14 +224,20 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
 	_M_refdata() throw()
 	{ return reinterpret_cast<_CharT*>(this + 1); }
 
 	_CharT*
 	_M_grab(const _Alloc& __alloc1, const _Alloc& __alloc2)
 	{
-	  return (!_M_is_leaked() && __alloc1 == __alloc2)
-	  ? _M_refcopy() : _M_clone(__alloc1);
+  _CharT* res = (_CharT*)0;
+	  if(!_M_is_leaked() && __alloc1 == __alloc2) {
+res = _M_refcopy();
+  }
+  if (res == (_CharT*)0) {
+res = _M_clone(__alloc1);
+  }
+  return res;
 	}
 
 	// Create & Destroy
 	static _Rep*
 	_S_create(size_type, size_type, const _Alloc&);
 
@@ -259,13 +265,29 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
 	_CharT*
 	_M_refcopy() throw()
 	{
 #if _GLIBCXX_FULLY_DYNAMIC_STRING == 0
 	  if (__builtin_expect(this != &_S_empty_rep(), false))
 #endif
+  {
 __gnu_cxx::__atomic_add_dispatch(&this->_M_refcount, 1);
+// Here we try to detect and compensate an unexpected decrement of
+// _M_refcount from another thread. In the properly designed code
+// this should not happen ever! If we do nothing about this
+// condition then the string is going to be freed twice.
+// Unfortunatelly, some cases that lead to this condition are not
+// obvious for the developers, e.g. non-constant
+// methods operator [], at(), begin, end, etc.
+// In many of these cases the string is not going to be
+// changed from another thread and it's actually safe to
+// clone the string.
+if (!this->_M_is_shared()) {
+  __gnu_cxx::__atomic_add_dispatch(&this->_M_refcount, -1);
+  return (_CharT*)0;
+}
+  }
 	  return _M_refdata();
 	}  // XXX MT
 
 	_CharT*
 	_M_clone(const _Alloc&, size_type __res = 0);
   };

Re: [C++ Patch] PR 53524

[Jason Merrill]

Does the C front end warn about this mismatch?  Do we warn about 
mismatch in comparisons?


Jason

[Patch,AVR]: Fix PR46261

[Georg-Johann Lay]

This fixes ICE on any source compiled with -mint8.
Missing definition of UINT16_TYPE (defined to 0) crashed
the compiler when it tries to build wchar stuff.

As mentioned in the PR, I chose to add the stdint stuff
as a new file.

The -mint8 part is only lightly tested because there is no
test suite for the non-C compliant code it generates.

Without -mint8 avr-stdint.h mimics as many as possible definitions
from newlib-stdint.h but for 2 cases where it deviates:

- SIG_ATOMIC_TYPE is 8-bit, AVR cannot access 16 bits atomically

- [U]INT_FAST8_TYPE is 8-bit because AVR is an 8-bit machine

Ok to install?

Johann

PR target/46261
* config/avr/avr-stdint.h: New file.
* config.gcc (avr-*-*,tm_file): Use avr/avr-stdint.h instead of
newlib-stdint.h
Index: config.gcc
===
--- config.gcc	(revision 187704)
+++ config.gcc	(working copy)
@@ -926,7 +926,7 @@ avr-*-rtems*)
 	extra_objs="avr-devices.o avr-log.o"
 	;;
 avr-*-*)
-	tm_file="elfos.h avr/elf.h avr/avr.h dbxelf.h newlib-stdint.h"
+	tm_file="elfos.h avr/elf.h avr/avr.h dbxelf.h avr/avr-stdint.h"
 	tmake_file="avr/t-avr avr/t-multilib"
 	use_gcc_stdint=wrap
 	extra_gcc_objs="driver-avr.o avr-devices.o"
Index: config/avr/avr-stdint.h
===
--- config/avr/avr-stdint.h	(revision 0)
+++ config/avr/avr-stdint.h	(revision 0)
@@ -0,0 +1,66 @@
+/* Definitions for  types on systems using newlib.
+   Copyright (C) 2012 Free Software Foundation, Inc.
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 3, or (at your option)
+any later version.
+
+GCC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GCC; see the file COPYING3.  If not see
+.  */
+
+/*
+   The intention of this file is to supply definitions that work with
+   avr-gcc's -mint8 that sets int to an 8-bit type.
+
+   This file is intended to yield the same results as newlib-stdint.h,
+   but there are some differences to newlib-stdint.h:
+
+   - AVR is an 8-bit architecture that cannot access 16-bit values
+ atomically, this SIG_ATOMIC_TYPE is "char".
+
+   - For the same reason, [u]int_fast8_t is defined as 8-bit type.
+
+*/
+   
+#define SIG_ATOMIC_TYPE "char"
+
+#define INT8_TYPE "signed char"
+#define INT16_TYPE (INT_TYPE_SIZE == 16 ? "short int" : "long int")
+#define INT32_TYPE (INT_TYPE_SIZE == 16 ? "long int" : "long long int")
+#define INT64_TYPE (INT_TYPE_SIZE == 16 ? "long long int" : 0)
+#define UINT8_TYPE "unsigned char"
+#define UINT16_TYPE (INT_TYPE_SIZE == 16 ? "short unsigned int" : "long unsigned int")
+#define UINT32_TYPE (INT_TYPE_SIZE == 16 ? "long unsigned int" : "long long unsigned int")
+#define UINT64_TYPE (INT_TYPE_SIZE == 16 ? "long long unsigned int" : 0)
+
+#define INT_LEAST8_TYPE INT8_TYPE
+#define INT_LEAST16_TYPE INT16_TYPE
+#define INT_LEAST32_TYPE INT32_TYPE
+#define INT_LEAST64_TYPE INT64_TYPE
+#define UINT_LEAST8_TYPE UINT8_TYPE
+#define UINT_LEAST16_TYPE UINT16_TYPE
+#define UINT_LEAST32_TYPE UINT32_TYPE
+#define UINT_LEAST64_TYPE UINT64_TYPE
+
+#define INT_FAST8_TYPE INT8_TYPE
+#define INT_FAST16_TYPE (INT_TYPE_SIZE == 16 ? "int" : INT16_TYPE)
+#define INT_FAST32_TYPE INT32_TYPE
+#define INT_FAST64_TYPE INT64_TYPE
+#define UINT_FAST8_TYPE UINT8_TYPE
+#define UINT_FAST16_TYPE (INT_TYPE_SIZE == 16 ? "unsigned int" : UINT16_TYPE)
+#define UINT_FAST32_TYPE UINT32_TYPE
+#define UINT_FAST64_TYPE UINT64_TYPE
+
+#define INTPTR_TYPE PTRDIFF_TYPE
+#ifndef UINTPTR_TYPE
+#define UINTPTR_TYPE SIZE_TYPE
+#endif

Re: [C++ Patch] PR 53524

[Paolo Carlini]

(resending to the mailing list because due to html content)

On 05/31/2012 04:43 PM, Jason Merrill wrote:

Does the C front end warn about this mismatch?


I just tried the first test of g++.old-deja/g++.other/cond5.C and the C 
front-end does *not* warn neither by default, neither with -Wall.



  Do we warn about mismatch in comparisons?


Comparisons are dealt with separately, we have -Wenum-compare:

|-Wenum-compare|
   Warn about a comparison between values of different enumerated
   types. In C++ this warning is enabled by default. In C this warning
   is enabled by -Wall.

Paolo.

[PATCH] Fix PR53541

[Richard Guenther]

This backports a fix for dumping.

Built and tested on x86_64-unknown-linux-gnu, applied.

Richard.

2012-05-31  Richard Guenther  

PR middle-end/53541
* tree-pretty-print.c (dump_generic_node): Guard against
NULL_TREE TREE_TYPE when dumping MEM_REF offset type.

Index: gcc/tree-pretty-print.c
===
--- gcc/tree-pretty-print.c (revision 188064)
+++ gcc/tree-pretty-print.c (working copy)
@@ -805,6 +805,8 @@ dump_generic_node (pretty_printer *buffe
   infer them and MEM_ATTR caching will share MEM_REFs
   with differently-typed op0s.  */
&& TREE_CODE (TREE_OPERAND (node, 0)) != INTEGER_CST
+   /* Released SSA_NAMES have no TREE_TYPE.  */
+   && TREE_TYPE (TREE_OPERAND (node, 0)) != NULL_TREE
/* Same pointer types, but ignoring POINTER_TYPE vs.
   REFERENCE_TYPE.  */
&& (TREE_TYPE (TREE_TYPE (TREE_OPERAND (node, 0)))
@@ -1171,6 +1173,8 @@ dump_generic_node (pretty_printer *buffe
 can't infer them and MEM_ATTR caching will share
 MEM_REFs with differently-typed op0s.  */
  && TREE_CODE (TREE_OPERAND (op0, 0)) != INTEGER_CST
+ /* Released SSA_NAMES have no TREE_TYPE.  */
+ && TREE_TYPE (TREE_OPERAND (op0, 0)) != NULL_TREE
  /* Same pointer types, but ignoring POINTER_TYPE vs.
 REFERENCE_TYPE.  */
  && (TREE_TYPE (TREE_TYPE (TREE_OPERAND (op0, 0)))

[AARCH64][libgcc] Add __aarch64_sync_cache_range as lib2func

[Jim MacArthur]

This patch makes __aarch64_sync_cache_range a LIB2ADD and removes it
from lib1funcs.S. Since it is the only function in lib1funcs.S, that
file can be removed. It also changes the functionality of
__aarch64_sync_cache_range to use userland instructions instead of an
exception.

This should be applied after the patch I suggested for t-aarch64:
http://gcc.gnu.org/ml/gcc-patches/2012-05/msg01884.html.

Additions to libgcc/ChangeLog:
2012-05-31 Jim MacArthur

* config.host (aarch64*-*-elf): Add t-aarch64.
(aarch64*-*-linux*): Add t-aarch64, remove t-linux.
* config/aarch64/lib1funcs.S: Delete.
* config/aarch64/sync-cache.S: New file.
* config/aarch64/t-aarch64: New file.
* config/aarch64/t-linux: Delete.


diff --git a/libgcc/config.host b/libgcc/config.host
index 56beddd..5a05c93 100644
--- a/libgcc/config.host
+++ b/libgcc/config.host
@@ -291,14 +291,15 @@ case ${host} in
;;
 aarch64*-*-elf)
extra_parts="$extra_parts crtbegin.o crtend.o crti.o crtn.o"
+   tmake_file="${tmake_file} ${cpu_type}/t-aarch64"
tmake_file="${tmake_file} t-softfp-sfdf t-softfp-excl"
tmake_file="${tmake_file} ${cpu_type}/t-softfp t-softfp"
;;
 aarch64*-*-linux*)
md_unwind_header=aarch64/linux-unwind.h
+   tmake_file="${tmake_file} ${cpu_type}/t-aarch64"
tmake_file="${tmake_file} t-softfp-sfdf t-softfp-excl"
tmake_file="${tmake_file} ${cpu_type}/t-softfp t-softfp"
-   tmake_file="${tmake_file} ${cpu_type}/t-linux"
;;
 alpha*-*-linux*)
tmake_file="${tmake_file} alpha/t-alpha alpha/t-ieee t-crtfm 
alpha/t-linux"
diff --git a/libgcc/config/aarch64/lib1funcs.S 
b/libgcc/config/aarch64/lib1funcs.S
deleted file mode 100644
index 5123609..000
--- a/libgcc/config/aarch64/lib1funcs.S
+++ /dev/null
@@ -1,73 +0,0 @@
-/* libgcc routines for AArch64
-
-   Copyright (C) 2009, 2010, 2011, 2012 Free Software Foundation, Inc.
-   Contributed by ARM Ltd.
-
-   This file is free software; you can redistribute it and/or modify it
-   under the terms of the GNU General Public License as published by the
-   Free Software Foundation; either version 3, or (at your option) any
-   later version.
-
-   This file is distributed in the hope that it will be useful, but
-   WITHOUT ANY WARRANTY; without even the implied warranty of
-   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-   General Public License for more details.
-
-   Under Section 7 of GPL version 3, you are granted additional
-   permissions described in the GCC Runtime Library Exception, version
-   3.1, as published by the Free Software Foundation.
-
-   You should have received a copy of the GNU General Public License and
-   a copy of the GCC Runtime Library Exception along with this program;
-   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
-   .  */
-
-/* We need to know what prefix to add to function names.  */
-
-#ifndef __USER_LABEL_PREFIX__
-#error  __USER_LABEL_PREFIX__ not defined
-#endif
-
-/* ANSI concatenation macros.  */
-
-#define CONCAT1(a, b) CONCAT2(a, b)
-#define CONCAT2(a, b) a ## b
-
-/* Use the right prefix for global labels.  */
-
-#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x)
-
-#ifdef __ELF__
-#define TYPE(x) .type SYM(x),function
-#define SIZE(x) .size SYM(x), . - SYM(x)
-#define LSYM(x) .x
-#else
-#define TYPE(x)
-#define SIZE(x)
-#define LSYM(x) x
-#endif
-
-.macro FUNC_START name
-   .text
-   .globl SYM (__\name)
-   TYPE (__\name)
-   .align 2
-SYM (__\name):
-.endm
-
-.macro FUNC_END name
-   SIZE (__\name)
-.endm
-
-#ifdef L_aarch64_sync_cache_range
-#if defined __linux__
-   FUNC_START aarch64_sync_cache_range
-   mov x3, 0
-   mov x8, 0x1002
-   svc 0
-   RET
-   FUNC_END aarch64_sync_cache_range
-#else
-#error "This is only for AARCH64 GNU/Linux"
-#endif
-#endif
\ No newline at end of file
diff --git a/libgcc/config/aarch64/t-aarch64 b/libgcc/config/aarch64/t-aarch64
new file mode 100644
index 000..002cb83
--- /dev/null
+++ b/libgcc/config/aarch64/t-aarch64
@@ -0,0 +1,21 @@
+# Machine description for AArch64 architecture.
+# Copyright (C) 2012 Free Software Foundation, Inc.
+# Contributed by ARM Ltd.
+#
+# This file is part of GCC.
+#
+# GCC is free software; you can redistribute it and/or modify it
+# under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3, or (at your option)
+# any later version.
+#
+# GCC is distributed in the hope that it will be useful, but
+# WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+# General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with GCC; see the file COPYING3.  If not see
+# .
+
+LIB2ADD += $(srcdir)/config/aar

[PATCH] Fix PR53471, remove DECL_ASSEMBLER_NAME deferred compute

[Richard Guenther]

This removes defering DECL_ASSEMBLER_NAME computation inside dwarf2out.c,
something which is not possible when LTO is enabled during compilation
as we free up tree fields after we think the frontend is finished - but
DECL_ASSEMBLER_NAME computation involves a langhook and frontend specific
data.  In theory we try hard to properly assign assembler names for
everything reachable in free_lang_data, but the frontend hands even
"unreachable" types to dwarf2out via rest_of_type_compilation
and debug_hooks->type_decl.

Another approach would be to only call add_linkage_attr if the
assembler name was set meanwhile by other means, thus

Index: gcc/dwarf2out.c
===
--- gcc/dwarf2out.c (revision 188063)
+++ gcc/dwarf2out.c (working copy)
@@ -22158,7 +22158,8 @@ dwarf2out_finish (const char *filename)
   for (node = deferred_asm_name; node; node = node->next)
 {
   tree decl = node->created_for;
-  if (DECL_ASSEMBLER_NAME (decl) != DECL_NAME (decl))
+  if (DECL_ASSEMBLER_NAME_SET_P (decl)
+ && DECL_ASSEMBLER_NAME (decl) != DECL_NAME (decl))
{
  add_linkage_attr (node->die, decl);
  move_linkage_attr (node->die);

But I bootstrapped and tested the following variant instead
which generates the same code and debuginfo with -O0 -g for
tramp3d at the cost of a 0.01% compile-time hit (not sure,
but I suppose the deferral was for a reason?).

Ok?

Thanks,
Richard.

2012-05-31  Richard Guenther  

PR debug/53471
* dwarf2out.c (deferred_asm_name): Remove.
(add_linkage_name): Force DECL_ASSEMBLER_NAME creation here.
(move_linkage_attr): Remove.
(dwarf2out_finish): Do not process deferred_asm_name.

Index: gcc/dwarf2out.c
===
--- gcc/dwarf2out.c (revision 188056)
+++ gcc/dwarf2out.c (working copy)
@@ -2652,10 +2652,6 @@ static GTY(()) comdat_type_node *comdat_
 /* A list of DIEs with a NULL parent waiting to be relocated.  */
 static GTY(()) limbo_die_node *limbo_die_list;
 
-/* A list of DIEs for which we may have to generate
-   DW_AT_{,MIPS_}linkage_name once their DECL_ASSEMBLER_NAMEs are set.  */
-static GTY(()) limbo_die_node *deferred_asm_name;
-
 /* Filenames referenced by this compilation unit.  */
 static GTY((param_is (struct dwarf_file_data))) htab_t file_table;
 
@@ -15394,22 +15390,9 @@ add_linkage_name (dw_die_ref die, tree d
&& TREE_PUBLIC (decl)
&& !DECL_ABSTRACT (decl)
&& !(TREE_CODE (decl) == VAR_DECL && DECL_REGISTER (decl))
-   && die->die_tag != DW_TAG_member)
-{
-  /* Defer until we have an assembler name set.  */
-  if (!DECL_ASSEMBLER_NAME_SET_P (decl))
-   {
- limbo_die_node *asm_name;
-
- asm_name = ggc_alloc_cleared_limbo_die_node ();
- asm_name->die = die;
- asm_name->created_for = decl;
- asm_name->next = deferred_asm_name;
- deferred_asm_name = asm_name;
-   }
-  else if (DECL_ASSEMBLER_NAME (decl) != DECL_NAME (decl))
-   add_linkage_attr (die, decl);
-}
+   && die->die_tag != DW_TAG_member
+   && DECL_ASSEMBLER_NAME (decl) != DECL_NAME (decl))
+add_linkage_attr (die, decl);
 }
 
 /* Add a DW_AT_name attribute and source coordinate attribute for the
@@ -21161,37 +21144,6 @@ htab_ct_eq (const void *of1, const void
 DWARF_TYPE_SIGNATURE_SIZE));
 }
 
-/* Move a DW_AT_{,MIPS_}linkage_name attribute just added to dw_die_ref
-   to the location it would have been added, should we know its
-   DECL_ASSEMBLER_NAME when we added other attributes.  This will
-   probably improve compactness of debug info, removing equivalent
-   abbrevs, and hide any differences caused by deferring the
-   computation of the assembler name, triggered by e.g. PCH.  */
-
-static inline void
-move_linkage_attr (dw_die_ref die)
-{
-  unsigned ix = VEC_length (dw_attr_node, die->die_attr);
-  dw_attr_node linkage = *VEC_index (dw_attr_node, die->die_attr, ix - 1);
-
-  gcc_assert (linkage.dw_attr == DW_AT_linkage_name
- || linkage.dw_attr == DW_AT_MIPS_linkage_name);
-
-  while (--ix > 0)
-{
-  dw_attr_node *prev = VEC_index (dw_attr_node, die->die_attr, ix - 1);
-
-  if (prev->dw_attr == DW_AT_decl_line || prev->dw_attr == DW_AT_name)
-   break;
-}
-
-  if (ix != VEC_length (dw_attr_node, die->die_attr) - 1)
-{
-  VEC_pop (dw_attr_node, die->die_attr);
-  VEC_quick_insert (dw_attr_node, die->die_attr, ix, &linkage);
-}
-}
-
 /* Helper function for resolve_addr, mark DW_TAG_base_type nodes
referenced from typed stack ops and count how often they are used.  */
 
@@ -22155,18 +22107,6 @@ dwarf2out_finish (const char *filename)
   resolve_addr (comp_unit_die ());
   move_marked_base_types ();
 
-  for (node = deferred_asm_name; node; node = node->next)
-{
-  tree decl = node->created_for;
-  if (DECL_ASS

Re: Use C++ in COMPILER_FOR_BUILD if needed (issue6191056)

[DJ Delorie]

> OK to commit this amended patch?

Ok.  Do we have a build-with-c++ FAQ page anywhere?  /me thinks it
will be useful soon ;-)

Re: Prevent double free in basic_string

[Marc Glisse]

On Thu, 31 May 2012, tlknv wrote:

I would like to propose a patch to 
libstdc++-v3/include/bits/basic_string.h that solves the problem 
described in the bug 21334 ( 
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=21334 ).


Hello,

correct me if I am wrong, but this patch doesn't aim to fix the issue, 
just paper over the most likely case to reduce the likelihood of a race, 
right?


--
Marc Glisse

[patch] Fix many Makefile dependencies, round 3

[Steven Bosscher]

Hello,

A smaller patch this time, but bigger impact: GIMPLE_H does not have
to depend on TARGET_H. Only a few files need TARGET_H as well as
GIMPLE_H, and most of them already included TARGET_H anyway. The ones
that don't, are fixed with this patch.

Bootstrapped&tested on powerpc64-unknown-linux-gnu, and verified that
my contrib/check_makefile_deps.sh output has no new missing
dependencies (and far fewer unneeded deps). OK?

Ciao!
Steven


fix_Makefile_in_3.diff
Description: Binary data

patch to clean up the many ways of saying 2 * HOST_BITS_PER_WIDE_INT

[Kenneth Zadeck]

This patch replaces the large number of spellings of "2 * 
HOST_BITS_PER_WIDE_INT" with the existing preprocessor symbol 
HOST_BITS_PER_DOUBLE_INT.


Even though this is a large patch, it is trivial and so unless i hear 
some objections, i will check it in soon.

the patch has been bootstrapped on x86-64.

2012-05-31  Kenneth Zadeck 

* expmed.c (expand_mult, choose_multiplier): Change "2 *
HOST_BITS_PER_WIDE_INT" to "HOST_BITS_PER_DOUBLE_INT".
* expr.c (convert_modes): Likewise.
* explow.c (plus_constant): Likewise.
* fixed-value.c (fixed_saturate1, fixed_saturate2)
(do_fixed_add, do_fixed_multiply, do_fixed_multiply)
(do_fixed_multiply, do_fixed_multiply, do_fixed_divide)
(do_fixed_divide, do_fixed_divide, do_fixed_divide)
(do_fixed_divide, do_fixed_divide, do_fixed_shift, do_fixed_shift)
(do_fixed_shift, fixed_convert, fixed_convert)
(fixed_convert_from_int, fixed_convert_from_int)
(fixed_convert_from_real): Likewise.
* fold-const.c (fold_convert_const_int_from_fixed, sign_bit_p)
(native_interpret_int, fold_binary_loc, fold_ternary_loc): Likewise.
* varasm.c (output_constructor_bitfield): Likewise.
* tree-vrp.c (register_edge_assert_for_2): Likewise.
* double-int.c (rshift_double, lshift_double): Likewise.
* double-int.h (double_int_fits_in_uhwi_p, double_int, double_int): 
Likewise.

* simplify-rtx.c (mode_signbit_p)
(simplify_const_unary_operation, simplify_binary_operation_1)
(simplify_immed_subreg): Likewise.
* builtins.c (c_readstr, fold_builtin_bitop): Likewise.
* tree-vect-generic.c (build_replicated_const): Likewise.
* dbxout.c (stabstr_O): Likewise.
* emit-rtl.c (immed_double_int_const, immed_double_const)
(gen_lowpart_common, init_emit_once): Likewise.
* tree.c (integer_pow2p, tree_log2, tree_floor_log2)
(widest_int_cst_value, upper_bound_in_type): Likewise.
* stor-layout.c (initialize_sizetypes, fixup_signed_type)
(fixup_unsigned_type): Likewise.
* real.c (real_to_integer2, real_from_integer): Likewise.
* dwarf2out.c (size_of_loc_descr, size_of_die, output_die)
(clz_loc_descriptor, mem_loc_descriptor): Likewise.

Index: expmed.c
===
--- expmed.c	(revision 188063)
+++ expmed.c	(working copy)
@@ -3155,8 +3155,8 @@ expand_mult (enum machine_mode mode, rtx
 	{
 	  int shift = floor_log2 (CONST_DOUBLE_HIGH (op1))
 			  + HOST_BITS_PER_WIDE_INT;
-	  if (shift < 2 * HOST_BITS_PER_WIDE_INT - 1
-		  || GET_MODE_BITSIZE (mode) <= 2 * HOST_BITS_PER_WIDE_INT)
+	  if (shift < HOST_BITS_PER_DOUBLE_INT - 1
+		  || GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_DOUBLE_INT)
 		return expand_shift (LSHIFT_EXPR, mode, op0,
  shift, target, unsignedp);
 	}
@@ -3316,7 +3316,7 @@ choose_multiplier (unsigned HOST_WIDE_IN
   /* We could handle this with some effort, but this case is much
  better handled directly with a scc insn, so rely on caller using
  that.  */
-  gcc_assert (pow != 2 * HOST_BITS_PER_WIDE_INT);
+  gcc_assert (pow != HOST_BITS_PER_DOUBLE_INT);
 
   /* mlow = 2^(N + lgup)/d */
  if (pow >= HOST_BITS_PER_WIDE_INT)
Index: expr.c
===
--- expr.c	(revision 188063)
+++ expr.c	(working copy)
@@ -723,7 +723,7 @@ convert_modes (enum machine_mode mode, e
  make the high-order word of the constant zero, not all ones.  */
 
   if (unsignedp && GET_MODE_CLASS (mode) == MODE_INT
-  && GET_MODE_BITSIZE (mode) == 2 * HOST_BITS_PER_WIDE_INT
+  && GET_MODE_BITSIZE (mode) == HOST_BITS_PER_DOUBLE_INT
   && CONST_INT_P (x) && INTVAL (x) < 0)
 {
   double_int val = uhwi_to_double_int (INTVAL (x));
Index: explow.c
===
--- explow.c	(revision 188063)
+++ explow.c	(working copy)
@@ -127,7 +127,7 @@ plus_constant (enum machine_mode mode, r
 	if (add_double_with_sign (l1, h1, l2, h2, &lv, &hv, false))
 	  /* Sorry, we have no way to represent overflows this wide.
 	 To fix, add constant support wider than CONST_DOUBLE.  */
-	  gcc_assert (GET_MODE_BITSIZE (mode) <= 2 * HOST_BITS_PER_WIDE_INT);
+	  gcc_assert (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_DOUBLE_INT);
 
 	return immed_double_const (lv, hv, VOIDmode);
   }
Index: fixed-value.c
===
--- fixed-value.c	(revision 188063)
+++ fixed-value.c	(working copy)
@@ -177,7 +177,7 @@ fixed_saturate1 (enum machine_mode mode,
   min.high = 0;
   min.low = 1;
   lshift_double (min.low, min.high, i_f_bits,
-		 2 * HOST_BITS_PER_WIDE_INT,
+		 HOST_BITS_PER_DOUBLE_INT,
 		 &min.low, &min.high, 1);
   min = double_int_ext (min, 1 + i_f_bits, 0);
   if (double_int_cmp (a, max, 0) == 1)
@@ -245,7 +245,7 @@ fixed_saturate2 (enum machine_mode mode,
   min_s.high = 0;
   min_s.low = 1;
   lshift_double (min_

[PATCH] [RFC] Add configuration support for additional executable/library directories

[Michael Meissner]

For some time now, I've wanted to add configuration support to add additional
directories for the compiler to search automatically, without having to edit
local files in my directory.

I have some questions about these patches, that I will put after the
explanation of the functionality.

One of the motivations is to tie into the installed IBM Advance Toolchain (AT),
which provides newer compilers and libraries to Power customers who need
facilities in the newer compilers, that aren't yet a part of the standard GCC
that is shipped with the distribution.  While the AT is a motivation, I'm
trying to write these patches to be more general.

The AT provides its own libraries, both static and shared that are built for
serveral different targets (power5, power6, power7, etc.).  It is not a
--sysroot type of release, because if a given library is not provided, it will
default to using the host libraries on the system.  The AT has its own dynamic
linker as well as the normal binutils and compiler binaries.

These patches add 4 configuration switches that add additional directories to
the search paths:

--with-extra-exec-prefix=

Add extra directories to the executable search path.  You can have more
that one directory, separated by colon's (":").  For example, to use
the binaries in /opt/at5.0/bin, I would do:

--with-extra-exec-prefix=/opt/at5.0/bin

--with-extra-startfile-prefix=

Add extra directories to the startfile and library search path.  You
can have more than one directory, separated by colon's.  In multilib
systems, the multilib prefix will be appended to this prefix to find
the correct multilib.  For example to use the libraries and startfiles
in /opt/at5.0/lib, I would do:

--with-extra-startfile-prefix=/opt/at5.0/lib

--with-extra-rpath-prefix=

Add extra directories via -rpath unless -static is used when linking.
Like the startfile prefix, this is appended with the current multilib
prefix to get the appropriate directory.  For example, with the Advance
Toolchain 5.0, I would use:

--with-extra-rpath-prefix=/opt/at5.0/lib

--with-extra-prefixes=

This is a combination option, that sets --with-extra-exec-prefixes,
--with-extra-startfile-prefixes, and --with-extra-rpath-prefixes if
they were not already set.  For example:

--with-extra-prefix=/opt/at5.0:/opt/at4.0

would be equivalent to:

--with-extra-exec-prefix=/opt/at5.0/bin:/opt/at4.0/bin
--with-extra-startfile-prefix=/opt/at5.0/lib:/opt/at4.0/lib
--with-extra-rpath-prefix=/opt/at5.0/lib:/opt/at4.0/lib

In the machine independent part of the patches, it will use the exec prefixes
to look up executables, it will add -L  for each of the startfile prefixed
directories when linking, and if -static is not used will add -rpath for each
of the directories in the rpath directories.

In the powerpc part of the patches, it will add code to look up the dynamic
linker in the prefixes, and to add -L/ if the user did
-mcpu= and -static to pick up the machine specific static libraries.
This code uses spec functions provided by gcc.c, so it is fairly easy to add
similar support to other targets.

My questions are:

1) Do people want this functionality in GCC?  If it isn't desirable to put in
   the general options, would people have objections if I put in
   powerpc64-linux specific configure options to accomplish the same thing?

2) In terms of the shared library paths, I am not up on all of the ins and outs
   of the various ways these paths get set (via -rpath=, -rpath-dir=, looking
   at LD_RUN_PATH if -rpath is not specified, and with/without the option
   --enable-new-dtags).  Is the current patch appropriate, or are there better
   ways to add directories to the path?  The current path adds the directories
   via -rpath.  If LD_RUN_PATH is set, it will also add the directories in
   LD_RUN_PATH, since the linker will only look at LD_RUN_PATH if -rpath is not
   set. 

3) Should I include a prefix option for finding include files?

4) Did we want to update other backends to look at dynamic linkers and machine
   dependent static libraries like I did for the powerpc.

Here is the ChangeLog.

2012-05-30  Michael Meissner  

* doc/install.texi (--with-extra-prefix=): Add new configuration
switches to specify alternate compiler binary, startfile and
library directories at configure time.  This allows the configured
compiler to use these alternate paths ahead of the standard paths,
but to fall back to using the standard paths if the executable or
library doesn't exist.  For static links, support a new spec
function to allow the backend to specify machine dependent
subdirectories to get access to a library compiled for a
particular machine.  For dynamic libr

Re: Prevent double free in basic_string

[tlknv]

Actually, for number of threads >=3 this patch is better:--- old/libstdc++-v3/include/bits/basic_string.h	2012-05-30 17:03:15.974035000 -0400
+++ new/libstdc++-v3/include/bits/basic_string.h	2012-05-31 13:06:39.903442000 -0400
@@ -224,14 +224,20 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
 	_M_refdata() throw()
 	{ return reinterpret_cast<_CharT*>(this + 1); }
 
 	_CharT*
 	_M_grab(const _Alloc& __alloc1, const _Alloc& __alloc2)
 	{
-	  return (!_M_is_leaked() && __alloc1 == __alloc2)
-	  ? _M_refcopy() : _M_clone(__alloc1);
+  _CharT* res = (_CharT*)0;
+	  if(!_M_is_leaked() && __alloc1 == __alloc2) {
+res = _M_refcopy();
+  }
+  if (res == (_CharT*)0) {
+res = _M_clone(__alloc1);
+  }
+  return res;
 	}
 
 	// Create & Destroy
 	static _Rep*
 	_S_create(size_type, size_type, const _Alloc&);
 
@@ -259,13 +265,28 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
 	_CharT*
 	_M_refcopy() throw()
 	{
 #if _GLIBCXX_FULLY_DYNAMIC_STRING == 0
 	  if (__builtin_expect(this != &_S_empty_rep(), false))
 #endif
-__gnu_cxx::__atomic_add_dispatch(&this->_M_refcount, 1);
+  {
+// Here we try to detect and compensate an unexpected decrement of
+// _M_refcount from another thread. In the properly designed code
+// this should not happen ever! If we do nothing about this
+// condition then the string is going to be freed twice.
+// Unfortunatelly, some cases that lead to this condition are not
+// obvious for the developers, e.g. non-constant
+// methods operator [], at(), begin, end, etc.
+// In many of these cases the string is not going to be
+// changed from another thread and it's actually safe to
+// clone the string.
+if (__gnu_cxx::__exchange_and_add_dispatch(&this->_M_refcount, 1) < 0) {
+  __gnu_cxx::__atomic_add_dispatch(&this->_M_refcount, -1);
+  return (_CharT*)0;
+}
+  }
 	  return _M_refdata();
 	}  // XXX MT
 
 	_CharT*
 	_M_clone(const _Alloc&, size_type __res = 0);
   };

Re: PowerPC prologue and epilogue 6

[Mike Stump]

On May 31, 2012, at 6:42 AM, Dominique Dhumieres wrote:
>> This is really stretching my testsuite knowledge.  Maybe add
>> 
>> /* { dg-additional-options "-mdynamic-no-pic" { target *-*-darwin* } } */
> 
> Using
> 
> /* { dg-options "-fno-inline -fomit-frame-pointer" } */
> /* { dg-additional-options "-mdynamic-no-pic" { target *-*-darwin* } } */
> 
> works for me on powerpc-apple-darwin9, but I can't test it on nondarwin 
> powerpc.

Looks good...

Re: Use C++ in COMPILER_FOR_BUILD if needed (issue6191056)

[Diego Novillo]

On 12-05-31 11:58 , DJ Delorie wrote:

OK to commit this amended patch?


Ok.


Thanks. Committed.


Do we have a build-with-c++ FAQ page anywhere?  /me thinks it
will be useful soon ;-)


Not yet.  If there are any FAQs, I propose adding them to 
http://gcc.gnu.org/wiki/cxx-conversion and then move them to the main 
FAQ page once the branch is merged.



Diego.

[AVR,Committed]: Update documentation

[Georg-Johann Lay]

Finally, I decided to document the new -msp8 option. It's always bad idea to
have undocumented stuff...

http://gcc.gnu.org/viewcvs?view=revision&revision=188070

Also flushed the 4.7 documentation to be the same as trunk:

http://gcc.gnu.org/viewcvs?view=revision&revision=188071

Johann

[contrib] New script to create ChangeLog entries (issue6259058)

[Diego Novillo]

Add new skeleton ChangeLog file generator to contrib/

This script analyzes a .diff file and generates a skeleton ChangeLog
entry for it.  It tries fairly hard to find function names, so it's
important to use the -p switch with diff.

I wrote the initial code a while ago.  Cary added a bunch of smarts to
make it understand C++ and guess the function names better than the
original version.

Committed to trunk rev 188072.

2012-05-31   Diego Novillo  
 Cary Coutant  

* mklog: New.

diff --git a/contrib/mklog b/contrib/mklog
new file mode 100755
index 000..70308ab
--- /dev/null
+++ b/contrib/mklog
@@ -0,0 +1,151 @@
+#!/usr/bin/perl
+# Copyright (C) 2012 Free Software Foundation, Inc.
+#
+# This file is part of GCC.
+#
+# GCC is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3, or (at your option)
+# any later version.
+#
+# GCC is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with GCC; see the file COPYING.  If not, write to
+# the Free Software Foundation, 51 Franklin Street, Fifth Floor,
+# Boston, MA 02110-1301, USA.
+
+# This script parses a .diff file generated with 'diff -up' or 'diff -cp'
+# and writes a skeleton ChangeLog file to stdout. It does not try to be
+# very smart when parsing function names, but it produces a reasonable
+# approximation.
+#
+# Author: Diego Novillo  and
+# Cary Coutant 
+
+# Change these settings to reflect your profile.
+$username = $ENV{'USER'};
+$name = `finger $username | grep -o 'Name: .*'`;
+@n = split(/:/, $name);
+$name = @n[1]; chop($name);
+$addr = $username . "\@my.domain.org";
+$date = `date +%Y-%m-%d`; chop ($date);
+
+
+#-
+# Program starts here. You should not need to edit anything below this
+# line.
+#-
+if ( $#ARGV != 0 ) {
+$prog = `basename $0`; chop ($prog);
+print "usage: $prog file.diff\n\n";
+print "Adds a ChangeLog template to the start of file.diff\n";
+print "It assumes that file.diff has been created with -up or -cp.\n";
+exit 1;
+}
+
+$diff = $ARGV[0];
+$dir = `dirname $diff`; chop ($dir);
+$basename = `basename $diff`; chop ($basename);
+$cl = `mktemp /tmp/$basename.XX` || exit 1; chop ($cl);
+$hdrline = "$date  $name  <$addr>";
+
+open (CLFILE, ">$cl") or die "Could not open file $cl for writing";
+
+print CLFILE "$hdrline\n\n";
+
+# For every file in the .diff print all the function names in ChangeLog
+# format.
+$bof = 0;
+open (DFILE, $diff) or die "Could not open file $diff for reading";
+while () {
+# Check if we found a new file.
+if (/^\+\+\+ (b\/)?(\S+)/) {
+   # If we have not seen any function names in the previous file (ie,
+   # $bof == 1), we just write out a ':' before starting the next
+   # file.
+   if ($bof == 1) {
+   print CLFILE ":\n";
+   }
+   $filename = $2;
+   print CLFILE "\t* $filename";
+   $bof = 1;
+}
+
+# Remember the last line in a unified diff block that might start
+# a new function.
+if (/^[-+ ]([a-zA-Z0-9_].*)/) {
+$save_fn = $1;
+}
+
+# If we find a new function, print it in brackets.  Special case if
+# this is the first function in a file.  
+#
+# Note that we don't try too hard to find good matches.  This should
+# return a superset of the actual set of functions in the .diff file.
+#
+# The first two patterns work with context diff files (diff -c). The
+# third pattern works with unified diff files (diff -u).
+#
+# The fourth pattern looks for the starts of functions or classes
+# within a unified diff block.
+
+if (/^\*\*\*\*\*\** ([a-zA-Z0-9_].*)/
+|| /^[\-\+\!] ([a-zA-Z0-9_]+)[ \t]*\(.*/
+   || /^@@ .* @@ ([a-zA-Z0-9_].*)/
+   || /^[-+ ](\{)/)
+  {
+   $_ = $1;
+   my $fn;
+   if (/^\{/) {
+   # Beginning of a new function.
+   $_ = $save_fn;
+   } else {
+   $save_fn = "";
+   }
+   if (/;$/) {
+   # No usable function name found.
+   } elsif (/^((class|struct|union|enum) [a-zA-Z0-9_]+)/) {
+   # Discard stuff after the class/struct/etc. tag.
+   $fn = $1;
+   } elsif (/([a-zA-Z0-9_][^(]*)\(/) {
+   # Discard template and function parameters.
+   $fn = $1;
+   1 while ($fn =~ s/<[^<>]*>//);
+   $fn =~ s/[ \t]*$//;
+   }
+   if ($fn && $seen_names{$fn} == 0) {
+   # If this is the first function in the file, we display it next
+   #

Re: [Patch, ARM][0/8] Epilogue in RTL: introduction (Sameera's patches, Part I)

[Paul Brook]

> Testing:
> * Crossbuild for target arm-none-eabi with cpu cortex-a9 neon softfp and
> tested in three configuration: -marm (default), -mthumb, -mapcs-frame. No
> regression on qemu.
> * Crossbuild for target arm-none-eabi thumb2 with cpu cortex-m3. No
> regression on qemu.
> * Crossbuild for target arm-none-eabi thumb1 with cpu arm7tdmi and
> arm1136jf-s. No regression on qemu.
> * Crossbuild for target arm-linux-gnueabi with cpu cortex-a9 with eglibc
> and used this compiler to build AEL linux kernel. It boots successfully. *
> Bootstrap the compiler on cortex-a8 successfully for
> --languages=c,c++,fortran and used this compiler to build gdb. No
> regression with check-gcc and check-gdb.

What other testing have you done?  Thate's a good number of combinations not 
covered by your above list.  In particular:
- Coverage of old cores looks pretty thin.  In particular ARMv4t has different 
interworking requirements.  
- iWMMXT has special alignment requirements.
- Interrupt functions with special prologue/epilogue.  Both traditional ARM 
and Cortex-M3.
- -mtpcs-frame and -mtpcs-leaf-frame

Some of these options are orthogonal.

As you've proved with -mapcs-frame it's near impossible to get these right 
without actually testing them.I'm not saying you have to do a full testrun 
in every combination, but it's worth testing a representative selection of 
functions (large and small frame, leaf or not, with and without frame pointer, 
uses alloca, etc).  Also worth explicitly clobbering a selection (both odd and 
even numbers) of callee saved registers to make sure we get that right.  Any 
difference in the output should be manually verified (ideally the assembly 
output would be identical).

> * The patches have not been explicitly tested with any FPA variants (which
> are deprecated in 4.7 and expected to become obsolete in 4.8).

I'm not keen on breaking these without actually removing them.

Paul

Re: [patch] Do not include output.h everywhere

[Diego Novillo]

On 12-05-31 14:57 , Steven Bosscher wrote:

Hello,

Almost all files include output.h because it defines dump_file. IMHO
output.h should only be included in files that actually output
something to asm_out_file. Therefore wanted to I move dump_file to
some other include file. I ended up with system.h because I couldn't
find a more suitable place. Another option is coretypes.h, but no
other file is included everywhere, and system.h also already defines
fancy_abort, which is also for dumping things - sort of... Anyway, the
point is that with dump_file moved out of output.h, ~120 files don't
have to include output.h anymore.


What about toplev.h?  dump_file is defined there, after all.  I don't 
mind it in system.h, if that's not a good place for it now.  The patch 
is OK either way.



While working on the above, I noticed we can also move all dbxout
prototypes from output.h to dbxout.h, and move some stabs-related
target hooks there also.


Sounds good.


Big patch, but IMHO a nice cleanup too :-)


Indeed.



* gcov-dump.c (dump_file): Rename to dump_gcov_file.  Update callers.

* collect2.h (dump_file): Rename to dump_ld_file.


Thanks.  I've always hated tagging for dump_file and stopping here.


Diego.

Re: [PATCH] Sparc longlong.h enhancements.

[David Miller]

From: Eric Botcazou 
Date: Thu, 31 May 2012 15:06:41 +0200

>> +  do {  
>> \
>> +UDItype __carry = 0;\
>> +__asm__ ("addcc\t%r5,%6,%1\n\t" \
>> + "add\t%r3,%4,%0\n\t"   \
>> + "movcs\t%%xcc, 1, %2\n\t"  \
>> + "add\t%0, %2, %0"  
>> \
>>
>> : "=r" ((UDItype)(sh)),  \
>>
>> - "=&r" ((UDItype)(sl))  \
>> + "=&r" ((UDItype)(sl)), \
>> + "=&r" (__carry)\
>>
>> : "%rJ" ((UDItype)(ah)), \
>>
>>   "rI" ((UDItype)(bh)),  \
>>   "%rJ" ((UDItype)(al)), \
>> - "rI" ((UDItype)(bl))   \
>> -   __CLOBBER_CC)
>> + "rI" ((UDItype)(bl)),  \
>> + "2" (__carry)  \
>> +   __CLOBBER_CC);   \
>> +  } while (0)
> 
> If __carry is used as both source and destination for %2, why not use a 
> single 
> operand with the + modifier?

Makes sense, I'll make that change and test it, thanks Eric.

Re: [PR tree-optimization/52558]: RFC: questions on store data race

[Aldy Hernandez]

On 05/29/12 06:13, Richard Guenther wrote:

On Mon, 21 May 2012, Aldy Hernandez wrote:


On 05/16/12 07:53, Richard Guenther wrote:

On Mon, 7 May 2012, Aldy Hernandez wrote:




(flag_tm&&  loop_preheader_edge (loop)->src->flags&  BB_IN_TRANSACTION)

can you encapsulate this into a predicate?  Like block_in_transaction ()
that also checks flag_tm?


Done.. whoops, forgot to check for flag_tm.  I will move this into the 
predicate after I do another round of testing.  I missed this bit, and 
I've just committed.




+  /* ?? FIXME TESTING TESTING ?? */
+  multi_threaded_model_p=true;
+  /* ?? FIXME TESTING TESTING ?? */

that of course needs fixing ;)  (and re-testing)


This was here on purpose, so you'd see how I was testing.  I have 
committed the attached patch, not before testing with _and_ without the 
above FIXME.


Thanks so much for the review.  I will follow up with the flag_tm 
abstraction.


Closing the PR...

Aldy
PR tree-optimization/52558
* cfg.c (alloc_aux_for_edge): Fix comment.
(alloc_aux_for_edge): Remove static.
* basic-block.h (alloc_aux_for_edge): Protoize.
* tree-ssa-loop-im.c (execute_sm_if_changed): New.
(execute_sm_if_changed_flag): New.
(execute_sm_if_changed_flag_set): New.
(execute_sm): Do not generate data races unless requested.
(tree_ssa_lim_initialize): Call alloc_aux_for_edges.
(tree_ssa_lim_finalize): Call free_aux_for_edges.
* gimple.h (block_in_transaction): New.
(gimple_in_transaction): Use block_in_transaction.

Index: testsuite/gcc.dg/pr52558-1.c
===
--- testsuite/gcc.dg/pr52558-1.c(revision 0)
+++ testsuite/gcc.dg/pr52558-1.c(revision 0)
@@ -0,0 +1,22 @@
+/* { dg-do compile } */
+/* { dg-options "--param allow-store-data-races=0 -O2 -fdump-tree-lim1" } */
+
+/* Test that `count' is not written to unless p->data > 0.  */
+
+int count;
+
+struct obj {
+int data;
+struct obj *next;
+} *q;
+
+void func()
+{
+  struct obj *p;
+  for (p = q; p; p = p->next)
+if (p->data > 0)
+  count++;
+}
+
+/* { dg-final { scan-tree-dump-times "MEM count_lsm.. count_lsm_flag" 1 "lim1" 
} } */
+/* { dg-final { cleanup-tree-dump "lim1" } } */
Index: testsuite/gcc.dg/pr52558-2.c
===
--- testsuite/gcc.dg/pr52558-2.c(revision 0)
+++ testsuite/gcc.dg/pr52558-2.c(revision 0)
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-options "--param allow-store-data-races=0 -O2 -fdump-tree-lim1" } */
+
+/* Test that g_2 is not written to unless !g_1.  */
+
+int g_1 = 1;
+int g_2 = 0;
+
+int func_1(void)
+{
+ int l;
+ for (l = 0; l < 1234; l++)
+ {
+   if (g_1)
+ return l;
+   else
+ g_2 = 0;
+ }
+ return 999;
+}
+
+/* { dg-final { scan-tree-dump-times "MEM.*g_2_lsm_flag" 1 "lim1" } } */
+/* { dg-final { cleanup-tree-dump "lim1" } } */
Index: testsuite/gcc.dg/tm/reg-promotion.c
===
--- testsuite/gcc.dg/tm/reg-promotion.c (revision 0)
+++ testsuite/gcc.dg/tm/reg-promotion.c (revision 0)
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-options "-fgnu-tm -O2 -fdump-tree-lim1" } */
+
+/* Test that `count' is not written to unless p->data>0.  */
+
+int count;
+
+struct obj {
+int data;
+struct obj *next;
+} *q;
+
+void func()
+{
+  struct obj *p;
+  __transaction_atomic {
+for (p = q; p; p = p->next)
+  if (p->data > 0)
+   count++;
+  }
+}
+
+/* { dg-final { scan-tree-dump-times "MEM count_lsm.. count_lsm_flag" 1 "lim1" 
} } */
+/* { dg-final { cleanup-tree-dump "lim1" } } */
Index: tree-ssa-loop-im.c
===
--- tree-ssa-loop-im.c  (revision 188080)
+++ tree-ssa-loop-im.c  (working copy)
@@ -52,7 +52,7 @@ along with GCC; see the file COPYING3.
 }
  }
 
-   Where COND and INV are is invariants, but evaluating INV may trap or be
+   Where COND and INV are invariants, but evaluating INV may trap or be
invalid from some other reason if !COND.  This may be transformed to
 
if (cond)
@@ -1626,6 +1626,7 @@ gather_mem_refs_stmt (struct loop *loop,
  fprintf (dump_file, "\n");
}
 }
+
   if (is_stored)
 mark_ref_stored (ref, loop);
 
@@ -1956,6 +1957,173 @@ get_lsm_tmp_name (tree ref, unsigned n)
   return lsm_tmp_name;
 }
 
+struct prev_flag_edges {
+  /* Edge to insert new flag comparison code.  */
+  edge append_cond_position;
+
+  /* Edge for fall through from previous flag comparison.  */
+  edge last_cond_fallthru;
+};
+
+/* Helper function for execute_sm.  Emit code to store TMP_VAR into
+   MEM along edge EX.
+
+   The store is only done if MEM has changed.  We do this so no
+   changes to MEM occur on code paths that did not originally store
+   into it.
+
+   The common case for execute_sm will transform:
+
+ for (...) {
+   if (foo)
+

Re: [Patch,AVR]: Use tr instead of set to canonicalize line endings for cmp

[Joerg Wunsch]

As Georg-Johann Lay wrote:

> So here is the next version of the patch, returning to printf again
> :-)

"works for me"

-- 
cheers, J"org   .-.-.   --... ...--   -.. .  DL8DTL

http://www.sax.de/~joerg/NIC: JW11-RIPE
Never trust an operating system you don't have sources for. ;-)

[PATCH] Fix output in mklog

[Marek Polacek]

The new mklog script prints three spaces after the date part, which
is wrong.  Thus fixed by adjusting the split pattern.  Tested manually.

2012-05-31  Marek Polacek  

* mklog: Prevent printing three spaces after the date.

--- gcc/contrib/mklog.mp2012-05-31 22:03:07.492457065 +0200
+++ gcc/contrib/mklog   2012-05-31 22:03:21.824493596 +0200
@@ -29,7 +29,7 @@
 # Change these settings to reflect your profile.
 $username = $ENV{'USER'};
 $name = `finger $username | grep -o 'Name: .*'`;
-@n = split(/:/, $name);
+@n = split(/: /, $name);
 $name = @n[1]; chop($name);
 $addr = $username . "\@my.domain.org";
 $date = `date +%Y-%m-%d`; chop ($date);

Marek

Re: [PATCH] Fix PR53471, remove DECL_ASSEMBLER_NAME deferred compute

[Jason Merrill]

The comment mentions PCH in connection with deferred seting of 
DECL_ASSEMBLER_NAME; off the top of my head it occurs to me that that 
might be connected with anonymous unions, which need to have different 
linkage names in different translation units.


Jason

[committed] check for flag_tm in block_in_transaction

[Aldy Hernandez]

As discussed earlier, I have moved the flag_tm check inside of 
block_in_transaction.


Committed to trunk.
* tree-ssa-loop-im.c (execute_sm): Do not check flag_tm.
* gimple.h (block_in_transaction): Check for flag_tm.

Index: tree-ssa-loop-im.c
===
--- tree-ssa-loop-im.c  (revision 188081)
+++ tree-ssa-loop-im.c  (working copy)
@@ -2154,7 +2154,7 @@ execute_sm (struct loop *loop, VEC (edge
   fmt_data.orig_loop = loop;
   for_each_index (&ref->mem, force_move_till, &fmt_data);
 
-  if ((flag_tm && block_in_transaction (loop_preheader_edge (loop)->src))
+  if (block_in_transaction (loop_preheader_edge (loop)->src)
   || !PARAM_VALUE (PARAM_ALLOW_STORE_DATA_RACES))
 multi_threaded_model_p = true;
 
Index: gimple.h
===
--- gimple.h(revision 188081)
+++ gimple.h(working copy)
@@ -1593,7 +1593,7 @@ gimple_set_has_volatile_ops (gimple stmt
 static inline bool
 block_in_transaction (basic_block bb)
 {
-  return bb->flags & BB_IN_TRANSACTION;
+  return flag_tm && bb->flags & BB_IN_TRANSACTION;
 }
 
 /* Return true if STMT is in a transaction.  */

[SH, 4.7] Backport Fix sh64-elf build failure [1/3]

[Oleg Endo]

Original patch:
http://gcc.gnu.org/ml/gcc-patches/2012-03/msg00208.html

'Tested' with..

../gcc-4_7-branch/configure --target=sh-elf --prefix=/usr/local
--enable-languages=c,c++ --enable-multilib --disable-libssp
--disable-nls --disable-werror --enable-lto --with-newlib --with-gnu-as
--with-gnu-ld --with-system-zlib

make all

OK for 4.7 branch?

ChangeLog:

Backport from mainline
2012-03-03  Kaz Kojima  
* config/sh/sh.c (shiftcosts): Return MAX_COST when the first
operand is CONST_INT.  Take COSTS_N_INSNS into account.
(sh_rtx_costs): Don't apply COSTS_N_INSNS to the return value
of shiftcosts.
Index: gcc/config/sh/sh.c
===
--- gcc/config/sh/sh.c	(revision 188026)
+++ gcc/config/sh/sh.c	(working copy)
@@ -2811,22 +2811,26 @@
 {
   int value;
 
+  /* There is no pattern for constant first operand.  */
+  if (CONST_INT_P (XEXP (x, 0)))
+return MAX_COST;
+
   if (TARGET_SHMEDIA)
-return 1;
+return COSTS_N_INSNS (1);
 
   if (GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD)
 {
   if (GET_MODE (x) == DImode
 	  && CONST_INT_P (XEXP (x, 1))
 	  && INTVAL (XEXP (x, 1)) == 1)
-	return 2;
+	return COSTS_N_INSNS (2);
 
   /* Everything else is invalid, because there is no pattern for it.  */
   return MAX_COST;
 }
   /* If shift by a non constant, then this will be expensive.  */
   if (!CONST_INT_P (XEXP (x, 1)))
-return SH_DYNAMIC_SHIFT_COST;
+return COSTS_N_INSNS (SH_DYNAMIC_SHIFT_COST);
 
   /* Otherwise, return the true cost in instructions.  Cope with out of range
  shift counts more or less arbitrarily.  */
@@ -2838,10 +2842,10 @@
   /* If SH3, then we put the constant in a reg and use shad.  */
   if (cost > 1 + SH_DYNAMIC_SHIFT_COST)
 	cost = 1 + SH_DYNAMIC_SHIFT_COST;
-  return cost;
+  return COSTS_N_INSNS (cost);
 }
   else
-return shift_insns[value];
+return COSTS_N_INSNS (shift_insns[value]);
 }
 
 /* Return the cost of an AND/XOR/IOR operation.  */
@@ -3074,7 +3078,7 @@
 case ASHIFT:
 case ASHIFTRT:
 case LSHIFTRT:
-  *total = COSTS_N_INSNS (shiftcosts (x));
+  *total = shiftcosts (x);
   return true;
 
 case DIV:

[SH, 4.7] Backport Fix sh64-elf build failure [2/3]

[Oleg Endo]

Original patch:
http://gcc.gnu.org/ml/gcc-patches/2012-03/msg00209.html

'Tested' with..

../gcc-4_7-branch/configure --target=sh-elf --prefix=/usr/local
--enable-languages=c,c++ --enable-multilib --disable-libssp
--disable-nls --disable-werror --enable-lto --with-newlib --with-gnu-as
--with-gnu-ld --with-system-zlib

make all

OK for 4.7 branch?

ChangeLog:

Backport from mainline
2012-03-03  Kaz Kojima  
* config/sh/sh.c (sh_dwarf_register_span): Don't apply
DBX_REGISTER_NUMBER.
Index: gcc/config/sh/sh.c
===
--- gcc/config/sh/sh.c	(revision 188026)
+++ gcc/config/sh/sh.c	(working copy)
@@ -8138,10 +8138,8 @@
   return
 gen_rtx_PARALLEL (VOIDmode,
 		  gen_rtvec (2,
- gen_rtx_REG (SFmode,
-	  DBX_REGISTER_NUMBER (regno+1)),
- gen_rtx_REG (SFmode,
-	  DBX_REGISTER_NUMBER (regno;
+ gen_rtx_REG (SFmode, regno + 1),
+ gen_rtx_REG (SFmode, regno)));
 }
 
 static enum machine_mode

[SH, 4.7] Backport Fix sh64-elf build failure [3/3]

[Oleg Endo]

Original patch:
http://gcc.gnu.org/ml/gcc-patches/2012-03/msg00210.html

'Tested' with..

../gcc-4_7-branch/configure --target=sh-elf --prefix=/usr/local
--enable-languages=c,c++ --enable-multilib --disable-libssp
--disable-nls --disable-werror --enable-lto --with-newlib --with-gnu-as
--with-gnu-ld --with-system-zlib

make all

OK for 4.7 branch?

ChangeLog:

Backport from mainline
2012-03-03  Kaz Kojima  
* config/sh/sh.md (abssi2): Add TARGET_SH1 condition.

[SH, 4.7] Backport Fix sh64-elf build failure [3/3]

[Oleg Endo]

Original patch:
http://gcc.gnu.org/ml/gcc-patches/2012-03/msg00210.html

'Tested' with..

../gcc-4_7-branch/configure --target=sh-elf --prefix=/usr/local
--enable-languages=c,c++ --enable-multilib --disable-libssp
--disable-nls --disable-werror --enable-lto --with-newlib --with-gnu-as
--with-gnu-ld --with-system-zlib

make all

OK for 4.7 branch?

ChangeLog:

Backport from mainline
2012-03-03  Kaz Kojima  
* config/sh/sh.md (abssi2): Add TARGET_SH1 condition.

Index: gcc/config/sh/sh.md
===
--- gcc/config/sh/sh.md	(revision 188026)
+++ gcc/config/sh/sh.md	(working copy)
@@ -4462,7 +4462,7 @@
   [(set (match_operand:SI 0 "arith_reg_dest" "")
   	(abs:SI (match_operand:SI 1 "arith_reg_operand" "")))
(clobber (reg:SI T_REG))]
-  ""
+  "TARGET_SH1"
   "")
 
 (define_insn_and_split "*abssi2"

[SH, 4.7] Backport PR52667, Fix for barrier insertion

[Oleg Endo]

Original patch:
http://gcc.gnu.org/ml/gcc-patches/2012-03/msg01695.html

'Tested' with..

../gcc-4_7-branch/configure --target=sh-elf --prefix=/usr/local
--enable-languages=c,c++ --enable-multilib --disable-libssp
--disable-nls --disable-werror --enable-lto --with-newlib --with-gnu-as
--with-gnu-ld --with-system-zlib

make all

OK for 4.7 branch?

ChangeLog:

Backport from mainline
2012-03-27  Chung-Lin Tang  
PR target/52667
* config/sh/sh.c (find_barrier): Add equality check of last_got
to avoid going above orig insn. Update comments.
Index: gcc/config/sh/sh.c
===
--- gcc/config/sh/sh.c	(revision 188026)
+++ gcc/config/sh/sh.c	(working copy)
@@ -4720,9 +4720,12 @@
   /* Don't emit a constant table int the middle of global pointer setting,
 	 since that that would move the addressing base GOT into another table. 
 	 We need the first mov instruction before the _GLOBAL_OFFSET_TABLE_
-	 in the pool anyway, so just move up the whole constant pool.  */
-  if (last_got)
-from = PREV_INSN (last_got);
+	 in the pool anyway, so just move up the whole constant pool.
+	 However, avoid doing so when the last single GOT mov is the starting
+	 insn itself.  Going past above the start insn would create a negative
+	 offset, causing errors.  */
+  if (last_got && last_got != orig)
+	from = PREV_INSN (last_got);
 
   /* Don't insert the constant pool table at the position which
 	 may be the landing pad.  */

[Patch, libgfortran] Silence compiler warnings on MinGW(64)

[Tobias Burnus]

This patch tries to silence most warnings reported for MinGW64 by 
Nightstrike at http://pastebin.mozilla.org/1652586


One item is a true bug. I didn't fix the coarray-related warnings as the 
ABI will still change. And I ignored the last ones as rstride is set. 
(The compiler cannot see that "dim" is always >= 0.)


Build on x86-64-gnu-linux.
OK for the trunk?

Tobias
2012-06-01  Tobias Burnus  

	* intrinsics/chmod.c (chmod_func): On MinGW, don't set is_dir and
	fix octal-mode handling.
	* io/unit.c (get_internal_unit): Add cast.
	* io/unix.c (min): Undef "min" before defining it.
	* runtime/backtrace.c (show_backtrace): Move label into
	ifndef __MINGW__ block.

diff --git a/libgfortran/intrinsics/chmod.c b/libgfortran/intrinsics/chmod.c
index e8a81d5..43b8de2 100644
--- a/libgfortran/intrinsics/chmod.c
+++ b/libgfortran/intrinsics/chmod.c
@@ -74,7 +74,10 @@ chmod_func (char *name, char *mode, gfc_charlen_type name_len,
   bool ugo[3];
   bool rwxXstugo[9];
   int set_mode, part;
-  bool is_dir, honor_umask, continue_clause = false;
+  bool honor_umask, continue_clause = false;
+#ifndef __MINGW32__
+  bool is_dir;
+#endif
   mode_t mode_mask, file_mode, new_mode;
   struct stat stat_buf;
 
@@ -93,10 +96,10 @@ chmod_func (char *name, char *mode, gfc_charlen_type name_len,
   if (mode[0] >= '0' && mode[0] <= '9')
 {
 #ifdef __MINGW32__
-  unsigned mode;
-  if (sscanf (mode, "%o", &mode) != 1)
+  unsigned fmode;
+  if (sscanf (mode, "%o", &fmode) != 1)
 	return 1;
-  file_mode = (mode_t) mode;
+  file_mode = (mode_t) fmode;
 #else
   if (sscanf (mode, "%o", &file_mode) != 1)
 	return 1;
@@ -109,7 +112,9 @@ chmod_func (char *name, char *mode, gfc_charlen_type name_len,
 return 1;
 
   file_mode = stat_buf.st_mode & ~S_IFMT;
+#ifndef __MINGW32__
   is_dir = stat_buf.st_mode & S_IFDIR;
+#endif
 
 #ifdef HAVE_UMASK
   /* Obtain the umask without distroying the setting.  */
diff --git a/libgfortran/io/unit.c b/libgfortran/io/unit.c
index 911521d..8b0926d 100644
--- a/libgfortran/io/unit.c
+++ b/libgfortran/io/unit.c
@@ -430,7 +430,8 @@ get_internal_unit (st_parameter_dt *dtp)
 	  else
 	{
 	  dtp->internal_unit_len =
-		string_len_trim_char4 (dtp->internal_unit_len, dtp->internal_unit);
+		string_len_trim_char4 (dtp->internal_unit_len,
+   (const gfc_char4_t*) dtp->internal_unit);
 	  iunit->recl = dtp->internal_unit_len;
 	}
 	}
diff --git a/libgfortran/io/unix.c b/libgfortran/io/unix.c
index c81163f..1a9faea 100644
--- a/libgfortran/io/unix.c
+++ b/libgfortran/io/unix.c
@@ -41,13 +41,6 @@ see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
 #include 
 
 
-/* min macro that evaluates its arguments only once.  */
-#define min(a,b)		\
-  ({ typeof (a) _a = (a);	\
-typeof (b) _b = (b);	\
-_a < _b ? _a : _b; })
-
-
 /* For mingw, we don't identify files by their inode number, but by a
64-bit identifier created from a BY_HANDLE_FILE_INFORMATION. */
 #ifdef __MINGW32__
@@ -106,8 +99,19 @@ id_from_fd (const int fd)
   return id_from_handle ((HANDLE) _get_osfhandle (fd));
 }
 
+#endif /* HAVE_WORKING_STAT */
+#endif /* __MINGW32__ */
+
+
+/* min macro that evaluates its arguments only once.  */
+#ifdef min
+#undef min
 #endif
-#endif
+
+#define min(a,b)		\
+  ({ typeof (a) _a = (a);	\
+typeof (b) _b = (b);	\
+_a < _b ? _a : _b; })
 
 #ifndef PATH_MAX
 #define PATH_MAX 1024
diff --git a/libgfortran/runtime/backtrace.c b/libgfortran/runtime/backtrace.c
index 6bfc560..9d88d13 100644
--- a/libgfortran/runtime/backtrace.c
+++ b/libgfortran/runtime/backtrace.c
@@ -270,9 +270,9 @@ fallback:
   }
   while (0);
 
+fallback_noerr:
 #endif /* CAN_PIPE */
 
-fallback_noerr:
   /* Fallback to the simple backtrace without addr2line.  */
   state.direct_output = 1;
   _Unwind_Backtrace (trace_function, &state);

[SH, 4.7] Backport PR 52642 - libstdc++ failures

[Oleg Endo]

Original patch:
http://gcc.gnu.org/ml/gcc-patches/2012-03/msg01393.html

'Tested' with..

../gcc-4_7-branch/configure --target=sh-elf --prefix=/usr/local
--enable-languages=c,c++ --enable-multilib --disable-libssp
--disable-nls --disable-werror --enable-lto --with-newlib --with-gnu-as
--with-gnu-ld --with-system-zlib

make all

OK for 4.7 branch?

ChangeLog:

Backport from mainline
2012-03-21  Kaz Kojima  
PR target/52642
* config/sh/sh.c (sh_expand_prologue): Emit blockage at the end
of prologue for unwinder and profiler.

Index: gcc/config/sh/sh.c
===
--- gcc/config/sh/sh.c	(revision 185554)
+++ gcc/config/sh/sh.c	(working copy)
@@ -7239,6 +7239,13 @@
   emit_insn (gen_shcompact_incoming_args ());
 }
 
+  /* If we are profiling, make sure no instructions are scheduled before
+ the call to mcount.  Similarly if some call instructions are swapped
+ before frame related insns, it'll confuse the unwinder because
+ currently SH has no unwind info for function epilogues.  */
+  if (crtl->profile || flag_exceptions || flag_unwind_tables)
+emit_insn (gen_blockage ());
+
   if (flag_stack_usage_info)
 current_function_static_stack_size = stack_usage;
 }

sparc build broken...

[David Miller]

Removing output.h from reload1.c broke the sparc build because
sparc's define of INITIAL_ELIMINATION_OFFSET (which is used in
reload1.c) references current_function_is_leaf.

Re: [AARCH64] [PATCH 3/3] AArch64 Port

[Richard Sandiford]

Tejas Belagod  writes:
> In the currect scheme, when multiple code/mode iterators are in an rtx 
> pattern, 
> they are expanded for each combination of iterator values in 
> apply_iterator_traverse () and a repeated traversal of the expanded rtx's for 
> each iterator achieves the 'cross-product' of rtx's for iterator value 
> combinations. This allows for having the place-holder codes/modes in new 
> rtx's 
> that are shallow-copied and a subsequent traversal will eventually replace 
> them 
> with actual code/mode iterator values. Doing away with the placeholders means 
> that we have to build a 'cross-product' of iterator values from a database of 
> iterator values as used in a pattern and make an rtx copy(deep) corresponding 
> to 
> each element of the cross-product with the iterator value combinations 
> substituted in. This is my understanding of the new implementation - am I on 
> the 
> right track?

That makes it sound a lot more complicated than it was supposed to be. :-)

I'm testing a patch to convert the modes and codes now.  Hopefully it'll
be easy to add your stuff on top of that.

Richard

Re: [PATCH 1/2] mips: Add R4600 scheduling support for imul and idiv

[Richard Sandiford]

Matt Turner  writes:
> On Sat, Feb 25, 2012 at 3:11 AM, Richard Sandiford
>  wrote:
>> Matt Turner  writes:
>>> The r4600_imul and r4600_idiv reservations were correct for si, but
>>> there were no *_di reservations.
>>>
>>> See page 4 of
>>> http://www.sgistuff.net/hardware/other/documents/R4600_Prod_OV.pdf
>>>
>>> 2012-02-24  Matt Turner  
>>>
>>>       * config/mips/4600.md (r4600_imul_si): Rename from r4600_imul.
>>>       (r4600_imul_di): New.
>>>       (r4600_idiv_si): Rename from r4600_idiv.
>>>       (r4600_idiv_di): New.
>>
>> Both patches look good, thanks.  Will commit once 4.8 is open and the
>> copyright assignment is sorted.
>>
>> Richard
>
> Copyright assignment is sorted. Please commit. :)

Applied this one.  Part 2 seems to be based on a different version
of driver-native.c though.

Thanks for perservering. :-)

Richard

Re: sparc build broken...

[Steven Bosscher]

On Thu, May 31, 2012 at 11:15 PM, David Miller  wrote:
>
> Removing output.h from reload1.c broke the sparc build because
> sparc's define of INITIAL_ELIMINATION_OFFSET (which is used in
> reload1.c) references current_function_is_leaf.

I was afraid of some fall-out. This is why target macros must die...

Could you please give the attached patch a try?
Sorry for the inconvenience!

Ciao!
Steven


fix_sparc_output_h.diff
Description: Binary data

Re: sparc build broken...

[David Miller]

From: Steven Bosscher 
Date: Thu, 31 May 2012 23:42:26 +0200

> Could you please give the attached patch a try?
> Sorry for the inconvenience!

I'm sure it works, but function calls are quite expensive on
sparc.

Re: [SH, 4.7] Backport Fix sh64-elf build failure [1/3]

[Kaz Kojima]

Oleg Endo  wrote:
> Original patch:
> http://gcc.gnu.org/ml/gcc-patches/2012-03/msg00208.html
> 
> 'Tested' with..
> 
> ../gcc-4_7-branch/configure --target=sh-elf --prefix=/usr/local
> --enable-languages=c,c++ --enable-multilib --disable-libssp
> --disable-nls --disable-werror --enable-lto --with-newlib --with-gnu-as
> --with-gnu-ld --with-system-zlib
> 
> make all
> 
> OK for 4.7 branch?
> 
> ChangeLog:
> 
>   Backport from mainline
>   2012-03-03  Kaz Kojima  
>   * config/sh/sh.c (shiftcosts): Return MAX_COST when the first
>   operand is CONST_INT.  Take COSTS_N_INSNS into account.
>   (sh_rtx_costs): Don't apply COSTS_N_INSNS to the return value
>   of shiftcosts.

OK as the fix for a regression from 4.6.

Regards,
kaz

Re: [SH, 4.7] Backport Fix sh64-elf build failure [2/3]

[Kaz Kojima]

Oleg Endo  wrote:
> Original patch:
> http://gcc.gnu.org/ml/gcc-patches/2012-03/msg00209.html
> 
> 'Tested' with..
> 
> ../gcc-4_7-branch/configure --target=sh-elf --prefix=/usr/local
> --enable-languages=c,c++ --enable-multilib --disable-libssp
> --disable-nls --disable-werror --enable-lto --with-newlib --with-gnu-as
> --with-gnu-ld --with-system-zlib
> 
> make all
> 
> OK for 4.7 branch?
> 
> ChangeLog:
> 
>   Backport from mainline
>   2012-03-03  Kaz Kojima  
>   * config/sh/sh.c (sh_dwarf_register_span): Don't apply
>   DBX_REGISTER_NUMBER.

OK as the fix for a regression from 4.6.

Regards,
kaz

Re: [SH, 4.7] Backport PR52667, Fix for barrier insertion

[Kaz Kojima]

Oleg Endo  wrote:
> Original patch:
> http://gcc.gnu.org/ml/gcc-patches/2012-03/msg01695.html
> 
> 'Tested' with..
> 
> ../gcc-4_7-branch/configure --target=sh-elf --prefix=/usr/local
> --enable-languages=c,c++ --enable-multilib --disable-libssp
> --disable-nls --disable-werror --enable-lto --with-newlib --with-gnu-as
> --with-gnu-ld --with-system-zlib
> 
> make all
> 
> OK for 4.7 branch?
> 
> ChangeLog:
> 
>   Backport from mainline
>   2012-03-27  Chung-Lin Tang  
>   PR target/52667
>   * config/sh/sh.c (find_barrier): Add equality check of last_got
>   to avoid going above orig insn. Update comments.

OK as the fix for a regression from 4.6.

Regards,
kaz

Re: [SH, 4.7] Backport PR 52642 - libstdc++ failures

[Kaz Kojima]

Oleg Endo  wrote:
> Original patch:
> http://gcc.gnu.org/ml/gcc-patches/2012-03/msg01393.html
> 
> 'Tested' with..
> 
> ../gcc-4_7-branch/configure --target=sh-elf --prefix=/usr/local
> --enable-languages=c,c++ --enable-multilib --disable-libssp
> --disable-nls --disable-werror --enable-lto --with-newlib --with-gnu-as
> --with-gnu-ld --with-system-zlib
> 
> make all
> 
> OK for 4.7 branch?
> 
> ChangeLog:
> 
>   Backport from mainline
>   2012-03-21  Kaz Kojima  
>   PR target/52642
>   * config/sh/sh.c (sh_expand_prologue): Emit blockage at the end
>   of prologue for unwinder and profiler.

OK as the fix for a regression from 4.6.

Regards,
kaz

Re: [SH, 4.7] Backport Fix sh64-elf build failure [3/3]

[Kaz Kojima]

Oleg Endo  wrote:
> Original patch:
> http://gcc.gnu.org/ml/gcc-patches/2012-03/msg00210.html
> 
> 'Tested' with..
> 
> ../gcc-4_7-branch/configure --target=sh-elf --prefix=/usr/local
> --enable-languages=c,c++ --enable-multilib --disable-libssp
> --disable-nls --disable-werror --enable-lto --with-newlib --with-gnu-as
> --with-gnu-ld --with-system-zlib
> 
> make all
> 
> OK for 4.7 branch?
> 
> ChangeLog:
> 
> Backport from mainline
> 2012-03-03  Kaz Kojima  
> * config/sh/sh.md (abssi2): Add TARGET_SH1 condition.

OK as the fix for a regression from 4.6.

Regards,
kaz

[SH] PR 53512 - Allow fsca and fsrra for non-SH4A

[Oleg Endo]

Hello,

The attached patch addresses PR 53512.
Tested with
make all-gcc
make info dvi pdf

Previous default behavior for SH4A:
make check-gcc RUNTESTFLAGS="sh.exp=sh4a-sincosf*
--target_board=sh-sim/-m4a-single/-ml"

 check-gcc RUNTESTFLAGS="sh.exp=sh4a-fsrra*
--target_board=sh-sim/-m4a-single/-ml"

New behavior:
make check-gcc RUNTESTFLAGS="sh.exp=pr53512-* --target_board=sh-sim
\{-m4a-single/-ml,-m2/-ml,-m2a/-mb,-m2e/-ml,-m4a/-ml,-m4a-single/-ml,-m4a-single-only/-ml,-m4a-nofpu/-ml}"

OK for 4.8?

ChangeLog:

PR target/53512
* sh.opt (mfsca, mfsrra): New options.
* sh.md (rsqrtsf2): Use TARGET_FPU_ANY and TARGET_FSRRA 
condition.
(fsca, sinsf2, cossf2): Use TARGET_FPU_ANY and TARGET_FSCA
condition.
* sh.c (sh_option_override): Handle TARGET_FSRRA and
TARGET_FSCA.
* doc/invoke.texi (SH Options): Add descriptions for -mfsca,
-mno-fsca, -mfsrra, -mno-fsrra.

testsuite/ChangeLog:

PR target/53512
* gcc.target/sh/pr53512-1.c: New.
* gcc.target/sh/pr53512-2.c: New.
* gcc.target/sh/pr53512-3.c: New.
* gcc.target/sh/pr53512-4.c: New.
Index: gcc/testsuite/gcc.target/sh/pr53512-1.c
===
--- gcc/testsuite/gcc.target/sh/pr53512-1.c	(revision 0)
+++ gcc/testsuite/gcc.target/sh/pr53512-1.c	(revision 0)
@@ -0,0 +1,15 @@
+/* Verify that the fsca insn is used when specifying -mfsca and
+  -funsafe-math-optimizations.  */
+/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-options "-O1 -mfsca -funsafe-math-optimizations" } */
+/* { dg-skip-if "" { "sh*-*-*" } { "-m1" "-m2*" "-m4al" "*nofpu" "-m4-340*" "-m4-400*" "-m4-500*" "-m5*" } { "" } }  */
+/* { dg-final { scan-assembler "fsca" } } */
+
+#include 
+
+float
+test_func_00 (float x)
+{
+  return sinf (x) + cosf (x);
+}
+
Index: gcc/testsuite/gcc.target/sh/pr53512-2.c
===
--- gcc/testsuite/gcc.target/sh/pr53512-2.c	(revision 0)
+++ gcc/testsuite/gcc.target/sh/pr53512-2.c	(revision 0)
@@ -0,0 +1,15 @@
+/* Verify that the fsca insn is not used when specifying -mno-fsca and
+  -funsafe-math-optimizations.  */
+/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-options "-O1 -mno-fsca -funsafe-math-optimizations" } */
+/* { dg-skip-if "" { "sh*-*-*" } { "-m1" "-m2*" "-m4al" "*nofpu" "-m4-340*" "-m4-400*" "-m4-500*" "-m5*" } { "" } }  */
+/* { dg-final { scan-assembler-not "fsca" } } */
+
+#include 
+
+float
+test_func_00 (float x)
+{
+  return sinf (x) + cosf (x);
+}
+
Index: gcc/testsuite/gcc.target/sh/pr53512-3.c
===
--- gcc/testsuite/gcc.target/sh/pr53512-3.c	(revision 0)
+++ gcc/testsuite/gcc.target/sh/pr53512-3.c	(revision 0)
@@ -0,0 +1,15 @@
+/* Verify that the fsrra insn is used when specifying -mfsrra and
+  -funsafe-math-optimizations and -ffinite-math-only.  */
+/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-options "-O1 -mfsrra -funsafe-math-optimizations -ffinite-math-only" } */
+/* { dg-skip-if "" { "sh*-*-*" } { "-m1" "-m2*" "-m4al" "*nofpu" "-m4-340*" "-m4-400*" "-m4-500*" "-m5*" } { "" } }  */
+/* { dg-final { scan-assembler "fsrra" } } */
+
+#include 
+
+float
+test_func_00 (float x)
+{
+  return 1 / sqrtf (x);
+}
+
Index: gcc/testsuite/gcc.target/sh/pr53512-4.c
===
--- gcc/testsuite/gcc.target/sh/pr53512-4.c	(revision 0)
+++ gcc/testsuite/gcc.target/sh/pr53512-4.c	(revision 0)
@@ -0,0 +1,15 @@
+/* Verify that the fsrra insn is not used when specifying -mno-fsrra and
+  -funsafe-math-optimizations and -ffinite-math-only.  */
+/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-options "-O1 -mno-fsrra -funsafe-math-optimizations -ffinite-math-only" } */
+/* { dg-skip-if "" { "sh*-*-*" } { "-m1" "-m2*" "-m4al" "*nofpu" "-m4-340*" "-m4-400*" "-m4-500*" "-m5*" } { "" } }  */
+/* { dg-final { scan-assembler-not "fsrra" } } */
+
+#include 
+
+float
+test_func_00 (float x)
+{
+  return 1 / sqrtf (x);
+}
+
Index: gcc/doc/invoke.texi
===
--- gcc/doc/invoke.texi	(revision 188026)
+++ gcc/doc/invoke.texi	(working copy)
@@ -886,7 +886,7 @@
 -mindexed-addressing -mgettrcost=@var{number} -mpt-fixed @gol
 -maccumulate-outgoing-args -minvalid-symbols -msoft-atomic -mhard-atomic @gol
 -mbranch-cost=@var{num} -mcbranchdi -mcmpeqdi -mfused-madd -mno-fused-madd @gol
--mpretend-cmove -menable-tas}
+-mfsca -mno-fsca -mfsrra -mno-fsrra -mpretend-cmove -menable-tas}
 
 @emph{Solaris 2 Options}
 @gccoptlist{-mimpure-text  -mno-impure-text @gol
@@ -18262,6 +18262,28 @@
 disallow the usage of the @code{fmac} instruction for regular calculations
 even if @option{-funsafe-math-optimizations} is in effect.
 
+@item -mfsca
+@itemx -mno-fsca
+@opindex mfsca
+@opindex mno-fsca
+Allow or disallow the compiler to emit the @code{fsca} instruction for

Re: [PATCH 1/2] mips: Add R4600 scheduling support for imul and idiv

[Matt Turner]

On Thu, May 31, 2012 at 5:35 PM, Richard Sandiford
 wrote:
> Matt Turner  writes:
>> On Sat, Feb 25, 2012 at 3:11 AM, Richard Sandiford
>>  wrote:
>>> Matt Turner  writes:
 The r4600_imul and r4600_idiv reservations were correct for si, but
 there were no *_di reservations.

 See page 4 of
 http://www.sgistuff.net/hardware/other/documents/R4600_Prod_OV.pdf

 2012-02-24  Matt Turner  

       * config/mips/4600.md (r4600_imul_si): Rename from r4600_imul.
       (r4600_imul_di): New.
       (r4600_idiv_si): Rename from r4600_idiv.
       (r4600_idiv_di): New.
>>>
>>> Both patches look good, thanks.  Will commit once 4.8 is open and the
>>> copyright assignment is sorted.
>>>
>>> Richard
>>
>> Copyright assignment is sorted. Please commit. :)
>
> Applied this one.  Part 2 seems to be based on a different version
> of driver-native.c though.
>
> Thanks for perservering. :-)
>
> Richard

Thanks a lot!

Ah, right, 2/2 was written before IRIX support was removed and changed
driver-native.c significantly.

Updated patch in your inbox shortly.

Thanks!
Matt

[PATCH 2/2] mips: Add R4700 scheduling support

[Matt Turner]

The R4700 is identical to the R4600 except for the integer and
floating-point multiplication costs.

See page 4 of http://datasheets.chipdb.org/IDT/MIPS/79RV4700.pdf

2012-03-24  Matt Turner  

gcc/
* config/mips/4600.md (r4700_imul_si): New.
(r4700_imul_di): New.
(r4700_fmul_single): New.
(r4700_fmul_double): New.
* config/mips/mips-cpus.def: Add r4700.
* config/mips/mips.c: Likewise.
* config/mips/mips.md: Likewise.
* config/mips/mips-tables.opt: Regenerate.
---
 gcc/config/mips/4600.md |   51 ++--
 gcc/config/mips/mips-cpus.def   |1 +
 gcc/config/mips/mips-tables.opt |  278 ---
 gcc/config/mips/mips.c  |3 +
 gcc/config/mips/mips.md |1 +
 5 files changed, 187 insertions(+), 147 deletions(-)

diff --git a/gcc/config/mips/4600.md b/gcc/config/mips/4600.md
index 53aa01b..36eab80 100644
--- a/gcc/config/mips/4600.md
+++ b/gcc/config/mips/4600.md
@@ -1,4 +1,4 @@
-;; R4600 and R4650 pipeline description.
+;; R4600, R4650, and R4700 pipeline description.
 ;;   Copyright (C) 2004, 2005, 2007, 2012 Free Software Foundation, Inc.
 ;;
 ;; This file is part of GCC.
@@ -21,8 +21,10 @@
 ;; This file overrides parts of generic.md.  It is derived from the
 ;; old define_function_unit description.
 ;;
-;; We handle the R4600 and R4650 in much the same way.  The only difference
-;; is in the integer multiplication and division costs.
+;; We handle the R4600, R4650, and R4700 in much the same way.  The only
+;; differences between R4600 and R4650 are the integer multiplication and
+;; division costs. The only differences between R4600 and R4700 are the
+;; integer and floating-point multiplication costs.
 
 (define_insn_reservation "r4600_imul_si" 10
   (and (eq_attr "cpu" "r4600")
@@ -37,13 +39,13 @@
   "imuldiv*12")
 
 (define_insn_reservation "r4600_idiv_si" 42
-  (and (eq_attr "cpu" "r4600")
+  (and (eq_attr "cpu" "r4600,r4700")
(eq_attr "type" "idiv")
(eq_attr "mode" "SI"))
   "imuldiv*42")
 
 (define_insn_reservation "r4600_idiv_di" 74
-  (and (eq_attr "cpu" "r4600")
+  (and (eq_attr "cpu" "r4600,r4700")
(eq_attr "type" "idiv")
(eq_attr "mode" "DI"))
   "imuldiv*74")
@@ -60,13 +62,26 @@
   "imuldiv*36")
 
 
+(define_insn_reservation "r4700_imul_si" 8
+  (and (eq_attr "cpu" "r4700")
+   (eq_attr "type" "imul,imul3,imadd")
+   (eq_attr "mode" "SI"))
+  "imuldiv*8")
+
+(define_insn_reservation "r4700_imul_di" 10
+  (and (eq_attr "cpu" "r4700")
+   (eq_attr "type" "imul,imul3,imadd")
+   (eq_attr "mode" "DI"))
+  "imuldiv*10")
+
+
 (define_insn_reservation "r4600_load" 2
-  (and (eq_attr "cpu" "r4600,r4650")
+  (and (eq_attr "cpu" "r4600,r4650,r4700")
(eq_attr "type" "load,fpload,fpidxload"))
   "alu")
 
 (define_insn_reservation "r4600_fmove" 1
-  (and (eq_attr "cpu" "r4600,r4650")
+  (and (eq_attr "cpu" "r4600,r4650,r4700")
(eq_attr "type" "fabs,fneg,fmove"))
   "alu")
 
@@ -82,26 +97,40 @@
(eq_attr "mode" "DF")))
   "alu")
 
+
+(define_insn_reservation "r4700_fmul_single" 4
+  (and (eq_attr "cpu" "r4700")
+   (and (eq_attr "type" "fmul,fmadd")
+   (eq_attr "mode" "SF")))
+  "alu")
+
+(define_insn_reservation "r4700_fmul_double" 5
+  (and (eq_attr "cpu" "r4700")
+   (and (eq_attr "type" "fmul,fmadd")
+   (eq_attr "mode" "DF")))
+  "alu")
+
+
 (define_insn_reservation "r4600_fdiv_single" 32
-  (and (eq_attr "cpu" "r4600,r4650")
+  (and (eq_attr "cpu" "r4600,r4650,r4700")
(and (eq_attr "type" "fdiv,frdiv")
(eq_attr "mode" "SF")))
   "alu")
 
 (define_insn_reservation "r4600_fdiv_double" 61
-  (and (eq_attr "cpu" "r4600,r4650")
+  (and (eq_attr "cpu" "r4600,r4650,r4700")
(and (eq_attr "type" "fdiv,frdiv")
(eq_attr "mode" "DF")))
   "alu")
 
 (define_insn_reservation "r4600_fsqrt_single" 31
-  (and (eq_attr "cpu" "r4600,r4650")
+  (and (eq_attr "cpu" "r4600,r4650,r4700")
(and (eq_attr "type" "fsqrt,frsqrt")
(eq_attr "mode" "SF")))
   "alu")
 
 (define_insn_reservation "r4600_fsqrt_double" 60
-  (and (eq_attr "cpu" "r4600,r4650")
+  (and (eq_attr "cpu" "r4600,r4650,r4700")
(and (eq_attr "type" "fsqrt,frsqrt")
(eq_attr "mode" "DF")))
   "alu")
diff --git a/gcc/config/mips/mips-cpus.def b/gcc/config/mips/mips-cpus.def
index 8271c47..356d3e5 100644
--- a/gcc/config/mips/mips-cpus.def
+++ b/gcc/config/mips/mips-cpus.def
@@ -70,6 +70,7 @@ MIPS_CPU ("r4400", PROCESSOR_R4000, 3, 0)
 MIPS_CPU ("r4600", PROCESSOR_R4600, 3, 0)
 MIPS_CPU ("orion", PROCESSOR_R4600, 3, 0)
 MIPS_CPU ("r4650", PROCESSOR_R4650, 3, 0)
+MIPS_CPU ("r4700", PROCESSOR_R4700, 3, 0)
 /* ST Loongson 2E/2F processors.  */
 MIPS_CPU ("loongson2e", PROCESSOR_LOONGSON_2E, 3, PTF_AVOID_BRANCHLIKELY)
 MIPS_CPU ("loongson2f", PROCESSOR_LOONGSON_2F, 3, PTF_AVOID_BRANCHLIKELY)
diff --git a/gcc/config/mips/mips-tables.opt b/gcc/config/mips/mips-tables.

Re: sparc build broken...

[Steven Bosscher]

On Fri, Jun 1, 2012 at 12:05 AM, David Miller  wrote:
> From: Steven Bosscher 
> Date: Thu, 31 May 2012 23:42:26 +0200
>
>> Could you please give the attached patch a try?
>> Sorry for the inconvenience!
>
> I'm sure it works, but function calls are quite expensive on
> sparc.

There are four eliminable registers on sparc, and for one of them
there already is a function call. On the whole of GCC, will the few
extra function calls be a problem?

FWIW:
targets that have INITIAL_ELIMINATION_OFFSET as a function (i.e. macro
that just calls a function): alpha, arm,avr, bfin, c6x, cr16, cris,
epiphany, fr30, frv, h8300, ix86, ia64, iq2000, lm32, m32c, m68k,
mcore, mep, microblaze, mips, mmix, mn10300, moxie, pa, pdp11,
picochip, rl78, rs6000, rx, s390, score, sh, spu, stormy16, tilegx,
tilepro,

targets that have it as an elaborate macro: m32r, sparc, v850, xtensa,

So SPARC is in the overwhelming minority :-) I'm sure that in the long
list of targets that have INITIAL_ELIMINATION_OFFSET as a call there
are other targets where a call is relatively expensive.

Besides, at least as far as I understand, it's sort-of a "design goal"
for gcc to move from target macros to target hooks. So you're going to
have to deal with some more calls anyway.

The alternative is to put back output.h in a file that really doesn't
need it, other than for some target macros. That seems rather fragile
to me, target hooks/functions are more robust.

Ciao!
Steven

[google/gcc-4_6] Backport r171031 from upstream to fix ICE on PowerPC64 (issue6255070)

[Doug Kwan]

Hi Diego,

This is a backport of this patch to fix an ICE on PowerPC64.

http://gcc.gnu.org/ml/gcc-patches/2011-03/msg00829.html

-Doug


2012-05-31   Doug Kwan  

Backport r171031 from upstream trunk in gcc/.
2011-03-16  Alan Modra  

PR target/45844
* config/rs6000/rs6000.c (rs6000_legitimize_reload_address):
Don't create invalid offset address for vsx splat insn.
* config/rs6000/predicates.md (splat_input_operand): New.
* config/rs6000/vsx.md (vsx_splat_*): Use it.

* contrib/testsuite-management/powerpc64-grtev2-linux-gnu.xfail:
Remove expected failures because now the bug is fixed by the above.

Index: contrib/testsuite-management/powerpc64-grtev2-linux-gnu.xfail
===
--- contrib/testsuite-management/powerpc64-grtev2-linux-gnu.xfail   
(revision 188083)
+++ contrib/testsuite-management/powerpc64-grtev2-linux-gnu.xfail   
(working copy)
@@ -69,8 +69,6 @@ FAIL: gcc.target/powerpc/pr47755-2.c execution tes
 
 # *** gfortran:
 XPASS: gfortran.dg/nint_2.f90  -O0  execution test
-FAIL: gfortran.dg/vect/pr45714-b.f  -O  (internal compiler error)
-FAIL: gfortran.dg/vect/pr45714-b.f  -O  (test for excess errors)
 FAIL: gfortran.dg/vect/fast-math-pr38968.f90 execution test
 
 # *** g++:
Index: gcc/config/rs6000/predicates.md
===
--- gcc/config/rs6000/predicates.md (revision 188083)
+++ gcc/config/rs6000/predicates.md (working copy)
@@ -1,5 +1,5 @@
 ;; Predicate definitions for POWER and PowerPC.
-;; Copyright (C) 2005, 2006, 2007, 2008, 2009, 2010
+;; Copyright (C) 2005, 2006, 2007, 2008, 2009, 2010, 2011
 ;; Free Software Foundation, Inc.
 ;;
 ;; This file is part of GCC.
@@ -871,6 +871,23 @@
   return 0;
 })
 
+;; Return 1 if this operand is a valid input for a vsx_splat insn.
+(define_predicate "splat_input_operand"
+  (match_code "label_ref,symbol_ref,const,high,reg,subreg,mem,
+  const_double,const_vector,const_int,plus")
+{
+  if (MEM_P (op))
+{
+  if (mode == DFmode)
+   mode = V2DFmode;
+  else if (mode == DImode)
+   mode = V2DImode;
+  else
+   gcc_unreachable ();
+}
+  return input_operand (op, mode);
+})
+
 ;; Return true if OP is an invalid SUBREG operation on the e500.
 (define_predicate "rs6000_nonimmediate_operand"
   (match_code "reg,subreg,mem")
Index: gcc/config/rs6000/rs6000.c
===
--- gcc/config/rs6000/rs6000.c  (revision 188083)
+++ gcc/config/rs6000/rs6000.c  (working copy)
@@ -6703,6 +6703,14 @@ rs6000_legitimize_reload_address (rtx x, enum mach
 {
   bool reg_offset_p = reg_offset_addressing_ok_p (mode);
 
+  /* Nasty hack for vsx_splat_V2DF/V2DI load from mem, which takes a
+ DFmode/DImode MEM.  */
+  if (reg_offset_p
+  && opnum == 1
+  && ((mode == DFmode && recog_data.operand_mode[0] == V2DFmode)
+ || (mode == DImode && recog_data.operand_mode[0] == V2DImode)))
+reg_offset_p = false;
+
   /* We must recognize output that we have already generated ourselves.  */
   if (GET_CODE (x) == PLUS
   && GET_CODE (XEXP (x, 0)) == PLUS
Index: gcc/config/rs6000/vsx.md
===
--- gcc/config/rs6000/vsx.md(revision 188083)
+++ gcc/config/rs6000/vsx.md(working copy)
@@ -1076,7 +1076,7 @@
 (define_insn "vsx_splat_"
   [(set (match_operand:VSX_D 0 "vsx_register_operand" "=wd,wd,wd,?wa,?wa,?wa")
(vec_duplicate:VSX_D
-(match_operand: 1 "input_operand" "ws,f,Z,wa,wa,Z")))]
+(match_operand: 1 "splat_input_operand" "ws,f,Z,wa,wa,Z")))]
   "VECTOR_MEM_VSX_P (mode)"
   "@
xxpermdi %x0,%x1,%x1,0

--
This patch is available for review at http://codereview.appspot.com/6255070

Re: sparc build broken...

[David Miller]

From: Steven Bosscher 
Date: Fri, 1 Jun 2012 01:00:37 +0200

> Besides, at least as far as I understand, it's sort-of a "design goal"
> for gcc to move from target macros to target hooks. So you're going to
> have to deal with some more calls anyway.

I understand, I'm just disappointed :-)

I'll test your fix for real after I finish the work I was trying to
finish when I hit the build regression you introduced.

[v3] libstdc++/53543

[Benjamin De Kosnik]

Renames to avoid builtins on clang. 

(This patch of code is actually the punchline to the joke, "how many
template aliases are really required if you are going for no line
breaks and using 80 columns while using policy based designs.")

tested x86/linux

-benjamin2012-05-31  Benjamin Kosnik  

	PR libstdc++/53543
	* include/bits/hashtable_policy.h (_Insert::__is_convertible):
	Rename to __is_conv to avoid clash with clang built-in.

diff --git a/libstdc++-v3/include/bits/hashtable_policy.h b/libstdc++-v3/include/bits/hashtable_policy.h
index 708ef98..27badbc 100644
--- a/libstdc++-v3/include/bits/hashtable_policy.h
+++ b/libstdc++-v3/include/bits/hashtable_policy.h
@@ -831,10 +831,10 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
   using __base_type::insert;
 
   template
-	using __is_convertible = std::is_convertible<_Pair, value_type>;
+	using __is_conv = std::is_convertible<_Pair, value_type>;
 
   template
-	using _IFconv = std::enable_if<__is_convertible<_Pair>::value>;
+	using _IFconv = std::enable_if<__is_conv<_Pair>::value>;
 
   template
 	using _IFconvp = typename _IFconv<_Pair>::type;

Re: sparc build broken...

[Eric Botcazou]

> I'm sure it works, but function calls are quite expensive on sparc.

I thought the whole business of the register windows was aimed at making them 
quite cheap. :-)  This one isn't performance critical anyway, so the fix is 
fine I think (without the terminal 's' in "Implements" though).

-- 
Eric Botcazou

[RFA:] fix bug in configure header-probing for stack protector support in target C library

[Hans-Peter Nilsson]

This patch fixes target-header-probing for cross-builds that
aren't using sysroot (just --target and --prefix), as in the
difference for crisv32-axis-linux-gnu with an eglibc-2.15-based
port:

--- cllog.prev  Thu May 31 22:00:10 2012
+++ cllog   Thu May 31 22:00:09 2012
@@ -1276,7 +1276,7 @@ checking linker --as-needed support... y
 checking linker --build-id support... yes
 checking linker *_sol2 emulation support... no
 checking linker --sysroot support... yes
-checking __stack_chk_fail in target C library... no
+checking __stack_chk_fail in target C library... yes
 checking sys/sdt.h in the target C library... no
 checking dl_iterate_phdr in target C library... unknown
 Using ggc-page for garbage collection.

Without this patch, the non-existing directory
target_header_dir=NONE/crisv32-axis-linux-gnu/sys-include is
probed due to exec_prefix=NONE, duh.  There's code setting a
separate variable test_exec_prefix that is then used to handle
this kind of testing for sysroot configures, but it is inside
code only executed if --with-sysroot is used.  There's no reason
for it being there as it's not depending on the processing done
there or on sysroot settings.  So let's move it to before the
with-sysroot stuff and use it when setting target_header_dir.
Tested configuring for crisv32-axis-linux-gnu and building past
this part (build completes successfully with the expected
observable change as per the use in gcc.c); no difference for
--with-sysroot.

Ok to commit?

gcc:
Fix configure test for "stack protector support in target C library".
* configure.ac (test_prefix, test_exec_prefix): Move setting from
inside sysroot handling to before and outside it.
* configure: Regenerate.

--- gcc.prev/gcc/configure.ac   2012-05-25 14:28:50.0 +0200
+++ gcc/gcc/configure.ac2012-05-31 21:20:07.0 +0200
@@ -747,6 +747,17 @@ AC_ARG_WITH(build-sysroot, 
   [SYSROOT_CFLAGS_FOR_TARGET=])
 AC_SUBST(SYSROOT_CFLAGS_FOR_TARGET)
 
+if test "x$prefix" = xNONE; then
+ test_prefix=/usr/local
+else
+ test_prefix=$prefix
+fi
+if test "x$exec_prefix" = xNONE; then
+ test_exec_prefix=$test_prefix
+else
+ test_exec_prefix=$exec_prefix
+fi
+
 AC_ARG_WITH(sysroot,
 [AS_HELP_STRING([[--with-sysroot[=DIR]]],
[search for usr/lib, usr/include, et al, within DIR])],
@@ -759,16 +770,6 @@ AC_ARG_WITH(sysroot,
  TARGET_SYSTEM_ROOT_DEFINE='-DTARGET_SYSTEM_ROOT=\"$(TARGET_SYSTEM_ROOT)\"'
  
CROSS_SYSTEM_HEADER_DIR='$(TARGET_SYSTEM_ROOT)$${sysroot_headers_suffix}$(NATIVE_SYSTEM_HEADER_DIR)'

- if test "x$prefix" = xNONE; then
-  test_prefix=/usr/local
- else
-  test_prefix=$prefix
- fi
- if test "x$exec_prefix" = xNONE; then
-  test_exec_prefix=$test_prefix
- else
-  test_exec_prefix=$exec_prefix
- fi
  case ${TARGET_SYSTEM_ROOT} in
  "${test_prefix}"|"${test_prefix}/"*|\
  "${test_exec_prefix}"|"${test_exec_prefix}/"*|\
@@ -4528,11 +4529,11 @@ if test x$host != x$target || test "x$TA
   if test "x$with_headers" != x; then
 target_header_dir=$with_headers
   elif test "x$with_sysroot" = x; then
-target_header_dir="${exec_prefix}/${target_noncanonical}/sys-include"
+target_header_dir="${test_exec_prefix}/${target_noncanonical}/sys-include"
   elif test "x$with_build_sysroot" != "x"; then
 target_header_dir="${with_build_sysroot}${native_system_header_dir}"
   elif test "x$with_sysroot" = xyes; then
-
target_header_dir="${exec_prefix}/${target_noncanonical}/sys-root${native_system_header_dir}"
+
target_header_dir="${test_exec_prefix}/${target_noncanonical}/sys-root${native_system_header_dir}"
   else
 target_header_dir="${with_sysroot}${native_system_header_dir}"
   fi


brgds, H-P

Re: [trunk] Copy TREE_STATIC() property from id in dwarf2asm.c (issue 6133061)

[asharif]

Reviewers: xur, davidxl, iant2, Diego Novillo,

Message:
The relevant bug is this:
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=53546.

Please take a look and provide feedback.

Thanks,

Description:
2012-05-31   Ahmad Sharif  

* gcc/dwarf2asm.c: (dw2_output_indirect_constant_1): Copy TREE_STATIC()
attribute from id to decl.

Index: gcc/dwarf2asm.c
===
--- gcc/dwarf2asm.c (revision 188089)
+++ gcc/dwarf2asm.c (working copy)
@@ -907,6 +907,7 @@
   DECL_IGNORED_P (decl) = 1;
   DECL_INITIAL (decl) = decl;
   TREE_READONLY (decl) = 1;
+  TREE_STATIC (decl) = TREE_STATIC (id);

   if (TREE_PUBLIC (id))
 {
@@ -915,8 +916,6 @@
   if (USE_LINKONCE_INDIRECT)
DECL_VISIBILITY (decl) = VISIBILITY_HIDDEN;
 }
-  else
-TREE_STATIC (decl) = 1;

   sym_ref = gen_rtx_SYMBOL_REF (Pmode, sym);
   assemble_variable (decl, 1, 1, 1);


Please review this at http://codereview.appspot.com/6133061/

Affected files:
  M gcc/dwarf2asm.c


2012-04-30   Ahmad Sharif  

* gcc/dwarf2asm.c: copy TREE_STATIC() property from id.

Index: gcc/dwarf2asm.c
===
--- gcc/dwarf2asm.c (revision 186998)
+++ gcc/dwarf2asm.c (working copy)
@@ -907,6 +907,7 @@
   DECL_IGNORED_P (decl) = 1;
   DECL_INITIAL (decl) = decl;
   TREE_READONLY (decl) = 1;
+  TREE_STATIC (decl) = TREE_STATIC (id);

   if (TREE_PUBLIC (id))
 {
@@ -915,8 +916,6 @@
   if (USE_LINKONCE_INDIRECT)
DECL_VISIBILITY (decl) = VISIBILITY_HIDDEN;
 }
-  else
-TREE_STATIC (decl) = 1;

   sym_ref = gen_rtx_SYMBOL_REF (Pmode, sym);
   assemble_variable (decl, 1, 1, 1);

[patch] PR 50134: improve docs for -Wmissing-prototypes and -Wmissing-declarations

[Jonathan Wakely]

2012-06-01  Manuel López-Ibáñez  
Jonathan Wakely  

PR c++/50134
* doc/invoke.texi (Warning Options): Explain purpose and differences
between -Wmissing-prototypes and -Wmissing-declarations.

This patch tries to improve the docs to clarify the intent of these options.

The new wording isn't strictly accurate when it says that in C++ "all
function declarations provide prototypes" because C++ doesn't use the
term "prototype" at all, but I think it's clear what it means.

OK for trunk?
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 3ad07f3..eb582b3 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -4416,8 +4416,12 @@ This warning is also enabled by @option{-Wextra}.
 @opindex Wno-missing-prototypes
 Warn if a global function is defined without a previous prototype
 declaration.  This warning is issued even if the definition itself
-provides a prototype.  The aim is to detect global functions that 
-are not declared in header files.
+provides a prototype.  Use this option to detect global functions
+that do not have a matching prototype declaration in a header file.
+This option is not valid for C++ because all function declarations
+provide prototypes and a non-matching declaration will declare an
+overload rather than conflict with an earlier declaration.
+Use @option{-Wmissing-declarations} to detect missing declarations in C++.
 
 @item -Wmissing-declarations
 @opindex Wmissing-declarations
@@ -4425,7 +4429,9 @@ are not declared in header files.
 Warn if a global function is defined without a previous declaration.
 Do so even if the definition itself provides a prototype.
 Use this option to detect global functions that are not declared in
-header files.  In C++, no warnings are issued for function templates,
+header files.  In C, no warnings are issued for functions with previous
+non-prototype declarations; use @option{-Wmissing-prototype} to detect
+missing prototypes.  In C++, no warnings are issued for function templates,
 or for inline functions, or for functions in anonymous namespaces.
 
 @item -Wmissing-field-initializers

[v3] Correct C++11 status table

[Jonathan Wakely]

The status table doesn't mention the fact we're missing the new const
char* constructors from all the exception classes.

* doc/xml/manual/status_cxx2011.xml: Correct C++11 status table.

Tested with make doc-xml-validate-docbook doc-html, committed to trunk.
commit 7cb382e8086a3769ae4085714b735f9405820424
Author: Jonathan Wakely 
Date:   Fri Jun 1 01:41:53 2012 +0100

* doc/xml/manual/status_cxx2011.xml: Correct C++11 status table.

diff --git a/libstdc++-v3/doc/xml/manual/status_cxx2011.xml 
b/libstdc++-v3/doc/xml/manual/status_cxx2011.xml
index 0ed63ea..15d1337 100644
--- a/libstdc++-v3/doc/xml/manual/status_cxx2011.xml
+++ b/libstdc++-v3/doc/xml/manual/status_cxx2011.xml
@@ -274,10 +274,11 @@ particular release.
   
 
 
+  
   19.2
   Exception classes
-  Y
-  
+  Partial
+  Missing const char* constructors.
 
 
   19.3
@@ -322,10 +323,11 @@ particular release.
   
 
 
+  
   19.5.5
   Class system_error
-  Y
-  
+  Partial
+  Missing const char* constructors.
 
 
   

[PATCH 0/5] Aggregate jump functions

[Martin Jambor]

Hi,

this patch set extends the current jump functions we use in
ipa-prop.[ch], ipa-inline-analysis.c and ipa-cp.c to also carry
information about aggregates passed across function calls in a
parameter, regardless whether by value or only by reference.

The long term goal is that these description of passed aggregate
contents will be as general as possible (and reasonable) with a number
of use cases, including for example devirtualization.  However, the
initial implementation was specifically aimed at Fortran array
descriptors which represent optimization barrier which we can
currently overcome only by cranking up general inlining limits (with
all potential drawbacks that has).  Arguably I have not gone all the
way, but these patches now can inline the testcase from PR 48636
(comment #4) at -O3 and the limit increase necessary to speed up
fatigue2 polyhedron benchmark has also decreased quite a bit.

The patches making use of the aggregate jump functions so far only
improve inlining, IPA-CP bits are yet to come.

The state of the patches is somewhere in between RFC and submission
material, I certainly expect comments, suggestions and some discussion
(meanwhile I'd like to add a few more testcases and experiment a
little more on other benchmarks) but the patches are now quite stable.
Last but not least, they all pass bootstrap and testing on
x86_64-linux.

Thanks,

Martin

[PATCH 1/5] Access methods for jump functions

[Martin Jambor]

Hi,

the first patch mainly introduces access methods to read parts of jump
functions.  I am no particular fan of these but the are now more
widely spread than originally and above all checking asserts verifying
that the correct part of the union is read should really be useful.

I have also unified creation of jump function in ipa-prop.c to new
functions so that all fields are initialized.  On the contrary, I have
left update_jump_functions_after_inlining largely alone because it
modifies jump functions in place (and there may be good reason not to
touch some parts in the future, if not now), dumping functions and
streaming because they are a bit special and simple too.

There is also a tiny amount of other cleanup.

Bootstrapped separately on x86_64-linux.  OK for trunk?

Thanks,

Martin



2012-05-03  Martin Jambor  

* ipa-prop.h (ipa_get_jf_known_type_offset): New function.
(ipa_get_jf_known_type_base_type): Likewise.
(ipa_get_jf_known_type_component_type): Likewise.
(ipa_get_jf_constant): Likewise.
(ipa_get_jf_pass_through_formal_id): Likewise.
(ipa_get_jf_pass_through_operation): Likewise.
(ipa_get_jf_ancestor_offset): Likewise.
(ipa_get_jf_ancestor_type): Likewise.
(ipa_get_jf_ancestor_formal_id): Likewise.
(ipa_get_jf_member_ptr_pfn): Likewise.

* ipa-prop.c (ipa_set_jf_known_type): New function.
(ipa_set_jf_constant): Likewise.
(ipa_set_jf_simple_pass_through): Likewise.
(ipa_set_jf_arith_pass_through): Likewise.
(ipa_set_ancestor_jf): Likewise.
(fill_member_ptr_cst_jump_function): Moved up and renamed to
ipa_set_jf_member_ptr_cst.
(detect_type_change_1): Use the new jump function creation functions.
(compute_complex_assign_jump_func): Likewise.
(compute_complex_ancestor_jump_func): Likewise.
(compute_known_type_jump_func): Likewise.
(compute_scalar_jump_functions): Likewise.
(compute_pass_through_member_ptrs): Likewise.
(determine_cst_member_ptr): Likewise.
(combine_known_type_and_ancestor_jfs): Likewise.
(try_make_edge_direct_simple_call): Likewise.
(try_make_edge_direct_virtual_call): Likewise.
(update_indirect_edges_after_inlining): Likewise.

* ipa-cp.c (ipa_get_jf_pass_through_result): Use jump function
access functions.  Incorporat NOP_EXPR and BINFO handling from its
callers.
(ipa_get_jf_ancestor_result): Likewise.  Incorporate handling BINFOs
which was in its callers.
(ipa_value_from_jfunc): Use jump function access functions.  Some
functionality moved to functions above.
(propagate_vals_accross_ancestor): Likewise.
(propagate_vals_accross_pass_through): Use jump function access
functions.
(propagate_accross_jump_function): Likewise.

* ipa-inline-analysis.c (remap_edge_change_prob): Use jump function
access functions.
(inline_merge_summary): Likewise.

Index: src/gcc/ipa-cp.c
===
--- src.orig/gcc/ipa-cp.c
+++ src/gcc/ipa-cp.c
@@ -638,17 +638,19 @@ ipa_get_jf_pass_through_result (struct i
 {
   tree restype, res;
 
-  gcc_checking_assert (is_gimple_ip_invariant (input));
-  if (jfunc->value.pass_through.operation == NOP_EXPR)
+  if (ipa_get_jf_pass_through_operation (jfunc) == NOP_EXPR)
 return input;
+  else if (TREE_CODE (input) == TREE_BINFO)
+return NULL_TREE;
 
-  if (TREE_CODE_CLASS (jfunc->value.pass_through.operation)
+  gcc_checking_assert (is_gimple_ip_invariant (input));
+  if (TREE_CODE_CLASS (ipa_get_jf_pass_through_operation (jfunc))
   == tcc_comparison)
 restype = boolean_type_node;
   else
 restype = TREE_TYPE (input);
-  res = fold_binary (jfunc->value.pass_through.operation, restype,
-input, jfunc->value.pass_through.operand);
+  res = fold_binary (ipa_get_jf_pass_through_operation (jfunc), restype,
+input, ipa_get_jf_pass_through_operand (jfunc));
 
   if (res && !is_gimple_ip_invariant (res))
 return NULL_TREE;
@@ -662,12 +664,16 @@ ipa_get_jf_pass_through_result (struct i
 static tree
 ipa_get_jf_ancestor_result (struct ipa_jump_func *jfunc, tree input)
 {
-  if (TREE_CODE (input) == ADDR_EXPR)
+  if (TREE_CODE (input) == TREE_BINFO)
+return get_binfo_at_offset (input,
+   ipa_get_jf_ancestor_offset (jfunc),
+   ipa_get_jf_ancestor_type (jfunc));
+  else if (TREE_CODE (input) == ADDR_EXPR)
 {
   tree t = TREE_OPERAND (input, 0);
   t = build_ref_for_offset (EXPR_LOCATION (t), t,
-   jfunc->value.ancestor.offset,
-   jfunc->value.ancestor.type, NULL, false);
+   ipa_get_jf_ancestor_offset (jfunc),
+   ipa_get_jf_ancestor_type (jfun

[PATCH 5/5] Compute predicates for phi node results in ipa-inline-analysis.c

[Martin Jambor]

Hi,

this patch is basically a proof-of-concept aiming at alleviating the
following code found in Fortran functions when they look at the
contents of array descriptors:

  :
stride.156_7 = strain_tensor_6(D)->dim[0].stride;
if (stride.156_7 != 0)
  goto ;
else
  goto ;

  :

  :
# stride.156_4 = PHI 

and stride.156_4 is then used for other computations.  Currently we
compute a predicate for SSA name stride.156_7 but the PHI node stops
us from having one for stride.156_4 and those computed from it.

This patch looks at phi nodes, and if its pairs of predecessors have
the same nearest common dominator, and the condition there is known to
be described by a predicate (computed either by
set_cond_stmt_execution_predicate or,
set_switch_stmt_execution_predicate, we depend on knowing how exactly
they behave), we use the parameter and offset from the predicate
condition and create one for the PHI node result, provided the
arguments of a phi node allow that, of course.

I hacked this together one evening a few days ago and I expect to talk
with Honza about how to do this properly, nevertheless the patch
passes bootstrap and testing on x86_64.

On current trunk, I need to pass -finline-limit=204 to cut down
execution time of fatigue2 polyhedron benchmark from 155 seconds to 91
seconds.  With the patch, I only need -finline-limit=166.  So there's
still some way to go but something along these lines can be part of
it.

Thanks for all comments and suggestions,

Martin


2012-05-30  Martin Jambor  

* ipa-inline-analysis.c (known_phi_condition_for_bb): New function.
(predicate_for_phi_result): Likewise.
(estimate_function_body_sizes): Use the above two functions.
(inline_analyze_function): Calculate and free dominance info.


Index: src/gcc/ipa-inline-analysis.c
===
--- src.orig/gcc/ipa-inline-analysis.c
+++ src/gcc/ipa-inline-analysis.c
@@ -1998,6 +1998,96 @@ param_change_prob (gimple stmt, int i)
   return REG_BR_PROB_BASE;
 }
 
+/* For basic block BB, find if all pairs of its predecesors have a common
+   dominator and if that dominator ends with a simple condition.  If so, return
+   TRUE and stor pointer to *C.  */
+
+static bool
+known_phi_condition_for_bb (struct inline_summary *info, basic_block bb,
+   struct condition **c)
+{
+  edge_iterator ei;
+  edge e;
+  basic_block computed_dom = NULL;
+  basic_block prev = NULL;
+
+  FOR_EACH_EDGE (e, ei, bb->preds)
+{
+  if (prev)
+   {
+ basic_block dom = nearest_common_dominator (CDI_DOMINATORS, prev,
+ e->src);
+ if (!computed_dom)
+   computed_dom = dom;
+ else if (dom != computed_dom)
+   return false;
+
+   }
+  prev = e->src;
+}
+
+  if (!computed_dom)
+return false;
+
+  FOR_EACH_EDGE (e, ei, computed_dom->succs)
+if (e->aux)
+  {
+   struct predicate *p;
+   int i;
+   p = (struct predicate *) e->aux;
+
+   if (p->clause[0] == 0 || p->clause[1] != 0)
+ return false;
+   for (i = 0 ; i < NUM_CONDITIONS; i++)
+ if (((1 << i) & p->clause[0]) == p->clause[0])
+   break;
+   if (i == NUM_CONDITIONS || i < predicate_first_dynamic_condition)
+ return false;
+
+   *c = VEC_index (condition, info->conds,
+   i - predicate_first_dynamic_condition);
+   return true;
+  }
+  return false;
+}
+
+/* Given a PHI statement STMT in a function described by inline properties INFO
+   and in a basic lock whose predecesors in CFG is selected according to a
+   parameter (and potentially offset) stored in condition *C, store a predicate
+   for the result of the PHI statement into NONCONSTANT_NAMES, if possible.  */
+
+static void
+predicate_for_phi_result (struct inline_summary *info, gimple stmt,
+ struct condition *c,
+ VEC (predicate_t, heap) *nonconstant_names)
+{
+  struct predicate p;
+  unsigned i;
+
+  for (i = 0; i < gimple_phi_num_args (stmt); i++)
+{
+  tree arg = gimple_phi_arg (stmt, i)->def;
+  if (!is_gimple_min_invariant (arg))
+   {
+ gcc_assert (TREE_CODE (arg) == SSA_NAME);
+ if (true_predicate_p (VEC_index (predicate_t, nonconstant_names,
+   SSA_NAME_VERSION (arg
+ return;
+   }
+}
+
+  p = add_condition (info, c->operand_num, c->agg_contents, c->offset,
+CHANGED, NULL);
+  if (dump_file && (dump_flags & TDF_DETAILS))
+{
+  fprintf (dump_file, "  ");
+  print_gimple_stmt (dump_file, stmt, 0, 0);
+  fprintf (dump_file, "\t\tphi predicate: ");
+  dump_predicate (dump_file, info->conds, &p);
+}
+  VEC_replace (predicate_t, nonconstant_names,
+  SSA_NAME_VERSION (gimple_phi_result (stmt)), &p);
+}
 
 /* Compute f