gcc-wwwdocs branch master updated. 0f957c9f31938c9d83e87c773052e5fe77ffaad9
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- Log -
commit 0f957c9f31938c9d83e87c773052e5fe77ffaad9
Author: Richard Sandiford
Date: Wed Apr 23 17:56:54 2025 +0100
Document AArch64 changes for GCC 15
The list is structured as:
- configurations changes
- command-line changes
- ACLE changes
- everything else
As usual, the list of new architectures, CPUs, and features is from a
purely mechanical trawl of the associated .def files. I've identified
features by their architectural name to try to improve searchability.
Similarly, the list of ACLE changes includes the associated ACLE
feature macros, again to try to improve searchability.
The list summarises some of the target-specific optimisations because
it sounded like Tamar had received feedback that people found such
information interesting.
I've used the passive tense for most entries, to try to follow the
style used elsewhere.
diff --git a/htdocs/gcc-15/changes.html b/htdocs/gcc-15/changes.html
index 89b38955..0a2da09c 100644
--- a/htdocs/gcc-15/changes.html
+++ b/htdocs/gcc-15/changes.html
@@ -686,7 +686,261 @@ asm (".text; %cc0: mov %cc2, %%r0; .previous;"
New Targets and Target Specific Improvements
-
+AArch64
+
+
+ Support has been added for the AArch64 MinGW target
+(aarch64-w64-mingw32). At present, this target
+supports C and C++ for base Armv8-A, but with some caveats:
+
+ Although most variadic functions work, the implementation
+of them is not yet complete.
+
+ C++ exception handling is not yet implemented.
+
+Further work is planned for GCC 16.
+
+ As noted above, support for ILP32 (-mabi=ilp32)
+has been deprecated and will be removed in a future release.
+aarch64*-elf targets no longer build the ILP32 multilibs.
+
+ The following architecture level is now supported by
+-march and related source-level constructs
+(GCC identifiers in parentheses):
+
+ Armv9.5-A (arm9.5-a)
+
+
+ The following CPUs are now supported by -mcpu,
+-mtune, and related source-level constructs
+(GCC identifiers in parentheses):
+
+ Apple A12 (apple-a12)
+ Apple M1 (apple-m1)
+ Apple M2 (apple-m2)
+ Apple M3 (apple-m3)
+ Arm Cortex-A520AE (cortex-a520ae)
+ Arm Cortex-A720AE (cortex-a720ae)
+ Arm Cortex-A725 (cortex-a725)
+ Arm Cortex-R82AE (cortex-r82ae)
+ Arm Cortex-X925 (cortex-x925)
+ Arm Neoverse N3 (neoverse-n3)
+ Arm Neoverse V3 (neoverse-v3)
+ Arm Neoverse V3AE (neoverse-v3ae)
+ FUJITSU-MONAKA (fujitsu-monaka)
+ NVIDIA Grace (grace)
+ NVIDIA Olympus (olympus)
+ Qualcomm Oryon-1 (oryon-1)
+
+
+ The following features are now supported by -march,
+-mcpu, and related source-level constructs
+(GCC modifiers in parentheses):
+
+ FEAT_CPA (+cpa), enabled by default for
+Arm9.5-A and above
+
+ FEAT_FAMINMAX (+faminmax), enabled by default for
+Arm9.5-A and above
+
+ FEAT_FCMA (+fcma), enabled by default for Armv8.3-A
+and above
+
+ FEAT_FLAGM2 (+flagm2), enabled by default for
+Armv8.5-A and above
+
+ FEAT_FP8 (+fp8)
+ FEAT_FP8DOT2 (+fp8dot2)
+ FEAT_FP8DOT4 (+fp8dot4)
+ FEAT_FP8FMA (+fp8fma)
+ FEAT_FRINTTS (+frintts), enabled by default for
+Armv8.5-A and above
+
+ FEAT_JSCVT (+jscvt), enabled by default for
+Armv8.3-A and above
+
+ FEAT_LUT (+lut), enabled by default for
+Arm9.5-A and above
+
+ FEAT_LRCPC2 (+rcpc2), enabled by default for
+Armv8.4-A and above
+
+ FEAT_SME_B16B16 (+sme-b16b16)
+ FEAT_SME_F16F16 (+sme-f16f16)
+ FEAT_SME2p1 (+sme2p1)
+ FEAT_SSVE_FP8DOT2 (+ssve-fp8dot2)
+ FEAT_SSVE_FP8DOT4 (+ssve-fp8dot4)
+ FEAT_SSVE_FP8FMA (+ssve-fp8fma)
+ FEAT_SVE_B16B16 (+sve-b16b16)
+ FEAT_SVE2p1 (+sve2p1), enabled by default for
+Armv9.4-A and above
+
+ FEAT_WFXT (+wfxt), enabled by default for
+Armv8.7-A and above
+
+ FEAT_XS (+xs), enabled by default for
+Armv8.7-A and above
+
+
+The features listed as being enabled by default for Armv8.7-A or earlier
+were previously only selectable using the associated architecture level.
+For example, FEAT_FCMA was previously selected by
+-march=armv8.3-a and above
gcc-wwwdocs branch master updated. 9e55d3a4d3db8659d9e6cb11d0dc85627c29d46f
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- Log -
commit 9e55d3a4d3db8659d9e6cb11d0dc85627c29d46f
Author: Richard Sandiford
Date: Fri Apr 25 11:03:02 2025 +0100
Tweak AArch64 FEAT_SSVE_* entries
Add "in Streaming SVE mode", to reduce ambiguity with the
preceding entries.
diff --git a/htdocs/gcc-15/changes.html b/htdocs/gcc-15/changes.html
index a71249ff..3cec4ff4 100644
--- a/htdocs/gcc-15/changes.html
+++ b/htdocs/gcc-15/changes.html
@@ -847,17 +847,20 @@ asm (".text; %cc0: mov %cc2, %%r0; .previous;"
instructions (predefined macro __ARM_FEATURE_FP8FMA,
enabled by +fp8fma)
- SVE FP8 2-way dot product to half precision instructions
-(predefined macro __ARM_FEATURE_SSVE_FP8DOT2,
-enabled by +ssve-fp8dot2)
+ SVE FP8 2-way dot product to half precision instructions in
+Streaming SVE mode (predefined macro
+__ARM_FEATURE_SSVE_FP8DOT2, enabled by
++ssve-fp8dot2)
- SVE FP8 4-way dot product to single precision instructions
-(predefined macro __ARM_FEATURE_SSVE_FP8DOT4,
-enabled by +ssve-fp8dot4)
+ SVE FP8 4-way dot product to single precision instructions in
+Streaming SVE mode (predefined macro
+__ARM_FEATURE_SSVE_FP8DOT4, enabled by
++ssve-fp8dot4)
SVE FP8 multiply-accumulate to half precision and single precision
-instructions (predefined macro __ARM_FEATURE_SSVE_FP8FMA,
-enabled by +ssve-fp8fma)
+instructions in Streaming SVE mode (predefined macro
+__ARM_FEATURE_SSVE_FP8FMA, enabled by
++ssve-fp8fma)
SVE2.1 instructions (predefined macro
__ARM_FEATURE_SVE2p1, enabled by +sve2p1)
---
Summary of changes:
htdocs/gcc-15/changes.html | 19 +++
1 file changed, 11 insertions(+), 8 deletions(-)
hooks/post-receive
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gcc-wwwdocs branch master updated. 04332b5fde5e09ee08a735897560162616d5a731
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commit 04332b5fde5e09ee08a735897560162616d5a731
Author: Heiko EiÃfeldt
Date: Fri May 30 17:23:40 2025 +0100
Fix typos in GCC 15 release notes
diff --git a/htdocs/gcc-15/changes.html b/htdocs/gcc-15/changes.html
index 541b3726..5d35253a 100644
--- a/htdocs/gcc-15/changes.html
+++ b/htdocs/gcc-15/changes.html
@@ -62,14 +62,14 @@ You may also want to check out our
The default vectorizer cost model at -O2 has been enhanced
-to handle unknown tripcount. But it still disables vectorization of loops
+to handle an unknown tripcount. But it still disables vectorization of
loops
when any runtime check for data dependence or alignment is required,
it also disables vectorization of epilogue loops but otherwise is equal
to the cheap cost model.
The vectorizer now supports vectorizing loops with early exits where
the number of elements for the input pointers are unknown through peeling
-for alignment. This is supported for only for loops with fixed vector
+for alignment. This is supported only for loops with fixed vector
lengths.
-ftime-report now only reports monotonic run time instead of
@@ -92,7 +92,7 @@ You may also want to check out our
Improvements for compiling very large input files. The compile time for
large input files with -Wmisleading-indentation has been
-significantly improved. The compiler can now track columnn numbers larger
+significantly improved. The compiler can now track column numbers larger
than 4096. Very large source files have more accurate location reporting.
GCC can now emit diagnostics in multiple formats simultaneously,
@@ -291,7 +291,7 @@ procedure Initialize (Obj : in out T);
for more information.
-The diagnostics code has seen a major refactor, it now supports the sarif
+The diagnostics code has seen major refactoring, it now supports the sarif
format -fdiagnostics-format=sarif-file among other
improvements. More changes are expected in following releases.
@@ -751,7 +751,7 @@ asm (".text; %cc0: mov %cc2, %%r0; .previous;"
and -fc-prototypes-external options.
-The -fc-prototypes now also generates prototypes for
+The -fc-prototypes option now also generates prototypes for
interoperable procedures with assumed shape and assumed rank
arguments that require the header file
.
@@ -775,7 +775,7 @@ asm (".text; %cc0: mov %cc2, %%r0; .previous;"
Access to the GCC
builtins clz, clzll, ctz
-and ctzll are now available from the
+and ctzll is now available from the
module Builtins.
@@ -791,7 +791,7 @@ the architecture specific functions of core
1.49.
Fixes to our automatic dereferencing algorithm for Deref and
-DerefMut. This makes gccrs more correct and allow to
handle
+DerefMut. This makes gccrs more correct and allows
handling
complicated cases where the type-checker would previously fail.
@@ -824,7 +824,7 @@ required for compiling core 1.49 correctly, in
which specialization
improve the runtime performance of Rust binaries.
- Support for more lang-items has been added
+ Support for more lang-items has been added.
Lowered minimum required Rust version to 1.49. This allows more systems to
compile the Rust
@@ -833,7 +833,7 @@ the line.
Rewrite of our name resolution algorithm to properly handle the complex
import/export
-structure used in core 1.49
+structure used in core 1.49.
@@ -1208,7 +1208,7 @@ structure used in core 1.49
AMX-TRANSPOSE intrinsics are available via the
-mamx-transpose
compiler switch.
- All of new feature support for Intel APX expect for CFCMOV was added,
+ All of new feature support for Intel APX except for CFCMOV was added,
including CCMP/CTEST, NF and ZU. APX support is available via the
-mapxf compiler switch.
@@ -1268,7 +1268,7 @@ structure used in core 1.49
Support has been added for the new option
https://gcc.gnu.org/onlinedocs/gcc-15.1.0/gcc/LoongArch-Options.html#index-mannotate-tablejump";>
- -mannotate-tablejump. Which can create an annotation
+ -mannotate-tablejump, which can create an annotation
section .discard.tablejump_annotate to correlate the
jirl instruction and the jump table.
--
