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commit 0f957c9f31938c9d83e87c773052e5fe77ffaad9
Author: Richard Sandiford
Date: Wed Apr 23 17:56:54 2025 +0100
Document AArch64 changes for GCC 15
The list is structured as:
- configurations changes
- command-line changes
- ACLE changes
- everything else
As usual, the list of new architectures, CPUs, and features is from a
purely mechanical trawl of the associated .def files. I've identified
features by their architectural name to try to improve searchability.
Similarly, the list of ACLE changes includes the associated ACLE
feature macros, again to try to improve searchability.
The list summarises some of the target-specific optimisations because
it sounded like Tamar had received feedback that people found such
information interesting.
I've used the passive tense for most entries, to try to follow the
style used elsewhere.
diff --git a/htdocs/gcc-15/changes.html b/htdocs/gcc-15/changes.html
index 89b38955..0a2da09c 100644
--- a/htdocs/gcc-15/changes.html
+++ b/htdocs/gcc-15/changes.html
@@ -686,7 +686,261 @@ asm (".text; %cc0: mov %cc2, %%r0; .previous;"
New Targets and Target Specific Improvements
-
+AArch64
+
+
+ Support has been added for the AArch64 MinGW target
+(aarch64-w64-mingw32). At present, this target
+supports C and C++ for base Armv8-A, but with some caveats:
+
+ Although most variadic functions work, the implementation
+of them is not yet complete.
+
+ C++ exception handling is not yet implemented.
+
+Further work is planned for GCC 16.
+
+ As noted above, support for ILP32 (-mabi=ilp32)
+has been deprecated and will be removed in a future release.
+aarch64*-elf targets no longer build the ILP32 multilibs.
+
+ The following architecture level is now supported by
+-march and related source-level constructs
+(GCC identifiers in parentheses):
+
+ Armv9.5-A (arm9.5-a)
+
+
+ The following CPUs are now supported by -mcpu,
+-mtune, and related source-level constructs
+(GCC identifiers in parentheses):
+
+ Apple A12 (apple-a12)
+ Apple M1 (apple-m1)
+ Apple M2 (apple-m2)
+ Apple M3 (apple-m3)
+ Arm Cortex-A520AE (cortex-a520ae)
+ Arm Cortex-A720AE (cortex-a720ae)
+ Arm Cortex-A725 (cortex-a725)
+ Arm Cortex-R82AE (cortex-r82ae)
+ Arm Cortex-X925 (cortex-x925)
+ Arm Neoverse N3 (neoverse-n3)
+ Arm Neoverse V3 (neoverse-v3)
+ Arm Neoverse V3AE (neoverse-v3ae)
+ FUJITSU-MONAKA (fujitsu-monaka)
+ NVIDIA Grace (grace)
+ NVIDIA Olympus (olympus)
+ Qualcomm Oryon-1 (oryon-1)
+
+
+ The following features are now supported by -march,
+-mcpu, and related source-level constructs
+(GCC modifiers in parentheses):
+
+ FEAT_CPA (+cpa), enabled by default for
+Arm9.5-A and above
+
+ FEAT_FAMINMAX (+faminmax), enabled by default for
+Arm9.5-A and above
+
+ FEAT_FCMA (+fcma), enabled by default for Armv8.3-A
+and above
+
+ FEAT_FLAGM2 (+flagm2), enabled by default for
+Armv8.5-A and above
+
+ FEAT_FP8 (+fp8)
+ FEAT_FP8DOT2 (+fp8dot2)
+ FEAT_FP8DOT4 (+fp8dot4)
+ FEAT_FP8FMA (+fp8fma)
+ FEAT_FRINTTS (+frintts), enabled by default for
+Armv8.5-A and above
+
+ FEAT_JSCVT (+jscvt), enabled by default for
+Armv8.3-A and above
+
+ FEAT_LUT (+lut), enabled by default for
+Arm9.5-A and above
+
+ FEAT_LRCPC2 (+rcpc2), enabled by default for
+Armv8.4-A and above
+
+ FEAT_SME_B16B16 (+sme-b16b16)
+ FEAT_SME_F16F16 (+sme-f16f16)
+ FEAT_SME2p1 (+sme2p1)
+ FEAT_SSVE_FP8DOT2 (+ssve-fp8dot2)
+ FEAT_SSVE_FP8DOT4 (+ssve-fp8dot4)
+ FEAT_SSVE_FP8FMA (+ssve-fp8fma)
+ FEAT_SVE_B16B16 (+sve-b16b16)
+ FEAT_SVE2p1 (+sve2p1), enabled by default for
+Armv9.4-A and above
+
+ FEAT_WFXT (+wfxt), enabled by default for
+Armv8.7-A and above
+
+ FEAT_XS (+xs), enabled by default for
+Armv8.7-A and above
+
+
+The features listed as being enabled by default for Armv8.7-A or earlier
+were previously only selectable using the associated architecture level.
+For example, FEAT_FCMA was previously selected by
+-march=armv8.3-a and above
