gcc-wwwdocs branch master updated. 033976162ed4745f7f808f14ba62b1c055e35d16
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commit 033976162ed4745f7f808f14ba62b1c055e35d16
Author: Haochen Jiang
Date: Fri Apr 12 16:34:48 2024 +0800
Uncomment MCore part title
diff --git a/htdocs/gcc-14/changes.html b/htdocs/gcc-14/changes.html
index 14301157..8ac08e9a 100644
--- a/htdocs/gcc-14/changes.html
+++ b/htdocs/gcc-14/changes.html
@@ -828,7 +828,7 @@ __asm (".global __flmap_lock" "\n\t"
-
+MCore
Bitfields are now signed by default per GCC policy. If you need
bitfields
to be unsigned, use -funsigned-bitfields.
---
Summary of changes:
htdocs/gcc-14/changes.html | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
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gcc-wwwdocs branch master updated. 7314f133f386fd3cc0e95bf266436576f89d335e
This is an automated email from the git hooks/post-receive script. It was generated because a ref change was pushed to the repository containing the project "gcc-wwwdocs". The branch, master has been updated via 7314f133f386fd3cc0e95bf266436576f89d335e (commit) from 56edd34fc291a0b46a4eb15e0aa835953b1eab6c (commit) Those revisions listed above that are new to this repository have not appeared on any other notification email; so we list those revisions in full, below. - Log - commit 7314f133f386fd3cc0e95bf266436576f89d335e Author: Haochen Jiang Date: Wed Aug 28 10:27:36 2024 +0800 gcc-15: Mention recent update for x86_64 backend Mention AVX10.2 support and Xeon Phi removal in GCC 15. diff --git a/htdocs/gcc-15/changes.html b/htdocs/gcc-15/changes.html index 91c020dd..edce138e 100644 --- a/htdocs/gcc-15/changes.html +++ b/htdocs/gcc-15/changes.html @@ -149,7 +149,23 @@ a work-in-progress. code like 1 << offset is not fast enough. - +IA-32/x86-64 + + + New ISA extension support for Intel AVX10.2 was added. + AVX10.2 intrinsics are available via the -mavx10.2 or + -mavx10.2-256 compiler switch with 256-bit vector size + support. 512-bit vector size support for AVX10.2 intrinsics are + available via the -mavx10.2-512 compiler switch. + + Support for Xeon Phi CPUs (a.k.a. Knight Landing and Knight Mill) were + removed in GCC 15. GCC will no longer accept -march=knl, + -march=knm,-mavx5124fmaps, + -mavx5124vnniw, -mavx512er, + -mavx512pf, -mprefetchwt1, + -mtune=knl or -mtune=knm compiler switches. + + --- Summary of changes: htdocs/gcc-15/changes.html | 18 +- 1 file changed, 17 insertions(+), 1 deletion(-) hooks/post-receive -- gcc-wwwdocs
gcc-wwwdocs branch master updated. 5c57cf68b55578d49f4fca7389dfba35ddbb53b5
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commit 5c57cf68b55578d49f4fca7389dfba35ddbb53b5
Author: Haochen Jiang
Date: Thu Sep 19 14:50:56 2024 +0800
gcc-14: Mention -march=gracemont support in x86_64
diff --git a/htdocs/gcc-14/changes.html b/htdocs/gcc-14/changes.html
index e0d856cc..ba9fc680 100644
--- a/htdocs/gcc-14/changes.html
+++ b/htdocs/gcc-14/changes.html
@@ -944,6 +944,10 @@ __asm (".global __flmap_lock" "\n\t"
Based on Sierra Forest, the switch further enables the AVX-VNNI-INT16,
PREFETCHI, SHA512, SM3, SM4 and USER_MSR ISA extensions.
+ GCC now supports the Intel CPU named Gracemont through
+-march=gracemont.
+Gracemont is based on Alder Lake.
+
GCC now supports the Intel CPU named Arrow Lake through
-march=arrowlake.
Based on Alder Lake, the switch further enables the AVX-IFMA,
---
Summary of changes:
htdocs/gcc-14/changes.html | 4
1 file changed, 4 insertions(+)
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gcc-wwwdocs branch master updated. 97538a42abcad8ffe9784c09c9559bff610eb2be
This is an automated email from the git hooks/post-receive script. It was generated because a ref change was pushed to the repository containing the project "gcc-wwwdocs". The branch, master has been updated via 97538a42abcad8ffe9784c09c9559bff610eb2be (commit) from 1ffabd5b457b3419c0d2b49748a123f0a6199b41 (commit) Those revisions listed above that are new to this repository have not appeared on any other notification email; so we list those revisions in full, below. - Log - commit 97538a42abcad8ffe9784c09c9559bff610eb2be Author: Haochen Jiang Date: Mon Nov 11 11:13:12 2024 +0800 gcc-15: Mention new ISA and Diamond Rapids support for x86_64 backend diff --git a/htdocs/gcc-15/changes.html b/htdocs/gcc-15/changes.html index 790a3acc..80604ab8 100644 --- a/htdocs/gcc-15/changes.html +++ b/htdocs/gcc-15/changes.html @@ -195,18 +195,56 @@ a work-in-progress. IA-32/x86-64 + New ISA extension support for Intel AMX-AVX512 was added. + AMX-AVX512 intrinsics are available via the -mamx-avx512 + compiler switch. + + New ISA extension support for Intel AMX-FP8 was added. + AMX-FP8 intrinsics are available via the -mamx-fp8 + compiler switch. + + New ISA extension support for Intel AMX-MOVRS was added. + AMX-MOVRS intrinsics are available via the -mamx-movrs + compiler switch. + + New ISA extension support for Intel AMX-TF32 was added. + AMX-TF32 intrinsics are available via the -mamx-tf32 + compiler switch. + + New ISA extension support for Intel AMX-TRANSPOSE was added. + AMX-TRANSPOSE intrinsics are available via the -mamx-transpose + compiler switch. + New ISA extension support for Intel AVX10.2 was added. AVX10.2 intrinsics are available via the -mavx10.2 or -mavx10.2-256 compiler switch with 256-bit vector size support. 512-bit vector size support for AVX10.2 intrinsics are available via the -mavx10.2-512 compiler switch. + New ISA extension support for Intel MOVRS was added. + MOVRS intrinsics are available via the -mmovrs + compiler switch. 128- and 256- bit MOVRS intrinsics are available via + the -mmovrs -mavx10.2 compiler switch. 512-bit MOVRS + intrinsics are available via the -mmovrs -mavx10.2-512 + compiler switch. + + EVEX version support for Intel SM4 was added. + New 512-bit SM4 intrinsics are available via the + -msm4 -mavx10.2-512 compiler switch. + + GCC now supports the Intel CPU named Diamond Rapids through +-march=diamondrapids. +Based on Granite Rapids, the switch further enables the AMX-AVX512, +AMX-FP8, AMX-MOVRS, AMX-TF32, AMX-TRANSPOSE, APX_F, AVX10.2 with 512-bit +support, AVX-IFMA. AVX-NE-CONVERT, AVX-VNNI-INT16, AVX-VNNI-INT8, +CMPccXADD, MOVRS, SHA512, SM3, SM4 and USER_MSR ISA extensions. + Support for Xeon Phi CPUs (a.k.a. Knight Landing and Knight Mill) were - removed in GCC 15. GCC will no longer accept -march=knl, - -march=knm,-mavx5124fmaps, + removed in GCC 15. GCC will no longer accepts -march=knl, + -march=knm, -mavx5124fmaps, -mavx5124vnniw, -mavx512er, -mavx512pf, -mprefetchwt1, - -mtune=knl or -mtune=knm compiler switches. + -mtune=knl and -mtune=knm compiler switches. --- Summary of changes: htdocs/gcc-15/changes.html | 44 +--- 1 file changed, 41 insertions(+), 3 deletions(-) hooks/post-receive -- gcc-wwwdocs
gcc-wwwdocs branch master updated. 5150c5e18b9a6a83a19d1aa9f352d304c638e242
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commit 5150c5e18b9a6a83a19d1aa9f352d304c638e242
Author: Haochen Jiang
Date: Tue Apr 8 10:50:49 2025 +0800
gcc-14/15: Mention recent change for Intel x86_64
Mention AVX10.1 option changes, revise AVX10.2 option and mention
APX_F new feature in GCC 15.
diff --git a/htdocs/gcc-14/changes.html b/htdocs/gcc-14/changes.html
index d720ab87..41047b7f 100644
--- a/htdocs/gcc-14/changes.html
+++ b/htdocs/gcc-14/changes.html
@@ -925,10 +925,13 @@ __asm (".global __flmap_lock" "\n\t"
instruction supports EGPR.
New ISA extension support for Intel AVX10.1 was added.
- AVX10.1 intrinsics are available via the -mavx10.1 or
- -mavx10.1-256 compiler switch with 256-bit vector size
- support. 512-bit vector size support for AVX10.1 intrinsics are
- available via the -mavx10.1-512 compiler switch.
+ AVX10.1 intrinsics are available via the -mavx10.1-256
+ compiler switch with 256-bit vector support. 512-bit vector support
+ for AVX10.1 intrinsics are available via the -mavx10.1-512
+ compiler switch. -mavx10.1 enables AVX10.1 intrinsics with
+ 256-bit vector support in GCC 14.1 and GCC 14.2. Since GCC 14.3, it
+ enables AVX10.1 intrinsics with 512-bit vector support (and emits a
+ warning due to this behavior change).
New ISA extension support for Intel AVX-VNNI-INT16 was added.
AVX-VNNI-INT16 intrinsics are available via the
-mavxvnniint16
diff --git a/htdocs/gcc-15/changes.html b/htdocs/gcc-15/changes.html
index d51a2ed8..37da4c26 100644
--- a/htdocs/gcc-15/changes.html
+++ b/htdocs/gcc-15/changes.html
@@ -630,29 +630,29 @@ asm (".text; %cc0: mov %cc2, %%r0; .previous;"
AMX-TRANSPOSE intrinsics are available via the
-mamx-transpose
compiler switch.
+ All of new feature support for Intel APX expect for CFCMOV was added,
+ including CCMP/CTEST, NF and ZU. APX support is available via the
+ -mapxf compiler switch.
+
New ISA extension support for Intel AVX10.2 was added.
- AVX10.2 intrinsics are available via the -mavx10.2 or
- -mavx10.2-256 compiler switch with 256-bit vector size
- support. 512-bit vector size support for AVX10.2 intrinsics are
- available via the -mavx10.2-512 compiler switch.
+ AVX10.2 intrinsics are available via the -mavx10.2
+ compiler switch.
New ISA extension support for Intel MOVRS was added.
MOVRS intrinsics are available via the -mmovrs
- compiler switch. 128- and 256- bit MOVRS intrinsics are available via
- the -mmovrs -mavx10.2 compiler switch. 512-bit MOVRS
- intrinsics are available via the -mmovrs -mavx10.2-512
- compiler switch.
+ compiler switch. MOVRS vector intrinsics are available via
+ the -mmovrs -mavx10.2 compiler switches.
EVEX version support for Intel SM4 was added.
New 512-bit SM4 intrinsics are available via the
- -msm4 -mavx10.2-512 compiler switch.
+ -msm4 -mavx10.2 compiler switches.
GCC now supports the Intel CPU named Diamond Rapids through
-march=diamondrapids.
Based on Granite Rapids, the switch further enables the AMX-AVX512,
-AMX-FP8, AMX-MOVRS, AMX-TF32, AMX-TRANSPOSE, APX_F, AVX10.2 with 512-bit
-support, AVX-IFMA. AVX-NE-CONVERT, AVX-VNNI-INT16, AVX-VNNI-INT8,
-CMPccXADD, MOVRS, SHA512, SM3, SM4 and USER_MSR ISA extensions.
+AMX-FP8, AMX-MOVRS, AMX-TF32, AMX-TRANSPOSE, APX_F, AVX10.2, AVX-IFMA,
+AVX-NE-CONVERT, AVX-VNNI-INT16, AVX-VNNI-INT8, CMPccXADD, MOVRS, SHA512,
+SM3, SM4, and USER_MSR ISA extensions.
Support for Xeon Phi CPUs (a.k.a. Knight Landing and Knight Mill) were
removed in GCC 15. GCC will no longer accept -march=knl,
@@ -661,6 +661,15 @@ asm (".text; %cc0: mov %cc2, %%r0; .previous;"
-mavx512pf, -mprefetchwt1,
-mtune=knl, and -mtune=knm compiler switches.
+ -mavx10.1-256, -mavx10.1-512, and
+ -mevex512 are deprecated. Meanwhile, -mavx10.1
+ enables AVX10.1 intrinsics with 512-bit vector support, while in GCC 14.1
+ and GCC 14.2, it only enables 256-bit vector support. GCC will emit a
+ warning when using these compiler switches. -mavx10.1-256,
+ -mavx10.1-512, and -mevex512 will be removed in
+ GCC 16 together with the warning for the behavior change on
+ -mavx10.1.
+
With the -mveclibabi compiler switch GCC is able to generate
vectorized calls to ext
gcc-wwwdocs branch master updated. 7fae909b4b7f24a68c7f8bf019b4368e7a45cd1e
This is an automated email from the git hooks/post-receive script. It was generated because a ref change was pushed to the repository containing the project "gcc-wwwdocs". The branch, master has been updated via 7fae909b4b7f24a68c7f8bf019b4368e7a45cd1e (commit) from 07648bff40636f485254e27ccb2919dff1714fdf (commit) Those revisions listed above that are new to this repository have not appeared on any other notification email; so we list those revisions in full, below. - Log - commit 7fae909b4b7f24a68c7f8bf019b4368e7a45cd1e Author: Haochen Jiang Date: Fri Jun 13 11:09:28 2025 +0800 gcc-15: Correct DMR ISA base platform to include AMX-COMPLEX diff --git a/htdocs/gcc-15/changes.html b/htdocs/gcc-15/changes.html index 5d35253a..d0b289e1 100644 --- a/htdocs/gcc-15/changes.html +++ b/htdocs/gcc-15/changes.html @@ -1227,10 +1227,10 @@ structure used in core 1.49. GCC now supports the Intel CPU named Diamond Rapids through -march=diamondrapids. -Based on Granite Rapids, the switch further enables the AMX-AVX512, -AMX-FP8, AMX-MOVRS, AMX-TF32, AMX-TRANSPOSE, APX_F, AVX10.2, AVX-IFMA, -AVX-NE-CONVERT, AVX-VNNI-INT16, AVX-VNNI-INT8, CMPccXADD, MOVRS, SHA512, -SM3, SM4, and USER_MSR ISA extensions. +Based on ISA extensions enabled on Granite Rapids D, the switch further +enables the AMX-AVX512, AMX-FP8, AMX-MOVRS, AMX-TF32, AMX-TRANSPOSE, APX_F, +AVX10.2, AVX-IFMA, AVX-NE-CONVERT, AVX-VNNI-INT16, AVX-VNNI-INT8, +CMPccXADD, MOVRS, SHA512, SM3, SM4, and USER_MSR ISA extensions. Support for Xeon Phi CPUs (a.k.a. Knight Landing and Knight Mill) were removed in GCC 15. GCC will no longer accept -march=knl, --- Summary of changes: htdocs/gcc-15/changes.html | 8 1 file changed, 4 insertions(+), 4 deletions(-) hooks/post-receive -- gcc-wwwdocs
