[gcc r14-9362] rs6000: Don't ICE when compiling the __builtin_vsx_splat_2di [PR113950]
https://gcc.gnu.org/g:fa0468877869f52b05742de6deef582e4dd296fc
commit r14-9362-gfa0468877869f52b05742de6deef582e4dd296fc
Author: Jeevitha
Date: Thu Mar 7 07:41:38 2024 -0600
rs6000: Don't ICE when compiling the __builtin_vsx_splat_2di [PR113950]
When we expand the __builtin_vsx_splat_2di built-in, we were allowing
immediate
value for second operand which causes an unrecognizable insn ICE. Even
though
the immediate value was forced into a register, it wasn't correctly assigned
to the second operand. So corrected the assignment of op1 to operands[1].
2024-03-07 Jeevitha Palanisamy
gcc/
PR target/113950
* config/rs6000/vsx.md (vsx_splat_): Correct assignment to
operand1
and simplify else if with else.
gcc/testsuite/
PR target/113950
* gcc.target/powerpc/pr113950.c: New testcase.
Diff:
---
gcc/config/rs6000/vsx.md| 4 ++--
gcc/testsuite/gcc.target/powerpc/pr113950.c | 24
2 files changed, 26 insertions(+), 2 deletions(-)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 6111cc90eb7..f135fa079bd 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -4666,8 +4666,8 @@
rtx op1 = operands[1];
if (MEM_P (op1))
operands[1] = rs6000_force_indexed_or_indirect_mem (op1);
- else if (!REG_P (op1))
-op1 = force_reg (mode, op1);
+ else
+operands[1] = force_reg (mode, op1);
})
(define_insn "vsx_splat__reg"
diff --git a/gcc/testsuite/gcc.target/powerpc/pr113950.c
b/gcc/testsuite/gcc.target/powerpc/pr113950.c
new file mode 100644
index 000..359963d1041
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr113950.c
@@ -0,0 +1,24 @@
+/* PR target/113950 */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O2 -mvsx" } */
+
+/* Verify we do not ICE on the following. */
+
+void abort (void);
+
+int main ()
+{
+ int i;
+ vector signed long long vsll_result, vsll_expected_result;
+ signed long long sll_arg1;
+
+ sll_arg1 = 300;
+ vsll_expected_result = (vector signed long long) {300, 300};
+ vsll_result = __builtin_vsx_splat_2di (sll_arg1);
+
+ for (i = 0; i < 2; i++)
+if (vsll_result[i] != vsll_expected_result[i])
+ abort();
+
+ return 0;
+}
[gcc r15-1895] rs6000: load high and low part of 128bit vector independently [PR110040]
https://gcc.gnu.org/g:5be97039aa6c27fdf5d5bd43ef393b307c5ecedd
commit r15-1895-g5be97039aa6c27fdf5d5bd43ef393b307c5ecedd
Author: Jeevitha
Date: Mon Jul 8 06:09:49 2024 -0500
rs6000: load high and low part of 128bit vector independently [PR110040]
PR110040 exposes an issue concerning moves from vector registers to GPRs.
There are two moves, one for upper 64 bits and the other for the lower
64 bits. In the problematic test case, we are only interested in storing
the lower 64 bits. However, the instruction for copying the upper 64 bits
is still emitted and is dead code. This patch adds a splitter that splits
apart the two move instructions so that DCE can remove the dead code after
splitting.
2024-07-08 Jeevitha Palanisamy
gcc/
PR target/110040
* config/rs6000/vsx.md (split pattern for V1TI to DI move): New
define.
gcc/testsuite/
PR target/110040
* gcc.target/powerpc/pr110040-1.c: New testcase.
* gcc.target/powerpc/pr110040-2.c: New testcase.
Diff:
---
gcc/config/rs6000/vsx.md | 17 +
gcc/testsuite/gcc.target/powerpc/pr110040-1.c | 15 +++
gcc/testsuite/gcc.target/powerpc/pr110040-2.c | 16
3 files changed, 48 insertions(+)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 48ba262f7e48..23ce5c740510 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -6735,3 +6735,20 @@
"vmsumcud %0,%1,%2,%3"
[(set_attr "type" "veccomplex")]
)
+
+(define_split
+ [(set (match_operand:V1TI 0 "gpc_reg_operand")
+ (match_operand:V1TI 1 "vsx_register_operand"))]
+ "reload_completed
+ && TARGET_DIRECT_MOVE_64BIT
+ && int_reg_operand (operands[0], V1TImode)
+ && vsx_register_operand (operands[1], V1TImode)"
+ [(pc)]
+{
+ rtx src_op = gen_rtx_REG (V2DImode, REGNO (operands[1]));
+ rtx dest_op0 = gen_rtx_REG (DImode, REGNO (operands[0]));
+ rtx dest_op1 = gen_rtx_REG (DImode, REGNO (operands[0]) + 1);
+ emit_insn (gen_vsx_extract_v2di (dest_op0, src_op, const0_rtx));
+ emit_insn (gen_vsx_extract_v2di (dest_op1, src_op, const1_rtx));
+ DONE;
+})
diff --git a/gcc/testsuite/gcc.target/powerpc/pr110040-1.c
b/gcc/testsuite/gcc.target/powerpc/pr110040-1.c
new file mode 100644
index ..0a521e9e51d2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr110040-1.c
@@ -0,0 +1,15 @@
+/* PR target/110040 */
+/* { dg-do compile } */
+/* { dg-require-effective-target int128 } */
+/* { dg-require-effective-target powerpc_vsx } */
+/* { dg-options "-O2 -mdejagnu-cpu=power9" } */
+/* { dg-final { scan-assembler-not {\mmfvsrd\M} } } */
+
+#include
+
+void
+foo (signed long *dst, vector signed __int128 src)
+{
+ *dst = (signed long) src[0];
+}
+
diff --git a/gcc/testsuite/gcc.target/powerpc/pr110040-2.c
b/gcc/testsuite/gcc.target/powerpc/pr110040-2.c
new file mode 100644
index ..8236f3cbe223
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr110040-2.c
@@ -0,0 +1,16 @@
+/* PR target/110040 */
+/* { dg-do compile } */
+/* { dg-options "-O2 -mdejagnu-cpu=power10" } */
+/* { dg-require-effective-target int128 } */
+/* { dg-require-effective-target powerpc_vsx } */
+/* { dg-final { scan-assembler-not {\mmfvsrd\M} } } */
+
+/* builtin vec_xst_trunc requires power10. */
+
+#include
+
+void
+foo (signed int *dst, vector signed __int128 src)
+{
+ __builtin_vec_xst_trunc (src, 0, dst);
+}
[gcc r13-8474] rs6000: Don't ICE when compiling the __builtin_vsx_splat_2di [PR113950]
https://gcc.gnu.org/g:27eb6e81e6e578da9f9947d3f96c0fa58971fe7f
commit r13-8474-g27eb6e81e6e578da9f9947d3f96c0fa58971fe7f
Author: Jeevitha
Date: Wed Mar 20 23:34:46 2024 -0500
rs6000: Don't ICE when compiling the __builtin_vsx_splat_2di [PR113950]
When we expand the __builtin_vsx_splat_2di built-in, we were allowing
immediate
value for second operand which causes an unrecognizable insn ICE. Even
though
the immediate value was forced into a register, it wasn't correctly assigned
to the second operand. So corrected the assignment of op1 to operands[1].
2024-03-07 Jeevitha Palanisamy
gcc/
PR target/113950
* config/rs6000/vsx.md (vsx_splat_): Correct assignment to
operand1
and simplify else if with else.
gcc/testsuite/
PR target/113950
* gcc.target/powerpc/pr113950.c: New testcase.
(cherry picked from commit fa0468877869f52b05742de6deef582e4dd296fc)
Diff:
---
gcc/config/rs6000/vsx.md| 4 ++--
gcc/testsuite/gcc.target/powerpc/pr113950.c | 24
2 files changed, 26 insertions(+), 2 deletions(-)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 3506913bd02..f70d69ee4b9 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -4551,8 +4551,8 @@
rtx op1 = operands[1];
if (MEM_P (op1))
operands[1] = rs6000_force_indexed_or_indirect_mem (op1);
- else if (!REG_P (op1))
-op1 = force_reg (mode, op1);
+ else
+operands[1] = force_reg (mode, op1);
})
(define_insn "vsx_splat__reg"
diff --git a/gcc/testsuite/gcc.target/powerpc/pr113950.c
b/gcc/testsuite/gcc.target/powerpc/pr113950.c
new file mode 100644
index 000..359963d1041
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr113950.c
@@ -0,0 +1,24 @@
+/* PR target/113950 */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O2 -mvsx" } */
+
+/* Verify we do not ICE on the following. */
+
+void abort (void);
+
+int main ()
+{
+ int i;
+ vector signed long long vsll_result, vsll_expected_result;
+ signed long long sll_arg1;
+
+ sll_arg1 = 300;
+ vsll_expected_result = (vector signed long long) {300, 300};
+ vsll_result = __builtin_vsx_splat_2di (sll_arg1);
+
+ for (i = 0; i < 2; i++)
+if (vsll_result[i] != vsll_expected_result[i])
+ abort();
+
+ return 0;
+}
[gcc r12-10406] rs6000: Don't ICE when compiling the __builtin_vsx_splat_2di [PR113950]
https://gcc.gnu.org/g:1b91818e47119863f827b19ae4c6c91af3962cd6
commit r12-10406-g1b91818e47119863f827b19ae4c6c91af3962cd6
Author: Jeevitha
Date: Sun Apr 28 23:38:41 2024 -0500
rs6000: Don't ICE when compiling the __builtin_vsx_splat_2di [PR113950]
When we expand the __builtin_vsx_splat_2di built-in, we were allowing
immediate
value for second operand which causes an unrecognizable insn ICE. Even
though
the immediate value was forced into a register, it wasn't correctly assigned
to the second operand. So corrected the assignment of op1 to operands[1].
2024-03-07 Jeevitha Palanisamy
gcc/
PR target/113950
* config/rs6000/vsx.md (vsx_splat_): Correct assignment to
operand1
and simplify else if with else.
gcc/testsuite/
PR target/113950
* gcc.target/powerpc/pr113950.c: New testcase.
(cherry picked from commit fa0468877869f52b05742de6deef582e4dd296fc)
Diff:
---
gcc/config/rs6000/vsx.md| 4 ++--
gcc/testsuite/gcc.target/powerpc/pr113950.c | 24
2 files changed, 26 insertions(+), 2 deletions(-)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index c45794fb9ed..e16f893c073 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -4562,8 +4562,8 @@
rtx op1 = operands[1];
if (MEM_P (op1))
operands[1] = rs6000_force_indexed_or_indirect_mem (op1);
- else if (!REG_P (op1))
-op1 = force_reg (mode, op1);
+ else
+operands[1] = force_reg (mode, op1);
})
(define_insn "vsx_splat__reg"
diff --git a/gcc/testsuite/gcc.target/powerpc/pr113950.c
b/gcc/testsuite/gcc.target/powerpc/pr113950.c
new file mode 100644
index 000..359963d1041
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr113950.c
@@ -0,0 +1,24 @@
+/* PR target/113950 */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O2 -mvsx" } */
+
+/* Verify we do not ICE on the following. */
+
+void abort (void);
+
+int main ()
+{
+ int i;
+ vector signed long long vsll_result, vsll_expected_result;
+ signed long long sll_arg1;
+
+ sll_arg1 = 300;
+ vsll_expected_result = (vector signed long long) {300, 300};
+ vsll_result = __builtin_vsx_splat_2di (sll_arg1);
+
+ for (i = 0; i < 2; i++)
+if (vsll_result[i] != vsll_expected_result[i])
+ abort();
+
+ return 0;
+}
[gcc r15-4514] rs6000: Correct the function code for _AMO_LD_DEC_BOUNDED
https://gcc.gnu.org/g:1a4c5643a5911d130dfab9a064222baeeb7f9be7
commit r15-4514-g1a4c5643a5911d130dfab9a064222baeeb7f9be7
Author: Jeevitha
Date: Thu Oct 10 14:42:45 2024 -0500
rs6000: Correct the function code for _AMO_LD_DEC_BOUNDED
Corrected the function code for the Atomic Memory Operation "Fetch and
Decrement
Bounded", changing it from 0x1A to 0x1C.
2024-10-11 Jeevitha Palanisamy
gcc/
* config/rs6000/amo.h (enum _AMO_LD): Correct the function code for
_AMO_LD_DEC_BOUNDED.
Diff:
---
gcc/config/rs6000/amo.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/config/rs6000/amo.h b/gcc/config/rs6000/amo.h
index 6b9e4e088b97..1303c9d9dab2 100644
--- a/gcc/config/rs6000/amo.h
+++ b/gcc/config/rs6000/amo.h
@@ -46,7 +46,7 @@ enum _AMO_LD {
_AMO_LD_CS_NE= 0x10, /* Compare and Swap Not Equal.
*/
_AMO_LD_INC_BOUNDED = 0x18, /* Fetch and Increment Bounded. */
_AMO_LD_INC_EQUAL= 0x19, /* Fetch and Increment Equal. */
- _AMO_LD_DEC_BOUNDED = 0x1A /* Fetch and Decrement Bounded. */
+ _AMO_LD_DEC_BOUNDED = 0x1C /* Fetch and Decrement Bounded. */
};
/* Implementation of the simple LWAT/LDAT operations that take one register and
[gcc r12-10779] rs6000: Correct the function code for _AMO_LD_DEC_BOUNDED
https://gcc.gnu.org/g:41377d0f4e791bcdd848e11eac172b8e81ecb6ec
commit r12-10779-g41377d0f4e791bcdd848e11eac172b8e81ecb6ec
Author: Jeevitha
Date: Mon Oct 21 04:01:46 2024 -0500
rs6000: Correct the function code for _AMO_LD_DEC_BOUNDED
Corrected the function code for the Atomic Memory Operation "Fetch and
Decrement
Bounded", changing it from 0x1A to 0x1C.
2024-10-11 Jeevitha Palanisamy
gcc/
* config/rs6000/amo.h (enum _AMO_LD): Correct the function code for
_AMO_LD_DEC_BOUNDED.
(cherry picked from commit 1a4c5643a5911d130dfab9a064222baeeb7f9be7)
Diff:
---
gcc/config/rs6000/amo.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/config/rs6000/amo.h b/gcc/config/rs6000/amo.h
index ea4668e0547f..47d19ee181c2 100644
--- a/gcc/config/rs6000/amo.h
+++ b/gcc/config/rs6000/amo.h
@@ -46,7 +46,7 @@ enum _AMO_LD {
_AMO_LD_CS_NE= 0x10, /* Compare and Swap Not Equal.
*/
_AMO_LD_INC_BOUNDED = 0x18, /* Fetch and Increment Bounded. */
_AMO_LD_INC_EQUAL= 0x19, /* Fetch and Increment Equal. */
- _AMO_LD_DEC_BOUNDED = 0x1A /* Fetch and Decrement Bounded. */
+ _AMO_LD_DEC_BOUNDED = 0x1C /* Fetch and Decrement Bounded. */
};
/* Implementation of the simple LWAT/LDAT operations that take one register and
[gcc r13-9140] rs6000: Correct the function code for _AMO_LD_DEC_BOUNDED
https://gcc.gnu.org/g:5be7a44c7a7f86dc2fe82dafcb76603a718dedbc
commit r13-9140-g5be7a44c7a7f86dc2fe82dafcb76603a718dedbc
Author: Jeevitha
Date: Mon Oct 21 03:58:28 2024 -0500
rs6000: Correct the function code for _AMO_LD_DEC_BOUNDED
Corrected the function code for the Atomic Memory Operation "Fetch and
Decrement
Bounded", changing it from 0x1A to 0x1C.
2024-10-11 Jeevitha Palanisamy
gcc/
* config/rs6000/amo.h (enum _AMO_LD): Correct the function code for
_AMO_LD_DEC_BOUNDED.
(cherry picked from commit 1a4c5643a5911d130dfab9a064222baeeb7f9be7)
Diff:
---
gcc/config/rs6000/amo.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/config/rs6000/amo.h b/gcc/config/rs6000/amo.h
index fa31bef9e935..e03fd7c71bb8 100644
--- a/gcc/config/rs6000/amo.h
+++ b/gcc/config/rs6000/amo.h
@@ -46,7 +46,7 @@ enum _AMO_LD {
_AMO_LD_CS_NE= 0x10, /* Compare and Swap Not Equal.
*/
_AMO_LD_INC_BOUNDED = 0x18, /* Fetch and Increment Bounded. */
_AMO_LD_INC_EQUAL= 0x19, /* Fetch and Increment Equal. */
- _AMO_LD_DEC_BOUNDED = 0x1A /* Fetch and Decrement Bounded. */
+ _AMO_LD_DEC_BOUNDED = 0x1C /* Fetch and Decrement Bounded. */
};
/* Implementation of the simple LWAT/LDAT operations that take one register and
[gcc r14-10808] rs6000: Correct the function code for _AMO_LD_DEC_BOUNDED
https://gcc.gnu.org/g:17f1277d78c51d64a222ade218796837f9153f42
commit r14-10808-g17f1277d78c51d64a222ade218796837f9153f42
Author: Jeevitha
Date: Mon Oct 21 03:54:03 2024 -0500
rs6000: Correct the function code for _AMO_LD_DEC_BOUNDED
Corrected the function code for the Atomic Memory Operation "Fetch and
Decrement
Bounded", changing it from 0x1A to 0x1C.
2024-10-11 Jeevitha Palanisamy
gcc/
* config/rs6000/amo.h (enum _AMO_LD): Correct the function code for
_AMO_LD_DEC_BOUNDED.
(cherry picked from commit 1a4c5643a5911d130dfab9a064222baeeb7f9be7)
Diff:
---
gcc/config/rs6000/amo.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/config/rs6000/amo.h b/gcc/config/rs6000/amo.h
index 6b9e4e088b97..1303c9d9dab2 100644
--- a/gcc/config/rs6000/amo.h
+++ b/gcc/config/rs6000/amo.h
@@ -46,7 +46,7 @@ enum _AMO_LD {
_AMO_LD_CS_NE= 0x10, /* Compare and Swap Not Equal.
*/
_AMO_LD_INC_BOUNDED = 0x18, /* Fetch and Increment Bounded. */
_AMO_LD_INC_EQUAL= 0x19, /* Fetch and Increment Equal. */
- _AMO_LD_DEC_BOUNDED = 0x1A /* Fetch and Decrement Bounded. */
+ _AMO_LD_DEC_BOUNDED = 0x1C /* Fetch and Decrement Bounded. */
};
/* Implementation of the simple LWAT/LDAT operations that take one register and
[gcc r15-6681] testsuite: Simplify target test and dg-options for AMO tests
https://gcc.gnu.org/g:51708cbd751e3af0d147ceae4da5c74dae1519ce
commit r15-6681-g51708cbd751e3af0d147ceae4da5c74dae1519ce
Author: Jeevitha
Date: Wed Jan 8 01:03:12 2025 -0600
testsuite: Simplify target test and dg-options for AMO tests
Removed powerpc*-*-* from the target test as it is always true. Simplified
options by removing -mpower9-misc and -mvsx, which are enabled by default
with
-mdejagnu-cpu=power9. The has_arch_pwr9 check is also true with
-mdejagnu-cpu=power9, so it has been removed.
2025-01-08 Jeevitha Palanisamy
gcc/testsuite/
* gcc.target/powerpc/amo1.c: Removed powerpc*-*-* from the target
and
simplified dg-options.
* gcc.target/powerpc/amo2.c: Simplified dg-options and added
powerpc_vsx
target check.
Diff:
---
gcc/testsuite/gcc.target/powerpc/amo1.c | 5 ++---
gcc/testsuite/gcc.target/powerpc/amo2.c | 4 ++--
2 files changed, 4 insertions(+), 5 deletions(-)
diff --git a/gcc/testsuite/gcc.target/powerpc/amo1.c
b/gcc/testsuite/gcc.target/powerpc/amo1.c
index c5af373b4e99..9a981cd4219f 100644
--- a/gcc/testsuite/gcc.target/powerpc/amo1.c
+++ b/gcc/testsuite/gcc.target/powerpc/amo1.c
@@ -1,6 +1,5 @@
-/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
-/* { dg-options "-mvsx -mpower9-misc -O2" } */
-/* { dg-additional-options "-mdejagnu-cpu=power9" { target { ! has_arch_pwr9 }
} } */
+/* { dg-do compile { target { lp64 } } } */
+/* { dg-options "-mdejagnu-cpu=power9 -O2" } */
/* { dg-require-effective-target powerpc_vsx } */
/* Verify P9 atomic memory operations. */
diff --git a/gcc/testsuite/gcc.target/powerpc/amo2.c
b/gcc/testsuite/gcc.target/powerpc/amo2.c
index 592f0fb3f92d..9e4ff0ce0645 100644
--- a/gcc/testsuite/gcc.target/powerpc/amo2.c
+++ b/gcc/testsuite/gcc.target/powerpc/amo2.c
@@ -1,6 +1,6 @@
/* { dg-do run { target { powerpc*-*-linux* && { lp64 && p9vector_hw } } } } */
-/* { dg-options "-O2 -mvsx -mpower9-misc" } */
-/* { dg-additional-options "-mdejagnu-cpu=power9" { target { ! has_arch_pwr9 }
} } */
+/* { dg-options "-mdejagnu-cpu=power9 -O2" } */
+/* { dg-require-effective-target powerpc_vsx } */
#include
#include
[gcc/ibm/heads/gcc-13-branch] (754 commits) ibm: Merge up to top of releases/gcc-13
The branch 'ibm/heads/gcc-13-branch' was updated to point to:
25cecef4a385... ibm: Merge up to top of releases/gcc-13
It previously pointed to:
b7341a9059d7... ibm: Merge up to top of releases/gcc-13
Diff:
Summary of changes (added commits):
---
25cecef... ibm: Merge up to top of releases/gcc-13
999a602... Daily bump. (*)
e665276... debug/101533 - ICE with variant typedef DIE generation (*)
068aa9a... middle-end/101478 - ICE with degenerate address during gimp (*)
da579a8... lto/91299 - weak definition inlined with LTO (*)
f2d0fb2... tree-optimization/87984 - hard register assignments not pre (*)
c0e3078... c++/79786 - bougs invocation of DATA_ABI_ALIGNMENT macro (*)
a145eaf... middle-end/66279 - gimplification clobbers shared asm const (*)
337d3cd... tree-optimization/25 - avoid BB vectorization in novect (*)
209fbbc... Daily bump. (*)
e0e85b6... Daily bump. (*)
10b8d94... Enable generation of GNU stack notes on Linux (*)
7e644ae... Daily bump. (*)
3817827... Daily bump. (*)
857f2c2... Daily bump. (*)
61367fc... Daily bump. (*)
5227f98... Daily bump. (*)
2317297... Fix GNAT build failure for x86/FreeBSD (*)
67d13d1... AVR: target/119989 - Add missing clobbers to xload__l (*)
b1163a2... Daily bump. (*)
85792c6... sra: Clear grp_same_access_path of acesses created by total (*)
087d91f... sra: Avoid creating TBAA hazards (PR118924) (*)
96040fd... Remove other processors from X86_TUNE_DEST_FALSE_DEP_FOR_GL (*)
29608b0... Daily bump. (*)
3aec5f3... Daily bump. (*)
0880731... Daily bump. (*)
0ec3743... Daily bump. (*)
12ceee1... Daily bump. (*)
261bcbf... Avoid using POINTER_DIFF_EXPR for overlap checks [PR119399] (*)
cf40537... vect: Enforce dr_with_seg_len::align precondition [PR116125 (*)
a6a66ec... s390: Accept only Pmode for registers AP/FP/RA [PR119235] (*)
7495787... Fix a pasto in ao_compare::compare_ao_refs (*)
a32919a... c++: templates, attributes, #pragma target [PR114772] (*)
b14ae44... c++: constexpr, trivial, and non-alias target [PR111075] (*)
7ac1a99... libatomic: Fix up libat_{,un}lock_n for mingw [PR119796] (*)
1982540... libatomic: Fix up libat_{,un}lock_n [PR119796] (*)
3abc678... expmed: Always use QImode for init_expmed set_zero_cost [PR (*)
b00d87f... driver: On linux hosts disable ASLR during -freport-bug [PR (*)
c3c451b... driver: Fix up -freport-bug for ASLR [PR119727] (*)
b498814... libquadmath: Fix up THREEp96 constant in expq (*)
622d171... lto: lto-opts fixes [PR119625] (*)
d6988fa... c: Fix ICEs with -fsanitize=pointer-{subtract,compare} [PR1 (*)
7c4b802... combine: Use reg_used_between_p rather than modified_betwee (*)
6eb9f80... Fix up some further cases of missing or extraneous spaces i (*)
997b3e9... builtins: Fix up strspn/strcspn folding [PR119219] (*)
f82a279... middle-end/119204 - ICE with strcspn folding (*)
34c76e5... tree: Improve skip_simple_arithmetic [PR119183] (*)
bfdd0e6... libgcc: Fix up unwind-dw2-btree.h [PR119151] (*)
1b6045c... c++: Update TYPE_FIELDS of variant types if cp_parser_late_ (*)
3424985... c++: Fix cxx_eval_store_expression {REAL,IMAG}PART_EXPR han (*)
7980ce5... c: stddef.h C23 fixes [PR114870] (*)
048a90f... openmp: Mark OpenMP atomic write expression as read [PR1190 (*)
9005efe... reassoc: Fix up optimize_range_tests_to_bit_test [PR118915] (*)
301d5e2... i386: Fix ICE with conditional QI/HI vector maxmin [PR11877 (*)
7cb4653... c++: Don't use CLEANUP_EH_ONLY for new expression cleanup [ (*)
eb3e7de... c++: Allow constexpr reads from volatile std::nullptr_t obj (*)
b4b559a... icf: Compare call argument types in certain cases and asm o (*)
0691f75... niter: Make build_cltz_expr more robust [PR118689] (*)
9e27bc5... d: give dependency files better filenames [PR118477] (*)
c7f51dc... c++: Only destruct elts of array for new expression if exce (*)
38f4559... builtins: Store unspecified value to *exp for inf/nan [PR11 (*)
3d70d8b... c++: Wrap force_target_expr in get_member_function_from_ptr (*)
e49c0a1... c++: Honor complain in cp_build_function_call_vec for check (*)
28646ac... c++: Diagnose earlier non-static data members with cv conta (*)
4bbd1ab... warn-access: Fix up matching_alloc_calls_p [PR118024] (*)
e244beb... cse: Fix up record_jump_equiv checks [PR117095] (*)
c71616c... docs: Clarify -fsanitize=hwaddress target support [PR117960 (*)
4dc7a5e... docs: Fix up __sync_* documentation [PR117642] (*)
ec1614b... c: Fix sizeof error recovery [PR117745] (*)
1ec99f6... builtins: Fix up DFP ICEs on __builtin_fpclassify [PR102674 (*)
c6a3fd5... builtins: Fix up DFP ICEs on __builtin_is{inf,finite,normal (*)
5b82543... phiopt: Fix a pasto in spaceship_replacement [PR117612] (*)
2911337... m2: Fix up dependencies some more (*)
1784de4... c++: Fix ICE on constexpr virtual function [PR117317] (*)
bf85c4d... store-merging: Don't use sub_byte_op_p mode for empty_ctor
[gcc(refs/vendors/ibm/heads/gcc-13-branch)] ibm: Merge up to top of releases/gcc-13
https://gcc.gnu.org/g:25cecef4a385faf4d2e343498059b51bab266ba6 commit 25cecef4a385faf4d2e343498059b51bab266ba6 Merge: b7341a9059d7 999a60264a5c Author: Jeevitha Palanisamy Date: Thu May 8 02:31:19 2025 -0500 ibm: Merge up to top of releases/gcc-13 2025-05-08 Jeevitha Palanisamy Merge up to releases/gcc-13 999a60264a5c11f23771581aea783ca40d9c0c62 Diff: gcc/ChangeLog | 2134 gcc/ChangeLog.ibm |4 + gcc/DATESTAMP |2 +- gcc/ada/ChangeLog | 144 ++ gcc/ada/Makefile.rtl |1 + gcc/ada/checks.adb | 10 +- gcc/ada/exp_aggr.adb | 54 +- gcc/ada/exp_aggr.ads |4 + gcc/ada/exp_ch3.adb| 15 +- gcc/ada/exp_put_image.adb |4 +- gcc/ada/exp_util.adb |1 + gcc/ada/gcc-interface/decl.cc |8 + gcc/ada/gcc-interface/trans.cc | 16 +- gcc/ada/gen_il-gen-gen_nodes.adb |2 +- gcc/ada/gnatvsn.ads|3 +- gcc/ada/libgnarl/s-taprop__dummy.adb | 11 +- gcc/ada/libgnat/a-ngcoar.adb | 42 +- gcc/ada/libgnat/a-ngrear.adb | 109 +- gcc/ada/libgnat/s-dorepr__freebsd.adb | 172 ++ gcc/ada/par-ch6.adb|1 + gcc/ada/sem_ch12.adb | 37 +- gcc/ada/sem_res.adb|2 +- gcc/ada/sem_warn.adb |4 + gcc/ada/version.c |5 +- gcc/asan.cc| 51 +- gcc/auto-profile.cc|4 +- gcc/builtins.cc| 67 +- gcc/c-family/ChangeLog | 30 + gcc/c-family/c-ada-spec.cc |4 +- gcc/c-family/c-cppbuiltin.cc | 19 +- gcc/c-family/c-warn.cc | 20 +- gcc/c/ChangeLog| 29 + gcc/c/c-parser.cc | 34 +- gcc/c/c-typeck.cc |8 +- gcc/cgraph.cc |7 +- gcc/combine.cc | 31 +- gcc/common/config/i386/cpuinfo.h | 16 + gcc/common/config/i386/i386-common.cc |6 +- gcc/common/config/i386/i386-cpuinfo.h |2 + gcc/config.gcc | 14 +- gcc/config.in |7 + gcc/config/aarch64/aarch64-c.cc|5 + gcc/config/aarch64/aarch64-freebsd.h |1 + gcc/config/aarch64/aarch64-sve-builtins-base.cc| 36 +- gcc/config/aarch64/aarch64-sve.md | 20 +- gcc/config/aarch64/aarch64.cc | 24 +- gcc/config/aarch64/aarch64.h |2 +- gcc/config/aarch64/aarch64.md |8 +- gcc/config/aarch64/driver-aarch64.cc | 53 +- gcc/config/alpha/alpha.md | 10 +- gcc/config/arm/arm.cc | 16 +- gcc/config/arm/arm_mve.h |4 + gcc/config/arm/arm_mve_types.h |4 + gcc/config/arm/freebsd.h |1 + gcc/config/arm/mve.md |2 +- gcc/config/arm/t-rtems |5 +- gcc/config/avr/avr-dimode.md | 26 +- gcc/config/avr/avr-mcus.def|6 + gcc/config/avr/avr-protos.h|2 +- gcc/config/avr/avr.cc | 191 +- gcc/config/avr/avr.md | 35 +- gcc/config/freebsd-spec.h | 18 +- gcc/config/i386/avx512dqintrin.h | 16 +- gcc/config/i386/avx512fp16intrin.h |4 +- gcc/config/i386/avx512vlbwintrin.h |4 +- gcc/config/i386/avx512vlintrin.h |2 +- gcc/config/i386/cmpccxaddintrin.h |6 +- gcc/config/i386/constraints.md |2 +- gcc/config/i386/driver-i386.cc |5 + gcc/config/i386/freebsd.h |1 + gcc/config/i386/freebsd64.h|1 + gcc/config/i386/i386-builtin.def | 16 +- gcc/config/i386/i386-c.cc |7 + gcc/config/i386/i386-expand.cc | 38 +- gcc/config/i386/i386-options
