[gcc r14-9352] LoongArch: testsuite:Fix problems with incorrect results in vector test cases.

[LuluCheng via Gcc-cvs]

https://gcc.gnu.org/g:ae1b05641ccf1cd4739b0998ce61cda6e5b772dd

commit r14-9352-gae1b05641ccf1cd4739b0998ce61cda6e5b772dd
Author: chenxiaolong 
Date:   Wed Mar 6 16:54:06 2024 +0800

LoongArch: testsuite:Fix problems with incorrect results in vector test 
cases.

In simd_correctness_check.h, the role of the macro ASSERTEQ_64 is to check 
the
result of the passed vector values for the 64-bit data of each array 
element.
It turns out that it uses the abs() function to check only the lower 32 bits
of the data at a time, so it replaces abs() with the llabs() function.

However, the following two problems may occur after modification:

1.FAIL in lasx-xvfrint_s.c and lsx-vfrint_s.c
The reason for the error is because vector test cases that use __m{128,256} 
to
define vector types are composed of 32-bit primitive types, they should use
ASSERTEQ_32 instead of ASSERTEQ_64 to check for correctness.

2.FAIL in lasx-xvshuf_b.c and lsx-vshuf.c
The cause of the error is that the expected result of the function setting 
in
the test case is incorrect.

gcc/testsuite/ChangeLog:

* gcc.target/loongarch/vector/lasx/lasx-xvfrint_s.c: Replace
ASSERTEQ_64 with the macro ASSERTEQ_32.
* gcc.target/loongarch/vector/lasx/lasx-xvshuf_b.c: Modify the 
expected
test results of some functions according to the function of the 
vector
instruction.
* gcc.target/loongarch/vector/lsx/lsx-vfrint_s.c: Same
modification as lasx-xvfrint_s.c.
* gcc.target/loongarch/vector/lsx/lsx-vshuf.c: Same
modification as lasx-xvshuf_b.c.
* gcc.target/loongarch/vector/simd_correctness_check.h: Use the 
llabs()
function instead of abs() to check the correctness of the results.

Diff:
---
 .../loongarch/vector/lasx/lasx-xvfrint_s.c | 58 +++---
 .../loongarch/vector/lasx/lasx-xvshuf_b.c  | 14 +++---
 .../gcc.target/loongarch/vector/lsx/lsx-vfrint_s.c | 50 +--
 .../gcc.target/loongarch/vector/lsx/lsx-vshuf.c| 12 ++---
 .../loongarch/vector/simd_correctness_check.h  |  2 +-
 5 files changed, 68 insertions(+), 68 deletions(-)

diff --git a/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvfrint_s.c 
b/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvfrint_s.c
index fbfe300eac4..4538528a67f 100644
--- a/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvfrint_s.c
+++ b/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvfrint_s.c
@@ -184,7 +184,7 @@ main ()
   *((int *)&__m256_result[1]) = 0x;
   *((int *)&__m256_result[0]) = 0x;
   __m256_out = __lasx_xvfrintrne_s (__m256_op0);
-  ASSERTEQ_64 (__LINE__, __m256_result, __m256_out);
+  ASSERTEQ_32 (__LINE__, __m256_result, __m256_out);
 
   *((int *)&__m256_op0[7]) = 0x;
   *((int *)&__m256_op0[6]) = 0x;
@@ -203,7 +203,7 @@ main ()
   *((int *)&__m256_result[1]) = 0x;
   *((int *)&__m256_result[0]) = 0x;
   __m256_out = __lasx_xvfrintrne_s (__m256_op0);
-  ASSERTEQ_64 (__LINE__, __m256_result, __m256_out);
+  ASSERTEQ_32 (__LINE__, __m256_result, __m256_out);
 
   *((int *)&__m256_op0[7]) = 0x;
   *((int *)&__m256_op0[6]) = 0x;
@@ -222,7 +222,7 @@ main ()
   *((int *)&__m256_result[1]) = 0x;
   *((int *)&__m256_result[0]) = 0x;
   __m256_out = __lasx_xvfrintrne_s (__m256_op0);
-  ASSERTEQ_64 (__LINE__, __m256_result, __m256_out);
+  ASSERTEQ_32 (__LINE__, __m256_result, __m256_out);
 
   *((int *)&__m256_op0[7]) = 0x01010101;
   *((int *)&__m256_op0[6]) = 0x01010101;
@@ -241,7 +241,7 @@ main ()
   *((int *)&__m256_result[1]) = 0x;
   *((int *)&__m256_result[0]) = 0x;
   __m256_out = __lasx_xvfrintrne_s (__m256_op0);
-  ASSERTEQ_64 (__LINE__, __m256_result, __m256_out);
+  ASSERTEQ_32 (__LINE__, __m256_result, __m256_out);
 
   *((int *)&__m256_op0[7]) = 0x;
   *((int *)&__m256_op0[6]) = 0x;
@@ -260,7 +260,7 @@ main ()
   *((int *)&__m256_result[1]) = 0x;
   *((int *)&__m256_result[0]) = 0x;
   __m256_out = __lasx_xvfrintrne_s (__m256_op0);
-  ASSERTEQ_64 (__LINE__, __m256_result, __m256_out);
+  ASSERTEQ_32 (__LINE__, __m256_result, __m256_out);
 
   *((int *)&__m256_op0[7]) = 0x;
   *((int *)&__m256_op0[6]) = 0x;
@@ -279,7 +279,7 @@ main ()
   *((int *)&__m256_result[1]) = 0x;
   *((int *)&__m256_result[0]) = 0x;
   __m256_out = __lasx_xvfrintrne_s (__m256_op0);
-  ASSERTEQ_64 (__LINE__, __m256_result, __m256_out);
+  ASSERTEQ_32 (__LINE__, __m256_result, __m256_out);
 
   *((int *)&__m256_op0[7]) = 0x;
   *((int *)&__m256_op0[6]) = 0x;
@@ -298,7 +298,7 @@ main ()
   *((int *)&__m256_result[1]) = 0x;
   *((int *)&__m256_result[0]) = 0x;
   __m256_out = __lasx_xvfrintrne_s (__m256_op0);
-  ASSERTEQ_64 (__LINE__, __m256_result, __m256_out);
+  ASSERTEQ

[gcc r14-9351] LoongArch: Use /lib instead of /lib64 as the library search path for MUSL.

[LuluCheng via Gcc-cvs]

https://gcc.gnu.org/g:2f7d4728dbfd976788f77b8f43d4dc3c718b71b7

commit r14-9351-g2f7d4728dbfd976788f77b8f43d4dc3c718b71b7
Author: Yang Yujie 
Date:   Wed Mar 6 09:19:59 2024 +0800

LoongArch: Use /lib instead of /lib64 as the library search path for MUSL.

gcc/ChangeLog:

* config.gcc: Add a case for loongarch*-*-linux-musl*.
* config/loongarch/linux.h: Disable the multilib-compatible
treatment for *musl* targets.
* config/loongarch/musl.h: New file.

Diff:
---
 gcc/config.gcc   |  3 +++
 gcc/config/loongarch/linux.h |  4 +++-
 gcc/config/loongarch/musl.h  | 23 +++
 3 files changed, 29 insertions(+), 1 deletion(-)

diff --git a/gcc/config.gcc b/gcc/config.gcc
index a1480b72c46..624e0dae191 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -2538,6 +2538,9 @@ riscv*-*-freebsd*)
 
 loongarch*-*-linux*)
tm_file="elfos.h gnu-user.h linux.h linux-android.h glibc-stdint.h 
${tm_file}"
+   case ${target} in
+ *-linux-musl*) tm_file="${tm_file} loongarch/musl.h"
+   esac
tm_file="${tm_file} loongarch/gnu-user.h loongarch/linux.h 
loongarch/loongarch-driver.h"
extra_options="${extra_options} linux-android.opt"
tmake_file="${tmake_file} loongarch/t-multilib loongarch/t-linux"
diff --git a/gcc/config/loongarch/linux.h b/gcc/config/loongarch/linux.h
index 17d9f87537b..40d9ba6d405 100644
--- a/gcc/config/loongarch/linux.h
+++ b/gcc/config/loongarch/linux.h
@@ -21,7 +21,9 @@ along with GCC; see the file COPYING3.  If not see
  * This ensures that a compiler configured with --disable-multilib
  * can work in a multilib environment.  */
 
-#if defined(LA_DISABLE_MULTILIB) && defined(LA_DISABLE_MULTIARCH)
+#if !defined(LA_DEFAULT_TARGET_MUSL) \
+  && defined(LA_DISABLE_MULTILIB) \
+  && defined(LA_DISABLE_MULTIARCH)
 
   #if DEFAULT_ABI_BASE == ABI_BASE_LP64D
 #define ABI_LIBDIR "lib64"
diff --git a/gcc/config/loongarch/musl.h b/gcc/config/loongarch/musl.h
new file mode 100644
index 000..fa43bc86606
--- /dev/null
+++ b/gcc/config/loongarch/musl.h
@@ -0,0 +1,23 @@
+/* Definitions for MUSL C library support.
+   Copyright (C) 2024 Free Software Foundation, Inc.
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 3, or (at your option)
+any later version.
+
+GCC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GCC; see the file COPYING3.  If not see
+.  */
+
+
+#ifndef LA_DEFAULT_TARGET_MUSL
+#define LA_DEFAULT_TARGET_MUSL
+#endif

[gcc r15-1764] LoongArch: Fix explicit-relocs-{extreme-, }tls-desc.c tests.

[LuluCheng via Gcc-cvs]

https://gcc.gnu.org/g:20909c97211f25fb29edcd12cb148309c919bf81

commit r15-1764-g20909c97211f25fb29edcd12cb148309c919bf81
Author: Lulu Cheng 
Date:   Fri Jun 28 15:04:26 2024 +0800

LoongArch: Fix explicit-relocs-{extreme-,}tls-desc.c tests.

After r15-1579, ADD and LD/ST pairs will be merged into LDX/STX.
Cause these two tests to fail. To guarantee that these two tests pass,
add the compilation option '-fno-late-combine-instructions'.

gcc/testsuite/ChangeLog:

* gcc.target/loongarch/explicit-relocs-extreme-tls-desc.c:
Add compilation options '-fno-late-combine-instructions'.
* gcc.target/loongarch/explicit-relocs-tls-desc.c: Likewise.

Diff:
---
 gcc/testsuite/gcc.target/loongarch/explicit-relocs-extreme-tls-desc.c | 2 +-
 gcc/testsuite/gcc.target/loongarch/explicit-relocs-tls-desc.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git 
a/gcc/testsuite/gcc.target/loongarch/explicit-relocs-extreme-tls-desc.c 
b/gcc/testsuite/gcc.target/loongarch/explicit-relocs-extreme-tls-desc.c
index 3797556e1e6..e9eb0d6f703 100644
--- a/gcc/testsuite/gcc.target/loongarch/explicit-relocs-extreme-tls-desc.c
+++ b/gcc/testsuite/gcc.target/loongarch/explicit-relocs-extreme-tls-desc.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O2 -fPIC -mexplicit-relocs -mtls-dialect=desc 
-mcmodel=extreme" } */
+/* { dg-options "-O2 -fPIC -mexplicit-relocs -mtls-dialect=desc 
-mcmodel=extreme -fno-late-combine-instructions" } */
 
 __thread int a __attribute__((visibility("hidden")));
 extern __thread int b __attribute__((visibility("default")));
diff --git a/gcc/testsuite/gcc.target/loongarch/explicit-relocs-tls-desc.c 
b/gcc/testsuite/gcc.target/loongarch/explicit-relocs-tls-desc.c
index f6690309156..fed478458a3 100644
--- a/gcc/testsuite/gcc.target/loongarch/explicit-relocs-tls-desc.c
+++ b/gcc/testsuite/gcc.target/loongarch/explicit-relocs-tls-desc.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O2 -fPIC -mexplicit-relocs -mtls-dialect=desc" } */
+/* { dg-options "-O2 -fPIC -mexplicit-relocs -mtls-dialect=desc 
-fno-late-combine-instructions" } */
 
 __thread int a __attribute__((visibility("hidden")));
 extern __thread int b __attribute__((visibility("default")));

[gcc r15-1765] LoongArch: Define loongarch_insn_cost and set the cost of movcf2gr and movgr2cf.

[LuluCheng via Gcc-cvs]

https://gcc.gnu.org/g:90c8782615e5fadb566ed4fbe4e08af9ea3d2d2d

commit r15-1765-g90c8782615e5fadb566ed4fbe4e08af9ea3d2d2d
Author: Lulu Cheng 
Date:   Fri Jun 28 15:09:48 2024 +0800

LoongArch: Define loongarch_insn_cost and set the cost of movcf2gr and 
movgr2cf.

The following two FAIL items have been fixed:

FAIL: gcc.target/loongarch/movcf2gr-via-fr.c scan-assembler 
movcf2fr\\t\$f[0-9]+,\$fcc
FAIL: gcc.target/loongarch/movcf2gr-via-fr.c scan-assembler 
movfr2gr.s\\t\$r4

gcc/ChangeLog:

* config/loongarch/loongarch.cc (loongarch_insn_cost):
New function.
(TARGET_INSN_COST): New macro.

Diff:
---
 gcc/config/loongarch/loongarch.cc | 29 +
 1 file changed, 29 insertions(+)

diff --git a/gcc/config/loongarch/loongarch.cc 
b/gcc/config/loongarch/loongarch.cc
index 0fb547e00f4..27f3dbdfb1a 100644
--- a/gcc/config/loongarch/loongarch.cc
+++ b/gcc/config/loongarch/loongarch.cc
@@ -4372,6 +4372,33 @@ loongarch_address_cost (rtx addr, machine_mode mode,
   return loongarch_address_insns (addr, mode, false);
 }
 
+/* Implement TARGET_INSN_COST.  */
+
+static int
+loongarch_insn_cost (rtx_insn *insn, bool speed)
+{
+  rtx x = PATTERN (insn);
+  int cost = pattern_cost (x, speed);
+
+  /* On LA464, prevent movcf2fr and movfr2gr from merging into movcf2gr.  */
+  if (GET_CODE (x) == SET
+  && GET_MODE (XEXP (x, 0)) == FCCmode)
+{
+  rtx dest, src;
+  dest = XEXP (x, 0);
+  src = XEXP (x, 1);
+
+  if (REG_P (dest) && REG_P (src))
+   {
+ if (GP_REG_P (REGNO (dest)) && FCC_REG_P (REGNO (src)))
+   cost = loongarch_cost->movcf2gr;
+ else if (FCC_REG_P (REGNO (dest)) && GP_REG_P (REGNO (src)))
+   cost = loongarch_cost->movgr2cf;
+   }
+}
+  return cost;
+}
+
 /* Return one word of double-word value OP, taking into account the fixed
endianness of certain registers.  HIGH_P is true to select the high part,
false to select the low part.  */
@@ -11105,6 +11132,8 @@ loongarch_asm_code_end (void)
 #define TARGET_RTX_COSTS loongarch_rtx_costs
 #undef TARGET_ADDRESS_COST
 #define TARGET_ADDRESS_COST loongarch_address_cost
+#undef TARGET_INSN_COST
+#define TARGET_INSN_COST loongarch_insn_cost
 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
   loongarch_builtin_vectorization_cost

[gcc r15-1986] LoongArch: TFmode is not allowed to be stored in the float register.

[LuluCheng via Gcc-cvs]

https://gcc.gnu.org/g:abeb6c8a62758faa0719e818e6e8a7db15a6793b

commit r15-1986-gabeb6c8a62758faa0719e818e6e8a7db15a6793b
Author: Lulu Cheng 
Date:   Thu Jul 4 10:37:26 2024 +0800

LoongArch: TFmode is not allowed to be stored in the float register.

PR target/115752

gcc/ChangeLog:

* config/loongarch/loongarch.cc
(loongarch_hard_regno_mode_ok_uncached): Replace
UNITS_PER_FPVALUE with UNITS_PER_HWFPVALUE.
* config/loongarch/loongarch.h (UNITS_PER_FPVALUE): Delete.

gcc/testsuite/ChangeLog:

* gcc.target/loongarch/pr115752.c: New test.

Diff:
---
 gcc/config/loongarch/loongarch.cc | 2 +-
 gcc/config/loongarch/loongarch.h  | 7 ---
 gcc/testsuite/gcc.target/loongarch/pr115752.c | 8 
 3 files changed, 9 insertions(+), 8 deletions(-)

diff --git a/gcc/config/loongarch/loongarch.cc 
b/gcc/config/loongarch/loongarch.cc
index 27f3dbdfb1a0..5d894a36b4d4 100644
--- a/gcc/config/loongarch/loongarch.cc
+++ b/gcc/config/loongarch/loongarch.cc
@@ -6763,7 +6763,7 @@ loongarch_hard_regno_mode_ok_uncached (unsigned int 
regno, machine_mode mode)
   if (mclass == MODE_FLOAT
  || mclass == MODE_COMPLEX_FLOAT
  || mclass == MODE_VECTOR_FLOAT)
-   return size <= UNITS_PER_FPVALUE;
+   return size <= UNITS_PER_HWFPVALUE;
 
   /* Allow integer modes that fit into a single register.  We need
 to put integers into FPRs when using instructions like CVT
diff --git a/gcc/config/loongarch/loongarch.h b/gcc/config/loongarch/loongarch.h
index b9323aba3948..5efeae53be6b 100644
--- a/gcc/config/loongarch/loongarch.h
+++ b/gcc/config/loongarch/loongarch.h
@@ -146,13 +146,6 @@ along with GCC; see the file COPYING3.  If not see
 #define UNITS_PER_HWFPVALUE \
   (TARGET_SOFT_FLOAT ? 0 : UNITS_PER_FP_REG)
 
-/* The largest size of value that can be held in floating-point
-   registers.  */
-#define UNITS_PER_FPVALUE \
-  (TARGET_SOFT_FLOAT ? 0 \
-   : TARGET_SINGLE_FLOAT ? UNITS_PER_FP_REG \
-: LA_LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT)
-
 /* The number of bytes in a double.  */
 #define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT)
 
diff --git a/gcc/testsuite/gcc.target/loongarch/pr115752.c 
b/gcc/testsuite/gcc.target/loongarch/pr115752.c
new file mode 100644
index ..df4bae524f75
--- /dev/null
+++ b/gcc/testsuite/gcc.target/loongarch/pr115752.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+
+long double
+test (long double xx)
+{
+   __asm ("" :: "f"(xx)); /* { dg-error "inconsistent operand constraints in 
an 'asm'" } */
+   return xx + 1;
+}

[gcc r15-1987] LoongArch: Remove unreachable codes.

[LuluCheng via Gcc-cvs]

https://gcc.gnu.org/g:3bc1a86d534db98d2e7647b734a198098f51267f

commit r15-1987-g3bc1a86d534db98d2e7647b734a198098f51267f
Author: Lulu Cheng 
Date:   Thu Jul 4 15:00:40 2024 +0800

LoongArch: Remove unreachable codes.

gcc/ChangeLog:

* config/loongarch/loongarch.cc
(loongarch_split_move): Delete.
(loongarch_hard_regno_mode_ok_uncached): Likewise.
* config/loongarch/loongarch.md
(move_doubleword_fpr): Likewise.
(load_low): Likewise.
(load_high): Likewise.
(store_word): Likewise.
(movgr2frh): Likewise.
(movfrh2gr): Likewise.

Diff:
---
 gcc/config/loongarch/loongarch.cc |  47 +++-
 gcc/config/loongarch/loongarch.md | 109 --
 2 files changed, 8 insertions(+), 148 deletions(-)

diff --git a/gcc/config/loongarch/loongarch.cc 
b/gcc/config/loongarch/loongarch.cc
index 5d894a36b4d4..8eb47ff95c36 100644
--- a/gcc/config/loongarch/loongarch.cc
+++ b/gcc/config/loongarch/loongarch.cc
@@ -4462,42 +4462,13 @@ loongarch_split_move_p (rtx dest, rtx src)
 void
 loongarch_split_move (rtx dest, rtx src)
 {
-  rtx low_dest;
-
   gcc_checking_assert (loongarch_split_move_p (dest, src));
   if (LSX_SUPPORTED_MODE_P (GET_MODE (dest)))
 loongarch_split_128bit_move (dest, src);
   else if (LASX_SUPPORTED_MODE_P (GET_MODE (dest)))
 loongarch_split_256bit_move (dest, src);
-  else if (FP_REG_RTX_P (dest) || FP_REG_RTX_P (src))
-{
-  if (!TARGET_64BIT && GET_MODE (dest) == DImode)
-   emit_insn (gen_move_doubleword_fprdi (dest, src));
-  else if (!TARGET_64BIT && GET_MODE (dest) == DFmode)
-   emit_insn (gen_move_doubleword_fprdf (dest, src));
-  else if (TARGET_64BIT && GET_MODE (dest) == TFmode)
-   emit_insn (gen_move_doubleword_fprtf (dest, src));
-  else
-   gcc_unreachable ();
-}
   else
-{
-  /* The operation can be split into two normal moves.  Decide in
-which order to do them.  */
-  low_dest = loongarch_subword (dest, false);
-  if (REG_P (low_dest) && reg_overlap_mentioned_p (low_dest, src))
-   {
- loongarch_emit_move (loongarch_subword (dest, true),
-  loongarch_subword (src, true));
- loongarch_emit_move (low_dest, loongarch_subword (src, false));
-   }
-  else
-   {
- loongarch_emit_move (low_dest, loongarch_subword (src, false));
- loongarch_emit_move (loongarch_subword (dest, true),
-  loongarch_subword (src, true));
-   }
-}
+gcc_unreachable ();
 }
 
 /* Check if adding an integer constant value for a specific mode can be
@@ -6746,20 +6717,18 @@ loongarch_hard_regno_mode_ok_uncached (unsigned int 
regno, machine_mode mode)
   size = GET_MODE_SIZE (mode);
   mclass = GET_MODE_CLASS (mode);
 
-  if (GP_REG_P (regno) && !LSX_SUPPORTED_MODE_P (mode)
+  if (GP_REG_P (regno)
+  && !LSX_SUPPORTED_MODE_P (mode)
   && !LASX_SUPPORTED_MODE_P (mode))
 return ((regno - GP_REG_FIRST) & 1) == 0 || size <= UNITS_PER_WORD;
 
-  /* For LSX, allow TImode and 128-bit vector modes in all FPR.  */
-  if (FP_REG_P (regno) && LSX_SUPPORTED_MODE_P (mode))
-return true;
-
-  /* FIXED ME: For LASX, allow TImode and 256-bit vector modes in all FPR.  */
-  if (FP_REG_P (regno) && LASX_SUPPORTED_MODE_P (mode))
-return true;
-
   if (FP_REG_P (regno))
 {
+  /* Allow 128-bit or 256-bit vector modes in all FPR.  */
+  if (LSX_SUPPORTED_MODE_P (mode)
+ || LASX_SUPPORTED_MODE_P (mode))
+   return true;
+
   if (mclass == MODE_FLOAT
  || mclass == MODE_COMPLEX_FLOAT
  || mclass == MODE_VECTOR_FLOAT)
diff --git a/gcc/config/loongarch/loongarch.md 
b/gcc/config/loongarch/loongarch.md
index 25c1d323ba0f..21890a2d94ba 100644
--- a/gcc/config/loongarch/loongarch.md
+++ b/gcc/config/loongarch/loongarch.md
@@ -400,9 +400,6 @@
 ;; 64-bit modes for which we provide move patterns.
 (define_mode_iterator MOVE64 [DI DF])
 
-;; 128-bit modes for which we provide move patterns on 64-bit targets.
-(define_mode_iterator MOVE128 [TI TF])
-
 ;; Iterator for sub-32-bit integer modes.
 (define_mode_iterator SHORT [QI HI])
 
@@ -421,12 +418,6 @@
 (define_mode_iterator ANYFI [(SI "TARGET_HARD_FLOAT")
 (DI "TARGET_DOUBLE_FLOAT")])
 
-;; A mode for which moves involving FPRs may need to be split.
-(define_mode_iterator SPLITF
-  [(DF "!TARGET_64BIT && TARGET_DOUBLE_FLOAT")
-   (DI "!TARGET_64BIT && TARGET_DOUBLE_FLOAT")
-   (TF "TARGET_64BIT && TARGET_DOUBLE_FLOAT")])
-
 ;; A mode for anything with 32 bits or more, and able to be loaded with
 ;; the same addressing mode as ld.w.
 (define_mode_iterator LD_AT_LEAST_32_BIT [GPR ANYF])
@@ -2421,41 +2412,6 @@
   [(set_attr "move_type" "move,load,store")
(set_attr "mode" "DF")])
 
-;; Emit a doubleword move in which exactly one of the operands is
-;; a floating-point

[gcc r14-10417] LoongArch: TFmode is not allowed to be stored in the float register.

[LuluCheng via Gcc-cvs]

https://gcc.gnu.org/g:89f9342980b7976f98ba43fac6a64a7a2214b6e6

commit r14-10417-g89f9342980b7976f98ba43fac6a64a7a2214b6e6
Author: Lulu Cheng 
Date:   Thu Jul 4 10:37:26 2024 +0800

LoongArch: TFmode is not allowed to be stored in the float register.

PR target/115752

gcc/ChangeLog:

* config/loongarch/loongarch.cc
(loongarch_hard_regno_mode_ok_uncached): Replace
UNITS_PER_FPVALUE with UNITS_PER_HWFPVALUE.
* config/loongarch/loongarch.h (UNITS_PER_FPVALUE): Delete.

gcc/testsuite/ChangeLog:

* gcc.target/loongarch/pr115752.c: New test.

(cherry picked from commit abeb6c8a62758faa0719e818e6e8a7db15a6793b)

Diff:
---
 gcc/config/loongarch/loongarch.cc | 2 +-
 gcc/config/loongarch/loongarch.h  | 7 ---
 gcc/testsuite/gcc.target/loongarch/pr115752.c | 8 
 3 files changed, 9 insertions(+), 8 deletions(-)

diff --git a/gcc/config/loongarch/loongarch.cc 
b/gcc/config/loongarch/loongarch.cc
index 1b6df6a43650..4b456e3ef1f5 100644
--- a/gcc/config/loongarch/loongarch.cc
+++ b/gcc/config/loongarch/loongarch.cc
@@ -6705,7 +6705,7 @@ loongarch_hard_regno_mode_ok_uncached (unsigned int 
regno, machine_mode mode)
   if (mclass == MODE_FLOAT
  || mclass == MODE_COMPLEX_FLOAT
  || mclass == MODE_VECTOR_FLOAT)
-   return size <= UNITS_PER_FPVALUE;
+   return size <= UNITS_PER_HWFPVALUE;
 
   /* Allow integer modes that fit into a single register.  We need
 to put integers into FPRs when using instructions like CVT
diff --git a/gcc/config/loongarch/loongarch.h b/gcc/config/loongarch/loongarch.h
index f7fe950f3332..6be1029bef9d 100644
--- a/gcc/config/loongarch/loongarch.h
+++ b/gcc/config/loongarch/loongarch.h
@@ -146,13 +146,6 @@ along with GCC; see the file COPYING3.  If not see
 #define UNITS_PER_HWFPVALUE \
   (TARGET_SOFT_FLOAT ? 0 : UNITS_PER_FP_REG)
 
-/* The largest size of value that can be held in floating-point
-   registers.  */
-#define UNITS_PER_FPVALUE \
-  (TARGET_SOFT_FLOAT ? 0 \
-   : TARGET_SINGLE_FLOAT ? UNITS_PER_FP_REG \
-: LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT)
-
 /* The number of bytes in a double.  */
 #define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT)
 
diff --git a/gcc/testsuite/gcc.target/loongarch/pr115752.c 
b/gcc/testsuite/gcc.target/loongarch/pr115752.c
new file mode 100644
index ..df4bae524f75
--- /dev/null
+++ b/gcc/testsuite/gcc.target/loongarch/pr115752.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+
+long double
+test (long double xx)
+{
+   __asm ("" :: "f"(xx)); /* { dg-error "inconsistent operand constraints in 
an 'asm'" } */
+   return xx + 1;
+}

[gcc r13-8910] LoongArch: TFmode is not allowed to be stored in the float register.

[LuluCheng via Gcc-cvs]

https://gcc.gnu.org/g:616c3290785c204b3019e7aaff8a7d9bb425d336

commit r13-8910-g616c3290785c204b3019e7aaff8a7d9bb425d336
Author: Lulu Cheng 
Date:   Thu Jul 4 10:37:26 2024 +0800

LoongArch: TFmode is not allowed to be stored in the float register.

PR target/115752

gcc/ChangeLog:

* config/loongarch/loongarch.cc
(loongarch_hard_regno_mode_ok_uncached): Replace
UNITS_PER_FPVALUE with UNITS_PER_HWFPVALUE.
* config/loongarch/loongarch.h (UNITS_PER_FPVALUE): Delete.

gcc/testsuite/ChangeLog:

* gcc.target/loongarch/pr115752.c: New test.

(cherry picked from commit abeb6c8a62758faa0719e818e6e8a7db15a6793b)

Diff:
---
 gcc/config/loongarch/loongarch.cc | 2 +-
 gcc/config/loongarch/loongarch.h  | 7 ---
 gcc/testsuite/gcc.target/loongarch/pr115752.c | 8 
 3 files changed, 9 insertions(+), 8 deletions(-)

diff --git a/gcc/config/loongarch/loongarch.cc 
b/gcc/config/loongarch/loongarch.cc
index 2238858cd6ab..be26e156beb8 100644
--- a/gcc/config/loongarch/loongarch.cc
+++ b/gcc/config/loongarch/loongarch.cc
@@ -5491,7 +5491,7 @@ loongarch_hard_regno_mode_ok_uncached (unsigned int 
regno, machine_mode mode)
   if (mclass == MODE_FLOAT
  || mclass == MODE_COMPLEX_FLOAT
  || mclass == MODE_VECTOR_FLOAT)
-   return size <= UNITS_PER_FPVALUE;
+   return size <= UNITS_PER_HWFPVALUE;
 
   /* Allow integer modes that fit into a single register.  We need
 to put integers into FPRs when using instructions like CVT
diff --git a/gcc/config/loongarch/loongarch.h b/gcc/config/loongarch/loongarch.h
index d072522e3cfe..b1149a12aba4 100644
--- a/gcc/config/loongarch/loongarch.h
+++ b/gcc/config/loongarch/loongarch.h
@@ -202,13 +202,6 @@ along with GCC; see the file COPYING3.  If not see
 #define UNITS_PER_HWFPVALUE \
   (TARGET_SOFT_FLOAT ? 0 : UNITS_PER_FPREG)
 
-/* The largest size of value that can be held in floating-point
-   registers.  */
-#define UNITS_PER_FPVALUE \
-  (TARGET_SOFT_FLOAT ? 0 \
-   : TARGET_SINGLE_FLOAT ? UNITS_PER_FPREG \
-: LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT)
-
 /* The number of bytes in a double.  */
 #define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT)
 
diff --git a/gcc/testsuite/gcc.target/loongarch/pr115752.c 
b/gcc/testsuite/gcc.target/loongarch/pr115752.c
new file mode 100644
index ..df4bae524f75
--- /dev/null
+++ b/gcc/testsuite/gcc.target/loongarch/pr115752.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+
+long double
+test (long double xx)
+{
+   __asm ("" :: "f"(xx)); /* { dg-error "inconsistent operand constraints in 
an 'asm'" } */
+   return xx + 1;
+}

[gcc r15-2167] LoongArch: Organize the code related to split move and merge the same functions.

[LuluCheng via Gcc-cvs]

https://gcc.gnu.org/g:390c3e4ed28f6c7ef176c90b557fa0203678dbb3

commit r15-2167-g390c3e4ed28f6c7ef176c90b557fa0203678dbb3
Author: Lulu Cheng 
Date:   Fri Jul 12 09:57:40 2024 +0800

LoongArch: Organize the code related to split move and merge the same 
functions.

gcc/ChangeLog:

* config/loongarch/loongarch-protos.h
(loongarch_split_128bit_move): Delete.
(loongarch_split_128bit_move_p): Delete.
(loongarch_split_256bit_move): Delete.
(loongarch_split_256bit_move_p): Delete.
(loongarch_split_vector_move): Add a function declaration.
* config/loongarch/loongarch.cc
(loongarch_vector_costs::finish_cost): Adjust the code
formatting.
(loongarch_split_vector_move_p): Merge
loongarch_split_128bit_move_p and loongarch_split_256bit_move_p.
(loongarch_split_move_p): Merge code.
(loongarch_split_move): Likewise.
(loongarch_split_128bit_move_p): Delete.
(loongarch_split_256bit_move_p): Delete.
(loongarch_split_128bit_move): Delete.
(loongarch_split_vector_move): Merge loongarch_split_128bit_move
and loongarch_split_256bit_move.
(loongarch_split_256bit_move): Delete.
(loongarch_global_init): Remove the extra semicolon at the
end of the function.
* config/loongarch/loongarch.md (*movdf_softfloat):  Added a new
condition TARGET_64BIT.

Diff:
---
 gcc/config/loongarch/loongarch-protos.h |   5 +-
 gcc/config/loongarch/loongarch.cc   | 221 
 gcc/config/loongarch/loongarch.md   |   1 +
 3 files changed, 58 insertions(+), 169 deletions(-)

diff --git a/gcc/config/loongarch/loongarch-protos.h 
b/gcc/config/loongarch/loongarch-protos.h
index e238d795a738..85f6e8943997 100644
--- a/gcc/config/loongarch/loongarch-protos.h
+++ b/gcc/config/loongarch/loongarch-protos.h
@@ -85,10 +85,7 @@ extern bool loongarch_split_move_p (rtx, rtx);
 extern void loongarch_split_move (rtx, rtx);
 extern bool loongarch_addu16i_imm12_operand_p (HOST_WIDE_INT, machine_mode);
 extern void loongarch_split_plus_constant (rtx *, machine_mode);
-extern void loongarch_split_128bit_move (rtx, rtx);
-extern bool loongarch_split_128bit_move_p (rtx, rtx);
-extern void loongarch_split_256bit_move (rtx, rtx);
-extern bool loongarch_split_256bit_move_p (rtx, rtx);
+extern void loongarch_split_vector_move (rtx, rtx);
 extern const char *loongarch_output_move (rtx, rtx);
 #ifdef RTX_CODE
 extern void loongarch_expand_scc (rtx *);
diff --git a/gcc/config/loongarch/loongarch.cc 
b/gcc/config/loongarch/loongarch.cc
index 8eb47ff95c36..c7a02103ef51 100644
--- a/gcc/config/loongarch/loongarch.cc
+++ b/gcc/config/loongarch/loongarch.cc
@@ -4354,10 +4354,10 @@ void
 loongarch_vector_costs::finish_cost (const vector_costs *scalar_costs)
 {
   loop_vec_info loop_vinfo = dyn_cast (m_vinfo);
+
   if (loop_vinfo)
-{
-  m_suggested_unroll_factor = determine_suggested_unroll_factor 
(loop_vinfo);
-}
+m_suggested_unroll_factor
+  = determine_suggested_unroll_factor (loop_vinfo);
 
   vector_costs::finish_cost (scalar_costs);
 }
@@ -4423,6 +4423,7 @@ loongarch_subword (rtx op, bool high_p)
   return simplify_gen_subreg (word_mode, op, mode, byte);
 }
 
+static bool loongarch_split_vector_move_p (rtx dest, rtx src);
 /* Return true if a move from SRC to DEST should be split into two.
SPLIT_TYPE describes the split condition.  */
 
@@ -,13 +4445,11 @@ loongarch_split_move_p (rtx dest, rtx src)
return false;
 }
 
-  /* Check if LSX moves need splitting.  */
-  if (LSX_SUPPORTED_MODE_P (GET_MODE (dest)))
-return loongarch_split_128bit_move_p (dest, src);
 
-  /* Check if LASX moves need splitting.  */
-  if (LASX_SUPPORTED_MODE_P (GET_MODE (dest)))
-return loongarch_split_256bit_move_p (dest, src);
+  /* Check if vector moves need splitting.  */
+  if (LSX_SUPPORTED_MODE_P (GET_MODE (dest))
+  || LASX_SUPPORTED_MODE_P (GET_MODE (dest)))
+return loongarch_split_vector_move_p (dest, src);
 
   /* Otherwise split all multiword moves.  */
   return size > UNITS_PER_WORD;
@@ -4463,10 +4462,9 @@ void
 loongarch_split_move (rtx dest, rtx src)
 {
   gcc_checking_assert (loongarch_split_move_p (dest, src));
-  if (LSX_SUPPORTED_MODE_P (GET_MODE (dest)))
-loongarch_split_128bit_move (dest, src);
-  else if (LASX_SUPPORTED_MODE_P (GET_MODE (dest)))
-loongarch_split_256bit_move (dest, src);
+  if (LSX_SUPPORTED_MODE_P (GET_MODE (dest))
+  || LASX_SUPPORTED_MODE_P (GET_MODE (dest)))
+loongarch_split_vector_move (dest, src);
   else
 gcc_unreachable ();
 }
@@ -4588,224 +4586,117 @@ loongarch_output_move_index_float (rtx x, 
machine_mode mode, bool ldr)
 
   return insn[ldr][index-2];
 }
-/* Return true if a 128-bit move from SRC to DEST should be split.  */
-
-bool
-loongarch_split_128bit_move_p (rt

[gcc r14-9407] LoongArch: Fixed an issue with the implementation of the template atomic_compare_and_swapsi.

[LuluCheng via Gcc-cvs]

https://gcc.gnu.org/g:3a3fbec0a4d3f36de58df9ef0b3992a3ffb359c2

commit r14-9407-g3a3fbec0a4d3f36de58df9ef0b3992a3ffb359c2
Author: Lulu Cheng 
Date:   Tue Mar 5 14:43:04 2024 +0800

LoongArch: Fixed an issue with the implementation of the template 
atomic_compare_and_swapsi.

If the hardware does not support LAMCAS, atomic_compare_and_swapsi needs to 
be
implemented through "ll.w+sc.w". In the implementation of the instruction 
sequence,
it is necessary to determine whether the two registers are equal.
Since LoongArch's comparison instructions do not distinguish between 32-bit
and 64-bit, the two operand registers that need to be compared are 
symbolically
extended, and one of the operand registers is obtained from memory through 
the
"ll.w" instruction, which can ensure that the symbolic expansion is carried 
out.
However, the value of the other operand register is not guaranteed to be the
value of the sign extension.

gcc/ChangeLog:

* config/loongarch/sync.md (atomic_cas_value_strong):
In loongarch64, a sign extension operation is added when
operands[2] is a register operand and the mode is SImode.

gcc/testsuite/ChangeLog:

* g++.target/loongarch/atomic-cas-int.C: New test.

Diff:
---
 gcc/config/loongarch/sync.md   | 46 --
 .../g++.target/loongarch/atomic-cas-int.C  | 32 +++
 2 files changed, 67 insertions(+), 11 deletions(-)

diff --git a/gcc/config/loongarch/sync.md b/gcc/config/loongarch/sync.md
index 8f35a5b48d2..d41c2d26811 100644
--- a/gcc/config/loongarch/sync.md
+++ b/gcc/config/loongarch/sync.md
@@ -245,18 +245,42 @@
(clobber (match_scratch:GPR 5 "=&r"))]
   ""
 {
-  return "1:\\n\\t"
-"ll.\\t%0,%1\\n\\t"
-"bne\\t%0,%z2,2f\\n\\t"
-"or%i3\\t%5,$zero,%3\\n\\t"
-"sc.\\t%5,%1\\n\\t"
-"beqz\\t%5,1b\\n\\t"
-"b\\t3f\\n\\t"
-"2:\\n\\t"
-"%G4\\n\\t"
-"3:\\n\\t";
+  output_asm_insn ("1:", operands);
+  output_asm_insn ("ll.\t%0,%1", operands);
+
+  /* Like the test case atomic-cas-int.C, in loongarch64, O1 and higher, the
+ return value of the val_without_const_folding will not be truncated and
+ will be passed directly to the function compare_exchange_strong.
+ However, the instruction 'bne' does not distinguish between 32-bit and
+ 64-bit operations.  so if the upper 32 bits of the register are not
+ extended by the 32nd bit symbol, then the comparison may not be valid
+ here.  This will affect the result of the operation.  */
+
+  if (TARGET_64BIT && REG_P (operands[2])
+  && GET_MODE (operands[2]) == SImode)
+{
+  output_asm_insn ("addi.w\t%5,%2,0", operands);
+  output_asm_insn ("bne\t%0,%5,2f", operands);
+}
+  else
+output_asm_insn ("bne\t%0,%z2,2f", operands);
+
+  output_asm_insn ("or%i3\t%5,$zero,%3", operands);
+  output_asm_insn ("sc.\t%5,%1", operands);
+  output_asm_insn ("beqz\t%5,1b", operands);
+  output_asm_insn ("b\t3f", operands);
+  output_asm_insn ("2:", operands);
+  output_asm_insn ("%G4", operands);
+  output_asm_insn ("3:", operands);
+
+  return "";
 }
-  [(set (attr "length") (const_int 28))])
+  [(set (attr "length")
+ (if_then_else
+   (and (match_test "GET_MODE (operands[2]) == SImode")
+(match_test "REG_P (operands[2])"))
+   (const_int 32)
+   (const_int 28)))])
 
 (define_insn "atomic_cas_value_strong_amcas"
   [(set (match_operand:QHWD 0 "register_operand" "=&r")
diff --git a/gcc/testsuite/g++.target/loongarch/atomic-cas-int.C 
b/gcc/testsuite/g++.target/loongarch/atomic-cas-int.C
new file mode 100644
index 000..830ce48267a
--- /dev/null
+++ b/gcc/testsuite/g++.target/loongarch/atomic-cas-int.C
@@ -0,0 +1,32 @@
+/* { dg-do run } */
+/* { dg-options "-O2" } */
+
+#include 
+#include 
+
+__attribute__ ((noinline)) long
+val_without_const_folding (long val)
+{
+  return val;
+}
+
+int
+main ()
+{
+  int oldval = 0xaa;
+  int newval = 0xbb;
+  std::atomic amo;
+
+  amo.store (oldval);
+
+  long longval = val_without_const_folding (0xff80 + oldval);
+  oldval = static_cast (longval);
+
+  amo.compare_exchange_strong (oldval, newval);
+
+  if (newval != amo.load (std::memory_order_relaxed))
+__builtin_abort ();
+
+  return 0;
+}
+

[gcc r14-9408] LoongArch: testsuite: Add compilation options to the regname-fp-s9.c.

[LuluCheng via Gcc-cvs]

https://gcc.gnu.org/g:6fe63013e3292a45288461b7efa9d52e0ac234dc

commit r14-9408-g6fe63013e3292a45288461b7efa9d52e0ac234dc
Author: Lulu Cheng 
Date:   Thu Mar 7 09:44:03 2024 +0800

LoongArch: testsuite: Add compilation options to the regname-fp-s9.c.

When the value of the macro DEFAULT_CFLAGS is set to '-ansi 
-pedantic-errors',
regname-s9-fp.c will test to fail. To solve this problem, add the 
compilation
option '-Wno-pedantic -std=gnu90' to this test case.

gcc/testsuite/ChangeLog:

* gcc.target/loongarch/regname-fp-s9.c: Add compilation option
'-Wno-pedantic -std=gnu90'.

Diff:
---
 gcc/testsuite/gcc.target/loongarch/regname-fp-s9.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/gcc/testsuite/gcc.target/loongarch/regname-fp-s9.c 
b/gcc/testsuite/gcc.target/loongarch/regname-fp-s9.c
index d2e3b80f83c..77a74f1f667 100644
--- a/gcc/testsuite/gcc.target/loongarch/regname-fp-s9.c
+++ b/gcc/testsuite/gcc.target/loongarch/regname-fp-s9.c
@@ -1,3 +1,4 @@
 /* { dg-do compile } */
+/* { dg-additional-options "-Wno-pedantic -std=gnu90" } */
 register long s9 asm("s9"); /* { dg-note "conflicts with 's9'" } */
 register long fp asm("fp"); /* { dg-warning "register of 'fp' used for 
multiple global register variables" } */

[gcc r13-8413] LoongArch: Fixed an issue with the implementation of the template atomic_compare_and_swapsi.

[LuluCheng via Gcc-cvs]

https://gcc.gnu.org/g:bf784936bc8be013db8b3e35002e76838f830f40

commit r13-8413-gbf784936bc8be013db8b3e35002e76838f830f40
Author: Lulu Cheng 
Date:   Tue Mar 5 14:43:04 2024 +0800

LoongArch: Fixed an issue with the implementation of the template 
atomic_compare_and_swapsi.

If the hardware does not support LAMCAS, atomic_compare_and_swapsi needs to 
be
implemented through "ll.w+sc.w". In the implementation of the instruction 
sequence,
it is necessary to determine whether the two registers are equal.
Since LoongArch's comparison instructions do not distinguish between 32-bit
and 64-bit, the two operand registers that need to be compared are 
symbolically
extended, and one of the operand registers is obtained from memory through 
the
"ll.w" instruction, which can ensure that the symbolic expansion is carried 
out.
However, the value of the other operand register is not guaranteed to be the
value of the sign extension.

gcc/ChangeLog:

* config/loongarch/sync.md (atomic_cas_value_strong):
In loongarch64, a sign extension operation is added when
operands[2] is a register operand and the mode is SImode.

gcc/testsuite/ChangeLog:

* g++.target/loongarch/atomic-cas-int.C: New test.

(cherry picked from commit 3a3fbec0a4d3f36de58df9ef0b3992a3ffb359c2)

Diff:
---
 gcc/config/loongarch/sync.md   | 46 --
 .../g++.target/loongarch/atomic-cas-int.C  | 32 +++
 2 files changed, 67 insertions(+), 11 deletions(-)

diff --git a/gcc/config/loongarch/sync.md b/gcc/config/loongarch/sync.md
index db3a21690b8..89956e07c79 100644
--- a/gcc/config/loongarch/sync.md
+++ b/gcc/config/loongarch/sync.md
@@ -129,18 +129,42 @@
(clobber (match_scratch:GPR 6 "=&r"))]
   ""
 {
-  return "1:\\n\\t"
-"ll.\\t%0,%1\\n\\t"
-"bne\\t%0,%z2,2f\\n\\t"
-"or%i3\\t%6,$zero,%3\\n\\t"
-"sc.\\t%6,%1\\n\\t"
-"beqz\\t%6,1b\\n\\t"
-"b\\t3f\\n\\t"
-"2:\\n\\t"
-"%G5\\n\\t"
-"3:\\n\\t";
+  output_asm_insn ("1:", operands);
+  output_asm_insn ("ll.\t%0,%1", operands);
+
+  /* Like the test case atomic-cas-int.C, in loongarch64, O1 and higher, the
+ return value of the val_without_const_folding will not be truncated and
+ will be passed directly to the function compare_exchange_strong.
+ However, the instruction 'bne' does not distinguish between 32-bit and
+ 64-bit operations.  so if the upper 32 bits of the register are not
+ extended by the 32nd bit symbol, then the comparison may not be valid
+ here.  This will affect the result of the operation.  */
+
+  if (TARGET_64BIT && REG_P (operands[2])
+  && GET_MODE (operands[2]) == SImode)
+{
+  output_asm_insn ("addi.w\t%6,%2,0", operands);
+  output_asm_insn ("bne\t%0,%6,2f", operands);
+}
+  else
+output_asm_insn ("bne\t%0,%z2,2f", operands);
+
+  output_asm_insn ("or%i3\t%6,$zero,%3", operands);
+  output_asm_insn ("sc.\t%6,%1", operands);
+  output_asm_insn ("beqz\t%6,1b", operands);
+  output_asm_insn ("b\t3f", operands);
+  output_asm_insn ("2:", operands);
+  output_asm_insn ("%G5", operands);
+  output_asm_insn ("3:", operands);
+
+  return "";
 }
-  [(set (attr "length") (const_int 28))])
+  [(set (attr "length")
+ (if_then_else
+   (and (match_test "GET_MODE (operands[2]) == SImode")
+(match_test "REG_P (operands[2])"))
+   (const_int 32)
+   (const_int 28)))])
 
 (define_expand "atomic_compare_and_swap"
   [(match_operand:SI 0 "register_operand" "")   ;; bool output
diff --git a/gcc/testsuite/g++.target/loongarch/atomic-cas-int.C 
b/gcc/testsuite/g++.target/loongarch/atomic-cas-int.C
new file mode 100644
index 000..830ce48267a
--- /dev/null
+++ b/gcc/testsuite/g++.target/loongarch/atomic-cas-int.C
@@ -0,0 +1,32 @@
+/* { dg-do run } */
+/* { dg-options "-O2" } */
+
+#include 
+#include 
+
+__attribute__ ((noinline)) long
+val_without_const_folding (long val)
+{
+  return val;
+}
+
+int
+main ()
+{
+  int oldval = 0xaa;
+  int newval = 0xbb;
+  std::atomic amo;
+
+  amo.store (oldval);
+
+  long longval = val_without_const_folding (0xff80 + oldval);
+  oldval = static_cast (longval);
+
+  amo.compare_exchange_strong (oldval, newval);
+
+  if (newval != amo.load (std::memory_order_relaxed))
+__builtin_abort ();
+
+  return 0;
+}
+

[gcc r12-10200] LoongArch: Fixed an issue with the implementation of the template atomic_compare_and_swapsi.

[LuluCheng via Gcc-cvs]

https://gcc.gnu.org/g:d77ed1d6eb82fb5ef5cd94c06f5c67db753fb7c2

commit r12-10200-gd77ed1d6eb82fb5ef5cd94c06f5c67db753fb7c2
Author: Lulu Cheng 
Date:   Tue Mar 5 14:43:04 2024 +0800

LoongArch: Fixed an issue with the implementation of the template 
atomic_compare_and_swapsi.

If the hardware does not support LAMCAS, atomic_compare_and_swapsi needs to 
be
implemented through "ll.w+sc.w". In the implementation of the instruction 
sequence,
it is necessary to determine whether the two registers are equal.
Since LoongArch's comparison instructions do not distinguish between 32-bit
and 64-bit, the two operand registers that need to be compared are 
symbolically
extended, and one of the operand registers is obtained from memory through 
the
"ll.w" instruction, which can ensure that the symbolic expansion is carried 
out.
However, the value of the other operand register is not guaranteed to be the
value of the sign extension.

gcc/ChangeLog:

* config/loongarch/sync.md (atomic_cas_value_strong):
In loongarch64, a sign extension operation is added when
operands[2] is a register operand and the mode is SImode.

gcc/testsuite/ChangeLog:

* g++.target/loongarch/atomic-cas-int.C: New test.

(cherry picked from commit 3a3fbec0a4d3f36de58df9ef0b3992a3ffb359c2)

Diff:
---
 gcc/config/loongarch/sync.md   | 46 --
 .../g++.target/loongarch/atomic-cas-int.C  | 32 +++
 2 files changed, 67 insertions(+), 11 deletions(-)

diff --git a/gcc/config/loongarch/sync.md b/gcc/config/loongarch/sync.md
index b8763b8f9d1..c2f0d33ab21 100644
--- a/gcc/config/loongarch/sync.md
+++ b/gcc/config/loongarch/sync.md
@@ -129,18 +129,42 @@
(clobber (match_scratch:GPR 6 "=&r"))]
   ""
 {
-  return "1:\\n\\t"
-"ll.\\t%0,%1\\n\\t"
-"bne\\t%0,%z2,2f\\n\\t"
-"or%i3\\t%6,$zero,%3\\n\\t"
-"sc.\\t%6,%1\\n\\t"
-"beqz\\t%6,1b\\n\\t"
-"b\\t3f\\n\\t"
-"2:\\n\\t"
-"%G5\\n\\t"
-"3:\\n\\t";
+  output_asm_insn ("1:", operands);
+  output_asm_insn ("ll.\t%0,%1", operands);
+
+  /* Like the test case atomic-cas-int.C, in loongarch64, O1 and higher, the
+ return value of the val_without_const_folding will not be truncated and
+ will be passed directly to the function compare_exchange_strong.
+ However, the instruction 'bne' does not distinguish between 32-bit and
+ 64-bit operations.  so if the upper 32 bits of the register are not
+ extended by the 32nd bit symbol, then the comparison may not be valid
+ here.  This will affect the result of the operation.  */
+
+  if (TARGET_64BIT && REG_P (operands[2])
+  && GET_MODE (operands[2]) == SImode)
+{
+  output_asm_insn ("addi.w\t%6,%2,0", operands);
+  output_asm_insn ("bne\t%0,%6,2f", operands);
+}
+  else
+output_asm_insn ("bne\t%0,%z2,2f", operands);
+
+  output_asm_insn ("or%i3\t%6,$zero,%3", operands);
+  output_asm_insn ("sc.\t%6,%1", operands);
+  output_asm_insn ("beqz\t%6,1b", operands);
+  output_asm_insn ("b\t3f", operands);
+  output_asm_insn ("2:", operands);
+  output_asm_insn ("%G5", operands);
+  output_asm_insn ("3:", operands);
+
+  return "";
 }
-  [(set (attr "length") (const_int 28))])
+  [(set (attr "length")
+ (if_then_else
+   (and (match_test "GET_MODE (operands[2]) == SImode")
+(match_test "REG_P (operands[2])"))
+   (const_int 32)
+   (const_int 28)))])
 
 (define_expand "atomic_compare_and_swap"
   [(match_operand:SI 0 "register_operand" "")   ;; bool output
diff --git a/gcc/testsuite/g++.target/loongarch/atomic-cas-int.C 
b/gcc/testsuite/g++.target/loongarch/atomic-cas-int.C
new file mode 100644
index 000..830ce48267a
--- /dev/null
+++ b/gcc/testsuite/g++.target/loongarch/atomic-cas-int.C
@@ -0,0 +1,32 @@
+/* { dg-do run } */
+/* { dg-options "-O2" } */
+
+#include 
+#include 
+
+__attribute__ ((noinline)) long
+val_without_const_folding (long val)
+{
+  return val;
+}
+
+int
+main ()
+{
+  int oldval = 0xaa;
+  int newval = 0xbb;
+  std::atomic amo;
+
+  amo.store (oldval);
+
+  long longval = val_without_const_folding (0xff80 + oldval);
+  oldval = static_cast (longval);
+
+  amo.compare_exchange_strong (oldval, newval);
+
+  if (newval != amo.load (std::memory_order_relaxed))
+__builtin_abort ();
+
+  return 0;
+}
+

[gcc r14-9486] LoongArch: Remove masking process for operand 3 of xvpermi.q.

[LuluCheng via Gcc-cvs]

https://gcc.gnu.org/g:d7d05824ae68da24908d97a10b9ec59d08f75a90

commit r14-9486-gd7d05824ae68da24908d97a10b9ec59d08f75a90
Author: Chenghui Pan 
Date:   Thu Mar 14 09:26:54 2024 +0800

LoongArch: Remove masking process for operand 3 of xvpermi.q.

The behavior of non-zero unused bits in xvpermi.q instruction's
third operand is undefined on LoongArch, according to our
discussion (https://github.com/llvm/llvm-project/pull/83540),
we think that keeping original insn operand as unmodified
state is better solution.

This patch partially reverts 7b158e036a95b1ab40793dd53bed7dbd770ffdaf.

gcc/ChangeLog:

* config/loongarch/lasx.md (lasx_xvpermi_q_):
Remove masking of operand 3.

gcc/testsuite/ChangeLog:

* gcc.target/loongarch/vector/lasx/lasx-xvpermi_q.c:
Reposition operand 3's value into instruction's defined accept 
range.

Diff:
---
 gcc/config/loongarch/lasx.md| 5 -
 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvpermi_q.c | 6 +++---
 2 files changed, 3 insertions(+), 8 deletions(-)

diff --git a/gcc/config/loongarch/lasx.md b/gcc/config/loongarch/lasx.md
index ac84db7f0ce..3f25c0c1756 100644
--- a/gcc/config/loongarch/lasx.md
+++ b/gcc/config/loongarch/lasx.md
@@ -640,8 +640,6 @@
(set_attr "mode" "")])
 
 ;; xvpermi.q
-;; Unused bits in operands[3] need be set to 0 to avoid
-;; causing undefined behavior on LA464.
 (define_insn "lasx_xvpermi_q_"
   [(set (match_operand:LASX 0 "register_operand" "=f")
(unspec:LASX
@@ -651,9 +649,6 @@
  UNSPEC_LASX_XVPERMI_Q))]
   "ISA_HAS_LASX"
 {
-  int mask = 0x33;
-  mask &= INTVAL (operands[3]);
-  operands[3] = GEN_INT (mask);
   return "xvpermi.q\t%u0,%u2,%3";
 }
   [(set_attr "type" "simd_splat")
diff --git a/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvpermi_q.c 
b/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvpermi_q.c
index dbc29d2fb22..f89dfc31120 100644
--- a/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvpermi_q.c
+++ b/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvpermi_q.c
@@ -27,7 +27,7 @@ main ()
   *((unsigned long*)& __m256i_result[2]) = 0x7fff7fff7fff;
   *((unsigned long*)& __m256i_result[1]) = 0x7fe37fe3001d001d;
   *((unsigned long*)& __m256i_result[0]) = 0x7fff7fff7fff;
-  __m256i_out = __lasx_xvpermi_q (__m256i_op0, __m256i_op1, 0x2a);
+  __m256i_out = __lasx_xvpermi_q (__m256i_op0, __m256i_op1, 0x22);
   ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out);
 
   *((unsigned long*)& __m256i_op0[3]) = 0x;
@@ -42,7 +42,7 @@ main ()
   *((unsigned long*)& __m256i_result[2]) = 0x0019001c;
   *((unsigned long*)& __m256i_result[1]) = 0x;
   *((unsigned long*)& __m256i_result[0]) = 0x01fe;
-  __m256i_out = __lasx_xvpermi_q (__m256i_op0, __m256i_op1, 0xb9);
+  __m256i_out = __lasx_xvpermi_q (__m256i_op0, __m256i_op1, 0x31);
   ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out);
 
   *((unsigned long*)& __m256i_op0[3]) = 0x00ff00ff00ff00ff;
@@ -57,7 +57,7 @@ main ()
   *((unsigned long*)& __m256i_result[2]) = 0x;
   *((unsigned long*)& __m256i_result[1]) = 0x00ff00ff00ff00ff;
   *((unsigned long*)& __m256i_result[0]) = 0x00ff00ff00ff00ff;
-  __m256i_out = __lasx_xvpermi_q (__m256i_op0, __m256i_op1, 0xca);
+  __m256i_out = __lasx_xvpermi_q (__m256i_op0, __m256i_op1, 0x02);
   ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out);
 
   return 0;

[gcc r14-9562] LoongArch: Remove unused/useless definitions.

[LuluCheng via Gcc-cvs]

https://gcc.gnu.org/g:0529f98b7b1b0eadb009a7aa3161462897e53745

commit r14-9562-g0529f98b7b1b0eadb009a7aa3161462897e53745
Author: Chenghui Pan 
Date:   Fri Mar 15 09:30:25 2024 +0800

LoongArch: Remove unused/useless definitions.

This patch removes some unnecessary definitions of target hook functions
according to the documentation of GCC.

gcc/ChangeLog:

* config/loongarch/loongarch-protos.h
(loongarch_cfun_has_cprestore_slot_p): Delete.
(loongarch_adjust_insn_length): Delete.
(current_section_name): Delete.
(loongarch_split_symbol_type): Delete.
* config/loongarch/loongarch.cc
(loongarch_case_values_threshold): Delete.
(loongarch_spill_class): Delete.
(TARGET_OPTAB_SUPPORTED_P): Delete.
(TARGET_CASE_VALUES_THRESHOLD): Delete.
(TARGET_SPILL_CLASS): Delete.

Diff:
---
 gcc/config/loongarch/loongarch-protos.h |  5 -
 gcc/config/loongarch/loongarch.cc   | 26 --
 2 files changed, 31 deletions(-)

diff --git a/gcc/config/loongarch/loongarch-protos.h 
b/gcc/config/loongarch/loongarch-protos.h
index 1fdfda9af01..871544f760c 100644
--- a/gcc/config/loongarch/loongarch-protos.h
+++ b/gcc/config/loongarch/loongarch-protos.h
@@ -93,7 +93,6 @@ extern void loongarch_split_lsx_copy_d (rtx, rtx, rtx, rtx 
(*)(rtx, rtx, rtx));
 extern void loongarch_split_lsx_insert_d (rtx, rtx, rtx, rtx);
 extern void loongarch_split_lsx_fill_d (rtx, rtx);
 extern const char *loongarch_output_move (rtx, rtx);
-extern bool loongarch_cfun_has_cprestore_slot_p (void);
 #ifdef RTX_CODE
 extern void loongarch_expand_scc (rtx *);
 extern bool loongarch_expand_vec_cmp (rtx *);
@@ -135,7 +134,6 @@ extern int loongarch_class_max_nregs (enum reg_class, 
machine_mode);
 extern machine_mode loongarch_hard_regno_caller_save_mode (unsigned int,
   unsigned int,
   machine_mode);
-extern int loongarch_adjust_insn_length (rtx_insn *, int);
 extern const char *loongarch_output_conditional_branch (rtx_insn *, rtx *,
const char *,
const char *);
@@ -157,7 +155,6 @@ extern bool loongarch_global_symbol_noweak_p (const_rtx);
 extern bool loongarch_weak_symbol_p (const_rtx);
 extern bool loongarch_symbol_binds_local_p (const_rtx);
 
-extern const char *current_section_name (void);
 extern unsigned int current_section_flags (void);
 extern bool loongarch_use_ins_ext_p (rtx, HOST_WIDE_INT, HOST_WIDE_INT);
 extern bool loongarch_check_zero_div_p (void);
@@ -198,8 +195,6 @@ extern bool loongarch_epilogue_uses (unsigned int);
 extern bool loongarch_load_store_bonding_p (rtx *, machine_mode, bool);
 extern bool loongarch_split_symbol_type (enum loongarch_symbol_type);
 
-typedef rtx (*mulsidi3_gen_fn) (rtx, rtx, rtx);
-
 extern void loongarch_register_frame_header_opt (void);
 extern void loongarch_expand_vec_cond_expr (machine_mode, machine_mode, rtx *);
 extern void loongarch_expand_vec_cond_mask_expr (machine_mode, machine_mode,
diff --git a/gcc/config/loongarch/loongarch.cc 
b/gcc/config/loongarch/loongarch.cc
index 5344f2a6987..570e9aebad1 100644
--- a/gcc/config/loongarch/loongarch.cc
+++ b/gcc/config/loongarch/loongarch.cc
@@ -10816,23 +10816,6 @@ loongarch_expand_vec_cmp (rtx operands[])
   return true;
 }
 
-/* Implement TARGET_CASE_VALUES_THRESHOLD.  */
-
-unsigned int
-loongarch_case_values_threshold (void)
-{
-  return default_case_values_threshold ();
-}
-
-/* Implement TARGET_SPILL_CLASS.  */
-
-static reg_class_t
-loongarch_spill_class (reg_class_t rclass ATTRIBUTE_UNUSED,
-  machine_mode mode ATTRIBUTE_UNUSED)
-{
-  return NO_REGS;
-}
-
 /* Implement TARGET_PROMOTE_FUNCTION_MODE.  */
 
 /* This function is equivalent to default_promote_function_mode_always_promote
@@ -11287,9 +11270,6 @@ loongarch_asm_code_end (void)
 #undef TARGET_FUNCTION_ARG_BOUNDARY
 #define TARGET_FUNCTION_ARG_BOUNDARY loongarch_function_arg_boundary
 
-#undef TARGET_OPTAB_SUPPORTED_P
-#define TARGET_OPTAB_SUPPORTED_P loongarch_optab_supported_p
-
 #undef TARGET_VECTOR_MODE_SUPPORTED_P
 #define TARGET_VECTOR_MODE_SUPPORTED_P loongarch_vector_mode_supported_p
 
@@ -11359,18 +11339,12 @@ loongarch_asm_code_end (void)
 #undef TARGET_SCHED_REASSOCIATION_WIDTH
 #define TARGET_SCHED_REASSOCIATION_WIDTH loongarch_sched_reassociation_width
 
-#undef TARGET_CASE_VALUES_THRESHOLD
-#define TARGET_CASE_VALUES_THRESHOLD loongarch_case_values_threshold
-
 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV loongarch_atomic_assign_expand_fenv
 
 #undef TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS
 #define TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS true
 
-#undef TARGET_SPILL_CLASS
-#define TARGET_SPILL_CLASS loongarch_spill_c

[gcc r14-9563] LoongArch: Change loongarch_expand_vec_cmp()'s return type from bool to void.

[LuluCheng via Gcc-cvs]

https://gcc.gnu.org/g:1938d9d2bb8ecf84d2aa3c3ef2fb78ec19433057

commit r14-9563-g1938d9d2bb8ecf84d2aa3c3ef2fb78ec19433057
Author: Chenghui Pan 
Date:   Fri Mar 15 09:30:26 2024 +0800

LoongArch: Change loongarch_expand_vec_cmp()'s return type from bool to 
void.

This function is always return true at the end of function implementation,
so the return value is useless.

gcc/ChangeLog:

* config/loongarch/lasx.md (vec_cmp): Remove 
checking
of loongarch_expand_vec_cmp()'s return value.
(vec_cmpu): Ditto.
* config/loongarch/lsx.md (vec_cmp): Ditto.
(vec_cmpu): Ditto.
* config/loongarch/loongarch-protos.h
(loongarch_expand_vec_cmp): Change loongarch_expand_vec_cmp()'s 
return
type from bool to void.
* config/loongarch/loongarch.cc (loongarch_expand_vec_cmp): Ditto.

Diff:
---
 gcc/config/loongarch/lasx.md| 6 ++
 gcc/config/loongarch/loongarch-protos.h | 2 +-
 gcc/config/loongarch/loongarch.cc   | 3 +--
 gcc/config/loongarch/lsx.md | 6 ++
 4 files changed, 6 insertions(+), 11 deletions(-)

diff --git a/gcc/config/loongarch/lasx.md b/gcc/config/loongarch/lasx.md
index 3f25c0c1756..2fa5e46c8e8 100644
--- a/gcc/config/loongarch/lasx.md
+++ b/gcc/config/loongarch/lasx.md
@@ -1378,8 +1378,7 @@
   (match_operand:LASX 3 "register_operand")]))]
   "ISA_HAS_LASX"
 {
-  bool ok = loongarch_expand_vec_cmp (operands);
-  gcc_assert (ok);
+  loongarch_expand_vec_cmp (operands);
   DONE;
 })
 
@@ -1390,8 +1389,7 @@
   (match_operand:ILASX 3 "register_operand")]))]
   "ISA_HAS_LASX"
 {
-  bool ok = loongarch_expand_vec_cmp (operands);
-  gcc_assert (ok);
+  loongarch_expand_vec_cmp (operands);
   DONE;
 })
 
diff --git a/gcc/config/loongarch/loongarch-protos.h 
b/gcc/config/loongarch/loongarch-protos.h
index 871544f760c..e3ed2b912a5 100644
--- a/gcc/config/loongarch/loongarch-protos.h
+++ b/gcc/config/loongarch/loongarch-protos.h
@@ -95,7 +95,7 @@ extern void loongarch_split_lsx_fill_d (rtx, rtx);
 extern const char *loongarch_output_move (rtx, rtx);
 #ifdef RTX_CODE
 extern void loongarch_expand_scc (rtx *);
-extern bool loongarch_expand_vec_cmp (rtx *);
+extern void loongarch_expand_vec_cmp (rtx *);
 extern void loongarch_expand_conditional_branch (rtx *);
 extern void loongarch_expand_conditional_move (rtx *);
 extern void loongarch_expand_conditional_trap (rtx);
diff --git a/gcc/config/loongarch/loongarch.cc 
b/gcc/config/loongarch/loongarch.cc
index 570e9aebad1..f11cf149bbf 100644
--- a/gcc/config/loongarch/loongarch.cc
+++ b/gcc/config/loongarch/loongarch.cc
@@ -10807,13 +10807,12 @@ loongarch_expand_vec_cond_mask_expr (machine_mode 
mode, machine_mode vimode,
 }
 
 /* Expand integer vector comparison */
-bool
+void
 loongarch_expand_vec_cmp (rtx operands[])
 {
 
   rtx_code code = GET_CODE (operands[1]);
   loongarch_expand_lsx_cmp (operands[0], code, operands[2], operands[3]);
-  return true;
 }
 
 /* Implement TARGET_PROMOTE_FUNCTION_MODE.  */
diff --git a/gcc/config/loongarch/lsx.md b/gcc/config/loongarch/lsx.md
index b9b94b9079c..87d3e7c5d9f 100644
--- a/gcc/config/loongarch/lsx.md
+++ b/gcc/config/loongarch/lsx.md
@@ -518,8 +518,7 @@
   (match_operand:LSX 3 "register_operand")]))]
   "ISA_HAS_LSX"
 {
-  bool ok = loongarch_expand_vec_cmp (operands);
-  gcc_assert (ok);
+  loongarch_expand_vec_cmp (operands);
   DONE;
 })
 
@@ -530,8 +529,7 @@
   (match_operand:ILSX 3 "register_operand")]))]
   "ISA_HAS_LSX"
 {
-  bool ok = loongarch_expand_vec_cmp (operands);
-  gcc_assert (ok);
+  loongarch_expand_vec_cmp (operands);
   DONE;
 })

[gcc r14-9564] LoongArch: Combine UNITS_PER_FP_REG and UNITS_PER_FPREG macros.

[LuluCheng via Gcc-cvs]

https://gcc.gnu.org/g:994d8f922b9d88f45775f57a490409ab1c3baf59

commit r14-9564-g994d8f922b9d88f45775f57a490409ab1c3baf59
Author: Chenghui Pan 
Date:   Fri Mar 15 09:30:27 2024 +0800

LoongArch: Combine UNITS_PER_FP_REG and UNITS_PER_FPREG macros.

These macros are completely same in definition, so we can keep the previous 
one
and eliminate later one.

gcc/ChangeLog:

* config/loongarch/loongarch.cc
(loongarch_hard_regno_mode_ok_uncached): Combine UNITS_PER_FP_REG 
and
UNITS_PER_FPREG macros.
(loongarch_hard_regno_nregs): Ditto.
(loongarch_class_max_nregs): Ditto.
(loongarch_get_separate_components): Ditto.
(loongarch_process_components): Ditto.
* config/loongarch/loongarch.h (UNITS_PER_FPREG): Ditto.
(UNITS_PER_HWFPVALUE): Ditto.
(UNITS_PER_FPVALUE): Ditto.

Diff:
---
 gcc/config/loongarch/loongarch.cc | 10 +-
 gcc/config/loongarch/loongarch.h  |  7 ++-
 2 files changed, 7 insertions(+), 10 deletions(-)

diff --git a/gcc/config/loongarch/loongarch.cc 
b/gcc/config/loongarch/loongarch.cc
index f11cf149bbf..030957db4e7 100644
--- a/gcc/config/loongarch/loongarch.cc
+++ b/gcc/config/loongarch/loongarch.cc
@@ -6776,7 +6776,7 @@ loongarch_hard_regno_mode_ok_uncached (unsigned int 
regno, machine_mode mode)
 and TRUNC.  There's no point allowing sizes smaller than a word,
 because the FPU has no appropriate load/store instructions.  */
   if (mclass == MODE_INT)
-   return size >= MIN_UNITS_PER_WORD && size <= UNITS_PER_FPREG;
+   return size >= MIN_UNITS_PER_WORD && size <= UNITS_PER_FP_REG;
 }
 
   return false;
@@ -6819,7 +6819,7 @@ loongarch_hard_regno_nregs (unsigned int regno, 
machine_mode mode)
   if (LASX_SUPPORTED_MODE_P (mode))
return 1;
 
-  return (GET_MODE_SIZE (mode) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG;
+  return (GET_MODE_SIZE (mode) + UNITS_PER_FP_REG - 1) / UNITS_PER_FP_REG;
 }
 
   /* All other registers are word-sized.  */
@@ -6854,7 +6854,7 @@ loongarch_class_max_nregs (enum reg_class rclass, 
machine_mode mode)
  else if (LSX_SUPPORTED_MODE_P (mode))
size = MIN (size, UNITS_PER_LSX_REG);
  else
-   size = MIN (size, UNITS_PER_FPREG);
+   size = MIN (size, UNITS_PER_FP_REG);
}
   left &= ~reg_class_contents[FP_REGS];
 }
@@ -8228,7 +8228,7 @@ loongarch_get_separate_components (void)
if (IMM12_OPERAND (offset))
  bitmap_set_bit (components, regno);
 
-   offset -= UNITS_PER_FPREG;
+   offset -= UNITS_PER_FP_REG;
   }
 
   /* Don't mess with the hard frame pointer.  */
@@ -8307,7 +8307,7 @@ loongarch_process_components (sbitmap components, 
loongarch_save_restore_fn fn)
if (bitmap_bit_p (components, regno))
  loongarch_save_restore_reg (mode, regno, offset, fn);
 
-   offset -= UNITS_PER_FPREG;
+   offset -= UNITS_PER_FP_REG;
   }
 }
 
diff --git a/gcc/config/loongarch/loongarch.h b/gcc/config/loongarch/loongarch.h
index bf2351f0968..888a633961d 100644
--- a/gcc/config/loongarch/loongarch.h
+++ b/gcc/config/loongarch/loongarch.h
@@ -138,19 +138,16 @@ along with GCC; see the file COPYING3.  If not see
 /* Width of a LASX vector register in bits.  */
 #define BITS_PER_LASX_REG (UNITS_PER_LASX_REG * BITS_PER_UNIT)
 
-/* For LARCH, width of a floating point register.  */
-#define UNITS_PER_FPREG (TARGET_DOUBLE_FLOAT ? 8 : 4)
-
 /* The largest size of value that can be held in floating-point
registers and moved with a single instruction.  */
 #define UNITS_PER_HWFPVALUE \
-  (TARGET_SOFT_FLOAT ? 0 : UNITS_PER_FPREG)
+  (TARGET_SOFT_FLOAT ? 0 : UNITS_PER_FP_REG)
 
 /* The largest size of value that can be held in floating-point
registers.  */
 #define UNITS_PER_FPVALUE \
   (TARGET_SOFT_FLOAT ? 0 \
-   : TARGET_SINGLE_FLOAT ? UNITS_PER_FPREG \
+   : TARGET_SINGLE_FLOAT ? UNITS_PER_FP_REG \
 : LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT)
 
 /* The number of bytes in a double.  */

[gcc r14-9736] LoongArch: Add descriptions of the compilation options.

[LuluCheng via Gcc-cvs]

https://gcc.gnu.org/g:7f424c3167b72db1ecd661ccb71559bf27cbcfc1

commit r14-9736-g7f424c3167b72db1ecd661ccb71559bf27cbcfc1
Author: Lulu Cheng 
Date:   Sat Mar 30 15:14:14 2024 +0800

LoongArch: Add descriptions of the compilation options.

Add descriptions for the compilation options '-mfrecipe' '-mdiv32'
'-mlam-bh' '-mlamcas' and '-mld-seq-sa'.

gcc/ChangeLog:

* doc/invoke.texi: Add descriptions for the compilation
options.

Diff:
---
 gcc/doc/invoke.texi | 45 +++--
 1 file changed, 43 insertions(+), 2 deletions(-)

diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index c584664e168..942103c23f5 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -1058,8 +1058,9 @@ Objective-C and Objective-C++ Dialects}.
 -mmax-inline-memcpy-size=@var{n}
 -mexplicit-relocs=@var{style} -mexplicit-relocs -mno-explicit-relocs
 -mdirect-extern-access -mno-direct-extern-access
--mcmodel=@var{code-model} -mrelax -mpass-mrelax-to-as}
--mrecip  -mrecip=@var{opt}
+-mcmodel=@var{code-model} -mrelax -mpass-mrelax-to-as
+-mrecip  -mrecip=@var{opt} -mfrecipe -mno-frecipe -mdiv32 -mno-div32
+-mlam-bh -mno-lam-bh -mlamcas -mno-lamcas -mld-seq-sa -mno-ld-seq-sa}
 
 @emph{M32R/D Options}
 @gccoptlist{-m32r2  -m32rx  -m32r
@@ -27095,6 +27096,46 @@ Enable the approximation for vectorized reciprocal 
square root.
 So, for example, @option{-mrecip=all,!sqrt} enables
 all of the reciprocal approximations, except for scalar square root.
 
+@opindex mfrecipe
+@opindex mno-frecipe
+@item -mfrecipe
+@itemx -mno-frecipe
+Use (do not use) @code{frecipe.@{s/d@}} and @code{frsqrte.@{s/d@}}
+instructions.  When build with @option{-march=la664}, it is enabled by default.
+The default is @option{-mno-frecipe}.
+
+@opindex mdiv32
+@opindex mno-div32
+@item -mdiv32
+@itemx -mno-div32
+Use (do not use) @code{div.w[u]} and @code{mod.w[u]} instructions with input
+not sign-extended.  When build with @option{-march=la664}, it is enabled by
+default.  The default is @option{-mno-div32}.
+
+@opindex mlam-bh
+@opindex mno-lam-bh
+@item -mlam-bh
+@itemx -mno-lam-bh
+Use (do not use) @code{am@{swap/add@}[_db].@{b/h@}} instructions.  When build
+with @option{-march=la664}, it is enabled by default.  The default is
+@option{-mno-lam-bh}.
+
+@opindex mlamcas
+@opindex mno-lamcas
+@item -mlamcas
+@itemx -mno-lamcas
+Use (do not use) @code{amcas[_db].@{b/h/w/d@}} instructions.  When build with
+@option{-march=la664}, it is enabled by default.  The default is
+@option{-mno-lamcas}.
+
+@opindex mld-seq-sa
+@opindex mno-ld-seq-sa
+@item -mld-seq-sa
+@itemx -mno-ld-seq-sa
+Whether a load-load barrier (@code{dbar 0x700}) is needed.  When build with
+@option{-march=la664}, it is enabled by default.  The default is
+@option{-mno-ld-seq-sa}, the load-load barrier is needed.
+
 @item loongarch-vect-unroll-limit
 The vectorizer will use available tuning information to determine whether it
 would be beneficial to unroll the main vectorized loop and by how much.  This

[gcc r14-9737] LoongArch: Split loongarch_option_override_internal into smaller procedures

[LuluCheng via Gcc-cvs]

https://gcc.gnu.org/g:d28ea8e5a70474cf9d28bf0c008092c936ad1358

commit r14-9737-gd28ea8e5a70474cf9d28bf0c008092c936ad1358
Author: Yang Yujie 
Date:   Sat Mar 30 16:43:14 2024 +0800

LoongArch: Split loongarch_option_override_internal into smaller procedures

gcc/ChangeLog:

* config/loongarch/genopts/loongarch.opt.in: Mark -m[no-]recip as
aliases to -mrecip={all,none}, respectively.
* config/loongarch/loongarch.opt: Regenerate.
* config/loongarch/loongarch-def.h (ABI_FPU_64): Rename to...
(ABI_FPU64_P): ...this.
(ABI_FPU_32): Rename to...
(ABI_FPU32_P): ...this.
(ABI_FPU_NONE): Rename to...
(ABI_NOFPU_P): ...this.
(ABI_LP64_P): Define.
* config/loongarch/loongarch.cc 
(loongarch_init_print_operand_punct):
Merged into loongarch_global_init.
(loongarch_cpu_option_override): Renamed to
loongarch_target_option_override.
(loongarch_option_override_internal): Move the work after
loongarch_config_target into loongarch_target_option_override.
(loongarch_global_init): Define.
(INIT_TARGET_FLAG): Move to loongarch-opts.cc.
(loongarch_option_override): Call loongarch_global_init
separately.
* config/loongarch/loongarch-opts.cc 
(loongarch_parse_mrecip_scheme):
Split the parsing of -mrecip= from
loongarch_option_override_internal.
(loongarch_generate_mrecip_scheme): Define. Split from
loongarch_option_override_internal.
(loongarch_target_option_override): Define. Renamed from
loongarch_cpu_option_override.
(loongarch_init_misc_options): Define. Split from
loongarch_option_override_internal.
(INIT_TARGET_FLAG): Move from loongarch.cc.
* config/loongarch/loongarch-opts.h 
(loongarch_target_option_override):
New prototype.
(loongarch_parse_mrecip_scheme): New prototype.
(loongarch_init_misc_options): New prototype.
(TARGET_ABI_LP64): Simplify with ABI_LP64_P.
* config/loongarch/loongarch.h (TARGET_RECIP_DIV): Simplify.
Do not reference specific CPU architecture (LA664).
(TARGET_RECIP_SQRT): Same.
(TARGET_RECIP_RSQRT): Same.
(TARGET_RECIP_VEC_DIV): Same.
(TARGET_RECIP_VEC_SQRT): Same.
(TARGET_RECIP_VEC_RSQRT): Same.

Diff:
---
 gcc/config/loongarch/genopts/loongarch.opt.in |   8 +-
 gcc/config/loongarch/loongarch-def.h  |  11 +-
 gcc/config/loongarch/loongarch-opts.cc| 253 ++
 gcc/config/loongarch/loongarch-opts.h |  27 ++-
 gcc/config/loongarch/loongarch.cc | 253 --
 gcc/config/loongarch/loongarch.h  |  18 +-
 gcc/config/loongarch/loongarch.opt|   8 +-
 7 files changed, 342 insertions(+), 236 deletions(-)

diff --git a/gcc/config/loongarch/genopts/loongarch.opt.in 
b/gcc/config/loongarch/genopts/loongarch.opt.in
index 02f918053f5..a77893d31d9 100644
--- a/gcc/config/loongarch/genopts/loongarch.opt.in
+++ b/gcc/config/loongarch/genopts/loongarch.opt.in
@@ -197,14 +197,14 @@ mexplicit-relocs
 Target Alias(mexplicit-relocs=, always, none)
 Use %reloc() assembly operators (for backward compatibility).
 
-mrecip
-Target RejectNegative Var(la_recip) Save
-Generate approximate reciprocal divide and square root for better throughput.
-
 mrecip=
 Target RejectNegative Joined Var(la_recip_name) Save
 Control generation of reciprocal estimates.
 
+mrecip
+Target Alias(mrecip=, all, none)
+Generate approximate reciprocal divide and square root for better throughput.
+
 ; The code model option names for -mcmodel.
 Enum
 Name(cmodel) Type(int)
diff --git a/gcc/config/loongarch/loongarch-def.h 
b/gcc/config/loongarch/loongarch-def.h
index 2dbf006d013..0cbf9476690 100644
--- a/gcc/config/loongarch/loongarch-def.h
+++ b/gcc/config/loongarch/loongarch-def.h
@@ -90,11 +90,16 @@ extern loongarch_def_array
 
 #define TO_LP64_ABI_BASE(C) (C)
 
-#define ABI_FPU_64(abi_base) \
+#define ABI_LP64_P(abi_base) \
+  (abi_base == ABI_BASE_LP64D \
+   || abi_base == ABI_BASE_LP64F \
+   || abi_base == ABI_BASE_LP64S)
+
+#define ABI_FPU64_P(abi_base) \
   (abi_base == ABI_BASE_LP64D)
-#define ABI_FPU_32(abi_base) \
+#define ABI_FPU32_P(abi_base) \
   (abi_base == ABI_BASE_LP64F)
-#define ABI_FPU_NONE(abi_base) \
+#define ABI_NOFPU_P(abi_base) \
   (abi_base == ABI_BASE_LP64S)
 
 
diff --git a/gcc/config/loongarch/loongarch-opts.cc 
b/gcc/config/loongarch/loongarch-opts.cc
index 627f9148adf..e600f08f03b 100644
--- a/gcc/config/loongarch/loongarch-opts.cc
+++ b/gcc/config/loongarch/loongarch-opts.cc
@@ -25,6 +25,7 @@ along with GCC; see the file COPYING3.  If not see
 #include "coretypes.h"
 #include "tm.h"
 #include "obstack.h"
+#include

[gcc r13-8545] LoongArch: gcc13: Implement option save/restore.

[LuluCheng via Gcc-cvs]

https://gcc.gnu.org/g:4736b317047ae6b04f7609843f21cb68fef6a0c1

commit r13-8545-g4736b317047ae6b04f7609843f21cb68fef6a0c1
Author: Lulu Cheng 
Date:   Fri Mar 15 16:23:05 2024 +0800

LoongArch: gcc13: Implement option save/restore.

LTO option streaming and target attributes both require per-function
target configuration, which is achieved via option save/restore.

We implement TARGET_OPTION_{SAVE,RESTORE} to switch the la_target
context in addition to other automatically maintained option states
(via the "Save" option property in the .opt files).

PR target/113233

gcc/ChangeLog:

* config/loongarch/genopts/loongarch.opt.in: Mark options with
the "Save" property.
* config/loongarch/loongarch-opts.cc
(loongarch_update_gcc_opt_status): Update the value of the
la_target to global_options.
* config/loongarch/loongarch-opts.h
(loongarch_update_gcc_opt_status): Add a function declaration.
* config/loongarch/loongarch.cc
(loongarch_option_override_internal): Call the function
loongarch_update_gcc_opt_status.
(loongarch_option_save): New functions.
(loongarch_option_restore): Likewise.
(TARGET_OPTION_SAVE): Define macro.
(TARGET_OPTION_RESTORE): Likewise.
* config/loongarch/loongarch.opt: Regenerate.

(cherry picked from commit ea2a9c76a1dcffbbec6e53655bef9236d3a8e691)

Diff:
---
 gcc/config/loongarch/genopts/loongarch.opt.in | 24 +--
 gcc/config/loongarch/loongarch-opts.cc| 22 +
 gcc/config/loongarch/loongarch-opts.h |  6 +
 gcc/config/loongarch/loongarch.cc | 34 +--
 gcc/config/loongarch/loongarch.opt| 24 +--
 5 files changed, 84 insertions(+), 26 deletions(-)

diff --git a/gcc/config/loongarch/genopts/loongarch.opt.in 
b/gcc/config/loongarch/genopts/loongarch.opt.in
index 76acd35d39c..aea4f2a4f61 100644
--- a/gcc/config/loongarch/genopts/loongarch.opt.in
+++ b/gcc/config/loongarch/genopts/loongarch.opt.in
@@ -58,7 +58,7 @@ EnumValue
 Enum(isa_ext_fpu) String(@@STR_ISA_EXT_FPU64@@) Value(ISA_EXT_FPU64)
 
 m@@OPTSTR_ISA_EXT_FPU@@=
-Target RejectNegative Joined ToLower Enum(isa_ext_fpu) Var(la_opt_fpu) 
Init(M_OPTION_NOT_SEEN)
+Target RejectNegative Joined ToLower Enum(isa_ext_fpu) Var(la_opt_fpu) 
Init(M_OPTION_NOT_SEEN) Save
 -m@@OPTSTR_ISA_EXT_FPU@@=FPU   Generate code for the given FPU.
 
 m@@OPTSTR_ISA_EXT_FPU@@=@@STR_ISA_EXT_FPU0@@
@@ -92,11 +92,11 @@ EnumValue
 Enum(cpu_type) String(@@STR_CPU_LA464@@) Value(CPU_LA464)
 
 m@@OPTSTR_ARCH@@=
-Target RejectNegative Joined Enum(cpu_type) Var(la_opt_cpu_arch) 
Init(M_OPTION_NOT_SEEN)
+Target RejectNegative Joined Enum(cpu_type) Var(la_opt_cpu_arch) 
Init(M_OPTION_NOT_SEEN) Save
 -m@@OPTSTR_ARCH@@=PROCESSORGenerate code for the given PROCESSOR ISA.
 
 m@@OPTSTR_TUNE@@=
-Target RejectNegative Joined Enum(cpu_type) Var(la_opt_cpu_tune) 
Init(M_OPTION_NOT_SEEN)
+Target RejectNegative Joined Enum(cpu_type) Var(la_opt_cpu_tune) 
Init(M_OPTION_NOT_SEEN) Save
 -m@@OPTSTR_TUNE@@=PROCESSORGenerate optimized code for PROCESSOR.
 
 
@@ -127,31 +127,31 @@ int la_opt_abi_ext = M_OPTION_NOT_SEEN
 
 
 mbranch-cost=
-Target RejectNegative Joined UInteger Var(loongarch_branch_cost)
+Target RejectNegative Joined UInteger Var(loongarch_branch_cost) Save
 -mbranch-cost=COST Set the cost of branches to roughly COST instructions.
 
 mcheck-zero-division
-Target Mask(CHECK_ZERO_DIV)
+Target Mask(CHECK_ZERO_DIV) Save
 Trap on integer divide by zero.
 
 mcond-move-int
-Target Var(TARGET_COND_MOVE_INT) Init(1)
+Target Var(TARGET_COND_MOVE_INT) Init(1) Save
 Conditional moves for integral are enabled.
 
 mcond-move-float
-Target Var(TARGET_COND_MOVE_FLOAT) Init(1)
+Target Var(TARGET_COND_MOVE_FLOAT) Init(1) Save
 Conditional moves for float are enabled.
 
 mmemcpy
-Target Mask(MEMCPY)
+Target Mask(MEMCPY) Save
 Prevent optimizing block moves, which is also the default behavior of -Os.
 
 mstrict-align
-Target Var(TARGET_STRICT_ALIGN) Init(0)
+Target Var(TARGET_STRICT_ALIGN) Init(0) Save
 Do not generate unaligned memory accesses.
 
 mmax-inline-memcpy-size=
-Target Joined RejectNegative UInteger Var(loongarch_max_inline_memcpy_size) 
Init(1024)
+Target Joined RejectNegative UInteger Var(loongarch_max_inline_memcpy_size) 
Init(1024) Save
 -mmax-inline-memcpy-size=SIZE  Set the max size of memcpy to inline, default 
is 1024.
 
 mexplicit-relocs
@@ -182,11 +182,11 @@ EnumValue
 Enum(cmodel) String(@@STR_CMODEL_EXTREME@@) Value(CMODEL_EXTREME)
 
 mcmodel=
-Target RejectNegative Joined Enum(cmodel) Var(la_opt_cmodel) 
Init(CMODEL_NORMAL)
+Target RejectNegative Joined Enum(cmodel) Var(la_opt_cmodel) 
Init(CMODEL_NORMAL) Save
 Specify the code model.
 
 mdirect-extern-access
-Target Var(TARGET_DIRECT_EXTERN_ACCESS) Init(0)
+Targ

[gcc r12-10303] LoongArch: gcc12: Implement option save/restore.

[LuluCheng via Gcc-cvs]

https://gcc.gnu.org/g:bf0b32d7929f8b4b15b21658d572b89ded03d8f8

commit r12-10303-gbf0b32d7929f8b4b15b21658d572b89ded03d8f8
Author: Lulu Cheng 
Date:   Fri Mar 15 16:41:20 2024 +0800

LoongArch: gcc12: Implement option save/restore.

LTO option streaming and target attributes both require per-function
target configuration, which is achieved via option save/restore.

We implement TARGET_OPTION_{SAVE,RESTORE} to switch the la_target
context in addition to other automatically maintained option states
(via the "Save" option property in the .opt files).

PR target/113233

gcc/ChangeLog:

* config/loongarch/genopts/loongarch.opt.in: Mark options with
the "Save" property.
* config/loongarch/loongarch-opts.cc
(loongarch_update_gcc_opt_status): Update the value of the
la_target to global_options.
* config/loongarch/loongarch-opts.h
(loongarch_update_gcc_opt_status): Add a function declaration.
* config/loongarch/loongarch.cc
(loongarch_option_override_internal): Call the function
loongarch_update_gcc_opt_status.
(loongarch_option_save): New functions.
(loongarch_option_restore): Likewise.
(TARGET_OPTION_SAVE): Define macro.
(TARGET_OPTION_RESTORE): Likewise.
* config/loongarch/loongarch.opt: Regenerate.

(cherry picked from commit ea2a9c76a1dcffbbec6e53655bef9236d3a8e691)

Diff:
---
 gcc/config/loongarch/genopts/loongarch.opt.in | 22 -
 gcc/config/loongarch/loongarch-opts.cc| 22 +
 gcc/config/loongarch/loongarch-opts.h |  6 +
 gcc/config/loongarch/loongarch.cc | 34 +--
 gcc/config/loongarch/loongarch.opt| 22 -
 5 files changed, 82 insertions(+), 24 deletions(-)

diff --git a/gcc/config/loongarch/genopts/loongarch.opt.in 
b/gcc/config/loongarch/genopts/loongarch.opt.in
index 420a3941b3b..a3107cb2294 100644
--- a/gcc/config/loongarch/genopts/loongarch.opt.in
+++ b/gcc/config/loongarch/genopts/loongarch.opt.in
@@ -58,7 +58,7 @@ EnumValue
 Enum(isa_ext_fpu) String(@@STR_ISA_EXT_FPU64@@) Value(ISA_EXT_FPU64)
 
 m@@OPTSTR_ISA_EXT_FPU@@=
-Target RejectNegative Joined ToLower Enum(isa_ext_fpu) Var(la_opt_fpu) 
Init(M_OPTION_NOT_SEEN)
+Target RejectNegative Joined ToLower Enum(isa_ext_fpu) Var(la_opt_fpu) 
Init(M_OPTION_NOT_SEEN) Save
 -m@@OPTSTR_ISA_EXT_FPU@@=FPU   Generate code for the given FPU.
 
 m@@OPTSTR_ISA_EXT_FPU@@=@@STR_ISA_EXT_FPU0@@
@@ -92,11 +92,11 @@ EnumValue
 Enum(cpu_type) String(@@STR_CPU_LA464@@) Value(CPU_LA464)
 
 m@@OPTSTR_ARCH@@=
-Target RejectNegative Joined Enum(cpu_type) Var(la_opt_cpu_arch) 
Init(M_OPTION_NOT_SEEN)
+Target RejectNegative Joined Enum(cpu_type) Var(la_opt_cpu_arch) 
Init(M_OPTION_NOT_SEEN) Save
 -m@@OPTSTR_ARCH@@=PROCESSORGenerate code for the given PROCESSOR ISA.
 
 m@@OPTSTR_TUNE@@=
-Target RejectNegative Joined Enum(cpu_type) Var(la_opt_cpu_tune) 
Init(M_OPTION_NOT_SEEN)
+Target RejectNegative Joined Enum(cpu_type) Var(la_opt_cpu_tune) 
Init(M_OPTION_NOT_SEEN) Save
 -m@@OPTSTR_TUNE@@=PROCESSORGenerate optimized code for PROCESSOR.
 
 
@@ -127,31 +127,31 @@ int la_opt_abi_ext = M_OPTION_NOT_SEEN
 
 
 mbranch-cost=
-Target RejectNegative Joined UInteger Var(loongarch_branch_cost)
+Target RejectNegative Joined UInteger Var(loongarch_branch_cost) Save
 -mbranch-cost=COST Set the cost of branches to roughly COST instructions.
 
 mcheck-zero-division
-Target Mask(CHECK_ZERO_DIV)
+Target Mask(CHECK_ZERO_DIV) Save
 Trap on integer divide by zero.
 
 mcond-move-int
-Target Var(TARGET_COND_MOVE_INT) Init(1)
+Target Var(TARGET_COND_MOVE_INT) Init(1) Save
 Conditional moves for integral are enabled.
 
 mcond-move-float
-Target Var(TARGET_COND_MOVE_FLOAT) Init(1)
+Target Var(TARGET_COND_MOVE_FLOAT) Init(1) Save
 Conditional moves for float are enabled.
 
 mmemcpy
-Target Mask(MEMCPY)
+Target Mask(MEMCPY) Save
 Prevent optimizing block moves, which is also the default behavior of -Os.
 
 mstrict-align
-Target Var(TARGET_STRICT_ALIGN) Init(0)
+Target Var(TARGET_STRICT_ALIGN) Init(0) Save
 Do not generate unaligned memory accesses.
 
 mmax-inline-memcpy-size=
-Target Joined RejectNegative UInteger Var(loongarch_max_inline_memcpy_size) 
Init(1024)
+Target Joined RejectNegative UInteger Var(loongarch_max_inline_memcpy_size) 
Init(1024) Save
 -mmax-inline-memcpy-size=SIZE  Set the max size of memcpy to inline, default 
is 1024.
 
 ; The code model option names for -mcmodel.
@@ -175,7 +175,7 @@ EnumValue
 Enum(cmodel) String(@@STR_CMODEL_EXTREME@@) Value(CMODEL_EXTREME)
 
 mcmodel=
-Target RejectNegative Joined Enum(cmodel) Var(la_opt_cmodel) 
Init(CMODEL_NORMAL)
+Target RejectNegative Joined Enum(cmodel) Var(la_opt_cmodel) 
Init(CMODEL_NORMAL) Save
 Specify the code model.
 
 mrelax
diff --git a/gcc/config/loongarch/loongarch-opt

[gcc r14-9741] LoongArch: Regenerate loongarch.opt.urls.

[LuluCheng via Gcc-cvs]

https://gcc.gnu.org/g:6f9ba3ea55477cf1bd3d37e40ad116150c06a75e

commit r14-9741-g6f9ba3ea55477cf1bd3d37e40ad116150c06a75e
Author: Lulu Cheng 
Date:   Mon Apr 1 11:00:21 2024 +0800

LoongArch: Regenerate loongarch.opt.urls.

Fixes: d28ea8e5a704 ("LoongArch: Split loongarch_option_override_internal
  into smaller procedures")

gcc/ChangeLog:

* config/loongarch/loongarch.opt.urls: Regenerate.

Diff:
---
 gcc/config/loongarch/loongarch.opt.urls | 19 +--
 1 file changed, 17 insertions(+), 2 deletions(-)

diff --git a/gcc/config/loongarch/loongarch.opt.urls 
b/gcc/config/loongarch/loongarch.opt.urls
index c78bbfea2da..8e16304b66a 100644
--- a/gcc/config/loongarch/loongarch.opt.urls
+++ b/gcc/config/loongarch/loongarch.opt.urls
@@ -51,10 +51,10 @@ 
UrlSuffix(gcc/LoongArch-Options.html#index-mexplicit-relocs-1)
 mexplicit-relocs
 UrlSuffix(gcc/LoongArch-Options.html#index-mexplicit-relocs-1)
 
-mrecip
+mrecip=
 UrlSuffix(gcc/LoongArch-Options.html#index-mrecip)
 
-mrecip=
+mrecip
 UrlSuffix(gcc/LoongArch-Options.html#index-mrecip)
 
 ; skipping UrlSuffix for 'mcmodel=' due to finding no URLs
@@ -64,3 +64,18 @@ 
UrlSuffix(gcc/LoongArch-Options.html#index-mdirect-extern-access)
 
 ; skipping UrlSuffix for 'mrelax' due to finding no URLs
 
+mfrecipe
+UrlSuffix(gcc/LoongArch-Options.html#index-mfrecipe)
+
+mdiv32
+UrlSuffix(gcc/LoongArch-Options.html#index-mdiv32)
+
+mlam-bh
+UrlSuffix(gcc/LoongArch-Options.html#index-mlam-bh)
+
+mlamcas
+UrlSuffix(gcc/LoongArch-Options.html#index-mlamcas)
+
+mld-seq-sa
+UrlSuffix(gcc/LoongArch-Options.html#index-mld-seq-sa)
+

[gcc r14-9742] LoongArch: Add support for TLS descriptors.

[LuluCheng via Gcc-cvs]

https://gcc.gnu.org/g:b253b4695ddac43301bb572895095b9569165ff4

commit r14-9742-gb253b4695ddac43301bb572895095b9569165ff4
Author: mengqinggang 
Date:   Tue Apr 2 09:57:20 2024 +0800

LoongArch: Add support for TLS descriptors.

Add support for TLS descriptors on normal code model and extreme
code model.

Normal code model instruction sequence:
  -mno-explicit-relocs:
la.tls.desc $r4, s
add.d   $r12, $r4, $r2
  -mexplicit-relocs:
pcalau12i   $r4,%desc_pc_hi20(s)
addi.d  $r4,$r4,%desc_pc_lo12(s)
ld.d$r1,$r4,%desc_ld(s)
jirl$r1,$r1,%desc_call(s)
add.d   $r12, $r4, $r2

Extreme code model instruction sequence:
  -mno-explicit-relocs:
la.tls.desc $r4, $r12, s
add.d   $r12, $r4, $r2
  -mexplicit-relocs:
pcalau12i   $r4,%desc_pc_hi20(s)
addi.d  $r12,$r0,%desc_pc_lo12(s)
lu32i.d $r12,%desc64_pc_lo20(s)
lu52i.d $r12,$r12,%desc64_pc_hi12(s)
add.d   $r4,$r4,$r12
ld.d$r1,$r4,%desc_ld(s)
jirl$r1,$r1,%desc_call(s)
add.d   $r12, $r4, $r2

The default is still traditional TLS model, but can be configured with
--with-tls={trad,desc}. The default can change to TLS descriptors once
libc and LLVM support this.

gcc/ChangeLog:

* config.gcc: Add --with-tls option to change TLS flavor.
* config/loongarch/genopts/loongarch.opt.in: Add -mtls-dialect to
configure TLS flavor.
* config/loongarch/loongarch-def.h (struct loongarch_target): Add
tls_dialect.
* config/loongarch/loongarch-driver.cc (la_driver_init): Add tls
flavor.
* config/loongarch/loongarch-opts.cc (loongarch_init_target): Add
tls_dialect.
(loongarch_config_target): Ditto.
(loongarch_update_gcc_opt_status): Ditto.
* config/loongarch/loongarch-opts.h (loongarch_init_target): Ditto.
(TARGET_TLS_DESC): New define.
* config/loongarch/loongarch.cc (loongarch_symbol_insns): Add TLS
DESC instructions sequence length.
(loongarch_legitimize_tls_address): New TLS DESC instruction 
sequence.
(loongarch_option_override_internal): Add la_opt_tls_dialect.
(loongarch_option_restore): Add la_target.tls_dialect.
* config/loongarch/loongarch.md (@got_load_tls_desc): Normal
code model for TLS DESC.
(got_load_tls_desc_off64): Extreme cmode model for TLS DESC.
* config/loongarch/loongarch.opt: Regenerate.
* config/loongarch/loongarch.opt.urls: Ditto.
* doc/invoke.texi: Add a description of the compilation option
'-mtls-dialect={trad,desc}'.

gcc/testsuite/ChangeLog:

* gcc.target/loongarch/cmodel-extreme-1.c: Add -mtls-dialect=trad.
* gcc.target/loongarch/cmodel-extreme-2.c: Ditto.
* gcc.target/loongarch/explicit-relocs-auto-tls-ld-gd.c: Ditto.
* 
gcc.target/loongarch/explicit-relocs-medium-call36-auto-tls-ld-gd.c:
Ditto.
* gcc.target/loongarch/func-call-medium-1.c: Ditto.
* gcc.target/loongarch/func-call-medium-2.c: Ditto.
* gcc.target/loongarch/func-call-medium-3.c: Ditto.
* gcc.target/loongarch/func-call-medium-4.c: Ditto.
* gcc.target/loongarch/tls-extreme-macro.c: Ditto.
* gcc.target/loongarch/tls-gd-noplt.c: Ditto.
* gcc.target/loongarch/explicit-relocs-auto-extreme-tls-desc.c: New 
test.
* gcc.target/loongarch/explicit-relocs-auto-tls-desc.c: New test.
* gcc.target/loongarch/explicit-relocs-extreme-tls-desc.c: New test.
* gcc.target/loongarch/explicit-relocs-tls-desc.c: New test.

Co-authored-by: Lulu Cheng 
Co-authored-by: Xi Ruoyao 

Diff:
---
 gcc/config.gcc | 19 +-
 gcc/config/loongarch/genopts/loongarch.opt.in  | 14 +
 gcc/config/loongarch/loongarch-def.h   |  7 +++
 gcc/config/loongarch/loongarch-driver.cc   |  2 +-
 gcc/config/loongarch/loongarch-opts.cc | 12 +++-
 gcc/config/loongarch/loongarch-opts.h  |  3 +
 gcc/config/loongarch/loongarch.cc  | 45 ++
 gcc/config/loongarch/loongarch.md  | 68 ++
 gcc/config/loongarch/loongarch.opt | 14 +
 gcc/config/loongarch/loongarch.opt.urls|  3 +
 gcc/doc/invoke.texi| 16 -
 .../gcc.target/loongarch/cmodel-extreme-1.c|  2 +-
 .../gcc.target/loongarch/cmodel-extreme-2.c|  2 +-
 .../explicit-relocs-auto-extreme-tls-desc.c| 10 
 .../loongarch/explicit-relocs-auto-tls-desc.c  | 10 
 .../loongarch/explicit-relocs-auto-t

[gcc r14-9743] LoongArch: Fix missing plugin header

[LuluCheng via Gcc-cvs]

https://gcc.gnu.org/g:078f4a958cd2267d5b1dccda838785836ac19b79

commit r14-9743-g078f4a958cd2267d5b1dccda838785836ac19b79
Author: Yang Yujie 
Date:   Tue Apr 2 09:20:32 2024 +0800

LoongArch: Fix missing plugin header

gcc/ChangeLog:

* config/loongarch/t-loongarch: Add loongarch-def-arrays.h
to OPTION_H_EXTRA.

Diff:
---
 gcc/config/loongarch/t-loongarch | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/gcc/config/loongarch/t-loongarch b/gcc/config/loongarch/t-loongarch
index 3dd7c4b031e..acf5da95310 100644
--- a/gcc/config/loongarch/t-loongarch
+++ b/gcc/config/loongarch/t-loongarch
@@ -18,8 +18,9 @@
 
 
 GTM_H += loongarch-multilib.h
-OPTIONS_H_EXTRA += $(srcdir)/config/loongarch/loongarch-def.h  \
-  $(srcdir)/config/loongarch/loongarch-tune.h  \
+OPTIONS_H_EXTRA += $(srcdir)/config/loongarch/loongarch-def.h  \
+  $(srcdir)/config/loongarch/loongarch-def-array.h \
+  $(srcdir)/config/loongarch/loongarch-tune.h  \
   $(srcdir)/config/loongarch/loongarch-cpucfg-map.h
 
 # Canonical target triplet from config.gcc

[gcc r14-9766] LoongArch: Remove unused code.

[LuluCheng via Gcc-cvs]

https://gcc.gnu.org/g:8677182f32234786fccce25583232ec5181dde75

commit r14-9766-g8677182f32234786fccce25583232ec5181dde75
Author: Jiahao Xu 
Date:   Wed Apr 3 09:38:23 2024 +0800

LoongArch: Remove unused code.

gcc/ChangeLog:

* config/loongarch/lasx.md: Remove unused code.
* config/loongarch/loongarch-protos.h
(loongarch_split_lsx_copy_d): Remove.
(loongarch_split_lsx_insert_d): Ditto.
(loongarch_split_lsx_fill_d): Ditto.
* config/loongarch/loongarch.cc
(loongarch_split_lsx_copy_d): Ditto.
(loongarch_split_lsx_insert_d): Ditto.
(loongarch_split_lsx_fill_d): Ditto.
* config/loongarch/lsx.md (lsx_vpickve2gr_du): Remove splitter.
(lsx_vpickve2gr_): Ditto.
(abs2): Remove expander.
(vabs2): Rename 2 abs2.

gcc/testsuite/ChangeLog:

* gcc.target/loongarch/vector/lsx/lsx-abs.c: New test.

Diff:
---
 gcc/config/loongarch/lasx.md   | 12 +--
 gcc/config/loongarch/loongarch-protos.h|  3 -
 gcc/config/loongarch/loongarch.cc  | 76 --
 gcc/config/loongarch/lsx.md| 89 ++
 .../gcc.target/loongarch/vector/lsx/lsx-abs.c  | 26 +++
 5 files changed, 35 insertions(+), 171 deletions(-)

diff --git a/gcc/config/loongarch/lasx.md b/gcc/config/loongarch/lasx.md
index 2fa5e46c8e8..7bd61f8ed5b 100644
--- a/gcc/config/loongarch/lasx.md
+++ b/gcc/config/loongarch/lasx.md
@@ -572,12 +572,7 @@
  (match_operand 3 "const__operand" "")))]
   "ISA_HAS_LASX"
 {
-#if 0
-  if (!TARGET_64BIT && (mode == V4DImode || mode == V4DFmode))
-return "#";
-  else
-#endif
-return "xvinsgr2vr.\t%u0,%z1,%y3";
+  return "xvinsgr2vr.\t%u0,%z1,%y3";
 }
   [(set_attr "type" "simd_insert")
(set_attr "mode" "")])
@@ -1446,10 +1441,7 @@
   if (which_alternative == 1)
 return "xvldi.b\t%u0,0" ;
 
-  if (!TARGET_64BIT && (mode == V2DImode || mode == V2DFmode))
-return "#";
-  else
-return "xvreplgr2vr.\t%u0,%z1";
+  return "xvreplgr2vr.\t%u0,%z1";
 }
   [(set_attr "type" "simd_fill")
(set_attr "mode" "")
diff --git a/gcc/config/loongarch/loongarch-protos.h 
b/gcc/config/loongarch/loongarch-protos.h
index e3ed2b912a5..e238d795a73 100644
--- a/gcc/config/loongarch/loongarch-protos.h
+++ b/gcc/config/loongarch/loongarch-protos.h
@@ -89,9 +89,6 @@ extern void loongarch_split_128bit_move (rtx, rtx);
 extern bool loongarch_split_128bit_move_p (rtx, rtx);
 extern void loongarch_split_256bit_move (rtx, rtx);
 extern bool loongarch_split_256bit_move_p (rtx, rtx);
-extern void loongarch_split_lsx_copy_d (rtx, rtx, rtx, rtx (*)(rtx, rtx, rtx));
-extern void loongarch_split_lsx_insert_d (rtx, rtx, rtx, rtx);
-extern void loongarch_split_lsx_fill_d (rtx, rtx);
 extern const char *loongarch_output_move (rtx, rtx);
 #ifdef RTX_CODE
 extern void loongarch_expand_scc (rtx *);
diff --git a/gcc/config/loongarch/loongarch.cc 
b/gcc/config/loongarch/loongarch.cc
index cbc91c94d9d..c90b701a533 100644
--- a/gcc/config/loongarch/loongarch.cc
+++ b/gcc/config/loongarch/loongarch.cc
@@ -4775,82 +4775,6 @@ loongarch_split_256bit_move (rtx dest, rtx src)
 }
 }
 
-
-/* Split a COPY_S.D with operands DEST, SRC and INDEX.  GEN is a function
-   used to generate subregs.  */
-
-void
-loongarch_split_lsx_copy_d (rtx dest, rtx src, rtx index,
-   rtx (*gen_fn)(rtx, rtx, rtx))
-{
-  gcc_assert ((GET_MODE (src) == V2DImode && GET_MODE (dest) == DImode)
- || (GET_MODE (src) == V2DFmode && GET_MODE (dest) == DFmode));
-
-  /* Note that low is always from the lower index, and high is always
- from the higher index.  */
-  rtx low = loongarch_subword (dest, false);
-  rtx high = loongarch_subword (dest, true);
-  rtx new_src = simplify_gen_subreg (V4SImode, src, GET_MODE (src), 0);
-
-  emit_insn (gen_fn (low, new_src, GEN_INT (INTVAL (index) * 2)));
-  emit_insn (gen_fn (high, new_src, GEN_INT (INTVAL (index) * 2 + 1)));
-}
-
-/* Split a INSERT.D with operand DEST, SRC1.INDEX and SRC2.  */
-
-void
-loongarch_split_lsx_insert_d (rtx dest, rtx src1, rtx index, rtx src2)
-{
-  int i;
-  gcc_assert (GET_MODE (dest) == GET_MODE (src1));
-  gcc_assert ((GET_MODE (dest) == V2DImode
-  && (GET_MODE (src2) == DImode || src2 == const0_rtx))
- || (GET_MODE (dest) == V2DFmode && GET_MODE (src2) == DFmode));
-
-  /* Note that low is always from the lower index, and high is always
- from the higher index.  */
-  rtx low = loongarch_subword (src2, false);
-  rtx high = loongarch_subword (src2, true);
-  rtx new_dest = simplify_gen_subreg (V4SImode, dest, GET_MODE (dest), 0);
-  rtx new_src1 = simplify_gen_subreg (V4SImode, src1, GET_MODE (src1), 0);
-  i = exact_log2 (INTVAL (index));
-  gcc_assert (i != -1);
-
-  emit_insn (gen_lsx_vinsgr2vr_w (new_dest, low, new_src1,
- 

[gcc r14-9824] LoongArch: Set default alignment for functions jumps and loops [PR112919].

[LuluCheng via Gcc-cvs]

https://gcc.gnu.org/g:8f0ff6b998748f3581e0f06e3108193866b1209d

commit r14-9824-g8f0ff6b998748f3581e0f06e3108193866b1209d
Author: Lulu Cheng 
Date:   Tue Apr 2 14:29:08 2024 +0800

LoongArch: Set default alignment for functions jumps and loops [PR112919].

Xi Ruoyao set the alignment rules under LA464 in commit r14-1839,
but the macro ASM_OUTPUT_ALIGN_WITH_NOP was removed in R14-4674,
which affected the alignment rules.

So I set different aligns on LA464 and LA664 again to test the
performance of spec2006, and modify the alignment based on the test
results.

gcc/ChangeLog:

PR target/112919
* config/loongarch/loongarch-def.cc (la664_align): Newly defined
function that sets alignment rules under the LA664 
microarchitecture.
* config/loongarch/loongarch-opts.cc
(loongarch_target_option_override): If not optimizing for size, set
the default alignment to what the target wants.
* config/loongarch/loongarch-tune.h (struct loongarch_align): Add
new member variables jump and loop.

Diff:
---
 gcc/config/loongarch/loongarch-def.cc  | 11 ---
 gcc/config/loongarch/loongarch-opts.cc | 19 +--
 gcc/config/loongarch/loongarch-tune.h  | 22 +++---
 3 files changed, 36 insertions(+), 16 deletions(-)

diff --git a/gcc/config/loongarch/loongarch-def.cc 
b/gcc/config/loongarch/loongarch-def.cc
index e8c129ce643..63a8f108f4e 100644
--- a/gcc/config/loongarch/loongarch-def.cc
+++ b/gcc/config/loongarch/loongarch-def.cc
@@ -81,14 +81,19 @@ array_tune loongarch_cpu_cache =
 
 static inline loongarch_align la464_align ()
 {
-  return loongarch_align ().function_ ("32").label_ ("16");
+  return loongarch_align ().function_ ("32").loop_ ("16").jump_ ("16");
+}
+
+static inline loongarch_align la664_align ()
+{
+  return loongarch_align ().function_ ("8").loop_ ("8").jump_ ("32");
 }
 
 array_tune loongarch_cpu_align =
   array_tune ()
-.set (CPU_LOONGARCH64, la464_align ())
+.set (CPU_LOONGARCH64, la664_align ())
 .set (CPU_LA464, la464_align ())
-.set (CPU_LA664, la464_align ());
+.set (CPU_LA664, la664_align ());
 
 /* Default RTX cost initializer.  */
 loongarch_rtx_cost_data::loongarch_rtx_cost_data ()
diff --git a/gcc/config/loongarch/loongarch-opts.cc 
b/gcc/config/loongarch/loongarch-opts.cc
index 2a6fc41b247..7b21cc311a8 100644
--- a/gcc/config/loongarch/loongarch-opts.cc
+++ b/gcc/config/loongarch/loongarch-opts.cc
@@ -922,13 +922,20 @@ loongarch_target_option_override (struct loongarch_target 
*target,
 {
   loongarch_update_gcc_opt_status (target, opts, opts_set);
 
-  /* alignments */
-  if (opts->x_flag_align_functions && !opts->x_str_align_functions)
-opts->x_str_align_functions
-  = loongarch_cpu_align[target->cpu_tune].function;
+  /* If not optimizing for size, set the default
+ alignment to what the target wants.  */
+  if (!opts->x_optimize_size)
+{
+  if (opts->x_flag_align_functions && !opts->x_str_align_functions)
+   opts->x_str_align_functions
+ = loongarch_cpu_align[target->cpu_tune].function;
+
+  if (opts->x_flag_align_loops && !opts->x_str_align_loops)
+   opts->x_str_align_loops = loongarch_cpu_align[target->cpu_tune].loop;
 
-  if (opts->x_flag_align_labels && !opts->x_str_align_labels)
-opts->x_str_align_labels = loongarch_cpu_align[target->cpu_tune].label;
+  if (opts->x_flag_align_jumps && !opts->x_str_align_jumps)
+   opts->x_str_align_jumps = loongarch_cpu_align[target->cpu_tune].jump;
+}
 
   /* Set up parameters to be used in prefetching algorithm.  */
   int simultaneous_prefetches
diff --git a/gcc/config/loongarch/loongarch-tune.h 
b/gcc/config/loongarch/loongarch-tune.h
index 72b75f6de3f..cec9deb541a 100644
--- a/gcc/config/loongarch/loongarch-tune.h
+++ b/gcc/config/loongarch/loongarch-tune.h
@@ -162,14 +162,16 @@ struct loongarch_cache {
   }
 };
 
-/* Alignment for functions and labels for best performance.  For new uarchs
-   the value should be measured via benchmarking.  See the documentation for
-   -falign-functions and -falign-labels in invoke.texi for the format.  */
+/* Alignment for functions loops and jumps for best performance.  For new
+   uarchs the value should be measured via benchmarking.  See the
+   documentation for -falign-functions, -falign-loops, and -falign-jumps in
+   invoke.texi for the format.  */
 struct loongarch_align {
   const char *function;/* default value for -falign-functions */
-  const char *label;   /* default value for -falign-labels */
+  const char *loop;/* default value for -falign-loops */
+  const char *jump;/* default value for -falign-jumps */
 
-  loongarch_align () : function (nullptr), label (nullptr) {}
+  loongarch_align () : function (nullptr), loop (nullptr), jump (nullptr) {}
 
   loongarch_align function_ (const char *_function)
   {
@@ -177,9 +179,15 @@ struct lo

[gcc r14-9866] LoongArch: Enable switchable target

[LuluCheng via Gcc-cvs]

https://gcc.gnu.org/g:8657d76d583f0f87000e9003ba75922f2bbe4455

commit r14-9866-g8657d76d583f0f87000e9003ba75922f2bbe4455
Author: Yang Yujie 
Date:   Mon Apr 8 16:45:13 2024 +0800

LoongArch: Enable switchable target

This patch fixes the back-end context switching in cases where functions
should be built with their own target contexts instead of the
global one, such as LTO linking and functions with target attributes (TBD).

PR target/113233

gcc/ChangeLog:

* config/loongarch/loongarch.cc (loongarch_reg_init):
Reinitialize the loongarch_regno_mode_ok cache.
(loongarch_option_override): Same.
(loongarch_save_restore_target_globals): Restore target globals.
(loongarch_set_current_function): Restore the target contexts
for functions.
(TARGET_SET_CURRENT_FUNCTION): Define.
* config/loongarch/loongarch.h (SWITCHABLE_TARGET): Enable
switchable target context.
* config/loongarch/loongarch-builtins.cc (loongarch_init_builtins):
Initialize all builtin functions at startup.
(loongarch_expand_builtin): Turn assertion of builtin availability
into a test.

gcc/testsuite/ChangeLog:

* lib/target-supports.exp: Define condition loongarch_sx_as.
* gcc.dg/lto/pr113233_0.c: New test.

Diff:
---
 gcc/config/loongarch/loongarch-builtins.cc | 25 
 gcc/config/loongarch/loongarch.cc  | 91 --
 gcc/config/loongarch/loongarch.h   |  2 +
 gcc/testsuite/gcc.dg/lto/pr113233_0.c  | 14 +
 gcc/testsuite/lib/target-supports.exp  | 12 
 5 files changed, 127 insertions(+), 17 deletions(-)

diff --git a/gcc/config/loongarch/loongarch-builtins.cc 
b/gcc/config/loongarch/loongarch-builtins.cc
index efe7e5e5ebc..fbe46833c9b 100644
--- a/gcc/config/loongarch/loongarch-builtins.cc
+++ b/gcc/config/loongarch/loongarch-builtins.cc
@@ -2512,14 +2512,11 @@ loongarch_init_builtins (void)
   for (i = 0; i < ARRAY_SIZE (loongarch_builtins); i++)
 {
   d = &loongarch_builtins[i];
-  if (d->avail ())
-   {
- type = loongarch_build_function_type (d->function_type);
- loongarch_builtin_decls[i]
-   = add_builtin_function (d->name, type, i, BUILT_IN_MD, NULL,
-   NULL);
- loongarch_get_builtin_decl_index[d->icode] = i;
-   }
+  type = loongarch_build_function_type (d->function_type);
+  loongarch_builtin_decls[i]
+   = add_builtin_function (d->name, type, i, BUILT_IN_MD, NULL,
+ NULL);
+  loongarch_get_builtin_decl_index[d->icode] = i;
 }
 }
 
@@ -3105,15 +3102,21 @@ loongarch_expand_builtin (tree exp, rtx target, rtx 
subtarget ATTRIBUTE_UNUSED,
  int ignore ATTRIBUTE_UNUSED)
 {
   tree fndecl;
-  unsigned int fcode, avail;
+  unsigned int fcode;
   const struct loongarch_builtin_description *d;
 
   fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
   fcode = DECL_MD_FUNCTION_CODE (fndecl);
   gcc_assert (fcode < ARRAY_SIZE (loongarch_builtins));
   d = &loongarch_builtins[fcode];
-  avail = d->avail ();
-  gcc_assert (avail != 0);
+
+  if (!d->avail ())
+{
+  error_at (EXPR_LOCATION (exp),
+   "built-in function %qD is not enabled", fndecl);
+  return target;
+}
+
   switch (d->builtin_type)
 {
 case LARCH_BUILTIN_DIRECT:
diff --git a/gcc/config/loongarch/loongarch.cc 
b/gcc/config/loongarch/loongarch.cc
index c90b701a533..6b92e7034c5 100644
--- a/gcc/config/loongarch/loongarch.cc
+++ b/gcc/config/loongarch/loongarch.cc
@@ -7570,15 +7570,19 @@ loongarch_global_init (void)
loongarch_dwarf_regno[i] = INVALID_REGNUM;
 }
 
+  /* Function to allocate machine-dependent function status.  */
+  init_machine_status = &loongarch_init_machine_status;
+};
+
+static void
+loongarch_reg_init (void)
+{
   /* Set up loongarch_hard_regno_mode_ok.  */
   for (int mode = 0; mode < MAX_MACHINE_MODE; mode++)
 for (int regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
   loongarch_hard_regno_mode_ok_p[mode][regno]
= loongarch_hard_regno_mode_ok_uncached (regno, (machine_mode) mode);
-
-  /* Function to allocate machine-dependent function status.  */
-  init_machine_status = &loongarch_init_machine_status;
-};
+}
 
 static void
 loongarch_option_override_internal (struct loongarch_target *target,
@@ -7605,20 +7609,92 @@ loongarch_option_override_internal (struct 
loongarch_target *target,
 
   /* Override some options according to the resolved target.  */
   loongarch_target_option_override (target, opts, opts_set);
+
+  target_option_default_node = target_option_current_node
+= build_target_option_node (opts, opts_set);
+
+  loongarch_reg_init ();
+}
+
+/* Remember the last target of loongarch_set_current_function.  */
+
+static GTY(()) tree loongarch_previous

[gcc r14-9984] LoongArch: Add indexes for some compilation options.

[LuluCheng via Gcc-cvs]

https://gcc.gnu.org/g:46d914d0e0b7e982627edb285c41c67cc4e640ac

commit r14-9984-g46d914d0e0b7e982627edb285c41c67cc4e640ac
Author: Lulu Cheng 
Date:   Tue Apr 9 11:48:13 2024 +0800

LoongArch: Add indexes for some compilation options.

gcc/ChangeLog:

* config/loongarch/loongarch.opt.urls: Regenerate.
* config/mn10300/mn10300.opt.urls: Likewise.
* config/msp430/msp430.opt.urls: Likewise.
* config/nds32/nds32-elf.opt.urls: Likewise.
* config/nds32/nds32-linux.opt.urls: Likewise.
* config/nds32/nds32.opt.urls: Likewise.
* config/pru/pru.opt.urls: Likewise.
* config/riscv/riscv.opt.urls: Likewise.
* config/rx/rx.opt.urls: Likewise.
* config/sh/sh.opt.urls: Likewise.
* config/sparc/sparc.opt.urls: Likewise.
* doc/invoke.texi: Add indexes for some compilation options.

Diff:
---
 gcc/config/loongarch/loongarch.opt.urls | 9 +++--
 gcc/config/mn10300/mn10300.opt.urls | 2 +-
 gcc/config/msp430/msp430.opt.urls   | 2 +-
 gcc/config/nds32/nds32-elf.opt.urls | 2 +-
 gcc/config/nds32/nds32-linux.opt.urls   | 2 +-
 gcc/config/nds32/nds32.opt.urls | 2 +-
 gcc/config/pru/pru.opt.urls | 2 +-
 gcc/config/riscv/riscv.opt.urls | 2 +-
 gcc/config/rx/rx.opt.urls   | 2 +-
 gcc/config/sh/sh.opt.urls   | 2 +-
 gcc/config/sparc/sparc.opt.urls | 2 +-
 gcc/doc/invoke.texi | 7 ++-
 12 files changed, 23 insertions(+), 13 deletions(-)

diff --git a/gcc/config/loongarch/loongarch.opt.urls 
b/gcc/config/loongarch/loongarch.opt.urls
index 88f0bb0f96f..9ed5d7b5596 100644
--- a/gcc/config/loongarch/loongarch.opt.urls
+++ b/gcc/config/loongarch/loongarch.opt.urls
@@ -57,12 +57,17 @@ UrlSuffix(gcc/LoongArch-Options.html#index-mrecip)
 mrecip
 UrlSuffix(gcc/LoongArch-Options.html#index-mrecip)
 
-; skipping UrlSuffix for 'mcmodel=' due to finding no URLs
+mcmodel=
+UrlSuffix(gcc/LoongArch-Options.html#index-mcmodel)
 
 mdirect-extern-access
 UrlSuffix(gcc/LoongArch-Options.html#index-mdirect-extern-access)
 
-; skipping UrlSuffix for 'mrelax' due to finding no URLs
+mrelax
+UrlSuffix(gcc/LoongArch-Options.html#index-mrelax-2)
+
+mpass-mrelax-to-as
+UrlSuffix(gcc/LoongArch-Options.html#index-mpass-mrelax-to-as)
 
 mtls-dialect=
 UrlSuffix(gcc/LoongArch-Options.html#index-mtls-dialect-1)
diff --git a/gcc/config/mn10300/mn10300.opt.urls 
b/gcc/config/mn10300/mn10300.opt.urls
index 396ca4aa2e6..d0d1cce53a0 100644
--- a/gcc/config/mn10300/mn10300.opt.urls
+++ b/gcc/config/mn10300/mn10300.opt.urls
@@ -19,7 +19,7 @@ mno-crt0
 UrlSuffix(gcc/MN10300-Options.html#index-mno-crt0)
 
 mrelax
-UrlSuffix(gcc/MN10300-Options.html#index-mrelax-2)
+UrlSuffix(gcc/MN10300-Options.html#index-mrelax-3)
 
 mreturn-pointer-on-d0
 UrlSuffix(gcc/MN10300-Options.html#index-mreturn-pointer-on-d0)
diff --git a/gcc/config/msp430/msp430.opt.urls 
b/gcc/config/msp430/msp430.opt.urls
index 420c1c50f13..b8b8f9ce184 100644
--- a/gcc/config/msp430/msp430.opt.urls
+++ b/gcc/config/msp430/msp430.opt.urls
@@ -28,7 +28,7 @@ msmall
 UrlSuffix(gcc/MSP430-Options.html#index-msmall)
 
 mrelax
-UrlSuffix(gcc/MSP430-Options.html#index-mrelax-3)
+UrlSuffix(gcc/MSP430-Options.html#index-mrelax-4)
 
 minrt
 UrlSuffix(gcc/MSP430-Options.html#index-minrt)
diff --git a/gcc/config/nds32/nds32-elf.opt.urls 
b/gcc/config/nds32/nds32-elf.opt.urls
index 5399afba7d3..3ae1efe7312 100644
--- a/gcc/config/nds32/nds32-elf.opt.urls
+++ b/gcc/config/nds32/nds32-elf.opt.urls
@@ -1,5 +1,5 @@
 ; Autogenerated by regenerate-opt-urls.py from gcc/config/nds32/nds32-elf.opt 
and generated HTML
 
 mcmodel=
-UrlSuffix(gcc/NDS32-Options.html#index-mcmodel)
+UrlSuffix(gcc/NDS32-Options.html#index-mcmodel-1)
 
diff --git a/gcc/config/nds32/nds32-linux.opt.urls 
b/gcc/config/nds32/nds32-linux.opt.urls
index 27d39f04ad9..ac589ccd472 100644
--- a/gcc/config/nds32/nds32-linux.opt.urls
+++ b/gcc/config/nds32/nds32-linux.opt.urls
@@ -1,5 +1,5 @@
 ; Autogenerated by regenerate-opt-urls.py from 
gcc/config/nds32/nds32-linux.opt and generated HTML
 
 mcmodel=
-UrlSuffix(gcc/NDS32-Options.html#index-mcmodel)
+UrlSuffix(gcc/NDS32-Options.html#index-mcmodel-1)
 
diff --git a/gcc/config/nds32/nds32.opt.urls b/gcc/config/nds32/nds32.opt.urls
index e34512d69ba..44fa0696b95 100644
--- a/gcc/config/nds32/nds32.opt.urls
+++ b/gcc/config/nds32/nds32.opt.urls
@@ -51,7 +51,7 @@ mctor-dtor
 UrlSuffix(gcc/NDS32-Options.html#index-mctor-dtor)
 
 mrelax
-UrlSuffix(gcc/NDS32-Options.html#index-mrelax-4)
+UrlSuffix(gcc/NDS32-Options.html#index-mrelax-5)
 
 ; skipping UrlSuffix for 'munaligned-access' due to finding no URLs
 
diff --git a/gcc/config/pru/pru.opt.urls b/gcc/config/pru/pru.opt.urls
index 1f8a26a0db5..c87affb112b 100644
--- a/gcc/config/pru/pru.opt.urls
+++ b/gcc/config/pru/pru.opt.urls
@@ -7,7 +7,7 @@ mmcu=
 UrlSuffix(gcc/PRU-Options.html#index-mmcu-2)
 
 mno-relax
-UrlSuffix(gc

[gcc r14-10083] LoongArch: Define ISA versions

[LuluCheng via Gcc-cvs]

https://gcc.gnu.org/g:b4ebdd153b2b068082b452772095260b03b78cc2

commit r14-10083-gb4ebdd153b2b068082b452772095260b03b78cc2
Author: Yang Yujie 
Date:   Tue Apr 23 10:42:47 2024 +0800

LoongArch: Define ISA versions

These ISA versions are defined as -march= parameters and
are recommended for building binaries for distribution.

Detailed description of these definitions can be found at
https://github.com/loongson/la-toolchain-conventions, which
the LoongArch GCC port aims to conform to.

gcc/ChangeLog:

* config.gcc: Make la64v1.0 the default ISA preset of the lp64d ABI.
* config/loongarch/genopts/loongarch-strings: Define la64v1.0, 
la64v1.1.
* config/loongarch/genopts/loongarch.opt.in: Likewise.
* config/loongarch/loongarch-c.cc (LARCH_CPP_SET_PROCESSOR): 
Likewise.
(loongarch_cpu_cpp_builtins): Likewise.
* config/loongarch/loongarch-cpu.cc (get_native_prid): Likewise.
(fill_native_cpu_config): Likewise.
* config/loongarch/loongarch-def.cc (array_tune): Likewise.
* config/loongarch/loongarch-def.h: Likewise.
* config/loongarch/loongarch-driver.cc (driver_set_m_parm): 
Likewise.
(driver_get_normalized_m_opts): Likewise.
* config/loongarch/loongarch-opts.cc (default_tune_for_arch): 
Likewise.
(TUNE_FOR_ARCH): Likewise.
(arch_str): Likewise.
(loongarch_target_option_override): Likewise.
* config/loongarch/loongarch-opts.h (TARGET_uARCH_LA464): Likewise.
(TARGET_uARCH_LA664): Likewise.
* config/loongarch/loongarch-str.h (STR_CPU_ABI_DEFAULT): Likewise.
(STR_ARCH_ABI_DEFAULT): Likewise.
(STR_TUNE_GENERIC): Likewise.
(STR_ARCH_LA64V1_0): Likewise.
(STR_ARCH_LA64V1_1): Likewise.
* config/loongarch/loongarch.cc 
(loongarch_cpu_sched_reassociation_width): Likewise.
(loongarch_asm_code_end): Likewise.
* config/loongarch/loongarch.opt: Likewise.
* doc/invoke.texi: Likewise.

Diff:
---
 gcc/config.gcc | 34 +--
 gcc/config/loongarch/genopts/loongarch-strings |  5 +-
 gcc/config/loongarch/genopts/loongarch.opt.in  | 43 ++---
 gcc/config/loongarch/loongarch-c.cc| 37 
 gcc/config/loongarch/loongarch-cpu.cc  | 35 ++-
 gcc/config/loongarch/loongarch-def.cc  | 83 +-
 gcc/config/loongarch/loongarch-def.h   | 37 
 gcc/config/loongarch/loongarch-driver.cc   |  8 +--
 gcc/config/loongarch/loongarch-opts.cc | 66 ++--
 gcc/config/loongarch/loongarch-opts.h  |  4 +-
 gcc/config/loongarch/loongarch-str.h   |  5 +-
 gcc/config/loongarch/loongarch.cc  | 11 ++--
 gcc/config/loongarch/loongarch.opt | 43 ++---
 gcc/doc/invoke.texi| 57 +++---
 14 files changed, 300 insertions(+), 168 deletions(-)

diff --git a/gcc/config.gcc b/gcc/config.gcc
index 029ad1f1f08..2cdecf78e05 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -5073,7 +5073,7 @@ case "${target}" in
 
# Perform initial sanity checks on --with-* options.
case ${with_arch} in
-   "" | abi-default | loongarch64 | la[46]64) ;; # OK, append here.
+   "" | la64v1.[01] | abi-default | loongarch64 | la[46]64) ;; # 
OK, append here.
native)
if test x${host} != x${target}; then
echo "--with-arch=native is illegal for 
cross-compiler." 1>&2
@@ -5120,10 +5120,18 @@ case "${target}" in
 
# Infer ISA-related default options from the ABI: pass 1
case ${abi_base}/${abi_ext} in
-   lp64*/base)
+   lp64d/base)
# architectures that support lp64* ABI
-   arch_pattern="native|abi-default|loongarch64|la[46]64"
-   # default architecture for lp64* ABI
+   
arch_pattern="native|abi-default|la64v1.[01]|loongarch64|la[46]64"
+
+   # default architecture for lp64d ABI
+   arch_default="la64v1.0"
+   ;;
+   lp64[fs]/base)
+   # architectures that support lp64* ABI
+   
arch_pattern="native|abi-default|la64v1.[01]|loongarch64|la[46]64"
+
+   # default architecture for lp64[fs] ABI
arch_default="abi-default"
;;
*)
@@ -5195,15 +5203,7 @@ case "${target}" in
 
 
# Check default with_tune configuration using with_arch.
-   case ${with_arch} in
-   loongarch64)
-   tune_pattern="native|abi-defaul

[gcc r14-10084] LoongArch: Define builtin macros for ISA evolutions

[LuluCheng via Gcc-cvs]

https://gcc.gnu.org/g:77e114bb0dc03d1df7f84221e3132d19030c34b4

commit r14-10084-g77e114bb0dc03d1df7f84221e3132d19030c34b4
Author: Yang Yujie 
Date:   Tue Apr 23 10:42:48 2024 +0800

LoongArch: Define builtin macros for ISA evolutions

Detailed description of these definitions can be found at
https://github.com/loongson/la-toolchain-conventions, which
the LoongArch GCC port aims to conform to.

gcc/ChangeLog:

* config.gcc: Add loongarch-evolution.o.
* config/loongarch/genopts/genstr.sh: Enable generation of
loongarch-evolution.[cc,h].
* config/loongarch/t-loongarch: Likewise.
* config/loongarch/genopts/gen-evolution.awk: New file.
* config/loongarch/genopts/isa-evolution.in: Mark ISA version
of introduction for each ISA evolution feature.
* config/loongarch/loongarch-c.cc (loongarch_cpu_cpp_builtins):
Define builtin macros for enabled ISA evolutions and the ISA
version.
* config/loongarch/loongarch-cpu.cc: Use loongarch-evolution.h.
* config/loongarch/loongarch.h: Likewise.
* config/loongarch/loongarch-cpucfg-map.h: Delete.
* config/loongarch/loongarch-evolution.cc: New file.
* config/loongarch/loongarch-evolution.h: New file.
* config/loongarch/loongarch-opts.h (ISA_HAS_FRECIPE): Define.
(ISA_HAS_DIV32): Likewise.
(ISA_HAS_LAM_BH): Likewise.
(ISA_HAS_LAMCAS): Likewise.
(ISA_HAS_LD_SEQ_SA): Likewise.

Diff:
---
 gcc/config.gcc |   2 +-
 gcc/config/loongarch/genopts/gen-evolution.awk | 230 +
 gcc/config/loongarch/genopts/genstr.sh |  82 ++--
 gcc/config/loongarch/genopts/isa-evolution.in  |  10 +-
 gcc/config/loongarch/loongarch-c.cc|  23 +++
 gcc/config/loongarch/loongarch-cpu.cc  |   2 +-
 gcc/config/loongarch/loongarch-evolution.cc|  60 ++
 ...oongarch-cpucfg-map.h => loongarch-evolution.h} |  46 -
 gcc/config/loongarch/loongarch-opts.h  |  11 -
 gcc/config/loongarch/loongarch.h   |   1 +
 gcc/config/loongarch/t-loongarch   |  26 ++-
 11 files changed, 398 insertions(+), 95 deletions(-)

diff --git a/gcc/config.gcc b/gcc/config.gcc
index 2cdecf78e05..ce683adcc8a 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -486,7 +486,7 @@ loongarch*-*-*)
cpu_type=loongarch
d_target_objs="loongarch-d.o"
extra_headers="larchintrin.h lsxintrin.h lasxintrin.h"
-   extra_objs="loongarch-c.o loongarch-builtins.o loongarch-cpu.o 
loongarch-opts.o loongarch-def.o"
+   extra_objs="loongarch-c.o loongarch-builtins.o loongarch-cpu.o 
loongarch-opts.o loongarch-def.o loongarch-evolution.o"
extra_gcc_objs="loongarch-driver.o loongarch-cpu.o loongarch-opts.o 
loongarch-def.o"
extra_options="${extra_options} g.opt fused-madd.opt"
;;
diff --git a/gcc/config/loongarch/genopts/gen-evolution.awk 
b/gcc/config/loongarch/genopts/gen-evolution.awk
new file mode 100644
index 000..4d105afa906
--- /dev/null
+++ b/gcc/config/loongarch/genopts/gen-evolution.awk
@@ -0,0 +1,230 @@
+#!/usr/bin/gawk
+#
+# A simple script that generates loongarch-evolution.h
+# from genopts/isa-evolution.in
+#
+# Copyright (C) 2021-2024 Free Software Foundation, Inc.
+#
+# This file is part of GCC.
+#
+# GCC is free software; you can redistribute it and/or modify it under
+# the terms of the GNU General Public License as published by the Free
+# Software Foundation; either version 3, or (at your option) any later
+# version.
+#
+# GCC is distributed in the hope that it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+# or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+# License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with GCC; see the file COPYING3.  If not see
+# .
+
+BEGIN {
+# isa_version_major[]
+# isa_version_minor[]
+# cpucfg_word[]
+# cpucfg_bit_in_word[]
+# name_capitalized[]
+# comment[]
+}
+
+{
+cpucfg_word[NR] = $1
+cpucfg_bit_in_word[NR] = $2
+name[NR] = gensub(/-/, "_", "g", $3)
+name_capitalized[NR] = toupper(name[NR])
+isa_version_major[NR] = gensub(/^([1-9][0-9]*)\.([0-9]+)$/, "\\1", 1, $4)
+isa_version_minor[NR] = gensub(/^([1-9][0-9]*)\.([0-9]+)$/, "\\2", 1, $4)
+
+$1 = $2 = $3 = $4 = ""
+sub (/^\s*/, "")
+comment[NR] = $0
+}
+
+function copyright_header(from_year,to_year)
+{
+print "   Copyright (C) " from_year "-" to_year \
+  " Free Software Foundation, Inc."
+print ""
+print "This file is part of GCC."
+print ""
+print "GCC is free software; you can redistribute it and/or modify"
+print "it under the t

[gcc r12-10403] LoongArch: Fix eh_return epilogue for normal returns.

[LuluCheng via Gcc-cvs]

https://gcc.gnu.org/g:bb78099d2624b52c781ed6e5d85e43d54c3cda1a

commit r12-10403-gbb78099d2624b52c781ed6e5d85e43d54c3cda1a
Author: Yang Yujie 
Date:   Fri Dec 8 18:01:18 2023 +0800

LoongArch: Fix eh_return epilogue for normal returns.

On LoongArch, the regitsters $r4 - $r7 (EH_RETURN_DATA_REGNO) will be saved
and restored in the function prologue and epilogue if the given function 
calls
__builtin_eh_return.  This causes the return value to be overwritten on 
normal
return paths and breaks a rare case of libgcc's _Unwind_RaiseException.

gcc/ChangeLog:

PR target/114848
* config/loongarch/loongarch.cc: Do not restore the saved eh_return
data registers ($r4-$r7) for a normal return of a function that 
calls
__builtin_eh_return elsewhere.
* config/loongarch/loongarch-protos.h: Same.
* config/loongarch/loongarch.md: Same.

gcc/testsuite/ChangeLog:

* gcc.target/loongarch/eh_return-normal-return.c: New test.

(cherry picked from commit 4b421728289e6f1caa0dfaa953a11698ab95d37d)

Diff:
---
 gcc/config/loongarch/loongarch-protos.h|  2 +-
 gcc/config/loongarch/loongarch.cc  | 35 ++--
 gcc/config/loongarch/loongarch.md  | 23 +++--
 .../gcc.target/loongarch/eh_return-normal-return.c | 38 ++
 4 files changed, 85 insertions(+), 13 deletions(-)

diff --git a/gcc/config/loongarch/loongarch-protos.h 
b/gcc/config/loongarch/loongarch-protos.h
index 2144c2421ed..8af82ffaa20 100644
--- a/gcc/config/loongarch/loongarch-protos.h
+++ b/gcc/config/loongarch/loongarch-protos.h
@@ -47,7 +47,7 @@ enum loongarch_symbol_type {
 extern rtx loongarch_emit_move (rtx, rtx);
 extern HOST_WIDE_INT loongarch_initial_elimination_offset (int, int);
 extern void loongarch_expand_prologue (void);
-extern void loongarch_expand_epilogue (bool);
+extern void loongarch_expand_epilogue (int);
 extern bool loongarch_can_use_return_insn (void);
 
 extern bool loongarch_symbolic_constant_p (rtx, enum loongarch_symbol_type *);
diff --git a/gcc/config/loongarch/loongarch.cc 
b/gcc/config/loongarch/loongarch.cc
index 33b1919e7a3..a0e11f2fc66 100644
--- a/gcc/config/loongarch/loongarch.cc
+++ b/gcc/config/loongarch/loongarch.cc
@@ -1008,7 +1008,8 @@ loongarch_save_restore_reg (machine_mode mode, int regno, 
HOST_WIDE_INT offset,
 
 static void
 loongarch_for_each_saved_reg (HOST_WIDE_INT sp_offset,
- loongarch_save_restore_fn fn)
+ loongarch_save_restore_fn fn,
+ bool skip_eh_data_regs_p)
 {
   HOST_WIDE_INT offset;
 
@@ -1017,7 +1018,15 @@ loongarch_for_each_saved_reg (HOST_WIDE_INT sp_offset,
   for (int regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
 if (BITSET_P (cfun->machine->frame.mask, regno - GP_REG_FIRST))
   {
-   loongarch_save_restore_reg (word_mode, regno, offset, fn);
+   /* Special care needs to be taken for $r4-$r7 (EH_RETURN_DATA_REGNO)
+  when returning normally from a function that calls
+  __builtin_eh_return.  In this case, these registers are saved but
+  should not be restored, or the return value may be clobbered.  */
+
+   if (!(skip_eh_data_regs_p
+ && GP_ARG_FIRST <= regno && regno < GP_ARG_FIRST + 4))
+ loongarch_save_restore_reg (word_mode, regno, offset, fn);
+
offset -= UNITS_PER_WORD;
   }
 
@@ -1289,7 +1298,7 @@ loongarch_expand_prologue (void)
GEN_INT (-step1));
   RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
   size -= step1;
-  loongarch_for_each_saved_reg (size, loongarch_save_reg);
+  loongarch_for_each_saved_reg (size, loongarch_save_reg, false);
 }
 
 
@@ -1336,11 +1345,13 @@ loongarch_can_use_return_insn (void)
   return reload_completed && cfun->machine->frame.total_size == 0;
 }
 
-/* Expand an "epilogue" or "sibcall_epilogue" pattern; SIBCALL_P
-   says which.  */
+/* Expand function epilogue using the following insn patterns:
+   "epilogue"(style == NORMAL_RETURN)
+   "sibcall_epilogue" (style == SIBCALL_RETURN)
+   "eh_return"   (style == EXCEPTION_RETURN) */
 
 void
-loongarch_expand_epilogue (bool sibcall_p)
+loongarch_expand_epilogue (int style)
 {
   /* Split the frame into two.  STEP1 is the amount of stack we should
  deallocate before restoring the registers.  STEP2 is the amount we
@@ -1357,7 +1368,8 @@ loongarch_expand_epilogue (bool sibcall_p)
   bool need_barrier_p
 = (get_frame_size () + cfun->machine->frame.arg_pointer_offset) != 0;
 
-  if (!sibcall_p && loongarch_can_use_return_insn ())
+  /* Handle simple returns.  */
+  if (style == NORMAL_RETURN && loongarch_can_use_return_insn ())
 {
   emit_jump_insn (gen_return ());
   return;
@@ -1433,7 +1445,9 @@ loongarch_expand_epilogue (bool sibcall_p)
 
   /* Restore the registers. 

[gcc r13-8661] LoongArch: Fix eh_return epilogue for normal returns.

[LuluCheng via Gcc-cvs]

https://gcc.gnu.org/g:88f22217521564e1a956e14ac55456caa160e055

commit r13-8661-g88f22217521564e1a956e14ac55456caa160e055
Author: Yang Yujie 
Date:   Fri Dec 8 18:01:18 2023 +0800

LoongArch: Fix eh_return epilogue for normal returns.

On LoongArch, the regitsters $r4 - $r7 (EH_RETURN_DATA_REGNO) will be saved
and restored in the function prologue and epilogue if the given function 
calls
__builtin_eh_return.  This causes the return value to be overwritten on 
normal
return paths and breaks a rare case of libgcc's _Unwind_RaiseException.

gcc/ChangeLog:

PR target/114848
* config/loongarch/loongarch.cc: Do not restore the saved eh_return
data registers ($r4-$r7) for a normal return of a function that 
calls
__builtin_eh_return elsewhere.
* config/loongarch/loongarch-protos.h: Same.
* config/loongarch/loongarch.md: Same.

gcc/testsuite/ChangeLog:

* gcc.target/loongarch/eh_return-normal-return.c: New test.

(cherry picked from commit 4b421728289e6f1caa0dfaa953a11698ab95d37d)

Diff:
---
 gcc/config/loongarch/loongarch-protos.h|  2 +-
 gcc/config/loongarch/loongarch.cc  | 35 ++--
 gcc/config/loongarch/loongarch.md  | 23 +++--
 .../gcc.target/loongarch/eh_return-normal-return.c | 38 ++
 4 files changed, 85 insertions(+), 13 deletions(-)

diff --git a/gcc/config/loongarch/loongarch-protos.h 
b/gcc/config/loongarch/loongarch-protos.h
index 35cc77c7367..0f608ee5179 100644
--- a/gcc/config/loongarch/loongarch-protos.h
+++ b/gcc/config/loongarch/loongarch-protos.h
@@ -60,7 +60,7 @@ enum loongarch_symbol_type {
 extern rtx loongarch_emit_move (rtx, rtx);
 extern HOST_WIDE_INT loongarch_initial_elimination_offset (int, int);
 extern void loongarch_expand_prologue (void);
-extern void loongarch_expand_epilogue (bool);
+extern void loongarch_expand_epilogue (int);
 extern bool loongarch_can_use_return_insn (void);
 
 extern bool loongarch_symbolic_constant_p (rtx, enum loongarch_symbol_type *);
diff --git a/gcc/config/loongarch/loongarch.cc 
b/gcc/config/loongarch/loongarch.cc
index f47a5fc2ad7..2238858cd6a 100644
--- a/gcc/config/loongarch/loongarch.cc
+++ b/gcc/config/loongarch/loongarch.cc
@@ -1012,7 +1012,8 @@ loongarch_save_restore_reg (machine_mode mode, int regno, 
HOST_WIDE_INT offset,
 
 static void
 loongarch_for_each_saved_reg (HOST_WIDE_INT sp_offset,
- loongarch_save_restore_fn fn)
+ loongarch_save_restore_fn fn,
+ bool skip_eh_data_regs_p)
 {
   HOST_WIDE_INT offset;
 
@@ -1021,7 +1022,15 @@ loongarch_for_each_saved_reg (HOST_WIDE_INT sp_offset,
   for (int regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
 if (BITSET_P (cfun->machine->frame.mask, regno - GP_REG_FIRST))
   {
-   loongarch_save_restore_reg (word_mode, regno, offset, fn);
+   /* Special care needs to be taken for $r4-$r7 (EH_RETURN_DATA_REGNO)
+  when returning normally from a function that calls
+  __builtin_eh_return.  In this case, these registers are saved but
+  should not be restored, or the return value may be clobbered.  */
+
+   if (!(skip_eh_data_regs_p
+ && GP_ARG_FIRST <= regno && regno < GP_ARG_FIRST + 4))
+ loongarch_save_restore_reg (word_mode, regno, offset, fn);
+
offset -= UNITS_PER_WORD;
   }
 
@@ -1290,7 +1299,7 @@ loongarch_expand_prologue (void)
GEN_INT (-step1));
   RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
   size -= step1;
-  loongarch_for_each_saved_reg (size, loongarch_save_reg);
+  loongarch_for_each_saved_reg (size, loongarch_save_reg, false);
 }
 
   /* Set up the frame pointer, if we're using one.  */
@@ -1375,11 +1384,13 @@ loongarch_can_use_return_insn (void)
   return reload_completed && cfun->machine->frame.total_size == 0;
 }
 
-/* Expand an "epilogue" or "sibcall_epilogue" pattern; SIBCALL_P
-   says which.  */
+/* Expand function epilogue using the following insn patterns:
+   "epilogue"(style == NORMAL_RETURN)
+   "sibcall_epilogue" (style == SIBCALL_RETURN)
+   "eh_return"   (style == EXCEPTION_RETURN) */
 
 void
-loongarch_expand_epilogue (bool sibcall_p)
+loongarch_expand_epilogue (int style)
 {
   /* Split the frame into two.  STEP1 is the amount of stack we should
  deallocate before restoring the registers.  STEP2 is the amount we
@@ -1396,7 +1407,8 @@ loongarch_expand_epilogue (bool sibcall_p)
   bool need_barrier_p
 = (get_frame_size () + cfun->machine->frame.arg_pointer_offset) != 0;
 
-  if (!sibcall_p && loongarch_can_use_return_insn ())
+  /* Handle simple returns.  */
+  if (style == NORMAL_RETURN && loongarch_can_use_return_insn ())
 {
   emit_jump_insn (gen_return ());
   return;
@@ -1472,7 +1484,9 @@ loongarch_expand_epil

[gcc r15-2660] LoongArch: Remove gawk extension from a generator script.

[LuluCheng via Gcc-cvs]

https://gcc.gnu.org/g:c48f38288fb17b70784ae5e71cb741e664da023a

commit r15-2660-gc48f38288fb17b70784ae5e71cb741e664da023a
Author: Yang Yujie 
Date:   Tue Jul 23 10:04:26 2024 +0800

LoongArch: Remove gawk extension from a generator script.

gcc/ChangeLog:

* config/loongarch/genopts/gen-evolution.awk: Do not use
"length()" to compute the size of an array.

Diff:
---
 gcc/config/loongarch/genopts/gen-evolution.awk | 7 ---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/gcc/config/loongarch/genopts/gen-evolution.awk 
b/gcc/config/loongarch/genopts/gen-evolution.awk
index 4d105afa9067..1c8004e4146c 100644
--- a/gcc/config/loongarch/genopts/gen-evolution.awk
+++ b/gcc/config/loongarch/genopts/gen-evolution.awk
@@ -1,4 +1,4 @@
-#!/usr/bin/gawk
+#!/usr/bin/awk -f
 #
 # A simple script that generates loongarch-evolution.h
 # from genopts/isa-evolution.in
@@ -94,8 +94,9 @@ function gen_cpucfg_useful_idx()
 idx_bucket[cpucfg_word[i]] = 1
 
 delete idx_list
+j = 1
 for (i in idx_bucket)
-idx_list[length(idx_list)-1] = i+0
+idx_list[j++] = i+0
 delete idx_bucket
 
 asort (idx_list)
@@ -108,7 +109,7 @@ function gen_cpucfg_useful_idx()
 print ""
 
 printf ("static constexpr int N_CPUCFG_WORDS = %d;\n",
-idx_list[length(idx_list)] + 1)
+idx_list[j - 1] + 1)
 
 delete idx_list
 }

[gcc r14-10549] LoongArch: Remove gawk extension from a generator script.

[LuluCheng via Gcc-cvs]

https://gcc.gnu.org/g:79d32baea4a94dd1d4e267a0e172fb15c238fb37

commit r14-10549-g79d32baea4a94dd1d4e267a0e172fb15c238fb37
Author: Yang Yujie 
Date:   Tue Jul 23 10:04:26 2024 +0800

LoongArch: Remove gawk extension from a generator script.

gcc/ChangeLog:

* config/loongarch/genopts/gen-evolution.awk: Do not use
"length()" to compute the size of an array.

(cherry picked from commit c48f38288fb17b70784ae5e71cb741e664da023a)

Diff:
---
 gcc/config/loongarch/genopts/gen-evolution.awk | 7 ---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/gcc/config/loongarch/genopts/gen-evolution.awk 
b/gcc/config/loongarch/genopts/gen-evolution.awk
index 4d105afa9067..1c8004e4146c 100644
--- a/gcc/config/loongarch/genopts/gen-evolution.awk
+++ b/gcc/config/loongarch/genopts/gen-evolution.awk
@@ -1,4 +1,4 @@
-#!/usr/bin/gawk
+#!/usr/bin/awk -f
 #
 # A simple script that generates loongarch-evolution.h
 # from genopts/isa-evolution.in
@@ -94,8 +94,9 @@ function gen_cpucfg_useful_idx()
 idx_bucket[cpucfg_word[i]] = 1
 
 delete idx_list
+j = 1
 for (i in idx_bucket)
-idx_list[length(idx_list)-1] = i+0
+idx_list[j++] = i+0
 delete idx_bucket
 
 asort (idx_list)
@@ -108,7 +109,7 @@ function gen_cpucfg_useful_idx()
 print ""
 
 printf ("static constexpr int N_CPUCFG_WORDS = %d;\n",
-idx_list[length(idx_list)] + 1)
+idx_list[j - 1] + 1)
 
 delete idx_list
 }

[gcc r15-2877] LoongArch: Use iorn and andn standard pattern names.

[LuluCheng via Gcc-cvs]

https://gcc.gnu.org/g:75e852b49fca399b9fd00a9cc943d9366e509711

commit r15-2877-g75e852b49fca399b9fd00a9cc943d9366e509711
Author: Lulu Cheng 
Date:   Thu Aug 1 16:07:25 2024 +0800

LoongArch: Use iorn and andn standard pattern names.

R15-1890 introduced new optabs iorc and andc, and its corresponding
internal functions BIT_{ANDC,IORC}, and if targets defines such optabs
for vector modes.  And in r15-2258 the iorc and andc were renamed to
iorn and andn.
So we changed the andn and iorn implementation templates to the standard
template names.

gcc/ChangeLog:

* config/loongarch/lasx.md (xvandn3): Rename to ...
(andn3): This.
(xvorn3): Rename to ...
(iorn3): This.
* config/loongarch/loongarch-builtins.cc
(CODE_FOR_lsx_vandn_v): Defined as the modified name.
(CODE_FOR_lsx_vorn_v): Likewise.
(CODE_FOR_lasx_xvandn_v): Likewise.
(CODE_FOR_lasx_xvorn_v): Likewise.
(loongarch_expand_builtin_insn): When the builtin function to be
called is __builtin_lasx_xvandn or __builtin_lsx_vandn, swap the
two operands.
* config/loongarch/loongarch.md (n): Rename to ...
(n3): This.
* config/loongarch/lsx.md (vandn3): Rename to ...
(andn3): This.
(vorn3): Rename to ...
(iorn3): This.

gcc/testsuite/ChangeLog:

* gcc.target/loongarch/lasx-andn-iorn.c: New test.
* gcc.target/loongarch/lsx-andn-iorn.c: New test.

Diff:
---
 gcc/config/loongarch/lasx.md   | 10 
 gcc/config/loongarch/loongarch-builtins.cc | 10 
 gcc/config/loongarch/loongarch.md  |  8 +++
 gcc/config/loongarch/lsx.md| 10 
 .../gcc.target/loongarch/lasx-andn-iorn.c  | 11 +
 gcc/testsuite/gcc.target/loongarch/lsx-andn-iorn.c | 28 ++
 6 files changed, 59 insertions(+), 18 deletions(-)

diff --git a/gcc/config/loongarch/lasx.md b/gcc/config/loongarch/lasx.md
index 7bd61f8ed5b7..ca523880683b 100644
--- a/gcc/config/loongarch/lasx.md
+++ b/gcc/config/loongarch/lasx.md
@@ -2716,12 +2716,12 @@
(set_attr "mode" "V4DI")])
 
 ;; Extend loongson-sx to loongson-asx.
-(define_insn "xvandn3"
+(define_insn "andn3"
   [(set (match_operand:LASX 0 "register_operand" "=f")
-   (and:LASX (not:LASX (match_operand:LASX 1 "register_operand" "f"))
-   (match_operand:LASX 2 "register_operand" "f")))]
+   (and:LASX (not:LASX (match_operand:LASX 2 "register_operand" "f"))
+   (match_operand:LASX 1 "register_operand" "f")))]
   "ISA_HAS_LASX"
-  "xvandn.v\t%u0,%u1,%u2"
+  "xvandn.v\t%u0,%u2,%u1"
   [(set_attr "type" "simd_logic")
(set_attr "mode" "")])
 
@@ -4637,7 +4637,7 @@
   [(set_attr "type" "simd_int_arith")
(set_attr "mode" "")])
 
-(define_insn "xvorn3"
+(define_insn "iorn3"
   [(set (match_operand:ILASX 0 "register_operand" "=f")
(ior:ILASX (not:ILASX (match_operand:ILASX 2 "register_operand" "f"))
   (match_operand:ILASX 1 "register_operand" "f")))]
diff --git a/gcc/config/loongarch/loongarch-builtins.cc 
b/gcc/config/loongarch/loongarch-builtins.cc
index fbe46833c9b7..cf92770de30e 100644
--- a/gcc/config/loongarch/loongarch-builtins.cc
+++ b/gcc/config/loongarch/loongarch-builtins.cc
@@ -458,8 +458,8 @@ AVAIL_ALL (lasx_frecipe, ISA_HAS_LASX && ISA_HAS_FRECIPE)
 #define CODE_FOR_lsx_vabsd_du CODE_FOR_lsx_vabsd_u_du
 #define CODE_FOR_lsx_vftint_wu_s CODE_FOR_lsx_vftint_u_wu_s
 #define CODE_FOR_lsx_vftint_lu_d CODE_FOR_lsx_vftint_u_lu_d
-#define CODE_FOR_lsx_vandn_v CODE_FOR_vandnv16qi3
-#define CODE_FOR_lsx_vorn_v CODE_FOR_vornv16qi3
+#define CODE_FOR_lsx_vandn_v CODE_FOR_andnv16qi3
+#define CODE_FOR_lsx_vorn_v CODE_FOR_iornv16qi3
 #define CODE_FOR_lsx_vneg_b CODE_FOR_vnegv16qi2
 #define CODE_FOR_lsx_vneg_h CODE_FOR_vnegv8hi2
 #define CODE_FOR_lsx_vneg_w CODE_FOR_vnegv4si2
@@ -692,8 +692,8 @@ AVAIL_ALL (lasx_frecipe, ISA_HAS_LASX && ISA_HAS_FRECIPE)
 #define CODE_FOR_lasx_xvrepli_w CODE_FOR_lasx_xvrepliv8si
 #define CODE_FOR_lasx_xvrepli_d CODE_FOR_lasx_xvrepliv4di
 
-#define CODE_FOR_lasx_xvandn_v CODE_FOR_xvandnv32qi3
-#define CODE_FOR_lasx_xvorn_v CODE_FOR_xvornv32qi3
+#define CODE_FOR_lasx_xvandn_v CODE_FOR_andnv32qi3
+#define CODE_FOR_lasx_xvorn_v CODE_FOR_iornv32qi3
 #define CODE_FOR_lasx_xvneg_b CODE_FOR_negv32qi2
 #define CODE_FOR_lasx_xvneg_h CODE_FOR_negv16hi2
 #define CODE_FOR_lasx_xvneg_w CODE_FOR_negv8si2
@@ -2858,6 +2858,7 @@ loongarch_expand_builtin_insn (enum insn_code icode, 
unsigned int nops,
 case CODE_FOR_lsx_vpickod_b:
 case CODE_FOR_lsx_vpickod_h:
 case CODE_FOR_lsx_vpickod_w:
+case CODE_FOR_lsx_vandn_v:
 case CODE_FOR_lasx_xvilvh_b:
 case CODE_FOR_lasx_xvilvh_h:
 case CODE_FOR_lasx_xvilvh_w:
@@ -2878,6 +2879,7 @@ loongarch_exp

[gcc r15-2878] LoongArch: Drop vcond{,u} expanders.

[LuluCheng via Gcc-cvs]

https://gcc.gnu.org/g:0498f8bda1d08b8ed8100d759917792baf2da15f

commit r15-2878-g0498f8bda1d08b8ed8100d759917792baf2da15f
Author: Lulu Cheng 
Date:   Thu Aug 8 10:39:54 2024 +0800

LoongArch: Drop vcond{,u} expanders.

Optabs vcond{,u} will be removed for GCC 15.  Since regtest shows no
fallout, dropping the expanders, now.

gcc/ChangeLog:

PR target/114189
* config/loongarch/lasx.md (vcondu): Delete.
(vcond): Likewise.
* config/loongarch/lsx.md (vcondu): Likewise.
(vcond): Likewise.

Diff:
---
 gcc/config/loongarch/lasx.md | 37 -
 gcc/config/loongarch/lsx.md  | 31 ---
 2 files changed, 68 deletions(-)

diff --git a/gcc/config/loongarch/lasx.md b/gcc/config/loongarch/lasx.md
index ca523880683b..d37b2e83c21e 100644
--- a/gcc/config/loongarch/lasx.md
+++ b/gcc/config/loongarch/lasx.md
@@ -165,9 +165,6 @@
 ;; All vector modes with 256 bits.
 (define_mode_iterator LASX [V4DF V8SF V4DI V8SI V16HI V32QI])
 
-;; Same as LASX.  Used by vcond to iterate two modes.
-(define_mode_iterator LASX_2 [V4DF V8SF V4DI V8SI V16HI V32QI])
-
 ;; Only used for splitting insert_d and copy_{u,s}.d.
 (define_mode_iterator LASX_D [V4DI V4DF])
 
@@ -762,40 +759,6 @@
DONE;
 })
 
-;; FIXME: 256??
-(define_expand "vcondu"
-  [(match_operand:LASX 0 "register_operand")
-   (match_operand:LASX 1 "reg_or_m1_operand")
-   (match_operand:LASX 2 "reg_or_0_operand")
-   (match_operator 3 ""
-[(match_operand:ILASX 4 "register_operand")
- (match_operand:ILASX 5 "register_operand")])]
-  "ISA_HAS_LASX
-   && (GET_MODE_NUNITS (mode)
-   == GET_MODE_NUNITS (mode))"
-{
-  loongarch_expand_vec_cond_expr (mode, mode,
- operands);
-  DONE;
-})
-
-;; FIXME: 256??
-(define_expand "vcond"
-  [(match_operand:LASX 0 "register_operand")
-   (match_operand:LASX 1 "reg_or_m1_operand")
-   (match_operand:LASX 2 "reg_or_0_operand")
-   (match_operator 3 ""
- [(match_operand:LASX_2 4 "register_operand")
-  (match_operand:LASX_2 5 "register_operand")])]
-  "ISA_HAS_LASX
-   && (GET_MODE_NUNITS (mode)
-   == GET_MODE_NUNITS (mode))"
-{
-  loongarch_expand_vec_cond_expr (mode, mode,
- operands);
-  DONE;
-})
-
 ;; Same as vcond_
 (define_expand "vcond_mask_"
   [(match_operand:LASX 0 "register_operand")
diff --git a/gcc/config/loongarch/lsx.md b/gcc/config/loongarch/lsx.md
index 6bdf4fe43f5e..fcba28b07515 100644
--- a/gcc/config/loongarch/lsx.md
+++ b/gcc/config/loongarch/lsx.md
@@ -186,9 +186,6 @@
 ;; All vector modes with 128 bits.
 (define_mode_iterator LSX  [V2DF V4SF V2DI V4SI V8HI V16QI])
 
-;; Same as LSX.  Used by vcond to iterate two modes.
-(define_mode_iterator LSX_2[V2DF V4SF V2DI V4SI V8HI V16QI])
-
 ;; Only used for vilvh and splitting insert_d and copy_{u,s}.d.
 (define_mode_iterator LSX_D[V2DI V2DF])
 
@@ -533,34 +530,6 @@
   DONE;
 })
 
-(define_expand "vcondu"
-  [(match_operand:LSX 0 "register_operand")
-   (match_operand:LSX 1 "reg_or_m1_operand")
-   (match_operand:LSX 2 "reg_or_0_operand")
-   (match_operator 3 ""
- [(match_operand:ILSX 4 "register_operand")
-  (match_operand:ILSX 5 "register_operand")])]
-  "ISA_HAS_LSX
-   && (GET_MODE_NUNITS (mode) == GET_MODE_NUNITS (mode))"
-{
-  loongarch_expand_vec_cond_expr (mode, mode, operands);
-  DONE;
-})
-
-(define_expand "vcond"
-  [(match_operand:LSX 0 "register_operand")
-   (match_operand:LSX 1 "reg_or_m1_operand")
-   (match_operand:LSX 2 "reg_or_0_operand")
-   (match_operator 3 ""
- [(match_operand:LSX_2 4 "register_operand")
-  (match_operand:LSX_2 5 "register_operand")])]
-  "ISA_HAS_LSX
-   && (GET_MODE_NUNITS (mode) == GET_MODE_NUNITS (mode))"
-{
-  loongarch_expand_vec_cond_expr (mode, mode, operands);
-  DONE;
-})
-
 (define_expand "vcond_mask_"
   [(match_operand:LSX 0 "register_operand")
(match_operand:LSX 1 "reg_or_m1_operand")

[gcc r15-2879] LoongArch: Provide ashr lshr and ashl RTL pattern for vectors.

[LuluCheng via Gcc-cvs]

https://gcc.gnu.org/g:7bf4cd48d4494ba65680578e9c7ae9a1b809aeaf

commit r15-2879-g7bf4cd48d4494ba65680578e9c7ae9a1b809aeaf
Author: Lulu Cheng 
Date:   Thu Aug 8 09:59:28 2024 +0800

LoongArch: Provide ashr lshr and ashl RTL pattern for vectors.

We support vashr vlshr and vashl. However, in r15-1638 support optimize
x < 0 ? -1 : 0 into (signed) x >> 31 and x < 0 ? 1 : 0 into (unsigned) x >> 
31.
To support this optimization, vector ashr lshr and ashl need to be 
implemented.

gcc/ChangeLog:

* config/loongarch/loongarch.md (insn): Added rotatert rotr pairs.
* config/loongarch/simd.md (rotr3): Remove to ...
(3): This.

gcc/testsuite/ChangeLog:

* g++.target/loongarch/vect-ashr-lshr.C: New test.

Diff:
---
 gcc/config/loongarch/loongarch.md  |   1 +
 gcc/config/loongarch/simd.md   |  13 +-
 .../g++.target/loongarch/vect-ashr-lshr.C  | 147 +
 3 files changed, 155 insertions(+), 6 deletions(-)

diff --git a/gcc/config/loongarch/loongarch.md 
b/gcc/config/loongarch/loongarch.md
index 261cb7d9d574..73cdb38a4061 100644
--- a/gcc/config/loongarch/loongarch.md
+++ b/gcc/config/loongarch/loongarch.md
@@ -559,6 +559,7 @@
 (define_code_attr insn [(ashift "sll")
(ashiftrt "sra")
(lshiftrt "srl")
+   (rotatert "rotr")
(ior "or")
(xor "xor")
(and "and")
diff --git a/gcc/config/loongarch/simd.md b/gcc/config/loongarch/simd.md
index 00ff2823a4e2..45ea114220e3 100644
--- a/gcc/config/loongarch/simd.md
+++ b/gcc/config/loongarch/simd.md
@@ -306,14 +306,15 @@
 operands[4] = gen_reg_rtx (mode);
   });
 
-;; vrotri.{b/h/w/d}
+;; v{rotr/sll/sra/srl}i.{b/h/w/d}
 
-(define_insn "rotr3"
+(define_insn "3"
   [(set (match_operand:IVEC 0 "register_operand" "=f")
-   (rotatert:IVEC (match_operand:IVEC 1 "register_operand" "f")
-  (match_operand:SI 2 "const__operand")))]
-  ""
-  "vrotri.\t%0,%1,%2";
+   (shift_w:IVEC
+ (match_operand:IVEC 1 "register_operand" "f")
+ (match_operand:SI 2 "const__operand")))]
+  "ISA_HAS_LSX"
+  "vi.\t%0,%1,%2"
   [(set_attr "type" "simd_int_arith")
(set_attr "mode" "")])
 
diff --git a/gcc/testsuite/g++.target/loongarch/vect-ashr-lshr.C 
b/gcc/testsuite/g++.target/loongarch/vect-ashr-lshr.C
new file mode 100644
index ..bcef985fae2e
--- /dev/null
+++ b/gcc/testsuite/g++.target/loongarch/vect-ashr-lshr.C
@@ -0,0 +1,147 @@
+/* { dg-do compile } */
+/* { dg-options "-mlasx -O2" } */
+/* { dg-final { scan-assembler-times "vsrli.b" 2 } } */
+/* { dg-final { scan-assembler-times "vsrli.h" 2 } } */
+/* { dg-final { scan-assembler-times "vsrli.w" 2 } } */
+/* { dg-final { scan-assembler-times "vsrli.d" 2 } } */
+/* { dg-final { scan-assembler-times "vsrai.b" 2 } } */
+/* { dg-final { scan-assembler-times "vsrai.h" 2 } } */
+/* { dg-final { scan-assembler-times "vsrai.w" 2 } } */
+/* { dg-final { scan-assembler-times "vsrai.d" 2 } } */
+
+typedef signed char v16qi __attribute__((vector_size(16)));
+typedef signed char v32qi __attribute__((vector_size(32)));
+typedef short v8hi __attribute__((vector_size(16)));
+typedef short v16hi __attribute__((vector_size(32)));
+typedef int v4si __attribute__((vector_size(16)));
+typedef int v8si __attribute__((vector_size(32)));
+typedef long long v2di __attribute__((vector_size(16)));
+typedef long long v4di __attribute__((vector_size(32)));
+
+v16qi
+foo (v16qi a)
+{
+  v16qi const1_op = __extension__(v16qi){1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1};
+  v16qi const0_op = __extension__(v16qi){0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};
+  return a < const0_op ? const1_op : const0_op;
+}
+
+v32qi
+foo2 (v32qi a)
+{
+  v32qi const1_op = 
__extension__(v32qi){1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1};
+  v32qi const0_op = 
__extension__(v32qi){0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};
+  return a < const0_op ? const1_op : const0_op;
+}
+
+v8hi
+foo3 (v8hi a)
+{
+  v8hi const1_op = __extension__(v8hi){1,1,1,1,1,1,1,1};
+  v8hi const0_op = __extension__(v8hi){0,0,0,0,0,0,0,0};
+  return a < const0_op ? const1_op : const0_op;
+}
+
+v16hi
+foo4 (v16hi a)
+{
+  v16hi const1_op = __extension__(v16hi){1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1};
+  v16hi const0_op = __extension__(v16hi){0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};
+  return a < const0_op ? const1_op : const0_op;
+}
+
+v4si
+foo5 (v4si a)
+{
+  v4si const1_op = __extension__(v4si){1,1,1,1};
+  v4si const0_op = __extension__(v4si){0,0,0,0};
+  return a < const0_op ? const1_op : const0_op;
+}
+
+v8si
+foo6 (v8si a)
+{
+  v8si const1_op = __extension__(v8si){1,1,1,1,1,1,1,1};
+  v8si const0_op = __extension__(v8si){0,0,0,0,0,0,0,0};
+  return a < const0_op ? const1_op : const0_op;
+}
+
+v2di
+foo7 (v2di a)
+{
+  v2di const1_op = __extension__(v2di){1,1};
+  v2di co

[gcc r15-4130] LoongArch: Add support to annotate tablejump

[LuluCheng via Gcc-cvs]

https://gcc.gnu.org/g:0ee028f556401846d27edf0ff67647a1a7a26b6c

commit r15-4130-g0ee028f556401846d27edf0ff67647a1a7a26b6c
Author: Xi Ruoyao 
Date:   Thu Jul 11 19:43:48 2024 +0800

LoongArch: Add support to annotate tablejump

This is per the request from the kernel developers.  For generating the
ORC unwind info, the objtool program needs to analysis the control flow
of a .o file.  If a jump table is used, objtool has to correlate the
jump instruction with the table.

On x86 (where objtool was initially developed) it's simple: a relocation
entry natrually correlates them because one single instruction is used
for table-based jump.  But on an RISC machine objtool would have to
reconstruct the data flow if it must find out the correlation on its
own.

So, emit an additional section to store the correlation info as pairs of
addresses, each pair contains the address of a jump instruction (jr) and
the address of the jump table.  This is very trivial to implement in
GCC.

gcc/ChangeLog:

* config/loongarch/genopts/loongarch.opt.in
(mannotate-tablejump): New option.
* config/loongarch/loongarch.opt: Regenerate.
* config/loongarch/loongarch.md (tablejump): Emit
additional correlation info between the jump instruction and the
jump table, if -mannotate-tablejump.
* doc/invoke.texi: Document -mannotate-tablejump.

gcc/testsuite/ChangeLog:

* gcc.target/loongarch/jump-table-annotate.c: New test.

Suggested-by: Tiezhu Yang 

Diff:
---
 gcc/config/loongarch/genopts/loongarch.opt.in|  4 
 gcc/config/loongarch/loongarch.md| 12 +++-
 gcc/config/loongarch/loongarch.opt   |  4 
 gcc/doc/invoke.texi  | 13 -
 gcc/testsuite/gcc.target/loongarch/jump-table-annotate.c | 15 +++
 5 files changed, 46 insertions(+), 2 deletions(-)

diff --git a/gcc/config/loongarch/genopts/loongarch.opt.in 
b/gcc/config/loongarch/genopts/loongarch.opt.in
index d00950cb4f43..d5bbf01d85ed 100644
--- a/gcc/config/loongarch/genopts/loongarch.opt.in
+++ b/gcc/config/loongarch/genopts/loongarch.opt.in
@@ -301,3 +301,7 @@ default value is 4.
 ; CPUCFG independently, so we use bit flags to specify them.
 TargetVariable
 HOST_WIDE_INT la_isa_evolution = 0
+
+mannotate-tablejump
+Target Mask(ANNOTATE_TABLEJUMP) Save
+Annotate table jump instruction (jr {reg}) to correlate it with the jump table.
diff --git a/gcc/config/loongarch/loongarch.md 
b/gcc/config/loongarch/loongarch.md
index f70ca85bfb38..bd0825002387 100644
--- a/gcc/config/loongarch/loongarch.md
+++ b/gcc/config/loongarch/loongarch.md
@@ -3496,12 +3496,22 @@
   DONE;
 })
 
+(define_mode_attr mode_size [(DI "8") (SI "4")])
+
 (define_insn "@tablejump"
   [(set (pc)
(match_operand:P 0 "register_operand" "e"))
(use (label_ref (match_operand 1 "" "")))]
   ""
-  "jr\t%0"
+  {
+return TARGET_ANNOTATE_TABLEJUMP
+  ? "1:jr\t%0\n\t"
+   ".pushsection\t.discard.tablejump_annotate\n\t"
+   "\t.byte\t1b\n\t"
+   "\t.byte\t%1\n\t"
+   ".popsection"
+  : "jr\t%0";
+  }
   [(set_attr "type" "jump")
(set_attr "mode" "none")])
 
diff --git a/gcc/config/loongarch/loongarch.opt 
b/gcc/config/loongarch/loongarch.opt
index 91cb5236ad89..6a396b539c46 100644
--- a/gcc/config/loongarch/loongarch.opt
+++ b/gcc/config/loongarch/loongarch.opt
@@ -310,6 +310,10 @@ default value is 4.
 TargetVariable
 HOST_WIDE_INT la_isa_evolution = 0
 
+mannotate-tablejump
+Target Mask(ANNOTATE_TABLEJUMP) Save
+Annotate table jump instruction (jr {reg}) to correlate it with the jump table
+
 mfrecipe
 Target Mask(ISA_FRECIPE) Var(la_isa_evolution)
 Support frecipe.{s/d} and frsqrte.{s/d} instructions.
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 987b63601520..b2f16b45eaf4 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -1071,7 +1071,7 @@ Objective-C and Objective-C++ Dialects}.
 -mcmodel=@var{code-model} -mrelax -mpass-mrelax-to-as
 -mrecip  -mrecip=@var{opt} -mfrecipe -mno-frecipe -mdiv32 -mno-div32
 -mlam-bh -mno-lam-bh -mlamcas -mno-lamcas -mld-seq-sa -mno-ld-seq-sa
--mtls-dialect=@var{opt}}
+-mtls-dialect=@var{opt} -mannotate-tablejump -mno-annotate-tablejump}
 
 @emph{M32R/D Options}
 @gccoptlist{-m32r2  -m32rx  -m32r
@@ -27512,6 +27512,17 @@ Whether a load-load barrier (@code{dbar 0x700}) is 
needed.  When build with
 This option controls which tls dialect may be used for general dynamic and
 local dynamic TLS models.
 
+@opindex mannotate-tablejump
+@opindex mno-annotate-tablejump
+@item -mannotate-tablejump
+@itemx -mno-annotate-tablejump
+Create an annotation section @code{.discard.tablejump_annotate} to
+correlate the @code{jirl} instruction and the jump table when a jump
+table is used to optimize the @code{switch} statement.  Some ext

[gcc r15-4588] libffi: LoongArch: Fix soft-float builds of libffi

[LuluCheng via Gcc-cvs]

https://gcc.gnu.org/g:a616b7e1db7319c587b9c65fe9548c59c67d1234

commit r15-4588-ga616b7e1db7319c587b9c65fe9548c59c67d1234
Author: Yang Yujie 
Date:   Sat Jan 27 15:09:46 2024 +0800

libffi: LoongArch: Fix soft-float builds of libffi

This patch correspond to the upstream PR:
https://github.com/libffi/libffi/pull/817
And has been merged.

libffi/ChangeLog:

* src/loongarch64/ffi.c: Avoid defining floats
in struct call_context if the ABI is soft-float.

Diff:
---
 libffi/src/loongarch64/ffi.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/libffi/src/loongarch64/ffi.c b/libffi/src/loongarch64/ffi.c
index 140be3bc3dc4..01c2e18a395f 100644
--- a/libffi/src/loongarch64/ffi.c
+++ b/libffi/src/loongarch64/ffi.c
@@ -58,7 +58,9 @@
 */
 typedef struct call_context
 {
+#if !defined(__loongarch_soft_float)
   ABI_FLOAT fa[8];
+#endif
   size_t a[10];
 } call_context;

[gcc r15-5583] LoongArch: Remove redundant code.

[LuluCheng via Gcc-cvs]

https://gcc.gnu.org/g:a3a375b2d1801b1bed8cb6c5a12fdda491215fd1

commit r15-5583-ga3a375b2d1801b1bed8cb6c5a12fdda491215fd1
Author: Lulu Cheng 
Date:   Sat Nov 2 10:01:31 2024 +0800

LoongArch: Remove redundant code.

TARGET_ASM_ALIGNED_{HI,SI,QI}_OP are defined repeatedly and deleted.

gcc/ChangeLog:

* config/loongarch/loongarch-builtins.cc
(loongarch_builtin_vectorized_function): Delete.
(LARCH_GET_BUILTIN): Delete.
* config/loongarch/loongarch-protos.h
(loongarch_builtin_vectorized_function): Delete.
* config/loongarch/loongarch.cc
(TARGET_ASM_ALIGNED_HI_OP): Delete.
(TARGET_ASM_ALIGNED_SI_OP): Delete.
(TARGET_ASM_ALIGNED_DI_OP): Delete.

Diff:
---
 gcc/config/loongarch/loongarch-builtins.cc | 102 -
 gcc/config/loongarch/loongarch-protos.h|   1 -
 gcc/config/loongarch/loongarch.cc  |   8 ---
 3 files changed, 111 deletions(-)

diff --git a/gcc/config/loongarch/loongarch-builtins.cc 
b/gcc/config/loongarch/loongarch-builtins.cc
index c95bea6f0366..6820a68facca 100644
--- a/gcc/config/loongarch/loongarch-builtins.cc
+++ b/gcc/config/loongarch/loongarch-builtins.cc
@@ -2531,108 +2531,6 @@ loongarch_builtin_decl (unsigned int code, bool 
initialize_p ATTRIBUTE_UNUSED)
   return loongarch_builtin_decls[code];
 }
 
-/* Implement TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION.  */
-
-tree
-loongarch_builtin_vectorized_function (unsigned int fn, tree type_out,
-  tree type_in)
-{
-  machine_mode in_mode, out_mode;
-  int in_n, out_n;
-
-  if (TREE_CODE (type_out) != VECTOR_TYPE
-  || TREE_CODE (type_in) != VECTOR_TYPE
-  || !ISA_HAS_LSX)
-return NULL_TREE;
-
-  out_mode = TYPE_MODE (TREE_TYPE (type_out));
-  out_n = TYPE_VECTOR_SUBPARTS (type_out);
-  in_mode = TYPE_MODE (TREE_TYPE (type_in));
-  in_n = TYPE_VECTOR_SUBPARTS (type_in);
-
-  /* INSN is the name of the associated instruction pattern, without
- the leading CODE_FOR_.  */
-#define LARCH_GET_BUILTIN(INSN) \
-  loongarch_builtin_decls[loongarch_get_builtin_decl_index[CODE_FOR_##INSN]]
-
-  switch (fn)
-{
-CASE_CFN_CEIL:
-  if (out_mode == DFmode && in_mode == DFmode)
-{
-  if (out_n == 2 && in_n == 2)
-   return LARCH_GET_BUILTIN (lsx_vfrintrp_d);
-  if (out_n == 4 && in_n == 4)
-   return LARCH_GET_BUILTIN (lasx_xvfrintrp_d);
-}
-  if (out_mode == SFmode && in_mode == SFmode)
-{
-  if (out_n == 4 && in_n == 4)
-   return LARCH_GET_BUILTIN (lsx_vfrintrp_s);
-  if (out_n == 8 && in_n == 8)
-   return LARCH_GET_BUILTIN (lasx_xvfrintrp_s);
-}
-  break;
-
-CASE_CFN_TRUNC:
-  if (out_mode == DFmode && in_mode == DFmode)
-{
-  if (out_n == 2 && in_n == 2)
-   return LARCH_GET_BUILTIN (lsx_vfrintrz_d);
-  if (out_n == 4 && in_n == 4)
-   return LARCH_GET_BUILTIN (lasx_xvfrintrz_d);
-}
-  if (out_mode == SFmode && in_mode == SFmode)
-{
-  if (out_n == 4 && in_n == 4)
-   return LARCH_GET_BUILTIN (lsx_vfrintrz_s);
-  if (out_n == 8 && in_n == 8)
-   return LARCH_GET_BUILTIN (lasx_xvfrintrz_s);
-}
-  break;
-
-CASE_CFN_RINT:
-CASE_CFN_ROUND:
-  if (out_mode == DFmode && in_mode == DFmode)
-{
-  if (out_n == 2 && in_n == 2)
-   return LARCH_GET_BUILTIN (lsx_vfrint_d);
-  if (out_n == 4 && in_n == 4)
-   return LARCH_GET_BUILTIN (lasx_xvfrint_d);
-}
-  if (out_mode == SFmode && in_mode == SFmode)
-{
-  if (out_n == 4 && in_n == 4)
-   return LARCH_GET_BUILTIN (lsx_vfrint_s);
-  if (out_n == 8 && in_n == 8)
-   return LARCH_GET_BUILTIN (lasx_xvfrint_s);
-}
-  break;
-
-CASE_CFN_FLOOR:
-  if (out_mode == DFmode && in_mode == DFmode)
-{
-  if (out_n == 2 && in_n == 2)
-   return LARCH_GET_BUILTIN (lsx_vfrintrm_d);
-  if (out_n == 4 && in_n == 4)
-   return LARCH_GET_BUILTIN (lasx_xvfrintrm_d);
-}
-  if (out_mode == SFmode && in_mode == SFmode)
-{
-  if (out_n == 4 && in_n == 4)
-   return LARCH_GET_BUILTIN (lsx_vfrintrm_s);
-  if (out_n == 8 && in_n == 8)
-   return LARCH_GET_BUILTIN (lasx_xvfrintrm_s);
-}
-  break;
-
-default:
-  break;
-}
-
-  return NULL_TREE;
-}
-
 /* Take argument ARGNO from EXP's argument list and convert it into
an expand operand.  Store the operand in *OP.  */
 
diff --git a/gcc/config/loongarch/loongarch-protos.h 
b/gcc/config/loongarch/loongarch-protos.h
index 85f6e8943997..bc1b94b41d30 100644
--- a/gcc/config/loongarch/loongarch-protos.h
+++ b/gcc/config/loongarch/loongarch-protos.h
@@ -203,7 +203,6 @@ extern void loongarch_atomic_assign_expand_fenv (tree *, 
tree *, tree *);
 extern tree loongarch_builtin_decl (unsigned int, bool);
 extern rtx loongarch_expand_builtin (tree, rtx, rtx subtarget ATTRIBUTE_UNUSED,
   

[gcc r15-5584] LoongArch: Modify the document to remove options that don't exist.

[LuluCheng via Gcc-cvs]

https://gcc.gnu.org/g:92864116586aa1bb143f29ef4761f7efdfe48528

commit r15-5584-g92864116586aa1bb143f29ef4761f7efdfe48528
Author: Lulu Cheng 
Date:   Wed Oct 9 15:50:13 2024 +0800

LoongArch: Modify the document to remove options that don't exist.

gcc/ChangeLog:

* doc/invoke.texi: Remove the non-existent option
'-msmall-data-limit' and add a description of '-G'.

Diff:
---
 gcc/doc/invoke.texi | 10 +-
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index c62c6bc59030..0951901f50af 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -1068,7 +1068,7 @@ Objective-C and Objective-C++ Dialects}.
 -mbranch-cost=@var{n}  -mcheck-zero-division -mno-check-zero-division
 -mcond-move-int  -mno-cond-move-int
 -mcond-move-float  -mno-cond-move-float
--memcpy  -mno-memcpy -mstrict-align -mno-strict-align
+-memcpy  -mno-memcpy -mstrict-align -mno-strict-align -G @var{num}
 -mmax-inline-memcpy-size=@var{n}
 -mexplicit-relocs=@var{style} -mexplicit-relocs -mno-explicit-relocs
 -mdirect-extern-access -mno-direct-extern-access
@@ -27282,10 +27282,10 @@ Avoid or allow generating memory accesses that may 
not be aligned on a natural
 object boundary as described in the architecture specification. The default is
 @option{-mno-strict-align}.
 
-@opindex msmall-data-limit
-@item -msmall-data-limit=@var{number}
-Put global and static data smaller than @var{number} bytes into a special
-section (on some targets).  The default value is 0.
+@opindex G
+@item -G @var{num}
+Put global and static data smaller than @var{num} bytes into a small data
+section.  The default value is 0.
 
 @opindex mmax-inline-memcpy-size
 @item -mmax-inline-memcpy-size=@var{n}

[gcc r15-5817] LoongArch: testsuite: Fix loongarch/vect-frint-scalar.c.

[LuluCheng via Gcc-cvs]

https://gcc.gnu.org/g:4f650ef8d56ca61ed4d0df9bdcd810b6a2e808df

commit r15-5817-g4f650ef8d56ca61ed4d0df9bdcd810b6a2e808df
Author: Lulu Cheng 
Date:   Tue Nov 26 14:51:30 2024 +0800

LoongArch: testsuite: Fix loongarch/vect-frint-scalar.c.

In r15-5327, change the default language version for C compilation from
-std=gnu17 to -std=gnu23.

ISO C99 and C11 allow ceil, floor, round and trunc, and their float and
long double variants, to raise the “inexact” exception,
but ISO/IEC TS 18661-1:2014, the C bindings to IEEE 754-2008, as
integrated into ISO C23, does not allow these functions to do so.

So add '-ffp-int-builtin-inexact' to this test case.

gcc/testsuite/ChangeLog:

* gcc.target/loongarch/vect-frint-scalar.c: Add
'-ffp-int-builtin-inexact'.

Diff:
---
 gcc/testsuite/gcc.target/loongarch/vect-frint-scalar.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/testsuite/gcc.target/loongarch/vect-frint-scalar.c 
b/gcc/testsuite/gcc.target/loongarch/vect-frint-scalar.c
index c7cb40be7d42..dbcb9065ad48 100644
--- a/gcc/testsuite/gcc.target/loongarch/vect-frint-scalar.c
+++ b/gcc/testsuite/gcc.target/loongarch/vect-frint-scalar.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O2 -mlsx" } */
+/* { dg-options "-O2 -mlsx -ffp-int-builtin-inexact" } */
 
 #define test(func, suffix) \
 __typeof__ (1.##suffix) \

[gcc r15-5818] LoongArch: testsuite: Fix l{a}sx-andn-iorn.c.

[LuluCheng via Gcc-cvs]

https://gcc.gnu.org/g:4ad1c87ad25b3fb01caa731927b7b26357acf7b4

commit r15-5818-g4ad1c87ad25b3fb01caa731927b7b26357acf7b4
Author: Lulu Cheng 
Date:   Tue Nov 26 16:04:24 2024 +0800

LoongArch: testsuite: Fix l{a}sx-andn-iorn.c.

Add '-fdump-tree-optimized' to this testcases.

gcc/testsuite/ChangeLog:

* gcc.target/loongarch/lasx-andn-iorn.c:
Add '-fdump-tree-optimized'.
* gcc.target/loongarch/lsx-andn-iorn.c:
Likewise.

Diff:
---
 gcc/testsuite/gcc.target/loongarch/lasx-andn-iorn.c | 2 +-
 gcc/testsuite/gcc.target/loongarch/lsx-andn-iorn.c  | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/gcc/testsuite/gcc.target/loongarch/lasx-andn-iorn.c 
b/gcc/testsuite/gcc.target/loongarch/lasx-andn-iorn.c
index 4aa5f19a650e..86b04dbbb335 100644
--- a/gcc/testsuite/gcc.target/loongarch/lasx-andn-iorn.c
+++ b/gcc/testsuite/gcc.target/loongarch/lasx-andn-iorn.c
@@ -3,7 +3,7 @@
 #include "./lsx-andn-iorn.c"
 
 /* { dg-do compile } */
-/* { dg-options "-O2 -mlasx -ftree-vectorize" } */
+/* { dg-options "-O2 -mlasx -ftree-vectorize -fdump-tree-optimized" } */
 
 /* We should produce a BIT_ANDC and BIT_IORC here.  */
 
diff --git a/gcc/testsuite/gcc.target/loongarch/lsx-andn-iorn.c 
b/gcc/testsuite/gcc.target/loongarch/lsx-andn-iorn.c
index 7bceccd37d47..14838ab8bff0 100644
--- a/gcc/testsuite/gcc.target/loongarch/lsx-andn-iorn.c
+++ b/gcc/testsuite/gcc.target/loongarch/lsx-andn-iorn.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O2 -mlsx -ftree-vectorize" } */
+/* { dg-options "-O2 -mlsx -ftree-vectorize -fdump-tree-optimized" } */
 
 #ifndef N
 #define N 4

[gcc r15-5819] LoongArch: Mask shift offset when emit {xv, v}{srl, sll, sra} with sameimm vector

[LuluCheng via Gcc-cvs]

https://gcc.gnu.org/g:cd107c1603ad5e030ee1001ec244e4d0d3f0b79b

commit r15-5819-gcd107c1603ad5e030ee1001ec244e4d0d3f0b79b
Author: Jinyang He 
Date:   Thu Nov 28 09:26:25 2024 +0800

LoongArch: Mask shift offset when emit {xv, v}{srl, sll, sra} with sameimm 
vector

For {xv,v}{srl,sll,sra}, the constraint `vector_same_uimm6` cause overflow
in when emit {w,h,b}. Since the number of bits shifted is the remainder of
the register value, it is actually unnecessary to constrain the range.
Simply mask the shift number with the unit-bit-width, without any
constraint on the shift range.

gcc/ChangeLog:

* config/loongarch/constraints.md (Uuv6, Uuvx): Remove Uuv6,
add Uuvx as replicated vector const with unsigned range [0,umax].
* config/loongarch/lasx.md (xvsrl, xvsra, xvsll): Mask shift
offset by its unit bits.
* config/loongarch/lsx.md (vsrl, vsra, vsll): Likewise.
* config/loongarch/loongarch-protos.h
(loongarch_const_vector_same_int_p): Set default for low and high.
* config/loongarch/predicates.md: Replace reg_or_vector_same_uimm6
_operand to reg_or_vector_same_uimm_operand.

gcc/testsuite/ChangeLog:

* gcc.target/loongarch/vector/lasx/lasx-shift-sameimm-vec.c: New 
test.
* gcc.target/loongarch/vector/lsx/lsx-shift-sameimm-vec.c: New test.

Diff:
---
 gcc/config/loongarch/constraints.md| 14 ++---
 gcc/config/loongarch/lasx.md   | 60 ++
 gcc/config/loongarch/loongarch-protos.h|  5 +-
 gcc/config/loongarch/lsx.md| 60 ++
 gcc/config/loongarch/predicates.md |  8 +--
 .../loongarch/vector/lasx/lasx-shift-sameimm-vec.c | 72 ++
 .../loongarch/vector/lsx/lsx-shift-sameimm-vec.c   | 72 ++
 7 files changed, 254 insertions(+), 37 deletions(-)

diff --git a/gcc/config/loongarch/constraints.md 
b/gcc/config/loongarch/constraints.md
index 18da8b31f499..66ef1073fad2 100644
--- a/gcc/config/loongarch/constraints.md
+++ b/gcc/config/loongarch/constraints.md
@@ -334,19 +334,19 @@
   (and (match_code "const_vector")
(match_test "loongarch_const_vector_same_int_p (op, mode, -16, 15)")))
 
-(define_constraint "Uuv6"
-  "@internal
-   A replicated vector const in which the replicated value is in the range
-   [0,63]."
-  (and (match_code "const_vector")
-   (match_test "loongarch_const_vector_same_int_p (op, mode, 0, 63)")))
-
 (define_constraint "Urv8"
   "@internal
A replicated vector const with replicated byte values as well as elements"
   (and (match_code "const_vector")
(match_test "loongarch_const_vector_same_bytes_p (op, mode)")))
 
+(define_constraint "Uuvx"
+  "@internal
+   A replicated vector const in which the replicated value is in the unsigned
+   range [0,umax]."
+  (and (match_code "const_vector")
+   (match_test "loongarch_const_vector_same_int_p (op, mode)")))
+
 (define_memory_constraint "ZC"
   "A memory operand whose address is formed by a base register and offset
that is suitable for use in instructions with the same addressing mode
diff --git a/gcc/config/loongarch/lasx.md b/gcc/config/loongarch/lasx.md
index 457ed163f317..90778dd8ff96 100644
--- a/gcc/config/loongarch/lasx.md
+++ b/gcc/config/loongarch/lasx.md
@@ -1013,11 +1013,23 @@
   [(set (match_operand:ILASX 0 "register_operand" "=f,f")
(lshiftrt:ILASX
  (match_operand:ILASX 1 "register_operand" "f,f")
- (match_operand:ILASX 2 "reg_or_vector_same_uimm6_operand" "f,Uuv6")))]
+ (match_operand:ILASX 2 "reg_or_vector_same_uimm_operand" "f,Uuvx")))]
   "ISA_HAS_LASX"
-  "@
-   xvsrl.\t%u0,%u1,%u2
-   xvsrli.\t%u0,%u1,%E2"
+{
+  switch (which_alternative)
+{
+case 0:
+  return "xvsrl.\t%u0,%u1,%u2";
+case 1:
+  {
+   unsigned HOST_WIDE_INT val = UINTVAL (CONST_VECTOR_ELT (operands[2], 
0));
+   operands[2] = GEN_INT (val & (GET_MODE_UNIT_BITSIZE (mode) - 1));
+   return "xvsrli.\t%u0,%u1,%d2";
+  }
+default:
+  gcc_unreachable ();
+}
+}
   [(set_attr "type" "simd_shift")
(set_attr "mode" "")])
 
@@ -1026,11 +1038,23 @@
   [(set (match_operand:ILASX 0 "register_operand" "=f,f")
(ashiftrt:ILASX
  (match_operand:ILASX 1 "register_operand" "f,f")
- (match_operand:ILASX 2 "reg_or_vector_same_uimm6_operand" "f,Uuv6")))]
+ (match_operand:ILASX 2 "reg_or_vector_same_uimm_operand" "f,Uuvx")))]
   "ISA_HAS_LASX"
-  "@
-   xvsra.\t%u0,%u1,%u2
-   xvsrai.\t%u0,%u1,%E2"
+{
+  switch (which_alternative)
+{
+case 0:
+  return "xvsra.\t%u0,%u1,%u2";
+case 1:
+  {
+   unsigned HOST_WIDE_INT val = UINTVAL (CONST_VECTOR_ELT (operands[2], 
0));
+   operands[2] = GEN_INT (val & (GET_MODE_UNIT_BITSIZE (mode) - 1));
+   return "xvsrai.\t%u0,%u1,%d2";
+  }
+def

[gcc r15-6477] LoongArch: Implement vector cbranch optab for LSX and LASX

[LuluCheng via Gcc-cvs]

https://gcc.gnu.org/g:81d4707a00a2d74a9caf2d806e5b0ebe13e1247c

commit r15-6477-g81d4707a00a2d74a9caf2d806e5b0ebe13e1247c
Author: Jiahao Xu 
Date:   Wed Dec 25 17:59:36 2024 +0800

LoongArch: Implement vector cbranch optab for LSX and LASX

In order to support vectorization of loops with multiple exits, this
patch adds the implementation of the conditional branch optab for
LoongArch LSX/LASX instructions.

This patch causes the gen-vect-{2,25}.c tests to fail.  This is because
the support for vectorizing loops with multiple exits has vectorized
the loop checking the results.  The failure is due to an issue in the
test case's own implementation.

gcc/ChangeLog:

* config/loongarch/simd.md (cbranch4): New expander.

gcc/testsuite/ChangeLog:

* lib/target-supports.exp 
(check_effective_target_vect_early_break_hw,
check_effective_target_vect_early_break): Support LoongArch LSX.
* gcc.target/loongarch/vector/lasx/lasx-vseteqz.c: New test.
* gcc.target/loongarch/vector/lsx/lsx-vseteqz.c: New test.

Co-authored-by: Deng Jianbo 

Diff:
---
 gcc/config/loongarch/simd.md   | 30 ++
 .../loongarch/vector/lasx/lasx-vseteqz.c   | 14 ++
 .../gcc.target/loongarch/vector/lsx/lsx-vseteqz.c  | 15 +++
 gcc/testsuite/lib/target-supports.exp  |  2 ++
 4 files changed, 61 insertions(+)

diff --git a/gcc/config/loongarch/simd.md b/gcc/config/loongarch/simd.md
index fc3d98a43402..4d0069027535 100644
--- a/gcc/config/loongarch/simd.md
+++ b/gcc/config/loongarch/simd.md
@@ -516,6 +516,36 @@
   DONE;
 })
 
+;; cbranch
+(define_expand "cbranch4"
+ [(set (pc)
+   (if_then_else
+ (match_operator 0 "equality_operator"
+   [(match_operand:IVEC 1 "register_operand")
+(match_operand:IVEC 2 "reg_or_vector_same_val_operand")])
+ (label_ref (match_operand 3 ""))
+ (pc)))]
+ ""
+{
+  RTX_CODE code = GET_CODE (operands[0]);
+  rtx tmp = operands[1];
+  rtx const0 = CONST0_RTX (SImode);
+
+  /* If comparing against a non-zero vector we have to do a comparison first
+so we can have a != 0 comparison with the result.  */
+  if (operands[2] != CONST0_RTX (mode))
+{
+  tmp = gen_reg_rtx (mode);
+  emit_insn (gen_xor3 (tmp, operands[1], operands[2]));
+}
+
+  if (code == NE)
+emit_jump_insn (gen__bnz_v_b (operands[3], tmp, const0));
+  else
+emit_jump_insn (gen__bz_v_b (operands[3], tmp, const0));
+  DONE;
+})
+
 ; The LoongArch SX Instructions.
 (include "lsx.md")
 
diff --git a/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-vseteqz.c 
b/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-vseteqz.c
new file mode 100644
index ..1f69a80a784e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-vseteqz.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-O3 -mlasx" } */
+/* { dg-final { scan-assembler "\txvset.*.v\t" } } */
+/* { dg-final { scan-assembler  "bcnez" } } */
+
+int
+foo (int N)
+{
+  for (int i = 0; i <= N; i++)
+if (i * i == N)
+  return i;
+  return -1;
+}
+
diff --git a/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vseteqz.c 
b/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vseteqz.c
new file mode 100644
index ..2536bb7945eb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vseteqz.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-O3 -mlsx" } */
+/* { dg-final { scan-assembler "\tvset.*.v\t" } } */
+/* { dg-final { scan-assembler  "bcnez" } } */
+
+int
+foo (int N)
+{
+  for (int i = 0; i <= N; i++)
+if (i * i == N)
+  return i;
+
+  return -1;
+}
+
diff --git a/gcc/testsuite/lib/target-supports.exp 
b/gcc/testsuite/lib/target-supports.exp
index a16e9534ccdd..30ee528d2308 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -4431,6 +4431,7 @@ proc check_effective_target_vect_early_break { } {
|| [check_effective_target_sse4]
|| [istarget amdgcn-*-*]
|| [check_effective_target_riscv_v]
+   || [check_effective_target_loongarch_sx]
}}]
 }
 
@@ -4447,6 +4448,7 @@ proc check_effective_target_vect_early_break_hw { } {
|| [check_sse4_hw_available]
|| [istarget amdgcn-*-*]
|| [check_effective_target_riscv_v_ok]
+   || [check_effective_target_loongarch_sx_hw]
}}]
 }

[gcc r15-6487] LoongArch: Remove useless UNSPECs and define_mode_attrs

[LuluCheng via Gcc-cvs]

https://gcc.gnu.org/g:429d08fbfb14f7c733bb151d6f4782eb5c958cb9

commit r15-6487-g429d08fbfb14f7c733bb151d6f4782eb5c958cb9
Author: Guo Jie 
Date:   Mon Dec 30 10:34:56 2024 +0800

LoongArch: Remove useless UNSPECs and define_mode_attrs

gcc/ChangeLog:

* config/loongarch/lasx.md: Remove useless code.
* config/loongarch/lsx.md: Ditto.

Diff:
---
 gcc/config/loongarch/lasx.md | 66 
 gcc/config/loongarch/lsx.md  | 35 ---
 2 files changed, 101 deletions(-)

diff --git a/gcc/config/loongarch/lasx.md b/gcc/config/loongarch/lasx.md
index 071a5cb1733e..8afd0ffd7c55 100644
--- a/gcc/config/loongarch/lasx.md
+++ b/gcc/config/loongarch/lasx.md
@@ -37,16 +37,12 @@
   UNSPEC_LASX_XVFCVTH
   UNSPEC_LASX_XVFCVTL
   UNSPEC_LASX_XVFLOGB
-  UNSPEC_LASX_XVFRECIP
   UNSPEC_LASX_XVFRECIPE
-  UNSPEC_LASX_XVFRINT
   UNSPEC_LASX_XVFRSQRT
   UNSPEC_LASX_XVFRSQRTE
   UNSPEC_LASX_XVFTINT_U
-  UNSPEC_LASX_XVCLO
   UNSPEC_LASX_XVSAT_S
   UNSPEC_LASX_XVSAT_U
-  UNSPEC_LASX_XVREPLVE0
   UNSPEC_LASX_XVREPL128VEI
   UNSPEC_LASX_XVSRAR
   UNSPEC_LASX_XVSRARI
@@ -57,7 +53,6 @@
   UNSPEC_LASX_BRANCH
   UNSPEC_LASX_BRANCH_V
 
-  UNSPEC_LASX_MXVEXTW_U
   UNSPEC_LASX_XVSLLWIL_S
   UNSPEC_LASX_XVSLLWIL_U
   UNSPEC_LASX_XVSRAN
@@ -130,7 +125,6 @@
   UNSPEC_LASX_XVADD_Q
   UNSPEC_LASX_XVSUB_Q
   UNSPEC_LASX_XVREPLVE
-  UNSPEC_LASX_XVSHUF4
   UNSPEC_LASX_XVMSKGEZ
   UNSPEC_LASX_XVMSKNZ
   UNSPEC_LASX_XVEXTH_Q_D
@@ -212,11 +206,6 @@
(V8SI "V4SI")
(V4DI "V2DI")])
 
-;;attribute gives half float modes for vector modes.
-(define_mode_attr VFHMODE256
-   [(V8SF "V4SF")
-   (V4DF "V2DF")])
-
 ;; The attribute gives half int/float modes for vector modes.
 (define_mode_attr VHMODE256_ALL
   [(V32QI "V16QI")
@@ -252,20 +241,6 @@
(V4DF "V8DF")
(V4DI "V8DI")])
 
-;; This attribute gives the mode of the result for "copy_s_b, copy_u_b" etc.
-(define_mode_attr VRES256
-  [(V4DF "DF")
-   (V8SF "SF")
-   (V4DI "DI")
-   (V8SI "SI")
-   (V16HI "SI")
-   (V32QI "SI")])
-
-;; Only used with LASX_D iterator.
-(define_mode_attr lasx_d
-  [(V4DI "reg_or_0")
-   (V4DF "register")])
-
 ;; This attribute gives the 256 bit integer vector mode with same size.
 (define_mode_attr mode256_i
   [(V4DF "v4di")
@@ -275,14 +250,6 @@
(V16HI "v16hi")
(V32QI "v32qi")])
 
-
-;; This attribute gives the 256 bit float vector mode with same size.
-(define_mode_attr mode256_f
-  [(V4DF "v4df")
-   (V8SF "v8sf")
-   (V4DI "v4df")
-   (V8SI "v8sf")])
-
 ;; This attribute gives V32QI mode and V16HI mode with half size.
 (define_mode_attr mode256_i_half
   [(V32QI "v16qi")
@@ -344,14 +311,6 @@
(V16HI "h")
(V32QI "b")])
 
-(define_mode_attr flasxfmt_f
-  [(V4DF "d_f")
-   (V8SF "s_f")
-   (V4DI "d")
-   (V8SI "w")
-   (V16HI "h")
-   (V32QI "b")])
-
 ;; This attribute gives define_insn suffix for LASX instructions that need
 ;; distinction between integer and floating point.
 (define_mode_attr lasxfmt_f_wd
@@ -438,27 +397,6 @@
(V4DI  "uimm6")])
 
 
-(define_mode_attr d2lasxfmt
-  [(V8SI "q")
-   (V16HI "d")
-   (V32QI "w")])
-
-(define_mode_attr d2lasxfmt_u
-  [(V8SI "qu")
-   (V16HI "du")
-   (V32QI "wu")])
-
-(define_mode_attr VD2MODE256
-  [(V8SI "V4DI")
-   (V16HI "V4DI")
-   (V32QI "V8SI")])
-
-(define_mode_attr lasxfmt_wd
-  [(V4DI "d")
-   (V8SI "w")
-   (V16HI "w")
-   (V32QI "w")])
-
 ;; Half modes of all LASX vector modes, in lower-case.
 (define_mode_attr lasxhalf [(V32QI "v16qi")  (V16HI "v8hi")
  (V8SI "v4si")  (V4DI  "v2di")
@@ -1402,10 +1340,6 @@
(set_attr "cnv_mode" "")
(set_attr "mode" "")])
 
-(define_mode_attr FFQ256
-  [(V4SF "V16HI")
-   (V2DF "V8SI")])
-
 (define_insn "lasx_xvreplgr2vr_"
   [(set (match_operand:ILASX 0 "register_operand" "=f,f")
(vec_duplicate:ILASX
diff --git a/gcc/config/loongarch/lsx.md b/gcc/config/loongarch/lsx.md
index 878ff11e1ace..6c92e69d2350 100644
--- a/gcc/config/loongarch/lsx.md
+++ b/gcc/config/loongarch/lsx.md
@@ -39,15 +39,12 @@
   UNSPEC_LSX_VFCVTH
   UNSPEC_LSX_VFCVTL
   UNSPEC_LSX_VFLOGB
-  UNSPEC_LSX_VFRECIP
   UNSPEC_LSX_VFRECIPE
-  UNSPEC_LSX_VFRINT
   UNSPEC_LSX_VFRSQRT
   UNSPEC_LSX_VFRSQRTE
   UNSPEC_LSX_VFTINT_U
   UNSPEC_LSX_VSAT_S
   UNSPEC_LSX_VSAT_U
-  UNSPEC_LSX_VREPLVEI
   UNSPEC_LSX_VSRAR
   UNSPEC_LSX_VSRARI
   UNSPEC_LSX_VSRLR
@@ -167,22 +164,6 @@
(V8HI "wu")
(V16QI "hu")])
 
-(define_mode_attr d2lsxfmt
-  [(V4SI "q")
-   (V8HI "d")
-   (V16QI "w")])
-
-(define_mode_attr d2lsxfmt_u
-  [(V4SI "qu")
-   (V8HI "du")
-   (V16QI "wu")])
-
-;; The attribute gives two double modes for vector modes.
-(define_mode_attr VD2MODE
-  [(V4SI "V2DI")
-   (V8HI "V2DI")
-   (V16QI "V4SI")])
-
 ;; Only used for vilvh and splitting insert_d and copy_{u,s}.d.
 (define_mode_iterator LSX_D[V2DI V2DF])
 
@@ -299,24 +280,12 @@
(V8HI "h")
(V16QI "b")])
 
-(define_mode_attr flsxfmt_f
-  [(V2DF "d_f")
-   (V4SF "s_f")
-   (V2DI "d")
-   (V4SI "w")
-   (V8HI "h")
-

[gcc r15-6490] LoongArch: Adjust insn patterns for better combine

[LuluCheng via Gcc-cvs]

https://gcc.gnu.org/g:66b6e578d99ea20e2c67593be7a772d7710e05b2

commit r15-6490-g66b6e578d99ea20e2c67593be7a772d7710e05b2
Author: Guo Jie 
Date:   Mon Dec 30 10:38:35 2024 +0800

LoongArch: Adjust insn patterns for better combine

For some instruction patterns with commutative operands,
the order of operands needs to be adjusted to match the rules.

gcc/ChangeLog:

* config/loongarch/loongarch.md
(bytepick_d__rev): New combiner.
(bstrpick_alsl_paired): Reorder input operands.

gcc/testsuite/ChangeLog:

* gcc.target/loongarch/bstrpick_alsl_paired.c: New test.
* gcc.target/loongarch/bytepick_combine.c: New test.

Diff:
---
 gcc/config/loongarch/loongarch.md  | 23 --
 .../gcc.target/loongarch/bstrpick_alsl_paired.c| 21 
 .../gcc.target/loongarch/bytepick_combine.c| 11 +++
 3 files changed, 49 insertions(+), 6 deletions(-)

diff --git a/gcc/config/loongarch/loongarch.md 
b/gcc/config/loongarch/loongarch.md
index 7a110ca9de6e..1c294d8088a5 100644
--- a/gcc/config/loongarch/loongarch.md
+++ b/gcc/config/loongarch/loongarch.md
@@ -3111,13 +3111,14 @@
 
 (define_insn "bstrpick_alsl_paired"
   [(set (match_operand:DI 0 "register_operand" "=&r")
-   (plus:DI (match_operand:DI 1 "register_operand" "r")
-(and:DI (ashift:DI (match_operand:DI 2 "register_operand" "r")
-   (match_operand 3 "const_immalsl_operand" 
""))
-(match_operand 4 "immediate_operand" ""]
+   (plus:DI
+ (and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r")
+(match_operand 2 "const_immalsl_operand" ""))
+ (match_operand 3 "immediate_operand" ""))
+ (match_operand:DI 4 "register_operand" "r")))]
   "TARGET_64BIT
-   && ((INTVAL (operands[4]) >> INTVAL (operands[3])) == 0x)"
-  "bstrpick.d\t%0,%2,31,0\n\talsl.d\t%0,%0,%1,%3"
+   && ((INTVAL (operands[3]) >> INTVAL (operands[2])) == 0x)"
+  "bstrpick.d\t%0,%1,31,0\n\talsl.d\t%0,%0,%4,%2"
   [(set_attr "type" "arith")
(set_attr "mode" "DI")
(set_attr "insn_count" "2")])
@@ -4221,6 +4222,16 @@
   "bytepick.d\t%0,%1,%2,"
   [(set_attr "mode" "DI")])
 
+(define_insn "bytepick_d__rev"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+   (ior:DI (ashift (match_operand:DI 1 "register_operand" "r")
+   (const_int bytepick_d_ashift_amount))
+   (lshiftrt (match_operand:DI 2 "register_operand" "r")
+ (const_int ]
+  "TARGET_64BIT"
+  "bytepick.d\t%0,%2,%1,"
+  [(set_attr "mode" "DI")])
+
 (define_insn "bitrev_4b"
   [(set (match_operand:SI 0 "register_operand" "=r")
(unspec:SI [(match_operand:SI 1 "register_operand" "r")]
diff --git a/gcc/testsuite/gcc.target/loongarch/bstrpick_alsl_paired.c 
b/gcc/testsuite/gcc.target/loongarch/bstrpick_alsl_paired.c
new file mode 100644
index ..0bca3886c32a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/loongarch/bstrpick_alsl_paired.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-mabi=lp64d -O2 -fdump-rtl-combine" } */
+/* { dg-final { scan-rtl-dump "{bstrpick_alsl_paired}" "combine" } } */
+/* { dg-final { scan-assembler-not 
"alsl.d\t\\\$r\[0-9\]+,\\\$r\[0-9\]+,\\\$r0" } } */
+
+struct SA
+{
+  const char *a;
+  unsigned int b : 16;
+  unsigned int c : 16;
+};
+
+extern struct SA SAs[];
+
+void
+test ()
+{
+  unsigned int i;
+  for (i = 0; i < 100; i++)
+SAs[i].c = i;
+}
diff --git a/gcc/testsuite/gcc.target/loongarch/bytepick_combine.c 
b/gcc/testsuite/gcc.target/loongarch/bytepick_combine.c
new file mode 100644
index ..2a880829ca5a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/loongarch/bytepick_combine.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+/* { dg-final { scan-assembler-not "slli\\.d" } } */
+/* { dg-final { scan-assembler-not "srli\\.d" } } */
+/* { dg-final { scan-assembler-times "bytepick\\.d" 1 } } */
+
+unsigned long
+bytepick_d_n (unsigned long a, unsigned long b)
+{
+  return a >> 56 | b << 8;
+}

[gcc r15-6492] LoongArch: Add standard patterns uabd and sabd

[LuluCheng via Gcc-cvs]

https://gcc.gnu.org/g:ea7476516dbd600b09ab1f05f4ed977c1cc7bb95

commit r15-6492-gea7476516dbd600b09ab1f05f4ed977c1cc7bb95
Author: Guo Jie 
Date:   Mon Dec 30 15:12:02 2024 +0800

LoongArch: Add standard patterns uabd and sabd

gcc/ChangeLog:

* config/loongarch/lasx.md (lasx_xvabsd_s_): Remove.
(abd3): New insn pattern.
(lasx_xvabsd_u_): Remove.
* config/loongarch/loongarch-builtins.cc (CODE_FOR_lsx_vabsd_b):
Rename.
(CODE_FOR_lsx_vabsd_h): Ditto.
(CODE_FOR_lsx_vabsd_w): Ditto.
(CODE_FOR_lsx_vabsd_d): Ditto.
(CODE_FOR_lsx_vabsd_bu): Ditto.
(CODE_FOR_lsx_vabsd_hu): Ditto.
(CODE_FOR_lsx_vabsd_wu): Ditto.
(CODE_FOR_lsx_vabsd_du): Ditto.
(CODE_FOR_lasx_xvabsd_b): Ditto.
(CODE_FOR_lasx_xvabsd_h): Ditto.
(CODE_FOR_lasx_xvabsd_w): Ditto.
(CODE_FOR_lasx_xvabsd_d): Ditto.
(CODE_FOR_lasx_xvabsd_bu): Ditto.
(CODE_FOR_lasx_xvabsd_hu): Ditto.
(CODE_FOR_lasx_xvabsd_wu): Ditto.
(CODE_FOR_lasx_xvabsd_du): Ditto.
* config/loongarch/loongarch.md (u): Add smax/umax.
* config/loongarch/lsx.md (SU_MAX): New iterator.
(su_min): New attr.
(lsx_vabsd_s_): Remove.
(abd3): New insn pattern.
(lsx_vabsd_u_): Remove.

gcc/testsuite/ChangeLog:

* gcc.target/loongarch/abd-lasx.c: New test.
* gcc.target/loongarch/abd-lsx.c: New test.

Diff:
---
 gcc/config/loongarch/lasx.md  | 30 +---
 gcc/config/loongarch/loongarch-builtins.cc| 32 ++---
 gcc/config/loongarch/loongarch.md |  6 ++-
 gcc/config/loongarch/lsx.md   | 37 +++
 gcc/testsuite/gcc.target/loongarch/abd-lasx.c | 67 +++
 gcc/testsuite/gcc.target/loongarch/abd-lsx.c  | 67 +++
 6 files changed, 182 insertions(+), 57 deletions(-)

diff --git a/gcc/config/loongarch/lasx.md b/gcc/config/loongarch/lasx.md
index 3c8ee2704672..fdfd52f8a875 100644
--- a/gcc/config/loongarch/lasx.md
+++ b/gcc/config/loongarch/lasx.md
@@ -20,8 +20,6 @@
 ;;
 
 (define_c_enum "unspec" [
-  UNSPEC_LASX_XVABSD_S
-  UNSPEC_LASX_XVABSD_U
   UNSPEC_LASX_XVAVG_S
   UNSPEC_LASX_XVAVG_U
   UNSPEC_LASX_XVAVGR_S
@@ -1125,23 +1123,17 @@
   [(set_attr "type" "simd_int_arith")
(set_attr "mode" "")])
 
-(define_insn "lasx_xvabsd_s_"
+(define_insn "abd3"
   [(set (match_operand:ILASX 0 "register_operand" "=f")
-   (unspec:ILASX [(match_operand:ILASX 1 "register_operand" "f")
-  (match_operand:ILASX 2 "register_operand" "f")]
- UNSPEC_LASX_XVABSD_S))]
-  "ISA_HAS_LASX"
-  "xvabsd.\t%u0,%u1,%u2"
-  [(set_attr "type" "simd_int_arith")
-   (set_attr "mode" "")])
-
-(define_insn "lasx_xvabsd_u_"
-  [(set (match_operand:ILASX 0 "register_operand" "=f")
-   (unspec:ILASX [(match_operand:ILASX 1 "register_operand" "f")
-  (match_operand:ILASX 2 "register_operand" "f")]
- UNSPEC_LASX_XVABSD_U))]
+   (minus:ILASX
+ (SU_MAX:ILASX
+   (match_operand:ILASX 1 "register_operand" "f")
+   (match_operand:ILASX 2 "register_operand" "f"))
+ (:ILASX
+   (match_dup 1)
+   (match_dup 2]
   "ISA_HAS_LASX"
-  "xvabsd.\t%u0,%u1,%u2"
+  "xvabsd.\t%u0,%u1,%u2"
   [(set_attr "type" "simd_int_arith")
(set_attr "mode" "")])
 
@@ -4926,7 +4918,7 @@
   rtx t1 = gen_reg_rtx (V32QImode);
   rtx t2 = gen_reg_rtx (V16HImode);
   rtx t3 = gen_reg_rtx (V8SImode);
-  emit_insn (gen_lasx_xvabsd_u_bu (t1, operands[1], operands[2]));
+  emit_insn (gen_uabdv32qi3 (t1, operands[1], operands[2]));
   emit_insn (gen_lasx_xvhaddw_hu_bu (t2, t1, t1));
   emit_insn (gen_lasx_xvhaddw_wu_hu (t3, t2, t2));
   emit_insn (gen_addv8si3 (operands[0], t3, operands[3]));
@@ -4943,7 +4935,7 @@
   rtx t1 = gen_reg_rtx (V32QImode);
   rtx t2 = gen_reg_rtx (V16HImode);
   rtx t3 = gen_reg_rtx (V8SImode);
-  emit_insn (gen_lasx_xvabsd_s_b (t1, operands[1], operands[2]));
+  emit_insn (gen_sabdv32qi3 (t1, operands[1], operands[2]));
   emit_insn (gen_lasx_xvhaddw_hu_bu (t2, t1, t1));
   emit_insn (gen_lasx_xvhaddw_wu_hu (t3, t2, t2));
   emit_insn (gen_addv8si3 (operands[0], t3, operands[3]));
diff --git a/gcc/config/loongarch/loongarch-builtins.cc 
b/gcc/config/loongarch/loongarch-builtins.cc
index 593aca56a6d4..b7579ea1b911 100644
--- a/gcc/config/loongarch/loongarch-builtins.cc
+++ b/gcc/config/loongarch/loongarch-builtins.cc
@@ -462,14 +462,14 @@ AVAIL_ALL (lasx_frecipe, ISA_HAS_LASX && ISA_HAS_FRECIPE)
 #define CODE_FOR_lsx_vssub_hu CODE_FOR_lsx_vssub_u_hu
 #define CODE_FOR_lsx_vssub_wu CODE_FOR_lsx_vssub_u_wu
 #define CODE_FOR_lsx_vssub_du CODE_FOR_lsx_vssub_u_du
-#define CODE_FOR_lsx_vabsd_b CODE_FOR_lsx_vabsd_s_b
-#define CODE_FOR_lsx_vabsd_h CODE_FOR_ls

[gcc r15-6489] LoongArch: Fix bugs in insn patterns lasx_xvrepl128vei_b/h/w/d_internal

[LuluCheng via Gcc-cvs]

https://gcc.gnu.org/g:18d3b87b17fd6157e3aff64099a5bf84ea5f82f3

commit r15-6489-g18d3b87b17fd6157e3aff64099a5bf84ea5f82f3
Author: Guo Jie 
Date:   Mon Dec 30 10:37:57 2024 +0800

LoongArch: Fix bugs in insn patterns lasx_xvrepl128vei_b/h/w/d_internal

There are two aspects that affect the matching of instruction templates:

1. vec_duplicate is redundant in the following operations.
set (match_operand:V4DI ...)
(vec_duplicate:V4DI (vec_select:V4DI ...))

2. The range of values for testing predicate const_8_to_15_operand and
const_16_to_31_operand should be [8, 15] and [16, 31] respectively.

However, there is currently no suitable testcase to verify.

gcc/ChangeLog:

* config/loongarch/lasx.md: Remove useless vec_select.
* config/loongarch/predicates.md: Correct error predicate.

Diff:
---
 gcc/config/loongarch/lasx.md   | 76 ++
 gcc/config/loongarch/predicates.md |  4 +-
 2 files changed, 38 insertions(+), 42 deletions(-)

diff --git a/gcc/config/loongarch/lasx.md b/gcc/config/loongarch/lasx.md
index df91016037f9..1a320a05222f 100644
--- a/gcc/config/loongarch/lasx.md
+++ b/gcc/config/loongarch/lasx.md
@@ -2281,21 +2281,20 @@
 
 (define_insn "lasx_xvrepl128vei_b_internal"
   [(set (match_operand:V32QI 0 "register_operand" "=f")
-   (vec_duplicate:V32QI
- (vec_select:V32QI
-   (match_operand:V32QI 1 "register_operand" "f")
-   (parallel [(match_operand 2 "const_uimm4_operand" "")
-  (match_dup 2) (match_dup 2) (match_dup 2)
-  (match_dup 2) (match_dup 2) (match_dup 2)
-  (match_dup 2) (match_dup 2) (match_dup 2)
-  (match_dup 2) (match_dup 2) (match_dup 2)
-  (match_dup 2) (match_dup 2) (match_dup 2)
-  (match_operand 3 "const_16_to_31_operand" "")
-  (match_dup 3) (match_dup 3) (match_dup 3)
-  (match_dup 3) (match_dup 3) (match_dup 3)
-  (match_dup 3) (match_dup 3) (match_dup 3)
-  (match_dup 3) (match_dup 3) (match_dup 3)
-  (match_dup 3) (match_dup 3) (match_dup 3)]]
+   (vec_select:V32QI
+ (match_operand:V32QI 1 "register_operand" "f")
+ (parallel [(match_operand 2 "const_uimm4_operand" "")
+(match_dup 2) (match_dup 2) (match_dup 2)
+(match_dup 2) (match_dup 2) (match_dup 2)
+(match_dup 2) (match_dup 2) (match_dup 2)
+(match_dup 2) (match_dup 2) (match_dup 2)
+(match_dup 2) (match_dup 2) (match_dup 2)
+(match_operand 3 "const_16_to_31_operand" "")
+(match_dup 3) (match_dup 3) (match_dup 3)
+(match_dup 3) (match_dup 3) (match_dup 3)
+(match_dup 3) (match_dup 3) (match_dup 3)
+(match_dup 3) (match_dup 3) (match_dup 3)
+(match_dup 3) (match_dup 3) (match_dup 3)])))]
   "ISA_HAS_LASX && ((INTVAL (operands[3]) - INTVAL (operands[2])) == 16)"
   "xvrepl128vei.b\t%u0,%u1,%2"
   [(set_attr "type" "simd_splat")
@@ -2303,17 +2302,16 @@
 
 (define_insn "lasx_xvrepl128vei_h_internal"
   [(set (match_operand:V16HI 0 "register_operand" "=f")
-   (vec_duplicate:V16HI
- (vec_select:V16HI
-   (match_operand:V16HI 1 "register_operand" "f")
-   (parallel [(match_operand 2 "const_uimm3_operand" "")
-  (match_dup 2) (match_dup 2) (match_dup 2)
-  (match_dup 2) (match_dup 2) (match_dup 2)
-  (match_dup 2)
-  (match_operand 3 "const_8_to_15_operand" "")
-  (match_dup 3) (match_dup 3) (match_dup 3)
-  (match_dup 3) (match_dup 3) (match_dup 3)
-  (match_dup 3)]]
+   (vec_select:V16HI
+ (match_operand:V16HI 1 "register_operand" "f")
+ (parallel [(match_operand 2 "const_uimm3_operand" "")
+(match_dup 2) (match_dup 2) (match_dup 2)
+(match_dup 2) (match_dup 2) (match_dup 2)
+(match_dup 2)
+(match_operand 3 "const_8_to_15_operand" "")
+(match_dup 3) (match_dup 3) (match_dup 3)
+(match_dup 3) (match_dup 3) (match_dup 3)
+(match_dup 3)])))]
   "ISA_HAS_LASX && ((INTVAL (operands[3]) - INTVAL (operands[2])) == 8)"
   "xvrepl128vei.h\t%u0,%u1,%2"
   [(set_attr "type" "simd_splat")
@@ -2321,13 +2319,12 @@
 
 (define_insn "lasx_xvrepl128vei_w_internal"
   [(set (match_operand:V8SI 0 "register_operand" "=f")
-   (vec_duplicate:V8SI
- (vec_select:V8SI
-   (match_operand:V8SI 1 "register_operand" "f")
-   (parallel [(match_operand 2 "const_0_to_3_operand" "")
-  

[gcc r15-6488] LoongArch: Fix selector error in lasx_xvexth_h/w/d* patterns

[LuluCheng via Gcc-cvs]

https://gcc.gnu.org/g:693a5e6ae83f8606a5af674e18166060cd6a2e0c

commit r15-6488-g693a5e6ae83f8606a5af674e18166060cd6a2e0c
Author: Guo Jie 
Date:   Mon Dec 30 10:37:18 2024 +0800

LoongArch: Fix selector error in lasx_xvexth_h/w/d* patterns

The xvexth related instructions operate SEPARATELY according to
the high and low 128 bits, and sign/zero extend the upper half
of every 128 bits in src to the corresponding 128 bits in dest.

For xvexth.d.w, the rule for the first element of dest should be:
dest.D[0] = sign_extend (src.W[2] ,64);
instead of:
dest.D[0] = sign_extend (src.W[4] ,64);

gcc/ChangeLog:

* config/loongarch/lasx.md: Fix selector index.

Diff:
---
 gcc/config/loongarch/lasx.md | 14 +++---
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/gcc/config/loongarch/lasx.md b/gcc/config/loongarch/lasx.md
index 8afd0ffd7c55..df91016037f9 100644
--- a/gcc/config/loongarch/lasx.md
+++ b/gcc/config/loongarch/lasx.md
@@ -4183,10 +4183,10 @@
(any_extend:V16HI
  (vec_select:V16QI
(match_operand:V32QI 1 "register_operand" "f")
- (parallel [(const_int 16) (const_int 17)
-(const_int 18) (const_int 19)
-(const_int 20) (const_int 21)
-(const_int 22) (const_int 23)
+ (parallel [(const_int 8) (const_int 9)
+(const_int 10) (const_int 11)
+(const_int 12) (const_int 13)
+(const_int 14) (const_int 15)
 (const_int 24) (const_int 25)
 (const_int 26) (const_int 27)
 (const_int 28) (const_int 29)
@@ -4201,8 +4201,8 @@
(any_extend:V8SI
  (vec_select:V8HI
(match_operand:V16HI 1 "register_operand" "f")
-   (parallel [(const_int 8) (const_int 9)
-  (const_int 10) (const_int 11)
+   (parallel [(const_int 4) (const_int 5)
+  (const_int 6) (const_int 7)
   (const_int 12) (const_int 13)
   (const_int 14) (const_int 15)]]
   "ISA_HAS_LASX"
@@ -4215,7 +4215,7 @@
(any_extend:V4DI
  (vec_select:V4SI
(match_operand:V8SI 1 "register_operand" "f")
-   (parallel [(const_int 4) (const_int 5)
+   (parallel [(const_int 2) (const_int 3)
   (const_int 6) (const_int 7)]]
   "ISA_HAS_LASX"
   "xvexth.d.w\t%u0,%u1"

[gcc r15-6491] LoongArch: Add some vector pack/unpack patterns

[LuluCheng via Gcc-cvs]

https://gcc.gnu.org/g:66a88e0f1726024fe0d34badd1db45c1b2ccf042

commit r15-6491-g66a88e0f1726024fe0d34badd1db45c1b2ccf042
Author: Guo Jie 
Date:   Mon Dec 30 10:38:51 2024 +0800

LoongArch: Add some vector pack/unpack patterns

gcc/ChangeLog:

* config/loongarch/lasx.md (vec_unpacks_lo_): Redefine.
(vec_unpacku_lo_): Ditto.
(lasx_vext2xv_h_b): Replaced by vec_unpack_lo_v32qi.
(vec_unpack_lo_v32qi): New insn.
(lasx_vext2xv_w_h): Replaced by vec_unpack_lo_v16hi.
(vec_unpack_lo_v16qi_internal): New insn, for 128 bits.
(vec_unpack_lo_v16hi): New insn.
(lasx_vext2xv_d_w): Replaced by vec_unpack_lo_v8si.
(vec_unpack_lo_v8hi_internal): New insn, for 128 bits.
(vec_unpack_lo_v8si): New insn.
(vec_unpack_lo_v4si_internal): New insn, for 128 bits.
(vec_packs_float_v4di): New expander.
(vec_pack_sfix_trunc_v4df): Ditto.
(vec_unpacks_float_hi_v8si): Ditto.
(vec_unpacks_float_lo_v8si): Ditto.
(vec_unpack_sfix_trunc_hi_v8sf): Ditto.
(vec_unpack_sfix_trunc_lo_v8sf): Ditto.
* config/loongarch/loongarch-builtins.cc
(CODE_FOR_lsx_vftintrz_w_d): Rename.
(CODE_FOR_lsx_vftintrzh_l_s): Ditto.
(CODE_FOR_lsx_vftintrzl_l_s): Ditto.
(CODE_FOR_lsx_vffint_s_l): Ditto.
(CODE_FOR_lsx_vffinth_d_w): Ditto.
(CODE_FOR_lsx_vffintl_d_w): Ditto.
(CODE_FOR_lsx_vexth_h_b): Ditto.
(CODE_FOR_lsx_vexth_w_h): Ditto.
(CODE_FOR_lsx_vexth_d_w): Ditto.
(CODE_FOR_lsx_vexth_hu_bu): Ditto.
(CODE_FOR_lsx_vexth_wu_hu): Ditto.
(CODE_FOR_lsx_vexth_du_wu): Ditto.
(CODE_FOR_lsx_vfcvth_d_s): Ditto.
(CODE_FOR_lsx_vfcvtl_d_s): Ditto.
(CODE_FOR_lasx_vext2xv_h_b): Ditto.
(CODE_FOR_lasx_vext2xv_w_h): Ditto.
(CODE_FOR_lasx_vext2xv_d_w): Ditto.
(CODE_FOR_lasx_vext2xv_hu_bu): Ditto.
(CODE_FOR_lasx_vext2xv_wu_hu): Ditto.
(CODE_FOR_lasx_vext2xv_du_wu): Ditto.
(loongarch_expand_builtin_insn): Swap source operands in
CODE_FOR_lsx_vftintrz_w_d and CODE_FOR_lsx_vffint_s_l.
* config/loongarch/loongarch-protos.h
(loongarch_expand_vec_unpack): Remove useless parameter high_p.
* config/loongarch/loongarch.cc (loongarch_expand_vec_unpack):
Rewrite.
* config/loongarch/lsx.md (vec_unpacks_hi_v4sf): Redefine.
(vec_unpacks_lo_v4sf): Ditto.
(vec_unpacks_hi_): Ditto.
(vec_unpacku_hi_): Ditto.
(lsx_vfcvth_d_s): Replaced by vec_unpacks_hi_v4sf.
(lsx_vfcvtl_d_s): Replaced by vec_unpacks_lo_v4sf.
(lsx_vffint_s_l): Replaced by vec_packs_float_v2di.
(vec_packs_float_v2di): New insn.
(lsx_vftintrz_w_d): Replaced by vec_pack_sfix_trunc_v2df.
(vec_pack_sfix_trunc_v2df): New insn.
(lsx_vffinth_d_w): Replaced by vec_unpacks_float_hi_v4si.
(vec_unpacks_float_hi_v4si): New insn.
(lsx_vffintl_d_w): Replaced by vec_unpacks_float_lo_v4si.
(vec_unpacks_float_lo_v4si): New insn.
(lsx_vftintrzh_l_s): Replaced by vec_unpack_sfix_trunc_hi_v4sf.
(vec_unpack_sfix_trunc_hi_v4sf): New insn.
(lsx_vftintrzl_l_s): Replaced by vec_unpack_sfix_trunc_lo_v4sf.
(vec_unpack_sfix_trunc_lo_v4sf): New insn.
(lsx_vexth_h_b): Replaced by vec_unpack_hi_v16qi.
(vec_unpack_hi_v16qi): New insn.
(lsx_vexth_w_h): Replaced by vec_unpack_hi_v8hi.
(vec_unpack_hi_v8hi): New insn.
(lsx_vexth_d_w): Replaced by vec_unpack_hi_v4si.
(vec_unpack_hi_v4si): New insn.

gcc/testsuite/ChangeLog:

* gcc.target/loongarch/vec_pack_unpack_128.c: New test.
* gcc.target/loongarch/vec_pack_unpack_256.c: New test.

Diff:
---
 gcc/config/loongarch/lasx.md   | 140 +
 gcc/config/loongarch/loongarch-builtins.cc |  22 
 gcc/config/loongarch/loongarch-protos.h|   2 +-
 gcc/config/loongarch/loongarch.cc  |  49 +++-
 gcc/config/loongarch/lsx.md| 120 +++---
 .../gcc.target/loongarch/vec_pack_unpack_128.c | 120 ++
 .../gcc.target/loongarch/vec_pack_unpack_256.c | 118 +
 7 files changed, 436 insertions(+), 135 deletions(-)

diff --git a/gcc/config/loongarch/lasx.md b/gcc/config/loongarch/lasx.md
index 1a320a05222f..3c8ee2704672 100644
--- a/gcc/config/loongarch/lasx.md
+++ b/gcc/config/loongarch/lasx.md
@@ -463,17 +463,7 @@
(match_operand:ILASX_WHB 1 "register_operand")]
   "ISA_HAS_LASX"
 {
-  loongarch_expand_vec_unpack (operands, false/*unsigned_p*/

[gcc r15-6493] LoongArch: Optimize for conditional move operations

[LuluCheng via Gcc-cvs]

https://gcc.gnu.org/g:d55d40afd42a280c80729b538e3cce994f20961d

commit r15-6493-gd55d40afd42a280c80729b538e3cce994f20961d
Author: Guo Jie 
Date:   Mon Dec 30 10:39:13 2024 +0800

LoongArch: Optimize for conditional move operations

The optimization example is as follows.

From:
  if (condition)
dest += 1 << 16;
To:
  dest += (condition ? 1 : 0) << 16;

It does not use maskeqz and masknez, thus reducing the number of
instructions.

gcc/ChangeLog:

* config/loongarch/loongarch.cc
(loongarch_expand_conditional_move): Add some optimization
implementations based on noce_try_cmove_arith.

gcc/testsuite/ChangeLog:

* gcc.target/loongarch/conditional-move-opt-1.c: New test.
* gcc.target/loongarch/conditional-move-opt-2.c: New test.

Diff:
---
 gcc/config/loongarch/loongarch.cc  | 103 -
 .../gcc.target/loongarch/conditional-move-opt-1.c  |  58 
 .../gcc.target/loongarch/conditional-move-opt-2.c  |  42 +
 3 files changed, 202 insertions(+), 1 deletion(-)

diff --git a/gcc/config/loongarch/loongarch.cc 
b/gcc/config/loongarch/loongarch.cc
index 029616c1db2a..23cbd2eead97 100644
--- a/gcc/config/loongarch/loongarch.cc
+++ b/gcc/config/loongarch/loongarch.cc
@@ -5294,6 +5294,81 @@ loongarch_expand_conditional_move (rtx *operands)
 loongarch_emit_float_compare (&code, &op0, &op1);
   else
 {
+  /* Optimize to reduce the number of instructions for ternary operations.
+Mainly implemented based on noce_try_cmove_arith.
+For dest = (condition) ? value_if_true : value_if_false;
+the optimization requires:
+ a. value_if_false = var;
+ b. value_if_true = var OP C (a positive integer power of 2).
+
+Situations similar to the following:
+   if (condition)
+ dest += 1 << imm;
+to:
+   dest += (condition ? 1 : 0) << imm;  */
+
+  rtx_insn *insn;
+  HOST_WIDE_INT val = 0; /* The value of rtx C.  */
+  /* INSN with operands[2] as the output.  */
+  rtx_insn *value_if_true_insn = NULL;
+  /* INSN with operands[3] as the output.  */
+  rtx_insn *value_if_false_insn = NULL;
+  rtx value_if_true_insn_src = NULL_RTX;
+  /* Common operand var in value_if_true and value_if_false.  */
+  rtx comm_var = NULL_RTX;
+  bool can_be_optimized = false;
+
+  /* Search value_if_true_insn and value_if_false_insn.  */
+  struct sequence_stack *seq = get_current_sequence ()->next;
+  for (insn = seq->last; insn; insn = PREV_INSN (insn))
+   {
+ if (single_set (insn))
+   {
+ rtx set_dest = SET_DEST (single_set (insn));
+ if (rtx_equal_p (set_dest, operands[2]))
+   value_if_true_insn = insn;
+ else if (rtx_equal_p (set_dest, operands[3]))
+   value_if_false_insn = insn;
+ if (value_if_true_insn && value_if_false_insn)
+   break;
+   }
+   }
+
+  /* Check if the optimization conditions are met.  */
+  if (value_if_true_insn
+ && value_if_false_insn
+ /* Make sure that value_if_false and var are the same.  */
+ && BINARY_P (value_if_true_insn_src
+  = SET_SRC (single_set (value_if_true_insn)))
+ /* Make sure that both value_if_true and value_if_false
+has the same var.  */
+ && rtx_equal_p (XEXP (value_if_true_insn_src, 0),
+ SET_SRC (single_set (value_if_false_insn
+   {
+ comm_var = SET_SRC (single_set (value_if_false_insn));
+ rtx src = XEXP (value_if_true_insn_src, 1);
+ rtx imm = NULL_RTX;
+ if (CONST_INT_P (src))
+   imm = src;
+ else
+   for (insn = seq->last; insn; insn = PREV_INSN (insn))
+ {
+   rtx set = single_set (insn);
+   if (set && rtx_equal_p (SET_DEST (set), src))
+ {
+   imm = SET_SRC (set);
+   break;
+ }
+ }
+ if (imm && CONST_INT_P (imm))
+   {
+ val = INTVAL (imm);
+ /* Make sure that imm is a positive integer power of 2.  */
+ if (val > 0 && !(val & (val - 1)))
+   can_be_optimized = true;
+   }
+   }
+
   if (GET_MODE_SIZE (GET_MODE (op0)) < UNITS_PER_WORD)
{
  promote_op[0] = (REG_P (op0) && REG_P (operands[2]) &&
@@ -5314,22 +5389,48 @@ loongarch_expand_conditional_move (rtx *operands)
   op0_extend = op0;
   op1_extend = force_reg (word_mode, op1);
 
+  rtx target = gen_reg_rtx (GET_MODE (op0));
+
   if (code == EQ || code == NE)
{
  op0 = loongarch_zero_if_equal (op0, op1);
  op1 = const0_rtx;
+ /* For EQ, set target to 1 if op0 and op1 are the same,
+  

[gcc r15-6617] LoongArch: Optimize initializing fp resgister to zero

[LuluCheng via Gcc-cvs]

https://gcc.gnu.org/g:61400b669688848dc764d946a4d16fb51a27e286

commit r15-6617-g61400b669688848dc764d946a4d16fb51a27e286
Author: Deng Jianbo 
Date:   Tue Dec 31 19:33:23 2024 +0800

LoongArch: Optimize initializing fp resgister to zero

In LoongArch, currently uses instruction movgr2fr.{d|w} to move zero
from fixed-point register to floating-pointer regsiter for initializing
fp register to zero. When LSX or LASX is enabled, we can use instruction
vxor.v which has lower latency than instruction movgr2fr.{d|w} to set fp
register to zero directly.

gcc/ChangeLog:

* config/loongarch/loongarch.cc (loongarch_output_move):
Optimize instructions for initializing fp regsiter to zero.

gcc/testsuite/ChangeLog:

* gcc.target/loongarch/mov-zero-1.c: New test.
* gcc.target/loongarch/mov-zero-2.c: New test.

Diff:
---
 gcc/config/loongarch/loongarch.cc   |  2 ++
 gcc/testsuite/gcc.target/loongarch/mov-zero-1.c | 15 +++
 gcc/testsuite/gcc.target/loongarch/mov-zero-2.c | 15 +++
 3 files changed, 32 insertions(+)

diff --git a/gcc/config/loongarch/loongarch.cc 
b/gcc/config/loongarch/loongarch.cc
index 89237c377e77..d506354c48a0 100644
--- a/gcc/config/loongarch/loongarch.cc
+++ b/gcc/config/loongarch/loongarch.cc
@@ -4772,6 +4772,8 @@ loongarch_output_move (rtx dest, rtx src)
  gcc_unreachable ();
}
}
+ if (ISA_HAS_LSX && src == CONST0_RTX (GET_MODE (src)))
+   return "vxor.v\t%w0,%w0,%w0";
 
  return dbl_p ? "movgr2fr.d\t%0,%z1" : "movgr2fr.w\t%0,%z1";
}
diff --git a/gcc/testsuite/gcc.target/loongarch/mov-zero-1.c 
b/gcc/testsuite/gcc.target/loongarch/mov-zero-1.c
new file mode 100644
index ..4744f2f2fdb9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/loongarch/mov-zero-1.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mlsx" } */
+/* { dg-final { scan-assembler-times "vxor\\.v" 2 } } */
+
+double
+get_double_zero ()
+{
+  return 0;
+}
+
+float
+get_float_zero ()
+{
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.target/loongarch/mov-zero-2.c 
b/gcc/testsuite/gcc.target/loongarch/mov-zero-2.c
new file mode 100644
index ..6cb48052d0b4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/loongarch/mov-zero-2.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mno-lsx" } */
+/* { dg-final { scan-assembler-times "movgr2fr" 2 } } */
+
+double
+get_double_zero ()
+{
+  return 0;
+}
+
+float
+get_float_zero ()
+{
+  return 0;
+}

[gcc r15-6445] LoongArch: Support immediate_operand for vec_cmp

[LuluCheng via Gcc-cvs]

https://gcc.gnu.org/g:4731ead79fac259258dbb027090f3d085f518040

commit r15-6445-g4731ead79fac259258dbb027090f3d085f518040
Author: Jiahao Xu 
Date:   Wed Dec 18 15:45:17 2024 +0800

LoongArch: Support immediate_operand for vec_cmp

We can't vectorize the code into instructions like vslti.w that compare
with immediate_operand, because we miss immediate_operand support for
integer comparisons.

gcc/ChangeLog:

* config/loongarch/lasx.md (vec_cmp): Remove.
(vec_cmpu): Remove.
* config/loongarch/loongarch.cc (loongarch_expand_lsx_cmp):
Ensure vector comparison instructions support CMP_OP1.
* config/loongarch/lsx.md (vec_cmp): Remove.
(vec_cmpu): Remove.
* config/loongarch/simd.md (ALLVEC, allmode_i): New mode iterators.
(vec_cmp): New define_expand.
(vec_cmpu): Likewise.

gcc/testsuite/ChangeLog:

* gcc.target/loongarch/vector/lasx/lasx-vcond-3.c: New test.

Diff:
---
 gcc/config/loongarch/lasx.md   | 25 ---
 gcc/config/loongarch/loongarch.cc  | 12 
 gcc/config/loongarch/lsx.md| 25 ---
 gcc/config/loongarch/simd.md   | 40 +++
 .../loongarch/vector/lasx/lasx-vcond-3.c   | 81 ++
 5 files changed, 133 insertions(+), 50 deletions(-)

diff --git a/gcc/config/loongarch/lasx.md b/gcc/config/loongarch/lasx.md
index 90778dd8ff96..071a5cb1733e 100644
--- a/gcc/config/loongarch/lasx.md
+++ b/gcc/config/loongarch/lasx.md
@@ -162,9 +162,6 @@
   UNSPEC_LASX_XVILVL_INTERNAL
 ])
 
-;; All vector modes with 256 bits.
-(define_mode_iterator LASX [V4DF V8SF V4DI V8SI V16HI V32QI])
-
 ;; Only used for splitting insert_d and copy_{u,s}.d.
 (define_mode_iterator LASX_D [V4DI V4DF])
 
@@ -1365,28 +1362,6 @@
   [(set_attr "type" "simd_int_arith")
(set_attr "mode" "")])
 
-(define_expand "vec_cmp"
-  [(set (match_operand: 0 "register_operand")
-   (match_operator 1 ""
- [(match_operand:LASX 2 "register_operand")
-  (match_operand:LASX 3 "register_operand")]))]
-  "ISA_HAS_LASX"
-{
-  loongarch_expand_vec_cmp (operands);
-  DONE;
-})
-
-(define_expand "vec_cmpu"
-  [(set (match_operand: 0 "register_operand")
-   (match_operator 1 ""
- [(match_operand:ILASX 2 "register_operand")
-  (match_operand:ILASX 3 "register_operand")]))]
-  "ISA_HAS_LASX"
-{
-  loongarch_expand_vec_cmp (operands);
-  DONE;
-})
-
 (define_insn "lasx_xvfclass_"
   [(set (match_operand: 0 "register_operand" "=f")
(unspec: [(match_operand:FLASX 1 "register_operand" "f")]
diff --git a/gcc/config/loongarch/loongarch.cc 
b/gcc/config/loongarch/loongarch.cc
index 125ecc26c9cd..2d4290bc2d11 100644
--- a/gcc/config/loongarch/loongarch.cc
+++ b/gcc/config/loongarch/loongarch.cc
@@ -10399,19 +10399,29 @@ loongarch_expand_lsx_cmp (rtx dest, enum rtx_code 
cond, rtx op0, rtx op1)
   switch (cond)
{
case NE:
+ if (!loongarch_const_vector_same_int_p (op1, cmp_mode, -16, 15))
+   op1 = force_reg (cmp_mode, op1);
  cond = reverse_condition (cond);
  negate = true;
  break;
case EQ:
case LT:
case LE:
+ if (!loongarch_const_vector_same_int_p (op1, cmp_mode, -16, 15))
+   op1 = force_reg (cmp_mode, op1);
+ break;
case LTU:
case LEU:
+ if (!loongarch_const_vector_same_int_p (op1, cmp_mode, 0, 31))
+   op1 = force_reg (cmp_mode, op1);
  break;
case GE:
case GT:
case GEU:
case GTU:
+ /* Only supports reg-reg comparison.  */
+ if (!register_operand (op1, cmp_mode))
+   op1 = force_reg (cmp_mode, op1);
  std::swap (op0, op1);
  cond = swap_condition (cond);
  break;
@@ -10427,6 +10437,8 @@ loongarch_expand_lsx_cmp (rtx dest, enum rtx_code cond, 
rtx op0, rtx op1)
 case E_V2DFmode:
 case E_V8SFmode:
 case E_V4DFmode:
+  if (!register_operand (op1, cmp_mode))
+   op1 = force_reg (cmp_mode, op1);
   loongarch_emit_binary (cond, dest, op0, op1);
   break;
 
diff --git a/gcc/config/loongarch/lsx.md b/gcc/config/loongarch/lsx.md
index 2466d8c87bea..878ff11e1ace 100644
--- a/gcc/config/loongarch/lsx.md
+++ b/gcc/config/loongarch/lsx.md
@@ -183,9 +183,6 @@
(V8HI "V2DI")
(V16QI "V4SI")])
 
-;; All vector modes with 128 bits.
-(define_mode_iterator LSX  [V2DF V4SF V2DI V4SI V8HI V16QI])
-
 ;; Only used for vilvh and splitting insert_d and copy_{u,s}.d.
 (define_mode_iterator LSX_D[V2DI V2DF])
 
@@ -508,28 +505,6 @@
   DONE;
 })
 
-(define_expand "vec_cmp"
-  [(set (match_operand: 0 "register_operand")
-   (match_operator 1 ""
- [(match_operand:LSX 2 "register_operand")
-  (match_operand:LSX 3 "register_operand")]))]
-  "ISA_HAS_LSX"
-{
-  loongarch_expand_vec_cmp (operands);

[gcc r15-7386] LoongArch: Fix ICE caused by illegal calls to builtin functions [PR118561].

[LuluCheng via Gcc-cvs]

https://gcc.gnu.org/g:50d2bde68a097c2e9fb3bdd7e6664c899828

commit r15-7386-g50d2bde68a097c2e9fb3bdd7e6664c899828
Author: Lulu Cheng 
Date:   Wed Jan 22 17:57:21 2025 +0800

LoongArch: Fix ICE caused by illegal calls to builtin functions [PR118561].

PR target/118561

gcc/ChangeLog:

* config/loongarch/loongarch-builtins.cc
(loongarch_expand_builtin_lsx_test_branch):
NULL_RTX will not be returned when an error is detected.
(loongarch_expand_builtin): Likewise.

gcc/testsuite/ChangeLog:

* gcc.target/loongarch/pr118561.c: New test.

Diff:
---
 gcc/config/loongarch/loongarch-builtins.cc| 7 +--
 gcc/testsuite/gcc.target/loongarch/pr118561.c | 9 +
 2 files changed, 14 insertions(+), 2 deletions(-)

diff --git a/gcc/config/loongarch/loongarch-builtins.cc 
b/gcc/config/loongarch/loongarch-builtins.cc
index 92d995a916a9..1849b35357cb 100644
--- a/gcc/config/loongarch/loongarch-builtins.cc
+++ b/gcc/config/loongarch/loongarch-builtins.cc
@@ -2996,7 +2996,10 @@ loongarch_expand_builtin_lsx_test_branch (enum insn_code 
icode, tree exp)
 ops[1].value = force_reg (ops[1].mode, ops[1].value);
 
   if ((cbranch = maybe_gen_insn (icode, 3, ops)) == NULL_RTX)
-error ("failed to expand built-in function");
+{
+  error ("failed to expand built-in function");
+  return const0_rtx;
+}
 
   cmp_result = gen_reg_rtx (SImode);
 
@@ -3036,7 +3039,7 @@ loongarch_expand_builtin (tree exp, rtx target, rtx 
subtarget ATTRIBUTE_UNUSED,
 {
   error_at (EXPR_LOCATION (exp),
"built-in function %qD is not enabled", fndecl);
-  return target;
+  return target ? target : const0_rtx;
 }
 
   switch (d->builtin_type)
diff --git a/gcc/testsuite/gcc.target/loongarch/pr118561.c 
b/gcc/testsuite/gcc.target/loongarch/pr118561.c
new file mode 100644
index ..81a776eada39
--- /dev/null
+++ b/gcc/testsuite/gcc.target/loongarch/pr118561.c
@@ -0,0 +1,9 @@
+/* PR target/118561: ICE with -mfpu=none */
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=loongarch64 -mfpu=none" } */
+
+int
+test (void)
+{
+  return __builtin_loongarch_movfcsr2gr (0); /* { dg-error "built-in function 
'__builtin_loongarch_movfcsr2gr' is not enabled" } */
+}

[gcc r14-11275] LoongArch: Fix ICE caused by illegal calls to builtin functions [PR118561].

[LuluCheng via Gcc-cvs]

https://gcc.gnu.org/g:9a09fc9b8495f6cfa7b848b0064a96112dcb4a7f

commit r14-11275-g9a09fc9b8495f6cfa7b848b0064a96112dcb4a7f
Author: Lulu Cheng 
Date:   Wed Jan 22 17:57:21 2025 +0800

LoongArch: Fix ICE caused by illegal calls to builtin functions [PR118561].

PR target/118561

gcc/ChangeLog:

* config/loongarch/loongarch-builtins.cc
(loongarch_expand_builtin_lsx_test_branch):
NULL_RTX will not be returned when an error is detected.
(loongarch_expand_builtin): Likewise.

gcc/testsuite/ChangeLog:

* gcc.target/loongarch/pr118561.c: New test.

(cherry picked from commit 50d2bde68a097c2e9fb3bdd7e6664c899828)

Diff:
---
 gcc/config/loongarch/loongarch-builtins.cc| 7 +--
 gcc/testsuite/gcc.target/loongarch/pr118561.c | 9 +
 2 files changed, 14 insertions(+), 2 deletions(-)

diff --git a/gcc/config/loongarch/loongarch-builtins.cc 
b/gcc/config/loongarch/loongarch-builtins.cc
index 8a635938deed..669313ac9b7a 100644
--- a/gcc/config/loongarch/loongarch-builtins.cc
+++ b/gcc/config/loongarch/loongarch-builtins.cc
@@ -3074,7 +3074,10 @@ loongarch_expand_builtin_lsx_test_branch (enum insn_code 
icode, tree exp)
 ops[1].value = force_reg (ops[1].mode, ops[1].value);
 
   if ((cbranch = maybe_gen_insn (icode, 3, ops)) == NULL_RTX)
-error ("failed to expand built-in function");
+{
+  error ("failed to expand built-in function");
+  return const0_rtx;
+}
 
   cmp_result = gen_reg_rtx (SImode);
 
@@ -3114,7 +3117,7 @@ loongarch_expand_builtin (tree exp, rtx target, rtx 
subtarget ATTRIBUTE_UNUSED,
 {
   error_at (EXPR_LOCATION (exp),
"built-in function %qD is not enabled", fndecl);
-  return target;
+  return target ? target : const0_rtx;
 }
 
   switch (d->builtin_type)
diff --git a/gcc/testsuite/gcc.target/loongarch/pr118561.c 
b/gcc/testsuite/gcc.target/loongarch/pr118561.c
new file mode 100644
index ..81a776eada39
--- /dev/null
+++ b/gcc/testsuite/gcc.target/loongarch/pr118561.c
@@ -0,0 +1,9 @@
+/* PR target/118561: ICE with -mfpu=none */
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=loongarch64 -mfpu=none" } */
+
+int
+test (void)
+{
+  return __builtin_loongarch_movfcsr2gr (0); /* { dg-error "built-in function 
'__builtin_loongarch_movfcsr2gr' is not enabled" } */
+}

[gcc r15-5580] LoongArch: Make __builtin_lsx_vorn_v and __builtin_lasx_xvorn_v arguments and return values unsigned

[LuluCheng via Gcc-cvs]

https://gcc.gnu.org/g:ae7e25662f3f1255786f6bc13428d95b4ace6839

commit r15-5580-gae7e25662f3f1255786f6bc13428d95b4ace6839
Author: Xi Ruoyao 
Date:   Thu Oct 31 23:58:23 2024 +0800

LoongArch: Make __builtin_lsx_vorn_v and __builtin_lasx_xvorn_v arguments 
and return values unsigned

Align them with other vector bitwise builtins.

This may break programs directly invoking __builtin_lsx_vorn_v or
__builtin_lasx_xvorn_v, but doing so is not supported (as builtins are
not documented, only intrinsics are documented and users should use them
instead).

gcc/ChangeLog:

* config/loongarch/loongarch-builtins.cc (vorn_v, xvorn_v): Use
unsigned vector modes.
* config/loongarch/lsxintrin.h (__lsx_vorn_v): Cast arguments to
v16u8.
* config/loongarch/lasxintrin.h (__lasx_xvorn_v): Cast arguments
to v32u8.

gcc/testsuite/ChangeLog:

* gcc.target/loongarch/vector/lsx/lsx-builtin.c (__lsx_vorn_v):
Change arguments and return value to v16u8.
* gcc.target/loongarch/vector/lasx/lasx-builtin.c
(__lasx_xvorn_v): Change arguments and return value to v32u8.

Diff:
---
 gcc/config/loongarch/lasxintrin.h | 4 ++--
 gcc/config/loongarch/loongarch-builtins.cc| 4 ++--
 gcc/config/loongarch/lsxintrin.h  | 4 ++--
 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-builtin.c | 4 ++--
 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-builtin.c   | 4 ++--
 5 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/gcc/config/loongarch/lasxintrin.h 
b/gcc/config/loongarch/lasxintrin.h
index 16b21455d815..82ab625c58c5 100644
--- a/gcc/config/loongarch/lasxintrin.h
+++ b/gcc/config/loongarch/lasxintrin.h
@@ -3564,11 +3564,11 @@ __m256i __lasx_xvssrln_w_d (__m256i _1, __m256i _2)
 }
 
 /* Assembly instruction format:xd, xj, xk.  */
-/* Data types in instruction templates:  V32QI, V32QI, V32QI.  */
+/* Data types in instruction templates:  UV32QI, UV32QI, UV32QI.  */
 extern __inline __attribute__((__gnu_inline__, __always_inline__, 
__artificial__))
 __m256i __lasx_xvorn_v (__m256i _1, __m256i _2)
 {
-  return (__m256i)__builtin_lasx_xvorn_v ((v32i8)_1, (v32i8)_2);
+  return (__m256i)__builtin_lasx_xvorn_v ((v32u8)_1, (v32u8)_2);
 }
 
 /* Assembly instruction format:xd, i13.  */
diff --git a/gcc/config/loongarch/loongarch-builtins.cc 
b/gcc/config/loongarch/loongarch-builtins.cc
index 64529da8250c..c95bea6f0366 100644
--- a/gcc/config/loongarch/loongarch-builtins.cc
+++ b/gcc/config/loongarch/loongarch-builtins.cc
@@ -1569,7 +1569,7 @@ static const struct loongarch_builtin_description 
loongarch_builtins[] = {
   LSX_BUILTIN (vssrln_b_h, LARCH_V16QI_FTYPE_V8HI_V8HI),
   LSX_BUILTIN (vssrln_h_w, LARCH_V8HI_FTYPE_V4SI_V4SI),
   LSX_BUILTIN (vssrln_w_d, LARCH_V4SI_FTYPE_V2DI_V2DI),
-  LSX_BUILTIN (vorn_v, LARCH_V16QI_FTYPE_V16QI_V16QI),
+  LSX_BUILTIN (vorn_v, LARCH_UV16QI_FTYPE_UV16QI_UV16QI),
   LSX_BUILTIN (vldi, LARCH_V2DI_FTYPE_HI),
   LSX_BUILTIN (vshuf_b, LARCH_V16QI_FTYPE_V16QI_V16QI_V16QI),
   LSX_BUILTIN (vldx, LARCH_V16QI_FTYPE_CVPOINTER_DI),
@@ -2119,7 +2119,7 @@ static const struct loongarch_builtin_description 
loongarch_builtins[] = {
   LASX_BUILTIN (xvssrln_b_h, LARCH_V32QI_FTYPE_V16HI_V16HI),
   LASX_BUILTIN (xvssrln_h_w, LARCH_V16HI_FTYPE_V8SI_V8SI),
   LASX_BUILTIN (xvssrln_w_d, LARCH_V8SI_FTYPE_V4DI_V4DI),
-  LASX_BUILTIN (xvorn_v, LARCH_V32QI_FTYPE_V32QI_V32QI),
+  LASX_BUILTIN (xvorn_v, LARCH_UV32QI_FTYPE_UV32QI_UV32QI),
   LASX_BUILTIN (xvldi, LARCH_V4DI_FTYPE_HI),
   LASX_BUILTIN (xvldx, LARCH_V32QI_FTYPE_CVPOINTER_DI),
   LASX_NO_TARGET_BUILTIN (xvstx, LARCH_VOID_FTYPE_V32QI_CVPOINTER_DI),
diff --git a/gcc/config/loongarch/lsxintrin.h b/gcc/config/loongarch/lsxintrin.h
index 9ab8269db706..0f47b5929d17 100644
--- a/gcc/config/loongarch/lsxintrin.h
+++ b/gcc/config/loongarch/lsxintrin.h
@@ -4745,11 +4745,11 @@ __m128i __lsx_vssrln_w_d (__m128i _1, __m128i _2)
 }
 
 /* Assembly instruction format:vd, vj, vk.  */
-/* Data types in instruction templates:  V16QI, V16QI, V16QI.  */
+/* Data types in instruction templates:  UV16QI, UV16QI, UV16QI.  */
 extern __inline __attribute__((__gnu_inline__, __always_inline__, 
__artificial__))
 __m128i __lsx_vorn_v (__m128i _1, __m128i _2)
 {
-  return (__m128i)__builtin_lsx_vorn_v ((v16i8)_1, (v16i8)_2);
+  return (__m128i)__builtin_lsx_vorn_v ((v16u8)_1, (v16u8)_2);
 }
 
 /* Assembly instruction format:vd, i13.  */
diff --git a/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-builtin.c 
b/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-builtin.c
index b1a903b4a2b1..64ff870a4c57 100644
--- a/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-builtin.c
+++ b/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-builtin.c
@@ -3178,8 +3178,8 @@ __lasx_xvssrln_w_d (v4i64 _1, v4i64 _2)
 {
   return _

[gcc r15-5581] LoongArch: Fix clerical errors in lasx_xvreplgr2vr_* and lsx_vreplgr2vr_*.

[LuluCheng via Gcc-cvs]

https://gcc.gnu.org/g:f0cb64fb3f9d8e6f765007d4d62f1f5df73dc498

commit r15-5581-gf0cb64fb3f9d8e6f765007d4d62f1f5df73dc498
Author: Lulu Cheng 
Date:   Sat Nov 2 15:30:40 2024 +0800

LoongArch: Fix clerical errors in lasx_xvreplgr2vr_* and lsx_vreplgr2vr_*.

[x]vldi.{b/h/w/d} is not implemented in LoongArch.
Use the macro [x]vrepli.{b/h/w/d} to replace.

gcc/ChangeLog:

* config/loongarch/lasx.md: Fixed.
* config/loongarch/lsx.md: Fixed.

Diff:
---
 gcc/config/loongarch/lasx.md | 2 +-
 gcc/config/loongarch/lsx.md  | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/gcc/config/loongarch/lasx.md b/gcc/config/loongarch/lasx.md
index d37b2e83c21e..457ed163f317 100644
--- a/gcc/config/loongarch/lasx.md
+++ b/gcc/config/loongarch/lasx.md
@@ -1402,7 +1402,7 @@
   "ISA_HAS_LASX"
 {
   if (which_alternative == 1)
-return "xvldi.b\t%u0,0" ;
+return "xvrepli.b\t%u0,0";
 
   return "xvreplgr2vr.\t%u0,%z1";
 }
diff --git a/gcc/config/loongarch/lsx.md b/gcc/config/loongarch/lsx.md
index fcba28b07515..a9004290371f 100644
--- a/gcc/config/loongarch/lsx.md
+++ b/gcc/config/loongarch/lsx.md
@@ -1275,7 +1275,7 @@
   "ISA_HAS_LSX"
 {
   if (which_alternative == 1)
-return "vldi.\t%w0,0";
+return "vrepli.b\t%w0,0";
 
   return "vreplgr2vr.\t%w0,%z1";
 }

[gcc r14-10960] LoongArch: Make __builtin_lsx_vorn_v and __builtin_lasx_xvorn_v arguments and return values unsigned

[LuluCheng via Gcc-cvs]

https://gcc.gnu.org/g:bd82a141ee45589e3fc85cb25bc7c45a07449d7a

commit r14-10960-gbd82a141ee45589e3fc85cb25bc7c45a07449d7a
Author: Xi Ruoyao 
Date:   Thu Oct 31 23:58:23 2024 +0800

LoongArch: Make __builtin_lsx_vorn_v and __builtin_lasx_xvorn_v arguments 
and return values unsigned

Align them with other vector bitwise builtins.

This may break programs directly invoking __builtin_lsx_vorn_v or
__builtin_lasx_xvorn_v, but doing so is not supported (as builtins are
not documented, only intrinsics are documented and users should use them
instead).

gcc/ChangeLog:

* config/loongarch/loongarch-builtins.cc (vorn_v, xvorn_v): Use
unsigned vector modes.
* config/loongarch/lsxintrin.h (__lsx_vorn_v): Cast arguments to
v16u8.
* config/loongarch/lasxintrin.h (__lasx_xvorn_v): Cast arguments
to v32u8.

gcc/testsuite/ChangeLog:

* gcc.target/loongarch/vector/lsx/lsx-builtin.c (__lsx_vorn_v):
Change arguments and return value to v16u8.
* gcc.target/loongarch/vector/lasx/lasx-builtin.c
(__lasx_xvorn_v): Change arguments and return value to v32u8.

(cherry picked from commit ae7e25662f3f1255786f6bc13428d95b4ace6839)

Diff:
---
 gcc/config/loongarch/lasxintrin.h | 4 ++--
 gcc/config/loongarch/loongarch-builtins.cc| 4 ++--
 gcc/config/loongarch/lsxintrin.h  | 4 ++--
 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-builtin.c | 4 ++--
 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-builtin.c   | 4 ++--
 5 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/gcc/config/loongarch/lasxintrin.h 
b/gcc/config/loongarch/lasxintrin.h
index 16b21455d815..82ab625c58c5 100644
--- a/gcc/config/loongarch/lasxintrin.h
+++ b/gcc/config/loongarch/lasxintrin.h
@@ -3564,11 +3564,11 @@ __m256i __lasx_xvssrln_w_d (__m256i _1, __m256i _2)
 }
 
 /* Assembly instruction format:xd, xj, xk.  */
-/* Data types in instruction templates:  V32QI, V32QI, V32QI.  */
+/* Data types in instruction templates:  UV32QI, UV32QI, UV32QI.  */
 extern __inline __attribute__((__gnu_inline__, __always_inline__, 
__artificial__))
 __m256i __lasx_xvorn_v (__m256i _1, __m256i _2)
 {
-  return (__m256i)__builtin_lasx_xvorn_v ((v32i8)_1, (v32i8)_2);
+  return (__m256i)__builtin_lasx_xvorn_v ((v32u8)_1, (v32u8)_2);
 }
 
 /* Assembly instruction format:xd, i13.  */
diff --git a/gcc/config/loongarch/loongarch-builtins.cc 
b/gcc/config/loongarch/loongarch-builtins.cc
index fbe46833c9b7..8a635938deed 100644
--- a/gcc/config/loongarch/loongarch-builtins.cc
+++ b/gcc/config/loongarch/loongarch-builtins.cc
@@ -1568,7 +1568,7 @@ static const struct loongarch_builtin_description 
loongarch_builtins[] = {
   LSX_BUILTIN (vssrln_b_h, LARCH_V16QI_FTYPE_V8HI_V8HI),
   LSX_BUILTIN (vssrln_h_w, LARCH_V8HI_FTYPE_V4SI_V4SI),
   LSX_BUILTIN (vssrln_w_d, LARCH_V4SI_FTYPE_V2DI_V2DI),
-  LSX_BUILTIN (vorn_v, LARCH_V16QI_FTYPE_V16QI_V16QI),
+  LSX_BUILTIN (vorn_v, LARCH_UV16QI_FTYPE_UV16QI_UV16QI),
   LSX_BUILTIN (vldi, LARCH_V2DI_FTYPE_HI),
   LSX_BUILTIN (vshuf_b, LARCH_V16QI_FTYPE_V16QI_V16QI_V16QI),
   LSX_BUILTIN (vldx, LARCH_V16QI_FTYPE_CVPOINTER_DI),
@@ -2118,7 +2118,7 @@ static const struct loongarch_builtin_description 
loongarch_builtins[] = {
   LASX_BUILTIN (xvssrln_b_h, LARCH_V32QI_FTYPE_V16HI_V16HI),
   LASX_BUILTIN (xvssrln_h_w, LARCH_V16HI_FTYPE_V8SI_V8SI),
   LASX_BUILTIN (xvssrln_w_d, LARCH_V8SI_FTYPE_V4DI_V4DI),
-  LASX_BUILTIN (xvorn_v, LARCH_V32QI_FTYPE_V32QI_V32QI),
+  LASX_BUILTIN (xvorn_v, LARCH_UV32QI_FTYPE_UV32QI_UV32QI),
   LASX_BUILTIN (xvldi, LARCH_V4DI_FTYPE_HI),
   LASX_BUILTIN (xvldx, LARCH_V32QI_FTYPE_CVPOINTER_DI),
   LASX_NO_TARGET_BUILTIN (xvstx, LARCH_VOID_FTYPE_V32QI_CVPOINTER_DI),
diff --git a/gcc/config/loongarch/lsxintrin.h b/gcc/config/loongarch/lsxintrin.h
index 9ab8269db706..0f47b5929d17 100644
--- a/gcc/config/loongarch/lsxintrin.h
+++ b/gcc/config/loongarch/lsxintrin.h
@@ -4745,11 +4745,11 @@ __m128i __lsx_vssrln_w_d (__m128i _1, __m128i _2)
 }
 
 /* Assembly instruction format:vd, vj, vk.  */
-/* Data types in instruction templates:  V16QI, V16QI, V16QI.  */
+/* Data types in instruction templates:  UV16QI, UV16QI, UV16QI.  */
 extern __inline __attribute__((__gnu_inline__, __always_inline__, 
__artificial__))
 __m128i __lsx_vorn_v (__m128i _1, __m128i _2)
 {
-  return (__m128i)__builtin_lsx_vorn_v ((v16i8)_1, (v16i8)_2);
+  return (__m128i)__builtin_lsx_vorn_v ((v16u8)_1, (v16u8)_2);
 }
 
 /* Assembly instruction format:vd, i13.  */
diff --git a/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-builtin.c 
b/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-builtin.c
index b1a903b4a2b1..64ff870a4c57 100644
--- a/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-builtin.c
+++ b/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-builtin

[gcc r14-10961] LoongArch: Fix clerical errors in lasx_xvreplgr2vr_* and lsx_vreplgr2vr_*.

[LuluCheng via Gcc-cvs]

https://gcc.gnu.org/g:8cf47ce60cb02fa63e13ea0d5443906aa039101f

commit r14-10961-g8cf47ce60cb02fa63e13ea0d5443906aa039101f
Author: Lulu Cheng 
Date:   Sat Nov 2 15:30:40 2024 +0800

LoongArch: Fix clerical errors in lasx_xvreplgr2vr_* and lsx_vreplgr2vr_*.

[x]vldi.{b/h/w/d} is not implemented in LoongArch.
Use the macro [x]vrepli.{b/h/w/d} to replace.

gcc/ChangeLog:

* config/loongarch/lasx.md: Fixed.
* config/loongarch/lsx.md: Fixed.

(cherry picked from commit f0cb64fb3f9d8e6f765007d4d62f1f5df73dc498)

Diff:
---
 gcc/config/loongarch/lasx.md | 2 +-
 gcc/config/loongarch/lsx.md  | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/gcc/config/loongarch/lasx.md b/gcc/config/loongarch/lasx.md
index 7bd61f8ed5b7..94bbd0c26bbc 100644
--- a/gcc/config/loongarch/lasx.md
+++ b/gcc/config/loongarch/lasx.md
@@ -1439,7 +1439,7 @@
   "ISA_HAS_LASX"
 {
   if (which_alternative == 1)
-return "xvldi.b\t%u0,0" ;
+return "xvrepli.b\t%u0,0";
 
   return "xvreplgr2vr.\t%u0,%z1";
 }
diff --git a/gcc/config/loongarch/lsx.md b/gcc/config/loongarch/lsx.md
index 454cda47876b..5ee5845e84b0 100644
--- a/gcc/config/loongarch/lsx.md
+++ b/gcc/config/loongarch/lsx.md
@@ -1306,7 +1306,7 @@
   "ISA_HAS_LSX"
 {
   if (which_alternative == 1)
-return "vldi.\t%w0,0";
+return "vrepli.b\t%w0,0";
 
   return "vreplgr2vr.\t%w0,%z1";
 }

[gcc r15-6817] LoongArch: Generate the final immediate for lu12i.w, lu32i.d and lu52i.d

[LuluCheng via Gcc-cvs]

https://gcc.gnu.org/g:f30423ea8c2152dcee91056e75a4f3736cce6a6e

commit r15-6817-gf30423ea8c2152dcee91056e75a4f3736cce6a6e
Author: mengqinggang 
Date:   Fri Jan 10 10:27:09 2025 +0800

LoongArch: Generate the final immediate for lu12i.w, lu32i.d and lu52i.d

Generate 0x1010 instead of 0x101>>12 for lu12i.w. lu32i.d and lu52i.d 
use
the same processing.

gcc/ChangeLog:

* config/loongarch/lasx.md: Use new loongarch_output_move.
* config/loongarch/loongarch-protos.h (loongarch_output_move):
Change parameters from (rtx, rtx) to (rtx *).
* config/loongarch/loongarch.cc (loongarch_output_move):
Generate final immediate for lu12i.w and lu52i.d.
* config/loongarch/loongarch.md:
Generate final immediate for lu32i.d and lu52i.d.
* config/loongarch/lsx.md: Use new loongarch_output_move.

gcc/testsuite/ChangeLog:

* gcc.target/loongarch/imm-load.c: Not generate ">>".

Diff:
---
 gcc/config/loongarch/lasx.md  |  2 +-
 gcc/config/loongarch/loongarch-protos.h   |  2 +-
 gcc/config/loongarch/loongarch.cc | 14 ---
 gcc/config/loongarch/loongarch.md | 34 +--
 gcc/config/loongarch/lsx.md   |  2 +-
 gcc/testsuite/gcc.target/loongarch/imm-load.c |  1 +
 6 files changed, 36 insertions(+), 19 deletions(-)

diff --git a/gcc/config/loongarch/lasx.md b/gcc/config/loongarch/lasx.md
index edaf64eeb959..a37c85a25a4b 100644
--- a/gcc/config/loongarch/lasx.md
+++ b/gcc/config/loongarch/lasx.md
@@ -723,7 +723,7 @@
   [(set (match_operand:LASX 0 "nonimmediate_operand" "=f,f,R,*r,*f")
(match_operand:LASX 1 "move_operand" "fYGYI,R,f,*f,*r"))]
   "ISA_HAS_LASX"
-  { return loongarch_output_move (operands[0], operands[1]); }
+  { return loongarch_output_move (operands); }
   [(set_attr "type" "simd_move,simd_load,simd_store,simd_copy,simd_insert")
(set_attr "mode" "")
(set_attr "length" "8,4,4,4,4")])
diff --git a/gcc/config/loongarch/loongarch-protos.h 
b/gcc/config/loongarch/loongarch-protos.h
index fb544ad75ca1..6601f767dab4 100644
--- a/gcc/config/loongarch/loongarch-protos.h
+++ b/gcc/config/loongarch/loongarch-protos.h
@@ -86,7 +86,7 @@ extern void loongarch_split_move (rtx, rtx);
 extern bool loongarch_addu16i_imm12_operand_p (HOST_WIDE_INT, machine_mode);
 extern void loongarch_split_plus_constant (rtx *, machine_mode);
 extern void loongarch_split_vector_move (rtx, rtx);
-extern const char *loongarch_output_move (rtx, rtx);
+extern const char *loongarch_output_move (rtx *);
 #ifdef RTX_CODE
 extern void loongarch_expand_scc (rtx *);
 extern void loongarch_expand_vec_cmp (rtx *);
diff --git a/gcc/config/loongarch/loongarch.cc 
b/gcc/config/loongarch/loongarch.cc
index 24c19031026a..9d97f0216f0d 100644
--- a/gcc/config/loongarch/loongarch.cc
+++ b/gcc/config/loongarch/loongarch.cc
@@ -4721,8 +4721,10 @@ loongarch_split_vector_move (rtx dest, rtx src)
that SRC is operand 1 and DEST is operand 0.  */
 
 const char *
-loongarch_output_move (rtx dest, rtx src)
+loongarch_output_move (rtx *operands)
 {
+  rtx src = operands[1];
+  rtx dest = operands[0];
   enum rtx_code dest_code = GET_CODE (dest);
   enum rtx_code src_code = GET_CODE (src);
   machine_mode mode = GET_MODE (dest);
@@ -4877,13 +4879,19 @@ loongarch_output_move (rtx dest, rtx src)
   if (src_code == CONST_INT)
{
  if (LU12I_INT (src))
-   return "lu12i.w\t%0,%1>>12\t\t\t# %X1";
+   {
+ operands[1] = GEN_INT (INTVAL (operands[1]) >> 12);
+ return "lu12i.w\t%0,%1\t\t\t# %X1";
+   }
  else if (IMM12_INT (src))
return "addi.w\t%0,$r0,%1\t\t\t# %X1";
  else if (IMM12_INT_UNSIGNED (src))
return "ori\t%0,$r0,%1\t\t\t# %X1";
  else if (LU52I_INT (src))
-   return "lu52i.d\t%0,$r0,%X1>>52\t\t\t# %1";
+   {
+ operands[1] = GEN_INT (INTVAL (operands[1]) >> 52);
+ return "lu52i.d\t%0,$r0,%X1\t\t\t# %1";
+   }
  else
gcc_unreachable ();
}
diff --git a/gcc/config/loongarch/loongarch.md 
b/gcc/config/loongarch/loongarch.md
index 3eff4077160e..59f457703110 100644
--- a/gcc/config/loongarch/loongarch.md
+++ b/gcc/config/loongarch/loongarch.md
@@ -2209,7 +2209,7 @@
   "!TARGET_64BIT
&& (register_operand (operands[0], DImode)
|| reg_or_0_operand (operands[1], DImode))"
-  { return loongarch_output_move (operands[0], operands[1]); }
+  { return loongarch_output_move (operands); }
   "CONST_INT_P (operands[1]) && REG_P (operands[0]) && GP_REG_P (REGNO
   (operands[0]))"
   [(const_int 0)]
@@ -2228,7 +2228,9 @@
   "TARGET_64BIT
&& (register_operand (operands[0], DImode)
|| reg_or_0_operand (operands[1], DImode))"
-  { return loongarch_output_move (operands[0], operands[1]); }
+  {
+return loongarch_output_move (operands);

[gcc r15-6755] LoongArch: Opitmize the cost of vec_construct.

[LuluCheng via Gcc-cvs]

https://gcc.gnu.org/g:e8a57884ad4898fdec5c13a8933d73bcbaf06099

commit r15-6755-ge8a57884ad4898fdec5c13a8933d73bcbaf06099
Author: chenxiaolong 
Date:   Tue Jan 7 21:04:51 2025 +0800

LoongArch: Opitmize the cost of vec_construct.

When analyzing 525 on LoongArch architecture, it was found that the
for loop of hotspot function x264_pixel_satd_8x4 could not be quantized
256-bit due to the cost of vec_construct setting. After re-adjusting
vec_construct, the performance of 525 program was improved by 16.57%.
It was found that this function can be vectorized on the aarch64 and
x86 architectures, see [PR98138].

Co-Authored-By: Deng Jianbo .

gcc/ChangeLog:

* config/loongarch/loongarch.cc
(loongarch_builtin_vectorization_cost): Modify the
construction cost of the vec_construct vector.

gcc/testsuite/ChangeLog:

* gcc.target/loongarch/vect-slp-two-operator.c: New test.

Diff:
---
 gcc/config/loongarch/loongarch.cc  |  6 ++--
 .../gcc.target/loongarch/vect-slp-two-operator.c   | 38 ++
 2 files changed, 41 insertions(+), 3 deletions(-)

diff --git a/gcc/config/loongarch/loongarch.cc 
b/gcc/config/loongarch/loongarch.cc
index d506354c48a0..24c19031026a 100644
--- a/gcc/config/loongarch/loongarch.cc
+++ b/gcc/config/loongarch/loongarch.cc
@@ -4127,10 +4127,10 @@ loongarch_builtin_vectorization_cost (enum 
vect_cost_for_stmt type_of_cost,
 
   case vec_construct:
elements = TYPE_VECTOR_SUBPARTS (vectype);
-   if (ISA_HAS_LASX)
- return elements + 1;
+   if (LASX_SUPPORTED_MODE_P (mode) && !LSX_SUPPORTED_MODE_P (mode))
+ return elements / 2 + 3;
else
- return elements;
+ return elements / 2 + 1;
 
   default:
gcc_unreachable ();
diff --git a/gcc/testsuite/gcc.target/loongarch/vect-slp-two-operator.c 
b/gcc/testsuite/gcc.target/loongarch/vect-slp-two-operator.c
new file mode 100644
index ..43b46759902b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/loongarch/vect-slp-two-operator.c
@@ -0,0 +1,38 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mlasx -ftree-vectorize -fdump-tree-vect 
-fdump-tree-vect-details" } */
+
+typedef unsigned char uint8_t;
+typedef unsigned int uint32_t;
+
+#define HADAMARD4(d0, d1, d2, d3, s0, s1, s2, s3) \
+  {   \
+int t0 = s0 + s1; \
+int t1 = s0 - s1; \
+int t2 = s2 + s3; \
+int t3 = s2 - s3; \
+d0 = t0 + t2; \
+d1 = t1 + t3; \
+d2 = t0 - t2; \
+d3 = t1 - t3; \
+  }
+
+void sink (uint32_t tmp[4][4]);
+
+void
+x264_pixel_satd_8x4 (uint8_t *pix1, int i_pix1, uint8_t *pix2, int i_pix2)
+{
+  uint32_t tmp[4][4];
+  int sum = 0;
+  for (int i = 0; i < 4; i++, pix1 += i_pix1, pix2 += i_pix2)
+{
+  uint32_t a0 = (pix1[0] - pix2[0]) + ((pix1[4] - pix2[4]) << 16);
+  uint32_t a1 = (pix1[1] - pix2[1]) + ((pix1[5] - pix2[5]) << 16);
+  uint32_t a2 = (pix1[2] - pix2[2]) + ((pix1[6] - pix2[6]) << 16);
+  uint32_t a3 = (pix1[3] - pix2[3]) + ((pix1[7] - pix2[7]) << 16);
+  HADAMARD4 (tmp[i][0], tmp[i][1], tmp[i][2], tmp[i][3], a0, a1, a2, a3);
+}
+  sink (tmp);
+}
+
+/* { dg-final { scan-tree-dump "vectorizing stmts using SLP" "vect" } } */
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */

[gcc r15-7092] LoongArch: Implement target attribute.

[LuluCheng via Gcc-cvs]

https://gcc.gnu.org/g:c01ad91886527f685e67037ab4d36a6b0cd07c08

commit r15-7092-gc01ad91886527f685e67037ab4d36a6b0cd07c08
Author: Lulu Cheng 
Date:   Tue Jan 7 11:42:25 2025 +0800

LoongArch: Implement target attribute.

Add function attributes support for LoongArch.

Currently, the following items are supported:

__attribute__ ((target ("{no-}strict-align")))
__attribute__ ((target ("cmodel=")))
__attribute__ ((target ("arch=")))
__attribute__ ((target ("tune=")))
__attribute__ ((target ("{no-}lsx")))
__attribute__ ((target ("{no-}lasx")))

This implementation is derived from AArch64.

gcc/ChangeLog:

* attr-urls.def: Regenerate.
* config.gcc: Add loongarch-target-attr.o to extra_objs.
* config/loongarch/loongarch-protos.h
(loongarch_option_valid_attribute_p): Function declaration.
(loongarch_option_override_internal): Likewise.
* config/loongarch/loongarch.cc
(loongarch_option_override_internal): Delete the modifications
to target_option_default_node and target_option_current_node.
(loongarch_set_current_function): Add annotation information.
(loongarch_option_override): add assignment operations to
target_option_default_node and target_option_current_node.
(TARGET_OPTION_VALID_ATTRIBUTE_P): Define.
* config/loongarch/t-loongarch: Add compilation of target file
loongarch-target-attr.o.
* doc/extend.texi: Add description information of LoongArch
Function Attributes.
* config/loongarch/loongarch-target-attr.cc: New file.

gcc/testsuite/ChangeLog:

* gcc.target/loongarch/arch-func-attr-1.c: New test.
* gcc.target/loongarch/cmodel-func-attr-1.c: New test.
* gcc.target/loongarch/lasx-func-attr-1.c: New test.
* gcc.target/loongarch/lasx-func-attr-2.c: New test.
* gcc.target/loongarch/lsx-func-attr-1.c: New test.
* gcc.target/loongarch/lsx-func-attr-2.c: New test.
* gcc.target/loongarch/strict_align-func-attr-1.c: New test.
* gcc.target/loongarch/strict_align-func-attr-2.c: New test.
* gcc.target/loongarch/vector-func-attr-1.c: New test.
* gcc.target/loongarch/attr-check-error-message.c: New test.

Diff:
---
 gcc/attr-urls.def  |   6 +
 gcc/config.gcc |   2 +-
 gcc/config/loongarch/loongarch-protos.h|   2 +
 gcc/config/loongarch/loongarch-target-attr.cc  | 413 +
 gcc/config/loongarch/loongarch.cc  |  26 +-
 gcc/config/loongarch/t-loongarch   |   6 +
 gcc/doc/extend.texi|  75 
 .../gcc.target/loongarch/arch-func-attr-1.c|  16 +
 .../loongarch/attr-check-error-message.c   |  30 ++
 .../gcc.target/loongarch/cmodel-func-attr-1.c  |  17 +
 .../gcc.target/loongarch/lasx-func-attr-1.c|  15 +
 .../gcc.target/loongarch/lasx-func-attr-2.c|  12 +
 .../gcc.target/loongarch/lsx-func-attr-1.c |  15 +
 .../gcc.target/loongarch/lsx-func-attr-2.c |  12 +
 .../loongarch/strict_align-func-attr-1.c   |  17 +
 .../loongarch/strict_align-func-attr-2.c   |  17 +
 .../gcc.target/loongarch/vector-func-attr-1.c  |  15 +
 17 files changed, 691 insertions(+), 5 deletions(-)

diff --git a/gcc/attr-urls.def b/gcc/attr-urls.def
index e8417cff43c3..0d27400d218a 100644
--- a/gcc/attr-urls.def
+++ b/gcc/attr-urls.def
@@ -18,6 +18,7 @@ const attr_url_entry function_attrs[] = {
  { "amdgpu_hsa_kernel", 
"gcc/AMD-GCN-Function-Attributes.html#index-amdgpu_005fhsa_005fkernel-function-attribute_002c-AMD-GCN",
 "AMD GCN", 17},
  { "arch=", 
"gcc/AArch64-Function-Attributes.html#index-arch_003d-function-attribute_002c-AArch64",
 "AArch64", 5},
  { "arch=", 
"gcc/ARM-Function-Attributes.html#index-arch_003d-function-attribute_002c-ARM", 
"ARM", 5},
+ { "arch=", 
"gcc/LoongArch-Function-Attributes.html#index-arch_003d-function-attribute_002c-LoongArch",
 "LoongArch", 5},
  { "arch=", 
"gcc/RISC-V-Function-Attributes.html#index-arch_003d-function-attribute_002c-RISC-V",
 "RISC-V", 5},
  { "artificial", 
"gcc/Common-Function-Attributes.html#index-artificial-function-attribute", "", 
10},
  { "assume_aligned", 
"gcc/Common-Function-Attributes.html#index-assume_005faligned-function-attribute",
 "", 14},
@@ -29,6 +30,7 @@ const attr_url_entry function_attrs[] = {
  { "cdecl", 
"gcc/x86-Function-Attributes.html#index-cdecl-function-attribute_002c-x86-32", 
"x86-32", 5},
  { "cf_check", 
"gcc/x86-Function-Attributes.html#index-cf_005fcheck-function-attribute_002c-x86",
 "x86", 8},
  { "cmodel=", 
"gcc/AArch64-Function-Attributes.html#index-cmodel_003d-function-attribute_002c-AAr

[gcc r15-7093] LoongArch: Implement target pragma.

[LuluCheng via Gcc-cvs]

https://gcc.gnu.org/g:4d2a1c292611514dfa5de4cbdb8a426eb437c964

commit r15-7093-g4d2a1c292611514dfa5de4cbdb8a426eb437c964
Author: Lulu Cheng 
Date:   Tue Jan 7 12:00:12 2025 +0800

LoongArch: Implement target pragma.

The target pragmas defined correspond to the target function attributes.

This implementation is derived from AArch64.

gcc/ChangeLog:

* config/loongarch/loongarch-protos.h
(loongarch_reset_previous_fndecl):  Add function declaration.
(loongarch_save_restore_target_globals): Likewise.
(loongarch_register_pragmas): Likewise.
* config/loongarch/loongarch-target-attr.cc
(loongarch_option_valid_attribute_p): Optimize the processing
of attributes.
(loongarch_pragma_target_parse): New functions.
(loongarch_register_pragmas): Likewise.
* config/loongarch/loongarch.cc
(loongarch_reset_previous_fndecl): New functions.
(loongarch_set_current_function): When the old_tree is the same
as the new_tree, the rules for using registers, etc.,
are set according to the option values to ensure that the
pragma can be processed correctly.
* config/loongarch/loongarch.h (REGISTER_TARGET_PRAGMAS):
Define macro.
* doc/extend.texi: Supplemental Documentation.

gcc/testsuite/ChangeLog:

* gcc.target/loongarch/arch-func-attr-1.c: Add '#pragma'.
* gcc.target/loongarch/cmodel-func-attr-1.c: Likewise.
* gcc.target/loongarch/lasx-func-attr-1.c: Likewise.
* gcc.target/loongarch/lsx-func-attr-1.c: Likewise.
* gcc.target/loongarch/strict_align-func-attr-1.c: Likewise.
* gcc.target/loongarch/strict_align-func-attr-2.c: Likewise.
* gcc.target/loongarch/vector-func-attr-1.c: Likewise.
* gcc.target/loongarch/arch-pragma-attr-1.c: Likewise.
* gcc.target/loongarch/cmodel-pragma-attr-1.c: New test.
* gcc.target/loongarch/lasx-pragma-attr-1.c: New test.
* gcc.target/loongarch/lasx-pragma-attr-2.c: New test.
* gcc.target/loongarch/lsx-pragma-attr-1.c: New test.
* gcc.target/loongarch/lsx-pragma-attr-2.c: New test.
* gcc.target/loongarch/strict_align-pragma-attr-1.c: New test.
* gcc.target/loongarch/strict_align-pragma-attr-2.c: New test.
* gcc.target/loongarch/vector-pragma-attr-1.c: New test.
* gcc.target/loongarch/pragma-push-pop.c: New test.

Diff:
---
 gcc/config/loongarch/loongarch-protos.h|  3 ++
 gcc/config/loongarch/loongarch-target-attr.cc  | 59 ++
 gcc/config/loongarch/loongarch.cc  | 19 ---
 gcc/config/loongarch/loongarch.h   |  2 +
 gcc/doc/extend.texi| 13 +
 .../gcc.target/loongarch/arch-func-attr-1.c|  6 ++-
 .../gcc.target/loongarch/arch-pragma-attr-1.c  |  7 +++
 .../gcc.target/loongarch/cmodel-func-attr-1.c  |  4 ++
 .../gcc.target/loongarch/cmodel-pragma-attr-1.c|  7 +++
 .../gcc.target/loongarch/lasx-func-attr-1.c|  4 ++
 .../gcc.target/loongarch/lasx-pragma-attr-1.c  |  7 +++
 .../gcc.target/loongarch/lasx-pragma-attr-2.c  | 12 +
 .../gcc.target/loongarch/lsx-func-attr-1.c |  4 ++
 .../gcc.target/loongarch/lsx-pragma-attr-1.c   |  7 +++
 .../gcc.target/loongarch/lsx-pragma-attr-2.c   | 12 +
 .../gcc.target/loongarch/pragma-push-pop.c | 22 
 .../loongarch/strict_align-func-attr-1.c   |  4 ++
 .../loongarch/strict_align-func-attr-2.c   |  4 ++
 .../loongarch/strict_align-pragma-attr-1.c |  7 +++
 .../loongarch/strict_align-pragma-attr-2.c |  7 +++
 .../gcc.target/loongarch/vector-func-attr-1.c  |  4 ++
 .../gcc.target/loongarch/vector-pragma-attr-1.c|  7 +++
 22 files changed, 213 insertions(+), 8 deletions(-)

diff --git a/gcc/config/loongarch/loongarch-protos.h 
b/gcc/config/loongarch/loongarch-protos.h
index dba52beac00a..b99f949a004e 100644
--- a/gcc/config/loongarch/loongarch-protos.h
+++ b/gcc/config/loongarch/loongarch-protos.h
@@ -216,4 +216,7 @@ extern bool loongarch_explicit_relocs_p (enum 
loongarch_symbol_type);
 extern bool loongarch_symbol_extreme_p (enum loongarch_symbol_type);
 extern bool loongarch_option_valid_attribute_p (tree, tree, tree, int);
 extern void loongarch_option_override_internal (struct loongarch_target *, 
struct gcc_options *, struct gcc_options *);
+extern void loongarch_reset_previous_fndecl (void);
+extern void loongarch_save_restore_target_globals (tree new_tree);
+extern void loongarch_register_pragmas (void);
 #endif /* ! GCC_LOONGARCH_PROTOS_H */
diff --git a/gcc/config/loongarch/loongarch-target-attr.cc 
b/gcc/config/loongarch/loongarch-target-attr.cc
index 6bb1e6b753cb..cee7031ca1e7 100644
--- a/gcc/

[gcc r15-6432] LoongArch: Implement TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS hook

[LuluCheng via Gcc-cvs]

https://gcc.gnu.org/g:44e61bd7124c762e81d8c6e615fbe7c88f773637

commit r15-6432-g44e61bd7124c762e81d8c6e615fbe7c88f773637
Author: Jiahao Xu 
Date:   Tue Dec 17 10:41:48 2024 +0800

LoongArch: Implement TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS hook

The hook changes the allocno class to either FP_REGS or GR_REGS depending on
the mode of the register. This results in better register allocation 
overall,
fewer spills and reduced codesize - particularly in SPEC2017 lbm.

gcc/ChangeLog:

* config/loongarch/loongarch.cc
(loongarch_ira_change_pseudo_allocno_class): New function.
(TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS): Define macro.

Diff:
---
 gcc/config/loongarch/loongarch.cc | 38 ++
 1 file changed, 38 insertions(+)

diff --git a/gcc/config/loongarch/loongarch.cc 
b/gcc/config/loongarch/loongarch.cc
index 861558f07bcc..125ecc26c9cd 100644
--- a/gcc/config/loongarch/loongarch.cc
+++ b/gcc/config/loongarch/loongarch.cc
@@ -6989,6 +6989,40 @@ loongarch_secondary_reload (bool in_p ATTRIBUTE_UNUSED, 
rtx x,
   return NO_REGS;
 }
 
+/* Implement TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS.
+
+   The register allocator chooses ALL_REGS if FP_REGS and GR_REGS have the
+   same cost - even if ALL_REGS has a much higher cost.  ALL_REGS is also used
+   if the cost of both FP_REGS and GR_REGS is lower than the memory cost (in
+   this case the best class is the lowest cost one).  Using ALL_REGS
+   irrespectively of itself cost results in bad allocations with many redundant
+   int<->FP moves which are expensive on various cores.
+
+   To avoid this we don't allow ALL_REGS as the allocno class, but force a
+   decision between FP_REGS and GR_REGS.  We use the allocno class if it isn't
+   ALL_REGS.  Similarly, use the best class if it isn't ALL_REGS.  Otherwise 
Set
+   the allocno class depending on the mode.
+
+   This change has a similar effect to increasing the cost of FPR->GPR register
+   moves for integer modes so that they are higher than the cost of memory but
+   changing the allocno class is more reliable.  */
+
+static reg_class_t
+loongarch_ira_change_pseudo_allocno_class (int regno, reg_class_t 
allocno_class,
+  reg_class_t best_class)
+{
+  enum machine_mode mode;
+
+  if (allocno_class != ALL_REGS)
+return allocno_class;
+
+  if (best_class != ALL_REGS)
+return best_class;
+
+  mode = PSEUDO_REGNO_MODE (regno);
+  return FLOAT_MODE_P (mode) || VECTOR_MODE_P (mode) ? FP_REGS : GR_REGS;
+}
+
 /* Implement TARGET_VALID_POINTER_MODE.  */
 
 static bool
@@ -11148,6 +11182,10 @@ loongarch_asm_code_end (void)
 #undef TARGET_SECONDARY_RELOAD
 #define TARGET_SECONDARY_RELOAD loongarch_secondary_reload
 
+#undef TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS
+#define TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS \
+  loongarch_ira_change_pseudo_allocno_class
+
 #undef  TARGET_HAVE_SPECULATION_SAFE_VALUE
 #define TARGET_HAVE_SPECULATION_SAFE_VALUE speculation_safe_value_not_needed

[gcc r15-7581] LoongArch: Fix the issue of function jump out of range caused by crtbeginS.o [PR118844].

[LuluCheng via Gcc-cvs]

https://gcc.gnu.org/g:ae14d7d04da8c6cb542269722638071f999f94d8

commit r15-7581-gae14d7d04da8c6cb542269722638071f999f94d8
Author: Lulu Cheng 
Date:   Wed Feb 12 14:29:58 2025 +0800

LoongArch: Fix the issue of function jump out of range caused by 
crtbeginS.o [PR118844].

Due to the presence of R_LARCH_B26 in
/usr/lib/gcc/loongarch64-linux-gnu/14/crtbeginS.o, its addressing
range is [PC-128MiB, PC+128MiB-4]. This means that when the code
segment size exceeds 128MB, linking with lld will definitely fail
(ld will not fail because the order of the two is different).

The linking order:
  lld: crtbeginS.o + .text + .plt
  ld : .plt + crtbeginS.o + .text

To solve this issue, add '-mcmodel=extreme' when compiling crtbeginS.o.

PR target/118844

libgcc/ChangeLog:

* config/loongarch/t-crtstuff: Add '-mcmodel=extreme'
to CRTSTUFF_T_CFLAGS_S.

Diff:
---
 libgcc/config/loongarch/t-crtstuff | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/libgcc/config/loongarch/t-crtstuff 
b/libgcc/config/loongarch/t-crtstuff
index b8c36eb66b78..2a2489b7ef4e 100644
--- a/libgcc/config/loongarch/t-crtstuff
+++ b/libgcc/config/loongarch/t-crtstuff
@@ -3,3 +3,9 @@
 # to .eh_frame data from crtbeginT.o instead of the user-defined object
 # during static linking.
 CRTSTUFF_T_CFLAGS += -fno-omit-frame-pointer -fno-asynchronous-unwind-tables
+
+# As shown in the test case PR118844, when using lld for linking,
+# it fails due to B26 in crtbeginS.o causing the link to exceed the range.
+# Therefore, the issue was resolved by adding the compilation option
+# "-mcmodel=extreme" when compiling crtbeginS.o.
+CRTSTUFF_T_CFLAGS_S += -mcmodel=extreme

[gcc r14-11538] LoongArch: Add LoongArch architecture detection to __float128 support in libgfortran and libquadmath

[LuluCheng via Gcc-cvs]

https://gcc.gnu.org/g:73a62377ae638ce85c0a40327e67b41c861fb156

commit r14-11538-g73a62377ae638ce85c0a40327e67b41c861fb156
Author: Lulu Cheng 
Date:   Mon Apr 7 10:00:27 2025 +0800

LoongArch: Add LoongArch architecture detection to __float128 support in 
libgfortran and libquadmath [PR119408].

In GCC14, LoongArch added __float128 as an alias for _Float128.
In commit r15-8962, support for q/Q suffixes for 128-bit floating point
numbers.  This will cause the compiler to automatically link libquadmath
when compiling Fortran programs.  But on LoongArch `long double` is
IEEE quad, so there is no need to implement libquadmath.
This causes link failure.

PR target/119408

libgfortran/ChangeLog:

* acinclude.m4: When checking for __float128 support, determine
whether the current architecture is LoongArch.  If so, return false.
* configure: Regenerate.

libquadmath/ChangeLog:

* configure.ac: When checking for __float128 support, determine
whether the current architecture is LoongArch.  If so, return false.
* configure: Regenerate.

Sigend-off-by: Xi Ruoyao 
Sigend-off-by: Jakub Jelinek 

(cherry picked from commit 1534f0099c98ea14c08a401302b05edf2231f411)

Diff:
---
 libgfortran/acinclude.m4 | 4 
 libgfortran/configure| 8 
 libquadmath/configure| 8 
 libquadmath/configure.ac | 4 
 4 files changed, 24 insertions(+)

diff --git a/libgfortran/acinclude.m4 b/libgfortran/acinclude.m4
index a73207e54656..23fd621e5188 100644
--- a/libgfortran/acinclude.m4
+++ b/libgfortran/acinclude.m4
@@ -274,6 +274,10 @@ AC_DEFUN([LIBGFOR_CHECK_FLOAT128], [
   AC_CACHE_CHECK([whether we have a usable _Float128 type],
  libgfor_cv_have_float128, [
GCC_TRY_COMPILE_OR_LINK([
+#ifdef __loongarch__
+#error On LoongArch we should use long double instead; __float128 is only 
for porting existing code easier.
+#endif
+
 _Float128 foo (_Float128 x)
 {
  _Complex _Float128 z1, z2;
diff --git a/libgfortran/configure b/libgfortran/configure
index 774dd52fc95d..16bad2924749 100755
--- a/libgfortran/configure
+++ b/libgfortran/configure
@@ -30288,6 +30288,10 @@ else
   cat confdefs.h - <<_ACEOF >conftest.$ac_ext
 /* end confdefs.h.  */
 
+#ifdef __loongarch__
+#error On LoongArch we should use long double instead; __float128 is only 
for porting existing code easier.
+#endif
+
 _Float128 foo (_Float128 x)
 {
  _Complex _Float128 z1, z2;
@@ -30341,6 +30345,10 @@ fi
 cat confdefs.h - <<_ACEOF >conftest.$ac_ext
 /* end confdefs.h.  */
 
+#ifdef __loongarch__
+#error On LoongArch we should use long double instead; __float128 is only 
for porting existing code easier.
+#endif
+
 _Float128 foo (_Float128 x)
 {
  _Complex _Float128 z1, z2;
diff --git a/libquadmath/configure b/libquadmath/configure
index 49d70809218c..f82dd3d0d6d4 100755
--- a/libquadmath/configure
+++ b/libquadmath/configure
@@ -12843,6 +12843,10 @@ else
   cat confdefs.h - <<_ACEOF >conftest.$ac_ext
 /* end confdefs.h.  */
 
+#ifdef __loongarch__
+#error  On LoongArch we should use long double instead; __float128 is only 
for porting existing code easier.
+#endif
+
 #if (!defined(_ARCH_PPC)) || defined(__LONG_DOUBLE_IEEE128__)
 typedef _Complex float __attribute__((mode(TC))) __complex128;
 #else
@@ -12894,6 +12898,10 @@ fi
 cat confdefs.h - <<_ACEOF >conftest.$ac_ext
 /* end confdefs.h.  */
 
+#ifdef __loongarch__
+#error  On LoongArch we should use long double instead; __float128 is only 
for porting existing code easier.
+#endif
+
 #if (!defined(_ARCH_PPC)) || defined(__LONG_DOUBLE_IEEE128__)
 typedef _Complex float __attribute__((mode(TC))) __complex128;
 #else
diff --git a/libquadmath/configure.ac b/libquadmath/configure.ac
index 349be2607c64..c64a84892191 100644
--- a/libquadmath/configure.ac
+++ b/libquadmath/configure.ac
@@ -233,6 +233,10 @@ AM_CONDITIONAL(LIBQUAD_USE_SYMVER_SUN, [test 
"x$quadmath_use_symver" = xsun])
 
 AC_CACHE_CHECK([whether __float128 is supported], [libquad_cv_have_float128],
   [GCC_TRY_COMPILE_OR_LINK([
+#ifdef __loongarch__
+#error  On LoongArch we should use long double instead; __float128 is only 
for porting existing code easier.
+#endif
+
 #if (!defined(_ARCH_PPC)) || defined(__LONG_DOUBLE_IEEE128__)
 typedef _Complex float __attribute__((mode(TC))) __complex128;
 #else

[gcc r15-9324] LoongArch: Fix awk / sed usage for compatibility

[LuluCheng via Gcc-cvs]

https://gcc.gnu.org/g:6ed8c17c2bce631ae370d93164ceb6c1b5adf925

commit r15-9324-g6ed8c17c2bce631ae370d93164ceb6c1b5adf925
Author: Yang Yujie 
Date:   Mon Apr 7 10:31:46 2025 +0800

LoongArch: Fix awk / sed usage for compatibility

Tested with nawk, mawk, and gawk.

gcc/ChangeLog:

* config/loongarch/genopts/gen-evolution.awk: remove
usage of "asort".
* config/loongarch/genopts/genstr.sh: replace sed with awk.

Diff:
---
 gcc/config/loongarch/genopts/gen-evolution.awk | 12 +-
 gcc/config/loongarch/genopts/genstr.sh | 57 ++
 2 files changed, 40 insertions(+), 29 deletions(-)

diff --git a/gcc/config/loongarch/genopts/gen-evolution.awk 
b/gcc/config/loongarch/genopts/gen-evolution.awk
index 142b658fe7a3..507063bd50df 100644
--- a/gcc/config/loongarch/genopts/gen-evolution.awk
+++ b/gcc/config/loongarch/genopts/gen-evolution.awk
@@ -101,10 +101,18 @@ function gen_cpucfg_useful_idx()
 idx_list[j++] = i+0
 delete idx_bucket
 
-asort (idx_list)
+for (i = 1; i < j; i++) {
+t = i
+for (k = i + 1; k < j; k++)
+t = idx_list[k] < idx_list[t] ? k : t
+
+k = idx_list[t]
+idx_list[t] = idx_list[i]
+idx_list[i] = k
+}
 
 print "static constexpr int cpucfg_useful_idx[] = {"
-for (i in idx_list)
+for (i = 1; i < j; i++)
 printf("  %d,\n", idx_list[i])
 print "};"
 
diff --git a/gcc/config/loongarch/genopts/genstr.sh 
b/gcc/config/loongarch/genopts/genstr.sh
index 16c2edd4fa8a..97517da40f49 100755
--- a/gcc/config/loongarch/genopts/genstr.sh
+++ b/gcc/config/loongarch/genopts/genstr.sh
@@ -51,18 +51,18 @@ along with GCC; see the file COPYING3.  If not see
 #define LOONGARCH_STR_H
 EOF
 
-sed -e '/^$/n' -e 's@#.*$@@' -e '/^$/d' \
-   -e 's@^\([^ \t]\+\)[ \t]*\([^ \t]*\)@#define \1 "\2"@' \
-   loongarch-strings
+awk '/^#.*$/ { next } /^$/ { print; next }
+ { printf ("#define %s \"%s\"\n", $1, $2) }' \
+ loongarch-strings
 
 echo
 
-   # Generate the strings from isa-evolution.in.
-   awk '{
- a=$3
- gsub(/-/, "_", a)
- print("#define OPTSTR_"toupper(a)"\t\""$3"\"")
-   }' isa-evolution.in
+# Generate the strings from isa-evolution.in.
+awk '{
+  a=$3
+  gsub(/-/, "_", a)
+  print("#define OPTSTR_"toupper(a)"\t\""$3"\"")
+}' isa-evolution.in
 
 echo
 echo "#endif /* LOONGARCH_STR_H */"
@@ -73,18 +73,8 @@ EOF
 # according to the key-value pairs defined in loongarch-strings.
 
 gen_options() {
-
-sed -e '/^$/n' -e 's@#.*$@@' -e '/^$/d' \
-   -e 's@^\([^ \t]\+\)[ \t]*\([^ \t]*\)@\1="\2"@' \
-   loongarch-strings | { \
-
-   # read the definitions
-   while read -r line; do
-   eval "$line"
-   done
-
-   # print a header
-   cat << EOF
+# print a header
+cat << EOF
 ; Generated by "genstr" from the template "loongarch.opt.in"
 ; and definitions from "loongarch-strings" and "isa-evolution.in".
 ;
@@ -95,12 +85,25 @@ gen_options() {
 ;
 EOF
 
-   # make the substitutions
-   sed -e 's@"@\\"@g' -e 's/@@\([^@]\+\)@@/${\1}/g' loongarch.opt.in | \
-   while read -r line; do
-   eval "echo \"$line\""
-   done
-}
+# Generate loongarch.opt.
+awk 'BEGIN {
+delete strtab
+while (getline < "loongarch-strings" > 0) {
+if ($0 ~ /^#.*$/ || $0 ~ /^$/) continue
+strtab[$1] = $2
+}
+}
+{
+n = split($0, tmp, "@@")
+for (i = 2; i <= n; i += 2)
+tmp[i] = strtab[tmp[i]]
+
+for (i = 1; i <= n; i++)
+printf("%s", tmp[i])
+printf ("\n")
+
+}' loongarch.opt.in
+
 
 # Generate the strings from isa-evolution.in.
 awk '{

[gcc r14-11545] LoongArch: Fix awk / sed usage for compatibility

[LuluCheng via Gcc-cvs]

https://gcc.gnu.org/g:4d5fd1176d1a5d387dbc53f00324f86a1afa2ecb

commit r14-11545-g4d5fd1176d1a5d387dbc53f00324f86a1afa2ecb
Author: Yang Yujie 
Date:   Mon Apr 7 10:31:46 2025 +0800

LoongArch: Fix awk / sed usage for compatibility

Tested with nawk, mawk, and gawk.

gcc/ChangeLog:

* config/loongarch/genopts/gen-evolution.awk: remove
usage of "asort".
* config/loongarch/genopts/genstr.sh: replace sed with awk.

(cherry picked from commit 6ed8c17c2bce631ae370d93164ceb6c1b5adf925)

Diff:
---
 gcc/config/loongarch/genopts/gen-evolution.awk | 12 +-
 gcc/config/loongarch/genopts/genstr.sh | 57 ++
 2 files changed, 40 insertions(+), 29 deletions(-)

diff --git a/gcc/config/loongarch/genopts/gen-evolution.awk 
b/gcc/config/loongarch/genopts/gen-evolution.awk
index a2ecd9a8bcf5..97f7b0a33c29 100644
--- a/gcc/config/loongarch/genopts/gen-evolution.awk
+++ b/gcc/config/loongarch/genopts/gen-evolution.awk
@@ -101,10 +101,18 @@ function gen_cpucfg_useful_idx()
 idx_list[j++] = i+0
 delete idx_bucket
 
-asort (idx_list)
+for (i = 1; i < j; i++) {
+t = i
+for (k = i + 1; k < j; k++)
+t = idx_list[k] < idx_list[t] ? k : t
+
+k = idx_list[t]
+idx_list[t] = idx_list[i]
+idx_list[i] = k
+}
 
 print "static constexpr int cpucfg_useful_idx[] = {"
-for (i in idx_list)
+for (i = 1; i < j; i++)
 printf("  %d,\n", idx_list[i])
 print "};"
 
diff --git a/gcc/config/loongarch/genopts/genstr.sh 
b/gcc/config/loongarch/genopts/genstr.sh
index 5b3bf7fdf0c0..501546d19bc9 100755
--- a/gcc/config/loongarch/genopts/genstr.sh
+++ b/gcc/config/loongarch/genopts/genstr.sh
@@ -51,18 +51,18 @@ along with GCC; see the file COPYING3.  If not see
 #define LOONGARCH_STR_H
 EOF
 
-sed -e '/^$/n' -e 's@#.*$@@' -e '/^$/d' \
-   -e 's@^\([^ \t]\+\)[ \t]*\([^ \t]*\)@#define \1 "\2"@' \
-   loongarch-strings
+awk '/^#.*$/ { next } /^$/ { print; next }
+ { printf ("#define %s \"%s\"\n", $1, $2) }' \
+ loongarch-strings
 
 echo
 
-   # Generate the strings from isa-evolution.in.
-   awk '{
- a=$3
- gsub(/-/, "_", a)
- print("#define OPTSTR_"toupper(a)"\t\""$3"\"")
-   }' isa-evolution.in
+# Generate the strings from isa-evolution.in.
+awk '{
+  a=$3
+  gsub(/-/, "_", a)
+  print("#define OPTSTR_"toupper(a)"\t\""$3"\"")
+}' isa-evolution.in
 
 echo
 echo "#endif /* LOONGARCH_STR_H */"
@@ -73,18 +73,8 @@ EOF
 # according to the key-value pairs defined in loongarch-strings.
 
 gen_options() {
-
-sed -e '/^$/n' -e 's@#.*$@@' -e '/^$/d' \
-   -e 's@^\([^ \t]\+\)[ \t]*\([^ \t]*\)@\1="\2"@' \
-   loongarch-strings | { \
-
-   # read the definitions
-   while read -r line; do
-   eval "$line"
-   done
-
-   # print a header
-   cat << EOF
+# print a header
+cat << EOF
 ; Generated by "genstr" from the template "loongarch.opt.in"
 ; and definitions from "loongarch-strings" and "isa-evolution.in".
 ;
@@ -95,12 +85,25 @@ gen_options() {
 ;
 EOF
 
-   # make the substitutions
-   sed -e 's@"@\\"@g' -e 's/@@\([^@]\+\)@@/${\1}/g' loongarch.opt.in | \
-   while read -r line; do
-   eval "echo \"$line\""
-   done
-}
+# Generate loongarch.opt.
+awk 'BEGIN {
+delete strtab
+while (getline < "loongarch-strings" > 0) {
+if ($0 ~ /^#.*$/ || $0 ~ /^$/) continue
+strtab[$1] = $2
+}
+}
+{
+n = split($0, tmp, "@@")
+for (i = 2; i <= n; i += 2)
+tmp[i] = strtab[tmp[i]]
+
+for (i = 1; i <= n; i++)
+printf("%s", tmp[i])
+printf ("\n")
+
+}' loongarch.opt.in
+
 
 # Generate the strings from isa-evolution.in.
 awk '{

[gcc r15-9245] LoongArch: Add LoongArch architecture detection to __float128 support in libgfortran and libquadmath

[LuluCheng via Gcc-cvs]

https://gcc.gnu.org/g:1534f0099c98ea14c08a401302b05edf2231f411

commit r15-9245-g1534f0099c98ea14c08a401302b05edf2231f411
Author: Lulu Cheng 
Date:   Mon Apr 7 10:00:27 2025 +0800

LoongArch: Add LoongArch architecture detection to __float128 support in 
libgfortran and libquadmath [PR119408].

In GCC14, LoongArch added __float128 as an alias for _Float128.
In commit r15-8962, support for q/Q suffixes for 128-bit floating point
numbers.  This will cause the compiler to automatically link libquadmath
when compiling Fortran programs.  But on LoongArch `long double` is
IEEE quad, so there is no need to implement libquadmath.
This causes link failure.

PR target/119408

libgfortran/ChangeLog:

* acinclude.m4: When checking for __float128 support, determine
whether the current architecture is LoongArch.  If so, return false.
* configure: Regenerate.

libquadmath/ChangeLog:

* configure.ac: When checking for __float128 support, determine
whether the current architecture is LoongArch.  If so, return false.
* configure: Regenerate.

Sigend-off-by: Xi Ruoyao 
Sigend-off-by: Jakub Jelinek 

Diff:
---
 libgfortran/acinclude.m4 | 4 
 libgfortran/configure| 8 
 libquadmath/configure| 8 
 libquadmath/configure.ac | 4 
 4 files changed, 24 insertions(+)

diff --git a/libgfortran/acinclude.m4 b/libgfortran/acinclude.m4
index a73207e54656..23fd621e5188 100644
--- a/libgfortran/acinclude.m4
+++ b/libgfortran/acinclude.m4
@@ -274,6 +274,10 @@ AC_DEFUN([LIBGFOR_CHECK_FLOAT128], [
   AC_CACHE_CHECK([whether we have a usable _Float128 type],
  libgfor_cv_have_float128, [
GCC_TRY_COMPILE_OR_LINK([
+#ifdef __loongarch__
+#error On LoongArch we should use long double instead; __float128 is only 
for porting existing code easier.
+#endif
+
 _Float128 foo (_Float128 x)
 {
  _Complex _Float128 z1, z2;
diff --git a/libgfortran/configure b/libgfortran/configure
index 11a1bc5f0708..9898a94a372a 100755
--- a/libgfortran/configure
+++ b/libgfortran/configure
@@ -30283,6 +30283,10 @@ else
   cat confdefs.h - <<_ACEOF >conftest.$ac_ext
 /* end confdefs.h.  */
 
+#ifdef __loongarch__
+#error On LoongArch we should use long double instead; __float128 is only 
for porting existing code easier.
+#endif
+
 _Float128 foo (_Float128 x)
 {
  _Complex _Float128 z1, z2;
@@ -30336,6 +30340,10 @@ fi
 cat confdefs.h - <<_ACEOF >conftest.$ac_ext
 /* end confdefs.h.  */
 
+#ifdef __loongarch__
+#error On LoongArch we should use long double instead; __float128 is only 
for porting existing code easier.
+#endif
+
 _Float128 foo (_Float128 x)
 {
  _Complex _Float128 z1, z2;
diff --git a/libquadmath/configure b/libquadmath/configure
index 49d70809218c..f82dd3d0d6d4 100755
--- a/libquadmath/configure
+++ b/libquadmath/configure
@@ -12843,6 +12843,10 @@ else
   cat confdefs.h - <<_ACEOF >conftest.$ac_ext
 /* end confdefs.h.  */
 
+#ifdef __loongarch__
+#error  On LoongArch we should use long double instead; __float128 is only 
for porting existing code easier.
+#endif
+
 #if (!defined(_ARCH_PPC)) || defined(__LONG_DOUBLE_IEEE128__)
 typedef _Complex float __attribute__((mode(TC))) __complex128;
 #else
@@ -12894,6 +12898,10 @@ fi
 cat confdefs.h - <<_ACEOF >conftest.$ac_ext
 /* end confdefs.h.  */
 
+#ifdef __loongarch__
+#error  On LoongArch we should use long double instead; __float128 is only 
for porting existing code easier.
+#endif
+
 #if (!defined(_ARCH_PPC)) || defined(__LONG_DOUBLE_IEEE128__)
 typedef _Complex float __attribute__((mode(TC))) __complex128;
 #else
diff --git a/libquadmath/configure.ac b/libquadmath/configure.ac
index 349be2607c64..c64a84892191 100644
--- a/libquadmath/configure.ac
+++ b/libquadmath/configure.ac
@@ -233,6 +233,10 @@ AM_CONDITIONAL(LIBQUAD_USE_SYMVER_SUN, [test 
"x$quadmath_use_symver" = xsun])
 
 AC_CACHE_CHECK([whether __float128 is supported], [libquad_cv_have_float128],
   [GCC_TRY_COMPILE_OR_LINK([
+#ifdef __loongarch__
+#error  On LoongArch we should use long double instead; __float128 is only 
for porting existing code easier.
+#endif
+
 #if (!defined(_ARCH_PPC)) || defined(__LONG_DOUBLE_IEEE128__)
 typedef _Complex float __attribute__((mode(TC))) __complex128;
 #else

[gcc r15-9556] LoongArch: Change {dg-do-what-default} save and restore logical.

[LuluCheng via Gcc-cvs]

https://gcc.gnu.org/g:96171a5cc7b99cb6e74b7df651f96577f6e794b3

commit r15-9556-g96171a5cc7b99cb6e74b7df651f96577f6e794b3
Author: Xing Li 
Date:   Wed Apr 16 10:29:57 2025 +0800

LoongArch: Change {dg-do-what-default} save and restore logical.

The set of {dg-do-what-default} to 'run' may lead some test hang
during make check.

gcc/testsuite/ChangeLog:

* gcc.target/loongarch/vector/loongarch-vector.exp: Change
{dg-do-what-default} save and restore logical.

(cherry picked from commit dd982198656d914a4958bf86356a4c996c728b9d)

Diff:
---
 gcc/testsuite/gcc.target/loongarch/vector/loongarch-vector.exp | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/gcc/testsuite/gcc.target/loongarch/vector/loongarch-vector.exp 
b/gcc/testsuite/gcc.target/loongarch/vector/loongarch-vector.exp
index f56d2f11bb37..9df3f2908573 100644
--- a/gcc/testsuite/gcc.target/loongarch/vector/loongarch-vector.exp
+++ b/gcc/testsuite/gcc.target/loongarch/vector/loongarch-vector.exp
@@ -35,7 +35,7 @@ dg-init
 
 # If the target hardware supports LSX, the default action is "run", otherwise
 # just "compile".
-global dg-do-what-default
+set saved-dg-do-what-default ${dg-do-what-default}
 if {[check_effective_target_loongarch_sx_hw]} then {
   set dg-do-what-default run
 } else {
@@ -45,6 +45,7 @@ if {[check_effective_target_loongarch_sx_hw]} then {
 #Main loop.
 dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/lsx/*.\[cS\]]] \
" -mlsx" $DEFAULT_CFLAGS
+set dg-do-what-default ${saved-dg-do-what-default}
 
 dg-finish
 
@@ -52,7 +53,7 @@ dg-init
 # If the target hardware supports LASX, the default action is "run", otherwise
 # just "compile".
 
-global dg-do-what-default
+set saved-dg-do-what-default ${dg-do-what-default}
 if {[check_effective_target_loongarch_asx_hw]} then {
   set dg-do-what-default run
 } else {
@@ -61,5 +62,6 @@ if {[check_effective_target_loongarch_asx_hw]} then {
 
 dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/lasx/*.\[cS\]]] \
" -mlasx" $DEFAULT_CFLAGS
+set dg-do-what-default ${saved-dg-do-what-default}
 # All done.
 dg-finish

[gcc r16-13] LoongArch: Change {dg-do-what-default} save and restore logical.

[LuluCheng via Gcc-cvs]

https://gcc.gnu.org/g:dd982198656d914a4958bf86356a4c996c728b9d

commit r16-13-gdd982198656d914a4958bf86356a4c996c728b9d
Author: Xing Li 
Date:   Wed Apr 16 10:29:57 2025 +0800

LoongArch: Change {dg-do-what-default} save and restore logical.

The set of {dg-do-what-default} to 'run' may lead some test hang
during make check.

gcc/testsuite/ChangeLog:

* gcc.target/loongarch/vector/loongarch-vector.exp: Change
{dg-do-what-default} save and restore logical.

Diff:
---
 gcc/testsuite/gcc.target/loongarch/vector/loongarch-vector.exp | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/gcc/testsuite/gcc.target/loongarch/vector/loongarch-vector.exp 
b/gcc/testsuite/gcc.target/loongarch/vector/loongarch-vector.exp
index f56d2f11bb37..9df3f2908573 100644
--- a/gcc/testsuite/gcc.target/loongarch/vector/loongarch-vector.exp
+++ b/gcc/testsuite/gcc.target/loongarch/vector/loongarch-vector.exp
@@ -35,7 +35,7 @@ dg-init
 
 # If the target hardware supports LSX, the default action is "run", otherwise
 # just "compile".
-global dg-do-what-default
+set saved-dg-do-what-default ${dg-do-what-default}
 if {[check_effective_target_loongarch_sx_hw]} then {
   set dg-do-what-default run
 } else {
@@ -45,6 +45,7 @@ if {[check_effective_target_loongarch_sx_hw]} then {
 #Main loop.
 dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/lsx/*.\[cS\]]] \
" -mlsx" $DEFAULT_CFLAGS
+set dg-do-what-default ${saved-dg-do-what-default}
 
 dg-finish
 
@@ -52,7 +53,7 @@ dg-init
 # If the target hardware supports LASX, the default action is "run", otherwise
 # just "compile".
 
-global dg-do-what-default
+set saved-dg-do-what-default ${dg-do-what-default}
 if {[check_effective_target_loongarch_asx_hw]} then {
   set dg-do-what-default run
 } else {
@@ -61,5 +62,6 @@ if {[check_effective_target_loongarch_asx_hw]} then {
 
 dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/lasx/*.\[cS\]]] \
" -mlasx" $DEFAULT_CFLAGS
+set dg-do-what-default ${saved-dg-do-what-default}
 # All done.
 dg-finish

[gcc r14-11652] LoongArch: Change {dg-do-what-default} save and restore logical.

[LuluCheng via Gcc-cvs]

https://gcc.gnu.org/g:2048dcc39b1d2206edb741393dbadfb18950bd21

commit r14-11652-g2048dcc39b1d2206edb741393dbadfb18950bd21
Author: Xing Li 
Date:   Wed Apr 16 10:29:57 2025 +0800

LoongArch: Change {dg-do-what-default} save and restore logical.

The set of {dg-do-what-default} to 'run' may lead some test hang
during make check.

gcc/testsuite/ChangeLog:

* gcc.target/loongarch/vector/loongarch-vector.exp: Change
{dg-do-what-default} save and restore logical.

(cherry picked from commit dd982198656d914a4958bf86356a4c996c728b9d)

Diff:
---
 gcc/testsuite/gcc.target/loongarch/vector/loongarch-vector.exp | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/gcc/testsuite/gcc.target/loongarch/vector/loongarch-vector.exp 
b/gcc/testsuite/gcc.target/loongarch/vector/loongarch-vector.exp
index 823c2230c3fb..dc75eb6aec20 100644
--- a/gcc/testsuite/gcc.target/loongarch/vector/loongarch-vector.exp
+++ b/gcc/testsuite/gcc.target/loongarch/vector/loongarch-vector.exp
@@ -35,7 +35,7 @@ dg-init
 
 # If the target hardware supports LSX, the default action is "run", otherwise
 # just "compile".
-global dg-do-what-default
+set saved-dg-do-what-default ${dg-do-what-default}
 if {[check_effective_target_loongarch_sx_hw]} then {
   set dg-do-what-default run
 } else {
@@ -45,6 +45,7 @@ if {[check_effective_target_loongarch_sx_hw]} then {
 #Main loop.
 dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/lsx/*.\[cS\]]] \
" -mlsx" $DEFAULT_CFLAGS
+set dg-do-what-default ${saved-dg-do-what-default}
 
 dg-finish
 
@@ -52,7 +53,7 @@ dg-init
 # If the target hardware supports LASX, the default action is "run", otherwise
 # just "compile".
 
-global dg-do-what-default
+set saved-dg-do-what-default ${dg-do-what-default}
 if {[check_effective_target_loongarch_asx_hw]} then {
   set dg-do-what-default run
 } else {
@@ -61,5 +62,6 @@ if {[check_effective_target_loongarch_asx_hw]} then {
 
 dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/lasx/*.\[cS\]]] \
" -mlasx" $DEFAULT_CFLAGS
+set dg-do-what-default ${saved-dg-do-what-default}
 # All done.
 dg-finish

[gcc r14-11544] LoongArch: Make gen-evolution.awk compatible with FreeBSD awk

[LuluCheng via Gcc-cvs]

https://gcc.gnu.org/g:fd7d5a6b775090c93158b1cc3244c190e51b2dd3

commit r14-11544-gfd7d5a6b775090c93158b1cc3244c190e51b2dd3
Author: Xi Ruoyao 
Date:   Wed Apr 2 10:41:18 2025 +0800

LoongArch: Make gen-evolution.awk compatible with FreeBSD awk

Avoid using gensub that FreeBSD awk lacks, use gsub and split those each
of gawk, mawk, and FreeBSD awk provides.

Reported-by: mp...@vip.163.com
Link: https://man.freebsd.org/cgi/man.cgi?query=awk

gcc/ChangeLog:

* config/loongarch/genopts/gen-evolution.awk: Avoid using gensub
that FreeBSD awk lacks.

(cherry picked from commit 92ca72b41a74aef53978cadbda33dd38b69d3ed3)

Diff:
---
 gcc/config/loongarch/genopts/gen-evolution.awk | 8 +---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/gcc/config/loongarch/genopts/gen-evolution.awk 
b/gcc/config/loongarch/genopts/gen-evolution.awk
index 1c8004e4146c..a2ecd9a8bcf5 100644
--- a/gcc/config/loongarch/genopts/gen-evolution.awk
+++ b/gcc/config/loongarch/genopts/gen-evolution.awk
@@ -33,10 +33,12 @@ BEGIN {
 {
 cpucfg_word[NR] = $1
 cpucfg_bit_in_word[NR] = $2
-name[NR] = gensub(/-/, "_", "g", $3)
+name[NR] = $3
+gsub("-", "_", name[NR])
 name_capitalized[NR] = toupper(name[NR])
-isa_version_major[NR] = gensub(/^([1-9][0-9]*)\.([0-9]+)$/, "\\1", 1, $4)
-isa_version_minor[NR] = gensub(/^([1-9][0-9]*)\.([0-9]+)$/, "\\2", 1, $4)
+split($4, isa_ver, "\\.")
+isa_version_major[NR] = isa_ver[1]
+isa_version_minor[NR] = isa_ver[2]
 
 $1 = $2 = $3 = $4 = ""
 sub (/^\s*/, "")

[gcc r15-7920] LoongArch: testsuite: Fix gcc.dg/vect/slp-26.c.

[LuluCheng via Gcc-cvs]

https://gcc.gnu.org/g:62a6a53766ba46ada1112472b71d4ea21411ea39

commit r15-7920-g62a6a53766ba46ada1112472b71d4ea21411ea39
Author: Lulu Cheng 
Date:   Mon Mar 3 17:09:10 2025 +0800

LoongArch: testsuite: Fix gcc.dg/vect/slp-26.c.

After d34cda720988674bcf8a24267c9e1ec61335d6de, what was originally
not vectorizable can now be vectorized.  So adjust
gcc.dg/vect/slp-26.c.

gcc/testsuite/ChangeLog:

* gcc.dg/vect/slp-26.c: Adjust.

Diff:
---
 gcc/testsuite/gcc.dg/vect/slp-26.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/gcc/testsuite/gcc.dg/vect/slp-26.c 
b/gcc/testsuite/gcc.dg/vect/slp-26.c
index 23917474ddc1..b916bb3ff9ce 100644
--- a/gcc/testsuite/gcc.dg/vect/slp-26.c
+++ b/gcc/testsuite/gcc.dg/vect/slp-26.c
@@ -50,5 +50,5 @@ int main (void)
 /* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" { target { 
! { mips_msa || { amdgcn-*-* || { riscv_v || loongarch_sx } } } } } } } */
 /* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { 
mips_msa || { amdgcn-*-* || { riscv_v || loongarch_sx } } } } } } */
 /* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 0 "vect" { 
target { ! { mips_msa || { amdgcn-*-* || { riscv_v || loongarch_sx } } } } } } 
} */
-/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 1 "vect" { 
target { mips_msa || loongarch_sx } } } } */
-/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 2 "vect" { 
target { riscv_v || amdgcn-*-* } } } } */
+/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 1 "vect" { 
target { mips_msa } } } } */
+/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 2 "vect" { 
target { loongarch_sx || { riscv_v || amdgcn-*-* } } } } } */

[gcc r15-7918] LoongArch: testsuite: Fix pr112325.c and pr117888-1.c.

[LuluCheng via Gcc-cvs]

https://gcc.gnu.org/g:671702b29f252b417810b7a1dc7506f096339577

commit r15-7918-g671702b29f252b417810b7a1dc7506f096339577
Author: Lulu Cheng 
Date:   Mon Mar 3 16:52:43 2025 +0800

LoongArch: testsuite: Fix pr112325.c and pr117888-1.c.

By default, vectorization is not enabled on LoongArch,
resulting in the failure of these two test cases.

gcc/testsuite/ChangeLog:

* gcc.dg/vect/pr112325.c: Add the vector compilation
option '-mlsx' for LoongArch.
* gcc.dg/vect/pr117888-1.c: Likewise.

Diff:
---
 gcc/testsuite/gcc.dg/vect/pr112325.c   | 1 +
 gcc/testsuite/gcc.dg/vect/pr117888-1.c | 1 +
 2 files changed, 2 insertions(+)

diff --git a/gcc/testsuite/gcc.dg/vect/pr112325.c 
b/gcc/testsuite/gcc.dg/vect/pr112325.c
index 143903beab20..8689fbfe092d 100644
--- a/gcc/testsuite/gcc.dg/vect/pr112325.c
+++ b/gcc/testsuite/gcc.dg/vect/pr112325.c
@@ -4,6 +4,7 @@
 /* { dg-require-effective-target vect_shift } */
 /* { dg-additional-options "-mavx2" { target x86_64-*-* i?86-*-* } } */
 /* { dg-additional-options "--param max-completely-peeled-insns=200" { target 
powerpc64*-*-* } } */
+/* { dg-additional-options "-mlsx" { target loongarch64-*-* } } */
 
 typedef unsigned short ggml_fp16_t;
 static float table_f32_f16[1 << 16];
diff --git a/gcc/testsuite/gcc.dg/vect/pr117888-1.c 
b/gcc/testsuite/gcc.dg/vect/pr117888-1.c
index 4796a7c83c16..0b31fcdc423b 100644
--- a/gcc/testsuite/gcc.dg/vect/pr117888-1.c
+++ b/gcc/testsuite/gcc.dg/vect/pr117888-1.c
@@ -4,6 +4,7 @@
 /* { dg-require-effective-target vect_shift } */
 /* { dg-additional-options "-mavx2" { target x86_64-*-* i?86-*-* } } */
 /* { dg-additional-options "--param max-completely-peeled-insns=200" { target 
powerpc64*-*-* } } */
+/* { dg-additional-options "-mlsx" { target loongarch64-*-* } } */
 
 typedef unsigned short ggml_fp16_t;
 static float table_f32_f16[1 << 16];

[gcc r15-7919] LoongArch: testsuite: Fix gcc.dg/vect/bb-slp-77.c.

[LuluCheng via Gcc-cvs]

https://gcc.gnu.org/g:546567367a9d5c4ff3f1f416b55cf168153d03c7

commit r15-7919-g546567367a9d5c4ff3f1f416b55cf168153d03c7
Author: Lulu Cheng 
Date:   Mon Mar 3 16:58:28 2025 +0800

LoongArch: testsuite: Fix gcc.dg/vect/bb-slp-77.c.

The issue is the same as 12383255fe4e82c31f5e42c72a8fbcb1b5dea35d.
Neither is .REDUC_PLUS set for V2SImode on LoongArch, so add it
to the list of targets not expecting BB vectorization.

gcc/testsuite/ChangeLog:

* gcc.dg/vect/bb-slp-77.c: Add loongarch*-*-* to the list
of expected failing targets.

Diff:
---
 gcc/testsuite/gcc.dg/vect/bb-slp-77.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/testsuite/gcc.dg/vect/bb-slp-77.c 
b/gcc/testsuite/gcc.dg/vect/bb-slp-77.c
index bc74f6a4db31..2057f038f2f3 100644
--- a/gcc/testsuite/gcc.dg/vect/bb-slp-77.c
+++ b/gcc/testsuite/gcc.dg/vect/bb-slp-77.c
@@ -71,4 +71,4 @@ void test(const int n, float * restrict s, const void * 
restrict vx, const void
 *s = sumf;
 }
 
-/* { dg-final { scan-tree-dump-times "optimized: basic block" 1 "slp1"  { 
target { { vect_int_mult && vect_element_align } && { ! { powerpc*-*-* 
x86_64-*-* i?86-*-* } } } } } } */
+/* { dg-final { scan-tree-dump-times "optimized: basic block" 1 "slp1"  { 
target { { vect_int_mult && vect_element_align } && { ! { powerpc*-*-* 
x86_64-*-* i?86-*-* loongarch*-*-* } } } } } } */

[gcc r15-7522] LoongArch: Split the function loongarch_cpu_cpp_builtins into two functions.

[LuluCheng via Gcc-cvs]

https://gcc.gnu.org/g:c1af05f3d0320b5af98f27a76abfc9263bd42bb8

commit r15-7522-gc1af05f3d0320b5af98f27a76abfc9263bd42bb8
Author: Lulu Cheng 
Date:   Tue Feb 11 20:05:13 2025 +0800

LoongArch: Split the function loongarch_cpu_cpp_builtins into two functions.

Split the implementation of the function loongarch_cpu_cpp_builtins into 
two parts:
  1. Macro definitions that do not change (only considering 64-bit 
architecture)
  2. Macro definitions that change with different compilation options.

gcc/ChangeLog:

* config/loongarch/loongarch-c.cc (builtin_undef): New macro.
(loongarch_cpu_cpp_builtins): Split to loongarch_update_cpp_builtins
and loongarch_define_unconditional_macros.
(loongarch_def_or_undef): New functions.
(loongarch_define_unconditional_macros): Likewise.
(loongarch_update_cpp_builtins): Likewise.

Diff:
---
 gcc/config/loongarch/loongarch-c.cc | 122 +++-
 1 file changed, 77 insertions(+), 45 deletions(-)

diff --git a/gcc/config/loongarch/loongarch-c.cc 
b/gcc/config/loongarch/loongarch-c.cc
index 5d8c02e094bc..9a8de1ec3812 100644
--- a/gcc/config/loongarch/loongarch-c.cc
+++ b/gcc/config/loongarch/loongarch-c.cc
@@ -31,26 +31,22 @@ along with GCC; see the file COPYING3.  If not see
 
 #define preprocessing_asm_p() (cpp_get_options (pfile)->lang == CLK_ASM)
 #define builtin_define(TXT) cpp_define (pfile, TXT)
+#define builtin_undef(TXT) cpp_undef (pfile, TXT)
 #define builtin_assert(TXT) cpp_assert (pfile, TXT)
 
-void
-loongarch_cpu_cpp_builtins (cpp_reader *pfile)
+static void
+loongarch_def_or_undef (bool def_p, const char *macro, cpp_reader *pfile)
 {
-  builtin_assert ("machine=loongarch");
-  builtin_assert ("cpu=loongarch");
-  builtin_define ("__loongarch__");
-
-  builtin_define_with_value ("__loongarch_arch",
-loongarch_arch_strings[la_target.cpu_arch], 1);
-
-  builtin_define_with_value ("__loongarch_tune",
-loongarch_tune_strings[la_target.cpu_tune], 1);
-
-  builtin_define_with_value ("_LOONGARCH_ARCH",
-loongarch_arch_strings[la_target.cpu_arch], 1);
+  if (def_p)
+cpp_define (pfile, macro);
+  else
+cpp_undef (pfile, macro);
+}
 
-  builtin_define_with_value ("_LOONGARCH_TUNE",
-loongarch_tune_strings[la_target.cpu_tune], 1);
+static void
+loongarch_define_unconditional_macros (cpp_reader *pfile)
+{
+  builtin_define ("__loongarch__");
 
   /* Base architecture / ABI.  */
   if (TARGET_64BIT)
@@ -66,6 +62,48 @@ loongarch_cpu_cpp_builtins (cpp_reader *pfile)
   builtin_define ("__loongarch_lp64");
 }
 
+  /* Add support for FLOAT128_TYPE on the LoongArch architecture.  */
+  builtin_define ("__FLOAT128_TYPE__");
+
+  /* Map the old _Float128 'q' builtins into the new 'f128' builtins.  */
+  builtin_define ("__builtin_fabsq=__builtin_fabsf128");
+  builtin_define ("__builtin_copysignq=__builtin_copysignf128");
+  builtin_define ("__builtin_nanq=__builtin_nanf128");
+  builtin_define ("__builtin_nansq=__builtin_nansf128");
+  builtin_define ("__builtin_infq=__builtin_inff128");
+  builtin_define ("__builtin_huge_valq=__builtin_huge_valf128");
+
+  /* Native Data Sizes.  */
+  builtin_define_with_int_value ("_LOONGARCH_SZINT", INT_TYPE_SIZE);
+  builtin_define_with_int_value ("_LOONGARCH_SZLONG", LONG_TYPE_SIZE);
+  builtin_define_with_int_value ("_LOONGARCH_SZPTR", POINTER_SIZE);
+  builtin_define_with_int_value ("_LOONGARCH_FPSET", 32);
+  builtin_define_with_int_value ("_LOONGARCH_SPFPSET", 32);
+}
+
+static void
+loongarch_update_cpp_builtins (cpp_reader *pfile)
+{
+  /* Since the macros in this function might be redefined, it's necessary to
+ undef them first.*/
+  builtin_undef ("__loongarch_arch");
+  builtin_define_with_value ("__loongarch_arch",
+loongarch_arch_strings[la_target.cpu_arch], 1);
+
+  builtin_undef ("__loongarch_tune");
+  builtin_define_with_value ("__loongarch_tune",
+loongarch_tune_strings[la_target.cpu_tune], 1);
+
+  builtin_undef ("_LOONGARCH_ARCH");
+  builtin_define_with_value ("_LOONGARCH_ARCH",
+loongarch_arch_strings[la_target.cpu_arch], 1);
+
+  builtin_undef ("_LOONGARCH_TUNE");
+  builtin_define_with_value ("_LOONGARCH_TUNE",
+loongarch_tune_strings[la_target.cpu_tune], 1);
+
+  builtin_undef ("__loongarch_double_float");
+  builtin_undef ("__loongarch_single_float");
   /* These defines reflect the ABI in use, not whether the
  FPU is directly accessible.  */
   if (TARGET_DOUBLE_FLOAT_ABI)
@@ -73,6 +111,8 @@ loongarch_cpu_cpp_builtins (cpp_reader *pfile)
   else if (TARGET_SINGLE_FLOAT_ABI)
 builtin_define ("__loongarch_single_float=1");
 
+  builtin_undef ("__loongarch_soft_float");
+  builtin_undef ("__loongarch_hard_float");
   if (TARGET_DOUBLE_FLOAT_ABI ||

[gcc r15-7521] LoongArch: Move the function loongarch_register_pragmas to loongarch-c.cc.

[LuluCheng via Gcc-cvs]

https://gcc.gnu.org/g:46ce50b44e3d06f103c9136bc052a7354e07cfca

commit r15-7521-g46ce50b44e3d06f103c9136bc052a7354e07cfca
Author: Lulu Cheng 
Date:   Wed Feb 12 09:57:02 2025 +0800

LoongArch: Move the function loongarch_register_pragmas to loongarch-c.cc.

gcc/ChangeLog:

* config/loongarch/loongarch-target-attr.cc
(loongarch_pragma_target_parse): Move to ...
(loongarch_register_pragmas): Move to ...
* config/loongarch/loongarch-c.cc
(loongarch_pragma_target_parse): ... here.
(loongarch_register_pragmas): ... here.
* config/loongarch/loongarch-protos.h
(loongarch_process_target_attr): Function Declaration.

Diff:
---
 gcc/config/loongarch/loongarch-c.cc   | 51 +++
 gcc/config/loongarch/loongarch-protos.h   |  1 +
 gcc/config/loongarch/loongarch-target-attr.cc | 48 -
 3 files changed, 52 insertions(+), 48 deletions(-)

diff --git a/gcc/config/loongarch/loongarch-c.cc 
b/gcc/config/loongarch/loongarch-c.cc
index c95c0f373be6..5d8c02e094bc 100644
--- a/gcc/config/loongarch/loongarch-c.cc
+++ b/gcc/config/loongarch/loongarch-c.cc
@@ -23,9 +23,11 @@ along with GCC; see the file COPYING3.  If not see
 #include "config.h"
 #include "system.h"
 #include "coretypes.h"
+#include "target.h"
 #include "tm.h"
 #include "c-family/c-common.h"
 #include "cpplib.h"
+#include "tm_p.h"
 
 #define preprocessing_asm_p() (cpp_get_options (pfile)->lang == CLK_ASM)
 #define builtin_define(TXT) cpp_define (pfile, TXT)
@@ -145,3 +147,52 @@ loongarch_cpu_cpp_builtins (cpp_reader *pfile)
   builtin_define_with_int_value ("_LOONGARCH_SPFPSET", 32);
 
 }
+
+/* Hook to validate the current #pragma GCC target and set the state, and
+   update the macros based on what was changed.  If ARGS is NULL, then
+   POP_TARGET is used to reset the options.  */
+
+static bool
+loongarch_pragma_target_parse (tree args, tree pop_target)
+{
+  /* If args is not NULL then process it and setup the target-specific
+ information that it specifies.  */
+  if (args)
+{
+  if (!loongarch_process_target_attr (args, NULL))
+   return false;
+
+  loongarch_option_override_internal (&la_target,
+ &global_options,
+ &global_options_set);
+}
+
+  /* args is NULL, restore to the state described in pop_target.  */
+  else
+{
+  pop_target = pop_target ? pop_target : target_option_default_node;
+  cl_target_option_restore (&global_options, &global_options_set,
+   TREE_TARGET_OPTION (pop_target));
+}
+
+  target_option_current_node
+= build_target_option_node (&global_options, &global_options_set);
+
+  loongarch_reset_previous_fndecl ();
+
+  /* If we're popping or reseting make sure to update the globals so that
+ the optab availability predicates get recomputed.  */
+  if (pop_target)
+loongarch_save_restore_target_globals (pop_target);
+
+  return true;
+}
+
+/* Implement REGISTER_TARGET_PRAGMAS.  */
+
+void
+loongarch_register_pragmas (void)
+{
+  /* Update pragma hook to allow parsing #pragma GCC target.  */
+  targetm.target_option.pragma_parse = loongarch_pragma_target_parse;
+}
diff --git a/gcc/config/loongarch/loongarch-protos.h 
b/gcc/config/loongarch/loongarch-protos.h
index b99f949a004e..e7b318143bfe 100644
--- a/gcc/config/loongarch/loongarch-protos.h
+++ b/gcc/config/loongarch/loongarch-protos.h
@@ -219,4 +219,5 @@ extern void loongarch_option_override_internal (struct 
loongarch_target *, struc
 extern void loongarch_reset_previous_fndecl (void);
 extern void loongarch_save_restore_target_globals (tree new_tree);
 extern void loongarch_register_pragmas (void);
+extern bool loongarch_process_target_attr (tree args, tree fndecl);
 #endif /* ! GCC_LOONGARCH_PROTOS_H */
diff --git a/gcc/config/loongarch/loongarch-target-attr.cc 
b/gcc/config/loongarch/loongarch-target-attr.cc
index cee7031ca1e7..cb537446dffe 100644
--- a/gcc/config/loongarch/loongarch-target-attr.cc
+++ b/gcc/config/loongarch/loongarch-target-attr.cc
@@ -422,51 +422,3 @@ loongarch_option_valid_attribute_p (tree fndecl, tree, 
tree args, int)
   return ret;
 }
 
-/* Hook to validate the current #pragma GCC target and set the state, and
-   update the macros based on what was changed.  If ARGS is NULL, then
-   POP_TARGET is used to reset the options.  */
-
-static bool
-loongarch_pragma_target_parse (tree args, tree pop_target)
-{
-  /* If args is not NULL then process it and setup the target-specific
- information that it specifies.  */
-  if (args)
-{
-  if (!loongarch_process_target_attr (args, NULL))
-   return false;
-
-  loongarch_option_override_internal (&la_target,
- &global_options,
- &global_options_set);
-}
-
-  /* args is NULL, restore to the state

[gcc r15-7523] LoongArch: After setting the compilation options, update the predefined macros.

[LuluCheng via Gcc-cvs]

https://gcc.gnu.org/g:753306bbaebb4a56ee8dde893e14dbd9e5269df6

commit r15-7523-g753306bbaebb4a56ee8dde893e14dbd9e5269df6
Author: Lulu Cheng 
Date:   Tue Feb 11 20:36:17 2025 +0800

LoongArch: After setting the compilation options, update the predefined 
macros.

PR target/118828

gcc/ChangeLog:

* config/loongarch/loongarch-c.cc (loongarch_pragma_target_parse):
Update the predefined macros.

gcc/testsuite/ChangeLog:

* gcc.target/loongarch/pr118828.c: New test.
* gcc.target/loongarch/pr118828-2.c: New test.
* gcc.target/loongarch/pr118828-3.c: New test.
* gcc.target/loongarch/pr118828-4.c: New test.

Diff:
---
 gcc/config/loongarch/loongarch-c.cc | 14 ++
 gcc/testsuite/gcc.target/loongarch/pr118828-2.c | 30 ++
 gcc/testsuite/gcc.target/loongarch/pr118828-3.c | 32 +++
 gcc/testsuite/gcc.target/loongarch/pr118828-4.c | 32 +++
 gcc/testsuite/gcc.target/loongarch/pr118828.c   | 34 +
 5 files changed, 142 insertions(+)

diff --git a/gcc/config/loongarch/loongarch-c.cc 
b/gcc/config/loongarch/loongarch-c.cc
index 9a8de1ec3812..66ae77ad665f 100644
--- a/gcc/config/loongarch/loongarch-c.cc
+++ b/gcc/config/loongarch/loongarch-c.cc
@@ -27,6 +27,7 @@ along with GCC; see the file COPYING3.  If not see
 #include "tm.h"
 #include "c-family/c-common.h"
 #include "cpplib.h"
+#include "c-family/c-pragma.h"
 #include "tm_p.h"
 
 #define preprocessing_asm_p() (cpp_get_options (pfile)->lang == CLK_ASM)
@@ -212,6 +213,19 @@ loongarch_pragma_target_parse (tree args, tree pop_target)
 
   loongarch_reset_previous_fndecl ();
 
+  /* For the definitions, ensure all newly defined macros are considered
+ as used for -Wunused-macros.  There is no point warning about the
+ compiler predefined macros.  */
+  cpp_options *cpp_opts = cpp_get_options (parse_in);
+  unsigned char saved_warn_unused_macros = cpp_opts->warn_unused_macros;
+  cpp_opts->warn_unused_macros = 0;
+
+  cpp_force_token_locations (parse_in, BUILTINS_LOCATION);
+  loongarch_update_cpp_builtins (parse_in);
+  cpp_stop_forcing_token_locations (parse_in);
+
+  cpp_opts->warn_unused_macros = saved_warn_unused_macros;
+
   /* If we're popping or reseting make sure to update the globals so that
  the optab availability predicates get recomputed.  */
   if (pop_target)
diff --git a/gcc/testsuite/gcc.target/loongarch/pr118828-2.c 
b/gcc/testsuite/gcc.target/loongarch/pr118828-2.c
new file mode 100644
index ..3d32fcc15c95
--- /dev/null
+++ b/gcc/testsuite/gcc.target/loongarch/pr118828-2.c
@@ -0,0 +1,30 @@
+/* { dg-do preprocess } */
+/* { dg-options "-mno-lsx" } */
+
+#ifdef __loongarch_sx
+#error LSX should not be available here
+#endif
+
+#ifdef __loongarch_simd_width
+#error simd width shuold not be available here
+#endif
+
+#pragma GCC push_options
+#pragma GCC target("lsx")
+#ifndef __loongarch_sx
+#error LSX should be available here
+#endif
+#ifndef __loongarch_simd_width
+#error simd width should be available here
+#elif __loongarch_simd_width != 128
+#error simd width should be 128
+#endif
+#pragma GCC pop_options
+
+#ifdef __loongarch_sx
+#error LSX should become unavailable again
+#endif
+
+#ifdef __loongarch_simd_width
+#error simd width shuold become unavailable again
+#endif
diff --git a/gcc/testsuite/gcc.target/loongarch/pr118828-3.c 
b/gcc/testsuite/gcc.target/loongarch/pr118828-3.c
new file mode 100644
index ..31ab8e59a3fc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/loongarch/pr118828-3.c
@@ -0,0 +1,32 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=loongarch64" } */
+/* { dg-final { scan-assembler "t1: loongarch64" } } */
+/* { dg-final { scan-assembler "t2: la64v1.1" } } */
+/* { dg-final { scan-assembler "t3: loongarch64" } } */
+
+#ifndef __loongarch_arch
+#error __loongarch_arch should be available here
+#endif
+
+void
+t1 (void)
+{
+  asm volatile ("# t1: " __loongarch_arch);
+}
+
+#pragma GCC push_options
+#pragma GCC target("arch=la64v1.1")
+
+void
+t2 (void)
+{
+  asm volatile ("# t2: " __loongarch_arch);
+}
+
+#pragma GCC pop_options
+
+void
+t3 (void)
+{
+  asm volatile ("# t3: " __loongarch_arch);
+}
diff --git a/gcc/testsuite/gcc.target/loongarch/pr118828-4.c 
b/gcc/testsuite/gcc.target/loongarch/pr118828-4.c
new file mode 100644
index ..77587ee56148
--- /dev/null
+++ b/gcc/testsuite/gcc.target/loongarch/pr118828-4.c
@@ -0,0 +1,32 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=loongarch64 -mtune=la464" } */
+/* { dg-final { scan-assembler "t1: la464" } } */
+/* { dg-final { scan-assembler "t2: la664" } } */
+/* { dg-final { scan-assembler "t3: la464" } } */
+
+#ifndef __loongarch_tune
+#error __loongarch_tune should be available here
+#endif
+
+void
+t1 (void)
+{
+  asm volatile ("# t1: " __loongarch_tune);
+}
+
+#pragma GCC push_options
+#pragma GCC target("tune=

[gcc r15-7524] LoongArch: When -mfpu=none, '__loongarch_frecipe' shouldn't be defined [PR118843].

[LuluCheng via Gcc-cvs]

https://gcc.gnu.org/g:ee579b7c257468b9032ab4583ec455fa871d4428

commit r15-7524-gee579b7c257468b9032ab4583ec455fa871d4428
Author: Lulu Cheng 
Date:   Wed Feb 12 11:50:50 2025 +0800

LoongArch: When -mfpu=none, '__loongarch_frecipe' shouldn't be defined 
[PR118843].

PR target/118843

gcc/ChangeLog:

* config/loongarch/loongarch-c.cc
(loongarch_update_cpp_builtins): Fix macro definition issues.

gcc/testsuite/ChangeLog:

* gcc.target/loongarch/pr118843.c: New test.

Diff:
---
 gcc/config/loongarch/loongarch-c.cc   | 27 +++
 gcc/testsuite/gcc.target/loongarch/pr118843.c |  6 ++
 2 files changed, 21 insertions(+), 12 deletions(-)

diff --git a/gcc/config/loongarch/loongarch-c.cc 
b/gcc/config/loongarch/loongarch-c.cc
index 66ae77ad665f..effdcf0e2554 100644
--- a/gcc/config/loongarch/loongarch-c.cc
+++ b/gcc/config/loongarch/loongarch-c.cc
@@ -129,9 +129,6 @@ loongarch_update_cpp_builtins (cpp_reader *pfile)
   else
 builtin_define ("__loongarch_frlen=0");
 
-  loongarch_def_or_undef (TARGET_HARD_FLOAT && ISA_HAS_FRECIPE,
- "__loongarch_frecipe", pfile);
-
   loongarch_def_or_undef (ISA_HAS_LSX, "__loongarch_simd", pfile);
   loongarch_def_or_undef (ISA_HAS_LSX, "__loongarch_sx", pfile);
   loongarch_def_or_undef (ISA_HAS_LASX, "__loongarch_asx", pfile);
@@ -149,17 +146,23 @@ loongarch_update_cpp_builtins (cpp_reader *pfile)
   int max_v_major = 1, max_v_minor = 0;
 
   for (int i = 0; i < N_EVO_FEATURES; i++)
-if (la_target.isa.evolution & la_evo_feature_masks[i])
-  {
-   builtin_define (la_evo_macro_name[i]);
+{
+  builtin_undef (la_evo_macro_name[i]);
 
-   int major = la_evo_version_major[i],
-   minor = la_evo_version_minor[i];
+  if (la_target.isa.evolution & la_evo_feature_masks[i]
+ && (la_evo_feature_masks[i] != OPTION_MASK_ISA_FRECIPE
+ || TARGET_HARD_FLOAT))
+   {
+ builtin_define (la_evo_macro_name[i]);
 
-   max_v_major = major > max_v_major ? major : max_v_major;
-   max_v_minor = major == max_v_major
- ? (minor > max_v_minor ? minor : max_v_minor) : max_v_minor;
-  }
+ int major = la_evo_version_major[i],
+ minor = la_evo_version_minor[i];
+
+ max_v_major = major > max_v_major ? major : max_v_major;
+ max_v_minor = major == max_v_major
+   ? (minor > max_v_minor ? minor : max_v_minor) : max_v_minor;
+   }
+}
 
   /* Find the minimum ISA version required to run the target program.  */
   builtin_undef ("__loongarch_version_major");
diff --git a/gcc/testsuite/gcc.target/loongarch/pr118843.c 
b/gcc/testsuite/gcc.target/loongarch/pr118843.c
new file mode 100644
index ..30372b8ffe6a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/loongarch/pr118843.c
@@ -0,0 +1,6 @@
+/* { dg-do preprocess } */
+/* { dg-options "-mfrecipe -mfpu=none" } */
+
+#ifdef __loongarch_frecipe
+#error __loongarch_frecipe should not be avaliable here
+#endif

[gcc r15-7525] LoongArch: Adjust the cost of ADDRESS_REG_REG.

[LuluCheng via Gcc-cvs]

https://gcc.gnu.org/g:7c50f95421b6de50e4f40773558d0072eafb2365

commit r15-7525-g7c50f95421b6de50e4f40773558d0072eafb2365
Author: Lulu Cheng 
Date:   Tue Dec 10 20:59:22 2024 +0800

LoongArch: Adjust the cost of ADDRESS_REG_REG.

After changing this cost from 1 to 3, the performance of spec2006
401 473 416 465 482 can be improved by about 2% on LA664.

Add option '-maddr-reg-reg-cost='.

gcc/ChangeLog:

* config/loongarch/genopts/loongarch.opt.in: Add
option '-maddr-reg-reg-cost='.
* config/loongarch/loongarch-def.cc
(loongarch_rtx_cost_data::loongarch_rtx_cost_data): Initialize
addr_reg_reg_cost to 3.
* config/loongarch/loongarch-opts.cc
(loongarch_target_option_override): If '-maddr-reg-reg-cost='
is not used, set it to the initial value.
* config/loongarch/loongarch-tune.h
(struct loongarch_rtx_cost_data): Add the member
addr_reg_reg_cost and its assignment function to the structure
loongarch_rtx_cost_data.
* config/loongarch/loongarch.cc (loongarch_address_insns):
Use la_addr_reg_reg_cost to set the cost of ADDRESS_REG_REG.
* config/loongarch/loongarch.opt: Regenerate.
* config/loongarch/loongarch.opt.urls: Regenerate.
* doc/invoke.texi: Add description of '-maddr-reg-reg-cost='.

gcc/testsuite/ChangeLog:

* gcc.target/loongarch/const-double-zero-stx.c: Add
'-maddr-reg-reg-cost=1'.
* gcc.target/loongarch/stack-check-alloca-1.c: Likewise.

Diff:
---
 gcc/config/loongarch/genopts/loongarch.opt.in  | 4 
 gcc/config/loongarch/loongarch-def.cc  | 1 +
 gcc/config/loongarch/loongarch-opts.cc | 3 +++
 gcc/config/loongarch/loongarch-tune.h  | 7 +++
 gcc/config/loongarch/loongarch.cc  | 2 +-
 gcc/config/loongarch/loongarch.opt | 4 
 gcc/config/loongarch/loongarch.opt.urls| 3 +++
 gcc/doc/invoke.texi| 7 ++-
 gcc/testsuite/gcc.target/loongarch/const-double-zero-stx.c | 2 +-
 gcc/testsuite/gcc.target/loongarch/stack-check-alloca-1.c  | 2 +-
 10 files changed, 31 insertions(+), 4 deletions(-)

diff --git a/gcc/config/loongarch/genopts/loongarch.opt.in 
b/gcc/config/loongarch/genopts/loongarch.opt.in
index 8c292c8600d0..39c1545e5408 100644
--- a/gcc/config/loongarch/genopts/loongarch.opt.in
+++ b/gcc/config/loongarch/genopts/loongarch.opt.in
@@ -177,6 +177,10 @@ mbranch-cost=
 Target RejectNegative Joined UInteger Var(la_branch_cost) Save
 -mbranch-cost=COST Set the cost of branches to roughly COST instructions.
 
+maddr-reg-reg-cost=
+Target RejectNegative Joined UInteger Var(la_addr_reg_reg_cost) Save
+-maddr-reg-reg-cost=COST  Set the cost of ADDRESS_REG_REG to the value 
calculated by COST.
+
 mcheck-zero-division
 Target Mask(CHECK_ZERO_DIV) Save
 Trap on integer divide by zero.
diff --git a/gcc/config/loongarch/loongarch-def.cc 
b/gcc/config/loongarch/loongarch-def.cc
index b0271eb3b9ad..5f235a04ef2f 100644
--- a/gcc/config/loongarch/loongarch-def.cc
+++ b/gcc/config/loongarch/loongarch-def.cc
@@ -136,6 +136,7 @@ loongarch_rtx_cost_data::loongarch_rtx_cost_data ()
 movcf2gr (COSTS_N_INSNS (7)),
 movgr2cf (COSTS_N_INSNS (15)),
 branch_cost (6),
+addr_reg_reg_cost (3),
 memory_latency (4) {}
 
 /* The following properties cannot be looked up directly using "cpucfg".
diff --git a/gcc/config/loongarch/loongarch-opts.cc 
b/gcc/config/loongarch/loongarch-opts.cc
index 36342cc93731..c2a63f75fc24 100644
--- a/gcc/config/loongarch/loongarch-opts.cc
+++ b/gcc/config/loongarch/loongarch-opts.cc
@@ -1010,6 +1010,9 @@ loongarch_target_option_override (struct loongarch_target 
*target,
   if (!opts_set->x_la_branch_cost)
 opts->x_la_branch_cost = loongarch_cost->branch_cost;
 
+  if (!opts_set->x_la_addr_reg_reg_cost)
+opts->x_la_addr_reg_reg_cost = loongarch_cost->addr_reg_reg_cost;
+
   /* other stuff */
   if (ABI_LP64_P (target->abi.base))
 opts->x_flag_pcc_struct_return = 0;
diff --git a/gcc/config/loongarch/loongarch-tune.h 
b/gcc/config/loongarch/loongarch-tune.h
index e69173ebf79e..f7819fe76783 100644
--- a/gcc/config/loongarch/loongarch-tune.h
+++ b/gcc/config/loongarch/loongarch-tune.h
@@ -38,6 +38,7 @@ struct loongarch_rtx_cost_data
   unsigned short movcf2gr;
   unsigned short movgr2cf;
   unsigned short branch_cost;
+  unsigned short addr_reg_reg_cost;
   unsigned short memory_latency;
 
   /* Default RTX cost initializer, implemented in loongarch-def.cc.  */
@@ -115,6 +116,12 @@ struct loongarch_rtx_cost_data
 return *this;
   }
 
+  loongarch_rtx_cost_data addr_reg_reg_cost_ (unsigned short 
_addr_reg_reg_cost)
+  {
+addr_reg_reg_cost = _addr_reg_reg_cost;
+return *this;
+  }
+
   loongar

[gcc r14-11316] LoongArch: When -mfpu=none, '__loongarch_frecipe' shouldn't be defined [PR118843].

[LuluCheng via Gcc-cvs]

https://gcc.gnu.org/g:889fb66025cef4e434cc60e35add9f7406e38db7

commit r14-11316-g889fb66025cef4e434cc60e35add9f7406e38db7
Author: Lulu Cheng 
Date:   Wed Feb 12 11:50:50 2025 +0800

LoongArch: When -mfpu=none, '__loongarch_frecipe' shouldn't be defined 
[PR118843].

PR target/118843

gcc/ChangeLog:

* config/loongarch/loongarch-c.cc
(loongarch_update_cpp_builtins): Fix macro definition issues.

gcc/testsuite/ChangeLog:

* gcc.target/loongarch/pr118843.c: New test.

(cherry picked from commit ee579b7c257468b9032ab4583ec455fa871d4428)

Diff:
---
 gcc/config/loongarch/loongarch-c.cc   | 7 +++
 gcc/testsuite/gcc.target/loongarch/pr118843.c | 6 ++
 2 files changed, 9 insertions(+), 4 deletions(-)

diff --git a/gcc/config/loongarch/loongarch-c.cc 
b/gcc/config/loongarch/loongarch-c.cc
index c6763647cd13..591d1dabcdf9 100644
--- a/gcc/config/loongarch/loongarch-c.cc
+++ b/gcc/config/loongarch/loongarch-c.cc
@@ -85,9 +85,6 @@ loongarch_cpu_cpp_builtins (cpp_reader *pfile)
   else
 builtin_define ("__loongarch_frlen=0");
 
-  if (TARGET_HARD_FLOAT && ISA_HAS_FRECIPE)
-builtin_define ("__loongarch_frecipe");
-
   if (ISA_HAS_LSX)
 {
   builtin_define ("__loongarch_simd");
@@ -107,7 +104,9 @@ loongarch_cpu_cpp_builtins (cpp_reader *pfile)
   int max_v_major = 1, max_v_minor = 0;
 
   for (int i = 0; i < N_EVO_FEATURES; i++)
-if (la_target.isa.evolution & la_evo_feature_masks[i])
+if (la_target.isa.evolution & la_evo_feature_masks[i]
+   && (la_evo_feature_masks[i] != OPTION_MASK_ISA_FRECIPE
+   || TARGET_HARD_FLOAT))
   {
builtin_define (la_evo_macro_name[i]);
 
diff --git a/gcc/testsuite/gcc.target/loongarch/pr118843.c 
b/gcc/testsuite/gcc.target/loongarch/pr118843.c
new file mode 100644
index ..30372b8ffe6a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/loongarch/pr118843.c
@@ -0,0 +1,6 @@
+/* { dg-do preprocess } */
+/* { dg-options "-mfrecipe -mfpu=none" } */
+
+#ifdef __loongarch_frecipe
+#error __loongarch_frecipe should not be avaliable here
+#endif

[gcc r14-11321] LoongArch: Fix the issue of function jump out of range caused by crtbeginS.o [PR118844].

[LuluCheng via Gcc-cvs]

https://gcc.gnu.org/g:9ffecde121af883b60bbe60d00425036bc873048

commit r14-11321-g9ffecde121af883b60bbe60d00425036bc873048
Author: Lulu Cheng 
Date:   Wed Feb 12 14:29:58 2025 +0800

LoongArch: Fix the issue of function jump out of range caused by 
crtbeginS.o [PR118844].

Due to the presence of R_LARCH_B26 in
/usr/lib/gcc/loongarch64-linux-gnu/14/crtbeginS.o, its addressing
range is [PC-128MiB, PC+128MiB-4]. This means that when the code
segment size exceeds 128MB, linking with lld will definitely fail
(ld will not fail because the order of the two is different).

The linking order:
  lld: crtbeginS.o + .text + .plt
  ld : .plt + crtbeginS.o + .text

To solve this issue, add '-mcmodel=extreme' when compiling crtbeginS.o.

PR target/118844

libgcc/ChangeLog:

* config/loongarch/t-crtstuff: Add '-mcmodel=extreme'
to CRTSTUFF_T_CFLAGS_S.

(cherry picked from commit ae14d7d04da8c6cb542269722638071f999f94d8)

Diff:
---
 libgcc/config/loongarch/t-crtstuff | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/libgcc/config/loongarch/t-crtstuff 
b/libgcc/config/loongarch/t-crtstuff
index b8c36eb66b78..2a2489b7ef4e 100644
--- a/libgcc/config/loongarch/t-crtstuff
+++ b/libgcc/config/loongarch/t-crtstuff
@@ -3,3 +3,9 @@
 # to .eh_frame data from crtbeginT.o instead of the user-defined object
 # during static linking.
 CRTSTUFF_T_CFLAGS += -fno-omit-frame-pointer -fno-asynchronous-unwind-tables
+
+# As shown in the test case PR118844, when using lld for linking,
+# it fails due to B26 in crtbeginS.o causing the link to exceed the range.
+# Therefore, the issue was resolved by adding the compilation option
+# "-mcmodel=extreme" when compiling crtbeginS.o.
+CRTSTUFF_T_CFLAGS_S += -mcmodel=extreme

[gcc r14-11480] LoongArch: doc: Add same-address constraint to the description of '-mld-seq-sa'.

[LuluCheng via Gcc-cvs]

https://gcc.gnu.org/g:3d9c933c4cd31806cc9bef3a2b8238370b6df986

commit r14-11480-g3d9c933c4cd31806cc9bef3a2b8238370b6df986
Author: Lulu Cheng 
Date:   Thu Mar 27 11:42:11 2025 +0800

LoongArch: doc: Add same-address constraint to the description of 
'-mld-seq-sa'.

gcc/ChangeLog:

* doc/invoke.texi: Modify the description of '-mld-seq-sa'.

(cherry picked from commit 8ad8f74972923bf2b6d6291d31ef53c4ded4)

Diff:
---
 gcc/doc/invoke.texi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 6a94c7b70a5f..c85cac24f3ce 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -27211,8 +27211,8 @@ Use (do not use) @code{amcas[_db].@{b/h/w/d@}} 
instructions.  When build with
 @opindex mno-ld-seq-sa
 @item -mld-seq-sa
 @itemx -mno-ld-seq-sa
-Whether a load-load barrier (@code{dbar 0x700}) is needed.  When build with
-@option{-march=la664}, it is enabled by default.  The default is
+Whether a same-address load-load barrier (@code{dbar 0x700}) is needed.  When
+build with @option{-march=la664}, it is enabled by default.  The default is
 @option{-mno-ld-seq-sa}, the load-load barrier is needed.
 
 @opindex mtls-dialect

[gcc r15-9022] LoongArch: Set default alignment for functions jumps loops and labels.

[LuluCheng via Gcc-cvs]

https://gcc.gnu.org/g:6525b408b25945970d84ed1f534616fd63b03a50

commit r15-9022-g6525b408b25945970d84ed1f534616fd63b03a50
Author: Lulu Cheng 
Date:   Thu Mar 27 11:27:40 2025 +0800

LoongArch: Set default alignment for functions jumps loops and labels.

Based on r15-7624, a set of align combinations with better performance
was tested through spec2006.

LA464: -falign-loops=8 -falign-functions=32 -falign-jumps=32 
-falign-labels=8
LA664: -falign-loops=16 -falign-functions=16 -falign-jumps=32 
-falign-labels=8

gcc/ChangeLog:

* config/loongarch/loongarch-def.cc
(la464_align): Add settings for labels.
(la664_align): Likewise.
* config/loongarch/loongarch-opts.cc
(loongarch_target_option_override): Likewise.
* config/loongarch/loongarch-tune.h
(struct loongarch_align): Implement the function `label_`.

Diff:
---
 gcc/config/loongarch/loongarch-def.cc  | 4 ++--
 gcc/config/loongarch/loongarch-opts.cc | 3 +++
 gcc/config/loongarch/loongarch-tune.h  | 9 -
 3 files changed, 13 insertions(+), 3 deletions(-)

diff --git a/gcc/config/loongarch/loongarch-def.cc 
b/gcc/config/loongarch/loongarch-def.cc
index 5f235a04ef2f..04b277eb7425 100644
--- a/gcc/config/loongarch/loongarch-def.cc
+++ b/gcc/config/loongarch/loongarch-def.cc
@@ -107,12 +107,12 @@ array_tune loongarch_cpu_cache =
 
 static inline loongarch_align la464_align ()
 {
-  return loongarch_align ().function_ ("32").loop_ ("16").jump_ ("16");
+  return loongarch_align ().function_ ("32").loop_ ("8").jump_ ("32").label_ 
("8");
 }
 
 static inline loongarch_align la664_align ()
 {
-  return loongarch_align ().function_ ("8").loop_ ("8").jump_ ("32");
+  return loongarch_align ().function_ ("16").loop_ ("16").jump_ ("32").label_ 
("8");
 }
 
 array_tune loongarch_cpu_align =
diff --git a/gcc/config/loongarch/loongarch-opts.cc 
b/gcc/config/loongarch/loongarch-opts.cc
index c2a63f75fc24..6e72084b9beb 100644
--- a/gcc/config/loongarch/loongarch-opts.cc
+++ b/gcc/config/loongarch/loongarch-opts.cc
@@ -965,6 +965,9 @@ loongarch_target_option_override (struct loongarch_target 
*target,
 
   if (opts->x_flag_align_jumps && !opts->x_str_align_jumps)
opts->x_str_align_jumps = loongarch_cpu_align[target->cpu_tune].jump;
+
+  if (opts->x_flag_align_labels && !opts->x_str_align_labels)
+   opts->x_str_align_labels = loongarch_cpu_align[target->cpu_tune].label;
 }
 
   /* Set up parameters to be used in prefetching algorithm.  */
diff --git a/gcc/config/loongarch/loongarch-tune.h 
b/gcc/config/loongarch/loongarch-tune.h
index f7819fe76783..0ae74e77f996 100644
--- a/gcc/config/loongarch/loongarch-tune.h
+++ b/gcc/config/loongarch/loongarch-tune.h
@@ -177,8 +177,9 @@ struct loongarch_align {
   const char *function;/* default value for -falign-functions */
   const char *loop;/* default value for -falign-loops */
   const char *jump;/* default value for -falign-jumps */
+  const char *label;   /* default value for -falign-labels */
 
-  loongarch_align () : function (nullptr), loop (nullptr), jump (nullptr) {}
+  loongarch_align () : function (nullptr), loop (nullptr), jump (nullptr), 
label (nullptr) {}
 
   loongarch_align function_ (const char *_function)
   {
@@ -197,6 +198,12 @@ struct loongarch_align {
 jump = _jump;
 return *this;
   }
+
+  loongarch_align label_ (const char *_label)
+  {
+label = _label;
+return *this;
+  }
 };
 
 #endif /* LOONGARCH_TUNE_H */

[gcc r15-9023] LoongArch: doc: Add same-address constraint to the description of '-mld-seq-sa'.

[LuluCheng via Gcc-cvs]

https://gcc.gnu.org/g:8ad8f74972923bf2b6d6291d31ef53c4ded4

commit r15-9023-g8ad8f74972923bf2b6d6291d31ef53c4ded4
Author: Lulu Cheng 
Date:   Thu Mar 27 11:42:11 2025 +0800

LoongArch: doc: Add same-address constraint to the description of 
'-mld-seq-sa'.

gcc/ChangeLog:

* doc/invoke.texi: Modify the description of '-mld-seq-sa'.

Diff:
---
 gcc/doc/invoke.texi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 2397e5ddf5ff..df4610908243 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -28000,8 +28000,8 @@ Use (do not use) @code{amcas[_db].@{b/h/w/d@}} 
instructions.  When build with
 @opindex mno-ld-seq-sa
 @item -mld-seq-sa
 @itemx -mno-ld-seq-sa
-Whether a load-load barrier (@code{dbar 0x700}) is needed.  When build with
-@option{-march=la664}, it is enabled by default.  The default is
+Whether a same-address load-load barrier (@code{dbar 0x700}) is needed.  When
+build with @option{-march=la664}, it is enabled by default.  The default is
 @option{-mno-ld-seq-sa}, the load-load barrier is needed.
 
 @opindex mtls-dialect

[gcc r15-8962] LoongArch: Support Q suffix for __float128.

[LuluCheng via Gcc-cvs]

https://gcc.gnu.org/g:7c8da04c412ed4f54596f10434aa46592d000fbf

commit r15-8962-g7c8da04c412ed4f54596f10434aa46592d000fbf
Author: Lulu Cheng 
Date:   Sat Mar 22 14:37:01 2025 +0800

LoongArch: Support Q suffix for __float128.

In r14-3635 supports `__float128`, but does not support the 'q/Q' suffix.

PR target/119408

gcc/ChangeLog:

* config/loongarch/loongarch.cc
(loongarch_c_mode_for_suffix): New.
(TARGET_C_MODE_FOR_SUFFIX): Define.

gcc/testsuite/ChangeLog:

* gcc.target/loongarch/pr119408.c: New test.

Diff:
---
 gcc/config/loongarch/loongarch.cc | 13 +
 gcc/testsuite/gcc.target/loongarch/pr119408.c | 12 
 2 files changed, 25 insertions(+)

diff --git a/gcc/config/loongarch/loongarch.cc 
b/gcc/config/loongarch/loongarch.cc
index 01f048664b55..7533e53839f4 100644
--- a/gcc/config/loongarch/loongarch.cc
+++ b/gcc/config/loongarch/loongarch.cc
@@ -11206,6 +11206,16 @@ loongarch_asm_code_end (void)
 #undef DUMP_FEATURE
 }
 
+/* Target hook for c_mode_for_suffix.  */
+static machine_mode
+loongarch_c_mode_for_suffix (char suffix)
+{
+  if (suffix == 'q')
+return TFmode;
+
+  return VOIDmode;
+}
+
 /* Initialize the GCC target structure.  */
 #undef TARGET_ASM_ALIGNED_HI_OP
 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
@@ -11477,6 +11487,9 @@ loongarch_asm_code_end (void)
 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
 #define TARGET_OPTION_VALID_ATTRIBUTE_P loongarch_option_valid_attribute_p
 
+#undef TARGET_C_MODE_FOR_SUFFIX
+#define TARGET_C_MODE_FOR_SUFFIX loongarch_c_mode_for_suffix
+
 struct gcc_target targetm = TARGET_INITIALIZER;
 
 #include "gt-loongarch.h"
diff --git a/gcc/testsuite/gcc.target/loongarch/pr119408.c 
b/gcc/testsuite/gcc.target/loongarch/pr119408.c
new file mode 100644
index ..f46399aa0b59
--- /dev/null
+++ b/gcc/testsuite/gcc.target/loongarch/pr119408.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -Wno-pedantic" } */
+
+__float128 a;
+__float128 b;
+void
+test (void)
+{
+  a = 1.Q;
+  b = 1.434345q;   
+}
+

[gcc r14-11456] LoongArch: Support Q suffix for __float128.

[LuluCheng via Gcc-cvs]

https://gcc.gnu.org/g:243e634f5bee3912685756f31d3648df73fa6938

commit r14-11456-g243e634f5bee3912685756f31d3648df73fa6938
Author: Lulu Cheng 
Date:   Sat Mar 22 14:37:01 2025 +0800

LoongArch: Support Q suffix for __float128.

In r14-3635 supports `__float128`, but does not support the 'q/Q' suffix.

PR target/119408

gcc/ChangeLog:

* config/loongarch/loongarch.cc
(loongarch_c_mode_for_suffix): New.
(TARGET_C_MODE_FOR_SUFFIX): Define.

gcc/testsuite/ChangeLog:

* gcc.target/loongarch/pr119408.c: New test.

(cherry picked from commit 7c8da04c412ed4f54596f10434aa46592d000fbf)

Diff:
---
 gcc/config/loongarch/loongarch.cc | 13 +
 gcc/testsuite/gcc.target/loongarch/pr119408.c | 12 
 2 files changed, 25 insertions(+)

diff --git a/gcc/config/loongarch/loongarch.cc 
b/gcc/config/loongarch/loongarch.cc
index 4b456e3ef1f5..afedc8e33e44 100644
--- a/gcc/config/loongarch/loongarch.cc
+++ b/gcc/config/loongarch/loongarch.cc
@@ -11004,6 +11004,16 @@ loongarch_asm_code_end (void)
 #undef DUMP_FEATURE
 }
 
+/* Target hook for c_mode_for_suffix.  */
+static machine_mode
+loongarch_c_mode_for_suffix (char suffix)
+{
+  if (suffix == 'q')
+return TFmode;
+
+  return VOIDmode;
+}
+
 /* Initialize the GCC target structure.  */
 #undef TARGET_ASM_ALIGNED_HI_OP
 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
@@ -11263,6 +11273,9 @@ loongarch_asm_code_end (void)
 #define TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT \
   loongarch_builtin_support_vector_misalignment
 
+#undef TARGET_C_MODE_FOR_SUFFIX
+#define TARGET_C_MODE_FOR_SUFFIX loongarch_c_mode_for_suffix
+
 struct gcc_target targetm = TARGET_INITIALIZER;
 
 #include "gt-loongarch.h"
diff --git a/gcc/testsuite/gcc.target/loongarch/pr119408.c 
b/gcc/testsuite/gcc.target/loongarch/pr119408.c
new file mode 100644
index ..f46399aa0b59
--- /dev/null
+++ b/gcc/testsuite/gcc.target/loongarch/pr119408.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -Wno-pedantic" } */
+
+__float128 a;
+__float128 b;
+void
+test (void)
+{
+  a = 1.Q;
+  b = 1.434345q;   
+}
+

[gcc r15-9115] LoongArch: doc: Put the '-mtls-dialect=opt' option description in the correct position.

[LuluCheng via Gcc-cvs]

https://gcc.gnu.org/g:f6da8c5b993a326fe0528f26b600a25a4bd7c11e

commit r15-9115-gf6da8c5b993a326fe0528f26b600a25a4bd7c11e
Author: Lulu Cheng 
Date:   Mon Mar 31 15:05:27 2025 +0800

LoongArch: doc: Put the '-mtls-dialect=opt' option description in the 
correct position.

gcc/ChangeLog:

* doc/invoke.texi: Corrected the position of '-mtls-dialect=opt'
option.

Diff:
---
 gcc/doc/invoke.texi | 16 
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 0da3f296beb0..ab4867cc5947 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -28029,6 +28029,14 @@ build with @option{-march=la664}, it is enabled by 
default.  The default is
 This option controls which tls dialect may be used for general dynamic and
 local dynamic TLS models.
 
+@table @samp
+@item trad
+Use traditional TLS. This is the default.
+
+@item desc
+Use TLS descriptors.
+@end table
+
 @opindex mannotate-tablejump
 @opindex mno-annotate-tablejump
 @item -mannotate-tablejump
@@ -28040,14 +28048,6 @@ tools, for example @file{objtool} of the Linux kernel 
building system,
 need the annotation to analysis the control flow.  The default is
 @option{-mno-annotate-tablejump}.
 
-@table @samp
-@item trad
-Use traditional TLS. This is the default.
-
-@item desc
-Use TLS descriptors.
-@end table
-
 @item --param loongarch-vect-unroll-limit=@var{n}
 The vectorizer will use available tuning information to determine whether it
 would be beneficial to unroll the main vectorized loop and by how much.  This