from:"John David Anglin via Gcc\-cvs"

[gcc r14-9342] Revert "Set num_threads to 50 on 32-bit hppa in two libgomp loop tests"

2024-03-06 Thread John David Anglin via Gcc-cvs

https://gcc.gnu.org/g:49c3f24552ee550f78416b6470b22af9be8bea72

commit r14-9342-g49c3f24552ee550f78416b6470b22af9be8bea72
Author: John David Anglin 
Date:   Wed Mar 6 17:01:59 2024 +

Revert "Set num_threads to 50 on 32-bit hppa in two libgomp loop tests"

This reverts commit b14209715e659f6d3ca0f9eef9a4851e7bd6e373.

Diff:
---
 libgomp/testsuite/libgomp.c++/loop-3.C   | 8 +---
 libgomp/testsuite/libgomp.c/omp-loop03.c | 8 +---
 2 files changed, 2 insertions(+), 14 deletions(-)

diff --git a/libgomp/testsuite/libgomp.c++/loop-3.C 
b/libgomp/testsuite/libgomp.c++/loop-3.C
index 3f460f114bf..fa50f099f3f 100644
--- a/libgomp/testsuite/libgomp.c++/loop-3.C
+++ b/libgomp/testsuite/libgomp.c++/loop-3.C
@@ -1,9 +1,3 @@
-#if defined(__hppa__) && !defined(__LP64__)
-#define NUM_THREADS 50
-#else
-#define NUM_THREADS 64
-#endif
-
 extern "C" void abort (void);
 int a;
 
@@ -25,7 +19,7 @@ foo ()
 int
 main (void)
 {
-#pragma omp parallel num_threads (NUM_THREADS)
+#pragma omp parallel num_threads (64)
   foo ();
 
   return 0;
diff --git a/libgomp/testsuite/libgomp.c/omp-loop03.c 
b/libgomp/testsuite/libgomp.c/omp-loop03.c
index 9879981cf4a..7bb9a194331 100644
--- a/libgomp/testsuite/libgomp.c/omp-loop03.c
+++ b/libgomp/testsuite/libgomp.c/omp-loop03.c
@@ -1,9 +1,3 @@
-#if defined(__hppa__) && !defined(__LP64__)
-#define NUM_THREADS 50
-#else
-#define NUM_THREADS 64
-#endif
-
 extern void abort (void);
 int a;
 
@@ -25,7 +19,7 @@ foo ()
 int
 main (void)
 {
-#pragma omp parallel num_threads (NUM_THREADS)
+#pragma omp parallel num_threads (64)
   foo ();
 
   return 0;

[gcc r15-3307] hppa: Fix handling of unscaled index addresses on HP-UX

2024-08-29 Thread John David Anglin via Gcc-cvs

https://gcc.gnu.org/g:81c47986e1d8efa70a4bd28e8dfc62bfca8e8362

commit r15-3307-g81c47986e1d8efa70a4bd28e8dfc62bfca8e8362
Author: John David Anglin 
Date:   Thu Aug 29 11:53:45 2024 -0400

hppa: Fix handling of unscaled index addresses on HP-UX

The PA-RISC architecture uses the top two bits of memory pointers
to select space registers.  The space register ID is ored with the
pointer offset to compute the global virtual address for an access.

The new late combine passes broke gcc on HP-UX.  One of these passes
runs after reload.  The existing code assumed no unscaled index
instructions would be created after reload as the REG_POINTER flag
is not reliable after reload.  The new pass sometimes interchanged
the base and index registers, causing these instructions to fault
when the wrong space register was selected.

I investigated various alternatives to try to retain generation
of unscaled index instructions on HP-UX.  It's not possible to
simply treat unscaled index addresses as not legitimate after
reload as sometimes instructions need to be rerecognized after
reload.  So, we needed to allow unscaled index addresses after
reload and to disable the late combine passes.

I had noticed that reversing the current order of base and index
register canonicalization resulted in more accesses using unscaled
index addresses.  However, this exposed issues with the REG_POINTER
flag.

The flag is not propagated when a constant is added to a pointer.
Tree opimization sometimes adds two pointers.  I found that I had
to treat the result as a pointer but the addition generally corrupts
the space register bits.  These get fixed when a negative pointer
is added.  Finally, the REG_POINTER flag isn't set when a pointer
is passed in a function call.  I couldn't get this approach to work.

Thus, I came to the conclusion that the best approach was to
disable use of unscaled index addresses on HP-UX.  I don't think
this impacts performance significantly.  Code size might get
slightly larger but we get some or more back from having the late
combine passes.

2024-08-29  John David Anglin  

gcc/ChangeLog:

* config/pa/pa.cc (load_reg): Don't generate load with
unscaled index address when !TARGET_NO_SPACE_REGS.
(pa_legitimate_address_p): Only allow unscaled index
addresses when TARGET_NO_SPACE_REGS.

Diff:
---
 gcc/config/pa/pa.cc | 20 
 1 file changed, 8 insertions(+), 12 deletions(-)

diff --git a/gcc/config/pa/pa.cc b/gcc/config/pa/pa.cc
index 911b7d96e9b6..297ec3a6f69b 100644
--- a/gcc/config/pa/pa.cc
+++ b/gcc/config/pa/pa.cc
@@ -4517,7 +4517,7 @@ load_reg (int reg, HOST_WIDE_INT disp, int base)
   rtx tmpreg = gen_rtx_REG (Pmode, 1);
 
   emit_move_insn (tmpreg, delta);
-  if (TARGET_DISABLE_INDEXING)
+  if (!TARGET_NO_SPACE_REGS || TARGET_DISABLE_INDEXING)
{
  emit_move_insn (tmpreg, gen_rtx_PLUS (Pmode, tmpreg, basereg));
  src = gen_rtx_MEM (word_mode, tmpreg);
@@ -11009,17 +11009,13 @@ pa_legitimate_address_p (machine_mode mode, rtx x, 
bool strict, code_helper)
}
 
   if (!TARGET_DISABLE_INDEXING
- /* Only accept the "canonical" INDEX+BASE operand order
-on targets with non-equivalent space registers.  */
- && (TARGET_NO_SPACE_REGS
- ? REG_P (index)
- : (base == XEXP (x, 1) && REG_P (index)
-&& (reload_completed
-|| (reload_in_progress && HARD_REGISTER_P (base))
-|| REG_POINTER (base))
-&& (reload_completed
-|| (reload_in_progress && HARD_REGISTER_P (index))
-|| !REG_POINTER (index
+ /* Currently, the REG_POINTER flag is not set in a variety
+of situations (e.g., call arguments and pointer arithmetic).
+As a result, we can't reliably determine when unscaled
+addresses are legitimate on targets that need space register
+selection.  */
+ && TARGET_NO_SPACE_REGS
+ && REG_P (index)
  && MODE_OK_FOR_UNSCALED_INDEXING_P (mode)
  && (strict ? STRICT_REG_OK_FOR_INDEX_P (index)
 : REG_OK_FOR_INDEX_P (index))

[gcc r15-3335] hppa: Enable PA 2.0 symbolic operands on ELF32 targets

2024-08-31 Thread John David Anglin via Gcc-cvs

https://gcc.gnu.org/g:b7e9f361088055c49cee8225a6cc0f4288458211

commit r15-3335-gb7e9f361088055c49cee8225a6cc0f4288458211
Author: John David Anglin 
Date:   Sat Aug 31 12:20:14 2024 -0400

hppa: Enable PA 2.0 symbolic operands on ELF32 targets

The GNU ELF32 linker has been fixed and it can now handle PA 2.0
symbolic relocations.

This only affects non-pic code generation.

2024-08-31  John David Anglin  

gcc/ChangeLog:

* config/pa/pa.cc (pa_emit_move_sequence): Remove symbolic
memory work arounds for TARGET_ELF32.
(pa_legitimate_address_p): Likewise.  Allow symbolic
operands.  Adjust comment.
* config/pa/pa.md: Replace reg_or_0_or_nonsymb_mem_operand
with reg_or_0_or_mem_operand predicate in various unnamed
move insns.
* config/pa/predicates.md (floating_point_store_memory_operand):
Update comment.  Remove symbolic memory work arounds for
TARGET_ELF32.
(nonsymb_mem_operand): Rename to mem_operand.  Allow
symbolic memory operands.
(reg_or_0_or_nonsymb_mem_operand): Rename to
reg_or_0_or_mem_operand.  Allow symbolic memory operands.

Diff:
---
 gcc/config/pa/pa.cc | 13 ++---
 gcc/config/pa/pa.md | 12 ++--
 gcc/config/pa/predicates.md | 27 +--
 3 files changed, 25 insertions(+), 27 deletions(-)

diff --git a/gcc/config/pa/pa.cc b/gcc/config/pa/pa.cc
index 297ec3a6f69b..631f18a0ef51 100644
--- a/gcc/config/pa/pa.cc
+++ b/gcc/config/pa/pa.cc
@@ -2043,8 +2043,7 @@ pa_emit_move_sequence (rtx *operands, machine_mode mode, 
rtx scratch_reg)
  op1 = replace_equiv_address (op1, scratch_reg);
}
}
-  else if (((TARGET_ELF32 || !TARGET_PA_20)
-   && symbolic_memory_operand (op1, VOIDmode))
+  else if ((!INT14_OK_STRICT && symbolic_memory_operand (op1, VOIDmode))
   || IS_LO_SUM_DLT_ADDR_P (XEXP (op1, 0))
   || IS_INDEX_ADDR_P (XEXP (op1, 0)))
{
@@ -2093,8 +2092,7 @@ pa_emit_move_sequence (rtx *operands, machine_mode mode, 
rtx scratch_reg)
  op0 = replace_equiv_address (op0, scratch_reg);
}
}
-  else if (((TARGET_ELF32 || !TARGET_PA_20)
-   && symbolic_memory_operand (op0, VOIDmode))
+  else if ((!INT14_OK_STRICT && symbolic_memory_operand (op0, VOIDmode))
   || IS_LO_SUM_DLT_ADDR_P (XEXP (op0, 0))
   || IS_INDEX_ADDR_P (XEXP (op0, 0)))
{
@@ -11059,20 +11057,21 @@ pa_legitimate_address_p (machine_mode mode, rtx x, 
bool strict, code_helper)
{
  y = XEXP (x, 1);
 
- /* Needed for -fPIC */
+ /* UNSPEC_DLTIND14R is always okay.  Needed for -fPIC */
  if (mode == Pmode
  && GET_CODE (y) == UNSPEC)
return true;
 
  /* Before reload, we need support for 14-bit floating
 point loads and stores, and associated relocations.  */
- if ((TARGET_ELF32 || !INT14_OK_STRICT)
+ if (!INT14_OK_STRICT
  && !reload_completed
  && mode != QImode
  && mode != HImode)
return false;
 
- if (CONSTANT_P (y))
+ if (CONSTANT_P (y)
+ || (!flag_pic && symbolic_operand (y, mode)))
return true;
}
   return false;
diff --git a/gcc/config/pa/pa.md b/gcc/config/pa/pa.md
index 9e410f43052d..1e781efb66b0 100644
--- a/gcc/config/pa/pa.md
+++ b/gcc/config/pa/pa.md
@@ -3866,7 +3866,7 @@
 (define_insn ""
   [(set (match_operand:DF 0 "move_dest_operand"
  "=f,*r,T,?o,?Q,f,*r,*r,?*r,?f")
-   (match_operand:DF 1 "reg_or_0_or_nonsymb_mem_operand"
+   (match_operand:DF 1 "reg_or_0_or_mem_operand"
  "fG,*rG,f,*r,*r,RT,o,RQ,f,*r"))]
   "(register_operand (operands[0], DFmode)
 || reg_or_0_operand (operands[1], DFmode))
@@ -4040,7 +4040,7 @@
 (define_insn ""
   [(set (match_operand:DF 0 "move_dest_operand"
  "=r,?o,?Q,r,r")
-   (match_operand:DF 1 "reg_or_0_or_nonsymb_mem_operand"
+   (match_operand:DF 1 "reg_or_0_or_mem_operand"
  "rG,r,r,o,RQ"))]
   "(register_operand (operands[0], DFmode)
 || reg_or_0_operand (operands[1], DFmode))
@@ -4440,7 +4440,7 @@
 (define_insn ""
   [(set (match_operand:SF 0 "move_dest_operand"
  "=f,!*r,f,*r,T,Q,?*r,?f")
-   (match_operand:SF 1 "reg_or_0_or_nonsymb_mem_operand"
+   (match_operand:SF 1 "reg_or_0_or_mem_operand"
  "fG,!*rG,RT,RQ,f,*rG,f,*r"))]
   "(register_operand (operands[0], SFmode)
 || reg_or_0_operand (operands[1], SFmode))
@@ -4462,7 +4462,7 @@
 (define_insn ""
   [(set (match_operand:SF 0 "move_dest_operand"
  "=f,!*r,f,*r,T,Q")
-   (match_operand:SF 1 "reg_or_0_or_nonsymb_mem_operand"
+

[gcc r15-3549] hppa: Don't canonicalize operand order of scaled index addresses

2024-09-09 Thread John David Anglin via Gcc-cvs

https://gcc.gnu.org/g:8f3b402b6fca3e4b018e99f65bf22f478e888c16

commit r15-3549-g8f3b402b6fca3e4b018e99f65bf22f478e888c16
Author: John David Anglin 
Date:   Mon Sep 9 10:23:00 2024 -0400

hppa: Don't canonicalize operand order of scaled index addresses

pa_print_operand handles both operand orders for scaled index
addresses, so it isn't necessary to canonicalize the order of
operands.

2024-09-09  John David Anglin  

gcc/ChangeLog:

* config/pa/pa.cc (pa_legitimate_address_p): Don't
canonicalize operand order of scaled index addresses.

Diff:
---
 gcc/config/pa/pa.cc | 9 -
 1 file changed, 4 insertions(+), 5 deletions(-)

diff --git a/gcc/config/pa/pa.cc b/gcc/config/pa/pa.cc
index 631f18a0ef51..84aa4f1b1f2a 100644
--- a/gcc/config/pa/pa.cc
+++ b/gcc/config/pa/pa.cc
@@ -11022,14 +11022,13 @@ pa_legitimate_address_p (machine_mode mode, rtx x, 
bool strict, code_helper)
return true;
 
   if (!TARGET_DISABLE_INDEXING
- && GET_CODE (index) == MULT
  /* Only accept base operands with the REG_POINTER flag prior to
 reload on targets with non-equivalent space registers.  */
  && (TARGET_NO_SPACE_REGS
- || (base == XEXP (x, 1)
- && (reload_completed
- || (reload_in_progress && HARD_REGISTER_P (base))
- || REG_POINTER (base
+ || reload_completed
+ || (reload_in_progress && HARD_REGISTER_P (base))
+ || REG_POINTER (base))
+ && GET_CODE (index) == MULT
  && REG_P (XEXP (index, 0))
  && GET_MODE (XEXP (index, 0)) == Pmode
  && MODE_OK_FOR_SCALED_INDEXING_P (mode)

[gcc r15-1731] hppa: Fix ICE caused by mismatched predicate and constraint in xmpyu patterns

2024-06-30 Thread John David Anglin via Gcc-cvs

https://gcc.gnu.org/g:30ad2fafa9ab2497cc12df62a3240cff6ef25d00

commit r15-1731-g30ad2fafa9ab2497cc12df62a3240cff6ef25d00
Author: John David Anglin 
Date:   Sun Jun 30 09:48:21 2024 -0400

hppa: Fix ICE caused by mismatched predicate and constraint in xmpyu 
patterns

2024-06-30  John David Anglin  

gcc/ChangeLog:

PR target/115691
* config/pa/pa.md: Remove incorrect xmpyu patterns.

Diff:
---
 gcc/config/pa/pa.md | 18 --
 1 file changed, 18 deletions(-)

diff --git a/gcc/config/pa/pa.md b/gcc/config/pa/pa.md
index b0f29a44bae..9e410f43052 100644
--- a/gcc/config/pa/pa.md
+++ b/gcc/config/pa/pa.md
@@ -5503,24 +5503,6 @@
   [(set_attr "type" "fpmuldbl")
(set_attr "length" "4")])
 
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=f")
-   (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "f"))
-(match_operand:DI 2 "uint32_operand" "f")))]
-  "TARGET_PA_11 && ! TARGET_SOFT_FLOAT && ! TARGET_SOFT_MULT && !TARGET_64BIT"
-  "xmpyu %1,%R2,%0"
-  [(set_attr "type" "fpmuldbl")
-   (set_attr "length" "4")])
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=f")
-   (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "f"))
-(match_operand:DI 2 "uint32_operand" "f")))]
-  "TARGET_PA_11 && ! TARGET_SOFT_FLOAT && ! TARGET_SOFT_MULT && TARGET_64BIT"
-  "xmpyu %1,%2R,%0"
-  [(set_attr "type" "fpmuldbl")
-   (set_attr "length" "4")])
-
 (define_insn ""
   [(set (reg:SI 29) (mult:SI (reg:SI 26) (reg:SI 25)))
(clobber (match_operand:SI 0 "register_operand" "=a"))

[gcc r14-10375] hppa: Fix ICE caused by mismatched predicate and constraint in xmpyu patterns

2024-07-03 Thread John David Anglin via Gcc-cvs

https://gcc.gnu.org/g:acde9f81da39450b90e12ccf937d35aa8da1b478

commit r14-10375-gacde9f81da39450b90e12ccf937d35aa8da1b478
Author: John David Anglin 
Date:   Sun Jun 30 09:48:21 2024 -0400

hppa: Fix ICE caused by mismatched predicate and constraint in xmpyu 
patterns

2024-06-30  John David Anglin  

gcc/ChangeLog:

PR target/115691
* config/pa/pa.md: Remove incorrect xmpyu patterns.

Diff:
---
 gcc/config/pa/pa.md | 18 --
 1 file changed, 18 deletions(-)

diff --git a/gcc/config/pa/pa.md b/gcc/config/pa/pa.md
index b0f29a44bae..9e410f43052 100644
--- a/gcc/config/pa/pa.md
+++ b/gcc/config/pa/pa.md
@@ -5503,24 +5503,6 @@
   [(set_attr "type" "fpmuldbl")
(set_attr "length" "4")])
 
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=f")
-   (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "f"))
-(match_operand:DI 2 "uint32_operand" "f")))]
-  "TARGET_PA_11 && ! TARGET_SOFT_FLOAT && ! TARGET_SOFT_MULT && !TARGET_64BIT"
-  "xmpyu %1,%R2,%0"
-  [(set_attr "type" "fpmuldbl")
-   (set_attr "length" "4")])
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=f")
-   (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "f"))
-(match_operand:DI 2 "uint32_operand" "f")))]
-  "TARGET_PA_11 && ! TARGET_SOFT_FLOAT && ! TARGET_SOFT_MULT && TARGET_64BIT"
-  "xmpyu %1,%2R,%0"
-  [(set_attr "type" "fpmuldbl")
-   (set_attr "length" "4")])
-
 (define_insn ""
   [(set (reg:SI 29) (mult:SI (reg:SI 26) (reg:SI 25)))
(clobber (match_operand:SI 0 "register_operand" "=a"))

[gcc r13-8888] hppa: Fix ICE caused by mismatched predicate and constraint in xmpyu patterns

2024-07-03 Thread John David Anglin via Gcc-cvs

https://gcc.gnu.org/g:ecd6ebe5fb0151f9649705a5798325032bbc811a

commit r13--gecd6ebe5fb0151f9649705a5798325032bbc811a
Author: John David Anglin 
Date:   Sun Jun 30 09:48:21 2024 -0400

hppa: Fix ICE caused by mismatched predicate and constraint in xmpyu 
patterns

2024-06-30  John David Anglin  

gcc/ChangeLog:

PR target/115691
* config/pa/pa.md: Remove incorrect xmpyu patterns.

Diff:
---
 gcc/config/pa/pa.md | 18 --
 1 file changed, 18 deletions(-)

diff --git a/gcc/config/pa/pa.md b/gcc/config/pa/pa.md
index 36d20576102..d832a29683c 100644
--- a/gcc/config/pa/pa.md
+++ b/gcc/config/pa/pa.md
@@ -5493,24 +5493,6 @@
   [(set_attr "type" "fpmuldbl")
(set_attr "length" "4")])
 
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=f")
-   (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "f"))
-(match_operand:DI 2 "uint32_operand" "f")))]
-  "TARGET_PA_11 && ! TARGET_SOFT_FLOAT && ! TARGET_SOFT_MULT && !TARGET_64BIT"
-  "xmpyu %1,%R2,%0"
-  [(set_attr "type" "fpmuldbl")
-   (set_attr "length" "4")])
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=f")
-   (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "f"))
-(match_operand:DI 2 "uint32_operand" "f")))]
-  "TARGET_PA_11 && ! TARGET_SOFT_FLOAT && ! TARGET_SOFT_MULT && TARGET_64BIT"
-  "xmpyu %1,%2R,%0"
-  [(set_attr "type" "fpmuldbl")
-   (set_attr "length" "4")])
-
 (define_insn ""
   [(set (reg:SI 29) (mult:SI (reg:SI 26) (reg:SI 25)))
(clobber (match_operand:SI 0 "register_operand" "=a"))

[gcc r12-10597] hppa: Fix ICE caused by mismatched predicate and constraint in xmpyu patterns

2024-07-03 Thread John David Anglin via Gcc-cvs

https://gcc.gnu.org/g:0c98d9479cec88148eb3be8d0098e36bce061cd6

commit r12-10597-g0c98d9479cec88148eb3be8d0098e36bce061cd6
Author: John David Anglin 
Date:   Sun Jun 30 09:48:21 2024 -0400

hppa: Fix ICE caused by mismatched predicate and constraint in xmpyu 
patterns

2024-06-30  John David Anglin  

gcc/ChangeLog:

PR target/115691
* config/pa/pa.md: Remove incorrect xmpyu patterns.

Diff:
---
 gcc/config/pa/pa.md | 18 --
 1 file changed, 18 deletions(-)

diff --git a/gcc/config/pa/pa.md b/gcc/config/pa/pa.md
index d82f168c8a3..43241958722 100644
--- a/gcc/config/pa/pa.md
+++ b/gcc/config/pa/pa.md
@@ -5493,24 +5493,6 @@
   [(set_attr "type" "fpmuldbl")
(set_attr "length" "4")])
 
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=f")
-   (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "f"))
-(match_operand:DI 2 "uint32_operand" "f")))]
-  "TARGET_PA_11 && ! TARGET_SOFT_FLOAT && ! TARGET_SOFT_MULT && !TARGET_64BIT"
-  "xmpyu %1,%R2,%0"
-  [(set_attr "type" "fpmuldbl")
-   (set_attr "length" "4")])
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=f")
-   (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "f"))
-(match_operand:DI 2 "uint32_operand" "f")))]
-  "TARGET_PA_11 && ! TARGET_SOFT_FLOAT && ! TARGET_SOFT_MULT && TARGET_64BIT"
-  "xmpyu %1,%2R,%0"
-  [(set_attr "type" "fpmuldbl")
-   (set_attr "length" "4")])
-
 (define_insn ""
   [(set (reg:SI 29) (mult:SI (reg:SI 26) (reg:SI 25)))
(clobber (match_operand:SI 0 "register_operand" "=a"))

[gcc r11-11555] hppa: Fix ICE caused by mismatched predicate and constraint in xmpyu patterns

2024-07-03 Thread John David Anglin via Gcc-cvs

https://gcc.gnu.org/g:ce713016fb50796e906e39ba4244fbaf47ae77a9

commit r11-11555-gce713016fb50796e906e39ba4244fbaf47ae77a9
Author: John David Anglin 
Date:   Sun Jun 30 09:48:21 2024 -0400

hppa: Fix ICE caused by mismatched predicate and constraint in xmpyu 
patterns

2024-06-30  John David Anglin  

gcc/ChangeLog:

PR target/115691
* config/pa/pa.md: Remove incorrect xmpyu patterns.

Diff:
---
 gcc/config/pa/pa.md | 18 --
 1 file changed, 18 deletions(-)

diff --git a/gcc/config/pa/pa.md b/gcc/config/pa/pa.md
index b252486fa94..072e62455d8 100644
--- a/gcc/config/pa/pa.md
+++ b/gcc/config/pa/pa.md
@@ -5493,24 +5493,6 @@
   [(set_attr "type" "fpmuldbl")
(set_attr "length" "4")])
 
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=f")
-   (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "f"))
-(match_operand:DI 2 "uint32_operand" "f")))]
-  "TARGET_PA_11 && ! TARGET_SOFT_FLOAT && ! TARGET_SOFT_MULT && !TARGET_64BIT"
-  "xmpyu %1,%R2,%0"
-  [(set_attr "type" "fpmuldbl")
-   (set_attr "length" "4")])
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=f")
-   (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "f"))
-(match_operand:DI 2 "uint32_operand" "f")))]
-  "TARGET_PA_11 && ! TARGET_SOFT_FLOAT && ! TARGET_SOFT_MULT && TARGET_64BIT"
-  "xmpyu %1,%2R,%0"
-  [(set_attr "type" "fpmuldbl")
-   (set_attr "length" "4")])
-
 (define_insn ""
   [(set (reg:SI 29) (mult:SI (reg:SI 26) (reg:SI 25)))
(clobber (match_operand:SI 0 "register_operand" "=a"))

[gcc r15-1827] Revert "Delete MALLOC_ABI_ALIGNMENT define from pa32-linux.h"

2024-07-03 Thread John David Anglin via Gcc-cvs

https://gcc.gnu.org/g:ad2206d576603c94b0c1778c84b7f43fbf8a13b4

commit r15-1827-gad2206d576603c94b0c1778c84b7f43fbf8a13b4
Author: John David Anglin 
Date:   Wed Jul 3 14:34:47 2024 -0400

Revert "Delete MALLOC_ABI_ALIGNMENT define from pa32-linux.h"

This reverts commit 0ee3266b3dec4d984d43c79e2b3e649256e3eaaa.

Diff:
---
 gcc/config/pa/pa32-linux.h | 5 +
 1 file changed, 5 insertions(+)

diff --git a/gcc/config/pa/pa32-linux.h b/gcc/config/pa/pa32-linux.h
index 63abba26deb..187ae62b0f8 100644
--- a/gcc/config/pa/pa32-linux.h
+++ b/gcc/config/pa/pa32-linux.h
@@ -68,6 +68,11 @@ call_ ## FUNC (void) \
 #undef  WCHAR_TYPE_SIZE
 #define WCHAR_TYPE_SIZE BITS_PER_WORD
 
+/* POSIX types such as pthread_mutex_t require 16-byte alignment to retain
+   layout compatibility with the original linux thread implementation.  */
+#undef MALLOC_ABI_ALIGNMENT
+#define MALLOC_ABI_ALIGNMENT 128
+
 /* Place jump tables in the text section except when generating non-PIC
code.  When generating non-PIC code, the relocations needed to load the
address of the jump table result in a text label in the final executable

[gcc r14-10376] Revert "Delete MALLOC_ABI_ALIGNMENT define from pa32-linux.h"

2024-07-03 Thread John David Anglin via Gcc-cvs

https://gcc.gnu.org/g:6e1fb1f9db3b722598a7332b92f4470a7bbc9c95

commit r14-10376-g6e1fb1f9db3b722598a7332b92f4470a7bbc9c95
Author: John David Anglin 
Date:   Wed Jul 3 14:34:47 2024 -0400

Revert "Delete MALLOC_ABI_ALIGNMENT define from pa32-linux.h"

This reverts commit 0ee3266b3dec4d984d43c79e2b3e649256e3eaaa.

Diff:
---
 gcc/config/pa/pa32-linux.h | 5 +
 1 file changed, 5 insertions(+)

diff --git a/gcc/config/pa/pa32-linux.h b/gcc/config/pa/pa32-linux.h
index 63abba26deb..187ae62b0f8 100644
--- a/gcc/config/pa/pa32-linux.h
+++ b/gcc/config/pa/pa32-linux.h
@@ -68,6 +68,11 @@ call_ ## FUNC (void) \
 #undef  WCHAR_TYPE_SIZE
 #define WCHAR_TYPE_SIZE BITS_PER_WORD
 
+/* POSIX types such as pthread_mutex_t require 16-byte alignment to retain
+   layout compatibility with the original linux thread implementation.  */
+#undef MALLOC_ABI_ALIGNMENT
+#define MALLOC_ABI_ALIGNMENT 128
+
 /* Place jump tables in the text section except when generating non-PIC
code.  When generating non-PIC code, the relocations needed to load the
address of the jump table result in a text label in the final executable

[gcc r15-1843] Skip 30_threads/future/members/poll.cc on hppa--linux*

2024-07-04 Thread John David Anglin via Gcc-cvs

https://gcc.gnu.org/g:46ffda9bf19abeed95e9d758ed5e776ee221ee9e

commit r15-1843-g46ffda9bf19abeed95e9d758ed5e776ee221ee9e
Author: John David Anglin 
Date:   Thu Jul 4 09:16:18 2024 -0400

Skip 30_threads/future/members/poll.cc on hppa*-*-linux*

hppa*-*-linux* lacks high resolution timer support. Timer resolution
ranges from 1 to 10ms. As a result, a large number of iterations are
needed for the wait_for_0 and ready loops. This causes the
wait_until_sys_epoch and wait_until_steady_epoch loops to timeout.
There the loop wait time is determined by the timer resolution.

2024-07-04  John David Anglin  

libstdc++-v3/ChangeLog:
PR libstdc++/98678
* testsuite/30_threads/future/members/poll.cc: Skip on 
hppa*-*-linux*.

Diff:
---
 libstdc++-v3/testsuite/30_threads/future/members/poll.cc | 1 +
 1 file changed, 1 insertion(+)

diff --git a/libstdc++-v3/testsuite/30_threads/future/members/poll.cc 
b/libstdc++-v3/testsuite/30_threads/future/members/poll.cc
index 4fa282bd87f..2bdbe7a48ce 100644
--- a/libstdc++-v3/testsuite/30_threads/future/members/poll.cc
+++ b/libstdc++-v3/testsuite/30_threads/future/members/poll.cc
@@ -19,6 +19,7 @@
 // { dg-do run { target c++11 } }
 // { dg-additional-options "-pthread" { target pthread } }
 // { dg-require-gthreads "" }
+// { dg-skip-if "no high resolution timer support" { hppa*-*-linux* } }
 
 #include 
 #include

[gcc r14-9482] hppa: Fix REG+D address support before reload

2024-03-14 Thread John David Anglin via Gcc-cvs

https://gcc.gnu.org/g:53fd0f5b1fd737a208c12909fa1188281cb370a3

commit r14-9482-g53fd0f5b1fd737a208c12909fa1188281cb370a3
Author: John David Anglin 
Date:   Thu Mar 14 18:32:56 2024 +

hppa: Fix REG+D address support before reload

When generating PA 1.x code or code for GNU ld, floating-point
accesses only support 5-bit displacements but integer accesses
support 14-bit displacements.  I mistakenly assumed reload
could fix an invalid 14-bit displacement in a floating-point
access but this is not the case.

2024-03-14  John David Anglin  

gcc/ChangeLog:

PR target/114288
* config/pa/pa.cc (pa_legitimate_address_p): Don't allow
14-bit displacements before reload for modes that may use
a floating-point load or store.

Diff:
---
 gcc/config/pa/pa.cc | 15 +--
 1 file changed, 5 insertions(+), 10 deletions(-)

diff --git a/gcc/config/pa/pa.cc b/gcc/config/pa/pa.cc
index 694123e37c9..129289f8e62 100644
--- a/gcc/config/pa/pa.cc
+++ b/gcc/config/pa/pa.cc
@@ -10968,20 +10968,15 @@ pa_legitimate_address_p (machine_mode mode, rtx x, 
bool strict, code_helper)
 
  /* Long 14-bit displacements always okay for these cases.  */
  if (INT14_OK_STRICT
+ || reload_completed
  || mode == QImode
  || mode == HImode)
return true;
 
- /* A secondary reload may be needed to adjust the displacement
-of floating-point accesses when STRICT is nonzero.  */
- if (strict)
-   return false;
-
- /* We get significantly better code if we allow long displacements
-before reload for all accesses.  Instructions must satisfy their
-constraints after reload, so we must have an integer access.
-Return true for both cases.  */
- return true;
+ /* We have to limit displacements to those supported by
+both floating-point and integer accesses as reload can't
+fix invalid displacements.  See PR114288.  */
+ return false;
}
 
   if (!TARGET_DISABLE_INDEXING

[gcc r14-9508] hppa: Fix complaint about non-delegitimized UNSPEC UNSPEC_TP

2024-03-17 Thread John David Anglin via Gcc-cvs

https://gcc.gnu.org/g:8064107535328717aeb78418edf778559cd5c3ac

commit r14-9508-g8064107535328717aeb78418edf778559cd5c3ac
Author: John David Anglin 
Date:   Sun Mar 17 16:38:48 2024 +

hppa: Fix complaint about non-delegitimized UNSPEC UNSPEC_TP

2024-03-17  John David Anglin  

gcc/ChangeLog:

* config/pa/pa.cc (pa_delegitimize_address): Delegitimize UNSPEC_TP.

Diff:
---
 gcc/config/pa/pa.cc | 8 +++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/gcc/config/pa/pa.cc b/gcc/config/pa/pa.cc
index 129289f8e62..5ab9eff4b5e 100644
--- a/gcc/config/pa/pa.cc
+++ b/gcc/config/pa/pa.cc
@@ -10707,7 +10707,13 @@ pa_trampoline_adjust_address (rtx addr)
 static rtx
 pa_delegitimize_address (rtx orig_x)
 {
-  rtx x = delegitimize_mem_from_attrs (orig_x);
+  rtx x;
+
+  if (GET_CODE (orig_x) == UNSPEC
+  && XINT (orig_x, 1) == UNSPEC_TP)
+orig_x = XVECEXP (orig_x, 0, 0);
+
+  x = delegitimize_mem_from_attrs (orig_x);
 
   if (GET_CODE (x) == LO_SUM
   && GET_CODE (XEXP (x, 1)) == UNSPEC

[gcc r14-9511] hppa: Improve handling of REG+D addresses when generating PA 2.0 code

2024-03-17 Thread John David Anglin via Gcc-cvs

https://gcc.gnu.org/g:f0fda1aff0b752e4182c009c5526b9306bd35f7c

commit r14-9511-gf0fda1aff0b752e4182c009c5526b9306bd35f7c
Author: John David Anglin 
Date:   Mon Mar 18 00:19:36 2024 +

hppa: Improve handling of REG+D addresses when generating PA 2.0 code

In looking at PR 112415, it became clear that improvements could be
made in the handling of loads and stores using REG+D addresses.  A
change in 2002 conflated two issues:

1) We can't generate insns with 14-bit displacements before reload
completes when generating PA 1.x code since floating-point loads and
stores only support 5-bit offsets in PA 1.x.

2) The GNU ELF 32-bit linker lacks relocation support for PA 2.0
floating point instructions with 14-bit displacements.  These
relocations affect instructions with symbolic references.

The result of the change was to block creation of PA 2.0 instructions
with 14-bit REG_D displacements for SImode, DImode, SFmode and DFmode
on the GNU linux target before reload.  This was unnecessary as these
instructions don't need relocation.

This change revises the INT14_OK_STRICT define to allow creation
of instructions with 14-bit REG+D addresses before reload when
generating PA 2.0 code.

2024-03-17  John David Anglin  

gcc/ChangeLog:

PR rtl-optimization/112415
* config/pa/pa.cc (pa_emit_move_sequence): Revise condition
for symbolic memory operands.
(pa_legitimate_address_p): Revise LO_SUM condition.
* config/pa/pa.h (INT14_OK_STRICT): Revise define.  Move
comment about GNU linker to predicates.md.
* config/pa/predicates.md (floating_point_store_memory_operand):
Revise condition for symbolic memory operands.  Update
comment.

Diff:
---
 gcc/config/pa/pa.cc | 18 --
 gcc/config/pa/pa.h  | 15 ++-
 gcc/config/pa/predicates.md | 17 +++--
 3 files changed, 25 insertions(+), 25 deletions(-)

diff --git a/gcc/config/pa/pa.cc b/gcc/config/pa/pa.cc
index 5ab9eff4b5e..d7666103de8 100644
--- a/gcc/config/pa/pa.cc
+++ b/gcc/config/pa/pa.cc
@@ -2039,7 +2039,8 @@ pa_emit_move_sequence (rtx *operands, machine_mode mode, 
rtx scratch_reg)
  op1 = replace_equiv_address (op1, scratch_reg);
}
}
-  else if ((!INT14_OK_STRICT && symbolic_memory_operand (op1, VOIDmode))
+  else if (((TARGET_ELF32 || !TARGET_PA_20)
+   && symbolic_memory_operand (op1, VOIDmode))
   || IS_LO_SUM_DLT_ADDR_P (XEXP (op1, 0))
   || IS_INDEX_ADDR_P (XEXP (op1, 0)))
{
@@ -2088,7 +2089,8 @@ pa_emit_move_sequence (rtx *operands, machine_mode mode, 
rtx scratch_reg)
  op0 = replace_equiv_address (op0, scratch_reg);
}
}
-  else if ((!INT14_OK_STRICT && symbolic_memory_operand (op0, VOIDmode))
+  else if (((TARGET_ELF32 || !TARGET_PA_20)
+   && symbolic_memory_operand (op0, VOIDmode))
   || IS_LO_SUM_DLT_ADDR_P (XEXP (op0, 0))
   || IS_INDEX_ADDR_P (XEXP (op0, 0)))
{
@@ -11038,18 +11040,22 @@ pa_legitimate_address_p (machine_mode mode, rtx x, 
bool strict, code_helper)
  && (strict ? STRICT_REG_OK_FOR_BASE_P (y)
 : REG_OK_FOR_BASE_P (y)))
{
+ y = XEXP (x, 1);
+
  /* Needed for -fPIC */
  if (mode == Pmode
- && GET_CODE (XEXP (x, 1)) == UNSPEC)
+ && GET_CODE (y) == UNSPEC)
return true;
 
- if (!INT14_OK_STRICT
- && (strict || !(reload_in_progress || reload_completed))
+ /* Before reload, we need support for 14-bit floating
+point loads and stores, and associated relocations.  */
+ if ((TARGET_ELF32 || !INT14_OK_STRICT)
+ && !reload_completed
  && mode != QImode
  && mode != HImode)
return false;
 
- if (CONSTANT_P (XEXP (x, 1)))
+ if (CONSTANT_P (y))
return true;
}
   return false;
diff --git a/gcc/config/pa/pa.h b/gcc/config/pa/pa.h
index 7abaeae269e..403f16c5cb5 100644
--- a/gcc/config/pa/pa.h
+++ b/gcc/config/pa/pa.h
@@ -828,19 +828,8 @@ extern int may_call_alloca;
 
 /* Nonzero if 14-bit offsets can be used for all loads and stores.
This is not possible when generating PA 1.x code as floating point
-   accesses only support 5-bit offsets.  Note that we do not forbid
-   the use of 14-bit offsets prior to reload.  Instead, we use secondary
-   reloads to fix REG+D memory addresses for floating-point accesses.
-
-   FIXME: the GNU ELF linker clobbers the LSB of the FP register number
-   in PA 2.0 floating-point insns with long displacements.  This is
-   because R_PARISC_DPREL14WR and other relocations like it are not
-   yet supported by GNU ld.  For now, we reject long displacements
-   on this t

[gcc r14-9645] hppa: Fix LO_SUM DLTIND14R address support in PRINT_OPERAND_ADDRESS

2024-03-23 Thread John David Anglin via Gcc-cvs

https://gcc.gnu.org/g:2e4b3374cb7af10e188bb5100526ad3150b9b272

commit r14-9645-g2e4b3374cb7af10e188bb5100526ad3150b9b272
Author: John David Anglin 
Date:   Sat Mar 23 13:47:31 2024 +

hppa: Fix LO_SUM DLTIND14R address support in PRINT_OPERAND_ADDRESS

This bug was hidden since LO_SUM DLTIND14R addresses are normally
handled by the A constraint in the move patterns.

2024-03-23  John David Anglin  

gcc/ChangeLog:

* config/pa/pa.cc (pa_output_global_address): Handle
UNSPEC_DLTIND14R addresses.
* config/pa/pa.h (PRINT_OPERAND_ADDRESS): Output "RT'" for
UNSPEC_DLTIND14R address.

Diff:
---
 gcc/config/pa/pa.cc | 7 ++-
 gcc/config/pa/pa.h  | 7 +--
 2 files changed, 11 insertions(+), 3 deletions(-)

diff --git a/gcc/config/pa/pa.cc b/gcc/config/pa/pa.cc
index d7666103de8..a7af6b8c121 100644
--- a/gcc/config/pa/pa.cc
+++ b/gcc/config/pa/pa.cc
@@ -5784,7 +5784,12 @@ pa_output_global_address (FILE *file, rtx x, int 
round_constant)
   if (GET_CODE (x) == HIGH)
 x = XEXP (x, 0);
 
-  if (GET_CODE (x) == SYMBOL_REF && read_only_operand (x, VOIDmode))
+  if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_DLTIND14R)
+{
+  x = XVECEXP (x, 0, 0);
+  output_addr_const (file, x);
+}
+  else if (GET_CODE (x) == SYMBOL_REF && read_only_operand (x, VOIDmode))
 output_addr_const (file, x);
   else if (GET_CODE (x) == SYMBOL_REF && !flag_pic)
 {
diff --git a/gcc/config/pa/pa.h b/gcc/config/pa/pa.h
index 403f16c5cb5..127a0d1966d 100644
--- a/gcc/config/pa/pa.h
+++ b/gcc/config/pa/pa.h
@@ -1247,12 +1247,15 @@ do {
 \
   reg_names [REGNO (XEXP (addr, 0))]); \
   break;   \
 case LO_SUM:   \
-  if (!symbolic_operand (XEXP (addr, 1), VOIDmode))
\
+  if (GET_CODE (XEXP (addr, 1)) == UNSPEC  \
+ && XINT (XEXP (addr, 1), 1) == UNSPEC_DLTIND14R)  \
+   fputs ("RT'", FILE);\
+  else if (!symbolic_operand (XEXP (addr, 1), VOIDmode))   \
fputs ("R'", FILE); \
   else if (flag_pic == 0)  \
fputs ("RR'", FILE);\
   else \
-   fputs ("RT'", FILE);\
+   gcc_unreachable (); \
   pa_output_global_address (FILE, XEXP (addr, 1), 0);  \
   fputs ("(", FILE);   \
   output_operand (XEXP (addr, 0), 0);  \

[gcc r14-9714] Fix failure of c-c++-common/analyzer/stdarg-pr111289-int.c on hpux

2024-03-28 Thread John David Anglin via Gcc-cvs

https://gcc.gnu.org/g:86b0b1bec6790f84b7a56fcef2a0a6c8cd91ffef

commit r14-9714-g86b0b1bec6790f84b7a56fcef2a0a6c8cd91ffef
Author: John David Anglin 
Date:   Thu Mar 28 18:32:12 2024 +

Fix failure of c-c++-common/analyzer/stdarg-pr111289-int.c on hpux

2024-03-28  John David Anglin  

gcc/testsuite/ChangeLog:

PR analyzer/111289
* c-c++-common/analyzer/stdarg-pr111289-int.c: Don't include
.

Diff:
---
 gcc/testsuite/c-c++-common/analyzer/stdarg-pr111289-int.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/gcc/testsuite/c-c++-common/analyzer/stdarg-pr111289-int.c 
b/gcc/testsuite/c-c++-common/analyzer/stdarg-pr111289-int.c
index 33d83169c3e..8faa58c9480 100644
--- a/gcc/testsuite/c-c++-common/analyzer/stdarg-pr111289-int.c
+++ b/gcc/testsuite/c-c++-common/analyzer/stdarg-pr111289-int.c
@@ -1,6 +1,5 @@
 #include 
 #include 
-#include 
 
 typedef unsigned int mode_t;

[gcc r15-2365] testsuite: Fix unaligned accesses in ipa-sra-8.c and ipa-sra-9.c

2024-07-28 Thread John David Anglin via Gcc-cvs

https://gcc.gnu.org/g:59c6d6a5b53d7b0e483a686f6b9db093bb77c064

commit r15-2365-g59c6d6a5b53d7b0e483a686f6b9db093bb77c064
Author: John David Anglin 
Date:   Sun Jul 28 13:34:54 2024 -0400

testsuite: Fix unaligned accesses in ipa-sra-8.c and ipa-sra-9.c

2024-07-28  John David Anglin  

gcc/testsuite/ChangeLog:

PR testsuite/92550
* gcc.dg/ipa/ipa-sra-8.c: Change get_a argument type to SSS.
* gcc.dg/ipa/ipa-sra-9.c: Likewise.

Diff:
---
 gcc/testsuite/gcc.dg/ipa/ipa-sra-8.c | 2 +-
 gcc/testsuite/gcc.dg/ipa/ipa-sra-9.c | 4 +++-
 2 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/gcc/testsuite/gcc.dg/ipa/ipa-sra-8.c 
b/gcc/testsuite/gcc.dg/ipa/ipa-sra-8.c
index 9e6e40ac54df..dd5c5d0c32b4 100644
--- a/gcc/testsuite/gcc.dg/ipa/ipa-sra-8.c
+++ b/gcc/testsuite/gcc.dg/ipa/ipa-sra-8.c
@@ -11,7 +11,7 @@ typedef SS __attribute__((aligned(1))) SSS;
 
 
 static unsigned int __attribute__ ((noinline))
-get_a (SS s)
+get_a (SSS s)
 {
   return s.a;
 };
diff --git a/gcc/testsuite/gcc.dg/ipa/ipa-sra-9.c 
b/gcc/testsuite/gcc.dg/ipa/ipa-sra-9.c
index c5468cfbb76a..41d7ddd9fecb 100644
--- a/gcc/testsuite/gcc.dg/ipa/ipa-sra-9.c
+++ b/gcc/testsuite/gcc.dg/ipa/ipa-sra-9.c
@@ -7,6 +7,8 @@ typedef struct S {
   unsigned a, b, c;
 } SS;
 
+typedef SS __attribute__((aligned(1))) SSS;
+
 typedef struct U {
   SS s[2];
 } UU;
@@ -14,7 +16,7 @@ typedef struct U {
 typedef UU __attribute__((aligned(1))) UUU;
 
 static unsigned int __attribute__ ((noinline))
-get_a (SS s)
+get_a (SSS s)
 {
   return s.a;
 };

[gcc r15-2765] hppa: Fix (plus (plus (mult (a) (mem_shadd_constant)) (b)) (c)) optimization

2024-08-06 Thread John David Anglin via Gcc-cvs

https://gcc.gnu.org/g:dc01f249db5c4d08b76dc2783b1539290a800f2d

commit r15-2765-gdc01f249db5c4d08b76dc2783b1539290a800f2d
Author: John David Anglin 
Date:   Tue Aug 6 13:40:26 2024 -0400

hppa: Fix (plus (plus (mult (a) (mem_shadd_constant)) (b)) (c)) optimization

The constant C must be an integral multiple of the shift value in
the above optimization.  Non integral values can occur evaluating
IMAGPART_EXPR when the shadd constant is 8 and we have SFmode.

2024-08-06  John David Anglin  

gcc/ChangeLog:

PR target/113384
* config/pa/pa.cc (hppa_legitimize_address): Add check to
ensure constant is an integral multiple of shift the value.

Diff:
---
 gcc/config/pa/pa.cc | 1 +
 1 file changed, 1 insertion(+)

diff --git a/gcc/config/pa/pa.cc b/gcc/config/pa/pa.cc
index ab4bfc5d0c26..911b7d96e9b6 100644
--- a/gcc/config/pa/pa.cc
+++ b/gcc/config/pa/pa.cc
@@ -1410,6 +1410,7 @@ hppa_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
   /* If the index adds a large constant, try to scale the
 constant so that it can be loaded with only one insn.  */
   if (GET_CODE (XEXP (idx, 1)) == CONST_INT
+ && INTVAL (XEXP (idx, 1)) % (1 << shift_val) == 0
  && VAL_14_BITS_P (INTVAL (XEXP (idx, 1))
/ INTVAL (XEXP (XEXP (idx, 0), 1)))
  && INTVAL (XEXP (idx, 1)) % INTVAL (XEXP (XEXP (idx, 0), 1)) == 0)

[gcc r14-10568] hppa: Fix (plus (plus (mult (a) (mem_shadd_constant)) (b)) (c)) optimization

2024-08-06 Thread John David Anglin via Gcc-cvs

https://gcc.gnu.org/g:ba26c471cf6ee760e53836fd4e9bc00250b8b882

commit r14-10568-gba26c471cf6ee760e53836fd4e9bc00250b8b882
Author: John David Anglin 
Date:   Tue Aug 6 13:40:26 2024 -0400

hppa: Fix (plus (plus (mult (a) (mem_shadd_constant)) (b)) (c)) optimization

The constant C must be an integral multiple of the shift value in
the above optimization.  Non integral values can occur evaluating
IMAGPART_EXPR when the shadd constant is 8 and we have SFmode.

2024-08-06  John David Anglin  

gcc/ChangeLog:

PR target/113384
* config/pa/pa.cc (hppa_legitimize_address): Add check to
ensure constant is an integral multiple of shift the value.

Diff:
---
 gcc/config/pa/pa.cc | 1 +
 1 file changed, 1 insertion(+)

diff --git a/gcc/config/pa/pa.cc b/gcc/config/pa/pa.cc
index a7af6b8c121f..b24434628fa5 100644
--- a/gcc/config/pa/pa.cc
+++ b/gcc/config/pa/pa.cc
@@ -1407,6 +1407,7 @@ hppa_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
   /* If the index adds a large constant, try to scale the
 constant so that it can be loaded with only one insn.  */
   if (GET_CODE (XEXP (idx, 1)) == CONST_INT
+ && INTVAL (XEXP (idx, 1)) % (1 << shift_val) == 0
  && VAL_14_BITS_P (INTVAL (XEXP (idx, 1))
/ INTVAL (XEXP (XEXP (idx, 0), 1)))
  && INTVAL (XEXP (idx, 1)) % INTVAL (XEXP (XEXP (idx, 0), 1)) == 0)

[gcc r13-8963] hppa: Fix (plus (plus (mult (a) (mem_shadd_constant)) (b)) (c)) optimization

2024-08-06 Thread John David Anglin via Gcc-cvs

https://gcc.gnu.org/g:f6624adc535a165ab667646c57b73e213d868cca

commit r13-8963-gf6624adc535a165ab667646c57b73e213d868cca
Author: John David Anglin 
Date:   Tue Aug 6 13:40:26 2024 -0400

hppa: Fix (plus (plus (mult (a) (mem_shadd_constant)) (b)) (c)) optimization

The constant C must be an integral multiple of the shift value in
the above optimization.  Non integral values can occur evaluating
IMAGPART_EXPR when the shadd constant is 8 and we have SFmode.

2024-08-06  John David Anglin  

gcc/ChangeLog:

PR target/113384
* config/pa/pa.cc (hppa_legitimize_address): Add check to
ensure constant is an integral multiple of shift the value.

Diff:
---
 gcc/config/pa/pa.cc | 1 +
 1 file changed, 1 insertion(+)

diff --git a/gcc/config/pa/pa.cc b/gcc/config/pa/pa.cc
index 3e2ae9fa677f..8ed376a9f49a 100644
--- a/gcc/config/pa/pa.cc
+++ b/gcc/config/pa/pa.cc
@@ -1263,6 +1263,7 @@ hppa_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
   /* If the index adds a large constant, try to scale the
 constant so that it can be loaded with only one insn.  */
   if (GET_CODE (XEXP (idx, 1)) == CONST_INT
+ && INTVAL (XEXP (idx, 1)) % (1 << shift_val) == 0
  && VAL_14_BITS_P (INTVAL (XEXP (idx, 1))
/ INTVAL (XEXP (XEXP (idx, 0), 1)))
  && INTVAL (XEXP (idx, 1)) % INTVAL (XEXP (XEXP (idx, 0), 1)) == 0)

[gcc r12-10661] hppa: Fix (plus (plus (mult (a) (mem_shadd_constant)) (b)) (c)) optimization

2024-08-06 Thread John David Anglin via Gcc-cvs

https://gcc.gnu.org/g:960e42bba8d276ea31cb0b37acfa8f3739d55f1d

commit r12-10661-g960e42bba8d276ea31cb0b37acfa8f3739d55f1d
Author: John David Anglin 
Date:   Tue Aug 6 13:40:26 2024 -0400

hppa: Fix (plus (plus (mult (a) (mem_shadd_constant)) (b)) (c)) optimization

The constant C must be an integral multiple of the shift value in
the above optimization.  Non integral values can occur evaluating
IMAGPART_EXPR when the shadd constant is 8 and we have SFmode.

2024-08-06  John David Anglin  

gcc/ChangeLog:

PR target/113384
* config/pa/pa.cc (hppa_legitimize_address): Add check to
ensure constant is an integral multiple of shift the value.

Diff:
---
 gcc/config/pa/pa.cc | 1 +
 1 file changed, 1 insertion(+)

diff --git a/gcc/config/pa/pa.cc b/gcc/config/pa/pa.cc
index ec81f403a011..bd4dcc4e2b36 100644
--- a/gcc/config/pa/pa.cc
+++ b/gcc/config/pa/pa.cc
@@ -1263,6 +1263,7 @@ hppa_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
   /* If the index adds a large constant, try to scale the
 constant so that it can be loaded with only one insn.  */
   if (GET_CODE (XEXP (idx, 1)) == CONST_INT
+ && INTVAL (XEXP (idx, 1)) % (1 << shift_val) == 0
  && VAL_14_BITS_P (INTVAL (XEXP (idx, 1))
/ INTVAL (XEXP (XEXP (idx, 0), 1)))
  && INTVAL (XEXP (idx, 1)) % INTVAL (XEXP (XEXP (idx, 0), 1)) == 0)

[gcc r15-4088] hppa: Fix indirect_goto constraint

2024-10-05 Thread John David Anglin via Gcc-cvs

https://gcc.gnu.org/g:f6539107b8804bcc3532e748f3f596c5a8b29b44

commit r15-4088-gf6539107b8804bcc3532e748f3f596c5a8b29b44
Author: John David Anglin 
Date:   Sat Oct 5 18:18:31 2024 -0400

hppa: Fix indirect_goto constraint

Noticed testing LRA.

2024-10-05  John David Anglin  

gcc/ChangeLog:

* config/pa/pa.md: Fix indirect_got constraint.

Diff:
---
 gcc/config/pa/pa.md | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/config/pa/pa.md b/gcc/config/pa/pa.md
index f0520bb2c353..fae9e4305547 100644
--- a/gcc/config/pa/pa.md
+++ b/gcc/config/pa/pa.md
@@ -7426,7 +7426,7 @@
 })
 
 (define_insn "indirect_goto"
-  [(unspec [(match_operand 0 "register_operand" "=r")] UNSPEC_GOTO)]
+  [(unspec [(match_operand 0 "register_operand" "r")] UNSPEC_GOTO)]
   "GET_MODE (operands[0]) == word_mode"
   "bv%* %%r0(%0)"
   [(set_attr "type" "branch")

[gcc r12-10744] hppa: Fix indirect_goto constraint

2024-10-05 Thread John David Anglin via Gcc-cvs

https://gcc.gnu.org/g:00100084dbabf8acfd8b12e5b5025bd08ee52f75

commit r12-10744-g00100084dbabf8acfd8b12e5b5025bd08ee52f75
Author: John David Anglin 
Date:   Sat Oct 5 18:18:31 2024 -0400

hppa: Fix indirect_goto constraint

Noticed testing LRA.

2024-10-05  John David Anglin  

gcc/ChangeLog:

* config/pa/pa.md: Fix indirect_got constraint.

Diff:
---
 gcc/config/pa/pa.md | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/config/pa/pa.md b/gcc/config/pa/pa.md
index 432419587225..1d97cb6f4866 100644
--- a/gcc/config/pa/pa.md
+++ b/gcc/config/pa/pa.md
@@ -7316,7 +7316,7 @@
 })
 
 (define_insn "indirect_goto"
-  [(unspec [(match_operand 0 "register_operand" "=r")] UNSPEC_GOTO)]
+  [(unspec [(match_operand 0 "register_operand" "r")] UNSPEC_GOTO)]
   "GET_MODE (operands[0]) == word_mode"
   "bv%* %%r0(%0)"
   [(set_attr "type" "branch")

[gcc r14-10748] hppa: Fix indirect_goto constraint

2024-10-05 Thread John David Anglin via Gcc-cvs

https://gcc.gnu.org/g:27582d4a68f8fb79955f1261a19ef6a8c1f9f71b

commit r14-10748-g27582d4a68f8fb79955f1261a19ef6a8c1f9f71b
Author: John David Anglin 
Date:   Sat Oct 5 18:18:31 2024 -0400

hppa: Fix indirect_goto constraint

Noticed testing LRA.

2024-10-05  John David Anglin  

gcc/ChangeLog:

* config/pa/pa.md: Fix indirect_got constraint.

Diff:
---
 gcc/config/pa/pa.md | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/config/pa/pa.md b/gcc/config/pa/pa.md
index c03332761442..f5e7d67c69fd 100644
--- a/gcc/config/pa/pa.md
+++ b/gcc/config/pa/pa.md
@@ -7426,7 +7426,7 @@
 })
 
 (define_insn "indirect_goto"
-  [(unspec [(match_operand 0 "register_operand" "=r")] UNSPEC_GOTO)]
+  [(unspec [(match_operand 0 "register_operand" "r")] UNSPEC_GOTO)]
   "GET_MODE (operands[0]) == word_mode"
   "bv%* %%r0(%0)"
   [(set_attr "type" "branch")

[gcc r15-4483] hppa: Add LRA support

2024-10-18 Thread John David Anglin via Gcc-cvs

https://gcc.gnu.org/g:44a81aaf73f795e6992cbfb98ec48480e5ca94ec

commit r15-4483-g44a81aaf73f795e6992cbfb98ec48480e5ca94ec
Author: John David Anglin 
Date:   Fri Oct 18 11:28:23 2024 -0400

hppa: Add LRA support

LRA is not enabled as default since there are some new test fails
remaining to resolve.

2024-10-18  John David Anglin  

gcc/ChangeLog:

PR target/113933
* config/pa/pa.cc (pa_use_lra_p): Declare.
(TARGET_LRA_P): Change define to pa_use_lra_p.
(pa_use_lra_p): New function.
(legitimize_pic_address): Also check lra_in_progress.
(pa_emit_move_sequence): Likewise.
(pa_legitimate_constant_p): Likewise.
(pa_legitimate_address_p): Likewise.
(pa_secondary_reload): For floating-point loads and stores,
return NO_REGS for REG and SUBREG operands.  Return
GENERAL_REGS for some shift register spills.
* config/pa/pa.opt: Add mlra option.
* config/pa/predicates.md (integer_store_memory_operand):
Also check lra_in_progress.
(floating_point_store_memory_operand): Likewise.
(reg_before_reload_operand): Likewise.

Diff:
---
 gcc/config/pa/pa.cc | 86 -
 gcc/config/pa/pa.opt|  4 +++
 gcc/config/pa/predicates.md | 14 
 3 files changed, 66 insertions(+), 38 deletions(-)

diff --git a/gcc/config/pa/pa.cc b/gcc/config/pa/pa.cc
index 84aa4f1b1f2a..62f8764b7ca5 100644
--- a/gcc/config/pa/pa.cc
+++ b/gcc/config/pa/pa.cc
@@ -209,6 +209,7 @@ static bool pa_can_change_mode_class (machine_mode, 
machine_mode, reg_class_t);
 static HOST_WIDE_INT pa_starting_frame_offset (void);
 static section* pa_elf_select_rtx_section(machine_mode, rtx, unsigned 
HOST_WIDE_INT) ATTRIBUTE_UNUSED;
 static void pa_atomic_assign_expand_fenv (tree *, tree *, tree *);
+static bool pa_use_lra_p (void);
 
 /* The following extra sections are only used for SOM.  */
 static GTY(()) section *som_readonly_data_section;
@@ -412,7 +413,7 @@ static size_t n_deferred_plabels = 0;
 #define TARGET_LEGITIMATE_ADDRESS_P pa_legitimate_address_p
 
 #undef TARGET_LRA_P
-#define TARGET_LRA_P hook_bool_void_false
+#define TARGET_LRA_P pa_use_lra_p
 
 #undef TARGET_HARD_REGNO_NREGS
 #define TARGET_HARD_REGNO_NREGS pa_hard_regno_nregs
@@ -973,7 +974,7 @@ legitimize_pic_address (rtx orig, machine_mode mode, rtx 
reg)
 
   /* During and after reload, we need to generate a REG_LABEL_OPERAND note
 and update LABEL_NUSES because this is not done automatically.  */
-  if (reload_in_progress || reload_completed)
+  if (lra_in_progress || reload_in_progress || reload_completed)
{
  /* Extract LABEL_REF.  */
  if (GET_CODE (orig) == CONST)
@@ -998,7 +999,7 @@ legitimize_pic_address (rtx orig, machine_mode mode, rtx 
reg)
   /* Before reload, allocate a temporary register for the intermediate
 result.  This allows the sequence to be deleted when the final
 result is unused and the insns are trivially dead.  */
-  tmp_reg = ((reload_in_progress || reload_completed)
+  tmp_reg = ((lra_in_progress || reload_in_progress || reload_completed)
 ? reg : gen_reg_rtx (Pmode));
 
   if (function_label_operand (orig, VOIDmode))
@@ -1959,11 +1960,13 @@ pa_emit_move_sequence (rtx *operands, machine_mode 
mode, rtx scratch_reg)
   copy_to_mode_reg (Pmode, XEXP (operand1, 0)));
 
   if (scratch_reg
-  && reload_in_progress && GET_CODE (operand0) == REG
+  && reload_in_progress
+  && GET_CODE (operand0) == REG
   && REGNO (operand0) >= FIRST_PSEUDO_REGISTER)
 operand0 = reg_equiv_mem (REGNO (operand0));
   else if (scratch_reg
-  && reload_in_progress && GET_CODE (operand0) == SUBREG
+  && reload_in_progress
+  && GET_CODE (operand0) == SUBREG
   && GET_CODE (SUBREG_REG (operand0)) == REG
   && REGNO (SUBREG_REG (operand0)) >= FIRST_PSEUDO_REGISTER)
 {
@@ -1976,11 +1979,13 @@ pa_emit_move_sequence (rtx *operands, machine_mode 
mode, rtx scratch_reg)
 }
 
   if (scratch_reg
-  && reload_in_progress && GET_CODE (operand1) == REG
+  && reload_in_progress
+  && GET_CODE (operand1) == REG
   && REGNO (operand1) >= FIRST_PSEUDO_REGISTER)
 operand1 = reg_equiv_mem (REGNO (operand1));
   else if (scratch_reg
-  && reload_in_progress && GET_CODE (operand1) == SUBREG
+  && reload_in_progress
+  && GET_CODE (operand1) == SUBREG
   && GET_CODE (SUBREG_REG (operand1)) == REG
   && REGNO (SUBREG_REG (operand1)) >= FIRST_PSEUDO_REGISTER)
 {
@@ -1992,12 +1997,16 @@ pa_emit_move_sequence (rtx *operands, machine_mode 
mode, rtx scratch_reg)
   operand1 = alter_subreg (&temp, true);
 }
 
-  if (scratch_reg && reload_in_progress && GET_CODE (operand0) == MEM
+  if (scratc

[gcc r15-4485] hppa: Fix up pa.opt.urls

2024-10-18 Thread John David Anglin via Gcc-cvs

https://gcc.gnu.org/g:aaa855fac0c7003d823b48fe4cc4b9ded9331a2b

commit r15-4485-gaaa855fac0c7003d823b48fe4cc4b9ded9331a2b
Author: John David Anglin 
Date:   Fri Oct 18 12:43:15 2024 -0400

hppa: Fix up pa.opt.urls

2024-10-18  John David Anglin  

gcc/ChangeLog:

* config/pa/pa.opt.urls: Fix for -mlra.

Diff:
---
 gcc/config/pa/pa.opt.urls | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/gcc/config/pa/pa.opt.urls b/gcc/config/pa/pa.opt.urls
index 5b8bcebdd0da..5516332ead13 100644
--- a/gcc/config/pa/pa.opt.urls
+++ b/gcc/config/pa/pa.opt.urls
@@ -36,6 +36,8 @@ UrlSuffix(gcc/HPPA-Options.html#index-mlinker-opt)
 mlong-calls
 UrlSuffix(gcc/HPPA-Options.html#index-mlong-calls-5)
 
+; skipping UrlSuffix for 'mlra' due to finding no URLs
+
 mlong-load-store
 UrlSuffix(gcc/HPPA-Options.html#index-mlong-load-store)

[gcc r15-4093] hppa: Use stack slot SP-40 to copy between integer and floating-point registers

2024-10-06 Thread John David Anglin via Gcc-cvs

https://gcc.gnu.org/g:220402bfc03cf6a6c5bff11da8497b5374dccfe0

commit r15-4093-g220402bfc03cf6a6c5bff11da8497b5374dccfe0
Author: John David Anglin 
Date:   Sun Oct 6 15:21:21 2024 -0400

hppa: Use stack slot SP-40 to copy between integer and floating-point 
registers

2024-10-06  John David Anglin  

gcc/ChangeLog:

* config/pa/pa-64.h (PA_SECONDARY_MEMORY_NEEDED): Define
to false.  Update comment.
* config/pa/pa.md: Modify 64-bit move patterns to support
copying between integer and floating-point registers using
stack slot SP-40.

Diff:
---
 gcc/config/pa/pa-64.h | 12 ++--
 gcc/config/pa/pa.md   | 48 
 2 files changed, 34 insertions(+), 26 deletions(-)

diff --git a/gcc/config/pa/pa-64.h b/gcc/config/pa/pa-64.h
index b676468d2cec..3fae3f851e55 100644
--- a/gcc/config/pa/pa-64.h
+++ b/gcc/config/pa/pa-64.h
@@ -91,9 +91,9 @@ along with GCC; see the file COPYING3.  If not see
the RTL to avoid scheduling related problems.  For example, the
store and load could be separated by a call to a pure or const
function which has no frame and this function might also use SP-16.
-   We have 14-bit immediates on the 64-bit port, so we use secondary
-   memory for the copies.  */
-#define PA_SECONDARY_MEMORY_NEEDED(MODE, CLASS1, CLASS2) \
-  (MAYBE_FP_REG_CLASS_P (CLASS1) != FP_REG_CLASS_P (CLASS2)\
-   || MAYBE_FP_REG_CLASS_P (CLASS2) != FP_REG_CLASS_P (CLASS1))
-
+   
+   On the 64-bit port, I couldn't get SECONDARY_MEMORY_NEEDED to work
+   with LRA, so I modified the move patterns to use SP-40.  The HP
+   compiler also uses this slot in the frame marker for moving data
+   between the general and floating-point registers.  */
+#define PA_SECONDARY_MEMORY_NEEDED(MODE, CLASS1, CLASS2) false
diff --git a/gcc/config/pa/pa.md b/gcc/config/pa/pa.md
index 2f82b431c0cd..bf59b7f601e6 100644
--- a/gcc/config/pa/pa.md
+++ b/gcc/config/pa/pa.md
@@ -,9 +,9 @@
 
 (define_insn ""
   [(set (match_operand:SI 0 "move_dest_operand"
- "=r,r,r,r,r,r,Q,!*q,!r,!*f,*f,T")
+ "=r,r,r,r,r,r,Q,!*q,!r,!*f,*f,T,?r,?*f")
(match_operand:SI 1 "move_src_operand"
- "A,r,J,N,K,RQ,rM,!rM,!*q,!*fM,RT,*f"))]
+ "A,r,J,N,K,RQ,rM,!rM,!*q,!*fM,RT,*f,*f,r"))]
   "(register_operand (operands[0], SImode)
 || reg_or_0_operand (operands[1], SImode))
&& !TARGET_SOFT_FLOAT
@@ -2241,10 +2241,12 @@
{mfctl|mfctl,w} %%sar,%0
fcpy,sgl %f1,%0
fldw%F1 %1,%0
-   fstw%F0 %1,%0"
-  [(set_attr "type" 
"load,move,move,move,shift,load,store,move,move,fpalu,fpload,fpstore")
+   fstw%F0 %1,%0
+   fstw %1,-40(%%sp)\n\tldw -40(%%sp),%0
+   stw %1,-40(%%sp)\n\tfldw -40(%%sp),%0"
+  [(set_attr "type" 
"load,move,move,move,shift,load,store,move,move,fpalu,fpload,fpstore,fpstore_load,store_fpload")
(set_attr "pa_combine_type" "addmove")
-   (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4")])
+   (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4,8,8")])
 
 (define_insn ""
   [(set (match_operand:SI 0 "move_dest_operand"
@@ -4107,9 +4109,9 @@
 
 (define_insn ""
   [(set (match_operand:DF 0 "move_dest_operand"
- "=!*r,*r,*r,*r,*r,Q,f,f,T")
+ "=!*r,*r,*r,*r,*r,Q,f,f,T,?*r,?f")
(match_operand:DF 1 "move_src_operand"
- "!*rG,J,N,K,RQ,*rG,fG,RT,f"))]
+ "!*rG,J,N,K,RQ,*rG,fG,RT,f,f,*r"))]
   "(register_operand (operands[0], DFmode)
 || reg_or_0_operand (operands[1], DFmode))
&& !TARGET_SOFT_FLOAT && TARGET_64BIT"
@@ -4122,10 +4124,12 @@
std%M0 %r1,%0
fcpy,dbl %f1,%0
fldd%F1 %1,%0
-   fstd%F0 %1,%0"
-  [(set_attr "type" "move,move,move,shift,load,store,fpalu,fpload,fpstore")
+   fstd%F0 %1,%0
+   fstd %1,-40(%%sp)\n\tldd -40(%%sp),%0
+   std %1,-40(%%sp)\n\tfldd -40(%%sp),%0"
+  [(set_attr "type" 
"move,move,move,shift,load,store,fpalu,fpload,fpstore,fpstore_load,store_fpload")
(set_attr "pa_combine_type" "addmove")
-   (set_attr "length" "4,4,4,4,4,4,4,4,4")])
+   (set_attr "length" "4,4,4,4,4,4,4,4,4,8,8")])
 
 (define_insn ""
   [(set (match_operand:DF 0 "move_dest_operand"
@@ -4281,9 +4285,9 @@
 
 (define_insn ""
   [(set (match_operand:DI 0 "move_dest_operand"
- "=r,r,r,r,r,r,Q,!*q,!r,!*f,*f,T")
+ "=r,r,r,r,r,r,Q,!*q,!r,!*f,*f,T,?r,?*f")
(match_operand:DI 1 "move_src_operand"
- "A,r,J,N,K,RQ,rM,!rM,!*q,!*fM,RT,*f"))]
+ "A,r,J,N,K,RQ,rM,!rM,!*q,!*fM,RT,*f,*f,r"))]
   "(register_operand (operands[0], DImode)
 || reg_or_0_operand (operands[1], DImode))
&& !TARGET_SOFT_FLOAT && TARGET_64BIT"
@@ -4299,10 +4303,12 @@
{mfctl|mfctl,w} %%sar,%0
fcpy,dbl %f1,%0
fldd%F1 %1,%0
-   fstd%F0 %1,%0"
-  [(set_attr "type" 
"load,move,move,move,shift,load,store,move,move,fpalu

[gcc r15-4094] testsuite: Require lto in three tests

2024-10-06 Thread John David Anglin via Gcc-cvs

https://gcc.gnu.org/g:4782662796ac8fa3174416cf04982290ee6bbc20

commit r15-4094-g4782662796ac8fa3174416cf04982290ee6bbc20
Author: John David Anglin 
Date:   Sun Oct 6 16:09:28 2024 -0400

testsuite: Require lto in three tests

2024-10-06  John David Anglin  

gcc/testsuite/ChangeLog:

* g++.dg/cpp0x/noexcept87.C: Require lto.
* g++.dg/ext/pragma-unroll-lambda-lto.C: Likewise.
* gcc.dg/enum-alias-3.c: Likewise.

Diff:
---
 gcc/testsuite/g++.dg/cpp0x/noexcept87.C | 1 +
 gcc/testsuite/g++.dg/ext/pragma-unroll-lambda-lto.C | 1 +
 gcc/testsuite/gcc.dg/enum-alias-3.c | 1 +
 3 files changed, 3 insertions(+)

diff --git a/gcc/testsuite/g++.dg/cpp0x/noexcept87.C 
b/gcc/testsuite/g++.dg/cpp0x/noexcept87.C
index 339569d15ae5..bb7bb6055324 100644
--- a/gcc/testsuite/g++.dg/cpp0x/noexcept87.C
+++ b/gcc/testsuite/g++.dg/cpp0x/noexcept87.C
@@ -1,5 +1,6 @@
 // PR c++/115223
 // { dg-do compile { target c++11 } }
+// { dg-require-effective-target lto }
 // { dg-additional-options -flto }
 
 template
diff --git a/gcc/testsuite/g++.dg/ext/pragma-unroll-lambda-lto.C 
b/gcc/testsuite/g++.dg/ext/pragma-unroll-lambda-lto.C
index 64cdf90f34d3..ddf11730e338 100644
--- a/gcc/testsuite/g++.dg/ext/pragma-unroll-lambda-lto.C
+++ b/gcc/testsuite/g++.dg/ext/pragma-unroll-lambda-lto.C
@@ -1,4 +1,5 @@
 // { dg-do link { target c++11 } }
+// { dg-require-effective-target lto }
 // { dg-options "-O2 -flto -fdump-rtl-loop2_unroll" }
 // { dg-skip-if "requires hosted libstdc++ for cstdlib rand" { ! hostedlib } }
 
diff --git a/gcc/testsuite/gcc.dg/enum-alias-3.c 
b/gcc/testsuite/gcc.dg/enum-alias-3.c
index 36a4f02a4552..322c8d82952c 100644
--- a/gcc/testsuite/gcc.dg/enum-alias-3.c
+++ b/gcc/testsuite/gcc.dg/enum-alias-3.c
@@ -1,4 +1,5 @@
 /* { dg-do run } */
+/* { dg-require-effective-target lto } */
 /* { dg-options "-O2 -flto" } */
 
 typedef int *A;

[gcc r13-9087] hppa: Fix indirect_goto constraint

2024-10-05 Thread John David Anglin via Gcc-cvs

https://gcc.gnu.org/g:829803662b505ef85d2db643a9ec44048a447558

commit r13-9087-g829803662b505ef85d2db643a9ec44048a447558
Author: John David Anglin 
Date:   Sat Oct 5 18:18:31 2024 -0400

hppa: Fix indirect_goto constraint

Noticed testing LRA.

2024-10-05  John David Anglin  

gcc/ChangeLog:

* config/pa/pa.md: Fix indirect_got constraint.

Diff:
---
 gcc/config/pa/pa.md | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/config/pa/pa.md b/gcc/config/pa/pa.md
index c01719467856..970669ebee3b 100644
--- a/gcc/config/pa/pa.md
+++ b/gcc/config/pa/pa.md
@@ -7416,7 +7416,7 @@
 })
 
 (define_insn "indirect_goto"
-  [(unspec [(match_operand 0 "register_operand" "=r")] UNSPEC_GOTO)]
+  [(unspec [(match_operand 0 "register_operand" "r")] UNSPEC_GOTO)]
   "GET_MODE (operands[0]) == word_mode"
   "bv%* %%r0(%0)"
   [(set_attr "type" "branch")

[gcc r15-4089] hppa: Don't clobber frame_pointer_rtx in expanders

2024-10-05 Thread John David Anglin via Gcc-cvs

https://gcc.gnu.org/g:29f47b0929e00ef9b880e9157f156c78ff924f5b

commit r15-4089-g29f47b0929e00ef9b880e9157f156c78ff924f5b
Author: John David Anglin 
Date:   Sat Oct 5 18:39:41 2024 -0400

hppa: Don't clobber frame_pointer_rtx in expanders

Noticed testing LRA.  Clobbers cause internal compiler errors.

2024-10-05  John David Anglin  

gcc/ChangeLog:

* config/pa/pa.md (nonlocal_goto): Don't clobber
frame_pointer_rtx.
(builtin_longjmp): Likewise.

Diff:
---
 gcc/config/pa/pa.md | 2 --
 1 file changed, 2 deletions(-)

diff --git a/gcc/config/pa/pa.md b/gcc/config/pa/pa.md
index fae9e4305547..2f82b431c0cd 100644
--- a/gcc/config/pa/pa.md
+++ b/gcc/config/pa/pa.md
@@ -7411,7 +7411,6 @@
   /* Ensure the frame pointer move is not optimized.  */
   emit_insn (gen_blockage ());
   emit_clobber (hard_frame_pointer_rtx);
-  emit_clobber (frame_pointer_rtx);
   emit_move_insn (hard_frame_pointer_rtx, fp);
 
   emit_use (hard_frame_pointer_rtx);
@@ -9202,7 +9201,6 @@ add,l %2,%3,%3\;bv,n %%r0(%3)"
   /* Ensure the frame pointer move is not optimized.  */
   emit_insn (gen_blockage ());
   emit_clobber (hard_frame_pointer_rtx);
-  emit_clobber (frame_pointer_rtx);
   emit_move_insn (hard_frame_pointer_rtx, fp);
 
   emit_use (hard_frame_pointer_rtx);

[gcc r15-5049] hppa: Fix handling of secondary reloads involving a SUBREG

2024-11-08 Thread John David Anglin via Gcc-cvs

https://gcc.gnu.org/g:1ea45291af0bc8f7b6dff67a0f23be662b2f9908

commit r15-5049-g1ea45291af0bc8f7b6dff67a0f23be662b2f9908
Author: John David Anglin 
Date:   Fri Nov 8 16:34:41 2024 -0500

hppa: Fix handling of secondary reloads involving a SUBREG

This is fairly subtle.

When handling spills for SUBREG arguments in pa_emit_move_sequence,
alter_subreg may be called.  It in turn calls adjust_address_1 and
change_address_1.  change_address_1 calls pa_legitimate_address_p
to validate the new spill address.  change_address_1 generates an
internal compiler error if the address is not valid.  We need to
allow 14-bit displacements for all modes when reload_in_progress
is true and strict is false to prevent the internal compiler error.

SUBREGs are only used with the general registers, so the spill
should result in an integer access.  14-bit displacements are okay
for integer loads and stores but not for floating-point loads and
stores.

Potentially, the change could break the handling of spills for the
floating point-registers but I believe these are handled separately
in pa_emit_move_sequence.

This change fixes the build of symmetrica-3.0.1+ds.

2024-11-08  John David Anglin  

gcc/ChangeLog:

PR target/117443
* config/pa/pa.cc (pa_legitimate_address_p): Allow any
14-bit displacement when reload is in progress and strict
is false.

Diff:
---
 gcc/config/pa/pa.cc | 1 +
 1 file changed, 1 insertion(+)

diff --git a/gcc/config/pa/pa.cc b/gcc/config/pa/pa.cc
index 94ee7dbfa8ee..941ef3a71287 100644
--- a/gcc/config/pa/pa.cc
+++ b/gcc/config/pa/pa.cc
@@ -11009,6 +11009,7 @@ pa_legitimate_address_p (machine_mode mode, rtx x, bool 
strict, code_helper)
  /* Long 14-bit displacements always okay for these cases.  */
  if (INT14_OK_STRICT
  || reload_completed
+ || (reload_in_progress && !strict)
  || mode == QImode
  || mode == HImode)
return true;

[gcc r14-10910] hppa: Fix handling of secondary reloads involving a SUBREG

2024-11-08 Thread John David Anglin via Gcc-cvs

https://gcc.gnu.org/g:4b30972e5171093c472ef344297994dd00bf5e97

commit r14-10910-g4b30972e5171093c472ef344297994dd00bf5e97
Author: John David Anglin 
Date:   Fri Nov 8 16:34:41 2024 -0500

hppa: Fix handling of secondary reloads involving a SUBREG

This is fairly subtle.

When handling spills for SUBREG arguments in pa_emit_move_sequence,
alter_subreg may be called.  It in turn calls adjust_address_1 and
change_address_1.  change_address_1 calls pa_legitimate_address_p
to validate the new spill address.  change_address_1 generates an
internal compiler error if the address is not valid.  We need to
allow 14-bit displacements for all modes when reload_in_progress
is true and strict is false to prevent the internal compiler error.

SUBREGs are only used with the general registers, so the spill
should result in an integer access.  14-bit displacements are okay
for integer loads and stores but not for floating-point loads and
stores.

Potentially, the change could break the handling of spills for the
floating point-registers but I believe these are handled separately
in pa_emit_move_sequence.

This change fixes the build of symmetrica-3.0.1+ds.

2024-11-08  John David Anglin  

gcc/ChangeLog:

PR target/117443
* config/pa/pa.cc (pa_legitimate_address_p): Allow any
14-bit displacement when reload is in progress and strict
is false.

Diff:
---
 gcc/config/pa/pa.cc | 1 +
 1 file changed, 1 insertion(+)

diff --git a/gcc/config/pa/pa.cc b/gcc/config/pa/pa.cc
index b24434628fa5..d72946f6c198 100644
--- a/gcc/config/pa/pa.cc
+++ b/gcc/config/pa/pa.cc
@@ -10983,6 +10983,7 @@ pa_legitimate_address_p (machine_mode mode, rtx x, bool 
strict, code_helper)
  /* Long 14-bit displacements always okay for these cases.  */
  if (INT14_OK_STRICT
  || reload_completed
+ || (reload_in_progress && !strict)
  || mode == QImode
  || mode == HImode)
return true;

[gcc r15-5050] hppa: Don't allow large modes in hard registers

2024-11-08 Thread John David Anglin via Gcc-cvs

https://gcc.gnu.org/g:3a1da8ffb71af1005c5a035d0eb5f956056adf32

commit r15-5050-g3a1da8ffb71af1005c5a035d0eb5f956056adf32
Author: John David Anglin 
Date:   Fri Nov 8 16:49:34 2024 -0500

hppa: Don't allow large modes in hard registers

LRA has problems handling spills for OI and TI modes.  There are
issues with SUBREG support as well.

This change fixes gcc.c-torture/compile/pr92618.c with LRA.

2024-11-08  John David Anglin  

gcc/ChangeLog:

PR target/117238
* config/pa/pa32-regs.h (PA_HARD_REGNO_MODE_OK): Don't allow
mode size 32.  Limit mode size 16 in general registers to
complex modes.

Diff:
---
 gcc/config/pa/pa32-regs.h | 15 ++-
 1 file changed, 6 insertions(+), 9 deletions(-)

diff --git a/gcc/config/pa/pa32-regs.h b/gcc/config/pa/pa32-regs.h
index 3467e03afed7..c9a27ef16587 100644
--- a/gcc/config/pa/pa32-regs.h
+++ b/gcc/config/pa/pa32-regs.h
@@ -187,10 +187,9 @@ see the files COPYING3 and COPYING.RUNTIME respectively.  
If not, see
that includes the incoming arguments and the return value.  We specify a
set with no overlaps so that we don't have to specify that the destination
register is an early clobber in patterns using this mode.  Except for the
-   return value, the starting registers are odd.  For 128 and 256 bit modes,
-   we similarly specify non-overlapping sets of cpu registers.  However,
-   there aren't any patterns defined for modes larger than 64 bits at the
-   moment.
+   return value, the starting registers are odd.  Except for complex modes,
+   we don't allow modes larger than 64 bits in the general registers as there
+   are issues with copies, spills and SUBREG support.
 
We limit the modes allowed in the floating point registers to the
set of modes used in the machine definition.  In addition, we allow
@@ -217,15 +216,13 @@ see the files COPYING3 and COPYING.RUNTIME respectively.  
If not, see
  ? (VALID_FP_MODE_P (MODE) \
&& (GET_MODE_SIZE (MODE) <= 4   \
|| (GET_MODE_SIZE (MODE) == 8 && ((REGNO) & 1) == 0)\
-   || (GET_MODE_SIZE (MODE) == 16 && ((REGNO) & 3) == 0)   \
-   || (GET_MODE_SIZE (MODE) == 32 && ((REGNO) & 7) == 0))) \
+   || (GET_MODE_SIZE (MODE) == 16 && ((REGNO) & 3) == 0))) \
: (GET_MODE_SIZE (MODE) <= UNITS_PER_WORD   \
   || (GET_MODE_SIZE (MODE) == 2 * UNITS_PER_WORD   \
  && REGNO) & 1) == 1 && (REGNO) <= 25) || (REGNO) == 28))  \
   || (GET_MODE_SIZE (MODE) == 4 * UNITS_PER_WORD   \
- && ((REGNO) & 3) == 3 && (REGNO) <= 23)   \
-  || (GET_MODE_SIZE (MODE) == 8 * UNITS_PER_WORD   \
- && ((REGNO) & 7) == 3 && (REGNO) <= 19)))
+ && COMPLEX_MODE_P (MODE)  \
+ && ((REGNO) & 3) == 3 && (REGNO) <= 23)))
 
 /* How to renumber registers for gdb.

[gcc r15-5051] hppa: Don't use '%' operator in base14_operand

2024-11-08 Thread John David Anglin via Gcc-cvs

https://gcc.gnu.org/g:c9db5322ae39a49db0728a0a4cb5003efb6ae668

commit r15-5051-gc9db5322ae39a49db0728a0a4cb5003efb6ae668
Author: John David Anglin 
Date:   Fri Nov 8 16:54:48 2024 -0500

hppa: Don't use '%' operator in base14_operand

Division is slow on hppa and mode sizes are powers of 2.  So, we
can use '&' operator to check displacement alignment.

2024-11-08  John David Anglin  

gcc/ChangeLog:

* config/pa/predicates.md (base14_operand): Use '&' operator
instead of '%' to check displacement alignment.

Diff:
---
 gcc/config/pa/predicates.md | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/config/pa/predicates.md b/gcc/config/pa/predicates.md
index 0defd2282fbf..a27b2b1c78db 100644
--- a/gcc/config/pa/predicates.md
+++ b/gcc/config/pa/predicates.md
@@ -285,7 +285,7 @@
   return false;
 
 default:
-  return (INTVAL (op) % GET_MODE_SIZE (mode)) == 0;
+  return (INTVAL (op) & (GET_MODE_SIZE (mode) - 1)) == 0;
 }
 
   return false;

[gcc r14-10911] hppa: Don't use '%' operator in base14_operand

2024-11-08 Thread John David Anglin via Gcc-cvs

https://gcc.gnu.org/g:3bc7af0e2b06131465b8de560692c7011b45cf22

commit r14-10911-g3bc7af0e2b06131465b8de560692c7011b45cf22
Author: John David Anglin 
Date:   Fri Nov 8 16:54:48 2024 -0500

hppa: Don't use '%' operator in base14_operand

Division is slow on hppa and mode sizes are powers of 2.  So, we
can use '&' operator to check displacement alignment.

2024-11-08  John David Anglin  

gcc/ChangeLog:

* config/pa/predicates.md (base14_operand): Use '&' operator
instead of '%' to check displacement alignment.

Diff:
---
 gcc/config/pa/predicates.md | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/config/pa/predicates.md b/gcc/config/pa/predicates.md
index 50dffa1138ca..74f75770676e 100644
--- a/gcc/config/pa/predicates.md
+++ b/gcc/config/pa/predicates.md
@@ -285,7 +285,7 @@
   return false;
 
 default:
-  return (INTVAL (op) % GET_MODE_SIZE (mode)) == 0;
+  return (INTVAL (op) & (GET_MODE_SIZE (mode) - 1)) == 0;
 }
 
   return false;

[gcc r15-5052] hppa: Don't allow mode size 32 in hard registers

2024-11-08 Thread John David Anglin via Gcc-cvs

https://gcc.gnu.org/g:7175fece7df50326703e4ca8b49d7cc93a5e8dfe

commit r15-5052-g7175fece7df50326703e4ca8b49d7cc93a5e8dfe
Author: John David Anglin 
Date:   Fri Nov 8 16:58:49 2024 -0500

hppa: Don't allow mode size 32 in hard registers

LRA has problems handling spills for OI mode.  There are issues with
SUBREG support as well.

2024-11-08  John David Anglin  

gcc/ChangeLog:

PR target/117238
* config/pa/pa64-regs.h (PA_HARD_REGNO_MODE_OK): Don't allow
mode size 32.

Diff:
---
 gcc/config/pa/pa64-regs.h | 7 ++-
 1 file changed, 2 insertions(+), 5 deletions(-)

diff --git a/gcc/config/pa/pa64-regs.h b/gcc/config/pa/pa64-regs.h
index 3b9273c28677..90762e119dcf 100644
--- a/gcc/config/pa/pa64-regs.h
+++ b/gcc/config/pa/pa64-regs.h
@@ -157,13 +157,10 @@ along with GCC; see the file COPYING3.  If not see
: FP_REGNO_P (REGNO)
\
  ? (VALID_FP_MODE_P (MODE) \
&& (GET_MODE_SIZE (MODE) <= 8   \
-   || (GET_MODE_SIZE (MODE) == 16 && ((REGNO) & 1) == 0)   \
-   || (GET_MODE_SIZE (MODE) == 32 && ((REGNO) & 3) == 0))) \
+   || (GET_MODE_SIZE (MODE) == 16 && ((REGNO) & 1) == 0))) \
: (GET_MODE_SIZE (MODE) <= UNITS_PER_WORD   \
   || (GET_MODE_SIZE (MODE) == 2 * UNITS_PER_WORD   \
- && REGNO) & 1) == 1 && (REGNO) <= 25) || (REGNO) == 28))  \
-  || (GET_MODE_SIZE (MODE) == 4 * UNITS_PER_WORD   \
- && ((REGNO) & 3) == 3 && (REGNO) <= 23)))
+ && REGNO) & 1) == 1 && (REGNO) <= 25) || (REGNO) == 28
 
 /* How to renumber registers for gdb.

[gcc r14-10924] hppa: Fix decrement_and_branch_until_zero constraint

2024-11-12 Thread John David Anglin via Gcc-cvs

https://gcc.gnu.org/g:2a41d31fa8c2d025854e9459c135c45633936fc3

commit r14-10924-g2a41d31fa8c2d025854e9459c135c45633936fc3
Author: John David Anglin 
Date:   Tue Nov 12 14:26:08 2024 -0500

hppa: Fix decrement_and_branch_until_zero constraint

The third alternative for argument 4 needs to be an early clobber
constraint.  Noticed testing LRA.

2024-11-12  John David Anglin  

gcc/ChangeLog:

* config/pa/pa.md (decrement_and_branch_until_zero): Fix
constraint.

Diff:
---
 gcc/config/pa/pa.md | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/config/pa/pa.md b/gcc/config/pa/pa.md
index f5e7d67c69fd..a72edc76f062 100644
--- a/gcc/config/pa/pa.md
+++ b/gcc/config/pa/pa.md
@@ -9561,7 +9561,7 @@ add,l %2,%3,%3\;bv,n %%r0(%3)"
  (pc)))
(set (match_dup 0)
(plus:SI (match_dup 0) (match_dup 1)))
-   (clobber (match_scratch:SI 4 "=X,r,r"))]
+   (clobber (match_scratch:SI 4 "=X,r,&r"))]
   ""
   "* return pa_output_dbra (operands, insn, which_alternative); "
 ;; Do not expect to understand this the first time through.

[gcc r13-9181] hppa: Fix decrement_and_branch_until_zero constraint

2024-11-12 Thread John David Anglin via Gcc-cvs

https://gcc.gnu.org/g:581b7122f0843507b82e639b283ef14b904cdd54

commit r13-9181-g581b7122f0843507b82e639b283ef14b904cdd54
Author: John David Anglin 
Date:   Tue Nov 12 14:26:08 2024 -0500

hppa: Fix decrement_and_branch_until_zero constraint

The third alternative for argument 4 needs to be an early clobber
constraint.  Noticed testing LRA.

2024-11-12  John David Anglin  

gcc/ChangeLog:

* config/pa/pa.md (decrement_and_branch_until_zero): Fix
constraint.

Diff:
---
 gcc/config/pa/pa.md | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/config/pa/pa.md b/gcc/config/pa/pa.md
index 970669ebee3b..37803ffa0fce 100644
--- a/gcc/config/pa/pa.md
+++ b/gcc/config/pa/pa.md
@@ -9551,7 +9551,7 @@ add,l %2,%3,%3\;bv,n %%r0(%3)"
  (pc)))
(set (match_dup 0)
(plus:SI (match_dup 0) (match_dup 1)))
-   (clobber (match_scratch:SI 4 "=X,r,r"))]
+   (clobber (match_scratch:SI 4 "=X,r,&r"))]
   ""
   "* return pa_output_dbra (operands, insn, which_alternative); "
 ;; Do not expect to understand this the first time through.

[gcc r12-10811] hppa: Fix decrement_and_branch_until_zero constraint

2024-11-12 Thread John David Anglin via Gcc-cvs

https://gcc.gnu.org/g:571a5103a1e195dbfac3447065ccfb6c4e69aa2f

commit r12-10811-g571a5103a1e195dbfac3447065ccfb6c4e69aa2f
Author: John David Anglin 
Date:   Tue Nov 12 14:26:08 2024 -0500

hppa: Fix decrement_and_branch_until_zero constraint

The third alternative for argument 4 needs to be an early clobber
constraint.  Noticed testing LRA.

2024-11-12  John David Anglin  

gcc/ChangeLog:

* config/pa/pa.md (decrement_and_branch_until_zero): Fix
constraint.

Diff:
---
 gcc/config/pa/pa.md | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/config/pa/pa.md b/gcc/config/pa/pa.md
index 1d97cb6f4866..63335c2480c8 100644
--- a/gcc/config/pa/pa.md
+++ b/gcc/config/pa/pa.md
@@ -9451,7 +9451,7 @@ add,l %2,%3,%3\;bv,n %%r0(%3)"
  (pc)))
(set (match_dup 0)
(plus:SI (match_dup 0) (match_dup 1)))
-   (clobber (match_scratch:SI 4 "=X,r,r"))]
+   (clobber (match_scratch:SI 4 "=X,r,&r"))]
   ""
   "* return pa_output_dbra (operands, insn, which_alternative); "
 ;; Do not expect to understand this the first time through.

[gcc r15-5178] hppa: Fix decrement_and_branch_until_zero constraint

2024-11-12 Thread John David Anglin via Gcc-cvs

https://gcc.gnu.org/g:b59c4b1803fca7cd66c27e8a82f89f7c10264f34

commit r15-5178-gb59c4b1803fca7cd66c27e8a82f89f7c10264f34
Author: John David Anglin 
Date:   Tue Nov 12 14:26:08 2024 -0500

hppa: Fix decrement_and_branch_until_zero constraint

The third alternative for argument 4 needs to be an early clobber
constraint.  Noticed testing LRA.

2024-11-12  John David Anglin  

gcc/ChangeLog:

* config/pa/pa.md (decrement_and_branch_until_zero): Fix
constraint.

Diff:
---
 gcc/config/pa/pa.md | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/config/pa/pa.md b/gcc/config/pa/pa.md
index bf59b7f601e6..360198e9d087 100644
--- a/gcc/config/pa/pa.md
+++ b/gcc/config/pa/pa.md
@@ -9567,7 +9567,7 @@ add,l %2,%3,%3\;bv,n %%r0(%3)"
  (pc)))
(set (match_dup 0)
(plus:SI (match_dup 0) (match_dup 1)))
-   (clobber (match_scratch:SI 4 "=X,r,r"))]
+   (clobber (match_scratch:SI 4 "=X,r,&r"))]
   ""
   "* return pa_output_dbra (operands, insn, which_alternative); "
 ;; Do not expect to understand this the first time through.

[gcc r12-10814] hppa: Remove inner `fix:SF/DF` from fixed-point patterns

2024-11-13 Thread John David Anglin via Gcc-cvs

https://gcc.gnu.org/g:424bd4c3d14473c18850e7366804e761fc0b03de

commit r12-10814-g424bd4c3d14473c18850e7366804e761fc0b03de
Author: John David Anglin 
Date:   Wed Nov 13 09:40:42 2024 -0500

hppa: Remove inner `fix:SF/DF` from fixed-point patterns

2024-11-13  John David Anglin  

gcc/ChangeLog:

PR target/117525
* config/pa/pa.md (fix_truncsfsi2): Remove inner `fix:SF`.
(fix_truncdfsi2, fix_truncsfdi2, fix_truncdfdi2,
fixuns_truncsfsi2, fixuns_truncdfsi2, fixuns_truncsfdi2,
fixuns_truncdfdi2): Likewise.

Diff:
---
 gcc/config/pa/pa.md | 16 
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/gcc/config/pa/pa.md b/gcc/config/pa/pa.md
index 63335c2480c8..2b1ee3d32a3b 100644
--- a/gcc/config/pa/pa.md
+++ b/gcc/config/pa/pa.md
@@ -4908,7 +4908,7 @@
 
 (define_insn "fix_truncsfsi2"
   [(set (match_operand:SI 0 "register_operand" "=f")
-   (fix:SI (fix:SF (match_operand:SF 1 "register_operand" "f"]
+   (fix:SI (match_operand:SF 1 "register_operand" "f")))]
   "! TARGET_SOFT_FLOAT"
   "{fcnvfxt,sgl,sgl|fcnv,t,sgl,w} %1,%0"
   [(set_attr "type" "fpalu")
@@ -4916,7 +4916,7 @@
 
 (define_insn "fix_truncdfsi2"
   [(set (match_operand:SI 0 "register_operand" "=f")
-   (fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f"]
+   (fix:SI (match_operand:DF 1 "register_operand" "f")))]
   "! TARGET_SOFT_FLOAT"
   "{fcnvfxt,dbl,sgl|fcnv,t,dbl,w} %1,%0"
   [(set_attr "type" "fpalu")
@@ -4924,7 +4924,7 @@
 
 (define_insn "fix_truncsfdi2"
   [(set (match_operand:DI 0 "register_operand" "=f")
-   (fix:DI (fix:SF (match_operand:SF 1 "register_operand" "f"]
+   (fix:DI (match_operand:SF 1 "register_operand" "f")))]
   "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
   "{fcnvfxt,sgl,dbl|fcnv,t,sgl,dw} %1,%0"
   [(set_attr "type" "fpalu")
@@ -4932,7 +4932,7 @@
 
 (define_insn "fix_truncdfdi2"
   [(set (match_operand:DI 0 "register_operand" "=f")
-   (fix:DI (fix:DF (match_operand:DF 1 "register_operand" "f"]
+   (fix:DI (match_operand:DF 1 "register_operand" "f")))]
   "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
   "{fcnvfxt,dbl,dbl|fcnv,t,dbl,dw} %1,%0"
   [(set_attr "type" "fpalu")
@@ -4972,7 +4972,7 @@
 
 (define_insn "fixuns_truncsfsi2"
   [(set (match_operand:SI 0 "register_operand" "=f")
-   (unsigned_fix:SI (fix:SF (match_operand:SF 1 "register_operand" "f"]
+   (unsigned_fix:SI (match_operand:SF 1 "register_operand" "f")))]
   "! TARGET_SOFT_FLOAT && TARGET_PA_20"
   "fcnv,t,sgl,uw %1,%0"
   [(set_attr "type" "fpalu")
@@ -4980,7 +4980,7 @@
 
 (define_insn "fixuns_truncdfsi2"
   [(set (match_operand:SI 0 "register_operand" "=f")
-   (unsigned_fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f"]
+   (unsigned_fix:SI (match_operand:DF 1 "register_operand" "f")))]
   "! TARGET_SOFT_FLOAT && TARGET_PA_20"
   "fcnv,t,dbl,uw %1,%0"
   [(set_attr "type" "fpalu")
@@ -4988,7 +4988,7 @@
 
 (define_insn "fixuns_truncsfdi2"
   [(set (match_operand:DI 0 "register_operand" "=f")
-   (unsigned_fix:DI (fix:SF (match_operand:SF 1 "register_operand" "f"]
+   (unsigned_fix:DI (match_operand:SF 1 "register_operand" "f")))]
   "! TARGET_SOFT_FLOAT && TARGET_PA_20"
   "fcnv,t,sgl,udw %1,%0"
   [(set_attr "type" "fpalu")
@@ -4996,7 +4996,7 @@
 
 (define_insn "fixuns_truncdfdi2"
   [(set (match_operand:DI 0 "register_operand" "=f")
-   (unsigned_fix:DI (fix:DF (match_operand:DF 1 "register_operand" "f"]
+   (unsigned_fix:DI (match_operand:DF 1 "register_operand" "f")))]
   "! TARGET_SOFT_FLOAT && TARGET_PA_20"
   "fcnv,t,dbl,udw %1,%0"
   [(set_attr "type" "fpalu")

[gcc r13-9184] hppa: Remove inner `fix:SF/DF` from fixed-point patterns

2024-11-13 Thread John David Anglin via Gcc-cvs

https://gcc.gnu.org/g:4ac301e399ceff496646fc8da06ad423521b7a29

commit r13-9184-g4ac301e399ceff496646fc8da06ad423521b7a29
Author: John David Anglin 
Date:   Wed Nov 13 09:40:42 2024 -0500

hppa: Remove inner `fix:SF/DF` from fixed-point patterns

2024-11-13  John David Anglin  

gcc/ChangeLog:

PR target/117525
* config/pa/pa.md (fix_truncsfsi2): Remove inner `fix:SF`.
(fix_truncdfsi2, fix_truncsfdi2, fix_truncdfdi2,
fixuns_truncsfsi2, fixuns_truncdfsi2, fixuns_truncsfdi2,
fixuns_truncdfdi2): Likewise.

Diff:
---
 gcc/config/pa/pa.md | 16 
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/gcc/config/pa/pa.md b/gcc/config/pa/pa.md
index 37803ffa0fce..63c9472bf1ae 100644
--- a/gcc/config/pa/pa.md
+++ b/gcc/config/pa/pa.md
@@ -5008,7 +5008,7 @@
 
 (define_insn "fix_truncsfsi2"
   [(set (match_operand:SI 0 "register_operand" "=f")
-   (fix:SI (fix:SF (match_operand:SF 1 "register_operand" "f"]
+   (fix:SI (match_operand:SF 1 "register_operand" "f")))]
   "! TARGET_SOFT_FLOAT"
   "{fcnvfxt,sgl,sgl|fcnv,t,sgl,w} %1,%0"
   [(set_attr "type" "fpalu")
@@ -5016,7 +5016,7 @@
 
 (define_insn "fix_truncdfsi2"
   [(set (match_operand:SI 0 "register_operand" "=f")
-   (fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f"]
+   (fix:SI (match_operand:DF 1 "register_operand" "f")))]
   "! TARGET_SOFT_FLOAT"
   "{fcnvfxt,dbl,sgl|fcnv,t,dbl,w} %1,%0"
   [(set_attr "type" "fpalu")
@@ -5024,7 +5024,7 @@
 
 (define_insn "fix_truncsfdi2"
   [(set (match_operand:DI 0 "register_operand" "=f")
-   (fix:DI (fix:SF (match_operand:SF 1 "register_operand" "f"]
+   (fix:DI (match_operand:SF 1 "register_operand" "f")))]
   "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
   "{fcnvfxt,sgl,dbl|fcnv,t,sgl,dw} %1,%0"
   [(set_attr "type" "fpalu")
@@ -5032,7 +5032,7 @@
 
 (define_insn "fix_truncdfdi2"
   [(set (match_operand:DI 0 "register_operand" "=f")
-   (fix:DI (fix:DF (match_operand:DF 1 "register_operand" "f"]
+   (fix:DI (match_operand:DF 1 "register_operand" "f")))]
   "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
   "{fcnvfxt,dbl,dbl|fcnv,t,dbl,dw} %1,%0"
   [(set_attr "type" "fpalu")
@@ -5072,7 +5072,7 @@
 
 (define_insn "fixuns_truncsfsi2"
   [(set (match_operand:SI 0 "register_operand" "=f")
-   (unsigned_fix:SI (fix:SF (match_operand:SF 1 "register_operand" "f"]
+   (unsigned_fix:SI (match_operand:SF 1 "register_operand" "f")))]
   "! TARGET_SOFT_FLOAT && TARGET_PA_20"
   "fcnv,t,sgl,uw %1,%0"
   [(set_attr "type" "fpalu")
@@ -5080,7 +5080,7 @@
 
 (define_insn "fixuns_truncdfsi2"
   [(set (match_operand:SI 0 "register_operand" "=f")
-   (unsigned_fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f"]
+   (unsigned_fix:SI (match_operand:DF 1 "register_operand" "f")))]
   "! TARGET_SOFT_FLOAT && TARGET_PA_20"
   "fcnv,t,dbl,uw %1,%0"
   [(set_attr "type" "fpalu")
@@ -5088,7 +5088,7 @@
 
 (define_insn "fixuns_truncsfdi2"
   [(set (match_operand:DI 0 "register_operand" "=f")
-   (unsigned_fix:DI (fix:SF (match_operand:SF 1 "register_operand" "f"]
+   (unsigned_fix:DI (match_operand:SF 1 "register_operand" "f")))]
   "! TARGET_SOFT_FLOAT && TARGET_PA_20"
   "fcnv,t,sgl,udw %1,%0"
   [(set_attr "type" "fpalu")
@@ -5096,7 +5096,7 @@
 
 (define_insn "fixuns_truncdfdi2"
   [(set (match_operand:DI 0 "register_operand" "=f")
-   (unsigned_fix:DI (fix:DF (match_operand:DF 1 "register_operand" "f"]
+   (unsigned_fix:DI (match_operand:DF 1 "register_operand" "f")))]
   "! TARGET_SOFT_FLOAT && TARGET_PA_20"
   "fcnv,t,dbl,udw %1,%0"
   [(set_attr "type" "fpalu")

[gcc r15-5203] hppa: Remove inner `fix:SF/DF` from fixed-point patterns

2024-11-13 Thread John David Anglin via Gcc-cvs

https://gcc.gnu.org/g:0342d024ff9af258df3bc8a23c9e999bea6be3e0

commit r15-5203-g0342d024ff9af258df3bc8a23c9e999bea6be3e0
Author: John David Anglin 
Date:   Wed Nov 13 09:40:42 2024 -0500

hppa: Remove inner `fix:SF/DF` from fixed-point patterns

2024-11-13  John David Anglin  

gcc/ChangeLog:

PR target/117525
* config/pa/pa.md (fix_truncsfsi2): Remove inner `fix:SF`.
(fix_truncdfsi2, fix_truncsfdi2, fix_truncdfdi2,
fixuns_truncsfsi2, fixuns_truncdfsi2, fixuns_truncsfdi2,
fixuns_truncdfdi2): Likewise.

Diff:
---
 gcc/config/pa/pa.md | 16 
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/gcc/config/pa/pa.md b/gcc/config/pa/pa.md
index 360198e9d087..f3c6262230d8 100644
--- a/gcc/config/pa/pa.md
+++ b/gcc/config/pa/pa.md
@@ -5026,7 +5026,7 @@
 
 (define_insn "fix_truncsfsi2"
   [(set (match_operand:SI 0 "register_operand" "=f")
-   (fix:SI (fix:SF (match_operand:SF 1 "register_operand" "f"]
+   (fix:SI (match_operand:SF 1 "register_operand" "f")))]
   "! TARGET_SOFT_FLOAT"
   "{fcnvfxt,sgl,sgl|fcnv,t,sgl,w} %1,%0"
   [(set_attr "type" "fpalu")
@@ -5034,7 +5034,7 @@
 
 (define_insn "fix_truncdfsi2"
   [(set (match_operand:SI 0 "register_operand" "=f")
-   (fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f"]
+   (fix:SI (match_operand:DF 1 "register_operand" "f")))]
   "! TARGET_SOFT_FLOAT"
   "{fcnvfxt,dbl,sgl|fcnv,t,dbl,w} %1,%0"
   [(set_attr "type" "fpalu")
@@ -5042,7 +5042,7 @@
 
 (define_insn "fix_truncsfdi2"
   [(set (match_operand:DI 0 "register_operand" "=f")
-   (fix:DI (fix:SF (match_operand:SF 1 "register_operand" "f"]
+   (fix:DI (match_operand:SF 1 "register_operand" "f")))]
   "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
   "{fcnvfxt,sgl,dbl|fcnv,t,sgl,dw} %1,%0"
   [(set_attr "type" "fpalu")
@@ -5050,7 +5050,7 @@
 
 (define_insn "fix_truncdfdi2"
   [(set (match_operand:DI 0 "register_operand" "=f")
-   (fix:DI (fix:DF (match_operand:DF 1 "register_operand" "f"]
+   (fix:DI (match_operand:DF 1 "register_operand" "f")))]
   "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
   "{fcnvfxt,dbl,dbl|fcnv,t,dbl,dw} %1,%0"
   [(set_attr "type" "fpalu")
@@ -5090,7 +5090,7 @@
 
 (define_insn "fixuns_truncsfsi2"
   [(set (match_operand:SI 0 "register_operand" "=f")
-   (unsigned_fix:SI (fix:SF (match_operand:SF 1 "register_operand" "f"]
+   (unsigned_fix:SI (match_operand:SF 1 "register_operand" "f")))]
   "! TARGET_SOFT_FLOAT && TARGET_PA_20"
   "fcnv,t,sgl,uw %1,%0"
   [(set_attr "type" "fpalu")
@@ -5098,7 +5098,7 @@
 
 (define_insn "fixuns_truncdfsi2"
   [(set (match_operand:SI 0 "register_operand" "=f")
-   (unsigned_fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f"]
+   (unsigned_fix:SI (match_operand:DF 1 "register_operand" "f")))]
   "! TARGET_SOFT_FLOAT && TARGET_PA_20"
   "fcnv,t,dbl,uw %1,%0"
   [(set_attr "type" "fpalu")
@@ -5106,7 +5106,7 @@
 
 (define_insn "fixuns_truncsfdi2"
   [(set (match_operand:DI 0 "register_operand" "=f")
-   (unsigned_fix:DI (fix:SF (match_operand:SF 1 "register_operand" "f"]
+   (unsigned_fix:DI (match_operand:SF 1 "register_operand" "f")))]
   "! TARGET_SOFT_FLOAT && TARGET_PA_20"
   "fcnv,t,sgl,udw %1,%0"
   [(set_attr "type" "fpalu")
@@ -5114,7 +5114,7 @@
 
 (define_insn "fixuns_truncdfdi2"
   [(set (match_operand:DI 0 "register_operand" "=f")
-   (unsigned_fix:DI (fix:DF (match_operand:DF 1 "register_operand" "f"]
+   (unsigned_fix:DI (match_operand:DF 1 "register_operand" "f")))]
   "! TARGET_SOFT_FLOAT && TARGET_PA_20"
   "fcnv,t,dbl,udw %1,%0"
   [(set_attr "type" "fpalu")

[gcc r14-10926] hppa: Remove inner `fix:SF/DF` from fixed-point patterns

2024-11-13 Thread John David Anglin via Gcc-cvs

https://gcc.gnu.org/g:39b0fb9bbcf49fc7a7c97c9efbc4453e1593b536

commit r14-10926-g39b0fb9bbcf49fc7a7c97c9efbc4453e1593b536
Author: John David Anglin 
Date:   Wed Nov 13 09:40:42 2024 -0500

hppa: Remove inner `fix:SF/DF` from fixed-point patterns

2024-11-13  John David Anglin  

gcc/ChangeLog:

PR target/117525
* config/pa/pa.md (fix_truncsfsi2): Remove inner `fix:SF`.
(fix_truncdfsi2, fix_truncsfdi2, fix_truncdfdi2,
fixuns_truncsfsi2, fixuns_truncdfsi2, fixuns_truncsfdi2,
fixuns_truncdfdi2): Likewise.

Diff:
---
 gcc/config/pa/pa.md | 16 
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/gcc/config/pa/pa.md b/gcc/config/pa/pa.md
index a72edc76f062..aa2d9956bd26 100644
--- a/gcc/config/pa/pa.md
+++ b/gcc/config/pa/pa.md
@@ -5018,7 +5018,7 @@
 
 (define_insn "fix_truncsfsi2"
   [(set (match_operand:SI 0 "register_operand" "=f")
-   (fix:SI (fix:SF (match_operand:SF 1 "register_operand" "f"]
+   (fix:SI (match_operand:SF 1 "register_operand" "f")))]
   "! TARGET_SOFT_FLOAT"
   "{fcnvfxt,sgl,sgl|fcnv,t,sgl,w} %1,%0"
   [(set_attr "type" "fpalu")
@@ -5026,7 +5026,7 @@
 
 (define_insn "fix_truncdfsi2"
   [(set (match_operand:SI 0 "register_operand" "=f")
-   (fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f"]
+   (fix:SI (match_operand:DF 1 "register_operand" "f")))]
   "! TARGET_SOFT_FLOAT"
   "{fcnvfxt,dbl,sgl|fcnv,t,dbl,w} %1,%0"
   [(set_attr "type" "fpalu")
@@ -5034,7 +5034,7 @@
 
 (define_insn "fix_truncsfdi2"
   [(set (match_operand:DI 0 "register_operand" "=f")
-   (fix:DI (fix:SF (match_operand:SF 1 "register_operand" "f"]
+   (fix:DI (match_operand:SF 1 "register_operand" "f")))]
   "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
   "{fcnvfxt,sgl,dbl|fcnv,t,sgl,dw} %1,%0"
   [(set_attr "type" "fpalu")
@@ -5042,7 +5042,7 @@
 
 (define_insn "fix_truncdfdi2"
   [(set (match_operand:DI 0 "register_operand" "=f")
-   (fix:DI (fix:DF (match_operand:DF 1 "register_operand" "f"]
+   (fix:DI (match_operand:DF 1 "register_operand" "f")))]
   "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
   "{fcnvfxt,dbl,dbl|fcnv,t,dbl,dw} %1,%0"
   [(set_attr "type" "fpalu")
@@ -5082,7 +5082,7 @@
 
 (define_insn "fixuns_truncsfsi2"
   [(set (match_operand:SI 0 "register_operand" "=f")
-   (unsigned_fix:SI (fix:SF (match_operand:SF 1 "register_operand" "f"]
+   (unsigned_fix:SI (match_operand:SF 1 "register_operand" "f")))]
   "! TARGET_SOFT_FLOAT && TARGET_PA_20"
   "fcnv,t,sgl,uw %1,%0"
   [(set_attr "type" "fpalu")
@@ -5090,7 +5090,7 @@
 
 (define_insn "fixuns_truncdfsi2"
   [(set (match_operand:SI 0 "register_operand" "=f")
-   (unsigned_fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f"]
+   (unsigned_fix:SI (match_operand:DF 1 "register_operand" "f")))]
   "! TARGET_SOFT_FLOAT && TARGET_PA_20"
   "fcnv,t,dbl,uw %1,%0"
   [(set_attr "type" "fpalu")
@@ -5098,7 +5098,7 @@
 
 (define_insn "fixuns_truncsfdi2"
   [(set (match_operand:DI 0 "register_operand" "=f")
-   (unsigned_fix:DI (fix:SF (match_operand:SF 1 "register_operand" "f"]
+   (unsigned_fix:DI (match_operand:SF 1 "register_operand" "f")))]
   "! TARGET_SOFT_FLOAT && TARGET_PA_20"
   "fcnv,t,sgl,udw %1,%0"
   [(set_attr "type" "fpalu")
@@ -5106,7 +5106,7 @@
 
 (define_insn "fixuns_truncdfdi2"
   [(set (match_operand:DI 0 "register_operand" "=f")
-   (unsigned_fix:DI (fix:DF (match_operand:DF 1 "register_operand" "f"]
+   (unsigned_fix:DI (match_operand:DF 1 "register_operand" "f")))]
   "! TARGET_SOFT_FLOAT && TARGET_PA_20"
   "fcnv,t,dbl,udw %1,%0"
   [(set_attr "type" "fpalu")

[gcc r13-9051] hppa: Add peephole2 optimizations for REG+D loads and stores

2024-09-22 Thread John David Anglin via Gcc-cvs

https://gcc.gnu.org/g:f4f2d6dd3d73321f177b2f9926a41bcd2e3a3300

commit r13-9051-gf4f2d6dd3d73321f177b2f9926a41bcd2e3a3300
Author: John David Anglin 
Date:   Wed Sep 18 11:02:32 2024 -0400

hppa: Add peephole2 optimizations for REG+D loads and stores

The PA 1.x architecture only supports long displacements in
integer loads and stores.  Floating-point loads and stores
only support short displacements.  As a result, we have to
wait until reload is complete before generating insns with
long displacements.

The PA 2.0 architecture supports long displacements in both
integer and floating-point loads and stores.

The peephole2 optimizations added in this change are only
enabled when 14-bit long displacements aren't supported for
floating-point loads and stores.

2024-09-18  John David Anglin  

gcc/ChangeLog:

* config/pa/pa.h (GENERAL_REGNO_P): Define.
* config/pa/pa.md: Add SImode and SFmode peephole2
patterns to generate loads and stores with long
displacements.

Diff:
---
 gcc/config/pa/pa.h  |   3 ++
 gcc/config/pa/pa.md | 100 
 2 files changed, 103 insertions(+)

diff --git a/gcc/config/pa/pa.h b/gcc/config/pa/pa.h
index 6e29be282ad9..2e8b248c2fcc 100644
--- a/gcc/config/pa/pa.h
+++ b/gcc/config/pa/pa.h
@@ -475,6 +475,9 @@ extern rtx hppa_pic_save_rtx (void);
 #define INDEX_REG_CLASS GENERAL_REGS
 #define BASE_REG_CLASS GENERAL_REGS
 
+/* True if register is a general register.  */
+#define GENERAL_REGNO_P(N) ((N) >= 1 && (N) <= 31)
+
 #define FP_REG_CLASS_P(CLASS) \
   ((CLASS) == FP_REGS || (CLASS) == FPUPPER_REGS)
 
diff --git a/gcc/config/pa/pa.md b/gcc/config/pa/pa.md
index d832a29683c2..c01719467856 100644
--- a/gcc/config/pa/pa.md
+++ b/gcc/config/pa/pa.md
@@ -2270,6 +2270,58 @@
(set_attr "pa_combine_type" "addmove")
(set_attr "length" "4")])
 
+; Rewrite RTL using a REG+D store.  This will allow the insn that
+; computes the address to be deleted if the register it sets is dead.
+(define_peephole2
+  [(set (match_operand:SI 0 "register_operand" "")
+   (plus:SI (match_operand:SI 1 "register_operand" "")
+(match_operand:SI 2 "const_int_operand" "")))
+   (set (mem:SI (match_dup 0))
+   (match_operand:SI 3 "register_operand" ""))]
+  "!TARGET_64BIT
+   && !INT14_OK_STRICT
+   && GENERAL_REGNO_P (REGNO (operands[0]))
+   && GENERAL_REGNO_P (REGNO (operands[3]))
+   && REGNO (operands[0]) != REGNO (operands[3])
+   && base14_operand (operands[2], E_SImode)"
+  [(set (mem:SI (plus:SI (match_dup 1) (match_dup 2))) (match_dup 3))
+   (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
+  "")
+
+; Rewrite RTL using a REG+D load.  This will allow the insn that
+; computes the address to be deleted if the register it sets is dead.
+(define_peephole2
+  [(set (match_operand:SI 0 "register_operand" "")
+   (plus:SI (match_operand:SI 1 "register_operand" "")
+(match_operand:SI 2 "const_int_operand" "")))
+   (set (match_operand:SI 3 "register_operand" "")
+   (mem:SI (match_dup 0)))]
+  "!TARGET_64BIT
+   && !INT14_OK_STRICT
+   && GENERAL_REGNO_P (REGNO (operands[0]))
+   && GENERAL_REGNO_P (REGNO (operands[3]))
+   && REGNO (operands[0]) != REGNO (operands[3])
+   && REGNO (operands[1]) != REGNO (operands[3])
+   && base14_operand (operands[2], E_SImode)"
+  [(set (match_dup 3) (mem:SI (plus:SI (match_dup 1) (match_dup 2
+   (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
+  "")
+
+(define_peephole2
+  [(set (match_operand:SI 0 "register_operand" "")
+   (plus:SI (match_operand:SI 1 "register_operand" "")
+(match_operand:SI 2 "const_int_operand" "")))
+   (set (match_operand:SI 3 "register_operand" "")
+   (mem:SI (match_dup 0)))]
+  "!TARGET_64BIT
+   && !INT14_OK_STRICT
+   && GENERAL_REGNO_P (REGNO (operands[0]))
+   && GENERAL_REGNO_P (REGNO (operands[3]))
+   && REGNO (operands[0]) == REGNO (operands[3])
+   && base14_operand (operands[2], E_SImode)"
+  [(set (match_dup 3) (mem:SI (plus:SI (match_dup 1) (match_dup 2]
+  "")
+
 ; Rewrite RTL using an indexed store.  This will allow the insn that
 ; computes the address to be deleted if the register it sets is dead.
 (define_peephole2
@@ -4497,6 +4549,54 @@
(set_attr "pa_combine_type" "addmove")
(set_attr "length" "4")])
 
+(define_peephole2
+  [(set (match_operand:SI 0 "register_operand" "")
+   (plus:SI (match_operand:SI 1 "register_operand" "")
+(match_operand:SI 2 "const_int_operand" "")))
+   (set (mem:SF (match_dup 0))
+   (match_operand:SF 3 "register_operand" ""))]
+  "!TARGET_64BIT
+   && !INT14_OK_STRICT
+   && GENERAL_REGNO_P (REGNO (operands[0]))
+   && GENERAL_REGNO_P (REGNO (operands[3]))
+   && REGNO (operands[0]) != REGNO (operands[3])
+   && base14_operand (operands[2], E_SImode)"
+  [(set (mem:SF (plus:SI (match_dup 1) (match_dup

[gcc r14-10700] hppa: Add peephole2 optimizations for REG+D loads and stores

2024-09-22 Thread John David Anglin via Gcc-cvs

https://gcc.gnu.org/g:cf4086628dd5546cc0efdd5afa102fee6b16385d

commit r14-10700-gcf4086628dd5546cc0efdd5afa102fee6b16385d
Author: John David Anglin 
Date:   Wed Sep 18 11:02:32 2024 -0400

hppa: Add peephole2 optimizations for REG+D loads and stores

The PA 1.x architecture only supports long displacements in
integer loads and stores.  Floating-point loads and stores
only support short displacements.  As a result, we have to
wait until reload is complete before generating insns with
long displacements.

The PA 2.0 architecture supports long displacements in both
integer and floating-point loads and stores.

The peephole2 optimizations added in this change are only
enabled when 14-bit long displacements aren't supported for
floating-point loads and stores.

2024-09-18  John David Anglin  

gcc/ChangeLog:

* config/pa/pa.h (GENERAL_REGNO_P): Define.
* config/pa/pa.md: Add SImode and SFmode peephole2
patterns to generate loads and stores with long
displacements.

Diff:
---
 gcc/config/pa/pa.h  |   3 ++
 gcc/config/pa/pa.md | 100 
 2 files changed, 103 insertions(+)

diff --git a/gcc/config/pa/pa.h b/gcc/config/pa/pa.h
index 127a0d1966d2..49c798e49338 100644
--- a/gcc/config/pa/pa.h
+++ b/gcc/config/pa/pa.h
@@ -480,6 +480,9 @@ extern rtx hppa_pic_save_rtx (void);
 #define INDEX_REG_CLASS GENERAL_REGS
 #define BASE_REG_CLASS GENERAL_REGS
 
+/* True if register is a general register.  */
+#define GENERAL_REGNO_P(N) ((N) >= 1 && (N) <= 31)
+
 #define FP_REG_CLASS_P(CLASS) \
   ((CLASS) == FP_REGS || (CLASS) == FPUPPER_REGS)
 
diff --git a/gcc/config/pa/pa.md b/gcc/config/pa/pa.md
index 9e410f43052d..c03332761442 100644
--- a/gcc/config/pa/pa.md
+++ b/gcc/config/pa/pa.md
@@ -2280,6 +2280,58 @@
(set_attr "pa_combine_type" "addmove")
(set_attr "length" "4")])
 
+; Rewrite RTL using a REG+D store.  This will allow the insn that
+; computes the address to be deleted if the register it sets is dead.
+(define_peephole2
+  [(set (match_operand:SI 0 "register_operand" "")
+   (plus:SI (match_operand:SI 1 "register_operand" "")
+(match_operand:SI 2 "const_int_operand" "")))
+   (set (mem:SI (match_dup 0))
+   (match_operand:SI 3 "register_operand" ""))]
+  "!TARGET_64BIT
+   && !INT14_OK_STRICT
+   && GENERAL_REGNO_P (REGNO (operands[0]))
+   && GENERAL_REGNO_P (REGNO (operands[3]))
+   && REGNO (operands[0]) != REGNO (operands[3])
+   && base14_operand (operands[2], E_SImode)"
+  [(set (mem:SI (plus:SI (match_dup 1) (match_dup 2))) (match_dup 3))
+   (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
+  "")
+
+; Rewrite RTL using a REG+D load.  This will allow the insn that
+; computes the address to be deleted if the register it sets is dead.
+(define_peephole2
+  [(set (match_operand:SI 0 "register_operand" "")
+   (plus:SI (match_operand:SI 1 "register_operand" "")
+(match_operand:SI 2 "const_int_operand" "")))
+   (set (match_operand:SI 3 "register_operand" "")
+   (mem:SI (match_dup 0)))]
+  "!TARGET_64BIT
+   && !INT14_OK_STRICT
+   && GENERAL_REGNO_P (REGNO (operands[0]))
+   && GENERAL_REGNO_P (REGNO (operands[3]))
+   && REGNO (operands[0]) != REGNO (operands[3])
+   && REGNO (operands[1]) != REGNO (operands[3])
+   && base14_operand (operands[2], E_SImode)"
+  [(set (match_dup 3) (mem:SI (plus:SI (match_dup 1) (match_dup 2
+   (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
+  "")
+
+(define_peephole2
+  [(set (match_operand:SI 0 "register_operand" "")
+   (plus:SI (match_operand:SI 1 "register_operand" "")
+(match_operand:SI 2 "const_int_operand" "")))
+   (set (match_operand:SI 3 "register_operand" "")
+   (mem:SI (match_dup 0)))]
+  "!TARGET_64BIT
+   && !INT14_OK_STRICT
+   && GENERAL_REGNO_P (REGNO (operands[0]))
+   && GENERAL_REGNO_P (REGNO (operands[3]))
+   && REGNO (operands[0]) == REGNO (operands[3])
+   && base14_operand (operands[2], E_SImode)"
+  [(set (match_dup 3) (mem:SI (plus:SI (match_dup 1) (match_dup 2]
+  "")
+
 ; Rewrite RTL using an indexed store.  This will allow the insn that
 ; computes the address to be deleted if the register it sets is dead.
 (define_peephole2
@@ -4507,6 +4559,54 @@
(set_attr "pa_combine_type" "addmove")
(set_attr "length" "4")])
 
+(define_peephole2
+  [(set (match_operand:SI 0 "register_operand" "")
+   (plus:SI (match_operand:SI 1 "register_operand" "")
+(match_operand:SI 2 "const_int_operand" "")))
+   (set (mem:SF (match_dup 0))
+   (match_operand:SF 3 "register_operand" ""))]
+  "!TARGET_64BIT
+   && !INT14_OK_STRICT
+   && GENERAL_REGNO_P (REGNO (operands[0]))
+   && GENERAL_REGNO_P (REGNO (operands[3]))
+   && REGNO (operands[0]) != REGNO (operands[3])
+   && base14_operand (operands[2], E_SImode)"
+  [(set (mem:SF (plus:SI (match_dup 1) (match_dup

[gcc r15-3692] hppa: Add peephole2 optimizations for REG+D loads and stores

2024-09-18 Thread John David Anglin via Gcc-cvs

https://gcc.gnu.org/g:4b03750f8cda0a8745b10639a8ac7df71aced0cc

commit r15-3692-g4b03750f8cda0a8745b10639a8ac7df71aced0cc
Author: John David Anglin 
Date:   Wed Sep 18 11:02:32 2024 -0400

hppa: Add peephole2 optimizations for REG+D loads and stores

The PA 1.x architecture only supports long displacements in
integer loads and stores.  Floating-point loads and stores
only support short displacements.  As a result, we have to
wait until reload is complete before generating insns with
long displacements.

The PA 2.0 architecture supports long displacements in both
integer and floating-point loads and stores.

The peephole2 optimizations added in this change are only
enabled when 14-bit long displacements aren't supported for
floating-point loads and stores.

2024-09-18  John David Anglin  

gcc/ChangeLog:

* config/pa/pa.h (GENERAL_REGNO_P): Define.
* config/pa/pa.md: Add SImode and SFmode peephole2
patterns to generate loads and stores with long
displacements.

Diff:
---
 gcc/config/pa/pa.h  |   3 ++
 gcc/config/pa/pa.md | 100 
 2 files changed, 103 insertions(+)

diff --git a/gcc/config/pa/pa.h b/gcc/config/pa/pa.h
index 7e45c358895b..6fcc2fa2ac76 100644
--- a/gcc/config/pa/pa.h
+++ b/gcc/config/pa/pa.h
@@ -480,6 +480,9 @@ extern rtx hppa_pic_save_rtx (void);
 #define INDEX_REG_CLASS GENERAL_REGS
 #define BASE_REG_CLASS GENERAL_REGS
 
+/* True if register is a general register.  */
+#define GENERAL_REGNO_P(N) ((N) >= 1 && (N) <= 31)
+
 #define FP_REG_CLASS_P(CLASS) \
   ((CLASS) == FP_REGS || (CLASS) == FPUPPER_REGS)
 
diff --git a/gcc/config/pa/pa.md b/gcc/config/pa/pa.md
index 1e781efb66b0..f0520bb2c353 100644
--- a/gcc/config/pa/pa.md
+++ b/gcc/config/pa/pa.md
@@ -2280,6 +2280,58 @@
(set_attr "pa_combine_type" "addmove")
(set_attr "length" "4")])
 
+; Rewrite RTL using a REG+D store.  This will allow the insn that
+; computes the address to be deleted if the register it sets is dead.
+(define_peephole2
+  [(set (match_operand:SI 0 "register_operand" "")
+   (plus:SI (match_operand:SI 1 "register_operand" "")
+(match_operand:SI 2 "const_int_operand" "")))
+   (set (mem:SI (match_dup 0))
+   (match_operand:SI 3 "register_operand" ""))]
+  "!TARGET_64BIT
+   && !INT14_OK_STRICT
+   && GENERAL_REGNO_P (REGNO (operands[0]))
+   && GENERAL_REGNO_P (REGNO (operands[3]))
+   && REGNO (operands[0]) != REGNO (operands[3])
+   && base14_operand (operands[2], E_SImode)"
+  [(set (mem:SI (plus:SI (match_dup 1) (match_dup 2))) (match_dup 3))
+   (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
+  "")
+
+; Rewrite RTL using a REG+D load.  This will allow the insn that
+; computes the address to be deleted if the register it sets is dead.
+(define_peephole2
+  [(set (match_operand:SI 0 "register_operand" "")
+   (plus:SI (match_operand:SI 1 "register_operand" "")
+(match_operand:SI 2 "const_int_operand" "")))
+   (set (match_operand:SI 3 "register_operand" "")
+   (mem:SI (match_dup 0)))]
+  "!TARGET_64BIT
+   && !INT14_OK_STRICT
+   && GENERAL_REGNO_P (REGNO (operands[0]))
+   && GENERAL_REGNO_P (REGNO (operands[3]))
+   && REGNO (operands[0]) != REGNO (operands[3])
+   && REGNO (operands[1]) != REGNO (operands[3])
+   && base14_operand (operands[2], E_SImode)"
+  [(set (match_dup 3) (mem:SI (plus:SI (match_dup 1) (match_dup 2
+   (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
+  "")
+
+(define_peephole2
+  [(set (match_operand:SI 0 "register_operand" "")
+   (plus:SI (match_operand:SI 1 "register_operand" "")
+(match_operand:SI 2 "const_int_operand" "")))
+   (set (match_operand:SI 3 "register_operand" "")
+   (mem:SI (match_dup 0)))]
+  "!TARGET_64BIT
+   && !INT14_OK_STRICT
+   && GENERAL_REGNO_P (REGNO (operands[0]))
+   && GENERAL_REGNO_P (REGNO (operands[3]))
+   && REGNO (operands[0]) == REGNO (operands[3])
+   && base14_operand (operands[2], E_SImode)"
+  [(set (match_dup 3) (mem:SI (plus:SI (match_dup 1) (match_dup 2]
+  "")
+
 ; Rewrite RTL using an indexed store.  This will allow the insn that
 ; computes the address to be deleted if the register it sets is dead.
 (define_peephole2
@@ -4507,6 +4559,54 @@
(set_attr "pa_combine_type" "addmove")
(set_attr "length" "4")])
 
+(define_peephole2
+  [(set (match_operand:SI 0 "register_operand" "")
+   (plus:SI (match_operand:SI 1 "register_operand" "")
+(match_operand:SI 2 "const_int_operand" "")))
+   (set (mem:SF (match_dup 0))
+   (match_operand:SF 3 "register_operand" ""))]
+  "!TARGET_64BIT
+   && !INT14_OK_STRICT
+   && GENERAL_REGNO_P (REGNO (operands[0]))
+   && GENERAL_REGNO_P (REGNO (operands[3]))
+   && REGNO (operands[0]) != REGNO (operands[3])
+   && base14_operand (operands[2], E_SImode)"
+  [(set (mem:SF (plus:SI (match_dup 1) (match_dup

[gcc r15-5659] hppa: Revise TImode aritmetic patterns to support arith11_operands

2024-11-25 Thread John David Anglin via Gcc-cvs

https://gcc.gnu.org/g:22b13b1d4e3dce6bbc8792ffa08cefeb5e125a03

commit r15-5659-g22b13b1d4e3dce6bbc8792ffa08cefeb5e125a03
Author: John David Anglin 
Date:   Mon Nov 25 16:40:29 2024 -0500

hppa: Revise TImode aritmetic patterns to support arith11_operands

2024-11-25  John David Anglin  

gcc/ChangeLog:

PR target/117645
* config/pa/pa.md (addti3): Revise pattern to support
arith11_operands.  Use "R" operand prefix to print least
significant register of TImode register pair.
(addvti3, subti3, subvti3): Likewise.
(negti2, negvti2): Use "R" operand prefix.

Diff:
---
 gcc/config/pa/pa.md | 118 +++-
 1 file changed, 62 insertions(+), 56 deletions(-)

diff --git a/gcc/config/pa/pa.md b/gcc/config/pa/pa.md
index dd1267e04a5a..c4441d8b91d0 100644
--- a/gcc/config/pa/pa.md
+++ b/gcc/config/pa/pa.md
@@ -5481,18 +5481,20 @@
 
 (define_insn "addti3"
   [(set (match_operand:TI 0 "register_operand" "=r")
-   (plus:TI (match_operand:TI 1 "register_operand" "r")
-(match_operand:TI 2 "register_operand" "r")))]
+   (plus:TI (match_operand:TI 1 "register_operand" "%r")
+(match_operand:TI 2 "arith11_operand" "rI")))]
   "TARGET_64BIT"
   "*
 {
-  operands[3] = gen_lowpart (DImode, operands[0]);
-  operands[4] = gen_lowpart (DImode, operands[1]);
-  operands[5] = gen_lowpart (DImode, operands[2]);
-  operands[0] = gen_highpart (DImode, operands[0]);
-  operands[1] = gen_highpart (DImode, operands[1]);
-  operands[2] = gen_highpart (DImode, operands[2]);
-  return \"add %4,%5,%3\;add,dc %1,%2,%0\";
+  if (GET_CODE (operands[2]) == CONST_INT)
+{
+  if (INTVAL (operands[2]) >= 0)
+   return \"addi %2,%R1,%R0\;add,dc %1,%%r0,%0\";
+  else
+   return \"addi %2,%R1,%R0\;sub,db %1,%%r0,%0\";
+}
+  else
+return \"add %R2,%R1,%R0\;add,dc %2,%1,%0\";
 }"
   [(set_attr "type" "multi")
(set_attr "length" "8")])
@@ -5500,7 +5502,7 @@
 (define_insn "addvti3"
   [(set (match_operand:TI 0 "register_operand" "=r")
(plus:TI (match_operand:TI 1 "register_operand" "r")
-(match_operand:TI 2 "register_operand" "r")))
+(match_operand:TI 2 "arith11_operand" "rI")))
(trap_if (ne (plus:OI (sign_extend:OI (match_dup 1))
 (sign_extend:OI (match_dup 2)))
(sign_extend:OI (plus:TI (match_dup 1)
@@ -5509,39 +5511,49 @@
   "TARGET_64BIT"
   "*
 {
-  operands[3] = gen_lowpart (DImode, operands[0]);
-  operands[4] = gen_lowpart (DImode, operands[1]);
-  operands[5] = gen_lowpart (DImode, operands[2]);
-  operands[0] = gen_highpart (DImode, operands[0]);
-  operands[1] = gen_highpart (DImode, operands[1]);
-  operands[2] = gen_highpart (DImode, operands[2]);
-  return \"add %4,%5,%3\;add,dc,tsv %1,%2,%0\";
+  if (GET_CODE (operands[2]) == CONST_INT)
+{
+  if (INTVAL (operands[2]) >= 0)
+   return \"addi %2,%R1,%R0\;add,dc,tsv %1,%%r0,%0\";
+  else
+   return \"addi %2,%R1,%R0\;sub,db,tsv %1,%%r0,%0\";
+}
+  else
+return \"add %R2,%R1,%R0\;add,dc,tsv %2,%1,%0\";
 }"
   [(set_attr "type" "multi")
(set_attr "length" "8")])
 
 (define_insn "subti3"
-  [(set (match_operand:TI 0 "register_operand" "=r")
-   (minus:TI (match_operand:TI 1 "register_operand" "r")
- (match_operand:TI 2 "register_operand" "r")))]
+  [(set (match_operand:TI 0 "register_operand" "=r,&r")
+   (minus:TI (match_operand:TI 1 "arith11_operand" "r,I")
+ (match_operand:TI 2 "reg_or_0_operand" "rM,rM")))]
   "TARGET_64BIT"
   "*
 {
-  operands[3] = gen_lowpart (DImode, operands[0]);
-  operands[4] = gen_lowpart (DImode, operands[1]);
-  operands[5] = gen_lowpart (DImode, operands[2]);
-  operands[0] = gen_highpart (DImode, operands[0]);
-  operands[1] = gen_highpart (DImode, operands[1]);
-  operands[2] = gen_highpart (DImode, operands[2]);
-  return \"sub %4,%5,%3\;sub,db %1,%2,%0\";
+  if (GET_CODE (operands[1]) == CONST_INT)
+{
+  if (INTVAL (operands[1]) >= 0)
+   return \"subi %1,%R2,%R0\;sub,db %%r0,%2,%0\";
+  else
+   return \"ldi -1,%0\;subi %1,%R2,%R0\;sub,db %0,%2,%0\";
+}
+  else
+return \"sub %R1,%R2,%R0\;sub,db %1,%2,%0\";
 }"
   [(set_attr "type" "multi")
-   (set_attr "length" "8")])
+   (set (attr "length")
+   (if_then_else (eq_attr "alternative" "0")
+ (const_int 8)
+ (if_then_else (ge (symbol_ref "INTVAL (operands[1])")
+   (const_int 0))
+   (const_int 8)
+   (const_int 12])
 
 (define_insn "subvti3"
-  [(set (match_operand:TI 0 "register_operand" "=r")
-   (minus:TI (match_operand:TI 1 "register_operand" "r")
- (match_operand:TI 2 "register_operand" "r")))
+  [(set (match_operand:TI 0 "register_operand" "=r,&r")
+   (minus:TI (match_operand:TI 1 "arith11_operand" "r,I")
+ (match_op

[gcc r15-5370] hppa: Remove typedef for bool type

2024-11-18 Thread John David Anglin via Gcc-cvs

https://gcc.gnu.org/g:8f50a0794076d6e1d4d1ed693b94d6ee2e4cd849

commit r15-5370-g8f50a0794076d6e1d4d1ed693b94d6ee2e4cd849
Author: John David Anglin 
Date:   Sun Nov 17 14:42:39 2024 -0500

hppa: Remove typedef for bool type

In C23, bool is now a keyword.  So, doing a typedef for it is invalid.

2024-11-17  John David Anglin  

libgcc/ChangeLog:

PR target/117627
* config/pa/linux-atomic.c: Remove typedef for bool type.

Diff:
---
 libgcc/config/pa/linux-atomic.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/libgcc/config/pa/linux-atomic.c b/libgcc/config/pa/linux-atomic.c
index 03ebccfc0707..6191f83ed1c7 100644
--- a/libgcc/config/pa/linux-atomic.c
+++ b/libgcc/config/pa/linux-atomic.c
@@ -264,8 +264,6 @@ OP_AND_FETCH_WORD (and,   , &)
 OP_AND_FETCH_WORD (xor,   , ^)
 OP_AND_FETCH_WORD (nand, ~, &)
 
-typedef unsigned char bool;
-
 #define COMPARE_AND_SWAP_2(TYPE, WIDTH, INDEX) \
   TYPE HIDDEN  \
   __sync_val_compare_and_swap_##WIDTH (volatile void *ptr, TYPE oldval,
\

[gcc r14-10932] hppa: Fix typos in 32-bit SFmode peephole2 patterns

2024-11-15 Thread John David Anglin via Gcc-cvs

https://gcc.gnu.org/g:878b3354859ace887c0613fda6b79e96d6d5024b

commit r14-10932-g878b3354859ace887c0613fda6b79e96d6d5024b
Author: John David Anglin 
Date:   Fri Nov 15 11:05:58 2024 -0500

hppa: Fix typos in 32-bit SFmode peephole2 patterns

2024-11-15  John David Anglin  

gcc/ChangeLog:

PR target/117564
* config/pa/pa.md: Fix typos in 32-bit SFmode peephole2 patterns.

Diff:
---
 gcc/config/pa/pa.md | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/gcc/config/pa/pa.md b/gcc/config/pa/pa.md
index aa2d9956bd26..6a661b4980ce 100644
--- a/gcc/config/pa/pa.md
+++ b/gcc/config/pa/pa.md
@@ -4588,7 +4588,7 @@
&& REGNO (operands[0]) != REGNO (operands[3])
&& REGNO (operands[1]) != REGNO (operands[3])
&& base14_operand (operands[2], E_SImode)"
-  [(set (match_dup 3) (mem:SF (plus:DI (match_dup 1) (match_dup 2
+  [(set (match_dup 3) (mem:SF (plus:SI (match_dup 1) (match_dup 2
(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
   "")
 
@@ -4604,7 +4604,7 @@
&& GENERAL_REGNO_P (REGNO (operands[3]))
&& REGNO (operands[0]) == REGNO (operands[3])
&& base14_operand (operands[2], E_SImode)"
-  [(set (match_dup 3) (mem:SF (plus:DI (match_dup 1) (match_dup 2]
+  [(set (match_dup 3) (mem:SF (plus:SI (match_dup 1) (match_dup 2]
   "")
 
 (define_peephole2

[gcc r13-9194] hppa: Fix typos in 32-bit SFmode peephole2 patterns

2024-11-15 Thread John David Anglin via Gcc-cvs

https://gcc.gnu.org/g:e99c6e555703bd2b5d139914b24958a1a5de1d69

commit r13-9194-ge99c6e555703bd2b5d139914b24958a1a5de1d69
Author: John David Anglin 
Date:   Fri Nov 15 11:05:58 2024 -0500

hppa: Fix typos in 32-bit SFmode peephole2 patterns

2024-11-15  John David Anglin  

gcc/ChangeLog:

PR target/117564
* config/pa/pa.md: Fix typos in 32-bit SFmode peephole2 patterns.

Diff:
---
 gcc/config/pa/pa.md | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/gcc/config/pa/pa.md b/gcc/config/pa/pa.md
index 63c9472bf1ae..194d57527aa6 100644
--- a/gcc/config/pa/pa.md
+++ b/gcc/config/pa/pa.md
@@ -4578,7 +4578,7 @@
&& REGNO (operands[0]) != REGNO (operands[3])
&& REGNO (operands[1]) != REGNO (operands[3])
&& base14_operand (operands[2], E_SImode)"
-  [(set (match_dup 3) (mem:SF (plus:DI (match_dup 1) (match_dup 2
+  [(set (match_dup 3) (mem:SF (plus:SI (match_dup 1) (match_dup 2
(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
   "")
 
@@ -4594,7 +4594,7 @@
&& GENERAL_REGNO_P (REGNO (operands[3]))
&& REGNO (operands[0]) == REGNO (operands[3])
&& base14_operand (operands[2], E_SImode)"
-  [(set (match_dup 3) (mem:SF (plus:DI (match_dup 1) (match_dup 2]
+  [(set (match_dup 3) (mem:SF (plus:SI (match_dup 1) (match_dup 2]
   "")
 
 (define_peephole2

[gcc r15-5323] hppa: Fix typos in 32-bit SFmode peephole2 patterns

2024-11-15 Thread John David Anglin via Gcc-cvs

https://gcc.gnu.org/g:029c16c15f79dc27d44d77d82fd38aabe83bd4f7

commit r15-5323-g029c16c15f79dc27d44d77d82fd38aabe83bd4f7
Author: John David Anglin 
Date:   Fri Nov 15 11:05:58 2024 -0500

hppa: Fix typos in 32-bit SFmode peephole2 patterns

2024-11-15  John David Anglin  

gcc/ChangeLog:

PR target/117564
* config/pa/pa.md: Fix typos in 32-bit SFmode peephole2 patterns.

Diff:
---
 gcc/config/pa/pa.md | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/gcc/config/pa/pa.md b/gcc/config/pa/pa.md
index f3c6262230d8..dd1267e04a5a 100644
--- a/gcc/config/pa/pa.md
+++ b/gcc/config/pa/pa.md
@@ -4596,7 +4596,7 @@
&& REGNO (operands[0]) != REGNO (operands[3])
&& REGNO (operands[1]) != REGNO (operands[3])
&& base14_operand (operands[2], E_SImode)"
-  [(set (match_dup 3) (mem:SF (plus:DI (match_dup 1) (match_dup 2
+  [(set (match_dup 3) (mem:SF (plus:SI (match_dup 1) (match_dup 2
(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
   "")
 
@@ -4612,7 +4612,7 @@
&& GENERAL_REGNO_P (REGNO (operands[3]))
&& REGNO (operands[0]) == REGNO (operands[3])
&& base14_operand (operands[2], E_SImode)"
-  [(set (match_dup 3) (mem:SF (plus:DI (match_dup 1) (match_dup 2]
+  [(set (match_dup 3) (mem:SF (plus:SI (match_dup 1) (match_dup 2]
   "")
 
 (define_peephole2

[gcc r15-6443] Fix timevar.cc build on systems that don't have CLOCK_MONOTONIC

2024-12-26 Thread John David Anglin via Gcc-cvs

https://gcc.gnu.org/g:06867d9fa69ca6d4ded4602e6601c7153599cbff

commit r15-6443-g06867d9fa69ca6d4ded4602e6601c7153599cbff
Author: John David Anglin 
Date:   Thu Dec 26 11:27:36 2024 -0500

Fix timevar.cc build on systems that don't have CLOCK_MONOTONIC

2024-12-26  John David Anglin  

gcc/ChangeLog:

PR target/118050
* timevar.cc (get_time): Only use CLOCK_MONOTONIC if
'_POSIX_TIMERS > 0 && defined(_POSIX_MONOTONIC_CLOCK)'.
Otherise, use CLOCK_REALTIME.

Diff:
---
 gcc/timevar.cc | 4 
 1 file changed, 4 insertions(+)

diff --git a/gcc/timevar.cc b/gcc/timevar.cc
index 48d0c72cbdfc..21fd65d2f892 100644
--- a/gcc/timevar.cc
+++ b/gcc/timevar.cc
@@ -160,7 +160,11 @@ get_time (struct timevar_time_def *now)
 
 #ifdef HAVE_CLOCK_GETTIME
   struct timespec ts;
+#if _POSIX_TIMERS > 0 && defined(_POSIX_MONOTONIC_CLOCK)
   clock_gettime (CLOCK_MONOTONIC, &ts);
+#else
+  clock_gettime (CLOCK_REALTIME, &ts);
+#endif
   now->wall = ts.tv_sec * 10 + ts.tv_nsec;
   return;
 #define HAVE_WALL_TIME 1

[gcc r15-7333] hppa: Revise various millicode insn patterns to use match_operand

2025-02-03 Thread John David Anglin via Gcc-cvs

https://gcc.gnu.org/g:88bb18ccd87d43abe401a1228cc337e4b46be88d

commit r15-7333-g88bb18ccd87d43abe401a1228cc337e4b46be88d
Author: John David Anglin 
Date:   Mon Feb 3 11:35:38 2025 -0500

hppa: Revise various millicode insn patterns to use match_operand

LRA does not correctly support hard-register input operands that
are clobbered.  This is needed to support millicode calls on hppa.
The operand setup is sometimes deleted.

This problem can be avoided by hiding hard-register input operands
using match_operand.  This also potentially allows for constraints
that specify the operand is both read and written.

2025-02-03  John David Anglin  

gcc/ChangeLog:

PR rtl-optimization/117248
* config/pa/predicates.md (r25_operand): New predicate.
(r26_operand): Likewise.
* config/pa/pa.md: Use match_operand for r25 and r26 hard
register operands in mult, div, udiv, mod and umod millicode
patterns.

Diff:
---
 gcc/config/pa/pa.md | 56 +
 gcc/config/pa/predicates.md | 16 +
 2 files changed, 52 insertions(+), 20 deletions(-)

diff --git a/gcc/config/pa/pa.md b/gcc/config/pa/pa.md
index df1b61e871f1..23129940e644 100644
--- a/gcc/config/pa/pa.md
+++ b/gcc/config/pa/pa.md
@@ -5632,8 +5632,10 @@
(set_attr "length" "4")])
 
 (define_insn ""
-  [(set (reg:SI 29) (mult:SI (reg:SI 26) (reg:SI 25)))
-   (clobber (match_operand:SI 0 "register_operand" "=a"))
+  [(set (reg:SI 29)
+   (mult:SI (match_operand:SI 1 "r26_operand" "")
+(match_operand:SI 0 "r25_operand" "")))
+   (clobber (match_operand:SI 2 "register_operand" "=a"))
(clobber (reg:SI 26))
(clobber (reg:SI 25))
(clobber (reg:SI 31))]
@@ -5645,8 +5647,10 @@
  (symbol_ref "pa_attr_length_millicode_call (insn)")))])
 
 (define_insn ""
-  [(set (reg:SI 29) (mult:SI (reg:SI 26) (reg:SI 25)))
-   (clobber (match_operand:SI 0 "register_operand" "=a"))
+  [(set (reg:SI 29)
+   (mult:SI (match_operand:SI 1 "r26_operand" "")
+(match_operand:SI 0 "r25_operand" "")))
+   (clobber (match_operand:SI 2 "register_operand" "=a"))
(clobber (reg:SI 26))
(clobber (reg:SI 25))
(clobber (reg:SI 2))]
@@ -5753,8 +5757,9 @@
 
 (define_insn ""
   [(set (reg:SI 29)
-   (div:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
-   (clobber (match_operand:SI 1 "register_operand" "=a"))
+   (div:SI (match_operand:SI 1 "r26_operand" "")
+   (match_operand:SI 0 "div_operand" "")))
+   (clobber (match_operand:SI 2 "register_operand" "=a"))
(clobber (reg:SI 26))
(clobber (reg:SI 25))
(clobber (reg:SI 31))]
@@ -5768,8 +5773,9 @@
 
 (define_insn ""
   [(set (reg:SI 29)
-   (div:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
-   (clobber (match_operand:SI 1 "register_operand" "=a"))
+   (div:SI (match_operand:SI 1 "r26_operand" "")
+   (match_operand:SI 0 "div_operand" "")))
+   (clobber (match_operand:SI 2 "register_operand" "=a"))
(clobber (reg:SI 26))
(clobber (reg:SI 25))
(clobber (reg:SI 2))]
@@ -5800,8 +5806,9 @@
 
 (define_insn ""
   [(set (reg:SI 29)
-   (udiv:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
-   (clobber (match_operand:SI 1 "register_operand" "=a"))
+   (udiv:SI (match_operand:SI 1 "r26_operand" "")
+(match_operand:SI 0 "div_operand" "")))
+   (clobber (match_operand:SI 2 "register_operand" "=a"))
(clobber (reg:SI 26))
(clobber (reg:SI 25))
(clobber (reg:SI 31))]
@@ -5815,8 +5822,9 @@
 
 (define_insn ""
   [(set (reg:SI 29)
-   (udiv:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
-   (clobber (match_operand:SI 1 "register_operand" "=a"))
+   (udiv:SI (match_operand:SI 1 "r26_operand" "")
+(match_operand:SI 0 "div_operand" "")))
+   (clobber (match_operand:SI 2 "register_operand" "=a"))
(clobber (reg:SI 26))
(clobber (reg:SI 25))
(clobber (reg:SI 2))]
@@ -5844,8 +5852,10 @@
 }")
 
 (define_insn ""
-  [(set (reg:SI 29) (mod:SI (reg:SI 26) (reg:SI 25)))
-   (clobber (match_operand:SI 0 "register_operand" "=a"))
+  [(set (reg:SI 29)
+   (mod:SI (match_operand:SI 1 "r26_operand" "")
+   (match_operand:SI 0 "r25_operand" "")))
+   (clobber (match_operand:SI 2 "register_operand" "=a"))
(clobber (reg:SI 26))
(clobber (reg:SI 25))
(clobber (reg:SI 31))]
@@ -5858,8 +5868,10 @@
  (symbol_ref "pa_attr_length_millicode_call (insn)")))])
 
 (define_insn ""
-  [(set (reg:SI 29) (mod:SI (reg:SI 26) (reg:SI 25)))
-   (clobber (match_operand:SI 0 "register_operand" "=a"))
+  [(set (reg:SI 29)
+   (mod:SI (match_operand:SI 1 "r26_operand" "")
+   (match_operand:SI 0 "r25_operand" "")))
+   (clobber (match_operand:SI 2 "register_operand" "=a"))
(clobber (reg:SI 26))
(clobber (reg:SI 25))
(clobber (reg:SI 2))]
@

[gcc r15-6266] testsuite: Require lto in g++.dg/modules/enum-14.C

2024-12-15 Thread John David Anglin via Gcc-cvs

https://gcc.gnu.org/g:de0033bad742b5fe4127a72821a3dab139f6960d

commit r15-6266-gde0033bad742b5fe4127a72821a3dab139f6960d
Author: John David Anglin 
Date:   Sun Dec 15 15:39:50 2024 -0500

testsuite: Require lto in g++.dg/modules/enum-14.C

2024-12-15  John David Anglin  

gcc/testsuite/ChangeLog:

* g++.dg/modules/enum-14.C: Require lto.

Diff:
---
 gcc/testsuite/g++.dg/modules/enum-14.C | 1 +
 1 file changed, 1 insertion(+)

diff --git a/gcc/testsuite/g++.dg/modules/enum-14.C 
b/gcc/testsuite/g++.dg/modules/enum-14.C
index 636d797afdcb..d8d41ce6f752 100644
--- a/gcc/testsuite/g++.dg/modules/enum-14.C
+++ b/gcc/testsuite/g++.dg/modules/enum-14.C
@@ -1,4 +1,5 @@
 // PR c++/116929
+// { dg-require-effective-target lto }
 // { dg-additional-options "-flto -fmodules-ts -Wno-global-module" }
 
 module;

[gcc r15-6269] hppa: Implement TARGET_FRAME_POINTER_REQUIRED

2024-12-15 Thread John David Anglin via Gcc-cvs

https://gcc.gnu.org/g:3e7ae868fa057a808448a5ab081d2ad30ad80bab

commit r15-6269-g3e7ae868fa057a808448a5ab081d2ad30ad80bab
Author: John David Anglin 
Date:   Sun Dec 15 17:18:40 2024 -0500

hppa: Implement TARGET_FRAME_POINTER_REQUIRED

If a function receives nonlocal gotos, it needs to save the frame
pointer in the argument save area.  This ensures that LRA sets
frame_pointer_needed when it saves arguments in the save area.

2024-12-15  John David Anglin  

gcc/ChangeLog:

PR target/118018
* config/pa/pa.cc (pa_frame_pointer_required): Declare and
implement.
(TARGET_FRAME_POINTER_REQUIRED): Define.

Diff:
---
 gcc/config/pa/pa.cc | 16 
 1 file changed, 16 insertions(+)

diff --git a/gcc/config/pa/pa.cc b/gcc/config/pa/pa.cc
index 99ed2863eb9f..df2ec3c515f9 100644
--- a/gcc/config/pa/pa.cc
+++ b/gcc/config/pa/pa.cc
@@ -209,6 +209,7 @@ static HOST_WIDE_INT pa_starting_frame_offset (void);
 static section* pa_elf_select_rtx_section(machine_mode, rtx, unsigned 
HOST_WIDE_INT) ATTRIBUTE_UNUSED;
 static void pa_atomic_assign_expand_fenv (tree *, tree *, tree *);
 static bool pa_use_lra_p (void);
+static bool pa_frame_pointer_required (void);
 
 /* The following extra sections are only used for SOM.  */
 static GTY(()) section *som_readonly_data_section;
@@ -393,6 +394,8 @@ static size_t n_deferred_plabels = 0;
 #define TARGET_DELEGITIMIZE_ADDRESS pa_delegitimize_address
 #undef TARGET_INTERNAL_ARG_POINTER
 #define TARGET_INTERNAL_ARG_POINTER pa_internal_arg_pointer
+#undef TARGET_FRAME_POINTER_REQUIRED
+#define TARGET_FRAME_POINTER_REQUIRED pa_frame_pointer_required
 #undef TARGET_CAN_ELIMINATE
 #define TARGET_CAN_ELIMINATE pa_can_eliminate
 #undef TARGET_CONDITIONAL_REGISTER_USAGE
@@ -11334,4 +11337,17 @@ pa_use_lra_p ()
   return pa_lra_p;
 }
 
+/* Implement TARGET_FRAME_POINTER_REQUIRED.  */
+
+bool
+pa_frame_pointer_required (void)
+{
+  /* If the function receives nonlocal gotos, it needs to save the frame
+ pointer in the argument save area.  */
+  if (cfun->has_nonlocal_label)
+return true;
+
+  return false;
+}
+
 #include "gt-pa.h"

[gcc r15-6267] testsuite: xfail scan-assembler-times in c-c++-common/gomp/unroll-[45].c

2024-12-15 Thread John David Anglin via Gcc-cvs

https://gcc.gnu.org/g:acca546b99e0773355649e276268a7672f273f18

commit r15-6267-gacca546b99e0773355649e276268a7672f273f18
Author: John David Anglin 
Date:   Sun Dec 15 15:53:12 2024 -0500

testsuite: xfail scan-assembler-times in c-c++-common/gomp/unroll-[45].c

Count differs on hppa*-*-hpux* due to hpux specific directives.

2024-12-15  John David Anglin  

gcc/testsuite/ChangeLog:

* c-c++-common/gomp/unroll-4.c: xfail scan-assembler-times
"dummy" for hppa*-*-hpux*.
* c-c++-common/gomp/unroll-5.c: Likewise.

Diff:
---
 gcc/testsuite/c-c++-common/gomp/unroll-4.c | 2 +-
 gcc/testsuite/c-c++-common/gomp/unroll-5.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/gcc/testsuite/c-c++-common/gomp/unroll-4.c 
b/gcc/testsuite/c-c++-common/gomp/unroll-4.c
index 65c51cc0e501..47bdbbc8300f 100644
--- a/gcc/testsuite/c-c++-common/gomp/unroll-4.c
+++ b/gcc/testsuite/c-c++-common/gomp/unroll-4.c
@@ -15,4 +15,4 @@ test1 (void)
 /* { dg-final { scan-tree-dump "#pragma omp unroll" "original" } } */
 /* { dg-final { scan-tree-dump-not "#pragma omp" "gimple" } } */
 /* { dg-final { scan-tree-dump-times "dummy" 1 "gimple" } } */
-/* { dg-final { scan-assembler-times "dummy" 8 } } */
+/* { dg-final { scan-assembler-times "dummy" 8 { xfail hppa*-*-hpux* } } } */
diff --git a/gcc/testsuite/c-c++-common/gomp/unroll-5.c 
b/gcc/testsuite/c-c++-common/gomp/unroll-5.c
index 415d42136a7e..810ac27b230d 100644
--- a/gcc/testsuite/c-c++-common/gomp/unroll-5.c
+++ b/gcc/testsuite/c-c++-common/gomp/unroll-5.c
@@ -15,4 +15,4 @@ test1 (void)
 /* { dg-final { scan-tree-dump "#pragma omp unroll" "original" } } */
 /* { dg-final { scan-tree-dump-not "#pragma omp" "gimple" } } */
 /* { dg-final { scan-tree-dump-times "dummy" 1 "gimple" } } */
-/* { dg-final { scan-assembler-times "dummy" 8 } } */
+/* { dg-final { scan-assembler-times "dummy" 8 { xfail hppa*-*-hpux* } } } */

[gcc r15-6268] testsuite: Enable TImode tests on hppa64

2024-12-15 Thread John David Anglin via Gcc-cvs

https://gcc.gnu.org/g:9573fd7bc8ac5564be5e7fe45358298fc9733067

commit r15-6268-g9573fd7bc8ac5564be5e7fe45358298fc9733067
Author: John David Anglin 
Date:   Sun Dec 15 16:02:54 2024 -0500

testsuite: Enable TImode tests on hppa64

2024-12-15  John David Anglin  

gcc/testsuite/ChangeLog:

* gcc.dg/tree-ssa/ivopts-1.c: Enable TImode tests on hppa64.

Diff:
---
 gcc/testsuite/gcc.dg/tree-ssa/ivopts-1.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/testsuite/gcc.dg/tree-ssa/ivopts-1.c 
b/gcc/testsuite/gcc.dg/tree-ssa/ivopts-1.c
index 5ee87b033b11..ebd5d59b9270 100644
--- a/gcc/testsuite/gcc.dg/tree-ssa/ivopts-1.c
+++ b/gcc/testsuite/gcc.dg/tree-ssa/ivopts-1.c
@@ -1,7 +1,7 @@
 /* { dg-do compile } */
 
 /* Not all platforms support TImode integers.  */
-#if defined(__LP64__) && !defined(__hppa__)
+#if defined(__LP64__)
 typedef int TItype __attribute__ ((mode (TI)));
 #else
 typedef long TItype;

[gcc r15-6182] hppa: Remove extra clobber from divsi3, udivsi3, modsi3 and umodsi3 patterns

2024-12-12 Thread John David Anglin via Gcc-cvs

https://gcc.gnu.org/g:6f7626f7a7a7460158c4d55363df81ca4087000c

commit r15-6182-g6f7626f7a7a7460158c4d55363df81ca4087000c
Author: John David Anglin 
Date:   Thu Dec 12 15:22:22 2024 -0500

hppa: Remove extra clobber from divsi3, udivsi3, modsi3 and umodsi3 patterns

The $$divI, $$divU, $$remI and $$remU millicode calls clobber r1,
r26, r25 and the return link register (r31 or r2).  We don't need
to clobber any other registers.

2024-12-12  John David Anglin  

gcc/ChangeLog:

* config/pa/pa.cc (pa_emit_hpdiv_const): Clobber r1, r25,
r25 and return register.
* config/pa/pa.md (divsi3): Revise clobbers and operands.
Remove second clobber from div:SI insns.
(udivsi3, modsi3, umodsi3): Likewise.

Diff:
---
 gcc/config/pa/pa.cc |  5 ++--
 gcc/config/pa/pa.md | 81 +
 2 files changed, 16 insertions(+), 70 deletions(-)

diff --git a/gcc/config/pa/pa.cc b/gcc/config/pa/pa.cc
index 776cb1ffa24a..99ed2863eb9f 100644
--- a/gcc/config/pa/pa.cc
+++ b/gcc/config/pa/pa.cc
@@ -6159,13 +6159,12 @@ pa_emit_hpdiv_const (rtx *operands, int unsignedp)
   emit
(gen_rtx_PARALLEL
 (VOIDmode,
- gen_rtvec (6, gen_rtx_SET (gen_rtx_REG (SImode, 29),
+ gen_rtvec (5, gen_rtx_SET (gen_rtx_REG (SImode, 29),
 gen_rtx_fmt_ee (unsignedp ? UDIV : DIV,
 SImode,
 gen_rtx_REG (SImode, 26),
 operands[2])),
-gen_rtx_CLOBBER (VOIDmode, operands[4]),
-gen_rtx_CLOBBER (VOIDmode, operands[3]),
+gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 1)),
 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 26)),
 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 25)),
 gen_rtx_CLOBBER (VOIDmode, ret;
diff --git a/gcc/config/pa/pa.md b/gcc/config/pa/pa.md
index 61447c0db5c5..352447272e06 100644
--- a/gcc/config/pa/pa.md
+++ b/gcc/config/pa/pa.md
@@ -5738,27 +5738,16 @@
   [(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
(set (reg:SI 25) (match_operand:SI 2 "move_src_operand" ""))
(parallel [(set (reg:SI 29) (div:SI (reg:SI 26) (reg:SI 25)))
- (clobber (match_dup 3))
- (clobber (match_dup 4))
+ (clobber (reg:SI 1))
  (clobber (reg:SI 26))
  (clobber (reg:SI 25))
- (clobber (match_dup 5))])
+ (clobber (match_dup 3))])
(set (match_operand:SI 0 "move_dest_operand" "") (reg:SI 29))]
   ""
   "
 {
-  operands[3] = gen_reg_rtx (SImode);
-  if (TARGET_64BIT)
-{
-  operands[5] = gen_rtx_REG (SImode, 2);
-  operands[4] = operands[5];
-}
-  else
-{
-  operands[5] = gen_rtx_REG (SImode, 31);
-  operands[4] = gen_reg_rtx (SImode);
-}
-  if (GET_CODE (operands[2]) == CONST_INT && pa_emit_hpdiv_const (operands, 0))
+  operands[3] = gen_rtx_REG (SImode, TARGET_64BIT ? 2 : 31);
+  if (pa_emit_hpdiv_const (operands, 0))
 DONE;
 }")
 
@@ -5766,7 +5755,6 @@
   [(set (reg:SI 29)
(div:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
(clobber (match_operand:SI 1 "register_operand" "=a"))
-   (clobber (match_operand:SI 2 "register_operand" "=&r"))
(clobber (reg:SI 26))
(clobber (reg:SI 25))
(clobber (reg:SI 31))]
@@ -5782,7 +5770,6 @@
   [(set (reg:SI 29)
(div:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
(clobber (match_operand:SI 1 "register_operand" "=a"))
-   (clobber (match_operand:SI 2 "register_operand" "=&r"))
(clobber (reg:SI 26))
(clobber (reg:SI 25))
(clobber (reg:SI 2))]
@@ -5798,28 +5785,16 @@
   [(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
(set (reg:SI 25) (match_operand:SI 2 "move_src_operand" ""))
(parallel [(set (reg:SI 29) (udiv:SI (reg:SI 26) (reg:SI 25)))
- (clobber (match_dup 3))
- (clobber (match_dup 4))
+ (clobber (reg:SI 1))
  (clobber (reg:SI 26))
  (clobber (reg:SI 25))
- (clobber (match_dup 5))])
+ (clobber (match_dup 3))])
(set (match_operand:SI 0 "move_dest_operand" "") (reg:SI 29))]
   ""
   "
 {
-  operands[3] = gen_reg_rtx (SImode);
-
-  if (TARGET_64BIT)
-{
-  operands[5] = gen_rtx_REG (SImode, 2);
-  operands[4] = operands[5];
-}
-  else
-{
-  operands[5] = gen_rtx_REG (SImode, 31);
-  operands[4] = gen_reg_rtx (SImode);
-}
-  if (GET_CODE (operands[2]) == CONST_INT && pa_emit_hpdiv_const (operands, 1))
+  operands[3] = gen_rtx_REG (SImode, TARGET_64BIT ? 2 : 31);
+  if (pa_emit_hpdiv_const (operands, 1))
 DONE;
 }")
 
@@ -5827,7 +5802,6 @@
   [(set (reg:SI 29)
(udiv:SI (reg:SI 26) (match_operand:SI 0 "d

[gcc r15-7167] hppa: Fix typo in ADDITIONAL_REGISTER_NAMES in pa32-regs.h

2025-01-23 Thread John David Anglin via Gcc-cvs

https://gcc.gnu.org/g:ce28eb9f91e39a95a499eea36865e394c2bf614b

commit r15-7167-gce28eb9f91e39a95a499eea36865e394c2bf614b
Author: John David Anglin 
Date:   Thu Jan 23 14:35:22 2025 -0500

hppa: Fix typo in ADDITIONAL_REGISTER_NAMES in pa32-regs.h

2025-01-23  John David Anglin  

gcc/ChangeLog:

* config/pa/pa32-regs.h (ADDITIONAL_REGISTER_NAMES): Change
register 86 name to "%fr31L".

Diff:
---
 gcc/config/pa/pa32-regs.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/config/pa/pa32-regs.h b/gcc/config/pa/pa32-regs.h
index c6fd3bf160b0..b61d0e4749f5 100644
--- a/gcc/config/pa/pa32-regs.h
+++ b/gcc/config/pa/pa32-regs.h
@@ -341,7 +341,7 @@ enum reg_class { NO_REGS, R1_REGS, GENERAL_REGS, 
FPUPPER_REGS, FP_REGS,
  {"%fr16L",56}, {"%fr17L",58}, {"%fr18L",60}, {"%fr19L",62},   \
  {"%fr20L",64}, {"%fr21L",66}, {"%fr22L",68}, {"%fr23L",70},   \
  {"%fr24L",72}, {"%fr25L",74}, {"%fr26L",76}, {"%fr27L",78},   \
- {"%fr28L",80}, {"%fr29L",82}, {"%fr30L",84}, {"%fr31R",86},   \
+ {"%fr28L",80}, {"%fr29L",82}, {"%fr30L",84}, {"%fr31L",86},   \
  {"%cr11",88}}
 
 #define FP_SAVED_REG_LAST 66

[gcc r14-11239] hppa: Fix typo in ADDITIONAL_REGISTER_NAMES in pa32-regs.h

2025-01-23 Thread John David Anglin via Gcc-cvs

https://gcc.gnu.org/g:11abd61656c870ac9af4e44e2ee5c2fba0583ef0

commit r14-11239-g11abd61656c870ac9af4e44e2ee5c2fba0583ef0
Author: John David Anglin 
Date:   Thu Jan 23 14:35:22 2025 -0500

hppa: Fix typo in ADDITIONAL_REGISTER_NAMES in pa32-regs.h

2025-01-23  John David Anglin  

gcc/ChangeLog:

* config/pa/pa32-regs.h (ADDITIONAL_REGISTER_NAMES): Change
register 86 name to "%fr31L".

Diff:
---
 gcc/config/pa/pa32-regs.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/config/pa/pa32-regs.h b/gcc/config/pa/pa32-regs.h
index 6485ab2031e0..6226414cdca0 100644
--- a/gcc/config/pa/pa32-regs.h
+++ b/gcc/config/pa/pa32-regs.h
@@ -344,7 +344,7 @@ enum reg_class { NO_REGS, R1_REGS, GENERAL_REGS, 
FPUPPER_REGS, FP_REGS,
  {"%fr16L",56}, {"%fr17L",58}, {"%fr18L",60}, {"%fr19L",62},   \
  {"%fr20L",64}, {"%fr21L",66}, {"%fr22L",68}, {"%fr23L",70},   \
  {"%fr24L",72}, {"%fr25L",74}, {"%fr26L",76}, {"%fr27L",78},   \
- {"%fr28L",80}, {"%fr29L",82}, {"%fr30L",84}, {"%fr31R",86},   \
+ {"%fr28L",80}, {"%fr29L",82}, {"%fr30L",84}, {"%fr31L",86},   \
  {"%cr11",88}}
 
 #define FP_SAVED_REG_LAST 66

[gcc r12-10927] hppa: Fix typo in ADDITIONAL_REGISTER_NAMES in pa32-regs.h

2025-01-23 Thread John David Anglin via Gcc-cvs

https://gcc.gnu.org/g:40eafb7b58f95a71444d7f4506d9abee54df7de4

commit r12-10927-g40eafb7b58f95a71444d7f4506d9abee54df7de4
Author: John David Anglin 
Date:   Thu Jan 23 14:35:22 2025 -0500

hppa: Fix typo in ADDITIONAL_REGISTER_NAMES in pa32-regs.h

2025-01-23  John David Anglin  

gcc/ChangeLog:

* config/pa/pa32-regs.h (ADDITIONAL_REGISTER_NAMES): Change
register 86 name to "%fr31L".

Diff:
---
 gcc/config/pa/pa32-regs.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/config/pa/pa32-regs.h b/gcc/config/pa/pa32-regs.h
index 62084a50abc9..8199c476d350 100644
--- a/gcc/config/pa/pa32-regs.h
+++ b/gcc/config/pa/pa32-regs.h
@@ -344,7 +344,7 @@ enum reg_class { NO_REGS, R1_REGS, GENERAL_REGS, 
FPUPPER_REGS, FP_REGS,
  {"%fr16L",56}, {"%fr17L",58}, {"%fr18L",60}, {"%fr19L",62},   \
  {"%fr20L",64}, {"%fr21L",66}, {"%fr22L",68}, {"%fr23L",70},   \
  {"%fr24L",72}, {"%fr25L",74}, {"%fr26L",76}, {"%fr27L",78},   \
- {"%fr28L",80}, {"%fr29L",82}, {"%fr30L",84}, {"%fr31R",86},   \
+ {"%fr28L",80}, {"%fr29L",82}, {"%fr30L",84}, {"%fr31L",86},   \
  {"%cr11",88}}
 
 #define FP_SAVED_REG_LAST 66

[gcc r13-9341] hppa: Fix typo in ADDITIONAL_REGISTER_NAMES in pa32-regs.h

2025-01-23 Thread John David Anglin via Gcc-cvs

https://gcc.gnu.org/g:1126e315d9540610a0ec4a9c10c3e9888c05c113

commit r13-9341-g1126e315d9540610a0ec4a9c10c3e9888c05c113
Author: John David Anglin 
Date:   Thu Jan 23 14:35:22 2025 -0500

hppa: Fix typo in ADDITIONAL_REGISTER_NAMES in pa32-regs.h

2025-01-23  John David Anglin  

gcc/ChangeLog:

* config/pa/pa32-regs.h (ADDITIONAL_REGISTER_NAMES): Change
register 86 name to "%fr31L".

Diff:
---
 gcc/config/pa/pa32-regs.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/config/pa/pa32-regs.h b/gcc/config/pa/pa32-regs.h
index 22a4451f2e6d..63e626927c2b 100644
--- a/gcc/config/pa/pa32-regs.h
+++ b/gcc/config/pa/pa32-regs.h
@@ -344,7 +344,7 @@ enum reg_class { NO_REGS, R1_REGS, GENERAL_REGS, 
FPUPPER_REGS, FP_REGS,
  {"%fr16L",56}, {"%fr17L",58}, {"%fr18L",60}, {"%fr19L",62},   \
  {"%fr20L",64}, {"%fr21L",66}, {"%fr22L",68}, {"%fr23L",70},   \
  {"%fr24L",72}, {"%fr25L",74}, {"%fr26L",76}, {"%fr27L",78},   \
- {"%fr28L",80}, {"%fr29L",82}, {"%fr30L",84}, {"%fr31R",86},   \
+ {"%fr28L",80}, {"%fr29L",82}, {"%fr30L",84}, {"%fr31L",86},   \
  {"%cr11",88}}
 
 #define FP_SAVED_REG_LAST 66

[gcc r15-7233] c++: Use mapped reads and writes when munmap and msync are available

2025-01-27 Thread John David Anglin via Gcc-cvs

https://gcc.gnu.org/g:9d450dee7112635a541c5a34268d54f63da48f71

commit r15-7233-g9d450dee7112635a541c5a34268d54f63da48f71
Author: John David Anglin 
Date:   Mon Jan 27 12:39:00 2025 -0500

c++: Use mapped reads and writes when munmap and msync are available

Module support is broken when MAPPED_READING and MAPPED_WRITING
are defined to 0.  This causes internal compiler errors in the
permissive-error-1.C and permissive-error-2.C tests.

HP-UX 11.11 doesn't define _POSIX_MAPPED_FILES but it does have
munmap and msync.  Testing indicates support is sufficient for
c++ modules, so use checks for these functions instead of
_POSIX_MAPPED_FILES check.

2025-01-27  John David Anglin  

gcc/ChangeLog:

PR c++/116524
* configure.ac: Check for munmap and msync.
* configure: Regenerate.
* config.in: Regenerate.

gcc/cp/ChangeLog:
* module.cc: Test HAVE_MUNMAP and HAVE_MSYNC instead of
_POSIX_MAPPED_FILES > 0.

Diff:
---
 gcc/config.in| 12 
 gcc/configure|  2 +-
 gcc/configure.ac |  2 +-
 gcc/cp/module.cc |  6 +++---
 4 files changed, 17 insertions(+), 5 deletions(-)

diff --git a/gcc/config.in b/gcc/config.in
index 44de5a546116..3b06533c4829 100644
--- a/gcc/config.in
+++ b/gcc/config.in
@@ -1972,6 +1972,18 @@
 #endif
 
 
+/* Define to 1 if you have the `msync' function. */
+#ifndef USED_FOR_TARGET
+#undef HAVE_MSYNC
+#endif
+
+
+/* Define to 1 if you have the `munmap' function. */
+#ifndef USED_FOR_TARGET
+#undef HAVE_MUNMAP
+#endif
+
+
 /* Define if GCC has been configured with --enable-newlib-nano-formatted-io.
*/
 #ifndef USED_FOR_TARGET
diff --git a/gcc/configure b/gcc/configure
index b4c52de62184..e36d1d91612a 100755
--- a/gcc/configure
+++ b/gcc/configure
@@ -10637,7 +10637,7 @@ for ac_func in times clock kill getrlimit setrlimit 
atoq \
popen sysconf strsignal getrusage nl_langinfo \
gettimeofday mbstowcs wcswidth mmap posix_fallocate setlocale \
clearerr_unlocked feof_unlocked   ferror_unlocked fflush_unlocked 
fgetc_unlocked fgets_unlocked   fileno_unlocked fprintf_unlocked fputc_unlocked 
fputs_unlocked   fread_unlocked fwrite_unlocked getchar_unlocked getc_unlocked  
 putchar_unlocked putc_unlocked madvise mallinfo mallinfo2 fstatat getauxval \
-   clock_gettime
+   clock_gettime munmap msync
 do :
   as_ac_var=`$as_echo "ac_cv_func_$ac_func" | $as_tr_sh`
 ac_fn_cxx_check_func "$LINENO" "$ac_func" "$as_ac_var"
diff --git a/gcc/configure.ac b/gcc/configure.ac
index 6c38c4925fb3..8fab93c93654 100644
--- a/gcc/configure.ac
+++ b/gcc/configure.ac
@@ -1574,7 +1574,7 @@ AC_CHECK_FUNCS(times clock kill getrlimit setrlimit atoq \
popen sysconf strsignal getrusage nl_langinfo \
gettimeofday mbstowcs wcswidth mmap posix_fallocate setlocale \
gcc_UNLOCKED_FUNCS madvise mallinfo mallinfo2 fstatat getauxval \
-   clock_gettime)
+   clock_gettime munmap msync)
 
 # At least for glibc, clock_gettime is in librt.  But don't pull that
 # in if it still doesn't give us the function we want.
diff --git a/gcc/cp/module.cc b/gcc/cp/module.cc
index 312ff6687508..59716e1873e9 100644
--- a/gcc/cp/module.cc
+++ b/gcc/cp/module.cc
@@ -241,11 +241,11 @@ Classes used:
 #define MAPPED_READING 0
 #define MAPPED_WRITING 0
 #else
-#if HAVE_MMAP_FILE && _POSIX_MAPPED_FILES > 0
-/* mmap, munmap.  */
+#if HAVE_MMAP_FILE && HAVE_MUNMAP && HAVE_MSYNC
+/* mmap, munmap, msync.  */
 #define MAPPED_READING 1
 #if HAVE_SYSCONF && defined (_SC_PAGE_SIZE)
-/* msync, sysconf (_SC_PAGE_SIZE), ftruncate  */
+/* sysconf (_SC_PAGE_SIZE), ftruncate  */
 /* posix_fallocate used if available.  */
 #define MAPPED_WRITING 1
 #else

[gcc r15-6459] Add support to provide libiberty mkstemps in gcc

2024-12-29 Thread John David Anglin via Gcc-cvs

https://gcc.gnu.org/g:9fbf4a6adf6212cfe762c5ade87e6e5066b5b05b

commit r15-6459-g9fbf4a6adf6212cfe762c5ade87e6e5066b5b05b
Author: John David Anglin 
Date:   Sun Dec 29 14:38:09 2024 -0500

Add support to provide libiberty mkstemps in gcc

2024-12-28  John David Anglin  

gcc/ChangeLog:

PR target/118121
* configure.ac: Check for mkstemps declaration.
* configure: Regenerate.
* config.in: Regenerate.

include/ChangeLog:

* libiberty.h (mkstemps): Declare

Diff:
---
 gcc/config.in   | 7 +++
 gcc/configure   | 2 +-
 gcc/configure.ac| 2 +-
 include/libiberty.h | 4 
 4 files changed, 13 insertions(+), 2 deletions(-)

diff --git a/gcc/config.in b/gcc/config.in
index d8145a1453b4..44de5a546116 100644
--- a/gcc/config.in
+++ b/gcc/config.in
@@ -1164,6 +1164,13 @@
 #endif
 
 
+/* Define to 1 if we found a declaration for 'mkstemps', otherwise define to
+   0. */
+#ifndef USED_FOR_TARGET
+#undef HAVE_DECL_MKSTEMPS
+#endif
+
+
 /* Define to 1 if we found a declaration for 'putchar_unlocked', otherwise
define to 0. */
 #ifndef USED_FOR_TARGET
diff --git a/gcc/configure b/gcc/configure
index a8b531d8fae0..a495762724d7 100755
--- a/gcc/configure
+++ b/gcc/configure
@@ -12153,7 +12153,7 @@ _ACEOF
 
 
 for ac_func in getenv atol atoll asprintf sbrk abort atof getcwd getwd \
-   madvise stpcpy strnlen strsignal strverscmp \
+   madvise mkstemps stpcpy strnlen strsignal strverscmp \
strtol strtoul strtoll strtoull setenv unsetenv \
errno snprintf vsnprintf vasprintf malloc realloc calloc \
free getopt clock getpagesize ffs fmemopen clearerr_unlocked 
feof_unlocked   ferror_unlocked fflush_unlocked fgetc_unlocked fgets_unlocked   
fileno_unlocked fprintf_unlocked fputc_unlocked fputs_unlocked   fread_unlocked 
fwrite_unlocked getchar_unlocked getc_unlocked   putchar_unlocked putc_unlocked
diff --git a/gcc/configure.ac b/gcc/configure.ac
index 77fab885a428..5a178e056efb 100644
--- a/gcc/configure.ac
+++ b/gcc/configure.ac
@@ -1652,7 +1652,7 @@ AC_CHECK_DECLS([basename(const char*), strstr(const 
char*,const char*)], , ,[
 #include "system.h"])
 
 gcc_AC_CHECK_DECLS(getenv atol atoll asprintf sbrk abort atof getcwd getwd \
-   madvise stpcpy strnlen strsignal strverscmp \
+   madvise mkstemps stpcpy strnlen strsignal strverscmp \
strtol strtoul strtoll strtoull setenv unsetenv \
errno snprintf vsnprintf vasprintf malloc realloc calloc \
free getopt clock getpagesize ffs fmemopen gcc_UNLOCKED_FUNCS, , ,[
diff --git a/include/libiberty.h b/include/libiberty.h
index 6259d7d54ca6..174fefb3d759 100644
--- a/include/libiberty.h
+++ b/include/libiberty.h
@@ -199,6 +199,10 @@ extern int fdmatch (int fd1, int fd2);
 extern int ffs(int);
 #endif
 
+#if defined (HAVE_DECL_MKSTEMPS) && !HAVE_DECL_MKSTEMPS
+extern int mkstemps(char *, int);
+#endif
+
 /* Get the working directory.  The result is cached, so don't call
chdir() between calls to getpwd().  */

[gcc r15-8089] testsuite: Add -gno-strict-dwarf option to dwarf2 inline[26].c tests

2025-03-17 Thread John David Anglin via Gcc-cvs

https://gcc.gnu.org/g:45f7424ce8961631ee12ba473e3c36d3952d19f2

commit r15-8089-g45f7424ce8961631ee12ba473e3c36d3952d19f2
Author: John David Anglin 
Date:   Mon Mar 17 11:33:01 2025 -0400

testsuite: Add -gno-strict-dwarf option to dwarf2 inline[26].c tests

Some targets default to strict dwarf.

2025-03-17  John David Anglin  

gcc/testsuite/ChangeLog:

PR testsuite/119220
* gcc.dg/debug/dwarf2/inline2.c: Add -gno-strict-dwarf option.
* gcc.dg/debug/dwarf2/inline6.c: Likewise.

Diff:
---
 gcc/testsuite/gcc.dg/debug/dwarf2/inline2.c | 2 +-
 gcc/testsuite/gcc.dg/debug/dwarf2/inline6.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/gcc/testsuite/gcc.dg/debug/dwarf2/inline2.c 
b/gcc/testsuite/gcc.dg/debug/dwarf2/inline2.c
index 6893ddfa2ebe..f5d7e4efd161 100644
--- a/gcc/testsuite/gcc.dg/debug/dwarf2/inline2.c
+++ b/gcc/testsuite/gcc.dg/debug/dwarf2/inline2.c
@@ -16,7 +16,7 @@
 
 /* Explicitly use dwarf-2 because dwarf-5 might use DW_FORM_implicit_const
which is hard to scan for. */
-/* { dg-options "-O -g3 -gdwarf-2 -dA -fgnu89-inline" } */
+/* { dg-options "-O -g3 -gdwarf-2 -gno-strict-dwarf -dA -fgnu89-inline" } */
 /* { dg-do compile } */
 
 /* There are 6 inlined subroutines:
diff --git a/gcc/testsuite/gcc.dg/debug/dwarf2/inline6.c 
b/gcc/testsuite/gcc.dg/debug/dwarf2/inline6.c
index d7c86f89895c..f271ebbcc803 100644
--- a/gcc/testsuite/gcc.dg/debug/dwarf2/inline6.c
+++ b/gcc/testsuite/gcc.dg/debug/dwarf2/inline6.c
@@ -16,7 +16,7 @@
 
 /* Explicitly use dwarf-5 which uses DW_FORM_implicit_const.  */
 /* { dg-do compile } */
-/* { dg-options "-O -g3 -gdwarf-5 -dA -fgnu89-inline -gno-as-loc-support" } */
+/* { dg-options "-O -g3 -gdwarf-5 -gno-strict-dwarf -dA -fgnu89-inline 
-gno-as-loc-support" } */
 
 /* There are 6 inlined subroutines:
- One for each subroutine inlined into main, that's 3.

[gcc r15-9360] hpux: Remove _GLIBCXX_USE_LONG_LONG define from hpux os_defines.h

2025-04-10 Thread John David Anglin via Gcc-cvs

https://gcc.gnu.org/g:a5a7233dfcee5eb20ed4853c8a1f3cbebe352a7b

commit r15-9360-ga5a7233dfcee5eb20ed4853c8a1f3cbebe352a7b
Author: John David Anglin 
Date:   Thu Apr 10 09:59:01 2025 -0400

hpux: Remove _GLIBCXX_USE_LONG_LONG define from hpux os_defines.h

_GLIBCXX_USE_LONG_LONG is now defined by configure.

2025-04-05  John David Anglin  

libstdc++-v3/ChangeLog:
* config/os/hpux/os_defines.h: Remove _GLIBCXX_USE_LONG_LONG
define.

Diff:
---
 libstdc++-v3/config/os/hpux/os_defines.h | 7 +--
 1 file changed, 1 insertion(+), 6 deletions(-)

diff --git a/libstdc++-v3/config/os/hpux/os_defines.h 
b/libstdc++-v3/config/os/hpux/os_defines.h
index d3a6c5ab1426..acc1a022bdec 100644
--- a/libstdc++-v3/config/os/hpux/os_defines.h
+++ b/libstdc++-v3/config/os/hpux/os_defines.h
@@ -52,10 +52,7 @@
 
Also note that the compiler defines _INCLUDE_LONGLONG for C++
unconditionally, which makes intmax_t and uintmax_t long long
-   types.
-
-   We also force _GLIBCXX_USE_LONG_LONG here so that we don't have
-   to bastardize configure to deal with this sillyness.  */
+   types.  */
 
 #if __cplusplus >= 201103L
 namespace std
@@ -77,8 +74,6 @@ namespace std
 } // namespace std
 #endif // __cplusplus
 
-#define _GLIBCXX_USE_LONG_LONG 1
-
 // HPUX on IA64 requires vtable to be 64 bit aligned even at 32 bit
 // mode.  We need to pad the vtable structure to achieve this.
 #if !defined(_LP64) && defined (__ia64__)

[gcc r15-9361] libbacktrace: Add hpux fileline support

2025-04-10 Thread John David Anglin via Gcc-cvs

https://gcc.gnu.org/g:911973a784aab34e13c683545f28177d0d7716cd

commit r15-9361-g911973a784aab34e13c683545f28177d0d7716cd
Author: John David Anglin 
Date:   Thu Apr 10 10:00:13 2025 -0400

libbacktrace: Add hpux fileline support

Fixes libstdc++ stacktrace tests.

2025-04-10  John David Anglin  

libbacktrace/ChangeLog:
* fileline.c (hpux_get_executable_path): New.
(fileline_initialize): Add pass to get hpux executable path.

Diff:
---
 libbacktrace/fileline.c | 36 +++-
 1 file changed, 35 insertions(+), 1 deletion(-)

diff --git a/libbacktrace/fileline.c b/libbacktrace/fileline.c
index c9fd86b8c0cd..d2900aa3c66b 100644
--- a/libbacktrace/fileline.c
+++ b/libbacktrace/fileline.c
@@ -47,6 +47,10 @@ POSSIBILITY OF SUCH DAMAGE.  */
 #include 
 #endif
 
+#ifdef __hpux__
+#include 
+#endif
+
 #ifdef HAVE_WINDOWS_H
 #ifndef WIN32_LEAN_AND_MEAN
 #define WIN32_LEAN_AND_MEAN
@@ -66,6 +70,33 @@ POSSIBILITY OF SUCH DAMAGE.  */
 #define getexecname() NULL
 #endif
 
+#ifdef __hpux__
+static char *
+hpux_get_executable_path (struct backtrace_state *state,
+ backtrace_error_callback error_callback, void *data)
+{
+  struct shl_descriptor *desc;
+  size_t len = sizeof (struct shl_descriptor);
+
+  desc = backtrace_alloc (state, len, error_callback, data);
+  if (desc == NULL)
+return NULL;
+
+  if (shl_get_r (0, desc) == -1)
+{
+  backtrace_free (state, desc, len, error_callback, data);
+  return NULL;
+}
+
+  return desc->filename;
+}
+
+#else
+
+#define hpux_get_executable_path(state, error_callback, data) NULL
+
+#endif
+
 #if !defined (HAVE_KERN_PROC_ARGS) && !defined (HAVE_KERN_PROC)
 
 #define sysctl_exec_name1(state, error_callback, data) NULL
@@ -245,7 +276,7 @@ fileline_initialize (struct backtrace_state *state,
 
   descriptor = -1;
   called_error_callback = 0;
-  for (pass = 0; pass < 10; ++pass)
+  for (pass = 0; pass < 11; ++pass)
 {
   int does_not_exist;
 
@@ -285,6 +316,9 @@ fileline_initialize (struct backtrace_state *state,
case 9:
  filename = windows_get_executable_path (buf, error_callback, data);
  break;
+   case 10:
+ filename = hpux_get_executable_path (state, error_callback, data);
+ break;
default:
  abort ();
}

[gcc r12-11062] Fix compilation of server.cc on hpux.

2025-04-20 Thread John David Anglin via Gcc-cvs

https://gcc.gnu.org/g:3ea4b96173db521366cd5d62c125d4cb6c8f6065

commit r12-11062-g3ea4b96173db521366cd5d62c125d4cb6c8f6065
Author: John David Anglin 
Date:   Mon Jan 9 15:41:51 2023 +

Fix compilation of server.cc on hpux.

Select and FD_ISSET are declared in sys/time.h on most versions
of hpux.  As a result, HAVE_PSELECT and HAVE_SELECT can be 0.

2023-01-08  John David Anglin  

c++tools/ChangeLog:

PR other/107616
* server.cc (server): Don't call FD_ISSET when HAVE_PSELECT
and HAVE_SELECT are zero.

Diff:
---
 c++tools/server.cc | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/c++tools/server.cc b/c++tools/server.cc
index 00154a05925d..693aec6820a5 100644
--- a/c++tools/server.cc
+++ b/c++tools/server.cc
@@ -753,8 +753,10 @@ server (bool ipv6, int sock_fd, module_resolver *resolver)
  }
  }
 
+#if defined (HAVE_PSELECT) || defined (HAVE_SELECT)
  if (active < 0 && sock_fd >= 0 && FD_ISSET (sock_fd, &readers))
active = -1;
+#endif
}
 
  if (active >= 0)

[gcc r16-388] testsuite: Link gcc.dg/lto/modref-2_0 with libm

2025-05-05 Thread John David Anglin via Gcc-cvs

https://gcc.gnu.org/g:7fae8dca82abf714a055ff505df51a4c8b43c211

commit r16-388-g7fae8dca82abf714a055ff505df51a4c8b43c211
Author: John David Anglin 
Date:   Mon May 5 09:30:45 2025 -0400

testsuite: Link gcc.dg/lto/modref-2_0 with libm

2025-05-05  John David Anglin  

gcc/testsuite/ChangeLog:

PR testsuite/120085
* gcc.dg/lto/modref-2_0.c: Link test with libm.

Diff:
---
 gcc/testsuite/gcc.dg/lto/modref-2_0.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/gcc/testsuite/gcc.dg/lto/modref-2_0.c 
b/gcc/testsuite/gcc.dg/lto/modref-2_0.c
index cf84ed95e775..bba4c8df95ea 100644
--- a/gcc/testsuite/gcc.dg/lto/modref-2_0.c
+++ b/gcc/testsuite/gcc.dg/lto/modref-2_0.c
@@ -1,5 +1,6 @@
 /* { dg-lto-do run } */
 /* { dg-lto-options {"-O2 -flto-partition=max -flto -fno-ipa-sra"}  } */
+/* { dg-extra-ld-options { -lm } } */
 __attribute__ ((noinline))
 void
 test (char *a)

[gcc r13-9632] Enable generation of GNU stack notes on Linux

2025-05-05 Thread John David Anglin via Gcc-cvs

https://gcc.gnu.org/g:10b8d94e7f45608dd896c7a780370136ed975c6f

commit r13-9632-g10b8d94e7f45608dd896c7a780370136ed975c6f
Author: John David Anglin 
Date:   Mon Nov 6 20:33:15 2023 +

Enable generation of GNU stack notes on Linux

2023-11-06  John David Anglin  

* config/pa/pa-linux.h (NEED_INDICATE_EXEC_STACK): Define to 1.

Diff:
---
 gcc/config/pa/pa-linux.h | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/gcc/config/pa/pa-linux.h b/gcc/config/pa/pa-linux.h
index d38f68b1fa54..96c54765ddb9 100644
--- a/gcc/config/pa/pa-linux.h
+++ b/gcc/config/pa/pa-linux.h
@@ -144,8 +144,7 @@ along with GCC; see the file COPYING3.  If not see
 #define HAVE_sync_compare_and_swapsi 1
 #define HAVE_sync_compare_and_swapdi 1
 
-/* It's not possible to enable GNU_stack notes since the kernel needs
-   an executable stack for signal returns and syscall restarts.  */
+/* Enable GNU stack notes.  */
 
 #undef NEED_INDICATE_EXEC_STACK
-#define NEED_INDICATE_EXEC_STACK 0
+#define NEED_INDICATE_EXEC_STACK 1

[gcc r12-11087] Enable generation of GNU stack notes on Linux

2025-05-05 Thread John David Anglin via Gcc-cvs

https://gcc.gnu.org/g:8b26ee407613cdbfc3fb2095c09ae28b4642fd63

commit r12-11087-g8b26ee407613cdbfc3fb2095c09ae28b4642fd63
Author: John David Anglin 
Date:   Mon Nov 6 20:33:15 2023 +

Enable generation of GNU stack notes on Linux

2023-11-06  John David Anglin  

* config/pa/pa-linux.h (NEED_INDICATE_EXEC_STACK): Define to 1.

Diff:
---
 gcc/config/pa/pa-linux.h | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/gcc/config/pa/pa-linux.h b/gcc/config/pa/pa-linux.h
index 5af11a1df804..f467d3acbb99 100644
--- a/gcc/config/pa/pa-linux.h
+++ b/gcc/config/pa/pa-linux.h
@@ -147,8 +147,7 @@ along with GCC; see the file COPYING3.  If not see
 #define HAVE_sync_compare_and_swapsi 1
 #define HAVE_sync_compare_and_swapdi 1
 
-/* It's not possible to enable GNU_stack notes since the kernel needs
-   an executable stack for signal returns and syscall restarts.  */
+/* Enable GNU stack notes.  */
 
 #undef NEED_INDICATE_EXEC_STACK
-#define NEED_INDICATE_EXEC_STACK 0
+#define NEED_INDICATE_EXEC_STACK 1

[gcc r14-11685] libbacktrace: Add hpux fileline support

2025-04-25 Thread John David Anglin via Gcc-cvs

https://gcc.gnu.org/g:57f930fa9774ab3ec7479fc85d70135df271a8b0

commit r14-11685-g57f930fa9774ab3ec7479fc85d70135df271a8b0
Author: John David Anglin 
Date:   Thu Apr 10 10:00:13 2025 -0400

libbacktrace: Add hpux fileline support

Fixes libstdc++ stacktrace tests.

2025-04-10  John David Anglin  

libbacktrace/ChangeLog:
* fileline.c (hpux_get_executable_path): New.
(fileline_initialize): Add pass to get hpux executable path.

Diff:
---
 libbacktrace/fileline.c | 36 +++-
 1 file changed, 35 insertions(+), 1 deletion(-)

diff --git a/libbacktrace/fileline.c b/libbacktrace/fileline.c
index 68e80c6d2742..767e08e87b89 100644
--- a/libbacktrace/fileline.c
+++ b/libbacktrace/fileline.c
@@ -47,6 +47,10 @@ POSSIBILITY OF SUCH DAMAGE.  */
 #include 
 #endif
 
+#ifdef __hpux__
+#include 
+#endif
+
 #ifdef HAVE_WINDOWS_H
 #ifndef WIN32_MEAN_AND_LEAN
 #define WIN32_MEAN_AND_LEAN
@@ -66,6 +70,33 @@ POSSIBILITY OF SUCH DAMAGE.  */
 #define getexecname() NULL
 #endif
 
+#ifdef __hpux__
+static char *
+hpux_get_executable_path (struct backtrace_state *state,
+ backtrace_error_callback error_callback, void *data)
+{
+  struct shl_descriptor *desc;
+  size_t len = sizeof (struct shl_descriptor);
+
+  desc = backtrace_alloc (state, len, error_callback, data);
+  if (desc == NULL)
+return NULL;
+
+  if (shl_get_r (0, desc) == -1)
+{
+  backtrace_free (state, desc, len, error_callback, data);
+  return NULL;
+}
+
+  return desc->filename;
+}
+
+#else
+
+#define hpux_get_executable_path(state, error_callback, data) NULL
+
+#endif
+
 #if !defined (HAVE_KERN_PROC_ARGS) && !defined (HAVE_KERN_PROC)
 
 #define sysctl_exec_name1(state, error_callback, data) NULL
@@ -245,7 +276,7 @@ fileline_initialize (struct backtrace_state *state,
 
   descriptor = -1;
   called_error_callback = 0;
-  for (pass = 0; pass < 10; ++pass)
+  for (pass = 0; pass < 11; ++pass)
 {
   int does_not_exist;
 
@@ -285,6 +316,9 @@ fileline_initialize (struct backtrace_state *state,
case 9:
  filename = windows_get_executable_path (buf, error_callback, data);
  break;
+   case 10:
+ filename = hpux_get_executable_path (state, error_callback, data);
+ break;
default:
  abort ();
}

[gcc r15-7607] testsuite: Include stdint.h instead of stdint-gcc.h in some tests

2025-02-18 Thread John David Anglin via Gcc-cvs

https://gcc.gnu.org/g:8c03fbd77654713b3bc90ebada3f880f9dd06bf7

commit r15-7607-g8c03fbd77654713b3bc90ebada3f880f9dd06bf7
Author: John David Anglin 
Date:   Tue Feb 18 10:36:48 2025 -0500

testsuite: Include stdint.h instead of stdint-gcc.h in some tests

When use_gcc_stdint=provide, the stdint-gcc.h header is not provided.

2025-02-18  John David Anglin  

gcc/testsuite/ChangeLog:

PR testsuite/116986
* gcc.dg/crc-builtin-rev-target32.c: Include stdint.h
instead of stdint-gcc.h.
* gcc.dg/crc-builtin-rev-target64.c: Likewise.
* gcc.dg/crc-builtin-target32.c: Likewise.
* gcc.dg/crc-builtin-target64.c: Likewise.
* gcc.dg/torture/pr115387-2.c: Likewise.

Diff:
---
 gcc/testsuite/gcc.dg/crc-builtin-rev-target32.c | 2 +-
 gcc/testsuite/gcc.dg/crc-builtin-rev-target64.c | 2 +-
 gcc/testsuite/gcc.dg/crc-builtin-target32.c | 2 +-
 gcc/testsuite/gcc.dg/crc-builtin-target64.c | 2 +-
 gcc/testsuite/gcc.dg/torture/pr115387-2.c   | 2 +-
 5 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/gcc/testsuite/gcc.dg/crc-builtin-rev-target32.c 
b/gcc/testsuite/gcc.dg/crc-builtin-rev-target32.c
index 4fc58e5f5137..f2b63db7fd13 100644
--- a/gcc/testsuite/gcc.dg/crc-builtin-rev-target32.c
+++ b/gcc/testsuite/gcc.dg/crc-builtin-rev-target32.c
@@ -2,7 +2,7 @@
 /* { dg-require-effective-target int32plus } */
 /* { dg-additional-options "-fdump-rtl-expand-details" } */
 
-#include 
+#include 
 
 int8_t rev_crc8_data8 ()
 {
diff --git a/gcc/testsuite/gcc.dg/crc-builtin-rev-target64.c 
b/gcc/testsuite/gcc.dg/crc-builtin-rev-target64.c
index d63981e01018..97e80004d377 100644
--- a/gcc/testsuite/gcc.dg/crc-builtin-rev-target64.c
+++ b/gcc/testsuite/gcc.dg/crc-builtin-rev-target64.c
@@ -2,7 +2,7 @@
 /* { dg-require-effective-target int32plus } */
 /* { dg-additional-options "-fdump-rtl-expand-details" } */
 
-#include 
+#include 
 
 int8_t rev_crc8_data8 ()
 {
diff --git a/gcc/testsuite/gcc.dg/crc-builtin-target32.c 
b/gcc/testsuite/gcc.dg/crc-builtin-target32.c
index 13db531e93a3..43db8c96e16e 100644
--- a/gcc/testsuite/gcc.dg/crc-builtin-target32.c
+++ b/gcc/testsuite/gcc.dg/crc-builtin-target32.c
@@ -2,7 +2,7 @@
 /* { dg-require-effective-target int32plus } */
 /* { dg-additional-options "-fdump-rtl-expand-details" } */
 
-#include 
+#include 
 
 int8_t crc8_data8 ()
 {
diff --git a/gcc/testsuite/gcc.dg/crc-builtin-target64.c 
b/gcc/testsuite/gcc.dg/crc-builtin-target64.c
index 4b3d813995a1..09aa39fcd86a 100644
--- a/gcc/testsuite/gcc.dg/crc-builtin-target64.c
+++ b/gcc/testsuite/gcc.dg/crc-builtin-target64.c
@@ -2,7 +2,7 @@
 /* { dg-require-effective-target int32plus } */
 /* { dg-additional-options "-fdump-rtl-expand-details" } */
 
-#include 
+#include 
 
 int8_t crc8_data8 ()
 {
diff --git a/gcc/testsuite/gcc.dg/torture/pr115387-2.c 
b/gcc/testsuite/gcc.dg/torture/pr115387-2.c
index 9e93024b45ce..190ad4b09772 100644
--- a/gcc/testsuite/gcc.dg/torture/pr115387-2.c
+++ b/gcc/testsuite/gcc.dg/torture/pr115387-2.c
@@ -2,7 +2,7 @@
 /* { dg-do compile } */
 
 #include 
-#include 
+#include 
 
 char *
 test (char *string, size_t maxlen)

[gcc r15-9159] xfail __tcf_ZL1b assembler check on hppa--hpux* in g++.dg/modules/pr98893_b.C

2025-04-02 Thread John David Anglin via Gcc-cvs

https://gcc.gnu.org/g:3b00f8b56c1b92356da81c0d80ab40da2075d536

commit r15-9159-g3b00f8b56c1b92356da81c0d80ab40da2075d536
Author: John David Anglin 
Date:   Wed Apr 2 15:06:38 2025 -0400

xfail __tcf_ZL1b assembler check on hppa*-*-hpux* in 
g++.dg/modules/pr98893_b.C

2025-04-02  John David Anglin  

gcc/testsuite/ChangeLog:

* g++.dg/modules/pr98893_b.C: xfail __tcf_ZL1b
assembler check on hppa*-*-hpux*.

Diff:
---
 gcc/testsuite/g++.dg/modules/pr98893_b.C | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/testsuite/g++.dg/modules/pr98893_b.C 
b/gcc/testsuite/g++.dg/modules/pr98893_b.C
index 9065589bdfbf..692eafb0afdc 100644
--- a/gcc/testsuite/g++.dg/modules/pr98893_b.C
+++ b/gcc/testsuite/g++.dg/modules/pr98893_b.C
@@ -7,4 +7,4 @@ int main() {
 }
 
 // { dg-final { scan-assembler {__tcf_ZZ3foovE1a:} } }
-// { dg-final { scan-assembler {__tcf_ZL1b:} } }
+// { dg-final { scan-assembler {__tcf_ZL1b:} { xfail hppa*-*-hpux* } } }

[gcc r15-9157] hpux: Only use long long when __cplusplus >= 201103L

2025-04-02 Thread John David Anglin via Gcc-cvs

https://gcc.gnu.org/g:6d18be71d3c164dfc8a2aa0f53a15b2ec2af2182

commit r15-9157-g6d18be71d3c164dfc8a2aa0f53a15b2ec2af2182
Author: John David Anglin 
Date:   Wed Apr 2 14:50:53 2025 -0400

hpux: Only use long long when __cplusplus >= 201103L

2025-04-02  John David Anglin  

libstdc++-v3/ChangeLog:
* config/os/hpux/os_defines.h: Only use long long when
__cplusplus >= 201103L.

Diff:
---
 libstdc++-v3/config/os/hpux/os_defines.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/libstdc++-v3/config/os/hpux/os_defines.h 
b/libstdc++-v3/config/os/hpux/os_defines.h
index 30bd4c7ba14d..d3a6c5ab1426 100644
--- a/libstdc++-v3/config/os/hpux/os_defines.h
+++ b/libstdc++-v3/config/os/hpux/os_defines.h
@@ -57,7 +57,7 @@
We also force _GLIBCXX_USE_LONG_LONG here so that we don't have
to bastardize configure to deal with this sillyness.  */
 
-#ifdef __cplusplus
+#if __cplusplus >= 201103L
 namespace std
 {
   extern "C"

[gcc r15-9158] Skip g++.dg/abi/abi-tag18a.C on hppa--hpux*

2025-04-02 Thread John David Anglin via Gcc-cvs

https://gcc.gnu.org/g:aeca210ecfb97ae7f3d0de69276ec77b65ea34e9

commit r15-9158-gaeca210ecfb97ae7f3d0de69276ec77b65ea34e9
Author: John David Anglin 
Date:   Wed Apr 2 14:58:01 2025 -0400

Skip g++.dg/abi/abi-tag18a.C on hppa*-*-hpux*

2025-04-02  John David Anglin  

gcc/testsuite/ChangeLog:

* g++.dg/abi/abi-tag18a.C: Skip on hppa*-*-hpux*.

Diff:
---
 gcc/testsuite/g++.dg/abi/abi-tag18a.C | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/testsuite/g++.dg/abi/abi-tag18a.C 
b/gcc/testsuite/g++.dg/abi/abi-tag18a.C
index c6fb1607a418..392abf78062a 100644
--- a/gcc/testsuite/g++.dg/abi/abi-tag18a.C
+++ b/gcc/testsuite/g++.dg/abi/abi-tag18a.C
@@ -1,4 +1,4 @@
-// { dg-skip-if "PR 70349" { hppa*-*-hpux* && { ! lp64 } } }
+// { dg-skip-if "PR 70349" { hppa*-*-hpux* } }
 // { dg-options "-fabi-version=9 -fno-implicit-constexpr" }
 // { dg-final { scan-assembler "_Z1fB7__test1v" } }
 // { dg-final { scan-assembler "_ZZ1fB7__test1vEN1T1gB7__test2Ev" } }

[gcc r16-739] hpux: Fix detection of atomic support when profiling

2025-05-19 Thread John David Anglin via Gcc-cvs

https://gcc.gnu.org/g:23a8659a3e3a1877f70d196ae498a76d0fd2783c

commit r16-739-g23a8659a3e3a1877f70d196ae498a76d0fd2783c
Author: John David Anglin 
Date:   Mon May 19 17:28:00 2025 -0400

hpux: Fix detection of atomic support when profiling

The pa target lacks atomic sync compare and swap instructions.
These are implemented as libcalls and in libatomic.  As on linux,
we lie about their availability.

This fixes the gcov-30.c test on hppa64-hpux11.

2025-05-19  John David Anglin  

gcc/ChangeLog:

* config/pa/pa-hpux.h (TARGET_HAVE_LIBATOMIC): Define.
(HAVE_sync_compare_and_swapqi): Likewise.
(HAVE_sync_compare_and_swaphi): Likewise.
(HAVE_sync_compare_and_swapsi): Likewise.
(HAVE_sync_compare_and_swapdi): Likewise.

Diff:
---
 gcc/config/pa/pa-hpux.h | 14 ++
 1 file changed, 14 insertions(+)

diff --git a/gcc/config/pa/pa-hpux.h b/gcc/config/pa/pa-hpux.h
index 74e30eda9b5c..1439447fdbed 100644
--- a/gcc/config/pa/pa-hpux.h
+++ b/gcc/config/pa/pa-hpux.h
@@ -114,3 +114,17 @@ along with GCC; see the file COPYING3.  If not see
 
 #undef TARGET_LIBC_HAS_FUNCTION
 #define TARGET_LIBC_HAS_FUNCTION no_c99_libc_has_function
+
+/* Assume we have libatomic if sync libcalls are disabled.  */
+#undef TARGET_HAVE_LIBATOMIC
+#define TARGET_HAVE_LIBATOMIC (!flag_sync_libcalls)
+
+/* The SYNC operations are implemented as library functions, not
+   INSN patterns.  As a result, the HAVE defines for the patterns are
+   not defined.  We need to define them to generate the corresponding
+   __GCC_HAVE_SYNC_COMPARE_AND_SWAP_* and __GCC_ATOMIC_*_LOCK_FREE
+   defines.  */
+#define HAVE_sync_compare_and_swapqi (flag_sync_libcalls)
+#define HAVE_sync_compare_and_swaphi (flag_sync_libcalls)
+#define HAVE_sync_compare_and_swapsi (flag_sync_libcalls)
+#define HAVE_sync_compare_and_swapdi (flag_sync_libcalls)

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