[gcc r15-3044] RISC-V: Remove testcase XFAIL
https://gcc.gnu.org/g:3676816caa510de226b357be1c68cf798da63576
commit r15-3044-g3676816caa510de226b357be1c68cf798da63576
Author: Edwin Lu
Date: Mon Aug 19 13:10:15 2024 -0700
RISC-V: Remove testcase XFAIL
The testcase has been modified to include the -fwrapv flag which now
causes the test to pass. Remove the xfail exception
gcc/testsuite/ChangeLog:
* gcc.dg/signbit-5.c: Remove riscv xfail exception
Signed-off-by: Edwin Lu
Diff:
---
gcc/testsuite/gcc.dg/signbit-5.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/gcc/testsuite/gcc.dg/signbit-5.c b/gcc/testsuite/gcc.dg/signbit-5.c
index 2bca640f930b..e65c8910c825 100644
--- a/gcc/testsuite/gcc.dg/signbit-5.c
+++ b/gcc/testsuite/gcc.dg/signbit-5.c
@@ -4,7 +4,6 @@
/* This test does not work when the truth type does not match vector type. */
/* { dg-additional-options "-march=armv8-a" { target aarch64_sve } } */
/* { dg-xfail-run-if "truth type does not match vector type" { amdgcn-*-* } }
*/
-/* { dg-xfail-run-if "truth type does not match vector type" { riscv_v } } */
#include
[gcc r15-1948] RISC-V: Add support for B standard extension
https://gcc.gnu.org/g:2a90c41a131080e5fdd2b5554fcdba5c654cb93f
commit r15-1948-g2a90c41a131080e5fdd2b5554fcdba5c654cb93f
Author: Edwin Lu
Date: Wed Jul 10 09:44:48 2024 -0700
RISC-V: Add support for B standard extension
This patch adds support for recognizing the B standard extension to be the
collection of Zba, Zbb, Zbs extensions for consistency and conciseness
across toolchains
https://github.com/riscv/riscv-b/tags
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: Add imply rules for B
extension
* config/riscv/arch-canonicalize: Ditto
Signed-off-by: Edwin Lu
Diff:
---
gcc/common/config/riscv/riscv-common.cc | 7 +++
gcc/config/riscv/arch-canonicalize | 1 +
2 files changed, 8 insertions(+)
diff --git a/gcc/common/config/riscv/riscv-common.cc
b/gcc/common/config/riscv/riscv-common.cc
index dab2e7679653..b0a16f5bd30f 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -84,6 +84,10 @@ static const riscv_implied_info_t riscv_implied_info[] =
{"zabha", "zaamo"},
+ {"b", "zba"},
+ {"b", "zbb"},
+ {"b", "zbs"},
+
{"zdinx", "zfinx"},
{"zfinx", "zicsr"},
{"zdinx", "zicsr"},
@@ -245,6 +249,8 @@ static const struct riscv_ext_version
riscv_ext_version_table[] =
{"c", ISA_SPEC_CLASS_20190608, 2, 0},
{"c", ISA_SPEC_CLASS_2P2, 2, 0},
+ {"b", ISA_SPEC_CLASS_NONE, 1, 0},
+
{"h", ISA_SPEC_CLASS_NONE, 1, 0},
{"v", ISA_SPEC_CLASS_NONE, 1, 0},
@@ -405,6 +411,7 @@ static const struct riscv_ext_version
riscv_ext_version_table[] =
static const struct riscv_ext_version riscv_combine_info[] =
{
{"a", ISA_SPEC_CLASS_20191213, 2, 1},
+ {"b", ISA_SPEC_CLASS_NONE, 1, 0},
{"zk", ISA_SPEC_CLASS_NONE, 1, 0},
{"zkn", ISA_SPEC_CLASS_NONE, 1, 0},
{"zks", ISA_SPEC_CLASS_NONE, 1, 0},
diff --git a/gcc/config/riscv/arch-canonicalize
b/gcc/config/riscv/arch-canonicalize
index 35a7fe4455a6..2ea514dd9869 100755
--- a/gcc/config/riscv/arch-canonicalize
+++ b/gcc/config/riscv/arch-canonicalize
@@ -45,6 +45,7 @@ IMPLIED_EXT = {
"zabha" : ["zaamo"],
"f" : ["zicsr"],
+ "b" : ["zba", "zbb", "zbs"],
"zdinx" : ["zfinx", "zicsr"],
"zfinx" : ["zicsr"],
"zhinx" : ["zhinxmin", "zfinx", "zicsr"],
[gcc r15-1949] RISC-V: Update testsuite to use b
https://gcc.gnu.org/g:04df2a924bba38c271bfe4ed0e94af1877413818
commit r15-1949-g04df2a924bba38c271bfe4ed0e94af1877413818
Author: Edwin Lu
Date: Wed Jul 3 17:17:27 2024 -0700
RISC-V: Update testsuite to use b
Update all instances of zba_zbb_zbs in the testsuite to use b instead
gcc/testsuite/ChangeLog:
* g++.target/riscv/redundant-bitmap-1.C: Use gcb instead of
zba_zbb_zbs
* g++.target/riscv/redundant-bitmap-2.C: Ditto
* g++.target/riscv/redundant-bitmap-3.C: Ditto
* g++.target/riscv/redundant-bitmap-4.C: Ditto
* gcc.target/riscv/shift-add-1.c: Ditto
* gcc.target/riscv/shift-add-2.c: Ditto
* gcc.target/riscv/synthesis-1.c: Ditto
* gcc.target/riscv/synthesis-2.c: Ditto
* gcc.target/riscv/synthesis-3.c: Ditto
* gcc.target/riscv/synthesis-4.c: Ditto
* gcc.target/riscv/synthesis-5.c: Ditto
* gcc.target/riscv/synthesis-6.c: Ditto
* gcc.target/riscv/synthesis-7.c: Ditto
* gcc.target/riscv/synthesis-8.c: Ditto
* gcc.target/riscv/zba_zbs_and-1.c: Ditto
* gcc.target/riscv/zbs-zext-3.c: Ditto
* lib/target-supports.exp: Add b to riscv_get_arch
Signed-off-by: Edwin Lu
Diff:
---
gcc/testsuite/g++.target/riscv/redundant-bitmap-1.C | 2 +-
gcc/testsuite/g++.target/riscv/redundant-bitmap-2.C | 2 +-
gcc/testsuite/g++.target/riscv/redundant-bitmap-3.C | 2 +-
gcc/testsuite/g++.target/riscv/redundant-bitmap-4.C | 2 +-
gcc/testsuite/gcc.target/riscv/shift-add-1.c| 2 +-
gcc/testsuite/gcc.target/riscv/shift-add-2.c| 2 +-
gcc/testsuite/gcc.target/riscv/synthesis-1.c| 2 +-
gcc/testsuite/gcc.target/riscv/synthesis-2.c| 2 +-
gcc/testsuite/gcc.target/riscv/synthesis-3.c| 2 +-
gcc/testsuite/gcc.target/riscv/synthesis-4.c| 2 +-
gcc/testsuite/gcc.target/riscv/synthesis-5.c| 2 +-
gcc/testsuite/gcc.target/riscv/synthesis-6.c| 2 +-
gcc/testsuite/gcc.target/riscv/synthesis-7.c| 2 +-
gcc/testsuite/gcc.target/riscv/synthesis-8.c| 2 +-
gcc/testsuite/gcc.target/riscv/zba_zbs_and-1.c | 2 +-
gcc/testsuite/gcc.target/riscv/zbs-zext-3.c | 4 ++--
gcc/testsuite/lib/target-supports.exp | 2 +-
17 files changed, 18 insertions(+), 18 deletions(-)
diff --git a/gcc/testsuite/g++.target/riscv/redundant-bitmap-1.C
b/gcc/testsuite/g++.target/riscv/redundant-bitmap-1.C
index 37066f10eeae..62bb2ab7b67d 100644
--- a/gcc/testsuite/g++.target/riscv/redundant-bitmap-1.C
+++ b/gcc/testsuite/g++.target/riscv/redundant-bitmap-1.C
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O2 -march=rv64gc_zba_zbb_zbs -mabi=lp64" } */
+/* { dg-options "-O2 -march=rv64gcb -mabi=lp64" } */
void setBit(char &a, int b) {
char c = 0x1UL << b;
diff --git a/gcc/testsuite/g++.target/riscv/redundant-bitmap-2.C
b/gcc/testsuite/g++.target/riscv/redundant-bitmap-2.C
index 86acaba298fc..52204daecd11 100644
--- a/gcc/testsuite/g++.target/riscv/redundant-bitmap-2.C
+++ b/gcc/testsuite/g++.target/riscv/redundant-bitmap-2.C
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O2 -march=rv64gc_zba_zbb_zbs -mabi=lp64" } */
+/* { dg-options "-O2 -march=rv64gcb -mabi=lp64" } */
void setBit(char &a, int b) {
char c = 0x1UL << b;
diff --git a/gcc/testsuite/g++.target/riscv/redundant-bitmap-3.C
b/gcc/testsuite/g++.target/riscv/redundant-bitmap-3.C
index 16bd7c1785e7..6745220f2f41 100644
--- a/gcc/testsuite/g++.target/riscv/redundant-bitmap-3.C
+++ b/gcc/testsuite/g++.target/riscv/redundant-bitmap-3.C
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O2 -march=rv64gc_zba_zbb_zbs -mabi=lp64" } */
+/* { dg-options "-O2 -march=rv64gcb -mabi=lp64" } */
void setBit(char &a, int b) {
char c = 0x1UL << b;
diff --git a/gcc/testsuite/g++.target/riscv/redundant-bitmap-4.C
b/gcc/testsuite/g++.target/riscv/redundant-bitmap-4.C
index f664ee01a016..5e351fe457e9 100644
--- a/gcc/testsuite/g++.target/riscv/redundant-bitmap-4.C
+++ b/gcc/testsuite/g++.target/riscv/redundant-bitmap-4.C
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O2 -march=rv64gc_zba_zbb_zbs -mabi=lp64" } */
+/* { dg-options "-O2 -march=rv64gcb -mabi=lp64" } */
void setBit(char &a, int b) {
char c = 0x1UL << b;
diff --git a/gcc/testsuite/gcc.target/riscv/shift-add-1.c
b/gcc/testsuite/gcc.target/riscv/shift-add-1.c
index d98875c32716..db84a51a2227 100644
--- a/gcc/testsuite/gcc.target/riscv/shift-add-1.c
+++ b/gcc/testsuite/gcc.target/riscv/shift-add-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gc_zba_zbb_zbs -mabi=lp64" } */
+/* { dg-options "-march=rv64gcb -mabi=lp64" } */
/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */
int composeFromSurrogate(const unsigned short high) {
diff --git a/gcc/testsuite/gcc.target/riscv/shift-add-2.c
b/gcc/testsuite/gcc.target/riscv/sh
[gcc r15-2041] RISC-V: Fix testcase for vector .SAT_SUB in zip benchmark
https://gcc.gnu.org/g:4306f76192bc7ab71c5997a7e2c95320505029ab
commit r15-2041-g4306f76192bc7ab71c5997a7e2c95320505029ab
Author: Edwin Lu
Date: Fri Jul 12 11:31:16 2024 -0700
RISC-V: Fix testcase for vector .SAT_SUB in zip benchmark
The following testcase was not properly testing anything due to an
uninitialized variable. As a result, the loop was not iterating through
the testing data, but instead on undefined values which could cause an
unexpected abort.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/binop/vec_sat_binary_vx.h:
initialize variable
Signed-off-by: Edwin Lu
Diff:
---
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_binary_vx.h | 1 +
1 file changed, 1 insertion(+)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_binary_vx.h
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_binary_vx.h
index d238c6392def..309d63377d53 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_binary_vx.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_binary_vx.h
@@ -9,6 +9,7 @@ main ()
for (i = 0; i < sizeof (DATA) / sizeof (DATA[0]); i++)
{
+ d = DATA[i];
RUN_BINARY_VX (&d.x[N], d.b, N);
for (k = 0; k < N; k++)
[gcc r15-2107] RISC-V: Fix testcase missing arch attribute
https://gcc.gnu.org/g:5bb01e91d40c34e8f8230b142f7ebff3d6aa88d1
commit r15-2107-g5bb01e91d40c34e8f8230b142f7ebff3d6aa88d1
Author: Edwin Lu
Date: Tue Jul 16 17:43:45 2024 -0700
RISC-V: Fix testcase missing arch attribute
The C + F extention implies the zcf extension on rv32. Add missing zcf
extension for the rv32 target.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/target-attr-16.c: Update expected assembly
Signed-off-by: Edwin Lu
Diff:
---
gcc/testsuite/gcc.target/riscv/target-attr-16.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/testsuite/gcc.target/riscv/target-attr-16.c
b/gcc/testsuite/gcc.target/riscv/target-attr-16.c
index 1c7badccdeee..c6b626d0c6ce 100644
--- a/gcc/testsuite/gcc.target/riscv/target-attr-16.c
+++ b/gcc/testsuite/gcc.target/riscv/target-attr-16.c
@@ -24,5 +24,5 @@ void bar (void)
{
}
-/* { dg-final { scan-assembler-times ".option arch,
rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zba1p0_zbb1p0"
4 { target { rv32 } } } } */
+/* { dg-final { scan-assembler-times ".option arch,
rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zcf1p0_zba1p0_zbb1p0"
4 { target { rv32 } } } } */
/* { dg-final { scan-assembler-times ".option arch,
rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zba1p0_zbb1p0"
4 { target { rv64 } } } } */
[gcc r14-9552] RISC-V: Fix C23 (...) functions returning large aggregates [PR114175]
https://gcc.gnu.org/g:60586710b0646efdbbd77a7f53b93fb5edb87a61 commit r14-9552-g60586710b0646efdbbd77a7f53b93fb5edb87a61 Author: Edwin Lu Date: Mon Mar 18 11:43:41 2024 -0700 RISC-V: Fix C23 (...) functions returning large aggregates [PR114175] We assume that TYPE_NO_NAMED_ARGS_STDARG_P don't have any named arguments and there is nothing to advance, but that is not the case for (...) functions returning by hidden reference which have one such artificial argument. This causes gcc.dg/c23-stdarg-[68].c to fail Fix the issue by checking if arg.type is NULL as r14-9503-g218d1749612 explains Tested on linux rv64gcv. gcc/ChangeLog: PR target/114175 * config/riscv/riscv.cc (riscv_setup_incoming_varargs): Only skip riscv_funciton_arg_advance for TYPE_NO_NAMED_ARGS_STDARG_P functions if arg.type is NULL Diff: --- gcc/config/riscv/riscv.cc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 45015addd1f..02a927f96b4 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -5395,7 +5395,8 @@ riscv_setup_incoming_varargs (cumulative_args_t cum, argument. Advance a local copy of CUM past the last "real" named argument, to find out how many registers are left over. */ local_cum = *get_cumulative_args (cum); - if (!TYPE_NO_NAMED_ARGS_STDARG_P (TREE_TYPE (current_function_decl))) + if (!TYPE_NO_NAMED_ARGS_STDARG_P (TREE_TYPE (current_function_decl)) + || arg.type != NULL_TREE) riscv_function_arg_advance (pack_cumulative_args (&local_cum), arg); /* Found out how many registers we need to save. */
[gcc r14-9553] RISC-V: Update test expectancies with recent scheduler change
https://gcc.gnu.org/g:bc91e3870e9c984c180b478a3449a9a2e56cd107
commit r14-9553-gbc91e3870e9c984c180b478a3449a9a2e56cd107
Author: Edwin Lu
Date: Tue Mar 12 14:31:40 2024 -0700
RISC-V: Update test expectancies with recent scheduler change
Given the recent change with adding the scheduler pipeline descriptions,
many scan-dump failures emerged. Relax the expected assembler output
conditions on the affected tests to reduce noise.
gcc/testsuite/ChangeLog:
* gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-6.c: Disable
scheduling
* gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-8.c: Ditto
* gcc.target/riscv/rvv/base/pr108185-1.c: Update test expectancies
* gcc.target/riscv/rvv/base/pr108185-2.c: Ditto
* gcc.target/riscv/rvv/base/pr108185-3.c: Ditto
* gcc.target/riscv/rvv/base/pr108185-4.c: Ditto
* gcc.target/riscv/rvv/base/pr108185-5.c: Ditto
* gcc.target/riscv/rvv/base/pr108185-6.c: Ditto
* gcc.target/riscv/rvv/base/pr108185-7.c: Ditto
* gcc.target/riscv/rvv/base/vcreate.c: Disable scheduling and update
test expectancies
* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-30.c: Disable
scheduling
* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-31.c: Ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_single_block-17.c: Update test
expectancies
* gcc.target/riscv/rvv/vsetvl/vlmax_single_block-18.c: Ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-10.c: Ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-11.c: Ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-12.c: Ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-4.c: Ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-5.c: Ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-6.c: Ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-7.c: Ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-8.c: Ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-9.c: Ditto
Signed-off-by: Edwin Lu
Diff:
---
.../gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-6.c| 1 +
.../gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-8.c| 1 +
gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-1.c | 12 ++--
gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-2.c | 12 ++--
gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-3.c | 12 ++--
gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-4.c | 12 ++--
gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-5.c | 12 ++--
gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-6.c | 12 ++--
gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-7.c | 12 ++--
gcc/testsuite/gcc.target/riscv/rvv/base/vcreate.c| 6 --
.../gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-30.c | 1 +
.../gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-31.c | 1 +
.../gcc.target/riscv/rvv/vsetvl/vlmax_single_block-17.c | 12 ++--
.../gcc.target/riscv/rvv/vsetvl/vlmax_single_block-18.c | 6 +++---
.../gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-10.c | 4 ++--
.../gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-11.c | 2 +-
.../gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-12.c | 2 +-
.../gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-4.c | 4 ++--
.../gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-5.c | 4 ++--
.../gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-6.c | 4 ++--
.../gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-7.c | 4 ++--
.../gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-8.c | 4 ++--
.../gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-9.c | 4 ++--
23 files changed, 75 insertions(+), 69 deletions(-)
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-6.c
b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-6.c
index bd7ce23f6b8..b23acebc916 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-6.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-6.c
@@ -1,5 +1,6 @@
/* { dg-do compile } */
/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize --param
riscv-autovec-lmul=dynamic -mrvv-vector-bits=scalable -fselective-scheduling
-fdump-tree-vect-details" } */
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
#include
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-8.c
b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-8.c
index 61619a0c879..ef719ee8445 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-8.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-8.c
@@ -1,5 +1,6 @@
/* { dg-do compile } */
/* { dg-
[gcc r13-8579] RISC-V: Fix C23 (...) functions returning large aggregates [PR114175]
https://gcc.gnu.org/g:c4eff4ece764d836eb7ee0c0163780d100471730 commit r13-8579-gc4eff4ece764d836eb7ee0c0163780d100471730 Author: Edwin Lu Date: Mon Mar 18 11:43:41 2024 -0700 RISC-V: Fix C23 (...) functions returning large aggregates [PR114175] We assume that TYPE_NO_NAMED_ARGS_STDARG_P don't have any named arguments and there is nothing to advance, but that is not the case for (...) functions returning by hidden reference which have one such artificial argument. This causes gcc.dg/c23-stdarg-[68].c to fail Fix the issue by checking if arg.type is NULL as r14-9503-g218d1749612 explains Tested on linux rv64gcv. gcc/ChangeLog: PR target/114175 * config/riscv/riscv.cc (riscv_setup_incoming_varargs): Only skip riscv_funciton_arg_advance for TYPE_NO_NAMED_ARGS_STDARG_P functions if arg.type is NULL (cherry picked from commit 60586710b0646efdbbd77a7f53b93fb5edb87a61) Diff: --- gcc/config/riscv/riscv.cc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 01eebc83cc5..cefd3b7b2b2 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -3961,7 +3961,8 @@ riscv_setup_incoming_varargs (cumulative_args_t cum, argument. Advance a local copy of CUM past the last "real" named argument, to find out how many registers are left over. */ local_cum = *get_cumulative_args (cum); - if (!TYPE_NO_NAMED_ARGS_STDARG_P (TREE_TYPE (current_function_decl))) + if (!TYPE_NO_NAMED_ARGS_STDARG_P (TREE_TYPE (current_function_decl)) + || arg.type != NULL_TREE) riscv_function_arg_advance (pack_cumulative_args (&local_cum), arg); /* Found out how many registers we need to save. */
[gcc r15-2418] RISC-V: Add configure check for B extention support
https://gcc.gnu.org/g:7ef8a9d4b1cea3fea3791859074df79b71abd549
commit r15-2418-g7ef8a9d4b1cea3fea3791859074df79b71abd549
Author: Edwin Lu
Date: Wed Jul 24 16:37:18 2024 -0700
RISC-V: Add configure check for B extention support
Binutils 2.42 and before don't recognize the b extension in the march
strings even though it supports zba_zbb_zbs. Add a configure check to
ignore the b in the march string if found.
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc
(riscv_subset_list::to_string):
Skip b in march string
* config.in: Regenerate.
* configure: Regenerate.
* configure.ac: Add B assembler check
Signed-off-by: Edwin Lu
Diff:
---
gcc/common/config/riscv/riscv-common.cc | 8
gcc/config.in | 6 ++
gcc/configure | 31 +++
gcc/configure.ac| 5 +
4 files changed, 50 insertions(+)
diff --git a/gcc/common/config/riscv/riscv-common.cc
b/gcc/common/config/riscv/riscv-common.cc
index 0c12e12cde51..1944c7785c48 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -858,6 +858,7 @@ riscv_subset_list::to_string (bool version_p) const
bool skip_zifencei = false;
bool skip_zaamo_zalrsc = false;
bool skip_zicsr = false;
+ bool skip_b = false;
bool i2p0 = false;
/* For RISC-V ISA version 2.2 or earlier version, zicsr and zifencei is
@@ -890,6 +891,10 @@ riscv_subset_list::to_string (bool version_p) const
for users with an older version of binutils. */
skip_zaamo_zalrsc = true;
#endif
+#ifndef HAVE_AS_MARCH_B
+ /* Skip since binutils 2.42 and earlier don't recognize b. */
+ skip_b = true;
+#endif
for (subset = m_head; subset != NULL; subset = subset->next)
{
@@ -907,6 +912,9 @@ riscv_subset_list::to_string (bool version_p) const
if (skip_zaamo_zalrsc && subset->name == "zalrsc")
continue;
+ if (skip_b && subset->name == "b")
+ continue;
+
/* For !version_p, we only separate extension with underline for
multi-letter extension. */
if (!first &&
diff --git a/gcc/config.in b/gcc/config.in
index 3af153eaec5c..7fcabbe5061d 100644
--- a/gcc/config.in
+++ b/gcc/config.in
@@ -629,6 +629,12 @@
#endif
+/* Define if the assembler understands -march=rv*_b. */
+#ifndef USED_FOR_TARGET
+#undef HAVE_AS_MARCH_B
+#endif
+
+
/* Define if the assembler understands -march=rv*_zaamo_zalrsc. */
#ifndef USED_FOR_TARGET
#undef HAVE_AS_MARCH_ZAAMO_ZALRSC
diff --git a/gcc/configure b/gcc/configure
index 7541bdeb7248..557ea5fa3ac9 100755
--- a/gcc/configure
+++ b/gcc/configure
@@ -30882,6 +30882,37 @@ if test $gcc_cv_as_riscv_march_zaamo_zalrsc = yes; then
$as_echo "#define HAVE_AS_MARCH_ZAAMO_ZALRSC 1" >>confdefs.h
+fi
+
+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking assembler for
-march=rv32i_b support" >&5
+$as_echo_n "checking assembler for -march=rv32i_b support... " >&6; }
+if ${gcc_cv_as_riscv_march_b+:} false; then :
+ $as_echo_n "(cached) " >&6
+else
+ gcc_cv_as_riscv_march_b=no
+ if test x$gcc_cv_as != x; then
+$as_echo '' > conftest.s
+if { ac_try='$gcc_cv_as $gcc_cv_as_flags -march=rv32i_b -o conftest.o
conftest.s >&5'
+ { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_try\""; } >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5
+ test $ac_status = 0; }; }
+then
+ gcc_cv_as_riscv_march_b=yes
+else
+ echo "configure: failed program was" >&5
+ cat conftest.s >&5
+fi
+rm -f conftest.o conftest.s
+ fi
+fi
+{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $gcc_cv_as_riscv_march_b" >&5
+$as_echo "$gcc_cv_as_riscv_march_b" >&6; }
+if test $gcc_cv_as_riscv_march_b = yes; then
+
+$as_echo "#define HAVE_AS_MARCH_B 1" >>confdefs.h
+
fi
;;
diff --git a/gcc/configure.ac b/gcc/configure.ac
index 52c1780379d5..eaa01d0d7e56 100644
--- a/gcc/configure.ac
+++ b/gcc/configure.ac
@@ -5461,6 +5461,11 @@ configured with --enable-newlib-nano-formatted-io.])
[-march=rv32i_zaamo_zalrsc],,,
[AC_DEFINE(HAVE_AS_MARCH_ZAAMO_ZALRSC, 1,
[Define if the assembler understands
-march=rv*_zaamo_zalrsc.])])
+gcc_GAS_CHECK_FEATURE([-march=rv32i_b support],
+ gcc_cv_as_riscv_march_b,
+ [-march=rv32i_b],,,
+ [AC_DEFINE(HAVE_AS_MARCH_B, 1,
+[Define if the assembler understands -march=rv*_b.])])
;;
loongarch*-*-*)
gcc_GAS_CHECK_FEATURE([.dtprelword support],
[gcc r15-2895] RISC-V: Fix missing abi arg in test
https://gcc.gnu.org/g:ef90a136da4c3e0b28997da25c30fdce1bcb115c
commit r15-2895-gef90a136da4c3e0b28997da25c30fdce1bcb115c
Author: Edwin Lu
Date: Wed Aug 7 10:34:10 2024 -0700
RISC-V: Fix missing abi arg in test
The following test was failing when building on 32 bit targets
due to not overwriting the mabi arg. This resulted in dejagnu
attempting to run the test with -mabi=ilp32d -march=rv64gcv_zvl256b
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/pr116202-run-1.c: Add mabi arg
Signed-off-by: Edwin Lu
Diff:
---
gcc/testsuite/gcc.target/riscv/rvv/base/pr116202-run-1.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr116202-run-1.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/pr116202-run-1.c
index d150f20b5d93..02814183dbb9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr116202-run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr116202-run-1.c
@@ -1,5 +1,5 @@
/* { dg-do run } */
-/* { dg-options "-O3 -march=rv64gcv_zvl256b -fdump-rtl-expand-details" } */
+/* { dg-options "-O3 -march=rv64gcv_zvl256b -mabi=lp64d
-fdump-rtl-expand-details" } */
int b[24];
_Bool c[24];
[gcc r15-1420] RISC-V: Fix vwsll combine on rv32 targets
https://gcc.gnu.org/g:6638ba17eadc0f450faa3d8c2f77afe7fdb20614
commit r15-1420-g6638ba17eadc0f450faa3d8c2f77afe7fdb20614
Author: Edwin Lu
Date: Tue Jun 11 13:50:02 2024 -0700
RISC-V: Fix vwsll combine on rv32 targets
On rv32 targets, vwsll_zext1_scalar_ would trigger an ice in
maybe_legitimize_instruction when zero extending a uint32 to uint64 due
to a mismatch between the input operand's mode (DI) and the expanded insn
operand's mode (Pmode == SI). Ensure that mode of the operands match
gcc/ChangeLog:
* config/riscv/autovec-opt.md: Fix mode mismatch
Signed-off-by: Edwin Lu
Co-authored-by: Robin Dapp
Diff:
---
gcc/config/riscv/autovec-opt.md | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md
index 6a2eabbd8544..d7a3cfd4602b 100644
--- a/gcc/config/riscv/autovec-opt.md
+++ b/gcc/config/riscv/autovec-opt.md
@@ -1517,8 +1517,7 @@
"&& 1"
[(const_int 0)]
{
-if (GET_CODE (operands[2]) == SUBREG)
- operands[2] = SUBREG_REG (operands[2]);
+operands[2] = gen_lowpart (Pmode, operands[2]);
insn_code icode = code_for_pred_vwsll_scalar (mode);
riscv_vector::emit_vlmax_insn (icode, riscv_vector::BINARY_OP, operands);
DONE;
@@ -1584,8 +1583,7 @@
"&& 1"
[(const_int 0)]
{
-if (GET_CODE (operands[2]) == SUBREG)
- operands[2] = SUBREG_REG (operands[2]);
+operands[2] = gen_lowpart (Pmode, operands[2]);
insn_code icode = code_for_pred_vwsll_scalar (mode);
riscv_vector::emit_vlmax_insn (icode, riscv_vector::BINARY_OP, operands);
DONE;
[gcc r15-1421] RISC-V: Move mode assertion out of conditional branch in emit_insn
https://gcc.gnu.org/g:ffe5141f30655e1889c8d0471a4f60fa4d64d1b0
commit r15-1421-gffe5141f30655e1889c8d0471a4f60fa4d64d1b0
Author: Edwin Lu
Date: Fri Jun 14 09:46:01 2024 -0700
RISC-V: Move mode assertion out of conditional branch in emit_insn
When emitting insns, we have an early assertion to ensure the input
operand's mode and the expanded operand's mode are the same; however, it
does not perform this check if the pattern does not have an explicit
machine mode specifying the operand. In this scenario, it will always
assume that mode = Pmode to correctly satisfy the
maybe_legitimize_operand check, however, there may be problems when
working in 32 bit environments.
Make the assert unconditional and replace it with an internal error for
more descriptive logging
gcc/ChangeLog:
* config/riscv/riscv-v.cc: Move assert out of conditional block
Signed-off-by: Edwin Lu
Co-authored-by: Robin Dapp
Diff:
---
gcc/config/riscv/riscv-v.cc | 25 +++--
1 file changed, 19 insertions(+), 6 deletions(-)
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 8911f5783c88..5306711c1b73 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -50,6 +50,7 @@
#include "rtx-vector-builder.h"
#include "targhooks.h"
#include "predict.h"
+#include "errors.h"
using namespace riscv_vector;
@@ -290,11 +291,17 @@ public:
always Pmode. */
if (mode == VOIDmode)
mode = Pmode;
- else
- /* Early assertion ensures same mode since maybe_legitimize_operand
-will check this. */
- gcc_assert (GET_MODE (ops[opno]) == VOIDmode
- || GET_MODE (ops[opno]) == mode);
+
+ /* Early assertion ensures same mode since maybe_legitimize_operand
+ will check this. */
+ machine_mode required_mode = GET_MODE (ops[opno]);
+ if (required_mode != VOIDmode && required_mode != mode)
+ internal_error ("expected mode %s for operand %d of "
+ "insn %s but got mode %s.\n",
+ GET_MODE_NAME (mode),
+ opno,
+ insn_data[(int) icode].name,
+ GET_MODE_NAME (required_mode));
add_input_operand (ops[opno], mode);
}
@@ -346,7 +353,13 @@ public:
else if (m_insn_flags & VXRM_RDN_P)
add_rounding_mode_operand (VXRM_RDN);
-gcc_assert (insn_data[(int) icode].n_operands == m_opno);
+
+if (insn_data[(int) icode].n_operands != m_opno)
+ internal_error ("invalid number of operands for insn %s, "
+ "expected %d but got %d.\n",
+ insn_data[(int) icode].name,
+ insn_data[(int) icode].n_operands, m_opno);
+
expand (icode, any_mem_p);
}
[gcc r15-5177] RISC-V: testsuite: Remove deprecated compatibility headers
https://gcc.gnu.org/g:534e14ad115da0fc1581a637b048a03ecbda1eaf
commit r15-5177-g534e14ad115da0fc1581a637b048a03ecbda1eaf
Author: Edwin Lu
Date: Mon Nov 11 10:09:02 2024 -0800
RISC-V: testsuite: Remove deprecated compatibility headers
Since r15-4981-g5c34f02ba7e these tests have been failing on vector
targets with excess errors due to the new deprecation warning message.
Remove the header.
gcc/testsuite/ChangeLog:
* g++.target/riscv/rvv/base/bug-10.C: Remove cstdalign header.
* g++.target/riscv/rvv/base/bug-11.C: Ditto.
* g++.target/riscv/rvv/base/bug-12.C: Ditto.
* g++.target/riscv/rvv/base/bug-13.C: Ditto.
* g++.target/riscv/rvv/base/bug-14.C: Ditto.
* g++.target/riscv/rvv/base/bug-15.C: Ditto.
* g++.target/riscv/rvv/base/bug-16.C: Ditto.
* g++.target/riscv/rvv/base/bug-17.C: Ditto.
* g++.target/riscv/rvv/base/bug-2.C: Ditto.
* g++.target/riscv/rvv/base/bug-23.C: Ditto.
* g++.target/riscv/rvv/base/bug-3.C: Ditto.
* g++.target/riscv/rvv/base/bug-4.C: Ditto.
* g++.target/riscv/rvv/base/bug-5.C: Ditto.
* g++.target/riscv/rvv/base/bug-6.C: Ditto.
* g++.target/riscv/rvv/base/bug-7.C: Ditto.
* g++.target/riscv/rvv/base/bug-8.C: Ditto.
* g++.target/riscv/rvv/base/bug-9.C: Ditto.
Signed-off-by: Edwin Lu
Diff:
---
gcc/testsuite/g++.target/riscv/rvv/base/bug-10.C | 1 -
gcc/testsuite/g++.target/riscv/rvv/base/bug-11.C | 1 -
gcc/testsuite/g++.target/riscv/rvv/base/bug-12.C | 1 -
gcc/testsuite/g++.target/riscv/rvv/base/bug-13.C | 1 -
gcc/testsuite/g++.target/riscv/rvv/base/bug-14.C | 1 -
gcc/testsuite/g++.target/riscv/rvv/base/bug-15.C | 1 -
gcc/testsuite/g++.target/riscv/rvv/base/bug-16.C | 1 -
gcc/testsuite/g++.target/riscv/rvv/base/bug-17.C | 1 -
gcc/testsuite/g++.target/riscv/rvv/base/bug-2.C | 1 -
gcc/testsuite/g++.target/riscv/rvv/base/bug-23.C | 1 -
gcc/testsuite/g++.target/riscv/rvv/base/bug-3.C | 1 -
gcc/testsuite/g++.target/riscv/rvv/base/bug-4.C | 1 -
gcc/testsuite/g++.target/riscv/rvv/base/bug-5.C | 1 -
gcc/testsuite/g++.target/riscv/rvv/base/bug-6.C | 1 -
gcc/testsuite/g++.target/riscv/rvv/base/bug-7.C | 1 -
gcc/testsuite/g++.target/riscv/rvv/base/bug-8.C | 1 -
gcc/testsuite/g++.target/riscv/rvv/base/bug-9.C | 1 -
17 files changed, 17 deletions(-)
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/bug-10.C
b/gcc/testsuite/g++.target/riscv/rvv/base/bug-10.C
index 4fe7fd30bb48..877b9bbdb6e7 100644
--- a/gcc/testsuite/g++.target/riscv/rvv/base/bug-10.C
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/bug-10.C
@@ -1,7 +1,6 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-options "-O2" } */
-#include
#include
#include
#include
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/bug-11.C
b/gcc/testsuite/g++.target/riscv/rvv/base/bug-11.C
index a916d721d5ac..25f20b194156 100644
--- a/gcc/testsuite/g++.target/riscv/rvv/base/bug-11.C
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/bug-11.C
@@ -1,7 +1,6 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-options "-O2" } */
-#include
#include
#include
#include
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/bug-12.C
b/gcc/testsuite/g++.target/riscv/rvv/base/bug-12.C
index daa0e3bfadc7..de73162d0a44 100644
--- a/gcc/testsuite/g++.target/riscv/rvv/base/bug-12.C
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/bug-12.C
@@ -1,7 +1,6 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-options "-O2" } */
-#include
#include
#include
#include
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/bug-13.C
b/gcc/testsuite/g++.target/riscv/rvv/base/bug-13.C
index 4b96899c1f61..bd5ce57f5de5 100644
--- a/gcc/testsuite/g++.target/riscv/rvv/base/bug-13.C
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/bug-13.C
@@ -1,7 +1,6 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-options "-O2" } */
-#include
#include
#include
#include
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/bug-14.C
b/gcc/testsuite/g++.target/riscv/rvv/base/bug-14.C
index f2d67c859681..6c6e89743cbc 100644
--- a/gcc/testsuite/g++.target/riscv/rvv/base/bug-14.C
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/bug-14.C
@@ -3,7 +3,6 @@
/* { dg-require-effective-target rv64 } */
/* { dg-require-effective-target riscv_v } */
-#include
#include
#include
#include
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/bug-15.C
b/gcc/testsuite/g++.target/riscv/rvv/base/bug-15.C
index da95400cc902..2839013d7f9a 100644
--- a/gcc/testsuite/g++.target/riscv/rvv/base/bug-15.C
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/bug-15.C
@@ -1,7 +1,6 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-options "-O2" } */
-#include
#include
#include
#include
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/bug-16.C
b/gcc/testsuite/g++.target/riscv/rvv/base/bug-16.C
index 5e749d5496d6..4b28be03898c
[gcc r15-5468] RISC-V: testsuite: fix old-style function definition error [NFC]
https://gcc.gnu.org/g:c4156864611ea231acd842a8d3705989217a8a13
commit r15-5468-gc4156864611ea231acd842a8d3705989217a8a13
Author: Edwin Lu
Date: Mon Nov 18 14:36:17 2024 -0800
RISC-V: testsuite: fix old-style function definition error [NFC]
The following testcase was failing with the warning: old-style function
definition ever since the c standard version has been updated. Update
the function definition.
gcc/testsuite/ChangeLog:
* gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul-ice-3.c: Update
function definition.
Signed-off-by: Edwin Lu
Diff:
---
gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul-ice-3.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul-ice-3.c
b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul-ice-3.c
index c0a7e1c35e6c..476d03469d01 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul-ice-3.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul-ice-3.c
@@ -2,9 +2,7 @@
/* { dg-options "-march=rv32gcv -mabi=ilp32 -O2 -ftree-vectorize -flto
-fno-use-linker-plugin -flto-partition=none -mrvv-max-lmul=dynamic" } */
void (*foo[6][6]) (int);
-void bar (hdR)
-int hdR;
-{ }
+void bar (int hdR) { }
void xxx ()
{
unsigned int i, j;
[gcc r15-5525] RISC-V: testsuite: restrict big endian test to non vector
https://gcc.gnu.org/g:342eb518bd029fe818cb640e1cc12e12dc074bdd
commit r15-5525-g342eb518bd029fe818cb640e1cc12e12dc074bdd
Author: Edwin Lu
Date: Tue Nov 19 12:55:15 2024 -0800
RISC-V: testsuite: restrict big endian test to non vector
RISC-V vector currently does not support big endian so the postcommit
was getting the sorry, not implemented error on vector targets. Restrict
the testcase to non-vector targets
gcc/testsuite/ChangeLog:
* gcc.target/riscv/pr117595.c: Restrict to non vector targets.
Signed-off-by: Edwin Lu
Diff:
---
gcc/testsuite/gcc.target/riscv/pr117595.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/testsuite/gcc.target/riscv/pr117595.c
b/gcc/testsuite/gcc.target/riscv/pr117595.c
index a870df08ee4b..156b9388d6e4 100644
--- a/gcc/testsuite/gcc.target/riscv/pr117595.c
+++ b/gcc/testsuite/gcc.target/riscv/pr117595.c
@@ -1,4 +1,4 @@
-/* { dg-do compile } */
+/* { dg-do compile { target { ! riscv_v } } } */
/* { dg-options "-mbig-endian" } */
_Atomic enum { E0 } e;
[gcc r15-5899] RISC-V: Fix test target selector
https://gcc.gnu.org/g:eee3182e1af633f99e5264854cb6b5c00ce7a5dd
commit r15-5899-geee3182e1af633f99e5264854cb6b5c00ce7a5dd
Author: Edwin Lu
Date: Mon Dec 2 17:29:55 2024 -0800
RISC-V: Fix test target selector
The previous target selector was not properly gating the tests to rv32
and rv64 targets. This was triggering an excess failure on rv32 targets
where it would try to run the zbc64 tests. Fix selector
gcc/testsuite/ChangeLog:
* gcc.target/riscv/crc-builtin-zbc32.c: Fix selector.
* gcc.target/riscv/crc-builtin-zbc64.c: Ditto.
Signed-off-by: Edwin Lu
Diff:
---
gcc/testsuite/gcc.target/riscv/crc-builtin-zbc32.c | 2 +-
gcc/testsuite/gcc.target/riscv/crc-builtin-zbc64.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/gcc/testsuite/gcc.target/riscv/crc-builtin-zbc32.c
b/gcc/testsuite/gcc.target/riscv/crc-builtin-zbc32.c
index 3eb4be78dcb5..ca90feaef26b 100644
--- a/gcc/testsuite/gcc.target/riscv/crc-builtin-zbc32.c
+++ b/gcc/testsuite/gcc.target/riscv/crc-builtin-zbc32.c
@@ -1,4 +1,4 @@
-/* { dg-do compile { target { riscv32*-*-* } } } */
+/* { dg-do compile { target { rv32 } } } */
/* { dg-options "-march=rv32gc_zbc" } */
#include
diff --git a/gcc/testsuite/gcc.target/riscv/crc-builtin-zbc64.c
b/gcc/testsuite/gcc.target/riscv/crc-builtin-zbc64.c
index d99a78daaa93..f31a8bd949f5 100644
--- a/gcc/testsuite/gcc.target/riscv/crc-builtin-zbc64.c
+++ b/gcc/testsuite/gcc.target/riscv/crc-builtin-zbc64.c
@@ -1,4 +1,4 @@
-/* { dg-do compile { target { riscv64*-*-* } } } */
+/* { dg-do compile { target { rv64 } } } */
/* { dg-options "-march=rv64gc_zbc" } */
#include
[gcc r15-6753] RISC-V: testsuite: fix target selector for sync_char_short
https://gcc.gnu.org/g:2d0f3457a80b804dc0d33924781cf386a0088511
commit r15-6753-g2d0f3457a80b804dc0d33924781cf386a0088511
Author: Edwin Lu
Date: Thu Jan 9 10:32:07 2025 -0800
RISC-V: testsuite: fix target selector for sync_char_short
The effective-target selector for riscv on sync_char_short did not
check to see if atomics were enabled. As a result, these test cases were
ran on targets without the a extension. Add additional checks for zalrsc
or zabha extensions.
gcc/testsuite/ChangeLog:
* lib/target-supports.exp: Fix effective target sync_char_short
for riscv*-*-*
Signed-off-by: Edwin Lu
Diff:
---
gcc/testsuite/lib/target-supports.exp | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/gcc/testsuite/lib/target-supports.exp
b/gcc/testsuite/lib/target-supports.exp
index a89f531f8876..939ef3a41196 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -10080,7 +10080,9 @@ proc check_effective_target_sync_char_short { } {
|| ([istarget sparc*-*-*] && [check_effective_target_sparc_v9])
|| ([istarget arc*-*-*] && [check_effective_target_arc_atomic])
|| [istarget loongarch*-*-*]
-|| [istarget riscv*-*-*]
+|| ([istarget riscv*-*-*]
+&& ([check_effective_target_riscv_zalrsc]
+|| [check_effective_target_riscv_zabha]))
|| [check_effective_target_mips_llsc] }}]
}
[gcc r15-8982] RISC-V: testsuite: fix syntax error for assembler scan
https://gcc.gnu.org/g:c35b4bcad17ce1f59aebd779d7aab85cc9539154
commit r15-8982-gc35b4bcad17ce1f59aebd779d7aab85cc9539154
Author: Edwin Lu
Date: Thu Mar 27 10:45:13 2025 -0700
RISC-V: testsuite: fix syntax error for assembler scan
When the dg brackets were added, they forgot to add the brackets for the
scan-assembler-times directive.
Committed as obvious.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/vls/merge-4.c: Fix typo
Signed-off-by: Edwin Lu
Diff:
---
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-4.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-4.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-4.c
index 30ef22f9f9ea..4ae341a091e8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-4.c
@@ -3,6 +3,6 @@
#include "../vls-vlmax/merge-4.c"
-/* { dg-final scan-assembler-times {\tvmerge.vvm} 11 } */
+/* { dg-final { scan-assembler-times {\tvmerge.vvm} 11 } } */
/* { dg-final { scan-assembler-not {\tvms} } } */
/* { dg-final { scan-assembler-times {\tvlm.v} 11 } } */
[gcc r16-1421] RISC-V: Prevent speculative vsetvl insn scheduling
https://gcc.gnu.org/g:1c5e99ce8744c166d82cb96bbb2d58392b5fb8d7
commit r16-1421-g1c5e99ce8744c166d82cb96bbb2d58392b5fb8d7
Author: Edwin Lu
Date: Tue Jun 10 13:26:42 2025 -0700
RISC-V: Prevent speculative vsetvl insn scheduling
The instruction scheduler appears to be speculatively hoisting vsetvl
insns outside of their basic block without checking for data
dependencies. This resulted in a situation where the following occurs
vsetvli a5,a1,e32,m1,tu,ma
vle32.v v2,0(a0)
sub a1,a1,a5 <-- a1 potentially set to 0
sh2add a0,a5,a0
vfmacc.vv v1,v2,v2
vsetvli a5,a1,e32,m1,tu,ma <-- incompatible vinfo. update vl to 0
beq a1,zero,.L12 <-- check if avl is 0
This patch would essentially delay the vsetvl update to after the branch
to prevent unnecessarily updating the vinfo at the end of a basic block.
PR/117974
gcc/ChangeLog:
* config/riscv/riscv.cc (struct riscv_tune_param): Add tune
param.
(riscv_sched_can_speculate_insn): Implement.
(TARGET_SCHED_CAN_SPECULATE_INSN): Ditto.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/vsetvl/pr117974.c: New test.
Signed-off-by: Edwin Lu
Diff:
---
gcc/config/riscv/riscv.cc | 35 ++
.../gcc.target/riscv/rvv/vsetvl/pr117974.c | 19
2 files changed, 54 insertions(+)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 0c99850c14d8..c6e0ffb0755e 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -302,6 +302,7 @@ struct riscv_tune_param
bool vector_unaligned_access;
bool use_divmod_expansion;
bool overlap_op_by_pieces;
+ bool speculative_sched_vsetvl;
unsigned int fusible_ops;
const struct cpu_vector_cost *vec_costs;
const char *function_align;
@@ -464,6 +465,7 @@ static const struct riscv_tune_param rocket_tune_info = {
false, /* vector_unaligned_access */
false, /* use_divmod_expansion */
false, /* overlap_op_by_pieces */
+ false, /* speculative_sched_vsetvl */
RISCV_FUSE_NOTHING, /* fusible_ops */
NULL,/* vector cost */
NULL,/* function_align */
@@ -486,6 +488,7 @@ static const struct riscv_tune_param sifive_7_tune_info = {
false, /* vector_unaligned_access */
false, /* use_divmod_expansion */
false, /* overlap_op_by_pieces */
+ false, /* speculative_sched_vsetvl */
RISCV_FUSE_NOTHING, /* fusible_ops */
NULL,/* vector cost */
NULL,/* function_align */
@@ -508,6 +511,7 @@ static const struct riscv_tune_param sifive_p400_tune_info
= {
false, /* vector_unaligned_access */
false, /* use_divmod_expansion */
false, /* overlap_op_by_pieces */
+ false, /* speculative_sched_vsetvl */
RISCV_FUSE_LUI_ADDI | RISCV_FUSE_AUIPC_ADDI, /* fusible_ops */
&generic_vector_cost,/* vector cost */
NULL,/* function_align */
@@ -530,6 +534,7 @@ static const struct riscv_tune_param sifive_p600_tune_info
= {
false, /* vector_unaligned_access */
false, /* use_divmod_expansion */
false, /* overlap_op_by_pieces */
+ false, /* speculative_sched_vsetvl */
RISCV_FUSE_LUI_ADDI | RISCV_FUSE_AUIPC_ADDI, /* fusible_ops */
&generic_vector_cost,/* vector cost */
NULL,/* function_align */
@@ -552,6 +557,7 @@ static const struct riscv_tune_param thead_c906_tune_info =
{
false, /* vector_unaligned_access */
false, /* use_divmod_expansion */
false, /* overlap_op_by_pieces */
+ false, /* speculative_sched_vsetvl */
RISCV_FUSE_NOTHING, /* fusible_ops */
NULL,/* vector cost */
NULL,/* function_align */
@@ -574,6 +580,7 @
