[gcc r15-3519] rs6000, extend and document built-ins vec_test_lsbb_all_ones and vec_test_lsbb_all_zeros
https://gcc.gnu.org/g:6c9a714a26522ea89944b4c4f01f1d5bc344a364
commit r15-3519-g6c9a714a26522ea89944b4c4f01f1d5bc344a364
Author: Carl Love
Date: Fri Sep 6 12:06:34 2024 -0400
rs6000,extend and document built-ins vec_test_lsbb_all_ones and
vec_test_lsbb_all_zeros
The built-ins currently support vector unsigned char arguments. Extend the
built-ins to also support vector signed char and vector bool char
arguments.
Add documentation for the Power 10 built-ins vec_test_lsbb_all_ones
and vec_test_lsbb_all_zeros. The vec_test_lsbb_all_ones built-in
returns 1 if the least significant bit in each byte is a 1, returns
0 otherwise. Similarly, vec_test_lsbb_all_zeros returns a 1 if
the least significant bit in each byte is a zero and 0 otherwise.
Add addtional test cases for the built-ins in files:
gcc/testsuite/gcc.target/powerpc/lsbb.c
gcc/testsuite/gcc.target/powerpc/lsbb-runnable.c
gcc/ChangeLog:
* config/rs6000/rs6000-overload.def (vec_test_lsbb_all_ones,
vec_test_lsbb_all_zeros): Add built-in instances for vector signed
char and vector bool char.
* doc/extend.texi (vec_test_lsbb_all_ones,
vec_test_lsbb_all_zeros): Add documentation for the
existing built-ins.
gcc/testsuite/ChangeLog:gcc/testsuite/ChangeLog:
* gcc.target/powerpc/lsbb-runnable.c: Add test cases for the vector
signed char and vector bool char instances of
vec_test_lsbb_all_zeros and vec_test_lsbb_all_ones built-ins.
* gcc.target/powerpc/lsbb.c: Add compile test cases for the vector
signed char and vector bool char instances of
vec_test_lsbb_all_zeros and vec_test_lsbb_all_ones built-ins.
Diff:
---
gcc/config/rs6000/rs6000-overload.def| 12 ++-
gcc/doc/extend.texi | 19
gcc/testsuite/gcc.target/powerpc/lsbb-runnable.c | 131 ++-
gcc/testsuite/gcc.target/powerpc/lsbb.c | 28 +++--
4 files changed, 158 insertions(+), 32 deletions(-)
diff --git a/gcc/config/rs6000/rs6000-overload.def
b/gcc/config/rs6000/rs6000-overload.def
index 87495aded49..7d9e31c3f9e 100644
--- a/gcc/config/rs6000/rs6000-overload.def
+++ b/gcc/config/rs6000/rs6000-overload.def
@@ -4403,12 +4403,20 @@
XXEVAL XXEVAL_VUQ
[VEC_TEST_LSBB_ALL_ONES, vec_test_lsbb_all_ones,
__builtin_vec_xvtlsbb_all_ones]
+ signed int __builtin_vec_xvtlsbb_all_ones (vsc);
+XVTLSBB_ONES LSBB_ALL_ONES_VSC
signed int __builtin_vec_xvtlsbb_all_ones (vuc);
-XVTLSBB_ONES
+XVTLSBB_ONES LSBB_ALL_ONES_VUC
+ signed int __builtin_vec_xvtlsbb_all_ones (vbc);
+XVTLSBB_ONES LSBB_ALL_ONES_VBC
[VEC_TEST_LSBB_ALL_ZEROS, vec_test_lsbb_all_zeros,
__builtin_vec_xvtlsbb_all_zeros]
+ signed int __builtin_vec_xvtlsbb_all_zeros (vsc);
+XVTLSBB_ZEROS LSBB_ALL_ZEROS_VSC
signed int __builtin_vec_xvtlsbb_all_zeros (vuc);
-XVTLSBB_ZEROS
+XVTLSBB_ZEROS LSBB_ALL_ZEROS_VUC
+ signed int __builtin_vec_xvtlsbb_all_zeros (vbc);
+XVTLSBB_ZEROS LSBB_ALL_ZEROS_VBC
[VEC_TRUNC, vec_trunc, __builtin_vec_trunc]
vf __builtin_vec_trunc (vf);
diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
index af0c45b42e0..2d795ba7e59 100644
--- a/gcc/doc/extend.texi
+++ b/gcc/doc/extend.texi
@@ -23421,6 +23421,25 @@ signed long long will sign extend the rightmost byte
of each doubleword.
The following additional built-in functions are also available for the
PowerPC family of processors, starting with ISA 3.1 (@option{-mcpu=power10}):
+@smallexample
+@exdent int vec_test_lsbb_all_ones (vector signed char);
+@exdent int vec_test_lsbb_all_ones (vector unsigned char);
+@exdent int vec_test_lsbb_all_ones (vector bool char);
+@end smallexample
+@findex vec_test_lsbb_all_ones
+
+The builtin @code{vec_test_lsbb_all_ones} returns 1 if the least significant
+bit in each byte is equal to 1. It returns 0 otherwise.
+
+@smallexample
+@exdent int vec_test_lsbb_all_zeros (vector signed char);
+@exdent int vec_test_lsbb_all_zeros (vector unsigned char);
+@exdent int vec_test_lsbb_all_zeros (vector bool char);
+@end smallexample
+@findex vec_test_lsbb_all_zeros
+
+The builtin @code{vec_test_lsbb_all_zeros} returns 1 if the least significant
+bit in each byte is equal to zero. It returns 0 otherwise.
@smallexample
@exdent vector unsigned long long int
diff --git a/gcc/testsuite/gcc.target/powerpc/lsbb-runnable.c
b/gcc/testsuite/gcc.target/powerpc/lsbb-runnable.c
index 2e97cc17b60..3e4f71bed12 100644
--- a/gcc/testsuite/gcc.target/powerpc/lsbb-runnable.c
+++ b/gcc/testsuite/gcc.target/powerpc/lsbb-runnable.c
@@ -17,7 +17,27 @@
void abort (void);
#define ITERS 7
-vector char input_vec[ITERS] = {
+vector signed char input_svec[ITERS] = {
+ {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
+ {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1},
+ {0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0,
[gcc r15-1656] rs6000, altivec-1-runnable.c update the require-effective-target
https://gcc.gnu.org/g:4bf719bc5858cf7e5c96a1b396b0b4b0480c7e5b
commit r15-1656-g4bf719bc5858cf7e5c96a1b396b0b4b0480c7e5b
Author: Carl Love
Date: Mon Jun 24 12:31:19 2024 -0400
rs6000, altivec-1-runnable.c update the require-effective-target
Update the dg test directives.
gcc/testsuite/ChangeLog:gcc/testsuite/ChangeLog:
* gcc.target/powerpc/altivec-1-runnable.c: Change the
require-effective-target for the test.
Diff:
---
gcc/testsuite/gcc.target/powerpc/altivec-1-runnable.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-1-runnable.c
b/gcc/testsuite/gcc.target/powerpc/altivec-1-runnable.c
index 4e32860a169..3f084c91798 100644
--- a/gcc/testsuite/gcc.target/powerpc/altivec-1-runnable.c
+++ b/gcc/testsuite/gcc.target/powerpc/altivec-1-runnable.c
@@ -1,5 +1,6 @@
-/* { dg-do compile { target powerpc*-*-* } } */
-/* { dg-options "-maltivec" } */
+/* { dg-do run { target vmx_hw } } */
+/* { dg-do compile { target { ! vmx_hw } } } */
+/* { dg-options "-O2 -maltivec" } */
/* { dg-require-effective-target powerpc_altivec } */
#include
[gcc r15-1657] rs6000, altivec-2-runnable.c update the require-effective-target
https://gcc.gnu.org/g:0699de2a590f147218323c942e91ccf87273af14
commit r15-1657-g0699de2a590f147218323c942e91ccf87273af14
Author: Carl Love
Date: Fri Jun 14 12:46:00 2024 -0400
rs6000, altivec-2-runnable.c update the require-effective-target
The test requires a minimum of Power8 vector HW and a compile level
of -O2. Update the dg test directives.
gcc/testsuite/ChangeLog:gcc/testsuite/ChangeLog:
* gcc.target/powerpc/altivec-2-runnable.c: Change the
require-effective-target for the test.
Diff:
---
gcc/testsuite/gcc.target/powerpc/altivec-2-runnable.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-2-runnable.c
b/gcc/testsuite/gcc.target/powerpc/altivec-2-runnable.c
index 17b23eb9d50..660669f69fd 100644
--- a/gcc/testsuite/gcc.target/powerpc/altivec-2-runnable.c
+++ b/gcc/testsuite/gcc.target/powerpc/altivec-2-runnable.c
@@ -1,6 +1,6 @@
-/* { dg-do run } */
-/* { dg-options "-mvsx" } */
-/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 }
} } */
+/* { dg-do run { target p8vector_hw } } */
+/* { dg-do compile { target { ! p8vector_hw } } } */
+/* { dg-options "-O2 -mdejagnu-cpu=power8" } */
/* { dg-require-effective-target powerpc_vsx } */
#include
[gcc r15-1658] rs6000, change altivec*-runnable.c test file names
https://gcc.gnu.org/g:e499aee4a35cb780ecd1d011661e4ee9bdcd2d48
commit r15-1658-ge499aee4a35cb780ecd1d011661e4ee9bdcd2d48
Author: Carl Love
Date: Fri Jun 21 11:56:36 2024 -0400
rs6000, change altivec*-runnable.c test file names
Changed the names of the test files.
gcc/testsuite/ChangeLog:gcc/testsuite/ChangeLog:
* gcc.target/powerpc/altivec-1-runnable.c: Change the name to
altivec-38.c.
* gcc.target/powerpc/altivec-2-runnable.c: Change the name to
p8vector-builtin-9.c.
Diff:
---
gcc/testsuite/gcc.target/powerpc/{altivec-1-runnable.c => altivec-38.c} | 0
.../gcc.target/powerpc/{altivec-2-runnable.c => p8vector-builtin-9.c} | 0
2 files changed, 0 insertions(+), 0 deletions(-)
diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-1-runnable.c
b/gcc/testsuite/gcc.target/powerpc/altivec-38.c
similarity index 100%
rename from gcc/testsuite/gcc.target/powerpc/altivec-1-runnable.c
rename to gcc/testsuite/gcc.target/powerpc/altivec-38.c
diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-2-runnable.c
b/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-9.c
similarity index 100%
rename from gcc/testsuite/gcc.target/powerpc/altivec-2-runnable.c
rename to gcc/testsuite/gcc.target/powerpc/p8vector-builtin-9.c
[gcc r15-1915] rs6000, Remove __builtin_vsx_cmple* builtins
https://gcc.gnu.org/g:7ed9a4593baeaaef6850c7ebcda677dabf229df1
commit r15-1915-g7ed9a4593baeaaef6850c7ebcda677dabf229df1
Author: Carl Love
Date: Tue Jul 9 13:12:39 2024 -0400
rs6000, Remove __builtin_vsx_cmple* builtins
The built-ins __builtin_vsx_cmple_u16qi, __builtin_vsx_cmple_u2di,
__builtin_vsx_cmple_u4si and __builtin_vsx_cmple_u8hi should take
unsigned arguments and return an unsigned result. The current definitions
take signed arguments and return signed results which is incorrect.
The signed and unsigned versions of __builtin_vsx_cmple* are not
documented in extend.texi. Also there are no test cases for the
built-ins.
Users can use the existing vec_cmple as PVIPR defines instead of
__builtin_vsx_cmple_u16qi, __builtin_vsx_cmple_u2di,
__builtin_vsx_cmple_u4si and __builtin_vsx_cmple_u8hi,
__builtin_vsx_cmple_16qi, __builtin_vsx_cmple_2di,
__builtin_vsx_cmple_4si and __builtin_vsx_cmple_8hi,
__builtin_altivec_cmple_1ti, __builtin_altivec_cmple_u1ti.
Hence these built-ins are redundant and are removed by this patch.
gcc/ChangeLog:
* config/rs6000/rs6000-builtin.cc (RS6000_BIF_CMPLE_16QI,
RS6000_BIF_CMPLE_U16QI, RS6000_BIF_CMPLE_8HI,
RS6000_BIF_CMPLE_U8HI, RS6000_BIF_CMPLE_4SI, RS6000_BIF_CMPLE_U4SI,
RS6000_BIF_CMPLE_2DI, RS6000_BIF_CMPLE_U2DI, RS6000_BIF_CMPLE_1TI,
RS6000_BIF_CMPLE_U1TI): Remove case statements.
* config/rs6000/rs6000-builtins.def (__builtin_vsx_cmple_16qi,
__builtin_vsx_cmple_2di, __builtin_vsx_cmple_4si,
__builtin_vsx_cmple_8hi, __builtin_vsx_cmple_u16qi,
__builtin_vsx_cmple_u2di, __builtin_vsx_cmple_u4si,
__builtin_vsx_cmple_u8hi): Remove buit-in definitions.
Diff:
---
gcc/config/rs6000/rs6000-builtin.cc | 13 -
gcc/config/rs6000/rs6000-builtins.def | 30 --
2 files changed, 43 deletions(-)
diff --git a/gcc/config/rs6000/rs6000-builtin.cc
b/gcc/config/rs6000/rs6000-builtin.cc
index bb9da68edc73..e68b94f3d52c 100644
--- a/gcc/config/rs6000/rs6000-builtin.cc
+++ b/gcc/config/rs6000/rs6000-builtin.cc
@@ -2030,19 +2030,6 @@ rs6000_gimple_fold_builtin (gimple_stmt_iterator *gsi)
fold_compare_helper (gsi, GT_EXPR, stmt);
return true;
-case RS6000_BIF_CMPLE_16QI:
-case RS6000_BIF_CMPLE_U16QI:
-case RS6000_BIF_CMPLE_8HI:
-case RS6000_BIF_CMPLE_U8HI:
-case RS6000_BIF_CMPLE_4SI:
-case RS6000_BIF_CMPLE_U4SI:
-case RS6000_BIF_CMPLE_2DI:
-case RS6000_BIF_CMPLE_U2DI:
-case RS6000_BIF_CMPLE_1TI:
-case RS6000_BIF_CMPLE_U1TI:
- fold_compare_helper (gsi, LE_EXPR, stmt);
- return true;
-
/* flavors of vec_splat_[us]{8,16,32}. */
case RS6000_BIF_VSPLTISB:
case RS6000_BIF_VSPLTISH:
diff --git a/gcc/config/rs6000/rs6000-builtins.def
b/gcc/config/rs6000/rs6000-builtins.def
index 736890fe6cb8..73064c9636e2 100644
--- a/gcc/config/rs6000/rs6000-builtins.def
+++ b/gcc/config/rs6000/rs6000-builtins.def
@@ -1337,30 +1337,6 @@
const vss __builtin_vsx_cmpge_u8hi (vus, vus);
CMPGE_U8HI vector_nltuv8hi {}
- const vsc __builtin_vsx_cmple_16qi (vsc, vsc);
-CMPLE_16QI vector_ngtv16qi {}
-
- const vsll __builtin_vsx_cmple_2di (vsll, vsll);
-CMPLE_2DI vector_ngtv2di {}
-
- const vsi __builtin_vsx_cmple_4si (vsi, vsi);
-CMPLE_4SI vector_ngtv4si {}
-
- const vss __builtin_vsx_cmple_8hi (vss, vss);
-CMPLE_8HI vector_ngtv8hi {}
-
- const vsc __builtin_vsx_cmple_u16qi (vsc, vsc);
-CMPLE_U16QI vector_ngtuv16qi {}
-
- const vsll __builtin_vsx_cmple_u2di (vsll, vsll);
-CMPLE_U2DI vector_ngtuv2di {}
-
- const vsi __builtin_vsx_cmple_u4si (vsi, vsi);
-CMPLE_U4SI vector_ngtuv4si {}
-
- const vss __builtin_vsx_cmple_u8hi (vss, vss);
-CMPLE_U8HI vector_ngtuv8hi {}
-
const vd __builtin_vsx_concat_2df (double, double);
CONCAT_2DF vsx_concat_v2df {}
@@ -3117,12 +3093,6 @@
const vbq __builtin_altivec_cmpge_u1ti (vuq, vuq);
CMPGE_U1TI vector_nltuv1ti {}
- const vbq __builtin_altivec_cmple_1ti (vsq, vsq);
-CMPLE_1TI vector_ngtv1ti {}
-
- const vbq __builtin_altivec_cmple_u1ti (vuq, vuq);
-CMPLE_U1TI vector_ngtuv1ti {}
-
const unsigned long long __builtin_altivec_cntmbb (vuc, const int<1>);
VCNTMBB vec_cntmb_v16qi {}
[gcc r15-1916] rs6000, Remove __builtin_vsx_xvcv{sp{sx, u}ws, dpuxds_uns}
https://gcc.gnu.org/g:224cc560a6ac19c9454038efe6230096b46f4806
commit r15-1916-g224cc560a6ac19c9454038efe6230096b46f4806
Author: Carl Love
Date: Tue Jul 9 13:17:16 2024 -0400
rs6000, Remove __builtin_vsx_xvcv{sp{sx,u}ws,dpuxds_uns}
The built-in __builtin_vsx_xvcvspsxws is covered by built-in vec_signed
built-in that is documented in the PVIPR. The __builtin_vsx_xvcvspsxws
built-in is not documented and there are no test cases for it.
The built-in __builtin_vsx_xvcvdpuxds_uns is redundant as it is covered by
vec_unsigned, remove.
The __builtin_vsx_xvcvspuxws is redundant as it is covered by
vec_unsigned, remove.
The built-in __builtin_vsx_xvcvdpsxws is redundant as it is covered by
vec_signed{e,o}, remove.
The built-in __builtin_vsx_xvcvdpuxws is redundant as it is covered by
vec_unsigned{e,o}, remove.
This patch removes the redundant built-ins.
gcc/ChangeLog:
* config/rs6000/rs6000-builtins.def (__builtin_vsx_xvcvspsxws,
__builtin_vsx_xvcvdpuxds_uns, __builtin_vsx_xvcvspuxws,
__builtin_vsx_xvcvdpsxws, __builtin_vsx_xvcvdpuxws): Remove
built-in definitions.
Diff:
---
gcc/config/rs6000/rs6000-builtins.def | 15 ---
1 file changed, 15 deletions(-)
diff --git a/gcc/config/rs6000/rs6000-builtins.def
b/gcc/config/rs6000/rs6000-builtins.def
index 73064c9636e2..465a43038fd2 100644
--- a/gcc/config/rs6000/rs6000-builtins.def
+++ b/gcc/config/rs6000/rs6000-builtins.def
@@ -1688,36 +1688,21 @@
const vsll __builtin_vsx_xvcvdpsxds_scale (vd, const int);
XVCVDPSXDS_SCALE vsx_xvcvdpsxds_scale {}
- const vsi __builtin_vsx_xvcvdpsxws (vd);
-XVCVDPSXWS vsx_xvcvdpsxws {}
-
const vsll __builtin_vsx_xvcvdpuxds (vd);
XVCVDPUXDS vsx_fixuns_truncv2dfv2di2 {}
const vsll __builtin_vsx_xvcvdpuxds_scale (vd, const int);
XVCVDPUXDS_SCALE vsx_xvcvdpuxds_scale {}
- const vull __builtin_vsx_xvcvdpuxds_uns (vd);
-XVCVDPUXDS_UNS vsx_fixuns_truncv2dfv2di2 {}
-
- const vsi __builtin_vsx_xvcvdpuxws (vd);
-XVCVDPUXWS vsx_xvcvdpuxws {}
-
const vd __builtin_vsx_xvcvspdp (vf);
XVCVSPDP vsx_xvcvspdp {}
const vsll __builtin_vsx_xvcvspsxds (vf);
XVCVSPSXDS vsx_xvcvspsxds {}
- const vsi __builtin_vsx_xvcvspsxws (vf);
-XVCVSPSXWS vsx_fix_truncv4sfv4si2 {}
-
const vsll __builtin_vsx_xvcvspuxds (vf);
XVCVSPUXDS vsx_xvcvspuxds {}
- const vsi __builtin_vsx_xvcvspuxws (vf);
-XVCVSPUXWS vsx_fixuns_truncv4sfv4si2 {}
-
const vd __builtin_vsx_xvcvsxddp (vsll);
XVCVSXDDP vsx_floatv2div2df2 {}
[gcc r15-1917] rs6000, fix error in unsigned vector float to unsigned int built-in definitions
https://gcc.gnu.org/g:6031e34af130d114a7a3de0108fdb39360e8b1b3
commit r15-1917-g6031e34af130d114a7a3de0108fdb39360e8b1b3
Author: Carl Love
Date: Tue Jul 9 13:17:28 2024 -0400
rs6000, fix error in unsigned vector float to unsigned int built-in
definitions
The built-in __builtin_vsx_vunsigned_v2df is supposed to take a vector of
doubles and return a vector of unsigned long long ints. Similarly
__builtin_vsx_vunsigned_v4sf takes a vector of floats an is supposed to
return a vector of unsinged ints. The definitions are using the signed
version of the instructions not the unsigned version of the instruction.
The results should also be unsigned. The built-ins are used by the
overloaded vec_unsigned built-in which has an unsigned result.
Similarly the built-ins __builtin_vsx_vunsignede_v2df and
__builtin_vsx_vunsignedo_v2df are supposed to return an unsigned result.
If the floating point argument is negative, the unsigned result is zero.
The built-ins are used in the overloaded built-in vec_unsignede and
vec_unsignedo respectively.
Add a test cases for a negative floating point arguments for each of the
above built-ins.
gcc/ChangeLog:
* config/rs6000/rs6000-builtins.def (__builtin_vsx_vunsigned_v2df,
__builtin_vsx_vunsigned_v4sf, __builtin_vsx_vunsignede_v2df,
__builtin_vsx_vunsignedo_v2df): Change the result type to unsigned.
gcc/testsuite/ChangeLog:
* gcc.target/powerpc/builtins-3-runnable.c: Add tests for
vec_unsignede and vec_unsignedo with negative arguments.
Diff:
---
gcc/config/rs6000/rs6000-builtins.def | 12 -
.../gcc.target/powerpc/builtins-3-runnable.c | 30 +++---
2 files changed, 33 insertions(+), 9 deletions(-)
diff --git a/gcc/config/rs6000/rs6000-builtins.def
b/gcc/config/rs6000/rs6000-builtins.def
index 465a43038fd2..f0aee29f1a1d 100644
--- a/gcc/config/rs6000/rs6000-builtins.def
+++ b/gcc/config/rs6000/rs6000-builtins.def
@@ -1580,16 +1580,16 @@
const vsi __builtin_vsx_vsignedo_v2df (vd);
VEC_VSIGNEDO_V2DF vsignedo_v2df {}
- const vsll __builtin_vsx_vunsigned_v2df (vd);
-VEC_VUNSIGNED_V2DF vsx_xvcvdpsxds {}
+ const vull __builtin_vsx_vunsigned_v2df (vd);
+VEC_VUNSIGNED_V2DF vsx_xvcvdpuxds {}
- const vsi __builtin_vsx_vunsigned_v4sf (vf);
-VEC_VUNSIGNED_V4SF vsx_xvcvspsxws {}
+ const vui __builtin_vsx_vunsigned_v4sf (vf);
+VEC_VUNSIGNED_V4SF vsx_xvcvspuxws {}
- const vsi __builtin_vsx_vunsignede_v2df (vd);
+ const vui __builtin_vsx_vunsignede_v2df (vd);
VEC_VUNSIGNEDE_V2DF vunsignede_v2df {}
- const vsi __builtin_vsx_vunsignedo_v2df (vd);
+ const vui __builtin_vsx_vunsignedo_v2df (vd);
VEC_VUNSIGNEDO_V2DF vunsignedo_v2df {}
const vf __builtin_vsx_xscvdpsp (double);
diff --git a/gcc/testsuite/gcc.target/powerpc/builtins-3-runnable.c
b/gcc/testsuite/gcc.target/powerpc/builtins-3-runnable.c
index 0231a1fd086b..5dcdfbee7916 100644
--- a/gcc/testsuite/gcc.target/powerpc/builtins-3-runnable.c
+++ b/gcc/testsuite/gcc.target/powerpc/builtins-3-runnable.c
@@ -313,6 +313,14 @@ int main()
test_unsigned_int_result (ALL, vec_uns_int_result,
vec_uns_int_expected);
+ /* Convert single precision float to unsigned int. Negative
+ arguments. */
+ vec_flt0 = (vector float){-14.930, -834.49, -3.3, -5.4};
+ vec_uns_int_expected = (vector unsigned int){0, 0, 0, 0};
+ vec_uns_int_result = vec_unsigned (vec_flt0);
+ test_unsigned_int_result (ALL, vec_uns_int_result,
+ vec_uns_int_expected);
+
/* Convert double precision float to long long unsigned int */
vec_dble0 = (vector double){124.930, 8134.49};
vec_ll_uns_int_expected = (vector long long unsigned int){124, 8134};
@@ -320,10 +328,18 @@ int main()
test_ll_unsigned_int_result (vec_ll_uns_int_result,
vec_ll_uns_int_expected);
+ /* Convert double precision float to long long unsigned int. Negative
+ arguments. */
+ vec_dble0 = (vector double){-24.93, -134.9};
+ vec_ll_uns_int_expected = (vector long long unsigned int){0, 0};
+ vec_ll_uns_int_result = vec_unsigned (vec_dble0);
+ test_ll_unsigned_int_result (vec_ll_uns_int_result,
+vec_ll_uns_int_expected);
+
/* Convert double precision vector float to vector unsigned int,
- even words */
- vec_dble0 = (vector double){3124.930, 8234.49};
- vec_uns_int_expected = (vector unsigned int){3124, 0, 8234, 0};
+ even words. Negative arguments */
+ vec_dble0 = (vector double){-124.930, -234.49};
+ vec_uns_int_expected = (vector unsigned int){0, 0, 0, 0};
vec_uns_int_result = vec_unsignede (vec_dble0);
test_unsigned_int_result (EVEN, vec_uns_int
[gcc r15-1918] rs6000, extend the current vec_{un, }signed{e, o} built-ins
https://gcc.gnu.org/g:b620845fff7d38bca3b79ca9f5a5d049eba9e7f8
commit r15-1918-gb620845fff7d38bca3b79ca9f5a5d049eba9e7f8
Author: Carl Love
Date: Tue Jul 9 13:17:44 2024 -0400
rs6000, extend the current vec_{un,}signed{e,o} built-ins
The built-ins __builtin_vsx_xvcvspsxds and __builtin_vsx_xvcvspuxds
convert a vector of floats to a vector of signed/unsigned long long ints.
Extend the existing vec_{un,}signed{e,o} built-ins to handle the argument
vector of floats to return a vector of even/odd signed/unsigned integers.
The define expands vsignede_v4sf, vsignedo_v4sf, vunsignede_v4sf,
vunsignedo_v4sf are added to support the new vec_{un,}signed{e,o}
built-ins.
The built-ins __builtin_vsx_xvcvspsxds and __builtin_vsx_xvcvspuxds are
now for internal use only. They are not documented and they do not
have test cases.
Add testcases and update documentation.
gcc/ChangeLog:
* config/rs6000/rs6000-builtins.def (__builtin_vsx_xvcvspsxds,
__builtin_vsx_xvcvspuxds): Rename to __builtin_vsignede_v4sf,
__builtin_vunsignede_v4sf respectively.
(XVCVSPSXDS, XVCVSPUXDS): Rename to VEC_VSIGNEDE_V4SF,
VEC_VUNSIGNEDE_V4SF respectively.
(__builtin_vsignedo_v4sf, __builtin_vunsignedo_v4sf): New
built-in definitions.
* config/rs6000/rs6000-overload.def (vec_signede, vec_signedo,
vec_unsignede, vec_unsignedo): Add new overloaded specifications.
* config/rs6000/vsx.md (vsignede_v4sf, vsignedo_v4sf,
vunsignede_v4sf, vunsignedo_v4sf): New define_expands.
* doc/extend.texi (vec_signedo, vec_signede, vec_unsignedo,
vec_unsignede): Add documentation for new overloaded built-ins to
convert vector float to vector {un,}signed long long.
gcc/testsuite/ChangeLog:
* gcc.target/powerpc/builtins-3-runnable.c
(test_unsigned_int_result, test_ll_unsigned_int_result): Add
new argument.
(vec_signede, vec_signedo, vec_unsignede, vec_unsignedo): New
tests for the overloaded built-ins.
Diff:
---
gcc/config/rs6000/rs6000-builtins.def | 14 ++--
gcc/config/rs6000/rs6000-overload.def | 8 +++
gcc/config/rs6000/vsx.md | 84 ++
gcc/doc/extend.texi| 10 +++
.../gcc.target/powerpc/builtins-3-runnable.c | 49 +++--
5 files changed, 154 insertions(+), 11 deletions(-)
diff --git a/gcc/config/rs6000/rs6000-builtins.def
b/gcc/config/rs6000/rs6000-builtins.def
index f0aee29f1a1d..5f353f5faeb2 100644
--- a/gcc/config/rs6000/rs6000-builtins.def
+++ b/gcc/config/rs6000/rs6000-builtins.def
@@ -1697,11 +1697,17 @@
const vd __builtin_vsx_xvcvspdp (vf);
XVCVSPDP vsx_xvcvspdp {}
- const vsll __builtin_vsx_xvcvspsxds (vf);
-XVCVSPSXDS vsx_xvcvspsxds {}
+ const vsll __builtin_vsignede_v4sf (vf);
+VEC_VSIGNEDE_V4SF vsignede_v4sf {}
- const vsll __builtin_vsx_xvcvspuxds (vf);
-XVCVSPUXDS vsx_xvcvspuxds {}
+ const vsll __builtin_vsignedo_v4sf (vf);
+VEC_VSIGNEDO_V4SF vsignedo_v4sf {}
+
+ const vull __builtin_vunsignede_v4sf (vf);
+VEC_VUNSIGNEDE_V4SF vunsignede_v4sf {}
+
+ const vull __builtin_vunsignedo_v4sf (vf);
+VEC_VUNSIGNEDO_V4SF vunsignedo_v4sf {}
const vd __builtin_vsx_xvcvsxddp (vsll);
XVCVSXDDP vsx_floatv2div2df2 {}
diff --git a/gcc/config/rs6000/rs6000-overload.def
b/gcc/config/rs6000/rs6000-overload.def
index 84bd9ae6554a..4d857bb1af3e 100644
--- a/gcc/config/rs6000/rs6000-overload.def
+++ b/gcc/config/rs6000/rs6000-overload.def
@@ -3307,10 +3307,14 @@
[VEC_SIGNEDE, vec_signede, __builtin_vec_vsignede]
vsi __builtin_vec_vsignede (vd);
VEC_VSIGNEDE_V2DF
+ vsll __builtin_vec_vsignede (vf);
+VEC_VSIGNEDE_V4SF
[VEC_SIGNEDO, vec_signedo, __builtin_vec_vsignedo]
vsi __builtin_vec_vsignedo (vd);
VEC_VSIGNEDO_V2DF
+ vsll __builtin_vec_vsignedo (vf);
+VEC_VSIGNEDO_V4SF
[VEC_SIGNEXTI, vec_signexti, __builtin_vec_signexti]
vsi __builtin_vec_signexti (vsc);
@@ -4433,10 +4437,14 @@
[VEC_UNSIGNEDE, vec_unsignede, __builtin_vec_vunsignede]
vui __builtin_vec_vunsignede (vd);
VEC_VUNSIGNEDE_V2DF
+ vull __builtin_vec_vunsignede (vf);
+VEC_VUNSIGNEDE_V4SF
[VEC_UNSIGNEDO, vec_unsignedo, __builtin_vec_vunsignedo]
vui __builtin_vec_vunsignedo (vd);
VEC_VUNSIGNEDO_V2DF
+ vull __builtin_vec_vunsignedo (vf);
+VEC_VUNSIGNEDO_V4SF
[VEC_VEE, vec_extract_exp, __builtin_vec_extract_exp]
vui __builtin_vec_extract_exp (vf);
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 23ce5c740510..8001d1778b89 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -2704,6 +2704,90 @@
DONE;
})
+;; Convert float vector even elements to signed long long vector
+(define_expand "vsignede_v4sf"
+ [(match_operand:V2D
[gcc r15-1919] rs6000, Remove redundant vector float/double type conversions
https://gcc.gnu.org/g:fd9fdb33ae252ec34cc33675433eb56637905257
commit r15-1919-gfd9fdb33ae252ec34cc33675433eb56637905257
Author: Carl Love
Date: Tue Jul 9 13:29:31 2024 -0400
rs6000, Remove redundant vector float/double type conversions
The following built-ins are redundant as they are covered by another
overloaded built-in.
__builtin_vsx_xvcvspdp covered by vec_double{e,o}
__builtin_vsx_xvcvdpsp covered by vec_float{e,o}
__builtin_vsx_xvcvsxwdp covered by vec_double{e,o}
__builtin_vsx_xvcvuxddp_uns covered by vec_double
Remove the redundant built-ins. They are not documented nor do they have
test cases.
gcc/ChangeLog:
* config/rs6000/rs6000-builtins.def (__builtin_vsx_xvcvspdp,
__builtin_vsx_xvcvdpsp, __builtin_vsx_xvcvsxwdp,
__builtin_vsx_xvcvuxddp_uns): Remove.
Diff:
---
gcc/config/rs6000/rs6000-builtins.def | 12
1 file changed, 12 deletions(-)
diff --git a/gcc/config/rs6000/rs6000-builtins.def
b/gcc/config/rs6000/rs6000-builtins.def
index 5f353f5faeb2..cd629c654986 100644
--- a/gcc/config/rs6000/rs6000-builtins.def
+++ b/gcc/config/rs6000/rs6000-builtins.def
@@ -1679,9 +1679,6 @@
const signed int __builtin_vsx_xvcmpgtsp_p (signed int, vf, vf);
XVCMPGTSP_P vector_gt_v4sf_p {pred}
- const vf __builtin_vsx_xvcvdpsp (vd);
-XVCVDPSP vsx_xvcvdpsp {}
-
const vsll __builtin_vsx_xvcvdpsxds (vd);
XVCVDPSXDS vsx_fix_truncv2dfv2di2 {}
@@ -1694,9 +1691,6 @@
const vsll __builtin_vsx_xvcvdpuxds_scale (vd, const int);
XVCVDPUXDS_SCALE vsx_xvcvdpuxds_scale {}
- const vd __builtin_vsx_xvcvspdp (vf);
-XVCVSPDP vsx_xvcvspdp {}
-
const vsll __builtin_vsignede_v4sf (vf);
VEC_VSIGNEDE_V4SF vsignede_v4sf {}
@@ -1718,9 +1712,6 @@
const vf __builtin_vsx_xvcvsxdsp (vsll);
XVCVSXDSP vsx_xvcvsxdsp {}
- const vd __builtin_vsx_xvcvsxwdp (vsi);
-XVCVSXWDP vsx_xvcvsxwdp {}
-
const vf __builtin_vsx_xvcvsxwsp (vsi);
XVCVSXWSP vsx_floatv4siv4sf2 {}
@@ -1730,9 +1721,6 @@
const vd __builtin_vsx_xvcvuxddp_scale (vsll, const int<5>);
XVCVUXDDP_SCALE vsx_xvcvuxddp_scale {}
- const vd __builtin_vsx_xvcvuxddp_uns (vull);
-XVCVUXDDP_UNS vsx_floatunsv2div2df2 {}
-
const vf __builtin_vsx_xvcvuxdsp (vull);
XVCVUXDSP vsx_xvcvuxdsp {}
[gcc r15-1920] rs6000, remove duplicated built-ins of vecmergl and vec_mergeh
https://gcc.gnu.org/g:8d6326eeb773076643d9babf55f7cca19968313e
commit r15-1920-g8d6326eeb773076643d9babf55f7cca19968313e
Author: Carl Love
Date: Tue Jul 9 13:31:12 2024 -0400
rs6000, remove duplicated built-ins of vecmergl and vec_mergeh
The following undocumented built-ins are same as existing documented
overloaded builtins.
const vf __builtin_vsx_xxmrghw (vf, vf);
same as vf __builtin_vec_mergeh (vf, vf); (overloaded vec_mergeh)
const vsi __builtin_vsx_xxmrghw_4si (vsi, vsi);
same as vsi __builtin_vec_mergeh (vsi, vsi); (overloaded vec_mergeh)
const vf __builtin_vsx_xxmrglw (vf, vf);
same as vf __builtin_vec_mergel (vf, vf); (overloaded vec_mergel)
const vsi __builtin_vsx_xxmrglw_4si (vsi, vsi);
same as vsi __builtin_vec_mergel (vsi, vsi); (overloaded vec_mergel)
This patch removes the duplicate built-in definitions so only the
documented built-ins will be available for use. The case statements in
rs6000_gimple_fold_builtin are removed as they are no longer needed. The
patch removes the now unused define_expands for vsx_xxmrghw_ and
vsx_xxmrglw_.
gcc/ChangeLog:
* config/rs6000/rs6000-builtins.def (__builtin_vsx_xxmrghw,
__builtin_vsx_xxmrghw_4si, __builtin_vsx_xxmrglw,
__builtin_vsx_xxmrglw_4si, __builtin_vsx_xxsel_16qi): Remove
built-in definition.
* config/rs6000/rs6000-builtin.cc (rs6000_gimple_fold_builtin):
remove case entries RS6000_BIF_XXMRGLW_4SI,
RS6000_BIF_XXMRGLW_4SF, RS6000_BIF_XXMRGHW_4SI,
RS6000_BIF_XXMRGHW_4SF.
* config/rs6000/vsx.md (vsx_xxmrghw_, vsx_xxmrglw_):
Remove unused define_expands.
Diff:
---
gcc/config/rs6000/rs6000-builtin.cc | 4
gcc/config/rs6000/rs6000-builtins.def | 12 --
gcc/config/rs6000/vsx.md | 45 ---
3 files changed, 61 deletions(-)
diff --git a/gcc/config/rs6000/rs6000-builtin.cc
b/gcc/config/rs6000/rs6000-builtin.cc
index e68b94f3d52c..646e740774eb 100644
--- a/gcc/config/rs6000/rs6000-builtin.cc
+++ b/gcc/config/rs6000/rs6000-builtin.cc
@@ -2100,20 +2100,16 @@ rs6000_gimple_fold_builtin (gimple_stmt_iterator *gsi)
/* vec_mergel (integrals). */
case RS6000_BIF_VMRGLH:
case RS6000_BIF_VMRGLW:
-case RS6000_BIF_XXMRGLW_4SI:
case RS6000_BIF_VMRGLB:
case RS6000_BIF_VEC_MERGEL_V2DI:
-case RS6000_BIF_XXMRGLW_4SF:
case RS6000_BIF_VEC_MERGEL_V2DF:
fold_mergehl_helper (gsi, stmt, 1);
return true;
/* vec_mergeh (integrals). */
case RS6000_BIF_VMRGHH:
case RS6000_BIF_VMRGHW:
-case RS6000_BIF_XXMRGHW_4SI:
case RS6000_BIF_VMRGHB:
case RS6000_BIF_VEC_MERGEH_V2DI:
-case RS6000_BIF_XXMRGHW_4SF:
case RS6000_BIF_VEC_MERGEH_V2DF:
fold_mergehl_helper (gsi, stmt, 0);
return true;
diff --git a/gcc/config/rs6000/rs6000-builtins.def
b/gcc/config/rs6000/rs6000-builtins.def
index cd629c654986..e89319badd0e 100644
--- a/gcc/config/rs6000/rs6000-builtins.def
+++ b/gcc/config/rs6000/rs6000-builtins.def
@@ -1880,18 +1880,6 @@
const signed int __builtin_vsx_xvtsqrtsp_fg (vf);
XVTSQRTSP_FG vsx_tsqrtv4sf2_fg {}
- const vf __builtin_vsx_xxmrghw (vf, vf);
-XXMRGHW_4SF vsx_xxmrghw_v4sf {}
-
- const vsi __builtin_vsx_xxmrghw_4si (vsi, vsi);
-XXMRGHW_4SI vsx_xxmrghw_v4si {}
-
- const vf __builtin_vsx_xxmrglw (vf, vf);
-XXMRGLW_4SF vsx_xxmrglw_v4sf {}
-
- const vsi __builtin_vsx_xxmrglw_4si (vsi, vsi);
-XXMRGLW_4SI vsx_xxmrglw_v4si {}
-
const vsc __builtin_vsx_xxpermdi_16qi (vsc, vsc, const int<2>);
XXPERMDI_16QI vsx_xxpermdi_v16qi {}
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 8001d1778b89..7892477fa922 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -4896,51 +4896,6 @@
}
[(set_attr "type" "vecperm")])
-;; V4SF/V4SI interleave
-(define_expand "vsx_xxmrghw_"
- [(set (match_operand:VSX_W 0 "vsx_register_operand" "=wa")
-(vec_select:VSX_W
- (vec_concat:
- (match_operand:VSX_W 1 "vsx_register_operand" "wa")
- (match_operand:VSX_W 2 "vsx_register_operand" "wa"))
- (parallel [(const_int 0) (const_int 4)
-(const_int 1) (const_int 5)])))]
- "VECTOR_MEM_VSX_P (mode)"
-{
- if (BYTES_BIG_ENDIAN)
-emit_insn (gen_altivec_vmrghw_direct_v4si_be (operands[0],
- operands[1],
- operands[2]));
- else
-emit_insn (gen_altivec_vmrglw_direct_v4si_le (operands[0],
- operands[2],
- operands[1]));
- DONE;
-}
- [(set_attr "type" "vecperm")])
-
-(define_expand "vsx_xxmrglw_"
- [(set (match_operand:VSX_W 0 "vsx_register_operand" "=wa")
- (vec_select
[gcc r15-1921] rs6000, add overloaded vec_sel with int128 arguments
https://gcc.gnu.org/g:807bed024d03f73bc1cf47ac8f23da9307c88464
commit r15-1921-g807bed024d03f73bc1cf47ac8f23da9307c88464
Author: Carl Love
Date: Tue Jul 9 13:31:22 2024 -0400
rs6000, add overloaded vec_sel with int128 arguments
Extend the vec_sel built-in to take three signed/unsigned/bool int128
arguments and return a signed/unsigned/bool int128 result.
Extending the vec_sel built-in makes the existing buit-ins
__builtin_vsx_xxsel_1ti and __builtin_vsx_xxsel_1ti_uns obsolete. The
patch removes these built-ins.
The patch adds documentation and test cases for the new overloaded
vec_sel built-ins.
gcc/ChangeLog:
* config/rs6000/rs6000-builtins.def (__builtin_vsx_xxsel_1ti,
__builtin_vsx_xxsel_1ti_uns): Remove built-in definitions.
* config/rs6000/rs6000-overload.def (vec_sel): Add new
overloaded vector signed, unsigned and bool 128-bit definitions.
* doc/extend.texi (vec_sel): Add documentation for new instances
with signed, unsigned and bool 129-bit bool arguments.
gcc/testsuite/ChangeLog:
* gcc.target/powerpc/builtins-10-runnable.c: New runnable test
file.
* gcc.target/powerpc/builtins-10.c: New compile only test file.
Diff:
---
gcc/config/rs6000/rs6000-builtins.def | 6 -
gcc/config/rs6000/rs6000-overload.def | 12 ++
gcc/doc/extend.texi| 20 ++
.../gcc.target/powerpc/builtins-10-runnable.c | 220 +
gcc/testsuite/gcc.target/powerpc/builtins-10.c | 63 ++
5 files changed, 315 insertions(+), 6 deletions(-)
diff --git a/gcc/config/rs6000/rs6000-builtins.def
b/gcc/config/rs6000/rs6000-builtins.def
index e89319badd0e..c62df9e4b685 100644
--- a/gcc/config/rs6000/rs6000-builtins.def
+++ b/gcc/config/rs6000/rs6000-builtins.def
@@ -1907,12 +1907,6 @@
const vuc __builtin_vsx_xxsel_16qi_uns (vuc, vuc, vuc);
XXSEL_16QI_UNS vector_select_v16qi_uns {}
- const vsq __builtin_vsx_xxsel_1ti (vsq, vsq, vsq);
-XXSEL_1TI vector_select_v1ti {}
-
- const vsq __builtin_vsx_xxsel_1ti_uns (vsq, vsq, vsq);
-XXSEL_1TI_UNS vector_select_v1ti_uns {}
-
const vd __builtin_vsx_xxsel_2df (vd, vd, vd);
XXSEL_2DF vector_select_v2df {}
diff --git a/gcc/config/rs6000/rs6000-overload.def
b/gcc/config/rs6000/rs6000-overload.def
index 4d857bb1af3e..855b9aa73cce 100644
--- a/gcc/config/rs6000/rs6000-overload.def
+++ b/gcc/config/rs6000/rs6000-overload.def
@@ -3266,6 +3266,18 @@
VSEL_2DI_UNS VSEL_2DI_BB
vbll __builtin_vec_sel (vbll, vbll, vull);
VSEL_2DI_UNS VSEL_2DI_BU
+ vsq __builtin_vec_sel (vsq, vsq, vbq);
+VSEL_1TI VSEL_1TI_B
+ vsq __builtin_vec_sel (vsq, vsq, vuq);
+VSEL_1TI VSEL_1TI_U
+ vuq __builtin_vec_sel (vuq, vuq, vbq);
+VSEL_1TI_UNS VSEL_1TI_UB
+ vuq __builtin_vec_sel (vuq, vuq, vuq);
+VSEL_1TI_UNS VSEL_1TI_UU
+ vbq __builtin_vec_sel (vbq, vbq, vbq);
+VSEL_1TI_UNS VSEL_1TI_BB
+ vbq __builtin_vec_sel (vbq, vbq, vuq);
+VSEL_1TI_UNS VSEL_1TI_BU
vf __builtin_vec_sel (vf, vf, vbi);
VSEL_4SF VSEL_4SF_B
vf __builtin_vec_sel (vf, vf, vui);
diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
index 98e392ae..6ab69840f3f7 100644
--- a/gcc/doc/extend.texi
+++ b/gcc/doc/extend.texi
@@ -21444,6 +21444,26 @@ Additional built-in functions are available for the
64-bit PowerPC
family of processors, for efficient use of 128-bit floating point
(@code{__float128}) values.
+Vector select
+
+@smallexample
+vector signed __int128 vec_sel (vector signed __int128,
+ vector signed __int128, vector bool __int128);
+vector signed __int128 vec_sel (vector signed __int128,
+ vector signed __int128, vector unsigned __int128);
+vector unsigned __int128 vec_sel (vector unsigned __int128,
+ vector unsigned __int128, vector bool __int128);
+vector unsigned __int128 vec_sel (vector unsigned __int128,
+ vector unsigned __int128, vector unsigned __int128);
+vector bool __int128 vec_sel (vector bool __int128,
+ vector bool __int128, vector bool __int128);
+vector bool __int128 vec_sel (vector bool __int128,
+ vector bool __int128, vector unsigned __int128);
+@end smallexample
+
+The instance is an extension of the exiting overloaded built-in @code{vec_sel}
+that is documented in the PVIPR.
+
@node Basic PowerPC Built-in Functions Available on ISA 2.06
@subsubsection Basic PowerPC Built-in Functions Available on ISA 2.06
diff --git a/gcc/testsuite/gcc.target/powerpc/builtins-10-runnable.c
b/gcc/testsuite/gcc.target/powerpc/builtins-10-runnable.c
new file mode 100644
index ..dede08358e13
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/builtins-10-runnable.c
@@ -0,0 +1,220 @@
+/* { dg-do run } */
+/* { dg-require-effective-target vmx_hw } */
+/* { dg-options "-maltivec -O2 " } */
+
+#include
+
[gcc r15-1922] rs6000, remove the vec_xxsel built-ins, they are duplicates
https://gcc.gnu.org/g:52d56983d516975d945318b81e1d2600676bb780
commit r15-1922-g52d56983d516975d945318b81e1d2600676bb780
Author: Carl Love
Date: Tue Jul 9 13:31:34 2024 -0400
rs6000, remove the vec_xxsel built-ins, they are duplicates
The following undocumented built-ins are covered by the existing overloaded
vec_sel built-in definitions.
const vsc __builtin_vsx_xxsel_16qi (vsc, vsc, vsc);
same as vsc __builtin_vec_sel (vsc, vsc, vuc); (overloaded vec_sel)
const vuc __builtin_vsx_xxsel_16qi_uns (vuc, vuc, vuc);
same as vuc __builtin_vec_sel (vuc, vuc, vuc); (overloaded vec_sel)
const vd __builtin_vsx_xxsel_2df (vd, vd, vd);
same as vd __builtin_vec_sel (vd, vd, vull); (overloaded vec_sel)
const vsll __builtin_vsx_xxsel_2di (vsll, vsll, vsll);
same as vsll __builtin_vec_sel (vsll, vsll, vsll); (overloaded vec_sel)
const vull __builtin_vsx_xxsel_2di_uns (vull, vull, vull);
same as vull __builtin_vec_sel (vull, vull, vsll); (overloaded vec_sel)
const vf __builtin_vsx_xxsel_4sf (vf, vf, vf);
same as vf __builtin_vec_sel (vf, vf, vsi) (overloaded vec_sel)
const vsi __builtin_vsx_xxsel_4si (vsi, vsi, vsi);
same as vsi __builtin_vec_sel (vsi, vsi, vbi); (overloaded vec_sel)
const vui __builtin_vsx_xxsel_4si_uns (vui, vui, vui);
same as vui __builtin_vec_sel (vui, vui, vui); (overloaded vec_sel)
const vss __builtin_vsx_xxsel_8hi (vss, vss, vss);
same as vss __builtin_vec_sel (vss, vss, vbs); (overloaded vec_sel)
const vus __builtin_vsx_xxsel_8hi_uns (vus, vus, vus);
same as vus __builtin_vec_sel (vus, vus, vus); (overloaded vec_sel)
This patch removed the duplicate built-in definitions so users will only
use the documented vec_sel built-in. The __builtin_vsx_xxsel_[4si, 8hi,
16qi, 4sf, 2df] tests are also removed.
gcc/ChangeLog:
* config/rs6000/rs6000-builtins.def (__builtin_vsx_xxsel_16qi,
__builtin_vsx_xxsel_16qi_uns, __builtin_vsx_xxsel_2df,
__builtin_vsx_xxsel_2di,__builtin_vsx_xxsel_2di_uns,
__builtin_vsx_xxsel_4sf,__builtin_vsx_xxsel_4si,
__builtin_vsx_xxsel_4si_uns,__builtin_vsx_xxsel_8hi,
__builtin_vsx_xxsel_8hi_uns): Removebuilt-in definitions.
gcc/testsuite/ChangeLog:
* gcc.target/powerpc/vsx-builtin-3.c (__builtin_vsx_xxsel_4si,
__builtin_vsx_xxsel_8hi, __builtin_vsx_xxsel_16qi,
__builtin_vsx_xxsel_4sf, __builtin_vsx_xxsel_2df,
__builtin_vsx_xxsel): Change built-in call to overloaded built-in
call vec_sel.
Diff:
---
gcc/config/rs6000/rs6000-builtins.def| 30
gcc/testsuite/gcc.target/powerpc/vsx-builtin-3.c | 36 +---
2 files changed, 19 insertions(+), 47 deletions(-)
diff --git a/gcc/config/rs6000/rs6000-builtins.def
b/gcc/config/rs6000/rs6000-builtins.def
index c62df9e4b685..80fdc959698b 100644
--- a/gcc/config/rs6000/rs6000-builtins.def
+++ b/gcc/config/rs6000/rs6000-builtins.def
@@ -1901,36 +1901,6 @@
const vss __builtin_vsx_xxpermdi_8hi (vss, vss, const int<2>);
XXPERMDI_8HI vsx_xxpermdi_v8hi {}
- const vsc __builtin_vsx_xxsel_16qi (vsc, vsc, vsc);
-XXSEL_16QI vector_select_v16qi {}
-
- const vuc __builtin_vsx_xxsel_16qi_uns (vuc, vuc, vuc);
-XXSEL_16QI_UNS vector_select_v16qi_uns {}
-
- const vd __builtin_vsx_xxsel_2df (vd, vd, vd);
-XXSEL_2DF vector_select_v2df {}
-
- const vsll __builtin_vsx_xxsel_2di (vsll, vsll, vsll);
-XXSEL_2DI vector_select_v2di {}
-
- const vull __builtin_vsx_xxsel_2di_uns (vull, vull, vull);
-XXSEL_2DI_UNS vector_select_v2di_uns {}
-
- const vf __builtin_vsx_xxsel_4sf (vf, vf, vf);
-XXSEL_4SF vector_select_v4sf {}
-
- const vsi __builtin_vsx_xxsel_4si (vsi, vsi, vsi);
-XXSEL_4SI vector_select_v4si {}
-
- const vui __builtin_vsx_xxsel_4si_uns (vui, vui, vui);
-XXSEL_4SI_UNS vector_select_v4si_uns {}
-
- const vss __builtin_vsx_xxsel_8hi (vss, vss, vss);
-XXSEL_8HI vector_select_v8hi {}
-
- const vus __builtin_vsx_xxsel_8hi_uns (vus, vus, vus);
-XXSEL_8HI_UNS vector_select_v8hi_uns {}
-
const vsc __builtin_vsx_xxsldwi_16qi (vsc, vsc, const int<2>);
XXSLDWI_16QI vsx_xxsldwi_v16qi {}
diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-builtin-3.c
b/gcc/testsuite/gcc.target/powerpc/vsx-builtin-3.c
index 79d9343d12a2..5e3051841fee 100644
--- a/gcc/testsuite/gcc.target/powerpc/vsx-builtin-3.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsx-builtin-3.c
@@ -37,6 +37,8 @@
/* { dg-final { scan-assembler "xvcvsxdsp" } } */
/* { dg-final { scan-assembler "xvcvuxdsp" } } */
+#include
+
extern __vector int si[][4];
extern __vector short ss[][4];
extern __vector signed char sc[][4];
@@ -61,23 +63,23 @@ int do_sel(void)
{
int i = 0;
- si[i][0] = __builtin_vsx_xxse
[gcc r15-1923] rs6000, remove __builtin_vsx_vperm_* built-ins
https://gcc.gnu.org/g:7121926b20c2f62ff49e769e26b994180b0a16af
commit r15-1923-g7121926b20c2f62ff49e769e26b994180b0a16af
Author: Carl Love
Date: Tue Jul 9 13:31:52 2024 -0400
rs6000, remove __builtin_vsx_vperm_* built-ins
The undocumented built-ins:
__builtin_vsx_vperm_16qi_uns,
__builtin_vsx_vperm_1ti,
__builtin_vsx_vperm_1ti_uns,
__builtin_vsx_vperm_2df,
__builtin_vsx_vperm_2di,
__builtin_vsx_vperm_2di_uns,
__builtin_vsx_vperm_4sf,
__builtin_vsx_vperm_4si,
__builtin_vsx_vperm_4si_uns
are duplicats of the __builtin_altivec_* built-ins that are used by
the overloaded vec_perm built-in that is documented in the PVIPR.
gcc/ChangeLog:
* config/rs6000/rs6000-builtins.def (__builtin_vsx_vperm_16qi_uns,
__builtin_vsx_vperm_1ti, __builtin_vsx_vperm_1ti_uns,
__builtin_vsx_vperm_2df, __builtin_vsx_vperm_2di,
__builtin_vsx_vperm_2di_uns, __builtin_vsx_vperm_4sf,
__builtin_vsx_vperm_4si, __builtin_vsx_vperm_4si_uns): Remove
built-in definitions and comments.
gcc/testsuite/ChangeLog:
* gcc.target/powerpc/vsx-builtin-3.c (__builtin_vsx_vperm_16qi_uns,
__builtin_vsx_vperm_1ti, __builtin_vsx_vperm_1ti_uns,
__builtin_vsx_vperm_2df, __builtin_vsx_vperm_2di,
__builtin_vsx_vperm_2di_uns, __builtin_vsx_vperm_4sf,
__builtin_vsx_vperm_4si, __builtin_vsx_vperm_4si_uns,
__builtin_vsx_vperm): Change call to built-in to the overloaded
built-in vec_perm.
Diff:
---
gcc/config/rs6000/rs6000-builtins.def| 33
gcc/testsuite/gcc.target/powerpc/vsx-builtin-3.c | 22
2 files changed, 11 insertions(+), 44 deletions(-)
diff --git a/gcc/config/rs6000/rs6000-builtins.def
b/gcc/config/rs6000/rs6000-builtins.def
index 80fdc959698b..4b1f5522cf55 100644
--- a/gcc/config/rs6000/rs6000-builtins.def
+++ b/gcc/config/rs6000/rs6000-builtins.def
@@ -1529,39 +1529,6 @@
const vf __builtin_vsx_uns_floato_v2di (vsll);
UNS_FLOATO_V2DI unsfloatov2di {}
-; These are duplicates of __builtin_altivec_* counterparts, and are being
-; kept for backwards compatibility. The reason for their existence is
-; unclear. TODO: Consider deprecation/removal at some point.
- const vsc __builtin_vsx_vperm_16qi (vsc, vsc, vuc);
-VPERM_16QI_X altivec_vperm_v16qi {}
-
- const vuc __builtin_vsx_vperm_16qi_uns (vuc, vuc, vuc);
-VPERM_16QI_UNS_X altivec_vperm_v16qi_uns {}
-
- const vsq __builtin_vsx_vperm_1ti (vsq, vsq, vsc);
-VPERM_1TI_X altivec_vperm_v1ti {}
-
- const vsq __builtin_vsx_vperm_1ti_uns (vsq, vsq, vsc);
-VPERM_1TI_UNS_X altivec_vperm_v1ti_uns {}
-
- const vd __builtin_vsx_vperm_2df (vd, vd, vuc);
-VPERM_2DF_X altivec_vperm_v2df {}
-
- const vsll __builtin_vsx_vperm_2di (vsll, vsll, vuc);
-VPERM_2DI_X altivec_vperm_v2di {}
-
- const vull __builtin_vsx_vperm_2di_uns (vull, vull, vuc);
-VPERM_2DI_UNS_X altivec_vperm_v2di_uns {}
-
- const vf __builtin_vsx_vperm_4sf (vf, vf, vuc);
-VPERM_4SF_X altivec_vperm_v4sf {}
-
- const vsi __builtin_vsx_vperm_4si (vsi, vsi, vuc);
-VPERM_4SI_X altivec_vperm_v4si {}
-
- const vui __builtin_vsx_vperm_4si_uns (vui, vui, vuc);
-VPERM_4SI_UNS_X altivec_vperm_v4si_uns {}
-
const vss __builtin_vsx_vperm_8hi (vss, vss, vuc);
VPERM_8HI_X altivec_vperm_v8hi {}
diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-builtin-3.c
b/gcc/testsuite/gcc.target/powerpc/vsx-builtin-3.c
index 5e3051841fee..60f91aad23c2 100644
--- a/gcc/testsuite/gcc.target/powerpc/vsx-builtin-3.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsx-builtin-3.c
@@ -88,17 +88,17 @@ int do_perm(void)
{
int i = 0;
- si[i][0] = __builtin_vsx_vperm_4si (si[i][1], si[i][2], uc[i][3]); i++;
- ss[i][0] = __builtin_vsx_vperm_8hi (ss[i][1], ss[i][2], uc[i][3]); i++;
- sc[i][0] = __builtin_vsx_vperm_16qi (sc[i][1], sc[i][2], uc[i][3]); i++;
- f[i][0] = __builtin_vsx_vperm_4sf (f[i][1], f[i][2], uc[i][3]); i++;
- d[i][0] = __builtin_vsx_vperm_2df (d[i][1], d[i][2], uc[i][3]); i++;
-
- si[i][0] = __builtin_vsx_vperm (si[i][1], si[i][2], uc[i][3]); i++;
- ss[i][0] = __builtin_vsx_vperm (ss[i][1], ss[i][2], uc[i][3]); i++;
- sc[i][0] = __builtin_vsx_vperm (sc[i][1], sc[i][2], uc[i][3]); i++;
- f[i][0] = __builtin_vsx_vperm (f[i][1], f[i][2], uc[i][3]); i++;
- d[i][0] = __builtin_vsx_vperm (d[i][1], d[i][2], uc[i][3]); i++;
+ si[i][0] = vec_perm (si[i][1], si[i][2], uc[i][3]); i++;
+ ss[i][0] = vec_perm (ss[i][1], ss[i][2], uc[i][3]); i++;
+ sc[i][0] = vec_perm (sc[i][1], sc[i][2], uc[i][3]); i++;
+ f[i][0] = vec_perm (f[i][1], f[i][2], uc[i][3]); i++;
+ d[i][0] = vec_perm (d[i][1], d[i][2], uc[i][3]); i++;
+
+ si[i][0] = vec_perm (si[i][1], si[i][2], uc[i][3]); i++;
+ ss[i][0] = vec_perm (ss[i][1], ss[i][2], uc[i][3]); i++;
+ sc[i][0] = vec_perm (sc[i][1], sc[i][2], uc[i][3]); i++;
+ f[i][0] =
[gcc r15-1924] rs6000, remove __builtin_vsx_xvnegdp and __builtin_vsx_xvnegsp built-ins
https://gcc.gnu.org/g:ca4842f4f47dac33fb43def287d8ec5663fdf63f
commit r15-1924-gca4842f4f47dac33fb43def287d8ec5663fdf63f
Author: Carl Love
Date: Tue Jul 9 13:32:02 2024 -0400
rs6000, remove __builtin_vsx_xvnegdp and __builtin_vsx_xvnegsp built-ins
The undocumented __builtin_vsx_xvnegdp and __builtin_vsx_xvnegsp are
redundant. The overloaded vec_neg built-in provides the same
functionality. The two built-ins are not documented nor are there any
test cases for them.
Remove the definitions so users will use the overloaded vec_neg built-in
which is documented in the PVIPR.
gcc/ChangeLog:
* config/rs6000/rs6000-builtins.def (__builtin_vsx_xvnegdp,
__builtin_vsx_xvnegsp): Remove built-in definitions.
Diff:
---
gcc/config/rs6000/rs6000-builtins.def | 6 --
1 file changed, 6 deletions(-)
diff --git a/gcc/config/rs6000/rs6000-builtins.def
b/gcc/config/rs6000/rs6000-builtins.def
index 4b1f5522cf55..f1351cb3505e 100644
--- a/gcc/config/rs6000/rs6000-builtins.def
+++ b/gcc/config/rs6000/rs6000-builtins.def
@@ -1739,12 +1739,6 @@
const vf __builtin_vsx_xvnabssp (vf);
XVNABSSP vsx_nabsv4sf2 {}
- const vd __builtin_vsx_xvnegdp (vd);
-XVNEGDP negv2df2 {}
-
- const vf __builtin_vsx_xvnegsp (vf);
-XVNEGSP negv4sf2 {}
-
const vd __builtin_vsx_xvnmadddp (vd, vd, vd);
XVNMADDDP nfmav2df4 {}
[gcc r15-1925] rs6000, extend vec_xxpermdi built-in for __int128 args
https://gcc.gnu.org/g:c5b4bfe9bdb6fb614255b9a3b092a0b55076f862
commit r15-1925-gc5b4bfe9bdb6fb614255b9a3b092a0b55076f862
Author: Carl Love
Date: Tue Jul 9 13:32:10 2024 -0400
rs6000, extend vec_xxpermdi built-in for __int128 args
Add a new signed and unsigned int128 overloaded vector instances for
vec_xxpermdi:
__int128 vec_xxpermdi (__int128, __int128, const int);
__uint128 vec_xxpermdi (__uint128, __uint128, const int);
Update the documentation to include a reference to the new vector built-in
instances of vec_xxpermdi.
Add test cases for the new overloaded instances.
gcc/ChangeLog:
* config/rs6000/rs6000-overload.def (vec_xxpermdi): Add new
overloaded built-in instances of vector signed and unsigned
int128.
* doc/extend.texi: Add documentation for built-in instances of
vector signed and unsigned int128.
gcc/testsuite/ChangeLog:gcc/testsuite/ChangeLog:
* gcc.target/powerpc/vec_perm-runnable-i128.c: New test file.
Diff:
---
gcc/config/rs6000/rs6000-overload.def | 4 +
gcc/doc/extend.texi| 4 +
.../gcc.target/powerpc/vec_perm-runnable-i128.c| 229 +
3 files changed, 237 insertions(+)
diff --git a/gcc/config/rs6000/rs6000-overload.def
b/gcc/config/rs6000/rs6000-overload.def
index 855b9aa73cce..c4ecafc6f7ef 100644
--- a/gcc/config/rs6000/rs6000-overload.def
+++ b/gcc/config/rs6000/rs6000-overload.def
@@ -4936,6 +4936,10 @@
XXPERMDI_2DI XXPERMDI_VSLL
vull __builtin_vsx_xxpermdi (vull, vull, const int);
XXPERMDI_2DI XXPERMDI_VULL
+ vsq __builtin_vsx_xxpermdi (vsq, vsq, const int);
+XXPERMDI_1TI XXPERMDI_SQ
+ vuq __builtin_vsx_xxpermdi (vuq, vuq, const int);
+XXPERMDI_1TI XXPERMDI_UQ
vf __builtin_vsx_xxpermdi (vf, vf, const int);
XXPERMDI_4SF XXPERMDI_VF
vd __builtin_vsx_xxpermdi (vd, vd, const int);
diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
index 6ab69840f3f7..0b572afca720 100644
--- a/gcc/doc/extend.texi
+++ b/gcc/doc/extend.texi
@@ -22634,6 +22634,10 @@ void vec_vsx_st (vector bool char, int, signed char *);
vector double vec_xxpermdi (vector double, vector double, const int);
vector float vec_xxpermdi (vector float, vector float, const int);
+vector __int128 vec_xxpermdi (vector __int128,
+ vector __int128, const int);
+vector __uint128 vec_xxpermdi (vector __uint128,
+ vector __uint128, const int);
vector long long vec_xxpermdi (vector long long, vector long long, const int);
vector unsigned long long vec_xxpermdi (vector unsigned long long,
vector unsigned long long, const int);
diff --git a/gcc/testsuite/gcc.target/powerpc/vec_perm-runnable-i128.c
b/gcc/testsuite/gcc.target/powerpc/vec_perm-runnable-i128.c
new file mode 100644
index ..0e0d77bcb845
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec_perm-runnable-i128.c
@@ -0,0 +1,229 @@
+/* { dg-do run } */
+/* { dg-require-effective-target vmx_hw } */
+/* { dg-options "-maltivec -O2 " } */
+
+#include
+
+#define DEBUG 0
+
+#if DEBUG
+#include
+void print_i128 (unsigned __int128 val)
+{
+ printf(" 0x%016llx%016llx",
+ (unsigned long long)(val >> 64),
+ (unsigned long long)(val & 0x));
+}
+#endif
+
+extern void abort (void);
+
+union convert_union {
+ vector signed __int128s128;
+ vector unsigned __int128 u128;
+ char val[16];
+} convert;
+
+int check_u128_result(vector unsigned __int128 vresult_u128,
+ vector unsigned __int128 expected_vresult_u128)
+{
+ /* Use a for loop to check each byte manually so the test case will
+ run with ISA 2.06.
+
+ Return 1 if they match, 0 otherwise. */
+
+ int i;
+
+ union convert_union result;
+ union convert_union expected;
+
+ result.u128 = vresult_u128;
+ expected.u128 = expected_vresult_u128;
+
+ /* Check if each byte of the result and expected match. */
+ for (i = 0; i < 16; i++)
+{
+ if (result.val[i] != expected.val[i])
+ return 0;
+}
+ return 1;
+}
+
+int check_s128_result(vector signed __int128 vresult_s128,
+ vector signed __int128 expected_vresult_s128)
+{
+ /* Convert the arguments to unsigned, then check equality. */
+ union convert_union result;
+ union convert_union expected;
+
+ result.s128 = vresult_s128;
+ expected.s128 = expected_vresult_s128;
+
+ return check_u128_result (result.u128, expected.u128);
+}
+
+
+int
+main (int argc, char *argv [])
+{
+ int i;
+
+ vector signed __int128 src_va_s128;
+ vector signed __int128 src_vb_s128;
+ vector signed __int128 vresult_s128;
+ vector signed __int128 expected_vresult_s128;
+
+ vector unsigned __int128 src_va_u128;
+ vector unsigned __int128 src_vb_u128;
+ vector unsigned __int128 src_vc_u128;
+ vector unsigned __int128 vre
[gcc r15-1926] rs6000, remove __builtin_vsx_xvcmpeqsp_p built-in
https://gcc.gnu.org/g:5db91b3073895700380ae34c63b103a33fa635a6
commit r15-1926-g5db91b3073895700380ae34c63b103a33fa635a6
Author: Carl Love
Date: Tue Jul 9 13:32:19 2024 -0400
rs6000, remove __builtin_vsx_xvcmpeqsp_p built-in
The built-in __builtin_vsx_xvcmpeqsp_p is a duplicate of the overloaded
__builtin_altivec_vcmpeqfp_p built-in. The built-in is undocumented and
there are no test cases for it. The patch removes built-in
__builtin_vsx_xvcmpeqsp_p.
gcc/ChangeLog:
* config/rs6000/rs6000-builtins.def (__builtin_vsx_xvcmpeqsp_p):
Remove built-in definition.
Diff:
---
gcc/config/rs6000/rs6000-builtins.def | 3 ---
1 file changed, 3 deletions(-)
diff --git a/gcc/config/rs6000/rs6000-builtins.def
b/gcc/config/rs6000/rs6000-builtins.def
index f1351cb3505e..cec50e0d0fd4 100644
--- a/gcc/config/rs6000/rs6000-builtins.def
+++ b/gcc/config/rs6000/rs6000-builtins.def
@@ -1619,9 +1619,6 @@
const vf __builtin_vsx_xvcmpeqsp (vf, vf);
XVCMPEQSP vector_eqv4sf {}
- const signed int __builtin_vsx_xvcmpeqsp_p (signed int, vf, vf);
-XVCMPEQSP_P vector_eq_v4sf_p {pred}
-
const vd __builtin_vsx_xvcmpgedp (vd, vd);
XVCMPGEDP vector_gev2df {}
[gcc r15-1927] rs6000, remove vector set and vector init built-ins.
https://gcc.gnu.org/g:e611189899bb885a27ef8d17f77c02ada6c69069
commit r15-1927-ge611189899bb885a27ef8d17f77c02ada6c69069
Author: Carl Love
Date: Tue Jul 9 13:32:28 2024 -0400
rs6000, remove vector set and vector init built-ins.
The vector init built-ins:
__builtin_vec_init_v16qi, __builtin_vec_init_v8hi,
__builtin_vec_init_v4si, __builtin_vec_init_v4sf,
__builtin_vec_init_v2di, __builtin_vec_init_v2df,
__builtin_vec_init_v1ti
perform the same operation as initializing the vector in C code. For
example:
result_v4si = __builtin_vec_init_v4si (1, 2, 3, 4);
result_v4si = {1, 2, 3, 4};
These two constructs were tested and verified they generate identical
assembly instructions with no optimization and -O3 optimization.
The vector set built-ins:
__builtin_vec_set_v16qi, __builtin_vec_set_v8hi.
__builtin_vec_set_v4si, __builtin_vec_set_v4sf,
__builtin_vec_set_v1ti, __builtin_vec_set_v2di,
__builtin_vec_set_v2df
perform the same operation as setting a specific element in the vector in
C code. For example:
src_v4si = __builtin_vec_set_v4si (src_v4si, int_val, index);
src_v4si[index] = int_val;
The built-in actually generates more instructions than the inline C code
with no optimization but is identical with -O3 optimizations.
All of the above built-ins that are removed do not have test cases and
are not documented.
Built-ins __builtin_vec_set_v1ti __builtin_vec_set_v2di,
__builtin_vec_set_v2df are not removed as they are used in function
resolve_vec_insert() in file rs6000-c.cc.
The built-ins are removed as they don't provide any benefit over just
using C code.
The code to define the bif_init_bit, bif_is_init, as well as their uses
are removed. The function altivec_expand_vec_init_builtin is also removed.
gcc/ChangeLog:
* config/rs6000/rs6000-builtin.cc (altivec_expand_vec_init_builtin):
Remove the function.
(rs6000_expand_builtin): Remove the if bif_is_int check to call
the altivec_expand_vec_init_builtin function.
* config/rs6000/rs6000-builtins.def: Remove the attribute string
comment for init.
(__builtin_vec_init_v16qi,
__builtin_vec_init_v4sf, __builtin_vec_init_v4si,
__builtin_vec_init_v8hi, __builtin_vec_init_v1ti,
__builtin_vec_init_v2df, __builtin_vec_init_v2di,
__builtin_vec_set_v16qi, __builtin_vec_set_v4sf,
__builtin_vec_set_v4si, __builtin_vec_set_v8hi): Remove
built-in definitions.
* config/rs6000/rs6000-gen-builtins.cc: Remove comment for init
attribute string.
(struct attrinfo): Remove isinit entry.
(parse_bif_attrs): Remove the if statement to check for attribute
init.
(ifdef DEBUG): Remove print for init attribute string.
(write_decls): Remove print for define bif_init_bit and
define for bif_is_init.
(write_bif_static_init): Remove if bifp->attrs.isinit statement.
Diff:
---
gcc/config/rs6000/rs6000-builtin.cc | 40
gcc/config/rs6000/rs6000-builtins.def| 45 +++-
gcc/config/rs6000/rs6000-gen-builtins.cc | 29 +++-
3 files changed, 14 insertions(+), 100 deletions(-)
diff --git a/gcc/config/rs6000/rs6000-builtin.cc
b/gcc/config/rs6000/rs6000-builtin.cc
index 646e740774eb..0a24d20a58c4 100644
--- a/gcc/config/rs6000/rs6000-builtin.cc
+++ b/gcc/config/rs6000/rs6000-builtin.cc
@@ -2313,43 +2313,6 @@ altivec_expand_predicate_builtin (enum insn_code icode,
tree exp, rtx target)
return target;
}
-/* Expand vec_init builtin. */
-static rtx
-altivec_expand_vec_init_builtin (tree type, tree exp, rtx target)
-{
- machine_mode tmode = TYPE_MODE (type);
- machine_mode inner_mode = GET_MODE_INNER (tmode);
- int i, n_elt = GET_MODE_NUNITS (tmode);
-
- gcc_assert (VECTOR_MODE_P (tmode));
- gcc_assert (n_elt == call_expr_nargs (exp));
-
- if (!target || !register_operand (target, tmode))
-target = gen_reg_rtx (tmode);
-
- /* If we have a vector compromised of a single element, such as V1TImode, do
- the initialization directly. */
- if (n_elt == 1 && GET_MODE_SIZE (tmode) == GET_MODE_SIZE (inner_mode))
-{
- rtx x = expand_normal (CALL_EXPR_ARG (exp, 0));
- emit_move_insn (target, gen_lowpart (tmode, x));
-}
- else
-{
- rtvec v = rtvec_alloc (n_elt);
-
- for (i = 0; i < n_elt; ++i)
- {
- rtx x = expand_normal (CALL_EXPR_ARG (exp, i));
- RTVEC_ELT (v, i) = gen_lowpart (inner_mode, x);
- }
-
- rs6000_expand_vector_init (target, gen_rtx_PARALLEL (tmode, v));
-}
-
- return target;
-}
-
/* Return the integer constant in ARG. Constrain it to be in th
[gcc r15-2143] rs6000, update effective target for tests builtins-10*.c and vec_perm-runnable-i128.c
https://gcc.gnu.org/g:c19237614b42ddae80a9a24e0b282cecc8aefb86
commit r15-2143-gc19237614b42ddae80a9a24e0b282cecc8aefb86
Author: Carl Love
Date: Fri Jul 12 13:37:36 2024 -0500
rs6000, update effective target for tests builtins-10*.c and
vec_perm-runnable-i128.c
The tests:
tests builtins-10-runnable.c
tests builtins-10.c
vec_perm-runnable-i128.c
use __int128 types that are not supported on all platforms. Update the
tests to check int128 effective target to avoid unsupported type errors
on unsupported platforms.
gcc/testsuite/ChangeLog:
* gcc.target/powerpc/builtins-10-runnable.c: Add
target int128.
* gcc.target/powerpc/builtins-10.c: Add
target int128.
* gcc.target/powerpc/vec_perm-runnable-i128.c: Add
target int128.
Diff:
---
gcc/testsuite/gcc.target/powerpc/builtins-10-runnable.c | 2 +-
gcc/testsuite/gcc.target/powerpc/builtins-10.c| 2 +-
gcc/testsuite/gcc.target/powerpc/vec_perm-runnable-i128.c | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/gcc/testsuite/gcc.target/powerpc/builtins-10-runnable.c
b/gcc/testsuite/gcc.target/powerpc/builtins-10-runnable.c
index dede08358e13..e2d3c9908521 100644
--- a/gcc/testsuite/gcc.target/powerpc/builtins-10-runnable.c
+++ b/gcc/testsuite/gcc.target/powerpc/builtins-10-runnable.c
@@ -1,4 +1,4 @@
-/* { dg-do run } */
+/* { dg-do run { target int128 } } */
/* { dg-require-effective-target vmx_hw } */
/* { dg-options "-maltivec -O2 " } */
diff --git a/gcc/testsuite/gcc.target/powerpc/builtins-10.c
b/gcc/testsuite/gcc.target/powerpc/builtins-10.c
index b00f53cfc628..007892e2731a 100644
--- a/gcc/testsuite/gcc.target/powerpc/builtins-10.c
+++ b/gcc/testsuite/gcc.target/powerpc/builtins-10.c
@@ -1,4 +1,4 @@
-/* { dg-do compile } */
+/* { dg-do compile { target int128 } } */
/* { dg-options "-O2 -maltivec" } */
/* { dg-require-effective-target powerpc_altivec } */
/* { dg-final { scan-assembler-times "xxsel" 6 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec_perm-runnable-i128.c
b/gcc/testsuite/gcc.target/powerpc/vec_perm-runnable-i128.c
index 0e0d77bcb845..df1bf873cfc9 100644
--- a/gcc/testsuite/gcc.target/powerpc/vec_perm-runnable-i128.c
+++ b/gcc/testsuite/gcc.target/powerpc/vec_perm-runnable-i128.c
@@ -1,4 +1,4 @@
-/* { dg-do run } */
+/* { dg-do run { target int128 } } */
/* { dg-require-effective-target vmx_hw } */
/* { dg-options "-maltivec -O2 " } */
[gcc r15-2327] rs6000, remove __builtin_vsx_xvcmp* built-ins
https://gcc.gnu.org/g:6689c587412547a995b81dce2cc2954dda98df59
commit r15-2327-g6689c587412547a995b81dce2cc2954dda98df59
Author: Carl Love
Date: Tue Jul 9 14:09:42 2024 -0400
rs6000, remove __builtin_vsx_xvcmp* built-ins
This patch removes the built-ins:
__builtin_vsx_xvcmpeqsp, __builtin_vsx_xvcmpgesp,
__builtin_vsx_xvcmpgtsp.
which are similar to the recommended PVIPR documented overloaded
vec_cmpeq, vec_cmpgt and vec_cmpge built-ins.
The difference is that the overloaded built-ins return a vector of
32-bit booleans. The removed built-ins returned a vector of floats.
The __builtin_vsx_xvcmpeqdp, __builtin_vsx_xvcmpgedp and
__builtin_vsx_xvcmpgtdp are not removed as they are used by the
overloaded vec_cmpeq, vec_cmpgt and vec_cmpge built-ins.
The test cases for the __builtin_vsx_xvcmpeqsp, __builtin_vsx_xvcmpgesp,
__builtin_vsx_xvcmpgtsp, __builtin_vsx_xvcmpeqdp,
__builtin_vsx_xvcmpgedp and __builtin_vsx_xvcmpgtdp are changed to use
the overloaded vec_cmpeq, vec_cmpgt, vec_cmpge built-ins. Use of the
overloaded built-ins requires the result to be stored in a vector of
boolean of the appropriate size or the result must be cast to the return
type used by the original __builtin_vsx_xvcmp* built-ins.
gcc/ChangeLog:
* config/rs6000/rs6000-builtins.def (__builtin_vsx_xvcmpeqsp,
__builtin_vsx_xvcmpgesp, __builtin_vsx_xvcmpgtsp): Remove
definitions.
gcc/testsuite/ChangeLog:
* gcc.target/powerpc/vsx-builtin-3.c (do_cmp): Replace
__builtin_vsx_xvcmp{eq,gt,ge}{sp,dp} by vec_cmp{eq,gt,ge}
respectively and add explicit casts to vector {float,double}.
Add more testing code assigning result to vector boolean types.
Diff:
---
gcc/config/rs6000/rs6000-builtins.def| 9
gcc/testsuite/gcc.target/powerpc/vsx-builtin-3.c | 28 ++--
2 files changed, 21 insertions(+), 16 deletions(-)
diff --git a/gcc/config/rs6000/rs6000-builtins.def
b/gcc/config/rs6000/rs6000-builtins.def
index ffbeff64d6d6..900488c72423 100644
--- a/gcc/config/rs6000/rs6000-builtins.def
+++ b/gcc/config/rs6000/rs6000-builtins.def
@@ -1579,18 +1579,12 @@
const signed int __builtin_vsx_xvcmpeqdp_p (signed int, vd, vd);
XVCMPEQDP_P vector_eq_v2df_p {pred}
- const vf __builtin_vsx_xvcmpeqsp (vf, vf);
-XVCMPEQSP vector_eqv4sf {}
-
const vd __builtin_vsx_xvcmpgedp (vd, vd);
XVCMPGEDP vector_gev2df {}
const signed int __builtin_vsx_xvcmpgedp_p (signed int, vd, vd);
XVCMPGEDP_P vector_ge_v2df_p {pred}
- const vf __builtin_vsx_xvcmpgesp (vf, vf);
-XVCMPGESP vector_gev4sf {}
-
const signed int __builtin_vsx_xvcmpgesp_p (signed int, vf, vf);
XVCMPGESP_P vector_ge_v4sf_p {pred}
@@ -1600,9 +1594,6 @@
const signed int __builtin_vsx_xvcmpgtdp_p (signed int, vd, vd);
XVCMPGTDP_P vector_gt_v2df_p {pred}
- const vf __builtin_vsx_xvcmpgtsp (vf, vf);
-XVCMPGTSP vector_gtv4sf {}
-
const signed int __builtin_vsx_xvcmpgtsp_p (signed int, vf, vf);
XVCMPGTSP_P vector_gt_v4sf_p {pred}
diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-builtin-3.c
b/gcc/testsuite/gcc.target/powerpc/vsx-builtin-3.c
index 60f91aad23c2..d67f97c8011d 100644
--- a/gcc/testsuite/gcc.target/powerpc/vsx-builtin-3.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsx-builtin-3.c
@@ -156,13 +156,27 @@ int do_cmp (void)
{
int i = 0;
- d[i][0] = __builtin_vsx_xvcmpeqdp (d[i][1], d[i][2]); i++;
- d[i][0] = __builtin_vsx_xvcmpgtdp (d[i][1], d[i][2]); i++;
- d[i][0] = __builtin_vsx_xvcmpgedp (d[i][1], d[i][2]); i++;
-
- f[i][0] = __builtin_vsx_xvcmpeqsp (f[i][1], f[i][2]); i++;
- f[i][0] = __builtin_vsx_xvcmpgtsp (f[i][1], f[i][2]); i++;
- f[i][0] = __builtin_vsx_xvcmpgesp (f[i][1], f[i][2]); i++;
+ /* The __builtin_vsx_xvcmp[gt|ge|eq]dp and __builtin_vsx_xvcmp[gt|ge|eq]sp
+ have been removed in favor of the overloaded vec_cmpeq, vec_cmpgt and
+ vec_cmpge built-ins. The __builtin_vsx_xvcmp* builtins returned a vector
+ result of the same type as the arguments. The vec_cmp* built-ins return
+ a vector of boolenas of the same size as the arguments. Thus the result
+ assignment must be to a boolean or cast to a boolean. Test both cases.
+ */
+
+ d[i][0] = (vector double) vec_cmpeq (d[i][1], d[i][2]); i++;
+ d[i][0] = (vector double) vec_cmpgt (d[i][1], d[i][2]); i++;
+ d[i][0] = (vector double) vec_cmpge (d[i][1], d[i][2]); i++;
+ bl[i][0] = vec_cmpeq (d[i][1], d[i][2]); i++;
+ bl[i][0] = vec_cmpgt (d[i][1], d[i][2]); i++;
+ bl[i][0] = vec_cmpge (d[i][1], d[i][2]); i++;
+
+ f[i][0] = (vector float) vec_cmpeq (f[i][1], f[i][2]); i++;
+ f[i][0] = (vector float) vec_cmpgt (f[i][1], f[i][2]); i++;
+ f[i][0] = (vector float) vec_cmpge (f[i][1], f[i][2]); i++;
+ bi[i][0] = vec_cmpeq (f[i][1], f[i][2]); i++;
+ bi[i][0] = vec_cmpgt (f[i][1], f[i][2]); i++;
+ b
[gcc r15-2328] rs6000, Remove __builtin_vec_set_v1ti, __builtin_vec_set_v2df, __builtin_vec_set_v2di
https://gcc.gnu.org/g:9ecf36b6f1d0688af5b69815e0244ea5118900dc
commit r15-2328-g9ecf36b6f1d0688af5b69815e0244ea5118900dc
Author: Carl Love
Date: Tue Jul 9 14:53:33 2024 -0400
rs6000, Remove __builtin_vec_set_v1ti, __builtin_vec_set_v2df,
__builtin_vec_set_v2di
This patch removes the __builtin_vec_set_v1ti, __builtin_vec_set_v2df
and __builtin_vec_set_v2di built-ins. The users should just use
normal C-code to update the various vector elements. This change was
originally intended to be part of the earlier series of cleanup
patches. It was initially thought that some additional work would be
needed to do some gimple generation instead of these built-ins.
However, the existing default code generation does produce the needed
code.For the vec_set bif, the equivalent C code is as good or
better than the built-in. For the vec_insert bif whose resolving
previously made use of the vec_set bif, the assembly code generation
is as good as before with the -O3 optimization.
Remove the built-ins, use the default gimple generation instead.
gcc/ChangeLog:
* config/rs6000/rs6000-builtins.def (__builtin_vec_set_v1ti,
__builtin_vec_set_v2df, __builtin_vec_set_v2di): Remove built-in
definitions.
* config/rs6000/rs6000-c.cc (resolve_vec_insert): Remove the
handling for constant vec_insert position with
VECTOR_UNIT_VSX_P V1TImode, V2DFmode and V2DImode modes.
Diff:
---
gcc/config/rs6000/rs6000-builtins.def | 13
gcc/config/rs6000/rs6000-c.cc | 40 ---
2 files changed, 53 deletions(-)
diff --git a/gcc/config/rs6000/rs6000-builtins.def
b/gcc/config/rs6000/rs6000-builtins.def
index 900488c72423..dd80b81b666f 100644
--- a/gcc/config/rs6000/rs6000-builtins.def
+++ b/gcc/config/rs6000/rs6000-builtins.def
@@ -1263,19 +1263,6 @@
const signed long long __builtin_vec_ext_v2di (vsll, signed int);
VEC_EXT_V2DI nothing {extract}
-;; VEC_SET_V1TI, VEC_SET_V2DF and VEC_SET_V2DI are used in
-;; resolve_vec_insert(), rs6000-c.cc
-;; TODO: Remove VEC_SET_V1TI, VEC_SET_V2DF and VEC_SET_V2DI once the uses
-;; in resolve_vec_insert are replaced by the equivalent gimple statements.
- const vsq __builtin_vec_set_v1ti (vsq, signed __int128, const int<0,0>);
-VEC_SET_V1TI nothing {set}
-
- const vd __builtin_vec_set_v2df (vd, double, const int<1>);
-VEC_SET_V2DF nothing {set}
-
- const vsll __builtin_vec_set_v2di (vsll, signed long long, const int<1>);
-VEC_SET_V2DI nothing {set}
-
const vsc __builtin_vsx_cmpge_16qi (vsc, vsc);
CMPGE_16QI vector_nltv16qi {}
diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc
index 68519e1397f1..04882c396bfe 100644
--- a/gcc/config/rs6000/rs6000-c.cc
+++ b/gcc/config/rs6000/rs6000-c.cc
@@ -1524,46 +1524,6 @@ resolve_vec_insert (resolution *res, vec
*arglist,
return error_mark_node;
}
- /* If we can use the VSX xxpermdi instruction, use that for insert. */
- machine_mode mode = TYPE_MODE (arg1_type);
-
- if ((mode == V2DFmode || mode == V2DImode)
- && VECTOR_UNIT_VSX_P (mode)
- && TREE_CODE (arg2) == INTEGER_CST)
-{
- wide_int selector = wi::to_wide (arg2);
- selector = wi::umod_trunc (selector, 2);
- arg2 = wide_int_to_tree (TREE_TYPE (arg2), selector);
-
- tree call = NULL_TREE;
- if (mode == V2DFmode)
- call = rs6000_builtin_decls[RS6000_BIF_VEC_SET_V2DF];
- else if (mode == V2DImode)
- call = rs6000_builtin_decls[RS6000_BIF_VEC_SET_V2DI];
-
- /* Note, __builtin_vec_insert_ has vector and scalar types
-reversed. */
- if (call)
- {
- *res = resolved;
- return build_call_expr (call, 3, arg1, arg0, arg2);
- }
-}
-
- else if (mode == V1TImode
- && VECTOR_UNIT_VSX_P (mode)
- && TREE_CODE (arg2) == INTEGER_CST)
-{
- tree call = rs6000_builtin_decls[RS6000_BIF_VEC_SET_V1TI];
- wide_int selector = wi::zero(32);
- arg2 = wide_int_to_tree (TREE_TYPE (arg2), selector);
-
- /* Note, __builtin_vec_insert_ has vector and scalar types
-reversed. */
- *res = resolved;
- return build_call_expr (call, 3, arg1, arg0, arg2);
-}
-
/* Build *(((arg1_inner_type*) & (vector type){arg1}) + arg2) = arg0 with
VIEW_CONVERT_EXPR. i.e.:
D.3192 = v1;
[gcc r15-2329] rs6000, remove built-ins __builtin_vsx_set_1ti, __builtin_vsx_set_2df, __builtin_vsx_set_2di
https://gcc.gnu.org/g:dafd1247b10dbf47177cb81ad267fe569baf0b97
commit r15-2329-gdafd1247b10dbf47177cb81ad267fe569baf0b97
Author: Carl Love
Date: Mon Jul 22 13:40:10 2024 -0400
rs6000, remove built-ins __builtin_vsx_set_1ti, __builtin_vsx_set_2df,
__builtin_vsx_set_2di
The built-ins set a value in a vector. The same operation can be done
in C-code. The assembly code generated from the C-code is as good or
better than the code generated by the built-ins. With default
optimization the number of assembly generated for the two methods are
similar. With -O3 optimization, the assembly generated for the two
approaches is identical for the 2DF and 2DI types. The assembly for
the C-code version of the 1Ti requires one less assembly instruction.
It also only uses one load versus two loads for the built-in.
With the removal of the built-ins, there are no other uses of the
set built-in attribute. The code associated with the set built-in
attribute is removed.
Finally, the testcase for the __builtin_vsx_set_2df is removed. The
other built-ins do not have testcases.
gcc/ChangeLog:
* config/rs6000/rs6000-builtin.cc (get_element_number,
altivec_expand_vec_set_builtin): Remove functions.
(rs6000_expand_builtin): Remove the if statement to call
altivec_expand_vec_set_builtin.
* config/rs6000/rs6000-builtins.def (__builtin_vsx_set_1ti,
__builtin_vsx_set_2df, __builtin_vsx_set_2di): Remove the
built-in definitions.
* config/rs6000/rs6000-gen-builtins.cc (struct attrinfo):
Remove the isset variable from the structure.
(parse_bif_attrs): Remove the uses of the isset variable.
gcc/testsuite/ChangeLog:
* gcc.target/powerpc/vsx-builtin-3.c: Remove test cases for the
__builtin_vsx_set_2df built-in.
Diff:
---
gcc/config/rs6000/rs6000-builtin.cc | 53
gcc/config/rs6000/rs6000-builtins.def| 10 -
gcc/config/rs6000/rs6000-gen-builtins.cc | 28 +
gcc/testsuite/gcc.target/powerpc/vsx-builtin-3.c | 6 ---
4 files changed, 10 insertions(+), 87 deletions(-)
diff --git a/gcc/config/rs6000/rs6000-builtin.cc
b/gcc/config/rs6000/rs6000-builtin.cc
index 117cf0125f86..099cbc822459 100644
--- a/gcc/config/rs6000/rs6000-builtin.cc
+++ b/gcc/config/rs6000/rs6000-builtin.cc
@@ -2313,56 +2313,6 @@ altivec_expand_predicate_builtin (enum insn_code icode,
tree exp, rtx target)
return target;
}
-/* Return the integer constant in ARG. Constrain it to be in the range
- of the subparts of VEC_TYPE; issue an error if not. */
-
-static int
-get_element_number (tree vec_type, tree arg)
-{
- unsigned HOST_WIDE_INT elt, max = TYPE_VECTOR_SUBPARTS (vec_type) - 1;
-
- if (!tree_fits_uhwi_p (arg)
- || (elt = tree_to_uhwi (arg), elt > max))
-{
- error ("selector must be an integer constant in the range [0, %wi]",
max);
- return 0;
-}
-
- return elt;
-}
-
-/* Expand vec_set builtin. */
-static rtx
-altivec_expand_vec_set_builtin (tree exp)
-{
- machine_mode tmode, mode1;
- tree arg0, arg1, arg2;
- int elt;
- rtx op0, op1;
-
- arg0 = CALL_EXPR_ARG (exp, 0);
- arg1 = CALL_EXPR_ARG (exp, 1);
- arg2 = CALL_EXPR_ARG (exp, 2);
-
- tmode = TYPE_MODE (TREE_TYPE (arg0));
- mode1 = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
- gcc_assert (VECTOR_MODE_P (tmode));
-
- op0 = expand_expr (arg0, NULL_RTX, tmode, EXPAND_NORMAL);
- op1 = expand_expr (arg1, NULL_RTX, mode1, EXPAND_NORMAL);
- elt = get_element_number (TREE_TYPE (arg0), arg2);
-
- if (GET_MODE (op1) != mode1 && GET_MODE (op1) != VOIDmode)
-op1 = convert_modes (mode1, GET_MODE (op1), op1, true);
-
- op0 = force_reg (tmode, op0);
- op1 = force_reg (mode1, op1);
-
- rs6000_expand_vector_set (op0, op1, GEN_INT (elt));
-
- return op0;
-}
-
/* Expand vec_ext builtin. */
static rtx
altivec_expand_vec_ext_builtin (tree exp, rtx target)
@@ -3365,9 +3315,6 @@ rs6000_expand_builtin (tree exp, rtx target, rtx /*
subtarget */,
if (bif_is_cpu (*bifaddr))
return cpu_expand_builtin (fcode, exp, target);
- if (bif_is_set (*bifaddr))
-return altivec_expand_vec_set_builtin (exp);
-
if (bif_is_extract (*bifaddr))
return altivec_expand_vec_ext_builtin (exp, target);
diff --git a/gcc/config/rs6000/rs6000-builtins.def
b/gcc/config/rs6000/rs6000-builtins.def
index dd80b81b666f..12d131d016d6 100644
--- a/gcc/config/rs6000/rs6000-builtins.def
+++ b/gcc/config/rs6000/rs6000-builtins.def
@@ -115,7 +115,6 @@
;
; Attributes are strings, and the allowed ones are listed below.
;
-; set Process as a vec_set function
; extract Process as a vec_extract function
; nosoft Not valid with -msoft-float
; ldvecNeeds special handling for vec_ld semantics
@@ -1401,15 +1400,6 @@
const vsll __builtin_vsx_mul_2di (vsll, vsll);
[gcc r15-2380] rs6000, add comment to VEC_IC definition
https://gcc.gnu.org/g:b30eda6ad4877508bf0cb5dcc7cba3b18cd5265e commit r15-2380-gb30eda6ad4877508bf0cb5dcc7cba3b18cd5265e Author: Carl Love Date: Mon Jul 29 11:17:14 2024 -0400 rs6000, add comment to VEC_IC definition This patch adds a comment to the VEC_IC definition to clarify the V1TI "TARGET_POWER10" mode that was added. gcc/ChangeLog: * config/rs6000/vector.md: Add comment for the VEC_IC define_mode_iterator. Diff: --- gcc/config/rs6000/vector.md | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/gcc/config/rs6000/vector.md b/gcc/config/rs6000/vector.md index 0d3e0a24e118..524ba87d6d1d 100644 --- a/gcc/config/rs6000/vector.md +++ b/gcc/config/rs6000/vector.md @@ -26,7 +26,8 @@ ;; Vector int modes (define_mode_iterator VEC_I [V16QI V8HI V4SI V2DI]) -;; Vector int modes for comparison, shift and rotation +;; Vector int modes for comparison, shift and rotation. ISA 3.1 adds the V1TI mode +;; for the vector int128 type. (define_mode_iterator VEC_IC [V16QI V8HI V4SI V2DI (V1TI "TARGET_POWER10")]) ;; 128-bit int modes
[gcc r15-2795] rs6000, Add new overloaded vector shift builtin int128 variants
https://gcc.gnu.org/g:083918a343d6cb9fd28c8b47dd1138220d95c820
commit r15-2795-g083918a343d6cb9fd28c8b47dd1138220d95c820
Author: Carl Love
Date: Wed Aug 7 10:55:03 2024 -0400
rs6000, Add new overloaded vector shift builtin int128 variants
Add the signed __int128 and unsigned __int128 argument types for the
overloaded built-ins vec_sld, vec_sldb, vec_sldw, vec_sll, vec_slo,
vec_srdb, vec_srl, vec_sro. For each of the new argument types add a
testcase and update the documentation for the built-in.
gcc/ChangeLog:
* config/rs6000/altivec.md (vsdb_): Change
define_insn iterator to VEC_IC.
* config/rs6000/rs6000-builtins.def (__builtin_altivec_vsldoi_v1ti,
__builtin_vsx_xxsldwi_v1ti, __builtin_altivec_vsldb_v1ti,
__builtin_altivec_vsrdb_v1ti): New builtin definitions.
* config/rs6000/rs6000-overload.def (vec_sld, vec_sldb, vec_sldw,
vec_sll, vec_slo, vec_srdb, vec_srl, vec_sro): New overloaded
definitions.
* doc/extend.texi (vec_sld, vec_sldb, vec_sldw, vec_sll, vec_slo,
vec_srdb, vec_srl, vec_sro): Add documentation for new overloaded
built-ins.
gcc/testsuite/ChangeLog:
* gcc.target/powerpc/vec-shift-double-runnable-int128.c: New test
file.
Diff:
---
gcc/config/rs6000/altivec.md | 6 +-
gcc/config/rs6000/rs6000-builtins.def | 12 +
gcc/config/rs6000/rs6000-overload.def | 40 ++
gcc/doc/extend.texi| 43 +++
.../powerpc/vec-shift-double-runnable-int128.c | 419 +
5 files changed, 517 insertions(+), 3 deletions(-)
diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
index aa9d8fffc901..1f5489b974f6 100644
--- a/gcc/config/rs6000/altivec.md
+++ b/gcc/config/rs6000/altivec.md
@@ -877,9 +877,9 @@
(define_int_iterator VSHIFT_DBL_LR [UNSPEC_SLDB UNSPEC_SRDB])
(define_insn "vsdb_"
- [(set (match_operand:VI2 0 "register_operand" "=v")
- (unspec:VI2 [(match_operand:VI2 1 "register_operand" "v")
- (match_operand:VI2 2 "register_operand" "v")
+ [(set (match_operand:VEC_IC 0 "register_operand" "=v")
+ (unspec:VEC_IC [(match_operand:VEC_IC 1 "register_operand" "v")
+ (match_operand:VEC_IC 2 "register_operand" "v")
(match_operand:QI 3 "const_0_to_12_operand" "n")]
VSHIFT_DBL_LR))]
"TARGET_POWER10"
diff --git a/gcc/config/rs6000/rs6000-builtins.def
b/gcc/config/rs6000/rs6000-builtins.def
index 0c3c884c1104..5b513a7ef2b8 100644
--- a/gcc/config/rs6000/rs6000-builtins.def
+++ b/gcc/config/rs6000/rs6000-builtins.def
@@ -963,6 +963,9 @@
const vss __builtin_altivec_vsldoi_8hi (vss, vss, const int<4>);
VSLDOI_8HI altivec_vsldoi_v8hi {}
+ const vsq __builtin_altivec_vsldoi_v1ti (vsq, vsq, const int<4>);
+VSLDOI_1TI altivec_vsldoi_v1ti {}
+
const vss __builtin_altivec_vslh (vss, vus);
VSLH vashlv8hi3 {}
@@ -1799,6 +1802,9 @@
const vsll __builtin_vsx_xxsldwi_2di (vsll, vsll, const int<2>);
XXSLDWI_2DI vsx_xxsldwi_v2di {}
+ const vsq __builtin_vsx_xxsldwi_v1ti (vsq, vsq, const int<2>);
+XXSLDWI_1TI vsx_xxsldwi_v1ti {}
+
const vf __builtin_vsx_xxsldwi_4sf (vf, vf, const int<2>);
XXSLDWI_4SF vsx_xxsldwi_v4sf {}
@@ -3267,6 +3273,9 @@
const vss __builtin_altivec_vsldb_v8hi (vss, vss, const int<3>);
VSLDB_V8HI vsldb_v8hi {}
+ const vsq __builtin_altivec_vsldb_v1ti (vsq, vsq, const int<3>);
+VSLDB_V1TI vsldb_v1ti {}
+
const vsq __builtin_altivec_vslq (vsq, vuq);
VSLQ vashlv1ti3 {}
@@ -3285,6 +3294,9 @@
const vss __builtin_altivec_vsrdb_v8hi (vss, vss, const int<3>);
VSRDB_V8HI vsrdb_v8hi {}
+ const vsq __builtin_altivec_vsrdb_v1ti (vsq, vsq, const int<3>);
+VSRDB_V1TI vsrdb_v1ti {}
+
const vsq __builtin_altivec_vsrq (vsq, vuq);
VSRQ vlshrv1ti3 {}
diff --git a/gcc/config/rs6000/rs6000-overload.def
b/gcc/config/rs6000/rs6000-overload.def
index c4ecafc6f7ef..87495aded49e 100644
--- a/gcc/config/rs6000/rs6000-overload.def
+++ b/gcc/config/rs6000/rs6000-overload.def
@@ -3399,6 +3399,10 @@
VSLDOI_4SF
vd __builtin_vec_sld (vd, vd, const int);
VSLDOI_2DF
+ vsq __builtin_vec_sld (vsq, vsq, const int);
+VSLDOI_1TI VSLDOI_VSQ
+ vuq __builtin_vec_sld (vuq, vuq, const int);
+VSLDOI_1TI VSLDOI_VUQ
[VEC_SLDB, vec_sldb, __builtin_vec_sldb]
vsc __builtin_vec_sldb (vsc, vsc, const int);
@@ -3417,6 +3421,10 @@
VSLDB_V2DI VSLDB_VSLL
vull __builtin_vec_sldb (vull, vull, const int);
VSLDB_V2DI VSLDB_VULL
+ vsq __builtin_vec_sldb (vsq, vsq, const int);
+VSLDB_V1TI VSLDB_VSQ
+ vuq __builtin_vec_sldb (vuq, vuq, const int);
+VSLDB_V1TI VSLDB_VUQ
[VEC_SLDW, vec_sldw, __builtin_vec_sldw]
vsc __builtin_vec_sldw (vsc, vsc, const int);
@@ -3439,6 +3447,10 @@
XXSLDWI_4SF XXSLDWI_VF
vd __builtin_vec_sldw (vd, v
[gcc r15-1299] rs6000, altivec-2-runnable.c should be a runnable test
https://gcc.gnu.org/g:8c9b4dff6298a203aba41c90377099f7ed678bde
commit r15-1299-g8c9b4dff6298a203aba41c90377099f7ed678bde
Author: Carl Love
Date: Tue Jun 11 14:01:16 2024 -0400
rs6000, altivec-2-runnable.c should be a runnable test
The test case has "dg-do compile" set not "dg-do run" for a runnable
test. This patch changes the dg-do command argument to run.
gcc/testsuite/ChangeLog:gcc/testsuite/ChangeLog:
* gcc.target/powerpc/altivec-2-runnable.c: Change dg-do
argument to run.
Diff:
---
gcc/testsuite/gcc.target/powerpc/altivec-2-runnable.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-2-runnable.c
b/gcc/testsuite/gcc.target/powerpc/altivec-2-runnable.c
index 6975ea57e657..17b23eb9d50e 100644
--- a/gcc/testsuite/gcc.target/powerpc/altivec-2-runnable.c
+++ b/gcc/testsuite/gcc.target/powerpc/altivec-2-runnable.c
@@ -1,4 +1,4 @@
-/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-do run } */
/* { dg-options "-mvsx" } */
/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 }
} } */
/* { dg-require-effective-target powerpc_vsx } */
[gcc r15-6999] rs6000, fix test builtins-1-p10-runnable.c
https://gcc.gnu.org/g:5d779765b0123cc64c1e6af2656a20979ecaaf96
commit r15-6999-g5d779765b0123cc64c1e6af2656a20979ecaaf96
Author: Carl Love
Date: Wed Oct 2 21:05:08 2024 -0400
rs6000, fix test builtins-1-p10-runnable.c
The test has two issues:
1) The test should generate execute abort() if an error is found.
However, the test contains a #define 0 which actually enables the
error prints not exectuting void() because the debug code is protected
by an #ifdef not #if. The #define DEBUG needs to be removed to so the
test will abort on an error.
2) The vec_i_expected output was tweeked to test that it would fail.
The test value was not removed.
By removing the #define DEBUG, the test fails and reports 1 failure.
Removing the intentionally wrong expected value results in the test
passing with no errors as expected.
gcc/testsuite/ChangeLog:
* gcc.target/powerpc/builtins-1-p10-runnable.c: Remove #define
DEBUG. Replace vec_i_expected value with correct value.
Diff:
---
gcc/testsuite/gcc.target/powerpc/builtins-1-p10-runnable.c | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/gcc/testsuite/gcc.target/powerpc/builtins-1-p10-runnable.c
b/gcc/testsuite/gcc.target/powerpc/builtins-1-p10-runnable.c
index 222c8b3a409c..3e8a1c736e33 100644
--- a/gcc/testsuite/gcc.target/powerpc/builtins-1-p10-runnable.c
+++ b/gcc/testsuite/gcc.target/powerpc/builtins-1-p10-runnable.c
@@ -25,8 +25,6 @@
#include
#include
-#define DEBUG 0
-
#ifdef DEBUG
#include
#endif
@@ -281,8 +279,7 @@ int main()
/* Signed word multiply high */
i_arg1 = (vector int){ 2147483648, 2147483648, 2147483648, 2147483648 };
i_arg2 = (vector int){ 2, 3, 4, 5};
-//vec_i_expected = (vector int){-1, -2, -2, -3};
-vec_i_expected = (vector int){1, -2, -2, -3};
+vec_i_expected = (vector int){-1, -2, -2, -3};
vec_i_result = vec_mulh (i_arg1, i_arg2);
[gcc r15-7002] rs6000, Remove redundant built-in __builtin_vsx_xvcvuxwdp
https://gcc.gnu.org/g:7a47e480390f9087ee75adbba8aaff2022244b2b
commit r15-7002-g7a47e480390f9087ee75adbba8aaff2022244b2b
Author: Carl Love
Date: Thu Aug 1 18:33:42 2024 -0400
rs6000, Remove redundant built-in __builtin_vsx_xvcvuxwdp
The built-in __builtin_vsx_xvcvuxwdp can be covered with PVIPR
function vec_doubleo on LE and vec_doublee on BE. There are no test
cases or documentation for __builtin_vsx_xvcvuxwdp. This patch
removes the redundant built-in.
gcc/ChangeLog:
* config/rs6000/rs6000-builtins.def (__builtin_vsx_xvcvuxwdp):
Remove built-in definition.
Diff:
---
gcc/config/rs6000/rs6000-builtins.def | 3 ---
1 file changed, 3 deletions(-)
diff --git a/gcc/config/rs6000/rs6000-builtins.def
b/gcc/config/rs6000/rs6000-builtins.def
index 6c455b91e147..555d7d589506 100644
--- a/gcc/config/rs6000/rs6000-builtins.def
+++ b/gcc/config/rs6000/rs6000-builtins.def
@@ -1616,9 +1616,6 @@
const vf __builtin_vsx_xvcvuxdsp (vull);
XVCVUXDSP vsx_xvcvuxdsp {}
- const vd __builtin_vsx_xvcvuxwdp (vsi);
-XVCVUXWDP vsx_xvcvuxwdp {}
-
const vf __builtin_vsx_xvcvuxwsp (vsi);
XVCVUXWSP vsx_floatunsv4siv4sf2 {}
[gcc r15-7001] rs6000, remove built-ins __builtin_vsx_vperm_8hi and __builtin_vsx_vperm_8hi_uns
https://gcc.gnu.org/g:38e862a6aa1b8ed209100a28f754f53cb10207de
commit r15-7001-g38e862a6aa1b8ed209100a28f754f53cb10207de
Author: Carl Love
Date: Wed Jul 31 16:40:34 2024 -0400
rs6000, remove built-ins __builtin_vsx_vperm_8hi and
__builtin_vsx_vperm_8hi_uns
The two built-ins __builtin_vsx_vperm_8hi and __builtin_vsx_vperm_8hi_uns
are redundant. The are covered by the overloaded vec_perm built-in. The
built-ins are not documented and do not have test cases.
The removal of these built-ins was missed in commit gcc r15-1923 on
7/9/2024.
This patch removes the redundant built-ins.
gcc/ChangeLog:
* config/rs6000/rs6000-builtins.def (__builtin_vsx_vperm_8hi,
__builtin_vsx_vperm_8hi_uns): Remove built-in definitions.
Diff:
---
gcc/config/rs6000/rs6000-builtins.def | 6 --
1 file changed, 6 deletions(-)
diff --git a/gcc/config/rs6000/rs6000-builtins.def
b/gcc/config/rs6000/rs6000-builtins.def
index 3ca63739d317..6c455b91e147 100644
--- a/gcc/config/rs6000/rs6000-builtins.def
+++ b/gcc/config/rs6000/rs6000-builtins.def
@@ -1472,12 +1472,6 @@
const vf __builtin_vsx_uns_floato_v2di (vsll);
UNS_FLOATO_V2DI unsfloatov2di {}
- const vss __builtin_vsx_vperm_8hi (vss, vss, vuc);
-VPERM_8HI_X altivec_vperm_v8hi {}
-
- const vus __builtin_vsx_vperm_8hi_uns (vus, vus, vuc);
-VPERM_8HI_UNS_X altivec_vperm_v8hi_uns {}
-
const vsll __builtin_vsx_vsigned_v2df (vd);
VEC_VSIGNED_V2DF vsx_xvcvdpsxds {}
[gcc r15-7000] rs6000, add testcases to the overloaded vec_perm built-in
https://gcc.gnu.org/g:bc5753332649c5bcb31cbf6763207d8a9495b77b
commit r15-7000-gbc5753332649c5bcb31cbf6763207d8a9495b77b
Author: Carl Love
Date: Wed Jul 31 16:31:34 2024 -0400
rs6000, add testcases to the overloaded vec_perm built-in
The overloaded vec_perm built-in supports permuting signed and unsigned
vectors of char, bool char, short int, short bool, int, bool, long long
int, long long bool, int128, float and double. However, not all of the
supported arguments are included in the test cases. This patch adds
the missing test cases.
Additionally, in the 128-bit debug print statements the expected result and
the result need to be cast to unsigned long long to print correctly. The
patch makes this additional change to the print statements.
gcc/ChangeLog:
* doc/extend.texi: Fix spelling mistake in description of the
vec_sel built-in. Add documentation of the 128-bit vec_perm
instance.
gcc/testsuite/ChangeLog:
* gcc.target/powerpc/vsx-builtin-3.c: Add vec_perm test cases for
arguments of type vector signed long long int, long long bool,
bool, bool short, bool char and pixel, vector unsigned long long
int, unsigned int, unsigned short int, unsigned char. Cast
arguments for debug prints to unsigned long long.
* gcc.target/powerpc/builtins-4-int128-runnable.c: Add vec_perm
test cases for signed and unsigned int128 arguments.
Diff:
---
gcc/doc/extend.texi| 12 ++-
.../powerpc/builtins-4-int128-runnable.c | 108 ++---
gcc/testsuite/gcc.target/powerpc/vsx-builtin-3.c | 14 ++-
3 files changed, 116 insertions(+), 18 deletions(-)
diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
index beaf67e59a1b..dd9a8d2f8ba5 100644
--- a/gcc/doc/extend.texi
+++ b/gcc/doc/extend.texi
@@ -21852,9 +21852,19 @@ vector bool __int128 vec_sel (vector bool __int128,
vector bool __int128, vector unsigned __int128);
@end smallexample
-The instance is an extension of the exiting overloaded built-in @code{vec_sel}
+The instance is an extension of the existing overloaded built-in @code{vec_sel}
that is documented in the PVIPR.
+@smallexample
+vector signed __int128 vec_perm (vector signed __int128,
+ vector signed __int128);
+vector unsigned __int128 vec_perm (vector unsigned __int128,
+ vector unsigned __int128);
+@end smallexample
+
+The instance is an extension of the existing overloaded built-in
+@code{vec_perm} that is documented in the PVIPR.
+
@node Basic PowerPC Built-in Functions Available on ISA 2.06
@subsubsection Basic PowerPC Built-in Functions Available on ISA 2.06
diff --git a/gcc/testsuite/gcc.target/powerpc/builtins-4-int128-runnable.c
b/gcc/testsuite/gcc.target/powerpc/builtins-4-int128-runnable.c
index 62c11132cf33..c61b0ecb854b 100644
--- a/gcc/testsuite/gcc.target/powerpc/builtins-4-int128-runnable.c
+++ b/gcc/testsuite/gcc.target/powerpc/builtins-4-int128-runnable.c
@@ -18,6 +18,16 @@ int main() {
__uint128_t data_u128[100];
__int128_t data_128[100];
+#ifdef __BIG_ENDIAN__
+ vector unsigned char vuc = {0xC, 0xD, 0xE, 0xF, 0x8, 0x9, 0xA, 0xB,
+ 0x1C, 0x1D, 0x1E, 0x1F, 0x18, 0x19, 0x1A, 0x1B};
+#else
+ vector unsigned char vuc = {0x4, 0x5, 0x6, 0x7, 0x0, 0x1, 0x2, 0x3,
+ 0x14, 0x15, 0x16, 0x17, 0x10, 0x11, 0x12, 0x13};
+#endif
+
+ vector __int128_t vec_128_arg1, vec_128_arg2;
+ vector __uint128_t vec_u128_arg1, vec_u128_arg2;
vector __int128_t vec_128_expected1, vec_128_result1;
vector __uint128_t vec_u128_expected1, vec_u128_result1;
signed long long zero = (signed long long) 0;
@@ -37,11 +47,13 @@ int main() {
{
#ifdef DEBUG
printf("Error: vec_xl(), vec_128_result1[0] = %lld %llu; ",
- vec_128_result1[0] >> 64,
- vec_128_result1[0] & (__int128_t)0x);
+ (unsigned long long)(vec_128_result1[0] >> 64),
+ (unsigned long long)(vec_128_result1[0]
+ & (__int128_t)0x));
printf("vec_128_expected1[0] = %lld %llu\n",
- vec_128_expected1[0] >> 64,
- vec_128_expected1[0] & (__int128_t)0x);
+ (unsigned long long)(vec_128_expected1[0] >> 64),
+ (unsigned long long)(vec_128_expected1[0]
+ & (__int128_t)0x));
#else
abort ();
#endif
@@ -53,11 +65,13 @@ int main() {
{
#ifdef DEBUG
printf("Error: vec_xl(), vec_u128_result1[0] = %lld; ",
- vec_u128_result1[0] >> 64,
- vec_u128_result1[0] & (__int128_t)0x);
+ (unsigned long long)(vec_u128_result1[0] >> 64),
+ (unsigned long long)(vec_u128_result1[0]
+
