[gcc r15-3023] aarch64: Fix tme intrinsic availability

[Andrew Carlotti via Gcc-cvs]

https://gcc.gnu.org/g:32afbb604b4958e78428006b10b3ca5e9ccd49f5

commit r15-3023-g32afbb604b4958e78428006b10b3ca5e9ccd49f5
Author: Andrew Carlotti 
Date:   Thu Oct 26 15:43:44 2023 +0100

aarch64: Fix tme intrinsic availability

The availability of tme intrinsics was previously gated at both
initialisation time (using global target options) and usage time
(accounting for function-specific target options).  This patch removes
the check at initialisation time, and also moves the intrinsics out of
the header file to allow for better error messages (matching the
existing error messages for SVE intrinsics).

gcc/ChangeLog:

PR target/112108
* config/aarch64/aarch64-builtins.cc (aarch64_init_tme_builtins):
Define intrinsic names directly.
(aarch64_general_init_builtins): Move tme initialisation...
(handle_arm_acle_h): ...to here, and remove feature check.
(aarch64_general_check_builtin_call): Check tme intrinsics.
* config/aarch64/arm_acle.h (__tstart, __tcommit, __tcancel)
(__ttest): Remove.
(_TMFAILURE_*): Define unconditionally.

gcc/testsuite/ChangeLog:

PR target/112108
* gcc.target/aarch64/acle/tme_guard-1.c: New test.
* gcc.target/aarch64/acle/tme_guard-2.c: New test.
* gcc.target/aarch64/acle/tme_guard-3.c: New test.
* gcc.target/aarch64/acle/tme_guard-4.c: New test.

Diff:
---
 gcc/config/aarch64/aarch64-builtins.cc | 57 +-
 gcc/config/aarch64/arm_acle.h  | 36 +-
 .../gcc.target/aarch64/acle/tme_guard-1.c  |  9 
 .../gcc.target/aarch64/acle/tme_guard-2.c  | 10 
 .../gcc.target/aarch64/acle/tme_guard-3.c  |  9 
 .../gcc.target/aarch64/acle/tme_guard-4.c  | 10 
 6 files changed, 72 insertions(+), 59 deletions(-)

diff --git a/gcc/config/aarch64/aarch64-builtins.cc 
b/gcc/config/aarch64/aarch64-builtins.cc
index a07adcee6e2..60e4c217921 100644
--- a/gcc/config/aarch64/aarch64-builtins.cc
+++ b/gcc/config/aarch64/aarch64-builtins.cc
@@ -1791,21 +1791,17 @@ aarch64_init_tme_builtins (void)
 = build_function_type_list (void_type_node, uint64_type_node, NULL);
 
   aarch64_builtin_decls[AARCH64_TME_BUILTIN_TSTART]
-= aarch64_general_add_builtin ("__builtin_aarch64_tstart",
-  ftype_uint64_void,
-  AARCH64_TME_BUILTIN_TSTART);
+= aarch64_general_simulate_builtin ("__tstart", ftype_uint64_void,
+   AARCH64_TME_BUILTIN_TSTART);
   aarch64_builtin_decls[AARCH64_TME_BUILTIN_TTEST]
-= aarch64_general_add_builtin ("__builtin_aarch64_ttest",
-  ftype_uint64_void,
-  AARCH64_TME_BUILTIN_TTEST);
+= aarch64_general_simulate_builtin ("__ttest", ftype_uint64_void,
+   AARCH64_TME_BUILTIN_TTEST);
   aarch64_builtin_decls[AARCH64_TME_BUILTIN_TCOMMIT]
-= aarch64_general_add_builtin ("__builtin_aarch64_tcommit",
-  ftype_void_void,
-  AARCH64_TME_BUILTIN_TCOMMIT);
+= aarch64_general_simulate_builtin ("__tcommit", ftype_void_void,
+   AARCH64_TME_BUILTIN_TCOMMIT);
   aarch64_builtin_decls[AARCH64_TME_BUILTIN_TCANCEL]
-= aarch64_general_add_builtin ("__builtin_aarch64_tcancel",
-  ftype_void_uint64,
-  AARCH64_TME_BUILTIN_TCANCEL);
+= aarch64_general_simulate_builtin ("__tcancel", ftype_void_uint64,
+   AARCH64_TME_BUILTIN_TCANCEL);
 }
 
 /* Add builtins for Random Number instructions.  */
@@ -2068,6 +2064,7 @@ handle_arm_acle_h (void)
 {
   if (TARGET_LS64)
 aarch64_init_ls64_builtins ();
+  aarch64_init_tme_builtins ();
 }
 
 /* Initialize fpsr fpcr getters and setters.  */
@@ -2160,9 +2157,6 @@ aarch64_general_init_builtins (void)
   if (!TARGET_ILP32)
 aarch64_init_pauth_hint_builtins ();
 
-  if (TARGET_TME)
-aarch64_init_tme_builtins ();
-
   if (TARGET_MEMTAG)
 aarch64_init_memtag_builtins ();
 
@@ -2285,6 +2279,7 @@ aarch64_general_check_builtin_call (location_t location, 
vec,
unsigned int code, tree fndecl,
unsigned int nargs ATTRIBUTE_UNUSED, tree *args)
 {
+  tree decl = aarch64_builtin_decls[code];
   switch (code)
 {
 case AARCH64_RSR:
@@ -2297,15 +2292,29 @@ aarch64_general_check_builtin_call (location_t 
location, vec,
 case AARCH64_WSR64:
 case AARCH64_WSRF:
 case AARCH64_WSRF64:
-  tree addr = STRIP_NOPS (args[0]);
-  if (TREE_CODE (TREE_TYPE (addr)) != POINTER_TYPE
- || TREE_CODE (addr) != ADDR_EXPR
- || TREE_CODE (TREE_OPERAND (addr, 0)) !

[gcc r15-3024] aarch64: Fix memtag intrinsic availability

[Andrew Carlotti via Gcc-cvs]

https://gcc.gnu.org/g:4e1b617b35631df4dd6089d4044aa19d0c1adea7

commit r15-3024-g4e1b617b35631df4dd6089d4044aa19d0c1adea7
Author: Andrew Carlotti 
Date:   Tue Jul 18 20:09:38 2023 +0100

aarch64: Fix memtag intrinsic availability

The availability of memtag intrinsics and data types were determined
solely by the globally specified architecture features, which did not
reflect any changes specified in target pragmas or attributes.

This patch removes the initialisation-time guards for the intrinsics,
and replaces them with checks at use time. It also removes the macro
indirection from the header file - this simplifies the header, and
allows the missing extension error reporting to find the user-facing
intrinsic names.

gcc/ChangeLog:

PR target/112108
* config/aarch64/aarch64-builtins.cc (aarch64_init_memtag_builtins):
Define intrinsic names directly.
(aarch64_general_init_builtins): Move memtag intialisation...
(handle_arm_acle_h): ...to here, and remove feature check.
(aarch64_general_check_builtin_call): Check memtag intrinsics.
* config/aarch64/arm_acle.h (__arm_mte_create_random_tag)
(__arm_mte_exclude_tag, __arm_mte_ptrdiff)
(__arm_mte_increment_tag, __arm_mte_set_tag, __arm_mte_get_tag):
Remove.

gcc/testsuite/ChangeLog:

PR target/112108
* gcc.target/aarch64/acle/memtag_guard-1.c: New test.
* gcc.target/aarch64/acle/memtag_guard-2.c: New test.
* gcc.target/aarch64/acle/memtag_guard-3.c: New test.
* gcc.target/aarch64/acle/memtag_guard-4.c: New test.

Diff:
---
 gcc/config/aarch64/aarch64-builtins.cc | 23 --
 gcc/config/aarch64/arm_acle.h  | 23 --
 .../gcc.target/aarch64/acle/memtag_guard-1.c   |  9 +
 .../gcc.target/aarch64/acle/memtag_guard-2.c   | 10 ++
 .../gcc.target/aarch64/acle/memtag_guard-3.c   |  9 +
 .../gcc.target/aarch64/acle/memtag_guard-4.c   | 10 ++
 6 files changed, 51 insertions(+), 33 deletions(-)

diff --git a/gcc/config/aarch64/aarch64-builtins.cc 
b/gcc/config/aarch64/aarch64-builtins.cc
index 60e4c217921..9c6d9ec7537 100644
--- a/gcc/config/aarch64/aarch64-builtins.cc
+++ b/gcc/config/aarch64/aarch64-builtins.cc
@@ -1932,27 +1932,27 @@ aarch64_init_memtag_builtins (void)
 
 #define AARCH64_INIT_MEMTAG_BUILTINS_DECL(F, N, I, T) \
   aarch64_builtin_decls[AARCH64_MEMTAG_BUILTIN_##F] \
-= aarch64_general_add_builtin ("__builtin_aarch64_memtag_"#N, \
-  T, AARCH64_MEMTAG_BUILTIN_##F); \
+= aarch64_general_simulate_builtin ("__arm_mte_"#N, T, \
+   AARCH64_MEMTAG_BUILTIN_##F); \
   aarch64_memtag_builtin_data[AARCH64_MEMTAG_BUILTIN_##F - \
  AARCH64_MEMTAG_BUILTIN_START - 1] = \
{T, CODE_FOR_##I};
 
   fntype = build_function_type_list (ptr_type_node, ptr_type_node,
 uint64_type_node, NULL);
-  AARCH64_INIT_MEMTAG_BUILTINS_DECL (IRG, irg, irg, fntype);
+  AARCH64_INIT_MEMTAG_BUILTINS_DECL (IRG, create_random_tag, irg, fntype);
 
   fntype = build_function_type_list (uint64_type_node, ptr_type_node,
 uint64_type_node, NULL);
-  AARCH64_INIT_MEMTAG_BUILTINS_DECL (GMI, gmi, gmi, fntype);
+  AARCH64_INIT_MEMTAG_BUILTINS_DECL (GMI, exclude_tag, gmi, fntype);
 
   fntype = build_function_type_list (ptrdiff_type_node, ptr_type_node,
 ptr_type_node, NULL);
-  AARCH64_INIT_MEMTAG_BUILTINS_DECL (SUBP, subp, subp, fntype);
+  AARCH64_INIT_MEMTAG_BUILTINS_DECL (SUBP, ptrdiff, subp, fntype);
 
   fntype = build_function_type_list (ptr_type_node, ptr_type_node,
 unsigned_type_node, NULL);
-  AARCH64_INIT_MEMTAG_BUILTINS_DECL (INC_TAG, inc_tag, addg, fntype);
+  AARCH64_INIT_MEMTAG_BUILTINS_DECL (INC_TAG, increment_tag, addg, fntype);
 
   fntype = build_function_type_list (void_type_node, ptr_type_node, NULL);
   AARCH64_INIT_MEMTAG_BUILTINS_DECL (SET_TAG, set_tag, stg, fntype);
@@ -2065,6 +2065,7 @@ handle_arm_acle_h (void)
   if (TARGET_LS64)
 aarch64_init_ls64_builtins ();
   aarch64_init_tme_builtins ();
+  aarch64_init_memtag_builtins ();
 }
 
 /* Initialize fpsr fpcr getters and setters.  */
@@ -2157,9 +2158,6 @@ aarch64_general_init_builtins (void)
   if (!TARGET_ILP32)
 aarch64_init_pauth_hint_builtins ();
 
-  if (TARGET_MEMTAG)
-aarch64_init_memtag_builtins ();
-
   if (in_lto_p)
 handle_arm_acle_h ();
 }
@@ -2316,7 +2314,12 @@ aarch64_general_check_builtin_call (location_t location, 
vec,
 default:
   break;
 }
-  /* Default behavior.  */
+
+  if (code >= AARCH64_MEMTAG_BUILTIN_START
+  && code <= AARCH64_MEMTAG_BUILTIN

[gcc r15-3021] aarch64: Refactor check_required_extensions

[Andrew Carlotti via Gcc-cvs]

https://gcc.gnu.org/g:a4b39dc4bfad2b224cd2041568d469b5724f8f88

commit r15-3021-ga4b39dc4bfad2b224cd2041568d469b5724f8f88
Author: Andrew Carlotti 
Date:   Tue Aug 13 16:15:11 2024 +0100

aarch64: Refactor check_required_extensions

Replace TARGET_GENERAL_REGS_ONLY check with an explicit check that
aarch64_isa_flags enables all required extensions.  This will be more
flexible when repurposing this function for non-SVE intrinsics.

gcc/ChangeLog:

* config/aarch64/aarch64-sve-builtins.cc
(check_required_registers): Remove target check and rename to...
(report_missing_registers): ...this.
(check_required_extensions): Refactor.

Diff:
---
 gcc/config/aarch64/aarch64-sve-builtins.cc | 38 --
 1 file changed, 20 insertions(+), 18 deletions(-)

diff --git a/gcc/config/aarch64/aarch64-sve-builtins.cc 
b/gcc/config/aarch64/aarch64-sve-builtins.cc
index 0a560eaedca..1fe380dd1ef 100644
--- a/gcc/config/aarch64/aarch64-sve-builtins.cc
+++ b/gcc/config/aarch64/aarch64-sve-builtins.cc
@@ -1094,27 +1094,19 @@ report_missing_extension (location_t location, tree 
fndecl,
   reported_missing_extension_p = true;
 }
 
-/* Check whether the registers required by SVE function fndecl are available.
-   Report an error against LOCATION and return false if not.  */
-static bool
-check_required_registers (location_t location, tree fndecl)
+/* Report an error against LOCATION that the user has tried to use
+   function FNDECL when non-general registers are disabled.  */
+static void
+report_missing_registers (location_t location, tree fndecl)
 {
   /* Avoid reporting a slew of messages for a single oversight.  */
   if (reported_missing_registers_p)
-return false;
-
-  if (TARGET_GENERAL_REGS_ONLY)
-{
-  /* SVE registers are not usable when -mgeneral-regs-only option
-is specified.  */
-  error_at (location,
-   "ACLE function %qD is incompatible with the use of %qs",
-   fndecl, "-mgeneral-regs-only");
-  reported_missing_registers_p = true;
-  return false;
-}
+return;
 
-  return true;
+  error_at (location,
+   "ACLE function %qD is incompatible with the use of %qs",
+   fndecl, "-mgeneral-regs-only");
+  reported_missing_registers_p = true;
 }
 
 /* Check whether all the AARCH64_FL_* values in REQUIRED_EXTENSIONS are
@@ -1124,9 +1116,19 @@ static bool
 check_required_extensions (location_t location, tree fndecl,
   aarch64_feature_flags required_extensions)
 {
+  if ((required_extensions & ~aarch64_isa_flags) == 0)
+return true;
+
   auto missing_extensions = required_extensions & ~aarch64_asm_isa_flags;
+
   if (missing_extensions == 0)
-return check_required_registers (location, fndecl);
+{
+  /* All required extensions are enabled in aarch64_asm_isa_flags, so the
+error must be the use of general-regs-only.  */
+  report_missing_registers (location, fndecl);
+  return false;
+}
+
 
   if (missing_extensions & AARCH64_FL_SM_OFF)
 {

[gcc r15-3022] aarch64: Move check_required_extensions

[Andrew Carlotti via Gcc-cvs]

https://gcc.gnu.org/g:baf71ec56b40858c5b2a4cc8481403685d753477

commit r15-3022-gbaf71ec56b40858c5b2a4cc8481403685d753477
Author: Andrew Carlotti 
Date:   Tue Jul 18 16:40:58 2023 +0100

aarch64: Move check_required_extensions

Move SVE extension checking functionality to aarch64-builtins.cc, so
that it can be shared by non-SVE intrinsics.

gcc/ChangeLog:

* config/aarch64/aarch64-sve-builtins.cc (check_builtin_call)
(expand_builtin): Update calls to the below.
(report_missing_extension, report_missing_registers)
(check_required_extensions): Move out of aarch64_sve namespace,
rename, and move into...
* config/aarch64/aarch64-builtins.cc 
(aarch64_report_missing_extension)
(aarch64_report_missing_registers)
(aarch64_check_required_extensions) ...here.
* config/aarch64/aarch64-protos.h 
(aarch64_check_required_extensions):
Add prototype.

Diff:
---
 gcc/config/aarch64/aarch64-builtins.cc | 100 +++
 gcc/config/aarch64/aarch64-protos.h|   2 +
 gcc/config/aarch64/aarch64-sve-builtins.cc | 107 ++---
 3 files changed, 106 insertions(+), 103 deletions(-)

diff --git a/gcc/config/aarch64/aarch64-builtins.cc 
b/gcc/config/aarch64/aarch64-builtins.cc
index 30669f8aa18..a07adcee6e2 100644
--- a/gcc/config/aarch64/aarch64-builtins.cc
+++ b/gcc/config/aarch64/aarch64-builtins.cc
@@ -2180,6 +2180,106 @@ aarch64_general_builtin_decl (unsigned code, bool)
   return aarch64_builtin_decls[code];
 }
 
+/* True if we've already complained about attempts to use functions
+   when the required extension is disabled.  */
+static bool reported_missing_extension_p;
+
+/* True if we've already complained about attempts to use functions
+   which require registers that are missing.  */
+static bool reported_missing_registers_p;
+
+/* Report an error against LOCATION that the user has tried to use
+   function FNDECL when extension EXTENSION is disabled.  */
+static void
+aarch64_report_missing_extension (location_t location, tree fndecl,
+ const char *extension)
+{
+  /* Avoid reporting a slew of messages for a single oversight.  */
+  if (reported_missing_extension_p)
+return;
+
+  error_at (location, "ACLE function %qD requires ISA extension %qs",
+   fndecl, extension);
+  inform (location, "you can enable %qs using the command-line"
+ " option %<-march%>, or by using the %"
+ " attribute or pragma", extension);
+  reported_missing_extension_p = true;
+}
+
+/* Report an error against LOCATION that the user has tried to use
+   function FNDECL when non-general registers are disabled.  */
+static void
+aarch64_report_missing_registers (location_t location, tree fndecl)
+{
+  /* Avoid reporting a slew of messages for a single oversight.  */
+  if (reported_missing_registers_p)
+return;
+
+  error_at (location,
+   "ACLE function %qD is incompatible with the use of %qs",
+   fndecl, "-mgeneral-regs-only");
+  reported_missing_registers_p = true;
+}
+
+/* Check whether all the AARCH64_FL_* values in REQUIRED_EXTENSIONS are
+   enabled, given that those extensions are required for function FNDECL.
+   Report an error against LOCATION if not.  */
+bool
+aarch64_check_required_extensions (location_t location, tree fndecl,
+  aarch64_feature_flags required_extensions)
+{
+  if ((required_extensions & ~aarch64_isa_flags) == 0)
+return true;
+
+  auto missing_extensions = required_extensions & ~aarch64_asm_isa_flags;
+
+  if (missing_extensions == 0)
+{
+  /* All required extensions are enabled in aarch64_asm_isa_flags, so the
+error must be the use of general-regs-only.  */
+  aarch64_report_missing_registers (location, fndecl);
+  return false;
+}
+
+  if (missing_extensions & AARCH64_FL_SM_OFF)
+{
+  error_at (location, "ACLE function %qD cannot be called when"
+   " SME streaming mode is enabled", fndecl);
+  return false;
+}
+
+  if (missing_extensions & AARCH64_FL_SM_ON)
+{
+  error_at (location, "ACLE function %qD can only be called when"
+   " SME streaming mode is enabled", fndecl);
+  return false;
+}
+
+  if (missing_extensions & AARCH64_FL_ZA_ON)
+{
+  error_at (location, "ACLE function %qD can only be called from"
+   " a function that has %qs state", fndecl, "za");
+  return false;
+}
+
+  static const struct {
+aarch64_feature_flags flag;
+const char *name;
+  } extensions[] = {
+#define AARCH64_OPT_EXTENSION(EXT_NAME, IDENT, C, D, E, F) \
+{ AARCH64_FL_##IDENT, EXT_NAME },
+#include "aarch64-option-extensions.def"
+  };
+
+  for (unsigned int i = 0; i < ARRAY_SIZE (extensions); ++i)
+if (missing_extensions & extensions[i].flag)
+  {
+   aarch64_report_missing_extension (loca

[gcc r15-3025] aarch64: Fix ls64 intrinsic availability

[Andrew Carlotti via Gcc-cvs]

https://gcc.gnu.org/g:fceecc511d4918e2b27a0609f8885ec8aba8723d

commit r15-3025-gfceecc511d4918e2b27a0609f8885ec8aba8723d
Author: Andrew Carlotti 
Date:   Thu Oct 26 15:45:15 2023 +0100

aarch64: Fix ls64 intrinsic availability

The availability of ls64 intrinsics and data types were determined
solely by the globally specified architecture features, which did not
reflect any changes specified in target pragmas or attributes.

This patch removes the initialisation-time guards for the intrinsics,
and replaces them with checks at use time. We also get better error
messages when ls64 is not available (matching the existing error
messages for SVE intrinsics).

The data512_t type is made always available; this is consistent with the
present behaviour for Neon fp16/bf16 types.

gcc/ChangeLog:

PR target/112108
* config/aarch64/aarch64-builtins.cc (handle_arm_acle_h): Remove
feature check at initialisation.
(aarch64_general_check_builtin_call): Check ls64 intrinsics.
* config/aarch64/arm_acle.h: (data512_t) Make always available.

gcc/testsuite/ChangeLog:

PR target/112108
* gcc.target/aarch64/acle/ls64_guard-1.c: New test.
* gcc.target/aarch64/acle/ls64_guard-2.c: New test.
* gcc.target/aarch64/acle/ls64_guard-3.c: New test.
* gcc.target/aarch64/acle/ls64_guard-4.c: New test.

Diff:
---
 gcc/config/aarch64/aarch64-builtins.cc   | 10 --
 gcc/config/aarch64/arm_acle.h|  2 --
 gcc/testsuite/gcc.target/aarch64/acle/ls64_guard-1.c |  9 +
 gcc/testsuite/gcc.target/aarch64/acle/ls64_guard-2.c | 10 ++
 gcc/testsuite/gcc.target/aarch64/acle/ls64_guard-3.c |  9 +
 gcc/testsuite/gcc.target/aarch64/acle/ls64_guard-4.c | 10 ++
 6 files changed, 46 insertions(+), 4 deletions(-)

diff --git a/gcc/config/aarch64/aarch64-builtins.cc 
b/gcc/config/aarch64/aarch64-builtins.cc
index 9c6d9ec7537..eb878b933fe 100644
--- a/gcc/config/aarch64/aarch64-builtins.cc
+++ b/gcc/config/aarch64/aarch64-builtins.cc
@@ -2062,8 +2062,7 @@ aarch64_init_data_intrinsics (void)
 void
 handle_arm_acle_h (void)
 {
-  if (TARGET_LS64)
-aarch64_init_ls64_builtins ();
+  aarch64_init_ls64_builtins ();
   aarch64_init_tme_builtins ();
   aarch64_init_memtag_builtins ();
 }
@@ -2311,6 +2310,13 @@ aarch64_general_check_builtin_call (location_t location, 
vec,
   return aarch64_check_required_extensions (location, decl,
AARCH64_FL_TME);
 
+case AARCH64_LS64_BUILTIN_LD64B:
+case AARCH64_LS64_BUILTIN_ST64B:
+case AARCH64_LS64_BUILTIN_ST64BV:
+case AARCH64_LS64_BUILTIN_ST64BV0:
+  return aarch64_check_required_extensions (location, decl,
+   AARCH64_FL_LS64);
+
 default:
   break;
 }
diff --git a/gcc/config/aarch64/arm_acle.h b/gcc/config/aarch64/arm_acle.h
index ab043267913..ab4e7e60e04 100644
--- a/gcc/config/aarch64/arm_acle.h
+++ b/gcc/config/aarch64/arm_acle.h
@@ -265,9 +265,7 @@ __crc32d (uint32_t __a, uint64_t __b)
 #define _TMFAILURE_INT0x0080u
 #define _TMFAILURE_TRIVIAL0x0100u
 
-#ifdef __ARM_FEATURE_LS64
 typedef __arm_data512_t data512_t;
-#endif
 
 #pragma GCC push_options
 #pragma GCC target ("+nothing+rng")
diff --git a/gcc/testsuite/gcc.target/aarch64/acle/ls64_guard-1.c 
b/gcc/testsuite/gcc.target/aarch64/acle/ls64_guard-1.c
new file mode 100644
index 000..7dfc193a293
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/acle/ls64_guard-1.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=armv8.6-a" } */
+
+#include 
+
+data512_t foo (void * p)
+{
+  return __arm_ld64b (p); /* { dg-error {ACLE function '__arm_ld64b' requires 
ISA extension 'ls64'} } */
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/acle/ls64_guard-2.c 
b/gcc/testsuite/gcc.target/aarch64/acle/ls64_guard-2.c
new file mode 100644
index 000..3ede05a81f0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/acle/ls64_guard-2.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=armv8.6-a" } */
+
+#include 
+
+#pragma GCC target("arch=armv8-a+ls64")
+data512_t foo (void * p)
+{
+  return __arm_ld64b (p);
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/acle/ls64_guard-3.c 
b/gcc/testsuite/gcc.target/aarch64/acle/ls64_guard-3.c
new file mode 100644
index 000..e0fccdad7be
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/acle/ls64_guard-3.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=armv8-a+ls64 -mgeneral-regs-only" } */
+
+#include 
+
+data512_t foo (void * p)
+{
+  return __arm_ld64b (p);
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/acle/ls64_guard-4.c 
b/gcc/testsuite/gcc.target/aarch64/acle/ls64_guard-4.c
new file mode 100644
index 000..af1d9a

[gcc r14-10631] aarch64: Refactor check_required_extensions

[Andrew Carlotti via Gcc-cvs]

https://gcc.gnu.org/g:c6e04d1f92fc3b4215e7c179da5d4a51356f69a8

commit r14-10631-gc6e04d1f92fc3b4215e7c179da5d4a51356f69a8
Author: Andrew Carlotti 
Date:   Tue Aug 13 16:15:11 2024 +0100

aarch64: Refactor check_required_extensions

Replace TARGET_GENERAL_REGS_ONLY check with an explicit check that
aarch64_isa_flags enables all required extensions.  This will be more
flexible when repurposing this function for non-SVE intrinsics.

gcc/ChangeLog:

* config/aarch64/aarch64-sve-builtins.cc
(check_required_registers): Remove target check and rename to...
(report_missing_registers): ...this.
(check_required_extensions): Refactor.

Diff:
---
 gcc/config/aarch64/aarch64-sve-builtins.cc | 38 --
 1 file changed, 20 insertions(+), 18 deletions(-)

diff --git a/gcc/config/aarch64/aarch64-sve-builtins.cc 
b/gcc/config/aarch64/aarch64-sve-builtins.cc
index f3983a123e3..46bd9bc5a35 100644
--- a/gcc/config/aarch64/aarch64-sve-builtins.cc
+++ b/gcc/config/aarch64/aarch64-sve-builtins.cc
@@ -1094,27 +1094,19 @@ report_missing_extension (location_t location, tree 
fndecl,
   reported_missing_extension_p = true;
 }
 
-/* Check whether the registers required by SVE function fndecl are available.
-   Report an error against LOCATION and return false if not.  */
-static bool
-check_required_registers (location_t location, tree fndecl)
+/* Report an error against LOCATION that the user has tried to use
+   function FNDECL when non-general registers are disabled.  */
+static void
+report_missing_registers (location_t location, tree fndecl)
 {
   /* Avoid reporting a slew of messages for a single oversight.  */
   if (reported_missing_registers_p)
-return false;
-
-  if (TARGET_GENERAL_REGS_ONLY)
-{
-  /* SVE registers are not usable when -mgeneral-regs-only option
-is specified.  */
-  error_at (location,
-   "ACLE function %qD is incompatible with the use of %qs",
-   fndecl, "-mgeneral-regs-only");
-  reported_missing_registers_p = true;
-  return false;
-}
+return;
 
-  return true;
+  error_at (location,
+   "ACLE function %qD is incompatible with the use of %qs",
+   fndecl, "-mgeneral-regs-only");
+  reported_missing_registers_p = true;
 }
 
 /* Check whether all the AARCH64_FL_* values in REQUIRED_EXTENSIONS are
@@ -1124,9 +1116,19 @@ static bool
 check_required_extensions (location_t location, tree fndecl,
   aarch64_feature_flags required_extensions)
 {
+  if ((required_extensions & ~aarch64_isa_flags) == 0)
+return true;
+
   auto missing_extensions = required_extensions & ~aarch64_asm_isa_flags;
+
   if (missing_extensions == 0)
-return check_required_registers (location, fndecl);
+{
+  /* All required extensions are enabled in aarch64_asm_isa_flags, so the
+error must be the use of general-regs-only.  */
+  report_missing_registers (location, fndecl);
+  return false;
+}
+
 
   if (missing_extensions & AARCH64_FL_SM_OFF)
 {

[gcc r14-10632] aarch64: Move check_required_extensions

[Andrew Carlotti via Gcc-cvs]

https://gcc.gnu.org/g:422c3f1965d76a541385bdc419a4e1c46f007525

commit r14-10632-g422c3f1965d76a541385bdc419a4e1c46f007525
Author: Andrew Carlotti 
Date:   Tue Jul 18 16:40:58 2023 +0100

aarch64: Move check_required_extensions

Move SVE extension checking functionality to aarch64-builtins.cc, so
that it can be shared by non-SVE intrinsics.

gcc/ChangeLog:

* config/aarch64/aarch64-sve-builtins.cc (check_builtin_call)
(expand_builtin): Update calls to the below.
(report_missing_extension, report_missing_registers)
(check_required_extensions): Move out of aarch64_sve namespace,
rename, and move into...
* config/aarch64/aarch64-builtins.cc 
(aarch64_report_missing_extension)
(aarch64_report_missing_registers)
(aarch64_check_required_extensions) ...here.
* config/aarch64/aarch64-protos.h 
(aarch64_check_required_extensions):
Add prototype.

Diff:
---
 gcc/config/aarch64/aarch64-builtins.cc | 100 +++
 gcc/config/aarch64/aarch64-protos.h|   2 +
 gcc/config/aarch64/aarch64-sve-builtins.cc | 107 ++---
 3 files changed, 106 insertions(+), 103 deletions(-)

diff --git a/gcc/config/aarch64/aarch64-builtins.cc 
b/gcc/config/aarch64/aarch64-builtins.cc
index 75d21de1401..ad3986ce002 100644
--- a/gcc/config/aarch64/aarch64-builtins.cc
+++ b/gcc/config/aarch64/aarch64-builtins.cc
@@ -2098,6 +2098,106 @@ aarch64_general_builtin_decl (unsigned code, bool)
   return aarch64_builtin_decls[code];
 }
 
+/* True if we've already complained about attempts to use functions
+   when the required extension is disabled.  */
+static bool reported_missing_extension_p;
+
+/* True if we've already complained about attempts to use functions
+   which require registers that are missing.  */
+static bool reported_missing_registers_p;
+
+/* Report an error against LOCATION that the user has tried to use
+   function FNDECL when extension EXTENSION is disabled.  */
+static void
+aarch64_report_missing_extension (location_t location, tree fndecl,
+ const char *extension)
+{
+  /* Avoid reporting a slew of messages for a single oversight.  */
+  if (reported_missing_extension_p)
+return;
+
+  error_at (location, "ACLE function %qD requires ISA extension %qs",
+   fndecl, extension);
+  inform (location, "you can enable %qs using the command-line"
+ " option %<-march%>, or by using the %"
+ " attribute or pragma", extension);
+  reported_missing_extension_p = true;
+}
+
+/* Report an error against LOCATION that the user has tried to use
+   function FNDECL when non-general registers are disabled.  */
+static void
+aarch64_report_missing_registers (location_t location, tree fndecl)
+{
+  /* Avoid reporting a slew of messages for a single oversight.  */
+  if (reported_missing_registers_p)
+return;
+
+  error_at (location,
+   "ACLE function %qD is incompatible with the use of %qs",
+   fndecl, "-mgeneral-regs-only");
+  reported_missing_registers_p = true;
+}
+
+/* Check whether all the AARCH64_FL_* values in REQUIRED_EXTENSIONS are
+   enabled, given that those extensions are required for function FNDECL.
+   Report an error against LOCATION if not.  */
+bool
+aarch64_check_required_extensions (location_t location, tree fndecl,
+  aarch64_feature_flags required_extensions)
+{
+  if ((required_extensions & ~aarch64_isa_flags) == 0)
+return true;
+
+  auto missing_extensions = required_extensions & ~aarch64_asm_isa_flags;
+
+  if (missing_extensions == 0)
+{
+  /* All required extensions are enabled in aarch64_asm_isa_flags, so the
+error must be the use of general-regs-only.  */
+  aarch64_report_missing_registers (location, fndecl);
+  return false;
+}
+
+  if (missing_extensions & AARCH64_FL_SM_OFF)
+{
+  error_at (location, "ACLE function %qD cannot be called when"
+   " SME streaming mode is enabled", fndecl);
+  return false;
+}
+
+  if (missing_extensions & AARCH64_FL_SM_ON)
+{
+  error_at (location, "ACLE function %qD can only be called when"
+   " SME streaming mode is enabled", fndecl);
+  return false;
+}
+
+  if (missing_extensions & AARCH64_FL_ZA_ON)
+{
+  error_at (location, "ACLE function %qD can only be called from"
+   " a function that has %qs state", fndecl, "za");
+  return false;
+}
+
+  static const struct {
+aarch64_feature_flags flag;
+const char *name;
+  } extensions[] = {
+#define AARCH64_OPT_EXTENSION(EXT_NAME, IDENT, C, D, E, F) \
+{ AARCH64_FL_##IDENT, EXT_NAME },
+#include "aarch64-option-extensions.def"
+  };
+
+  for (unsigned int i = 0; i < ARRAY_SIZE (extensions); ++i)
+if (missing_extensions & extensions[i].flag)
+  {
+   aarch64_report_missing_extension (loc

[gcc r14-10633] aarch64: Fix tme intrinsic availability

[Andrew Carlotti via Gcc-cvs]

https://gcc.gnu.org/g:0a3a0d4a5e32e9b914b5c5cc283ee485adc6cd11

commit r14-10633-g0a3a0d4a5e32e9b914b5c5cc283ee485adc6cd11
Author: Andrew Carlotti 
Date:   Thu Oct 26 15:43:44 2023 +0100

aarch64: Fix tme intrinsic availability

The availability of tme intrinsics was previously gated at both
initialisation time (using global target options) and usage time
(accounting for function-specific target options).  This patch removes
the check at initialisation time, and also moves the intrinsics out of
the header file to allow for better error messages (matching the
existing error messages for SVE intrinsics).

gcc/ChangeLog:

PR target/112108
* config/aarch64/aarch64-builtins.cc (aarch64_init_tme_builtins):
Define intrinsic names directly.
(aarch64_general_init_builtins): Move tme initialisation...
(handle_arm_acle_h): ...to here, and remove feature check.
(aarch64_general_check_builtin_call): Check tme intrinsics.
* config/aarch64/arm_acle.h (__tstart, __tcommit, __tcancel)
(__ttest): Remove.
(_TMFAILURE_*): Define unconditionally.

gcc/testsuite/ChangeLog:

PR target/112108
* gcc.target/aarch64/acle/tme_guard-1.c: New test.
* gcc.target/aarch64/acle/tme_guard-2.c: New test.
* gcc.target/aarch64/acle/tme_guard-3.c: New test.
* gcc.target/aarch64/acle/tme_guard-4.c: New test.

Diff:
---
 gcc/config/aarch64/aarch64-builtins.cc | 57 +-
 gcc/config/aarch64/arm_acle.h  | 36 +-
 .../gcc.target/aarch64/acle/tme_guard-1.c  |  9 
 .../gcc.target/aarch64/acle/tme_guard-2.c  | 10 
 .../gcc.target/aarch64/acle/tme_guard-3.c  |  9 
 .../gcc.target/aarch64/acle/tme_guard-4.c  | 10 
 6 files changed, 72 insertions(+), 59 deletions(-)

diff --git a/gcc/config/aarch64/aarch64-builtins.cc 
b/gcc/config/aarch64/aarch64-builtins.cc
index ad3986ce002..70437641219 100644
--- a/gcc/config/aarch64/aarch64-builtins.cc
+++ b/gcc/config/aarch64/aarch64-builtins.cc
@@ -1709,21 +1709,17 @@ aarch64_init_tme_builtins (void)
 = build_function_type_list (void_type_node, uint64_type_node, NULL);
 
   aarch64_builtin_decls[AARCH64_TME_BUILTIN_TSTART]
-= aarch64_general_add_builtin ("__builtin_aarch64_tstart",
-  ftype_uint64_void,
-  AARCH64_TME_BUILTIN_TSTART);
+= aarch64_general_simulate_builtin ("__tstart", ftype_uint64_void,
+   AARCH64_TME_BUILTIN_TSTART);
   aarch64_builtin_decls[AARCH64_TME_BUILTIN_TTEST]
-= aarch64_general_add_builtin ("__builtin_aarch64_ttest",
-  ftype_uint64_void,
-  AARCH64_TME_BUILTIN_TTEST);
+= aarch64_general_simulate_builtin ("__ttest", ftype_uint64_void,
+   AARCH64_TME_BUILTIN_TTEST);
   aarch64_builtin_decls[AARCH64_TME_BUILTIN_TCOMMIT]
-= aarch64_general_add_builtin ("__builtin_aarch64_tcommit",
-  ftype_void_void,
-  AARCH64_TME_BUILTIN_TCOMMIT);
+= aarch64_general_simulate_builtin ("__tcommit", ftype_void_void,
+   AARCH64_TME_BUILTIN_TCOMMIT);
   aarch64_builtin_decls[AARCH64_TME_BUILTIN_TCANCEL]
-= aarch64_general_add_builtin ("__builtin_aarch64_tcancel",
-  ftype_void_uint64,
-  AARCH64_TME_BUILTIN_TCANCEL);
+= aarch64_general_simulate_builtin ("__tcancel", ftype_void_uint64,
+   AARCH64_TME_BUILTIN_TCANCEL);
 }
 
 /* Add builtins for Random Number instructions.  */
@@ -1986,6 +1982,7 @@ handle_arm_acle_h (void)
 {
   if (TARGET_LS64)
 aarch64_init_ls64_builtins ();
+  aarch64_init_tme_builtins ();
 }
 
 /* Initialize fpsr fpcr getters and setters.  */
@@ -2078,9 +2075,6 @@ aarch64_general_init_builtins (void)
   if (!TARGET_ILP32)
 aarch64_init_pauth_hint_builtins ();
 
-  if (TARGET_TME)
-aarch64_init_tme_builtins ();
-
   if (TARGET_MEMTAG)
 aarch64_init_memtag_builtins ();
 
@@ -2203,6 +2197,7 @@ aarch64_general_check_builtin_call (location_t location, 
vec,
unsigned int code, tree fndecl,
unsigned int nargs ATTRIBUTE_UNUSED, tree *args)
 {
+  tree decl = aarch64_builtin_decls[code];
   switch (code)
 {
 case AARCH64_RSR:
@@ -2215,15 +2210,29 @@ aarch64_general_check_builtin_call (location_t 
location, vec,
 case AARCH64_WSR64:
 case AARCH64_WSRF:
 case AARCH64_WSRF64:
-  tree addr = STRIP_NOPS (args[0]);
-  if (TREE_CODE (TREE_TYPE (addr)) != POINTER_TYPE
- || TREE_CODE (addr) != ADDR_EXPR
- || TREE_CODE (TREE_OPERAND (addr, 0)) 

[gcc r14-10634] aarch64: Fix memtag intrinsic availability

[Andrew Carlotti via Gcc-cvs]

https://gcc.gnu.org/g:8485606056ed3ca0d0acf6e0d943975e9173e7cd

commit r14-10634-g8485606056ed3ca0d0acf6e0d943975e9173e7cd
Author: Andrew Carlotti 
Date:   Tue Jul 18 20:09:38 2023 +0100

aarch64: Fix memtag intrinsic availability

The availability of memtag intrinsics and data types were determined
solely by the globally specified architecture features, which did not
reflect any changes specified in target pragmas or attributes.

This patch removes the initialisation-time guards for the intrinsics,
and replaces them with checks at use time. It also removes the macro
indirection from the header file - this simplifies the header, and
allows the missing extension error reporting to find the user-facing
intrinsic names.

gcc/ChangeLog:

PR target/112108
* config/aarch64/aarch64-builtins.cc (aarch64_init_memtag_builtins):
Define intrinsic names directly.
(aarch64_general_init_builtins): Move memtag intialisation...
(handle_arm_acle_h): ...to here, and remove feature check.
(aarch64_general_check_builtin_call): Check memtag intrinsics.
* config/aarch64/arm_acle.h (__arm_mte_create_random_tag)
(__arm_mte_exclude_tag, __arm_mte_ptrdiff)
(__arm_mte_increment_tag, __arm_mte_set_tag, __arm_mte_get_tag):
Remove.

gcc/testsuite/ChangeLog:

PR target/112108
* gcc.target/aarch64/acle/memtag_guard-1.c: New test.
* gcc.target/aarch64/acle/memtag_guard-2.c: New test.
* gcc.target/aarch64/acle/memtag_guard-3.c: New test.
* gcc.target/aarch64/acle/memtag_guard-4.c: New test.

Diff:
---
 gcc/config/aarch64/aarch64-builtins.cc | 23 --
 gcc/config/aarch64/arm_acle.h  | 23 --
 .../gcc.target/aarch64/acle/memtag_guard-1.c   |  9 +
 .../gcc.target/aarch64/acle/memtag_guard-2.c   | 10 ++
 .../gcc.target/aarch64/acle/memtag_guard-3.c   |  9 +
 .../gcc.target/aarch64/acle/memtag_guard-4.c   | 10 ++
 6 files changed, 51 insertions(+), 33 deletions(-)

diff --git a/gcc/config/aarch64/aarch64-builtins.cc 
b/gcc/config/aarch64/aarch64-builtins.cc
index 70437641219..ba04424645d 100644
--- a/gcc/config/aarch64/aarch64-builtins.cc
+++ b/gcc/config/aarch64/aarch64-builtins.cc
@@ -1850,27 +1850,27 @@ aarch64_init_memtag_builtins (void)
 
 #define AARCH64_INIT_MEMTAG_BUILTINS_DECL(F, N, I, T) \
   aarch64_builtin_decls[AARCH64_MEMTAG_BUILTIN_##F] \
-= aarch64_general_add_builtin ("__builtin_aarch64_memtag_"#N, \
-  T, AARCH64_MEMTAG_BUILTIN_##F); \
+= aarch64_general_simulate_builtin ("__arm_mte_"#N, T, \
+   AARCH64_MEMTAG_BUILTIN_##F); \
   aarch64_memtag_builtin_data[AARCH64_MEMTAG_BUILTIN_##F - \
  AARCH64_MEMTAG_BUILTIN_START - 1] = \
{T, CODE_FOR_##I};
 
   fntype = build_function_type_list (ptr_type_node, ptr_type_node,
 uint64_type_node, NULL);
-  AARCH64_INIT_MEMTAG_BUILTINS_DECL (IRG, irg, irg, fntype);
+  AARCH64_INIT_MEMTAG_BUILTINS_DECL (IRG, create_random_tag, irg, fntype);
 
   fntype = build_function_type_list (uint64_type_node, ptr_type_node,
 uint64_type_node, NULL);
-  AARCH64_INIT_MEMTAG_BUILTINS_DECL (GMI, gmi, gmi, fntype);
+  AARCH64_INIT_MEMTAG_BUILTINS_DECL (GMI, exclude_tag, gmi, fntype);
 
   fntype = build_function_type_list (ptrdiff_type_node, ptr_type_node,
 ptr_type_node, NULL);
-  AARCH64_INIT_MEMTAG_BUILTINS_DECL (SUBP, subp, subp, fntype);
+  AARCH64_INIT_MEMTAG_BUILTINS_DECL (SUBP, ptrdiff, subp, fntype);
 
   fntype = build_function_type_list (ptr_type_node, ptr_type_node,
 unsigned_type_node, NULL);
-  AARCH64_INIT_MEMTAG_BUILTINS_DECL (INC_TAG, inc_tag, addg, fntype);
+  AARCH64_INIT_MEMTAG_BUILTINS_DECL (INC_TAG, increment_tag, addg, fntype);
 
   fntype = build_function_type_list (void_type_node, ptr_type_node, NULL);
   AARCH64_INIT_MEMTAG_BUILTINS_DECL (SET_TAG, set_tag, stg, fntype);
@@ -1983,6 +1983,7 @@ handle_arm_acle_h (void)
   if (TARGET_LS64)
 aarch64_init_ls64_builtins ();
   aarch64_init_tme_builtins ();
+  aarch64_init_memtag_builtins ();
 }
 
 /* Initialize fpsr fpcr getters and setters.  */
@@ -2075,9 +2076,6 @@ aarch64_general_init_builtins (void)
   if (!TARGET_ILP32)
 aarch64_init_pauth_hint_builtins ();
 
-  if (TARGET_MEMTAG)
-aarch64_init_memtag_builtins ();
-
   if (in_lto_p)
 handle_arm_acle_h ();
 }
@@ -2234,7 +2232,12 @@ aarch64_general_check_builtin_call (location_t location, 
vec,
 default:
   break;
 }
-  /* Default behavior.  */
+
+  if (code >= AARCH64_MEMTAG_BUILTIN_START
+  && code <= AARCH64_MEMTAG_BUILTI

[gcc r14-10635] aarch64: Fix ls64 intrinsic availability

[Andrew Carlotti via Gcc-cvs]

https://gcc.gnu.org/g:9899be7d5380c732b56ba155d4a9e192a2c483b1

commit r14-10635-g9899be7d5380c732b56ba155d4a9e192a2c483b1
Author: Andrew Carlotti 
Date:   Thu Oct 26 15:45:15 2023 +0100

aarch64: Fix ls64 intrinsic availability

The availability of ls64 intrinsics and data types were determined
solely by the globally specified architecture features, which did not
reflect any changes specified in target pragmas or attributes.

This patch removes the initialisation-time guards for the intrinsics,
and replaces them with checks at use time. We also get better error
messages when ls64 is not available (matching the existing error
messages for SVE intrinsics).

The data512_t type is made always available; this is consistent with the
present behaviour for Neon fp16/bf16 types.

gcc/ChangeLog:

PR target/112108
* config/aarch64/aarch64-builtins.cc (handle_arm_acle_h): Remove
feature check at initialisation.
(aarch64_general_check_builtin_call): Check ls64 intrinsics.
* config/aarch64/arm_acle.h: (data512_t) Make always available.

gcc/testsuite/ChangeLog:

PR target/112108
* gcc.target/aarch64/acle/ls64_guard-1.c: New test.
* gcc.target/aarch64/acle/ls64_guard-2.c: New test.
* gcc.target/aarch64/acle/ls64_guard-3.c: New test.
* gcc.target/aarch64/acle/ls64_guard-4.c: New test.

Diff:
---
 gcc/config/aarch64/aarch64-builtins.cc   | 10 --
 gcc/config/aarch64/arm_acle.h|  2 --
 gcc/testsuite/gcc.target/aarch64/acle/ls64_guard-1.c |  9 +
 gcc/testsuite/gcc.target/aarch64/acle/ls64_guard-2.c | 10 ++
 gcc/testsuite/gcc.target/aarch64/acle/ls64_guard-3.c |  9 +
 gcc/testsuite/gcc.target/aarch64/acle/ls64_guard-4.c | 10 ++
 6 files changed, 46 insertions(+), 4 deletions(-)

diff --git a/gcc/config/aarch64/aarch64-builtins.cc 
b/gcc/config/aarch64/aarch64-builtins.cc
index ba04424645d..d5b5700d25d 100644
--- a/gcc/config/aarch64/aarch64-builtins.cc
+++ b/gcc/config/aarch64/aarch64-builtins.cc
@@ -1980,8 +1980,7 @@ aarch64_init_data_intrinsics (void)
 void
 handle_arm_acle_h (void)
 {
-  if (TARGET_LS64)
-aarch64_init_ls64_builtins ();
+  aarch64_init_ls64_builtins ();
   aarch64_init_tme_builtins ();
   aarch64_init_memtag_builtins ();
 }
@@ -2229,6 +2228,13 @@ aarch64_general_check_builtin_call (location_t location, 
vec,
   return aarch64_check_required_extensions (location, decl,
AARCH64_FL_TME);
 
+case AARCH64_LS64_BUILTIN_LD64B:
+case AARCH64_LS64_BUILTIN_ST64B:
+case AARCH64_LS64_BUILTIN_ST64BV:
+case AARCH64_LS64_BUILTIN_ST64BV0:
+  return aarch64_check_required_extensions (location, decl,
+   AARCH64_FL_LS64);
+
 default:
   break;
 }
diff --git a/gcc/config/aarch64/arm_acle.h b/gcc/config/aarch64/arm_acle.h
index ab043267913..ab4e7e60e04 100644
--- a/gcc/config/aarch64/arm_acle.h
+++ b/gcc/config/aarch64/arm_acle.h
@@ -265,9 +265,7 @@ __crc32d (uint32_t __a, uint64_t __b)
 #define _TMFAILURE_INT0x0080u
 #define _TMFAILURE_TRIVIAL0x0100u
 
-#ifdef __ARM_FEATURE_LS64
 typedef __arm_data512_t data512_t;
-#endif
 
 #pragma GCC push_options
 #pragma GCC target ("+nothing+rng")
diff --git a/gcc/testsuite/gcc.target/aarch64/acle/ls64_guard-1.c 
b/gcc/testsuite/gcc.target/aarch64/acle/ls64_guard-1.c
new file mode 100644
index 000..7dfc193a293
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/acle/ls64_guard-1.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=armv8.6-a" } */
+
+#include 
+
+data512_t foo (void * p)
+{
+  return __arm_ld64b (p); /* { dg-error {ACLE function '__arm_ld64b' requires 
ISA extension 'ls64'} } */
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/acle/ls64_guard-2.c 
b/gcc/testsuite/gcc.target/aarch64/acle/ls64_guard-2.c
new file mode 100644
index 000..3ede05a81f0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/acle/ls64_guard-2.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=armv8.6-a" } */
+
+#include 
+
+#pragma GCC target("arch=armv8-a+ls64")
+data512_t foo (void * p)
+{
+  return __arm_ld64b (p);
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/acle/ls64_guard-3.c 
b/gcc/testsuite/gcc.target/aarch64/acle/ls64_guard-3.c
new file mode 100644
index 000..e0fccdad7be
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/acle/ls64_guard-3.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=armv8-a+ls64 -mgeneral-regs-only" } */
+
+#include 
+
+data512_t foo (void * p)
+{
+  return __arm_ld64b (p);
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/acle/ls64_guard-4.c 
b/gcc/testsuite/gcc.target/aarch64/acle/ls64_guard-4.c
new file mode 100644
index 000..af1d9

[gcc r15-2260] aarch64: Remove unused global aarch64_tune_flags

[Andrew Carlotti via Gcc-cvs]

https://gcc.gnu.org/g:4cb933f8f9ff223695b4929a32aa736c6b218e37

commit r15-2260-g4cb933f8f9ff223695b4929a32aa736c6b218e37
Author: Andrew Carlotti 
Date:   Wed Apr 17 19:28:20 2024 +0100

aarch64: Remove unused global aarch64_tune_flags

gcc/ChangeLog:

* config/aarch64/aarch64.cc
(aarch64_tune_flags): Remove unused global variable.
(aarch64_override_options_internal): Remove dead assignment.

Diff:
---
 gcc/config/aarch64/aarch64.cc | 4 
 1 file changed, 4 deletions(-)

diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc
index 9e51236ce9fa..d8fbd7102e7b 100644
--- a/gcc/config/aarch64/aarch64.cc
+++ b/gcc/config/aarch64/aarch64.cc
@@ -349,9 +349,6 @@ static bool aarch64_print_address_internal (FILE*, 
machine_mode, rtx,
 /* The processor for which instructions should be scheduled.  */
 enum aarch64_processor aarch64_tune = cortexa53;
 
-/* Mask to specify which instruction scheduling options should be used.  */
-uint64_t aarch64_tune_flags = 0;
-
 /* Global flag for PC relative loads.  */
 bool aarch64_pcrelative_literal_loads;
 
@@ -18273,7 +18270,6 @@ void
 aarch64_override_options_internal (struct gcc_options *opts)
 {
   const struct processor *tune = aarch64_get_tune_cpu (opts->x_selected_tune);
-  aarch64_tune_flags = tune->flags;
   aarch64_tune = tune->sched_core;
   /* Make a copy of the tuning parameters attached to the core, which
  we may later overwrite.  */

[gcc r15-2261] aarch64: Move AARCH64_NUM_ISA_MODES definition

[Andrew Carlotti via Gcc-cvs]

https://gcc.gnu.org/g:f11692fbfd85e6d62ecdb07e5affb611b29a6715

commit r15-2261-gf11692fbfd85e6d62ecdb07e5affb611b29a6715
Author: Andrew Carlotti 
Date:   Fri May 3 16:09:27 2024 +0100

aarch64: Move AARCH64_NUM_ISA_MODES definition

AARCH64_NUM_ISA_MODES will be used within aarch64-opts.h in a later
commit.

gcc/ChangeLog:

* config/aarch64/aarch64.h (DEF_AARCH64_ISA_MODE): Move to...
* config/aarch64/aarch64-opts.h (DEF_AARCH64_ISA_MODE): ...here.

Diff:
---
 gcc/config/aarch64/aarch64-opts.h | 5 +
 gcc/config/aarch64/aarch64.h  | 5 -
 2 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/gcc/config/aarch64/aarch64-opts.h 
b/gcc/config/aarch64/aarch64-opts.h
index a05c0d3ded1c..06a4fed38334 100644
--- a/gcc/config/aarch64/aarch64-opts.h
+++ b/gcc/config/aarch64/aarch64-opts.h
@@ -24,6 +24,11 @@
 
 #ifndef USED_FOR_TARGET
 typedef uint64_t aarch64_feature_flags;
+
+constexpr unsigned int AARCH64_NUM_ISA_MODES = (0
+#define DEF_AARCH64_ISA_MODE(IDENT) + 1
+#include "aarch64-isa-modes.def"
+);
 #endif
 
 /* The various cores that implement AArch64.  */
diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h
index fac1882bcb38..2be6dc4089b8 100644
--- a/gcc/config/aarch64/aarch64.h
+++ b/gcc/config/aarch64/aarch64.h
@@ -183,11 +183,6 @@ enum class aarch64_feature : unsigned char {
 
 constexpr auto AARCH64_FL_SM_STATE = AARCH64_FL_SM_ON | AARCH64_FL_SM_OFF;
 
-constexpr unsigned int AARCH64_NUM_ISA_MODES = (0
-#define DEF_AARCH64_ISA_MODE(IDENT) + 1
-#include "aarch64-isa-modes.def"
-);
-
 /* The mask of all ISA modes.  */
 constexpr auto AARCH64_FL_ISA_MODES
   = (aarch64_feature_flags (1) << AARCH64_NUM_ISA_MODES) - 1;

[gcc r15-2262] aarch64: Eliminate a temporary variable.

[Andrew Carlotti via Gcc-cvs]

https://gcc.gnu.org/g:b5fa14e886f0f5f3e10970c705042bc3157be714

commit r15-2262-gb5fa14e886f0f5f3e10970c705042bc3157be714
Author: Andrew Carlotti 
Date:   Fri May 10 12:56:44 2024 +0100

aarch64: Eliminate a temporary variable.

The name would become misleading in a later commit anyway, and I think
this is marginally more readable.

gcc/ChangeLog:

* config/aarch64/aarch64.cc
(aarch64_override_options): Remove temporary variable.

Diff:
---
 gcc/config/aarch64/aarch64.cc | 9 -
 1 file changed, 4 insertions(+), 5 deletions(-)

diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc
index d8fbd7102e7b..4e3a4047ea80 100644
--- a/gcc/config/aarch64/aarch64.cc
+++ b/gcc/config/aarch64/aarch64.cc
@@ -18856,7 +18856,6 @@ aarch64_override_options (void)
   SUBTARGET_OVERRIDE_OPTIONS;
 #endif
 
-  auto isa_mode = AARCH64_FL_DEFAULT_ISA_MODE;
   if (cpu && arch)
 {
   /* If both -mcpu and -march are specified, warn if they are not
@@ -18879,25 +18878,25 @@ aarch64_override_options (void)
}
 
   selected_arch = arch->arch;
-  aarch64_set_asm_isa_flags (arch_isa | isa_mode);
+  aarch64_set_asm_isa_flags (arch_isa | AARCH64_FL_DEFAULT_ISA_MODE);
 }
   else if (cpu)
 {
   selected_arch = cpu->arch;
-  aarch64_set_asm_isa_flags (cpu_isa | isa_mode);
+  aarch64_set_asm_isa_flags (cpu_isa | AARCH64_FL_DEFAULT_ISA_MODE);
 }
   else if (arch)
 {
   cpu = &all_cores[arch->ident];
   selected_arch = arch->arch;
-  aarch64_set_asm_isa_flags (arch_isa | isa_mode);
+  aarch64_set_asm_isa_flags (arch_isa | AARCH64_FL_DEFAULT_ISA_MODE);
 }
   else
 {
   /* No -mcpu or -march specified, so use the default CPU.  */
   cpu = &all_cores[TARGET_CPU_DEFAULT];
   selected_arch = cpu->arch;
-  aarch64_set_asm_isa_flags (cpu->flags | isa_mode);
+  aarch64_set_asm_isa_flags (cpu->flags | AARCH64_FL_DEFAULT_ISA_MODE);
 }
 
   selected_tune = tune ? tune->ident : cpu->ident;

[gcc r15-2264] aarch64: Define aarch64_get_{asm_|}isa_flags

[Andrew Carlotti via Gcc-cvs]

https://gcc.gnu.org/g:c0ed0823a6fa35dc074d3323163473a663721441

commit r15-2264-gc0ed0823a6fa35dc074d3323163473a663721441
Author: Andrew Carlotti 
Date:   Fri May 10 11:46:17 2024 +0100

aarch64: Define aarch64_get_{asm_|}isa_flags

Building an aarch64_feature_flags value from data within a gcc_options
or cl_target_option struct will get more complicated in a later commit.
Use a macro to avoid doing this manually in more than one location.

gcc/ChangeLog:

* common/config/aarch64/aarch64-common.cc
(aarch64_handle_option): Use new macro.
* config/aarch64/aarch64.cc
(aarch64_override_options_internal): Ditto.
(aarch64_option_print): Ditto.
(aarch64_set_current_function): Ditto.
(aarch64_can_inline_p): Ditto.
(aarch64_declare_function_name): Ditto.
(aarch64_start_file): Ditto.
* config/aarch64/aarch64.h (aarch64_get_asm_isa_flags): New
(aarch64_get_isa_flags): New.
(aarch64_asm_isa_flags): Use new macro.
(aarch64_isa_flags): Ditto.

Diff:
---
 gcc/common/config/aarch64/aarch64-common.cc |  2 +-
 gcc/config/aarch64/aarch64.cc   | 36 ++---
 gcc/config/aarch64/aarch64.h| 11 +
 3 files changed, 26 insertions(+), 23 deletions(-)

diff --git a/gcc/common/config/aarch64/aarch64-common.cc 
b/gcc/common/config/aarch64/aarch64-common.cc
index 951d041d3109..63c50189a09d 100644
--- a/gcc/common/config/aarch64/aarch64-common.cc
+++ b/gcc/common/config/aarch64/aarch64-common.cc
@@ -111,7 +111,7 @@ aarch64_handle_option (struct gcc_options *opts,
 
 case OPT_mgeneral_regs_only:
   opts->x_target_flags |= MASK_GENERAL_REGS_ONLY;
-  aarch64_set_asm_isa_flags (opts, opts->x_aarch64_asm_isa_flags);
+  aarch64_set_asm_isa_flags (opts, aarch64_get_asm_isa_flags (opts));
   return true;
 
 case OPT_mfix_cortex_a53_835769:
diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc
index 1b343c9ae1c7..66ce04d77e17 100644
--- a/gcc/config/aarch64/aarch64.cc
+++ b/gcc/config/aarch64/aarch64.cc
@@ -18329,10 +18329,11 @@ aarch64_override_options_internal (struct gcc_options 
*opts)
   && !fixed_regs[R18_REGNUM])
 error ("%<-fsanitize=shadow-call-stack%> requires %<-ffixed-x18%>");
 
-  if ((opts->x_aarch64_isa_flags & (AARCH64_FL_SM_ON | AARCH64_FL_ZA_ON))
-  && !(opts->x_aarch64_isa_flags & AARCH64_FL_SME))
+  aarch64_feature_flags isa_flags = aarch64_get_isa_flags (opts);
+  if ((isa_flags & (AARCH64_FL_SM_ON | AARCH64_FL_ZA_ON))
+  && !(isa_flags & AARCH64_FL_SME))
 {
-  if (opts->x_aarch64_isa_flags & AARCH64_FL_SM_ON)
+  if (isa_flags & AARCH64_FL_SM_ON)
error ("streaming functions require the ISA extension %qs", "sme");
   else
error ("functions with SME state require the ISA extension %qs",
@@ -18341,8 +18342,7 @@ aarch64_override_options_internal (struct gcc_options 
*opts)
  " option %<-march%>, or by using the %"
  " attribute or pragma", "sme");
   opts->x_target_flags &= ~MASK_GENERAL_REGS_ONLY;
-  auto new_flags = (opts->x_aarch64_asm_isa_flags
-   | feature_deps::SME ().enable);
+  auto new_flags = isa_flags | feature_deps::SME ().enable;
   aarch64_set_asm_isa_flags (opts, new_flags);
 }
 
@@ -19036,9 +19036,9 @@ aarch64_option_print (FILE *file, int indent, struct 
cl_target_option *ptr)
   const struct processor *cpu
 = aarch64_get_tune_cpu (ptr->x_selected_tune);
   const struct processor *arch = aarch64_get_arch (ptr->x_selected_arch);
+  aarch64_feature_flags isa_flags = aarch64_get_asm_isa_flags(ptr);
   std::string extension
-= aarch64_get_extension_string_for_isa_flags (ptr->x_aarch64_asm_isa_flags,
- arch->flags);
+= aarch64_get_extension_string_for_isa_flags (isa_flags, arch->flags);
 
   fprintf (file, "%*sselected tune = %s\n", indent, "", cpu->name);
   fprintf (file, "%*sselected arch = %s%s\n", indent, "",
@@ -19098,7 +19098,7 @@ aarch64_set_current_function (tree fndecl)
   auto new_isa_mode = (fndecl
   ? aarch64_fndecl_isa_mode (fndecl)
   : AARCH64_DEFAULT_ISA_MODE);
-  auto isa_flags = TREE_TARGET_OPTION (new_tree)->x_aarch64_isa_flags;
+  auto isa_flags = aarch64_get_isa_flags (TREE_TARGET_OPTION (new_tree));
 
   static bool reported_zt0_p;
   if (!reported_zt0_p
@@ -20703,16 +20703,16 @@ aarch64_can_inline_p (tree caller, tree callee)
   : target_option_default_node);
 
   /* Callee's ISA flags should be a subset of the caller's.  */
-  auto caller_asm_isa = (caller_opts->x_aarch64_asm_isa_flags
+  auto caller_asm_isa = (aarch64_get_asm_isa_flags (caller_opts)
 & ~AARCH64_FL_ISA_MODES);
-  auto callee_asm_isa = (callee_opts->x_aarch64_asm_isa_fla

[gcc r15-2265] aarch64: Decouple feature flag option storage type

[Andrew Carlotti via Gcc-cvs]

https://gcc.gnu.org/g:033d9053dae3c1aafae63d22641adb49210301d8

commit r15-2265-g033d9053dae3c1aafae63d22641adb49210301d8
Author: Andrew Carlotti 
Date:   Fri May 10 11:56:57 2024 +0100

aarch64: Decouple feature flag option storage type

The awk scripts that process the .opt files are relatively fragile and
only handle a limited set of data types correctly.  The unrecognised
aarch64_feature_flags type is handled as a uint64_t, which happens to be
correct for now.  However, that assumption will change when we extend
the mask to 128 bits.

This patch changes the option members to use uint64_t types, and adds a
"_0" suffix to the names (both for future extensibility, and to allow
the original name to be used for the full aarch64_feature_flags mask
within generator files).

gcc/ChangeLog:

* common/config/aarch64/aarch64-common.cc
(aarch64_set_asm_isa_flags): Reorder, and add suffix to names.
* config/aarch64/aarch64.h
(aarch64_get_asm_isa_flags): Add "_0" suffix.
(aarch64_get_isa_flags): Ditto.
(aarch64_asm_isa_flags): Redefine using renamed uint64_t value.
(aarch64_isa_flags): Ditto.
* config/aarch64/aarch64.opt:
(aarch64_asm_isa_flags): Rename to...
(aarch64_asm_isa_flags_0): ...this, and change to uint64_t.
(aarch64_isa_flags): Rename to...
(aarch64_isa_flags_0): ...this, and change to uint64_t.

Diff:
---
 gcc/common/config/aarch64/aarch64-common.cc | 11 ++-
 gcc/config/aarch64/aarch64.h| 11 ---
 gcc/config/aarch64/aarch64.opt  |  4 ++--
 3 files changed, 16 insertions(+), 10 deletions(-)

diff --git a/gcc/common/config/aarch64/aarch64-common.cc 
b/gcc/common/config/aarch64/aarch64-common.cc
index 63c50189a09d..bd0770dd0d84 100644
--- a/gcc/common/config/aarch64/aarch64-common.cc
+++ b/gcc/common/config/aarch64/aarch64-common.cc
@@ -66,15 +66,16 @@ static const struct default_options 
aarch_option_optimization_table[] =
 { OPT_LEVELS_NONE, 0, NULL, 0 }
   };
 
-/* Set OPTS->x_aarch64_asm_isa_flags to FLAGS and update
-   OPTS->x_aarch64_isa_flags accordingly.  */
+
+/* Set OPTS->x_aarch64_asm_isa_flags_0 to FLAGS and update
+   OPTS->x_aarch64_isa_flags_0 accordingly.  */
 void
 aarch64_set_asm_isa_flags (gcc_options *opts, aarch64_feature_flags flags)
 {
-  opts->x_aarch64_asm_isa_flags = flags;
-  opts->x_aarch64_isa_flags = flags;
+  opts->x_aarch64_asm_isa_flags_0 = flags;
   if (opts->x_target_flags & MASK_GENERAL_REGS_ONLY)
-opts->x_aarch64_isa_flags &= ~feature_deps::get_flags_off (AARCH64_FL_FP);
+flags &= ~feature_deps::get_flags_off (AARCH64_FL_FP);
+  opts->x_aarch64_isa_flags_0 = flags;
 }
 
 /* Implement TARGET_HANDLE_OPTION.
diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h
index 193f2486176b..903e708565dc 100644
--- a/gcc/config/aarch64/aarch64.h
+++ b/gcc/config/aarch64/aarch64.h
@@ -23,13 +23,18 @@
 #define GCC_AARCH64_H
 
 #define aarch64_get_asm_isa_flags(opts) \
-  (aarch64_feature_flags ((opts)->x_aarch64_asm_isa_flags))
+  (aarch64_feature_flags ((opts)->x_aarch64_asm_isa_flags_0))
 #define aarch64_get_isa_flags(opts) \
-  (aarch64_feature_flags ((opts)->x_aarch64_isa_flags))
+  (aarch64_feature_flags ((opts)->x_aarch64_isa_flags_0))
 
 /* Make these flags read-only so that all uses go via
aarch64_set_asm_isa_flags.  */
-#ifndef GENERATOR_FILE
+#ifdef GENERATOR_FILE
+#undef aarch64_asm_isa_flags
+#define aarch64_asm_isa_flags (aarch64_feature_flags (aarch64_asm_isa_flags_0))
+#undef aarch64_isa_flags
+#define aarch64_isa_flags (aarch64_feature_flags (aarch64_isa_flags_0))
+#else
 #undef aarch64_asm_isa_flags
 #define aarch64_asm_isa_flags (aarch64_get_asm_isa_flags (&global_options))
 #undef aarch64_isa_flags
diff --git a/gcc/config/aarch64/aarch64.opt b/gcc/config/aarch64/aarch64.opt
index 6356c419399b..45aab49de27b 100644
--- a/gcc/config/aarch64/aarch64.opt
+++ b/gcc/config/aarch64/aarch64.opt
@@ -31,10 +31,10 @@ TargetVariable
 enum aarch64_arch selected_arch = aarch64_no_arch
 
 TargetVariable
-aarch64_feature_flags aarch64_asm_isa_flags = 0
+uint64_t aarch64_asm_isa_flags_0 = 0
 
 TargetVariable
-aarch64_feature_flags aarch64_isa_flags = 0
+uint64_t aarch64_isa_flags_0 = 0
 
 TargetVariable
 unsigned aarch_enable_bti = 2

[gcc r15-2266] aarch64: Add explicit bool cast to return value

[Andrew Carlotti via Gcc-cvs]

https://gcc.gnu.org/g:7700fe40b5281057640b61c9b04fc608f9cdc3c2

commit r15-2266-g7700fe40b5281057640b61c9b04fc608f9cdc3c2
Author: Andrew Carlotti 
Date:   Wed Jul 10 15:00:16 2024 +0100

aarch64: Add explicit bool cast to return value

gcc/ChangeLog:

* config/aarch64/aarch64.cc
(aarch64_valid_sysreg_name_p): Add bool cast.

Diff:
---
 gcc/config/aarch64/aarch64.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc
index 66ce04d77e17..7c2af1316b67 100644
--- a/gcc/config/aarch64/aarch64.cc
+++ b/gcc/config/aarch64/aarch64.cc
@@ -30296,7 +30296,7 @@ aarch64_valid_sysreg_name_p (const char *regname)
   if (sysreg == NULL)
 return aarch64_is_implem_def_reg (regname);
   if (sysreg->arch_reqs)
-return (aarch64_isa_flags & sysreg->arch_reqs);
+return bool (aarch64_isa_flags & sysreg->arch_reqs);
   return true;
 }

[gcc r15-2267] aarch64: Add bool conversion to TARGET_* macros

[Andrew Carlotti via Gcc-cvs]

https://gcc.gnu.org/g:8797a869c011f99ada3aced877b187f5430ec2f3

commit r15-2267-g8797a869c011f99ada3aced877b187f5430ec2f3
Author: Andrew Carlotti 
Date:   Wed Jul 10 14:42:37 2024 +0100

aarch64: Add bool conversion to TARGET_* macros

Use a new AARCH64_HAVE_ISA macro in TARGET_* definitions, and eliminate
all the AARCH64_ISA_* feature macros.

gcc/ChangeLog:

* config/aarch64/aarch64-c.cc
(aarch64_define_unconditional_macros): Use TARGET_V8R macro.
(aarch64_update_cpp_builtins): Use TARGET_* macros.
* config/aarch64/aarch64.h (AARCH64_HAVE_ISA): New macro.
(AARCH64_ISA_SM_OFF, AARCH64_ISA_SM_ON, AARCH64_ISA_ZA_ON)
(AARCH64_ISA_V8A, AARCH64_ISA_V8_1A, AARCH64_ISA_CRC)
(AARCH64_ISA_FP, AARCH64_ISA_SIMD, AARCH64_ISA_LSE)
(AARCH64_ISA_RDMA, AARCH64_ISA_V8_2A, AARCH64_ISA_F16)
(AARCH64_ISA_SVE, AARCH64_ISA_SVE2, AARCH64_ISA_SVE2_AES)
(AARCH64_ISA_SVE2_BITPERM, AARCH64_ISA_SVE2_SHA3)
(AARCH64_ISA_SVE2_SM4, AARCH64_ISA_SME, AARCH64_ISA_SME_I16I64)
(AARCH64_ISA_SME_F64F64, AARCH64_ISA_SME2, AARCH64_ISA_V8_3A)
(AARCH64_ISA_DOTPROD, AARCH64_ISA_AES, AARCH64_ISA_SHA2)
(AARCH64_ISA_V8_4A, AARCH64_ISA_SM4, AARCH64_ISA_SHA3)
(AARCH64_ISA_F16FML, AARCH64_ISA_RCPC, AARCH64_ISA_RCPC8_4)
(AARCH64_ISA_RNG, AARCH64_ISA_V8_5A, AARCH64_ISA_TME)
(AARCH64_ISA_MEMTAG, AARCH64_ISA_V8_6A, AARCH64_ISA_I8MM)
(AARCH64_ISA_F32MM, AARCH64_ISA_F64MM, AARCH64_ISA_BF16)
(AARCH64_ISA_SB, AARCH64_ISA_RCPC3, AARCH64_ISA_V8R)
(AARCH64_ISA_PAUTH, AARCH64_ISA_V8_7A, AARCH64_ISA_V8_8A)
(AARCH64_ISA_V8_9A, AARCH64_ISA_V9A, AARCH64_ISA_V9_1A)
(AARCH64_ISA_V9_2A, AARCH64_ISA_V9_3A, AARCH64_ISA_V9_4A)
(AARCH64_ISA_MOPS, AARCH64_ISA_LS64, AARCH64_ISA_CSSC)
(AARCH64_ISA_D128, AARCH64_ISA_THE, AARCH64_ISA_GCS): Remove.
(TARGET_BASE_SIMD, TARGET_SIMD, TARGET_FLOAT)
(TARGET_NON_STREAMING, TARGET_STREAMING, TARGET_ZA, TARGET_SHA2)
(TARGET_SHA3, TARGET_AES, TARGET_SM4, TARGET_F16FML)
(TARGET_CRC32, TARGET_LSE, TARGET_FP_F16INST)
(TARGET_SIMD_F16INST, TARGET_DOTPROD, TARGET_SVE, TARGET_SVE2)
(TARGET_SVE2_AES, TARGET_SVE2_BITPERM, TARGET_SVE2_SHA3)
(TARGET_SVE2_SM4, TARGET_SME, TARGET_SME_I16I64)
(TARGET_SME_F64F64, TARGET_SME2, TARGET_ARMV8_3, TARGET_JSCVT)
(TARGET_FRINT, TARGET_TME, TARGET_RNG, TARGET_MEMTAG)
(TARGET_I8MM, TARGET_SVE_I8MM, TARGET_SVE_F32MM)
(TARGET_SVE_F64MM, TARGET_BF16_FP, TARGET_BF16_SIMD)
(TARGET_SVE_BF16, TARGET_PAUTH, TARGET_BTI, TARGET_MOPS)
(TARGET_LS64, TARGET_CSSC, TARGET_SB, TARGET_RCPC, TARGET_RCPC2)
(TARGET_RCPC3, TARGET_SIMD_RDMA, TARGET_ARMV9_4, TARGET_D128)
(TARGET_THE, TARGET_GCS): Redefine using AARCH64_HAVE_ISA.
(TARGET_V8R, TARGET_V9A): New.
* config/aarch64/aarch64.md (arch_enabled): Use TARGET_RCPC2.
* config/aarch64/iterators.md (GPI_I16): Use TARGET_FP_F16INST.
(GPF_F16): Ditto.
* config/aarch64/predicates.md
(aarch64_rcpc_memory_operand): Use TARGET_RCPC2.

Diff:
---
 gcc/config/aarch64/aarch64-c.cc  |   6 +-
 gcc/config/aarch64/aarch64.h | 196 ++-
 gcc/config/aarch64/aarch64.md|   2 +-
 gcc/config/aarch64/iterators.md  |   4 +-
 gcc/config/aarch64/predicates.md |   2 +-
 5 files changed, 79 insertions(+), 131 deletions(-)

diff --git a/gcc/config/aarch64/aarch64-c.cc b/gcc/config/aarch64/aarch64-c.cc
index 2aff097dd33c..f9b9e3793755 100644
--- a/gcc/config/aarch64/aarch64-c.cc
+++ b/gcc/config/aarch64/aarch64-c.cc
@@ -64,7 +64,7 @@ aarch64_define_unconditional_macros (cpp_reader *pfile)
   builtin_define ("__ARM_ARCH_8A");
 
   builtin_define_with_int_value ("__ARM_ARCH_PROFILE",
-  AARCH64_ISA_V8R ? 'R' : 'A');
+  TARGET_V8R ? 'R' : 'A');
   builtin_define ("__ARM_FEATURE_CLZ");
   builtin_define ("__ARM_FEATURE_IDIV");
   builtin_define ("__ARM_FEATURE_UNALIGNED");
@@ -132,7 +132,7 @@ aarch64_update_cpp_builtins (cpp_reader *pfile)
   aarch64_def_or_undef (flag_unsafe_math_optimizations, "__ARM_FP_FAST", 
pfile);
 
   cpp_undef (pfile, "__ARM_ARCH");
-  builtin_define_with_int_value ("__ARM_ARCH", AARCH64_ISA_V9A ? 9 : 8);
+  builtin_define_with_int_value ("__ARM_ARCH", TARGET_V9A ? 9 : 8);
 
   builtin_define_with_int_value ("__ARM_SIZEOF_MINIMAL_ENUM",
 flag_short_enums ? 1 : 4);
@@ -259,7 +259,7 @@ aarch64_update_cpp_builtins (cpp_reader *pfile)
 
   aarch64_def_or_undef (TARGET_LS64,
"__ARM_FEATURE_LS64", pfile);
-  aarch64_def_or_undef (AARCH64_ISA_RCPC, "__ARM_FEATURE_RCPC", pfile);
+  aarch64_def_or_undef (TARGET_RCPC, "__ARM_FEATURE_RCPC", pf

[gcc r15-2269] Add new bbitmap class

[Andrew Carlotti via Gcc-cvs]

https://gcc.gnu.org/g:181fdad106c353529850b3af7687a1b9b7509b0b

commit r15-2269-g181fdad106c353529850b3af7687a1b9b7509b0b
Author: Andrew Carlotti 
Date:   Fri Jun 21 18:59:25 2024 +0100

Add new bbitmap class

This class provides a constant-size bitmap that can be used as almost a
drop-in replacement for bitmaps stored in integer types.  The
implementation is entirely within the header file and uses recursive
templated operations to support effective optimisation and usage in
constexpr expressions.

This initial implementation hardcodes the choice of uint64_t elements
for storage and initialisation, but this could instead be specified via
a second template parameter.

gcc/ChangeLog:

* bbitmap.h: New file.

Diff:
---
 gcc/bbitmap.h | 236 ++
 1 file changed, 236 insertions(+)

diff --git a/gcc/bbitmap.h b/gcc/bbitmap.h
new file mode 100644
index ..716c013b1035
--- /dev/null
+++ b/gcc/bbitmap.h
@@ -0,0 +1,236 @@
+/* Functions to support fixed-length bitmaps.
+   Copyright (C) 2024 Free Software Foundation, Inc.
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify it under
+the terms of the GNU General Public License as published by the Free
+Software Foundation; either version 3, or (at your option) any later
+version.
+
+GCC is distributed in the hope that it will be useful, but WITHOUT ANY
+WARRANTY; without even the implied warranty of MERCHANTABILITY or
+FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+for more details.
+
+You should have received a copy of the GNU General Public License
+along with GCC; see the file COPYING3.  If not see
+.  */
+
+#ifndef GCC_BBITMAP_H
+#define GCC_BBITMAP_H
+
+/* Implementation of bounded (fixed length) bitmaps.
+
+   This provides a drop-in replacement for bitmaps that have outgrown the
+   storage capacity of a single integer.
+
+   Sets are stored as a fixed length array of uint64_t elements.  The length of
+   this array is given as a template parameter.  */
+
+/* Use recusive templated functions to define constexpr operations.  */
+template
+struct bbitmap_operators
+{
+  /* Return a result that maps binary operator OP to elements [0, M) of
+ X and Y, and takes the remaining elements from REST.  */
+  template
+  static constexpr Result binary(Operator op, const Arg &x, const Arg &y,
+Rest ...rest)
+  {
+return bbitmap_operators::template binary
+  (op, x, y, op (x.val[M - 1], y.val[M - 1]), rest...);
+  }
+
+  /* Return a result that contains the bitwise inverse of elements [0, M) of X,
+ and takes the remaining elements from REST.  */
+  template
+  static constexpr Result bit_not(const Arg &x, Rest ...rest)
+  {
+return bbitmap_operators::template bit_not
+  (x, ~(x.val[M - 1]), rest...);
+  }
+
+  /* Return true if any element [0, M) of X is nonzero.  */
+  template
+  static constexpr bool non_zero(const Arg &x)
+  {
+return (bool) x.val[M - 1]
+  || bbitmap_operators::template non_zero (x);
+  }
+
+  /* Return true if elements [0, M) of X are all equal to the corresponding
+ elements of Y.  */
+  template
+  static constexpr bool equal(const Arg &x, const Arg &y)
+  {
+return x.val[M - 1] == y.val[M - 1]
+  && bbitmap_operators::template equal (x, y);
+  }
+
+  /* If bit index INDEX selects a bit in the first M elements, return a
+ Result with that bit set and the other bits of the leading M elements
+ clear.  Clear the leading M elements otherwise.  Take the remaining
+ elements of the Result from REST.  */
+  template
+  static constexpr Result from_index(int index, Rest ...rest)
+  {
+return bbitmap_operators::template from_index
+  (index,
+   uint64_t ((index - (M - 1) * 64) == (index & 63)) << (index & 63),
+   rest...);
+  }
+};
+
+/* These functions form the base for the recursive functions above.  They
+   return either bitmap containing the elements passed in REST, or a default
+   bool result.  */
+template<>
+struct bbitmap_operators<0>
+{
+  template
+  static constexpr Result binary(Operator, const Arg, const Arg,
+Rest ...rest)
+  {
+return Result { rest... };
+  }
+
+  template
+  static constexpr Result bit_not(const Arg, Rest ...rest)
+  {
+return Result { rest... };
+  }
+
+  template
+  static constexpr bool non_zero(const Arg)
+  {
+return false;
+  }
+
+  template
+  static constexpr bool equal(const Arg, const Arg)
+  {
+return true;
+  }
+
+  template
+  static constexpr Result from_index(int, Rest ...rest)
+  {
+return Result { rest... };
+  }
+};
+
+template
+constexpr T bbitmap_element_or(T x, T y) { return x | y;}
+
+template
+constexpr T bbitmap_element_and(T x, T y) { return x & y;}
+
+template
+constexpr T bbitmap_element_xor(T x, T y) { return x ^ y;}

[gcc r15-2270] aarch64: Extend aarch64_feature_flags to 128 bits

[Andrew Carlotti via Gcc-cvs]

https://gcc.gnu.org/g:129b40529e906f423f008b484206ef6edeb21f42

commit r15-2270-g129b40529e906f423f008b484206ef6edeb21f42
Author: Andrew Carlotti 
Date:   Fri May 10 13:34:34 2024 +0100

aarch64: Extend aarch64_feature_flags to 128 bits

Replace the existing uint64_t typedef with a bbitmap<2> typedef.  Most
of the preparatory work was carried out in previous commits, so this
patch itself is fairly small.

gcc/ChangeLog:

* common/config/aarch64/aarch64-common.cc
(aarch64_set_asm_isa_flags): Store a second uint64_t value.
* config/aarch64/aarch64-opts.h
(aarch64_feature_flags): Switch typedef to bbitmap<2>.
* config/aarch64/aarch64.cc
(aarch64_set_current_function): Extract isa mode from val[0].
* config/aarch64/aarch64.h
(aarch64_get_asm_isa_flags): Load a second uint64_t value.
(aarch64_get_isa_flags): Ditto.
(aarch64_asm_isa_flags): Ditto.
(aarch64_isa_flags): Ditto.
(HANDLE): Use bbitmap<2>::from_index to initialise flags.
(AARCH64_FL_ISA_MODES): Do arithmetic on integer type.
(AARCH64_ISA_MODE): Extract value from bbitmap<2> array.
* config/aarch64/aarch64.opt
(aarch64_asm_isa_flags_1): New variable.
(aarch64_isa_flags_1): Ditto.

Diff:
---
 gcc/common/config/aarch64/aarch64-common.cc | 12 
 gcc/config/aarch64/aarch64-opts.h   |  6 --
 gcc/config/aarch64/aarch64.cc   |  6 +++---
 gcc/config/aarch64/aarch64.h| 20 
 gcc/config/aarch64/aarch64.opt  |  6 ++
 5 files changed, 33 insertions(+), 17 deletions(-)

diff --git a/gcc/common/config/aarch64/aarch64-common.cc 
b/gcc/common/config/aarch64/aarch64-common.cc
index bd0770dd0d84..64b65b7ff9e4 100644
--- a/gcc/common/config/aarch64/aarch64-common.cc
+++ b/gcc/common/config/aarch64/aarch64-common.cc
@@ -67,15 +67,19 @@ static const struct default_options 
aarch_option_optimization_table[] =
   };
 
 
-/* Set OPTS->x_aarch64_asm_isa_flags_0 to FLAGS and update
-   OPTS->x_aarch64_isa_flags_0 accordingly.  */
+/* Set OPTS->x_aarch64_asm_isa_flags_<0..n> to FLAGS and update
+   OPTS->x_aarch64_isa_flags_<0..n> accordingly.  */
 void
 aarch64_set_asm_isa_flags (gcc_options *opts, aarch64_feature_flags flags)
 {
-  opts->x_aarch64_asm_isa_flags_0 = flags;
+  opts->x_aarch64_asm_isa_flags_0 = flags.val[0];
+  opts->x_aarch64_asm_isa_flags_1 = flags.val[1];
+
   if (opts->x_target_flags & MASK_GENERAL_REGS_ONLY)
 flags &= ~feature_deps::get_flags_off (AARCH64_FL_FP);
-  opts->x_aarch64_isa_flags_0 = flags;
+
+  opts->x_aarch64_isa_flags_0 = flags.val[0];
+  opts->x_aarch64_isa_flags_1 = flags.val[1];
 }
 
 /* Implement TARGET_HANDLE_OPTION.
diff --git a/gcc/config/aarch64/aarch64-opts.h 
b/gcc/config/aarch64/aarch64-opts.h
index 2c36bfaad19b..80ec1a05253d 100644
--- a/gcc/config/aarch64/aarch64-opts.h
+++ b/gcc/config/aarch64/aarch64-opts.h
@@ -23,14 +23,16 @@
 #define GCC_AARCH64_OPTS_H
 
 #ifndef USED_FOR_TARGET
-typedef uint64_t aarch64_isa_mode;
+#include "bbitmap.h"
 
-typedef uint64_t aarch64_feature_flags;
+typedef uint64_t aarch64_isa_mode;
 
 constexpr unsigned int AARCH64_NUM_ISA_MODES = (0
 #define DEF_AARCH64_ISA_MODE(IDENT) + 1
 #include "aarch64-isa-modes.def"
 );
+
+typedef bbitmap<2> aarch64_feature_flags;
 #endif
 
 /* The various cores that implement AArch64.  */
diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc
index 7c2af1316b67..e0cf382998c7 100644
--- a/gcc/config/aarch64/aarch64.cc
+++ b/gcc/config/aarch64/aarch64.cc
@@ -19119,7 +19119,7 @@ aarch64_set_current_function (tree fndecl)
  aarch64_pragma_target_parse.  */
   if (old_tree == new_tree
   && (!fndecl || aarch64_previous_fndecl)
-  && (aarch64_isa_mode) (isa_flags & AARCH64_FL_ISA_MODES) == new_isa_mode)
+  && (isa_flags & AARCH64_FL_ISA_MODES).val[0] == new_isa_mode)
 {
   gcc_assert (AARCH64_ISA_MODE == new_isa_mode);
   return;
@@ -19134,11 +19134,11 @@ aarch64_set_current_function (tree fndecl)
   /* The ISA mode can vary based on function type attributes and
  function declaration attributes.  Make sure that the target
  options correctly reflect these attributes.  */
-  if ((aarch64_isa_mode) (isa_flags & AARCH64_FL_ISA_MODES) != new_isa_mode)
+  if ((isa_flags & AARCH64_FL_ISA_MODES).val[0] != new_isa_mode)
 {
   auto base_flags = (aarch64_asm_isa_flags & ~AARCH64_FL_ISA_MODES);
   aarch64_set_asm_isa_flags (base_flags
-| (aarch64_feature_flags) new_isa_mode);
+| aarch64_feature_flags (new_isa_mode));
 
   aarch64_override_options_internal (&global_options);
   new_tree = build_target_option_node (&global_options,
diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h
index 6310ebd72ff2..b7e3304

[gcc r15-2263] aarch64: Introduce aarch64_isa_mode type

[Andrew Carlotti via Gcc-cvs]

https://gcc.gnu.org/g:2abf063aee3ed75ab8e7839dad8a701740828f6c

commit r15-2263-g2abf063aee3ed75ab8e7839dad8a701740828f6c
Author: Andrew Carlotti 
Date:   Fri May 3 16:51:05 2024 +0100

aarch64: Introduce aarch64_isa_mode type

Currently there are many places where an aarch64_feature_flags variable
is used, but only the bottom three isa mode bits are set and read.
Using a separate data type for these value makes it more clear that
they're not expected or required to have any of their upper feature bits
set.  It will also make things simpler and more efficient when we extend
aarch64_feature_flags to 128 bits.

This patch uses explicit casts whenever converting from an
aarch64_feature_flags value to an aarch64_isa_mode value.  This isn't
strictly necessary, but serves to highlight the locations where an
explicit conversion will become necessary later.

gcc/ChangeLog:

* config/aarch64/aarch64-opts.h: Add aarch64_isa_mode typedef.
* config/aarch64/aarch64-protos.h
(aarch64_gen_callee_cookie): Use aarch64_isa_mode parameter.
(aarch64_sme_vq_immediate): Ditto.
* config/aarch64/aarch64.cc
(aarch64_fntype_pstate_sm): Use aarch64_isa_mode values.
(aarch64_fntype_pstate_za): Ditto.
(aarch64_fndecl_pstate_sm): Ditto.
(aarch64_fndecl_pstate_za): Ditto.
(aarch64_fndecl_isa_mode): Ditto.
(aarch64_cfun_incoming_pstate_sm): Ditto.
(aarch64_cfun_enables_pstate_sm): Ditto.
(aarch64_call_switches_pstate_sm): Ditto.
(aarch64_gen_callee_cookie): Ditto.
(aarch64_callee_isa_mode): Ditto.
(aarch64_insn_callee_abi): Ditto.
(aarch64_sme_vq_immediate): Ditto.
(aarch64_add_offset_temporaries): Ditto.
(aarch64_add_offset): Ditto.
(aarch64_add_sp): Ditto.
(aarch64_sub_sp): Ditto.
(aarch64_guard_switch_pstate_sm): Ditto.
(aarch64_switch_pstate_sm): Ditto.
(aarch64_init_cumulative_args): Ditto.
(aarch64_allocate_and_probe_stack_space): Ditto.
(aarch64_expand_prologue): Ditto.
(aarch64_expand_epilogue): Ditto.
(aarch64_start_call_args): Ditto.
(aarch64_expand_call): Ditto.
(aarch64_end_call_args): Ditto.
(aarch64_set_current_function): Ditto, with added conversions.
(aarch64_handle_attr_arch): Avoid macro with changed type.
(aarch64_handle_attr_cpu): Ditto.
(aarch64_handle_attr_isa_flags): Ditto.
(aarch64_switch_pstate_sm_for_landing_pad):
Use arch64_isa_mode values.
(aarch64_switch_pstate_sm_for_jump): Ditto.
(pass_switch_pstate_sm::gate): Ditto.
* config/aarch64/aarch64.h
(AARCH64_ISA_MODE_{SM_ON|SM_OFF|ZA_ON}): New macros.
(AARCH64_FL_SM_STATE): Mark as possibly unused.
(AARCH64_ISA_MODE_SM_STATE): New aarch64_isa_mode mask.
(AARCH64_DEFAULT_ISA_MODE): New aarch64_isa_mode value.
(AARCH64_FL_DEFAULT_ISA_MODE): Define using above value.
(AARCH64_ISA_MODE): Change type to aarch64_isa_mode.
(arm_pcs): Use aarch64_isa_mode value.

Diff:
---
 gcc/config/aarch64/aarch64-opts.h   |   2 +
 gcc/config/aarch64/aarch64-protos.h |   4 +-
 gcc/config/aarch64/aarch64.cc   | 144 ++--
 gcc/config/aarch64/aarch64.h|  21 +-
 4 files changed, 94 insertions(+), 77 deletions(-)

diff --git a/gcc/config/aarch64/aarch64-opts.h 
b/gcc/config/aarch64/aarch64-opts.h
index 06a4fed38334..2c36bfaad19b 100644
--- a/gcc/config/aarch64/aarch64-opts.h
+++ b/gcc/config/aarch64/aarch64-opts.h
@@ -23,6 +23,8 @@
 #define GCC_AARCH64_OPTS_H
 
 #ifndef USED_FOR_TARGET
+typedef uint64_t aarch64_isa_mode;
+
 typedef uint64_t aarch64_feature_flags;
 
 constexpr unsigned int AARCH64_NUM_ISA_MODES = (0
diff --git a/gcc/config/aarch64/aarch64-protos.h 
b/gcc/config/aarch64/aarch64-protos.h
index 42639e9efcf1..f64afe288901 100644
--- a/gcc/config/aarch64/aarch64-protos.h
+++ b/gcc/config/aarch64/aarch64-protos.h
@@ -767,7 +767,7 @@ bool aarch64_constant_address_p (rtx);
 bool aarch64_emit_approx_div (rtx, rtx, rtx);
 bool aarch64_emit_approx_sqrt (rtx, rtx, bool);
 tree aarch64_vector_load_decl (tree);
-rtx aarch64_gen_callee_cookie (aarch64_feature_flags, arm_pcs);
+rtx aarch64_gen_callee_cookie (aarch64_isa_mode, arm_pcs);
 void aarch64_expand_call (rtx, rtx, rtx, bool);
 bool aarch64_expand_cpymem_mops (rtx *, bool);
 bool aarch64_expand_cpymem (rtx *, bool);
@@ -808,7 +808,7 @@ int aarch64_add_offset_temporaries (rtx);
 void aarch64_split_add_offset (scalar_int_mode, rtx, rtx, rtx, rtx, rtx);
 bool aarch64_rdsvl_immediate_p (const_rtx);
 rtx aarch64_sme_vq_immediate (machine_mode mode, HOST_WIDE_INT,
-   

[gcc r15-2268] aarch64: Use constructor explicitly in get_flags_off

[Andrew Carlotti via Gcc-cvs]

https://gcc.gnu.org/g:8977a1270b9c17e6682d25eb4b4030d7f2204df9

commit r15-2268-g8977a1270b9c17e6682d25eb4b4030d7f2204df9
Author: Andrew Carlotti 
Date:   Thu Jul 11 01:25:05 2024 +0100

aarch64: Use constructor explicitly in get_flags_off

gcc/ChangeLog:

* config/aarch64/aarch64-feature-deps.h
(get_flags_off): Construct aarch64_feature_flags (0) explicitly.

Diff:
---
 gcc/config/aarch64/aarch64-feature-deps.h | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/gcc/config/aarch64/aarch64-feature-deps.h 
b/gcc/config/aarch64/aarch64-feature-deps.h
index 79126db88254..a14ae22b7298 100644
--- a/gcc/config/aarch64/aarch64-feature-deps.h
+++ b/gcc/config/aarch64/aarch64-feature-deps.h
@@ -97,9 +97,10 @@ template struct info;
 constexpr aarch64_feature_flags
 get_flags_off (aarch64_feature_flags mask)
 {
-  return (0
+  return (aarch64_feature_flags (0)
 #define AARCH64_OPT_EXTENSION(A, IDENT, C, D, E, F) \
- | (feature_deps::IDENT ().enable & mask ? AARCH64_FL_##IDENT : 0)
+ | (feature_deps::IDENT ().enable & mask ? AARCH64_FL_##IDENT \
+ : aarch64_feature_flags (0))
 #include "config/aarch64/aarch64-option-extensions.def"
  );
 }

[gcc r14-9918] aarch64: Reorder FMV feature priorities

[Andrew Carlotti via Gcc-cvs]

https://gcc.gnu.org/g:e33fc847d5457bd56734cad056955102a23f405b

commit r14-9918-ge33fc847d5457bd56734cad056955102a23f405b
Author: Andrew Carlotti 
Date:   Wed Apr 3 23:32:12 2024 +0100

aarch64: Reorder FMV feature priorities

Some higher priority FMV features were dependent subsets of lower
priority features.  Fix this, using the new priorities specified in
https://github.com/ARM-software/acle/pull/279.

gcc/ChangeLog:

* config/aarch64/aarch64-option-extensions.def: Reorder FMV entries.

gcc/testsuite/ChangeLog:

* gcc.target/aarch64/cpunative/native_cpu_21.c: Reorder features.
* gcc.target/aarch64/cpunative/native_cpu_22.c: Ditto.

Diff:
---
 gcc/config/aarch64/aarch64-option-extensions.def   | 18 +++---
 .../gcc.target/aarch64/cpunative/native_cpu_21.c   |  2 +-
 .../gcc.target/aarch64/cpunative/native_cpu_22.c   |  2 +-
 3 files changed, 9 insertions(+), 13 deletions(-)

diff --git a/gcc/config/aarch64/aarch64-option-extensions.def 
b/gcc/config/aarch64/aarch64-option-extensions.def
index aa3cd99f791..0078dd09288 100644
--- a/gcc/config/aarch64/aarch64-option-extensions.def
+++ b/gcc/config/aarch64/aarch64-option-extensions.def
@@ -99,17 +99,17 @@ AARCH64_OPT_EXTENSION(NAME, IDENT, REQUIRES, EXPLICIT_ON, 
EXPLICIT_OFF, \
 AARCH64_FMV_FEATURE(NAME, IDENT, (IDENT))
 
 
-AARCH64_OPT_EXTENSION("fp", FP, (), (), (), "fp")
-
-AARCH64_OPT_EXTENSION("simd", SIMD, (FP), (), (), "asimd")
-
 AARCH64_OPT_FMV_EXTENSION("rng", RNG, (), (), (), "rng")
 
 AARCH64_OPT_FMV_EXTENSION("flagm", FLAGM, (), (), (), "flagm")
 
 AARCH64_FMV_FEATURE("flagm2", FLAGM2, (FLAGM))
 
-AARCH64_FMV_FEATURE("fp16fml", FP16FML, (F16FML))
+AARCH64_OPT_FMV_EXTENSION("lse", LSE, (), (), (), "atomics")
+
+AARCH64_OPT_FMV_EXTENSION("fp", FP, (), (), (), "fp")
+
+AARCH64_OPT_FMV_EXTENSION("simd", SIMD, (FP), (), (), "asimd")
 
 AARCH64_OPT_FMV_EXTENSION("dotprod", DOTPROD, (SIMD), (), (), "asimddp")
 
@@ -121,12 +121,6 @@ AARCH64_OPT_EXTENSION("rdma", RDMA, (), (SIMD), (), 
"asimdrdm")
 
 AARCH64_FMV_FEATURE("rmd", RDM, (RDMA))
 
-AARCH64_OPT_FMV_EXTENSION("lse", LSE, (), (), (), "atomics")
-
-AARCH64_FMV_FEATURE("fp", FP, (FP))
-
-AARCH64_FMV_FEATURE("simd", SIMD, (SIMD))
-
 AARCH64_OPT_FMV_EXTENSION("crc", CRC, (), (), (), "crc32")
 
 AARCH64_FMV_FEATURE("sha1", SHA1, ())
@@ -160,6 +154,8 @@ AARCH64_FMV_FEATURE("fp16", FP16, (F16))
-march=armv8.4-a+nofp16+fp16 enables F16 but not F16FML.  */
 AARCH64_OPT_EXTENSION("fp16fml", F16FML, (), (F16), (), "asimdfhm")
 
+AARCH64_FMV_FEATURE("fp16fml", FP16FML, (F16FML))
+
 AARCH64_FMV_FEATURE("dit", DIT, ())
 
 AARCH64_FMV_FEATURE("dpb", DPB, ())
diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_21.c 
b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_21.c
index 920e1d65711..1d90e9ec9d9 100644
--- a/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_21.c
+++ b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_21.c
@@ -7,7 +7,7 @@ int main()
   return 0;
 }
 
-/* { dg-final { scan-assembler {\.arch 
armv8-a\+flagm\+dotprod\+rdma\+lse\+crc\+fp16fml\+rcpc\+i8mm\+bf16\+sve2-aes\+sve2-bitperm\+sve2-sha3\+sve2-sm4\+sb\+ssbs\n}
 } } */
+/* { dg-final { scan-assembler {\.arch 
armv8-a\+flagm\+lse\+dotprod\+rdma\+crc\+fp16fml\+rcpc\+i8mm\+bf16\+sve2-aes\+sve2-bitperm\+sve2-sha3\+sve2-sm4\+sb\+ssbs\n}
 } } */
 
 /* Check that an Armv8-A core doesn't fall apart on extensions without midr
values.  */
diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_22.c 
b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_22.c
index 416a29b514a..17050a0b72c 100644
--- a/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_22.c
+++ b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_22.c
@@ -7,7 +7,7 @@ int main()
   return 0;
 }
 
-/* { dg-final { scan-assembler {\.arch 
armv8-a\+flagm\+dotprod\+rdma\+lse\+crc\+fp16fml\+rcpc\+i8mm\+bf16\+sve2-aes\+sve2-bitperm\+sve2-sha3\+sve2-sm4\+sb\+ssbs\+pauth\n}
 } } */
+/* { dg-final { scan-assembler {\.arch 
armv8-a\+flagm\+lse\+dotprod\+rdma\+crc\+fp16fml\+rcpc\+i8mm\+bf16\+sve2-aes\+sve2-bitperm\+sve2-sha3\+sve2-sm4\+sb\+ssbs\+pauth\n}
 } } */
 
 /* Check that an Armv8-A core doesn't fall apart on extensions without midr
values and that it enables optional features.  */

[gcc r14-9919] aarch64: Fix FMV array iteration bounds

[Andrew Carlotti via Gcc-cvs]

https://gcc.gnu.org/g:3ef14f56343ad3445f874638700f6b82f032a1ae

commit r14-9919-g3ef14f56343ad3445f874638700f6b82f032a1ae
Author: Andrew Carlotti 
Date:   Wed Apr 3 23:35:08 2024 +0100

aarch64: Fix FMV array iteration bounds

There was an assumption in some places that the aarch64_fmv_feature_data
array contained FEAT_MAX elements.  While this assumption held up till
now, it is safer and more flexible to use the array size directly.

Also fix the lower bound in compare_feature_masks to use ">=0" instead
of ">0", and add a test using the features at index 0 and 1. However,
the test already passed, because the earlier popcount check makes it
impossible to reach the loop if the masks differ in exactly one
location.

gcc/ChangeLog:

* config/aarch64/aarch64.cc (compare_feature_masks):
Use ARRAY_SIZE and >=0 for iteration bounds.
(aarch64_mangle_decl_assembler_name): Use ARRAY_SIZE.

gcc/testsuite/ChangeLog:

* g++.target/aarch64/mv-1.C: New test.

Diff:
---
 gcc/config/aarch64/aarch64.cc   |  8 ---
 gcc/testsuite/g++.target/aarch64/mv-1.C | 38 +
 2 files changed, 43 insertions(+), 3 deletions(-)

diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc
index c763a8a6298..91481f9fada 100644
--- a/gcc/config/aarch64/aarch64.cc
+++ b/gcc/config/aarch64/aarch64.cc
@@ -19738,7 +19738,7 @@ aarch64_parse_fmv_features (const char *str, 
aarch64_feature_flags *isa_flags,
   if (len == 0)
return AARCH_PARSE_MISSING_ARG;
 
-  static const int num_features = ARRAY_SIZE (aarch64_fmv_feature_data);
+  int num_features = ARRAY_SIZE (aarch64_fmv_feature_data);
   int i;
   for (i = 0; i < num_features; i++)
{
@@ -19937,7 +19937,8 @@ compare_feature_masks (aarch64_fmv_feature_mask mask1,
   auto diff_mask = mask1 ^ mask2;
   if (diff_mask == 0ULL)
 return 0;
-  for (int i = FEAT_MAX - 1; i > 0; i--)
+  int num_features = ARRAY_SIZE (aarch64_fmv_feature_data);
+  for (int i = num_features - 1; i >= 0; i--)
 {
   auto bit_mask = aarch64_fmv_feature_data[i].feature_mask;
   if (diff_mask & bit_mask)
@@ -20020,7 +20021,8 @@ aarch64_mangle_decl_assembler_name (tree decl, tree id)
 
   name += "._";
 
-  for (int i = 0; i < FEAT_MAX; i++)
+  int num_features = ARRAY_SIZE (aarch64_fmv_feature_data);
+  for (int i = 0; i < num_features; i++)
{
  if (feature_mask & aarch64_fmv_feature_data[i].feature_mask)
{
diff --git a/gcc/testsuite/g++.target/aarch64/mv-1.C 
b/gcc/testsuite/g++.target/aarch64/mv-1.C
new file mode 100644
index 000..b4b0e5e3fea
--- /dev/null
+++ b/gcc/testsuite/g++.target/aarch64/mv-1.C
@@ -0,0 +1,38 @@
+/* { dg-do compile } */
+/* { dg-require-ifunc "" } */
+/* { dg-options "-O0" } */
+
+__attribute__((target_version("default")))
+int foo ()
+{
+  return 1;
+}
+
+__attribute__((target_version("rng")))
+int foo ()
+{
+  return 1;
+}
+
+__attribute__((target_version("flagm")))
+int foo ()
+{
+  return 1;
+}
+
+__attribute__((target_version("rng+flagm")))
+int foo ()
+{
+  return 1;
+}
+
+int bar()
+{
+  return foo ();
+}
+
+/* Check usage of the first two FMV features, in case of off-by-one errors.  */
+/* { dg-final { scan-assembler-times "\n_Z3foov\.default:\n" 1 } } */
+/* { dg-final { scan-assembler-times "\n_Z3foov\._Mrng:\n" 1 } } */
+/* { dg-final { scan-assembler-times "\n_Z3foov\._MrngMflagm:\n" 1 } } */
+/* { dg-final { scan-assembler-times "\n_Z3foov\._Mflagm:\n" 1 } } */

[gcc r14-9920] aarch64: Fix typo and make rdma/rdm alias for FMV

[Andrew Carlotti via Gcc-cvs]

https://gcc.gnu.org/g:a28df11276647da16316d0621cb69ff5f878cd91

commit r14-9920-ga28df11276647da16316d0621cb69ff5f878cd91
Author: Andrew Carlotti 
Date:   Wed Apr 3 23:37:16 2024 +0100

aarch64: Fix typo and make rdma/rdm alias for FMV

gcc/ChangeLog:

* config/aarch64/aarch64-option-extensions.def:
Fix "rmd"->"rdm", and add FMV to "rdma".
* config/aarch64/aarch64.cc (FEAT_RDMA): Define as FEAT_RDM.

Diff:
---
 gcc/config/aarch64/aarch64-option-extensions.def | 5 +++--
 gcc/config/aarch64/aarch64.cc| 4 
 2 files changed, 7 insertions(+), 2 deletions(-)

diff --git a/gcc/config/aarch64/aarch64-option-extensions.def 
b/gcc/config/aarch64/aarch64-option-extensions.def
index 0078dd09288..b7b307b24ea 100644
--- a/gcc/config/aarch64/aarch64-option-extensions.def
+++ b/gcc/config/aarch64/aarch64-option-extensions.def
@@ -117,9 +117,10 @@ AARCH64_OPT_FMV_EXTENSION("sm4", SM4, (SIMD), (), (), "sm3 
sm4")
 
 /* An explicit +rdma implies +simd, but +rdma+nosimd still enables scalar
RDMA instructions.  */
-AARCH64_OPT_EXTENSION("rdma", RDMA, (), (SIMD), (), "asimdrdm")
+AARCH64_OPT_FMV_EXTENSION("rdma", RDMA, (), (SIMD), (), "asimdrdm")
 
-AARCH64_FMV_FEATURE("rmd", RDM, (RDMA))
+/* rdm is an alias for rdma.  */
+AARCH64_FMV_FEATURE("rdm", RDM, (RDMA))
 
 AARCH64_OPT_FMV_EXTENSION("crc", CRC, (), (), (), "crc32")
 
diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc
index 91481f9fada..a2e3d208d76 100644
--- a/gcc/config/aarch64/aarch64.cc
+++ b/gcc/config/aarch64/aarch64.cc
@@ -19695,6 +19695,10 @@ typedef struct
 #define AARCH64_FMV_FEATURE(NAME, FEAT_NAME, C) \
   {NAME, 1ULL << FEAT_##FEAT_NAME, ::feature_deps::fmv_deps_##FEAT_NAME},
 
+/* The "rdma" alias uses a different FEAT_NAME to avoid a duplicate
+   feature_deps name.  */
+#define FEAT_RDMA FEAT_RDM
+
 /* FMV features are listed in priority order, to make it easier to sort target
strings.  */
 static aarch64_fmv_feature_datum aarch64_fmv_feature_data[] = {

[gcc r14-9921] aarch64: Remove unsupported FMV features

[Andrew Carlotti via Gcc-cvs]

https://gcc.gnu.org/g:27e34311760456683d8316532dc57db24b3f410b

commit r14-9921-g27e34311760456683d8316532dc57db24b3f410b
Author: Andrew Carlotti 
Date:   Wed Apr 3 23:53:52 2024 +0100

aarch64: Remove unsupported FMV features

It currently isn't possible to support function multiversioning features
properly in GCC without also enabling the extension in the command line
options (with the exception of features such as "rpres" that do not
require assembler support).  We therefore remove unsupported features
from GCC's list of FMV features.

Some of these features ("fcma", "jscvt", "frintts", "flagm2", "wfxt",
"rcpc2", and perhaps "dpb" and "dpb2") will be added back in the future
once support for the command line option has been added.

The rest of the removed features I have proposed removing from the ACLE
specification as well, since it doesn't seem worthwhile to include support
for them; see the ACLE pull request for more detailed justification:
https://github.com/ARM-software/acle/pull/315

gcc/ChangeLog:

* config/aarch64/aarch64-option-extensions.def:
Remove "flagm2", "sha1", "pmull", "dit", "dpb", "dpb2", "jscvt",
"fcma", "rcpc2", "frintts", "dgh", "ebf16", "sve-bf16",
"sve-ebf16", "sve-i8mm", "sve2-pmull128", "memtag3", "bti" and
"wfxt" entries.

Diff:
---
 gcc/config/aarch64/aarch64-option-extensions.def | 38 
 1 file changed, 38 deletions(-)

diff --git a/gcc/config/aarch64/aarch64-option-extensions.def 
b/gcc/config/aarch64/aarch64-option-extensions.def
index b7b307b24ea..54bbf9c41e7 100644
--- a/gcc/config/aarch64/aarch64-option-extensions.def
+++ b/gcc/config/aarch64/aarch64-option-extensions.def
@@ -103,8 +103,6 @@ AARCH64_OPT_FMV_EXTENSION("rng", RNG, (), (), (), "rng")
 
 AARCH64_OPT_FMV_EXTENSION("flagm", FLAGM, (), (), (), "flagm")
 
-AARCH64_FMV_FEATURE("flagm2", FLAGM2, (FLAGM))
-
 AARCH64_OPT_FMV_EXTENSION("lse", LSE, (), (), (), "atomics")
 
 AARCH64_OPT_FMV_EXTENSION("fp", FP, (), (), (), "fp")
@@ -124,16 +122,12 @@ AARCH64_FMV_FEATURE("rdm", RDM, (RDMA))
 
 AARCH64_OPT_FMV_EXTENSION("crc", CRC, (), (), (), "crc32")
 
-AARCH64_FMV_FEATURE("sha1", SHA1, ())
-
 AARCH64_OPT_FMV_EXTENSION("sha2", SHA2, (SIMD), (), (), "sha1 sha2")
 
 AARCH64_FMV_FEATURE("sha3", SHA3, (SHA3))
 
 AARCH64_OPT_FMV_EXTENSION("aes", AES, (SIMD), (), (), "aes")
 
-AARCH64_FMV_FEATURE("pmull", PMULL, ())
-
 /* +nocrypto disables AES, SHA2 and SM4, and anything that depends on them
(such as SHA3 and the SVE2 crypto extensions).  */
 AARCH64_OPT_EXTENSION("crypto", CRYPTO, (AES, SHA2), (), (AES, SHA2, SM4),
@@ -157,44 +151,20 @@ AARCH64_OPT_EXTENSION("fp16fml", F16FML, (), (F16), (), 
"asimdfhm")
 
 AARCH64_FMV_FEATURE("fp16fml", FP16FML, (F16FML))
 
-AARCH64_FMV_FEATURE("dit", DIT, ())
-
-AARCH64_FMV_FEATURE("dpb", DPB, ())
-
-AARCH64_FMV_FEATURE("dpb2", DPB2, ())
-
-AARCH64_FMV_FEATURE("jscvt", JSCVT, ())
-
-AARCH64_FMV_FEATURE("fcma", FCMA, (SIMD))
-
 AARCH64_OPT_FMV_EXTENSION("rcpc", RCPC, (), (), (), "lrcpc")
 
-AARCH64_FMV_FEATURE("rcpc2", RCPC2, (RCPC))
-
 AARCH64_OPT_FMV_EXTENSION("rcpc3", RCPC3, (), (), (), "lrcpc3")
 
-AARCH64_FMV_FEATURE("frintts", FRINTTS, ())
-
-AARCH64_FMV_FEATURE("dgh", DGH, ())
-
 AARCH64_OPT_FMV_EXTENSION("i8mm", I8MM, (SIMD), (), (), "i8mm")
 
 /* An explicit +bf16 implies +simd, but +bf16+nosimd still enables scalar BF16
instructions.  */
 AARCH64_OPT_FMV_EXTENSION("bf16", BF16, (FP), (SIMD), (), "bf16")
 
-AARCH64_FMV_FEATURE("ebf16", EBF16, (BF16))
-
 AARCH64_FMV_FEATURE("rpres", RPRES, ())
 
 AARCH64_OPT_FMV_EXTENSION("sve", SVE, (SIMD, F16), (), (), "sve")
 
-AARCH64_FMV_FEATURE("sve-bf16", SVE_BF16, (SVE, BF16))
-
-AARCH64_FMV_FEATURE("sve-ebf16", SVE_EBF16, (SVE, BF16))
-
-AARCH64_FMV_FEATURE("sve-i8mm", SVE_I8MM, (SVE, I8MM))
-
 AARCH64_OPT_EXTENSION("f32mm", F32MM, (SVE), (), (), "f32mm")
 
 AARCH64_FMV_FEATURE("f32mm", SVE_F32MM, (F32MM))
@@ -209,8 +179,6 @@ AARCH64_OPT_EXTENSION("sve2-aes", SVE2_AES, (SVE2, AES), 
(), (), "sveaes")
 
 AARCH64_FMV_FEATURE("sve2-aes", SVE_AES, (SVE2_AES))
 
-AARCH64_FMV_FEATURE("sve2-pmull128", SVE_PMULL128, (SVE2))
-
 AARCH64_OPT_EXTENSION("sve2-bitperm", SVE2_BITPERM, (SVE2), (), (),
  "svebitperm")
 
@@ -230,8 +198,6 @@ AARCH64_OPT_FMV_EXTENSION("memtag", MEMTAG, (), (), (), "")
 
 AARCH64_FMV_FEATURE("memtag2", MEMTAG2, (MEMTAG))
 
-AARCH64_FMV_FEATURE("memtag3", MEMTAG3, (MEMTAG))
-
 AARCH64_OPT_FMV_EXTENSION("sb", SB, (), (), (), "sb")
 
 AARCH64_OPT_FMV_EXTENSION("predres", PREDRES, (), (), (), "")
@@ -240,8 +206,6 @@ AARCH64_OPT_FMV_EXTENSION("ssbs", SSBS, (), (), (), "ssbs")
 
 AARCH64_FMV_FEATURE("ssbs2", SSBS2, (SSBS))
 
-AARCH64_FMV_FEATURE("bti", BTI, ())
-
 AARCH64_OPT_EXTENSION("profile", PROFILE, (), (), (), "")
 
 AARCH64_OPT_EXTENSION("tme", TME, (), (), (), "")
@@ -256,8 +220,6 @@ AARCH64_FMV_FEATURE("ls64_v", LS64_V, ())
 
 AARCH64_FMV

[gcc r14-9922] aarch64: Remove FMV features whose names may change

[Andrew Carlotti via Gcc-cvs]

https://gcc.gnu.org/g:d33ec3b78fe9f6e0234bc08669b5021f324d67b3

commit r14-9922-gd33ec3b78fe9f6e0234bc08669b5021f324d67b3
Author: Andrew Carlotti 
Date:   Fri Apr 5 17:12:46 2024 +0100

aarch64: Remove FMV features whose names may change

Some architecture features have been combined under a single command
line flag, but have been assigned multiple FMV feature names with the
command line flag name enabling only a subset of these features in
the FMV specification.  I've proposed reallocating names in the FMV
specification to match the command line flags [1], but for GCC 14 we'll
just remove them from the FMV feature list.

[1] https://github.com/ARM-software/acle/pull/315

gcc/ChangeLog:

* config/aarch64/aarch64-option-extensions.def:
Remove "memtag", "memtag2", "ssbs", "ssbs2", "ls64", "ls64_v"
and "ls64_accdata" FMV features.

Diff:
---
 gcc/config/aarch64/aarch64-option-extensions.def | 14 ++
 1 file changed, 2 insertions(+), 12 deletions(-)

diff --git a/gcc/config/aarch64/aarch64-option-extensions.def 
b/gcc/config/aarch64/aarch64-option-extensions.def
index 54bbf9c41e7..3155eccd39c 100644
--- a/gcc/config/aarch64/aarch64-option-extensions.def
+++ b/gcc/config/aarch64/aarch64-option-extensions.def
@@ -194,17 +194,13 @@ AARCH64_FMV_FEATURE("sve2-sm4", SVE_SM4, (SVE2_SM4))
 
 AARCH64_OPT_FMV_EXTENSION("sme", SME, (BF16, SVE2), (), (), "sme")
 
-AARCH64_OPT_FMV_EXTENSION("memtag", MEMTAG, (), (), (), "")
-
-AARCH64_FMV_FEATURE("memtag2", MEMTAG2, (MEMTAG))
+AARCH64_OPT_EXTENSION("memtag", MEMTAG, (), (), (), "")
 
 AARCH64_OPT_FMV_EXTENSION("sb", SB, (), (), (), "sb")
 
 AARCH64_OPT_FMV_EXTENSION("predres", PREDRES, (), (), (), "")
 
-AARCH64_OPT_FMV_EXTENSION("ssbs", SSBS, (), (), (), "ssbs")
-
-AARCH64_FMV_FEATURE("ssbs2", SSBS2, (SSBS))
+AARCH64_OPT_EXTENSION("ssbs", SSBS, (), (), (), "ssbs")
 
 AARCH64_OPT_EXTENSION("profile", PROFILE, (), (), (), "")
 
@@ -214,12 +210,6 @@ AARCH64_OPT_EXTENSION("pauth", PAUTH, (), (), (), "paca 
pacg")
 
 AARCH64_OPT_EXTENSION("ls64", LS64, (), (), (), "")
 
-AARCH64_FMV_FEATURE("ls64", LS64, ())
-
-AARCH64_FMV_FEATURE("ls64_v", LS64_V, ())
-
-AARCH64_FMV_FEATURE("ls64_accdata", LS64_ACCDATA, (LS64))
-
 AARCH64_OPT_EXTENSION("sme-f64f64", SME_F64F64, (SME), (), (), "")
 
 AARCH64_FMV_FEATURE("sme-f64f64", SME_F64, (SME_F64F64))

[gcc r14-9951] aarch64: Enable +cssc for armv8.9-a

[Andrew Carlotti via Gcc-cvs]

https://gcc.gnu.org/g:b18162759a6d464256b0195bc6447f0a1c9dd5dd

commit r14-9951-gb18162759a6d464256b0195bc6447f0a1c9dd5dd
Author: Andrew Carlotti 
Date:   Thu Apr 11 17:00:30 2024 +0100

aarch64: Enable +cssc for armv8.9-a

FEAT_CSSC is mandatory in the architecture from Armv8.9.

gcc/ChangeLog:

* config/aarch64/aarch64-arches.def: Add CSSC to V8_9A
dependencies.

Diff:
---
 gcc/config/aarch64/aarch64-arches.def | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/config/aarch64/aarch64-arches.def 
b/gcc/config/aarch64/aarch64-arches.def
index 9bec30e9203..4634b272e28 100644
--- a/gcc/config/aarch64/aarch64-arches.def
+++ b/gcc/config/aarch64/aarch64-arches.def
@@ -39,7 +39,7 @@ AARCH64_ARCH("armv8.5-a", generic_armv8_a,   V8_5A, 
8,  (V8_4A, SB, SSBS
 AARCH64_ARCH("armv8.6-a", generic_armv8_a,   V8_6A, 8,  (V8_5A, I8MM, 
BF16))
 AARCH64_ARCH("armv8.7-a", generic_armv8_a,   V8_7A, 8,  (V8_6A))
 AARCH64_ARCH("armv8.8-a", generic_armv8_a,   V8_8A, 8,  (V8_7A, MOPS))
-AARCH64_ARCH("armv8.9-a", generic_armv8_a,   V8_9A, 8,  (V8_8A))
+AARCH64_ARCH("armv8.9-a", generic_armv8_a,   V8_9A, 8,  (V8_8A, CSSC))
 AARCH64_ARCH("armv8-r",   generic_armv8_a,   V8R  , 8,  (V8_4A))
 AARCH64_ARCH("armv9-a",   generic_armv9_a,   V9A  , 9,  (V8_5A, SVE2))
 AARCH64_ARCH("armv9.1-a", generic_armv9_a,   V9_1A, 9,  (V8_6A, V9A))

[gcc r15-4520] aarch64: Fix costing of move to/from MOVEABLE_SYSREGS

[Andrew Carlotti via Gcc-cvs]

https://gcc.gnu.org/g:8193e71a07de010c041175e7a8acf62eeae5b336

commit r15-4520-g8193e71a07de010c041175e7a8acf62eeae5b336
Author: Andrew Carlotti 
Date:   Thu Aug 22 11:59:33 2024 +0100

aarch64: Fix costing of move to/from MOVEABLE_SYSREGS

This is necessary to prevent reload assuming that a direct FP->FPMR move
is valid.

gcc/ChangeLog:

* config/aarch64/aarch64.cc (aarch64_register_move_cost):
Increase costs involving MOVEABLE_SYSREGS.

Diff:
---
 gcc/config/aarch64/aarch64.cc | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc
index 0dbc2aaa99ff..21d9a6b5a20e 100644
--- a/gcc/config/aarch64/aarch64.cc
+++ b/gcc/config/aarch64/aarch64.cc
@@ -15565,6 +15565,12 @@ aarch64_register_move_cost (machine_mode mode,
reg_class_contents[FFR_REGS]))
 return 80;
 
+  /* Moves to/from sysregs are expensive, and must go via GPR.  */
+  if (from == MOVEABLE_SYSREGS)
+return 80 + aarch64_register_move_cost (mode, GENERAL_REGS, to);
+  if (to == MOVEABLE_SYSREGS)
+return 80 + aarch64_register_move_cost (mode, from, GENERAL_REGS);
+
   /* Moving between GPR and stack cost is the same as GP2GP.  */
   if ((from == GENERAL_REGS && to == STACK_REG)
   || (to == GENERAL_REGS && from == STACK_REG))

[gcc r15-4674] aarch64: Add support for mfloat8x{8|16}_t types

[Andrew Carlotti via Gcc-cvs]

https://gcc.gnu.org/g:d74b0c698c8feb63589af4085760f6349a7386a6

commit r15-4674-gd74b0c698c8feb63589af4085760f6349a7386a6
Author: Andrew Carlotti 
Date:   Mon Oct 21 16:22:09 2024 +0100

aarch64: Add support for mfloat8x{8|16}_t types

gcc/ChangeLog:

* config/aarch64/aarch64-builtins.cc
(aarch64_init_simd_builtin_types): Initialise FP8 simd types.
* config/aarch64/aarch64-builtins.h
(enum aarch64_type_qualifiers): Add qualifier_modal_float bit.
* config/aarch64/aarch64-simd-builtin-types.def:
Add Mfloat8x{8|16}_t types.
* config/aarch64/arm_neon.h: Add mfloat8x{8|16}_t typedefs.

gcc/testsuite/ChangeLog:

* gcc.target/aarch64/movv16qi_2.c: Test mfloat as well.
* gcc.target/aarch64/movv16qi_3.c: Ditto.
* gcc.target/aarch64/movv2x16qi_1.c: Ditto.
* gcc.target/aarch64/movv3x16qi_1.c: Ditto.
* gcc.target/aarch64/movv4x16qi_1.c: Ditto.
* gcc.target/aarch64/movv8qi_2.c: Ditto.
* gcc.target/aarch64/movv8qi_3.c: Ditto.
* gcc.target/aarch64/mfloat-init-1.c: New test.

Diff:
---
 gcc/config/aarch64/aarch64-builtins.cc| 4 
 gcc/config/aarch64/aarch64-builtins.h | 2 ++
 gcc/config/aarch64/aarch64-simd-builtin-types.def | 2 ++
 gcc/config/aarch64/arm_neon.h | 3 +++
 gcc/testsuite/gcc.target/aarch64/mfloat-init-1.c  | 5 +
 gcc/testsuite/gcc.target/aarch64/movv16qi_2.c | 1 +
 gcc/testsuite/gcc.target/aarch64/movv16qi_3.c | 1 +
 gcc/testsuite/gcc.target/aarch64/movv2x16qi_1.c   | 1 +
 gcc/testsuite/gcc.target/aarch64/movv3x16qi_1.c   | 1 +
 gcc/testsuite/gcc.target/aarch64/movv4x16qi_1.c   | 1 +
 gcc/testsuite/gcc.target/aarch64/movv8qi_2.c  | 1 +
 gcc/testsuite/gcc.target/aarch64/movv8qi_3.c  | 1 +
 12 files changed, 23 insertions(+)

diff --git a/gcc/config/aarch64/aarch64-builtins.cc 
b/gcc/config/aarch64/aarch64-builtins.cc
index c4885630b90a..a41e37a7ea73 100644
--- a/gcc/config/aarch64/aarch64-builtins.cc
+++ b/gcc/config/aarch64/aarch64-builtins.cc
@@ -1220,6 +1220,10 @@ aarch64_init_simd_builtin_types (void)
   aarch64_simd_types[Bfloat16x4_t].eltype = bfloat16_type_node;
   aarch64_simd_types[Bfloat16x8_t].eltype = bfloat16_type_node;
 
+  /* Init FP8 element types.  */
+  aarch64_simd_types[Mfloat8x8_t].eltype = aarch64_mfp8_type_node;
+  aarch64_simd_types[Mfloat8x16_t].eltype = aarch64_mfp8_type_node;
+
   for (i = 0; i < nelts; i++)
 {
   tree eltype = aarch64_simd_types[i].eltype;
diff --git a/gcc/config/aarch64/aarch64-builtins.h 
b/gcc/config/aarch64/aarch64-builtins.h
index e326fe666769..00db7a74885d 100644
--- a/gcc/config/aarch64/aarch64-builtins.h
+++ b/gcc/config/aarch64/aarch64-builtins.h
@@ -54,6 +54,8 @@ enum aarch64_type_qualifiers
   /* Lane indices selected in quadtuplets. - must be in range, and flipped for
  bigendian.  */
   qualifier_lane_quadtup_index = 0x1000,
+  /* Modal FP types.  */
+  qualifier_modal_float = 0x2000,
 };
 
 #define ENTRY(E, M, Q, G) E,
diff --git a/gcc/config/aarch64/aarch64-simd-builtin-types.def 
b/gcc/config/aarch64/aarch64-simd-builtin-types.def
index 6111cd0d4fe1..83b2da2e7dc0 100644
--- a/gcc/config/aarch64/aarch64-simd-builtin-types.def
+++ b/gcc/config/aarch64/aarch64-simd-builtin-types.def
@@ -52,3 +52,5 @@
   ENTRY (Float64x2_t, V2DF, none, 13)
   ENTRY (Bfloat16x4_t, V4BF, none, 14)
   ENTRY (Bfloat16x8_t, V8BF, none, 14)
+  ENTRY (Mfloat8x8_t, V8QI, modal_float, 13)
+  ENTRY (Mfloat8x16_t, V16QI, modal_float, 14)
diff --git a/gcc/config/aarch64/arm_neon.h b/gcc/config/aarch64/arm_neon.h
index e376685489da..730d9d3fa815 100644
--- a/gcc/config/aarch64/arm_neon.h
+++ b/gcc/config/aarch64/arm_neon.h
@@ -72,6 +72,9 @@ typedef __Poly16_t poly16_t;
 typedef __Poly64_t poly64_t;
 typedef __Poly128_t poly128_t;
 
+typedef __Mfloat8x8_t mfloat8x8_t;
+typedef __Mfloat8x16_t mfloat8x16_t;
+
 typedef __fp16 float16_t;
 typedef float float32_t;
 typedef double float64_t;
diff --git a/gcc/testsuite/gcc.target/aarch64/mfloat-init-1.c 
b/gcc/testsuite/gcc.target/aarch64/mfloat-init-1.c
new file mode 100644
index ..15a6b331fd39
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/mfloat-init-1.c
@@ -0,0 +1,5 @@
+/* { dg-do assemble } */
+/* { dg-options "-O --save-temps" } */
+
+/* { dg-error "invalid conversion to type 'mfloat8_t" "" {target *-*-*} 0 } */
+__Mfloat8x8_t const_mf8x8 () { return (__Mfloat8x8_t) { 1, 1, 1, 1, 1, 1, 1, 1 
}; }
diff --git a/gcc/testsuite/gcc.target/aarch64/movv16qi_2.c 
b/gcc/testsuite/gcc.target/aarch64/movv16qi_2.c
index 08a0a19b5151..39a06db07075 100644
--- a/gcc/testsuite/gcc.target/aarch64/movv16qi_2.c
+++ b/gcc/testsuite/gcc.target/aarch64/movv16qi_2.c
@@ -17,6 +17,7 @@ TEST_GENERAL (__Bfloat16x8_t)
 TEST_GENERAL (__Float16x8_t)
 TEST_GENERAL (__Float32x4_t)
 TEST_GENERAL (__Float64x2_t)
+TEST_GENERAL (__Mfloat8x16_t)
 
 __Int8x16_t const_s8x8 

[gcc r15-4675] aarch64: Add mfloat vreinterpret intrinsics

[Andrew Carlotti via Gcc-cvs]

https://gcc.gnu.org/g:17d7a4b01a54b1af90c8c87bde59f067ed630cd1

commit r15-4675-g17d7a4b01a54b1af90c8c87bde59f067ed630cd1
Author: Andrew Carlotti 
Date:   Mon Oct 21 16:22:43 2024 +0100

aarch64: Add mfloat vreinterpret intrinsics

gcc/ChangeLog:

* config/aarch64/aarch64-builtins.cc (MODE_d_mf8): New.
(MODE_q_mf8): New.
(QUAL_mf8): New.
(VREINTERPRET_BUILTINS1): Add mf8 entry.
(VREINTERPRET_BUILTINS): Ditto.
(VREINTERPRETQ_BUILTINS1): Ditto.
(VREINTERPRETQ_BUILTINS): Ditto.
(aarch64_lookup_simd_type_in_table): Match modal_float bit

gcc/testsuite/ChangeLog:

* gcc.target/aarch64/advsimd-intrinsics/mf8-reinterpret.c: New test.

Diff:
---
 gcc/config/aarch64/aarch64-builtins.cc | 12 +-
 .../aarch64/advsimd-intrinsics/mf8-reinterpret.c   | 46 ++
 2 files changed, 57 insertions(+), 1 deletion(-)

diff --git a/gcc/config/aarch64/aarch64-builtins.cc 
b/gcc/config/aarch64/aarch64-builtins.cc
index a41e37a7ea73..86d96e47f01c 100644
--- a/gcc/config/aarch64/aarch64-builtins.cc
+++ b/gcc/config/aarch64/aarch64-builtins.cc
@@ -133,6 +133,7 @@
 #define MODE_d_f16 E_V4HFmode
 #define MODE_d_f32 E_V2SFmode
 #define MODE_d_f64 E_V1DFmode
+#define MODE_d_mf8 E_V8QImode
 #define MODE_d_s8 E_V8QImode
 #define MODE_d_s16 E_V4HImode
 #define MODE_d_s32 E_V2SImode
@@ -148,6 +149,7 @@
 #define MODE_q_f16 E_V8HFmode
 #define MODE_q_f32 E_V4SFmode
 #define MODE_q_f64 E_V2DFmode
+#define MODE_q_mf8 E_V16QImode
 #define MODE_q_s8 E_V16QImode
 #define MODE_q_s16 E_V8HImode
 #define MODE_q_s32 E_V4SImode
@@ -177,6 +179,7 @@
 #define QUAL_p16 qualifier_poly
 #define QUAL_p64 qualifier_poly
 #define QUAL_p128 qualifier_poly
+#define QUAL_mf8 qualifier_modal_float
 
 #define LENGTH_d ""
 #define LENGTH_q "q"
@@ -598,6 +601,7 @@ static aarch64_simd_builtin_datum 
aarch64_simd_builtin_data[] = {
 /* vreinterpret intrinsics are defined for any pair of element types.
{ _bf16   }   { _bf16   }
{  _f16 _f32 _f64 }   {  _f16 _f32 _f64 }
+   { _mf8}   { _mf8}
{ _s8  _s16 _s32 _s64 } x { _s8  _s16 _s32 _s64 }
{ _u8  _u16 _u32 _u64 }   { _u8  _u16 _u32 _u64 }
{ _p8  _p16  _p64 }   { _p8  _p16  _p64 }.  */
@@ -609,6 +613,7 @@ static aarch64_simd_builtin_datum 
aarch64_simd_builtin_data[] = {
   VREINTERPRET_BUILTIN2 (A, f16) \
   VREINTERPRET_BUILTIN2 (A, f32) \
   VREINTERPRET_BUILTIN2 (A, f64) \
+  VREINTERPRET_BUILTIN2 (A, mf8) \
   VREINTERPRET_BUILTIN2 (A, s8) \
   VREINTERPRET_BUILTIN2 (A, s16) \
   VREINTERPRET_BUILTIN2 (A, s32) \
@@ -626,6 +631,7 @@ static aarch64_simd_builtin_datum 
aarch64_simd_builtin_data[] = {
   VREINTERPRET_BUILTINS1 (f16) \
   VREINTERPRET_BUILTINS1 (f32) \
   VREINTERPRET_BUILTINS1 (f64) \
+  VREINTERPRET_BUILTINS1 (mf8) \
   VREINTERPRET_BUILTINS1 (s8) \
   VREINTERPRET_BUILTINS1 (s16) \
   VREINTERPRET_BUILTINS1 (s32) \
@@ -641,6 +647,7 @@ static aarch64_simd_builtin_datum 
aarch64_simd_builtin_data[] = {
 /* vreinterpretq intrinsics are additionally defined for p128.
{ _bf16 }   { _bf16 }
{  _f16 _f32 _f64   }   {  _f16 _f32 _f64   }
+   { _mf8  }   { _mf8  }
{ _s8  _s16 _s32 _s64   } x { _s8  _s16 _s32 _s64   }
{ _u8  _u16 _u32 _u64   }   { _u8  _u16 _u32 _u64   }
{ _p8  _p16  _p64 _p128 }   { _p8  _p16  _p64 _p128 }.  */
@@ -652,6 +659,7 @@ static aarch64_simd_builtin_datum 
aarch64_simd_builtin_data[] = {
   VREINTERPRETQ_BUILTIN2 (A, f16) \
   VREINTERPRETQ_BUILTIN2 (A, f32) \
   VREINTERPRETQ_BUILTIN2 (A, f64) \
+  VREINTERPRETQ_BUILTIN2 (A, mf8) \
   VREINTERPRETQ_BUILTIN2 (A, s8) \
   VREINTERPRETQ_BUILTIN2 (A, s16) \
   VREINTERPRETQ_BUILTIN2 (A, s32) \
@@ -670,6 +678,7 @@ static aarch64_simd_builtin_datum 
aarch64_simd_builtin_data[] = {
   VREINTERPRETQ_BUILTINS1 (f16) \
   VREINTERPRETQ_BUILTINS1 (f32) \
   VREINTERPRETQ_BUILTINS1 (f64) \
+  VREINTERPRETQ_BUILTINS1 (mf8) \
   VREINTERPRETQ_BUILTINS1 (s8) \
   VREINTERPRETQ_BUILTINS1 (s16) \
   VREINTERPRETQ_BUILTINS1 (s32) \
@@ -1117,7 +1126,8 @@ aarch64_lookup_simd_type_in_table (machine_mode mode,
 {
   int i;
   int nelts = ARRAY_SIZE (aarch64_simd_types);
-  int q = qualifiers & (qualifier_poly | qualifier_unsigned);
+  int q = qualifiers
+& (qualifier_poly | qualifier_unsigned | qualifier_modal_float);
 
   for (i = 0; i < nelts; i++)
 {
diff --git 
a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/mf8-reinterpret.c 
b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/mf8-reinterpret.c
new file mode 100644
index ..5e5921746036
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/mf8-reinterpret.c
@@ -0,0 +1,46 @@
+/* { dg-do compile { target { aarch64*-*-* } } } */
+
+#include 
+
+#define TEST_128(T, S) 

[gcc r14-10920] testsuite: Adjust jump threading test expectation

[Andrew Carlotti via Gcc-cvs]

https://gcc.gnu.org/g:6d5f550231b57b0fa9d8ec53cc6354961ead358b

commit r14-10920-g6d5f550231b57b0fa9d8ec53cc6354961ead358b
Author: Andrew Carlotti 
Date:   Fri Nov 1 17:27:38 2024 +

testsuite: Adjust jump threading test expectation

This test started failing on aarch64 after 0cfc9c95 in 2023 ("Phi
analyzer - Initialize with range instead of a tree.").

The only change visible in the pass dumps prior to thread2 is the upper
bounds of some ranges are reduced from +INF to 7, consistent with the
bitamsk information.  After thread2, there are changes in the control
flow, but only affecting edges that are obviously never taken (from
basic blocks 6 through 12).  These are cleaned up in the following pass,
but the final codegen remains different.

There isn't anything obviously wrong with the change in dump output, so
let's just update the test expectations (as has happened previously
here).

gcc/testsuite/ChangeLog:

PR tree-optimization/112376
* gcc.dg/tree-ssa/ssa-dom-thread-7.c: Update expectation.

Diff:
---
 gcc/testsuite/gcc.dg/tree-ssa/ssa-dom-thread-7.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/testsuite/gcc.dg/tree-ssa/ssa-dom-thread-7.c 
b/gcc/testsuite/gcc.dg/tree-ssa/ssa-dom-thread-7.c
index 47b8fdfa29a5..d84aceebc5d0 100644
--- a/gcc/testsuite/gcc.dg/tree-ssa/ssa-dom-thread-7.c
+++ b/gcc/testsuite/gcc.dg/tree-ssa/ssa-dom-thread-7.c
@@ -12,7 +12,7 @@
jump threading opportunities.  Skip the later tests on aarch64.  */
 /* { dg-final { scan-tree-dump-not "Jumps threaded"  "dom3" { target { ! 
aarch64*-*-* } } } } */
 /* { dg-final { scan-tree-dump "Jumps threaded: 9"  "thread2" { target { ! 
aarch64*-*-* } } } } */
-/* { dg-final { scan-tree-dump "Jumps threaded: 18"  "thread2" { target { 
aarch64*-*-* } } } } */
+/* { dg-final { scan-tree-dump "Jumps threaded: 17"  "thread2" { target { 
aarch64*-*-* } } } } */
 
 enum STATE {
   S0=0,

[gcc r15-5175] testsuite: Adjust jump threading test expectation

[Andrew Carlotti via Gcc-cvs]

https://gcc.gnu.org/g:f72f8c34952fe27795fc750e80cb78b97b51fa97

commit r15-5175-gf72f8c34952fe27795fc750e80cb78b97b51fa97
Author: Andrew Carlotti 
Date:   Fri Nov 1 17:27:38 2024 +

testsuite: Adjust jump threading test expectation

This test started failing on aarch64 after 0cfc9c95 in 2023 ("Phi
analyzer - Initialize with range instead of a tree.").

The only change visible in the pass dumps prior to thread2 is the upper
bounds of some ranges are reduced from +INF to 7, consistent with the
bitamsk information.  After thread2, there are changes in the control
flow, but only affecting edges that are obviously never taken (from
basic blocks 6 through 12).  These are cleaned up in the following pass,
but the final codegen remains different.

There isn't anything obviously wrong with the change in dump output, so
let's just update the test expectations (as has happened previously
here).

gcc/testsuite/ChangeLog:

PR tree-optimization/112376
* gcc.dg/tree-ssa/ssa-dom-thread-7.c: Update expectation.

Diff:
---
 gcc/testsuite/gcc.dg/tree-ssa/ssa-dom-thread-7.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/testsuite/gcc.dg/tree-ssa/ssa-dom-thread-7.c 
b/gcc/testsuite/gcc.dg/tree-ssa/ssa-dom-thread-7.c
index 47b8fdfa29a5..d84aceebc5d0 100644
--- a/gcc/testsuite/gcc.dg/tree-ssa/ssa-dom-thread-7.c
+++ b/gcc/testsuite/gcc.dg/tree-ssa/ssa-dom-thread-7.c
@@ -12,7 +12,7 @@
jump threading opportunities.  Skip the later tests on aarch64.  */
 /* { dg-final { scan-tree-dump-not "Jumps threaded"  "dom3" { target { ! 
aarch64*-*-* } } } } */
 /* { dg-final { scan-tree-dump "Jumps threaded: 9"  "thread2" { target { ! 
aarch64*-*-* } } } } */
-/* { dg-final { scan-tree-dump "Jumps threaded: 18"  "thread2" { target { 
aarch64*-*-* } } } } */
+/* { dg-final { scan-tree-dump "Jumps threaded: 17"  "thread2" { target { 
aarch64*-*-* } } } } */
 
 enum STATE {
   S0=0,

[gcc r15-7480] aarch64: Update fp8 dependencies

[Andrew Carlotti via Gcc-cvs]

https://gcc.gnu.org/g:299a8e2dc667e795991bc439d2cad5ea5bd379e2

commit r15-7480-g299a8e2dc667e795991bc439d2cad5ea5bd379e2
Author: Andrew Carlotti 
Date:   Wed Feb 5 17:27:56 2025 +

aarch64: Update fp8 dependencies

We agreed with LLVM developers to not enforce the architectural
dependencies between fp8 multiplication features, and they have already
been removed from LLVM and Binutils.  Remove them from GCC as well.

gcc/ChangeLog:

* config/aarch64/aarch64-option-extensions.def
(SSVE_FP8FMA): Adjust formatting.
(FP8DOT4): Replace FP8FMA dependency with FP8.
(SSVE_FP8DOT4): Replace SSVE_FP8FMA dependency with SME2+FP8.
(FP8DOT2): Replace FP8DOT4 dependency with FP8.
(SSVE_FP8DOT2): Replace SSVE_FP8DOT4 dependency with SME2+FP8.

gcc/testsuite/ChangeLog:

* gcc.target/aarch64/pragma_cpp_predefs_4.c: Adjust expected
defines.
* gcc.target/aarch64/simd/vmla_lane_indices_1.c: Modify target
pragmas.
* gcc.target/aarch64/sve/acle/general-c/ternary_mfloat8_1.c:
Ditto.
* 
gcc.target/aarch64/sve/acle/general-c/ternary_mfloat8_lane_group_selection_1.c:
Ditto.
* gcc.target/aarch64/sve2/acle/asm/dot_lane_mf8.c: Ditto.
* gcc.target/aarch64/sve2/acle/asm/dot_mf8.c: Ditto.

Diff:
---
 gcc/config/aarch64/aarch64-option-extensions.def   | 10 +-
 gcc/testsuite/gcc.target/aarch64/pragma_cpp_predefs_4.c|  6 +++---
 gcc/testsuite/gcc.target/aarch64/simd/vmla_lane_indices_1.c|  2 +-
 .../gcc.target/aarch64/sve/acle/general-c/ternary_mfloat8_1.c  |  2 +-
 .../acle/general-c/ternary_mfloat8_lane_group_selection_1.c|  2 +-
 gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/dot_lane_mf8.c  |  4 ++--
 gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/dot_mf8.c   |  4 ++--
 7 files changed, 15 insertions(+), 15 deletions(-)

diff --git a/gcc/config/aarch64/aarch64-option-extensions.def 
b/gcc/config/aarch64/aarch64-option-extensions.def
index cc42bd518dca..aa8d315c240f 100644
--- a/gcc/config/aarch64/aarch64-option-extensions.def
+++ b/gcc/config/aarch64/aarch64-option-extensions.def
@@ -261,17 +261,17 @@ AARCH64_OPT_EXTENSION("fp8", FP8, (SIMD), (), (), "f8cvt")
 
 AARCH64_OPT_EXTENSION("fp8fma", FP8FMA, (FP8), (), (), "f8fma")
 
-AARCH64_OPT_EXTENSION("ssve-fp8fma", SSVE_FP8FMA, (SME2,FP8), (), (), 
"smesf8fma")
+AARCH64_OPT_EXTENSION("ssve-fp8fma", SSVE_FP8FMA, (SME2, FP8), (), (), 
"smesf8fma")
 
 AARCH64_OPT_EXTENSION("faminmax", FAMINMAX, (SIMD), (), (), "faminmax")
 
-AARCH64_OPT_EXTENSION("fp8dot4", FP8DOT4, (FP8FMA), (), (), "f8dp4")
+AARCH64_OPT_EXTENSION("fp8dot4", FP8DOT4, (FP8), (), (), "f8dp4")
 
-AARCH64_OPT_EXTENSION("ssve-fp8dot4", SSVE_FP8DOT4, (SSVE_FP8FMA), (), (), 
"smesf8dp4")
+AARCH64_OPT_EXTENSION("ssve-fp8dot4", SSVE_FP8DOT4, (SME2, FP8), (), (), 
"smesf8dp4")
 
-AARCH64_OPT_EXTENSION("fp8dot2", FP8DOT2, (FP8DOT4), (), (), "f8dp2")
+AARCH64_OPT_EXTENSION("fp8dot2", FP8DOT2, (FP8), (), (), "f8dp2")
 
-AARCH64_OPT_EXTENSION("ssve-fp8dot2", SSVE_FP8DOT2, (SSVE_FP8DOT4), (), (), 
"smesf8dp2")
+AARCH64_OPT_EXTENSION("ssve-fp8dot2", SSVE_FP8DOT2, (SME2, FP8), (), (), 
"smesf8dp2")
 
 AARCH64_OPT_EXTENSION("lut", LUT, (SIMD), (), (), "lut")
 
diff --git a/gcc/testsuite/gcc.target/aarch64/pragma_cpp_predefs_4.c 
b/gcc/testsuite/gcc.target/aarch64/pragma_cpp_predefs_4.c
index 0dcfbec05bad..97d68b94512e 100644
--- a/gcc/testsuite/gcc.target/aarch64/pragma_cpp_predefs_4.c
+++ b/gcc/testsuite/gcc.target/aarch64/pragma_cpp_predefs_4.c
@@ -292,7 +292,7 @@
 #ifndef __ARM_FEATURE_FP8
 #error Foo
 #endif
-#ifndef __ARM_FEATURE_FP8FMA
+#ifdef __ARM_FEATURE_FP8FMA
 #error Foo
 #endif
 #ifndef __ARM_FEATURE_FP8DOT4
@@ -306,10 +306,10 @@
 #ifndef __ARM_FEATURE_FP8
 #error Foo
 #endif
-#ifndef __ARM_FEATURE_FP8FMA
+#ifdef __ARM_FEATURE_FP8FMA
 #error Foo
 #endif
-#ifndef __ARM_FEATURE_FP8DOT4
+#ifdef __ARM_FEATURE_FP8DOT4
 #error Foo
 #endif
 #ifndef __ARM_FEATURE_FP8DOT2
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vmla_lane_indices_1.c 
b/gcc/testsuite/gcc.target/aarch64/simd/vmla_lane_indices_1.c
index d1a69f4ba541..739ff4c6a75a 100644
--- a/gcc/testsuite/gcc.target/aarch64/simd/vmla_lane_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vmla_lane_indices_1.c
@@ -2,7 +2,7 @@
 
 #include "arm_neon.h"
 
-#pragma GCC target "+fp8dot4+fp8dot2"
+#pragma GCC target "+fp8fma"
 
 void
 test(float16x4_t f16, float16x8_t f16q, float32x2_t f32,
diff --git 
a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/ternary_mfloat8_1.c 
b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/ternary_mfloat8_1.c
index 9ad789a8ad2c..fa0df46db226 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/ternary_mfloat8_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/ternary_mfloat8_1.c
@@ -2,7 +2,7 @@
 
 #include 
 
-#pragma GCC target ("arch=armv8.2

[gcc r15-7479] testsuite: Enable reduced parallel batch sizes

[Andrew Carlotti via Gcc-cvs]

https://gcc.gnu.org/g:00d943bf840386bd6e3e8a04554df5b528722e46

commit r15-7479-g00d943bf840386bd6e3e8a04554df5b528722e46
Author: Andrew Carlotti 
Date:   Tue Feb 4 19:45:31 2025 +

testsuite: Enable reduced parallel batch sizes

Various aarch64 tests attempt to reduce the batch size for parallel test
execution to a single test per batch, but it looks like the necessary
changes to gcc_parallel_test_run_p were accidentally omitted when the
aarch64-*-acle-asm.exp files were merged.  This patch corrects that
omission.

This does have a measurable performance impact when running a limited
number of tests.  For example, in aarch64-sve-acle-asm.exp the use of
torture options results in 16 compiler executions for each test; when
running two such tests I observed a total test duration of 3m39 without
this patch, and 1m55 with the patch.  A full batch of 10 tests would
have taken over 15 minutes to run on this machine.

gcc/testsuite/ChangeLog:

* lib/gcc-defs.exp
(gcc_runtest_parallelize_limit_minor): New global variable.
(gcc_parallel_test_run_p): Use new variable for batch size.

Diff:
---
 gcc/testsuite/lib/gcc-defs.exp | 7 +--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/gcc/testsuite/lib/gcc-defs.exp b/gcc/testsuite/lib/gcc-defs.exp
index 29403d7317c7..2f8b7d488691 100644
--- a/gcc/testsuite/lib/gcc-defs.exp
+++ b/gcc/testsuite/lib/gcc-defs.exp
@@ -172,6 +172,7 @@ if { [info exists env(GCC_RUNTEST_PARALLELIZE_DIR)] \
  && [info procs gcc_parallelize_saved_runtest_file_p] == [list] } then {
 global gcc_runtest_parallelize_counter
 global gcc_runtest_parallelize_counter_minor
+global gcc_runtest_parallelize_limit_minor
 global gcc_runtest_parallelize_enable
 global gcc_runtest_parallelize_dir
 global gcc_runtest_parallelize_last
@@ -212,6 +213,7 @@ if { [info exists env(GCC_RUNTEST_PARALLELIZE_DIR)] \
 #and investigate if they don't.
 set gcc_runtest_parallelize_counter 0
 set gcc_runtest_parallelize_counter_minor 0
+set gcc_runtest_parallelize_limit_minor 10
 set gcc_runtest_parallelize_enable 1
 set gcc_runtest_parallelize_dir [getenv GCC_RUNTEST_PARALLELIZE_DIR]
 set gcc_runtest_parallelize_last 0
@@ -219,6 +221,7 @@ if { [info exists env(GCC_RUNTEST_PARALLELIZE_DIR)] \
 proc gcc_parallel_test_run_p { testcase } {
global gcc_runtest_parallelize_counter
global gcc_runtest_parallelize_counter_minor
+   global gcc_runtest_parallelize_limit_minor
global gcc_runtest_parallelize_enable
global gcc_runtest_parallelize_dir
global gcc_runtest_parallelize_last
@@ -228,10 +231,10 @@ if { [info exists env(GCC_RUNTEST_PARALLELIZE_DIR)] \
}
 
# Only test the filesystem every 10th iteration
-   incr gcc_runtest_parallelize_counter_minor
-   if { $gcc_runtest_parallelize_counter_minor == 10 } {
+   if { $gcc_runtest_parallelize_counter_minor >= 
$gcc_runtest_parallelize_limit_minor } {
set gcc_runtest_parallelize_counter_minor 0
}
+   incr gcc_runtest_parallelize_counter_minor
if { $gcc_runtest_parallelize_counter_minor != 1 } {
#verbose -log "gcc_parallel_test_run_p $testcase 
$gcc_runtest_parallelize_counter $gcc_runtest_parallelize_last"
return $gcc_runtest_parallelize_last

[gcc r15-6368] Fix comment typos in tree-assume.cc

[Andrew Carlotti via Gcc-cvs]

https://gcc.gnu.org/g:fc95e8776cf4b11bbffc593167105883165b9e4c

commit r15-6368-gfc95e8776cf4b11bbffc593167105883165b9e4c
Author: Andrew Carlotti 
Date:   Wed Dec 18 16:16:51 2024 +

Fix comment typos in tree-assume.cc

gcc/ChangeLog:

* tree-assume.cc: Fix comment typos.

Diff:
---
 gcc/tree-assume.cc | 32 
 1 file changed, 16 insertions(+), 16 deletions(-)

diff --git a/gcc/tree-assume.cc b/gcc/tree-assume.cc
index 883338bcef1e..9a934f21dc03 100644
--- a/gcc/tree-assume.cc
+++ b/gcc/tree-assume.cc
@@ -36,16 +36,16 @@ along with GCC; see the file COPYING3.  If not see
 #include "tree-cfg.h"
 #include "gimple-pretty-print.h"
 
-// An assume query utilizes the current range query to implelemtn the assume
+// An assume query utilizes the current range query to implement the assume
 // keyword.
 // For any return value of 1 from the function, it attempts to determine
-// which paths leads to a 1 value being returned. On those paths, what
+// which paths lead to a 1 value being returned. On those paths, it determines
 // the ranges of any ssa_names listed in bitmap P (usually the parm list for
-// the function) are, and combined them all.
+// the function), and combines them all.
 // These ranges are then set as the global ranges for those parms in this
 // function.
-// Other functions which then refer to this function in an assume builtin
-// will then pick up these ranges for the paramters via the inferred range
+// Other functions which refer to this function in an assume builtin
+// will then pick up these ranges for the parameters via the inferred range
 // mechanism.
 //   See gimple-range-infer.cc::gimple_infer_range::check_assume_func ()
 //
@@ -57,11 +57,11 @@ along with GCC; see the file COPYING3.  If not see
 //
 // a small temporary assume function consisting of
 // assume_f1 (int x) { return x == 1 || x == 4; }
-// is constructed by the front end, and optimzed, at the very end of
+// is constructed by the front end, and optimized, at the very end of
 // optimization, instead of generating code, we instead invoke the assume pass
 // which uses this query to set the the global value of parm x to [1,1][4,4]
 //
-// Meanwhile., my_Fund has been rewritten to be:
+// Meanwhile., my_func has been rewritten to be:
 //
 // my_func (int x_2)
 // {
@@ -70,12 +70,12 @@ along with GCC; see the file COPYING3.  If not see
 //   if (x_2 == 3)
 //
 // When ranger is processing the assume_builtin_call, it looks up the global
-// value of the paramter in assume_f1, which is [1,1][4,4].  It then registers
+// value of the parameter in assume_f1, which is [1,1][4,4].  It then registers
 // and inferred range at this statement setting the value x_2 to [1,1][4,4]
 //
-// Any uses of x_2 after this statement will now utilzie this inferred range.
+// Any uses of x_2 after this statement will now utilize this inferred range.
 //
-// When VRP precoesses if (x_2 == 3), it picks up the inferred range, and
+// When VRP processes if (x_2 == 3), it picks up the inferred range, and
 // determines that x_2 can never be 3, and will rewrite the branch to
 //   if (0 != 0)
 
@@ -109,7 +109,7 @@ assume_query::assume_query (function *f, bitmap p) : 
m_parm_list (p),
 m_func (f)
 {
   basic_block exit_bb = EXIT_BLOCK_PTR_FOR_FN (f);
-  // If there is more than one precessor to the exit block, bail.
+  // If there is more than one predecessor to the exit block, bail.
   if (!single_pred_p (exit_bb))
 return;
 
@@ -130,7 +130,7 @@ assume_query::assume_query (function *f, bitmap p) : 
m_parm_list (p),
   if (!irange::supports_p (lhs_type))
 return;
 
-  // Only values of interest are when the return value is 1.  The defintion
+  // Only values of interest are when the return value is 1.  The definition
   // of the return value must be in the same block, or we have
   // complicated flow control we don't understand, and just return.
   unsigned prec = TYPE_PRECISION (lhs_type);
@@ -169,7 +169,7 @@ assume_query::assume_query (function *f, bitmap p) : 
m_parm_list (p),
}
 }
 
-// This function Will update all the current value of interesting parameters.
+// This function will update all the current values of interesting parameters.
 // It tries, in order:
 //a) a range found via path calculations.
 //b) range of the parm at SRC point in the IL. (either edge or stmt)
@@ -423,9 +423,9 @@ public:
   bool gate (function *fun) final override { return fun->assume_function; }
   unsigned int execute (function *fun) final override
 {
-  // Create a bitmap of all the paramters in this function.
-  // Invoke the assume_query to detemine what values these parameters
-  // have when the function returns TRUE, and set the globals value of
+  // Create a bitmap of all the parameters in this function.
+  // Invoke the assume_query to determine what values these parameters
+  // have when the fu

[gcc r14-11104] Fix comment typos in tree-assume.cc

[Andrew Carlotti via Gcc-cvs]

https://gcc.gnu.org/g:87f9c0e4ae2ad7f5f4fde2438ba57af7ea45cafc

commit r14-11104-g87f9c0e4ae2ad7f5f4fde2438ba57af7ea45cafc
Author: Andrew Carlotti 
Date:   Wed Dec 18 16:16:51 2024 +

Fix comment typos in tree-assume.cc

gcc/ChangeLog:

* tree-assume.cc: Fix comment typos.

Diff:
---
 gcc/tree-assume.cc | 32 
 1 file changed, 16 insertions(+), 16 deletions(-)

diff --git a/gcc/tree-assume.cc b/gcc/tree-assume.cc
index 897b5ce3bafe..10c1343492c0 100644
--- a/gcc/tree-assume.cc
+++ b/gcc/tree-assume.cc
@@ -36,16 +36,16 @@ along with GCC; see the file COPYING3.  If not see
 #include "gimple-pretty-print.h"
 #include "tree-cfg.h"
 
-// An assume query utilizes the current range query to implelemtn the assume
+// An assume query utilizes the current range query to implement the assume
 // keyword.
 // For any return value of 1 from the function, it attempts to determine
-// which paths leads to a 1 value being returned. On those paths, what
+// which paths lead to a 1 value being returned. On those paths, it determines
 // the ranges of any ssa_names listed in bitmap P (usually the parm list for
-// the function) are, and combined them all.
+// the function), and combines them all.
 // These ranges are then set as the global ranges for those parms in this
 // function.
-// Other functions which then refer to this function in an assume builtin
-// will then pick up these ranges for the paramters via the inferred range
+// Other functions which refer to this function in an assume builtin
+// will then pick up these ranges for the parameters via the inferred range
 // mechanism.
 //   See gimple-range-infer.cc::gimple_infer_range::check_assume_func ()
 //
@@ -57,11 +57,11 @@ along with GCC; see the file COPYING3.  If not see
 //
 // a small temporary assume function consisting of
 // assume_f1 (int x) { return x == 1 || x == 4; }
-// is constructed by the front end, and optimzed, at the very end of
+// is constructed by the front end, and optimized, at the very end of
 // optimization, instead of generating code, we instead invoke the assume pass
 // which uses this query to set the the global value of parm x to [1,1][4,4]
 //
-// Meanwhile., my_Fund has been rewritten to be:
+// Meanwhile., my_func has been rewritten to be:
 //
 // my_func (int x_2)
 // {
@@ -70,12 +70,12 @@ along with GCC; see the file COPYING3.  If not see
 //   if (x_2 == 3)
 //
 // When ranger is processing the assume_builtin_call, it looks up the global
-// value of the paramter in assume_f1, which is [1,1][4,4].  It then registers
+// value of the parameter in assume_f1, which is [1,1][4,4].  It then registers
 // and inferred range at this statement setting the value x_2 to [1,1][4,4]
 //
-// Any uses of x_2 after this statement will now utilzie this inferred range.
+// Any uses of x_2 after this statement will now utilize this inferred range.
 //
-// When VRP precoesses if (x_2 == 3), it picks up the inferred range, and
+// When VRP processes if (x_2 == 3), it picks up the inferred range, and
 // determines that x_2 can never be 3, and will rewrite the branch to
 //   if (0 != 0)
 
@@ -110,7 +110,7 @@ assume_query::assume_query (gimple_ranger *ranger, function 
*f, bitmap p)
   : m_ranger (ranger), m_parm_list (p), m_func (f)
 {
   basic_block exit_bb = EXIT_BLOCK_PTR_FOR_FN (f);
-  // If there is more than one precessor to the exit block, bail.
+  // If there is more than one predecessor to the exit block, bail.
   if (!single_pred_p (exit_bb))
 return;
 
@@ -131,7 +131,7 @@ assume_query::assume_query (gimple_ranger *ranger, function 
*f, bitmap p)
   if (!irange::supports_p (lhs_type))
 return;
 
-  // Only values of interest are when the return value is 1.  The defintion
+  // Only values of interest are when the return value is 1.  The definition
   // of the return value must be in the same block, or we have
   // complicated flow control we don't understand, and just return.
   unsigned prec = TYPE_PRECISION (lhs_type);
@@ -173,7 +173,7 @@ assume_query::assume_query (gimple_ranger *ranger, function 
*f, bitmap p)
 }
 }
 
-// This function Will update all the current value of interesting parameters.
+// This function will update all the current values of interesting parameters.
 // It tries, in order:
 //a) a range found via path calculations.
 //b) range of the parm at SRC point in the IL. (either edge or stmt)
@@ -341,9 +341,9 @@ public:
   bool gate (function *fun) final override { return fun->assume_function; }
   unsigned int execute (function *fun) final override
 {
-  // Create a bitmap of all the paramters in this function.
-  // Invoke the assume_query to detemine what values these parameters
-  // have when the function returns TRUE, and set the globals value of
+  // Create a bitmap of all the parameters in this function.
+  // Invoke the assume_query to determine what values these parameters
+  // have when the 

[gcc r15-7199] aarch64: Add +cpa feature flag

[Andrew Carlotti via Gcc-cvs]

https://gcc.gnu.org/g:12b7220dc5beafaf9c738b473e046ed66e49a52a

commit r15-7199-g12b7220dc5beafaf9c738b473e046ed66e49a52a
Author: Andrew Carlotti 
Date:   Fri Jan 24 11:00:41 2025 +

aarch64: Add +cpa feature flag

This doesn't enable anything within the compiler, but this allows the
flag to be passed the assembler.  There also doesn't appear to be a
kernel cpuinfo name yet.

gcc/ChangeLog:

* config/aarch64/aarch64-arches.def (V9_5A): Add CPA.
* config/aarch64/aarch64-option-extensions.def (CPA): New.
* doc/invoke.texi: Document +cpa.

Diff:
---
 gcc/config/aarch64/aarch64-arches.def| 2 +-
 gcc/config/aarch64/aarch64-option-extensions.def | 2 ++
 gcc/doc/invoke.texi  | 4 +++-
 3 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/gcc/config/aarch64/aarch64-arches.def 
b/gcc/config/aarch64/aarch64-arches.def
index dacb7b6f37a3..34a792d69510 100644
--- a/gcc/config/aarch64/aarch64-arches.def
+++ b/gcc/config/aarch64/aarch64-arches.def
@@ -46,6 +46,6 @@ AARCH64_ARCH("armv9.1-a", generic_armv9_a,   V9_1A, 
9,  (V8_6A, V9A))
 AARCH64_ARCH("armv9.2-a", generic_armv9_a,   V9_2A, 9,  (V8_7A, V9_1A))
 AARCH64_ARCH("armv9.3-a", generic_armv9_a,   V9_3A, 9,  (V8_8A, V9_2A))
 AARCH64_ARCH("armv9.4-a", generic_armv9_a,   V9_4A, 9,  (V8_9A, V9_3A))
-AARCH64_ARCH("armv9.5-a", generic_armv9_a,   V9_5A, 9,  (V9_4A, 
FAMINMAX, LUT))
+AARCH64_ARCH("armv9.5-a", generic_armv9_a,   V9_5A, 9,  (V9_4A, CPA, 
FAMINMAX, LUT))
 
 #undef AARCH64_ARCH
diff --git a/gcc/config/aarch64/aarch64-option-extensions.def 
b/gcc/config/aarch64/aarch64-option-extensions.def
index a1133accfce5..cc42bd518dca 100644
--- a/gcc/config/aarch64/aarch64-option-extensions.def
+++ b/gcc/config/aarch64/aarch64-option-extensions.def
@@ -275,6 +275,8 @@ AARCH64_OPT_EXTENSION("ssve-fp8dot2", SSVE_FP8DOT2, 
(SSVE_FP8DOT4), (), (), "sme
 
 AARCH64_OPT_EXTENSION("lut", LUT, (SIMD), (), (), "lut")
 
+AARCH64_OPT_EXTENSION("cpa", CPA, (), (), (), "")
+
 #undef AARCH64_OPT_FMV_EXTENSION
 #undef AARCH64_OPT_EXTENSION
 #undef AARCH64_FMV_FEATURE
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index c8721064f91e..e54a287d 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -21672,7 +21672,7 @@ and the features that they enable by default:
 @item @samp{armv9.2-a} @tab Armv9.2-A @tab @samp{armv9.1-a}, @samp{+wfxt}, 
@samp{+xs}
 @item @samp{armv9.3-a} @tab Armv9.3-A @tab @samp{armv9.2-a}, @samp{+mops}
 @item @samp{armv9.4-a} @tab Armv9.4-A @tab @samp{armv9.3-a}
-@item @samp{armv9.5-a} @tab Armv9.4-A @tab @samp{armv9.4-a}, @samp{+faminmax}, 
@samp{+lut}
+@item @samp{armv9.5-a} @tab Armv9.4-A @tab @samp{armv9.4-a}, @samp{cpa}, 
@samp{+faminmax}, @samp{+lut}
 @item @samp{armv8-r} @tab Armv8-R @tab @samp{armv8-r}
 @end multitable
 
@@ -22085,6 +22085,8 @@ extension in streaming mode.
 Enable the Floating Point Absolute Maximum/Minimum extension.
 @item lut
 Enable the Lookup Table extension.
+@item cpa
+Enable the Checked Pointer Arithmetic instructions.
 @item sve-b16b16
 Enable the SVE non-widening brain floating-point (@code{bf16}) extension.
 This only has an effect when @code{sve2} or @code{sme2} are also enabled.

[gcc r15-7189] aarch64: Rename info structs in aarch64-common.cc

[Andrew Carlotti via Gcc-cvs]

https://gcc.gnu.org/g:5a674214b9fe96db4c1a033c585e40cd97592d5b

commit r15-7189-g5a674214b9fe96db4c1a033c585e40cd97592d5b
Author: Andrew Carlotti 
Date:   Wed Jan 8 22:58:05 2025 +

aarch64: Rename info structs in aarch64-common.cc

Also add a (currently unused) processor field to aarch64_processor_info,
and change name from "" to NULL for the terminating array entries.

gcc/ChangeLog:

* common/config/aarch64/aarch64-common.cc
(struct aarch64_option_extension): Rename to..
(struct aarch64_extension_info): ...this.
(all_extensions): Update type name.
(struct arch_to_arch_name): Rename to...
(struct aarch64_arch_info): ...this, and rename name field.
(all_architectures): Update type names, and move before...
(struct processor_name_to_arch): ...this. Rename to...
(struct aarch64_processor_info): ...this, rename name field and
add cpu field.
(all_cores): Update type name, and set new field.
(aarch64_parse_extension): Update names.
(aarch64_get_all_extension_candidates): Ditto.
(aarch64_rewrite_selected_cpu): Ditto.

Diff:
---
 gcc/common/config/aarch64/aarch64-common.cc | 50 -
 1 file changed, 27 insertions(+), 23 deletions(-)

diff --git a/gcc/common/config/aarch64/aarch64-common.cc 
b/gcc/common/config/aarch64/aarch64-common.cc
index 75600548fdc6..3368af00b030 100644
--- a/gcc/common/config/aarch64/aarch64-common.cc
+++ b/gcc/common/config/aarch64/aarch64-common.cc
@@ -145,8 +145,9 @@ aarch64_handle_option (struct gcc_options *opts,
 }
 }
 
+
 /* An ISA extension in the co-processor and main instruction set space.  */
-struct aarch64_option_extension
+struct aarch64_extension_info
 {
   /* The extension name to pass on to the assembler.  */
   const char *name;
@@ -159,7 +160,7 @@ struct aarch64_option_extension
 };
 
 /* ISA extensions in AArch64.  */
-static constexpr aarch64_option_extension all_extensions[] =
+static constexpr aarch64_extension_info all_extensions[] =
 {
 #define AARCH64_OPT_EXTENSION(NAME, IDENT, C, D, E, FEATURE_STRING) \
   {NAME, AARCH64_FL_##IDENT, feature_deps::IDENT ().explicit_on, \
@@ -168,38 +169,41 @@ static constexpr aarch64_option_extension 
all_extensions[] =
   {NULL, 0, 0, 0}
 };
 
-struct processor_name_to_arch
+struct aarch64_arch_info
 {
-  const char *processor_name;
+  const char *name;
   aarch64_arch arch;
   aarch64_feature_flags flags;
 };
 
-struct arch_to_arch_name
+/* Map architecture revisions to their string representation.  */
+static constexpr aarch64_arch_info all_architectures[] =
+{
+#define AARCH64_ARCH(NAME, B, ARCH_IDENT, D, E)\
+  {NAME, AARCH64_ARCH_##ARCH_IDENT, feature_deps::ARCH_IDENT ().enable},
+#include "config/aarch64/aarch64-arches.def"
+  {NULL, aarch64_no_arch, 0}
+};
+
+struct aarch64_processor_info
 {
+  const char *name;
+  aarch64_cpu processor;
   aarch64_arch arch;
-  const char *arch_name;
   aarch64_feature_flags flags;
 };
 
 /* Map processor names to the architecture revision they implement and
the default set of architectural feature flags they support.  */
-static constexpr processor_name_to_arch all_cores[] =
+static constexpr aarch64_processor_info all_cores[] =
 {
 #define AARCH64_CORE(NAME, CORE_IDENT, C, ARCH_IDENT, E, F, G, H, I) \
-  {NAME, AARCH64_ARCH_##ARCH_IDENT, feature_deps::cpu_##CORE_IDENT},
+  {NAME, AARCH64_CPU_##CORE_IDENT, AARCH64_ARCH_##ARCH_IDENT, \
+   feature_deps::cpu_##CORE_IDENT},
 #include "config/aarch64/aarch64-cores.def"
-  {"", aarch64_no_arch, 0}
+  {NULL, aarch64_no_cpu, aarch64_no_arch, 0}
 };
 
-/* Map architecture revisions to their string representation.  */
-static constexpr arch_to_arch_name all_architectures[] =
-{
-#define AARCH64_ARCH(NAME, B, ARCH_IDENT, D, E)\
-  {AARCH64_ARCH_##ARCH_IDENT, NAME, feature_deps::ARCH_IDENT ().enable},
-#include "config/aarch64/aarch64-arches.def"
-  {aarch64_no_arch, "", 0}
-};
 
 /* Parse the architecture extension string STR and update ISA_FLAGS
with the architecture features turned on or off.  Return a
@@ -212,7 +216,7 @@ aarch64_parse_extension (const char *str, 
aarch64_feature_flags *isa_flags,
  std::string *invalid_extension)
 {
   /* The extension string is parsed left to right.  */
-  const struct aarch64_option_extension *opt = NULL;
+  const struct aarch64_extension_info *opt = NULL;
 
   /* Flag to say whether we are adding or removing an extension.  */
   int adding_ext = -1;
@@ -276,7 +280,7 @@ aarch64_parse_extension (const char *str, 
aarch64_feature_flags *isa_flags,
 void
 aarch64_get_all_extension_candidates (auto_vec *candidates)
 {
-  const struct aarch64_option_extension *opt;
+  const struct aarch64_extension_info *opt;
   for (opt = all_extensions; opt->name != NULL; opt++)
 candidates->safe_push (opt->name);
 }
@@ -396,16 +400,16 @@ aarch64_rewrit

[gcc r15-7195] aarch64: Refactor aarch64_rewrite_mcpu

[Andrew Carlotti via Gcc-cvs]

https://gcc.gnu.org/g:c6ef35b4c3c092bf5e0171827ed918d4249575ca

commit r15-7195-gc6ef35b4c3c092bf5e0171827ed918d4249575ca
Author: Andrew Carlotti 
Date:   Thu Jan 23 19:07:09 2025 +

aarch64: Refactor aarch64_rewrite_mcpu

Use aarch64_validate_cpu instead of the existing duplicate (and worse)
version of the -mcpu parsing code.

The original code used fatal_error; I'm guessing that using error
instead should be ok.

gcc/ChangeLog:

* common/config/aarch64/aarch64-common.cc
(aarch64_rewrite_selected_cpu): Refactor and inline into...
(aarch64_rewrite_mcpu): this.
* config/aarch64/aarch64-protos.h
(aarch64_rewrite_selected_cpu): Delete.

Diff:
---
 gcc/common/config/aarch64/aarch64-common.cc | 78 +++--
 gcc/config/aarch64/aarch64-protos.h |  1 -
 2 files changed, 17 insertions(+), 62 deletions(-)

diff --git a/gcc/common/config/aarch64/aarch64-common.cc 
b/gcc/common/config/aarch64/aarch64-common.cc
index abb9565e13e1..427a1938902c 100644
--- a/gcc/common/config/aarch64/aarch64-common.cc
+++ b/gcc/common/config/aarch64/aarch64-common.cc
@@ -732,60 +732,29 @@ aarch64_rewrite_march (int argc, const char **argv)
   return xstrdup (outstr.c_str ());
 }
 
-/* Attempt to rewrite NAME, which has been passed on the command line
-   as a -mcpu option to an equivalent -march value.  If we can do so,
-   return the new string, otherwise return an error.  */
+/* Called by the driver to rewrite a name passed to the -mcpu argument
+   to an equivalent -march value to be passed to the assembler.  The
+   names passed from the commend line will be in ARGV, we want
+   to use the right-most argument, which should be in
+   ARGV[ARGC - 1].  ARGC should always be greater than 0.  */
 
 const char *
-aarch64_rewrite_selected_cpu (const char *name)
+aarch64_rewrite_mcpu (int argc, const char **argv)
 {
-  std::string original_string (name);
-  std::string extension_str;
-  std::string processor;
-  size_t extension_pos = original_string.find_first_of ('+');
-
-  /* Strip and save the extension string.  */
-  if (extension_pos != std::string::npos)
-{
-  processor = original_string.substr (0, extension_pos);
-  extension_str = original_string.substr (extension_pos,
- std::string::npos);
-}
-  else
-{
-  /* No extensions.  */
-  processor = original_string;
-}
-
-  const struct aarch64_processor_info* p_to_a;
-  for (p_to_a = all_cores;
-   p_to_a->arch != aarch64_no_arch;
-   p_to_a++)
-{
-  if (p_to_a->name == processor)
-   break;
-}
-
-  const struct aarch64_arch_info* a_to_an;
-  for (a_to_an = all_architectures;
-   a_to_an->arch != aarch64_no_arch;
-   a_to_an++)
-{
-  if (a_to_an->arch == p_to_a->arch)
-   break;
-}
+  gcc_assert (argc);
+  const char *name = argv[argc - 1];
+  aarch64_cpu cpu;
+  aarch64_feature_flags flags;
 
-  /* We couldn't find that processor name, or the processor name we
- found does not map to an architecture we understand.  */
-  if (p_to_a->arch == aarch64_no_arch
-  || a_to_an->arch == aarch64_no_arch)
-fatal_error (input_location, "unknown value %qs for %<-mcpu%>", name);
+  aarch64_validate_mcpu (name, &cpu, &flags);
 
-  aarch64_feature_flags extensions = p_to_a->flags;
-  aarch64_parse_extension (extension_str.c_str (), &extensions, NULL);
+  const struct aarch64_processor_info *entry;
+  for (entry = all_cores; entry->processor != aarch64_no_cpu; entry++)
+if (entry->processor == cpu)
+  break;
 
-  std::string outstr = aarch64_get_arch_string_for_assembler (a_to_an->arch,
- extensions);
+  std::string outstr = aarch64_get_arch_string_for_assembler (entry->arch,
+ flags);
 
   /* We are going to memory leak here, nobody elsewhere
  in the callchain is going to clean up after us.  The alternative is
@@ -794,19 +763,6 @@ aarch64_rewrite_selected_cpu (const char *name)
   return xstrdup (outstr.c_str ());
 }
 
-/* Called by the driver to rewrite a name passed to the -mcpu
-   argument in preparation to be passed to the assembler.  The
-   names passed from the commend line will be in ARGV, we want
-   to use the right-most argument, which should be in
-   ARGV[ARGC - 1].  ARGC should always be greater than 0.  */
-
-const char *
-aarch64_rewrite_mcpu (int argc, const char **argv)
-{
-  gcc_assert (argc);
-  return aarch64_rewrite_selected_cpu (argv[argc - 1]);
-}
-
 /* Checks to see if the host CPU may not be Cortex-A53 or an unknown Armv8-a
baseline CPU.  */
 
diff --git a/gcc/config/aarch64/aarch64-protos.h 
b/gcc/config/aarch64/aarch64-protos.h
index b27da1e25720..4235f4a0ca51 100644
--- a/gcc/config/aarch64/aarch64-protos.h
+++ b/gcc/config/aarch64/aarch64-protos.h
@@ -1210,7 +1210,6 @@ boo

[gcc r15-7192] aarch64: Move arch/cpu parsing to aarch64-common.cc

[Andrew Carlotti via Gcc-cvs]

https://gcc.gnu.org/g:ecb4565a473adf810ea6d4e11709efc41d968dff

commit r15-7192-gecb4565a473adf810ea6d4e11709efc41d968dff
Author: Andrew Carlotti 
Date:   Thu Jan 23 17:08:17 2025 +

aarch64: Move arch/cpu parsing to aarch64-common.cc

Aside from moving the functions, the only changes are to make them
non-static, and to use the existing info arrays within aarch64-common.cc
instead of the info arrays remaining in aarch64.cc.

gcc/ChangeLog:

* common/config/aarch64/aarch64-common.cc
(aarch64_get_all_extension_candidates): Move within file.
(aarch64_print_hint_candidates): Move from aarch64.cc.
(aarch64_print_hint_for_extensions): Ditto.
(aarch64_print_hint_for_arch): Ditto.
(aarch64_print_hint_for_core): Ditto.
(enum aarch_parse_opt_result): Ditto.
(aarch64_parse_arch): Ditto.
(aarch64_parse_cpu): Ditto.
(aarch64_parse_tune): Ditto.
(aarch64_validate_march): Ditto.
(aarch64_validate_mcpu): Ditto.
(aarch64_validate_mtune): Ditto.
* config/aarch64/aarch64-protos.h
(aarch64_rewrite_selected_cpu): Move within file.
(aarch64_print_hint_for_extensions): Share function prototype.
(aarch64_print_hint_for_arch): Ditto.
(aarch64_print_hint_for_core): Ditto.
(enum aarch_parse_opt_result): Ditto.
(aarch64_validate_march): Ditto.
(aarch64_validate_mcpu): Ditto.
(aarch64_validate_mtune): Ditto.
(aarch64_get_all_extension_candidates): Unshare prototype.
* config/aarch64/aarch64.cc
(aarch64_parse_arch): Move to aarch64-common.cc.
(aarch64_parse_cpu): Ditto.
(aarch64_parse_tune): Ditto.
(aarch64_print_hint_candidates): Ditto.
(aarch64_print_hint_for_core): Ditto.
(aarch64_print_hint_for_arch): Ditto.
(aarch64_print_hint_for_extensions): Ditto.
(aarch64_validate_mcpu): Ditto.
(aarch64_validate_march): Ditto.
(aarch64_validate_mtune): Ditto.

Diff:
---
 gcc/common/config/aarch64/aarch64-common.cc | 334 +++-
 gcc/config/aarch64/aarch64-protos.h |  20 +-
 gcc/config/aarch64/aarch64.cc   | 320 --
 3 files changed, 346 insertions(+), 328 deletions(-)

diff --git a/gcc/common/config/aarch64/aarch64-common.cc 
b/gcc/common/config/aarch64/aarch64-common.cc
index 3368af00b030..c3ea54ca3f77 100644
--- a/gcc/common/config/aarch64/aarch64-common.cc
+++ b/gcc/common/config/aarch64/aarch64-common.cc
@@ -205,6 +205,78 @@ static constexpr aarch64_processor_info all_cores[] =
 };
 
 
+/* Print a list of CANDIDATES for an argument, and try to suggest a specific
+   close match.  */
+
+inline static void
+aarch64_print_hint_candidates (const char *str,
+  const auto_vec & candidates)
+{
+  char *s;
+  const char *hint = candidates_list_and_hint (str, s, candidates);
+  if (hint)
+inform (input_location, "valid arguments are: %s;"
+" did you mean %qs?", s, hint);
+  else
+inform (input_location, "valid arguments are: %s", s);
+
+  XDELETEVEC (s);
+}
+
+/* Append all architecture extension candidates to the CANDIDATES vector.  */
+
+void
+aarch64_get_all_extension_candidates (auto_vec *candidates)
+{
+  const struct aarch64_extension_info *opt;
+  for (opt = all_extensions; opt->name != NULL; opt++)
+candidates->safe_push (opt->name);
+}
+
+/* Print a hint with a suggestion for an extension name
+   that most closely resembles what the user passed in STR.  */
+
+void
+aarch64_print_hint_for_extensions (const char *str)
+{
+  auto_vec candidates;
+  aarch64_get_all_extension_candidates (&candidates);
+  aarch64_print_hint_candidates (str, candidates);
+}
+
+/* Print a hint with a suggestion for an architecture name that most closely
+   resembles what the user passed in STR.  */
+
+void
+aarch64_print_hint_for_arch (const char *str)
+{
+  auto_vec candidates;
+  const struct aarch64_arch_info *entry = all_architectures;
+  for (; entry->name != NULL; entry++)
+candidates.safe_push (entry->name);
+
+#ifdef HAVE_LOCAL_CPU_DETECT
+  /* Add also "native" as possible value.  */
+  candidates.safe_push ("native");
+#endif
+
+  aarch64_print_hint_candidates (str, candidates);
+}
+
+/* Print a hint with a suggestion for a core name that most closely resembles
+   what the user passed in STR.  */
+
+void
+aarch64_print_hint_for_core (const char *str)
+{
+  auto_vec candidates;
+  const struct aarch64_processor_info *entry = all_cores;
+  for (; entry->name != NULL; entry++)
+candidates.safe_push (entry->name);
+  aarch64_print_hint_candidates (str, candidates);
+}
+
+
 /* Parse the architecture extension string STR and update ISA_FLAGS
with the architecture features turned o

[gcc r15-7187] aarch64: Replace duplicate cpu enums

[Andrew Carlotti via Gcc-cvs]

https://gcc.gnu.org/g:997bba31ea8c1f7b4b7227e18afa8adb734ee946

commit r15-7187-g997bba31ea8c1f7b4b7227e18afa8adb734ee946
Author: Andrew Carlotti 
Date:   Wed Jan 8 20:06:09 2025 +

aarch64: Replace duplicate cpu enums

Replace `enum aarch64_processor` and `enum target_cpus` with
`enum aarch64_cpu`, and prefix the entries with `AARCH64_CPU_`.
Also rename aarch64_none to aarch64_no_cpu.

gcc/ChangeLog:

* config/aarch64/aarch64-opts.h
(enum aarch64_processor): Rename to...
(enum aarch64_cpu): ...this, and rename the entries.
* config/aarch64/aarch64.cc
(aarch64_type): Rename type and initial value.
(struct processor): Rename member types.
(all_architectures): Rename enum members.
(all_cores): Ditto.
(aarch64_get_tune_cpu): Rename type and enum member.
* config/aarch64/aarch64.h (enum target_cpus): Remove.
(TARGET_CPU_DEFAULT): Rename default value.
(aarch64_tune): Rename type.
* config/aarch64/aarch64.opt:
(selected_tune): Rename type and default value.

Diff:
---
 gcc/config/aarch64/aarch64-opts.h |  6 +++---
 gcc/config/aarch64/aarch64.cc | 18 +-
 gcc/config/aarch64/aarch64.h  | 11 ++-
 gcc/config/aarch64/aarch64.opt|  2 +-
 4 files changed, 15 insertions(+), 22 deletions(-)

diff --git a/gcc/config/aarch64/aarch64-opts.h 
b/gcc/config/aarch64/aarch64-opts.h
index 3f0b1e9414c3..a6ca5cf016b0 100644
--- a/gcc/config/aarch64/aarch64-opts.h
+++ b/gcc/config/aarch64/aarch64-opts.h
@@ -38,13 +38,13 @@ typedef bbitmap<2> aarch64_feature_flags;
 #endif
 
 /* The various cores that implement AArch64.  */
-enum aarch64_processor
+enum aarch64_cpu
 {
 #define AARCH64_CORE(NAME, INTERNAL_IDENT, SCHED, ARCH, FLAGS, COSTS, IMP, 
PART, VARIANT) \
-  INTERNAL_IDENT,
+  AARCH64_CPU_##INTERNAL_IDENT,
 #include "aarch64-cores.def"
   /* Used to mark the end of the processor table.  */
-  aarch64_none
+  aarch64_no_cpu
 };
 
 enum aarch64_arch
diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc
index e7a75411f071..4d3b28b4cdb4 100644
--- a/gcc/config/aarch64/aarch64.cc
+++ b/gcc/config/aarch64/aarch64.cc
@@ -357,7 +357,7 @@ static bool aarch64_print_address_internal (FILE*, 
machine_mode, rtx,
aarch64_addr_query_type);
 
 /* The processor for which instructions should be scheduled.  */
-enum aarch64_processor aarch64_tune = cortexa53;
+enum aarch64_cpu aarch64_tune = AARCH64_CPU_cortexa53;
 
 /* Global flag for PC relative loads.  */
 bool aarch64_pcrelative_literal_loads;
@@ -451,8 +451,8 @@ aarch64_tuning_override_functions[] =
 struct processor
 {
   const char *name;
-  aarch64_processor ident;
-  aarch64_processor sched_core;
+  aarch64_cpu ident;
+  aarch64_cpu sched_core;
   aarch64_arch arch;
   aarch64_feature_flags flags;
   const tune_params *tune;
@@ -462,20 +462,20 @@ struct processor
 static CONSTEXPR const processor all_architectures[] =
 {
 #define AARCH64_ARCH(NAME, CORE, ARCH_IDENT, D, E) \
-  {NAME, CORE, CORE, AARCH64_ARCH_##ARCH_IDENT, \
+  {NAME, AARCH64_CPU_##CORE, AARCH64_CPU_##CORE, AARCH64_ARCH_##ARCH_IDENT, \
feature_deps::ARCH_IDENT ().enable, NULL},
 #include "aarch64-arches.def"
-  {NULL, aarch64_none, aarch64_none, aarch64_no_arch, 0, NULL}
+  {NULL, aarch64_no_cpu, aarch64_no_cpu, aarch64_no_arch, 0, NULL}
 };
 
 /* Processor cores implementing AArch64.  */
 static const struct processor all_cores[] =
 {
 #define AARCH64_CORE(NAME, IDENT, SCHED, ARCH, E, COSTS, G, H, I) \
-  {NAME, IDENT, SCHED, AARCH64_ARCH_##ARCH, \
+  {NAME, AARCH64_CPU_##IDENT, AARCH64_CPU_##SCHED, AARCH64_ARCH_##ARCH, \
feature_deps::cpu_##IDENT, &COSTS##_tunings},
 #include "aarch64-cores.def"
-  {NULL, aarch64_none, aarch64_none, aarch64_no_arch, 0, NULL}
+  {NULL, aarch64_no_cpu, aarch64_no_cpu, aarch64_no_arch, 0, NULL}
 };
 /* Internal representation of system registers.  */
 typedef struct {
@@ -18566,9 +18566,9 @@ initialize_aarch64_tls_size (struct gcc_options *opts)
 /* Return the CPU corresponding to the enum CPU.  */
 
 static const struct processor *
-aarch64_get_tune_cpu (enum aarch64_processor cpu)
+aarch64_get_tune_cpu (enum aarch64_cpu cpu)
 {
-  gcc_assert (cpu != aarch64_none);
+  gcc_assert (cpu != aarch64_no_cpu);
 
   return &all_cores[cpu];
 }
diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h
index 1a19b27fd934..6f7a73fe1d7e 100644
--- a/gcc/config/aarch64/aarch64.h
+++ b/gcc/config/aarch64/aarch64.h
@@ -928,16 +928,9 @@ enum reg_class
 /* CPU/ARCH option handling.  */
 #include "config/aarch64/aarch64-opts.h"
 
-enum target_cpus
-{
-#define AARCH64_CORE(NAME, INTERNAL_IDENT, SCHED, ARCH, FLAGS, COSTS, IMP, 
PART, VARIANT) \
-  TARGET_CPU_##INTERNAL_IDENT,
-#include "aarch64-cores.def"
-};
-
 /* If there is no CPU defined at configure, use generic as default.  */
 #ifn

[gcc r15-7194] aarch64: Rewrite architecture strings for assembler

[Andrew Carlotti via Gcc-cvs]

https://gcc.gnu.org/g:15e07e14372cfeb53cbdfb7cf96a8a49e402da68

commit r15-7194-g15e07e14372cfeb53cbdfb7cf96a8a49e402da68
Author: Andrew Carlotti 
Date:   Mon Nov 11 12:20:25 2024 +

aarch64: Rewrite architecture strings for assembler

Add infrastructure to allow rewriting the architecture strings passed to
the assembler (either as -march options or .arch directives).  There was
already canonicalisation everywhere except for an -march driver option
passed directly to the compiler; this patch applies the same
canonicalisation there as well.

gcc/ChangeLog:

* common/config/aarch64/aarch64-common.cc
(aarch64_get_arch_string_for_assembler): New.
(aarch64_rewrite_march): New.
(aarch64_rewrite_selected_cpu): Call new function.
* config/aarch64/aarch64-elf.h (ASM_SPEC): Remove identity mapping.
* config/aarch64/aarch64-protos.h
(aarch64_get_arch_string_for_assembler): New.
* config/aarch64/aarch64.cc
(aarch64_declare_function_name): Call new function.
(aarch64_start_file): Ditto.
* config/aarch64/aarch64.h
(EXTRA_SPEC_FUNCTIONS): Use new macro name.
(MCPU_TO_MARCH_SPEC): Rename to...
(MARCH_REWRITE_SPEC): ...this, and extend the spec rule.
(aarch64_rewrite_march): New declaration.
(MCPU_TO_MARCH_SPEC_FUNCTIONS): Rename to...
(AARCH64_BASE_SPEC_FUNCTIONS): ...this, and add new function.
(ASM_CPU_SPEC): Use new macro name.

Diff:
---
 gcc/common/config/aarch64/aarch64-common.cc | 49 ++---
 gcc/config/aarch64/aarch64-elf.h|  1 -
 gcc/config/aarch64/aarch64-protos.h |  2 ++
 gcc/config/aarch64/aarch64.cc   | 31 +++---
 gcc/config/aarch64/aarch64.h| 15 +
 5 files changed, 68 insertions(+), 30 deletions(-)

diff --git a/gcc/common/config/aarch64/aarch64-common.cc 
b/gcc/common/config/aarch64/aarch64-common.cc
index 9923437761c9..abb9565e13e1 100644
--- a/gcc/common/config/aarch64/aarch64-common.cc
+++ b/gcc/common/config/aarch64/aarch64-common.cc
@@ -690,6 +690,48 @@ aarch64_get_extension_string_for_isa_flags
   return outstr;
 }
 
+/* Generate an arch string to be passed to the assembler.  */
+
+std::string
+aarch64_get_arch_string_for_assembler (aarch64_arch arch,
+  aarch64_feature_flags flags)
+{
+  const struct aarch64_arch_info *entry;
+  for (entry = all_architectures; entry->arch != aarch64_no_arch; entry++)
+if (entry->arch == arch)
+   break;
+
+  std::string outstr = entry->name
+   + aarch64_get_extension_string_for_isa_flags (flags, entry->flags);
+
+  return outstr;
+}
+
+/* Called by the driver to rewrite a name passed to the -march
+   argument in preparation to be passed to the assembler.  The
+   names passed from the commend line will be in ARGV, we want
+   to use the right-most argument, which should be in
+   ARGV[ARGC - 1].  ARGC should always be greater than 0.  */
+
+const char *
+aarch64_rewrite_march (int argc, const char **argv)
+{
+  gcc_assert (argc);
+  const char *name = argv[argc - 1];
+  aarch64_arch arch;
+  aarch64_feature_flags flags;
+
+  aarch64_validate_march (name, &arch, &flags);
+
+  std::string outstr = aarch64_get_arch_string_for_assembler (arch, flags);
+
+  /* We are going to memory leak here, nobody elsewhere
+ in the callchain is going to clean up after us.  The alternative is
+ to allocate a static buffer, and assert that it is big enough for our
+ modified string, which seems much worse!  */
+  return xstrdup (outstr.c_str ());
+}
+
 /* Attempt to rewrite NAME, which has been passed on the command line
as a -mcpu option to an equivalent -march value.  If we can do so,
return the new string, otherwise return an error.  */
@@ -733,7 +775,7 @@ aarch64_rewrite_selected_cpu (const char *name)
break;
 }
 
-  /* We couldn't find that proceesor name, or the processor name we
+  /* We couldn't find that processor name, or the processor name we
  found does not map to an architecture we understand.  */
   if (p_to_a->arch == aarch64_no_arch
   || a_to_an->arch == aarch64_no_arch)
@@ -742,9 +784,8 @@ aarch64_rewrite_selected_cpu (const char *name)
   aarch64_feature_flags extensions = p_to_a->flags;
   aarch64_parse_extension (extension_str.c_str (), &extensions, NULL);
 
-  std::string outstr = a_to_an->name
-   + aarch64_get_extension_string_for_isa_flags (extensions,
- a_to_an->flags);
+  std::string outstr = aarch64_get_arch_string_for_assembler (a_to_an->arch,
+ extensions);
 
   /* We are going to memory leak here, nobody elsewhere
  in the callchain is going to clean up after us.  The alternative is
diff --git a/gcc/config

[gcc r15-7191] aarch64: Inline aarch64_print_hint_for_core_or_arch

[Andrew Carlotti via Gcc-cvs]

https://gcc.gnu.org/g:5c5b6a922ad3931039690cd79c8d1351361790f3

commit r15-7191-g5c5b6a922ad3931039690cd79c8d1351361790f3
Author: Andrew Carlotti 
Date:   Thu Jan 9 00:53:11 2025 +

aarch64: Inline aarch64_print_hint_for_core_or_arch

It seems odd that we add "native" to the list for -march but not for
-mcpu.  This is probably a bug, but for now we'll preserve the existing
behaviour.

gcc/ChangeLog:

* config/aarch64/aarch64.cc
(aarch64_print_hint_candidates): New helper function.
(aarch64_print_hint_for_core_or_arch): Inline into callers.
(aarch64_print_hint_for_core): Inline callee and use new helper.
(aarch64_print_hint_for_arch): Ditto.
(aarch64_print_hint_for_extensions): Use new helper.

Diff:
---
 gcc/config/aarch64/aarch64.cc | 50 +++
 1 file changed, 22 insertions(+), 28 deletions(-)

diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc
index 56c9f66861b3..ae1235640d27 100644
--- a/gcc/config/aarch64/aarch64.cc
+++ b/gcc/config/aarch64/aarch64.cc
@@ -18891,25 +18891,13 @@ aarch64_override_options_internal (struct gcc_options 
*opts)
   aarch64_override_options_after_change_1 (opts);
 }
 
-/* Print a hint with a suggestion for a core or architecture name that
-   most closely resembles what the user passed in STR.  ARCH is true if
-   the user is asking for an architecture name.  ARCH is false if the user
-   is asking for a core name.  */
+/* Print a list of CANDIDATES for an argument, and try to suggest a specific
+   close match.  */
 
-static void
-aarch64_print_hint_for_core_or_arch (const char *str, bool arch)
+inline static void
+aarch64_print_hint_candidates (const char *str,
+  const auto_vec & candidates)
 {
-  auto_vec candidates;
-  const struct processor *entry = arch ? all_architectures : all_cores;
-  for (; entry->name != NULL; entry++)
-candidates.safe_push (entry->name);
-
-#ifdef HAVE_LOCAL_CPU_DETECT
-  /* Add also "native" as possible value.  */
-  if (arch)
-candidates.safe_push ("native");
-#endif
-
   char *s;
   const char *hint = candidates_list_and_hint (str, s, candidates);
   if (hint)
@@ -18927,7 +18915,11 @@ aarch64_print_hint_for_core_or_arch (const char *str, 
bool arch)
 inline static void
 aarch64_print_hint_for_core (const char *str)
 {
-  aarch64_print_hint_for_core_or_arch (str, false);
+  auto_vec candidates;
+  const struct processor *entry = all_cores;
+  for (; entry->name != NULL; entry++)
+candidates.safe_push (entry->name);
+  aarch64_print_hint_candidates (str, candidates);
 }
 
 /* Print a hint with a suggestion for an architecture name that most closely
@@ -18936,7 +18928,17 @@ aarch64_print_hint_for_core (const char *str)
 inline static void
 aarch64_print_hint_for_arch (const char *str)
 {
-  aarch64_print_hint_for_core_or_arch (str, true);
+  auto_vec candidates;
+  const struct processor *entry = all_architectures;
+  for (; entry->name != NULL; entry++)
+candidates.safe_push (entry->name);
+
+#ifdef HAVE_LOCAL_CPU_DETECT
+  /* Add also "native" as possible value.  */
+  candidates.safe_push ("native");
+#endif
+
+  aarch64_print_hint_candidates (str, candidates);
 }
 
 
@@ -18948,15 +18950,7 @@ aarch64_print_hint_for_extensions (const char *str)
 {
   auto_vec candidates;
   aarch64_get_all_extension_candidates (&candidates);
-  char *s;
-  const char *hint = candidates_list_and_hint (str, s, candidates);
-  if (hint)
-inform (input_location, "valid arguments are: %s;"
-" did you mean %qs?", s, hint);
-  else
-inform (input_location, "valid arguments are: %s", s);
-
-  XDELETEVEC (s);
+  aarch64_print_hint_candidates (str, candidates);
 }
 
 /* Validate a command-line -mcpu option.  Parse the cpu and extensions (if any)

[gcc r15-7186] aarch64: Improve mcpu/march conflict check

[Andrew Carlotti via Gcc-cvs]

https://gcc.gnu.org/g:936463004836cb565f4fc4773dccedbfccf0028f

commit r15-7186-g936463004836cb565f4fc4773dccedbfccf0028f
Author: Andrew Carlotti 
Date:   Wed Jan 8 18:29:27 2025 +

aarch64: Improve mcpu/march conflict check

Features from a cpu or base architecture that were explicitly disabled
by a +nofeat option were being incorrectly added back in before checking
for conflicts between -mcpu and -march options.  This patch instead
compares the returned feature masks directly.

gcc/ChangeLog:

* config/aarch64/aarch64.cc (aarch64_override_options): Compare
returned feature masks directly.

gcc/testsuite/ChangeLog:

* gcc.target/aarch64/target_attr_crypto_ice_1.c: Prune warning.
* gcc.target/aarch64/target_attr_crypto_ice_2.c: Ditto.

Diff:
---
 gcc/config/aarch64/aarch64.cc   | 7 ++-
 gcc/testsuite/gcc.target/aarch64/target_attr_crypto_ice_1.c | 1 +
 gcc/testsuite/gcc.target/aarch64/target_attr_crypto_ice_2.c | 1 +
 3 files changed, 4 insertions(+), 5 deletions(-)

diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc
index 9c4e9bc8acde..e7a75411f071 100644
--- a/gcc/config/aarch64/aarch64.cc
+++ b/gcc/config/aarch64/aarch64.cc
@@ -19289,13 +19289,10 @@ aarch64_override_options (void)
 cpu features would end up disabling an achitecture feature.  In
 otherwords the cpu features need to be a strict superset of the arch
 features and if so prefer the -march ISA flags.  */
-  auto full_arch_flags = arch->flags | arch_isa;
-  auto full_cpu_flags = cpu->flags | cpu_isa;
-  if (~full_cpu_flags & full_arch_flags)
+  if (~cpu_isa & arch_isa)
{
  std::string ext_diff
-   = aarch64_get_extension_string_for_isa_flags (full_arch_flags,
- full_cpu_flags);
+   = aarch64_get_extension_string_for_isa_flags (arch_isa, cpu_isa);
  warning (0, "switch %<-mcpu=%s%> conflicts with %<-march=%s%> switch "
  "and resulted in options %qs being added",
   aarch64_cpu_string,
diff --git a/gcc/testsuite/gcc.target/aarch64/target_attr_crypto_ice_1.c 
b/gcc/testsuite/gcc.target/aarch64/target_attr_crypto_ice_1.c
index 3b354c061109..f13e5e2560cd 100644
--- a/gcc/testsuite/gcc.target/aarch64/target_attr_crypto_ice_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/target_attr_crypto_ice_1.c
@@ -1,5 +1,6 @@
 /* { dg-do compile } */
 /* { dg-options "-O2 -mcpu=thunderx+nofp -march=armv8-a" } */
+/* { dg-prune-output "warning: switch .* conflicts" } */
 
 #include "arm_neon.h"
 
diff --git a/gcc/testsuite/gcc.target/aarch64/target_attr_crypto_ice_2.c 
b/gcc/testsuite/gcc.target/aarch64/target_attr_crypto_ice_2.c
index d0a62b83351b..ab2549228a7f 100644
--- a/gcc/testsuite/gcc.target/aarch64/target_attr_crypto_ice_2.c
+++ b/gcc/testsuite/gcc.target/aarch64/target_attr_crypto_ice_2.c
@@ -1,5 +1,6 @@
 /* { dg-do compile } */
 /* { dg-options "-O2 -mcpu=thunderx+nofp -march=armv8-a" } */
+/* { dg-prune-output "warning: switch .* conflicts" } */
 
 /* Make sure that we don't ICE when dealing with vector parameters
in a simd-tagged function within a non-simd translation unit.  */

[gcc r15-7198] docs: Add +wfxt and +xs to armv9.2-a

[Andrew Carlotti via Gcc-cvs]

https://gcc.gnu.org/g:25464e795eb35f859bdb353c806e93e6ae924ff0

commit r15-7198-g25464e795eb35f859bdb353c806e93e6ae924ff0
Author: Andrew Carlotti 
Date:   Fri Jan 10 19:22:20 2025 +

docs: Add +wfxt and +xs to armv9.2-a

I missed that the documentation doesn't include armv8.7-a
within armv9.2-a.

gcc/ChangeLog:

* doc/invoke.texi: Add +wfxt and +xs to armv9.2-a

Diff:
---
 gcc/doc/invoke.texi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 819a68439342..c8721064f91e 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -21669,7 +21669,7 @@ and the features that they enable by default:
 @item @samp{armv8.9-a} @tab Armv8.9-a @tab @samp{armv8.8-a}
 @item @samp{armv9-a} @tab Armv9-A @tab @samp{armv8.5-a}, @samp{+sve}, 
@samp{+sve2}
 @item @samp{armv9.1-a} @tab Armv9.1-A @tab @samp{armv9-a}, @samp{+bf16}, 
@samp{+i8mm}
-@item @samp{armv9.2-a} @tab Armv9.2-A @tab @samp{armv9.1-a}
+@item @samp{armv9.2-a} @tab Armv9.2-A @tab @samp{armv9.1-a}, @samp{+wfxt}, 
@samp{+xs}
 @item @samp{armv9.3-a} @tab Armv9.3-A @tab @samp{armv9.2-a}, @samp{+mops}
 @item @samp{armv9.4-a} @tab Armv9.4-A @tab @samp{armv9.3-a}
 @item @samp{armv9.5-a} @tab Armv9.4-A @tab @samp{armv9.4-a}, @samp{+faminmax}, 
@samp{+lut}

[gcc r15-7197] aarch64: Add command line support for armv9.5-a

[Andrew Carlotti via Gcc-cvs]

https://gcc.gnu.org/g:c7847680cf18aaa26d607de5b3678c50470b9e87

commit r15-7197-gc7847680cf18aaa26d607de5b3678c50470b9e87
Author: Andrew Carlotti 
Date:   Fri Jan 10 19:19:19 2025 +

aarch64: Add command line support for armv9.5-a

gcc/ChangeLog:

* config/aarch64/aarch64-arches.def (V9_5A): New.
* doc/invoke.texi: Document armv9.5-a option.

gcc/testsuite/ChangeLog:

* gcc.target/aarch64/simd/armv9p5.c: New test.

Diff:
---
 gcc/config/aarch64/aarch64-arches.def   |  1 +
 gcc/doc/invoke.texi |  1 +
 gcc/testsuite/gcc.target/aarch64/simd/armv9p5.c | 14 ++
 3 files changed, 16 insertions(+)

diff --git a/gcc/config/aarch64/aarch64-arches.def 
b/gcc/config/aarch64/aarch64-arches.def
index fd4881a8ebfb..dacb7b6f37a3 100644
--- a/gcc/config/aarch64/aarch64-arches.def
+++ b/gcc/config/aarch64/aarch64-arches.def
@@ -46,5 +46,6 @@ AARCH64_ARCH("armv9.1-a", generic_armv9_a,   V9_1A, 
9,  (V8_6A, V9A))
 AARCH64_ARCH("armv9.2-a", generic_armv9_a,   V9_2A, 9,  (V8_7A, V9_1A))
 AARCH64_ARCH("armv9.3-a", generic_armv9_a,   V9_3A, 9,  (V8_8A, V9_2A))
 AARCH64_ARCH("armv9.4-a", generic_armv9_a,   V9_4A, 9,  (V8_9A, V9_3A))
+AARCH64_ARCH("armv9.5-a", generic_armv9_a,   V9_5A, 9,  (V9_4A, 
FAMINMAX, LUT))
 
 #undef AARCH64_ARCH
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 2f5d60baadbe..819a68439342 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -21672,6 +21672,7 @@ and the features that they enable by default:
 @item @samp{armv9.2-a} @tab Armv9.2-A @tab @samp{armv9.1-a}
 @item @samp{armv9.3-a} @tab Armv9.3-A @tab @samp{armv9.2-a}, @samp{+mops}
 @item @samp{armv9.4-a} @tab Armv9.4-A @tab @samp{armv9.3-a}
+@item @samp{armv9.5-a} @tab Armv9.4-A @tab @samp{armv9.4-a}, @samp{+faminmax}, 
@samp{+lut}
 @item @samp{armv8-r} @tab Armv8-R @tab @samp{armv8-r}
 @end multitable
 
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/armv9p5.c 
b/gcc/testsuite/gcc.target/aarch64/simd/armv9p5.c
new file mode 100644
index ..6df47b8de1cc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/armv9p5.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=armv9.5-a" } */
+
+#include "arm_neon.h"
+
+int8x16_t foo (int8x16_t table, uint8x16_t indicies)
+{
+  return vluti2q_laneq_s8 (table, indicies, 1);
+}
+
+float32x4_t bar (float32x4_t a, float32x4_t b)
+{
+  return vaminq_f32 (a, b);
+}

[gcc r15-7196] aarch64: Make AARCH64_FL_CRYPTO always unset

[Andrew Carlotti via Gcc-cvs]

https://gcc.gnu.org/g:b53781ce1e49fcaa18c2b7c0d4602c6ed780a9e9

commit r15-7196-gb53781ce1e49fcaa18c2b7c0d4602c6ed780a9e9
Author: Andrew Carlotti 
Date:   Thu Jan 9 19:33:25 2025 +

aarch64: Make AARCH64_FL_CRYPTO always unset

This feature flag bit only exists to support the +crypto alias.  Outside
of option processing this bit needs to be set or unset consistently.
This patch goes with the latter option.

gcc/ChangeLog:

* common/config/aarch64/aarch64-common.cc: Assert that CRYPTO
bit is not set.
* config/aarch64/aarch64-feature-deps.h
(info.explicit_on): Unset CRYPTO bit.
(cpu_##CORE_IDENT): Ditto.

gcc/testsuite/ChangeLog:

* gcc.target/aarch64/crypto-alias-1.c: New test.

Diff:
---
 gcc/common/config/aarch64/aarch64-common.cc   |  4 
 gcc/config/aarch64/aarch64-feature-deps.h | 12 
 gcc/testsuite/gcc.target/aarch64/crypto-alias-1.c | 14 ++
 3 files changed, 26 insertions(+), 4 deletions(-)

diff --git a/gcc/common/config/aarch64/aarch64-common.cc 
b/gcc/common/config/aarch64/aarch64-common.cc
index 427a1938902c..ef4458fb6930 100644
--- a/gcc/common/config/aarch64/aarch64-common.cc
+++ b/gcc/common/config/aarch64/aarch64-common.cc
@@ -613,6 +613,10 @@ aarch64_get_extension_string_for_isa_flags
 {
   std::string outstr = "";
 
+  /* The CRYPTO bit should only be used to support the +crypto alias
+ during option processing, and should be cleared at all other times.
+ Verify this property for the supplied flags bitmask.  */
+  gcc_assert (!(AARCH64_FL_CRYPTO & aarch64_isa_flags));
   aarch64_feature_flags current_flags = default_arch_flags;
 
   /* As a special case, do not assume that the assembler will enable CRC
diff --git a/gcc/config/aarch64/aarch64-feature-deps.h 
b/gcc/config/aarch64/aarch64-feature-deps.h
index 67c3a5da8aa3..55a0dbfae610 100644
--- a/gcc/config/aarch64/aarch64-feature-deps.h
+++ b/gcc/config/aarch64/aarch64-feature-deps.h
@@ -56,7 +56,8 @@ get_enable (T1 i, Ts... args)
 
- explicit_on: the transitive closure of the features that an
  explicit +FEATURE enables, including FLAG itself.  This is
- always a superset of ENABLE
+ always a superset of ENABLE, except that the CRYPTO alias bit is
+ explicitly unset for consistency.
 
Also define a function FEATURE () that returns an info
(which is an empty structure, since all members are static).
@@ -69,7 +70,8 @@ template struct info;
   template<> struct info { \
 static constexpr auto flag = AARCH64_FL_##IDENT;   \
 static constexpr auto enable = flag | get_enable REQUIRES; \
-static constexpr auto explicit_on = enable | get_enable EXPLICIT_ON; \
+static constexpr auto explicit_on   \
+  = (enable | get_enable EXPLICIT_ON) & ~AARCH64_FL_CRYPTO; \
   };   \
   constexpr aarch64_feature_flags info::flag;  \
   constexpr aarch64_feature_flags info::enable;
\
@@ -114,9 +116,11 @@ get_flags_off (aarch64_feature_flags mask)
 #include "config/aarch64/aarch64-option-extensions.def"
 
 /* Define cpu_ variables for each CPU, giving the transitive
-   closure of all the features that the CPU supports.  */
+   closure of all the features that the CPU supports.  The CRYPTO bit is just
+   an alias, so explicitly unset it for consistency.  */
 #define AARCH64_CORE(A, CORE_IDENT, C, ARCH_IDENT, FEATURES, F, G, H, I) \
-  constexpr auto cpu_##CORE_IDENT = ARCH_IDENT ().enable | get_enable FEATURES;
+  constexpr auto cpu_##CORE_IDENT \
+= (ARCH_IDENT ().enable | get_enable FEATURES) & ~AARCH64_FL_CRYPTO;
 #include "config/aarch64/aarch64-cores.def"
 
 /* Define fmv_deps_ variables for each FMV feature, giving the transitive
diff --git a/gcc/testsuite/gcc.target/aarch64/crypto-alias-1.c 
b/gcc/testsuite/gcc.target/aarch64/crypto-alias-1.c
new file mode 100644
index ..e2662b44e2db
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/crypto-alias-1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-mcpu=ampere1" } */
+
+__attribute__ ((__always_inline__))
+__attribute__ ((target ("arch=armv8-a+crypto")))
+inline int bar()
+{
+  return 5;
+}
+
+int foo()
+{
+  return bar();
+}

[gcc r15-7193] aarch64: Inline aarch64_get_all_extension_candidates

[Andrew Carlotti via Gcc-cvs]

https://gcc.gnu.org/g:1edf47698a8204da74a6f154b7380f6016f2f78b

commit r15-7193-g1edf47698a8204da74a6f154b7380f6016f2f78b
Author: Andrew Carlotti 
Date:   Thu Jan 23 17:24:17 2025 +

aarch64: Inline aarch64_get_all_extension_candidates

gcc/ChangeLog:

* common/config/aarch64/aarch64-common.cc
(aarch64_get_all_extension_candidates): Inline into...
(aarch64_print_hint_for_extensions): ...this.

Diff:
---
 gcc/common/config/aarch64/aarch64-common.cc | 15 ---
 1 file changed, 4 insertions(+), 11 deletions(-)

diff --git a/gcc/common/config/aarch64/aarch64-common.cc 
b/gcc/common/config/aarch64/aarch64-common.cc
index c3ea54ca3f77..9923437761c9 100644
--- a/gcc/common/config/aarch64/aarch64-common.cc
+++ b/gcc/common/config/aarch64/aarch64-common.cc
@@ -223,16 +223,6 @@ aarch64_print_hint_candidates (const char *str,
   XDELETEVEC (s);
 }
 
-/* Append all architecture extension candidates to the CANDIDATES vector.  */
-
-void
-aarch64_get_all_extension_candidates (auto_vec *candidates)
-{
-  const struct aarch64_extension_info *opt;
-  for (opt = all_extensions; opt->name != NULL; opt++)
-candidates->safe_push (opt->name);
-}
-
 /* Print a hint with a suggestion for an extension name
that most closely resembles what the user passed in STR.  */
 
@@ -240,7 +230,10 @@ void
 aarch64_print_hint_for_extensions (const char *str)
 {
   auto_vec candidates;
-  aarch64_get_all_extension_candidates (&candidates);
+  const struct aarch64_extension_info *opt;
+  for (opt = all_extensions; opt->name != NULL; opt++)
+candidates.safe_push (opt->name);
+
   aarch64_print_hint_candidates (str, candidates);
 }

[gcc r15-7190] aarch64: Adjust option parsing parameter types.

[Andrew Carlotti via Gcc-cvs]

https://gcc.gnu.org/g:1ba5027ebfe96b507d32f884a0ee8064cbbbc15d

commit r15-7190-g1ba5027ebfe96b507d32f884a0ee8064cbbbc15d
Author: Andrew Carlotti 
Date:   Wed Jan 8 23:52:01 2025 +

aarch64: Adjust option parsing parameter types.

Replace `const struct processor *` in output parameters with
`aarch64_arch` or `aarch64_cpu`.

Replace `std:string` parameter in aarch64_print_hint_for_extensions with
`char *`.

Also name the return parameters more clearly and consistently.

gcc/ChangeLog:

* config/aarch64/aarch64.cc
(aarch64_print_hint_for_extensions): Receive string as a char *.
(aarch64_parse_arch): Don't return a const struct processor *.
(aarch64_parse_cpu): Ditto.
(aarch64_parse_tune): Ditto.
(aarch64_validate_mtune): Ditto.
(aarch64_validate_mcpu): Ditto, and use temporary variables for
march/mcpu cross-check.
(aarch64_validate_march): Ditto.
(aarch64_override_options): Adjust for changed parameter types.
(aarch64_handle_attr_arch): Ditto.
(aarch64_handle_attr_cpu): Ditto.
(aarch64_handle_attr_tune): Ditto.

Diff:
---
 gcc/config/aarch64/aarch64.cc | 174 ++
 1 file changed, 93 insertions(+), 81 deletions(-)

diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc
index 4d3b28b4cdb4..56c9f66861b3 100644
--- a/gcc/config/aarch64/aarch64.cc
+++ b/gcc/config/aarch64/aarch64.cc
@@ -18224,16 +18224,16 @@ better_main_loop_than_p (const vector_costs 
*uncast_other) const
 
 static void initialize_aarch64_code_model (struct gcc_options *);
 
-/* Parse the TO_PARSE string and put the architecture struct that it
-   selects into RES and the architectural features into ISA_FLAGS.
+/* Parse the TO_PARSE string and put the architecture that it
+   selects into RES_ARCH and the architectural features into RES_FLAGS.
Return an aarch_parse_opt_result describing the parse result.
-   If there is an error parsing, RES and ISA_FLAGS are left unchanged.
+   If there is an error parsing, RES_ARCH and RES_FLAGS are left unchanged.
When the TO_PARSE string contains an invalid extension,
a copy of the string is created and stored to INVALID_EXTENSION.  */
 
 static enum aarch_parse_opt_result
-aarch64_parse_arch (const char *to_parse, const struct processor **res,
-   aarch64_feature_flags *isa_flags,
+aarch64_parse_arch (const char *to_parse, aarch64_arch *res_arch,
+   aarch64_feature_flags *res_flags,
std::string *invalid_extension)
 {
   const char *ext;
@@ -18257,21 +18257,21 @@ aarch64_parse_arch (const char *to_parse, const 
struct processor **res,
   if (strlen (arch->name) == len
  && strncmp (arch->name, to_parse, len) == 0)
{
- auto isa_temp = arch->flags;
+ auto isa_flags = arch->flags;
 
  if (ext != NULL)
{
  /* TO_PARSE string contains at least one extension.  */
  enum aarch_parse_opt_result ext_res
-   = aarch64_parse_extension (ext, &isa_temp, invalid_extension);
+   = aarch64_parse_extension (ext, &isa_flags, invalid_extension);
 
  if (ext_res != AARCH_PARSE_OK)
return ext_res;
}
  /* Extension parsing was successful.  Confirm the result
 arch and ISA flags.  */
- *res = arch;
- *isa_flags = isa_temp;
+ *res_arch = arch->arch;
+ *res_flags = isa_flags;
  return AARCH_PARSE_OK;
}
 }
@@ -18280,16 +18280,16 @@ aarch64_parse_arch (const char *to_parse, const 
struct processor **res,
   return AARCH_PARSE_INVALID_ARG;
 }
 
-/* Parse the TO_PARSE string and put the result tuning in RES and the
-   architecture flags in ISA_FLAGS.  Return an aarch_parse_opt_result
-   describing the parse result.  If there is an error parsing, RES and
-   ISA_FLAGS are left unchanged.
+/* Parse the TO_PARSE string and put the result tuning in RES_CPU and the
+   architecture flags in RES_FLAGS.  Return an aarch_parse_opt_result
+   describing the parse result.  If there is an error parsing, RES_CPU and
+   RES_FLAGS are left unchanged.
When the TO_PARSE string contains an invalid extension,
a copy of the string is created and stored to INVALID_EXTENSION.  */
 
 static enum aarch_parse_opt_result
-aarch64_parse_cpu (const char *to_parse, const struct processor **res,
-  aarch64_feature_flags *isa_flags,
+aarch64_parse_cpu (const char *to_parse, aarch64_cpu *res_cpu,
+  aarch64_feature_flags *res_flags,
   std::string *invalid_extension)
 {
   const char *ext;
@@ -18312,21 +18312,21 @@ aarch64_parse_cpu (const char *to_parse, const struct 
processor **res,
 {
   if (strlen (cpu->name) == len && strncmp (cpu->name, to_parse, len) == 0)

[gcc r15-7188] aarch64: Remove redundant generic cpu entry

[Andrew Carlotti via Gcc-cvs]

https://gcc.gnu.org/g:362cdb70bc25598e17f79b604975d63ccad13a4f

commit r15-7188-g362cdb70bc25598e17f79b604975d63ccad13a4f
Author: Andrew Carlotti 
Date:   Wed Jan 8 20:27:17 2025 +

aarch64: Remove redundant generic cpu entry

The list of cores in aarch64-common.cc included an explicit "generic"
entry, despite this entry also being present in aarch64-cores.def.

gcc/ChangeLog:

* common/config/aarch64/aarch64-common.cc
(all_cores): Remove explicit generic entry.

Diff:
---
 gcc/common/config/aarch64/aarch64-common.cc | 1 -
 1 file changed, 1 deletion(-)

diff --git a/gcc/common/config/aarch64/aarch64-common.cc 
b/gcc/common/config/aarch64/aarch64-common.cc
index 92df8b619305..75600548fdc6 100644
--- a/gcc/common/config/aarch64/aarch64-common.cc
+++ b/gcc/common/config/aarch64/aarch64-common.cc
@@ -189,7 +189,6 @@ static constexpr processor_name_to_arch all_cores[] =
 #define AARCH64_CORE(NAME, CORE_IDENT, C, ARCH_IDENT, E, F, G, H, I) \
   {NAME, AARCH64_ARCH_##ARCH_IDENT, feature_deps::cpu_##CORE_IDENT},
 #include "config/aarch64/aarch64-cores.def"
-  {"generic", AARCH64_ARCH_V8A, feature_deps::V8A ().enable},
   {"", aarch64_no_arch, 0}
 };

[gcc r15-6790] docs: Document new hardreg PRE pass

[Andrew Carlotti via Gcc-cvs]

https://gcc.gnu.org/g:016e2f00d40d76676f38fb9d268ac550e5ec878a

commit r15-6790-g016e2f00d40d76676f38fb9d268ac550e5ec878a
Author: Andrew Carlotti 
Date:   Wed Dec 18 15:59:24 2024 +

docs: Document new hardreg PRE pass

gcc/ChangeLog:

* doc/passes.texi: Document hardreg PRE pass.

Diff:
---
 gcc/doc/passes.texi | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/gcc/doc/passes.texi b/gcc/doc/passes.texi
index 59a143292c78..282fc1a6a12b 100644
--- a/gcc/doc/passes.texi
+++ b/gcc/doc/passes.texi
@@ -959,6 +959,12 @@ global constant and  copy propagation.
 The source file for this pass is @file{gcse.cc}, and the LCM routines
 are in @file{lcm.cc}.
 
+A third version of this pass is run on some targets to optimise assignments to
+specific hard registers.  This can be used in cases where a register has a
+single purpose, such as specifying a mode as an extra input for specific
+instructions (@pxref{mode switching optimization} for another way of handling
+instruction modes).
+
 @item Loop optimization
 
 This pass performs several loop related optimizations.
@@ -1018,6 +1024,7 @@ combination approaches as well.
 The pass runs twice, once before register allocation and once after
 register allocation.  The code is located in @file{late-combine.cc}.
 
+@anchor{mode switching optimization}
 @item Mode switching optimization
 
 This pass looks for instructions that require the processor to be in a

[gcc r15-6789] Add new hardreg PRE pass

[Andrew Carlotti via Gcc-cvs]

https://gcc.gnu.org/g:e7f98d9603808b1c17106d3d9f2000bc34f2c50c

commit r15-6789-ge7f98d9603808b1c17106d3d9f2000bc34f2c50c
Author: Andrew Carlotti 
Date:   Tue Oct 15 17:31:28 2024 +0100

Add new hardreg PRE pass

This pass is used to optimise assignments to the FPMR register in
aarch64.  I chose to implement this as a middle-end pass because it
mostly reuses the existing RTL PRE code within gcse.cc.

Compared to RTL PRE, the key difference in this new pass is that we
insert new writes directly to the destination hardreg, instead of
writing to a new pseudo-register and copying the result later.  This
requires changes to the analysis portion of the pass, because sets
cannot be moved before existing instructions that set, use or clobber
the hardreg, and the value becomes unavailable after any uses of
clobbers of the hardreg.

Any uses of the hardreg in debug insns will be deleted.  We could do
better than this, but for the aarch64 fpmr I don't think we emit useful
debuginfo for deleted fp8 instructions anyway (and I don't even know if
it's possible to have a debug fpmr use when entering hardreg PRE).

gcc/ChangeLog:

* config/aarch64/aarch64.h (HARDREG_PRE_REGNOS): New macro.
* gcse.cc (doing_hardreg_pre_p): New global variable.
(do_load_motion): New boolean check.
(current_hardreg_regno): New global variable.
(compute_local_properties): Unset transp for hardreg clobbers.
(prune_hardreg_uses): New function.
(want_to_gcse_p): Use different checks for hardreg PRE.
(oprs_unchanged_p): Disable load motion for hardreg PRE pass.
(hash_scan_set): For hardreg PRE, skip non-hardreg sets and
check for hardreg clobbers.
(record_last_mem_set_info): Skip for hardreg PRE.
(compute_pre_data): Prune hardreg uses from transp bitmap.
(pre_expr_reaches_here_p_work): Add sentence to comment.
(insert_insn_start_basic_block): New functions.
(pre_edge_insert): Don't add hardreg sets to predecessor block.
(pre_delete): Use hardreg for the reaching reg.
(reset_hardreg_debug_uses): New function.
(pre_gcse): For hardreg PRE, reset debug uses and don't insert
copies.
(one_pre_gcse_pass): Disable load motion for hardreg PRE.
(execute_hardreg_pre): New.
(class pass_hardreg_pre): New.
(pass_hardreg_pre::gate): New.
(make_pass_hardreg_pre): New.
* passes.def (pass_hardreg_pre): New pass.
* tree-pass.h (make_pass_hardreg_pre): New.

gcc/testsuite/ChangeLog:

* gcc.target/aarch64/acle/fpmr-1.c: New test.
* gcc.target/aarch64/acle/fpmr-2.c: New test.
* gcc.target/aarch64/acle/fpmr-3.c: New test.
* gcc.target/aarch64/acle/fpmr-4.c: New test.

Diff:
---
 gcc/config/aarch64/aarch64.h   |   4 +
 gcc/gcse.cc| 339 ++---
 gcc/passes.def |   1 +
 gcc/testsuite/gcc.target/aarch64/acle/fpmr-1.c |  58 +
 gcc/testsuite/gcc.target/aarch64/acle/fpmr-2.c |  15 ++
 gcc/testsuite/gcc.target/aarch64/acle/fpmr-3.c |  18 ++
 gcc/testsuite/gcc.target/aarch64/acle/fpmr-4.c |  23 ++
 gcc/tree-pass.h|   1 +
 8 files changed, 427 insertions(+), 32 deletions(-)

diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h
index 3f3a475eb01d..1ab49e229b08 100644
--- a/gcc/config/aarch64/aarch64.h
+++ b/gcc/config/aarch64/aarch64.h
@@ -1652,6 +1652,10 @@ enum class aarch64_tristate_mode : int { NO, YES, MAYBE 
};
   { int (aarch64_tristate_mode::MAYBE), \
 int (aarch64_local_sme_state::ANY) }
 
+/* Zero terminated list of regnos for which hardreg PRE should be
+   applied.  */
+#define HARDREG_PRE_REGNOS { FPM_REGNUM, 0 }
+
 #endif
 
 #endif /* GCC_AARCH64_H */
diff --git a/gcc/gcse.cc b/gcc/gcse.cc
index 839cac3ddab3..3f3f7fe15b0c 100644
--- a/gcc/gcse.cc
+++ b/gcc/gcse.cc
@@ -415,6 +415,17 @@ static int gcse_create_count;
 
 /* Doing code hoisting.  */
 static bool doing_code_hoisting_p = false;
+
+/* Doing hardreg_pre.  */
+static bool doing_hardreg_pre_p = false;
+
+inline bool
+do_load_motion ()
+{
+  return flag_gcse_lm && !doing_hardreg_pre_p;
+}
+
+static unsigned int current_hardreg_regno;
 
 /* For available exprs */
 static sbitmap *ae_kill;
@@ -689,14 +700,32 @@ compute_local_properties (sbitmap *transp, sbitmap *comp, 
sbitmap *antloc,
  int indx = expr->bitmap_index;
  struct gcse_occr *occr;
 
- /* The expression is transparent in this block if it is not killed.
-We start by assuming all are transparent [none are killed], and
-then reset the bits for those that are.  */
+ /* In most cases, the expre

[gcc r15-6780] aarch64: Add new +fcma flag

[Andrew Carlotti via Gcc-cvs]

https://gcc.gnu.org/g:9bbb91e8e0a3a26fe2ff651a89011ca5a0b4794d

commit r15-6780-g9bbb91e8e0a3a26fe2ff651a89011ca5a0b4794d
Author: Andrew Carlotti 
Date:   Thu Aug 1 11:54:20 2024 +0100

aarch64: Add new +fcma flag

This includes +fcma as a dependency of +sve, and means that we can
finally support fcma intrinsics on a64fx.

Also add fcma to the Features list in several cpunative testcases that
incorrectly included sve without fcma.

gcc/ChangeLog:

* config/aarch64/aarch64-arches.def (V8_3A): Add FCMA.
* config/aarch64/aarch64-option-extensions.def (FCMA): New flag.
(SVE): Add FCMA dependency.
* config/aarch64/aarch64.h (TARGET_COMPLEX): Use new flag.
* config/aarch64/arm_neon.h: Use new flag for fcma intrinsics.

gcc/testsuite/ChangeLog:

* gcc.target/aarch64/cpunative/info_15: Add fcma to Features.
* gcc.target/aarch64/cpunative/info_16: Ditto.
* gcc.target/aarch64/cpunative/info_17: Ditto.
* gcc.target/aarch64/cpunative/info_8: Ditto.
* gcc.target/aarch64/cpunative/info_9: Ditto.

Diff:
---
 gcc/config/aarch64/aarch64-arches.def  | 2 +-
 gcc/config/aarch64/aarch64-option-extensions.def   | 4 +++-
 gcc/config/aarch64/aarch64.h   | 2 +-
 gcc/config/aarch64/arm_neon.h  | 2 +-
 gcc/testsuite/gcc.target/aarch64/cpunative/info_15 | 2 +-
 gcc/testsuite/gcc.target/aarch64/cpunative/info_16 | 2 +-
 gcc/testsuite/gcc.target/aarch64/cpunative/info_17 | 2 +-
 gcc/testsuite/gcc.target/aarch64/cpunative/info_8  | 2 +-
 gcc/testsuite/gcc.target/aarch64/cpunative/info_9  | 2 +-
 9 files changed, 11 insertions(+), 9 deletions(-)

diff --git a/gcc/config/aarch64/aarch64-arches.def 
b/gcc/config/aarch64/aarch64-arches.def
index 62a7d9fd2442..d85b14be4c3f 100644
--- a/gcc/config/aarch64/aarch64-arches.def
+++ b/gcc/config/aarch64/aarch64-arches.def
@@ -33,7 +33,7 @@
 AARCH64_ARCH("armv8-a",   generic_armv8_a,   V8A,   8,  (SIMD))
 AARCH64_ARCH("armv8.1-a", generic_armv8_a,   V8_1A, 8,  (V8A, LSE, 
CRC, RDMA))
 AARCH64_ARCH("armv8.2-a", generic_armv8_a,   V8_2A, 8,  (V8_1A))
-AARCH64_ARCH("armv8.3-a", generic_armv8_a,   V8_3A, 8,  (V8_2A, PAUTH, 
RCPC))
+AARCH64_ARCH("armv8.3-a", generic_armv8_a,   V8_3A, 8,  (V8_2A, PAUTH, 
RCPC, FCMA))
 AARCH64_ARCH("armv8.4-a", generic_armv8_a,   V8_4A, 8,  (V8_3A, 
F16FML, DOTPROD, FLAGM))
 AARCH64_ARCH("armv8.5-a", generic_armv8_a,   V8_5A, 8,  (V8_4A, SB, 
SSBS, PREDRES))
 AARCH64_ARCH("armv8.6-a", generic_armv8_a,   V8_6A, 8,  (V8_5A, I8MM, 
BF16))
diff --git a/gcc/config/aarch64/aarch64-option-extensions.def 
b/gcc/config/aarch64/aarch64-option-extensions.def
index 6a70a63afd0a..c41c4998c5cb 100644
--- a/gcc/config/aarch64/aarch64-option-extensions.def
+++ b/gcc/config/aarch64/aarch64-option-extensions.def
@@ -151,6 +151,8 @@ AARCH64_OPT_EXTENSION("fp16fml", F16FML, (), (F16), (), 
"asimdfhm")
 
 AARCH64_FMV_FEATURE("fp16fml", FP16FML, (F16FML))
 
+AARCH64_OPT_FMV_EXTENSION("fcma", FCMA, (SIMD), (), (), "fcma")
+
 AARCH64_OPT_FMV_EXTENSION("rcpc", RCPC, (), (), (), "lrcpc")
 
 AARCH64_OPT_FMV_EXTENSION("rcpc3", RCPC3, (RCPC), (), (), "lrcpc3")
@@ -163,7 +165,7 @@ AARCH64_OPT_FMV_EXTENSION("bf16", BF16, (FP), (SIMD), (), 
"bf16")
 
 AARCH64_FMV_FEATURE("rpres", RPRES, ())
 
-AARCH64_OPT_FMV_EXTENSION("sve", SVE, (SIMD, F16), (), (), "sve")
+AARCH64_OPT_FMV_EXTENSION("sve", SVE, (SIMD, F16, FCMA), (), (), "sve")
 
 /* This specifically does not imply +sve.  */
 AARCH64_OPT_EXTENSION("sve-b16b16", SVE_B16B16, (), (), (), "sveb16b16")
diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h
index 75ea2a6910ee..250edb7d426d 100644
--- a/gcc/config/aarch64/aarch64.h
+++ b/gcc/config/aarch64/aarch64.h
@@ -364,7 +364,7 @@ constexpr auto AARCH64_FL_DEFAULT_ISA_MODE ATTRIBUTE_UNUSED
 #define TARGET_JSCVT   (TARGET_FLOAT && TARGET_ARMV8_3)
 
 /* Armv8.3-a Complex number extension to AdvSIMD extensions.  */
-#define TARGET_COMPLEX (TARGET_SIMD && TARGET_ARMV8_3)
+#define TARGET_COMPLEX AARCH64_HAVE_ISA (FCMA)
 
 /* Floating-point rounding instructions from Armv8.5-a.  */
 #define TARGET_FRINT (AARCH64_HAVE_ISA (V8_5A) && TARGET_FLOAT)
diff --git a/gcc/config/aarch64/arm_neon.h b/gcc/config/aarch64/arm_neon.h
index 20849b0b8a6d..da145adf6749 100644
--- a/gcc/config/aarch64/arm_neon.h
+++ b/gcc/config/aarch64/arm_neon.h
@@ -26975,7 +26975,7 @@ vbcaxq_s64 (int64x2_t __a, int64x2_t __b, int64x2_t __c)
 /* AdvSIMD Complex numbers intrinsics.  */
 
 #pragma GCC push_options
-#pragma GCC target ("arch=armv8.3-a")
+#pragma GCC target ("+nothing+fcma")
 
 #pragma GCC push_options
 #pragma GCC target ("+fp16")
diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/info_15 
b/gcc/testsuite/gcc.target/aarch64/cpunative/info_15
index 6b425ea20135..1a31a75d6b48 100644
--- a/gcc/testsuite/gcc.target/aarch64/cpu

[gcc r15-6784] aarch64: Add new +rcpc2 flag

[Andrew Carlotti via Gcc-cvs]

https://gcc.gnu.org/g:5747c121e9caa66a8173ad01db78769be08c407e

commit r15-6784-g5747c121e9caa66a8173ad01db78769be08c407e
Author: Andrew Carlotti 
Date:   Tue Jul 30 18:48:48 2024 +0100

aarch64: Add new +rcpc2 flag

gcc/ChangeLog:

* config/aarch64/aarch64-arches.def (V8_4A): Add RCPC2.
* config/aarch64/aarch64-option-extensions.def
(RCPC2): New flag.
(RCPC3): Add RCPC2 dependency.
* config/aarch64/aarch64.h (TARGET_RCPC2): Use new flag.

gcc/testsuite/ChangeLog:

* gcc.target/aarch64/cpunative/native_cpu_21.c: Add rcpc2 to
expected feature string instead of rcpc.
* gcc.target/aarch64/cpunative/native_cpu_22.c: Ditto.

Diff:
---
 gcc/config/aarch64/aarch64-arches.def  | 2 +-
 gcc/config/aarch64/aarch64-option-extensions.def   | 4 +++-
 gcc/config/aarch64/aarch64.h   | 2 +-
 gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_21.c | 2 +-
 gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_22.c | 2 +-
 5 files changed, 7 insertions(+), 5 deletions(-)

diff --git a/gcc/config/aarch64/aarch64-arches.def 
b/gcc/config/aarch64/aarch64-arches.def
index 8c2aa4e477fc..bcd08e21fde5 100644
--- a/gcc/config/aarch64/aarch64-arches.def
+++ b/gcc/config/aarch64/aarch64-arches.def
@@ -34,7 +34,7 @@ AARCH64_ARCH("armv8-a",   generic_armv8_a,   V8A,   
8,  (SIMD))
 AARCH64_ARCH("armv8.1-a", generic_armv8_a,   V8_1A, 8,  (V8A, LSE, 
CRC, RDMA))
 AARCH64_ARCH("armv8.2-a", generic_armv8_a,   V8_2A, 8,  (V8_1A))
 AARCH64_ARCH("armv8.3-a", generic_armv8_a,   V8_3A, 8,  (V8_2A, PAUTH, 
RCPC, FCMA, JSCVT))
-AARCH64_ARCH("armv8.4-a", generic_armv8_a,   V8_4A, 8,  (V8_3A, 
F16FML, DOTPROD, FLAGM))
+AARCH64_ARCH("armv8.4-a", generic_armv8_a,   V8_4A, 8,  (V8_3A, 
F16FML, DOTPROD, FLAGM, RCPC2))
 AARCH64_ARCH("armv8.5-a", generic_armv8_a,   V8_5A, 8,  (V8_4A, SB, 
SSBS, PREDRES, FRINTTS, FLAGM2))
 AARCH64_ARCH("armv8.6-a", generic_armv8_a,   V8_6A, 8,  (V8_5A, I8MM, 
BF16))
 AARCH64_ARCH("armv8.7-a", generic_armv8_a,   V8_7A, 8,  (V8_6A))
diff --git a/gcc/config/aarch64/aarch64-option-extensions.def 
b/gcc/config/aarch64/aarch64-option-extensions.def
index 00533c38839b..3558a6ed5ad7 100644
--- a/gcc/config/aarch64/aarch64-option-extensions.def
+++ b/gcc/config/aarch64/aarch64-option-extensions.def
@@ -159,7 +159,9 @@ AARCH64_OPT_FMV_EXTENSION("fcma", FCMA, (SIMD), (), (), 
"fcma")
 
 AARCH64_OPT_FMV_EXTENSION("rcpc", RCPC, (), (), (), "lrcpc")
 
-AARCH64_OPT_FMV_EXTENSION("rcpc3", RCPC3, (RCPC), (), (), "lrcpc3")
+AARCH64_OPT_FMV_EXTENSION("rcpc2", RCPC2, (RCPC), (), (), "ilrcpc")
+
+AARCH64_OPT_FMV_EXTENSION("rcpc3", RCPC3, (RCPC2), (), (), "lrcpc3")
 
 AARCH64_OPT_FMV_EXTENSION("frintts", FRINTTS, (FP), (), (), "frint")
 
diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h
index 1c8fcd5c582f..3f3a475eb01d 100644
--- a/gcc/config/aarch64/aarch64.h
+++ b/gcc/config/aarch64/aarch64.h
@@ -427,7 +427,7 @@ constexpr auto AARCH64_FL_DEFAULT_ISA_MODE ATTRIBUTE_UNUSED
 
 /* The RCPC2 extensions from Armv8.4-a that allow immediate offsets to LDAPR
and sign-extending versions.*/
-#define TARGET_RCPC2 ((AARCH64_HAVE_ISA (V8_4A) && TARGET_RCPC) || 
TARGET_RCPC3)
+#define TARGET_RCPC2 AARCH64_HAVE_ISA (RCPC2)
 
 /* RCPC3 (Release Consistency) extensions, optional from Armv8.2-a.  */
 #define TARGET_RCPC3 AARCH64_HAVE_ISA (RCPC3)
diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_21.c 
b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_21.c
index c1d5896e1eb0..904cdf452263 100644
--- a/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_21.c
+++ b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_21.c
@@ -7,7 +7,7 @@ int main()
   return 0;
 }
 
-/* { dg-final { scan-assembler {\.arch 
armv8-a\+flagm2\+lse\+dotprod\+rdma\+crc\+fp16fml\+jscvt\+rcpc\+frintts\+i8mm\+bf16\+sve2-aes\+sve2-bitperm\+sve2-sha3\+sve2-sm4\+sb\+ssbs\n}
 } } */
+/* { dg-final { scan-assembler {\.arch 
armv8-a\+flagm2\+lse\+dotprod\+rdma\+crc\+fp16fml\+jscvt\+rcpc2\+frintts\+i8mm\+bf16\+sve2-aes\+sve2-bitperm\+sve2-sha3\+sve2-sm4\+sb\+ssbs\n}
 } } */
 
 /* Check that an Armv8-A core doesn't fall apart on extensions without midr
values.  */
diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_22.c 
b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_22.c
index 4533a2bf5912..feb959b11b0e 100644
--- a/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_22.c
+++ b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_22.c
@@ -7,7 +7,7 @@ int main()
   return 0;
 }
 
-/* { dg-final { scan-assembler {\.arch 
armv8-a\+flagm2\+lse\+dotprod\+rdma\+crc\+fp16fml\+jscvt\+rcpc\+frintts\+i8mm\+bf16\+sve2-aes\+sve2-bitperm\+sve2-sha3\+sve2-sm4\+sb\+ssbs\+pauth\n}
 } } */
+/* { dg-final { scan-assembler {\.arch 
armv8-a\+flagm2\+lse\+dotprod\+rdma\+crc\+fp16fml\+js

[gcc r15-6786] aarch64: Add new +xs flag

[Andrew Carlotti via Gcc-cvs]

https://gcc.gnu.org/g:f06c6f8bf33e0b13d410b2305c58803a79754009

commit r15-6786-gf06c6f8bf33e0b13d410b2305c58803a79754009
Author: Andrew Carlotti 
Date:   Tue Jul 30 19:01:27 2024 +0100

aarch64: Add new +xs flag

GCC does not emit tlbi instructions, so this only affects the flags
passed through to the assembler.

gcc/ChangeLog:

* config/aarch64/aarch64-arches.def (V8_7A): Add XS.
* config/aarch64/aarch64-option-extensions.def (XS): New flag.

Diff:
---
 gcc/config/aarch64/aarch64-arches.def| 2 +-
 gcc/config/aarch64/aarch64-option-extensions.def | 2 ++
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/gcc/config/aarch64/aarch64-arches.def 
b/gcc/config/aarch64/aarch64-arches.def
index ff873a372431..fd4881a8ebfb 100644
--- a/gcc/config/aarch64/aarch64-arches.def
+++ b/gcc/config/aarch64/aarch64-arches.def
@@ -37,7 +37,7 @@ AARCH64_ARCH("armv8.3-a", generic_armv8_a,   V8_3A, 
8,  (V8_2A, PAUTH, R
 AARCH64_ARCH("armv8.4-a", generic_armv8_a,   V8_4A, 8,  (V8_3A, 
F16FML, DOTPROD, FLAGM, RCPC2))
 AARCH64_ARCH("armv8.5-a", generic_armv8_a,   V8_5A, 8,  (V8_4A, SB, 
SSBS, PREDRES, FRINTTS, FLAGM2))
 AARCH64_ARCH("armv8.6-a", generic_armv8_a,   V8_6A, 8,  (V8_5A, I8MM, 
BF16))
-AARCH64_ARCH("armv8.7-a", generic_armv8_a,   V8_7A, 8,  (V8_6A, WFXT))
+AARCH64_ARCH("armv8.7-a", generic_armv8_a,   V8_7A, 8,  (V8_6A, WFXT, 
XS))
 AARCH64_ARCH("armv8.8-a", generic_armv8_a,   V8_8A, 8,  (V8_7A, MOPS))
 AARCH64_ARCH("armv8.9-a", generic_armv8_a,   V8_9A, 8,  (V8_8A, CSSC))
 AARCH64_ARCH("armv8-r",   generic_armv8_a,   V8R  , 8,  (V8_4A))
diff --git a/gcc/config/aarch64/aarch64-option-extensions.def 
b/gcc/config/aarch64/aarch64-option-extensions.def
index d0d01f91c0fc..a1133accfce5 100644
--- a/gcc/config/aarch64/aarch64-option-extensions.def
+++ b/gcc/config/aarch64/aarch64-option-extensions.def
@@ -227,6 +227,8 @@ AARCH64_OPT_EXTENSION("ls64", LS64, (), (), (), "")
 
 AARCH64_OPT_FMV_EXTENSION("wfxt", WFXT, (), (), (), "wfxt")
 
+AARCH64_OPT_EXTENSION("xs", XS, (), (), (), "")
+
 AARCH64_OPT_EXTENSION("sme-f64f64", SME_F64F64, (SME), (), (), "smef64f64")
 
 AARCH64_FMV_FEATURE("sme-f64f64", SME_F64, (SME_F64F64))

[gcc r15-6782] aarch64: Add new +frintts flag

[Andrew Carlotti via Gcc-cvs]

https://gcc.gnu.org/g:32a45a216e63a205eed62f26c20ba919a77b025b

commit r15-6782-g32a45a216e63a205eed62f26c20ba919a77b025b
Author: Andrew Carlotti 
Date:   Tue Jul 30 18:36:22 2024 +0100

aarch64: Add new +frintts flag

gcc/ChangeLog:

* config/aarch64/aarch64-arches.def (V8_5A): Add FRINTTS
* config/aarch64/aarch64-option-extensions.def (FRINTTS): New flag.
* config/aarch64/aarch64.h (TARGET_FRINT): Use new flag.
* config/aarch64/arm_acle.h: Use new flag for frintts intrinsics.
* config/aarch64/arm_neon.h: Ditto.

gcc/testsuite/ChangeLog:

* gcc.target/aarch64/cpunative/native_cpu_21.c: Add frintts to
expected feature string.
* gcc.target/aarch64/cpunative/native_cpu_22.c: Ditto.

Diff:
---
 gcc/config/aarch64/aarch64-arches.def  | 2 +-
 gcc/config/aarch64/aarch64-option-extensions.def   | 2 ++
 gcc/config/aarch64/aarch64.h   | 2 +-
 gcc/config/aarch64/arm_acle.h  | 2 +-
 gcc/config/aarch64/arm_neon.h  | 2 +-
 gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_21.c | 2 +-
 gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_22.c | 2 +-
 7 files changed, 8 insertions(+), 6 deletions(-)

diff --git a/gcc/config/aarch64/aarch64-arches.def 
b/gcc/config/aarch64/aarch64-arches.def
index a21e5de496e9..e0f6cc21d198 100644
--- a/gcc/config/aarch64/aarch64-arches.def
+++ b/gcc/config/aarch64/aarch64-arches.def
@@ -35,7 +35,7 @@ AARCH64_ARCH("armv8.1-a", generic_armv8_a,   V8_1A, 
8,  (V8A, LSE, CRC,
 AARCH64_ARCH("armv8.2-a", generic_armv8_a,   V8_2A, 8,  (V8_1A))
 AARCH64_ARCH("armv8.3-a", generic_armv8_a,   V8_3A, 8,  (V8_2A, PAUTH, 
RCPC, FCMA, JSCVT))
 AARCH64_ARCH("armv8.4-a", generic_armv8_a,   V8_4A, 8,  (V8_3A, 
F16FML, DOTPROD, FLAGM))
-AARCH64_ARCH("armv8.5-a", generic_armv8_a,   V8_5A, 8,  (V8_4A, SB, 
SSBS, PREDRES))
+AARCH64_ARCH("armv8.5-a", generic_armv8_a,   V8_5A, 8,  (V8_4A, SB, 
SSBS, PREDRES, FRINTTS))
 AARCH64_ARCH("armv8.6-a", generic_armv8_a,   V8_6A, 8,  (V8_5A, I8MM, 
BF16))
 AARCH64_ARCH("armv8.7-a", generic_armv8_a,   V8_7A, 8,  (V8_6A))
 AARCH64_ARCH("armv8.8-a", generic_armv8_a,   V8_8A, 8,  (V8_7A, MOPS))
diff --git a/gcc/config/aarch64/aarch64-option-extensions.def 
b/gcc/config/aarch64/aarch64-option-extensions.def
index 96518ba6..9921e51c85f9 100644
--- a/gcc/config/aarch64/aarch64-option-extensions.def
+++ b/gcc/config/aarch64/aarch64-option-extensions.def
@@ -159,6 +159,8 @@ AARCH64_OPT_FMV_EXTENSION("rcpc", RCPC, (), (), (), "lrcpc")
 
 AARCH64_OPT_FMV_EXTENSION("rcpc3", RCPC3, (RCPC), (), (), "lrcpc3")
 
+AARCH64_OPT_FMV_EXTENSION("frintts", FRINTTS, (FP), (), (), "frint")
+
 AARCH64_OPT_FMV_EXTENSION("i8mm", I8MM, (SIMD), (), (), "i8mm")
 
 /* An explicit +bf16 implies +simd, but +bf16+nosimd still enables scalar BF16
diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h
index f652869625a8..1c8fcd5c582f 100644
--- a/gcc/config/aarch64/aarch64.h
+++ b/gcc/config/aarch64/aarch64.h
@@ -367,7 +367,7 @@ constexpr auto AARCH64_FL_DEFAULT_ISA_MODE ATTRIBUTE_UNUSED
 #define TARGET_COMPLEX AARCH64_HAVE_ISA (FCMA)
 
 /* Floating-point rounding instructions from Armv8.5-a.  */
-#define TARGET_FRINT (AARCH64_HAVE_ISA (V8_5A) && TARGET_FLOAT)
+#define TARGET_FRINT AARCH64_HAVE_ISA (FRINTTS)
 
 /* TME instructions are enabled.  */
 #define TARGET_TME AARCH64_HAVE_ISA (TME)
diff --git a/gcc/config/aarch64/arm_acle.h b/gcc/config/aarch64/arm_acle.h
index 985a18fba678..7976c117daf7 100644
--- a/gcc/config/aarch64/arm_acle.h
+++ b/gcc/config/aarch64/arm_acle.h
@@ -130,7 +130,7 @@ __jcvt (double __a)
 #pragma GCC pop_options
 
 #pragma GCC push_options
-#pragma GCC target ("arch=armv8.5-a")
+#pragma GCC target ("+nothing+frintts")
 __extension__ extern __inline float
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __rint32zf (float __a)
diff --git a/gcc/config/aarch64/arm_neon.h b/gcc/config/aarch64/arm_neon.h
index da145adf6749..33594cb65d28 100644
--- a/gcc/config/aarch64/arm_neon.h
+++ b/gcc/config/aarch64/arm_neon.h
@@ -27638,7 +27638,7 @@ vfmlslq_laneq_high_f16 (float32x4_t __r, float16x8_t 
__a, float16x8_t __b,
 #pragma GCC pop_options
 
 #pragma GCC push_options
-#pragma GCC target ("arch=armv8.5-a")
+#pragma GCC target ("+nothing+simd+frintts")
 
 __extension__ extern __inline float32x2_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_21.c 
b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_21.c
index 603ee48d584b..aa70d1d22b82 100644
--- a/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_21.c
+++ b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_21.c
@@ -7,7 +7,7 @@ int main()
   return 0;
 }
 
-/* { dg-final { scan-assembler {\.arc

[gcc r15-6785] aarch64: Add new +wfxt flag

[Andrew Carlotti via Gcc-cvs]

https://gcc.gnu.org/g:4984119b75e0fb8b653dd46b5d196017c90fd6a5

commit r15-6785-g4984119b75e0fb8b653dd46b5d196017c90fd6a5
Author: Andrew Carlotti 
Date:   Tue Jul 30 18:56:01 2024 +0100

aarch64: Add new +wfxt flag

GCC does not currently emit the wfet or wfit instructions, so this
primarily affects the flags passed through to the assembler.

gcc/ChangeLog:

* config/aarch64/aarch64-arches.def (V8_7A): Add WFXT.
* config/aarch64/aarch64-option-extensions.def (WFXT): New flag.

Diff:
---
 gcc/config/aarch64/aarch64-arches.def| 2 +-
 gcc/config/aarch64/aarch64-option-extensions.def | 2 ++
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/gcc/config/aarch64/aarch64-arches.def 
b/gcc/config/aarch64/aarch64-arches.def
index bcd08e21fde5..ff873a372431 100644
--- a/gcc/config/aarch64/aarch64-arches.def
+++ b/gcc/config/aarch64/aarch64-arches.def
@@ -37,7 +37,7 @@ AARCH64_ARCH("armv8.3-a", generic_armv8_a,   V8_3A, 
8,  (V8_2A, PAUTH, R
 AARCH64_ARCH("armv8.4-a", generic_armv8_a,   V8_4A, 8,  (V8_3A, 
F16FML, DOTPROD, FLAGM, RCPC2))
 AARCH64_ARCH("armv8.5-a", generic_armv8_a,   V8_5A, 8,  (V8_4A, SB, 
SSBS, PREDRES, FRINTTS, FLAGM2))
 AARCH64_ARCH("armv8.6-a", generic_armv8_a,   V8_6A, 8,  (V8_5A, I8MM, 
BF16))
-AARCH64_ARCH("armv8.7-a", generic_armv8_a,   V8_7A, 8,  (V8_6A))
+AARCH64_ARCH("armv8.7-a", generic_armv8_a,   V8_7A, 8,  (V8_6A, WFXT))
 AARCH64_ARCH("armv8.8-a", generic_armv8_a,   V8_8A, 8,  (V8_7A, MOPS))
 AARCH64_ARCH("armv8.9-a", generic_armv8_a,   V8_9A, 8,  (V8_8A, CSSC))
 AARCH64_ARCH("armv8-r",   generic_armv8_a,   V8R  , 8,  (V8_4A))
diff --git a/gcc/config/aarch64/aarch64-option-extensions.def 
b/gcc/config/aarch64/aarch64-option-extensions.def
index 3558a6ed5ad7..d0d01f91c0fc 100644
--- a/gcc/config/aarch64/aarch64-option-extensions.def
+++ b/gcc/config/aarch64/aarch64-option-extensions.def
@@ -225,6 +225,8 @@ AARCH64_OPT_EXTENSION("pauth", PAUTH, (), (), (), "paca 
pacg")
 
 AARCH64_OPT_EXTENSION("ls64", LS64, (), (), (), "")
 
+AARCH64_OPT_FMV_EXTENSION("wfxt", WFXT, (), (), (), "wfxt")
+
 AARCH64_OPT_EXTENSION("sme-f64f64", SME_F64F64, (SME), (), (), "smef64f64")
 
 AARCH64_FMV_FEATURE("sme-f64f64", SME_F64, (SME_F64F64))

[gcc r15-6787] docs: Add new AArch64 flags

[Andrew Carlotti via Gcc-cvs]

https://gcc.gnu.org/g:abbe2905eddcedf2c6247e6bb76136e850458d74

commit r15-6787-gabbe2905eddcedf2c6247e6bb76136e850458d74
Author: Andrew Carlotti 
Date:   Tue Nov 5 17:24:12 2024 +

docs: Add new AArch64 flags

gcc/ChangeLog:

* doc/invoke.texi: Add new AArch64 flags.

Diff:
---
 gcc/doc/invoke.texi | 22 ++
 1 file changed, 18 insertions(+), 4 deletions(-)

diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 17fe2c64c1f8..dd0d2b41a1a9 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -21653,11 +21653,11 @@ and the features that they enable by default:
 @item @samp{armv8-a} @tab Armv8-A @tab @samp{+fp}, @samp{+simd}
 @item @samp{armv8.1-a} @tab Armv8.1-A @tab @samp{armv8-a}, @samp{+crc}, 
@samp{+lse}, @samp{+rdma}
 @item @samp{armv8.2-a} @tab Armv8.2-A @tab @samp{armv8.1-a}
-@item @samp{armv8.3-a} @tab Armv8.3-A @tab @samp{armv8.2-a}, @samp{+pauth}
-@item @samp{armv8.4-a} @tab Armv8.4-A @tab @samp{armv8.3-a}, @samp{+flagm}, 
@samp{+fp16fml}, @samp{+dotprod}
-@item @samp{armv8.5-a} @tab Armv8.5-A @tab @samp{armv8.4-a}, @samp{+sb}, 
@samp{+ssbs}, @samp{+predres}
+@item @samp{armv8.3-a} @tab Armv8.3-A @tab @samp{armv8.2-a}, @samp{+pauth}, 
@samp{+fcma}, @samp{+jscvt}
+@item @samp{armv8.4-a} @tab Armv8.4-A @tab @samp{armv8.3-a}, @samp{+flagm}, 
@samp{+fp16fml}, @samp{+dotprod}, @samp{+rcpc2}
+@item @samp{armv8.5-a} @tab Armv8.5-A @tab @samp{armv8.4-a}, @samp{+sb}, 
@samp{+ssbs}, @samp{+predres}, @samp{+frintts}, @samp{+flagm2}
 @item @samp{armv8.6-a} @tab Armv8.6-A @tab @samp{armv8.5-a}, @samp{+bf16}, 
@samp{+i8mm}
-@item @samp{armv8.7-a} @tab Armv8.7-A @tab @samp{armv8.6-a}
+@item @samp{armv8.7-a} @tab Armv8.7-A @tab @samp{armv8.6-a}, @samp{+wfxt}, 
@samp{+xs}
 @item @samp{armv8.8-a} @tab Armv8.8-a @tab @samp{armv8.7-a}, @samp{+mops}
 @item @samp{armv8.9-a} @tab Armv8.9-a @tab @samp{armv8.8-a}
 @item @samp{armv9-a} @tab Armv9-A @tab @samp{armv8.5-a}, @samp{+sve}, 
@samp{+sve2}
@@ -21997,6 +21997,8 @@ Enable the instructions to accelerate memory operations 
like @code{memcpy},
 @option{-march=armv8.8-a}
 @item flagm
 Enable the Flag Manipulation instructions Extension.
+@item flagm2
+Enable the FlagM2 flag conversion instructions.
 @item pauth
 Enable the Pointer Authentication Extension.
 @item cssc
@@ -22020,6 +22022,16 @@ instructions.
 @item sme2p1
 Enable the Scalable Matrix Extension version 2.1.  This also enables SME2
 instructions.
+@item fcma
+Enable the complex number SIMD extensions.
+@item jscvt
+Enable the @code{fjcvtzs} JavaScript conversion instruction.
+@item frintts
+Enable floating-point round to integral value instructions.
+@item wfxt
+Enable @code{wfet} and @code{wfit} instructions.
+@item xs
+Enable the XS memory attribute extension.
 @item lse128
 Enable the LSE128 128-bit atomic instructions extension.  This also
 enables LSE instructions.
@@ -22030,6 +22042,8 @@ This also enables the LSE128 extension.
 Enable support for Armv9.4-a Guarded Control Stack extension.
 @item the
 Enable support for Armv8.9-a/9.4-a translation hardening extension.
+@item rcpc2
+Enable the RCpc2 extension.
 @item rcpc3
 Enable the RCpc3 (Release Consistency) extension.
 @item fp8

[gcc r15-6783] aarch64: Add new +flagm2 flag

[Andrew Carlotti via Gcc-cvs]

https://gcc.gnu.org/g:f5915726fd14cbf76a170338d6a91b11817e808a

commit r15-6783-gf5915726fd14cbf76a170338d6a91b11817e808a
Author: Andrew Carlotti 
Date:   Tue Jul 30 18:43:51 2024 +0100

aarch64: Add new +flagm2 flag

GCC does not currently emit the axflag or xaflag instructions, so this
primarily affects the flags passed through to the assembler.

gcc/ChangeLog:

* config/aarch64/aarch64-arches.def (V8_5A): Add FLAGM2.
* config/aarch64/aarch64-option-extensions.def (FLAGM2): New flag.

gcc/testsuite/ChangeLog:

* gcc.target/aarch64/cpunative/native_cpu_21.c: Add flagm2 to
expected feature string instead of flagm.
* gcc.target/aarch64/cpunative/native_cpu_22.c: Ditto.

Diff:
---
 gcc/config/aarch64/aarch64-arches.def  | 2 +-
 gcc/config/aarch64/aarch64-option-extensions.def   | 2 ++
 gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_21.c | 2 +-
 gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_22.c | 2 +-
 4 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/gcc/config/aarch64/aarch64-arches.def 
b/gcc/config/aarch64/aarch64-arches.def
index e0f6cc21d198..8c2aa4e477fc 100644
--- a/gcc/config/aarch64/aarch64-arches.def
+++ b/gcc/config/aarch64/aarch64-arches.def
@@ -35,7 +35,7 @@ AARCH64_ARCH("armv8.1-a", generic_armv8_a,   V8_1A, 
8,  (V8A, LSE, CRC,
 AARCH64_ARCH("armv8.2-a", generic_armv8_a,   V8_2A, 8,  (V8_1A))
 AARCH64_ARCH("armv8.3-a", generic_armv8_a,   V8_3A, 8,  (V8_2A, PAUTH, 
RCPC, FCMA, JSCVT))
 AARCH64_ARCH("armv8.4-a", generic_armv8_a,   V8_4A, 8,  (V8_3A, 
F16FML, DOTPROD, FLAGM))
-AARCH64_ARCH("armv8.5-a", generic_armv8_a,   V8_5A, 8,  (V8_4A, SB, 
SSBS, PREDRES, FRINTTS))
+AARCH64_ARCH("armv8.5-a", generic_armv8_a,   V8_5A, 8,  (V8_4A, SB, 
SSBS, PREDRES, FRINTTS, FLAGM2))
 AARCH64_ARCH("armv8.6-a", generic_armv8_a,   V8_6A, 8,  (V8_5A, I8MM, 
BF16))
 AARCH64_ARCH("armv8.7-a", generic_armv8_a,   V8_7A, 8,  (V8_6A))
 AARCH64_ARCH("armv8.8-a", generic_armv8_a,   V8_8A, 8,  (V8_7A, MOPS))
diff --git a/gcc/config/aarch64/aarch64-option-extensions.def 
b/gcc/config/aarch64/aarch64-option-extensions.def
index 9921e51c85f9..00533c38839b 100644
--- a/gcc/config/aarch64/aarch64-option-extensions.def
+++ b/gcc/config/aarch64/aarch64-option-extensions.def
@@ -103,6 +103,8 @@ AARCH64_OPT_FMV_EXTENSION("rng", RNG, (), (), (), "rng")
 
 AARCH64_OPT_FMV_EXTENSION("flagm", FLAGM, (), (), (), "flagm")
 
+AARCH64_OPT_FMV_EXTENSION("flagm2", FLAGM2, (FLAGM), (), (), "flagm2")
+
 AARCH64_OPT_FMV_EXTENSION("lse", LSE, (), (), (), "atomics")
 
 AARCH64_OPT_FMV_EXTENSION("fp", FP, (), (), (), "fp")
diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_21.c 
b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_21.c
index aa70d1d22b82..c1d5896e1eb0 100644
--- a/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_21.c
+++ b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_21.c
@@ -7,7 +7,7 @@ int main()
   return 0;
 }
 
-/* { dg-final { scan-assembler {\.arch 
armv8-a\+flagm\+lse\+dotprod\+rdma\+crc\+fp16fml\+jscvt\+rcpc\+frintts\+i8mm\+bf16\+sve2-aes\+sve2-bitperm\+sve2-sha3\+sve2-sm4\+sb\+ssbs\n}
 } } */
+/* { dg-final { scan-assembler {\.arch 
armv8-a\+flagm2\+lse\+dotprod\+rdma\+crc\+fp16fml\+jscvt\+rcpc\+frintts\+i8mm\+bf16\+sve2-aes\+sve2-bitperm\+sve2-sha3\+sve2-sm4\+sb\+ssbs\n}
 } } */
 
 /* Check that an Armv8-A core doesn't fall apart on extensions without midr
values.  */
diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_22.c 
b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_22.c
index ccd5d0d9bb7d..4533a2bf5912 100644
--- a/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_22.c
+++ b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_22.c
@@ -7,7 +7,7 @@ int main()
   return 0;
 }
 
-/* { dg-final { scan-assembler {\.arch 
armv8-a\+flagm\+lse\+dotprod\+rdma\+crc\+fp16fml\+jscvt\+rcpc\+frintts\+i8mm\+bf16\+sve2-aes\+sve2-bitperm\+sve2-sha3\+sve2-sm4\+sb\+ssbs\+pauth\n}
 } } */
+/* { dg-final { scan-assembler {\.arch 
armv8-a\+flagm2\+lse\+dotprod\+rdma\+crc\+fp16fml\+jscvt\+rcpc\+frintts\+i8mm\+bf16\+sve2-aes\+sve2-bitperm\+sve2-sha3\+sve2-sm4\+sb\+ssbs\+pauth\n}
 } } */
 
 /* Check that an Armv8-A core doesn't fall apart on extensions without midr
values and that it enables optional features.  */

[gcc r15-6779] aarch64: Use PAUTH instead of V8_3A in some places

[Andrew Carlotti via Gcc-cvs]

https://gcc.gnu.org/g:20385cb92cbd4a1934661ab97a162c1e25935836

commit r15-6779-g20385cb92cbd4a1934661ab97a162c1e25935836
Author: Andrew Carlotti 
Date:   Tue Jul 30 16:26:04 2024 +0100

aarch64: Use PAUTH instead of V8_3A in some places

gcc/ChangeLog:

* config/aarch64/aarch64.cc
(aarch64_expand_epilogue): Use TARGET_PAUTH.
* config/aarch64/aarch64.md: Update comment.

Diff:
---
 gcc/config/aarch64/aarch64.cc | 6 +++---
 gcc/config/aarch64/aarch64.md | 8 
 2 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc
index 6fe0fa2722bd..ad31e9d255c0 100644
--- a/gcc/config/aarch64/aarch64.cc
+++ b/gcc/config/aarch64/aarch64.cc
@@ -10283,12 +10283,12 @@ aarch64_expand_epilogue (rtx_call_insn *sibcall)
1) Sibcalls don't return in a normal way, so if we're about to call one
   we must authenticate.
 
-   2) The RETAA instruction is not available before ARMv8.3-A, so if we are
-  generating code for !TARGET_ARMV8_3 we can't use it and must
+   2) The RETAA instruction is not available without FEAT_PAuth, so if we
+  are generating code for !TARGET_PAUTH we can't use it and must
   explicitly authenticate.
 */
   if (aarch64_return_address_signing_enabled ()
-  && (sibcall || !TARGET_ARMV8_3))
+  && (sibcall || !TARGET_PAUTH))
 {
   switch (aarch64_ra_sign_key)
{
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index 0ed3c93b379e..44f5b7a54d25 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -7846,11 +7846,11 @@
   [(set_attr "type" "f_cvtf2i")]
 )
 
-;; Pointer authentication patterns are always provided.  In architecture
-;; revisions prior to ARMv8.3-A these HINT instructions operate as NOPs.
+;; Pointer authentication patterns are always provided.  On targets that
+;; don't implement FEAT_PAuth these HINT instructions operate as NOPs.
 ;; This lets the user write portable software which authenticates pointers
-;; when run on something which implements ARMv8.3-A, and which runs
-;; correctly, but does not authenticate pointers, where ARMv8.3-A is not
+;; when run on something which implements FEAT_PAuth, and which runs
+;; correctly, but does not authenticate pointers, where FEAT_PAuth is not
 ;; implemented.
 
 ;; Signing/Authenticating R30 using SP as the salt.

[gcc r15-6788] Disable a broken multiversioning optimisation

[Andrew Carlotti via Gcc-cvs]

https://gcc.gnu.org/g:21212f08d8258fa6d4cfdd21a35d0ee7c44ccbea

commit r15-6788-g21212f08d8258fa6d4cfdd21a35d0ee7c44ccbea
Author: Andrew Carlotti 
Date:   Tue Jan 7 18:32:23 2025 +

Disable a broken multiversioning optimisation

This patch skips redirect_to_specific clone for aarch64 and riscv,
because the optimisation has two flaws:

1. It checks the value of the "target" attribute, even on targets that
don't use this attribute for multiversioning.

2. The algorithm used is too aggressive, and will eliminate the
indirection in some cases where the runtime choice of callee version
can't be determined statically at compile time.  A correct would need to
verify that:
 - if the current caller version were selected at runtime, then the
   chosen callee version would be eligible for selection.
 - if any higher priority callee version were selected at runtime, then
   a higher priority caller version would have been eligble for
   selection (and hence the current caller version wouldn't have been
   selected).

The current checks only verify a more restrictive version of the first
condition, and don't check the second condition at all.

Fixing the optimisation properly would require implementing target hooks
to check for implications between version attributes, which is too
complicated for this stage.  However, I would like to see this hook
implemented in the future, since it could also help deduplicate other
multiversioning code.

Since this behaviour has existed for x86 and powerpc for a while, I
think it's best to preserve the existing behaviour on those targets,
unless any maintainer for those targets disagrees.

gcc/ChangeLog:

* multiple_target.cc
(redirect_to_specific_clone): Assert that "target" attribute is
used for FMV before checking it.
(ipa_target_clone): Skip redirect_to_specific_clone on some
targets.

gcc/testsuite/ChangeLog:

* g++.target/aarch64/mv-pragma.C: New test.

Diff:
---
 gcc/multiple_target.cc   | 15 +++---
 gcc/testsuite/g++.target/aarch64/mv-pragma.C | 31 
 2 files changed, 43 insertions(+), 3 deletions(-)

diff --git a/gcc/multiple_target.cc b/gcc/multiple_target.cc
index 552b9626aa71..d8becf4d9a96 100644
--- a/gcc/multiple_target.cc
+++ b/gcc/multiple_target.cc
@@ -442,7 +442,14 @@ expand_target_clones (struct cgraph_node *node, bool 
definition)
 
 /* When NODE is a target clone, consider all callees and redirect
to a clone with equal target attributes.  That prevents multiple
-   multi-versioning dispatches and a call-chain can be optimized.  */
+   multi-versioning dispatches and a call-chain can be optimized.
+
+   This optimisation might pick the wrong version in some cases, since knowing
+   that we meet the target requirements for a matching callee version does not
+   tell us that we won't also meet the target requirements for a higher
+   priority callee version at runtime.  Since this is longstanding behaviour
+   for x86 and powerpc, we preserve it for those targets, but skip the 
optimisation
+   for targets that use the "target_version" attribute for multi-versioning.  
*/
 
 static void
 redirect_to_specific_clone (cgraph_node *node)
@@ -451,6 +458,7 @@ redirect_to_specific_clone (cgraph_node *node)
   if (fv == NULL)
 return;
 
+  gcc_assert (TARGET_HAS_FMV_TARGET_ATTRIBUTE);
   tree attr_target = lookup_attribute ("target", DECL_ATTRIBUTES (node->decl));
   if (attr_target == NULL_TREE)
 return;
@@ -503,8 +511,9 @@ ipa_target_clone (void)
   for (unsigned i = 0; i < to_dispatch.length (); i++)
 create_dispatcher_calls (to_dispatch[i]);
 
-  FOR_EACH_FUNCTION (node)
-redirect_to_specific_clone (node);
+  if (TARGET_HAS_FMV_TARGET_ATTRIBUTE)
+FOR_EACH_FUNCTION (node)
+  redirect_to_specific_clone (node);
 
   return 0;
 }
diff --git a/gcc/testsuite/g++.target/aarch64/mv-pragma.C 
b/gcc/testsuite/g++.target/aarch64/mv-pragma.C
new file mode 100644
index ..545d0735438d
--- /dev/null
+++ b/gcc/testsuite/g++.target/aarch64/mv-pragma.C
@@ -0,0 +1,31 @@
+/* { dg-do compile } */
+/* { dg-require-ifunc "" } */
+/* { dg-options "-O0" } */
+
+#pragma GCC target ("+sve")
+
+__attribute__((target_version("default")))
+int foo ()
+{
+  return 1;
+}
+
+__attribute__((target_version("sve2")))
+int foo ()
+{
+  return 2;
+}
+
+__attribute__((target_version("default")))
+int bar ()
+{
+  return foo();
+}
+
+__attribute__((target_version("sha3")))
+int bar ()
+{
+  return foo() + 5;
+}
+
+/* { dg-final { scan-assembler-times "\n\tbl\t_Z3foov\n" 2 } } */

[gcc r15-6781] aarch64: Add new +jscvt flag

[Andrew Carlotti via Gcc-cvs]

https://gcc.gnu.org/g:2c8913576fa0bf234bde3c9c1f137a1b9cca95f1

commit r15-6781-g2c8913576fa0bf234bde3c9c1f137a1b9cca95f1
Author: Andrew Carlotti 
Date:   Thu Aug 1 11:54:41 2024 +0100

aarch64: Add new +jscvt flag

gcc/ChangeLog:

* config/aarch64/aarch64-arches.def (V8_3A): Add JSCVT.
* config/aarch64/aarch64-option-extensions.def (JSCVT): New flag.
* config/aarch64/aarch64.h (TARGET_JSCVT): Use new flag.
* config/aarch64/arm_acle.h: Use new flag for jscvt intrinsics.

gcc/testsuite/ChangeLog:

* gcc.target/aarch64/cpunative/native_cpu_21.c: Add jscvt to
expected feature string.
* gcc.target/aarch64/cpunative/native_cpu_22.c: Ditto.

Diff:
---
 gcc/config/aarch64/aarch64-arches.def  | 2 +-
 gcc/config/aarch64/aarch64-option-extensions.def   | 2 ++
 gcc/config/aarch64/aarch64.h   | 2 +-
 gcc/config/aarch64/arm_acle.h  | 2 +-
 gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_21.c | 2 +-
 gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_22.c | 2 +-
 6 files changed, 7 insertions(+), 5 deletions(-)

diff --git a/gcc/config/aarch64/aarch64-arches.def 
b/gcc/config/aarch64/aarch64-arches.def
index d85b14be4c3f..a21e5de496e9 100644
--- a/gcc/config/aarch64/aarch64-arches.def
+++ b/gcc/config/aarch64/aarch64-arches.def
@@ -33,7 +33,7 @@
 AARCH64_ARCH("armv8-a",   generic_armv8_a,   V8A,   8,  (SIMD))
 AARCH64_ARCH("armv8.1-a", generic_armv8_a,   V8_1A, 8,  (V8A, LSE, 
CRC, RDMA))
 AARCH64_ARCH("armv8.2-a", generic_armv8_a,   V8_2A, 8,  (V8_1A))
-AARCH64_ARCH("armv8.3-a", generic_armv8_a,   V8_3A, 8,  (V8_2A, PAUTH, 
RCPC, FCMA))
+AARCH64_ARCH("armv8.3-a", generic_armv8_a,   V8_3A, 8,  (V8_2A, PAUTH, 
RCPC, FCMA, JSCVT))
 AARCH64_ARCH("armv8.4-a", generic_armv8_a,   V8_4A, 8,  (V8_3A, 
F16FML, DOTPROD, FLAGM))
 AARCH64_ARCH("armv8.5-a", generic_armv8_a,   V8_5A, 8,  (V8_4A, SB, 
SSBS, PREDRES))
 AARCH64_ARCH("armv8.6-a", generic_armv8_a,   V8_6A, 8,  (V8_5A, I8MM, 
BF16))
diff --git a/gcc/config/aarch64/aarch64-option-extensions.def 
b/gcc/config/aarch64/aarch64-option-extensions.def
index c41c4998c5cb..96518ba6 100644
--- a/gcc/config/aarch64/aarch64-option-extensions.def
+++ b/gcc/config/aarch64/aarch64-option-extensions.def
@@ -151,6 +151,8 @@ AARCH64_OPT_EXTENSION("fp16fml", F16FML, (), (F16), (), 
"asimdfhm")
 
 AARCH64_FMV_FEATURE("fp16fml", FP16FML, (F16FML))
 
+AARCH64_OPT_FMV_EXTENSION("jscvt", JSCVT, (FP), (), (), "jscvt")
+
 AARCH64_OPT_FMV_EXTENSION("fcma", FCMA, (SIMD), (), (), "fcma")
 
 AARCH64_OPT_FMV_EXTENSION("rcpc", RCPC, (), (), (), "lrcpc")
diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h
index 250edb7d426d..f652869625a8 100644
--- a/gcc/config/aarch64/aarch64.h
+++ b/gcc/config/aarch64/aarch64.h
@@ -361,7 +361,7 @@ constexpr auto AARCH64_FL_DEFAULT_ISA_MODE ATTRIBUTE_UNUSED
 #define TARGET_ARMV8_3 AARCH64_HAVE_ISA (V8_3A)
 
 /* Javascript conversion instruction from Armv8.3-a.  */
-#define TARGET_JSCVT   (TARGET_FLOAT && TARGET_ARMV8_3)
+#define TARGET_JSCVT   AARCH64_HAVE_ISA (JSCVT)
 
 /* Armv8.3-a Complex number extension to AdvSIMD extensions.  */
 #define TARGET_COMPLEX AARCH64_HAVE_ISA (FCMA)
diff --git a/gcc/config/aarch64/arm_acle.h b/gcc/config/aarch64/arm_acle.h
index 5c3478d4ee82..985a18fba678 100644
--- a/gcc/config/aarch64/arm_acle.h
+++ b/gcc/config/aarch64/arm_acle.h
@@ -119,7 +119,7 @@ __revl (unsigned long __value)
 }
 
 #pragma GCC push_options
-#pragma GCC target ("arch=armv8.3-a")
+#pragma GCC target ("+nothing+jscvt")
 __extension__ extern __inline int32_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __jcvt (double __a)
diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_21.c 
b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_21.c
index 1d90e9ec9d97..603ee48d584b 100644
--- a/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_21.c
+++ b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_21.c
@@ -7,7 +7,7 @@ int main()
   return 0;
 }
 
-/* { dg-final { scan-assembler {\.arch 
armv8-a\+flagm\+lse\+dotprod\+rdma\+crc\+fp16fml\+rcpc\+i8mm\+bf16\+sve2-aes\+sve2-bitperm\+sve2-sha3\+sve2-sm4\+sb\+ssbs\n}
 } } */
+/* { dg-final { scan-assembler {\.arch 
armv8-a\+flagm\+lse\+dotprod\+rdma\+crc\+fp16fml\+jscvt\+rcpc\+i8mm\+bf16\+sve2-aes\+sve2-bitperm\+sve2-sha3\+sve2-sm4\+sb\+ssbs\n}
 } } */
 
 /* Check that an Armv8-A core doesn't fall apart on extensions without midr
values.  */
diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_22.c 
b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_22.c
index 17050a0b72c9..e0ba97fb6e9a 100644
--- a/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_22.c
+++ b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_22.c
@@ -7,7 +7,7 @@ int main()
   return 0;
 }
 
-/* { dg

[gcc r14-11197] Disable a broken multiversioning optimisation

[Andrew Carlotti via Gcc-cvs]

https://gcc.gnu.org/g:d0191d1631647436c4707ca6b915a46adf591d87

commit r14-11197-gd0191d1631647436c4707ca6b915a46adf591d87
Author: Andrew Carlotti 
Date:   Tue Jan 7 18:32:23 2025 +

Disable a broken multiversioning optimisation

This patch skips redirect_to_specific clone for aarch64 and riscv,
because the optimisation has two flaws:

1. It checks the value of the "target" attribute, even on targets that
don't use this attribute for multiversioning.

2. The algorithm used is too aggressive, and will eliminate the
indirection in some cases where the runtime choice of callee version
can't be determined statically at compile time.  A correct would need to
verify that:
 - if the current caller version were selected at runtime, then the
   chosen callee version would be eligible for selection.
 - if any higher priority callee version were selected at runtime, then
   a higher priority caller version would have been eligble for
   selection (and hence the current caller version wouldn't have been
   selected).

The current checks only verify a more restrictive version of the first
condition, and don't check the second condition at all.

Fixing the optimisation properly would require implementing target hooks
to check for implications between version attributes, which is too
complicated for this stage.  However, I would like to see this hook
implemented in the future, since it could also help deduplicate other
multiversioning code.

Since this behavior has existed for x86 and powerpc for a while, I
think it's best to preserve the existing behavior on those targets,
unless any maintainer for those targets disagrees.

gcc/ChangeLog:

* multiple_target.cc
(redirect_to_specific_clone): Assert that "target" attribute is
used for FMV before checking it.
(ipa_target_clone): Skip redirect_to_specific_clone on some
targets.

gcc/testsuite/ChangeLog:

* g++.target/aarch64/mv-pragma.C: New test.

Diff:
---
 gcc/multiple_target.cc   | 16 +++---
 gcc/testsuite/g++.target/aarch64/mv-pragma.C | 31 
 2 files changed, 44 insertions(+), 3 deletions(-)

diff --git a/gcc/multiple_target.cc b/gcc/multiple_target.cc
index 1fdd279da04a..60958a56c92d 100644
--- a/gcc/multiple_target.cc
+++ b/gcc/multiple_target.cc
@@ -437,7 +437,15 @@ expand_target_clones (struct cgraph_node *node, bool 
definition)
 
 /* When NODE is a target clone, consider all callees and redirect
to a clone with equal target attributes.  That prevents multiple
-   multi-versioning dispatches and a call-chain can be optimized.  */
+   multi-versioning dispatches and a call-chain can be optimized.
+
+   This optimisation might pick the wrong version in some cases, since knowing
+   that we meet the target requirements for a matching callee version does not
+   tell us that we won't also meet the target requirements for a higher
+   priority callee version at runtime.  Since this is longstanding behavior
+   for x86 and powerpc, we preserve it for those targets, but skip the
+   optimisation for targets that use the "target_version" attribute for
+   multi-versioning.  */
 
 static void
 redirect_to_specific_clone (cgraph_node *node)
@@ -446,6 +454,7 @@ redirect_to_specific_clone (cgraph_node *node)
   if (fv == NULL)
 return;
 
+  gcc_assert (TARGET_HAS_FMV_TARGET_ATTRIBUTE);
   tree attr_target = lookup_attribute ("target", DECL_ATTRIBUTES (node->decl));
   if (attr_target == NULL_TREE)
 return;
@@ -498,8 +507,9 @@ ipa_target_clone (void)
   for (unsigned i = 0; i < to_dispatch.length (); i++)
 create_dispatcher_calls (to_dispatch[i]);
 
-  FOR_EACH_FUNCTION (node)
-redirect_to_specific_clone (node);
+  if (TARGET_HAS_FMV_TARGET_ATTRIBUTE)
+FOR_EACH_FUNCTION (node)
+  redirect_to_specific_clone (node);
 
   return 0;
 }
diff --git a/gcc/testsuite/g++.target/aarch64/mv-pragma.C 
b/gcc/testsuite/g++.target/aarch64/mv-pragma.C
new file mode 100644
index ..545d0735438d
--- /dev/null
+++ b/gcc/testsuite/g++.target/aarch64/mv-pragma.C
@@ -0,0 +1,31 @@
+/* { dg-do compile } */
+/* { dg-require-ifunc "" } */
+/* { dg-options "-O0" } */
+
+#pragma GCC target ("+sve")
+
+__attribute__((target_version("default")))
+int foo ()
+{
+  return 1;
+}
+
+__attribute__((target_version("sve2")))
+int foo ()
+{
+  return 2;
+}
+
+__attribute__((target_version("default")))
+int bar ()
+{
+  return foo();
+}
+
+__attribute__((target_version("sha3")))
+int bar ()
+{
+  return foo() + 5;
+}
+
+/* { dg-final { scan-assembler-times "\n\tbl\t_Z3foov\n" 2 } } */

[gcc r15-7797] aarch64: Ignore target pragmas while defining intrinsics

[Andrew Carlotti via Gcc-cvs]

https://gcc.gnu.org/g:71355700432b15590123dc13833304c75ad8a0b6

commit r15-7797-g71355700432b15590123dc13833304c75ad8a0b6
Author: Andrew Carlotti 
Date:   Fri Feb 7 17:13:36 2025 +

aarch64: Ignore target pragmas while defining intrinsics

Refactor the switcher classes into two separate classes:

- sve_alignment_switcher takes the alignment switching functionality,
  and is used only for ABI correctness when defining sve structure
  types.
- aarch64_target_switcher takes the rest of the functionality of
  aarch64_simd_switcher and sve_switcher, and gates simd/sve specific
  parts upon the specified feature flags.

Additionally, aarch64_target_switcher now adds dependencies of the
specified flags (which adds +fcma and +bf16 to some intrinsic
declarations), and unsets current_target_pragma.

This last change fixes an internal bug where we would sometimes add a
user specified target pragma (stored in current_target_pragma) on top of
an internally specified target architecture while initialising
intrinsics with `#pragma GCC aarch64 "arm_*.h"`.  As far as I can tell, this
has no visible impact at the moment.  However, the unintended target
feature combinations lead to unwanted behaviour in an under-development
patch.

This also fixes a missing Makefile dependency, which was due to
aarch64-sve-builtins.o incorrectly depending on the undefined $(REG_H).
The correct $(REGS_H) dependency is added to the switcher's new source
location.

gcc/ChangeLog:

* common/config/aarch64/aarch64-common.cc
(struct aarch64_extension_info): Add field.
(aarch64_get_required_features): New.
* config/aarch64/aarch64-builtins.cc
(aarch64_simd_switcher::aarch64_simd_switcher): Rename to...
(aarch64_target_switcher::aarch64_target_switcher): ...this,
and extend to handle sve, nosimd and target pragmas.
(aarch64_simd_switcher::~aarch64_simd_switcher): Rename to...
(aarch64_target_switcher::~aarch64_target_switcher): ...this,
and extend to handle sve, nosimd and target pragmas.
(handle_arm_acle_h): Use aarch64_target_switcher.
(handle_arm_neon_h): Rename switcher and pass explicit flags.
(aarch64_general_init_builtins): Ditto.
* config/aarch64/aarch64-protos.h
(class aarch64_simd_switcher): Rename to...
(class aarch64_target_switcher): ...this, and add new members.
(aarch64_get_required_features): New prototype.
* config/aarch64/aarch64-sve-builtins.cc
(sve_switcher::sve_switcher): Delete
(sve_switcher::~sve_switcher): Delete
(sve_alignment_switcher::sve_alignment_switcher): New
(sve_alignment_switcher::~sve_alignment_switcher): New
(register_builtin_types): Use alignment switcher
(init_builtins): Rename switcher.
(handle_arm_neon_sve_bridge_h): Ditto.
(handle_arm_sme_h): Ditto.
(handle_arm_sve_h): Ditto, and use alignment switcher.
* config/aarch64/aarch64-sve-builtins.h
(class sve_switcher): Delete.
(class sme_switcher): Delete.
(class sve_alignment_switcher): New.
* config/aarch64/t-aarch64 (aarch64-builtins.o): Add $(REGS_H).
(aarch64-sve-builtins.o): Remove $(REG_H).

Diff:
---
 gcc/common/config/aarch64/aarch64-common.cc | 19 +++--
 gcc/config/aarch64/aarch64-builtins.cc  | 44 +
 gcc/config/aarch64/aarch64-protos.h |  9 --
 gcc/config/aarch64/aarch64-sve-builtins.cc  | 28 +++---
 gcc/config/aarch64/aarch64-sve-builtins.h   | 19 -
 gcc/config/aarch64/t-aarch64|  4 +--
 6 files changed, 74 insertions(+), 49 deletions(-)

diff --git a/gcc/common/config/aarch64/aarch64-common.cc 
b/gcc/common/config/aarch64/aarch64-common.cc
index ef4458fb6930..500bf784983d 100644
--- a/gcc/common/config/aarch64/aarch64-common.cc
+++ b/gcc/common/config/aarch64/aarch64-common.cc
@@ -157,6 +157,8 @@ struct aarch64_extension_info
   aarch64_feature_flags flags_on;
   /* If this feature is turned off, these bits also need to be turned off.  */
   aarch64_feature_flags flags_off;
+  /* If this feature remains enabled, these bits must also remain enabled.  */
+  aarch64_feature_flags flags_required;
 };
 
 /* ISA extensions in AArch64.  */
@@ -164,9 +166,10 @@ static constexpr aarch64_extension_info all_extensions[] =
 {
 #define AARCH64_OPT_EXTENSION(NAME, IDENT, C, D, E, FEATURE_STRING) \
   {NAME, AARCH64_FL_##IDENT, feature_deps::IDENT ().explicit_on, \
-   feature_deps::get_flags_off (feature_deps::root_off_##IDENT)},
+   feature_deps::get_flags_off (feature_deps::root_off_##IDENT), \
+   feature_deps::IDENT ().enable},
 #include "config/aarch64/aarch64

[gcc r15-9113] MAINTAINERS: Update my name

[Andrew Carlotti via Gcc-cvs]

https://gcc.gnu.org/g:ca354b174e6dbdd1ee14b75d5e36b7e80ab78483

commit r15-9113-gca354b174e6dbdd1ee14b75d5e36b7e80ab78483
Author: Alice Carlotti 
Date:   Mon Mar 31 22:50:23 2025 +0100

MAINTAINERS: Update my name

ChangeLog:

* MAINTAINERS: Update my name.

Diff:
---
 MAINTAINERS | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index 90c8e2aa9950..756227e0a506 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -396,7 +396,7 @@ Tobias Burnus   burnus  

 Adam Butcherabutcher
 Andrew Cagney   cagney  
 Paolo Carlini   paolo   
-Andrew Carlotti acarlotti   
+Alice Carlotti  acarlotti   
 Daniel Carrera  dcarrera
 Stephane Carrez ciceron 
 Gabriel Charettegchare