[gcc r16-1987] Add myself as an aarch64 port reviewer
https://gcc.gnu.org/g:f00023fa81e657bc7019384ec4cd773f58415d82 commit r16-1987-gf00023fa81e657bc7019384ec4cd773f58415d82 Author: Andrew Pinski Date: Thu Jul 3 09:13:59 2025 -0700 Add myself as an aarch64 port reviewer As mentioned in https://inbox.sourceware.org/gcc/ea828262-8f8f-4362-9ca8-312f7c20e...@nvidia.com/T/#m6e7e8e11656189598c759157d5d49cbd0ac9ba7c. Adding myself as an aarch64 port reviewer. ChangeLog: * MAINTAINERS: Add myself as an aarch64 port reviewer. Signed-off-by: Andrew Pinski Diff: --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index 6f663742fccc..5d5cfaa4e862 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -274,6 +274,7 @@ check in changes outside of the parts of the compiler they maintain. Reviewers +aarch64 portAndrew Pinski arm port (MVE) Christophe Lyon callgraph Martin Jambor C front end Marek Polacek
[gcc/devel/omp/gcc-15] OpenMP: Add omp_get_initial_device/omp_get_num_devices builtins: Fix test cases
https://gcc.gnu.org/g:7abb8d05c3a7ef3df5a8a477bda72ceaf0b1cd42
commit 7abb8d05c3a7ef3df5a8a477bda72ceaf0b1cd42
Author: Thomas Schwinge
Date: Thu Jul 3 14:44:21 2025 +0200
OpenMP: Add omp_get_initial_device/omp_get_num_devices builtins: Fix test
cases
With this fix-up for commit 387209938d2c476a67966c6ddbdbf817626f24a2
"OpenMP: Add omp_get_initial_device/omp_get_num_devices builtins", we
progress:
PASS: c-c++-common/gomp/omp_get_num_devices_initial_device.c (test for
excess errors)
PASS: c-c++-common/gomp/omp_get_num_devices_initial_device.c
scan-tree-dump-not optimized "abort"
-FAIL: c-c++-common/gomp/omp_get_num_devices_initial_device.c
scan-tree-dump-times optimized "omp_get_num_devices;" 1
+PASS: c-c++-common/gomp/omp_get_num_devices_initial_device.c
scan-tree-dump-times optimized "omp_get_num_devices" 1
PASS: c-c++-common/gomp/omp_get_num_devices_initial_device.c
scan-tree-dump optimized "_1 = __builtin_omp_get_num_devices \\(\\);[\\r\\n]+[
]+return _1;"
... etc. for offloading configurations.
gcc/testsuite/
* c-c++-common/gomp/omp_get_num_devices_initial_device.c: Fix.
* gfortran.dg/gomp/omp_get_num_devices_initial_device.f90: Likewise.
(cherry picked from commit 13c766066e23eb6ddf6bad7a5664b9d3ca8c1974)
Diff:
---
gcc/testsuite/c-c++-common/gomp/omp_get_num_devices_initial_device.c | 4 ++--
gcc/testsuite/gfortran.dg/gomp/omp_get_num_devices_initial_device.f90 | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git
a/gcc/testsuite/c-c++-common/gomp/omp_get_num_devices_initial_device.c
b/gcc/testsuite/c-c++-common/gomp/omp_get_num_devices_initial_device.c
index 4b17143c2829..6e2c1a8d98dc 100644
--- a/gcc/testsuite/c-c++-common/gomp/omp_get_num_devices_initial_device.c
+++ b/gcc/testsuite/c-c++-common/gomp/omp_get_num_devices_initial_device.c
@@ -25,8 +25,8 @@ int f()
/* { dg-final { scan-tree-dump-not "abort" "optimized" } } */
-/* { dg-final { scan-tree-dump-not "omp_get_num_devices;" "optimized" { target
{ ! offloading_enabled } } } } */
+/* { dg-final { scan-tree-dump-not "omp_get_num_devices" "optimized" { target
{ ! offloading_enabled } } } } */
/* { dg-final { scan-tree-dump "return 0;" "optimized" { target { !
offloading_enabled } } } } */
-/* { dg-final { scan-tree-dump-times "omp_get_num_devices;" 1 "optimized" {
target offloading_enabled } } } */
+/* { dg-final { scan-tree-dump-times "omp_get_num_devices" 1 "optimized" {
target offloading_enabled } } } */
/* { dg-final { scan-tree-dump "_1 = __builtin_omp_get_num_devices
\\(\\);\[\\r\\n\]+\[ \]+return _1;" "optimized" { target offloading_enabled } }
} */
diff --git
a/gcc/testsuite/gfortran.dg/gomp/omp_get_num_devices_initial_device.f90
b/gcc/testsuite/gfortran.dg/gomp/omp_get_num_devices_initial_device.f90
index 5409f12f4648..279656bdd840 100644
--- a/gcc/testsuite/gfortran.dg/gomp/omp_get_num_devices_initial_device.f90
+++ b/gcc/testsuite/gfortran.dg/gomp/omp_get_num_devices_initial_device.f90
@@ -17,8 +17,8 @@ end
! { dg-final { scan-tree-dump-not "error_stop" "optimized" } }
-! { dg-final { scan-tree-dump-not "omp_get_num_devices;" "optimized" { target
{ ! offloading_enabled } } } }
+! { dg-final { scan-tree-dump-not "omp_get_num_devices" "optimized" { target {
! offloading_enabled } } } }
! { dg-final { scan-tree-dump "return 0;" "optimized" { target { !
offloading_enabled } } } }
-! { dg-final { scan-tree-dump-times "omp_get_num_devices;" 1 "optimized" {
target offloading_enabled } } }
+! { dg-final { scan-tree-dump-times "omp_get_num_devices" 1 "optimized" {
target offloading_enabled } } }
! { dg-final { scan-tree-dump "_1 = __builtin_omp_get_num_devices
\\(\\);\[\\r\\n\]+\[ \]+return _1;" "optimized" { target offloading_enabled } }
}
[gcc/devel/omp/gcc-15] libgomp: Fix up omp_target_memset-3.c test for C++ [PR120444]
https://gcc.gnu.org/g:78c6033c44731e5fcb4d5453bab2f180ef7fc5d7
commit 78c6033c44731e5fcb4d5453bab2f180ef7fc5d7
Author: Jakub Jelinek
Date: Tue Jun 3 07:54:37 2025 +0200
libgomp: Fix up omp_target_memset-3.c test for C++ [PR120444]
The test PASSes for C, but FAILs for C++:
.../libgomp.c-c++-common/omp_target_memset-3.c: In function 'void
test_it(void*, int, size_t)':
.../libgomp.c-c++-common/omp_target_memset-3.c:31:7: warning: pointer of
type 'void *' used in arithmetic [-Wpointer-arith]
.../libgomp.c-c++-common/omp_target_memset-3.c:33:13: error: invalid
conversion from 'void*' to 'int8_t*' {aka 'signed char*'} [-fpermissive]
.../libgomp.c-c++-common/omp_target_memset-3.c:10:19: note: initializing
argument 1 of 'void init_val(int8_t*, int, size_t)'
.../libgomp.c-c++-common/omp_target_memset-3.c:37:14: error: invalid
conversion from 'void*' to 'int8_t*' {aka 'signed char*'} [-fpermissive]
.../libgomp.c-c++-common/omp_target_memset-3.c:17:20: note: initializing
argument 1 of 'void check_val(int8_t*, int, size_t)'
.../libgomp.c-c++-common/omp_target_memset-3.c:38:18: warning: pointer of
type 'void *' used in arithmetic [-Wpointer-arith]
.../libgomp.c-c++-common/omp_target_memset-3.c:38:18: error: invalid
conversion from 'void*' to 'int8_t*' {aka 'signed char*'} [-fpermissive]
.../libgomp.c-c++-common/omp_target_memset-3.c:17:20: note: initializing
argument 1 of 'void check_val(int8_t*, int, size_t)'
.../libgomp.c-c++-common/omp_target_memset-3.c: In function 'int main()':
.../libgomp.c-c++-common/omp_target_memset-3.c:46:7: warning: pointer of
type 'void *' used in arithmetic [-Wpointer-arith]
The following two-liner fixes that, tested on x86_64-linux and i686-linux.
2025-06-03 Jakub Jelinek
PR libgomp/120444
* testsuite/libgomp.c-c++-common/omp_target_memset-3.c (test_it):
Change ptr argument type from void * to int8_t *.
(main): Change ptr variable type from void * to int8_t * and cast
omp_target_alloc result to the latter type.
(cherry picked from commit a8c03f056f4070a618bc59afcae2290cf21456ea)
Diff:
---
libgomp/testsuite/libgomp.c-c++-common/omp_target_memset-3.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/libgomp/testsuite/libgomp.c-c++-common/omp_target_memset-3.c
b/libgomp/testsuite/libgomp.c-c++-common/omp_target_memset-3.c
index 6f2520410d13..c0e4fa905b2a 100644
--- a/libgomp/testsuite/libgomp.c-c++-common/omp_target_memset-3.c
+++ b/libgomp/testsuite/libgomp.c-c++-common/omp_target_memset-3.c
@@ -24,7 +24,7 @@ check_val (int8_t *ptr, int val, size_t count)
}
static void
-test_it (void *ptr, int lshift, size_t count)
+test_it (int8_t *ptr, int lshift, size_t count)
{
if (N < count + lshift) __builtin_abort ();
if (lshift >= 4) __builtin_abort ();
@@ -42,7 +42,7 @@ test_it (void *ptr, int lshift, size_t count)
int main()
{
size_t size;
- void *ptr = omp_target_alloc (N + 3, omp_get_default_device());
+ int8_t *ptr = (int8_t *) omp_target_alloc (N + 3, omp_get_default_device());
ptr += (4 - (uintptr_t) ptr % 4) % 4;
if ((uintptr_t) ptr % 4 != 0) __builtin_abort ();
[gcc/devel/omp/gcc-15] ChangeLog.omp bump
https://gcc.gnu.org/g:facd61f0b57f20a01d35eb8b7abeae11c2e18371 commit facd61f0b57f20a01d35eb8b7abeae11c2e18371 Author: Thomas Schwinge Date: Thu Jul 3 17:00:05 2025 +0200 ChangeLog.omp bump Diff: --- gcc/DATESTAMP.omp | 2 +- gcc/testsuite/ChangeLog.omp | 8 libgomp/ChangeLog.omp | 11 +++ 3 files changed, 20 insertions(+), 1 deletion(-) diff --git a/gcc/DATESTAMP.omp b/gcc/DATESTAMP.omp index aaa22e3d56a0..695297928f69 100644 --- a/gcc/DATESTAMP.omp +++ b/gcc/DATESTAMP.omp @@ -1 +1 @@ -20250617 +20250703 diff --git a/gcc/testsuite/ChangeLog.omp b/gcc/testsuite/ChangeLog.omp index 1684f7a388cf..a7ea0dbeb794 100644 --- a/gcc/testsuite/ChangeLog.omp +++ b/gcc/testsuite/ChangeLog.omp @@ -1,3 +1,11 @@ +2025-07-03 Thomas Schwinge + + Backported from master: + 2025-07-03 Thomas Schwinge + + * c-c++-common/gomp/omp_get_num_devices_initial_device.c: Fix. + * gfortran.dg/gomp/omp_get_num_devices_initial_device.f90: Likewise. + 2025-06-06 Tobias Burnus Backported from master: diff --git a/libgomp/ChangeLog.omp b/libgomp/ChangeLog.omp index d05b30381fbb..689cfbf963d4 100644 --- a/libgomp/ChangeLog.omp +++ b/libgomp/ChangeLog.omp @@ -1,3 +1,14 @@ +2025-07-03 Jakub Jelinek + + Backported from master: + 2025-06-03 Jakub Jelinek + + PR libgomp/120444 + * testsuite/libgomp.c-c++-common/omp_target_memset-3.c (test_it): + Change ptr argument type from void * to int8_t *. + (main): Change ptr variable type from void * to int8_t * and cast + omp_target_alloc result to the latter type. + 2025-06-17 Tobias Burnus Backported from master:
[gcc r16-1985] OpenMP: Add omp_get_initial_device/omp_get_num_devices builtins: Fix test cases
https://gcc.gnu.org/g:13c766066e23eb6ddf6bad7a5664b9d3ca8c1974
commit r16-1985-g13c766066e23eb6ddf6bad7a5664b9d3ca8c1974
Author: Thomas Schwinge
Date: Thu Jul 3 14:44:21 2025 +0200
OpenMP: Add omp_get_initial_device/omp_get_num_devices builtins: Fix test
cases
With this fix-up for commit 387209938d2c476a67966c6ddbdbf817626f24a2
"OpenMP: Add omp_get_initial_device/omp_get_num_devices builtins", we
progress:
PASS: c-c++-common/gomp/omp_get_num_devices_initial_device.c (test for
excess errors)
PASS: c-c++-common/gomp/omp_get_num_devices_initial_device.c
scan-tree-dump-not optimized "abort"
-FAIL: c-c++-common/gomp/omp_get_num_devices_initial_device.c
scan-tree-dump-times optimized "omp_get_num_devices;" 1
+PASS: c-c++-common/gomp/omp_get_num_devices_initial_device.c
scan-tree-dump-times optimized "omp_get_num_devices" 1
PASS: c-c++-common/gomp/omp_get_num_devices_initial_device.c
scan-tree-dump optimized "_1 = __builtin_omp_get_num_devices \\(\\);[\\r\\n]+[
]+return _1;"
... etc. for offloading configurations.
gcc/testsuite/
* c-c++-common/gomp/omp_get_num_devices_initial_device.c: Fix.
* gfortran.dg/gomp/omp_get_num_devices_initial_device.f90: Likewise.
Diff:
---
gcc/testsuite/c-c++-common/gomp/omp_get_num_devices_initial_device.c | 4 ++--
gcc/testsuite/gfortran.dg/gomp/omp_get_num_devices_initial_device.f90 | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git
a/gcc/testsuite/c-c++-common/gomp/omp_get_num_devices_initial_device.c
b/gcc/testsuite/c-c++-common/gomp/omp_get_num_devices_initial_device.c
index 4b17143c2829..6e2c1a8d98dc 100644
--- a/gcc/testsuite/c-c++-common/gomp/omp_get_num_devices_initial_device.c
+++ b/gcc/testsuite/c-c++-common/gomp/omp_get_num_devices_initial_device.c
@@ -25,8 +25,8 @@ int f()
/* { dg-final { scan-tree-dump-not "abort" "optimized" } } */
-/* { dg-final { scan-tree-dump-not "omp_get_num_devices;" "optimized" { target
{ ! offloading_enabled } } } } */
+/* { dg-final { scan-tree-dump-not "omp_get_num_devices" "optimized" { target
{ ! offloading_enabled } } } } */
/* { dg-final { scan-tree-dump "return 0;" "optimized" { target { !
offloading_enabled } } } } */
-/* { dg-final { scan-tree-dump-times "omp_get_num_devices;" 1 "optimized" {
target offloading_enabled } } } */
+/* { dg-final { scan-tree-dump-times "omp_get_num_devices" 1 "optimized" {
target offloading_enabled } } } */
/* { dg-final { scan-tree-dump "_1 = __builtin_omp_get_num_devices
\\(\\);\[\\r\\n\]+\[ \]+return _1;" "optimized" { target offloading_enabled } }
} */
diff --git
a/gcc/testsuite/gfortran.dg/gomp/omp_get_num_devices_initial_device.f90
b/gcc/testsuite/gfortran.dg/gomp/omp_get_num_devices_initial_device.f90
index 5409f12f4648..279656bdd840 100644
--- a/gcc/testsuite/gfortran.dg/gomp/omp_get_num_devices_initial_device.f90
+++ b/gcc/testsuite/gfortran.dg/gomp/omp_get_num_devices_initial_device.f90
@@ -17,8 +17,8 @@ end
! { dg-final { scan-tree-dump-not "error_stop" "optimized" } }
-! { dg-final { scan-tree-dump-not "omp_get_num_devices;" "optimized" { target
{ ! offloading_enabled } } } }
+! { dg-final { scan-tree-dump-not "omp_get_num_devices" "optimized" { target {
! offloading_enabled } } } }
! { dg-final { scan-tree-dump "return 0;" "optimized" { target { !
offloading_enabled } } } }
-! { dg-final { scan-tree-dump-times "omp_get_num_devices;" 1 "optimized" {
target offloading_enabled } } }
+! { dg-final { scan-tree-dump-times "omp_get_num_devices" 1 "optimized" {
target offloading_enabled } } }
! { dg-final { scan-tree-dump "_1 = __builtin_omp_get_num_devices
\\(\\);\[\\r\\n\]+\[ \]+return _1;" "optimized" { target offloading_enabled } }
}
[gcc r15-9916] c++: uninitialized TARGET_EXPR and constexpr [PR120684]
https://gcc.gnu.org/g:6b19e40f982829c460439d270d34c5c848d90c6e
commit r15-9916-g6b19e40f982829c460439d270d34c5c848d90c6e
Author: Jason Merrill
Date: Wed Jul 2 18:03:57 2025 -0400
c++: uninitialized TARGET_EXPR and constexpr [PR120684]
In r15-7532 for PR118856 I introduced a TARGET_EXPR with a
TARGET_EXPR_INITIAL of void_node to express that no initialization is done.
And indeed evaluating that doesn't store a value for the TARGET_EXPR_SLOT
variable.
But then at the end of the full-expression, destroy_value stores void_node
to express that its lifetime has ended. If we evaluate the same
full-expression again, global_ctx->values still holds the void_node, causing
confusion when we try to destroy it again. So clear out any value before
evaluating a TARGET_EXPR_INITIAL of void_type.
PR c++/120684
PR c++/118856
gcc/cp/ChangeLog:
* constexpr.cc (cxx_eval_constant_expression) [TARGET_EXPR]: Clear
the value first if is_complex.
gcc/testsuite/ChangeLog:
* g++.dg/cpp23/range-for10.C: New test.
Diff:
---
gcc/cp/constexpr.cc | 10 --
gcc/testsuite/g++.dg/cpp23/range-for10.C | 23 +++
2 files changed, 31 insertions(+), 2 deletions(-)
diff --git a/gcc/cp/constexpr.cc b/gcc/cp/constexpr.cc
index 1ed3aba0b0f8..60c0c9d35116 100644
--- a/gcc/cp/constexpr.cc
+++ b/gcc/cp/constexpr.cc
@@ -8021,14 +8021,20 @@ cxx_eval_constant_expression (const constexpr_ctx *ctx,
tree t,
ctx->global->put_value (new_ctx.object, new_ctx.ctor);
ctx = &new_ctx;
}
+
+ /* If the initializer is complex, evaluate it to initialize slot. */
+ bool is_complex = target_expr_needs_replace (t);
+ if (is_complex)
+ /* In case no initialization actually happens, clear out any
+void_node from a previous evaluation. */
+ ctx->global->put_value (slot, NULL_TREE);
+
/* Pass vc_prvalue because this indicates
initialization of a temporary. */
r = cxx_eval_constant_expression (ctx, TREE_OPERAND (t, 1), vc_prvalue,
non_constant_p, overflow_p);
if (*non_constant_p)
break;
- /* If the initializer is complex, evaluate it to initialize slot. */
- bool is_complex = target_expr_needs_replace (t);
if (!is_complex)
{
r = unshare_constructor (r);
diff --git a/gcc/testsuite/g++.dg/cpp23/range-for10.C
b/gcc/testsuite/g++.dg/cpp23/range-for10.C
new file mode 100644
index ..96eab006c327
--- /dev/null
+++ b/gcc/testsuite/g++.dg/cpp23/range-for10.C
@@ -0,0 +1,23 @@
+// PR c++/120684
+// { dg-do compile { target c++20 } }
+
+struct basic_string {
+ constexpr ~basic_string() {}
+};
+template struct lazy_split_view {
+ _Vp _M_base;
+ constexpr int* begin() { return nullptr; }
+ constexpr int* end() { return nullptr; }
+};
+constexpr void test_with_piping() {
+ basic_string input;
+ for (auto e : lazy_split_view(input))
+;
+}
+constexpr bool main_test() {
+ test_with_piping();
+ test_with_piping();
+ return true;
+}
+//int main() { main_test(); }
+static_assert(main_test());
[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Refine VX combine test case 0 to avoid code duplication
https://gcc.gnu.org/g:d683e1237df906abaa3de70896f07ef7ecd07b7a
commit d683e1237df906abaa3de70896f07ef7ecd07b7a
Author: Pan Li
Date: Sun Jun 15 16:28:38 2025 +0800
RISC-V: Refine VX combine test case 0 to avoid code duplication
The case 0 for vx combine def functions are most the same across
the different test files. Thus, re-arrange them in one place to
avoid code duplication.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c: Leverage
helper macros to avoid code duplication.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h: Add
signed and unsigned vx combine test macros.
Signed-off-by: Pan Li
(cherry picked from commit ad909d5c0ce7fcd0bcbacd0ee20c15bf479fd990)
Diff:
---
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c | 12 +--
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c | 12 +--
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c | 12 +--
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c | 12 +--
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c | 11 +-
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c | 11 +-
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c | 11 +-
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c | 11 +-
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c | 12 +--
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c | 12 +--
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c | 12 +--
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c | 12 +--
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c | 11 +-
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c | 11 +-
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c | 11 +-
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c | 11 +-
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c | 12 +--
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c | 12 +--
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c | 12 +--
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c | 12 +--
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c | 11 +-
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c | 11 +-
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c | 11 +-
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c | 11 +-
.../gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h | 25 ++
25 files changed, 49 insertions(+), 252 deletions(-)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c
index b070efdcbb20..e18a672704a2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c
@@ -5,17 +5,7 @@
#define T int16_t
-DEF_VX_BINARY_CASE_0_WRAP(T, +, add)
-DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
-DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub);
-DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
-DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
-DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
-DEF_VX_BINARY_CASE_0_WRAP(T, *, mul)
-DEF_VX_BINARY_CASE_0_WRAP(T, /, div)
-DEF_VX_BINARY_CASE_0_WRAP(T, %, rem)
-DEF_VX_BINARY_CASE_2_WRAP(T, MAX_FUNC_0_WARP(T), max)
-DEF_VX_BINARY_CASE_2_WRAP(T, MAX_FUNC_1_WARP(T), max)
+TEST_BINARY_VX_SIGNED_0(T)
/* { dg-final {
[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Combine vec_duplicate + vmin.vv to vmin.vx on GR2VR cost
https://gcc.gnu.org/g:105cb2db4ae6a5baa71a7d97fe3a011d3e0298a0
commit 105cb2db4ae6a5baa71a7d97fe3a011d3e0298a0
Author: Pan Li
Date: Tue Jun 17 10:00:54 2025 +0800
RISC-V: Combine vec_duplicate + vmin.vv to vmin.vx on GR2VR cost
This patch would like to combine the vec_duplicate + vmin.vv to the
vmin.vx. From example as below code. The related pattern will depend
on the cost of vec_duplicate from GR2VR. Then the late-combine will
take action if the cost of GR2VR is zero, and reject the combination
if the GR2VR cost is greater than zero.
Assume we have example code like below, GR2VR cost is 0.
#define DEF_VX_BINARY(T, FUNC) \
void\
test_vx_binary (T * restrict out, T * restrict in, T x, unsigned n) \
{ \
for (unsigned i = 0; i < n; i++) \
out[i] = FUNC (in[i], x); \
}
int32_t min(int32 a, int32 b)
{
return a > b ? b : a;
}
DEF_VX_BINARY(int32_t, min)
Before this patch:
10 │ test_vx_binary_or_int32_t_case_0:
11 │ beq a3,zero,.L8
12 │ vsetvli a5,zero,e32,m1,ta,ma
13 │ vmv.v.x v2,a2
14 │ sllia3,a3,32
15 │ srlia3,a3,32
16 │ .L3:
17 │ vsetvli a5,a3,e32,m1,ta,ma
18 │ vle32.v v1,0(a1)
19 │ sllia4,a5,2
20 │ sub a3,a3,a5
21 │ add a1,a1,a4
22 │ vmin.vv v1,v1,v2
23 │ vse32.v v1,0(a0)
24 │ add a0,a0,a4
25 │ bne a3,zero,.L3
After this patch:
10 │ test_vx_binary_or_int32_t_case_0:
11 │ beq a3,zero,.L8
12 │ sllia3,a3,32
13 │ srlia3,a3,32
14 │ .L3:
15 │ vsetvli a5,a3,e32,m1,ta,ma
16 │ vle32.v v1,0(a1)
17 │ sllia4,a5,2
18 │ sub a3,a3,a5
19 │ add a1,a1,a4
20 │ vmin.vx v1,v1,a2
21 │ vse32.v v1,0(a0)
22 │ add a0,a0,a4
23 │ bne a3,zero,.L3
gcc/ChangeLog:
* config/riscv/riscv-v.cc (expand_vx_binary_vec_dup_vec): Add
new case SMIN.
(expand_vx_binary_vec_vec_dup): Ditto.
* config/riscv/riscv.cc (riscv_rtx_costs): Ditto.
* config/riscv/vector-iterators.md: Add new op smin.
Signed-off-by: Pan Li
(cherry picked from commit 13c0ad1611eae7f0cd2a412b2f549a368d7d8be2)
Diff:
---
gcc/config/riscv/riscv-v.cc | 2 ++
gcc/config/riscv/riscv.cc| 1 +
gcc/config/riscv/vector-iterators.md | 4 ++--
3 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 011594966d35..a903de9280ab 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -5539,6 +5539,7 @@ expand_vx_binary_vec_dup_vec (rtx op_0, rtx op_1, rtx
op_2,
case MULT:
case SMAX:
case UMAX:
+case SMIN:
icode = code_for_pred_scalar (code, mode);
break;
case MINUS:
@@ -5575,6 +5576,7 @@ expand_vx_binary_vec_vec_dup (rtx op_0, rtx op_1, rtx
op_2,
case UMOD:
case SMAX:
case UMAX:
+case SMIN:
icode = code_for_pred_scalar (code, mode);
break;
default:
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 92f4e03c30cc..eb5349992c3f 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -3980,6 +3980,7 @@ riscv_rtx_costs (rtx x, machine_mode mode, int
outer_code, int opno ATTRIBUTE_UN
case MULT:
case SMAX:
case UMAX:
+ case SMIN:
{
rtx op;
rtx op_0 = XEXP (x, 0);
diff --git a/gcc/config/riscv/vector-iterators.md
b/gcc/config/riscv/vector-iterators.md
index 1e048c190a82..6cfa9269f935 100644
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -4042,11 +4042,11 @@
])
(define_code_iterator any_int_binop_no_shift_v_vdup [
- plus minus and ior xor mult div udiv mod umod smax umax
+ plus minus and ior xor mult div udiv mod umod smax umax smin
])
(define_code_iterator any_int_binop_no_shift_vdup_v [
- plus minus and ior xor mult smax umax
+ plus minus and ior xor mult smax umax smin
])
(define_code_iterator any_int_unop [neg not])
[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vmin.vv combine case 0 with GR2VR cost 0, 2 and 15
https://gcc.gnu.org/g:0b1f5033411fa875ac2a5438dc939fcbdfbf6f7d
commit 0b1f5033411fa875ac2a5438dc939fcbdfbf6f7d
Author: Pan Li
Date: Tue Jun 17 10:05:33 2025 +0800
RISC-V: Add test for vec_duplicate + vmin.vv combine case 0 with GR2VR cost
0, 2 and 15
Add asm dump check and run test for vec_duplicate + vmin.vv
combine to vmin.vx, with the GR2VR cost is 0, 2 and 15.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c: Add asm check.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h: Add test
helper macros.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h: Add test
data for run test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vmin-run-1-i16.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vmin-run-1-i32.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vmin-run-1-i64.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vmin-run-1-i8.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vmin-run-2-i16.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vmin-run-2-i32.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vmin-run-2-i64.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vmin-run-2-i8.c: New test.
Signed-off-by: Pan Li
(cherry picked from commit 29da9a40d1a1e21808dc596e3535058231004492)
Diff:
---
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c | 1 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c | 1 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c | 1 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c | 1 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c | 1 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c | 1 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c | 1 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c | 1 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c | 1 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c | 1 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c | 1 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c | 1 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h | 34 +++-
.../riscv/rvv/autovec/vx_vf/vx_binary_data.h | 196 +
.../riscv/rvv/autovec/vx_vf/vx_vmin-run-1-i16.c| 17 ++
.../riscv/rvv/autovec/vx_vf/vx_vmin-run-1-i32.c| 17 ++
.../riscv/rvv/autovec/vx_vf/vx_vmin-run-1-i64.c| 17 ++
.../riscv/rvv/autovec/vx_vf/vx_vmin-run-1-i8.c | 17 ++
.../riscv/rvv/autovec/vx_vf/vx_vmin-run-2-i16.c| 17 ++
.../riscv/rvv/autovec/vx_vf/vx_vmin-run-2-i32.c| 17 ++
.../riscv/rvv/autovec/vx_vf/vx_vmin-run-2-i64.c| 17 ++
.../riscv/rvv/autovec/vx_vf/vx_vmin-run-2-i8.c | 17 ++
22 files changed, 377 insertions(+), 1 deletion(-)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c
index e18a672704a2..c86d77c3d4e6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c
@@ -17,3 +17,4 @@ TEST_BINARY_VX_SIGNED_0(T)
/* { dg-final { scan-assembler-times {vdiv.vx} 1 } } */
/* { dg-final { scan-assembler-times {vrem.vx} 1 } } */
/* { dg-final { scan-assembler-times {vmax.vx} 2 } } */
+/* { dg-final { scan-assembler-times {vmin.vx} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c
index 5feec251a4cf..f6524cb8398f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c
@@ -17,3 +17,4 @@ TEST_BINARY_VX_SIGNED_0(T)
/* { dg-final { scan-assembler-times {vdiv.vx} 1 } } */
/* { dg-final { scan-assembler-times {vrem.vx} 1 } } */
/* { dg-final { scan-assembler-times {vmax.vx} 2 } } */
+/* { dg-final { scan-assembler-times {vmin.vx} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c
index 2474684aaafc..f1e8627c8d98 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec
[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vmin.vv combine case 1 with GR2VR cost 0, 1 and 2
https://gcc.gnu.org/g:f2192cd50d57966da1a538862de5b9cdc123c35b
commit f2192cd50d57966da1a538862de5b9cdc123c35b
Author: Pan Li
Date: Tue Jun 17 10:08:44 2025 +0800
RISC-V: Add test for vec_duplicate + vmin.vv combine case 1 with GR2VR cost
0, 1 and 2
Add asm dump check test for vec_duplicate + vmin.vv combine to
vmin.vx, with the GR2VR cost is 0, 1 and 2.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i16.c: Add asm check
for vmin.vx combine.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i32.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i64.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i8.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i16.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i32.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i64.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i8.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i32.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i64.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c: Ditto.
Signed-off-by: Pan Li
(cherry picked from commit a0ffc9b1bfd45da5ce676a0cef419381c021f54b)
Diff:
---
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i16.c | 3 +++
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i32.c | 3 +++
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i64.c | 3 +++
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i8.c | 3 +++
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i16.c | 3 +++
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i32.c | 3 +++
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i64.c | 3 +++
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i8.c | 3 +++
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c | 3 +++
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i32.c | 3 +++
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i64.c | 3 +++
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c | 3 +++
12 files changed, 36 insertions(+)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i16.c
index 5d684e69e134..199f8a758b44 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i16.c
@@ -16,6 +16,8 @@ DEF_VX_BINARY_CASE_1_WRAP(T, /, div, VX_BINARY_BODY_X16)
DEF_VX_BINARY_CASE_1_WRAP(T, %, rem, VX_BINARY_BODY_X16)
DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_0_WARP(T), max, VX_BINARY_FUNC_BODY_X8)
DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_1_WARP(T), max, VX_BINARY_FUNC_BODY_X8)
+DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_0_WARP(T), min, VX_BINARY_FUNC_BODY_X8)
+DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_1_WARP(T), min, VX_BINARY_FUNC_BODY_X8)
/* { dg-final { scan-assembler {vadd.vx} } } */
/* { dg-final { scan-assembler {vsub.vx} } } */
@@ -27,3 +29,4 @@ DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_1_WARP(T), max,
VX_BINARY_FUNC_BODY_X8)
/* { dg-final { scan-assembler {vdiv.vx} } } */
/* { dg-final { scan-assembler {vrem.vx} } } */
/* { dg-final { scan-assembler {vmax.vx} } } */
+/* { dg-final { scan-assembler {vmin.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i32.c
index 6c086d2bf902..392f4fe106ef 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i32.c
@@ -16,6 +16,8 @@ DEF_VX_BINARY_CASE_1_WRAP(T, /, div, VX_BINARY_BODY_X4)
DEF_VX_BINARY_CASE_1_WRAP(T, %, rem, VX_BINARY_BODY_X4)
DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_0_WARP(T), max, VX_BINARY_FUNC_BODY_X4)
DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_1_WARP(T), max, VX_BINARY_FUNC_BODY_X4)
+DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_0_WARP(T), min, VX_BINARY_FUNC_BODY_X4)
+DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_1_WARP(T), min, VX_BINARY_FUNC_BODY_X4)
/* { dg-final { scan-assembler {vadd.vx} } } */
/* { dg-final { scan-assembler {vsub.vx} } } */
@@ -27,3 +29,4 @@ DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_1_WARP(T), max,
VX_BINARY_FUNC_BODY_X4)
/* { dg-final { scan-assembler {vdiv.vx} } } */
/* { dg-final { scan-assembler {vrem.vx} } } */
/* { dg-final { scan-assembler {vmax.vx} } } */
+/* { dg-final { scan-assembler {vmin.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i64.c
index 0abae203151a..d22c3875948d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i64.c
@@ -16,6 +16,8 @@ DEF_VX_BINARY_CASE_1_WRAP(T, /, div, VX_BINARY_BODY)
DEF_VX_BINARY_CASE_1_WRAP(T, %, rem, VX_BINARY_BODY)
DEF_VX_BINARY_
[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Use riscv_2x_xlen_mode_p [NFC]
https://gcc.gnu.org/g:bff5289ba64ac8785ef1f73d3f4b30b447801da8
commit bff5289ba64ac8785ef1f73d3f4b30b447801da8
Author: Kito Cheng
Date: Tue Jun 17 13:01:01 2025 +0800
RISC-V: Use riscv_2x_xlen_mode_p [NFC]
Use riscv_v_ext_mode_p to check the mode size is 2x XLEN, instead of
using "(GET_MODE_UNIT_SIZE (mode) == (UNITS_PER_WORD * 2))".
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_legitimize_move): Use
riscv_2x_xlen_mode_p.
(riscv_binary_cost): Ditto.
(riscv_hard_regno_mode_ok): Ditto.
(cherry picked from commit c534174d4ca2fb1d2260923d47fb81609bc56e4c)
Diff:
---
gcc/config/riscv/riscv.cc | 12
1 file changed, 4 insertions(+), 8 deletions(-)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 61e181104157..6325f528560c 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -3788,10 +3788,8 @@ riscv_legitimize_move (machine_mode mode, rtx dest, rtx
src)
return true;
}
- if (TARGET_ZILSD
- && (GET_MODE_UNIT_SIZE (mode) == (UNITS_PER_WORD * 2))
- && ((REG_P (dest) && MEM_P (src))
- || (MEM_P (dest) && REG_P (src)))
+ if (TARGET_ZILSD && riscv_2x_xlen_mode_p (mode)
+ && ((REG_P (dest) && MEM_P (src)) || (MEM_P (dest) && REG_P (src)))
&& can_create_pseudo_p ())
{
rtx reg = REG_P (dest) ? dest : src;
@@ -3878,7 +3876,7 @@ static int
riscv_binary_cost (rtx x, int single_insns, int double_insns)
{
if (!riscv_v_ext_mode_p (GET_MODE (x))
- && GET_MODE_SIZE (GET_MODE (x)).to_constant () == UNITS_PER_WORD * 2)
+ && riscv_2x_xlen_mode_p (GET_MODE (x)))
return COSTS_N_INSNS (double_insns);
return COSTS_N_INSNS (single_insns);
}
@@ -10015,9 +10013,7 @@ riscv_hard_regno_mode_ok (unsigned int regno,
machine_mode mode)
return false;
/* Zilsd require load/store with even-odd reg pair. */
- if (TARGET_ZILSD
- && (GET_MODE_UNIT_SIZE (mode) == (UNITS_PER_WORD * 2))
- && ((regno % 2) != 0))
+ if (TARGET_ZILSD && riscv_2x_xlen_mode_p (mode) && ((regno % 2) != 0))
return false;
if (!GP_REG_P (regno + nregs - 1))
[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add generic tune as default.
https://gcc.gnu.org/g:209297cd3530972b8ad2e5d14c6dc96bb5d8b2ac
commit 209297cd3530972b8ad2e5d14c6dc96bb5d8b2ac
Author: Dongyan Chen
Date: Wed Jun 18 19:47:28 2025 +0800
RISC-V: Add generic tune as default.
According to the discussion in
https://gcc.gnu.org/pipermail/gcc-patches/2025-June/686893.html, by creating
a -mtune=generic may be a good idea to slove the question regarding the
branch
cost.
Changes for v2:
- Delete the code about -mcpu=generic.
gcc/ChangeLog:
* config/riscv/riscv-cores.def (RISCV_TUNE): Add "generic" tune.
* config/riscv/riscv.cc: Add generic_tune_info.
* config/riscv/riscv.h (RISCV_TUNE_STRING_DEFAULT): Change default
tune.
gcc/testsuite/ChangeLog:
*
gcc.target/riscv/zicond-primitiveSemantics_compare_reg_reg_return_reg_reg.c:
New test.
(cherry picked from commit 20f593018519fec1602dc39c08ba2e674a2d8a1c)
Diff:
---
gcc/config/riscv/riscv-cores.def | 1 +
gcc/config/riscv/riscv.cc | 23 ++
gcc/config/riscv/riscv.h | 2 +-
...itiveSemantics_compare_reg_reg_return_reg_reg.c | 21
4 files changed, 46 insertions(+), 1 deletion(-)
diff --git a/gcc/config/riscv/riscv-cores.def b/gcc/config/riscv/riscv-cores.def
index cff7c77a0bd7..2096c0095d4e 100644
--- a/gcc/config/riscv/riscv-cores.def
+++ b/gcc/config/riscv/riscv-cores.def
@@ -33,6 +33,7 @@
#define RISCV_TUNE(TUNE_NAME, PIPELINE_MODEL, TUNE_INFO)
#endif
+RISCV_TUNE("generic", generic, generic_tune_info)
RISCV_TUNE("rocket", generic, rocket_tune_info)
RISCV_TUNE("sifive-3-series", generic, rocket_tune_info)
RISCV_TUNE("sifive-5-series", generic, rocket_tune_info)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 6325f528560c..cf66e2b7a526 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -450,6 +450,29 @@ static const struct cpu_vector_cost generic_vector_cost = {
&rvv_regmove_vector_cost, /* regmove */
};
+/* Costs to use when optimizing for generic. */
+static const struct riscv_tune_param generic_tune_info = {
+ {COSTS_N_INSNS (4), COSTS_N_INSNS (5)}, /* fp_add */
+ {COSTS_N_INSNS (4), COSTS_N_INSNS (5)}, /* fp_mul */
+ {COSTS_N_INSNS (20), COSTS_N_INSNS (20)},/* fp_div */
+ {COSTS_N_INSNS (4), COSTS_N_INSNS (4)}, /* int_mul */
+ {COSTS_N_INSNS (33), COSTS_N_INSNS (65)},/* int_div */
+ 1, /* issue_rate */
+ 4, /* branch_cost */
+ 5, /* memory_cost */
+ 8, /* fmv_cost */
+ true,/*
slow_unaligned_access */
+ false, /* vector_unaligned_access */
+ false, /* use_divmod_expansion */
+ false, /* overlap_op_by_pieces */
+ false, /* speculative_sched_vsetvl */
+ RISCV_FUSE_NOTHING, /* fusible_ops */
+ NULL,/* vector cost */
+ NULL,/* function_align */
+ NULL,/* jump_align */
+ NULL,/* loop_align */
+};
+
/* Costs to use when optimizing for rocket. */
static const struct riscv_tune_param rocket_tune_info = {
{COSTS_N_INSNS (4), COSTS_N_INSNS (5)}, /* fp_add */
diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
index 2759a4cb1c9f..45fa521f219f 100644
--- a/gcc/config/riscv/riscv.h
+++ b/gcc/config/riscv/riscv.h
@@ -43,7 +43,7 @@ along with GCC; see the file COPYING3. If not see
#endif
#ifndef RISCV_TUNE_STRING_DEFAULT
-#define RISCV_TUNE_STRING_DEFAULT "rocket"
+#define RISCV_TUNE_STRING_DEFAULT "generic"
#endif
extern const char *riscv_expand_arch (int argc, const char **argv);
diff --git
a/gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_compare_reg_reg_return_reg_reg.c
b/gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_compare_reg_reg_return_reg_reg.c
new file mode 100644
index ..1ad1b77a2e65
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_compare_reg_reg_return_reg_reg.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zicond -mabi=lp64d -mtune=generic" { target {
rv64 } } } */
+/* { dg-options "-march=rv32gc_zicond -mabi=ilp32f -mtune=generic" { target {
rv32 } } } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" "-O3" } } */
+
+#define N 1
+
+int primitiveSemantics_compare_reg_reg_return_reg_reg_00(int *a, int min_v)
+{
+ int last = 0;
+
+ for (int i = 0; i < N; i++)
+ {
+if (a[i]
[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Adding cost model for zilsd
https://gcc.gnu.org/g:f6691d5f69ae5928bc6f9452fd4122101debfd41
commit f6691d5f69ae5928bc6f9452fd4122101debfd41
Author: Kito Cheng
Date: Tue Jun 17 12:56:17 2025 +0800
RISC-V: Adding cost model for zilsd
Motivation of this patch is we want to use ld/sd if possible when zilsd
is enabled, however the subreg pass may split that into two lw/sw
instructions because the cost, and it only check cost for 64 bits reg move,
that's why we need adjust cost for 64 bit reg move as well.
However even we adjust the cost model, 64 bit shift still use 32 bit
load because it already got split at expand time, this may need to fix
on the expander side, and this apparently need few more time to
investigate, so I just added a testcase with XFAIL to show the current
behavior,
and we can fix that...when we have time.
For long term, we may adding a new field to riscv_tune_param to control
the cost model for that.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_cost_model): Add cost model for
zilsd.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/zilsd-code-gen-split-subreg-1.c: New test.
* gcc.target/riscv/zilsd-code-gen-split-subreg-2.c: New test.
(cherry picked from commit 36b3488034929c2ff02c6a4a1946ea81376200a4)
Diff:
---
gcc/config/riscv/riscv.cc | 41 ++
.../riscv/zilsd-code-gen-split-subreg-1.c | 12 +++
.../riscv/zilsd-code-gen-split-subreg-2.c | 16 +
3 files changed, 69 insertions(+)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index eb5349992c3f..61e181104157 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -814,6 +814,16 @@ void riscv_frame_info::reset(void)
arg_pointer_offset = 0;
}
+/* Check if the mode is twice the size of the XLEN mode. */
+
+static bool
+riscv_2x_xlen_mode_p (machine_mode mode)
+{
+ poly_int64 mode_size = GET_MODE_SIZE (mode);
+ return mode_size.is_constant ()
+&& (mode_size.to_constant () == UNITS_PER_WORD * 2);
+}
+
/* Implement TARGET_MIN_ARITHMETIC_PRECISION. */
static unsigned int
@@ -4023,10 +4033,41 @@ riscv_rtx_costs (rtx x, machine_mode mode, int
outer_code, int opno ATTRIBUTE_UN
*total = COSTS_N_INSNS (1);
return true;
}
+
+ /* Register move for XLEN * 2. */
+ if (TARGET_ZILSD
+ && register_operand (SET_SRC (x), GET_MODE (SET_SRC (x)))
+ && riscv_2x_xlen_mode_p (mode))
+ {
+ /* We still need two instruction for move with ZILSD,
+but let minus one cost to let subreg split don't.
+TODO: Add riscv_tune_param for this. */
+ *total = COSTS_N_INSNS (2) - 1;
+ return true;
+ }
+
+ /* Load for XLEN * 2. */
+ if (TARGET_ZILSD && MEM_P (SET_SRC (x))
+ && riscv_2x_xlen_mode_p (mode))
+ {
+ /* TODO: Add riscv_tune_param for this. */
+ *total = COSTS_N_INSNS (1);
+ return true;
+ }
+
riscv_rtx_costs (SET_SRC (x), mode, SET, opno, total, speed);
return true;
}
+ /* Store for XLEN * 2. */
+ if (TARGET_ZILSD && MEM_P (SET_DEST (x)) && REG_P (SET_SRC (x))
+ && riscv_2x_xlen_mode_p (mode))
+ {
+ /* TODO: Add riscv_tune_param for this. */
+ *total = COSTS_N_INSNS (1);
+ return true;
+ }
+
/* Otherwise return FALSE indicating we should recurse into both the
SET_DEST and SET_SRC combining the cost of both. */
return false;
diff --git a/gcc/testsuite/gcc.target/riscv/zilsd-code-gen-split-subreg-1.c
b/gcc/testsuite/gcc.target/riscv/zilsd-code-gen-split-subreg-1.c
new file mode 100644
index ..36026269c13a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zilsd-code-gen-split-subreg-1.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32i_zilsd -mabi=ilp32" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+long long y;
+long long foo(long long x)
+{
+return y + x;
+}
+
+/* { dg-final { scan-assembler-times "ld\t" 1 } } */
+/* { dg-final { scan-assembler-not "lw\t" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/zilsd-code-gen-split-subreg-2.c
b/gcc/testsuite/gcc.target/riscv/zilsd-code-gen-split-subreg-2.c
new file mode 100644
index ..3adcd21ea061
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zilsd-code-gen-split-subreg-2.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32i_zilsd -mabi=ilp32" } */
+
+long long y;
+long long foo(long long x)
+{
+return y >> x;
+}
+/* TODO: We should not split that 64 bit load into two 32 bit load if we have
+ zilsd, but we split that during the expand time, so it's hard to fix via
cost
+ model turning, we could either fix that for expander,
[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Combine vec_duplicate + vminu.vv to vminu.vx on GR2VR cost
https://gcc.gnu.org/g:d384bfb5ecc16e2d25adc43a6ef451c983dac7df
commit d384bfb5ecc16e2d25adc43a6ef451c983dac7df
Author: Pan Li
Date: Thu Jun 19 10:44:14 2025 +0800
RISC-V: Combine vec_duplicate + vminu.vv to vminu.vx on GR2VR cost
This patch would like to combine the vec_duplicate + vminu.vv to the
vminu.vx. From example as below code. The related pattern will depend
on the cost of vec_duplicate from GR2VR. Then the late-combine will
take action if the cost of GR2VR is zero, and reject the combination
if the GR2VR cost is greater than zero.
Assume we have example code like below, GR2VR cost is 0.
#define DEF_VX_BINARY(T, FUNC) \
void\
test_vx_binary (T * restrict out, T * restrict in, T x, unsigned n) \
{ \
for (unsigned i = 0; i < n; i++) \
out[i] = FUNC (in[i], x); \
}
uint32_t min(uint32 a, uint32 b)
{
return a > b ? b : a;
}
DEF_VX_BINARY(uint32_t, min)
Before this patch:
10 │ test_vx_binary_or_int32_t_case_0:
11 │ beq a3,zero,.L8
12 │ vsetvli a5,zero,e32,m1,ta,ma
13 │ vmv.v.x v2,a2
14 │ sllia3,a3,32
15 │ srlia3,a3,32
16 │ .L3:
17 │ vsetvli a5,a3,e32,m1,ta,ma
18 │ vle32.v v1,0(a1)
19 │ sllia4,a5,2
20 │ sub a3,a3,a5
21 │ add a1,a1,a4
22 │ vminu.vv v1,v1,v2
23 │ vse32.v v1,0(a0)
24 │ add a0,a0,a4
25 │ bne a3,zero,.L3
After this patch:
10 │ test_vx_binary_or_int32_t_case_0:
11 │ beq a3,zero,.L8
12 │ sllia3,a3,32
13 │ srlia3,a3,32
14 │ .L3:
15 │ vsetvli a5,a3,e32,m1,ta,ma
16 │ vle32.v v1,0(a1)
17 │ sllia4,a5,2
18 │ sub a3,a3,a5
19 │ add a1,a1,a4
20 │ vminu.vx v1,v1,a2
21 │ vse32.v v1,0(a0)
22 │ add a0,a0,a4
23 │ bne a3,zero,.L3
gcc/ChangeLog:
* config/riscv/riscv-v.cc (expand_vx_binary_vec_dup_vec): Add
new case UMIN.
(expand_vx_binary_vec_vec_dup): Ditto.
* config/riscv/riscv.cc (riscv_rtx_costs): Ditto.
* config/riscv/vector-iterators.md: Add new op umin.
Signed-off-by: Pan Li
(cherry picked from commit 7ea9105f2609efe089461d7e92533324eb5b1103)
Diff:
---
gcc/config/riscv/riscv-v.cc | 2 ++
gcc/config/riscv/riscv.cc| 1 +
gcc/config/riscv/vector-iterators.md | 4 ++--
3 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index a903de9280ab..ac690df3688a 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -5540,6 +5540,7 @@ expand_vx_binary_vec_dup_vec (rtx op_0, rtx op_1, rtx
op_2,
case SMAX:
case UMAX:
case SMIN:
+case UMIN:
icode = code_for_pred_scalar (code, mode);
break;
case MINUS:
@@ -5577,6 +5578,7 @@ expand_vx_binary_vec_vec_dup (rtx op_0, rtx op_1, rtx
op_2,
case SMAX:
case UMAX:
case SMIN:
+case UMIN:
icode = code_for_pred_scalar (code, mode);
break;
default:
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index cf66e2b7a526..adbfe9de29c0 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -4012,6 +4012,7 @@ riscv_rtx_costs (rtx x, machine_mode mode, int
outer_code, int opno ATTRIBUTE_UN
case SMAX:
case UMAX:
case SMIN:
+ case UMIN:
{
rtx op;
rtx op_0 = XEXP (x, 0);
diff --git a/gcc/config/riscv/vector-iterators.md
b/gcc/config/riscv/vector-iterators.md
index 6cfa9269f935..44ae79c48aa7 100644
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -4042,11 +4042,11 @@
])
(define_code_iterator any_int_binop_no_shift_v_vdup [
- plus minus and ior xor mult div udiv mod umod smax umax smin
+ plus minus and ior xor mult div udiv mod umod smax umax smin umin
])
(define_code_iterator any_int_binop_no_shift_vdup_v [
- plus minus and ior xor mult smax umax smin
+ plus minus and ior xor mult smax umax smin umin
])
(define_code_iterator any_int_unop [neg not])
[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add -fno-pie flags to testcases
https://gcc.gnu.org/g:b11a59c708d6b35aeb5995695e2bd53f8b341461
commit b11a59c708d6b35aeb5995695e2bd53f8b341461
Author: Kito Cheng
Date: Tue Jun 17 12:52:00 2025 +0800
RISC-V: Add -fno-pie flags to testcases
PIE may cause some code gen difference in the testcases, that will cause
problem when we configure toolchain with `--enable-default-pie`.
So adding -fno-pie flags to the testcases to avoid this issue.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/jump-table-large-code-model.c: Adding
-fno-pie.
* gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv-nofm.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv-nofm.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv-nofm.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv-nofm.c: Ditto.
(cherry picked from commit 6a17361496afbef5a095b9d5f26642cc8465fa31)
Diff:
---
gcc/testsuite/gcc.target/riscv/jump-table-large-code-model.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv-nofm.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv-nofm.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv-nofm.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv-nofm.c | 2 +-
5 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/gcc/testsuite/gcc.target/riscv/jump-table-large-code-model.c
b/gcc/testsuite/gcc.target/riscv/jump-table-large-code-model.c
index 1ee7f6c07d3d..ab97b0fc0bb8 100644
--- a/gcc/testsuite/gcc.target/riscv/jump-table-large-code-model.c
+++ b/gcc/testsuite/gcc.target/riscv/jump-table-large-code-model.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gc -mabi=lp64 -mcmodel=large" } */
+/* { dg-options "-march=rv64gc -mabi=lp64 -mcmodel=large -fno-pie" } */
int foo(int x, int y)
{
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv-nofm.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv-nofm.c
index 667f457d6584..fab8e79fe723 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv-nofm.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv-nofm.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh
-mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh
-mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details -fno-pie"
} */
#include "vadd-template.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv-nofm.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv-nofm.c
index 1d8a19ce0b2d..80bdb683ad0a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv-nofm.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv-nofm.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh
-mabi=lp64d -mrvv-vector-bits=scalable -fdump-tree-optimized-details" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh
-mabi=lp64d -mrvv-vector-bits=scalable -fdump-tree-optimized-details -fno-pie"
} */
#include "vadd-template.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv-nofm.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv-nofm.c
index 1b6d50ed3bc0..28b923599ea9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv-nofm.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv-nofm.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh
-mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh
-mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details -fno-pie"
} */
#include "vsub-template.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv-nofm.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv-nofm.c
index 0b22e9ad2905..b0489493b049 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv-nofm.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv-nofm.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh
-mabi=lp64d -mrvv-vector-bits=scalable -fdump-tree-optimized-details" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh
-mabi=lp64d -mrvv-vector-bits=scalable -fdump-tree-optimized-details -fno-pie"
} */
#include "vsub-template.h"
[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [PATCH v1] RISC-V: Use scratch reg for loop control
https://gcc.gnu.org/g:e2f93299f84df050dfcd9a644eb6faed87c79fc6
commit e2f93299f84df050dfcd9a644eb6faed87c79fc6
Author: Umesh Kalappa
Date: Tue Jun 17 07:23:41 2025 -0600
[PATCH v1] RISC-V: Use scratch reg for loop control
By using the scratch register for loop control rather than the output
of the lr instruction we can avoid an unnecessary "mv" instruction.
--
V2: Testcase update with no regressions found for the following the changes.
gcc/ChangeLog:
* config/riscv/sync.md (lrsc_atomic_exchange): Use scratch
register for loop control rather than lr output.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/zalrsc.c: New test.
(cherry picked from commit a22ed5658797cc9ca4421e69db5d6259389a4156)
Diff:
---
gcc/config/riscv/sync.md| 11 +--
gcc/testsuite/gcc.target/riscv/zalrsc.c | 14 ++
2 files changed, 19 insertions(+), 6 deletions(-)
diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md
index 726800a96623..a75ea6834e46 100644
--- a/gcc/config/riscv/sync.md
+++ b/gcc/config/riscv/sync.md
@@ -405,18 +405,17 @@
(match_operand:SI 3 "const_int_operand")] ;; model
UNSPEC_SYNC_EXCHANGE))
(set (match_dup 1)
- (match_operand:GPR 2 "register_operand" "0"))
+ (match_operand:GPR 2 "reg_or_0_operand" "rJ"))
(clobber (match_scratch:GPR 4 "=&r"))];; tmp_1
"!TARGET_ZAAMO && TARGET_ZALRSC"
{
return "1:\;"
- "lr.%I3\t%4, %1\;"
- "sc.%J3\t%0, %0, %1\;"
- "bnez\t%0, 1b\;"
- "mv\t%0, %4";
+ "lr.%I3\t%0, %1\;"
+ "sc.%J3\t%4, %z2, %1\;"
+ "bnez\t%4, 1b\";
}
[(set_attr "type" "atomic")
- (set (attr "length") (const_int 16))])
+ (set (attr "length") (const_int 12))])
(define_expand "atomic_exchange"
[(match_operand:SHORT 0 "register_operand") ;; old value at mem
diff --git a/gcc/testsuite/gcc.target/riscv/zalrsc.c
b/gcc/testsuite/gcc.target/riscv/zalrsc.c
new file mode 100644
index ..19a26bfb47ce
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zalrsc.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64imfd_zalrsc -mabi=lp64" } */
+/* { dg-skip-if "" { *-*-* } {"-O0"} } */
+
+/* lr.w/sc.w */
+int *i;
+int lr_sc(int v)
+{
+ return __atomic_exchange_4(i, v, __ATOMIC_RELAXED);
+}
+
+/* { dg-final { scan-assembler-times {\mlr.w} 1 } } */
+/* { dg-final { scan-assembler-times {\msc.w} 1 } } */
+/* { dg-final { scan-assembler-not {"mv\t"} } } */
[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [committed][PR rtl-optimization/120550] Drop REG_EQUAL note after ext-dce transformation
https://gcc.gnu.org/g:4e879da55a35790c1c75fa71328bc0425fd5898c
commit 4e879da55a35790c1c75fa71328bc0425fd5898c
Author: Jeff Law
Date: Sun Jun 22 12:06:08 2025 -0600
[committed][PR rtl-optimization/120550] Drop REG_EQUAL note after ext-dce
transformation
This bug was found by Edwin's fuzzing efforts on RISC-V, though it likely
affects other targets.
In simplest terms when ext-dce converts an extension into a (possibly
simplified) subreg copy it may make an attached REG_EQUAL note invalid.
In the case Edwin found the note was an extension, but I don't think that
would
necessarily always be the case. The note could have other forms which
potentially need invalidation. So the safest thing to do is just remove any
attached REG_EQUAL or REG_EQUIV note.
Note adjusting Edwin's testcase in the obvious way to avoid having to
interpret
printf output for pass/fail status makes the bug go latent. That's why no
testcase is included with this patch.
Bootstrapped and regression tested on x86_64. Obviously also verified it
fixes
the testcase Edwin filed.
This is a good candidate for cherry-picking to the gcc-15 release branch
after
simmering on the trunk a bit.
PR rtl-optimization/120550
gcc/
* ext-dce.cc (ext_dce_try_optimize_insn): Drop REG_EQUAL/REG_EQUIV
notes on modified insns.
(cherry picked from commit 34e1e5e33ec3eb475c0c8278800b6fc246a86763)
Diff:
---
gcc/ext-dce.cc | 5 +
1 file changed, 5 insertions(+)
diff --git a/gcc/ext-dce.cc b/gcc/ext-dce.cc
index a03439501419..b5ccc1896494 100644
--- a/gcc/ext-dce.cc
+++ b/gcc/ext-dce.cc
@@ -441,6 +441,11 @@ ext_dce_try_optimize_insn (rtx_insn *insn, rtx set)
print_rtl_single (dump_file, new_pattern);
fprintf (dump_file, "\n");
}
+
+ /* INSN may have a REG_EQUAL note indicating that the value was
+sign or zero extended. That note is no longer valid since we've
+just removed the extension. Just wipe the notes. */
+ remove_reg_equal_equiv_notes (insn, true);
}
else
{
[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vminu.vv combine case 0 with GR2VR cost 0, 2 and 15
https://gcc.gnu.org/g:dddb4eaa80d2500c920e58b80d7aa0bbba9107f8
commit dddb4eaa80d2500c920e58b80d7aa0bbba9107f8
Author: Pan Li
Date: Thu Jun 19 10:47:33 2025 +0800
RISC-V: Add test for vec_duplicate + vminu.vv combine case 0 with GR2VR
cost 0, 2 and 15
Add asm dump check and run test for vec_duplicate + vminu.vv
combine to vminu.vx, with the GR2VR cost is 0, 2 and 15.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c: Add asm check.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h: Add test
helper macors.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h: Add
test data for run test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vmin-run-1-u16.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vmin-run-1-u32.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vmin-run-1-u64.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vmin-run-1-u8.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vmin-run-2-u16.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vmin-run-2-u32.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vmin-run-2-u64.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vmin-run-2-u8.c: New test.
Signed-off-by: Pan Li
(cherry picked from commit 289220af97f712d253d0b9d649e57e7da3dd37ea)
Diff:
---
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c | 1 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c | 1 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c | 1 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c | 1 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c | 1 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c | 1 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c | 1 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c | 1 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c | 1 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c | 1 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c | 1 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c | 1 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h | 14 +-
.../riscv/rvv/autovec/vx_vf/vx_binary_data.h | 196 +
.../riscv/rvv/autovec/vx_vf/vx_vmin-run-1-u16.c| 17 ++
.../riscv/rvv/autovec/vx_vf/vx_vmin-run-1-u32.c| 17 ++
.../riscv/rvv/autovec/vx_vf/vx_vmin-run-1-u64.c| 17 ++
.../riscv/rvv/autovec/vx_vf/vx_vmin-run-1-u8.c | 17 ++
.../riscv/rvv/autovec/vx_vf/vx_vmin-run-2-u16.c| 17 ++
.../riscv/rvv/autovec/vx_vf/vx_vmin-run-2-u32.c| 17 ++
.../riscv/rvv/autovec/vx_vf/vx_vmin-run-2-u64.c| 17 ++
.../riscv/rvv/autovec/vx_vf/vx_vmin-run-2-u8.c | 17 ++
22 files changed, 357 insertions(+), 1 deletion(-)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c
index e06829d621d5..bcfd5145d24f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c
@@ -16,3 +16,4 @@ TEST_BINARY_VX_UNSIGNED_0(T)
/* { dg-final { scan-assembler-times {vdivu.vx} 1 } } */
/* { dg-final { scan-assembler-times {vremu.vx} 1 } } */
/* { dg-final { scan-assembler-times {vmaxu.vx} 2 } } */
+/* { dg-final { scan-assembler-times {vminu.vx} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c
index 05fb829a87e0..b9a6a2830916 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c
@@ -16,3 +16,4 @@ TEST_BINARY_VX_UNSIGNED_0(T)
/* { dg-final { scan-assembler-times {vdivu.vx} 1 } } */
/* { dg-final { scan-assembler-times {vremu.vx} 1 } } */
/* { dg-final { scan-assembler-times {vmaxu.vx} 2 } } */
+/* { dg-final { scan-assembler-times {vminu.vx} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c
index 4681f36cd4b1..abb5e5e78428 100644
--- a/gcc/testsuite/gcc.target/risc
[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [RISC-V] Force several tests to use rocket tuning
https://gcc.gnu.org/g:1db0924426c7e2f1c2692079855a1999179a3f6b
commit 1db0924426c7e2f1c2692079855a1999179a3f6b
Author: Jeff Law
Date: Thu Jun 19 20:58:56 2025 -0600
[RISC-V] Force several tests to use rocket tuning
My tester has been flagging these regressions since the default cost model
was
committed, along with several others
> unix/-march=rv64gc_zba_zbb_zbs_zicond: gcc:
gcc.target/riscv/rvv/vsetvl/avl_single-37.c -O2 scan-assembler-times
\\.L[0-9]+\\:\\s+addi\\s+\\s*[a-x0-9]+,\\s*[a-x0-9]+,\\s*[0-9]00\\s+addi\\s+\\s*[a-x0-9]+,\\s*[a-x0-9]+,\\s*[0-9]00\\s+addi\\s+\\s*[a-x0-9]+,\\s*[a-x0-9]+,\\s*[0-9]00\\s+add\\s+\\s*[a-x0-9]+,\\s*[a-x0-9]+,\\s*[a-x0-9]+\\s+\\.L[0-9]+\\:
1
> unix/-march=rv64gc_zba_zbb_zbs_zicond: gcc:
gcc.target/riscv/rvv/vsetvl/avl_single-37.c -O2 -flto -fno-use-linker-plugin
-flto-partition=none scan-assembler-times
\\.L[0-9]+\\:\\s+addi\\s+\\s*[a-x0-9]+,\\s*[a-x0-9]+,\\s*[0-9]00\\s+addi\\s+\\s*[a-x0-9]+,\\s*[a-x0-9]+,\\s*[0-9]00\\s+addi\\s+\\s*[a-x0-9]+,\\s*[a-x0-9]+,\\s*[0-9]00\\s+add\\s+\\s*[a-x0-9]+,\\s*[a-x0-9]+,\\s*[a-x0-9]+\\s+\\.L[0-9]+\\:
1
> unix/-march=rv64gc_zba_zbb_zbs_zicond: gcc:
gcc.target/riscv/rvv/vsetvl/avl_single-37.c -O2 -flto -fuse-linker-plugin
-fno-fat-lto-objects scan-assembler-times
\\.L[0-9]+\\:\\s+addi\\s+\\s*[a-x0-9]+,\\s*[a-x0-9]+,\\s*[0-9]00\\s+addi\\s+\\s*[a-x0-9]+,\\s*[a-x0-9]+,\\s*[0-9]00\\s+addi\\s+\\s*[a-x0-9]+,\\s*[a-x0-9]+,\\s*[0-9]00\\s+add\\s+\\s*[a-x0-9]+,\\s*[a-x0-9]+,\\s*[a-x0-9]+\\s+\\.L[0-9]+\\:
1
I really question the value of checking the output that precisely in these
tests -- they're supposed to be checking vsetvl correctness and
optimization,
so the ordering and such of scalar ops shouldn't really be important at all.
Regardless, since I don't know these tests at all I resisted the temptation
to
rip out the undesirable aspects of the test.
Next up, fix the bogus scan or force the old cost model (rocket). I choose
the
latter as a path of least resistance and least surprise.
Waiting for pre-commit CI to spin.
gcc/testsuite
* gcc.target/riscv/rvv/vsetvl/avl_single-37.c: Force rocket tuning.
* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-17.c: Likewise.
* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-18.c: Likewise.
* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-19.c: Likewise.
* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-20.c: Likewise.
(cherry picked from commit c59cea256ad3eaf34298bb9ce947af89bbc7331f)
Diff:
---
gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-37.c| 2 +-
gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-17.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-18.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-19.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-20.c | 2 +-
5 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-37.c
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-37.c
index cd3e961cefe1..9bade063f17e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-37.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-37.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32
-fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32
-fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -mtune=rocket" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-17.c
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-17.c
index d7f6d18d1d61..321eb3b9f298 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-17.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-17.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32
-fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32
-fno-tree-vectorize -mtune=rocket" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-18.c
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-18.c
index 1354c5e46d02..29dcfefbd0cf 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-18.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-18.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32
-fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32
-fno-tree-vectorize -mtune=rocket" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-19.c
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-1
[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Fix ICE for expand_select_vldi [PR120652]
https://gcc.gnu.org/g:44ac6ec10ded179bc9794fb019b8280658c4e7fb
commit 44ac6ec10ded179bc9794fb019b8280658c4e7fb
Author: Pan Li
Date: Thu Jun 19 18:58:17 2025 +0800
RISC-V: Fix ICE for expand_select_vldi [PR120652]
The will be one ICE when expand pass, the bt similar as below.
during RTL pass: expand
red.c: In function 'main':
red.c:20:5: internal compiler error: in require, at machmode.h:323
20 | int main() {
| ^~~~
0x2e0b1d6 internal_error(char const*, ...)
../../../gcc/gcc/diagnostic-global-context.cc:517
0xd0d3ed fancy_abort(char const*, int, char const*)
../../../gcc/gcc/diagnostic.cc:1803
0xc3da74 opt_mode::require() const
../../../gcc/gcc/machmode.h:323
0xc3de2f opt_mode::require() const
../../../gcc/gcc/poly-int.h:1383
0xc3de2f riscv_vector::expand_select_vl(rtx_def**)
../../../gcc/gcc/config/riscv/riscv-v.cc:4218
0x21c7d22 gen_select_vldi(rtx_def*, rtx_def*, rtx_def*)
../../../gcc/gcc/config/riscv/autovec.md:1344
0x134db6c maybe_expand_insn(insn_code, unsigned int, expand_operand*)
../../../gcc/gcc/optabs.cc:8257
0x134db6c expand_insn(insn_code, unsigned int, expand_operand*)
../../../gcc/gcc/optabs.cc:8288
0x11b21d3 expand_fn_using_insn
../../../gcc/gcc/internal-fn.cc:318
0xef32cf expand_call_stmt
../../../gcc/gcc/cfgexpand.cc:3097
0xef32cf expand_gimple_stmt_1
../../../gcc/gcc/cfgexpand.cc:4264
0xef32cf expand_gimple_stmt
../../../gcc/gcc/cfgexpand.cc:4411
0xef95b6 expand_gimple_basic_block
../../../gcc/gcc/cfgexpand.cc:6472
0xefb66f execute
../../../gcc/gcc/cfgexpand.cc:7223
The select_vl op_1 and op_2 may be the same const_int like (const_int 32).
And then maybe_legitimize_operands will:
1. First mov the const op_1 to a reg.
2. Resue the reg of op_1 for op_2 as the op_1 and op_2 is equal.
That will break the assumption that the op_2 of select_vl is immediate,
or something like CONST_INT_POLY.
The below test suites are passed for this patch series.
* The rv64gcv fully regression test.
PR target/120652
gcc/ChangeLog:
* config/riscv/autovec.md: Add immediate_operand for
select_vl operand 2.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/pr120652-1.c: New test.
* gcc.target/riscv/rvv/autovec/pr120652-2.c: New test.
* gcc.target/riscv/rvv/autovec/pr120652-3.c: New test.
* gcc.target/riscv/rvv/autovec/pr120652.h: New test.
Signed-off-by: Pan Li
(cherry picked from commit 52582b40a9bf839ae3771de1557ce6691eb8eedd)
Diff:
---
gcc/config/riscv/autovec.md| 2 +-
.../gcc.target/riscv/rvv/autovec/pr120652-1.c | 5
.../gcc.target/riscv/rvv/autovec/pr120652-2.c | 5
.../gcc.target/riscv/rvv/autovec/pr120652-3.c | 5
.../gcc.target/riscv/rvv/autovec/pr120652.h| 31 ++
5 files changed, 47 insertions(+), 1 deletion(-)
diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index c678eefc7003..94a61bdc5cf5 100644
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -1338,7 +1338,7 @@
(define_expand "select_vl"
[(match_operand:P 0 "register_operand")
(match_operand:P 1 "vector_length_operand")
- (match_operand:P 2 "")]
+ (match_operand:P 2 "immediate_operand")]
"TARGET_VECTOR"
{
riscv_vector::expand_select_vl (operands);
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr120652-1.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr120652-1.c
new file mode 100644
index ..260e4c08f16f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr120652-1.c
@@ -0,0 +1,5 @@
+/* Test that we do not have ice when compile */
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zvl256b -mabi=lp64d -O3" } */
+
+#include "pr120652.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr120652-2.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr120652-2.c
new file mode 100644
index ..6f8594267662
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr120652-2.c
@@ -0,0 +1,5 @@
+/* Test that we do not have ice when compile */
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zvl512b -mabi=lp64d -O3" } */
+
+#include "pr120652.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr120652-3.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr120652-3.c
new file mode 100644
index ..9852b5de86a4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr120652-3.c
@@ -0,0 +1,5 @@
+/* Test that we do not have ice when compile */
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zvl1024b -mabi=lp64d -O3" } */
+
+#include "pr120652.h"
diff --git a/
[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vminu.vv combine case 1 with GR2VR cost 0, 1 and 2
https://gcc.gnu.org/g:b319ccfa4f8fb971baf62fac46e39bf7158d15a9
commit b319ccfa4f8fb971baf62fac46e39bf7158d15a9
Author: Pan Li
Date: Thu Jun 19 10:49:07 2025 +0800
RISC-V: Add test for vec_duplicate + vminu.vv combine case 1 with GR2VR
cost 0, 1 and 2
Add asm dump check test for vec_duplicate + vminu.vv combine to
vminu.vx, with the GR2VR cost is 0, 1 and 2.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u16.c: Add asm check
for vminu.vx combine.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u8.c: Ditto.
Signed-off-by: Pan Li
(cherry picked from commit 89ec7ba1b1815aa9ba68d17f01e1b5a4dc20bde5)
Diff:
---
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u16.c | 3 +++
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u32.c | 3 +++
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u64.c | 3 +++
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u8.c | 2 ++
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u16.c | 3 +++
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u32.c | 3 +++
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u64.c | 3 +++
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u8.c | 3 +++
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u16.c | 3 +++
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u32.c | 3 +++
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u64.c | 3 +++
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u8.c | 3 +++
12 files changed, 35 insertions(+)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u16.c
index bee4171c0b46..b62164347186 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u16.c
@@ -15,6 +15,8 @@ DEF_VX_BINARY_CASE_1_WRAP(T, /, div, VX_BINARY_BODY_X16)
DEF_VX_BINARY_CASE_1_WRAP(T, %, rem, VX_BINARY_BODY_X16)
DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_0_WARP(T), max, VX_BINARY_FUNC_BODY_X8)
DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_1_WARP(T), max, VX_BINARY_FUNC_BODY_X8)
+DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_0_WARP(T), min, VX_BINARY_FUNC_BODY_X8)
+DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_1_WARP(T), min, VX_BINARY_FUNC_BODY_X8)
/* { dg-final { scan-assembler {vadd.vx} } } */
/* { dg-final { scan-assembler {vsub.vx} } } */
@@ -25,3 +27,4 @@ DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_1_WARP(T), max,
VX_BINARY_FUNC_BODY_X8)
/* { dg-final { scan-assembler {vdivu.vx} } } */
/* { dg-final { scan-assembler {vremu.vx} } } */
/* { dg-final { scan-assembler {vmaxu.vx} } } */
+/* { dg-final { scan-assembler {vminu.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u32.c
index 376f1c63ff10..741a7495f136 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u32.c
@@ -15,6 +15,8 @@ DEF_VX_BINARY_CASE_1_WRAP(T, /, div, VX_BINARY_BODY_X4)
DEF_VX_BINARY_CASE_1_WRAP(T, %, rem, VX_BINARY_BODY_X4)
DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_0_WARP(T), max, VX_BINARY_FUNC_BODY_X4)
DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_1_WARP(T), max, VX_BINARY_FUNC_BODY_X4)
+DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_0_WARP(T), min, VX_BINARY_FUNC_BODY_X4)
+DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_1_WARP(T), min, VX_BINARY_FUNC_BODY_X4)
/* { dg-final { scan-assembler {vadd.vx} } } */
/* { dg-final { scan-assembler {vsub.vx} } } */
@@ -25,3 +27,4 @@ DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_1_WARP(T), max,
VX_BINARY_FUNC_BODY_X4)
/* { dg-final { scan-assembler {vdivu.vx} } } */
/* { dg-final { scan-assembler {vremu.vx} } } */
/* { dg-final { scan-assembler {vmaxu.vx} } } */
+/* { dg-final { scan-assembler {vminu.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u64.c
index 034f50dfe634..70375b174734 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u64.c
@@ -15,6 +15,8 @@ DEF_VX_BINARY_CASE_1_WRAP(T, /, div, VX_BINARY_BODY)
DEF_VX_BINARY_CASE_1_WRAP(T, %, rem, VX_BINARY_BODY)
DEF
[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [RISC-V][PR target/119830] Fix RISC-V codegen on 32bit hosts
https://gcc.gnu.org/g:2e8d2d138d795cd8e1b7899e560701cf20201a47
commit 2e8d2d138d795cd8e1b7899e560701cf20201a47
Author: Andrew Pinski
Date: Sun Jun 22 12:35:19 2025 -0600
[RISC-V][PR target/119830] Fix RISC-V codegen on 32bit hosts
So this is Andrew's patch from the PR. We weren't clean for a 32bit host in
some of the arithmetic for constant synthesis.
I confirmed the bug on a 32bit linux host, then confirmed that Andrew's
patch
from the PR fixes the problem, then ran Andrew's patch through my tester
successfully.
Naturally I'll wait for pre-commit testing, but I'm not expecting problems.
PR target/119830
gcc/
* config/riscv/riscv.cc (riscv_build_integer_1): Make arithmetic in
bclr case
clean for 32 bit hosts.
gcc/testsuite/
* gcc.target/riscv/pr119830.c: New test.
(cherry picked from commit 07c02ff39e121a496c46d3a997a25e2f46ce227e)
Diff:
---
gcc/config/riscv/riscv.cc | 6 +++---
gcc/testsuite/gcc.target/riscv/pr119830.c | 13 +
2 files changed, 16 insertions(+), 3 deletions(-)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index adbfe9de29c0..8148b2f3a9ed 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -1078,16 +1078,16 @@ riscv_build_integer_1 (struct riscv_integer_op
codes[RISCV_MAX_INTEGER_OPS],
/* Now iterate over the bits we want to clear until the cost is
too high or we're done. */
nval = value ^ HOST_WIDE_INT_C (-1);
- nval &= HOST_WIDE_INT_C (~0x7fff);
+ nval &= ~HOST_WIDE_INT_C (0x7fff);
while (nval && alt_cost < cost)
{
HOST_WIDE_INT bit = ctz_hwi (nval);
alt_codes[alt_cost].code = AND;
- alt_codes[alt_cost].value = ~(1UL << bit);
+ alt_codes[alt_cost].value = ~(HOST_WIDE_INT_UC (1) << bit);
alt_codes[alt_cost].use_uw = false;
alt_codes[alt_cost].save_temporary = false;
alt_cost++;
- nval &= ~(1UL << bit);
+ nval &= ~(HOST_WIDE_INT_UC (1) << bit);
}
if (nval == 0 && alt_cost <= cost)
diff --git a/gcc/testsuite/gcc.target/riscv/pr119830.c
b/gcc/testsuite/gcc.target/riscv/pr119830.c
new file mode 100644
index ..8c7cf3bd79d0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/pr119830.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zbb_zbs -mabi=lp64d" { target { rv64 } } } */
+/* { dg-options "-march=rv32gc_zbb_zbs -mabi=ilp32" { target { rv32 } } } */
+
+#include
+void test(int32_t N, int16_t* A, int16_t val) {
+int32_t i, j;
+for (i = 0; i < N; i++) {
+for (j = 0; j < N; j++) {
+A[i * N + j] += val;
+}
+}
+}
[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Combine vec_duplicate + vsaddu.vv to vsaddu.vx on GR2VR cost
https://gcc.gnu.org/g:fe2c046f055e14646f7e2908c135e6a3cf1973c7
commit fe2c046f055e14646f7e2908c135e6a3cf1973c7
Author: Pan Li
Date: Sat Jun 21 09:00:16 2025 +0800
RISC-V: Combine vec_duplicate + vsaddu.vv to vsaddu.vx on GR2VR cost
This patch would like to combine the vec_duplicate + vsaddu.vv to the
vsaddu.vx. From example as below code. The related pattern will depend
on the cost of vec_duplicate from GR2VR. Then the late-combine will
take action if the cost of GR2VR is zero, and reject the combination
if the GR2VR cost is greater than zero.
Assume we have example code like below, GR2VR cost is 0.
#define DEF_VX_BINARY(T, FUNC) \
void\
test_vx_binary (T * restrict out, T * restrict in, T x, unsigned n) \
{ \
for (unsigned i = 0; i < n; i++) \
out[i] = FUNC (in[i], x); \
}
T sat_add(T a, T b)
{
return (a + b) | (-(T)((T)(a + b) < a));
}
DEF_VX_BINARY(uint32_t, sat_add)
Before this patch:
10 │ test_vx_binary_or_int32_t_case_0:
11 │ beq a3,zero,.L8
12 │ vsetvli a5,zero,e32,m1,ta,ma
13 │ vmv.v.x v2,a2
14 │ sllia3,a3,32
15 │ srlia3,a3,32
16 │ .L3:
17 │ vsetvli a5,a3,e32,m1,ta,ma
18 │ vle32.v v1,0(a1)
19 │ sllia4,a5,2
20 │ sub a3,a3,a5
21 │ add a1,a1,a4
22 │ vsaddu.vv v1,v1,v2
23 │ vse32.v v1,0(a0)
24 │ add a0,a0,a4
25 │ bne a3,zero,.L3
After this patch:
10 │ test_vx_binary_or_int32_t_case_0:
11 │ beq a3,zero,.L8
12 │ sllia3,a3,32
13 │ srlia3,a3,32
14 │ .L3:
15 │ vsetvli a5,a3,e32,m1,ta,ma
16 │ vle32.v v1,0(a1)
17 │ sllia4,a5,2
18 │ sub a3,a3,a5
19 │ add a1,a1,a4
20 │ vsaddu.vx v1,v1,a2
21 │ vse32.v v1,0(a0)
22 │ add a0,a0,a4
23 │ bne a3,zero,.L3
gcc/ChangeLog:
* config/riscv/riscv-v.cc (expand_vx_binary_vec_dup_vec): Add
new case US_PLUS.
(expand_vx_binary_vec_vec_dup): Ditto.
* config/riscv/riscv.cc (riscv_rtx_costs): Ditto.
* config/riscv/vector-iterators.md: Add new op us_plus.
Signed-off-by: Pan Li
(cherry picked from commit a2d018b642019165511e89d47bfb46af55f81f98)
Diff:
---
gcc/config/riscv/riscv-v.cc | 2 ++
gcc/config/riscv/riscv.cc| 1 +
gcc/config/riscv/vector-iterators.md | 4 ++--
3 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index ac690df3688a..45dd9256d020 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -5541,6 +5541,7 @@ expand_vx_binary_vec_dup_vec (rtx op_0, rtx op_1, rtx
op_2,
case UMAX:
case SMIN:
case UMIN:
+case US_PLUS:
icode = code_for_pred_scalar (code, mode);
break;
case MINUS:
@@ -5579,6 +5580,7 @@ expand_vx_binary_vec_vec_dup (rtx op_0, rtx op_1, rtx
op_2,
case UMAX:
case SMIN:
case UMIN:
+case US_PLUS:
icode = code_for_pred_scalar (code, mode);
break;
default:
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 8148b2f3a9ed..e3abcaae2a61 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -3995,6 +3995,7 @@ riscv_rtx_costs (rtx x, machine_mode mode, int
outer_code, int opno ATTRIBUTE_UN
case UDIV:
case MOD:
case UMOD:
+ case US_PLUS:
*total = get_vector_binary_rtx_cost (op, scalar2vr_cost);
break;
default:
diff --git a/gcc/config/riscv/vector-iterators.md
b/gcc/config/riscv/vector-iterators.md
index 44ae79c48aa7..0e1318d1447c 100644
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -4042,11 +4042,11 @@
])
(define_code_iterator any_int_binop_no_shift_v_vdup [
- plus minus and ior xor mult div udiv mod umod smax umax smin umin
+ plus minus and ior xor mult div udiv mod umod smax umax smin umin us_plus
])
(define_code_iterator any_int_binop_no_shift_vdup_v [
- plus minus and ior xor mult smax umax smin umin
+ plus minus and ior xor mult smax umax smin umin us_plus
])
(define_code_iterator any_int_unop [neg not])
[gcc r15-9917] libstdc++: Update LWG 4166 changes to concat_view::end() [PR120934]
https://gcc.gnu.org/g:612690936f5ddd122b60cf843cb4f40ae7ede436
commit r15-9917-g612690936f5ddd122b60cf843cb4f40ae7ede436
Author: Patrick Palka
Date: Thu Jul 3 10:55:17 2025 -0400
libstdc++: Update LWG 4166 changes to concat_view::end() [PR120934]
In r15-4555-gf191c830154565 we proactively implemented the initial
proposed resolution for LWG 4166 which later turned out to be
insufficient, since we must also require equality_comparable of the
underlying iterators before concat_view could be a common range.
This patch implements the updated P/R, requiring all underlying
iterators to be forward (which implies equality_comparable) before
making concat_view common, which fixes the testcase from this PR.
PR libstdc++/120934
libstdc++-v3/ChangeLog:
* include/std/ranges (concat_view::end): Refine condition
for returning an iterator instead of default_sentinel as
per the updated P/R for LWG 4166.
* testsuite/std/ranges/concat/1.cc (test05): New test.
Reviewed-by: Jonathan Wakely
(cherry picked from commit c5a17e92ebf0c6f3887fb5698a1114a3fdf50576)
Diff:
---
libstdc++-v3/include/std/ranges | 4 ++--
libstdc++-v3/testsuite/std/ranges/concat/1.cc | 13 +
2 files changed, 15 insertions(+), 2 deletions(-)
diff --git a/libstdc++-v3/include/std/ranges b/libstdc++-v3/include/std/ranges
index 210ac8274fc1..8756065d 100644
--- a/libstdc++-v3/include/std/ranges
+++ b/libstdc++-v3/include/std/ranges
@@ -9735,7 +9735,7 @@ namespace ranges
end() requires (!(__detail::__simple_view<_Vs> && ...))
{
constexpr auto __n = sizeof...(_Vs);
- if constexpr ((semiregular> && ...)
+ if constexpr (__detail::__all_forward
&& common_range<_Vs...[__n - 1]>)
return _Iterator(this, in_place_index<__n - 1>,
ranges::end(std::get<__n - 1>(_M_views)));
@@ -9747,7 +9747,7 @@ namespace ranges
end() const requires (range && ...) &&
__detail::__concatable
{
constexpr auto __n = sizeof...(_Vs);
- if constexpr ((semiregular> && ...)
+ if constexpr (__detail::__all_forward
&& common_range)
return _Iterator(this, in_place_index<__n - 1>,
ranges::end(std::get<__n - 1>(_M_views)));
diff --git a/libstdc++-v3/testsuite/std/ranges/concat/1.cc
b/libstdc++-v3/testsuite/std/ranges/concat/1.cc
index 16721912a37d..f78ed08a610b 100644
--- a/libstdc++-v3/testsuite/std/ranges/concat/1.cc
+++ b/libstdc++-v3/testsuite/std/ranges/concat/1.cc
@@ -99,6 +99,18 @@ test04()
using type = decltype(v);
}
+void
+test05()
+{
+ // PR libstdc++/120934 - views::concat is ill-formed depending on argument
order
+ auto v1 = views::single(1);
+ std::vector vec = {2, 3};
+ auto v2 = views::join(views::transform(vec, views::single));
+
+ static_assert( ranges::range );
+ static_assert( ranges::range );
+}
+
int
main()
{
@@ -107,4 +119,5 @@ main()
test02();
test03();
test04();
+ test05();
}
[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [PATCH] RISC-V: Use builtin clz/ctz when count_leading_zeros and count_trailing_zeros is used
https://gcc.gnu.org/g:ac124f4a0405aa34a04943d8d55dedd02233258c commit ac124f4a0405aa34a04943d8d55dedd02233258c Author: Sosutha Sethuramapandian Date: Thu Jun 19 20:53:56 2025 -0600 [PATCH] RISC-V: Use builtin clz/ctz when count_leading_zeros and count_trailing_zeros is used longlong.h for RISCV should define count_leading_zeros and count_trailing_zeros and COUNT_LEADING_ZEROS_0 when ZBB is enabled. The following patch patch fixes the bug reported in, https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110181 The divdi3 on riscv32 with zbb extension generates __clz_tab instead of genearating __builtin_clzll/__builtin_clz which is not efficient since lookup table is emitted. Updating longlong.h to use this __builtin_clzll/__builtin_clz generates optimized code for the instruction. PR target/110181 include/ChangeLog * longlong.h [__riscv] (count_leading_zeros): Define. [__riscv] (count_trailing_zeros): Likewise. [__riscv] (COUNT_LEADING_ZEROS_0): Likewise. (cherry picked from commit e08ef05e4da86d34223118092bbb857b8dd5d002) Diff: --- include/longlong.h | 14 ++ 1 file changed, 14 insertions(+) diff --git a/include/longlong.h b/include/longlong.h index 40f94243a1af..5ae250f7192d 100644 --- a/include/longlong.h +++ b/include/longlong.h @@ -1065,6 +1065,20 @@ extern UDItype __umulsidi3 (USItype, USItype); #endif #if defined(__riscv) + +#ifdef __riscv_zbb +#if W_TYPE_SIZE == 32 +#define count_leading_zeros(COUNT, X) ((COUNT) = __builtin_clz (X)) +#define count_trailing_zeros(COUNT, X) ((COUNT) = __builtin_ctz (X)) +#define COUNT_LEADING_ZEROS_0 32 +#endif /* W_TYPE_SIZE == 32 */ +#if W_TYPE_SIZE == 64 +#define count_leading_zeros(COUNT, X) ((COUNT) = __builtin_clzll (X)) +#define count_trailing_zeros(COUNT, X) ((COUNT) = __builtin_ctzll (X)) +#define COUNT_LEADING_ZEROS_0 64 +#endif /* W_TYPE_SIZE == 64 */ +#endif /* __riscv_zbb */ + #ifdef __riscv_mul #define __umulsidi3(u,v) ((UDWtype)(UWtype)(u) * (UWtype)(v)) #define __muluw3(a, b) ((UWtype)(a) * (UWtype)(b))
[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vsaddu.vv combine case 1 with GR2VR cost 0, 1 and 2
https://gcc.gnu.org/g:8712876f6c44061432fb81540e13c9f7f91c6ac7
commit 8712876f6c44061432fb81540e13c9f7f91c6ac7
Author: Pan Li
Date: Sat Jun 21 10:07:38 2025 +0800
RISC-V: Add test for vec_duplicate + vsaddu.vv combine case 1 with GR2VR
cost 0, 1 and 2
Add asm dump check test for vec_duplicate + vsaddu.vv combine to
vsaddu.vx, with the GR2VR cost is 0, 1 and 2.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u16.c: Add asm check
for vsaddu.vx combine.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u8.c: Ditto.
Signed-off-by: Pan Li
(cherry picked from commit 11811e698b460b5fe45777f4c333aa74655cff39)
Diff:
---
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u16.c | 2 ++
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u32.c | 1 +
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u64.c | 2 ++
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u8.c | 3 +++
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u16.c | 2 ++
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u32.c | 2 ++
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u64.c | 2 ++
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u8.c | 2 ++
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u16.c | 2 ++
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u32.c | 2 ++
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u64.c | 2 ++
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u8.c | 2 ++
12 files changed, 24 insertions(+)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u16.c
index b62164347186..de10d66a1b23 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u16.c
@@ -17,6 +17,7 @@ DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_0_WARP(T), max,
VX_BINARY_FUNC_BODY_X8)
DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_1_WARP(T), max, VX_BINARY_FUNC_BODY_X8)
DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_0_WARP(T), min, VX_BINARY_FUNC_BODY_X8)
DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_1_WARP(T), min, VX_BINARY_FUNC_BODY_X8)
+DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_ADD_FUNC_WRAP(T), sat_add,
VX_BINARY_FUNC_BODY_X8)
/* { dg-final { scan-assembler {vadd.vx} } } */
/* { dg-final { scan-assembler {vsub.vx} } } */
@@ -28,3 +29,4 @@ DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_1_WARP(T), min,
VX_BINARY_FUNC_BODY_X8)
/* { dg-final { scan-assembler {vremu.vx} } } */
/* { dg-final { scan-assembler {vmaxu.vx} } } */
/* { dg-final { scan-assembler {vminu.vx} } } */
+/* { dg-final { scan-assembler {vsaddu.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u32.c
index 741a7495f136..2e59da06c979 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u32.c
@@ -17,6 +17,7 @@ DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_0_WARP(T), max,
VX_BINARY_FUNC_BODY_X4)
DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_1_WARP(T), max, VX_BINARY_FUNC_BODY_X4)
DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_0_WARP(T), min, VX_BINARY_FUNC_BODY_X4)
DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_1_WARP(T), min, VX_BINARY_FUNC_BODY_X4)
+DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_ADD_FUNC_WRAP(T), sat_add,
VX_BINARY_FUNC_BODY_X4)
/* { dg-final { scan-assembler {vadd.vx} } } */
/* { dg-final { scan-assembler {vsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u64.c
index 70375b174734..064ed1f2e892 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u64.c
@@ -17,6 +17,7 @@ DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_0_WARP(T), max,
VX_BINARY_FUNC_BODY)
DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_1_WARP(T), max, VX_BINARY_FUNC_BODY)
DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_0_WARP(T), min, VX_BINARY_FUNC_BODY)
DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_1_WARP(T), min, VX_BINARY_FUNC_BODY)
+DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_ADD_FUNC_WRAP(T), sat_add,
VX_BINARY_FUNC_BODY)
/* { dg-final { scan-assembler {vadd.vx} } } */
/* { dg-final { scan-asse
[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add patterns for vector-scalar multiply-(subtract-)accumulate [PR119100]
https://gcc.gnu.org/g:cbdf7944671243ff85bcda589fc138146ad8e4d7 commit cbdf7944671243ff85bcda589fc138146ad8e4d7 Author: Paul-Antoine Arras Date: Tue Jun 24 15:42:50 2025 -0600 RISC-V: Add patterns for vector-scalar multiply-(subtract-)accumulate [PR119100] This pattern enables the combine pass (or late-combine, depending on the case) to merge a vec_duplicate into a plus-mult or minus-mult RTL instruction. Before this patch, we have two instructions, e.g.: vfmv.v.f v6,fa0 vfmacc.vv v2,v6,v4 After, we get only one: vfmacc.vf v2,fa0,v4 PR target/119100 gcc/ChangeLog: * config/riscv/autovec-opt.md (*_vf_): Handle both add and acc FMA variants. * config/riscv/vector.md (*pred_mul__scalar_undef): New. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f16.c: Add vfmacc and vfmsac. * gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f32.c: Likewise. * gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f64.c: Likewise. * gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f16.c: Likewise. * gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f32.c: Likewise. * gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f64.c: Likewise. * gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f16.c: Likewise. * gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f32.c: Likewise. * gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f64.c: Likewise. * gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f16.c: Likewise. * gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f32.c: Likewise. * gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f64.c: Likewise. * gcc.target/riscv/rvv/autovec/vx_vf/vf_mulop.h: Add support for acc variants. * gcc.target/riscv/rvv/autovec/vx_vf/vf_mulop_run.h: Likewise. * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmadd-run-1-f16.c: Define TEST_OUT. * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmadd-run-1-f32.c: Likewise. * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmadd-run-1-f64.c: Likewise. * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsub-run-1-f16.c: Likewise. * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsub-run-1-f32.c: Likewise. * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsub-run-1-f64.c: Likewise. * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmadd-run-1-f16.c: Likewise. * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmadd-run-1-f32.c: Likewise. * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmadd-run-1-f64.c: Likewise. * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsub-run-1-f16.c: Likewise. * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsub-run-1-f32.c: Likewise. * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsub-run-1-f64.c: Likewise. * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmacc-run-1-f16.c: New test. * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmacc-run-1-f32.c: New test. * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmacc-run-1-f64.c: New test. * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsac-run-1-f16.c: New test. * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsac-run-1-f32.c: New test. * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsac-run-1-f64.c: New test. (cherry picked from commit 92e1893e0155b6b3baef2a935efd5936d23a67ea) Diff: --- gcc/config/riscv/autovec-opt.md| 14 +++-- gcc/config/riscv/vector.md | 37 +++- .../gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f16.c | 4 ++ .../gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f32.c | 4 ++ .../gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f64.c | 4 ++ .../gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f16.c | 9 +-- .../gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f32.c | 9 +-- .../gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f64.c | 9 +-- .../gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f16.c | 4 ++ .../gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f32.c | 4 ++ .../gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f64.c | 4 ++ .../gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f16.c | 9 +-- .../gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f32.c | 9 +-- .../gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f64.c | 9 +-- .../gcc.target/riscv/rvv/autovec/vx_vf/vf_mulop.h | 66 ++ .../riscv/rvv/autovec/vx_vf/vf_mulop_run.h | 8 +-- .../riscv/rvv/autovec/vx_vf/vf_vfmacc-run-1-f16.c | 16 ++ .../riscv/rvv/autovec/vx_vf/vf_vfmacc-run-1-f32.c | 16 ++ .../riscv/rvv/autovec/vx_vf/vf_vfmacc-run-1-f64.c | 16 ++ .../riscv/rvv/autovec/vx_vf/vf_vfmadd-run-1-f16.c | 1 + .../riscv/rvv/autovec/vx_vf/vf_vfmadd-run-1-f32.c | 1 + .../riscv/rvv/autovec/vx_vf/vf_vfmadd-run-1-f64.c | 1 + .../riscv/rvv/autovec/vx_vf/vf_vfmsac-run-1-f16.c | 16 ++ .../riscv/rvv/autovec/vx_v
[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [RISC-V][PR target/118241] Fix data prefetch predicate/constraint for RISC-V
https://gcc.gnu.org/g:4e8970b53e39c6589119e505873e6f994e97201f
commit 4e8970b53e39c6589119e505873e6f994e97201f
Author: Jeff Law
Date: Sat Jun 21 08:24:58 2025 -0600
[RISC-V][PR target/118241] Fix data prefetch predicate/constraint for RISC-V
The RISC-V prefetch support is broken in a few ways. This addresses the
data
side prefetch problems. I'd mistakenly thought this BZ was a prefetch.i
related (which has deeper problems).
The basic problem is we were accepting any valid address when in fact there
are
restrictions. This patch more precisely defines the predicate such that we
allow
REG
REG+D
Where D must have the low 5 bits clear. Note that absolute addresses fall
into
the REG+D form using the x0 for the register operand since it always has the
value zero. The test verifies REG, REG+D, ABS addressing modes that are
valid
as well as REG+D and ABS which must be reloaded into a REG because the
displacement has low bits set.
An earlier version of this patch has gone through testing in my tester on
rv32
and rv64. Obviously I'll wait for pre-commit CI to do its thing before
moving
forward.
This is a good backport candidate after simmering on the trunk for a bit.
PR target/118241
gcc/
* config/riscv/predicates.md (prefetch_operand): New predicate.
* config/riscv/constraints.md (Q): New constraint.
* config/riscv/riscv.md (prefetch): Use new predicate and
constraint.
(riscv_prefetchi_): Similarly.
gcc/testsuite/
* gcc.target/riscv/pr118241.c: New test.
(cherry picked from commit 49199bb29628365fc6c60bd185808a1bad65086d)
Diff:
---
gcc/config/riscv/constraints.md | 4
gcc/config/riscv/predicates.md| 12
gcc/config/riscv/riscv.md | 4 ++--
gcc/testsuite/gcc.target/riscv/pr118241.c | 16
4 files changed, 34 insertions(+), 2 deletions(-)
diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md
index 58355cf03f2f..ccab1a2e29df 100644
--- a/gcc/config/riscv/constraints.md
+++ b/gcc/config/riscv/constraints.md
@@ -325,3 +325,7 @@
"A 2-bit unsigned immediate."
(and (match_code "const_int")
(match_test "IN_RANGE (ival, 0, 3)")))
+
+(define_constraint "Q"
+ "An address operand that is valid for a prefetch instruction"
+ (match_operand 0 "prefetch_operand"))
diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md
index 23690792b32e..8072d67fbd97 100644
--- a/gcc/config/riscv/predicates.md
+++ b/gcc/config/riscv/predicates.md
@@ -27,6 +27,18 @@
(ior (match_operand 0 "const_arith_operand")
(match_operand 0 "register_operand")))
+;; REG or REG+D where D fits in a simm12 and has the low 4 bits
+;; off. The REG+D form can be reloaded into a temporary if needed
+;; after FP elimination if that exposes an invalid offset.
+(define_predicate "prefetch_operand"
+ (ior (match_operand 0 "register_operand")
+ (and (match_test "const_arith_operand (op, VOIDmode)")
+ (match_test "(INTVAL (op) & 0xf) == 0"))
+ (and (match_code "plus")
+ (match_test "register_operand (XEXP (op, 0), word_mode)")
+ (match_test "const_arith_operand (XEXP (op, 1), VOIDmode)")
+ (match_test "(INTVAL (XEXP (op, 1)) & 0xf) == 0"
+
(define_predicate "lui_operand"
(and (match_code "const_int")
(match_test "LUI_OPERAND (INTVAL (op))")))
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 3aed25c25880..3406b50518ed 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -4402,7 +4402,7 @@
)
(define_insn "prefetch"
- [(prefetch (match_operand 0 "address_operand" "r")
+ [(prefetch (match_operand 0 "prefetch_operand" "Q")
(match_operand 1 "imm5_operand" "i")
(match_operand 2 "const_int_operand" "n"))]
"TARGET_ZICBOP"
@@ -4422,7 +4422,7 @@
(const_string "4")))])
(define_insn "riscv_prefetchi_"
- [(unspec_volatile:X [(match_operand:X 0 "address_operand" "r")
+ [(unspec_volatile:X [(match_operand:X 0 "prefetch_operand" "Q")
(match_operand:X 1 "imm5_operand" "i")]
UNSPECV_PREI)]
"TARGET_ZICBOP"
diff --git a/gcc/testsuite/gcc.target/riscv/pr118241.c
b/gcc/testsuite/gcc.target/riscv/pr118241.c
new file mode 100644
index ..f1dc44bce0ca
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/pr118241.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zicbop" { target { rv64 } } } */
+/* { dg-options "-march=rv32gc_zicbop" { target { rv32 } } } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+void test1() { __builtin_prefetch((int *)2047); }
+void test2() { __builtin_prefetch((int *)1024); }
+void test3(char *x) { __builtin_prefetch(&x); }
+void test4(char *x) { __bui
[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vsaddu.vv combine case 0 with GR2VR cost 0, 2 and 15
https://gcc.gnu.org/g:68deb26b4f661a13c3e489ef8079ac885d194cf4
commit 68deb26b4f661a13c3e489ef8079ac885d194cf4
Author: Pan Li
Date: Sat Jun 21 09:10:07 2025 +0800
RISC-V: Add test for vec_duplicate + vsaddu.vv combine case 0 with GR2VR
cost 0, 2 and 15
Add asm dump check and run test for vec_duplicate + vsaddu.vv
combine to vsaddu.vx, with the GR2VR cost is 0, 2 and 15.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c: Add asm check.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h: Add test
helper macros.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h: Add test
data for run test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vsadd-run-1-u16.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vsadd-run-1-u32.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vsadd-run-1-u64.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vsadd-run-1-u8.c: New test.
Signed-off-by: Pan Li
(cherry picked from commit 9a8f82d6a63e36ffba883b365101b58955ca7c64)
Diff:
---
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c | 1 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c | 1 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c | 1 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c | 1 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c | 1 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c | 1 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c | 1 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c | 1 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c | 1 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c | 1 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c | 1 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c | 1 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h | 42 +++--
.../riscv/rvv/autovec/vx_vf/vx_binary_data.h | 196 +
.../riscv/rvv/autovec/vx_vf/vx_vsadd-run-1-u16.c | 17 ++
.../riscv/rvv/autovec/vx_vf/vx_vsadd-run-1-u32.c | 17 ++
.../riscv/rvv/autovec/vx_vf/vx_vsadd-run-1-u64.c | 17 ++
.../riscv/rvv/autovec/vx_vf/vx_vsadd-run-1-u8.c| 17 ++
18 files changed, 305 insertions(+), 13 deletions(-)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c
index bcfd5145d24f..21a207edce75 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c
@@ -17,3 +17,4 @@ TEST_BINARY_VX_UNSIGNED_0(T)
/* { dg-final { scan-assembler-times {vremu.vx} 1 } } */
/* { dg-final { scan-assembler-times {vmaxu.vx} 2 } } */
/* { dg-final { scan-assembler-times {vminu.vx} 2 } } */
+/* { dg-final { scan-assembler-times {vsaddu.vx} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c
index b9a6a2830916..d1063adb0d6c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c
@@ -17,3 +17,4 @@ TEST_BINARY_VX_UNSIGNED_0(T)
/* { dg-final { scan-assembler-times {vremu.vx} 1 } } */
/* { dg-final { scan-assembler-times {vmaxu.vx} 2 } } */
/* { dg-final { scan-assembler-times {vminu.vx} 2 } } */
+/* { dg-final { scan-assembler-times {vsaddu.vx} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c
index abb5e5e78428..3d96503fd9ad 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c
@@ -17,3 +17,4 @@ TEST_BINARY_VX_UNSIGNED_0(T)
/* { dg-final { scan-assembler-times {vremu.vx} 1 } } */
/* { dg-final { scan-assembler-times {vmaxu.vx} 2 } } */
/* { dg-final { scan-assembler-times {vminu.vx} 2 } } */
+/* { dg-final { scan-assembler-times {vsaddu.vx} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c
index 50065d0973b2..339a35c3f422 10064
[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: update prepare_ternary_operands to handle vector-scalar case [PR120828]
https://gcc.gnu.org/g:20e57a6541e283186ec5e26552149f454af27cc7
commit 20e57a6541e283186ec5e26552149f454af27cc7
Author: Paul-Antoine Arras
Date: Wed Jun 25 16:42:00 2025 +
RISC-V: update prepare_ternary_operands to handle vector-scalar case
[PR120828]
This is a followup to 92e1893e0 "RISC-V: Add patterns for vector-scalar
multiply-(subtract-)accumulate" that caused an ICE in some cases where the
mult
operands were wrongly swapped.
This patch ensures that operands are not swapped in the vector-scalar case.
PR target/120828
gcc/ChangeLog:
* config/riscv/riscv-v.cc (prepare_ternary_operands): Handle the
vector-scalar case.
(cherry picked from commit 181cb2943d53862aa41eab49a042dff991a3d94f)
Diff:
---
gcc/config/riscv/riscv-v.cc | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 45dd9256d020..a3d704e81cc4 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -4723,7 +4723,7 @@ prepare_ternary_operands (rtx *ops)
ops[4], ops[1], ops[6], ops[7], ops[9]));
ops[5] = ops[4] = ops[0];
}
- else
+ else if (VECTOR_MODE_P (GET_MODE (ops[2])))
{
/* Swap the multiplication ops if the fallback value is the
second of the two. */
@@ -4733,8 +4733,10 @@ prepare_ternary_operands (rtx *ops)
/* TODO: ??? Maybe we could support splitting FMA (a, 4, b)
into PLUS (ASHIFT (a, 2), b) according to uarchs. */
}
- gcc_assert (rtx_equal_p (ops[5], RVV_VUNDEF (mode))
- || rtx_equal_p (ops[5], ops[2]) || rtx_equal_p (ops[5], ops[4]));
+ gcc_assert (
+rtx_equal_p (ops[5], RVV_VUNDEF (mode)) || rtx_equal_p (ops[5], ops[2])
+|| (!VECTOR_MODE_P (GET_MODE (ops[2])) && rtx_equal_p (ops[5], ops[3]))
+|| rtx_equal_p (ops[5], ops[4]));
}
/* Expand VEC_MASK_LEN_{LOAD_LANES,STORE_LANES}. */
[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Fix build issue
https://gcc.gnu.org/g:eef3fd51a8c4a612fb627e386d0bc80dbb66f506 commit eef3fd51a8c4a612fb627e386d0bc80dbb66f506 Author: Kito Cheng Date: Thu Jun 26 14:35:47 2025 +0800 RISC-V: Fix build issue Apparently I forgot to squash this fix into the previous commit before I push... gcc/ChangeLog: * config/riscv/riscv.md: Fix build issue. (cherry picked from commit 7c67f7f8d4c8aadbe8efd733c29d13bfcbb0f50f) Diff: --- gcc/config/riscv/riscv.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index 04b8cc92cd60..893c925b6b94 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -4868,12 +4868,12 @@ (include "sync-ztso.md") (include "peephole.md") (include "pic.md") +(include "vector.md") (include "vector-crypto.md") (include "vector-bfloat16.md") (include "zicond.md") (include "sfb.md") (include "zc.md") -(include "vector.md") ;; Vendor extensions (include "thead.md") (include "corev.md")
[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add Profiles RVA/B23S64 support.
https://gcc.gnu.org/g:95c6127a2b69e654688072cc6d758a3778f45726
commit 95c6127a2b69e654688072cc6d758a3778f45726
Author: Jiawei
Date: Tue Jun 24 17:34:05 2025 +0800
RISC-V: Add Profiles RVA/B23S64 support.
This patch adds support for the RISC-V Profiles RVA23S64 and RVB23S64.
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: New Profiles.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/arch-rva23s.c: New test.
* gcc.target/riscv/arch-rvb23s.c: New test.
(cherry picked from commit e858dc702147b7de560afad165e7f16e3ee7d6c9)
Diff:
---
gcc/common/config/riscv/riscv-common.cc | 18 +-
gcc/testsuite/gcc.target/riscv/arch-rva23s.c | 14 ++
gcc/testsuite/gcc.target/riscv/arch-rvb23s.c | 12
3 files changed, 43 insertions(+), 1 deletion(-)
diff --git a/gcc/common/config/riscv/riscv-common.cc
b/gcc/common/config/riscv/riscv-common.cc
index 3c25848ccd38..82037a334528 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -295,6 +295,15 @@ static const riscv_profiles riscv_profiles_table[] =
"_zicboz_zfhmin_zkt_zvfhmin_zvbb_zvkt_zihintntl_zicond_zimop_zcmop_zcb"
"_zfa_zawrs_supm"},
+ /* RVA23S contains all mandatory base ISA for RVA23U64 and the privileged
+ extensions as mandatory extensions. */
+ {"rva23s64", "rv64imafdcbv_zicsr_zicntr_zihpm_ziccif_ziccrse_ziccamoa"
+ "_zicclsm_zic64b_za64rs_zihintpause_zba_zbb_zbs_zicbom_zicbop"
+ "_zicboz_zfhmin_zkt_zvfhmin_zvbb_zvkt_zihintntl_zicond_zimop_zcmop_zcb"
+ "_zfa_zawrs_svbare_svade_ssccptr_sstvecd_sstvala_sscounterenw_svpbmt"
+ "_svinval_svnapot_sstc_sscofpmf_ssnpm_ssu64xl_sha_supm"
+ },
+
/* RVB23 contains all mandatory base ISA for RVA22U64 and the new extension
'zihintntl,zicond,zimop,zcmop,zfa,zawrs' as mandatory
extensions. */
@@ -303,7 +312,14 @@ static const riscv_profiles riscv_profiles_table[] =
"_zicboz_zfhmin_zkt_zihintntl_zicond_zimop_zcmop_zcb"
"_zfa_zawrs"},
- /* Currently we do not define S/M mode Profiles in gcc part. */
+ /* RVB23S contains all mandatory base ISA for RVB23U64 and the privileged
+ extensions as mandatory extensions. */
+ {"rvb23s64", "rv64imafdcb_zicsr_zicntr_zihpm_ziccif_ziccrse_ziccamoa"
+ "_zicclsm_zic64b_za64rs_zihintpause_zba_zbb_zbs_zicbom_zicbop"
+ "_zicboz_zfhmin_zkt_zvfhmin_zvbb_zvkt_zihintntl_zicond_zimop_zcmop_zcb"
+ "_zfa_zawrs_svbare_svade_ssccptr_sstvecd_sstvala_sscounterenw_svpbmt"
+ "_svinval_svnapot_sstc_sscofpmf_ssu64xl_supm"
+ },
/* Terminate the list. */
{NULL, NULL}
diff --git a/gcc/testsuite/gcc.target/riscv/arch-rva23s.c
b/gcc/testsuite/gcc.target/riscv/arch-rva23s.c
new file mode 100644
index ..215249d52b14
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/arch-rva23s.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rva23s64 -mabi=lp64d" } */
+
+void foo(){}
+
+/* { dg-final { scan-assembler-times ".attribute arch,
\"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0"
+"_b1p0_v1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0"
+"_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0"
+"_za64rs1p0_zaamo1p0_zalrsc1p0_zawrs1p0_zfa1p0_zfhmin1p0_zca1p0_zcb1p0_zcd1p0_zcmop1p0"
+"_zba1p0_zbb1p0_zbs1p0_zkt1p0_zvbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0"
+"_zvfhmin1p0_zvkb1p0_zvkt1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_sha1p0_shcounterenw1p0"
+"_shgatpa1p0_shtvala1p0_shvsatpa1p0_shvstvala1p0_shvstvecd1p0_ssccptr1p0_sscofpmf1p0"
+"_sscounterenw1p0_ssnpm1p0_ssstateen1p0_sstc1p0_sstvala1p0_sstvecd1p0_ssu64xl1p0_supm1p0"
+"_svade1p0_svbare1p0_svinval1p0_svnapot1p0_svpbmt1p0\" 1} } */
diff --git a/gcc/testsuite/gcc.target/riscv/arch-rvb23s.c
b/gcc/testsuite/gcc.target/riscv/arch-rvb23s.c
new file mode 100644
index ..aa71f7dad7d7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/arch-rvb23s.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rvb23s64 -mabi=lp64d" } */
+
+void foo(){}
+
+/* { dg-final { scan-assembler-times ".attribute arch,
\"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0"
+"_b1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0"
+"_zicntr2p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_zmmul1p0"
+"_za64rs1p0_zaamo1p0_zalrsc1p0_zawrs1p0_zfa1p0_zfhmin1p0_zca1p0_zcb1p0_zcd1p0_zcmop1p0"
+"_zba1p0_zbb1p0_zbs1p0_zkt1p0_zvbb1p0_zve32f1p0_zve32x1p0_zvfhmin1p0_zvkb1p0_zvkt1p0"
+"_zvl32b1p0_ssccptr1p0_sscofpmf1p0_sscounterenw1p0_sstc1p0_sstvala1p0_sstvecd1p0"
+"_ssu64xl1p0_supm1p0_svade1p0_svbare1p0_svinval1p0_svnapot1p0_svpbmt1p0\" 1} }
*/
[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [RISC-V][PR target/118241] Fix data prefetch predicate/constraint for RISC-V
https://gcc.gnu.org/g:d08eceb84cca404dc0417ea69cd7ef9d7bae1ced commit d08eceb84cca404dc0417ea69cd7ef9d7bae1ced Author: Jeff Law Date: Mon Jun 23 18:27:49 2025 -0600 [RISC-V][PR target/118241] Fix data prefetch predicate/constraint for RISC-V Fix typo in comment spotted by Peter B. PR target/118241 gcc/ * config/riscv/predicates.md: Fix comment typo in recent change. (cherry picked from commit bf7162b321128ba93521a824e5a7a00d1cc3d1f8) Diff: --- gcc/config/riscv/predicates.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md index 8072d67fbd97..061904b6e000 100644 --- a/gcc/config/riscv/predicates.md +++ b/gcc/config/riscv/predicates.md @@ -27,7 +27,7 @@ (ior (match_operand 0 "const_arith_operand") (match_operand 0 "register_operand"))) -;; REG or REG+D where D fits in a simm12 and has the low 4 bits +;; REG or REG+D where D fits in a simm12 and has the low 5 bits ;; off. The REG+D form can be reloaded into a temporary if needed ;; after FP elimination if that exposes an invalid offset. (define_predicate "prefetch_operand"
[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add comment and reorder the the include files in riscv.md [NFC]
https://gcc.gnu.org/g:64af55c82a125e3fc6b0a601e0e50bbe78f6f6fc
commit 64af55c82a125e3fc6b0a601e0e50bbe78f6f6fc
Author: Kito Cheng
Date: Thu Jun 26 14:26:57 2025 +0800
RISC-V: Add comment and reorder the the include files in riscv.md [NFC]
This patch adds a comment to the riscv.md file to clarify the purpose of
the file and reorders the include files for better organization.
gcc/ChangeLog:
* config/riscv/riscv.md: Add comment and reorder include
files.
(cherry picked from commit 14035a14aac24fb60bf7bbc803d7275fc32fdcae)
Diff:
---
gcc/config/riscv/riscv.md | 19 +++
1 file changed, 11 insertions(+), 8 deletions(-)
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 3406b50518ed..04b8cc92cd60 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -4860,6 +4860,7 @@
{ operands[3] = GEN_INT (BITS_PER_WORD
- exact_log2 (INTVAL (operands[3]) + 1)); })
+;; Standard extensions and pattern for optimization
(include "bitmanip.md")
(include "crypto.md")
(include "sync.md")
@@ -4867,19 +4868,21 @@
(include "sync-ztso.md")
(include "peephole.md")
(include "pic.md")
-(include "generic.md")
-(include "sifive-7.md")
-(include "sifive-p400.md")
-(include "sifive-p600.md")
-(include "thead.md")
-(include "generic-vector-ooo.md")
-(include "generic-ooo.md")
-(include "vector.md")
(include "vector-crypto.md")
(include "vector-bfloat16.md")
(include "zicond.md")
(include "sfb.md")
(include "zc.md")
+(include "vector.md")
+;; Vendor extensions
+(include "thead.md")
(include "corev.md")
+;; Pipeline models
+(include "generic.md")
(include "xiangshan.md")
(include "mips-p8700.md")
+(include "sifive-7.md")
+(include "sifive-p400.md")
+(include "sifive-p600.md")
+(include "generic-vector-ooo.md")
+(include "generic-ooo.md")
[gcc r13-9781] c++: Fix up cp_build_array_ref COND_EXPR handling [PR120471]
https://gcc.gnu.org/g:78ce4720d13b3e82a4c718880a9ca9f0e955cf7e
commit r13-9781-g78ce4720d13b3e82a4c718880a9ca9f0e955cf7e
Author: Jakub Jelinek
Date: Tue Jul 1 15:28:10 2025 +0200
c++: Fix up cp_build_array_ref COND_EXPR handling [PR120471]
The following testcase is miscompiled since the introduction of UBSan,
cp_build_array_ref COND_EXPR handling replaces
(cond ? a : b)[idx] with cond ? a[idx] : b[idx], but if there are
SAVE_EXPRs inside of idx, they will be evaluated just in one of the
branches and the other uses uninitialized temporaries.
Fixed by keeping doing what it did if idx doesn't have side effects
and is invariant. Otherwise if op1/op2 are ARRAY_TYPE arrays with
invariant addresses or pointers with invariant values, use
SAVE_EXPR , SAVE_EXPR , SAVE_EXPR as a new condition
and SAVE_EXPR instead of idx for the recursive calls.
Otherwise punt, but if op1/op2 are ARRAY_TYPE, furthermore call
cp_default_conversion on array, so that COND_EXPR with ARRAY_TYPE doesn't
survive in the IL until expansion.
2025-07-01 Jakub Jelinek
PR c++/120471
gcc/cp/
* typeck.cc (cp_build_array_ref) : If idx is not
INTEGER_CST, don't optimize the case (but cp_default_conversion on
array early if it has ARRAY_TYPE) or use
SAVE_EXPR , SAVE_EXPR , SAVE_EXPR as new op0
depending
on flag_strong_eval_order and whether op1 and op2 are arrays with
invariant address or tree invariant pointers. Formatting fixes.
gcc/testsuite/
* g++.dg/ubsan/pr120471.C: New test.
* g++.dg/parse/pr120471.C: New test.
(cherry picked from commit 988e87b66882875b14a6cab11c17516863c74a63)
Diff:
---
gcc/cp/typeck.cc | 130 --
gcc/testsuite/g++.dg/parse/pr120471.C | 42 +++
gcc/testsuite/g++.dg/ubsan/pr120471.C | 21 ++
3 files changed, 186 insertions(+), 7 deletions(-)
diff --git a/gcc/cp/typeck.cc b/gcc/cp/typeck.cc
index e3bf1c53a9e6..38df8d8e6c2d 100644
--- a/gcc/cp/typeck.cc
+++ b/gcc/cp/typeck.cc
@@ -3961,13 +3961,129 @@ cp_build_array_ref (location_t loc, tree array, tree
idx,
}
case COND_EXPR:
- ret = build_conditional_expr
- (loc, TREE_OPERAND (array, 0),
- cp_build_array_ref (loc, TREE_OPERAND (array, 1), idx,
- complain),
- cp_build_array_ref (loc, TREE_OPERAND (array, 2), idx,
- complain),
- complain);
+ tree op0, op1, op2;
+ op0 = TREE_OPERAND (array, 0);
+ op1 = TREE_OPERAND (array, 1);
+ op2 = TREE_OPERAND (array, 1);
+ if (TREE_SIDE_EFFECTS (idx) || !tree_invariant_p (idx))
+ {
+ /* If idx could possibly have some SAVE_EXPRs, turning
+(op0 ? op1 : op2)[idx] into
+op0 ? op1[idx] : op2[idx] can lead into temporaries
+initialized in one conditional path and uninitialized
+uses of them in the other path.
+And if idx is a really large expression, evaluating it
+twice is also not optimal.
+On the other side, op0 must be sequenced before evaluation
+of op1 and op2 and for C++17 op0, op1 and op2 must be
+sequenced before idx.
+If idx is INTEGER_CST, we can just do the optimization
+without any SAVE_EXPRs, if op1 and op2 are both ARRAY_TYPE
+VAR_DECLs or COMPONENT_REFs thereof (so their address
+is constant or relative to frame), optimize into
+(SAVE_EXPR , SAVE_EXPR , SAVE_EXPR )
+? op1[SAVE_EXPR ] : op2[SAVE_EXPR ]
+Otherwise avoid this optimization. */
+ if (flag_strong_eval_order == 2)
+ {
+ if (TREE_CODE (TREE_TYPE (array)) == ARRAY_TYPE)
+ {
+ tree xop1 = op1;
+ tree xop2 = op2;
+ while (xop1 && handled_component_p (xop1))
+ {
+ switch (TREE_CODE (xop1))
+ {
+ case ARRAY_REF:
+ case ARRAY_RANGE_REF:
+ if (!tree_invariant_p (TREE_OPERAND (xop1, 1))
+ || TREE_OPERAND (xop1, 2) != NULL_TREE
+ || TREE_OPERAND (xop1, 3) != NULL_TREE)
+ {
+ xop1 = NULL_TREE;
+ continue;
+ }
+ break;
+
+ case COMPONENT_REF:
+ if (TREE_OPERAND (xop1, 2) != NULL_TREE)
+ {
+ xop1 = NULL_TREE;
+ continue;
+ }
+ break;
+
+ defaul
[gcc r16-1918] tree-optimization/118669 - fixup wrongly aligned loads/stores
https://gcc.gnu.org/g:37bf13adcda564dfdb28c3aa736f2cac71c73d09
commit r16-1918-g37bf13adcda564dfdb28c3aa736f2cac71c73d09
Author: Richard Biener
Date: Wed Jul 2 09:30:05 2025 +0200
tree-optimization/118669 - fixup wrongly aligned loads/stores
The vectorizer tracks alignment of datarefs with dr_aligned
and dr_unaligned_supported but that's aligned with respect to
the target alignment which can be less aligned than the mode
used for the access. The following fixes this discrepancy
for vectorizing loads and stores. The issue is visible for
aarch64 SVE and risc-v where VLA vector modes have larger than
element alignment but the target handles element alignment
just fine.
PR tree-optimization/118669
* tree-vect-stmts.cc (vectorizable_load): Emit loads
with proper (element) alignment.
(vectorizable_store): Likewise.
Diff:
---
gcc/tree-vect-stmts.cc | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/gcc/tree-vect-stmts.cc b/gcc/tree-vect-stmts.cc
index 69f5f6758a15..95406b4e3a3c 100644
--- a/gcc/tree-vect-stmts.cc
+++ b/gcc/tree-vect-stmts.cc
@@ -9626,7 +9626,8 @@ vectorizable_store (vec_info *vinfo,
data_ref = fold_build2 (MEM_REF, vectype, dataref_ptr,
dataref_offset ? dataref_offset
: build_int_cst (ref_type, 0));
- if (alignment_support_scheme == dr_aligned)
+ if (alignment_support_scheme == dr_aligned
+ && align >= TYPE_ALIGN_UNIT (vectype))
;
else
TREE_TYPE (data_ref)
@@ -11659,7 +11660,8 @@ vectorizable_load (vec_info *vinfo,
{
data_ref = fold_build2 (MEM_REF, ltype,
dataref_ptr, offset);
- if (alignment_support_scheme == dr_aligned)
+ if (alignment_support_scheme == dr_aligned
+ && align >= TYPE_ALIGN_UNIT (ltype))
;
else
TREE_TYPE (data_ref)
[gcc r16-1950] ada: Port System.Stack_Usage to CHERI
https://gcc.gnu.org/g:d22a59c2518e87de41add2d5daf9cf23149fb1a6 commit r16-1950-gd22a59c2518e87de41add2d5daf9cf23149fb1a6 Author: Daniel King Date: Thu Jun 12 10:03:53 2025 +0100 ada: Port System.Stack_Usage to CHERI This unit performed integer to address conversions to calculate stack addresses which, on a CHERI target, result in an invalid capability that triggers a capability tag fault when dereferenced during stack filling. This patch updates the unit to preserve addresses (capabilities) during the calculations. The method used to determine the stack base address is also updated to CHERI. The current method tries to get the stack base from the compiler info for the current task. If no info is found, then as a fallback it estimates the base by taking the address of a variable on the stack. This address is then derived to calculate the range of addresses to fill the stack. This fallback does not work on CHERI since taking the 'Address of a stack variable will result in a capability with bounds restricted to that object and attempting to write outside those bounds triggers a capability bounds fault. Instead, we add a new function Get_Stack_Base which, on CHERI, gets the exact stack base from the upper bound of the capability stack pointer (CSP) register. On non-CHERI platforms, Get_Stack_Base returns the stack base from the compiler info, resulting in the same behaviour as before on those platforms. gcc/ada/ChangeLog: * Makefile.rtl (LIBGNAT_TARGET_PAIRS): New unit s-tsgsba__cheri.adb for morello-freebsd. * libgnarl/s-tassta.adb (Get_Stack_Base): New function. * libgnarl/s-tsgsba__cheri.adb: New file for CHERI targets. * libgnarl/s-tsgsba.adb: New default file for non-CHERI targets. * libgnat/s-stausa.adb (Fill_Stack, Compute_Result): Port to CHERI. * libgnat/s-stausa.ads (Initialize_Analyzer, Stack_Analyzer): Port to CHERI. Diff: --- gcc/ada/Makefile.rtl | 1 + gcc/ada/libgnarl/s-tassta.adb| 18 +++-- gcc/ada/libgnarl/s-tsgsba.adb| 40 + gcc/ada/libgnarl/s-tsgsba__cheri.adb | 49 gcc/ada/libgnat/s-stausa.adb | 41 +++--- gcc/ada/libgnat/s-stausa.ads | 8 +++--- 6 files changed, 130 insertions(+), 27 deletions(-) diff --git a/gcc/ada/Makefile.rtl b/gcc/ada/Makefile.rtl index 8f925fce9e0d..50e683aa80a7 100644 --- a/gcc/ada/Makefile.rtl +++ b/gcc/ada/Makefile.rtl @@ -1854,6 +1854,7 @@ ifeq ($(strip $(filter-out %aarch64 freebsd%,$(target_cpu) $(target_os))),) LIBGNAT_TARGET_PAIRS += \ s-intman.adbhttp://www.gnu.org/licenses/>. -- +-- -- +-- GNARL was developed by the GNARL team at Florida State University. -- +-- Extensive contributions were provided by Ada Core Technologies, Inc. -- +-- -- +-- + +-- This is the default version for most platforms which tries to get the +-- stack base from the compiler info. It returns Null_Address if the stack +-- base is not available. + +separate (System.Tasking.Stages) +function Get_Stack_Base (Self_ID : Task_Id) return System.Address is +begin + return Self_ID.Common.Compiler_Data.Pri_Stack_Info.Base; +end Get_Stack_Base; diff --git a/gcc/ada/libgnarl/s-tsgsba__cheri.adb b/gcc/ada/libgnarl/s-tsgsba__cheri.adb new file mode 100644 index ..5c1783675b42 --- /dev/null +++ b/gcc/ada/libgnarl/s-tsgsba__cheri.adb @@ -0,0 +1,49 @@ +-- +-- -- +-- GNAT RUN-TIME LIBRARY (GNARL) COMPONENTS -- +-- -- +-- S Y S T E M . T A S K I N G . S T A G E S . G E T _ S T A C K _ B A S E -- +-- -- +-- B o d y -- +-- -- +-- Copyright (C) 1992-2025, Free Software Foundation, Inc. -- +-- -- +-- GNARL is free software; you can redistribute it and/or modify it under -- +-- terms of the GNU General Public License as published by the Free Soft- -- +-- ware Foundation; either version 3, or (at your option) any later ver- -- +-- sion. GNAT is distributed in the hope that it will be useful, but WITH- -- +-- OUT ANY WARRANTY;
[gcc r16-1949] ada: Improve retrieval of nominal unconstrained type in extended return
https://gcc.gnu.org/g:4222552aeb313fa40303d122c9cf2fb75299 commit r16-1949-g4222552aeb313fa40303d122c9cf2fb75299 Author: Piotr Trojanek Date: Thu Jun 12 00:47:38 2025 +0200 ada: Improve retrieval of nominal unconstrained type in extended return To reliably retrieve the nominal unconstrained type of object declared in extended return statement we need to rely on the Original_Node. gcc/ada/ChangeLog: * sem_ch3.adb (Check_Return_Subtype_Indication): Use Original_Node. Diff: --- gcc/ada/sem_ch3.adb | 6 +- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/gcc/ada/sem_ch3.adb b/gcc/ada/sem_ch3.adb index f25941d72a83..5354d82bd7da 100644 --- a/gcc/ada/sem_ch3.adb +++ b/gcc/ada/sem_ch3.adb @@ -4204,11 +4204,7 @@ package body Sem_Ch3 is -- to recover the nominal unconstrained type. if Is_Constr_Subt_For_U_Nominal (Obj_Typ) then -if Nkind (Object_Definition (Obj_Decl)) = N_Subtype_Indication then - Obj_Typ := Entity (Subtype_Mark (Object_Definition (Obj_Decl))); -else - Obj_Typ := Etype (Obj_Typ); -end if; +Obj_Typ := Entity (Original_Node (Object_Definition (Obj_Decl))); pragma Assert (not Is_Constrained (Obj_Typ)); end if;
[gcc r16-1952] ada: Make comment more precise
https://gcc.gnu.org/g:6e22849641d3fcfa6af3fac1e9117b684d6546ec commit r16-1952-g6e22849641d3fcfa6af3fac1e9117b684d6546ec Author: Ronan Desplanques Date: Fri Jun 13 10:34:50 2025 +0200 ada: Make comment more precise gcc/ada/ChangeLog: * exp_ch6.adb (Expand_Ctrl_Function_Call): Precisify comment. Diff: --- gcc/ada/exp_ch6.adb | 9 + 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/gcc/ada/exp_ch6.adb b/gcc/ada/exp_ch6.adb index e9a73e16b07e..c24c8c63ef1f 100644 --- a/gcc/ada/exp_ch6.adb +++ b/gcc/ada/exp_ch6.adb @@ -287,10 +287,11 @@ package body Exp_Ch6 is -- This expansion is necessary in all the cases where the constant object -- denoted by the call needs finalization in the current subprogram, which - -- excludes return statements, and is not identified with another object - -- that will be finalized, which excludes (statically) declared objects, - -- dynamically allocated objects, components of aggregates, and targets of - -- assignments that are done directly (without intermediate temporaries). + -- excludes simple return statements, and is not identified with another + -- object that will be finalized, which excludes (statically) declared + -- objects, dynamically allocated objects, components of aggregates, and + -- targets of assignments that are done directly (without intermediate + -- temporaries). procedure Expand_Non_Function_Return (N : Node_Id); -- Expand a simple return statement found in a procedure body, entry body,
[gcc r16-1951] ada: Fix missing finalization with conditional expression in extended return
https://gcc.gnu.org/g:448e857b977ef673fa8a28d24dcd4567f4d5d0cd commit r16-1951-g448e857b977ef673fa8a28d24dcd4567f4d5d0cd Author: Eric Botcazou Date: Thu Jun 12 21:58:49 2025 +0200 ada: Fix missing finalization with conditional expression in extended return Declarations of return objects are not (yet) distributed into the dependent expressions of conditional expressions. gcc/ada/ChangeLog: * exp_ch6.adb (Expand_Ctrl_Function_Call): Do not bail out for the declarations of return objects. Diff: --- gcc/ada/exp_ch6.adb | 7 ++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/gcc/ada/exp_ch6.adb b/gcc/ada/exp_ch6.adb index 72d00bcb3189..e9a73e16b07e 100644 --- a/gcc/ada/exp_ch6.adb +++ b/gcc/ada/exp_ch6.adb @@ -5387,8 +5387,13 @@ package body Exp_Ch6 is -- Note that object declarations are also distributed into conditional -- expressions, but we may be invoked before this distribution is done. + -- However that's not the case for the declarations of return objects, + -- see the twin Is_Optimizable_Declaration predicates that are present + -- in Expand_N_Case_Expression and Expand_N_If_Expression of Exp_Ch4. - elsif Nkind (Uncond_Par) = N_Object_Declaration then + elsif Nkind (Uncond_Par) = N_Object_Declaration +and then not Is_Return_Object (Defining_Identifier (Uncond_Par)) + then return; end if;
[gcc r16-1955] ada: Fix check for elaboration order on subprogram body stubs
https://gcc.gnu.org/g:251dab8bc9a596f094149e256f0d216cc5b1a60a commit r16-1955-g251dab8bc9a596f094149e256f0d216cc5b1a60a Author: Piotr Trojanek Date: Mon Jun 16 16:13:03 2025 +0200 ada: Fix check for elaboration order on subprogram body stubs Fix an assertion failure occurring when elaboration checks were applied to subprogram with a separate body. gcc/ada/ChangeLog: * sem_elab.adb (Check_Overriding_Primitive): Find early call region of the subprogram body declaration, not of the subprogram body stub. Diff: --- gcc/ada/sem_elab.adb | 10 +- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/gcc/ada/sem_elab.adb b/gcc/ada/sem_elab.adb index 6547813a8e2e..77b1e120b800 100644 --- a/gcc/ada/sem_elab.adb +++ b/gcc/ada/sem_elab.adb @@ -15236,7 +15236,15 @@ package body Sem_Elab is end if; Body_Decl := Unit_Declaration_Node (Body_Id); -Region:= Find_Early_Call_Region (Body_Decl); + +-- For subprogram bodies in subunits we check where the subprogram +-- body stub is declared. + +if Nkind (Parent (Body_Decl)) = N_Subunit then + Body_Decl := Corresponding_Stub (Parent (Body_Decl)); +end if; + +Region := Find_Early_Call_Region (Body_Decl); -- The freeze node appears prior to the early call region of the -- primitive body.
[gcc r16-1956] ada: Fix missing error on too large Component_Size not multiple of storage unit
https://gcc.gnu.org/g:fd092906db6823c4fb55db7e07b07d71c75d0b01
commit r16-1956-gfd092906db6823c4fb55db7e07b07d71c75d0b01
Author: Eric Botcazou
Date: Fri May 2 01:30:56 2025 +0200
ada: Fix missing error on too large Component_Size not multiple of storage
unit
This is a small regression introduced a few years ago.
gcc/ada/ChangeLog:
* gcc-interface/decl.cc (gnat_to_gnu_component_type): Validate the
Component_Size like the size of a type only if the component type
is actually packed.
Diff:
---
gcc/ada/gcc-interface/decl.cc | 16 +++-
1 file changed, 11 insertions(+), 5 deletions(-)
diff --git a/gcc/ada/gcc-interface/decl.cc b/gcc/ada/gcc-interface/decl.cc
index 972607a917b0..1d9832d69ad4 100644
--- a/gcc/ada/gcc-interface/decl.cc
+++ b/gcc/ada/gcc-interface/decl.cc
@@ -5444,7 +5444,7 @@ gnat_to_gnu_component_type (Entity_Id gnat_array, bool
definition,
const bool is_bit_packed = Is_Bit_Packed_Array (gnat_array);
tree gnu_type = gnat_to_gnu_type (gnat_type);
tree gnu_comp_size;
- bool has_packed_components;
+ bool has_packed_component;
unsigned int max_align;
/* If an alignment is specified, use it as a cap on the component type
@@ -5465,16 +5465,22 @@ gnat_to_gnu_component_type (Entity_Id gnat_array, bool
definition,
&& !TYPE_FAT_POINTER_P (gnu_type)
&& tree_fits_uhwi_p (TYPE_SIZE (gnu_type)))
{
- gnu_type = make_packable_type (gnu_type, false, max_align);
- has_packed_components = true;
+ tree gnu_packable_type = make_packable_type (gnu_type, false, max_align);
+ if (gnu_packable_type != gnu_type)
+ {
+ gnu_type = gnu_packable_type;
+ has_packed_component = true;
+ }
+ else
+ has_packed_component = false;
}
else
-has_packed_components = is_bit_packed;
+has_packed_component = is_bit_packed;
/* Get and validate any specified Component_Size. */
gnu_comp_size
= validate_size (Component_Size (gnat_array), gnu_type, gnat_array,
-has_packed_components ? TYPE_DECL : VAR_DECL, true,
+has_packed_component ? TYPE_DECL : VAR_DECL, true,
Has_Component_Size_Clause (gnat_array), NULL, NULL);
/* If the component type is a RECORD_TYPE that has a self-referential size,
[gcc r16-1954] ada: More Tbuild cleanup
https://gcc.gnu.org/g:aada6d75fe6392475c2abc02f5725690edc420cc commit r16-1954-gaada6d75fe6392475c2abc02f5725690edc420cc Author: Bob Duff Date: Mon Jun 16 11:03:22 2025 -0400 ada: More Tbuild cleanup Remove "Nmake_Assert => ..." on N_Unchecked_Type_Conversion at gen_il-gen-gen_nodes.adb:473 (was disabled). This was left over from commit 82a794419a00ea98b68d69b64363ae6746710de9 "Tbuild cleanup". In addition, the checks for "Is_Composite_Type" in Tbuild.Unchecked_Convert_To are narrowed to "not Is_Scalar_Type"; that way, useless duplicate unchecked conversions of access types will be removed as for composite types. gcc/ada/ChangeLog: * gen_il-gen-gen_nodes.adb (N_Unchecked_Type_Conversion): Remove useless Nmake_Assert. * tbuild.adb (Unchecked_Convert_To): Narrow the bitfield-related conditions. Diff: --- gcc/ada/gen_il-gen-gen_nodes.adb | 7 +-- gcc/ada/tbuild.adb | 6 +++--- 2 files changed, 4 insertions(+), 9 deletions(-) diff --git a/gcc/ada/gen_il-gen-gen_nodes.adb b/gcc/ada/gen_il-gen-gen_nodes.adb index debc66b0fcd6..f4e79173502c 100644 --- a/gcc/ada/gen_il-gen-gen_nodes.adb +++ b/gcc/ada/gen_il-gen-gen_nodes.adb @@ -469,12 +469,7 @@ begin -- Gen_IL.Gen.Gen_Nodes (Sy (Subtype_Mark, Node_Id, Default_Empty), Sy (Expression, Node_Id, Default_Empty), Sm (Kill_Range_Check, Flag), -Sm (No_Truncation, Flag)), - Nmake_Assert => "True or else Nkind (Expression) /= N_Unchecked_Type_Conversion"); --- Nmake_Assert => "Nkind (Expression) /= N_Unchecked_Type_Conversion"); - -- Assert that we don't have unchecked conversions of unchecked - -- conversions; if Expression might be an unchecked conversion, - -- then Tbuild.Unchecked_Convert_To should be used. +Sm (No_Truncation, Flag))); Cc (N_Subtype_Indication, N_Has_Etype, (Sy (Subtype_Mark, Node_Id, Default_Empty), diff --git a/gcc/ada/tbuild.adb b/gcc/ada/tbuild.adb index 52fdbfc2163f..b89c40851bc1 100644 --- a/gcc/ada/tbuild.adb +++ b/gcc/ada/tbuild.adb @@ -926,11 +926,11 @@ package body Tbuild is -- conversion of an unchecked conversion. Extra unchecked conversions -- make the .dg output less readable. We can't do this in cases -- involving bitfields, because the sizes might not match. The - -- Is_Composite_Type checks avoid such cases. + -- "not Is_Scalar_Type" checks avoid such cases. elsif Nkind (Expr) = N_Unchecked_Type_Conversion -and then Is_Composite_Type (Etype (Expr)) -and then Is_Composite_Type (Typ) +and then not Is_Scalar_Type (Etype (Expr)) +and then not Is_Scalar_Type (Typ) then Set_Subtype_Mark (Expr, New_Occurrence_Of (Typ, Loc)); Result := Relocate_Node (Expr);
[gcc r16-1960] ada: Fix poor code generated for return of Out parameter with access type
https://gcc.gnu.org/g:3d4073371168cf5e9f58d18f617b117fb5839f81 commit r16-1960-g3d4073371168cf5e9f58d18f617b117fb5839f81 Author: Eric Botcazou Date: Fri Jun 13 09:51:52 2025 +0200 ada: Fix poor code generated for return of Out parameter with access type The record type of the return object is unnecessarily given BLKmode. gcc/ada/ChangeLog: * gcc-interface/decl.cc (type_contains_only_integral_data): Do not return false only because the type contains pointer data. Diff: --- gcc/ada/gcc-interface/decl.cc | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/gcc/ada/gcc-interface/decl.cc b/gcc/ada/gcc-interface/decl.cc index 27d2cea1f3d2..903ec844b968 100644 --- a/gcc/ada/gcc-interface/decl.cc +++ b/gcc/ada/gcc-interface/decl.cc @@ -6022,7 +6022,8 @@ gnat_to_gnu_profile_type (Entity_Id gnat_type) return gnu_type; } -/* Return true if TYPE contains only integral data, recursively if need be. */ +/* Return true if TYPE contains only integral data, recursively if need be. + (integral data is to be understood as not floating-point data here). */ static bool type_contains_only_integral_data (tree type) @@ -6042,7 +6043,7 @@ type_contains_only_integral_data (tree type) return type_contains_only_integral_data (TREE_TYPE (type)); default: - return INTEGRAL_TYPE_P (type); + return INTEGRAL_TYPE_P (type) || POINTER_TYPE_P (type); } gcc_unreachable ();
[gcc r16-1953] ada: Refine sanity check in Insert_Actions
https://gcc.gnu.org/g:06c077d97a19a80ab4f1f9ccd6d058b34014ec87 commit r16-1953-g06c077d97a19a80ab4f1f9ccd6d058b34014ec87 Author: Ronan Desplanques Date: Tue Jun 10 12:51:26 2025 +0200 ada: Refine sanity check in Insert_Actions Insert_Actions performs a sanity check when it goes through an expression with actions while going up the three. That check was not perfectly right before this patch and spuriously failed when inserting range checks in some situation. This patch makes the check more robust. gcc/ada/ChangeLog: * exp_util.adb (Insert_Actions): Fix check. Diff: --- gcc/ada/exp_util.adb | 22 +++--- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/gcc/ada/exp_util.adb b/gcc/ada/exp_util.adb index 90778910e997..4f9877904052 100644 --- a/gcc/ada/exp_util.adb +++ b/gcc/ada/exp_util.adb @@ -8167,21 +8167,21 @@ package body Exp_Util is -- never climb up as far as the N_Expression_With_Actions itself. when N_Expression_With_Actions => - if N = Expression (P) then - if Is_Empty_List (Actions (P)) then - Append_List_To (Actions (P), Ins_Actions); - Analyze_List (Actions (P)); - else - Insert_List_After_And_Analyze - (Last (Actions (P)), Ins_Actions); - end if; - - return; + if Is_List_Member (N) and then List_Containing (N) = Actions (P) + then + raise Program_Error; + end if; + if Is_Empty_List (Actions (P)) then + Append_List_To (Actions (P), Ins_Actions); + Analyze_List (Actions (P)); else - raise Program_Error; + Insert_List_After_And_Analyze +(Last (Actions (P)), Ins_Actions); end if; + return; + -- Case of appearing in the condition of a while expression or -- elsif. We insert the actions into the Condition_Actions field. -- They will be moved further out when the while loop or elsif
[gcc r16-1957] ada: Fix wrong finalization of constrained subtype of unconstrained array type
https://gcc.gnu.org/g:546ca0115de5cfe2546c260350b275a368065799
commit r16-1957-g546ca0115de5cfe2546c260350b275a368065799
Author: Eric Botcazou
Date: Tue May 6 19:14:40 2025 +0200
ada: Fix wrong finalization of constrained subtype of unconstrained array
type
This implements the Is_Constr_Array_Subt_With_Bounds flag for allocators.
gcc/ada/ChangeLog:
* gcc-interface/trans.cc (gnat_to_gnu) : Allocate the
bounds alongside the data if the Is_Constr_Array_Subt_With_Bounds
flag is set on the designated type.
: Take into account the allocated bounds if the
Is_Constr_Array_Subt_With_Bounds flag is set on the designated type.
Diff:
---
gcc/ada/gcc-interface/trans.cc | 38 --
1 file changed, 32 insertions(+), 6 deletions(-)
diff --git a/gcc/ada/gcc-interface/trans.cc b/gcc/ada/gcc-interface/trans.cc
index 23fc814f9dec..7549b8e37bfd 100644
--- a/gcc/ada/gcc-interface/trans.cc
+++ b/gcc/ada/gcc-interface/trans.cc
@@ -7590,6 +7590,10 @@ gnat_to_gnu (Node_Id gnat_node)
case N_Allocator:
{
+ const Entity_Id gnat_desig_type
+ = Designated_Type (Underlying_Type (Etype (gnat_node)));
+ const Entity_Id gnat_pool = Storage_Pool (gnat_node);
+
tree gnu_type, gnu_init;
bool ignore_init_type;
@@ -7608,9 +7612,6 @@ gnat_to_gnu (Node_Id gnat_node)
else if (Nkind (gnat_temp) == N_Qualified_Expression)
{
- const Entity_Id gnat_desig_type
- = Designated_Type (Underlying_Type (Etype (gnat_node)));
-
ignore_init_type = Has_Constrained_Partial_View (gnat_desig_type);
gnu_init = gnat_to_gnu (Expression (gnat_temp));
@@ -7637,11 +7638,24 @@ gnat_to_gnu (Node_Id gnat_node)
else
gcc_unreachable ();
- gnu_result_type = get_unpadded_type (Etype (gnat_node));
+ /* If this is an array allocated with its bounds, use the thin pointer
+ as the result type to trigger the machinery in build_allocator, but
+ make sure not to do it for allocations on the return and secondary
+ stacks (see build_call_alloc_dealloc_proc for more details). */
+if (Is_Constr_Array_Subt_With_Bounds (gnat_desig_type)
+ && Is_Record_Type (Underlying_Type (Etype (gnat_pool)))
+ && !type_annotate_only)
+ {
+ tree gnu_array = gnat_to_gnu_type (Base_Type (gnat_desig_type));
+ gnu_result_type
+ = build_pointer_type (TYPE_OBJECT_RECORD_TYPE (gnu_array));
+ }
+ else
+ gnu_result_type = get_unpadded_type (Etype (gnat_node));
+
return build_allocator (gnu_type, gnu_init, gnu_result_type,
Procedure_To_Call (gnat_node),
- Storage_Pool (gnat_node), gnat_node,
- ignore_init_type);
+ gnat_pool, gnat_node, ignore_init_type);
}
break;
@@ -8577,6 +8591,18 @@ gnat_to_gnu (Node_Id gnat_node)
(void) gnat_to_gnu_entity (gnat_desig_type, NULL_TREE, false);
gnu_ptr = gnat_to_gnu (gnat_temp);
+
+ /* If this is an array allocated with its bounds, first convert to
+the thin pointer to trigger the special machinery below. */
+ if (Is_Constr_Array_Subt_With_Bounds (gnat_desig_type))
+ {
+ tree gnu_array = gnat_to_gnu_type (Base_Type (gnat_desig_type));
+ gnu_ptr
+ = convert (build_pointer_type
+ (TYPE_OBJECT_RECORD_TYPE (gnu_array)),
+ gnu_ptr);
+ }
+
gnu_ptr_type = TREE_TYPE (gnu_ptr);
/* If this is a thin pointer, we must first dereference it to create
[gcc r16-1958] ada: Fix alignment violation for mix of aligned and misaligned composite types
https://gcc.gnu.org/g:802efae1403365775591cc4ea6cf93f0b02d8459
commit r16-1958-g802efae1403365775591cc4ea6cf93f0b02d8459
Author: Eric Botcazou
Date: Mon May 26 09:25:57 2025 +0200
ada: Fix alignment violation for mix of aligned and misaligned composite
types
This happens when the chain of initialization procedures is called on the
subcomponents and causes the creation of temporaries along the way out of
alignment considerations. Now these temporaries are not necessary in the
context and were not created until recently, so this gets rid of them.
gcc/ada/ChangeLog:
* gcc-interface/trans.cc (addressable_p): Add COMPG third parameter.
: Do not return true out of alignment considerations
for non-strict-alignment targets if COMPG is set.
(Call_to_gnu): Pass true as COMPG in the call to the addressable_p
predicate if the called subprogram is an initialization procedure.
Diff:
---
gcc/ada/gcc-interface/trans.cc | 41 +++--
1 file changed, 23 insertions(+), 18 deletions(-)
diff --git a/gcc/ada/gcc-interface/trans.cc b/gcc/ada/gcc-interface/trans.cc
index 7549b8e37bfd..e02804b75af1 100644
--- a/gcc/ada/gcc-interface/trans.cc
+++ b/gcc/ada/gcc-interface/trans.cc
@@ -257,7 +257,7 @@ static tree emit_check (tree, tree, int, Node_Id);
static tree build_unary_op_trapv (enum tree_code, tree, tree, Node_Id);
static tree build_binary_op_trapv (enum tree_code, tree, tree, tree, Node_Id);
static tree convert_with_check (Entity_Id, tree, bool, bool, Node_Id);
-static bool addressable_p (tree, tree);
+static bool addressable_p (tree, tree, bool);
static bool aliasable_p (tree, tree);
static tree assoc_to_constructor (Entity_Id, Node_Id, tree);
static tree pos_to_constructor (Node_Id, tree);
@@ -4876,6 +4876,8 @@ Call_to_gnu (Node_Id gnat_node, tree *gnu_result_type_p,
tree gnu_target,
tree gnu_formal = present_gnu_tree (gnat_formal)
? get_gnu_tree (gnat_formal) : NULL_TREE;
tree gnu_actual_type = gnat_to_gnu_type (Etype (gnat_actual));
+ const bool is_init_proc
+ = Is_Entity_Name (gnat_subprog) && Is_Init_Proc (Entity (gnat_subprog));
const bool in_param = (Ekind (gnat_formal) == E_In_Parameter);
const bool is_true_formal_parm
= gnu_formal && TREE_CODE (gnu_formal) == PARM_DECL;
@@ -4925,7 +4927,7 @@ Call_to_gnu (Node_Id gnat_node, tree *gnu_result_type_p,
tree gnu_target,
copy to avoid breaking strict aliasing rules. */
if (is_by_ref_formal_parm
&& (gnu_name_type = gnat_to_gnu_type (Etype (gnat_name)))
- && (!addressable_p (gnu_name, gnu_name_type)
+ && (!addressable_p (gnu_name, gnu_name_type, is_init_proc)
|| (node_is_type_conversion (gnat_actual)
&& (aliasing = !aliasable_p (gnu_name, gnu_actual_type)
{
@@ -5051,9 +5053,7 @@ Call_to_gnu (Node_Id gnat_node, tree *gnu_result_type_p,
tree gnu_target,
/* Do not initialize it for the _Init parameter of an initialization
procedure since no data is meant to be passed in. */
- if (Ekind (gnat_formal) == E_Out_Parameter
- && Is_Entity_Name (gnat_subprog)
- && Is_Init_Proc (Entity (gnat_subprog)))
+ if (Ekind (gnat_formal) == E_Out_Parameter && is_init_proc)
gnu_name = gnu_temp = create_temporary ("A", TREE_TYPE (gnu_name));
/* Initialize it on the fly like for an implicit temporary in the
@@ -10379,7 +10379,8 @@ convert_with_check (Entity_Id gnat_type, tree gnu_expr,
bool overflow_p,
unless it is an expression involving computation or if it involves a
reference to a bitfield or to an object not sufficiently aligned for
its type. If GNU_TYPE is non-null, return true only if GNU_EXPR can
- be directly addressed as an object of this type.
+ be directly addressed as an object of this type. COMPG is true when
+ the predicate is invoked for compiler-generated code.
*** Notes on addressability issues in the Ada compiler ***
@@ -10436,7 +10437,7 @@ convert_with_check (Entity_Id gnat_type, tree gnu_expr,
bool overflow_p,
generated to connect everything together. */
static bool
-addressable_p (tree gnu_expr, tree gnu_type)
+addressable_p (tree gnu_expr, tree gnu_type, bool compg)
{
/* For an integral type, the size of the actual type of the object may not
be greater than that of the expected type, otherwise an indirect access
@@ -10497,13 +10498,13 @@ addressable_p (tree gnu_expr, tree gnu_type)
case COMPOUND_EXPR:
/* The address of a compound expression is that of its 2nd operand. */
- return addressable_p (TREE_OPERAND (gnu_expr, 1), gnu_type);
+ return addressable_p (TREE_OPERAND (gnu_expr, 1), gnu_type, compg);
case COND_EXPR:
/* We accept &COND_EXPR as soon as both operands are addressable and
expec
[gcc r16-1959] ada: Enforce alignment constraint for large Object_Size clauses
https://gcc.gnu.org/g:8fe64e4d9cd22f7638fc590353c34c79b07f428f
commit r16-1959-g8fe64e4d9cd22f7638fc590353c34c79b07f428f
Author: Eric Botcazou
Date: Thu Jun 12 22:31:06 2025 +0200
ada: Enforce alignment constraint for large Object_Size clauses
The constraint is that the Object_Size must be a multiple of the alignment
in bits. But it's enforced only when the value of the clause is lower than
the Value_Size rounded up to the alignment in bits, not for larger values.
gcc/ada/ChangeLog:
* gcc-interface/decl.cc (gnat_to_gnu_entity): Use default messages
for errors reported for Object_Size clauses.
(validate_size): Give an error for stand-alone objects of composite
types if the specified size is not a multiple of the alignment.
Diff:
---
gcc/ada/gcc-interface/decl.cc | 16 +++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff --git a/gcc/ada/gcc-interface/decl.cc b/gcc/ada/gcc-interface/decl.cc
index 1d9832d69ad4..27d2cea1f3d2 100644
--- a/gcc/ada/gcc-interface/decl.cc
+++ b/gcc/ada/gcc-interface/decl.cc
@@ -4502,7 +4502,7 @@ gnat_to_gnu_entity (Entity_Id gnat_entity, tree gnu_expr,
bool definition)
if (Known_Esize (gnat_entity))
gnu_size
= validate_size (Esize (gnat_entity), gnu_type, gnat_entity,
- VAR_DECL, false, false, size_s, type_s);
+ VAR_DECL, false, false, NULL, NULL);
/* ??? The test on Has_Size_Clause must be removed when "unknown" is
no longer represented as Uint_0 (i.e. Use_New_Unknown_Rep). */
@@ -9696,6 +9696,20 @@ validate_size (Uint uint_size, tree gnu_type, Entity_Id
gnat_object,
return NULL_TREE;
}
+ /* The size of stand-alone objects is always a multiple of the alignment,
+ but that's already enforced for elementary types by the front-end. */
+ if (kind == VAR_DECL
+ && !component_p
+ && RECORD_OR_UNION_TYPE_P (gnu_type)
+ && !TYPE_FAT_POINTER_P (gnu_type)
+ && !integer_zerop (size_binop (TRUNC_MOD_EXPR, size,
+bitsize_int (TYPE_ALIGN (gnu_type)
+{
+ post_error_ne_num ("size for& must be multiple of alignment ^",
+gnat_error_node, gnat_object, TYPE_ALIGN (gnu_type));
+ return NULL_TREE;
+}
+
return size;
}
[gcc r16-1968] Fix division by zero in ipa-cp.cc:update_profiling_info
https://gcc.gnu.org/g:a52484f1ac34dbb604dc862407d9abb32df444dd
commit r16-1968-ga52484f1ac34dbb604dc862407d9abb32df444dd
Author: Jan Hubicka
Date: Thu Jul 3 11:56:28 2025 +0200
Fix division by zero in ipa-cp.cc:update_profiling_info
This ICE has triggered for me during autoprofiledbootstrap. The
code already takes into care possible range, so I think in this case
we can just push to one side of it.
Bootstrapped/regtesed x86_64-linux, OK?
gcc/ChangeLog:
* ipa-cp.cc (update_profiling_info): Watch for division by zero.
Diff:
---
gcc/ipa-cp.cc | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/gcc/ipa-cp.cc b/gcc/ipa-cp.cc
index 901d4a5616e9..480cf48786c7 100644
--- a/gcc/ipa-cp.cc
+++ b/gcc/ipa-cp.cc
@@ -4838,11 +4838,12 @@ update_profiling_info (struct cgraph_node *orig_node,
profile_count unexp = orig_node_count - new_sum - orig_nonrec_call_count;
int limit_den = 2 * (orig_nonrec_calls + new_nonrec_calls);
- profile_count new_part
- = MAX(MIN (unexp.apply_scale (new_sum,
- new_sum + orig_nonrec_call_count),
- unexp.apply_scale (limit_den - 1, limit_den)),
- unexp.apply_scale (new_nonrec_calls, limit_den));
+ profile_count new_part = unexp.apply_scale (limit_den - 1, limit_den);
+ profile_count den = new_sum + orig_nonrec_call_count;
+ if (den.nonzero_p ())
+ new_part = MIN (unexp.apply_scale (new_sum, den), new_part);
+ new_part = MAX (new_part,
+ unexp.apply_scale (new_nonrec_calls, limit_den));
if (dump_file)
{
fprintf (dump_file, " Claiming ");
[gcc r15-9920] c++: Fix a pasto in the PR120471 fix [PR120940]
https://gcc.gnu.org/g:f9c43140bee94587cd60c8476db8c0e699206841
commit r15-9920-gf9c43140bee94587cd60c8476db8c0e699206841
Author: Jakub Jelinek
Date: Thu Jul 3 22:39:39 2025 +0200
c++: Fix a pasto in the PR120471 fix [PR120940]
No idea how this slipped in, I'm terribly sorry.
Strangely nothing in the testsuite has caught this, so I've added
a new test for that.
2025-07-03 Jakub Jelinek
PR c++/120940
* typeck.cc (cp_build_array_ref): Fix a pasto.
* g++.dg/parse/pr120940.C: New test.
* g++.dg/warn/Wduplicated-branches9.C: New test.
(cherry picked from commit dc90649466a54ab61926d88500a05f59a55cb055)
Diff:
---
gcc/cp/typeck.cc | 2 +-
gcc/testsuite/g++.dg/parse/pr120940.C | 18 ++
gcc/testsuite/g++.dg/warn/Wduplicated-branches9.C | 11 +++
3 files changed, 30 insertions(+), 1 deletion(-)
diff --git a/gcc/cp/typeck.cc b/gcc/cp/typeck.cc
index b43e449413b2..fb5b04f28e86 100644
--- a/gcc/cp/typeck.cc
+++ b/gcc/cp/typeck.cc
@@ -4002,7 +4002,7 @@ cp_build_array_ref (location_t loc, tree array, tree idx,
tree op0, op1, op2;
op0 = TREE_OPERAND (array, 0);
op1 = TREE_OPERAND (array, 1);
- op2 = TREE_OPERAND (array, 1);
+ op2 = TREE_OPERAND (array, 2);
if (TREE_SIDE_EFFECTS (idx) || !tree_invariant_p (idx))
{
/* If idx could possibly have some SAVE_EXPRs, turning
diff --git a/gcc/testsuite/g++.dg/parse/pr120940.C
b/gcc/testsuite/g++.dg/parse/pr120940.C
new file mode 100644
index ..5da36b2f88a0
--- /dev/null
+++ b/gcc/testsuite/g++.dg/parse/pr120940.C
@@ -0,0 +1,18 @@
+// PR c++/120940
+// { dg-do run }
+
+int a[8] = { 1, 2, 3, 4, 5, 6, 7, 8 };
+int b[8] = { 9, 10, 11, 12, 13, 14, 15, 16 };
+
+__attribute__((noipa)) int
+foo (int x, int y)
+{
+ return (x ? a : b)[y];
+}
+
+int
+main ()
+{
+ if (foo (1, 4) != 5 || foo (0, 6) != 15)
+__builtin_abort ();
+}
diff --git a/gcc/testsuite/g++.dg/warn/Wduplicated-branches9.C
b/gcc/testsuite/g++.dg/warn/Wduplicated-branches9.C
new file mode 100644
index ..f9fafcd467b4
--- /dev/null
+++ b/gcc/testsuite/g++.dg/warn/Wduplicated-branches9.C
@@ -0,0 +1,11 @@
+// PR c++/120940
+// { dg-do compile }
+// { dg-options "-Wduplicated-branches" }
+
+static char a[16][8], b[16][8];
+
+char *
+foo (int x, int y)
+{
+ return (x ? a : b)[y];
+}
[gcc r14-11876] c++: Fix a pasto in the PR120471 fix [PR120940]
https://gcc.gnu.org/g:f3db50e3a41af53f87e94cd31e86f63126b8
commit r14-11876-gf3db50e3a41af53f87e94cd31e86f63126b8
Author: Jakub Jelinek
Date: Thu Jul 3 22:39:39 2025 +0200
c++: Fix a pasto in the PR120471 fix [PR120940]
No idea how this slipped in, I'm terribly sorry.
Strangely nothing in the testsuite has caught this, so I've added
a new test for that.
2025-07-03 Jakub Jelinek
PR c++/120940
* typeck.cc (cp_build_array_ref): Fix a pasto.
* g++.dg/parse/pr120940.C: New test.
* g++.dg/warn/Wduplicated-branches9.C: New test.
(cherry picked from commit dc90649466a54ab61926d88500a05f59a55cb055)
Diff:
---
gcc/cp/typeck.cc | 2 +-
gcc/testsuite/g++.dg/parse/pr120940.C | 18 ++
gcc/testsuite/g++.dg/warn/Wduplicated-branches9.C | 11 +++
3 files changed, 30 insertions(+), 1 deletion(-)
diff --git a/gcc/cp/typeck.cc b/gcc/cp/typeck.cc
index 93c69c5ebad7..b97caeea6437 100644
--- a/gcc/cp/typeck.cc
+++ b/gcc/cp/typeck.cc
@@ -3970,7 +3970,7 @@ cp_build_array_ref (location_t loc, tree array, tree idx,
tree op0, op1, op2;
op0 = TREE_OPERAND (array, 0);
op1 = TREE_OPERAND (array, 1);
- op2 = TREE_OPERAND (array, 1);
+ op2 = TREE_OPERAND (array, 2);
if (TREE_SIDE_EFFECTS (idx) || !tree_invariant_p (idx))
{
/* If idx could possibly have some SAVE_EXPRs, turning
diff --git a/gcc/testsuite/g++.dg/parse/pr120940.C
b/gcc/testsuite/g++.dg/parse/pr120940.C
new file mode 100644
index ..5da36b2f88a0
--- /dev/null
+++ b/gcc/testsuite/g++.dg/parse/pr120940.C
@@ -0,0 +1,18 @@
+// PR c++/120940
+// { dg-do run }
+
+int a[8] = { 1, 2, 3, 4, 5, 6, 7, 8 };
+int b[8] = { 9, 10, 11, 12, 13, 14, 15, 16 };
+
+__attribute__((noipa)) int
+foo (int x, int y)
+{
+ return (x ? a : b)[y];
+}
+
+int
+main ()
+{
+ if (foo (1, 4) != 5 || foo (0, 6) != 15)
+__builtin_abort ();
+}
diff --git a/gcc/testsuite/g++.dg/warn/Wduplicated-branches9.C
b/gcc/testsuite/g++.dg/warn/Wduplicated-branches9.C
new file mode 100644
index ..f9fafcd467b4
--- /dev/null
+++ b/gcc/testsuite/g++.dg/warn/Wduplicated-branches9.C
@@ -0,0 +1,11 @@
+// PR c++/120940
+// { dg-do compile }
+// { dg-options "-Wduplicated-branches" }
+
+static char a[16][8], b[16][8];
+
+char *
+foo (int x, int y)
+{
+ return (x ? a : b)[y];
+}
[gcc r14-11875] Ada: Remove left-overs of front-end exception mechanism
https://gcc.gnu.org/g:a9b70e4c95c8881520b789c76169e5f8a7f385cc commit r14-11875-ga9b70e4c95c8881520b789c76169e5f8a7f385cc Author: Eric Botcazou Date: Thu Jul 3 20:02:43 2025 +0200 Ada: Remove left-overs of front-end exception mechanism It was removed from the compiler a few releases ago. gcc/ada/ * gcc-interface/Makefile.in (gnatlib-sjlj): Delete. (gnatlib-zcx): Do not modify Frontend_Exceptions constant. * libgnat/system-linux-loongarch.ads (Frontend_Exceptions): Delete. Diff: --- gcc/ada/gcc-interface/Makefile.in | 30 -- gcc/ada/libgnat/system-linux-loongarch.ads | 1 - 2 files changed, 31 deletions(-) diff --git a/gcc/ada/gcc-interface/Makefile.in b/gcc/ada/gcc-interface/Makefile.in index 0666fc00bb83..c1a6bbbf5b5f 100644 --- a/gcc/ada/gcc-interface/Makefile.in +++ b/gcc/ada/gcc-interface/Makefile.in @@ -822,35 +822,6 @@ gnatlib-shared: PICFLAG_FOR_TARGET="$(PICFLAG_FOR_TARGET)" \ $(GNATLIB_SHARED) -# When building a SJLJ runtime for VxWorks, we need to ensure that the extra -# linker options needed for ZCX are not passed to prevent the inclusion of -# useless objects and potential troubles from the presence of extra symbols -# and references in some configurations. The inhibition is performed by -# commenting the pragma instead of deleting the line, as the latter might -# result in getting multiple blank lines, hence possible style check errors. -gnatlib-sjlj: - $(MAKE) $(FLAGS_TO_PASS) \ -EH_MECHANISM="" \ -MULTISUBDIR="$(MULTISUBDIR)" \ -THREAD_KIND="$(THREAD_KIND)" \ -LN_S="$(LN_S)" \ -../stamp-gnatlib1-$(RTSDIR) - sed \ - -e 's/Frontend_Exceptions.*/Frontend_Exceptions : constant Boolean := True;/' \ - -e 's/ZCX_By_Default.*/ZCX_By_Default: constant Boolean := False;/' \ - $(RTSDIR)/system.ads > $(RTSDIR)/s.ads - $(MV) $(RTSDIR)/s.ads $(RTSDIR)/system.ads - $(MAKE) $(FLAGS_TO_PASS) \ -EH_MECHANISM="" \ -GNATLIBFLAGS="$(GNATLIBFLAGS)" \ -GNATLIBCFLAGS="$(GNATLIBCFLAGS)" \ -GNATLIBCFLAGS_FOR_C="$(GNATLIBCFLAGS_FOR_C)" \ -FORCE_DEBUG_ADAFLAGS="$(FORCE_DEBUG_ADAFLAGS)" \ -MULTISUBDIR="$(MULTISUBDIR)" \ -THREAD_KIND="$(THREAD_KIND)" \ -LN_S="$(LN_S)" \ -gnatlib - gnatlib-zcx: $(MAKE) $(FLAGS_TO_PASS) \ EH_MECHANISM="-gcc" \ @@ -859,7 +830,6 @@ gnatlib-zcx: LN_S="$(LN_S)" \ ../stamp-gnatlib1-$(RTSDIR) sed \ - -e 's/Frontend_Exceptions.*/Frontend_Exceptions : constant Boolean := False;/' \ -e 's/ZCX_By_Default.*/ZCX_By_Default: constant Boolean := True;/' \ $(RTSDIR)/system.ads > $(RTSDIR)/s.ads $(MV) $(RTSDIR)/s.ads $(RTSDIR)/system.ads diff --git a/gcc/ada/libgnat/system-linux-loongarch.ads b/gcc/ada/libgnat/system-linux-loongarch.ads index d44724df3050..79269d20839a 100644 --- a/gcc/ada/libgnat/system-linux-loongarch.ads +++ b/gcc/ada/libgnat/system-linux-loongarch.ads @@ -139,7 +139,6 @@ private Always_Compatible_Rep : constant Boolean := False; Suppress_Standard_Library : constant Boolean := False; Use_Ada_Main_Program_Name : constant Boolean := False; - Frontend_Exceptions : constant Boolean := False; ZCX_By_Default: constant Boolean := True; end System;
[gcc r16-1990] c++: Fix a pasto in the PR120471 fix [PR120940]
https://gcc.gnu.org/g:dc90649466a54ab61926d88500a05f59a55cb055
commit r16-1990-gdc90649466a54ab61926d88500a05f59a55cb055
Author: Jakub Jelinek
Date: Thu Jul 3 22:39:39 2025 +0200
c++: Fix a pasto in the PR120471 fix [PR120940]
No idea how this slipped in, I'm terribly sorry.
Strangely nothing in the testsuite has caught this, so I've added
a new test for that.
2025-07-03 Jakub Jelinek
PR c++/120940
* typeck.cc (cp_build_array_ref): Fix a pasto.
* g++.dg/parse/pr120940.C: New test.
* g++.dg/warn/Wduplicated-branches9.C: New test.
Diff:
---
gcc/cp/typeck.cc | 2 +-
gcc/testsuite/g++.dg/parse/pr120940.C | 18 ++
gcc/testsuite/g++.dg/warn/Wduplicated-branches9.C | 11 +++
3 files changed, 30 insertions(+), 1 deletion(-)
diff --git a/gcc/cp/typeck.cc b/gcc/cp/typeck.cc
index 447fe810633d..0bf5ae4e4e26 100644
--- a/gcc/cp/typeck.cc
+++ b/gcc/cp/typeck.cc
@@ -4004,7 +4004,7 @@ cp_build_array_ref (location_t loc, tree array, tree idx,
tree op0, op1, op2;
op0 = TREE_OPERAND (array, 0);
op1 = TREE_OPERAND (array, 1);
- op2 = TREE_OPERAND (array, 1);
+ op2 = TREE_OPERAND (array, 2);
if (TREE_SIDE_EFFECTS (idx) || !tree_invariant_p (idx))
{
/* If idx could possibly have some SAVE_EXPRs, turning
diff --git a/gcc/testsuite/g++.dg/parse/pr120940.C
b/gcc/testsuite/g++.dg/parse/pr120940.C
new file mode 100644
index ..5da36b2f88a0
--- /dev/null
+++ b/gcc/testsuite/g++.dg/parse/pr120940.C
@@ -0,0 +1,18 @@
+// PR c++/120940
+// { dg-do run }
+
+int a[8] = { 1, 2, 3, 4, 5, 6, 7, 8 };
+int b[8] = { 9, 10, 11, 12, 13, 14, 15, 16 };
+
+__attribute__((noipa)) int
+foo (int x, int y)
+{
+ return (x ? a : b)[y];
+}
+
+int
+main ()
+{
+ if (foo (1, 4) != 5 || foo (0, 6) != 15)
+__builtin_abort ();
+}
diff --git a/gcc/testsuite/g++.dg/warn/Wduplicated-branches9.C
b/gcc/testsuite/g++.dg/warn/Wduplicated-branches9.C
new file mode 100644
index ..f9fafcd467b4
--- /dev/null
+++ b/gcc/testsuite/g++.dg/warn/Wduplicated-branches9.C
@@ -0,0 +1,11 @@
+// PR c++/120940
+// { dg-do compile }
+// { dg-options "-Wduplicated-branches" }
+
+static char a[16][8], b[16][8];
+
+char *
+foo (int x, int y)
+{
+ return (x ? a : b)[y];
+}
[gcc r15-9919] Ada: Remove left-overs of front-end exception mechanism
https://gcc.gnu.org/g:733cd21cfdd82d11798512cc5c4af29b9fb3adb7 commit r15-9919-g733cd21cfdd82d11798512cc5c4af29b9fb3adb7 Author: Eric Botcazou Date: Thu Jul 3 20:02:43 2025 +0200 Ada: Remove left-overs of front-end exception mechanism It was removed from the compiler a few releases ago. gcc/ada/ * gcc-interface/Makefile.in (gnatlib-sjlj): Delete. (gnatlib-zcx): Do not modify Frontend_Exceptions constant. * libgnat/system-linux-loongarch.ads (Frontend_Exceptions): Delete. Diff: --- gcc/ada/gcc-interface/Makefile.in | 30 -- gcc/ada/libgnat/system-linux-loongarch.ads | 1 - 2 files changed, 31 deletions(-) diff --git a/gcc/ada/gcc-interface/Makefile.in b/gcc/ada/gcc-interface/Makefile.in index 4ffdc1e165d3..4b412b9298eb 100644 --- a/gcc/ada/gcc-interface/Makefile.in +++ b/gcc/ada/gcc-interface/Makefile.in @@ -843,35 +843,6 @@ gnatlib-shared: PICFLAG_FOR_TARGET="$(PICFLAG_FOR_TARGET)" \ $(GNATLIB_SHARED) -# When building a SJLJ runtime for VxWorks, we need to ensure that the extra -# linker options needed for ZCX are not passed to prevent the inclusion of -# useless objects and potential troubles from the presence of extra symbols -# and references in some configurations. The inhibition is performed by -# commenting the pragma instead of deleting the line, as the latter might -# result in getting multiple blank lines, hence possible style check errors. -gnatlib-sjlj: - $(MAKE) $(FLAGS_TO_PASS) \ -EH_MECHANISM="" \ -MULTISUBDIR="$(MULTISUBDIR)" \ -THREAD_KIND="$(THREAD_KIND)" \ -LN_S="$(LN_S)" \ -../stamp-gnatlib1-$(RTSDIR) - sed \ - -e 's/Frontend_Exceptions.*/Frontend_Exceptions : constant Boolean := True;/' \ - -e 's/ZCX_By_Default.*/ZCX_By_Default: constant Boolean := False;/' \ - $(RTSDIR)/system.ads > $(RTSDIR)/s.ads - $(MV) $(RTSDIR)/s.ads $(RTSDIR)/system.ads - $(MAKE) $(FLAGS_TO_PASS) \ -EH_MECHANISM="" \ -GNATLIBFLAGS="$(GNATLIBFLAGS)" \ -GNATLIBCFLAGS="$(GNATLIBCFLAGS)" \ -GNATLIBCFLAGS_FOR_C="$(GNATLIBCFLAGS_FOR_C)" \ -FORCE_DEBUG_ADAFLAGS="$(FORCE_DEBUG_ADAFLAGS)" \ -MULTISUBDIR="$(MULTISUBDIR)" \ -THREAD_KIND="$(THREAD_KIND)" \ -LN_S="$(LN_S)" \ -gnatlib - gnatlib-zcx: $(MAKE) $(FLAGS_TO_PASS) \ EH_MECHANISM="-gcc" \ @@ -880,7 +851,6 @@ gnatlib-zcx: LN_S="$(LN_S)" \ ../stamp-gnatlib1-$(RTSDIR) sed \ - -e 's/Frontend_Exceptions.*/Frontend_Exceptions : constant Boolean := False;/' \ -e 's/ZCX_By_Default.*/ZCX_By_Default: constant Boolean := True;/' \ $(RTSDIR)/system.ads > $(RTSDIR)/s.ads $(MV) $(RTSDIR)/s.ads $(RTSDIR)/system.ads diff --git a/gcc/ada/libgnat/system-linux-loongarch.ads b/gcc/ada/libgnat/system-linux-loongarch.ads index 77a213962550..683b7a441558 100644 --- a/gcc/ada/libgnat/system-linux-loongarch.ads +++ b/gcc/ada/libgnat/system-linux-loongarch.ads @@ -139,7 +139,6 @@ private Always_Compatible_Rep : constant Boolean := False; Suppress_Standard_Library : constant Boolean := False; Use_Ada_Main_Program_Name : constant Boolean := False; - Frontend_Exceptions : constant Boolean := False; ZCX_By_Default: constant Boolean := True; end System;
[gcc r13-9783] c++: Fix a pasto in the PR120471 fix [PR120940]
https://gcc.gnu.org/g:f3689dc2061481fa789dbf7b6ab55a8e5f52f198
commit r13-9783-gf3689dc2061481fa789dbf7b6ab55a8e5f52f198
Author: Jakub Jelinek
Date: Thu Jul 3 22:39:39 2025 +0200
c++: Fix a pasto in the PR120471 fix [PR120940]
No idea how this slipped in, I'm terribly sorry.
Strangely nothing in the testsuite has caught this, so I've added
a new test for that.
2025-07-03 Jakub Jelinek
PR c++/120940
* typeck.cc (cp_build_array_ref): Fix a pasto.
* g++.dg/parse/pr120940.C: New test.
* g++.dg/warn/Wduplicated-branches9.C: New test.
(cherry picked from commit dc90649466a54ab61926d88500a05f59a55cb055)
Diff:
---
gcc/cp/typeck.cc | 2 +-
gcc/testsuite/g++.dg/parse/pr120940.C | 18 ++
gcc/testsuite/g++.dg/warn/Wduplicated-branches9.C | 11 +++
3 files changed, 30 insertions(+), 1 deletion(-)
diff --git a/gcc/cp/typeck.cc b/gcc/cp/typeck.cc
index 38df8d8e6c2d..61d716e2a0ed 100644
--- a/gcc/cp/typeck.cc
+++ b/gcc/cp/typeck.cc
@@ -3964,7 +3964,7 @@ cp_build_array_ref (location_t loc, tree array, tree idx,
tree op0, op1, op2;
op0 = TREE_OPERAND (array, 0);
op1 = TREE_OPERAND (array, 1);
- op2 = TREE_OPERAND (array, 1);
+ op2 = TREE_OPERAND (array, 2);
if (TREE_SIDE_EFFECTS (idx) || !tree_invariant_p (idx))
{
/* If idx could possibly have some SAVE_EXPRs, turning
diff --git a/gcc/testsuite/g++.dg/parse/pr120940.C
b/gcc/testsuite/g++.dg/parse/pr120940.C
new file mode 100644
index ..5da36b2f88a0
--- /dev/null
+++ b/gcc/testsuite/g++.dg/parse/pr120940.C
@@ -0,0 +1,18 @@
+// PR c++/120940
+// { dg-do run }
+
+int a[8] = { 1, 2, 3, 4, 5, 6, 7, 8 };
+int b[8] = { 9, 10, 11, 12, 13, 14, 15, 16 };
+
+__attribute__((noipa)) int
+foo (int x, int y)
+{
+ return (x ? a : b)[y];
+}
+
+int
+main ()
+{
+ if (foo (1, 4) != 5 || foo (0, 6) != 15)
+__builtin_abort ();
+}
diff --git a/gcc/testsuite/g++.dg/warn/Wduplicated-branches9.C
b/gcc/testsuite/g++.dg/warn/Wduplicated-branches9.C
new file mode 100644
index ..f9fafcd467b4
--- /dev/null
+++ b/gcc/testsuite/g++.dg/warn/Wduplicated-branches9.C
@@ -0,0 +1,11 @@
+// PR c++/120940
+// { dg-do compile }
+// { dg-options "-Wduplicated-branches" }
+
+static char a[16][8], b[16][8];
+
+char *
+foo (int x, int y)
+{
+ return (x ? a : b)[y];
+}
[gcc r12-11245] c++: Fix a pasto in the PR120471 fix [PR120940]
https://gcc.gnu.org/g:ed950a9ed384389ff07ac793b7065abe31bcae3f
commit r12-11245-ged950a9ed384389ff07ac793b7065abe31bcae3f
Author: Jakub Jelinek
Date: Thu Jul 3 22:39:39 2025 +0200
c++: Fix a pasto in the PR120471 fix [PR120940]
No idea how this slipped in, I'm terribly sorry.
Strangely nothing in the testsuite has caught this, so I've added
a new test for that.
2025-07-03 Jakub Jelinek
PR c++/120940
* typeck.cc (cp_build_array_ref): Fix a pasto.
* g++.dg/parse/pr120940.C: New test.
* g++.dg/warn/Wduplicated-branches9.C: New test.
(cherry picked from commit dc90649466a54ab61926d88500a05f59a55cb055)
Diff:
---
gcc/cp/typeck.cc | 2 +-
gcc/testsuite/g++.dg/parse/pr120940.C | 18 ++
gcc/testsuite/g++.dg/warn/Wduplicated-branches9.C | 11 +++
3 files changed, 30 insertions(+), 1 deletion(-)
diff --git a/gcc/cp/typeck.cc b/gcc/cp/typeck.cc
index 19dfaf18928f..2f67bb33ff04 100644
--- a/gcc/cp/typeck.cc
+++ b/gcc/cp/typeck.cc
@@ -3814,7 +3814,7 @@ cp_build_array_ref (location_t loc, tree array, tree idx,
tree op0, op1, op2;
op0 = TREE_OPERAND (array, 0);
op1 = TREE_OPERAND (array, 1);
- op2 = TREE_OPERAND (array, 1);
+ op2 = TREE_OPERAND (array, 2);
if (TREE_SIDE_EFFECTS (idx) || !tree_invariant_p (idx))
{
/* If idx could possibly have some SAVE_EXPRs, turning
diff --git a/gcc/testsuite/g++.dg/parse/pr120940.C
b/gcc/testsuite/g++.dg/parse/pr120940.C
new file mode 100644
index ..5da36b2f88a0
--- /dev/null
+++ b/gcc/testsuite/g++.dg/parse/pr120940.C
@@ -0,0 +1,18 @@
+// PR c++/120940
+// { dg-do run }
+
+int a[8] = { 1, 2, 3, 4, 5, 6, 7, 8 };
+int b[8] = { 9, 10, 11, 12, 13, 14, 15, 16 };
+
+__attribute__((noipa)) int
+foo (int x, int y)
+{
+ return (x ? a : b)[y];
+}
+
+int
+main ()
+{
+ if (foo (1, 4) != 5 || foo (0, 6) != 15)
+__builtin_abort ();
+}
diff --git a/gcc/testsuite/g++.dg/warn/Wduplicated-branches9.C
b/gcc/testsuite/g++.dg/warn/Wduplicated-branches9.C
new file mode 100644
index ..f9fafcd467b4
--- /dev/null
+++ b/gcc/testsuite/g++.dg/warn/Wduplicated-branches9.C
@@ -0,0 +1,11 @@
+// PR c++/120940
+// { dg-do compile }
+// { dg-options "-Wduplicated-branches" }
+
+static char a[16][8], b[16][8];
+
+char *
+foo (int x, int y)
+{
+ return (x ? a : b)[y];
+}
[gcc r16-1986] libstdc++: Update LWG 4166 changes to concat_view::end() [PR120934]
https://gcc.gnu.org/g:c5a17e92ebf0c6f3887fb5698a1114a3fdf50576
commit r16-1986-gc5a17e92ebf0c6f3887fb5698a1114a3fdf50576
Author: Patrick Palka
Date: Thu Jul 3 10:55:17 2025 -0400
libstdc++: Update LWG 4166 changes to concat_view::end() [PR120934]
In r15-4555-gf191c830154565 we proactively implemented the initial
proposed resolution for LWG 4166 which later turned out to be
insufficient, since we must also require equality_comparable of the
underlying iterators before concat_view could be a common range.
This patch implements the updated P/R, requiring all underlying
iterators to be forward (which implies equality_comparable) before
making concat_view common, which fixes the testcase from this PR.
PR libstdc++/120934
libstdc++-v3/ChangeLog:
* include/std/ranges (concat_view::end): Refine condition
for returning an iterator instead of default_sentinel as
per the updated P/R for LWG 4166.
* testsuite/std/ranges/concat/1.cc (test05): New test.
Reviewed-by: Jonathan Wakely
Diff:
---
libstdc++-v3/include/std/ranges | 4 ++--
libstdc++-v3/testsuite/std/ranges/concat/1.cc | 13 +
2 files changed, 15 insertions(+), 2 deletions(-)
diff --git a/libstdc++-v3/include/std/ranges b/libstdc++-v3/include/std/ranges
index f764aa7512e3..3a6710bd0ae1 100644
--- a/libstdc++-v3/include/std/ranges
+++ b/libstdc++-v3/include/std/ranges
@@ -9735,7 +9735,7 @@ namespace ranges
end() requires (!(__detail::__simple_view<_Vs> && ...))
{
constexpr auto __n = sizeof...(_Vs);
- if constexpr ((semiregular> && ...)
+ if constexpr (__detail::__all_forward
&& common_range<_Vs...[__n - 1]>)
return _Iterator(this, in_place_index<__n - 1>,
ranges::end(std::get<__n - 1>(_M_views)));
@@ -9747,7 +9747,7 @@ namespace ranges
end() const requires (range && ...) &&
__detail::__concatable
{
constexpr auto __n = sizeof...(_Vs);
- if constexpr ((semiregular> && ...)
+ if constexpr (__detail::__all_forward
&& common_range)
return _Iterator(this, in_place_index<__n - 1>,
ranges::end(std::get<__n - 1>(_M_views)));
diff --git a/libstdc++-v3/testsuite/std/ranges/concat/1.cc
b/libstdc++-v3/testsuite/std/ranges/concat/1.cc
index 16721912a37d..f78ed08a610b 100644
--- a/libstdc++-v3/testsuite/std/ranges/concat/1.cc
+++ b/libstdc++-v3/testsuite/std/ranges/concat/1.cc
@@ -99,6 +99,18 @@ test04()
using type = decltype(v);
}
+void
+test05()
+{
+ // PR libstdc++/120934 - views::concat is ill-formed depending on argument
order
+ auto v1 = views::single(1);
+ std::vector vec = {2, 3};
+ auto v2 = views::join(views::transform(vec, views::single));
+
+ static_assert( ranges::range );
+ static_assert( ranges::range );
+}
+
int
main()
{
@@ -107,4 +119,5 @@ main()
test02();
test03();
test04();
+ test05();
}
[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vssubu.vv combine case 0 with GR2VR cost 0, 2 and 15
https://gcc.gnu.org/g:780792d78294406c43acef3352bd93a35a37cbd3
commit 780792d78294406c43acef3352bd93a35a37cbd3
Author: Pan Li
Date: Fri Jun 27 09:06:38 2025 +0800
RISC-V: Add test for vec_duplicate + vssubu.vv combine case 0 with GR2VR
cost 0, 2 and 15
Add asm dump check and run test for vec_duplicate + vssubu.vv
combine to vssubu.vx, with the GR2VR cost is 0, 2 and 15.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c: Add asm check.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h: Add test
helper macros.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h: Add test
data for run test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vssub-run-1-u16.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vssub-run-1-u32.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vssub-run-1-u64.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vssub-run-1-u8.c: New test.
Signed-off-by: Pan Li
(cherry picked from commit 342694acd59c87f35d97805609ba54f547b52881)
Diff:
---
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c | 1 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c | 1 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c | 1 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c | 1 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c | 1 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c | 1 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c | 1 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c | 1 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c | 1 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c | 1 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c | 1 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c | 1 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h | 18 +-
.../riscv/rvv/autovec/vx_vf/vx_binary_data.h | 196 +
.../riscv/rvv/autovec/vx_vf/vx_vssub-run-1-u16.c | 17 ++
.../riscv/rvv/autovec/vx_vf/vx_vssub-run-1-u32.c | 17 ++
.../riscv/rvv/autovec/vx_vf/vx_vssub-run-1-u64.c | 17 ++
.../riscv/rvv/autovec/vx_vf/vx_vssub-run-1-u8.c| 17 ++
18 files changed, 293 insertions(+), 1 deletion(-)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c
index 21a207edce75..b064748fc145 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c
@@ -18,3 +18,4 @@ TEST_BINARY_VX_UNSIGNED_0(T)
/* { dg-final { scan-assembler-times {vmaxu.vx} 2 } } */
/* { dg-final { scan-assembler-times {vminu.vx} 2 } } */
/* { dg-final { scan-assembler-times {vsaddu.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vssubu.vx} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c
index d1063adb0d6c..e334bb3690b7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c
@@ -18,3 +18,4 @@ TEST_BINARY_VX_UNSIGNED_0(T)
/* { dg-final { scan-assembler-times {vmaxu.vx} 2 } } */
/* { dg-final { scan-assembler-times {vminu.vx} 2 } } */
/* { dg-final { scan-assembler-times {vsaddu.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vssubu.vx} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c
index 3d96503fd9ad..3e8ca0570cdb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c
@@ -18,3 +18,4 @@ TEST_BINARY_VX_UNSIGNED_0(T)
/* { dg-final { scan-assembler-times {vmaxu.vx} 2 } } */
/* { dg-final { scan-assembler-times {vminu.vx} 2 } } */
/* { dg-final { scan-assembler-times {vsaddu.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vssubu.vx} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c
index 339a35c3f422..1f995cd8dc1f 100644
[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Vector-scalar negate-multiply-(subtract-)accumulate [PR119100]
https://gcc.gnu.org/g:302682829c254743170b11680231cf1023306776 commit 302682829c254743170b11680231cf1023306776 Author: Paul-Antoine Arras Date: Thu Jun 26 13:20:49 2025 + RISC-V: Vector-scalar negate-multiply-(subtract-)accumulate [PR119100] This pattern enables the combine pass (or late-combine, depending on the case) to merge a vec_duplicate into a (possibly negated) minus-mult RTL instruction. Before this patch, we have two instructions, e.g.: vfmv.v.fv6,fa0 vfnmacc.vv v2,v6,v4 After, we get only one: vfnmacc.vf v2,fa0,v4 PR target/119100 gcc/ChangeLog: * config/riscv/autovec-opt.md (*vfnmsub_,*vfnmadd_): Handle both add and acc variants. * config/riscv/vector.md (*pred_mul_neg__scalar_undef): New pattern. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f16.c: Add vfnmacc and vfnmsac. * gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f32.c: Likewise. * gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f64.c: Likewise. * gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f16.c: Likewise. * gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f32.c: Likewise. * gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f64.c: Likewise. * gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f16.c: Likewise. * gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f32.c: Likewise. * gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f64.c: Likewise. * gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f16.c: Likewise. * gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f32.c: Likewise. * gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f64.c: Likewise. * gcc.target/riscv/rvv/autovec/vx_vf/vf_mulop.h (DEF_VF_MULOP_CASE_1): Fix return type. * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmacc-run-1-f16.c: New test. * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmacc-run-1-f32.c: New test. * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmacc-run-1-f64.c: New test. * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsac-run-1-f16.c: New test. * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsac-run-1-f32.c: New test. * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsac-run-1-f64.c: New test. (cherry picked from commit 6e24814d9e09019bf42b33b66827648ceff6e7c0) Diff: --- gcc/config/riscv/autovec-opt.md| 30 + gcc/config/riscv/vector.md | 38 -- .../gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f16.c | 4 +++ .../gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f32.c | 4 +++ .../gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f64.c | 4 +++ .../gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f16.c | 2 ++ .../gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f32.c | 2 ++ .../gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f64.c | 2 ++ .../gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f16.c | 4 +++ .../gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f32.c | 4 +++ .../gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f64.c | 4 +++ .../gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f16.c | 2 ++ .../gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f32.c | 2 ++ .../gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f64.c | 2 ++ .../gcc.target/riscv/rvv/autovec/vx_vf/vf_mulop.h | 5 +-- .../riscv/rvv/autovec/vx_vf/vf_vfnmacc-run-1-f16.c | 16 + .../riscv/rvv/autovec/vx_vf/vf_vfnmacc-run-1-f32.c | 16 + .../riscv/rvv/autovec/vx_vf/vf_vfnmacc-run-1-f64.c | 16 + .../riscv/rvv/autovec/vx_vf/vf_vfnmsac-run-1-f16.c | 16 + .../riscv/rvv/autovec/vx_vf/vf_vfnmsac-run-1-f32.c | 16 + .../riscv/rvv/autovec/vx_vf/vf_vfnmsac-run-1-f64.c | 16 + 21 files changed, 187 insertions(+), 18 deletions(-) diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md index bb15d14b4e64..8df7f6494cf7 100644 --- a/gcc/config/riscv/autovec-opt.md +++ b/gcc/config/riscv/autovec-opt.md @@ -1723,6 +1723,8 @@ ;; - vfnmsub.vf ;; - vfmacc.vf ;; - vfmsac.vf +;; - vfnmacc.vf +;; - vfnmsac.vf ;; = ;; vfmadd.vf, vfmsub.vf, vfmacc.vf, vfmsac.vf @@ -1748,22 +1750,22 @@ [(set_attr "type" "vfmuladd")] ) -;; vfnmsub.vf +;; vfnmsub.vf, vfnmsac.vf (define_insn_and_split "*vfnmsub_" - [(set (match_operand:V_VLSF 0 "register_operand" "=vd") + [(set (match_operand:V_VLSF 0 "register_operand") (minus:V_VLSF - (match_operand:V_VLSF 3 "register_operand" " vr") - (mult:V_VLSF - (vec_duplicate:V_VLSF - (match_operand: 1 "register_operand" " f")) - (match_operand:V_VLSF 2 "register_operand"" 0"] + (match_operand:V_VLSF 3 "register_operand") + (mult:V_VLSF + (vec_duplicate:V_VLSF +
[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [RISC-V][PR target/119971] Avoid losing shift count masking
https://gcc.gnu.org/g:e520ad3e70ce45682d1f47682dee2c1e4a93f558
commit e520ad3e70ce45682d1f47682dee2c1e4a93f558
Author: Jeff Law
Date: Fri Jun 27 07:00:15 2025 -0600
[RISC-V][PR target/119971] Avoid losing shift count masking
Fix typo spotted by Bernhard Reutner-Fischer.
PR target/119971
gcc/testsuite/
* gcc.target/riscv/pr119971.c: Fix typo.
(cherry picked from commit de6124c9e5ed472f567b51fa76f18335cdddbbaf)
Diff:
---
gcc/testsuite/gcc.target/riscv/pr119971.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/testsuite/gcc.target/riscv/pr119971.c
b/gcc/testsuite/gcc.target/riscv/pr119971.c
index c3f23b05ec37..0d73d4ca3f13 100644
--- a/gcc/testsuite/gcc.target/riscv/pr119971.c
+++ b/gcc/testsuite/gcc.target/riscv/pr119971.c
@@ -1,6 +1,6 @@
/* { dg-do compile { target rv64 } } */
/* { dg-options "-march=rv64gcb -mabi=lp64" } */
-/* { dg-skip-if "" { *-*-* } { "-O0" "-g" "-Oz" "-Os" } } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Oz" "-Os" } } */
__attribute__ ((noipa)) unsigned
foo (unsigned b, unsigned e, unsigned i)
[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [sanitizer_common] Fix build on ppc64+musl (#120036)
https://gcc.gnu.org/g:040d02cb21f928c77ac8b976d69f1f6c8fa26683
commit 040d02cb21f928c77ac8b976d69f1f6c8fa26683
Author: Jeff Law
Date: Fri Jun 27 15:11:41 2025 -0600
[sanitizer_common] Fix build on ppc64+musl (#120036)
Cherry picked from LLVM commit 801b519dfd01e21da0be17aa8f8dc2ceb0eb9e77.
In powerpc64-unknown-linux-musl, signal.h does not include asm/ptrace.h,
which causes "member access into incomplete type 'struct pt_regs'"
errors. Include the header explicitly to fix this.
Also in sanitizer_linux_libcdep.cpp, there is a usage of TlsPreTcbSize
which is not defined in such a platform. Guard the branch with macro.
(cherry picked from commit 5111ea055f5699ad47605890fb45af5c3db1de4f)
Diff:
---
libsanitizer/sanitizer_common/sanitizer_linux.cpp | 4
libsanitizer/sanitizer_common/sanitizer_linux_libcdep.cpp | 13 +++--
.../sanitizer_common/sanitizer_platform_limits_posix.cpp| 2 +-
.../sanitizer_stoptheworld_linux_libcdep.cpp| 3 ++-
4 files changed, 14 insertions(+), 8 deletions(-)
diff --git a/libsanitizer/sanitizer_common/sanitizer_linux.cpp
b/libsanitizer/sanitizer_common/sanitizer_linux.cpp
index 8b1850f85010..6331c26c0a92 100644
--- a/libsanitizer/sanitizer_common/sanitizer_linux.cpp
+++ b/libsanitizer/sanitizer_common/sanitizer_linux.cpp
@@ -86,6 +86,10 @@
#include
# endif
+# if SANITIZER_LINUX && defined(__powerpc64__)
+#include
+# endif
+
# if SANITIZER_FREEBSD
#include
#include
diff --git a/libsanitizer/sanitizer_common/sanitizer_linux_libcdep.cpp
b/libsanitizer/sanitizer_common/sanitizer_linux_libcdep.cpp
index ed19e4031a53..9d01a97af5f4 100644
--- a/libsanitizer/sanitizer_common/sanitizer_linux_libcdep.cpp
+++ b/libsanitizer/sanitizer_common/sanitizer_linux_libcdep.cpp
@@ -619,21 +619,22 @@ static void GetTls(uptr *addr, uptr *size) {
*addr = tp - RoundUpTo(*size, align);
*size = tp - *addr + ThreadDescriptorSize();
# else
- if (SANITIZER_GLIBC)
-*size += 1664;
- else if (SANITIZER_FREEBSD)
-*size += 128; // RTLD_STATIC_TLS_EXTRA
-#if defined(__mips__) || defined(__powerpc64__) || SANITIZER_RISCV64
+#if SANITIZER_GLIBC
+ *size += 1664;
+#elif SANITIZER_FREEBSD
+ *size += 128; // RTLD_STATIC_TLS_EXTRA
+# if defined(__mips__) || defined(__powerpc64__) || SANITIZER_RISCV64
const uptr pre_tcb_size = TlsPreTcbSize();
*addr -= pre_tcb_size;
*size += pre_tcb_size;
-#else
+# else
// arm and aarch64 reserve two words at TP, so this underestimates the range.
// However, this is sufficient for the purpose of finding the pointers to
// thread-specific data keys.
const uptr tcb_size = ThreadDescriptorSize();
*addr -= tcb_size;
*size += tcb_size;
+# endif
#endif
# endif
#elif SANITIZER_NETBSD
diff --git a/libsanitizer/sanitizer_common/sanitizer_platform_limits_posix.cpp
b/libsanitizer/sanitizer_common/sanitizer_platform_limits_posix.cpp
index 7bbc6f2edac2..490e75fe8f65 100644
--- a/libsanitizer/sanitizer_common/sanitizer_platform_limits_posix.cpp
+++ b/libsanitizer/sanitizer_common/sanitizer_platform_limits_posix.cpp
@@ -96,7 +96,7 @@
# include
#if defined(__mips64) || defined(__aarch64__) || defined(__arm__) ||
\
defined(__hexagon__) || defined(__loongarch__) || SANITIZER_RISCV64 ||
\
-defined(__sparc__)
+defined(__sparc__) || defined(__powerpc64__)
# include
# ifdef __arm__
typedef struct user_fpregs elf_fpregset_t;
diff --git
a/libsanitizer/sanitizer_common/sanitizer_stoptheworld_linux_libcdep.cpp
b/libsanitizer/sanitizer_common/sanitizer_stoptheworld_linux_libcdep.cpp
index 945da99d41f4..58d17d90c343 100644
--- a/libsanitizer/sanitizer_common/sanitizer_stoptheworld_linux_libcdep.cpp
+++ b/libsanitizer/sanitizer_common/sanitizer_stoptheworld_linux_libcdep.cpp
@@ -31,7 +31,8 @@
#include // for pid_t
#include // for iovec
#include // for NT_PRSTATUS
-#if (defined(__aarch64__) || SANITIZER_RISCV64 || SANITIZER_LOONGARCH64) && \
+#if (defined(__aarch64__) || defined(__powerpc64__) || \
+ SANITIZER_RISCV64 || SANITIZER_LOONGARCH64) &&\
!SANITIZER_ANDROID
// GLIBC 2.20+ sys/user does not include asm/ptrace.h
# include
[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Refactor the function bitmap_union_of_preds_with_entry
https://gcc.gnu.org/g:e67bd2944d99dc1f1da4594da5075691149f7cb7
commit e67bd2944d99dc1f1da4594da5075691149f7cb7
Author: Jin Ma
Date: Sat Jun 28 19:55:00 2025 +0800
RISC-V: Refactor the function bitmap_union_of_preds_with_entry
The current implementation of this function is somewhat difficult to
understand, as it uses a direct break statement within the for loop,
rendering the loop meaningless. Additionally, during the Coverity check
on the for loop, a warning appeared: "unreachable: Since the loop
increment ix++; is unreachable, the loop body will never execute more
than once." Therefore, I have made some simple refactoring to address
these issues.
gcc/ChangeLog:
* config/riscv/riscv-vsetvl.cc (bitmap_union_of_preds_with_entry):
Refactor.
Signed-off-by: Jin Ma
(cherry picked from commit 2609a7a5971aa8a2ef1bafbf5581dcabd68a466e)
Diff:
---
gcc/config/riscv/riscv-vsetvl.cc | 41 +++-
1 file changed, 19 insertions(+), 22 deletions(-)
diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc
index 4891b6c95e85..4fe0ae6d97b7 100644
--- a/gcc/config/riscv/riscv-vsetvl.cc
+++ b/gcc/config/riscv/riscv-vsetvl.cc
@@ -100,31 +100,28 @@ using namespace riscv_vector;
static void
bitmap_union_of_preds_with_entry (sbitmap dst, sbitmap *src, basic_block b)
{
- unsigned int set_size = dst->size;
- edge e;
- unsigned ix;
-
- for (ix = 0; ix < EDGE_COUNT (b->preds); ix++)
+ /* Handle case with no predecessors (including ENTRY block). */
+ if (EDGE_COUNT (b->preds) == 0)
{
- e = EDGE_PRED (b, ix);
- bitmap_copy (dst, src[e->src->index]);
- break;
+ bitmap_clear (dst);
+ return;
}
- if (ix == EDGE_COUNT (b->preds))
-bitmap_clear (dst);
- else
-for (ix++; ix < EDGE_COUNT (b->preds); ix++)
- {
- unsigned int i;
- SBITMAP_ELT_TYPE *p, *r;
-
- e = EDGE_PRED (b, ix);
- p = src[e->src->index]->elms;
- r = dst->elms;
- for (i = 0; i < set_size; i++)
- *r++ |= *p++;
- }
+ edge e;
+ edge_iterator ei;
+ /* Union remaining predecessors' bitmaps. */
+ FOR_EACH_EDGE (e, ei, b->preds)
+{
+ /* Initialize with first predecessor's bitmap. */
+ if (ei.index == 0)
+ {
+ bitmap_copy (dst, src[e->src->index]);
+ continue;
+ }
+
+ /* Perform bitmap OR operation element-wise. */
+ bitmap_ior (dst, dst, src[e->src->index]);
+}
}
/* Compute the reaching definition in and out based on the gen and KILL
[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add pipeline-checker script
https://gcc.gnu.org/g:ce4e56eb6e8b6ffeb0ea353b4283e5ec0a8024c5
commit ce4e56eb6e8b6ffeb0ea353b4283e5ec0a8024c5
Author: Kito Cheng
Date: Thu Jun 26 17:21:27 2025 +0800
RISC-V: Add pipeline-checker script
Pipeline checker utility for RISC-V architecture that validates processor
pipeline models. This tool analyzes machine description files to ensure all
instruction types are properly handled by pipeline scheduling models.
I write this tool since I am implment vector pipeline stuff for SiFive
core, but it's hard to find which instruction type is not handled by
pipeline scheduling models. This tool will help me to find out which
instruction type is not handled by pipeline scheduling models, so I can
fix them.
And I think it may be useful for other RISC-V core developers, so I
decided to upstream that :)
Usage:
```
./pipeline-checker
```
Example:
```
$ ./pipeline-checker sifive-7.md
Error: Some types are not consumed by the pipemodel
Missing types:
{'vfclass', 'vimovxv', 'vmov', 'rdfrm', 'wrfrm', 'ghost', 'wrvxrm',
'crypto', 'vwsll', 'vfmovfv', 'vimovvx', 'sf_vc', 'vfmovvf', 'sf_vc_se',
'rdvlenb', 'vbrev', 'vrev8', 'sf_vqmacc', 'sf_vfnrclip', 'vsetvl_pre', 'rdvl',
'vsetvl'}
```
gcc/ChangeLog:
* config/riscv/pipeline-checker: New file.
(cherry picked from commit 9dda053e4188fed9b13feec43fdf6d3b31c8cbb3)
Diff:
---
gcc/config/riscv/pipeline-checker | 191 ++
1 file changed, 191 insertions(+)
diff --git a/gcc/config/riscv/pipeline-checker
b/gcc/config/riscv/pipeline-checker
new file mode 100755
index ..815698b0e20f
--- /dev/null
+++ b/gcc/config/riscv/pipeline-checker
@@ -0,0 +1,191 @@
+#!/usr/bin/env python3
+
+# RISC-V pipeline model checker.
+# Copyright (C) 2025 Free Software Foundation, Inc.
+#
+# This file is part of GCC.
+#
+# GCC is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3, or (at your option)
+# any later version.
+#
+# GCC is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with GCC; see the file COPYING3. If not see
+#
[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Adding B ext, fp16 and missing scalar instruction type for sifive-7 pipeline model [PR120659
https://gcc.gnu.org/g:a91fa2ad1f3f3ee4f1ee2e1b6071bf464de1b55e
commit a91fa2ad1f3f3ee4f1ee2e1b6071bf464de1b55e
Author: Kito Cheng
Date: Tue Jun 17 16:20:19 2025 +0800
RISC-V: Adding B ext, fp16 and missing scalar instruction type for sifive-7
pipeline model [PR120659]
gcc/ChangeLog:
PR target/120659
* config/riscv/sifive-7.md: Add B extension, fp16 and missing
scalar instruction type for sifive-7 pipeline model.
gcc/testsuite/ChangeLog:
PR target/120659
* gcc.target/riscv/pr120659.c: New test.
(cherry picked from commit c8cb537fdbdbc9e1c77ec389bcb99ad87b15cb92)
Diff:
---
gcc/config/riscv/sifive-7.md | 32 ---
gcc/testsuite/gcc.target/riscv/pr120659.c | 5 +
2 files changed, 34 insertions(+), 3 deletions(-)
diff --git a/gcc/config/riscv/sifive-7.md b/gcc/config/riscv/sifive-7.md
index c20854108893..b96d7eb8550e 100644
--- a/gcc/config/riscv/sifive-7.md
+++ b/gcc/config/riscv/sifive-7.md
@@ -60,9 +60,14 @@
(define_insn_reservation "sifive_7_alu" 2
(and (eq_attr "tune" "sifive_7")
(eq_attr "type" "unknown,arith,shift,slt,multi,logical,move,bitmanip,\
-
rotate,min,max,minu,maxu,clz,ctz,atomic,condmove,mvpair,zicond"))
+ min,max,minu,maxu,atomic,condmove,mvpair,zicond"))
"sifive_7_A|sifive_7_B")
+(define_insn_reservation "sifive_7_alu_b" 2
+ (and (eq_attr "tune" "sifive_7")
+ (eq_attr "type" "clz,ctz,rotate"))
+ "sifive_7_B")
+
(define_insn_reservation "sifive_7_load_immediate" 1
(and (eq_attr "tune" "sifive_7")
(eq_attr "type" "nop,const,auipc"))
@@ -91,6 +96,12 @@
(eq_attr "type" "fcvt,fcvt_i2f,fcvt_f2i,fcmp,fmove"))
"sifive_7_B")
+(define_insn_reservation "sifive_7_fdiv_h" 14
+ (and (eq_attr "tune" "sifive_7")
+ (eq_attr "type" "fdiv,fsqrt")
+ (eq_attr "mode" "HF"))
+ "sifive_7_B,sifive_7_fpu*13")
+
(define_insn_reservation "sifive_7_fdiv_s" 27
(and (eq_attr "tune" "sifive_7")
(eq_attr "type" "fdiv,fsqrt")
@@ -119,6 +130,21 @@
(eq_attr "type" "cpop,clmul"))
"sifive_7_A")
+(define_insn_reservation "sifive_7_csr" 5
+ (and (eq_attr "tune" "sifive_7")
+ (eq_attr "type" "rdfrm,wrfrm,wrvxrm"))
+ "sifive_7_A")
+
+(define_insn_reservation "sifive_7_crypto" 10
+ (and (eq_attr "tune" "sifive_7")
+ (eq_attr "type" "crypto"))
+ "sifive_7_A")
+
+(define_insn_reservation "sifive_7_unknown" 10
+ (and (eq_attr "tune" "sifive_7")
+ (eq_attr "type" "ghost"))
+ "sifive_7_A")
+
(define_bypass 1
"sifive_7_load,sifive_7_alu,sifive_7_mul,sifive_7_f2i,sifive_7_sfb_alu"
"sifive_7_alu,sifive_7_branch")
@@ -129,10 +155,10 @@
"sifive_7_store" "riscv_store_data_bypass_p")
(define_bypass 2 "sifive_7_i2f"
-
"sifive_7_sfma,sifive_7_dfma,sifive_7_fp_other,sifive_7_fdiv_s,sifive_7_fdiv_d")
+
"sifive_7_sfma,sifive_7_dfma,sifive_7_fp_other,sifive_7_fdiv_h,sifive_7_fdiv_s,sifive_7_fdiv_d,sifive_7_hfma")
(define_bypass 2 "sifive_7_fp_other"
-
"sifive_7_sfma,sifive_7_dfma,sifive_7_fp_other,sifive_7_fdiv_s,sifive_7_fdiv_d")
+
"sifive_7_sfma,sifive_7_dfma,sifive_7_fp_other,sifive_7_fdiv_h,sifive_7_fdiv_s,sifive_7_fdiv_d,sifive_7_hfma")
(define_bypass 2 "sifive_7_fp_other"
"sifive_7_alu,sifive_7_branch")
diff --git a/gcc/testsuite/gcc.target/riscv/pr120659.c
b/gcc/testsuite/gcc.target/riscv/pr120659.c
new file mode 100644
index ..91e6e42d4f95
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/pr120659.c
@@ -0,0 +1,5 @@
+/* { dg-do compile } */
+/* { dg-options "-mcpu=sifive-x280 -mabi=lp64" } */
+
+_Float16 f;
+void foo() { f /= 3; }
[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Ignore -Oz for most rvv testcase [NFC]
https://gcc.gnu.org/g:1c66ca29f0727fa749d80b2504ecf99d289dd5e2
commit 1c66ca29f0727fa749d80b2504ecf99d289dd5e2
Author: Kito Cheng
Date: Mon Jun 30 14:18:07 2025 +0800
RISC-V: Ignore -Oz for most rvv testcase [NFC]
Most testcase in rvv folder already ignore -Oz, but some of them
are not. This patch makes them consistent.
gcc/testsuite/ChangeLog.
* gcc.target/riscv/rvv/vsetvl/avl_single-21.c: Ignore -Oz.
* gcc.target/riscv/rvv/vsetvl/avl_single-26.c: Ditto.
* gcc.target/riscv/rvv/vsetvl/avl_single-36.c: Ditto.
* gcc.target/riscv/rvv/vsetvl/avl_single-39.c: Ditto.
* gcc.target/riscv/rvv/vsetvl/avl_single-41.c: Ditto.
* gcc.target/riscv/rvv/vsetvl/vsetvl-22.c: Ditto.
* gcc.target/riscv/rvv/vsetvl/vsetvlmax-15.c: Ditto.
* gcc.target/riscv/rvv/vsetvl/vsetvlmax-2.c: Ditto.
* gcc.target/riscv/rvv/vsetvl/vsetvlmax-4.c: Ditto.
(cherry picked from commit 139c6d1804bd7e1f37fb591a9327d72a0d1560fe)
Diff:
---
gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-21.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-26.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-36.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-39.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-41.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-22.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-15.c | 4 ++--
gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-2.c | 4 ++--
gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-4.c | 4 ++--
9 files changed, 12 insertions(+), 12 deletions(-)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-21.c
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-21.c
index 3a64b3b226de..e0bd0fe71ae1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-21.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-21.c
@@ -29,4 +29,4 @@ void f (int8_t * restrict in, int8_t * restrict out, int n,
int m, int cond)
}
/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu} 1 { target { no-opts
"-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli} 3 { target { no-opts "-O0"
no-opts "-Os" no-opts "-O1" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 3 { target { no-opts "-O0"
no-opts "-Os" no-opts "-O1" no-opts "-g" no-opts "-funroll-loops" no-opts "-Oz"
} } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-26.c
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-26.c
index cd9a5c8a93ef..0ff7f3b3c90f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-26.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-26.c
@@ -32,4 +32,4 @@ void f (int8_t * restrict in, int8_t * restrict out, int n,
int m, int cond)
}
/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu} 1 { target { no-opts
"-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli} 3 { target { no-opts "-O0"
no-opts "-O1" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 3 { target { no-opts "-O0"
no-opts "-O1" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" no-opts "-Oz"
} } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-36.c
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-36.c
index 35cad2df2d26..bd1585c5d06f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-36.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-36.c
@@ -22,4 +22,4 @@ void f (int8_t * restrict in, int8_t * restrict out, int n,
int cond)
}
/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]} 1 { target { no-opts
"-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0"
no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0"
no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" no-opts "-Oz" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-39.c
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-39.c
index fa5f3c610177..55740ba9610e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-39.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-39.c
@@ -16,4 +16,4 @@ void f (int8_t *base, int8_t *out, size_t m, size_t n) {
}
/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]} 1 { target { no-opts
"-O0" no-opts "-O1" no-opts "-g" no-opts "-funroll-loops" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts
[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Combine vec_duplicate + vssubu.vv to vssubu.vx on GR2VR cost
https://gcc.gnu.org/g:076b6cec4d441d628c31e1525fdc80821c63ccb9
commit 076b6cec4d441d628c31e1525fdc80821c63ccb9
Author: Pan Li
Date: Fri Jun 27 09:02:03 2025 +0800
RISC-V: Combine vec_duplicate + vssubu.vv to vssubu.vx on GR2VR cost
This patch would like to combine the vec_duplicate + vssubu.vv to the
vssubu.vx. From example as below code. The related pattern will depend
on the cost of vec_duplicate from GR2VR. Then the late-combine will
take action if the cost of GR2VR is zero, and reject the combination
if the GR2VR cost is greater than zero.
Assume we have example code like below, GR2VR cost is 0.
#define DEF_VX_BINARY(T, FUNC) \
void\
test_vx_binary (T * restrict out, T * restrict in, T x, unsigned n) \
{ \
for (unsigned i = 0; i < n; i++) \
out[i] = FUNC (in[i], x); \
}
T sat_sub(T a, T b)
{
return (a - b) & (-(T)(a >= b));
}
DEF_VX_BINARY(uint32_t, sat_sub)
Before this patch:
10 │ test_vx_binary_or_int32_t_case_0:
11 │ beq a3,zero,.L8
12 │ vsetvli a5,zero,e32,m1,ta,ma
13 │ vmv.v.x v2,a2
14 │ sllia3,a3,32
15 │ srlia3,a3,32
16 │ .L3:
17 │ vsetvli a5,a3,e32,m1,ta,ma
18 │ vle32.v v1,0(a1)
19 │ sllia4,a5,2
20 │ sub a3,a3,a5
21 │ add a1,a1,a4
22 │ vssubu.vv v1,v1,v2
23 │ vse32.v v1,0(a0)
24 │ add a0,a0,a4
25 │ bne a3,zero,.L3
After this patch:
10 │ test_vx_binary_or_int32_t_case_0:
11 │ beq a3,zero,.L8
12 │ sllia3,a3,32
13 │ srlia3,a3,32
14 │ .L3:
15 │ vsetvli a5,a3,e32,m1,ta,ma
16 │ vle32.v v1,0(a1)
17 │ sllia4,a5,2
18 │ sub a3,a3,a5
19 │ add a1,a1,a4
20 │ vssubu.vx v1,v1,a2
21 │ vse32.v v1,0(a0)
22 │ add a0,a0,a4
23 │ bne a3,zero,.L3
gcc/ChangeLog:
* config/riscv/riscv-v.cc (expand_vx_binary_vec_vec_dup): Add
new case US_MINUS.
* config/riscv/riscv.cc (riscv_rtx_costs): Ditto.
* config/riscv/vector-iterators.md: Add new op us_minus.
Signed-off-by: Pan Li
(cherry picked from commit b7fe719e449db56d665da17ca4f4ba7977da34ed)
Diff:
---
gcc/config/riscv/riscv-v.cc | 1 +
gcc/config/riscv/riscv.cc| 1 +
gcc/config/riscv/vector-iterators.md | 2 +-
3 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index a3d704e81cc4..69f2a1ece534 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -5583,6 +5583,7 @@ expand_vx_binary_vec_vec_dup (rtx op_0, rtx op_1, rtx
op_2,
case SMIN:
case UMIN:
case US_PLUS:
+case US_MINUS:
icode = code_for_pred_scalar (code, mode);
break;
default:
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index e3abcaae2a61..2cebc051a0e7 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -3996,6 +3996,7 @@ riscv_rtx_costs (rtx x, machine_mode mode, int
outer_code, int opno ATTRIBUTE_UN
case MOD:
case UMOD:
case US_PLUS:
+ case US_MINUS:
*total = get_vector_binary_rtx_cost (op, scalar2vr_cost);
break;
default:
diff --git a/gcc/config/riscv/vector-iterators.md
b/gcc/config/riscv/vector-iterators.md
index 0e1318d1447c..782544423c41 100644
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -4042,7 +4042,7 @@
])
(define_code_iterator any_int_binop_no_shift_v_vdup [
- plus minus and ior xor mult div udiv mod umod smax umax smin umin us_plus
+ plus minus and ior xor mult div udiv mod umod smax umax smin umin us_plus
us_minus
])
(define_code_iterator any_int_binop_no_shift_vdup_v [
[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Primary vector pipeline model for sifive 7 series
https://gcc.gnu.org/g:6f0e70e339cd2f2d87d766dbcce190f464bc429c commit 6f0e70e339cd2f2d87d766dbcce190f464bc429c Author: Kito Cheng Date: Thu Jun 19 14:31:42 2025 +0800 RISC-V: Primary vector pipeline model for sifive 7 series This commit introduces a primary vector pipeline model for the SiFive 7 series, that pipeline model is kind of simplified version, it only defined vector command queue, arithmetic unit, and vector load store unit. The latency of real hardware is LMUL-aware, but I realize that will complicate the model a lots, so I just use a simplified version, which all LMUL use same latency, we may improve it later once we have found meaningful performance difference. gcc/ChangeLog: * config/riscv/sifive-7.md: Add primary vector pipeline model for SiFive 7 series. (cherry picked from commit 9e9363e23dc9955d0f6b5b1669168b9b25378d79) Diff: --- gcc/config/riscv/sifive-7.md | 137 ++- 1 file changed, 136 insertions(+), 1 deletion(-) diff --git a/gcc/config/riscv/sifive-7.md b/gcc/config/riscv/sifive-7.md index b96d7eb8550e..a04b80bff04d 100644 --- a/gcc/config/riscv/sifive-7.md +++ b/gcc/config/riscv/sifive-7.md @@ -1,4 +1,4 @@ -(define_automaton "sifive_7") +(define_automaton "sifive_7,sifive_7_vec,sifive_7_vec_mem") ;; Sifive 7 Series Base Core ;; This has two pipelines, A (Address) and B (Branch). @@ -11,6 +11,14 @@ (define_cpu_unit "sifive_7_idiv" "sifive_7") (define_cpu_unit "sifive_7_fpu" "sifive_7") +;; Vector command queue +(define_cpu_unit "sifive_7_vcq" "sifive_7") +;; Vector arithmetic sequencer +(define_cpu_unit "sifive_7_va" "sifive_7_vec") +;; Vector store sequencer +(define_cpu_unit "sifive_7_vs" "sifive_7_vec_mem") +;; Vector load sequencer +(define_cpu_unit "sifive_7_vl" "sifive_7_vec_mem") (define_insn_reservation "sifive_7_load" 3 (and (eq_attr "tune" "sifive_7") @@ -165,3 +173,130 @@ (define_bypass 2 "sifive_7_fp_other" "sifive_7_store" "riscv_store_data_bypass_p") + +;; Vector pipeline +;; The latency is depend on LMUL, but we didn't model that yet since we don't +;; want to expand the rule too much unless we prove model that could get +;; meaningful performance difference. + +(define_insn_reservation "sifive_7_vsetvl" 2 + (and (eq_attr "tune" "sifive_7") + (eq_attr "type" "vsetvl_pre,vsetvl,rdvlenb,rdvl")) + "sifive_7_A") + +(define_insn_reservation "sifive_7_vec_load" 4 + (and (eq_attr "tune" "sifive_7") + (eq_attr "type" "vlde,vldm,vlds,vldux,vldox,vldff,vldr, +vlsegde,vlsegds,vlsegdux,vlsegdox,vlsegdff")) + "sifive_7_vcq,sifive_7_vl*3") + +(define_insn_reservation "sifive_7_vec_store" 4 + (and (eq_attr "tune" "sifive_7") + (eq_attr "type" "vste,vstm,vsts,vstux,vstox,vstr, +vssegte,vssegts,vssegtux,vssegtox")) + "sifive_7_vcq,sifive_7_vs*3") + +(define_insn_reservation "sifive_7_vec_ialu" 4 + (and (eq_attr "tune" "sifive_7") + (eq_attr "type" "vimovxv,vmov,vimovvx,vialu,vicalu,vext, +vshift,viminmax,vimerge,vbrev,vrev8, +vimov,vext,vbrev8,vclz,vctz,vcpop,vrol,vror,vandn")) + "sifive_7_vcq,sifive_7_va*3") + +(define_insn_reservation "sifive_7_vec_slow_ialu" 8 + (and (eq_attr "tune" "sifive_7") + (eq_attr "type" "vshift,vimul,vimuladd")) + "sifive_7_vcq,sifive_7_va*7") + +(define_insn_reservation "sifive_7_vec_cmp" 4 + (and (eq_attr "tune" "sifive_7") + (eq_attr "type" "vicmp")) + "sifive_7_vcq,sifive_7_va*3") + +(define_insn_reservation "sifive_7_vec_iwalu" 8 + (and (eq_attr "tune" "sifive_7") + (eq_attr "type" "viwalu,viwmul,viwmuladd,vnshift,vwsll")) + "sifive_7_vcq,sifive_7_va*7") + +(define_insn_reservation "sifive_7_vec_div" 16 + (and (eq_attr "tune" "sifive_7") + (eq_attr "type" "vidiv,vfdiv")) + "sifive_7_vcq,sifive_7_va*15") + +(define_insn_reservation "sifive_7_vec_fixed_point" 8 + (and (eq_attr "tune" "sifive_7") + (eq_attr "type" "vsalu,vaalu,vsmul,vsshift")) + "sifive_7_vcq,sifive_7_va*7") + +(define_insn_reservation "sifive_7_vec_narrow_fixed_point" 8 + (and (eq_attr "tune" "sifive_7") + (eq_attr "type" "vnclip")) + "sifive_7_vcq,sifive_7_va*7") + +(define_insn_reservation "sifive_7_vec_fsimple" 4 + (and (eq_attr "tune" "sifive_7") + (eq_attr "type" "vfmovvf,vfmovfv,vfclass")) + "sifive_7_vcq,sifive_7_va*3") + +(define_insn_reservation "sifive_7_vec_falu" 8 + (and (eq_attr "tune" "sifive_7") + (eq_attr "type" "vfalu,vfmul,vfmuladd,vfrecp, +vfcvtitof,vfcvtftoi,vfmerge,vfmov,vfsgnj")) + "sifive_7_vcq,sifive_7_va*7") + +(define_insn_reservation "sifive_7_vec_fcmp" 4 + (and (eq_attr "tune" "sifive_7") + (eq_attr "type" "vfcmp,vfminmax")) + "sifive_7_vcq,sifive_7_va*3") + +(define_insn_reservation "sifive_7_vec_fsqrt_fdiv" 16 + (and (eq_attr "tune" "sifive_7") + (eq_attr "type" "vfsqrt,vfd
[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Reconcile the existing test due to cost model change
https://gcc.gnu.org/g:fdc172e631327111c4ab8768c5c38fdeb3475753
commit fdc172e631327111c4ab8768c5c38fdeb3475753
Author: Pan Li
Date: Fri Jun 27 11:35:18 2025 +0800
RISC-V: Reconcile the existing test due to cost model change
The cost model change will make the default cost of vx to 2, thus
reconcile the asm check for this change.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u16.c:
Update the asm check due to cost model change.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u32.c:
Diito.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u8.c:
Ditto.
Signed-off-by: Pan Li
(cherry picked from commit db267b0d1dcabd09d9064093383e38f2596345a4)
Diff:
---
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u16.c| 2 +-
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u32.c| 2 +-
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u8.c | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u16.c
index 2261872e3de2..b32907afcbb1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u16.c
@@ -6,5 +6,5 @@
DEF_VEC_SAT_U_SUB_TRUNC_FMT_1(uint16_t, uint32_t)
/* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */
-/* { dg-final { scan-assembler-times {vssubu\.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */
/* { dg-final { scan-assembler-times {vnsrl\.wi} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u32.c
index 4250567686a6..344080cb93a7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u32.c
@@ -6,5 +6,5 @@
DEF_VEC_SAT_U_SUB_TRUNC_FMT_1(uint32_t, uint64_t)
/* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */
-/* { dg-final { scan-assembler-times {vssubu\.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */
/* { dg-final { scan-assembler-times {vnsrl\.wi} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u8.c
index 656aad70165c..492c3168216f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u8.c
@@ -6,5 +6,5 @@
DEF_VEC_SAT_U_SUB_TRUNC_FMT_1(uint8_t, uint16_t)
/* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */
-/* { dg-final { scan-assembler-times {vssubu\.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */
/* { dg-final { scan-assembler-times {vnsrl\.wi} 1 } } */
[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] Fixup dropping REG_EQUAL note in ext-dce
https://gcc.gnu.org/g:21c82c47b2c7dff14bba9e75a1e8a5a3cbbed725
commit 21c82c47b2c7dff14bba9e75a1e8a5a3cbbed725
Author: Sam James
Date: Mon Jun 23 23:28:01 2025 +0100
Fixup dropping REG_EQUAL note in ext-dce
Followup to r16-1613-g34e1e5e33ec3eb. remove_reg_equal_equiv_notes's
2nd argument is 'no_rescan' which we accidentally had on, tripping
an assert in combine or ira because we hadn't left things in a consistent
state.
Fix the thinko by enabling rescanning.
gcc/ChangeLog:
PR rtl-optimization/120795
* ext-dce.cc (ext_dce_try_optimize_insn): Enable rescan in
remove_reg_equal_equiv_notes call.
Co-authored-by: Jeff Law
(cherry picked from commit cdd678544fefc313cb1c9da0327158d3ed355f62)
Diff:
---
gcc/ext-dce.cc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/ext-dce.cc b/gcc/ext-dce.cc
index b5ccc1896494..36277b6ffede 100644
--- a/gcc/ext-dce.cc
+++ b/gcc/ext-dce.cc
@@ -445,7 +445,7 @@ ext_dce_try_optimize_insn (rtx_insn *insn, rtx set)
/* INSN may have a REG_EQUAL note indicating that the value was
sign or zero extended. That note is no longer valid since we've
just removed the extension. Just wipe the notes. */
- remove_reg_equal_equiv_notes (insn, true);
+ remove_reg_equal_equiv_notes (insn, false);
}
else
{
[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: testsuite: Skip tests providing -march/-mcpu for ILP32E/ILP64E ABIs
https://gcc.gnu.org/g:ef87b0d2cae7cef0cc7e80c557258af0039e5d8d
commit ef87b0d2cae7cef0cc7e80c557258af0039e5d8d
Author: Dimitar Dimitrov
Date: Fri Jun 20 20:57:15 2025 +0300
RISC-V: testsuite: Skip tests providing -march/-mcpu for ILP32E/ILP64E ABIs
Some test cases explicitly set -march or -mcpu with extensions which
are not compatible with the E ABI variants. This leads to spurious
errors when toolchain has been configured for RV32E base ISA and
ILP32E ABI:
cc1: error: ILP32E ABI does not support the 'D' extension
Also, test gcc.target/riscv/rvv/base/pr119164.c implicitly requires
rv64 since it explicitly selects -march=rv64gcv_zvl256b:
cc1: error: ABI requires '-march=rv32'
Testing done:
- Ensured cross riscv64-unknown-linux-gnu has no difference in test
output with and without the patch.
- For riscv32-unknown-elf there are no new failures. Test case pr119164.c
no longer fails and is now marked as unsupported.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/mcpu-xt-c908.c: Disable for E ABI variants.
* gcc.target/riscv/mcpu-xt-c908v.c: Ditto.
* gcc.target/riscv/mcpu-xt-c910.c: Ditto.
* gcc.target/riscv/mcpu-xt-c910v2.c: Ditto.
* gcc.target/riscv/mcpu-xt-c920.c: Ditto.
* gcc.target/riscv/mcpu-xt-c920v2.c: Ditto.
* gcc.target/riscv/pr118241.c: Ditto.
* gcc.target/riscv/pr120223.c: Ditto.
* gcc.target/riscv/rvv/base/pr119164.c: Disable for E ABI variants
and for 32-bit ISA.
Signed-off-by: Dimitar Dimitrov
(cherry picked from commit 81d738275f45e497c0c90ce75d407354fca7d891)
Diff:
---
gcc/testsuite/gcc.target/riscv/mcpu-xt-c908.c | 2 +-
gcc/testsuite/gcc.target/riscv/mcpu-xt-c908v.c | 2 +-
gcc/testsuite/gcc.target/riscv/mcpu-xt-c910.c | 2 +-
gcc/testsuite/gcc.target/riscv/mcpu-xt-c910v2.c| 2 +-
gcc/testsuite/gcc.target/riscv/mcpu-xt-c920.c | 2 +-
gcc/testsuite/gcc.target/riscv/mcpu-xt-c920v2.c| 2 +-
gcc/testsuite/gcc.target/riscv/pr118241.c | 2 +-
gcc/testsuite/gcc.target/riscv/pr120223.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/pr119164.c | 2 +-
9 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/gcc/testsuite/gcc.target/riscv/mcpu-xt-c908.c
b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c908.c
index cb28baf1ce72..4ad82a81dec8 100644
--- a/gcc/testsuite/gcc.target/riscv/mcpu-xt-c908.c
+++ b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c908.c
@@ -1,4 +1,4 @@
-/* { dg-do compile } */
+/* { dg-do compile { target { ! riscv_abi_e } } } */
/* { dg-skip-if "-march given" { *-*-* } { "-march=*" } } */
/* { dg-options "-mcpu=xt-c908" { target { rv64 } } } */
/* XuanTie C908 => rv64imafdc_zicbom_zicbop_zicboz_zicntr_zicsr_zifencei_
diff --git a/gcc/testsuite/gcc.target/riscv/mcpu-xt-c908v.c
b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c908v.c
index 1b1ee188229f..bb9e3109920a 100644
--- a/gcc/testsuite/gcc.target/riscv/mcpu-xt-c908v.c
+++ b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c908v.c
@@ -1,4 +1,4 @@
-/* { dg-do compile } */
+/* { dg-do compile { target { ! riscv_abi_e } } } */
/* { dg-skip-if "-march given" { *-*-* } { "-march=*" } } */
/* { dg-options "-mcpu=xt-c908v" { target { rv64 } } } */
/* XuanTie C908v => rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicsr_zifencei_
diff --git a/gcc/testsuite/gcc.target/riscv/mcpu-xt-c910.c
b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c910.c
index 1e276659c3ea..397e7b192670 100644
--- a/gcc/testsuite/gcc.target/riscv/mcpu-xt-c910.c
+++ b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c910.c
@@ -1,4 +1,4 @@
-/* { dg-do compile } */
+/* { dg-do compile { target { ! riscv_abi_e } } } */
/* { dg-skip-if "-march given" { *-*-* } { "-march=*" } } */
/* { dg-options "-mcpu=xt-c910" { target { rv64 } } } */
/* XuanTie C910 => rv64imafdc_zicntr_zicsr_zifencei_zihpm_zfh_xtheadba_
diff --git a/gcc/testsuite/gcc.target/riscv/mcpu-xt-c910v2.c
b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c910v2.c
index 6a54f0988780..9e39c9f89eb4 100644
--- a/gcc/testsuite/gcc.target/riscv/mcpu-xt-c910v2.c
+++ b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c910v2.c
@@ -1,4 +1,4 @@
-/* { dg-do compile } */
+/* { dg-do compile { target { ! riscv_abi_e } } } */
/* { dg-skip-if "-march given" { *-*-* } { "-march=*" } } */
/* { dg-options "-mcpu=xt-c910v2" { target { rv64 } } } */
/* XuanTie C910v2 => rv64imafdc_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_
diff --git a/gcc/testsuite/gcc.target/riscv/mcpu-xt-c920.c
b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c920.c
index 6bcd687e7424..4cce90a1e945 100644
--- a/gcc/testsuite/gcc.target/riscv/mcpu-xt-c920.c
+++ b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c920.c
@@ -1,4 +1,4 @@
-/* { dg-do compile } */
+/* { dg-do compile { target { ! riscv_abi_e } } } */
/* { dg-skip-if "-march given" { *-*-* } { "-march=*" } } */
/* { dg-options "-mcpu=xt-c920" { target { rv64 } } } */
/* XuanTie c920 =>
rv64i
[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [committed] [PR rtl-optimization/120242] Fix SUBREG_PROMOTED_VAR_P after ext-dce's actions
https://gcc.gnu.org/g:c09ee710d2fe89169946e1d2909d9fa27da47b8b
commit c09ee710d2fe89169946e1d2909d9fa27da47b8b
Author: Jeff Law
Date: Mon Jun 30 14:38:33 2025 -0600
[committed] [PR rtl-optimization/120242] Fix SUBREG_PROMOTED_VAR_P after
ext-dce's actions
I've gone back and forth of these problems multiple times. We have two
passes,
ext-dce and combine which eliminate extensions using totally different
mechanisms.
ext-dce looks for cases where the state of upper bits in an object aren't
observable and if they aren't observable, then eliminates extensions which
set
those bits.
combine looks for cases where we know the state of the upper bits and can
prove
an extension is just setting those bits to their prior value. Combine also
looks for cases where the precise extension isn't really important, just the
knowledge that the upper bits are zero or sign extended from a narrower mode
is needed.
Combine relies heavily on the SUBREG_PROMOTED_VAR state to do its job. If
the
actions of ext-dce (or any other pass for that matter) make
SUBREG_PROMOTED_VAR's state inconsistent with combine's expectations, then
combine can end up generating incorrect code.
--
When ext-dce eliminates an extension and turns it into a subreg copy
(without
any known SUBREG_PROMOTED_VAR state). Since we can no longer guarantee the
destination object has any known extension state, we scurry around and wipe
SUBREG_PROMOTED_VAR state for the destination object.
That's fine and dandy, but ultimately insufficient. Consider if the
destination of the optimized extension was used as a source in a simple copy
insn. Furthermore assume that the destination of that copy is used within a
SUBREG expression with SUBREG_PROMOTED_VAR set. ext-dce's actions have
clobbered the SUBREG_PROMOTED_VAR state on the destination of that copy,
albeit
indirectly.
This patch addresses this problem by taking the set of pseudos directly
impacted by ext-dce's actions and expands that set by building a transitive
closure for pseudos connected via copies. We then scurry around finding
SUBREG_PROMOTED_VAR state to wipe for everything in that expanded set of
pseudos. Voila, everything just works.
--
The other approach here would be to further expand the liveness sets inside
ext-dce. That's a simpler path forward, but ultimately regresses the
quality
of codes we do care about.
One good piece of news is that with the transitive closure bits in place, we
can eliminate a bit of the live set expansion we had in place for
SUBREG_PROMOTED_VAR objects.
--
So let's take one case of the 5 that have been reported.
In ext-dce we have this insn:
> (insn 29 27 30 3 (set (reg:DI 134 [ al_lsm.9 ])
> (zero_extend:DI (subreg:HI (reg:DI 162) 0))) "j.c":17:17 552
{*zero_extendhidi2_bitmanip}
> (expr_list:REG_DEAD (reg:DI 162)
> (nil)))
There are reachable uses of (reg 134):
> (insn 49 47 52 6 (set (mem/c:HI (lo_sum:DI (reg/f:DI 186)
> (symbol_ref:DI ("al") [flags 0x86] )) [2 al+0 S2 A16])
> (subreg/s/v:HI (reg:DI 134 [ al_lsm.9 ]) 0)) 279 {*movhi_internal}
> (expr_list:REG_DEAD (reg/f:DI 186)
> (nil)))Obviously safe if we were to remove the extension.
> (insn 52 49 53 6 (set (reg:DI 176)
> (and:DI (reg:DI 134 [ al_lsm.9 ])
> (const_int 5 [0x5]))) "j.c":21:12 106 {*anddi3}
> (expr_list:REG_DEAD (reg:DI 134 [ al_lsm.9 ])
> (nil)))
> (insn 53 52 56 6 (set (reg:SI 177 [ _8 ])
> (zero_extend:SI (subreg:HI (reg:DI 176) 0))) "j.c":21:12 551
{*zero_extendhisi2_bitmanip}
> (expr_list:REG_DEAD (reg:DI 176)
> (nil))) Safe to remove the extension as we only read the low 16
bits from the destination register (reg 176) in insn 53.
> (insn 27 26 29 3 (set (reg:DI 162)
> (sign_extend:DI (plus:SI (subreg/s/v:SI (reg:DI 134 [ al_lsm.9 ])
0)
> (const_int 1 [0x1] "j.c":17:17 8 {addsi3_extended}
> (expr_list:REG_DEAD (reg:DI 134 [ al_lsm.9 ])
> (nil)))
> (insn 29 27 30 3 (set (reg:DI 134 [ al_lsm.9 ])
> (zero_extend:DI (subreg:HI (reg:DI 162) 0))) "j.c":17:17 552
{*zero_extendhidi2_bitmanip}
> (expr_list:REG_DEAD (reg:DI 162)
> (nil)))
Again, not as obvious as the first case, but we only read the low 16 bits
from
(reg 162) in insn 29. So those upper bits in (reg 134) don't matter.
> (insn 26 92 27 3 (set (reg:DI 144 [ ivtmp.17 ])
> (reg:DI 134 [ al_lsm.9 ])) 277 {*movdi_64bit}
> (nil))
> (insn 30 29 31 3 (set (reg:DI 135 [ al.2_3 ])
> (sign_extend:DI (subreg/s/v:HI (reg:DI 144 [ ivtmp.17 ])
[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [RISC-V][PR target/118886] Refine when two insns are signaled as fusion candidates
https://gcc.gnu.org/g:f7d3710a20c4cd56c09defc2dc65c4732154
commit f7d3710a20c4cd56c09defc2dc65c4732154
Author: Jeff Law
Date: Thu Jul 3 06:44:31 2025 -0600
[RISC-V][PR target/118886] Refine when two insns are signaled as fusion
candidates
A number of folks have had their fingers in this code and it's going to
take a
few submissions to do everything we want to do.
This patch is primarily concerned with avoiding signaling that fusion can
occur
in cases where it obviously should not be signaling fusion.
Every DEC based fusion I'm aware of requires the first instruction to set a
destination register that is both used and set again by the second
instruction.
If the two instructions set different registers, then the destination of the
first instruction was not dead and would need to have a result produced.
This is complicated by the fact that we have pseudo registers prior to
reload.
So the approach we take is to signal fusion prior to reload even if the
destination registers don't match. Post reload we require them to match.
That allows us to clean up the code ever-so-slightly.
Second, we sometimes signaled fusion into loads that weren't scalar integer
loads. I'm not aware of a design that's fusing into FP loads or vector
loads.
So those get rejected explicitly.
Third, the store pair "fusion" code is cleaned up a little. We use fusion
to
model store pair commits since the basic properties for detection are the
same.
The point where they "fuse" is different. Also this code liked to "return
false" at each step along the way if fusion wasn't possible. Future work
for
additional fusion cases makes that behavior undesirable. So the logic gets
reworked a little bit to be more friendly to future work.
Fourth, if we already fused the previous instruction, then we can't fuse it
again. Signaling fusion in that case is, umm, bad as it creates an atomic
blob
of code from a scheduling standpoint.
Hopefully I got everything correct with extracting this work out of a larger
set of changes 🙂 We will contribute some instrumentation & testing code so
if
I botched things in a major way we'll soon have a way to test that and I'll
be
on the hook to fix any goof's.
From a correctness standpoint this should be a big fat nop. We've seen this
make measurable differences in pico benchmarks, but obviously as you scale
up
to bigger stuff the gains largely disappear into the noise.
This has been through Ventana's internal CI and my tester. I'll obviously
wait
for a verdict from the pre-commit tester.
PR target/118886
gcc/
* config/riscv/riscv.cc (riscv_macro_fusion_pair_p): Check
for fusion being disabled earlier. If PREV is already fused,
then it can't be fused again. Be more selective about fusing
when the destination registers do not match. Don't fuse into
loads that aren't scalar integer modes. Revamp store pair
commit support.
Co-authored-by: Daniel Barboza
Co-authored-by: Shreya Munnangi
(cherry picked from commit 83d19b5d842dadc1720b57486d4675a238966ba4)
Diff:
---
gcc/config/riscv/riscv.cc | 137 +++---
1 file changed, 80 insertions(+), 57 deletions(-)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 52143e0e85d7..afdacaf6b8a7 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -10209,17 +10209,33 @@ riscv_fusion_enabled_p(enum riscv_fusion_pairs op)
static bool
riscv_macro_fusion_pair_p (rtx_insn *prev, rtx_insn *curr)
{
+ /* If fusion is not enabled, then there's nothing to do. */
+ if (!riscv_macro_fusion_p ())
+return false;
+
+ /* If PREV is already marked as fused, then we can't fuse CURR with PREV
+ and if we were to fuse them we'd end up with a blob of insns that
+ essentially are an atomic unit which is bad for scheduling. */
+ if (SCHED_GROUP_P (prev))
+return false;
+
rtx prev_set = single_set (prev);
rtx curr_set = single_set (curr);
/* prev and curr are simple SET insns i.e. no flag setting or branching. */
bool simple_sets_p = prev_set && curr_set && !any_condjump_p (curr);
+ bool sched1 = can_create_pseudo_p ();
- if (!riscv_macro_fusion_p ())
-return false;
+ unsigned int prev_dest_regno = (REG_P (SET_DEST (prev_set))
+ ? REGNO (SET_DEST (prev_set))
+ : FIRST_PSEUDO_REGISTER);
+ unsigned int curr_dest_regno = (REG_P (SET_DEST (curr_set))
+ ? REGNO (SET_DEST (curr_set))
+ : FIRST_PSEUDO_REGISTER);
if (simple_sets_p
&& (riscv_fusion_enabled_p (RISCV_FUSE_ZEXTW)
- || riscv
[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] Refactor record_function_versions.
https://gcc.gnu.org/g:1d5cfe644cd2047badb9e247dba2d3d9596e273e
commit 1d5cfe644cd2047badb9e247dba2d3d9596e273e
Author: Alfie Richards
Date: Thu Mar 27 14:12:06 2025 +
Refactor record_function_versions.
Renames record_function_versions to add_function_version, and make it
explicit that it is adding a single version to the function structure.
Additionally, change the insertion point to always maintain priority
ordering
of the versions.
This allows for removing logic for moving the default to the first
position which was duplicated across target specific code and enables
easier reasoning about function sets.
gcc/ChangeLog:
* cgraph.cc (cgraph_node::record_function_versions): Refactor and
rename to...
(cgraph_node::add_function_version): new function.
* cgraph.h (cgraph_node::record_function_versions): Refactor and
rename to...
(cgraph_node::add_function_version): new function.
* config/aarch64/aarch64.cc
(aarch64_get_function_versions_dispatcher):
Remove reordering.
* config/i386/i386-features.cc
(ix86_get_function_versions_dispatcher):
Remove reordering.
* config/riscv/riscv.cc (riscv_get_function_versions_dispatcher):
Remove reordering.
* config/rs6000/rs6000.cc (rs6000_get_function_versions_dispatcher):
Remove reordering.
gcc/cp/ChangeLog:
* decl.cc (maybe_version_functions): Change record_function_versions
call to add_function_version.
(cherry picked from commit 5ed7e29d5d903f469d32d8f945f094e4c2881418)
Diff:
---
gcc/cgraph.cc| 75
gcc/cgraph.h | 6 ++--
gcc/config/aarch64/aarch64.cc| 34 --
gcc/config/i386/i386-features.cc | 34 --
gcc/config/riscv/riscv.cc| 38
gcc/config/rs6000/rs6000.cc | 35 ---
gcc/cp/decl.cc | 10 +-
7 files changed, 81 insertions(+), 151 deletions(-)
diff --git a/gcc/cgraph.cc b/gcc/cgraph.cc
index 6ae6a97f6f56..feaeebec40ba 100644
--- a/gcc/cgraph.cc
+++ b/gcc/cgraph.cc
@@ -231,45 +231,60 @@ cgraph_node::delete_function_version_by_decl (tree decl)
decl_node->remove ();
}
-/* Record that DECL1 and DECL2 are semantically identical function
+/* Add decl to the structure of semantically identical function versions.
+ The node is inserted at the point maintaining the priority ordering on the
versions. */
void
-cgraph_node::record_function_versions (tree decl1, tree decl2)
+cgraph_node::add_function_version (cgraph_function_version_info *fn_v,
+ tree decl)
{
- cgraph_node *decl1_node = cgraph_node::get_create (decl1);
- cgraph_node *decl2_node = cgraph_node::get_create (decl2);
- cgraph_function_version_info *decl1_v = NULL;
- cgraph_function_version_info *decl2_v = NULL;
- cgraph_function_version_info *before;
- cgraph_function_version_info *after;
-
- gcc_assert (decl1_node != NULL && decl2_node != NULL);
- decl1_v = decl1_node->function_version ();
- decl2_v = decl2_node->function_version ();
-
- if (decl1_v != NULL && decl2_v != NULL)
-return;
-
- if (decl1_v == NULL)
-decl1_v = decl1_node->insert_new_function_version ();
+ cgraph_node *decl_node = cgraph_node::get_create (decl);
+ cgraph_function_version_info *decl_v = NULL;
- if (decl2_v == NULL)
-decl2_v = decl2_node->insert_new_function_version ();
+ gcc_assert (decl_node != NULL);
- /* Chain decl2_v and decl1_v. All semantically identical versions
- will be chained together. */
+ decl_v = decl_node->function_version ();
- before = decl1_v;
- after = decl2_v;
+ /* If the nodes are already linked, skip. */
+ if (decl_v != NULL && (decl_v->next || decl_v->prev))
+return;
- while (before->next != NULL)
-before = before->next;
+ if (decl_v == NULL)
+decl_v = decl_node->insert_new_function_version ();
+
+ gcc_assert (decl_v);
+ gcc_assert (fn_v);
+
+ /* Go to start of the FMV structure. */
+ while (fn_v->prev)
+fn_v = fn_v->prev;
+
+ cgraph_function_version_info *insert_point_before = NULL;
+ cgraph_function_version_info *insert_point_after = fn_v;
+
+ /* Find the insertion point for the new version to maintain ordering.
+ The default node must always go at the beginning. */
+ if (!is_function_default_version (decl))
+while (insert_point_after
+ && (targetm.compare_version_priority
+(decl, insert_point_after->this_node->decl) > 0
+ || is_function_default_version
+ (insert_point_after->this_node->decl)
+ || lookup_attribute
+ ("target_clones",
+DECL_ATTRIBUTES (insert_point_after->this_node->decl
+ {
+ insert_poi
[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [PATCH] [RISC-V] Fix shift type for RVV interleaved stepped patterns [PR120356]
https://gcc.gnu.org/g:218279a4653032325cbe13c98f8ea38a5d36
commit 218279a4653032325cbe13c98f8ea38a5d36
Author: Alexey Merzlyakov
Date: Wed Jul 2 11:29:00 2025 -0600
[PATCH] [RISC-V] Fix shift type for RVV interleaved stepped patterns
[PR120356]
It corrects the shift type of interleaved stepped patterns for const vector
expanding in LRA. The shift instruction was initially LSHIFTRT, and it seems
still should be the same type for both LRA and other cases.
PR target/120356
gcc/ChangeLog:
* config/riscv/riscv-v.cc
(expand_const_vector_interleaved_stepped_npatterns):
Fix ASHIFT to LSHIFTRT insn.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/pr120356.c: New test.
(cherry picked from commit 9c1ed63e4c6b0f80dd47ce421dd7d80d52c38fd3)
Diff:
---
gcc/config/riscv/riscv-v.cc| 2 +-
.../gcc.target/riscv/rvv/autovec/pr120356.c| 26 ++
2 files changed, 27 insertions(+), 1 deletion(-)
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 69f2a1ece534..ce1633c72dee 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -1598,7 +1598,7 @@ expand_const_vector_interleaved_stepped_npatterns (rtx
target, rtx src,
shifted_vid = gen_reg_rtx (mode);
rtx shift = gen_int_mode (1, Xmode);
rtx shift_ops[] = {shifted_vid, vid, shift};
- emit_vlmax_insn (code_for_pred_scalar (ASHIFT, mode), BINARY_OP,
+ emit_vlmax_insn (code_for_pred_scalar (LSHIFTRT, mode), BINARY_OP,
shift_ops);
}
else
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr120356.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr120356.c
new file mode 100644
index ..2913f04e4c83
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr120356.c
@@ -0,0 +1,26 @@
+/* { dg-do run } */
+/* { dg-require-effective-target rvv_zvl256b_ok } */
+/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -mrvv-vector-bits=zvl -O2"
} */
+
+unsigned char a = 5;
+long long c[18];
+
+static void d ()
+{
+ for (short i = 0; i < 60; i += 65413)
+for (char j = 0; j < 18; j++)
+ {
+ for (char k = 0; k < 18; k++)
+ a *= 143;
+ for (char k = 0; k < 6; k++)
+ for (char l = 0; l < 18; l++)
+ c[l] = 0;
+ }
+}
+
+int main ()
+{
+ d ();
+ if (a + c[0] != 69)
+__builtin_abort ();
+}
[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] ext-dce: Don't refine live width with SUBREG mode if !TRULY_NOOP_TRUNCATION_MODES_P [PR 120050]
https://gcc.gnu.org/g:82b78b6bce0687e55834ebb8c9ec9d2a200dae0c commit 82b78b6bce0687e55834ebb8c9ec9d2a200dae0c Author: Xi Ruoyao Date: Sun May 11 16:44:31 2025 +0800 ext-dce: Don't refine live width with SUBREG mode if !TRULY_NOOP_TRUNCATION_MODES_P [PR 120050] If we see a promoted subreg and TRULY_NOOP_TRUNCATION says the truncation is not a noop, then all bits of the inner reg are live. We cannot reduce the live mask to that of the mode of the subreg. gcc/ChangeLog: PR rtl-optimization/120050 * ext-dce.cc (ext_dce_process_uses): Break early if a SUBREG in rhs is promoted and the truncation from the inner mode to the outer mode is not a noop when handling SETs. (cherry picked from commit 65f3a439c4f76fe780a30ac66969f51035c4bf98) Diff: --- gcc/ext-dce.cc | 17 +++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/gcc/ext-dce.cc b/gcc/ext-dce.cc index 36277b6ffede..df17b018bf1f 100644 --- a/gcc/ext-dce.cc +++ b/gcc/ext-dce.cc @@ -35,6 +35,7 @@ along with GCC; see the file COPYING3. If not see #include "print-rtl.h" #include "dbgcnt.h" #include "diagnostic-core.h" +#include "target.h" /* These should probably move into a C++ class. */ static vec livein; @@ -769,13 +770,25 @@ ext_dce_process_uses (rtx_insn *insn, rtx obj, We don't want to mark those bits live unnecessarily as that inhibits extension elimination in important cases such as those in Coremark. So we need that -outer code. */ +outer code. + +But if !TRULY_NOOP_TRUNCATION_MODES_P, the mode +change performed by Y would normally need to be a +TRUNCATE rather than a SUBREG. It is probably the +guarantee provided by SUBREG_PROMOTED_VAR_P that +allows the SUBREG in Y as an exception. We must +therefore preserve that guarantee and treat the +upper bits of the inner register as live +regardless of the outer code. See PR 120050. */ if (!REG_P (SUBREG_REG (y)) || (SUBREG_PROMOTED_VAR_P (y) && ((GET_CODE (SET_SRC (x)) == SIGN_EXTEND && SUBREG_PROMOTED_SIGNED_P (y)) || (GET_CODE (SET_SRC (x)) == ZERO_EXTEND - && SUBREG_PROMOTED_UNSIGNED_P (y) + && SUBREG_PROMOTED_UNSIGNED_P (y)) + || !TRULY_NOOP_TRUNCATION_MODES_P ( + GET_MODE (y), + GET_MODE (SUBREG_REG (y)) break; bit = subreg_lsb (y).to_constant ();
[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [RISC-V] Correct CFA notes for stack-clash protection [PR120714]
https://gcc.gnu.org/g:9576acb2f212389cdfb74eee325905b072a77063
commit 9576acb2f212389cdfb74eee325905b072a77063
Author: Alexey Merzlyakov
Date: Mon Jun 30 13:58:29 2025 -0600
[RISC-V] Correct CFA notes for stack-clash protection [PR120714]
Fixes incorrect SP-addresses used in CFA notes for the stack probes
unrelative to the frame's top. It applied to the RISC-V targets code
generation when the stack-clash protection is enabled.
PR target/120714
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_allocate_and_probe_stack_space):
Fix SP-addresses in REG_CFA_DEF_CFA notes for stack-clash case.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/pr120714.c: New test.
(cherry picked from commit 45a17e3081120f51f8e8b1d7cda73c7d89453e85)
Diff:
---
gcc/config/riscv/riscv.cc | 13 --
gcc/testsuite/gcc.target/riscv/pr120714.c | 40 +++
2 files changed, 51 insertions(+), 2 deletions(-)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 2cebc051a0e7..52143e0e85d7 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -8978,12 +8978,20 @@ riscv_allocate_and_probe_stack_space (rtx temp1,
HOST_WIDE_INT size)
temp2 = riscv_force_temporary (temp2, gen_int_mode (rounded_size,
Pmode));
insn = emit_insn (gen_sub3_insn (temp2, stack_pointer_rtx, temp2));
+ /* The size does not represent actual stack pointer address shift
+from the top of the frame, as it might be lowered before.
+To consider the correct SP addresses for the CFA notes, it is needed
+to correct them with the initial offset value. */
+ HOST_WIDE_INT initial_cfa_offset
+ = cfun->machine->frame.total_size.to_constant () - size;
+
if (!frame_pointer_needed)
{
/* We want the CFA independent of the stack pointer for the
duration of the loop. */
add_reg_note (insn, REG_CFA_DEF_CFA,
- plus_constant (Pmode, temp1, rounded_size));
+ plus_constant (Pmode, temp1,
+ initial_cfa_offset + rounded_size));
RTX_FRAME_RELATED_P (insn) = 1;
}
@@ -8996,7 +9004,8 @@ riscv_allocate_and_probe_stack_space (rtx temp1,
HOST_WIDE_INT size)
{
insn = get_last_insn ();
add_reg_note (insn, REG_CFA_DEF_CFA,
- plus_constant (Pmode, stack_pointer_rtx, rounded_size));
+ plus_constant (Pmode, stack_pointer_rtx,
+ initial_cfa_offset + rounded_size));
RTX_FRAME_RELATED_P (insn) = 1;
}
diff --git a/gcc/testsuite/gcc.target/riscv/pr120714.c
b/gcc/testsuite/gcc.target/riscv/pr120714.c
new file mode 100644
index ..dd71a3e11d3d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/pr120714.c
@@ -0,0 +1,40 @@
+/* Test checking that the backtrace on large frame size with additional
+ SP shift in the prologue won't broken when compiled with the
+ -fstack-clash-protection option. */
+/* { dg-do run { target { *-*-linux* } } } */
+/* -O0 does not have enough optimizations.
+ -O2/-O3 does inline and reduces number of addresses in the backtrace. */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-O2" "-O3" } } */
+/* { dg-options "-g -fstack-clash-protection" } */
+
+#include
+
+#define MAX 4000
+
+void goo ()
+{
+ int addresses;
+ void *buffer[10];
+
+ addresses = backtrace (buffer, 10);
+ if (addresses != 6)
+__builtin_abort ();
+}
+
+int foo (int a)
+{
+ long long A[MAX];
+ for (int i = 0; i < MAX; i++)
+A[i] = i;
+
+ goo ();
+
+ return A[a % MAX];
+}
+
+int main ()
+{
+ if (foo (20) != 20)
+__builtin_abort ();
+ return 0;
+}
[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vssubu.vv combine case 1 with GR2VR cost 0, 1 and 2
https://gcc.gnu.org/g:d96b59c82b4185b29c82dddfd1adf0035a3b723e
commit d96b59c82b4185b29c82dddfd1adf0035a3b723e
Author: Pan Li
Date: Fri Jun 27 09:09:08 2025 +0800
RISC-V: Add test for vec_duplicate + vssubu.vv combine case 1 with GR2VR
cost 0, 1 and 2
Add asm dump check test for vec_duplicate + vssubu.vv combine to
vssubu.vx, with the GR2VR cost is 0, 1 and 2.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u16.c: Add asm check
for vssubu.vx combine.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u8.c: Ditto.
Signed-off-by: Pan Li
(cherry picked from commit ff87aefc061d7de3b233bfe034fb29cc253f77a9)
Diff:
---
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u16.c | 2 ++
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u32.c | 2 ++
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u64.c | 2 ++
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u8.c | 2 ++
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u16.c | 2 ++
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u32.c | 2 ++
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u64.c | 2 ++
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u8.c | 2 ++
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u16.c | 2 ++
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u32.c | 2 ++
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u64.c | 2 ++
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u8.c | 2 ++
12 files changed, 24 insertions(+)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u16.c
index de10d66a1b23..afb5a8513a98 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u16.c
@@ -18,6 +18,7 @@ DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_1_WARP(T), max,
VX_BINARY_FUNC_BODY_X8)
DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_0_WARP(T), min, VX_BINARY_FUNC_BODY_X8)
DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_1_WARP(T), min, VX_BINARY_FUNC_BODY_X8)
DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_ADD_FUNC_WRAP(T), sat_add,
VX_BINARY_FUNC_BODY_X8)
+DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_SUB_FUNC_WRAP(T), sat_sub,
VX_BINARY_FUNC_BODY_X8)
/* { dg-final { scan-assembler {vadd.vx} } } */
/* { dg-final { scan-assembler {vsub.vx} } } */
@@ -30,3 +31,4 @@ DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_ADD_FUNC_WRAP(T), sat_add,
VX_BINARY_FUNC_BOD
/* { dg-final { scan-assembler {vmaxu.vx} } } */
/* { dg-final { scan-assembler {vminu.vx} } } */
/* { dg-final { scan-assembler {vsaddu.vx} } } */
+/* { dg-final { scan-assembler {vssubu.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u32.c
index 2e59da06c979..a907e9b7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u32.c
@@ -18,6 +18,7 @@ DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_1_WARP(T), max,
VX_BINARY_FUNC_BODY_X4)
DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_0_WARP(T), min, VX_BINARY_FUNC_BODY_X4)
DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_1_WARP(T), min, VX_BINARY_FUNC_BODY_X4)
DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_ADD_FUNC_WRAP(T), sat_add,
VX_BINARY_FUNC_BODY_X4)
+DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_SUB_FUNC_WRAP(T), sat_sub,
VX_BINARY_FUNC_BODY_X4)
/* { dg-final { scan-assembler {vadd.vx} } } */
/* { dg-final { scan-assembler {vsub.vx} } } */
@@ -29,3 +30,4 @@ DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_ADD_FUNC_WRAP(T), sat_add,
VX_BINARY_FUNC_BOD
/* { dg-final { scan-assembler {vremu.vx} } } */
/* { dg-final { scan-assembler {vmaxu.vx} } } */
/* { dg-final { scan-assembler {vminu.vx} } } */
+/* { dg-final { scan-assembler {vssubu.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u64.c
index 064ed1f2e892..efabf9930f0f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u64.c
@@ -18,6 +18,7 @@ DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_1_WARP(T), max,
VX_BINARY_FUNC_BODY)
DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_0_WARP(T), min, VX_BINARY_FU
[gcc r15-9918] middle-end: Fix complex lowering of cabs with no LHS [PR120369]
https://gcc.gnu.org/g:2cb1108c0929311f73fc9210d29681ba49607b8d
commit r15-9918-g2cb1108c0929311f73fc9210d29681ba49607b8d
Author: Andrew Pinski
Date: Tue May 20 13:21:28 2025 -0700
middle-end: Fix complex lowering of cabs with no LHS [PR120369]
This was introduced by r15-1797-gd8fe4f05ef448e . I had missed that
the LHS of the cabs call could be NULL. This seems to only happen at -O0,
I tried to produce one that happens at -O1 but needed many different
options to prevent the removal of the call.
Anyways the fix is just keep around the call if the LHS is null.
Bootstrapped and tested on x86_64-linux-gnu.
PR middle-end/120369
gcc/ChangeLog:
* tree-complex.cc (gimple_expand_builtin_cabs): Return early
if the LHS of cabs is null.
gcc/testsuite/ChangeLog:
* gcc.dg/torture/pr120369-1.c: New test.
Signed-off-by: Andrew Pinski
(cherry picked from commit 95c74f354ae3186e84fbada22d2e7f3845dbb659)
Diff:
---
gcc/testsuite/gcc.dg/torture/pr120369-1.c | 9 +
gcc/tree-complex.cc | 4
2 files changed, 13 insertions(+)
diff --git a/gcc/testsuite/gcc.dg/torture/pr120369-1.c
b/gcc/testsuite/gcc.dg/torture/pr120369-1.c
new file mode 100644
index ..4c20fb0932f0
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/torture/pr120369-1.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* PR middle-end/120369 */
+
+/* Make sure cabs without a lhs does not cause an ICE. */
+void f()
+{
+ double _Complex z = 1.0;
+ __builtin_cabs(z);
+}
diff --git a/gcc/tree-complex.cc b/gcc/tree-complex.cc
index 8a812d4bf9b0..e339b3a5b377 100644
--- a/gcc/tree-complex.cc
+++ b/gcc/tree-complex.cc
@@ -1715,6 +1715,10 @@ gimple_expand_builtin_cabs (gimple_stmt_iterator *gsi,
gimple *old_stmt)
tree lhs = gimple_call_lhs (old_stmt);
+ /* If there is not a LHS, then just keep the statement around. */
+ if (!lhs)
+return;
+
real_part = extract_component (gsi, arg, false, true);
imag_part = extract_component (gsi, arg, true, true);
location_t loc = gimple_location (old_stmt);
[gcc(refs/users/mikael/heads/move_alloc_pre_post_v02)] fortran: Add preliminary code of MOVE_ALLOC arguments
https://gcc.gnu.org/g:5ae9342ba36fc7f7639b28997b73f3e356979768
commit 5ae9342ba36fc7f7639b28997b73f3e356979768
Author: Mikael Morin
Date: Thu Jul 3 16:27:14 2025 +0200
fortran: Add preliminary code of MOVE_ALLOC arguments
Add the preliminary code produced for the evaluation of arguments FROM
and TO of the MOVE_ALLOC intrinsic before using their values. Before
this change, the preliminary code was ignored, limiting the validity of
the implementation of MOVE_ALLOC to simple cases without preliminary
code.
This change also adds the cleanup code of the same arguments. It
doesn't make any difference on the testcase though. Because of the
limited set of arguments that are allowed (variables or components
without subreference), it is possible that the cleanup code is actually
guaranteed to be empty. At least adding the cleanup code makes the
array case consistent with the scalar case.
gcc/fortran/ChangeLog:
* trans-intrinsic.cc (conv_intrinsic_move_alloc): Add pre and
post code for the FROM and TO arguments.
gcc/testsuite/ChangeLog:
* gfortran.dg/move_alloc_20.f03: New test.
Diff:
---
gcc/fortran/trans-intrinsic.cc | 5 +
gcc/testsuite/gfortran.dg/move_alloc_20.f03 | 151
2 files changed, 156 insertions(+)
diff --git a/gcc/fortran/trans-intrinsic.cc b/gcc/fortran/trans-intrinsic.cc
index f1bfd3eee510..be984271d6a8 100644
--- a/gcc/fortran/trans-intrinsic.cc
+++ b/gcc/fortran/trans-intrinsic.cc
@@ -13101,6 +13101,8 @@ conv_intrinsic_move_alloc (gfc_code *code)
}
gfc_conv_expr_descriptor (&to_se, to_expr);
gfc_conv_expr_descriptor (&from_se, from_expr);
+ gfc_add_block_to_block (&block, &to_se.pre);
+ gfc_add_block_to_block (&block, &from_se.pre);
/* For coarrays, call SYNC ALL if TO is already deallocated as MOVE_ALLOC
is an image control "statement", cf. IR F08/0040 in 12-006A. */
@@ -13174,6 +13176,9 @@ conv_intrinsic_move_alloc (gfc_code *code)
if (fin_label)
gfc_add_expr_to_block (&block, build1_v (LABEL_EXPR, fin_label));
+ gfc_add_block_to_block (&block, &to_se.post);
+ gfc_add_block_to_block (&block, &from_se.post);
+
return gfc_finish_block (&block);
}
diff --git a/gcc/testsuite/gfortran.dg/move_alloc_20.f03
b/gcc/testsuite/gfortran.dg/move_alloc_20.f03
new file mode 100644
index ..20403c300287
--- /dev/null
+++ b/gcc/testsuite/gfortran.dg/move_alloc_20.f03
@@ -0,0 +1,151 @@
+! { dg-do run }
+!
+! Check the presence of the pre and post code of the FROM and TO arguments
+! of the MOVE_ALLOC intrinsic subroutine.
+
+module m
+ implicit none
+ type :: t
+integer, allocatable :: a(:)
+ end type
+end module
+
+module pre
+ use m
+ implicit none
+ private
+ public :: check_pre
+
+contains
+
+ subroutine check_pre
+integer, parameter :: n = 5
+type(t) :: x(n)
+integer, allocatable :: tmp(:)
+integer :: array(4) = [ -1, 0, 1, 2 ]
+integer :: i
+
+if (allocated(tmp)) error stop 1
+
+tmp = [17]
+
+if (.not. allocated(tmp)) error stop 11
+if (any(shape(tmp) /= [1])) error stop 12
+if (any(tmp /= [17])) error stop 13
+do i=1,n
+ if (allocated(x(i)%a)) error stop 14
+end do
+
+! Check that the index of X is properly computed for the evaluation of TO.
+call move_alloc(tmp, x(sum(array))%a)
+
+do i=1,n
+ if (i == 2) cycle
+ if (allocated(x(i)%a)) error stop 21
+end do
+if (.not. allocated(x(2)%a)) error stop 22
+if (any(shape(x(2)%a) /= [1])) error stop 23
+if (any(x(2)%a /= [17])) error stop 24
+if (allocated(tmp)) error stop 25
+
+! Check that the index of X is properly computed for the evaluation of
FROM.
+call move_alloc(x(sum(array))%a, tmp)
+
+if (.not. allocated(tmp)) error stop 31
+if (any(shape(tmp) /= [1])) error stop 32
+if (any(tmp /= [17])) error stop 33
+do i=1,n
+ if (allocated(x(i)%a)) error stop 34
+end do
+ end subroutine
+
+end module
+
+module post
+ use m
+ implicit none
+ private
+ public :: check_post
+ integer, parameter :: n = 5
+ type(t), target :: x(n)
+ type :: u
+integer :: a
+ contains
+final :: finalize
+ end type
+ integer :: finalization_count = 0
+
+contains
+
+ function idx(arg)
+type(u) :: arg
+integer :: idx
+idx = mod(arg%a, n)
+ end function
+
+ subroutine check_post
+type(u) :: y
+integer, allocatable :: tmp(:)
+integer, target :: array(4) = [ -1, 0, 1, 2 ]
+integer :: i
+
+y%a = 12
+
+if (allocated(tmp)) error stop 1
+
+tmp = [37]
+
+if (.not. allocated(tmp)) error stop 11
+if (any(shape(tmp) /= [1])) error stop 12
+if (any(tmp /= [37])) error stop 13
+if (finalization_count /= 0) error stop 14
+do i=1,n
+ if (allocated(x(i)%a)) error stop 15
+end do
+
+! Check that the cleanup code for the evaluation of TO is properl
[gcc] Created branch 'mikael/heads/move_alloc_pre_post_v02' in namespace 'refs/users'
The branch 'mikael/heads/move_alloc_pre_post_v02' was created in namespace 'refs/users' pointing to: 5ae9342ba36f... fortran: Add preliminary code of MOVE_ALLOC arguments
[gcc r16-1989] Ada: Remove left-overs of front-end exception mechanism
https://gcc.gnu.org/g:ddab5cf206903f947f969562eb15d799891b0f47 commit r16-1989-gddab5cf206903f947f969562eb15d799891b0f47 Author: Eric Botcazou Date: Thu Jul 3 20:02:43 2025 +0200 Ada: Remove left-overs of front-end exception mechanism It was removed from the compiler a few releases ago. gcc/ada/ * gcc-interface/Makefile.in (gnatlib-sjlj): Delete. (gnatlib-zcx): Do not modify Frontend_Exceptions constant. * libgnat/system-linux-loongarch.ads (Frontend_Exceptions): Delete. Diff: --- gcc/ada/gcc-interface/Makefile.in | 30 -- gcc/ada/libgnat/system-linux-loongarch.ads | 1 - 2 files changed, 31 deletions(-) diff --git a/gcc/ada/gcc-interface/Makefile.in b/gcc/ada/gcc-interface/Makefile.in index 3557b46c64d1..8615b598623f 100644 --- a/gcc/ada/gcc-interface/Makefile.in +++ b/gcc/ada/gcc-interface/Makefile.in @@ -840,35 +840,6 @@ gnatlib-shared: PICFLAG_FOR_TARGET="$(PICFLAG_FOR_TARGET)" \ $(GNATLIB_SHARED) -# When building a SJLJ runtime for VxWorks, we need to ensure that the extra -# linker options needed for ZCX are not passed to prevent the inclusion of -# useless objects and potential troubles from the presence of extra symbols -# and references in some configurations. The inhibition is performed by -# commenting the pragma instead of deleting the line, as the latter might -# result in getting multiple blank lines, hence possible style check errors. -gnatlib-sjlj: - $(MAKE) $(FLAGS_TO_PASS) \ -EH_MECHANISM="" \ -MULTISUBDIR="$(MULTISUBDIR)" \ -THREAD_KIND="$(THREAD_KIND)" \ -LN_S="$(LN_S)" \ -../stamp-gnatlib1-$(RTSDIR) - sed \ - -e 's/Frontend_Exceptions.*/Frontend_Exceptions : constant Boolean := True;/' \ - -e 's/ZCX_By_Default.*/ZCX_By_Default: constant Boolean := False;/' \ - $(RTSDIR)/system.ads > $(RTSDIR)/s.ads - $(MV) $(RTSDIR)/s.ads $(RTSDIR)/system.ads - $(MAKE) $(FLAGS_TO_PASS) \ -EH_MECHANISM="" \ -GNATLIBFLAGS="$(GNATLIBFLAGS)" \ -GNATLIBCFLAGS="$(GNATLIBCFLAGS)" \ -GNATLIBCFLAGS_FOR_C="$(GNATLIBCFLAGS_FOR_C)" \ -FORCE_DEBUG_ADAFLAGS="$(FORCE_DEBUG_ADAFLAGS)" \ -MULTISUBDIR="$(MULTISUBDIR)" \ -THREAD_KIND="$(THREAD_KIND)" \ -LN_S="$(LN_S)" \ -gnatlib - gnatlib-zcx: $(MAKE) $(FLAGS_TO_PASS) \ EH_MECHANISM="-gcc" \ @@ -877,7 +848,6 @@ gnatlib-zcx: LN_S="$(LN_S)" \ ../stamp-gnatlib1-$(RTSDIR) sed \ - -e 's/Frontend_Exceptions.*/Frontend_Exceptions : constant Boolean := False;/' \ -e 's/ZCX_By_Default.*/ZCX_By_Default: constant Boolean := True;/' \ $(RTSDIR)/system.ads > $(RTSDIR)/s.ads $(MV) $(RTSDIR)/s.ads $(RTSDIR)/system.ads diff --git a/gcc/ada/libgnat/system-linux-loongarch.ads b/gcc/ada/libgnat/system-linux-loongarch.ads index 77a213962550..683b7a441558 100644 --- a/gcc/ada/libgnat/system-linux-loongarch.ads +++ b/gcc/ada/libgnat/system-linux-loongarch.ads @@ -139,7 +139,6 @@ private Always_Compatible_Rep : constant Boolean := False; Suppress_Standard_Library : constant Boolean := False; Use_Ada_Main_Program_Name : constant Boolean := False; - Frontend_Exceptions : constant Boolean := False; ZCX_By_Default: constant Boolean := True; end System;
[gcc r16-1988] s390: More vec-perm-const cases.
https://gcc.gnu.org/g:680ee33e1dfc24345f0a881eb96cf4431db335a9
commit r16-1988-g680ee33e1dfc24345f0a881eb96cf4431db335a9
Author: Juergen Christ
Date: Fri Jun 27 12:20:04 2025 +0200
s390: More vec-perm-const cases.
s390 missed constant vector permutation cases based on the vector pack
instruction or changing the size of the vector elements during vector
merge. This enables some more patterns that do not need to load a
constant vector for permutation.
gcc/ChangeLog:
* config/s390/s390.cc (expand_perm_with_merge): Add size change
cases.
(expand_perm_with_pack): New function.
(vectorize_vec_perm_const_1): Wire up new function.
gcc/testsuite/ChangeLog:
* gcc.target/s390/vector/vec-perm-merge-1.c: New test.
* gcc.target/s390/vector/vec-perm-pack-1.c: New test.
Signed-off-by: Juergen Christ
Diff:
---
gcc/config/s390/s390.cc| 169 +-
.../gcc.target/s390/vector/vec-perm-merge-1.c | 242 +
.../gcc.target/s390/vector/vec-perm-pack-1.c | 133 +++
3 files changed, 542 insertions(+), 2 deletions(-)
diff --git a/gcc/config/s390/s390.cc b/gcc/config/s390/s390.cc
index 38267202f668..de9c15c7bd42 100644
--- a/gcc/config/s390/s390.cc
+++ b/gcc/config/s390/s390.cc
@@ -18041,9 +18041,34 @@ expand_perm_with_merge (const struct expand_vec_perm_d
&d)
static const unsigned char lo_perm_qi_swap[16]
= {17, 1, 19, 3, 21, 5, 23, 7, 25, 9, 27, 11, 29, 13, 31, 15};
+ static const unsigned char hi_perm_qi_di[16]
+= {0, 1, 2, 3, 4, 5, 6, 7, 16, 17, 18, 19, 20, 21, 22, 23};
+ static const unsigned char hi_perm_qi_si[16]
+= {0, 1, 2, 3, 16, 17, 18, 19, 4, 5, 6, 7, 20, 21, 22, 23};
+ static const unsigned char hi_perm_qi_hi[16]
+= {0, 1, 16, 17, 2, 3, 18, 19, 4, 5, 20, 21, 6, 7, 22, 23};
+
+ static const unsigned char lo_perm_qi_di[16]
+= {8, 9, 10, 11, 12, 13, 14, 15, 24, 25, 26, 27, 28, 29, 30, 31};
+ static const unsigned char lo_perm_qi_si[16]
+= {8, 9, 10, 11, 24, 25, 26, 27, 12, 13, 14, 15, 28, 29, 30, 31};
+ static const unsigned char lo_perm_qi_hi[16]
+= {8, 9, 24, 25, 10, 11, 26, 27, 12, 13, 28, 29, 14, 15, 30, 31};
+
+ static const unsigned char hi_perm_hi_si[8] = {0, 1, 8, 9, 2, 3, 10, 11};
+ static const unsigned char hi_perm_hi_di[8] = {0, 1, 2, 3, 8, 9, 10, 11};
+
+ static const unsigned char lo_perm_hi_si[8] = {4, 5, 12, 13, 6, 7, 14, 15};
+ static const unsigned char lo_perm_hi_di[8] = {4, 5, 6, 7, 12, 13, 14, 15};
+
+ static const unsigned char hi_perm_si_di[4] = {0, 1, 4, 5};
+
+ static const unsigned char lo_perm_si_di[4] = {2, 3, 6, 7};
+
bool merge_lo_p = false;
bool merge_hi_p = false;
bool swap_operands_p = false;
+ machine_mode mergemode = d.vmode;
if ((d.nelt == 2 && memcmp (d.perm, hi_perm_di, 2) == 0)
|| (d.nelt == 4 && memcmp (d.perm, hi_perm_si, 4) == 0)
@@ -18075,6 +18100,75 @@ expand_perm_with_merge (const struct expand_vec_perm_d
&d)
merge_lo_p = true;
swap_operands_p = true;
}
+ else if (d.nelt == 16)
+{
+ if (memcmp (d.perm, hi_perm_qi_di, 16) == 0)
+ {
+ merge_hi_p = true;
+ mergemode = E_V2DImode;
+ }
+ else if (memcmp (d.perm, hi_perm_qi_si, 16) == 0)
+ {
+ merge_hi_p = true;
+ mergemode = E_V4SImode;
+ }
+ else if (memcmp (d.perm, hi_perm_qi_hi, 16) == 0)
+ {
+ merge_hi_p = true;
+ mergemode = E_V8HImode;
+ }
+ else if (memcmp (d.perm, lo_perm_qi_di, 16) == 0)
+ {
+ merge_lo_p = true;
+ mergemode = E_V2DImode;
+ }
+ else if (memcmp (d.perm, lo_perm_qi_si, 16) == 0)
+ {
+ merge_lo_p = true;
+ mergemode = E_V4SImode;
+ }
+ else if (memcmp (d.perm, lo_perm_qi_hi, 16) == 0)
+ {
+ merge_lo_p = true;
+ mergemode = E_V8HImode;
+ }
+}
+ else if (d.nelt == 8)
+{
+ if (memcmp (d.perm, hi_perm_hi_di, 8) == 0)
+ {
+ merge_hi_p = true;
+ mergemode = E_V2DImode;
+ }
+ else if (memcmp (d.perm, hi_perm_hi_si, 8) == 0)
+ {
+ merge_hi_p = true;
+ mergemode = E_V4SImode;
+ }
+ else if (memcmp (d.perm, lo_perm_hi_di, 8) == 0)
+ {
+ merge_lo_p = true;
+ mergemode = E_V2DImode;
+ }
+ else if (memcmp (d.perm, lo_perm_hi_si, 8) == 0)
+ {
+ merge_lo_p = true;
+ mergemode = E_V4SImode;
+ }
+}
+ else if (d.nelt == 4)
+{
+ if (memcmp (d.perm, hi_perm_si_di, 4) == 0)
+ {
+ merge_hi_p = true;
+ mergemode = E_V2DImode;
+ }
+ else if (memcmp (d.perm, lo_perm_si_di, 4) == 0)
+ {
+ merge_lo_p = true;
+ mergemode = E_V2DImode;
+ }
+}
if (!merge_lo_p && !merge_hi_p)
return false;
@@ -18082,7 +18176,7 @@ expand_perm_with
[gcc(refs/users/mikael/heads/suppr_allocated_in_scope_v03)] Sauvegarde suppression initialisation inutile bornes pour taire warnings
https://gcc.gnu.org/g:1b488ce13c7f722cef3a667b7f46dcb2d4f2e330
commit 1b488ce13c7f722cef3a667b7f46dcb2d4f2e330
Author: Mikael Morin
Date: Fri Mar 14 16:37:46 2025 +0100
Sauvegarde suppression initialisation inutile bornes pour taire warnings
Diff:
---
gcc/fortran/trans-array.cc | 20
gcc/fortran/trans-expr.cc | 39 +--
2 files changed, 41 insertions(+), 18 deletions(-)
diff --git a/gcc/fortran/trans-array.cc b/gcc/fortran/trans-array.cc
index 6f3fb5f04240..f225f013ea53 100644
--- a/gcc/fortran/trans-array.cc
+++ b/gcc/fortran/trans-array.cc
@@ -4767,13 +4767,12 @@ gfc_trans_scalarized_loop_boundary (gfc_loopinfo *
loop, stmtblock_t * body)
static void
evaluate_bound (stmtblock_t *block, tree *bounds, gfc_expr ** values,
- tree desc, int dim, bool lbound, bool deferred)
+ tree desc, int dim, bool lbound, bool deferred, bool save_value)
{
gfc_se se;
gfc_expr * input_val = values[dim];
tree *output = &bounds[dim];
-
if (input_val)
{
/* Specified section bound. */
@@ -4799,7 +4798,8 @@ evaluate_bound (stmtblock_t *block, tree *bounds,
gfc_expr ** values,
*output = lbound ? gfc_conv_array_lbound (desc, dim) :
gfc_conv_array_ubound (desc, dim);
}
- *output = gfc_evaluate_now (*output, block);
+ if (save_value)
+*output = gfc_evaluate_now (*output, block);
}
@@ -4832,18 +4832,18 @@ gfc_conv_section_startstride (stmtblock_t * block,
gfc_ss * ss, int dim)
|| ar->dimen_type[dim] == DIMEN_THIS_IMAGE);
desc = info->descriptor;
stride = ar->stride[dim];
-
+ bool save_value = !ss->is_alloc_lhs;
/* Calculate the start of the range. For vector subscripts this will
be the range of the vector. */
evaluate_bound (block, info->start, ar->start, desc, dim, true,
- ar->as->type == AS_DEFERRED);
+ ar->as->type == AS_DEFERRED, save_value);
/* Similarly calculate the end. Although this is not used in the
scalarizer, it is needed when checking bounds and where the end
is an expression with side-effects. */
evaluate_bound (block, info->end, ar->end, desc, dim, false,
- ar->as->type == AS_DEFERRED);
+ ar->as->type == AS_DEFERRED, save_value);
/* Calculate the stride. */
@@ -4854,7 +4854,11 @@ gfc_conv_section_startstride (stmtblock_t * block,
gfc_ss * ss, int dim)
gfc_init_se (&se, NULL);
gfc_conv_expr_type (&se, stride, gfc_array_index_type);
gfc_add_block_to_block (block, &se.pre);
- info->stride[dim] = gfc_evaluate_now (se.expr, block);
+ tree value = se.expr;
+ if (save_value)
+ info->stride[dim] = gfc_evaluate_now (value, block);
+ else
+ info->stride[dim] = value;
}
}
@@ -8466,7 +8470,7 @@ gfc_conv_expr_descriptor (gfc_se *se, gfc_expr *expr)
gcc_assert (n == codim - 1);
evaluate_bound (&loop.pre, info->start, ar->start,
info->descriptor, n + ndim, true,
- ar->as->type == AS_DEFERRED);
+ ar->as->type == AS_DEFERRED, true);
loop.from[n + loop.dimen] = info->start[n + ndim];
}
else
diff --git a/gcc/fortran/trans-expr.cc b/gcc/fortran/trans-expr.cc
index c8a207609e4b..3104badba0c4 100644
--- a/gcc/fortran/trans-expr.cc
+++ b/gcc/fortran/trans-expr.cc
@@ -13010,6 +13010,35 @@ gfc_trans_assignment_1 (gfc_expr * expr1, gfc_expr *
expr2, bool init_flag,
ompws_flags |= OMPWS_SCALARIZER_WS | OMPWS_SCALARIZER_BODY;
}
+ /* F2003: Allocate or reallocate lhs of allocatable array. */
+ if (realloc_flag)
+ {
+ realloc_lhs_warning (expr1->ts.type, true, &expr1->where);
+ ompws_flags &= ~OMPWS_SCALARIZER_WS;
+ tmp = gfc_alloc_allocatable_for_assignment (&loop, expr1, expr2);
+ if (tmp != NULL_TREE)
+ gfc_add_expr_to_block (&loop.pre, tmp);
+ }
+
+ for (gfc_ss *s = loop.ss; s != gfc_ss_terminator; s = s->loop_chain)
+ {
+ if (!s->is_alloc_lhs)
+ continue;
+
+ gcc_assert (s->info->type == GFC_SS_SECTION);
+ gfc_array_info *info = &s->info->data.array;
+ info->offset = gfc_evaluate_now (info->offset, &loop.pre);
+ info->saved_offset = info->offset;
+ for (int i = 0; i < s->dimen; i++)
+ {
+ int dim = s->dim[i];
+ info->start[dim] = gfc_evaluate_now (info->start[dim], &loop.pre);
+ info->end[dim] = gfc_evaluate_now (info->end[dim], &loop.pre);
+ info->stride[dim] = gfc_evaluate_now (info->stride[dim],
&loop.pre);
+ info->delta[dim] = gfc_evaluate_now (info->delta[dim], &loop.pre);
+ }
+ }
+
/* Start the scalarized loop body. */
gfc_start_scalarized_body (&loop, &body);
}
@@ -13318,16 +13347,6 @@ gfc_trans_as
[gcc(refs/users/mikael/heads/suppr_allocated_in_scope_v03)] Correction régression realloc_on_assign_23.f90
https://gcc.gnu.org/g:00c1aec1efb66a2cc8cff538bd061c6d21106111
commit 00c1aec1efb66a2cc8cff538bd061c6d21106111
Author: Mikael Morin
Date: Mon Feb 17 21:28:01 2025 +0100
Correction régression realloc_on_assign_23.f90
Diff:
---
gcc/fortran/trans-expr.cc | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/gcc/fortran/trans-expr.cc b/gcc/fortran/trans-expr.cc
index 3104badba0c4..8b2705d8d48c 100644
--- a/gcc/fortran/trans-expr.cc
+++ b/gcc/fortran/trans-expr.cc
@@ -12942,6 +12942,7 @@ gfc_trans_assignment_1 (gfc_expr * expr1, gfc_expr *
expr2, bool init_flag,
rhs_caf_attr = gfc_caf_attr (expr2, false, &rhs_refs_comp);
}
+ tree reallocation = NULL_TREE;
if (lss != gfc_ss_terminator)
{
/* The assignment needs scalarization. */
@@ -13015,9 +13016,7 @@ gfc_trans_assignment_1 (gfc_expr * expr1, gfc_expr *
expr2, bool init_flag,
{
realloc_lhs_warning (expr1->ts.type, true, &expr1->where);
ompws_flags &= ~OMPWS_SCALARIZER_WS;
- tmp = gfc_alloc_allocatable_for_assignment (&loop, expr1, expr2);
- if (tmp != NULL_TREE)
- gfc_add_expr_to_block (&loop.pre, tmp);
+ reallocation = gfc_alloc_allocatable_for_assignment (&loop, expr1,
expr2);
}
for (gfc_ss *s = loop.ss; s != gfc_ss_terminator; s = s->loop_chain)
@@ -13350,6 +13349,9 @@ gfc_trans_assignment_1 (gfc_expr * expr1, gfc_expr *
expr2, bool init_flag,
if (maybe_workshare)
ompws_flags &= ~OMPWS_SCALARIZER_BODY;
+ if (reallocation != NULL_TREE)
+ gfc_add_expr_to_block (&loop.code[loop.dimen - 1], reallocation);
+
/* Generate the copying loops. */
gfc_trans_scalarizing_loops (&loop, &body);
[gcc(refs/users/mikael/heads/suppr_allocated_in_scope_v03)] Correction régression allocate_with_source_5.f90
https://gcc.gnu.org/g:172f2922700fa4c4949bcc56acaeca99b4e925b4 commit 172f2922700fa4c4949bcc56acaeca99b4e925b4 Author: Mikael Morin Date: Tue Feb 18 17:25:29 2025 +0100 Correction régression allocate_with_source_5.f90 Diff: --- gcc/fortran/resolve.cc | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/gcc/fortran/resolve.cc b/gcc/fortran/resolve.cc index 36b1391a305b..7ed3be59885d 100644 --- a/gcc/fortran/resolve.cc +++ b/gcc/fortran/resolve.cc @@ -3664,7 +3664,9 @@ resolve_function (gfc_expr *expr) "Using function %qs at %L is deprecated", sym->name, &expr->where); - if (!expr->value.function.isym) + if (!(expr->value.function.isym + || !expr->value.function.esym + || expr->value.function.esym->attr.elemental)) gfc_expression_rank (expr); return t;
[gcc(refs/users/mikael/heads/suppr_allocated_in_scope_v03)] Correction régression realloc_on_assign_1.f03
https://gcc.gnu.org/g:cc2da149aafbccf497ba0921f446bc06c83a54c5
commit cc2da149aafbccf497ba0921f446bc06c83a54c5
Author: Mikael Morin
Date: Mon Feb 17 21:59:00 2025 +0100
Correction régression realloc_on_assign_1.f03
Diff:
---
gcc/fortran/trans-expr.cc | 42 +++---
1 file changed, 23 insertions(+), 19 deletions(-)
diff --git a/gcc/fortran/trans-expr.cc b/gcc/fortran/trans-expr.cc
index 8b2705d8d48c..ca8a45bf3885 100644
--- a/gcc/fortran/trans-expr.cc
+++ b/gcc/fortran/trans-expr.cc
@@ -13016,26 +13016,30 @@ gfc_trans_assignment_1 (gfc_expr * expr1, gfc_expr *
expr2, bool init_flag,
{
realloc_lhs_warning (expr1->ts.type, true, &expr1->where);
ompws_flags &= ~OMPWS_SCALARIZER_WS;
+ stmtblock_t reallocation_block;
+ gfc_init_block (&reallocation_block);
reallocation = gfc_alloc_allocatable_for_assignment (&loop, expr1,
expr2);
- }
-
- for (gfc_ss *s = loop.ss; s != gfc_ss_terminator; s = s->loop_chain)
- {
- if (!s->is_alloc_lhs)
- continue;
+ gfc_add_expr_to_block (&reallocation_block, reallocation);
- gcc_assert (s->info->type == GFC_SS_SECTION);
- gfc_array_info *info = &s->info->data.array;
- info->offset = gfc_evaluate_now (info->offset, &loop.pre);
- info->saved_offset = info->offset;
- for (int i = 0; i < s->dimen; i++)
+ for (gfc_ss *s = loop.ss; s != gfc_ss_terminator; s = s->loop_chain)
{
- int dim = s->dim[i];
- info->start[dim] = gfc_evaluate_now (info->start[dim], &loop.pre);
- info->end[dim] = gfc_evaluate_now (info->end[dim], &loop.pre);
- info->stride[dim] = gfc_evaluate_now (info->stride[dim],
&loop.pre);
- info->delta[dim] = gfc_evaluate_now (info->delta[dim], &loop.pre);
+ if (!s->is_alloc_lhs)
+ continue;
+
+ gcc_assert (s->info->type == GFC_SS_SECTION);
+ gfc_array_info *info = &s->info->data.array;
+ info->offset = gfc_evaluate_now (info->offset,
&reallocation_block);
+ info->saved_offset = info->offset;
+ for (int i = 0; i < s->dimen; i++)
+ {
+ int dim = s->dim[i];
+ info->start[dim] = gfc_evaluate_now (info->start[dim],
&reallocation_block);
+ info->end[dim] = gfc_evaluate_now (info->end[dim],
&reallocation_block);
+ info->stride[dim] = gfc_evaluate_now (info->stride[dim],
&reallocation_block);
+ info->delta[dim] = gfc_evaluate_now (info->delta[dim],
&reallocation_block);
+ }
}
+ reallocation = gfc_finish_block (&reallocation_block);
}
/* Start the scalarized loop body. */
@@ -13346,12 +13350,12 @@ gfc_trans_assignment_1 (gfc_expr * expr1, gfc_expr *
expr2, bool init_flag,
gfc_add_expr_to_block (&body, tmp);
}
- if (maybe_workshare)
- ompws_flags &= ~OMPWS_SCALARIZER_BODY;
-
if (reallocation != NULL_TREE)
gfc_add_expr_to_block (&loop.code[loop.dimen - 1], reallocation);
+ if (maybe_workshare)
+ ompws_flags &= ~OMPWS_SCALARIZER_BODY;
+
/* Generate the copying loops. */
gfc_trans_scalarizing_loops (&loop, &body);
[gcc(refs/users/mikael/heads/suppr_allocated_in_scope_v03)] Correction typebound_operator_9.f90
https://gcc.gnu.org/g:cbbab5c9c7d4cb8d7521b1fe5c0c752447564676
commit cbbab5c9c7d4cb8d7521b1fe5c0c752447564676
Author: Mikael Morin
Date: Tue Feb 18 22:41:55 2025 +0100
Correction typebound_operator_9.f90
Diff:
---
gcc/fortran/trans-expr.cc | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/gcc/fortran/trans-expr.cc b/gcc/fortran/trans-expr.cc
index c43c240811b7..ab21379c3b76 100644
--- a/gcc/fortran/trans-expr.cc
+++ b/gcc/fortran/trans-expr.cc
@@ -12957,8 +12957,12 @@ gfc_trans_assignment_1 (gfc_expr * expr1, gfc_expr *
expr2, bool init_flag,
/* Walk the rhs. */
rss = gfc_walk_expr (expr2);
if (rss == gfc_ss_terminator)
- /* The rhs is scalar. Add a ss for the expression. */
- rss = gfc_get_scalar_ss (gfc_ss_terminator, expr2);
+ {
+ /* The rhs is scalar. Add a ss for the expression. */
+ rss = gfc_get_scalar_ss (gfc_ss_terminator, expr2);
+ lss->is_alloc_lhs = 0;
+ }
+
/* When doing a class assign, then the handle to the rhs needs to be a
pointer to allow for polymorphism. */
if (is_poly_assign && expr2->rank == 0 && !UNLIMITED_POLY (expr2))
[gcc r14-11871] aarch64: Incorrect removal of ZA restore [PR120624]
https://gcc.gnu.org/g:72b828227f8faf8f0a85735a5c27545378cf20c5 commit r14-11871-g72b828227f8faf8f0a85735a5c27545378cf20c5 Author: Richard Sandiford Date: Thu Jul 3 08:12:42 2025 +0100 aarch64: Incorrect removal of ZA restore [PR120624] The PCS defines a lazy save scheme for managing ZA across normal "private-ZA" functions. GCC currently uses this scheme for calls to all private-ZA functions (rather than using caller-save). Therefore, before a sequence of calls to private-ZA functions, GCC emits code to set up a lazy save. After the sequence of calls, GCC emits code to check whether lazy save was committed and restore the ZA contents if so. These sequences are emitted by the mode-switching pass, in an attempt to reduce the number of redundant saves and restores. The lazy save scheme also means that, before a function can use ZA, it must first conditionally store the old contents of ZA to the caller's lazy save buffer, if any. This all creates some relatively complex dependencies between setup code, save/restore code, and normal reads from and writes to ZA. These dependencies are modelled using special fake hard registers: ;; Sometimes we use placeholder instructions to mark where later ;; ABI-related lowering is needed. These placeholders read and ;; write this register. Instructions that depend on the lowering ;; read the register. (LOWERING_REGNUM 87) ;; Represents the contents of the current function's TPIDR2 block, ;; in abstract form. (TPIDR2_BLOCK_REGNUM 88) ;; Holds the value that the current function wants PSTATE.ZA to be. ;; The actual value can sometimes vary, because it does not track ;; changes to PSTATE.ZA that happen during a lazy save and restore. ;; Those effects are instead tracked by ZA_SAVED_REGNUM. (SME_STATE_REGNUM 89) ;; Instructions write to this register if they set TPIDR2_EL0 to a ;; well-defined value. Instructions read from the register if they ;; depend on the result of such writes. ;; ;; The register does not model the architected TPIDR2_ELO, just the ;; current function's management of it. (TPIDR2_SETUP_REGNUM 90) ;; Represents the property "has an incoming lazy save been committed?". (ZA_FREE_REGNUM 91) ;; Represents the property "are the current function's ZA contents ;; stored in the lazy save buffer, rather than in ZA itself?". (ZA_SAVED_REGNUM 92) ;; Represents the contents of the current function's ZA state in ;; abstract form. At various times in the function, these contents ;; might be stored in ZA itself, or in the function's lazy save buffer. ;; ;; The contents persist even when the architected ZA is off. Private-ZA ;; functions have no effect on its contents. (ZA_REGNUM 93) Every normal read from ZA and write to ZA depends on SME_STATE_REGNUM, in order to sequence the code with the initial setup of ZA and with the lazy save scheme. The code to restore ZA after a call involves several instructions, including conditional control flow. It is initially represented as a single define_insn and is split late, after shrink-wrapping and prologue/epilogue insertion. The split form of the restore instruction includes a conditional call to __arm_tpidr2_restore: (define_insn "aarch64_tpidr2_restore" [(set (reg:DI ZA_SAVED_REGNUM) (unspec:DI [(reg:DI R0_REGNUM)] UNSPEC_TPIDR2_RESTORE)) (set (reg:DI SME_STATE_REGNUM) (unspec:DI [(reg:DI SME_STATE_REGNUM)] UNSPEC_TPIDR2_RESTORE)) ... ) The write to SME_STATE_REGNUM indicates the end of the region where ZA_REGNUM might differ from the real contents of ZA. In other words, it is the point at which normal reads from ZA and writes to ZA can safely take place. To finally get to the point, the problem in this PR was that the unsplit aarch64_restore_za pattern was missing this change to SME_STATE_REGNUM. It could therefore be deleted as dead before it had chance to be split. The split form had the correct dataflow, but the unsplit form didn't. Unfortunately, the tests for this code tended to use calls and asms to model regions of ZA usage, and those don't seem to be affected in the same way. gcc/ PR target/120624 * config/aarch64/aarch64.md (SME_STATE_REGNUM): Expand on comments. * config/aarch64/aarch64-sme.md (aarch64_restore_za): Also set SME_STATE_REGNUM gcc/testsuite/ PR target/120624 * gcc.target/aarch64/sme/za_state_7.c: New test. (cherry picked from commit 8546265e2ee386ea8a4b2f91
[gcc r16-1919] ada: Use consistent truncation of 'Value for decimal fixed-point types
https://gcc.gnu.org/g:0ef4195c17fe7b0b755686b13f65b57eff12dfe4 commit r16-1919-g0ef4195c17fe7b0b755686b13f65b57eff12dfe4 Author: Eric Botcazou Date: Mon May 26 23:56:47 2025 +0200 ada: Use consistent truncation of 'Value for decimal fixed-point types This uses truncation for all bases instead of for base 10 only. gcc/ada/ChangeLog: * libgnat/s-valued.adb (Integer_to_Decimal): Use truncation for the scaled divide operation performed for bases other than 10. Diff: --- gcc/ada/libgnat/s-valued.adb | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/gcc/ada/libgnat/s-valued.adb b/gcc/ada/libgnat/s-valued.adb index 4f2e10204668..b7982b6046f7 100644 --- a/gcc/ada/libgnat/s-valued.adb +++ b/gcc/ada/libgnat/s-valued.adb @@ -228,9 +228,9 @@ package body System.Value_D is raise Program_Error; end if; --- Perform a scaled divide operation with rounding to match 'Image +-- Perform a scaled divide operation with truncation -Scaled_Divide (To_Signed (V), Y, Z, Q, R, Round => True); +Scaled_Divide (To_Signed (V), Y, Z, Q, R, Round => False); return Q; end;
[gcc r16-1926] ada: Call Semantics when analyzing a renamed package
https://gcc.gnu.org/g:fe1e262fa75b1264663021628a47d216c353abe8 commit r16-1926-gfe1e262fa75b1264663021628a47d216c353abe8 Author: Viljar Indus Date: Thu May 29 10:54:30 2025 +0300 ada: Call Semantics when analyzing a renamed package Calling Semantics here will additionally update the reference to Current_Sem_Unit the renamed unit so that we will not receive bogus visibility errors when checking for self-referential with-s. gcc/ada/ChangeLog: * sem_ch10.adb(Analyze_With_Clause): Call Semantics instead of Analyze to bring Current_Sem_Unit up to date. Diff: --- gcc/ada/sem_ch10.adb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gcc/ada/sem_ch10.adb b/gcc/ada/sem_ch10.adb index 3a44149aeffc..f58513d115fb 100644 --- a/gcc/ada/sem_ch10.adb +++ b/gcc/ada/sem_ch10.adb @@ -3299,7 +3299,7 @@ package body Sem_Ch10 is -- the renamed unit, and the renaming declaration itself has not -- been analyzed. -Analyze (Parent (Parent (Entity (Pref; +Semantics (Parent (Parent (Entity (Pref; pragma Assert (Renamed_Entity (Entity (Pref)) = Par_Name); Par_Name := Entity (Pref); end if;
[gcc r16-1927] ada: Remove Empty_Or_Error
https://gcc.gnu.org/g:d02dfbfa3f1d21acf599e0308e365b296d6bae61 commit r16-1927-gd02dfbfa3f1d21acf599e0308e365b296d6bae61 Author: Bob Duff Date: Fri May 30 08:07:43 2025 -0400 ada: Remove Empty_Or_Error Minor stylistic improvement: Remove Empty_Or_Error, and replace comparisons with Empty_Or_Error with "[not] in Empty | Error". (Found while working on VAST.) gcc/ada/ChangeLog: * types.ads (Empty_Or_Error): Remove. * atree.adb: Remove reference to Empty_Or_Error. * par-endh.adb: Likewise. * sem_ch12.adb: Likewise. * sem_ch3.adb: Likewise. * sem_util.adb: Likewise. * treepr.adb: Likewise. Diff: --- gcc/ada/atree.adb| 7 +++ gcc/ada/par-endh.adb | 4 ++-- gcc/ada/sem_ch12.adb | 2 +- gcc/ada/sem_ch3.adb | 5 ++--- gcc/ada/sem_util.adb | 4 ++-- gcc/ada/treepr.adb | 13 ++--- gcc/ada/types.ads| 5 - 7 files changed, 16 insertions(+), 24 deletions(-) diff --git a/gcc/ada/atree.adb b/gcc/ada/atree.adb index 17538de8954d..20ca189ad8c3 100644 --- a/gcc/ada/atree.adb +++ b/gcc/ada/atree.adb @@ -1296,8 +1296,7 @@ package body Atree is Node_Offsets.Table (Node_Offsets.First .. Node_Offsets.Last); begin - -- Empty_Or_Error use as described in types.ads - if Destination <= Empty_Or_Error or No (Source) then + if Destination in Empty | Error or else No (Source) then pragma Assert (Serious_Errors_Detected > 0); return; end if; @@ -1458,7 +1457,7 @@ package body Atree is -- Start of processing for Copy_Separate_Tree begin - if Source <= Empty_Or_Error then + if Source in Empty | Error then return Source; elsif Is_Entity (Source) then @@ -1841,7 +1840,7 @@ package body Atree is pragma Debug (Validate_Node (Source)); S_Size : constant Slot_Count := Size_In_Slots_To_Alloc (Source); begin - if Source <= Empty_Or_Error then + if Source in Empty | Error then return Source; end if; diff --git a/gcc/ada/par-endh.adb b/gcc/ada/par-endh.adb index 12baed455d7f..b045d74bd0ee 100644 --- a/gcc/ada/par-endh.adb +++ b/gcc/ada/par-endh.adb @@ -300,7 +300,7 @@ package body Endh is else End_Labl := Scopes (Scope.Last).Labl; - if End_Labl > Empty_Or_Error then + if End_Labl not in Empty | Error then -- The task here is to construct a designator from the -- opening label, with the components all marked as not @@ -921,7 +921,7 @@ package body Endh is -- Suppress message if error was posted on opening label - if Error_Msg_Node_1 > Empty_Or_Error + if Error_Msg_Node_1 not in Empty | Error and then Error_Posted (Error_Msg_Node_1) then return; diff --git a/gcc/ada/sem_ch12.adb b/gcc/ada/sem_ch12.adb index f492b2368575..7ebf145d783e 100644 --- a/gcc/ada/sem_ch12.adb +++ b/gcc/ada/sem_ch12.adb @@ -3171,7 +3171,7 @@ package body Sem_Ch12 is end if; end if; - if Subtype_Mark (Def) <= Empty_Or_Error then + if Subtype_Mark (Def) in Empty | Error then pragma Assert (Serious_Errors_Detected > 0); -- avoid passing bad argument to Entity return; diff --git a/gcc/ada/sem_ch3.adb b/gcc/ada/sem_ch3.adb index 45b28bf96a4b..b4342af134e6 100644 --- a/gcc/ada/sem_ch3.adb +++ b/gcc/ada/sem_ch3.adb @@ -19159,8 +19159,7 @@ package body Sem_Ch3 is -- Otherwise we have a subtype mark without a constraint elsif Error_Posted (S) then - -- Don't rewrite if S is Empty or Error - if S > Empty_Or_Error then + if S not in Empty | Error then Rewrite (S, New_Occurrence_Of (Any_Id, Sloc (S))); end if; return Any_Type; @@ -21094,7 +21093,7 @@ package body Sem_Ch3 is -- If no range was given, set a dummy range - if RRS <= Empty_Or_Error then + if RRS in Empty | Error then Low_Val := -Small_Val; High_Val := Small_Val; diff --git a/gcc/ada/sem_util.adb b/gcc/ada/sem_util.adb index b61f3bbad5e1..ed8f054fc634 100644 --- a/gcc/ada/sem_util.adb +++ b/gcc/ada/sem_util.adb @@ -24112,7 +24112,7 @@ package body Sem_Util is Result := N; - if N > Empty_Or_Error then + if N not in Empty | Error then pragma Assert (Nkind (N) not in N_Entity); Result := New_Copy (N); @@ -24193,7 +24193,7 @@ package body Sem_Util is Result := Id; - if Id > Empty_Or_Error then + if Id not in Empty | Error then pragma Assert (Nkind (Id) in N_Entity); -- Determine whether the entity has a corresponding new entity diff --git a/gcc/ada/treepr.adb b/gcc/ada/treepr.adb index d58f3ceb36fb..375608d2ba66 100644 --- a/gcc/ada/treepr.adb +++ b/gcc/ada/treepr.adb @@ -2015,17 +2015,16 @@ pac
[gcc r16-1928] ada: Correct documentation of policy_identifiers for Assertion_Policy
https://gcc.gnu.org/g:80a68f555b2ff160be829fdf4f5c16926b01f2a7
commit r16-1928-g80a68f555b2ff160be829fdf4f5c16926b01f2a7
Author: Bob Duff
Date: Fri May 30 09:38:04 2025 -0400
ada: Correct documentation of policy_identifiers for Assertion_Policy
Follow-on to gnat-945.
Change Ignore to Disable; Ignore is defined by the language,
Disable is the implementation-defined one.
Also minor code cleanup.
gcc/ada/ChangeLog:
* doc/gnat_rm/implementation_defined_characteristics.rst:
Change Ignore to Disable.
* sem_ch13.ads (Analyze_Aspect_Specifications):
Minor: Remove incorrect comment; there is no need to check
Has_Aspects (N) at the call site.
* gnat_rm.texi: Regenerate.
* gnat_ugn.texi: Regenerate.
Diff:
---
gcc/ada/doc/gnat_rm/implementation_defined_characteristics.rst | 2 +-
gcc/ada/gnat_rm.texi | 2 +-
gcc/ada/gnat_ugn.texi | 2 +-
gcc/ada/sem_ch13.ads | 3 +--
4 files changed, 4 insertions(+), 5 deletions(-)
diff --git a/gcc/ada/doc/gnat_rm/implementation_defined_characteristics.rst
b/gcc/ada/doc/gnat_rm/implementation_defined_characteristics.rst
index 563f62a04f95..f7746c8e72fe 100644
--- a/gcc/ada/doc/gnat_rm/implementation_defined_characteristics.rst
+++ b/gcc/ada/doc/gnat_rm/implementation_defined_characteristics.rst
@@ -463,7 +463,7 @@ Implementation-defined assertion_aspect_marks include
Assert_And_Cut,
Assume, Contract_Cases, Debug, Ghost, Initial_Condition, Loop_Invariant,
Loop_Variant, Postcondition, Precondition, Predicate, Refined_Post,
Statement_Assertions, and Subprogram_Variant. Implementation-defined
-policy_identifiers include Ignore and Suppressible.
+policy_identifiers include Disable and Suppressible.
*
"The default assertion policy. See 11.4.2(10)."
diff --git a/gcc/ada/gnat_rm.texi b/gcc/ada/gnat_rm.texi
index 6e95e34359a2..79fb225a555f 100644
--- a/gcc/ada/gnat_rm.texi
+++ b/gcc/ada/gnat_rm.texi
@@ -16894,7 +16894,7 @@ Implementation-defined assertion_aspect_marks include
Assert_And_Cut,
Assume, Contract_Cases, Debug, Ghost, Initial_Condition, Loop_Invariant,
Loop_Variant, Postcondition, Precondition, Predicate, Refined_Post,
Statement_Assertions, and Subprogram_Variant. Implementation-defined
-policy_identifiers include Ignore and Suppressible.
+policy_identifiers include Disable and Suppressible.
@itemize *
diff --git a/gcc/ada/gnat_ugn.texi b/gcc/ada/gnat_ugn.texi
index 6cd0bed8d673..7b3175e3d279 100644
--- a/gcc/ada/gnat_ugn.texi
+++ b/gcc/ada/gnat_ugn.texi
@@ -30297,8 +30297,8 @@ to permit their use in free software.
@printindex ge
-@anchor{gnat_ugn/gnat_utility_programs switches-related-to-project-files}@w{
}
@anchor{d2}@w{ }
+@anchor{gnat_ugn/gnat_utility_programs switches-related-to-project-files}@w{
}
@c %**end of body
@bye
diff --git a/gcc/ada/sem_ch13.ads b/gcc/ada/sem_ch13.ads
index 9bf1ce310c5a..f2c5f7062007 100644
--- a/gcc/ada/sem_ch13.ads
+++ b/gcc/ada/sem_ch13.ads
@@ -43,8 +43,7 @@ package Sem_Ch13 is
procedure Analyze_Aspect_Specifications (N : Node_Id; E : Entity_Id);
-- This procedure is called to analyze aspect specifications for node N. E
- -- is the corresponding entity declared by the declaration node N. Callers
- -- should check that Has_Aspects (N) is True before calling this routine.
+ -- is the corresponding entity declared by the declaration node N.
procedure Analyze_Aspects_On_Subprogram_Body_Or_Stub (N : Node_Id);
-- Analyze the aspect specifications of [generic] subprogram body or stub
[gcc r16-1923] ada: Fix index bounds check in Super_Delete functions and procedures
https://gcc.gnu.org/g:38d77476147b4caea75c8935f8274f7d6517a1df commit r16-1923-g38d77476147b4caea75c8935f8274f7d6517a1df Author: Aleksandra Pasek Date: Mon Mar 3 20:09:25 2025 + ada: Fix index bounds check in Super_Delete functions and procedures gcc/ada/ChangeLog: * libgnat/a-strsup.adb (Super_Delete): Fix index check. * libgnat/a-stwisu.adb (Super_Delete): Likewise. * libgnat/a-stzsup.adb (Super_Delete): Likewise. Diff: --- gcc/ada/libgnat/a-strsup.adb | 4 ++-- gcc/ada/libgnat/a-stwisu.adb | 4 ++-- gcc/ada/libgnat/a-stzsup.adb | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/gcc/ada/libgnat/a-strsup.adb b/gcc/ada/libgnat/a-strsup.adb index 8afde7185816..3ac1a5ac7249 100644 --- a/gcc/ada/libgnat/a-strsup.adb +++ b/gcc/ada/libgnat/a-strsup.adb @@ -755,7 +755,7 @@ package body Ada.Strings.Superbounded with SPARK_Mode is if Num_Delete <= 0 then return Source; - elsif From - 1 > Slen then + elsif From > Slen then raise Ada.Strings.Index_Error; elsif Through >= Slen then @@ -784,7 +784,7 @@ package body Ada.Strings.Superbounded with SPARK_Mode is if Num_Delete <= 0 then return; - elsif From - 1 > Slen then + elsif From > Slen then raise Ada.Strings.Index_Error; elsif Through >= Slen then diff --git a/gcc/ada/libgnat/a-stwisu.adb b/gcc/ada/libgnat/a-stwisu.adb index e7e6b1f75c19..28ae887cc5a9 100644 --- a/gcc/ada/libgnat/a-stwisu.adb +++ b/gcc/ada/libgnat/a-stwisu.adb @@ -753,7 +753,7 @@ package body Ada.Strings.Wide_Superbounded is if Num_Delete <= 0 then return Source; - elsif From > Slen + 1 then + elsif From > Slen then raise Ada.Strings.Index_Error; elsif Through >= Slen then @@ -782,7 +782,7 @@ package body Ada.Strings.Wide_Superbounded is if Num_Delete <= 0 then return; - elsif From > Slen + 1 then + elsif From > Slen then raise Ada.Strings.Index_Error; elsif Through >= Slen then diff --git a/gcc/ada/libgnat/a-stzsup.adb b/gcc/ada/libgnat/a-stzsup.adb index fb1baf6c62cf..5dcbadf3c030 100644 --- a/gcc/ada/libgnat/a-stzsup.adb +++ b/gcc/ada/libgnat/a-stzsup.adb @@ -754,7 +754,7 @@ package body Ada.Strings.Wide_Wide_Superbounded is if Num_Delete <= 0 then return Source; - elsif From > Slen + 1 then + elsif From > Slen then raise Ada.Strings.Index_Error; elsif Through >= Slen then @@ -783,7 +783,7 @@ package body Ada.Strings.Wide_Wide_Superbounded is if Num_Delete <= 0 then return; - elsif From > Slen + 1 then + elsif From > Slen then raise Ada.Strings.Index_Error; elsif Through >= Slen then
[gcc r16-1924] ada: Document restriction on array length
https://gcc.gnu.org/g:613e8bafecd2b54407a23d5636799a2c896f5360 commit r16-1924-g613e8bafecd2b54407a23d5636799a2c896f5360 Author: Tonu Naks Date: Wed May 28 09:50:19 2025 + ada: Document restriction on array length gcc/ada/ChangeLog: * libgnat/i-cstrin.ads (Value): add documentation Diff: --- gcc/ada/libgnat/i-cstrin.ads | 11 +++ 1 file changed, 11 insertions(+) diff --git a/gcc/ada/libgnat/i-cstrin.ads b/gcc/ada/libgnat/i-cstrin.ads index 0d057d074e5d..5939fe041a47 100644 --- a/gcc/ada/libgnat/i-cstrin.ads +++ b/gcc/ada/libgnat/i-cstrin.ads @@ -100,6 +100,17 @@ is -- The Value functions copy the contents of a chars_ptr object -- into a char_array/String. + -- There is a guard for a storage error on an object declaration for + -- an array type with a modular index type with the size of + -- Long_Long_Integer. The special processing is needed in this case + -- to compute reliably the size of the object, and eventually, to + -- raise Storage_Error, when wrap-around arithmetic might compute + -- a meangingless size for the object. + -- + -- The guard raises Storage_Error when + -- + --(Arr'Last / 2 - Arr'First / 2) > (2 ** 30) + -- function Value (Item : chars_ptr) return char_array with Pre=> Item /= Null_Ptr, Global => (Input => C_Memory);
[gcc r16-1922] ada: Fix wrong conversion of controlled array with representation change
https://gcc.gnu.org/g:6f5035b0d710e540b283e9526298a8e33b5e5f4b commit r16-1922-g6f5035b0d710e540b283e9526298a8e33b5e5f4b Author: Eric Botcazou Date: Tue May 27 13:32:18 2025 +0200 ada: Fix wrong conversion of controlled array with representation change The problem is that a temporary is created for the conversion because of the representation change, and it is finalized without having been initialized. gcc/ada/ChangeLog: * exp_ch4.adb (Handle_Changed_Representation): Alphabetize local variables. Set the No_Finalize_Actions flag on the assignment. Diff: --- gcc/ada/exp_ch4.adb | 28 +--- 1 file changed, 17 insertions(+), 11 deletions(-) diff --git a/gcc/ada/exp_ch4.adb b/gcc/ada/exp_ch4.adb index b4270021fafd..a845982d6908 100644 --- a/gcc/ada/exp_ch4.adb +++ b/gcc/ada/exp_ch4.adb @@ -11285,11 +11285,12 @@ package body Exp_Ch4 is --- procedure Handle_Changed_Representation is - Temp : Entity_Id; + Cons : List_Id; Decl : Node_Id; - Odef : Node_Id; N_Ix : Node_Id; - Cons : List_Id; + Odef : Node_Id; + Stmt : Node_Id; + Temp : Entity_Id; begin -- Nothing else to do if no change of representation @@ -11432,19 +11433,24 @@ package body Exp_Ch4 is Defining_Identifier => Temp, Object_Definition => Odef); -Set_No_Initialization (Decl, True); +-- The temporary need not be initialized + +Set_No_Initialization (Decl); + +Stmt := + Make_Assignment_Statement (Loc, +Name => New_Occurrence_Of (Temp, Loc), +Expression => Relocate_Node (N)); + +-- And, therefore, cannot be finalized + +Set_No_Finalize_Actions (Stmt); -- Insert required actions. It is essential to suppress checks -- since we have suppressed default initialization, which means -- that the variable we create may have no discriminants. -Insert_Actions (N, - New_List ( -Decl, -Make_Assignment_Statement (Loc, - Name => New_Occurrence_Of (Temp, Loc), - Expression => Relocate_Node (N))), -Suppress => All_Checks); +Insert_Actions (N, New_List (Decl, Stmt), Suppress => All_Checks); Rewrite (N, New_Occurrence_Of (Temp, Loc)); return;
[gcc r16-1929] ada: Remove unnecessary "return;" statements
https://gcc.gnu.org/g:198afd76a1cf0ba88f9ba913347ba7ebb622
commit r16-1929-g198afd76a1cf0ba88f9ba913347ba7ebb622
Author: Bob Duff
Date: Fri May 30 14:53:41 2025 -0400
ada: Remove unnecessary "return;" statements
A "return;" at the end of a procedure is unnecessary and
misleading. This patch removes them.
gcc/ada/ChangeLog:
* checks.adb: Remove unnecessary "return;" statements.
* eval_fat.adb: Likewise.
* exp_aggr.adb: Likewise.
* exp_attr.adb: Likewise.
* exp_ch3.adb: Likewise.
* exp_ch4.adb: Likewise.
* exp_ch5.adb: Likewise.
* exp_ch6.adb: Likewise.
* exp_unst.adb: Likewise.
* krunch.adb: Likewise.
* layout.adb: Likewise.
* libgnat/s-excdeb.adb: Likewise.
* libgnat/s-trasym__dwarf.adb: Likewise.
* par-endh.adb: Likewise.
* par-tchk.adb: Likewise.
* sem.adb: Likewise.
* sem_attr.adb: Likewise.
* sem_ch6.adb: Likewise.
* sem_elim.adb: Likewise.
* sem_eval.adb: Likewise.
* sfn_scan.adb: Likewise.
Diff:
---
gcc/ada/checks.adb | 10 ++
gcc/ada/eval_fat.adb| 2 --
gcc/ada/exp_aggr.adb| 4 ++--
gcc/ada/exp_attr.adb| 2 +-
gcc/ada/exp_ch3.adb | 6 +++---
gcc/ada/exp_ch4.adb | 12 ++--
gcc/ada/exp_ch5.adb | 4 ++--
gcc/ada/exp_ch6.adb | 2 +-
gcc/ada/exp_unst.adb| 2 --
gcc/ada/krunch.adb | 2 --
gcc/ada/layout.adb | 4 +---
gcc/ada/libgnat/s-excdeb.adb| 2 +-
gcc/ada/libgnat/s-trasym__dwarf.adb | 2 +-
gcc/ada/par-endh.adb| 2 --
gcc/ada/par-tchk.adb| 1 -
gcc/ada/sem.adb | 3 ---
gcc/ada/sem_attr.adb| 1 -
gcc/ada/sem_ch6.adb | 1 -
gcc/ada/sem_elim.adb| 2 --
gcc/ada/sem_eval.adb| 1 -
gcc/ada/sfn_scan.adb| 2 --
21 files changed, 20 insertions(+), 47 deletions(-)
diff --git a/gcc/ada/checks.adb b/gcc/ada/checks.adb
index 6a98292d1cc1..0b3ae02259e3 100644
--- a/gcc/ada/checks.adb
+++ b/gcc/ada/checks.adb
@@ -750,7 +750,7 @@ package body Checks is
-- mode then just skip the check (it is not required in any case).
when RE_Not_Available =>
- return;
+ null;
end Apply_Address_Clause_Check;
-
@@ -1078,7 +1078,7 @@ package body Checks is
exception
when RE_Not_Available =>
-return;
+null;
end;
end Apply_Arithmetic_Overflow_Strict;
@@ -6437,8 +6437,6 @@ package body Checks is
if Debug_Flag_CC then
w (" exception occurred, overflow flag set");
end if;
-
- return;
end Enable_Overflow_Check;
@@ -6686,8 +6684,6 @@ package body Checks is
if Debug_Flag_CC then
w (" exception occurred, range flag set");
end if;
-
- return;
end Enable_Range_Check;
--
@@ -7091,8 +7087,6 @@ package body Checks is
end loop;
-- If we fall through entry was not found
-
- return;
end Find_Check;
-
diff --git a/gcc/ada/eval_fat.adb b/gcc/ada/eval_fat.adb
index 09a5b3fa1b7a..5a2e43ef5978 100644
--- a/gcc/ada/eval_fat.adb
+++ b/gcc/ada/eval_fat.adb
@@ -146,8 +146,6 @@ package body Eval_Fat is
if UR_Is_Negative (X) then
Fraction := -Fraction;
end if;
-
- return;
end Decompose;
---
diff --git a/gcc/ada/exp_aggr.adb b/gcc/ada/exp_aggr.adb
index e3734a2d8c9c..fcf57bf9c31c 100644
--- a/gcc/ada/exp_aggr.adb
+++ b/gcc/ada/exp_aggr.adb
@@ -6633,7 +6633,7 @@ package body Exp_Aggr is
exception
when RE_Not_Available =>
- return;
+ null;
end Expand_N_Aggregate;
---
@@ -7957,7 +7957,7 @@ package body Exp_Aggr is
exception
when RE_Not_Available =>
- return;
+ null;
end Expand_N_Extension_Aggregate;
-
diff --git a/gcc/ada/exp_attr.adb b/gcc/ada/exp_attr.adb
index 0f09ba587acc..4f9f16cfa55b 100644
--- a/gcc/ada/exp_attr.adb
+++ b/gcc/ada/exp_attr.adb
@@ -8776,7 +8776,7 @@ package body Exp_Attr is
exception
when RE_Not_Available =>
- return;
+ null;
end Expand_N_Attribute_Reference;
diff --git a/gcc/ada/exp_ch3.adb b/gcc/ada/exp_ch3.adb
index 7c18f81cb07e..2372a9f11df1 100644
--- a/gcc/ada/exp_ch3.adb
+++ b/gcc/ada/exp_ch3.adb
@@ -5956,7 +5956,7 @@ package body Exp_Ch3 is
exception
when RE_Not_Available =>
- retur
[gcc r16-1920] ada: Fix ALI elaboration flags for ghost compilation units (cont.)
https://gcc.gnu.org/g:35827ca717e3a3552fc513453fd37d1aeb339382 commit r16-1920-g35827ca717e3a3552fc513453fd37d1aeb339382 Author: Piotr Trojanek Date: Tue May 27 12:17:06 2025 +0200 ada: Fix ALI elaboration flags for ghost compilation units (cont.) When GNAT was compiling a ghost unit, the ALI file wrongly suggested that this unit required elaboration counters, which caused linking errors to non-existing objects. gcc/ada/ChangeLog: * sem_ch10.adb (Analyze_Compilation_Unit): Ignored ghost unit need no elaboration checks. Diff: --- gcc/ada/sem_ch10.adb | 4 1 file changed, 4 insertions(+) diff --git a/gcc/ada/sem_ch10.adb b/gcc/ada/sem_ch10.adb index 45aabadf21f8..3a44149aeffc 100644 --- a/gcc/ada/sem_ch10.adb +++ b/gcc/ada/sem_ch10.adb @@ -1491,6 +1491,10 @@ package body Sem_Ch10 is -- No checks required if no separate spec or else Acts_As_Spec (N) + +-- No checked needed for ignored ghost units + +or else Is_Ignored_Ghost_Entity (Spec_Id) ) then -- This is a case where we only need the entity for checking to
[gcc r16-1930] ada: Fix assertion failure on finalizable aggregate
https://gcc.gnu.org/g:ef439d213b712b664c3f25fea34c876fa3cb5848 commit r16-1930-gef439d213b712b664c3f25fea34c876fa3cb5848 Author: Ronan Desplanques Date: Mon Jun 2 12:09:59 2025 +0200 ada: Fix assertion failure on finalizable aggregate The Finalizable aspect makes it possible that Insert_Actions_In_Scope_Around is entered with an empty list of after actions. This patch fixes a condition that was not quite right in this case. gcc/ada/ChangeLog: * exp_ch7.adb (Insert_Actions_In_Scope_Around): Fix condition. Diff: --- gcc/ada/exp_ch7.adb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gcc/ada/exp_ch7.adb b/gcc/ada/exp_ch7.adb index 4d2b8348048e..381294b05d61 100644 --- a/gcc/ada/exp_ch7.adb +++ b/gcc/ada/exp_ch7.adb @@ -5460,7 +5460,7 @@ package body Exp_Ch7 is -- Finalization calls are inserted after the target - if Present (Act_After) then + if Is_Non_Empty_List (Act_After) then Last_Obj := Last (Act_After); Insert_List_After (Target, Act_After); else
[gcc r16-1925] ada: Fix SPARK context discovery from within subunits
https://gcc.gnu.org/g:0fb0140c2ec957b10f550a70a616e3205927b1b5 commit r16-1925-g0fb0140c2ec957b10f550a70a616e3205927b1b5 Author: Piotr Trojanek Date: Wed May 28 15:42:10 2025 +0200 ada: Fix SPARK context discovery from within subunits When navigating the AST to find the enclosing subprogram we must traverse from subunits to the corresponding stub. gcc/ada/ChangeLog: * lib-xref-spark_specific.adb (Enclosing_Subprogram_Or_Library_Package): Traverse subunits and body stubs. Diff: --- gcc/ada/lib-xref-spark_specific.adb | 7 +++ 1 file changed, 7 insertions(+) diff --git a/gcc/ada/lib-xref-spark_specific.adb b/gcc/ada/lib-xref-spark_specific.adb index d77d6aa4dd02..03693a96bae7 100644 --- a/gcc/ada/lib-xref-spark_specific.adb +++ b/gcc/ada/lib-xref-spark_specific.adb @@ -258,6 +258,13 @@ package body SPARK_Specific is Context := Defining_Entity (Context); exit; +when N_Subunit => + Context := Corresponding_Stub (Context); + +when N_Body_Stub => + Context := Corresponding_Spec_Of_Stub (Context); + exit; + when others => Context := Parent (Context); end case;
[gcc r16-1936] ada: Fix typo in comment
https://gcc.gnu.org/g:bf9080aec7731a5749442c1c2f1eb04c47ee2356 commit r16-1936-gbf9080aec7731a5749442c1c2f1eb04c47ee2356 Author: Ronan Desplanques Date: Thu Jun 5 10:51:20 2025 +0200 ada: Fix typo in comment gcc/ada/ChangeLog: * exp_ch7.adb (Build_Record_Deep_Procs): Fix typo in comment. Diff: --- gcc/ada/exp_ch7.adb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gcc/ada/exp_ch7.adb b/gcc/ada/exp_ch7.adb index 381294b05d61..95a790e5cee8 100644 --- a/gcc/ada/exp_ch7.adb +++ b/gcc/ada/exp_ch7.adb @@ -436,7 +436,7 @@ package body Exp_Ch7 is procedure Build_Record_Deep_Procs (Typ : Entity_Id); -- Build the deep Initialize/Adjust/Finalize for a record Typ with - -- Has_Component_Component set and store them using the TSS mechanism. + -- Has_Controlled_Component set and store them using the TSS mechanism. -- Transient Scope Management --
