[gcc(refs/users/meissner/heads/work210)] Change TARGET_MODULO to TARGET_POWER9.
https://gcc.gnu.org/g:b6890b71d1e7f294011c740c59bb960cf3fdc2dd commit b6890b71d1e7f294011c740c59bb960cf3fdc2dd Author: Michael Meissner Date: Thu May 29 18:25:23 2025 -0400 Change TARGET_MODULO to TARGET_POWER9. This patch changes TARGET_MODULO to TARGET_POWER9. The -mmodulo switch is not being changed, just the name of the macros used to determine if the PowerPC processor supports ISA 3.0 (Power9). 2025-05-29 Michael Meissner gcc/ * gcc/config/rs6000/rs6000-builtin.cc (rs6000_builtin_is_supported): Change TARGET_MODULO to TARGET_POWER9. * gcc/config/rs6000/rs6000.cc (rs6000_option_override_internal): Likewise. * gcc/config/rs6000/rs6000.h (TARGET_CTZ): Likewise. (TARGET_EXTSWSLI): Likewise. (TARGET_MADDLD): Likewise. (TARGET_POWER9): New macro. * gcc/config/rs6000/rs6000.md (enabled attribute): Change TARGET_MODULO to TARGET_POWER9. (mod3): Likewise. (umod3): Likewise. (divide/modulo peephole2): Likewise. Diff: --- gcc/config/rs6000/rs6000-builtin.cc | 4 ++-- gcc/config/rs6000/rs6000.cc | 4 ++-- gcc/config/rs6000/rs6000.h | 7 --- gcc/config/rs6000/rs6000.md | 14 +++--- 4 files changed, 15 insertions(+), 14 deletions(-) diff --git a/gcc/config/rs6000/rs6000-builtin.cc b/gcc/config/rs6000/rs6000-builtin.cc index 2366b2aee00a..d8ff7cf32dfd 100644 --- a/gcc/config/rs6000/rs6000-builtin.cc +++ b/gcc/config/rs6000/rs6000-builtin.cc @@ -169,9 +169,9 @@ rs6000_builtin_is_supported (enum rs6000_gen_builtins fncode) case ENB_P8V: return TARGET_P8_VECTOR; case ENB_P9: - return TARGET_MODULO; + return TARGET_POWER9; case ENB_P9_64: - return TARGET_MODULO && TARGET_POWERPC64; + return TARGET_POWER9 && TARGET_POWERPC64; case ENB_P9V: return TARGET_P9_VECTOR; case ENB_P10: diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index fdcaa184cb35..4366771be877 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -3887,7 +3887,7 @@ rs6000_option_override_internal (bool global_init_p) /* For the newer switches (vsx, dfp, etc.) set some of the older options, unless the user explicitly used the -mno- to disable the code. */ - if (TARGET_P9_VECTOR || TARGET_MODULO || TARGET_P9_MISC) + if (TARGET_P9_VECTOR || TARGET_POWER9 || TARGET_P9_MISC) rs6000_isa_flags |= (ISA_3_0_MASKS_SERVER & ~ignore_masks); else if (TARGET_P9_MINMAX) { @@ -22375,7 +22375,7 @@ rs6000_rtx_costs (rtx x, machine_mode mode, int outer_code, *total = rs6000_cost->divsi; } /* Add in shift and subtract for MOD unless we have a mod instruction. */ - if ((!TARGET_MODULO + if ((!TARGET_POWER9 || (RS6000_DISABLE_SCALAR_MODULO && SCALAR_INT_MODE_P (mode))) && (code == MOD || code == UMOD)) *total += COSTS_N_INSNS (2); diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index f1da5d31441a..c2f1910b0ea2 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -463,9 +463,9 @@ extern int rs6000_vector_align[]; #define TARGET_FCTIWUZ TARGET_POWER7 /* Only powerpc64 and powerpc476 support fctid. */ #define TARGET_FCTID (TARGET_POWERPC64 || rs6000_cpu == PROCESSOR_PPC476) -#define TARGET_CTZ TARGET_MODULO -#define TARGET_EXTSWSLI(TARGET_MODULO && TARGET_POWERPC64) -#define TARGET_MADDLD TARGET_MODULO +#define TARGET_CTZ TARGET_POWER9 +#define TARGET_EXTSWSLI(TARGET_POWER9 && TARGET_POWERPC64) +#define TARGET_MADDLD TARGET_POWER9 /* TARGET_DIRECT_MOVE is redundant to TARGET_P8_VECTOR, so alias it to that. */ #define TARGET_DIRECT_MOVE TARGET_P8_VECTOR @@ -504,6 +504,7 @@ extern int rs6000_vector_align[]; #define TARGET_POWER5X TARGET_FPRND #define TARGET_POWER6 TARGET_CMPB #define TARGET_POWER7 TARGET_POPCNTD +#define TARGET_POWER9 TARGET_MODULO /* In switching from using target_flags to using rs6000_isa_flags, the options machinery creates OPTION_MASK_ instead of MASK_. The MASK_ diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 87ec37a9f8e4..db1b6c2d1164 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -403,7 +403,7 @@ (const_int 1) (and (eq_attr "isa" "p9") - (match_test "TARGET_MODULO")) + (match_test "TARGET_POWER9")) (const_int 1) (and (eq_attr "isa" "p9v") @@ -3457,7 +3457,7 @@ || INTVAL (operands[2]) <= 0 || (i = exact_log2 (INTVAL (operands[2]))) < 0) { - if (!TARGET_MODULO) + if (!TARGET_POWER9) FAIL; operands[2] = force_reg (mode, operands[2]); @@ -3491,7 +3491,7 @@ [(set (match_operand:GPR 0 "gpc_reg_operand" "=&r,r") (mod:GPR (match_oper
[gcc(refs/users/meissner/heads/work210)] Change TARGET_POPCNTD to TARGET_POWER7.
https://gcc.gnu.org/g:a6b5cbb668ce7e2a3c01535811bc02200f28338a commit a6b5cbb668ce7e2a3c01535811bc02200f28338a Author: Michael Meissner Date: Thu May 29 18:24:32 2025 -0400 Change TARGET_POPCNTD to TARGET_POWER7. This patch changes TARGET_POPCNTD to TARGET_POWER7. The -mpopcntd switch is not being changed, just the name of the macros used to determine if the PowerPC processor supports ISA 2.6 (Power7). 2025-05-29 Michael Meissner gcc/ * gcc/config/rs6000/dfp.md (cmp_internal1): Change TARGET_POPCNTD to TARGET_POWER7. * gcc/config/rs6000/rs6000-builtin.cc (rs6000_builtin_is_supported): Likewise. * gcc/config/rs6000/rs6000-string.cc (expand_block_compare): Likewise. * gcc/config/rs6000/rs6000.cc (rs6000_hard_regno_mode_ok_uncached): Likewise. (rs6000_option_override_internal): Likewise. (rs6000_rtx_costs): Likewise. * gcc/config/rs6000/rs6000.h (TARGET_LDBRX): Likewise. (TARGET_FCFID): Likewise. (TARGET_LFIWZX): Likewise. (TARGET_FCFIDS): Likewise. (TARGET_FCFIDU): Likewise. (TARGET_FCFIDUS): Likewise. (TARGET_FCTIDUZ): Likewise. (TARGET_FCTIWUZ): Likewise. (TARGET_FCTIDUZ): Likewise. (TARGET_POWER7): New macro. (TARGET_EXTRA_BUILTINS): Change TARGET_POPCNTD to TARGET_POWER7. (CTZ_DEFINED_VALUE_AT_ZERO): Likewise. * gcc/config/rs6000/rs6000.md (enabled attribute): Likewise. (lrintsi2): Likewise. (lrintsi): Likewise. (lrintsi_di): Likewise. (cmpmemsi): Likewise. (bpermd_): Likewise. (addg6s): Likewise. (cdtbcd): Likewise. (cbcdtd): Likewise. (div_): Likewise. Diff: --- gcc/config/rs6000/dfp.md| 2 +- gcc/config/rs6000/rs6000-builtin.cc | 4 ++-- gcc/config/rs6000/rs6000-string.cc | 2 +- gcc/config/rs6000/rs6000.cc | 8 gcc/config/rs6000/rs6000.h | 21 +++-- gcc/config/rs6000/rs6000.md | 20 ++-- 6 files changed, 29 insertions(+), 28 deletions(-) diff --git a/gcc/config/rs6000/dfp.md b/gcc/config/rs6000/dfp.md index 59fa66ae15c8..5919149682b2 100644 --- a/gcc/config/rs6000/dfp.md +++ b/gcc/config/rs6000/dfp.md @@ -214,7 +214,7 @@ (define_insn "floatdidd2" [(set (match_operand:DD 0 "gpc_reg_operand" "=d") (float:DD (match_operand:DI 1 "gpc_reg_operand" "d")))] - "TARGET_DFP && TARGET_POPCNTD" + "TARGET_DFP && TARGET_POWER7" "dcffix %0,%1" [(set_attr "type" "dfp")]) diff --git a/gcc/config/rs6000/rs6000-builtin.cc b/gcc/config/rs6000/rs6000-builtin.cc index dbb8520ab039..2366b2aee00a 100644 --- a/gcc/config/rs6000/rs6000-builtin.cc +++ b/gcc/config/rs6000/rs6000-builtin.cc @@ -161,9 +161,9 @@ rs6000_builtin_is_supported (enum rs6000_gen_builtins fncode) case ENB_P6_64: return TARGET_POWER6 && TARGET_POWERPC64; case ENB_P7: - return TARGET_POPCNTD; + return TARGET_POWER7; case ENB_P7_64: - return TARGET_POPCNTD && TARGET_POWERPC64; + return TARGET_POWER7 && TARGET_POWERPC64; case ENB_P8: return TARGET_POWER8; case ENB_P8V: diff --git a/gcc/config/rs6000/rs6000-string.cc b/gcc/config/rs6000/rs6000-string.cc index 3d2911ca08a0..703f77fa0bf1 100644 --- a/gcc/config/rs6000/rs6000-string.cc +++ b/gcc/config/rs6000/rs6000-string.cc @@ -1949,7 +1949,7 @@ bool expand_block_compare (rtx operands[]) { /* TARGET_POPCNTD is already guarded at expand cmpmemsi. */ - gcc_assert (TARGET_POPCNTD); + gcc_assert (TARGET_POWER7); /* For P8, this case is complicated to handle because the subtract with carry instructions do not generate the 64-bit carry and so diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index 2b0367d8d131..fdcaa184cb35 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -1923,7 +1923,7 @@ rs6000_hard_regno_mode_ok_uncached (int regno, machine_mode mode) if(GET_MODE_SIZE (mode) == UNITS_PER_FP_WORD) return 1; - if (TARGET_POPCNTD && mode == SImode) + if (TARGET_POWER7 && mode == SImode) return 1; if (TARGET_P9_VECTOR && (mode == QImode || mode == HImode)) @@ -3917,7 +3917,7 @@ rs6000_option_override_internal (bool global_init_p) rs6000_isa_flags |= (ISA_2_7_MASKS_SERVER & ~ignore_masks); else if (TARGET_VSX) rs6000_isa_flags |= (ISA_2_6_MASKS_SERVER & ~ignore_masks); - else if (TARGET_POPCNTD) + else if (TARGET_POWER7) rs6000_isa_flags |= (ISA_2_6_MASKS_EMBEDDED & ~ignore_masks); else if (TARGET_DFP) rs6000_isa_flags |= (ISA_2_5_MASKS_SERVER & ~ignore_masks); @@ -4130,7 +4130,7 @@ rs6000_option_override_internal (bool global_init_p) else if (TARGET_LONG_DOUBLE_128)
[gcc(refs/users/meissner/heads/work210)] Change TARGET_CMPB to TARGET_POWER6.
https://gcc.gnu.org/g:d84b6465b9aac59effd9906dc98b22c3cee2436f commit d84b6465b9aac59effd9906dc98b22c3cee2436f Author: Michael Meissner Date: Thu May 29 18:20:21 2025 -0400 Change TARGET_CMPB to TARGET_POWER6. This patch changes TARGET_CMPB to TARGET_POWER6. The -mcmpb switch is not being changed, just the name of the macros used to determine if the PowerPC processor supports ISA 2.5 (Power6). 2025-05-29 Michael Meissner gcc/ * gcc/config/rs6000/rs6000-builtin.cc (rs6000_builtin_is_supported): Change TARGET_CMPB to TARGET_POWER6. * gcc/config/rs6000/rs6000.cc (rs6000_option_override_internal): Likewise. (rs6000_rtx_costs): Likewise. (rs6000_emit_parity): Likewise. * gcc/config/rs6000/rs6000.h (TARGET_FCFID): Likewise. (TARGET_LFIWAX): Likewise. (TARGET_POWER6): New macro. (TARGET_EXTRA_BUILTINS): Change TARGET_CMPB to TARGET_POWER6. * gcc/config/rs6000/rs6000.md (enabled attribute): Likewise. (parity2_cmp): Likewise. (cmpb3): Likewise. (copysign3): Likewise. (copysign3_fcpsgn): Likewise. (cmpstrnsi): Likewise. (cmpstrsi): Likewise. Diff: --- gcc/config/rs6000/rs6000-builtin.cc | 4 ++-- gcc/config/rs6000/rs6000.cc | 8 gcc/config/rs6000/rs6000.h | 7 --- gcc/config/rs6000/rs6000.md | 16 4 files changed, 18 insertions(+), 17 deletions(-) diff --git a/gcc/config/rs6000/rs6000-builtin.cc b/gcc/config/rs6000/rs6000-builtin.cc index 4ed2bc1ca89e..dbb8520ab039 100644 --- a/gcc/config/rs6000/rs6000-builtin.cc +++ b/gcc/config/rs6000/rs6000-builtin.cc @@ -157,9 +157,9 @@ rs6000_builtin_is_supported (enum rs6000_gen_builtins fncode) case ENB_P5: return TARGET_POWER5; case ENB_P6: - return TARGET_CMPB; + return TARGET_POWER6; case ENB_P6_64: - return TARGET_CMPB && TARGET_POWERPC64; + return TARGET_POWER6 && TARGET_POWERPC64; case ENB_P7: return TARGET_POPCNTD; case ENB_P7_64: diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index 300543282b0d..2b0367d8d131 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -3921,7 +3921,7 @@ rs6000_option_override_internal (bool global_init_p) rs6000_isa_flags |= (ISA_2_6_MASKS_EMBEDDED & ~ignore_masks); else if (TARGET_DFP) rs6000_isa_flags |= (ISA_2_5_MASKS_SERVER & ~ignore_masks); - else if (TARGET_CMPB) + else if (TARGET_POWER6) rs6000_isa_flags |= (ISA_2_5_MASKS_EMBEDDED & ~ignore_masks); else if (TARGET_POWER5X) rs6000_isa_flags |= (ISA_2_4_MASKS & ~ignore_masks); @@ -4796,7 +4796,7 @@ rs6000_option_override_internal (bool global_init_p) DERAT mispredict penalty. However the LVE and STVE altivec instructions need indexed accesses and the type used is the scalar type of the element being loaded or stored. */ -TARGET_AVOID_XFORM = (rs6000_tune == PROCESSOR_POWER6 && TARGET_CMPB +TARGET_AVOID_XFORM = (rs6000_tune == PROCESSOR_POWER6 && TARGET_POWER6 && !TARGET_ALTIVEC); /* Set the -mrecip options. */ @@ -22394,7 +22394,7 @@ rs6000_rtx_costs (rtx x, machine_mode mode, int outer_code, return false; case PARITY: - *total = COSTS_N_INSNS (TARGET_CMPB ? 2 : 6); + *total = COSTS_N_INSNS (TARGET_POWER6 ? 2 : 6); return false; case NOT: @@ -23221,7 +23221,7 @@ rs6000_emit_parity (rtx dst, rtx src) tmp = gen_reg_rtx (mode); /* Use the PPC ISA 2.05 prtyw/prtyd instruction if we can. */ - if (TARGET_CMPB) + if (TARGET_POWER6) { if (mode == SImode) { diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index 3794e3c0658d..5b8cf054f98a 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -449,12 +449,12 @@ extern int rs6000_vector_align[]; #define TARGET_FCFID (TARGET_POWERPC64 \ || TARGET_PPC_GPOPT/* 970/power4 */\ || TARGET_POWER5 /* ISA 2.02 */ \ -|| TARGET_CMPB /* ISA 2.05 */ \ +|| TARGET_POWER6 /* ISA 2.05 */ \ || TARGET_POPCNTD) /* ISA 2.06 */ #define TARGET_FCTIDZ TARGET_FCFID #define TARGET_STFIWX TARGET_PPC_GFXOPT -#define TARGET_LFIWAX TARGET_CMPB +#define TARGET_LFIWAX TARGET_POWER6 #define TARGET_LFIWZX TARGET_POPCNTD #define TARGET_FCFIDS TARGET_POPCNTD #define TARGET_FCFIDU TARGET_POPCNTD @@ -502,6 +502,7 @@ extern int rs6000_vector_align[]; /* Convert ISA bits like POPCNTB to PowerPC processors like POWER5. */ #define TARGET_POWER5 TARGET_POPCNTB #define TARGET_POWER5X TARGET_FPRND +#define TARGET_POWER6
[gcc(refs/users/meissner/heads/work210-bugs)] Add ChangeLog.bugs and update REVISION.
https://gcc.gnu.org/g:8d0c177a0f40713a7c3f35353264d13ad0b2b3da commit 8d0c177a0f40713a7c3f35353264d13ad0b2b3da Author: Michael Meissner Date: Thu May 29 16:53:29 2025 -0400 Add ChangeLog.bugs and update REVISION. 2025-05-29 Michael Meissner gcc/ * ChangeLog.bugs: New file for branch. * REVISION: Update. Diff: --- gcc/ChangeLog.bugs | 14 ++ gcc/REVISION | 2 +- 2 files changed, 15 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog.bugs b/gcc/ChangeLog.bugs new file mode 100644 index ..0b825b9eb960 --- /dev/null +++ b/gcc/ChangeLog.bugs @@ -0,0 +1,14 @@ + Branch work210-bugs, baseline + +2025-05-29 Michael Meissner + +Add ChangeLog.bugs and update REVISION. + +2025-05-29 Michael Meissner + +gcc/ + + * ChangeLog.bugs: New file for branch. + * REVISION: Update. + + Clone branch diff --git a/gcc/REVISION b/gcc/REVISION index 2cb696d34aa7..a47fa2561241 100644 --- a/gcc/REVISION +++ b/gcc/REVISION @@ -1 +1 @@ -work210 branch +work210-bugs branch
[gcc(refs/users/meissner/heads/work210-bugs)] Merge commit 'refs/users/meissner/heads/work210-bugs' of git+ssh://gcc.gnu.org/git/gcc into me/work2
https://gcc.gnu.org/g:4953b395bb9fc1f56a3e14c037b8ce3448317735 commit 4953b395bb9fc1f56a3e14c037b8ce3448317735 Merge: 8d0c177a0f40 5536ec166346 Author: Michael Meissner Date: Thu May 29 18:35:31 2025 -0400 Merge commit 'refs/users/meissner/heads/work210-bugs' of git+ssh://gcc.gnu.org/git/gcc into me/work210-bugs Diff:
[gcc/meissner/heads/work210-cmodel] (14 commits) Merge commit 'refs/users/meissner/heads/work210-cmodel' of
The branch 'meissner/heads/work210-cmodel' was updated to point to: c56ac2d3038c... Merge commit 'refs/users/meissner/heads/work210-cmodel' of It previously pointed to: cb0668b90a0f... Add ChangeLog.cmodel and update REVISION. Diff: Summary of changes (added commits): --- c56ac2d... Merge commit 'refs/users/meissner/heads/work210-cmodel' of 3128d82... Add ChangeLog.cmodel and update REVISION. 932ab75... Update ChangeLog.* (*) 7385dec... Use architecture flags for defining _ARCH_PWR macros. (*) 7eaaa4b... Add rs6000 architecture masks. (*) 6b6adab... Use vector pair load/store for memcpy with -mcpu=future (*) 4d392ca... Add -mcpu=future tests. (*) 96f4d34... Add -mcpu=future tuning support. (*) e0b8c5c... Add support for -mcpu=future (*) b6890b7... Change TARGET_MODULO to TARGET_POWER9. (*) a6b5cbb... Change TARGET_POPCNTD to TARGET_POWER7. (*) d84b646... Change TARGET_CMPB to TARGET_POWER6. (*) 9edeaa6... Change TARGET_FPRND to TARGET_POWER5X. (*) 19404f4... Change TARGET_POPCNTB to TARGET_POWER5. (*) (*) This commit already exists in another branch. Because the reference `refs/users/meissner/heads/work210-cmodel' matches your hooks.email-new-commits-only configuration, no separate email is sent for this commit.
[gcc(refs/users/meissner/heads/work210-cmodel)] Add ChangeLog.cmodel and update REVISION.
https://gcc.gnu.org/g:3128d82a3858281fe1b3f547bb7cbeb6af0cedfc commit 3128d82a3858281fe1b3f547bb7cbeb6af0cedfc Author: Michael Meissner Date: Thu May 29 16:54:50 2025 -0400 Add ChangeLog.cmodel and update REVISION. 2025-05-29 Michael Meissner gcc/ * ChangeLog.cmodel: New file for branch. * REVISION: Update. Diff: --- gcc/ChangeLog.cmodel | 14 ++ gcc/REVISION | 2 +- 2 files changed, 15 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog.cmodel b/gcc/ChangeLog.cmodel new file mode 100644 index ..6dcc0a7de404 --- /dev/null +++ b/gcc/ChangeLog.cmodel @@ -0,0 +1,14 @@ + Branch work210-cmodel, baseline + +2025-05-29 Michael Meissner + +Add ChangeLog.cmodel and update REVISION. + +2025-05-29 Michael Meissner + +gcc/ + + * ChangeLog.cmodel: New file for branch. + * REVISION: Update. + + Clone branch diff --git a/gcc/REVISION b/gcc/REVISION index 2cb696d34aa7..456c640337a3 100644 --- a/gcc/REVISION +++ b/gcc/REVISION @@ -1 +1 @@ -work210 branch +work210-cmodel branch
[gcc(refs/users/meissner/heads/work210-cmodel)] Merge commit 'refs/users/meissner/heads/work210-cmodel' of git+ssh://gcc.gnu.org/git/gcc into me/wor
https://gcc.gnu.org/g:c56ac2d3038c9a4c3f2eb2a9a0b0509a552a commit c56ac2d3038c9a4c3f2eb2a9a0b0509a552a Merge: 3128d82a3858 cb0668b90a0f Author: Michael Meissner Date: Thu May 29 18:40:15 2025 -0400 Merge commit 'refs/users/meissner/heads/work210-cmodel' of git+ssh://gcc.gnu.org/git/gcc into me/work210-cmodel Diff:
[gcc/meissner/heads/work210-dmf] (14 commits) Merge commit 'refs/users/meissner/heads/work210-dmf' of git
The branch 'meissner/heads/work210-dmf' was updated to point to: 20001c1cdc63... Merge commit 'refs/users/meissner/heads/work210-dmf' of git It previously pointed to: 6b74e9e2890b... Add ChangeLog.dmf and update REVISION. Diff: Summary of changes (added commits): --- 20001c1... Merge commit 'refs/users/meissner/heads/work210-dmf' of git 9202505... Add ChangeLog.dmf and update REVISION. 932ab75... Update ChangeLog.* (*) 7385dec... Use architecture flags for defining _ARCH_PWR macros. (*) 7eaaa4b... Add rs6000 architecture masks. (*) 6b6adab... Use vector pair load/store for memcpy with -mcpu=future (*) 4d392ca... Add -mcpu=future tests. (*) 96f4d34... Add -mcpu=future tuning support. (*) e0b8c5c... Add support for -mcpu=future (*) b6890b7... Change TARGET_MODULO to TARGET_POWER9. (*) a6b5cbb... Change TARGET_POPCNTD to TARGET_POWER7. (*) d84b646... Change TARGET_CMPB to TARGET_POWER6. (*) 9edeaa6... Change TARGET_FPRND to TARGET_POWER5X. (*) 19404f4... Change TARGET_POPCNTB to TARGET_POWER5. (*) (*) This commit already exists in another branch. Because the reference `refs/users/meissner/heads/work210-dmf' matches your hooks.email-new-commits-only configuration, no separate email is sent for this commit.
[gcc(refs/users/meissner/heads/work210-dmf)] Add ChangeLog.dmf and update REVISION.
https://gcc.gnu.org/g:92025052ee3ebd3f6bc42e300574ad4ac86700fa commit 92025052ee3ebd3f6bc42e300574ad4ac86700fa Author: Michael Meissner Date: Thu May 29 16:55:59 2025 -0400 Add ChangeLog.dmf and update REVISION. 2025-05-29 Michael Meissner gcc/ * ChangeLog.dmf: New file for branch. * REVISION: Update. Diff: --- gcc/ChangeLog.dmf | 14 ++ gcc/REVISION | 2 +- 2 files changed, 15 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog.dmf b/gcc/ChangeLog.dmf new file mode 100644 index ..5c1ad51f20ab --- /dev/null +++ b/gcc/ChangeLog.dmf @@ -0,0 +1,14 @@ + Branch work210-dmf, baseline + +2025-05-29 Michael Meissner + +Add ChangeLog.dmf and update REVISION. + +2025-05-29 Michael Meissner + +gcc/ + + * ChangeLog.dmf: New file for branch. + * REVISION: Update. + + Clone branch diff --git a/gcc/REVISION b/gcc/REVISION index 2cb696d34aa7..58b2ee6f5d7a 100644 --- a/gcc/REVISION +++ b/gcc/REVISION @@ -1 +1 @@ -work210 branch +work210-dmf branch
[gcc(refs/users/meissner/heads/work210-dmf)] Merge commit 'refs/users/meissner/heads/work210-dmf' of git+ssh://gcc.gnu.org/git/gcc into me/work21
https://gcc.gnu.org/g:20001c1cdc63fd6e604019b26d6343203579cfa3 commit 20001c1cdc63fd6e604019b26d6343203579cfa3 Merge: 92025052ee3e 6b74e9e2890b Author: Michael Meissner Date: Thu May 29 18:42:08 2025 -0400 Merge commit 'refs/users/meissner/heads/work210-dmf' of git+ssh://gcc.gnu.org/git/gcc into me/work210-dmf Diff:
[gcc(refs/users/meissner/heads/work210-libs)] Merge commit 'refs/users/meissner/heads/work210-libs' of git+ssh://gcc.gnu.org/git/gcc into me/work2
https://gcc.gnu.org/g:c328665211158ead7b82e203a2b7ccf530916635 commit c328665211158ead7b82e203a2b7ccf530916635 Merge: 905822dca086 41a5b16aae7b Author: Michael Meissner Date: Thu May 29 18:43:26 2025 -0400 Merge commit 'refs/users/meissner/heads/work210-libs' of git+ssh://gcc.gnu.org/git/gcc into me/work210-libs Diff:
[gcc(refs/users/meissner/heads/work210)] Add support for -mcpu=future
https://gcc.gnu.org/g:e0b8c5c7d2b6882eecc832bbecf31cfb331a25bc commit e0b8c5c7d2b6882eecc832bbecf31cfb331a25bc Author: Michael Meissner Date: Thu May 29 18:26:48 2025 -0400 Add support for -mcpu=future This patch adds the support that can be used in developing GCC support for future PowerPC processors. 2025-05-29 Michael Meissner * config.gcc (powerpc*-*-*): Add support for --with-cpu=future. * config/rs6000/aix71.h (ASM_CPU_SPEC): Add support for -mcpu=future. * config/rs6000/aix72.h (ASM_CPU_SPEC): Likewise. * config/rs6000/aix73.h (ASM_CPU_SPEC): Likewise. * config/rs6000/driver-rs6000.cc (asm_names): Likewise. * config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): If -mcpu=future, define _ARCH_FUTURE. * config/rs6000/rs6000-cpus.def (FUTURE_MASKS_SERVER): New macro. (POWERPC_MASKS): Add OPTION_MASK_FUTURE. (future cpu): Define. * config/rs6000/rs6000-opts.h (enum processor_type): Add PROCESSOR_FUTURE. * config/rs6000/rs6000-tables.opt: Regenerate. * config/rs6000/rs6000.cc (power10_cost): Update comment. (get_arch_flags): Add support for future processor. (rs6000_option_override_internal): Likewise. (rs6000_machine_from_flags): Likewise. (rs6000_reassociation_width): Likewise. (rs6000_adjust_cost): Likewise. (rs6000_issue_rate): Likewise. (rs6000_sched_reorder): Likewise. (rs6000_sched_reorder2): Likewise. (rs6000_register_move_cost): Likewise. (rs6000_opt_masks): Add -mfuture. * config/rs6000/rs6000.h (ASM_CPU_SPEC): Likewise. * config/rs6000/rs6000.md (cpu attribute): Likewise. * config/rs6000/rs6000.opt (-mfuture): New internal option. Diff: --- gcc/config.gcc | 4 ++-- gcc/config/rs6000/aix71.h | 1 + gcc/config/rs6000/aix72.h | 1 + gcc/config/rs6000/aix73.h | 1 + gcc/config/rs6000/driver-rs6000.cc | 2 ++ gcc/config/rs6000/rs6000-c.cc | 2 ++ gcc/config/rs6000/rs6000-cpus.def | 5 + gcc/config/rs6000/rs6000-opts.h | 1 + gcc/config/rs6000/rs6000-tables.opt | 11 +++ gcc/config/rs6000/rs6000.cc | 30 ++ gcc/config/rs6000/rs6000.h | 1 + gcc/config/rs6000/rs6000.md | 2 +- gcc/config/rs6000/rs6000.opt| 6 ++ 13 files changed, 52 insertions(+), 15 deletions(-) diff --git a/gcc/config.gcc b/gcc/config.gcc index 1e386a469e0e..b45eba8106be 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -533,7 +533,7 @@ powerpc*-*-*) extra_headers="${extra_headers} ppu_intrinsics.h spu2vmx.h vec_types.h si2vmx.h" extra_headers="${extra_headers} amo.h" case x$with_cpu in - xpowerpc64|xdefault64|x6[23]0|x970|xG5|xpower[3456789]|xpower1[01]|xpower6x|xrs64a|xcell|xa2|xe500mc64|xe5500|xe6500) + xpowerpc64|xdefault64|x6[23]0|x970|xG5|xpower[3456789]|xpower1[01]|xpower6x|xrs64a|xcell|xa2|xe500mc64|xe5500|xe6500|xfuture) cpu_is_64bit=yes ;; esac @@ -5696,7 +5696,7 @@ case "${target}" in tm_defines="${tm_defines} CONFIG_PPC405CR" eval "with_$which=405" ;; - "" | common | native \ + "" | common | native | future \ | power[3456789] | power1[01] | power5+ | power6x \ | powerpc | powerpc64 | powerpc64le \ | rs64 \ diff --git a/gcc/config/rs6000/aix71.h b/gcc/config/rs6000/aix71.h index 2b21dd7cd1e0..77651f5ea309 100644 --- a/gcc/config/rs6000/aix71.h +++ b/gcc/config/rs6000/aix71.h @@ -79,6 +79,7 @@ do { \ #undef ASM_CPU_SPEC #define ASM_CPU_SPEC \ "%{mcpu=native: %(asm_cpu_native); \ + mcpu=future: -mfuture; \ mcpu=power11: -mpwr11; \ mcpu=power10: -mpwr10; \ mcpu=power9: -mpwr9; \ diff --git a/gcc/config/rs6000/aix72.h b/gcc/config/rs6000/aix72.h index 53c0bde5ad4a..652f60c7f494 100644 --- a/gcc/config/rs6000/aix72.h +++ b/gcc/config/rs6000/aix72.h @@ -79,6 +79,7 @@ do { \ #undef ASM_CPU_SPEC #define ASM_CPU_SPEC \ "%{mcpu=native: %(asm_cpu_native); \ + mcpu=future: -mfuture; \ mcpu=power11: -mpwr11; \ mcpu=power10: -mpwr10; \ mcpu=power9: -mpwr9; \ diff --git a/gcc/config/rs6000/aix73.h b/gcc/config/rs6000/aix73.h index c7639368a264..3c66ac1d9171 100644 --- a/gcc/config/rs6000/aix73.h +++ b/gcc/config/rs6000/aix73.h @@ -79,6 +79,7 @@ do { \ #undef ASM_CPU_SPEC #define ASM_CPU_SPEC \ "%{mcpu=nati
[gcc(refs/users/meissner/heads/work210)] Add -mcpu=future tuning support.
https://gcc.gnu.org/g:96f4d3463fde174df4eed37702602bb7948d0c14 commit 96f4d3463fde174df4eed37702602bb7948d0c14 Author: Michael Meissner Date: Thu May 29 18:27:29 2025 -0400 Add -mcpu=future tuning support. This patch makes -mtune=future use the same tuning decision as -mtune=power11. 2025-05-29 Michael Meissner gcc/ * config/rs6000/power10.md (all reservations): Add future as an alterntive to power10 and power11. Diff: --- gcc/config/rs6000/power10.md | 145 ++- 1 file changed, 73 insertions(+), 72 deletions(-) diff --git a/gcc/config/rs6000/power10.md b/gcc/config/rs6000/power10.md index fd31b16b3314..bdd7e58145ba 100644 --- a/gcc/config/rs6000/power10.md +++ b/gcc/config/rs6000/power10.md @@ -1,4 +1,5 @@ -;; Scheduling description for the IBM Power10 and Power11 processors. +;; Scheduling description for the IBM Power10, Power11, and +;; potential future processors. ;; Copyright (C) 2020-2025 Free Software Foundation, Inc. ;; ;; Contributed by Pat Haugen (pthau...@us.ibm.com). @@ -97,12 +98,12 @@ (eq_attr "update" "no") (eq_attr "size" "!128") (eq_attr "prefixed" "no") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_any_power10,LU_power10") (define_insn_reservation "power10-fused-load" 4 (and (eq_attr "type" "fused_load_cmpi,fused_addis_load,fused_load_load") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_even_power10,LU_power10") (define_insn_reservation "power10-prefixed-load" 4 @@ -110,13 +111,13 @@ (eq_attr "update" "no") (eq_attr "size" "!128") (eq_attr "prefixed" "yes") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_even_power10,LU_power10") (define_insn_reservation "power10-load-update" 4 (and (eq_attr "type" "load") (eq_attr "update" "yes") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_even_power10,LU_power10+SXU_power10") (define_insn_reservation "power10-fpload-double" 4 @@ -124,7 +125,7 @@ (eq_attr "update" "no") (eq_attr "size" "64") (eq_attr "prefixed" "no") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_any_power10,LU_power10") (define_insn_reservation "power10-prefixed-fpload-double" 4 @@ -132,14 +133,14 @@ (eq_attr "update" "no") (eq_attr "size" "64") (eq_attr "prefixed" "yes") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_even_power10,LU_power10") (define_insn_reservation "power10-fpload-update-double" 4 (and (eq_attr "type" "fpload") (eq_attr "update" "yes") (eq_attr "size" "64") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_even_power10,LU_power10+SXU_power10") ; SFmode loads are cracked and have additional 3 cycles over DFmode @@ -148,27 +149,27 @@ (and (eq_attr "type" "fpload") (eq_attr "update" "no") (eq_attr "size" "32") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_even_power10,LU_power10") (define_insn_reservation "power10-fpload-update-single" 7 (and (eq_attr "type" "fpload") (eq_attr "update" "yes") (eq_attr "size" "32") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_even_power10,LU_power10+SXU_power10") (define_insn_reservation "power10-vecload" 4 (and (eq_attr "type" "vecload") (eq_attr "size" "!256") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_any_power10,LU_power10") ; lxvp (define_insn_reservation "power10-vecload-pair" 4 (and (eq_attr "type" "vecload") (eq_attr "size" "256") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_even_power10,LU_power10+SXU_power10") ; Store Unit @@ -178,12 +179,12 @@ (eq_attr "prefixed" "no") (eq_attr "size" "!128") (eq_attr "size" "!256") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_any_power10,STU_power10") (define_insn_reservation "power10-fused-store" 0 (and (eq_attr "type" "fused_store_store") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_even_power10,STU_power10") (define_insn_reservation "power10-prefixed-store" 0 @@ -191,52 +192,52 @@ (eq_attr "prefixed" "yes") (eq_attr "size" "!128") (eq_attr "size" "!256") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_even_power10,STU_power10") ; Update forms have 2 cycle lat
[gcc(refs/users/meissner/heads/work210)] Use vector pair load/store for memcpy with -mcpu=future
https://gcc.gnu.org/g:6b6adabec693c4971d789b2996a3584a54fe616c commit 6b6adabec693c4971d789b2996a3584a54fe616c Author: Michael Meissner Date: Thu May 29 18:29:25 2025 -0400 Use vector pair load/store for memcpy with -mcpu=future In the development for the power10 processor, GCC did not enable using the load vector pair and store vector pair instructions when optimizing things like memory copy. This patch enables using those instructions if -mcpu=future is used. 2025-05-29 Michael Meissner gcc/ * config/rs6000/rs6000-cpus.def (ISA_FUTURE_MASKS_SERVER): Enable using load vector pair and store vector pair instructions for memory copy operations. (POWERPC_MASKS): Make the bit for enabling using load vector pair and store vector pair operations set and reset when the PowerPC processor is changed. * gcc/config/rs6000/rs6000.cc (rs6000_machine_from_flags): Disable -mblock-ops-vector-pair from influcing .machine selection. gcc/testsuite/ * gcc.target/powerpc/future-3.c: New test. Diff: --- gcc/config/rs6000/rs6000-cpus.def | 4 +++- gcc/config/rs6000/rs6000.cc | 2 +- gcc/testsuite/gcc.target/powerpc/future-3.c | 22 ++ 3 files changed, 26 insertions(+), 2 deletions(-) diff --git a/gcc/config/rs6000/rs6000-cpus.def b/gcc/config/rs6000/rs6000-cpus.def index 228d0b5e7b54..063591f5c094 100644 --- a/gcc/config/rs6000/rs6000-cpus.def +++ b/gcc/config/rs6000/rs6000-cpus.def @@ -84,7 +84,8 @@ | OPTION_MASK_POWER11) #define FUTURE_MASKS_SERVER(POWER11_MASKS_SERVER \ -| OPTION_MASK_FUTURE) +| OPTION_MASK_FUTURE \ +| OPTION_MASK_BLOCK_OPS_VECTOR_PAIR) /* Flags that need to be turned off if -mno-vsx. */ #define OTHER_VSX_VECTOR_MASKS (OPTION_MASK_EFFICIENT_UNALIGNED_VSX\ @@ -114,6 +115,7 @@ /* Mask of all options to set the default isa flags based on -mcpu=. */ #define POWERPC_MASKS (OPTION_MASK_ALTIVEC\ +| OPTION_MASK_BLOCK_OPS_VECTOR_PAIR\ | OPTION_MASK_CMPB \ | OPTION_MASK_CRYPTO \ | OPTION_MASK_DFP \ diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index 3ed40358a8b1..e983f3d76991 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -5907,7 +5907,7 @@ rs6000_machine_from_flags (void) /* Disable the flags that should never influence the .machine selection. */ flags &= ~(OPTION_MASK_PPC_GFXOPT | OPTION_MASK_PPC_GPOPT | OPTION_MASK_ISEL -| OPTION_MASK_ALTIVEC); +| OPTION_MASK_ALTIVEC | OPTION_MASK_BLOCK_OPS_VECTOR_PAIR); if ((flags & (FUTURE_MASKS_SERVER & ~ISA_3_1_MASKS_SERVER)) != 0) return "future"; diff --git a/gcc/testsuite/gcc.target/powerpc/future-3.c b/gcc/testsuite/gcc.target/powerpc/future-3.c new file mode 100644 index ..afa8b96d --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/future-3.c @@ -0,0 +1,22 @@ +/* 32-bit doesn't generate vector pair instructions. */ +/* { dg-do compile { target lp64 } } */ +/* { dg-options "-mdejagnu-cpu=future -O2" } */ + +/* Test to see that memcpy will use load/store vector pair with + -mcpu=future. */ + +#ifndef SIZE +#define SIZE 4 +#endif + +extern vector double to[SIZE], from[SIZE]; + +void +copy (void) +{ + __builtin_memcpy (to, from, sizeof (to)); + return; +} + +/* { dg-final { scan-assembler {\mlxvpx?\M} } } */ +/* { dg-final { scan-assembler {\mstxvpx?\M} } } */
[gcc(refs/users/meissner/heads/work210)] Add -mcpu=future tests.
https://gcc.gnu.org/g:4d392cafa32d3b2d77a13bc742762df473c3b0d1 commit 4d392cafa32d3b2d77a13bc742762df473c3b0d1 Author: Michael Meissner Date: Thu May 29 18:28:26 2025 -0400 Add -mcpu=future tests. This patch adds simple tests for -mcpu=future. 2025-05-29 Michael Meissner gcc/testsuite/ * gcc.target/powerpc/future-1.c: New test. * gcc.target/powerpc/future-2.c: Likewise. Diff: --- gcc/testsuite/gcc.target/powerpc/future-1.c | 13 + gcc/testsuite/gcc.target/powerpc/future-2.c | 24 2 files changed, 37 insertions(+) diff --git a/gcc/testsuite/gcc.target/powerpc/future-1.c b/gcc/testsuite/gcc.target/powerpc/future-1.c new file mode 100644 index ..f1b940d7bebf --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/future-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mdejagnu-cpu=future -O2" } */ + +/* Basic check to see if the compiler supports -mcpu=future and if it defines + _ARCH_PWR11. */ + +#ifndef _ARCH_FUTURE +#error "-mcpu=future is not supported" +#endif + +void foo (void) +{ +} diff --git a/gcc/testsuite/gcc.target/powerpc/future-2.c b/gcc/testsuite/gcc.target/powerpc/future-2.c new file mode 100644 index ..5552cefa3c2e --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/future-2.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +/* Check if we can set the future target via a target attribute. */ + +__attribute__((__target__("cpu=power9"))) +void foo_p9 (void) +{ +} + +__attribute__((__target__("cpu=power10"))) +void foo_p10 (void) +{ +} + +__attribute__((__target__("cpu=power11"))) +void foo_p11 (void) +{ +} + +__attribute__((__target__("cpu=future"))) +void foo_future (void) +{ +}
[gcc(refs/users/meissner/heads/work210)] Update ChangeLog.*
https://gcc.gnu.org/g:932ab75b0c67168bc136741eabd20502682c1fa4 commit 932ab75b0c67168bc136741eabd20502682c1fa4 Author: Michael Meissner Date: Thu May 29 18:34:30 2025 -0400 Update ChangeLog.* Diff: --- gcc/ChangeLog.meissner | 363 + 1 file changed, 363 insertions(+) diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner index e5799c529019..9c3ff9ac957d 100644 --- a/gcc/ChangeLog.meissner +++ b/gcc/ChangeLog.meissner @@ -1,3 +1,366 @@ + Branch work210, patch #21 + +Use architecture flags for defining _ARCH_PWR macros. + +For the newer architectures, this patch changes GCC to define the _ARCH_PWR +macros using the new architecture flags instead of relying on isa options like +-mpower10. + +The -mpower8-internal, -mpower10, -mpower11, and -mfuture options were removed. +The -mpower11 and -mfuture options were removed completely, since they were just +added in GCC 15. The other two options were marked as WarnRemoved, and the +various ISA bits were removed. + +TARGET_POWER8, TARGET_POWER10, TARGET_POWER11, and TARGET_FUTURE were re-defined +to use the architeture bits instead of the ISA bits. + +There are other internal isa bits that aren't removed with this patch because +the built-in function support uses those bits. + +I have built both big endian and little endian bootstrap compilers and there +were no regressions. + +Can I install this patch on the GCC 16 trunk? + +2025-05-29 Michael Meissner + +gcc/ + + * config/rs6000/rs6000-c.cc (rs6000_target_modify_macros) Add support to + use architecture flags instead of ISA flags for setting most of the + _ARCH_PWR* macros. + (rs6000_cpu_cpp_builtins): Update rs6000_target_modify_macros call. + * config/rs6000/rs6000-cpus.def (ISA_2_7_MASKS_SERVER): Remove + OPTION_MASK_POWER8. + (ISA_3_1_MASKS_SERVER): Remove OPTION_MASK_POWER10. + (POWER11_MASKS_SERVER): Remove OPTION_MASK_POWER11. + (FUTURE_MASKS_SERVER): Remove OPTION_MASK_FUTURE. + (POWERPC_MASKS): Remove OPTION_MASK_POWER8, OPTION_MASK_POWER10, + OPTION_MASK_POWER11, and OPTION_MASK_FUTURE. + * config/rs6000/rs6000-protos.h (rs6000_target_modify_macros): Update + declaration. + (rs6000_target_modify_macros_ptr): Likewise. + * config/rs6000/rs6000.cc (rs6000_target_modify_macros_ptr): Likewise. + (rs6000_option_override_internal): Use architecture flags instead of ISA + flags. + (rs6000_opt_masks): Remove -mpower10, -mpower11, and -mfuture which are + no longer in the ISA flags. + (rs6000_pragma_target_parse): Use architecture flags as well as ISA + flags. + * config/rs6000/rs6000.h (TARGET_POWER5): Redefine to use architecture + flags. + (TARGET_POWER5X): Likewise. + (TARGET_POWER6): Likewise. + (TARGET_POWER7): Likewise. + (TARGET_POWER8): Likewise. + (TARGET_POWER9): Likewise. + (TARGET_POWER10): New macro. + (TARGET_POWER11): Likewise. + (TARGET_FUTURE): Likewise. + * config/rs6000/rs6000.opt (-mpower8-internal): Remove ISA flag bits. + (-mpower10): Likewise. + (-mpower11): Likewise. + (-mfuture): Likewise. + + Branch work210, patch #20 + +Add rs6000 architecture masks. + +This patch begins the journey to move architecture bits that are not user ISA +options from rs6000_isa_flags to a new targt variable rs6000_arch_flags. The +intention is to remove switches that are currently isa options, but the user +should not be using this particular option. For example, we want users to use +-mcpu=power10 and not just -mpower10. + +This patch also changes the target_clones support to use an architecture mask +instead of isa bits. + +This patch also switches the handling of .machine to use architecture masks if +they exist (power4 through power11). All of the other PowerPCs will continue to +use the existing code for setting the .machine option. + +I have built both big endian and little endian bootstrap compilers and there +were no regressions. + +In addition, I constructed a test case that used every archiecture define (like +_ARCH_PWR4, etc.) and I also looked at the .machine directive generated. I ran +this test for all supported combinations of -mcpu, big/little endian, and 32/64 +bit support. Every single instance generated exactly the same code with the +patches installed compared to the compiler before installing the patches. + +The only difference in this patch compared to the first version posted on +November 6th is that I the correct attribution and copyright year (i.e. that I +created rs6000-arch.def in 2024). + +Can I install this patch on the GCC 16 trunk? + +2025-05-29 Michael Meissner + +gcc/ + + * config/rs6000/default64.h (TARGET_CPU_DEFAULT): Set default cpu name. + * config/rs6000/rs6000-arch.def: New file. + * conf
[gcc/meissner/heads/work210-bugs] (14 commits) Merge commit 'refs/users/meissner/heads/work210-bugs' of gi
The branch 'meissner/heads/work210-bugs' was updated to point to: 4953b395bb9f... Merge commit 'refs/users/meissner/heads/work210-bugs' of gi It previously pointed to: 5536ec166346... Add ChangeLog.bugs and update REVISION. Diff: Summary of changes (added commits): --- 4953b39... Merge commit 'refs/users/meissner/heads/work210-bugs' of gi 8d0c177... Add ChangeLog.bugs and update REVISION. 932ab75... Update ChangeLog.* (*) 7385dec... Use architecture flags for defining _ARCH_PWR macros. (*) 7eaaa4b... Add rs6000 architecture masks. (*) 6b6adab... Use vector pair load/store for memcpy with -mcpu=future (*) 4d392ca... Add -mcpu=future tests. (*) 96f4d34... Add -mcpu=future tuning support. (*) e0b8c5c... Add support for -mcpu=future (*) b6890b7... Change TARGET_MODULO to TARGET_POWER9. (*) a6b5cbb... Change TARGET_POPCNTD to TARGET_POWER7. (*) d84b646... Change TARGET_CMPB to TARGET_POWER6. (*) 9edeaa6... Change TARGET_FPRND to TARGET_POWER5X. (*) 19404f4... Change TARGET_POPCNTB to TARGET_POWER5. (*) (*) This commit already exists in another branch. Because the reference `refs/users/meissner/heads/work210-bugs' matches your hooks.email-new-commits-only configuration, no separate email is sent for this commit.
[gcc(refs/users/meissner/heads/work210-dmf)] RFC2655-Add saturating subtract built-ins.
https://gcc.gnu.org/g:cbee8154f457a2a7980bb8ed179e8e7930be6415 commit cbee8154f457a2a7980bb8ed179e8e7930be6415 Author: Michael Meissner Date: Thu May 29 19:06:46 2025 -0400 RFC2655-Add saturating subtract built-ins. This patch adds support for a saturating subtract built-in function that may be added to a future PowerPC processor. Note, if it is added, the name of the built-in function may change before GCC 13 is released. If the name changes, we will submit a patch changing the name. I also added support for providing dense math built-in functions, even though at present, we have not added any new built-in functions for dense math. It is likely we will want to add new dense math built-in functions as the dense math support is fleshed out. The patches have been tested on both little and big endian systems. Can I check it into the master branch? 2025-05-29 Michael Meissner gcc/ * config/rs6000/rs6000-builtin.cc (rs6000_invalid_builtin): Add support for flagging invalid use of future built-in functions. (rs6000_builtin_is_supported): Add support for future built-in functions. * config/rs6000/rs6000-builtins.def (__builtin_saturate_subtract32): New built-in function for -mcpu=future. (__builtin_saturate_subtract64): Likewise. * config/rs6000/rs6000-gen-builtins.cc (enum bif_stanza): Add stanzas for -mcpu=future built-ins. (stanza_map): Likewise. (enable_string): Likewise. (struct attrinfo): Likewise. (parse_bif_attrs): Likewise. (write_decls): Likewise. * config/rs6000/rs6000.md (sat_sub3): Add saturating subtract built-in insn declarations. (sat_sub3_dot): Likewise. (sat_sub3_dot2): Likewise. * doc/extend.texi (Future PowerPC built-ins): New section. gcc/testsuite/ * gcc.target/powerpc/subfus-1.c: New test. * gcc.target/powerpc/subfus-2.c: Likewise. Diff: --- gcc/config/rs6000/rs6000-builtin.cc | 17 gcc/config/rs6000/rs6000-builtins.def | 10 + gcc/config/rs6000/rs6000-gen-builtins.cc| 35 ++--- gcc/config/rs6000/rs6000.md | 60 + gcc/doc/extend.texi | 24 gcc/testsuite/gcc.target/powerpc/subfus-1.c | 32 +++ gcc/testsuite/gcc.target/powerpc/subfus-2.c | 32 +++ 7 files changed, 205 insertions(+), 5 deletions(-) diff --git a/gcc/config/rs6000/rs6000-builtin.cc b/gcc/config/rs6000/rs6000-builtin.cc index ea8755b3ef8a..1885b1f636f3 100644 --- a/gcc/config/rs6000/rs6000-builtin.cc +++ b/gcc/config/rs6000/rs6000-builtin.cc @@ -139,6 +139,17 @@ rs6000_invalid_builtin (enum rs6000_gen_builtins fncode) case ENB_MMA: error ("%qs requires the %qs option", name, "-mmma"); break; +case ENB_FUTURE: + error ("%qs requires the %qs option", name, "-mcpu=future"); + break; +case ENB_FUTURE_64: + error ("%qs requires the %qs option and either the %qs or %qs option", +name, "-mcpu=future", "-m64", "-mpowerpc64"); + break; +case ENB_DM: + error ("%qs requires the %qs or %qs options", name, "-mcpu=future", +"-mdense-math"); + break; default: case ENB_ALWAYS: gcc_unreachable (); @@ -194,6 +205,12 @@ rs6000_builtin_is_supported (enum rs6000_gen_builtins fncode) return TARGET_HTM; case ENB_MMA: return TARGET_MMA; +case ENB_FUTURE: + return TARGET_FUTURE; +case ENB_FUTURE_64: + return TARGET_FUTURE && TARGET_POWERPC64; +case ENB_DM: + return TARGET_DENSE_MATH; default: gcc_unreachable (); } diff --git a/gcc/config/rs6000/rs6000-builtins.def b/gcc/config/rs6000/rs6000-builtins.def index 555d7d589506..eef5f41f7615 100644 --- a/gcc/config/rs6000/rs6000-builtins.def +++ b/gcc/config/rs6000/rs6000-builtins.def @@ -137,6 +137,8 @@ ; endian Needs special handling for endianness ; ibmldRestrict usage to the case when TFmode is IBM-128 ; ibm128 Restrict usage to the case where __ibm128 is supported or if ibmld +; future Restrict usage to future instructions +; dm Restrict usage to dense math ; ; Each attribute corresponds to extra processing required when ; the built-in is expanded. All such special processing should @@ -3924,3 +3926,11 @@ void __builtin_vsx_stxvp (v256, unsigned long, const v256 *); STXVP nothing {mma,pair} + +[future] + const signed int __builtin_saturate_subtract32 (signed int, signed int); + SAT_SUBSI sat_subsi3 {} + +[future-64] + const signed long __builtin_saturate_subtract64 (signed long, signed long); + SAT_SUBDI sat_subdi3 {} diff --git a/gcc/config/rs6000/rs6000-gen-builtins.cc b/gcc/conf
[gcc(refs/users/meissner/heads/work210-dmf)] RFC2656-Support load/store vector with right length.
https://gcc.gnu.org/g:41cc2c4beba13e9c182a7066577dccd59b01c1bb commit 41cc2c4beba13e9c182a7066577dccd59b01c1bb Author: Michael Meissner Date: Thu May 29 19:04:47 2025 -0400 RFC2656-Support load/store vector with right length. This patch adds support for new instructions that may be added to the PowerPC architecture in the future to enhance the load and store vector with length instructions. The current instructions (lxvl, lxvll, stxvl, and stxvll) are inconvient to use since the count for the number of bytes must be in the top 8 bits of the GPR register, instead of the bottom 8 bits. This meant that code generating these instructions typically had to do a shift left by 56 bits to get the count into the right position. In a future version of the PowerPC architecture, new variants of these instructions might be added that expect the count to be in the bottom 8 bits of the GPR register. These patches add this support to GCC if the user uses the -mcpu=future option. I discovered that the code in rs6000-string.cc to generate ISA 3.1 lxvl/stxvl future lxvll/stxvll instructions would generate these instructions on 32-bit. However the patterns for these instructions is only done on 64-bit systems. So I added a check for 64-bit support before generating the instructions. The patches have been tested on both little and big endian systems. Can I check it into the master branch? 2025-05-29 Michael Meissner gcc/ * config/rs6000/rs6000-string.cc (expand_block_move): Do not generate lxvl and stxvl on 32-bit. * config/rs6000/vsx.md (lxvl): If -mcpu=future, generate the lxvl with the shift count automaticaly used in the insn. (lxvrl): New insn for -mcpu=future. (lxvrll): Likewise. (stxvl): If -mcpu=future, generate the stxvl with the shift count automaticaly used in the insn. (stxvrl): New insn for -mcpu=future. (stxvrll): Likewise. gcc/testsuite/ * gcc.target/powerpc/lxvrl.c: New test. * lib/target-supports.exp (check_effective_target_powerpc_future_ok): New effective target. Diff: --- gcc/config/rs6000/rs6000-string.cc | 1 + gcc/config/rs6000/vsx.md | 122 +-- gcc/testsuite/gcc.target/powerpc/lxvrl.c | 32 3 files changed, 134 insertions(+), 21 deletions(-) diff --git a/gcc/config/rs6000/rs6000-string.cc b/gcc/config/rs6000/rs6000-string.cc index 703f77fa0bf1..814328140553 100644 --- a/gcc/config/rs6000/rs6000-string.cc +++ b/gcc/config/rs6000/rs6000-string.cc @@ -2786,6 +2786,7 @@ expand_block_move (rtx operands[], bool might_overlap) if (TARGET_MMA && TARGET_BLOCK_OPS_UNALIGNED_VSX && TARGET_BLOCK_OPS_VECTOR_PAIR + && TARGET_POWERPC64 && bytes >= 32 && (align >= 256 || !STRICT_ALIGNMENT)) { diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index dd3573b80868..89523cf4a0e5 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -5712,20 +5712,32 @@ DONE; }) -;; Load VSX Vector with Length +;; Load VSX Vector with Length. If we have lxvrl, we don't have to do an +;; explicit shift left into a pseudo. (define_expand "lxvl" - [(set (match_dup 3) -(ashift:DI (match_operand:DI 2 "register_operand") - (const_int 56))) - (set (match_operand:V16QI 0 "vsx_register_operand") - (unspec:V16QI -[(match_operand:DI 1 "gpc_reg_operand") - (mem:V16QI (match_dup 1)) - (match_dup 3)] -UNSPEC_LXVL))] + [(use (match_operand:V16QI 0 "vsx_register_operand")) + (use (match_operand:DI 1 "gpc_reg_operand")) + (use (match_operand:DI 2 "gpc_reg_operand"))] "TARGET_P9_VECTOR && TARGET_64BIT" { - operands[3] = gen_reg_rtx (DImode); + rtx shift_len = gen_rtx_ASHIFT (DImode, operands[2], GEN_INT (56)); + rtx len; + + if (TARGET_FUTURE) +len = shift_len; + else +{ + len = gen_reg_rtx (DImode); + emit_insn (gen_rtx_SET (len, shift_len)); +} + + rtx dest = operands[0]; + rtx addr = operands[1]; + rtx mem = gen_rtx_MEM (V16QImode, addr); + rtvec rv = gen_rtvec (3, addr, mem, len); + rtx lxvl = gen_rtx_UNSPEC (V16QImode, rv, UNSPEC_LXVL); + emit_insn (gen_rtx_SET (dest, lxvl)); + DONE; }) (define_insn "*lxvl" @@ -5749,6 +5761,34 @@ "lxvll %x0,%1,%2" [(set_attr "type" "vecload")]) +;; For lxvrl and lxvrll, use the combiner to eliminate the shift. The +;; define_expand for lxvl will already incorporate the shift in generating the +;; insn. The lxvll buitl-in function required the user to have already done +;; the shift. Defining lxvrll this way, will optimize cases where the user has +;; done the shift immediately before the built-in. +(define_insn "*lxvrl" + [(set (matc
[gcc(refs/users/meissner/heads/work210-dmf)] RFC2677-Add xvrlw support.
https://gcc.gnu.org/g:5e64d54a39fe2c2c3d67c030e49192ac69f05d24 commit 5e64d54a39fe2c2c3d67c030e49192ac69f05d24 Author: Michael Meissner Date: Thu May 29 19:08:58 2025 -0400 RFC2677-Add xvrlw support. 2025-05-29 Michael Meissner gcc/ * config/rs6000/altivec.md (xvrlw): New insn. * config/rs6000/rs6000.h (TARGET_XVRLW): New macro. gcc/testsuite/ * gcc.target/powerpc/vector-rotate-left.c: New test. Diff: --- gcc/config/rs6000/altivec.md | 14 + gcc/config/rs6000/rs6000.h | 3 ++ .../gcc.target/powerpc/vector-rotate-left.c| 34 ++ 3 files changed, 51 insertions(+) diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md index 7edc288a6565..d158cf479d60 100644 --- a/gcc/config/rs6000/altivec.md +++ b/gcc/config/rs6000/altivec.md @@ -1982,6 +1982,20 @@ } [(set_attr "type" "vecperm")]) +;; -mcpu=future adds a vector rotate left word variant. There is no vector +;; byte/half-word/double-word/quad-word rotate left. This insn occurs before +;; altivec_vrl and will match for -mcpu=future, while other cpus will +;; match the generic insn. +(define_insn "*xvrlw" + [(set (match_operand:V4SI 0 "register_operand" "=v,wa") + (rotate:V4SI (match_operand:V4SI 1 "register_operand" "v,wa") +(match_operand:V4SI 2 "register_operand" "v,wa")))] + "TARGET_XVRLW" + "@ + vrlw %0,%1,%2 + xvrlw %x0,%x1,%x2" + [(set_attr "type" "vecsimple")]) + (define_insn "altivec_vrl" [(set (match_operand:VI2 0 "register_operand" "=v") (rotate:VI2 (match_operand:VI2 1 "register_operand" "v") diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index 1267169de509..76f1f87290f3 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -584,6 +584,9 @@ extern int rs6000_vector_align[]; /* Whether we have PADDIS support. */ #define TARGET_PADDIS TARGET_FUTURE +/* Whether we have XVRLW support. */ +#define TARGET_XVRLW TARGET_FUTURE + /* Whether the various reciprocal divide/square root estimate instructions exist, and whether we should automatically generate code for the instruction by default. */ diff --git a/gcc/testsuite/gcc.target/powerpc/vector-rotate-left.c b/gcc/testsuite/gcc.target/powerpc/vector-rotate-left.c new file mode 100644 index ..5a5f37755077 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vector-rotate-left.c @@ -0,0 +1,34 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_future_ok } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-options "-mdejagnu-cpu=future -O2" } */ + +/* Test whether the xvrl (vector word rotate left using VSX registers insead of + Altivec registers is generated. */ + +#include + +typedef vector unsigned int v4si_t; + +v4si_t +rotl_v4si_scalar (v4si_t x, unsigned long n) +{ + __asm__ (" # %x0" : "+f" (x)); + return (x << n) | (x >> (32 - n)); /* xvrlw. */ +} + +v4si_t +rotr_v4si_scalar (v4si_t x, unsigned long n) +{ + __asm__ (" # %x0" : "+f" (x)); + return (x >> n) | (x << (32 - n)); /* xvrlw. */ +} + +v4si_t +rotl_v4si_vector (v4si_t x, v4si_t y) +{ + __asm__ (" # %x0" : "+f" (x)); /* xvrlw. */ + return vec_rl (x, y); +} + +/* { dg-final { scan-assembler-times {\mxvrlw\M} 3 } } */
[gcc(refs/users/meissner/heads/work210-dmf)] Update ChangeLog.*
https://gcc.gnu.org/g:3ba5ce0416ad7723ee0a953c65c306daf91ce303 commit 3ba5ce0416ad7723ee0a953c65c306daf91ce303 Author: Michael Meissner Date: Thu May 29 19:11:25 2025 -0400 Update ChangeLog.* Diff: --- gcc/ChangeLog.dmf | 361 ++ 1 file changed, 361 insertions(+) diff --git a/gcc/ChangeLog.dmf b/gcc/ChangeLog.dmf index 5c1ad51f20ab..4ca525e23fa4 100644 --- a/gcc/ChangeLog.dmf +++ b/gcc/ChangeLog.dmf @@ -1,3 +1,364 @@ + Branch work210-dmf, patch #221 + +RFC2677-Add xvrlw support. + +2025-05-29 Michael Meissner + +gcc/ + + * config/rs6000/altivec.md (xvrlw): New insn. + * config/rs6000/rs6000.h (TARGET_XVRLW): New macro. + +gcc/testsuite/ + + * gcc.target/powerpc/vector-rotate-left.c: New test. + + Branch work210-dmf, patch #220 + +RFC2686-Add paddis support. + +2025-05-29 Michael Meissner + +gcc/ + + * config/rs6000/constraints.md (eU): New constraint. + (eV): Likewise. + * config/rs6000/predicates.md (paddis_operand): New predicate. + (paddis_paddi_operand): Likewise. + (add_operand): Add paddis support. + * config/rs6000/rs6000.cc (num_insns_constant_gpr): Add paddis support. + (num_insns_constant_multi): Likewise. + (print_operand): Add %B for paddis support. + * config/rs6000/rs6000.h (TARGET_PADDIS): New macro. + (SIGNED_INTEGER_32BIT_P): Likewise. + * config/rs6000/rs6000.md (isa attribute): Add paddis support. + (enabled attribute); Likewise. + (add3): Likewise. + (adddi3 splitter): New splitter for paddis. + (movdi_internal64): Add paddis support. + (movdi splitter): New splitter for paddis. + +gcc/testsuite/ + + * gcc.target/powerpc/prefixed-addis.c: New test. + + Branch work210-dmf, patch #211 + +RFC2655-Add saturating subtract built-ins. + +This patch adds support for a saturating subtract built-in function that may be +added to a future PowerPC processor. Note, if it is added, the name of the +built-in function may change before GCC 13 is released. If the name changes, +we will submit a patch changing the name. + +I also added support for providing dense math built-in functions, even though +at present, we have not added any new built-in functions for dense math. It is +likely we will want to add new dense math built-in functions as the dense math +support is fleshed out. + +The patches have been tested on both little and big endian systems. Can I check +it into the master branch? + +2025-05-29 Michael Meissner + +gcc/ + + * config/rs6000/rs6000-builtin.cc (rs6000_invalid_builtin): Add support + for flagging invalid use of future built-in functions. + (rs6000_builtin_is_supported): Add support for future built-in + functions. + * config/rs6000/rs6000-builtins.def (__builtin_saturate_subtract32): New + built-in function for -mcpu=future. + (__builtin_saturate_subtract64): Likewise. + * config/rs6000/rs6000-gen-builtins.cc (enum bif_stanza): Add stanzas + for -mcpu=future built-ins. + (stanza_map): Likewise. + (enable_string): Likewise. + (struct attrinfo): Likewise. + (parse_bif_attrs): Likewise. + (write_decls): Likewise. + * config/rs6000/rs6000.md (sat_sub3): Add saturating subtract + built-in insn declarations. + (sat_sub3_dot): Likewise. + (sat_sub3_dot2): Likewise. + * doc/extend.texi (Future PowerPC built-ins): New section. + +gcc/testsuite/ + + * gcc.target/powerpc/subfus-1.c: New test. + * gcc.target/powerpc/subfus-2.c: Likewise. + + Branch work210-dmf, patch #210 + +RFC2656-Support load/store vector with right length. + +This patch adds support for new instructions that may be added to the PowerPC +architecture in the future to enhance the load and store vector with length +instructions. + +The current instructions (lxvl, lxvll, stxvl, and stxvll) are inconvient to use +since the count for the number of bytes must be in the top 8 bits of the GPR +register, instead of the bottom 8 bits. This meant that code generating these +instructions typically had to do a shift left by 56 bits to get the count into +the right position. In a future version of the PowerPC architecture, new +variants of these instructions might be added that expect the count to be in +the bottom 8 bits of the GPR register. These patches add this support to GCC +if the user uses the -mcpu=future option. + +I discovered that the code in rs6000-string.cc to generate ISA 3.1 lxvl/stxvl +future lxvll/stxvll instructions would generate these instructions on 32-bit. +However the patterns for these instructions is only done on 64-bit systems. So +I added a check for 64-bit support before generating the instructions. + +The patches have been tes
[gcc(refs/users/meissner/heads/work210-dmf)] RFC2686-Add paddis support.
https://gcc.gnu.org/g:030cc629e41d1c53859aca45a413ba1b9196b856 commit 030cc629e41d1c53859aca45a413ba1b9196b856 Author: Michael Meissner Date: Thu May 29 19:08:09 2025 -0400 RFC2686-Add paddis support. 2025-05-29 Michael Meissner gcc/ * config/rs6000/constraints.md (eU): New constraint. (eV): Likewise. * config/rs6000/predicates.md (paddis_operand): New predicate. (paddis_paddi_operand): Likewise. (add_operand): Add paddis support. * config/rs6000/rs6000.cc (num_insns_constant_gpr): Add paddis support. (num_insns_constant_multi): Likewise. (print_operand): Add %B for paddis support. * config/rs6000/rs6000.h (TARGET_PADDIS): New macro. (SIGNED_INTEGER_32BIT_P): Likewise. * config/rs6000/rs6000.md (isa attribute): Add paddis support. (enabled attribute); Likewise. (add3): Likewise. (adddi3 splitter): New splitter for paddis. (movdi_internal64): Add paddis support. (movdi splitter): New splitter for paddis. gcc/testsuite/ * gcc.target/powerpc/prefixed-addis.c: New test. Diff: --- gcc/config/rs6000/constraints.md | 10 +++ gcc/config/rs6000/predicates.md | 52 +++- gcc/config/rs6000/rs6000.cc | 25 ++ gcc/config/rs6000/rs6000.h| 4 + gcc/config/rs6000/rs6000.md | 96 --- gcc/testsuite/gcc.target/powerpc/prefixed-addis.c | 24 ++ 6 files changed, 197 insertions(+), 14 deletions(-) diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md index 3da9ed086810..5440becb6e6c 100644 --- a/gcc/config/rs6000/constraints.md +++ b/gcc/config/rs6000/constraints.md @@ -222,6 +222,16 @@ "An IEEE 128-bit constant that can be loaded into VSX registers." (match_operand 0 "easy_vector_constant_ieee128")) +(define_constraint "eU" + "@internal integer constant that can be loaded with paddis" + (and (match_code "const_int") + (match_operand 0 "paddis_operand"))) + +(define_constraint "eV" + "@internal integer constant that can be loaded with paddis + paddi" + (and (match_code "const_int") + (match_operand 0 "paddis_paddi_operand"))) + ;; Floating-point constraints. These two are defined so that insn ;; length attributes can be calculated exactly. diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md index c95b4336f062..c206860e4927 100644 --- a/gcc/config/rs6000/predicates.md +++ b/gcc/config/rs6000/predicates.md @@ -369,6 +369,53 @@ return SIGNED_INTEGER_34BIT_P (INTVAL (op)); }) +;; Return 1 if op is a 64-bit constant that uses the paddis instruction +(define_predicate "paddis_operand" + (match_code "const_int") +{ + if (!TARGET_PADDIS && TARGET_POWERPC64) +return 0; + + /* If addi, addis, or paddi can handle the number, don't return true. */ + HOST_WIDE_INT value = INTVAL (op); + if (SIGNED_INTEGER_34BIT_P (value)) +return false; + + /* If the number is too large for padds, return false. */ + if (!SIGNED_INTEGER_32BIT_P (value >> 32)) +return false; + + /* If the bottom 32-bits are non-zero, paddis can't handle it. */ + if ((value & HOST_WIDE_INT_C(0x)) != 0) +return false; + + return true; +}) + +;; Return 1 if op is a 64-bit constant that needs the paddis instruction and an +;; addi/addis/paddi instruction combination. +(define_predicate "paddis_paddi_operand" + (match_code "const_int") +{ + if (!TARGET_PADDIS && TARGET_POWERPC64) +return 0; + + /* If addi, addis, or paddi can handle the number, don't return true. */ + HOST_WIDE_INT value = INTVAL (op); + if (SIGNED_INTEGER_34BIT_P (value)) +return false; + + /* If the number is too large for padds, return false. */ + if (!SIGNED_INTEGER_32BIT_P (value >> 32)) +return false; + + /* If the bottom 32-bits are zero, we can use paddis alone to handle it. */ + if ((value & HOST_WIDE_INT_C(0x)) == 0) +return false; + + return true; +}) + ;; Return 1 if op is a register that is not special. ;; Disallow (SUBREG:SF (REG:SI)) and (SUBREG:SI (REG:SF)) on VSX systems where ;; you need to be careful in moving a SFmode to SImode and vice versa due to @@ -1113,7 +1160,10 @@ (if_then_else (match_code "const_int") (match_test "satisfies_constraint_I (op) || satisfies_constraint_L (op) -|| satisfies_constraint_eI (op)") +|| satisfies_constraint_eI (op) +|| satisfies_constraint_eU (op) +|| satisfies_constraint_eV (op)") + (match_operand 0 "gpc_reg_operand"))) ;; Return 1 if the operand is either a non-special register, or 0, or -1. diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index 32b3c5f92e71..b2ed9ec7521a 100644 --- a/gcc/con
[gcc r16-978] [AUTOFDO] Enable autofdo tests for aarch64
https://gcc.gnu.org/g:c8fdecf39434eb09b328a1a51535cac6704f7aff commit r16-978-gc8fdecf39434eb09b328a1a51535cac6704f7aff Author: Kugan Vivekanandarajah Date: Fri May 30 07:23:37 2025 +1000 [AUTOFDO] Enable autofdo tests for aarch64 autofdo tests are now running only for x86. This patch makes it run for aarch64 too. Verified that perf and create_gcov are running as expected. gcc/ChangeLog: * config/aarch64/gcc-auto-profile: Make script executable. gcc/testsuite/ChangeLog: * lib/target-supports.exp: Enable autofdo tests for aarch64. Signed-off-by: Kugan Vivekanandarajah Diff: --- gcc/config/aarch64/gcc-auto-profile | 0 gcc/testsuite/lib/target-supports.exp | 35 +-- 2 files changed, 29 insertions(+), 6 deletions(-) diff --git a/gcc/config/aarch64/gcc-auto-profile b/gcc/config/aarch64/gcc-auto-profile old mode 100644 new mode 100755 diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index 6286e361fed0..75d723c63275 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -759,7 +759,13 @@ proc check_effective_target_keeps_null_pointer_checks { } { # this allows parallelism of 16 and higher of parallel gcc-auto-profile proc profopt-perf-wrapper { } { global srcdir -return "$srcdir/../config/i386/gcc-auto-profile --all -m8 " +if { [check_effective_target_x86] } { + return "$srcdir/../config/i386/gcc-auto-profile -m8" +} +if { [istarget aarch64*-*-*] } { + return "$srcdir/../config/aarch64/gcc-auto-profile -m8" +} +return "" } # Return true if profiling is supported on the target. @@ -778,8 +784,7 @@ proc check_profiling_available { test_what } { } if { $test_what == "-fauto-profile" } { - if { !([check_effective_target_x86] && [istarget *-*-linux*]) } { - verbose "autofdo only supported on linux" + if { !([check_effective_target_autofdo]) } { return 0 } # not cross compiling? @@ -787,13 +792,14 @@ proc check_profiling_available { test_what } { verbose "autofdo not supported for non native builds" return 0 } - set event [profopt-perf-wrapper] - if {$event == "" } { + set wrapper [profopt-perf-wrapper] + if {$wrapper == "" } { verbose "autofdo not supported" return 0 } + puts $wrapper global srcdir - set status [remote_exec host "$srcdir/../config/i386/gcc-auto-profile" "-m8 true -v >/dev/null"] + set status [remote_exec host "$wrapper true -v >/dev/null"] if { [lindex $status 0] != 0 } { verbose "autofdo not supported because perf does not work" return 0 @@ -1423,6 +1429,23 @@ proc check_effective_target_fpic { } { return 0 } +# Check if target supports autofdo. + +proc check_effective_target_autofdo { } { +if { !([istarget *-*-linux*]) } { + verbose "autofdo only supported on linux" + return 0 +} +if { [check_effective_target_x86] } { + return 1 +} +if { [istarget aarch64*-*-*] } { + return 1 +} +return 0 +} + + # On AArch64, if -fpic is not supported, then we will fall back to -fPIC # silently. So, we can't rely on above "check_effective_target_fpic" as it # assumes compiler will give warning if -fpic not supported. Here we check
[gcc(refs/users/meissner/heads/work210)] Change TARGET_POPCNTB to TARGET_POWER5.
https://gcc.gnu.org/g:19404f4910110b52367999452fa68450b9d26fe2 commit 19404f4910110b52367999452fa68450b9d26fe2 Author: Michael Meissner Date: Thu May 29 18:18:54 2025 -0400 Change TARGET_POPCNTB to TARGET_POWER5. This patch changes TARGET_POPCNTB to TARGET_POWER5. The -mpopcntb switch is not being changed in this patch, just the name of the macros used to determine if the PowerPC processor supports ISA 2.2 (Power5). 2025-05-29 Michael Meissner gcc/ * gcc/config/rs6000/rs6000-builtin.cc (rs6000_builtin_is_supported): Change TARGET_POPCNTB to TARGET_POWER5. * gcc/config/rs6000/rs6000.cc (rs6000_option_override_internal): Likewise. * gcc/config/rs6000/rs6000.h (TARGET_FCFID): Likewise. (TARGET_POWER5): New macro. (TARGET_EXTRA_BUILTINS): Change TARGET_POPCNTB to TARGET_POWER5. (TARGET_FRE): Likewise. (TARGET_FRSQRTES): Likewise. * gcc/config/rs6000/rs6000.md (enabled attribute): Likewise. Diff: --- gcc/config/rs6000/rs6000-builtin.cc | 2 +- gcc/config/rs6000/rs6000.cc | 2 +- gcc/config/rs6000/rs6000.h | 11 +++ gcc/config/rs6000/rs6000.md | 2 +- 4 files changed, 10 insertions(+), 7 deletions(-) diff --git a/gcc/config/rs6000/rs6000-builtin.cc b/gcc/config/rs6000/rs6000-builtin.cc index 111802381acb..4ed2bc1ca89e 100644 --- a/gcc/config/rs6000/rs6000-builtin.cc +++ b/gcc/config/rs6000/rs6000-builtin.cc @@ -155,7 +155,7 @@ rs6000_builtin_is_supported (enum rs6000_gen_builtins fncode) case ENB_ALWAYS: return true; case ENB_P5: - return TARGET_POPCNTB; + return TARGET_POWER5; case ENB_P6: return TARGET_CMPB; case ENB_P6_64: diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index 7375c36e406d..dacfdb68071c 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -3925,7 +3925,7 @@ rs6000_option_override_internal (bool global_init_p) rs6000_isa_flags |= (ISA_2_5_MASKS_EMBEDDED & ~ignore_masks); else if (TARGET_FPRND) rs6000_isa_flags |= (ISA_2_4_MASKS & ~ignore_masks); - else if (TARGET_POPCNTB) + else if (TARGET_POWER5) rs6000_isa_flags |= (ISA_2_2_MASKS & ~ignore_masks); else if (TARGET_ALTIVEC) rs6000_isa_flags |= (OPTION_MASK_PPC_GFXOPT & ~ignore_masks); diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index db6112a09e11..d9a0ffe9f5b2 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -448,7 +448,7 @@ extern int rs6000_vector_align[]; Enable 32-bit fcfid's on any of the switches for newer ISA machines. */ #define TARGET_FCFID (TARGET_POWERPC64 \ || TARGET_PPC_GPOPT/* 970/power4 */\ -|| TARGET_POPCNTB /* ISA 2.02 */ \ +|| TARGET_POWER5 /* ISA 2.02 */ \ || TARGET_CMPB /* ISA 2.05 */ \ || TARGET_POPCNTD) /* ISA 2.06 */ @@ -499,6 +499,9 @@ extern int rs6000_vector_align[]; #define TARGET_MINMAX (TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT \ && (TARGET_P9_MINMAX || !flag_trapping_math)) +/* Convert ISA bits like POPCNTB to PowerPC processors like POWER5. */ +#define TARGET_POWER5 TARGET_POPCNTB + /* In switching from using target_flags to using rs6000_isa_flags, the options machinery creates OPTION_MASK_ instead of MASK_. The MASK_ options that have not yet been replaced by their OPTION_MASK_ @@ -525,7 +528,7 @@ extern int rs6000_vector_align[]; #define TARGET_EXTRA_BUILTINS (TARGET_POWERPC64\ || TARGET_PPC_GPOPT /* 970/power4 */\ -|| TARGET_POPCNTB /* ISA 2.02 */ \ +|| TARGET_POWER5/* ISA 2.02 */ \ || TARGET_CMPB /* ISA 2.05 */ \ || TARGET_POPCNTD /* ISA 2.06 */ \ || TARGET_ALTIVEC \ @@ -541,9 +544,9 @@ extern int rs6000_vector_align[]; #define TARGET_FRES(TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT) #define TARGET_FRE (TARGET_HARD_FLOAT \ -&& (TARGET_POPCNTB || VECTOR_UNIT_VSX_P (DFmode))) +&& (TARGET_POWER5 || VECTOR_UNIT_VSX_P (DFmode))) -#define TARGET_FRSQRTES(TARGET_HARD_FLOAT && TARGET_POPCNTB \ +#define TARGET_FRSQRTES(TARGET_HARD_FLOAT && TARGET_POWER5 \ && TARGET_PPC_GFXOPT) #define TARGET_FRSQRTE (TARGET_HARD_FLOAT \ diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 9c718ca2a226..c5bd273be8b3 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs
[gcc(refs/users/meissner/heads/work210)] Change TARGET_FPRND to TARGET_POWER5X.
https://gcc.gnu.org/g:9edeaa6531509f2f109de524811c7eee8030119a commit 9edeaa6531509f2f109de524811c7eee8030119a Author: Michael Meissner Date: Thu May 29 18:19:34 2025 -0400 Change TARGET_FPRND to TARGET_POWER5X. This patch changes TARGET_POWER5X to TARGET_POWER5. The -mfprnd switch is not being changed, just the name of the macros used to determine if the PowerPC processor supports ISA 2.4 (Power5x). 2025-05-29 Michael Meissner gcc/ * gcc/config/rs6000/rs6000.cc (rs6000_option_override_internal): Change TARGET_FPRND to TARGET_POWER5X. * gcc/config/rs6000/rs6000.h (TARGET_POWERP5X): New macro. * gcc/config/rs6000/rs6000.md (fmod3): Change TARGET_FPRND to TARGET_POWER5X. (remainder3): Likewise. (fctiwuz_): Likewise. (ceil2): Likewise. (floor2): Likewise. (round2): Likewise. Diff: --- gcc/config/rs6000/rs6000.cc | 4 ++-- gcc/config/rs6000/rs6000.h | 1 + gcc/config/rs6000/rs6000.md | 14 +++--- 3 files changed, 10 insertions(+), 9 deletions(-) diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index dacfdb68071c..300543282b0d 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -3923,7 +3923,7 @@ rs6000_option_override_internal (bool global_init_p) rs6000_isa_flags |= (ISA_2_5_MASKS_SERVER & ~ignore_masks); else if (TARGET_CMPB) rs6000_isa_flags |= (ISA_2_5_MASKS_EMBEDDED & ~ignore_masks); - else if (TARGET_FPRND) + else if (TARGET_POWER5X) rs6000_isa_flags |= (ISA_2_4_MASKS & ~ignore_masks); else if (TARGET_POWER5) rs6000_isa_flags |= (ISA_2_2_MASKS & ~ignore_masks); @@ -3950,7 +3950,7 @@ rs6000_option_override_internal (bool global_init_p) rs6000_isa_flags &= ~OPTION_MASK_CRYPTO; } - if (!TARGET_FPRND && TARGET_VSX) + if (!TARGET_POWER5X && TARGET_VSX) { if (rs6000_isa_flags_explicit & OPTION_MASK_FPRND) /* TARGET_VSX = 1 implies Power 7 and newer */ diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index d9a0ffe9f5b2..3794e3c0658d 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -501,6 +501,7 @@ extern int rs6000_vector_align[]; /* Convert ISA bits like POPCNTB to PowerPC processors like POWER5. */ #define TARGET_POWER5 TARGET_POPCNTB +#define TARGET_POWER5X TARGET_FPRND /* In switching from using target_flags to using rs6000_isa_flags, the options machinery creates OPTION_MASK_ instead of MASK_. The MASK_ diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index c5bd273be8b3..045ce22a03c8 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -5171,7 +5171,7 @@ (use (match_operand:SFDF 1 "gpc_reg_operand")) (use (match_operand:SFDF 2 "gpc_reg_operand"))] "TARGET_HARD_FLOAT - && TARGET_FPRND + && TARGET_POWER5X && flag_unsafe_math_optimizations" { rtx div = gen_reg_rtx (mode); @@ -5189,7 +5189,7 @@ (use (match_operand:SFDF 1 "gpc_reg_operand")) (use (match_operand:SFDF 2 "gpc_reg_operand"))] "TARGET_HARD_FLOAT - && TARGET_FPRND + && TARGET_POWER5X && flag_unsafe_math_optimizations" { rtx div = gen_reg_rtx (mode); @@ -6689,7 +6689,7 @@ (define_insn "*friz" [(set (match_operand:DF 0 "gpc_reg_operand" "=d,wa") (float:DF (fix:DI (match_operand:DF 1 "gpc_reg_operand" "d,wa"] - "TARGET_HARD_FLOAT && TARGET_FPRND + "TARGET_HARD_FLOAT && TARGET_POWER5X && flag_unsafe_math_optimizations && !flag_trapping_math && TARGET_FRIZ" "@ friz %0,%1 @@ -6817,7 +6817,7 @@ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa") (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "d,wa")] UNSPEC_FRIZ))] - "TARGET_HARD_FLOAT && TARGET_FPRND" + "TARGET_HARD_FLOAT && TARGET_POWER5X" "@ friz %0,%1 xsrdpiz %x0,%x1" @@ -6827,7 +6827,7 @@ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa") (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "d,wa")] UNSPEC_FRIP))] - "TARGET_HARD_FLOAT && TARGET_FPRND" + "TARGET_HARD_FLOAT && TARGET_POWER5X" "@ frip %0,%1 xsrdpip %x0,%x1" @@ -6837,7 +6837,7 @@ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa") (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "d,wa")] UNSPEC_FRIM))] - "TARGET_HARD_FLOAT && TARGET_FPRND" + "TARGET_HARD_FLOAT && TARGET_POWER5X" "@ frim %0,%1 xsrdpim %x0,%x1" @@ -6848,7 +6848,7 @@ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=") (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "")] UNSPEC_FRIN))] - "TARGET_HARD_FLOAT && TARGET_FPRND" + "TARGET_HARD_FLOAT && TARGET_POWER5X" "frin %0,%1" [(set_attr "type" "fp")])
[gcc(refs/users/meissner/heads/work210-bugs)] Fix PR 118541, do not generate unordered fp cmoves for IEEE compares.
https://gcc.gnu.org/g:fa4b1d19d6d8178a6fefef7112d600074c8a0868 commit fa4b1d19d6d8178a6fefef7112d600074c8a0868 Author: Michael Meissner Date: Thu May 29 18:50:12 2025 -0400 Fix PR 118541, do not generate unordered fp cmoves for IEEE compares. In bug PR target/118541 on power9, power10, and power11 systems, for the function: extern double __ieee754_acos (double); double __acospi (double x) { double ret = __ieee754_acos (x) / 3.14; return __builtin_isgreater (ret, 1.0) ? 1.0 : ret; } GCC currently generates the following code: Power9 Power10 and Power11 == === bl __ieee754_acos bl __ieee754_acos@notoc nop plfd 0,.LC0@pcrel addis 9,2,.LC2@toc@ha xxspltidp 12,1065353216 addi 1,1,32 addi 1,1,32 lfd 0,.LC2@toc@l(9) ld 0,16(1) addis 9,2,.LC0@toc@ha fdiv 0,1,0 ld 0,16(1) mtlr 0 lfd 12,.LC0@toc@l(9)xscmpgtdp 1,0,12 fdiv 0,1,0 xxsel 1,0,12,1 mtlr 0 blr xscmpgtdp 1,0,12 xxsel 1,0,12,1 blr This is because ifcvt.c optimizes the conditional floating point move to use the XSCMPGTDP instruction. However, the XSCMPGTDP instruction traps if one of the arguments is a signaling NaN. This patch disables generating XSCMP{EQ,GT,GE}{DP,QP} instructions unless -ffinite-math-only is in effect so that we do not get a trap. 2025-05-29 Michael Meissner gcc/ PR target/118541 * config/rs6000/rs6000.cc (have_compare_and_set_mask): Don't do compare and set mask operations unless -ffinite-math-only. * config/rs6000/rs6000.md (movcc_p9): Disable generating XSCMP{EQ,GT,GE}{DP,QP} unless -ffinite-math-only is in effect. (movcc_invert_p9): Likewise. (fpmask, SFDF iterator): Likewise. (xxsel, SFDF iterator): Likewise. (movcc, IEEE128 iterator): Likewise. (movcc_p10): Likewise. (movcc_invert_p10): Likewise. (fpmask, IEEE128 iterator): Likewise. (xxsel, IEEE128 iterator): Likewise. gcc/testsuite/ PR target/118541 * gcc.target/powerpc/float128-cmove.c: Change optimization flag to -Ofast instead of -O2. * gcc.target/powerpc/float128-minmax-3.: Likewise. * gcc.target/powerpc/p9-minmax-2.c: Delete test, the code is no longer valid unless NaNs are not handled. * gcc.target/powerpc/pr118541-1.c: New test. * gcc.target/powerpc/pr118541-2.c: Likewise. Diff: --- gcc/config/rs6000/rs6000.cc| 8 +- gcc/config/rs6000/rs6000.md| 27 ++- gcc/testsuite/gcc.target/powerpc/float128-cmove.c | 6 +- .../gcc.target/powerpc/float128-minmax-3.c | 6 +- gcc/testsuite/gcc.target/powerpc/p9-minmax-2.c | 190 - gcc/testsuite/gcc.target/powerpc/pr118541-1.c | 28 +++ gcc/testsuite/gcc.target/powerpc/pr118541-2.c | 26 +++ 7 files changed, 89 insertions(+), 202 deletions(-) diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index 7ce7932cc1f9..47a1f18c0b60 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -16508,11 +16508,17 @@ rs6000_maybe_emit_fp_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond) /* Helper function to return true if the target has instructions to do a compare and set mask instruction that can be used with XXSEL to implement a conditional move. It is also assumed that such a target also supports the - "C" minimum and maximum instructions. */ + "C" minimum and maximum instructions. + + However, these instructions will trap if given a signaling NaN, so we can + only use them if NaNs are not expected. */ static bool have_compare_and_set_mask (machine_mode mode) { + if (!flag_finite_math_only) +return false; + switch (mode) { case E_SFmode: diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 4c2bc81caf56..c65d564f5142 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -5653,6 +5653,10 @@ "fsel %0,%1,%2,%3" [(set_attr "type" "fp")]) +;; On power9, we can generate XSCMP{EQ,GT,GE}DP and XXSEL to do a floating +;; point conditional move. However, these instructions trap if one of the +;; arguments is a signalling NaN. Therefore we can only do this optimize if +;; NaNs are not expected in the code. (define_insn_and_split "*movcc
[gcc/meissner/heads/work210-libs] (14 commits) Merge commit 'refs/users/meissner/heads/work210-libs' of gi
The branch 'meissner/heads/work210-libs' was updated to point to: c32866521115... Merge commit 'refs/users/meissner/heads/work210-libs' of gi It previously pointed to: 41a5b16aae7b... Add ChangeLog.libs and update REVISION. Diff: Summary of changes (added commits): --- c328665... Merge commit 'refs/users/meissner/heads/work210-libs' of gi 905822d... Add ChangeLog.libs and update REVISION. 932ab75... Update ChangeLog.* (*) 7385dec... Use architecture flags for defining _ARCH_PWR macros. (*) 7eaaa4b... Add rs6000 architecture masks. (*) 6b6adab... Use vector pair load/store for memcpy with -mcpu=future (*) 4d392ca... Add -mcpu=future tests. (*) 96f4d34... Add -mcpu=future tuning support. (*) e0b8c5c... Add support for -mcpu=future (*) b6890b7... Change TARGET_MODULO to TARGET_POWER9. (*) a6b5cbb... Change TARGET_POPCNTD to TARGET_POWER7. (*) d84b646... Change TARGET_CMPB to TARGET_POWER6. (*) 9edeaa6... Change TARGET_FPRND to TARGET_POWER5X. (*) 19404f4... Change TARGET_POPCNTB to TARGET_POWER5. (*) (*) This commit already exists in another branch. Because the reference `refs/users/meissner/heads/work210-libs' matches your hooks.email-new-commits-only configuration, no separate email is sent for this commit.
[gcc(refs/users/meissner/heads/work210-libs)] Add ChangeLog.libs and update REVISION.
https://gcc.gnu.org/g:905822dca086f6f02934e9d8542f4846d46d5118 commit 905822dca086f6f02934e9d8542f4846d46d5118 Author: Michael Meissner Date: Thu May 29 16:57:17 2025 -0400 Add ChangeLog.libs and update REVISION. 2025-05-29 Michael Meissner gcc/ * ChangeLog.libs: New file for branch. * REVISION: Update. Diff: --- gcc/ChangeLog.libs | 14 ++ gcc/REVISION | 2 +- 2 files changed, 15 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog.libs b/gcc/ChangeLog.libs new file mode 100644 index ..e19dd1feba56 --- /dev/null +++ b/gcc/ChangeLog.libs @@ -0,0 +1,14 @@ + Branch work210-libs, baseline + +2025-05-29 Michael Meissner + +Add ChangeLog.libs and update REVISION. + +2025-05-29 Michael Meissner + +gcc/ + + * ChangeLog.libs: New file for branch. + * REVISION: Update. + + Clone branch diff --git a/gcc/REVISION b/gcc/REVISION index 2cb696d34aa7..835efa9f9139 100644 --- a/gcc/REVISION +++ b/gcc/REVISION @@ -1 +1 @@ -work210 branch +work210-libs branch
[gcc(refs/users/meissner/heads/work210-bugs)] Update ChangeLog.*
https://gcc.gnu.org/g:77d689b62386f56f803bcf6d1f621f3acb1031ac commit 77d689b62386f56f803bcf6d1f621f3acb1031ac Author: Michael Meissner Date: Thu May 29 18:52:08 2025 -0400 Update ChangeLog.* Diff: --- gcc/ChangeLog.bugs | 71 ++ 1 file changed, 71 insertions(+) diff --git a/gcc/ChangeLog.bugs b/gcc/ChangeLog.bugs index 0b825b9eb960..7341470f50dc 100644 --- a/gcc/ChangeLog.bugs +++ b/gcc/ChangeLog.bugs @@ -1,3 +1,74 @@ + Branch work210-bugs, patch #100 + +Fix PR 118541, do not generate unordered fp cmoves for IEEE compares. + +In bug PR target/118541 on power9, power10, and power11 systems, for the +function: + +extern double __ieee754_acos (double); + +double +__acospi (double x) +{ + double ret = __ieee754_acos (x) / 3.14; + return __builtin_isgreater (ret, 1.0) ? 1.0 : ret; +} + +GCC currently generates the following code: + +Power9 Power10 and Power11 +== === +bl __ieee754_acos bl __ieee754_acos@notoc +nop plfd 0,.LC0@pcrel +addis 9,2,.LC2@toc@ha xxspltidp 12,1065353216 +addi 1,1,32 addi 1,1,32 +lfd 0,.LC2@toc@l(9) ld 0,16(1) +addis 9,2,.LC0@toc@ha fdiv 0,1,0 +ld 0,16(1) mtlr 0 +lfd 12,.LC0@toc@l(9)xscmpgtdp 1,0,12 +fdiv 0,1,0 xxsel 1,0,12,1 +mtlr 0 blr +xscmpgtdp 1,0,12 +xxsel 1,0,12,1 +blr + +This is because ifcvt.c optimizes the conditional floating point move to use the +XSCMPGTDP instruction. + +However, the XSCMPGTDP instruction traps if one of the arguments is a signaling +NaN. This patch disables generating XSCMP{EQ,GT,GE}{DP,QP} instructions unless +-ffinite-math-only is in effect so that we do not get a trap. + +2025-05-29 Michael Meissner + +gcc/ + + PR target/118541 + * config/rs6000/rs6000.cc (have_compare_and_set_mask): Don't do compare + and set mask operations unless -ffinite-math-only. + * config/rs6000/rs6000.md (movcc_p9): Disable + generating XSCMP{EQ,GT,GE}{DP,QP} unless -ffinite-math-only is in + effect. + (movcc_invert_p9): Likewise. + (fpmask, SFDF iterator): Likewise. + (xxsel, SFDF iterator): Likewise. + (movcc, IEEE128 iterator): Likewise. + (movcc_p10): Likewise. + (movcc_invert_p10): Likewise. + (fpmask, IEEE128 iterator): Likewise. + (xxsel, IEEE128 iterator): Likewise. + +gcc/testsuite/ + + PR target/118541 + * gcc.target/powerpc/float128-cmove.c: Change optimization flag to + -Ofast instead of -O2. + * gcc.target/powerpc/float128-minmax-3.: Likewise. + * gcc.target/powerpc/p9-minmax-2.c: Delete test, the code is no longer + valid unless NaNs are not handled. + * gcc.target/powerpc/pr118541-1.c: New test. + * gcc.target/powerpc/pr118541-2.c: Likewise. + Branch work210-bugs, baseline 2025-05-29 Michael Meissner
[gcc(refs/users/meissner/heads/work210)] Add rs6000 architecture masks.
https://gcc.gnu.org/g:7eaaa4b8d228b5adb04c94ed3984c2e73bfe1501 commit 7eaaa4b8d228b5adb04c94ed3984c2e73bfe1501 Author: Michael Meissner Date: Thu May 29 18:30:48 2025 -0400 Add rs6000 architecture masks. This patch begins the journey to move architecture bits that are not user ISA options from rs6000_isa_flags to a new targt variable rs6000_arch_flags. The intention is to remove switches that are currently isa options, but the user should not be using this particular option. For example, we want users to use -mcpu=power10 and not just -mpower10. This patch also changes the target_clones support to use an architecture mask instead of isa bits. This patch also switches the handling of .machine to use architecture masks if they exist (power4 through power11). All of the other PowerPCs will continue to use the existing code for setting the .machine option. I have built both big endian and little endian bootstrap compilers and there were no regressions. In addition, I constructed a test case that used every archiecture define (like _ARCH_PWR4, etc.) and I also looked at the .machine directive generated. I ran this test for all supported combinations of -mcpu, big/little endian, and 32/64 bit support. Every single instance generated exactly the same code with the patches installed compared to the compiler before installing the patches. The only difference in this patch compared to the first version posted on November 6th is that I the correct attribution and copyright year (i.e. that I created rs6000-arch.def in 2024). Can I install this patch on the GCC 16 trunk? 2025-05-29 Michael Meissner gcc/ * config/rs6000/default64.h (TARGET_CPU_DEFAULT): Set default cpu name. * config/rs6000/rs6000-arch.def: New file. * config/rs6000/rs6000.cc (struct clone_map): Switch to using architecture masks instead of ISA masks. (rs6000_clone_map): Likewise. (rs6000_print_isa_options): Add an architecture flags argument, change all callers. (get_arch_flag): New function. (rs6000_debug_reg_global): Update rs6000_print_isa_options calls. (rs6000_option_override_internal): Likewise. (rs6000_machine_from_flags): Switch to using architecture masks instead of ISA masks. (struct rs6000_arch_mask): New structure. (rs6000_arch_masks): New table of architecutre masks and names. (rs6000_function_specific_save): Save architecture flags. (rs6000_function_specific_restore): Restore architecture flags. (rs6000_function_specific_print): Update rs6000_print_isa_options calls. (rs6000_print_options_internal): Add architecture flags options. (rs6000_clone_priority): Switch to using architecture masks instead of ISA masks. (rs6000_can_inline_p): Don't allow inling if the callee requires a newer architecture than the caller. * config/rs6000/rs6000.h: Use rs6000-arch.def to create the architecture masks. * config/rs6000/rs6000.opt (rs6000_arch_flags): New target variable. (x_rs6000_arch_flags): New save/restore field for rs6000_arch_flags. Diff: --- gcc/config/rs6000/default64.h | 11 ++ gcc/config/rs6000/rs6000-arch.def | 49 + gcc/config/rs6000/rs6000.cc | 222 +++--- gcc/config/rs6000/rs6000.h| 24 + gcc/config/rs6000/rs6000.opt | 8 ++ 5 files changed, 277 insertions(+), 37 deletions(-) diff --git a/gcc/config/rs6000/default64.h b/gcc/config/rs6000/default64.h index 7f6001ded852..188f5c1d1378 100644 --- a/gcc/config/rs6000/default64.h +++ b/gcc/config/rs6000/default64.h @@ -21,6 +21,7 @@ along with GCC; see the file COPYING3. If not see #define RS6000_CPU(NAME, CPU, FLAGS) #include "rs6000-cpus.def" #undef RS6000_CPU +#undef TARGET_CPU_DEFAULT #if (TARGET_DEFAULT & MASK_LITTLE_ENDIAN) #undef TARGET_DEFAULT @@ -28,10 +29,20 @@ along with GCC; see the file COPYING3. If not see | MASK_LITTLE_ENDIAN) #undef ASM_DEFAULT_SPEC #define ASM_DEFAULT_SPEC "-mpower8" +#define TARGET_CPU_DEFAULT "power8" + #else #undef TARGET_DEFAULT #define TARGET_DEFAULT (OPTION_MASK_PPC_GFXOPT | OPTION_MASK_PPC_GPOPT \ | OPTION_MASK_MFCRF | MASK_POWERPC64 | MASK_64BIT) #undef ASM_DEFAULT_SPEC #define ASM_DEFAULT_SPEC "-mpower4" + +#if (TARGET_DEFAULT & MASK_POWERPC64) +#define TARGET_CPU_DEFAULT "powerpc64" + +#else +#define TARGET_CPU_DEFAULT "powerpc" +#endif + #endif diff --git a/gcc/config/rs6000/rs6000-arch.def b/gcc/config/rs6000/rs6000-arch.def new file mode 100644 index ..c0dbc5834333 --- /dev/null +++ b/gcc/config/rs6000/rs6000-arch.def @
[gcc(refs/users/meissner/heads/work210)] Use architecture flags for defining _ARCH_PWR macros.
https://gcc.gnu.org/g:7385dec76316a31ee96904d1cef85590cac8ceff commit 7385dec76316a31ee96904d1cef85590cac8ceff Author: Michael Meissner Date: Thu May 29 18:31:32 2025 -0400 Use architecture flags for defining _ARCH_PWR macros. For the newer architectures, this patch changes GCC to define the _ARCH_PWR macros using the new architecture flags instead of relying on isa options like -mpower10. The -mpower8-internal, -mpower10, -mpower11, and -mfuture options were removed. The -mpower11 and -mfuture options were removed completely, since they were just added in GCC 15. The other two options were marked as WarnRemoved, and the various ISA bits were removed. TARGET_POWER8, TARGET_POWER10, TARGET_POWER11, and TARGET_FUTURE were re-defined to use the architeture bits instead of the ISA bits. There are other internal isa bits that aren't removed with this patch because the built-in function support uses those bits. I have built both big endian and little endian bootstrap compilers and there were no regressions. Can I install this patch on the GCC 16 trunk? 2025-05-29 Michael Meissner gcc/ * config/rs6000/rs6000-c.cc (rs6000_target_modify_macros) Add support to use architecture flags instead of ISA flags for setting most of the _ARCH_PWR* macros. (rs6000_cpu_cpp_builtins): Update rs6000_target_modify_macros call. * config/rs6000/rs6000-cpus.def (ISA_2_7_MASKS_SERVER): Remove OPTION_MASK_POWER8. (ISA_3_1_MASKS_SERVER): Remove OPTION_MASK_POWER10. (POWER11_MASKS_SERVER): Remove OPTION_MASK_POWER11. (FUTURE_MASKS_SERVER): Remove OPTION_MASK_FUTURE. (POWERPC_MASKS): Remove OPTION_MASK_POWER8, OPTION_MASK_POWER10, OPTION_MASK_POWER11, and OPTION_MASK_FUTURE. * config/rs6000/rs6000-protos.h (rs6000_target_modify_macros): Update declaration. (rs6000_target_modify_macros_ptr): Likewise. * config/rs6000/rs6000.cc (rs6000_target_modify_macros_ptr): Likewise. (rs6000_option_override_internal): Use architecture flags instead of ISA flags. (rs6000_opt_masks): Remove -mpower10, -mpower11, and -mfuture which are no longer in the ISA flags. (rs6000_pragma_target_parse): Use architecture flags as well as ISA flags. * config/rs6000/rs6000.h (TARGET_POWER5): Redefine to use architecture flags. (TARGET_POWER5X): Likewise. (TARGET_POWER6): Likewise. (TARGET_POWER7): Likewise. (TARGET_POWER8): Likewise. (TARGET_POWER9): Likewise. (TARGET_POWER10): New macro. (TARGET_POWER11): Likewise. (TARGET_FUTURE): Likewise. * config/rs6000/rs6000.opt (-mpower8-internal): Remove ISA flag bits. (-mpower10): Likewise. (-mpower11): Likewise. (-mfuture): Likewise. Diff: --- gcc/config/rs6000/rs6000-c.cc | 29 - gcc/config/rs6000/rs6000-cpus.def | 10 +- gcc/config/rs6000/rs6000-protos.h | 5 +++-- gcc/config/rs6000/rs6000.cc | 22 -- gcc/config/rs6000/rs6000.h| 19 +-- gcc/config/rs6000/rs6000.opt | 17 ++--- 6 files changed, 47 insertions(+), 55 deletions(-) diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc index 6757a2477ad1..6d6838735b33 100644 --- a/gcc/config/rs6000/rs6000-c.cc +++ b/gcc/config/rs6000/rs6000-c.cc @@ -338,7 +338,8 @@ rs6000_define_or_undefine_macro (bool define_p, const char *name) #pragma GCC target, we need to adjust the macros dynamically. */ void -rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags) +rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags, +HOST_WIDE_INT arch_flags) { if (TARGET_DEBUG_BUILTIN || TARGET_DEBUG_TARGET) fprintf (stderr, @@ -411,7 +412,7 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags) summary of the flags associated with particular cpu definitions. */ - /* rs6000_isa_flags based options. */ + /* rs6000_isa_flags and rs6000_arch_flags based options. */ rs6000_define_or_undefine_macro (define_p, "_ARCH_PPC"); if ((flags & OPTION_MASK_PPC_GPOPT) != 0) rs6000_define_or_undefine_macro (define_p, "_ARCH_PPCSQ"); @@ -419,25 +420,27 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags) rs6000_define_or_undefine_macro (define_p, "_ARCH_PPCGR"); if ((flags & OPTION_MASK_POWERPC64) != 0) rs6000_define_or_undefine_macro (define_p, "_ARCH_PPC64"); - if ((flags & OPTION_MASK_MFCRF) != 0) + if ((flags & OPTION_MASK_POWERPC64) != 0) +rs6000_define_or_undefine_macro (define_p, "_ARCH_PPC64"
[gcc/meissner/heads/work210-sha] (14 commits) Merge commit 'refs/users/meissner/heads/work210-sha' of git
The branch 'meissner/heads/work210-sha' was updated to point to: 9a5c902ba5f0... Merge commit 'refs/users/meissner/heads/work210-sha' of git It previously pointed to: c5f8256e3f5d... Add ChangeLog.sha and update REVISION. Diff: Summary of changes (added commits): --- 9a5c902... Merge commit 'refs/users/meissner/heads/work210-sha' of git 474dc0a... Add ChangeLog.sha and update REVISION. 932ab75... Update ChangeLog.* (*) 7385dec... Use architecture flags for defining _ARCH_PWR macros. (*) 7eaaa4b... Add rs6000 architecture masks. (*) 6b6adab... Use vector pair load/store for memcpy with -mcpu=future (*) 4d392ca... Add -mcpu=future tests. (*) 96f4d34... Add -mcpu=future tuning support. (*) e0b8c5c... Add support for -mcpu=future (*) b6890b7... Change TARGET_MODULO to TARGET_POWER9. (*) a6b5cbb... Change TARGET_POPCNTD to TARGET_POWER7. (*) d84b646... Change TARGET_CMPB to TARGET_POWER6. (*) 9edeaa6... Change TARGET_FPRND to TARGET_POWER5X. (*) 19404f4... Change TARGET_POPCNTB to TARGET_POWER5. (*) (*) This commit already exists in another branch. Because the reference `refs/users/meissner/heads/work210-sha' matches your hooks.email-new-commits-only configuration, no separate email is sent for this commit.
[gcc(refs/users/meissner/heads/work210-sha)] Merge commit 'refs/users/meissner/heads/work210-sha' of git+ssh://gcc.gnu.org/git/gcc into me/work21
https://gcc.gnu.org/g:9a5c902ba5f0089e6e3ccb1bd4570dca03a472a7 commit 9a5c902ba5f0089e6e3ccb1bd4570dca03a472a7 Merge: 474dc0ad6457 c5f8256e3f5d Author: Michael Meissner Date: Thu May 29 18:44:48 2025 -0400 Merge commit 'refs/users/meissner/heads/work210-sha' of git+ssh://gcc.gnu.org/git/gcc into me/work210-sha Diff:
[gcc(refs/users/meissner/heads/work210-sha)] Add ChangeLog.sha and update REVISION.
https://gcc.gnu.org/g:474dc0ad645788e66071691ad574a6884066fabb commit 474dc0ad645788e66071691ad574a6884066fabb Author: Michael Meissner Date: Thu May 29 16:58:35 2025 -0400 Add ChangeLog.sha and update REVISION. 2025-05-29 Michael Meissner gcc/ * ChangeLog.sha: New file for branch. * REVISION: Update. Diff: --- gcc/ChangeLog.sha | 14 ++ gcc/REVISION | 2 +- 2 files changed, 15 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog.sha b/gcc/ChangeLog.sha new file mode 100644 index ..3b49e9eb6ee0 --- /dev/null +++ b/gcc/ChangeLog.sha @@ -0,0 +1,14 @@ + Branch work210-sha, baseline + +2025-05-29 Michael Meissner + +Add ChangeLog.sha and update REVISION. + +2025-05-29 Michael Meissner + +gcc/ + + * ChangeLog.sha: New file for branch. + * REVISION: Update. + + Clone branch diff --git a/gcc/REVISION b/gcc/REVISION index 2cb696d34aa7..c502871443e0 100644 --- a/gcc/REVISION +++ b/gcc/REVISION @@ -1 +1 @@ -work210 branch +work210-sha branch
[gcc(refs/users/meissner/heads/work210-test)] Merge commit 'refs/users/meissner/heads/work210-test' of git+ssh://gcc.gnu.org/git/gcc into me/work2
https://gcc.gnu.org/g:028c2a432f98f80fbe59289636df8b5139849085 commit 028c2a432f98f80fbe59289636df8b5139849085 Merge: ae98945facc9 a57344a6884d Author: Michael Meissner Date: Thu May 29 18:46:30 2025 -0400 Merge commit 'refs/users/meissner/heads/work210-test' of git+ssh://gcc.gnu.org/git/gcc into me/work210-test Diff:
[gcc/meissner/heads/work210-test] (14 commits) Merge commit 'refs/users/meissner/heads/work210-test' of gi
The branch 'meissner/heads/work210-test' was updated to point to: 028c2a432f98... Merge commit 'refs/users/meissner/heads/work210-test' of gi It previously pointed to: a57344a6884d... Add ChangeLog.test and update REVISION. Diff: Summary of changes (added commits): --- 028c2a4... Merge commit 'refs/users/meissner/heads/work210-test' of gi ae98945... Add ChangeLog.test and update REVISION. 932ab75... Update ChangeLog.* (*) 7385dec... Use architecture flags for defining _ARCH_PWR macros. (*) 7eaaa4b... Add rs6000 architecture masks. (*) 6b6adab... Use vector pair load/store for memcpy with -mcpu=future (*) 4d392ca... Add -mcpu=future tests. (*) 96f4d34... Add -mcpu=future tuning support. (*) e0b8c5c... Add support for -mcpu=future (*) b6890b7... Change TARGET_MODULO to TARGET_POWER9. (*) a6b5cbb... Change TARGET_POPCNTD to TARGET_POWER7. (*) d84b646... Change TARGET_CMPB to TARGET_POWER6. (*) 9edeaa6... Change TARGET_FPRND to TARGET_POWER5X. (*) 19404f4... Change TARGET_POPCNTB to TARGET_POWER5. (*) (*) This commit already exists in another branch. Because the reference `refs/users/meissner/heads/work210-test' matches your hooks.email-new-commits-only configuration, no separate email is sent for this commit.
[gcc(refs/users/meissner/heads/work210-test)] Add ChangeLog.test and update REVISION.
https://gcc.gnu.org/g:ae98945facc9d3db826f3bebe879796dcf9d77c4 commit ae98945facc9d3db826f3bebe879796dcf9d77c4 Author: Michael Meissner Date: Thu May 29 16:59:47 2025 -0400 Add ChangeLog.test and update REVISION. 2025-05-29 Michael Meissner gcc/ * ChangeLog.test: New file for branch. * REVISION: Update. Diff: --- gcc/ChangeLog.test | 14 ++ gcc/REVISION | 2 +- 2 files changed, 15 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog.test b/gcc/ChangeLog.test new file mode 100644 index ..b0d63ee16d1f --- /dev/null +++ b/gcc/ChangeLog.test @@ -0,0 +1,14 @@ + Branch work210-test, baseline + +2025-05-29 Michael Meissner + +Add ChangeLog.test and update REVISION. + +2025-05-29 Michael Meissner + +gcc/ + + * ChangeLog.test: New file for branch. + * REVISION: Update. + + Clone branch diff --git a/gcc/REVISION b/gcc/REVISION index 2cb696d34aa7..494e1acdbf3a 100644 --- a/gcc/REVISION +++ b/gcc/REVISION @@ -1 +1 @@ -work210 branch +work210-test branch
[gcc(refs/users/meissner/heads/work210-dmf)] RFC2653-PowerPC: Add support for 1, 024 bit DMR registers.
https://gcc.gnu.org/g:a2ed5f314e5fd014ebc4dadcf681566a3a88a79b commit a2ed5f314e5fd014ebc4dadcf681566a3a88a79b Author: Michael Meissner Date: Thu May 29 19:01:32 2025 -0400 RFC2653-PowerPC: Add support for 1,024 bit DMR registers. This patch is a prelimianry patch to add the full 1,024 bit dense math register (DMRs) for -mcpu=future. The MMA 512-bit accumulators map onto the top of the DMR register. This patch only adds the new 1,024 bit register support. It does not add support for any instructions that need 1,024 bit registers instead of 512 bit registers. I used the new mode 'TDOmode' to be the opaque mode used for 1,024 bit registers. The 'wD' constraint added in previous patches is used for these registers. I added support to do load and store of DMRs via the VSX registers, since there are no load/store dense math instructions. I added the new keyword '__dmr' to create 1,024 bit types that can be loaded into DMRs. At present, I don't have aliases for __dmr512 and __dmr1024 that we've discussed internally. The patches have been tested on both little and big endian systems. Can I check it into the master branch? 2025-05-29 Michael Meissner gcc/ * config/rs6000/mma.md (UNSPEC_DM_INSERT512_UPPER): New unspec. (UNSPEC_DM_INSERT512_LOWER): Likewise. (UNSPEC_DM_EXTRACT512): Likewise. (UNSPEC_DMR_RELOAD_FROM_MEMORY): Likewise. (UNSPEC_DMR_RELOAD_TO_MEMORY): Likewise. (movtdo): New define_expand and define_insn_and_split to implement 1,024 bit DMR registers. (movtdo_insert512_upper): New insn. (movtdo_insert512_lower): Likewise. (movtdo_extract512): Likewise. (reload_dmr_from_memory): Likewise. (reload_dmr_to_memory): Likewise. * config/rs6000/rs6000-builtin.cc (rs6000_type_string): Add DMR support. (rs6000_init_builtins): Add support for __dmr keyword. * config/rs6000/rs6000-call.cc (rs6000_return_in_memory): Add support for TDOmode. (rs6000_function_arg): Likewise. * config/rs6000/rs6000-modes.def (TDOmode): New mode. * config/rs6000/rs6000.cc (rs6000_hard_regno_nregs_internal): Add support for TDOmode. (rs6000_hard_regno_mode_ok_uncached): Likewise. (rs6000_hard_regno_mode_ok): Likewise. (rs6000_modes_tieable_p): Likewise. (rs6000_debug_reg_global): Likewise. (rs6000_setup_reg_addr_masks): Likewise. (rs6000_init_hard_regno_mode_ok): Add support for TDOmode. Setup reload hooks for DMR mode. (reg_offset_addressing_ok_p): Add support for TDOmode. (rs6000_emit_move): Likewise. (rs6000_secondary_reload_simple_move): Likewise. (rs6000_preferred_reload_class): Likewise. (rs6000_secondary_reload_class): Likewise. (rs6000_mangle_type): Add mangling for __dmr type. (rs6000_dmr_register_move_cost): Add support for TDOmode. (rs6000_split_multireg_move): Likewise. (rs6000_invalid_conversion): Likewise. * config/rs6000/rs6000.h (VECTOR_ALIGNMENT_P): Add TDOmode. (enum rs6000_builtin_type_index): Add DMR type nodes. (dmr_type_node): Likewise. (ptr_dmr_type_node): Likewise. gcc/testsuite/ * gcc.target/powerpc/dm-1024bit.c: New test. * lib/target-supports.exp (check_effective_target_ppc_dmr_ok): New target test. Diff: --- gcc/config/rs6000/mma.md | 154 ++ gcc/config/rs6000/rs6000-builtin.cc | 17 +++ gcc/config/rs6000/rs6000-call.cc | 10 +- gcc/config/rs6000/rs6000-modes.def| 4 + gcc/config/rs6000/rs6000.cc | 101 - gcc/config/rs6000/rs6000.h| 6 +- gcc/testsuite/gcc.target/powerpc/dm-1024bit.c | 63 +++ gcc/testsuite/lib/target-supports.exp | 35 ++ 8 files changed, 356 insertions(+), 34 deletions(-) diff --git a/gcc/config/rs6000/mma.md b/gcc/config/rs6000/mma.md index 683d2398ef90..1420fadd4355 100644 --- a/gcc/config/rs6000/mma.md +++ b/gcc/config/rs6000/mma.md @@ -92,6 +92,11 @@ UNSPEC_MMA_XXMFACC UNSPEC_MMA_XXMTACC UNSPEC_MMA_DMSETDMRZ + UNSPEC_DM_INSERT512_UPPER + UNSPEC_DM_INSERT512_LOWER + UNSPEC_DM_EXTRACT512 + UNSPEC_DMR_RELOAD_FROM_MEMORY + UNSPEC_DMR_RELOAD_TO_MEMORY ]) (define_c_enum "unspecv" @@ -742,3 +747,152 @@ " %A0,%x2,%x3,%4,%5,%6" [(set_attr "type" "mma") (set_attr "prefixed" "yes")]) + +;; TDOmode (__dmr keyword for 1,024 bit registers). +(define_expand "movtdo" + [(set (match_operand:TDO 0 "nonimmediate_operand") + (match_operand:
[gcc(refs/users/meissner/heads/work210-dmf)] RFC2653-Add support for dense math registers.
https://gcc.gnu.org/g:acf6dffcff04e876a971efb096fdfa644197bc48 commit acf6dffcff04e876a971efb096fdfa644197bc48 Author: Michael Meissner Date: Thu May 29 19:00:44 2025 -0400 RFC2653-Add support for dense math registers. The MMA subsystem added the notion of accumulator registers as an optional feature of ISA 3.1 (power10). In ISA 3.1, these accumulators overlapped with the VSX registers 0..31, but logically the accumulator registers were separate from the FPR registers. In ISA 3.1, it was anticipated that in future systems, the accumulator registers may no overlap with the FPR registers. This patch adds the support for dense math registers as separate registers. This particular patch does not change the MMA support to use the accumulators within the dense math registers. This patch just adds the basic support for having separate DMRs. The next patch will switch the MMA support to use the accumulators if -mcpu=future is used. For testing purposes, I added an undocumented option '-mdense-math' to enable or disable the dense math support. This patch updates the wD constraint added in the previous patch. If MMA is selected but dense math is not selected (i.e. -mcpu=power10), the wD constraint will allow access to accumulators that overlap with VSX registers 0..31. If both MMA and dense math are selected (i.e. -mcpu=future), the wD constraint will only allow dense math registers. This patch modifies the existing %A output modifier. If MMA is selected but dense math is not selected, then %A output modifier converts the VSX register number to the accumulator number, by dividing it by 4. If both MMA and dense math are selected, then %A will map the separate DMR registers into 0..7. The intention is that user code using extended asm can be modified to run on both MMA without dense math and MMA with dense math: 1) If possible, don't use extended asm, but instead use the MMA built-in functions; 2) If you do need to write extended asm, change the d constraints targetting accumulators should now use wD; 3) Only use the built-in zero, assemble and disassemble functions create move data between vector quad types and dense math accumulators. I.e. do not use the xxmfacc, xxmtacc, and xxsetaccz directly in the extended asm code. The reason is these instructions assume there is a 1-to-1 correspondence between 4 adjacent FPR registers and an accumulator that overlaps with those instructions. With accumulators now being separate registers, there no longer is a 1-to-1 correspondence. It is possible that the mangling for DMRs and the GDB register numbers may produce other changes in the future. gcc/ 2025-05-29 Michael Meissner * config/rs6000/mma.md (UNSPEC_MMA_DMSETDMRZ): New unspec. (movxo): Add comments about dense math registers. (movxo_nodm): Rename from movxo and restrict the usage to machines without dense math registers. (movxo_dm): New insn for movxo support for machines with dense math registers. (mma_): Restrict usage to machines without dense math registers. (mma_xxsetaccz): Add a define_expand wrapper, and add support for dense math registers. (mma_dmsetaccz): New insn. * config/rs6000/predicates.md (dmr_operand): New predicate. (accumulator_operand): Add support for dense math registers. * config/rs6000/rs6000-builtin.cc (rs6000_gimple_fold_mma_builtin): Do not issue a de-prime instruction when disassembling a vector quad on a system with dense math registers. * config/rs6000/rs6000-c.cc (rs6000_define_or_undefine_macro): Define __DENSE_MATH__ if we have dense math registers. * config/rs6000/rs6000.cc (enum rs6000_reg_type): Add DMR_REG_TYPE. (enum rs6000_reload_reg_type): Add RELOAD_REG_DMR. (LAST_RELOAD_REG_CLASS): Add support for DMR registers and the wD constraint. (reload_reg_map): Likewise. (rs6000_reg_names): Likewise. (alt_reg_names): Likewise. (rs6000_hard_regno_nregs_internal): Likewise. (rs6000_hard_regno_mode_ok_uncached): Likewise. (rs6000_debug_reg_global): Likewise. (rs6000_setup_reg_addr_masks): Likewise. (rs6000_init_hard_regno_mode_ok): Likewise. (rs6000_secondary_reload_memory): Add support for DMR registers. (rs6000_secondary_reload_simple_move): Likewise. (rs6000_preferred_reload_class): Likewise. (rs6000_secondary_reload_class): Likewise. (print_operan
[gcc(refs/users/meissner/heads/work210-dmf)] RFC2653-Add wD constraint.
https://gcc.gnu.org/g:6d6dfb5eb2318db0a9ba47c32df6648133f9cf83 commit 6d6dfb5eb2318db0a9ba47c32df6648133f9cf83 Author: Michael Meissner Date: Thu May 29 18:59:46 2025 -0400 RFC2653-Add wD constraint. This patch adds a new constraint ('wD') that matches the accumulator registers that overlap with VSX registers 0..31 on power10. Future patches will add the support for a separate accumulator register class that will be used when the support for dense math registes is added. 2025-05-29 Michael Meissner * config/rs6000/constraints.md (wD): New constraint. * config/rs6000/mma.md (mma_): Prepare for alternate accumulator registers. Use wD constraint instead of 'd' constraint. Use accumulator_operand instead of fpr_reg_operand. (mma_): Likewise. (mma_): Likewise. (mma_): Likewise. (mma_): Likewise. (mma_): Likewise. (mma_): Likewise. (mma_): Likewise. (mma_): Likewise. (mma_): Likewise. (mma_): Likewise. (mma_): Likewise. (mma_): Likewise. (mma_" - [(set (match_operand:XO 0 "fpr_reg_operand" "=&d") - (unspec:XO [(match_operand:XO 1 "fpr_reg_operand" "0")] + [(set (match_operand:XO 0 "accumulator_operand" "=&wD") + (unspec:XO [(match_operand:XO 1 "accumulator_operand" "0")] MMA_ACC))] "TARGET_MMA" " %A0" @@ -523,7 +523,7 @@ [(set_attr "type" "mma")]) (define_insn "mma_" - [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d") + [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD") (unspec:XO [(match_operand:V16QI 1 "vsx_register_operand" "v,?wa") (match_operand:V16QI 2 "vsx_register_operand" "v,?wa")] MMA_VV))] @@ -532,8 +532,8 @@ [(set_attr "type" "mma")]) (define_insn "mma_" - [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d") - (unspec:XO [(match_operand:XO 1 "fpr_reg_operand" "0,0") + [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD") + (unspec:XO [(match_operand:XO 1 "accumulator_operand" "0,0") (match_operand:V16QI 2 "vsx_register_operand" "v,?wa") (match_operand:V16QI 3 "vsx_register_operand" "v,?wa")] MMA_AVV))] @@ -542,7 +542,7 @@ [(set_attr "type" "mma")]) (define_insn "mma_" - [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d") + [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD") (unspec:XO [(match_operand:OO 1 "vsx_register_operand" "v,?wa") (match_operand:V16QI 2 "vsx_register_operand" "v,?wa")] MMA_PV))] @@ -551,8 +551,8 @@ [(set_attr "type" "mma")]) (define_insn "mma_" - [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d") - (unspec:XO [(match_operand:XO 1 "fpr_reg_operand" "0,0") + [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD") + (unspec:XO [(match_operand:XO 1 "accumulator_operand" "0,0") (match_operand:OO 2 "vsx_register_operand" "v,?wa") (match_operand:V16QI 3 "vsx_register_operand" "v,?wa")] MMA_APV))] @@ -561,7 +561,7 @@ [(set_attr "type" "mma")]) (define_insn "mma_" - [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d") + [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD") (unspec:XO [(match_operand:V16QI 1 "vsx_register_operand" "v,?wa") (match_operand:V16QI 2 "vsx_register_operand" "v,?wa") (match_operand:SI 3 "const_0_to_15_operand" "n,n") @@ -574,8 +574,8 @@ (set_attr "prefixed" "yes")]) (define_insn "mma_" - [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d") - (unspec:XO [(match_operand:XO 1 "fpr_reg_operand" "0,0") + [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD") + (unspec:XO [(match_operand:XO 1 "accumulator_operand" "0,0") (match_operand:V16QI 2 "vsx_register_operand" "v,?wa") (match_operand:V16QI 3 "vsx_register_operand" "v,?wa") (match_operand:SI 4 "const_0_to_15_operand" "n,n") @@ -588,7 +588,7 @@ (set_attr "prefixed" "yes")]) (define_insn "mma_" - [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d") + [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD") (unspec:XO [(match_operand:V16QI 1 "vsx_register_operand" "v,?wa") (match_operand:V16QI 2 "vsx_register_operand" "v,?wa") (match_operand:SI 3 "const_0_to_15_operand" "n,n") @@ -601,8 +601,8 @@ (set_attr "prefixed" "yes")]) (define_insn "mma_" - [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d") - (unspec:XO [(match_operand:XO 1 "fpr_reg_operand" "0,0") + [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD") + (unspec:XO [(match_operand:XO 1 "accumulator_operand" "0,0")
[gcc r16-981] scc_copy: conditional return TODO_cleanup_cfg.
https://gcc.gnu.org/g:62ed7fb5259bbcc3268d6801a077903c38fc3b22 commit r16-981-g62ed7fb5259bbcc3268d6801a077903c38fc3b22 Author: Andrew Pinski Date: Thu May 29 15:07:38 2025 -0700 scc_copy: conditional return TODO_cleanup_cfg. Only have cleanup cfg happen if scc copy did some proping. This should be a small compile time improvement by not doing cleanup cfg if scc copy does nothing. Also removes TODO_update_ssa since it should not be needed. gcc/ChangeLog: * gimple-ssa-sccopy.cc (scc_copy_prop::replace_scc_by_value): Return true if something was done. (scc_copy_prop::propagate): Return true if something was changed. (pass_sccopy::execute): Return TODO_cleanup_cfg if a prop happened. Signed-off-by: Andrew Pinski Diff: --- gcc/gimple-ssa-sccopy.cc | 20 1 file changed, 12 insertions(+), 8 deletions(-) diff --git a/gcc/gimple-ssa-sccopy.cc b/gcc/gimple-ssa-sccopy.cc index ee2a7fa8a727..c93374572a9e 100644 --- a/gcc/gimple-ssa-sccopy.cc +++ b/gcc/gimple-ssa-sccopy.cc @@ -464,7 +464,7 @@ class scc_copy_prop public: scc_copy_prop (); ~scc_copy_prop (); - void propagate (); + bool propagate (); private: /* Bitmap tracking statements which were propagated so that they can be @@ -474,15 +474,16 @@ private: void visit_op (tree op, hash_set &outer_ops, hash_set &scc_set, bool &is_inner, tree &last_outer_op); - void replace_scc_by_value (vec scc, tree val); + bool replace_scc_by_value (vec scc, tree val); }; /* For each statement from given SCC, replace its usages by value VAL. */ -void +bool scc_copy_prop::replace_scc_by_value (vec scc, tree val) { + bool didsomething = false; for (gimple *stmt : scc) { tree name = gimple_get_lhs (stmt); @@ -497,10 +498,12 @@ scc_copy_prop::replace_scc_by_value (vec scc, tree val) } replace_uses_by (name, val); bitmap_set_bit (dead_stmts, SSA_NAME_VERSION (name)); + didsomething = true; } if (dump_file) fprintf (dump_file, "Replacing SCC of size %d\n", scc.length ()); + return didsomething; } /* Part of 'scc_copy_prop::propagate ()'. */ @@ -566,9 +569,10 @@ scc_copy_prop::visit_op (tree op, hash_set &outer_ops, Braun, Buchwald, Hack, Leissa, Mallon, Zwinkau, 2013, LNCS vol. 7791, Section 3.2. */ -void +bool scc_copy_prop::propagate () { + bool didsomething = false; auto_vec useful_stmts = get_all_stmt_may_generate_copy (); scc_discovery discovery; @@ -636,7 +640,7 @@ scc_copy_prop::propagate () { /* The only operand in outer_ops. */ tree outer_op = last_outer_op; - replace_scc_by_value (scc, outer_op); + didsomething |= replace_scc_by_value (scc, outer_op); } else if (outer_ops.elements () > 1) { @@ -651,6 +655,7 @@ scc_copy_prop::propagate () scc.release (); } + return didsomething; } scc_copy_prop::scc_copy_prop () @@ -683,7 +688,7 @@ const pass_data pass_data_sccopy = 0, /* properties_provided */ 0, /* properties_destroyed */ 0, /* todo_flags_start */ - TODO_update_ssa | TODO_cleanup_cfg, /* todo_flags_finish */ + 0, /* todo_flags_finish */ }; class pass_sccopy : public gimple_opt_pass @@ -703,8 +708,7 @@ unsigned pass_sccopy::execute (function *) { scc_copy_prop sccopy; - sccopy.propagate (); - return 0; + return sccopy.propagate () ? TODO_cleanup_cfg : 0; } } // anon namespace
[gcc r16-980] [AUTOFDO] Merge profiles of clones before annotating
https://gcc.gnu.org/g:f359866eea8b58a56af14688323e1fd2cd039ad3 commit r16-980-gf359866eea8b58a56af14688323e1fd2cd039ad3 Author: Kugan Vivekanandarajah Date: Fri May 30 13:33:42 2025 +1000 [AUTOFDO] Merge profiles of clones before annotating This patch add support for merging profiles from multiple clones. That is, when optimized binaries have clones such as IPA-CP clone or SRA clones, genarted gcov will have profiled them spereately. Currently we pick one and ignore the rest. This patch fixes this by merging the profiles. gcc/ChangeLog: * auto-profile.cc (function_instance::merge): New. (autofdo_source_profile::read): Call merge. Signed-off-by: Kugan Vivekanandarajah Diff: --- gcc/auto-profile.cc | 34 +- 1 file changed, 33 insertions(+), 1 deletion(-) diff --git a/gcc/auto-profile.cc b/gcc/auto-profile.cc index 3eefb970fde3..91cc8db2c832 100644 --- a/gcc/auto-profile.cc +++ b/gcc/auto-profile.cc @@ -233,6 +233,10 @@ public: function_instance *get_function_instance_by_decl (unsigned lineno, tree decl) const; + /* Merge profile of clones. Note that cloning hasnt been performed when + we annotate the CFG (at this stage). */ + void merge (function_instance *other); + /* Store the profile info for LOC in INFO. Return TRUE if profile info is found. */ bool get_count_info (location_t loc, count_info *info) const; @@ -558,6 +562,27 @@ function_instance::get_function_instance_by_decl (unsigned lineno, return NULL; } +/* Merge profile of clones. Note that cloning hasnt been performed when + we annotate the CFG (at this stage). */ + +void function_instance::merge (function_instance *other) +{ + total_count_ += other->total_count_; + head_count_ += other->head_count_; + + for (callsite_map::const_iterator iter = other->callsites.begin (); + iter != other->callsites.end (); ++iter) +if (callsites.count (iter->first) == 0) + callsites[iter->first] = iter->second; + + for (position_count_map::const_iterator iter = pos_counts.begin (); + iter != pos_counts.end (); ++iter) +if (pos_counts.count (iter->first) == 0) + pos_counts[iter->first] = iter->second; +else + pos_counts[iter->first].count += iter->second.count; +} + /* Store the profile info for LOC in INFO. Return TRUE if profile info is found. */ @@ -838,7 +863,14 @@ autofdo_source_profile::read () function_instance::function_instance_stack stack; function_instance *s = function_instance::read_function_instance ( &stack, gcov_read_counter ()); - map_[s->name ()] = s; + int fun_id = afdo_string_table->get_index + (afdo_string_table->get_name (s->name ())); + /* If function_instace with get_original_name (without the clone +suffix) exixts, merge the function instances. */ + if (map_.count (fun_id) == 0) + map_[fun_id] = s; + else + map_[fun_id]->merge (s); } return true; }
[gcc r16-960] ipa: When inlining, don't combine PT JFs changing signedness (PR120295)
https://gcc.gnu.org/g:0b004c92f5ea239936a403a2a757e12ca82ce6d8 commit r16-960-g0b004c92f5ea239936a403a2a757e12ca82ce6d8 Author: Martin Jambor Date: Thu May 29 16:32:04 2025 +0200 ipa: When inlining, don't combine PT JFs changing signedness (PR120295) In GCC 15 we allowed jump-function generation code to skip over a type-cast converting one integer to another as long as the latter can hold all the values of the former or has at least the same precision. This works well for IPA-CP where we do then evaluate each jump function as we propagate values and value-ranges. However, the test-case in PR 120295 shows a problem with inlining, where we combine pass-through jump-functions so that they are always relative to the function which is the root of the inline tree. Unfortunately, we are happy to combine also those with type-casts to a different signedness which makes us use sign zero extension for the expected value ranges where we should have used sign extension. When the value-range which then leads to wrong insertion of a call to builtin_unreachable is being computed, the information about an existence of a intermediary signed type has already been lost during previous inlining. This patch simply blocks combining such jump-functions so that it is back-portable to GCC 15. Once we switch pass-through jump functions to use a vector of operations rather than having room for just one, we will be able to address this situation with adding an extra conversion instead. gcc/ChangeLog: 2025-05-19 Martin Jambor PR ipa/120295 * ipa-prop.cc (update_jump_functions_after_inlining): Do not combine pass-through jump functions with type-casts changing signedness. gcc/testsuite/ChangeLog: 2025-05-19 Martin Jambor PR ipa/120295 * gcc.dg/ipa/pr120295.c: New test. Diff: --- gcc/ipa-prop.cc | 28 gcc/testsuite/gcc.dg/ipa/pr120295.c | 66 + 2 files changed, 94 insertions(+) diff --git a/gcc/ipa-prop.cc b/gcc/ipa-prop.cc index 24a538034e31..84d4fb5db674 100644 --- a/gcc/ipa-prop.cc +++ b/gcc/ipa-prop.cc @@ -3330,6 +3330,10 @@ update_jump_functions_after_inlining (struct cgraph_edge *cs, ipa_edge_args *args = ipa_edge_args_sum->get (e); if (!args) return; + ipa_node_params *old_inline_root_info = ipa_node_params_sum->get (cs->callee); + ipa_node_params *new_inline_root_info += ipa_node_params_sum->get (cs->caller->inlined_to + ? cs->caller->inlined_to : cs->caller); int count = ipa_get_cs_argument_count (args); int i; @@ -3541,6 +3545,30 @@ update_jump_functions_after_inlining (struct cgraph_edge *cs, enum tree_code operation; operation = ipa_get_jf_pass_through_operation (src); + tree old_ir_ptype = ipa_get_type (old_inline_root_info, + dst_fid); + tree new_ir_ptype = ipa_get_type (new_inline_root_info, + formal_id); + if (!useless_type_conversion_p (old_ir_ptype, new_ir_ptype)) + { + /* Jump-function construction now permits type-casts + from an integer to another if the latter can hold + all values or has at least the same precision. + However, as we're combining multiple pass-through + functions together, we are losing information about + signedness and thus if conversions should sign or + zero extend. Therefore we must prevent combining + such jump-function if signednesses do not match. */ + if (!INTEGRAL_TYPE_P (old_ir_ptype) + || !INTEGRAL_TYPE_P (new_ir_ptype) + || (TYPE_UNSIGNED (new_ir_ptype) + != TYPE_UNSIGNED (old_ir_ptype))) + { + ipa_set_jf_unknown (dst); + continue; + } + } + if (operation == NOP_EXPR) { bool agg_p; diff --git a/gcc/testsuite/gcc.dg/ipa/pr120295.c b/gcc/testsuite/gcc.dg/ipa/pr120295.c new file mode 100644 index ..2033ee9493d2 --- /dev/null +++ b/gcc/testsuite/gcc.dg/ipa/pr120295.c @@ -0,0 +1,66 @@ +/* { dg-do run } */ +/* { dg-options "-O3" } */ + +struct { + signed a; +} b; +int a, f, j, l; +char c, k, g, e; +short d[2] = {0}; +int *i = &j; + +volatile int glob; +void __attribute__((noipa)) sth (const char *, int a) +{ + glob = a; + return; +
[gcc r16-959] ipa: Fix whitespace when dumping VR in jump_functions
https://gcc.gnu.org/g:71e6b7b26a5169d217a62f34acbbc43c592b24bd commit r16-959-g71e6b7b26a5169d217a62f34acbbc43c592b24bd Author: Martin Jambor Date: Thu May 29 16:32:04 2025 +0200 ipa: Fix whitespace when dumping VR in jump_functions Lack of white space breakes the tree-visualisation structure and makes the dump unnecessarily difficult to read. gcc/ChangeLog: 2025-05-19 Martin Jambor * ipa-prop.cc (ipa_dump_jump_function): Fix whitespace when dumping IPA VRs. Diff: --- gcc/ipa-prop.cc | 1 + 1 file changed, 1 insertion(+) diff --git a/gcc/ipa-prop.cc b/gcc/ipa-prop.cc index 0398d69962f8..24a538034e31 100644 --- a/gcc/ipa-prop.cc +++ b/gcc/ipa-prop.cc @@ -542,6 +542,7 @@ ipa_dump_jump_function (FILE *f, ipa_jump_func *jump_func, if (jump_func->m_vr) { + fprintf (f, " "); jump_func->m_vr->dump (f); fprintf (f, "\n"); }
[gcc r16-968] c++: C++17 constexpr lambda and goto/static
https://gcc.gnu.org/g:5c6364b09a67de8d2237f65016ea1e3365a76e8d commit r16-968-g5c6364b09a67de8d2237f65016ea1e3365a76e8d Author: Jason Merrill Date: Thu May 29 12:21:28 2025 -0400 c++: C++17 constexpr lambda and goto/static We only want the error for these cases for functions explicitly declared constexpr, but we still want to set invalid_constexpr on C++17 lambdas so maybe_save_constexpr_fundef doesn't make them implicitly constexpr. The potential_constant_expression_1 change isn't necessary for this test, but still seems correct. gcc/cp/ChangeLog: * decl.cc (start_decl): Also set invalid_constexpr for maybe_constexpr_fn. * parser.cc (cp_parser_jump_statement): Likewise. * constexpr.cc (potential_constant_expression_1): Ignore goto to an artificial label. gcc/testsuite/ChangeLog: * g++.dg/cpp1z/constexpr-lambda29.C: New test. Diff: --- gcc/cp/constexpr.cc | 3 +++ gcc/cp/decl.cc | 28 +++-- gcc/cp/parser.cc| 7 --- gcc/testsuite/g++.dg/cpp1z/constexpr-lambda29.C | 19 + 4 files changed, 43 insertions(+), 14 deletions(-) diff --git a/gcc/cp/constexpr.cc b/gcc/cp/constexpr.cc index fa754b9a176a..272fab328968 100644 --- a/gcc/cp/constexpr.cc +++ b/gcc/cp/constexpr.cc @@ -10979,6 +10979,9 @@ potential_constant_expression_1 (tree t, bool want_rval, bool strict, bool now, *jump_target = *target; return true; } + if (DECL_ARTIFICIAL (*target)) + /* The user didn't write this goto, this isn't the problem. */ + return true; if (flags & tf_error) constexpr_error (loc, fundef_p, "% is not a constant " "expression"); diff --git a/gcc/cp/decl.cc b/gcc/cp/decl.cc index a9ef28bfd805..ec4b6298b11a 100644 --- a/gcc/cp/decl.cc +++ b/gcc/cp/decl.cc @@ -6198,22 +6198,28 @@ start_decl (const cp_declarator *declarator, } if (current_function_decl && VAR_P (decl) - && DECL_DECLARED_CONSTEXPR_P (current_function_decl) + && maybe_constexpr_fn (current_function_decl) && cxx_dialect < cxx23) { bool ok = false; if (CP_DECL_THREAD_LOCAL_P (decl) && !DECL_REALLY_EXTERN (decl)) - error_at (DECL_SOURCE_LOCATION (decl), - "%qD defined % in %qs function only " - "available with %<-std=c++23%> or %<-std=gnu++23%>", decl, - DECL_IMMEDIATE_FUNCTION_P (current_function_decl) - ? "consteval" : "constexpr"); + { + if (DECL_DECLARED_CONSTEXPR_P (current_function_decl)) + error_at (DECL_SOURCE_LOCATION (decl), + "%qD defined % in %qs function only " + "available with %<-std=c++23%> or %<-std=gnu++23%>", decl, + DECL_IMMEDIATE_FUNCTION_P (current_function_decl) + ? "consteval" : "constexpr"); + } else if (TREE_STATIC (decl)) - error_at (DECL_SOURCE_LOCATION (decl), - "%qD defined % in %qs function only available " - "with %<-std=c++23%> or %<-std=gnu++23%>", decl, - DECL_IMMEDIATE_FUNCTION_P (current_function_decl) - ? "consteval" : "constexpr"); + { + if (DECL_DECLARED_CONSTEXPR_P (current_function_decl)) + error_at (DECL_SOURCE_LOCATION (decl), + "%qD defined % in %qs function only available " + "with %<-std=c++23%> or %<-std=gnu++23%>", decl, + DECL_IMMEDIATE_FUNCTION_P (current_function_decl) + ? "consteval" : "constexpr"); + } else ok = true; if (!ok) diff --git a/gcc/cp/parser.cc b/gcc/cp/parser.cc index 3e39bf33fab0..091873cbe3a9 100644 --- a/gcc/cp/parser.cc +++ b/gcc/cp/parser.cc @@ -15431,11 +15431,12 @@ cp_parser_jump_statement (cp_parser* parser, tree &std_attrs) case RID_GOTO: if (parser->in_function_body - && DECL_DECLARED_CONSTEXPR_P (current_function_decl) + && maybe_constexpr_fn (current_function_decl) && cxx_dialect < cxx23) { - error ("% in % function only available with " -"%<-std=c++23%> or %<-std=gnu++23%>"); + if (DECL_DECLARED_CONSTEXPR_P (current_function_decl)) + error ("% in % function only available with " + "%<-std=c++23%> or %<-std=gnu++23%>"); cp_function_chain->invalid_constexpr = true; } diff --git a/gcc/testsuite/g++.dg/cpp1z/constexpr-lambda29.C b/gcc/testsuite/g++.dg/cpp1z/constexpr-lambda29.C new file mode 100644 index ..9e661b6a55d4 --- /dev/null +++ b/gcc/testsuite/g++.dg/cpp1z/constexpr-lambda29.C @@ -0,0 +1,19 @@ +// Test that we don't make lambdas with goto/static impli
[gcc] Created branch 'meissner/heads/work208' in namespace 'refs/users'
The branch 'meissner/heads/work208' was created in namespace 'refs/users' pointing to: 977fadd69776... c++, coroutines: Make a check more specific [PR109283].
[gcc] Created branch 'meissner/heads/work208-orig' in namespace 'refs/users'
The branch 'meissner/heads/work208-orig' was created in namespace 'refs/users' pointing to: 977fadd69776... c++, coroutines: Make a check more specific [PR109283].
[gcc(refs/users/meissner/heads/work208)] Add ChangeLog.meissner and REVISION.
https://gcc.gnu.org/g:f8ea91c0f3050d393a36b6386bd3088854f11edd commit f8ea91c0f3050d393a36b6386bd3088854f11edd Author: Michael Meissner Date: Thu May 29 16:00:41 2025 -0400 Add ChangeLog.meissner and REVISION. 2025-05-29 Michael Meissner gcc/ * REVISION: New file for branch. * ChangeLog.meissner: New file. gcc/c-family/ * ChangeLog.meissner: New file. gcc/c/ * ChangeLog.meissner: New file. gcc/cp/ * ChangeLog.meissner: New file. gcc/fortran/ * ChangeLog.meissner: New file. gcc/testsuite/ * ChangeLog.meissner: New file. libgcc/ * ChangeLog.meissner: New file. Diff: --- gcc/ChangeLog.meissner | 38 ++ gcc/REVISION | 1 + gcc/c-family/ChangeLog.meissner | 38 ++ gcc/c/ChangeLog.meissner | 38 ++ gcc/cp/ChangeLog.meissner| 38 ++ gcc/fortran/ChangeLog.meissner | 38 ++ gcc/testsuite/ChangeLog.meissner | 38 ++ libgcc/ChangeLog.meissner| 38 ++ libstdc++-v3/ChangeLog.meissner | 38 ++ 9 files changed, 305 insertions(+) diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner new file mode 100644 index ..9b89fb2c2fb2 --- /dev/null +++ b/gcc/ChangeLog.meissner @@ -0,0 +1,38 @@ + Branch work208, baseline + +2025-05-29 Michael Meissner + +Add ChangeLog.meissner and REVISION. + +2025-05-29 Michael Meissner + +gcc/ + + * REVISION: New file for branch. + * ChangeLog.meissner: New file. + +gcc/c-family/ + + * ChangeLog.meissner: New file. + +gcc/c/ + + * ChangeLog.meissner: New file. + +gcc/cp/ + + * ChangeLog.meissner: New file. + +gcc/fortran/ + + * ChangeLog.meissner: New file. + +gcc/testsuite/ + + * ChangeLog.meissner: New file. + +libgcc/ + + * ChangeLog.meissner: New file. + + Clone branch diff --git a/gcc/REVISION b/gcc/REVISION new file mode 100644 index ..beb15f6a2b1f --- /dev/null +++ b/gcc/REVISION @@ -0,0 +1 @@ +work208 branch diff --git a/gcc/c-family/ChangeLog.meissner b/gcc/c-family/ChangeLog.meissner new file mode 100644 index ..9b89fb2c2fb2 --- /dev/null +++ b/gcc/c-family/ChangeLog.meissner @@ -0,0 +1,38 @@ + Branch work208, baseline + +2025-05-29 Michael Meissner + +Add ChangeLog.meissner and REVISION. + +2025-05-29 Michael Meissner + +gcc/ + + * REVISION: New file for branch. + * ChangeLog.meissner: New file. + +gcc/c-family/ + + * ChangeLog.meissner: New file. + +gcc/c/ + + * ChangeLog.meissner: New file. + +gcc/cp/ + + * ChangeLog.meissner: New file. + +gcc/fortran/ + + * ChangeLog.meissner: New file. + +gcc/testsuite/ + + * ChangeLog.meissner: New file. + +libgcc/ + + * ChangeLog.meissner: New file. + + Clone branch diff --git a/gcc/c/ChangeLog.meissner b/gcc/c/ChangeLog.meissner new file mode 100644 index ..9b89fb2c2fb2 --- /dev/null +++ b/gcc/c/ChangeLog.meissner @@ -0,0 +1,38 @@ + Branch work208, baseline + +2025-05-29 Michael Meissner + +Add ChangeLog.meissner and REVISION. + +2025-05-29 Michael Meissner + +gcc/ + + * REVISION: New file for branch. + * ChangeLog.meissner: New file. + +gcc/c-family/ + + * ChangeLog.meissner: New file. + +gcc/c/ + + * ChangeLog.meissner: New file. + +gcc/cp/ + + * ChangeLog.meissner: New file. + +gcc/fortran/ + + * ChangeLog.meissner: New file. + +gcc/testsuite/ + + * ChangeLog.meissner: New file. + +libgcc/ + + * ChangeLog.meissner: New file. + + Clone branch diff --git a/gcc/cp/ChangeLog.meissner b/gcc/cp/ChangeLog.meissner new file mode 100644 index ..9b89fb2c2fb2 --- /dev/null +++ b/gcc/cp/ChangeLog.meissner @@ -0,0 +1,38 @@ + Branch work208, baseline + +2025-05-29 Michael Meissner + +Add ChangeLog.meissner and REVISION. + +2025-05-29 Michael Meissner + +gcc/ + + * REVISION: New file for branch. + * ChangeLog.meissner: New file. + +gcc/c-family/ + + * ChangeLog.meissner: New file. + +gcc/c/ + + * ChangeLog.meissner: New file. + +gcc/cp/ + + * ChangeLog.meissner: New file. + +gcc/fortran/ + + * ChangeLog.meissner: New file. + +gcc/testsuite/ + + * ChangeLog.meissner: New file. + +libgcc/ + + * ChangeLog.meissner: New file. + + Clone branch diff --git a/gcc/fortran/ChangeLog.meissner b/gcc/fortran/ChangeLog.meissner new file mode 100644 inde
[gcc] Created branch 'meissner/heads/work208-bugs' in namespace 'refs/users'
The branch 'meissner/heads/work208-bugs' was created in namespace 'refs/users' pointing to: f8ea91c0f305... Add ChangeLog.meissner and REVISION.
[gcc(refs/users/meissner/heads/work208-orig)] Add REVISION.
https://gcc.gnu.org/g:76857730439d8e03ee6204d0ae0a7bb2390e3c8c commit 76857730439d8e03ee6204d0ae0a7bb2390e3c8c Author: Michael Meissner Date: Thu May 29 16:01:46 2025 -0400 Add REVISION. 2025-05-29 Michael Meissner gcc/ * REVISION: New file for branch. Diff: --- gcc/REVISION | 1 + 1 file changed, 1 insertion(+) diff --git a/gcc/REVISION b/gcc/REVISION new file mode 100644 index ..0013a1c9384c --- /dev/null +++ b/gcc/REVISION @@ -0,0 +1 @@ +work208-orig branch
[gcc] Created branch 'meissner/heads/work208-cmodel' in namespace 'refs/users'
The branch 'meissner/heads/work208-cmodel' was created in namespace 'refs/users' pointing to: f8ea91c0f305... Add ChangeLog.meissner and REVISION.
[gcc(refs/users/meissner/heads/work208-bugs)] Add ChangeLog.bugs and update REVISION.
https://gcc.gnu.org/g:82db502a9fa7082606b06418b84989205fcc1423 commit 82db502a9fa7082606b06418b84989205fcc1423 Author: Michael Meissner Date: Thu May 29 16:03:00 2025 -0400 Add ChangeLog.bugs and update REVISION. 2025-05-29 Michael Meissner gcc/ * ChangeLog.bugs: New file for branch. * REVISION: Update. Diff: --- gcc/ChangeLog.bugs | 14 ++ gcc/REVISION | 2 +- 2 files changed, 15 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog.bugs b/gcc/ChangeLog.bugs new file mode 100644 index ..a29161054265 --- /dev/null +++ b/gcc/ChangeLog.bugs @@ -0,0 +1,14 @@ + Branch work208-bugs, baseline + +2025-05-29 Michael Meissner + +Add ChangeLog.bugs and update REVISION. + +2025-05-29 Michael Meissner + +gcc/ + + * ChangeLog.bugs: New file for branch. + * REVISION: Update. + + Clone branch diff --git a/gcc/REVISION b/gcc/REVISION index beb15f6a2b1f..38582e631036 100644 --- a/gcc/REVISION +++ b/gcc/REVISION @@ -1 +1 @@ -work208 branch +work208-bugs branch
[gcc] Created branch 'meissner/heads/work208-dmf' in namespace 'refs/users'
The branch 'meissner/heads/work208-dmf' was created in namespace 'refs/users' pointing to: f8ea91c0f305... Add ChangeLog.meissner and REVISION.
[gcc(refs/users/meissner/heads/work208-cmodel)] Add ChangeLog.cmodel and update REVISION.
https://gcc.gnu.org/g:3c573fbdbed1bf707ea4033344027fe7e304cfc0 commit 3c573fbdbed1bf707ea4033344027fe7e304cfc0 Author: Michael Meissner Date: Thu May 29 16:04:34 2025 -0400 Add ChangeLog.cmodel and update REVISION. 2025-05-29 Michael Meissner gcc/ * ChangeLog.cmodel: New file for branch. * REVISION: Update. Diff: --- gcc/ChangeLog.cmodel | 14 ++ gcc/REVISION | 2 +- 2 files changed, 15 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog.cmodel b/gcc/ChangeLog.cmodel new file mode 100644 index ..0e4c53faf027 --- /dev/null +++ b/gcc/ChangeLog.cmodel @@ -0,0 +1,14 @@ + Branch work208-cmodel, baseline + +2025-05-29 Michael Meissner + +Add ChangeLog.cmodel and update REVISION. + +2025-05-29 Michael Meissner + +gcc/ + + * ChangeLog.cmodel: New file for branch. + * REVISION: Update. + + Clone branch diff --git a/gcc/REVISION b/gcc/REVISION index beb15f6a2b1f..7da4af4150fb 100644 --- a/gcc/REVISION +++ b/gcc/REVISION @@ -1 +1 @@ -work208 branch +work208-cmodel branch
[gcc(refs/users/meissner/heads/work208-dmf)] Add ChangeLog.dmf and update REVISION.
https://gcc.gnu.org/g:e014d8dc929ea507c6ec603e2ee808ef13542df5 commit e014d8dc929ea507c6ec603e2ee808ef13542df5 Author: Michael Meissner Date: Thu May 29 16:05:42 2025 -0400 Add ChangeLog.dmf and update REVISION. 2025-05-29 Michael Meissner gcc/ * ChangeLog.dmf: New file for branch. * REVISION: Update. Diff: --- gcc/ChangeLog.dmf | 14 ++ gcc/REVISION | 2 +- 2 files changed, 15 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog.dmf b/gcc/ChangeLog.dmf new file mode 100644 index ..f07d358d9fe2 --- /dev/null +++ b/gcc/ChangeLog.dmf @@ -0,0 +1,14 @@ + Branch work208-dmf, baseline + +2025-05-29 Michael Meissner + +Add ChangeLog.dmf and update REVISION. + +2025-05-29 Michael Meissner + +gcc/ + + * ChangeLog.dmf: New file for branch. + * REVISION: Update. + + Clone branch diff --git a/gcc/REVISION b/gcc/REVISION index beb15f6a2b1f..acd0c0916e6b 100644 --- a/gcc/REVISION +++ b/gcc/REVISION @@ -1 +1 @@ -work208 branch +work208-dmf branch
[gcc] Created branch 'meissner/heads/work208-libs' in namespace 'refs/users'
The branch 'meissner/heads/work208-libs' was created in namespace 'refs/users' pointing to: f8ea91c0f305... Add ChangeLog.meissner and REVISION.
[gcc(refs/users/meissner/heads/work208-libs)] Add ChangeLog.libs and update REVISION.
https://gcc.gnu.org/g:dcb4e8f33e1ac9f7542820c793a55d704b596f6d commit dcb4e8f33e1ac9f7542820c793a55d704b596f6d Author: Michael Meissner Date: Thu May 29 16:06:45 2025 -0400 Add ChangeLog.libs and update REVISION. 2025-05-29 Michael Meissner gcc/ * ChangeLog.libs: New file for branch. * REVISION: Update. Diff: --- gcc/ChangeLog.libs | 14 ++ gcc/REVISION | 2 +- 2 files changed, 15 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog.libs b/gcc/ChangeLog.libs new file mode 100644 index ..d7600cf27ed2 --- /dev/null +++ b/gcc/ChangeLog.libs @@ -0,0 +1,14 @@ + Branch work208-libs, baseline + +2025-05-29 Michael Meissner + +Add ChangeLog.libs and update REVISION. + +2025-05-29 Michael Meissner + +gcc/ + + * ChangeLog.libs: New file for branch. + * REVISION: Update. + + Clone branch diff --git a/gcc/REVISION b/gcc/REVISION index beb15f6a2b1f..e2b35f36a93c 100644 --- a/gcc/REVISION +++ b/gcc/REVISION @@ -1 +1 @@ -work208 branch +work208-libs branch
[gcc] Created branch 'meissner/heads/work208-sha' in namespace 'refs/users'
The branch 'meissner/heads/work208-sha' was created in namespace 'refs/users' pointing to: f8ea91c0f305... Add ChangeLog.meissner and REVISION.
[gcc(refs/users/meissner/heads/work208-sha)] Add ChangeLog.sha and update REVISION.
https://gcc.gnu.org/g:cf32f67d9b8cbb85b1f982728535adc6c4df1cfa commit cf32f67d9b8cbb85b1f982728535adc6c4df1cfa Author: Michael Meissner Date: Thu May 29 16:07:53 2025 -0400 Add ChangeLog.sha and update REVISION. 2025-05-29 Michael Meissner gcc/ * ChangeLog.sha: New file for branch. * REVISION: Update. Diff: --- gcc/ChangeLog.sha | 14 ++ gcc/REVISION | 2 +- 2 files changed, 15 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog.sha b/gcc/ChangeLog.sha new file mode 100644 index ..08ac7740cb72 --- /dev/null +++ b/gcc/ChangeLog.sha @@ -0,0 +1,14 @@ + Branch work208-sha, baseline + +2025-05-29 Michael Meissner + +Add ChangeLog.sha and update REVISION. + +2025-05-29 Michael Meissner + +gcc/ + + * ChangeLog.sha: New file for branch. + * REVISION: Update. + + Clone branch diff --git a/gcc/REVISION b/gcc/REVISION index beb15f6a2b1f..fa2a7913128c 100644 --- a/gcc/REVISION +++ b/gcc/REVISION @@ -1 +1 @@ -work208 branch +work208-sha branch
[gcc] Created branch 'meissner/heads/work208-test' in namespace 'refs/users'
The branch 'meissner/heads/work208-test' was created in namespace 'refs/users' pointing to: f8ea91c0f305... Add ChangeLog.meissner and REVISION.
[gcc(refs/users/meissner/heads/work208-test)] Add ChangeLog.test and update REVISION.
https://gcc.gnu.org/g:bc73c8029103159c4a8c066da528114ebd95db9c commit bc73c8029103159c4a8c066da528114ebd95db9c Author: Michael Meissner Date: Thu May 29 16:09:03 2025 -0400 Add ChangeLog.test and update REVISION. 2025-05-29 Michael Meissner gcc/ * ChangeLog.test: New file for branch. * REVISION: Update. Diff: --- gcc/ChangeLog.test | 14 ++ gcc/REVISION | 2 +- 2 files changed, 15 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog.test b/gcc/ChangeLog.test new file mode 100644 index ..9ade1d252243 --- /dev/null +++ b/gcc/ChangeLog.test @@ -0,0 +1,14 @@ + Branch work208-test, baseline + +2025-05-29 Michael Meissner + +Add ChangeLog.test and update REVISION. + +2025-05-29 Michael Meissner + +gcc/ + + * ChangeLog.test: New file for branch. + * REVISION: Update. + + Clone branch diff --git a/gcc/REVISION b/gcc/REVISION index beb15f6a2b1f..38f91725f9bf 100644 --- a/gcc/REVISION +++ b/gcc/REVISION @@ -1 +1 @@ -work208 branch +work208-test branch
[gcc] Created branch 'meissner/heads/work209' in namespace 'refs/users'
The branch 'meissner/heads/work209' was created in namespace 'refs/users' pointing to: 977fadd69776... c++, coroutines: Make a check more specific [PR109283].
[gcc r16-962] c++, coroutines: Delete now unused code for parm guards.
https://gcc.gnu.org/g:7bba8d48ea556a03bdc4e9076740b83d3db6599e commit r16-962-g7bba8d48ea556a03bdc4e9076740b83d3db6599e Author: Iain Sandoe Date: Sun May 25 12:14:13 2025 +0100 c++, coroutines: Delete now unused code for parm guards. Since r16-775-g18df4a10bc9694 we use nested cleanups to handle parameter copy destructors in the ramp (and pass a list of cleanups required to the actor which will only be invoked if the parameter copies were all correctly built - and therefore does not need to guard destructors either. This deletes the provisions for frame parameter copy destructor guards. gcc/cp/ChangeLog: * coroutines.cc (analyze_fn_parms): No longer create a parameter copy guard var. * coroutines.h (struct param_info): Remove the entry for the parameter copy destructor guard. Signed-off-by: Iain Sandoe Diff: --- gcc/cp/coroutines.cc | 12 +--- gcc/cp/coroutines.h | 1 - 2 files changed, 1 insertion(+), 12 deletions(-) diff --git a/gcc/cp/coroutines.cc b/gcc/cp/coroutines.cc index b1e555cb3365..64a0a344349e 100644 --- a/gcc/cp/coroutines.cc +++ b/gcc/cp/coroutines.cc @@ -4089,17 +4089,7 @@ analyze_fn_parms (tree orig, hash_map *param_uses) } parm.field_id = name; if (TYPE_HAS_NONTRIVIAL_DESTRUCTOR (parm.frame_type)) - { - char *buf = xasprintf ("_Coro_q%u_%s_live", parm_num, -DECL_NAME (arg) ? IDENTIFIER_POINTER (name) -: "__unnamed"); - parm.guard_var - = coro_build_artificial_var (UNKNOWN_LOCATION, get_identifier (buf), -boolean_type_node, orig, -boolean_false_node); - free (buf); - parm.trivial_dtor = false; - } + parm.trivial_dtor = false; else parm.trivial_dtor = true; } diff --git a/gcc/cp/coroutines.h b/gcc/cp/coroutines.h index d13bea0f302b..10698cf2e129 100644 --- a/gcc/cp/coroutines.h +++ b/gcc/cp/coroutines.h @@ -9,7 +9,6 @@ struct param_info vec *body_uses; /* Worklist of uses, void if there are none. */ tree frame_type; /* The type used to represent this parm in the frame. */ tree orig_type;/* The original type of the parm (not as passed). */ - tree guard_var;/* If we need a DTOR on exception, this bool guards it. */ tree fr_copy_dtor; /* If we need a DTOR on exception, this is it. */ bool by_ref; /* Was passed by reference. */ bool pt_ref; /* Was a pointer to object. */
[gcc(refs/users/meissner/heads/work207-submit)] Add ChangeLog.submit and update REVISION.
https://gcc.gnu.org/g:82203a0eb539d7fb6a284862827fdd934eb63e6c commit 82203a0eb539d7fb6a284862827fdd934eb63e6c Author: Michael Meissner Date: Thu May 29 14:45:18 2025 -0400 Add ChangeLog.submit and update REVISION. 2025-05-29 Michael Meissner gcc/ * ChangeLog.submit: New file for branch. * REVISION: Update. Diff: --- gcc/ChangeLog.submit | 5 + gcc/REVISION | 2 +- 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog.submit b/gcc/ChangeLog.submit new file mode 100644 index ..91b4907da1f4 --- /dev/null +++ b/gcc/ChangeLog.submit @@ -0,0 +1,5 @@ + Branch work207-submit, baseline + +2025-05-29 Michael Meissner + + Clone branch diff --git a/gcc/REVISION b/gcc/REVISION index ab6980dca091..599cb8c8bd07 100644 --- a/gcc/REVISION +++ b/gcc/REVISION @@ -1 +1 @@ -work207 branch +work207-submit branch
[gcc/meissner/heads/work207-submit] (3 commits) Merge commit 'refs/users/meissner/heads/work207-submit' of
The branch 'meissner/heads/work207-submit' was updated to point to: 92bae5cd0aae... Merge commit 'refs/users/meissner/heads/work207-submit' of It previously pointed to: 85c51993de9a... Add ChangeLog.submit and update REVISION. Diff: Summary of changes (added commits): --- 92bae5c... Merge commit 'refs/users/meissner/heads/work207-submit' of 82203a0... Add ChangeLog.submit and update REVISION. 183e739... Update ChangeLog.* (*) (*) This commit already exists in another branch. Because the reference `refs/users/meissner/heads/work207-submit' matches your hooks.email-new-commits-only configuration, no separate email is sent for this commit.
[gcc(refs/users/meissner/heads/work207-test)] Merge commit 'refs/users/meissner/heads/work207-test' of git+ssh://gcc.gnu.org/git/gcc into me/work2
https://gcc.gnu.org/g:77f5a1bde001554ef5be72bd2159eb52ca685a18 commit 77f5a1bde001554ef5be72bd2159eb52ca685a18 Merge: 598573b397ba 3859b184132f Author: Michael Meissner Date: Thu May 29 15:00:03 2025 -0400 Merge commit 'refs/users/meissner/heads/work207-test' of git+ssh://gcc.gnu.org/git/gcc into me/work207-test Diff:
[gcc(refs/users/meissner/heads/work207-test)] Add ChangeLog.test and update REVISION.
https://gcc.gnu.org/g:598573b397ba08adaa6d86534f8ebae47b862a23 commit 598573b397ba08adaa6d86534f8ebae47b862a23 Author: Michael Meissner Date: Thu May 29 14:43:58 2025 -0400 Add ChangeLog.test and update REVISION. 2025-05-29 Michael Meissner gcc/ * ChangeLog.test: New file for branch. * REVISION: Update. Diff: --- gcc/ChangeLog.test | 5 + gcc/REVISION | 2 +- 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog.test b/gcc/ChangeLog.test new file mode 100644 index ..a68131e7ff6b --- /dev/null +++ b/gcc/ChangeLog.test @@ -0,0 +1,5 @@ + Branch work207-test, baseline + +2025-05-29 Michael Meissner + + Clone branch diff --git a/gcc/REVISION b/gcc/REVISION index ab6980dca091..85b69af43eee 100644 --- a/gcc/REVISION +++ b/gcc/REVISION @@ -1 +1 @@ -work207 branch +work207-test branch
[gcc(refs/users/meissner/heads/work207-submit)] Update ChangeLog.*
https://gcc.gnu.org/g:b40ea92b39c8c1abb99b35d89496992cad1b26c8 commit b40ea92b39c8c1abb99b35d89496992cad1b26c8 Author: Michael Meissner Date: Thu May 29 15:05:55 2025 -0400 Update ChangeLog.* Diff: --- gcc/ChangeLog.submit | 9 + 1 file changed, 9 insertions(+) diff --git a/gcc/ChangeLog.submit b/gcc/ChangeLog.submit index 91b4907da1f4..b511dbddc44e 100644 --- a/gcc/ChangeLog.submit +++ b/gcc/ChangeLog.submit @@ -1,5 +1,14 @@ Branch work207-submit, baseline +Add ChangeLog.submit and update REVISION. + +2025-05-29 Michael Meissner + +gcc/ + + * ChangeLog.submit: New file for branch. + * REVISION: Update. + 2025-05-29 Michael Meissner Clone branch
[gcc(refs/users/meissner/heads/work207-submit)] Merge commit 'refs/users/meissner/heads/work207-submit' of git+ssh://gcc.gnu.org/git/gcc into me/wor
https://gcc.gnu.org/g:92bae5cd0aaeb1639380d33a902c0cb3142f9998 commit 92bae5cd0aaeb1639380d33a902c0cb3142f9998 Merge: 82203a0eb539 85c51993de9a Author: Michael Meissner Date: Thu May 29 15:04:10 2025 -0400 Merge commit 'refs/users/meissner/heads/work207-submit' of git+ssh://gcc.gnu.org/git/gcc into me/work207-submit Diff:
[gcc/meissner/heads/work207-test] (3 commits) Merge commit 'refs/users/meissner/heads/work207-test' of gi
The branch 'meissner/heads/work207-test' was updated to point to: 77f5a1bde001... Merge commit 'refs/users/meissner/heads/work207-test' of gi It previously pointed to: 3859b184132f... Add ChangeLog.test and update REVISION. Diff: Summary of changes (added commits): --- 77f5a1b... Merge commit 'refs/users/meissner/heads/work207-test' of gi 598573b... Add ChangeLog.test and update REVISION. 183e739... Update ChangeLog.* (*) (*) This commit already exists in another branch. Because the reference `refs/users/meissner/heads/work207-test' matches your hooks.email-new-commits-only configuration, no separate email is sent for this commit.
[gcc r13-9726] [LRA]: Backporting solutions for PR112918 and PR113354 to solve PR99015
https://gcc.gnu.org/g:af73c8bf5168848275bf909ee44fbb8f4973438f commit r13-9726-gaf73c8bf5168848275bf909ee44fbb8f4973438f Author: Vladimir N. Makarov Date: Thu May 29 15:26:30 2025 -0400 [LRA]: Backporting solutions for PR112918 and PR113354 to solve PR99015 Patches for PR112918 and PR11354 depend on each other and can not be clearly applied to gcc-13 branch. So patches were modified and combined. gcc/ChangeLog: PR rtl-optimization/99015 * lra-constraints.cc (enough_allocatable_hard_regs_p): Extract from in_class_p. (in_class_p): Use it with added conditions. (process_alt_operands): Try to change class too. (curr_insn_transform): Pass true to in_class_p for reg operand win. Spill pseudo only used in the insn if the corresponding operand does not require hard register anymore. Diff: --- gcc/lra-constraints.cc | 124 ++--- 1 file changed, 75 insertions(+), 49 deletions(-) diff --git a/gcc/lra-constraints.cc b/gcc/lra-constraints.cc index 21f05df0d618..2d31fcc9b4f2 100644 --- a/gcc/lra-constraints.cc +++ b/gcc/lra-constraints.cc @@ -233,6 +233,41 @@ get_reg_class (int regno) return NO_REGS; } +/* Return true if REG_CLASS has enough allocatable hard regs to keep value of + REG_MODE. */ +static bool +enough_allocatable_hard_regs_p (enum reg_class reg_class, + enum machine_mode reg_mode) +{ + int i, j, hard_regno, class_size, nregs; + + if (hard_reg_set_subset_p (reg_class_contents[reg_class], lra_no_alloc_regs)) +return false; + class_size = ira_class_hard_regs_num[reg_class]; + for (i = 0; i < class_size; i++) +{ + hard_regno = ira_class_hard_regs[reg_class][i]; + nregs = hard_regno_nregs (hard_regno, reg_mode); + if (nregs == 1) + return true; + for (j = 0; j < nregs; j++) + if (TEST_HARD_REG_BIT (lra_no_alloc_regs, hard_regno + j) + || ! TEST_HARD_REG_BIT (reg_class_contents[reg_class], + hard_regno + j)) + break; + if (j >= nregs) + return true; +} + return false; +} + +/* True if C is a non-empty register class that has too few registers + to be safely used as a reload target class. */ +#define SMALL_REGISTER_CLASS_P(C) \ + (ira_class_hard_regs_num [(C)] == 1 \ + || (ira_class_hard_regs_num [(C)] >= 1 \ + && targetm.class_likely_spilled_p (C))) + /* Return true if REG satisfies (or will satisfy) reg class constraint CL. Use elimination first if REG is a hard register. If REG is a reload pseudo created by this constraints pass, assume that it will @@ -252,7 +287,6 @@ in_class_p (rtx reg, enum reg_class cl, enum reg_class *new_class, enum reg_class rclass, common_class; machine_mode reg_mode; rtx src; - int class_size, hard_regno, nregs, i, j; int regno = REGNO (reg); if (new_class != NULL) @@ -291,26 +325,11 @@ in_class_p (rtx reg, enum reg_class cl, enum reg_class *new_class, common_class = ira_reg_class_subset[rclass][cl]; if (new_class != NULL) *new_class = common_class; - if (hard_reg_set_subset_p (reg_class_contents[common_class], -lra_no_alloc_regs)) - return false; - /* Check that there are enough allocatable regs. */ - class_size = ira_class_hard_regs_num[common_class]; - for (i = 0; i < class_size; i++) - { - hard_regno = ira_class_hard_regs[common_class][i]; - nregs = hard_regno_nregs (hard_regno, reg_mode); - if (nregs == 1) - return true; - for (j = 0; j < nregs; j++) - if (TEST_HARD_REG_BIT (lra_no_alloc_regs, hard_regno + j) - || ! TEST_HARD_REG_BIT (reg_class_contents[common_class], - hard_regno + j)) - break; - if (j >= nregs) - return true; - } - return false; + return (enough_allocatable_hard_regs_p (common_class, reg_mode) + /* Do not permit reload insn operand matching (new_class == NULL +case) if the new class is too small. */ + && (new_class != NULL || common_class == rclass + || !SMALL_REGISTER_CLASS_P (common_class))); } } @@ -914,13 +933,6 @@ operands_match_p (rtx x, rtx y, int y_hard_regno) && GET_MODE_SIZE (MODE).is_constant () \ && !targetm.cannot_force_const_mem (MODE, X)) -/* True if C is a non-empty register class that has too few registers - to be safely used as a reload target class. */ -#define SMALL_REGISTER_CLASS_P(C) \ - (ira_class_hard_regs_num [(C)] == 1 \ - || (ira_class_hard_regs_num [(C)] >= 1 \ - && targetm.class_likely_spilled_p (C))) - /* If REG is a reload pseudo, try to make its class satisfying CL. */ static void
[gcc r16-954] libstdc++: Re-enable some XPASS tests for AIX
https://gcc.gnu.org/g:ff6647b41d4ed21490c0fad237ff6e6705902c4b commit r16-954-gff6647b41d4ed21490c0fad237ff6e6705902c4b Author: Jonathan Wakely Date: Wed May 28 23:04:42 2025 +0100 libstdc++: Re-enable some XPASS tests for AIX The deque shrink_to_fit.cc test always passes on AIX, I think it should not have been disabled. The 96088.cc tests pass for C++20 and later (I don't know why) so make them require C++20, as they fail otherwise. libstdc++-v3/ChangeLog: * testsuite/23_containers/deque/capacity/shrink_to_fit.cc: Remove dg-xfail-run-if for AIX. * testsuite/23_containers/unordered_map/96088.cc: Replace dg-xfail-run-if with dg-require-effective-target c++20. * testsuite/23_containers/unordered_multimap/96088.cc: Likewise. * testsuite/23_containers/unordered_multiset/96088.cc: Likewise. * testsuite/23_containers/unordered_set/96088.cc: Likewise. Diff: --- libstdc++-v3/testsuite/23_containers/deque/capacity/shrink_to_fit.cc | 1 - libstdc++-v3/testsuite/23_containers/unordered_map/96088.cc | 2 +- libstdc++-v3/testsuite/23_containers/unordered_multimap/96088.cc | 2 +- libstdc++-v3/testsuite/23_containers/unordered_multiset/96088.cc | 2 +- libstdc++-v3/testsuite/23_containers/unordered_set/96088.cc | 2 +- 5 files changed, 4 insertions(+), 5 deletions(-) diff --git a/libstdc++-v3/testsuite/23_containers/deque/capacity/shrink_to_fit.cc b/libstdc++-v3/testsuite/23_containers/deque/capacity/shrink_to_fit.cc index 4dbf405d57b8..63717554280c 100644 --- a/libstdc++-v3/testsuite/23_containers/deque/capacity/shrink_to_fit.cc +++ b/libstdc++-v3/testsuite/23_containers/deque/capacity/shrink_to_fit.cc @@ -1,6 +1,5 @@ // { dg-do run { target c++11 } } // { dg-require-effective-target std_allocator_new } -// { dg-xfail-run-if "AIX operator new" { powerpc-ibm-aix* } } // 2010-01-08 Paolo Carlini diff --git a/libstdc++-v3/testsuite/23_containers/unordered_map/96088.cc b/libstdc++-v3/testsuite/23_containers/unordered_map/96088.cc index c7dfd4fe1c60..0ec0bba2bba6 100644 --- a/libstdc++-v3/testsuite/23_containers/unordered_map/96088.cc +++ b/libstdc++-v3/testsuite/23_containers/unordered_map/96088.cc @@ -1,6 +1,6 @@ // { dg-do run { target c++17 } } // { dg-require-effective-target std_allocator_new } -// { dg-xfail-run-if "AIX operator new" { powerpc-ibm-aix* } } +// { dg-require-effective-target c++20 { target powerpc-ibm-aix* } } // Copyright (C) 2021-2025 Free Software Foundation, Inc. // diff --git a/libstdc++-v3/testsuite/23_containers/unordered_multimap/96088.cc b/libstdc++-v3/testsuite/23_containers/unordered_multimap/96088.cc index 6f9429610775..3c1de3761e65 100644 --- a/libstdc++-v3/testsuite/23_containers/unordered_multimap/96088.cc +++ b/libstdc++-v3/testsuite/23_containers/unordered_multimap/96088.cc @@ -1,6 +1,6 @@ // { dg-do run { target c++17 } } // { dg-require-effective-target std_allocator_new } -// { dg-xfail-run-if "AIX operator new" { powerpc-ibm-aix* } } +// { dg-require-effective-target c++20 { target powerpc-ibm-aix* } } // Copyright (C) 2021-2025 Free Software Foundation, Inc. // diff --git a/libstdc++-v3/testsuite/23_containers/unordered_multiset/96088.cc b/libstdc++-v3/testsuite/23_containers/unordered_multiset/96088.cc index 6f79ddf4c152..c016c88c1955 100644 --- a/libstdc++-v3/testsuite/23_containers/unordered_multiset/96088.cc +++ b/libstdc++-v3/testsuite/23_containers/unordered_multiset/96088.cc @@ -1,6 +1,6 @@ // { dg-do run { target c++17 } } // { dg-require-effective-target std_allocator_new } -// { dg-xfail-run-if "AIX operator new" { powerpc-ibm-aix* } } +// { dg-require-effective-target c++20 { target powerpc-ibm-aix* } } // Copyright (C) 2021-2025 Free Software Foundation, Inc. // diff --git a/libstdc++-v3/testsuite/23_containers/unordered_set/96088.cc b/libstdc++-v3/testsuite/23_containers/unordered_set/96088.cc index c09e6f747ef0..10838c4d24f8 100644 --- a/libstdc++-v3/testsuite/23_containers/unordered_set/96088.cc +++ b/libstdc++-v3/testsuite/23_containers/unordered_set/96088.cc @@ -1,6 +1,6 @@ // { dg-do run { target c++17 } } // { dg-require-effective-target std_allocator_new } -// { dg-xfail-run-if "AIX operator new" { powerpc-ibm-aix* } } +// { dg-require-effective-target c++20 { target powerpc-ibm-aix* } } // Copyright (C) 2021-2025 Free Software Foundation, Inc. //
[gcc] Created branch 'meissner/heads/work209-orig' in namespace 'refs/users'
The branch 'meissner/heads/work209-orig' was created in namespace 'refs/users' pointing to: 977fadd69776... c++, coroutines: Make a check more specific [PR109283].
[gcc(refs/users/meissner/heads/work209)] Add ChangeLog.meissner and REVISION.
https://gcc.gnu.org/g:c7052d7c1b58b3b8609713e9552794cba264f763 commit c7052d7c1b58b3b8609713e9552794cba264f763 Author: Michael Meissner Date: Thu May 29 16:15:38 2025 -0400 Add ChangeLog.meissner and REVISION. 2025-05-29 Michael Meissner gcc/ * REVISION: New file for branch. * ChangeLog.meissner: New file. gcc/c-family/ * ChangeLog.meissner: New file. gcc/c/ * ChangeLog.meissner: New file. gcc/cp/ * ChangeLog.meissner: New file. gcc/fortran/ * ChangeLog.meissner: New file. gcc/testsuite/ * ChangeLog.meissner: New file. libgcc/ * ChangeLog.meissner: New file. Diff: --- gcc/ChangeLog.meissner | 38 ++ gcc/REVISION | 1 + gcc/c-family/ChangeLog.meissner | 38 ++ gcc/c/ChangeLog.meissner | 38 ++ gcc/cp/ChangeLog.meissner| 38 ++ gcc/fortran/ChangeLog.meissner | 38 ++ gcc/testsuite/ChangeLog.meissner | 38 ++ libgcc/ChangeLog.meissner| 38 ++ libstdc++-v3/ChangeLog.meissner | 38 ++ 9 files changed, 305 insertions(+) diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner new file mode 100644 index ..b9c881a50082 --- /dev/null +++ b/gcc/ChangeLog.meissner @@ -0,0 +1,38 @@ + Branch work209, baseline + +2025-05-29 Michael Meissner + +Add ChangeLog.meissner and REVISION. + +2025-05-29 Michael Meissner + +gcc/ + + * REVISION: New file for branch. + * ChangeLog.meissner: New file. + +gcc/c-family/ + + * ChangeLog.meissner: New file. + +gcc/c/ + + * ChangeLog.meissner: New file. + +gcc/cp/ + + * ChangeLog.meissner: New file. + +gcc/fortran/ + + * ChangeLog.meissner: New file. + +gcc/testsuite/ + + * ChangeLog.meissner: New file. + +libgcc/ + + * ChangeLog.meissner: New file. + + Clone branch diff --git a/gcc/REVISION b/gcc/REVISION new file mode 100644 index ..68db0559d92a --- /dev/null +++ b/gcc/REVISION @@ -0,0 +1 @@ +work209 branch diff --git a/gcc/c-family/ChangeLog.meissner b/gcc/c-family/ChangeLog.meissner new file mode 100644 index ..b9c881a50082 --- /dev/null +++ b/gcc/c-family/ChangeLog.meissner @@ -0,0 +1,38 @@ + Branch work209, baseline + +2025-05-29 Michael Meissner + +Add ChangeLog.meissner and REVISION. + +2025-05-29 Michael Meissner + +gcc/ + + * REVISION: New file for branch. + * ChangeLog.meissner: New file. + +gcc/c-family/ + + * ChangeLog.meissner: New file. + +gcc/c/ + + * ChangeLog.meissner: New file. + +gcc/cp/ + + * ChangeLog.meissner: New file. + +gcc/fortran/ + + * ChangeLog.meissner: New file. + +gcc/testsuite/ + + * ChangeLog.meissner: New file. + +libgcc/ + + * ChangeLog.meissner: New file. + + Clone branch diff --git a/gcc/c/ChangeLog.meissner b/gcc/c/ChangeLog.meissner new file mode 100644 index ..b9c881a50082 --- /dev/null +++ b/gcc/c/ChangeLog.meissner @@ -0,0 +1,38 @@ + Branch work209, baseline + +2025-05-29 Michael Meissner + +Add ChangeLog.meissner and REVISION. + +2025-05-29 Michael Meissner + +gcc/ + + * REVISION: New file for branch. + * ChangeLog.meissner: New file. + +gcc/c-family/ + + * ChangeLog.meissner: New file. + +gcc/c/ + + * ChangeLog.meissner: New file. + +gcc/cp/ + + * ChangeLog.meissner: New file. + +gcc/fortran/ + + * ChangeLog.meissner: New file. + +gcc/testsuite/ + + * ChangeLog.meissner: New file. + +libgcc/ + + * ChangeLog.meissner: New file. + + Clone branch diff --git a/gcc/cp/ChangeLog.meissner b/gcc/cp/ChangeLog.meissner new file mode 100644 index ..b9c881a50082 --- /dev/null +++ b/gcc/cp/ChangeLog.meissner @@ -0,0 +1,38 @@ + Branch work209, baseline + +2025-05-29 Michael Meissner + +Add ChangeLog.meissner and REVISION. + +2025-05-29 Michael Meissner + +gcc/ + + * REVISION: New file for branch. + * ChangeLog.meissner: New file. + +gcc/c-family/ + + * ChangeLog.meissner: New file. + +gcc/c/ + + * ChangeLog.meissner: New file. + +gcc/cp/ + + * ChangeLog.meissner: New file. + +gcc/fortran/ + + * ChangeLog.meissner: New file. + +gcc/testsuite/ + + * ChangeLog.meissner: New file. + +libgcc/ + + * ChangeLog.meissner: New file. + + Clone branch diff --git a/gcc/fortran/ChangeLog.meissner b/gcc/fortran/ChangeLog.meissner new file mode 100644 inde
[gcc(refs/users/meissner/heads/work209-bugs)] Add ChangeLog.bugs and update REVISION.
https://gcc.gnu.org/g:7bc94cdaf8556ad501af4bf32a9ac4113406 commit 7bc94cdaf8556ad501af4bf32a9ac4113406 Author: Michael Meissner Date: Thu May 29 16:17:54 2025 -0400 Add ChangeLog.bugs and update REVISION. 2025-05-29 Michael Meissner gcc/ * ChangeLog.bugs: New file for branch. * REVISION: Update. Diff: --- gcc/ChangeLog.bugs | 14 ++ gcc/REVISION | 2 +- 2 files changed, 15 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog.bugs b/gcc/ChangeLog.bugs new file mode 100644 index ..05aef9150723 --- /dev/null +++ b/gcc/ChangeLog.bugs @@ -0,0 +1,14 @@ + Branch work209-bugs, baseline + +2025-05-29 Michael Meissner + +Add ChangeLog.bugs and update REVISION. + +2025-05-29 Michael Meissner + +gcc/ + + * ChangeLog.bugs: New file for branch. + * REVISION: Update. + + Clone branch diff --git a/gcc/REVISION b/gcc/REVISION index 68db0559d92a..cfb3244d3d24 100644 --- a/gcc/REVISION +++ b/gcc/REVISION @@ -1 +1 @@ -work209 branch +work209-bugs branch
[gcc] Created branch 'meissner/heads/work209-cmodel' in namespace 'refs/users'
The branch 'meissner/heads/work209-cmodel' was created in namespace 'refs/users' pointing to: c7052d7c1b58... Add ChangeLog.meissner and REVISION.
[gcc(refs/users/meissner/heads/work209-cmodel)] Add ChangeLog.cmodel and update REVISION.
https://gcc.gnu.org/g:38a4d49fccf762a9ce2630b844c23b2e7590ae56 commit 38a4d49fccf762a9ce2630b844c23b2e7590ae56 Author: Michael Meissner Date: Thu May 29 16:19:00 2025 -0400 Add ChangeLog.cmodel and update REVISION. 2025-05-29 Michael Meissner gcc/ * ChangeLog.cmodel: New file for branch. * REVISION: Update. Diff: --- gcc/ChangeLog.cmodel | 14 ++ gcc/REVISION | 2 +- 2 files changed, 15 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog.cmodel b/gcc/ChangeLog.cmodel new file mode 100644 index ..4514ef703d49 --- /dev/null +++ b/gcc/ChangeLog.cmodel @@ -0,0 +1,14 @@ + Branch work209-cmodel, baseline + +2025-05-29 Michael Meissner + +Add ChangeLog.cmodel and update REVISION. + +2025-05-29 Michael Meissner + +gcc/ + + * ChangeLog.cmodel: New file for branch. + * REVISION: Update. + + Clone branch diff --git a/gcc/REVISION b/gcc/REVISION index 68db0559d92a..497e1c367a91 100644 --- a/gcc/REVISION +++ b/gcc/REVISION @@ -1 +1 @@ -work209 branch +work209-cmodel branch
[gcc r16-970] c++: xobj lambda 'this' capture [PR113563]
https://gcc.gnu.org/g:2047aa4ce2ed9976fb36e984b43864fcd6f3a65d commit r16-970-g2047aa4ce2ed9976fb36e984b43864fcd6f3a65d Author: Jason Merrill Date: Thu May 29 12:36:23 2025 -0400 c++: xobj lambda 'this' capture [PR113563] Various places were still making assumptions that we could get to the 'this' capture through current_class_ref in a lambda op(), which is incorrect for an explicit object op(). PR c++/113563 gcc/cp/ChangeLog: * lambda.cc (build_capture_proxy): Check pointerness of the member, not the proxy type. (lambda_expr_this_capture): Don't assume current_class_ref. (nonlambda_method_basetype): Likewise. * semantics.cc (finish_non_static_data_member): Don't assume TREE_TYPE (object) is set. (finish_this_expr): Check current_class_type for lambda, not current_class_ref. gcc/testsuite/ChangeLog: * g++.dg/cpp23/explicit-obj-lambda16.C: New test. Diff: --- gcc/cp/lambda.cc | 12 +++ gcc/cp/semantics.cc| 17 -- gcc/testsuite/g++.dg/cpp23/explicit-obj-lambda16.C | 39 ++ 3 files changed, 50 insertions(+), 18 deletions(-) diff --git a/gcc/cp/lambda.cc b/gcc/cp/lambda.cc index a2bed9fb36aa..34c7defb6049 100644 --- a/gcc/cp/lambda.cc +++ b/gcc/cp/lambda.cc @@ -442,7 +442,7 @@ build_capture_proxy (tree member, tree init) type = lambda_proxy_type (object); - if (name == this_identifier && !INDIRECT_TYPE_P (type)) + if (name == this_identifier && !INDIRECT_TYPE_P (TREE_TYPE (member))) { type = build_pointer_type (type); type = cp_build_qualified_type (type, TYPE_QUAL_CONST); @@ -921,8 +921,9 @@ lambda_expr_this_capture (tree lambda, int add_capture_p) else { /* To make sure that current_class_ref is for the lambda. */ - gcc_assert (TYPE_MAIN_VARIANT (TREE_TYPE (current_class_ref)) - == LAMBDA_EXPR_CLOSURE (lambda)); + gcc_assert (!current_class_ref + || (TYPE_MAIN_VARIANT (TREE_TYPE (current_class_ref)) + == LAMBDA_EXPR_CLOSURE (lambda))); result = this_capture; @@ -1037,12 +1038,9 @@ current_nonlambda_function (void) tree nonlambda_method_basetype (void) { - if (!current_class_ref) -return NULL_TREE; - tree type = current_class_type; if (!type || !LAMBDA_TYPE_P (type)) -return type; +return current_class_ref ? type : NULL_TREE; while (true) { diff --git a/gcc/cp/semantics.cc b/gcc/cp/semantics.cc index 241f2730878b..1279d78b1868 100644 --- a/gcc/cp/semantics.cc +++ b/gcc/cp/semantics.cc @@ -2770,7 +2770,7 @@ finish_non_static_data_member (tree decl, tree object, tree qualifying_scope, else if (PACK_EXPANSION_P (type)) /* Don't bother trying to represent this. */ type = NULL_TREE; - else if (WILDCARD_TYPE_P (TREE_TYPE (object))) + else if (!TREE_TYPE (object) || WILDCARD_TYPE_P (TREE_TYPE (object))) /* We don't know what the eventual quals will be, so punt until instantiation time. @@ -3605,16 +3605,11 @@ finish_this_expr (void) { tree result = NULL_TREE; - if (current_class_ptr) -{ - tree type = TREE_TYPE (current_class_ref); - - /* In a lambda expression, 'this' refers to the captured 'this'. */ - if (LAMBDA_TYPE_P (type)) -result = lambda_expr_this_capture (CLASSTYPE_LAMBDA_EXPR (type), true); - else -result = current_class_ptr; -} + if (current_class_type && LAMBDA_TYPE_P (current_class_type)) +result = (lambda_expr_this_capture + (CLASSTYPE_LAMBDA_EXPR (current_class_type), /*add*/true)); + else if (current_class_ptr) +result = current_class_ptr; if (result) /* The keyword 'this' is a prvalue expression. */ diff --git a/gcc/testsuite/g++.dg/cpp23/explicit-obj-lambda16.C b/gcc/testsuite/g++.dg/cpp23/explicit-obj-lambda16.C new file mode 100644 index ..69936388969c --- /dev/null +++ b/gcc/testsuite/g++.dg/cpp23/explicit-obj-lambda16.C @@ -0,0 +1,39 @@ +// PR c++/113563 +// { dg-do compile { target c++23 } } + +struct S { + int x_; + void f() { +[this](this auto) { + this->x_ = 42; + return this; +}(); + } +}; + +struct R { + int x; + + auto foo() { +return [*this](this auto &self) { + this->x = 4; +}; + } +}; + + +struct A +{ +int n; +void fun() +{ +auto _ = [&](this auto self) { return n; }; +} +}; + +struct B { + int i = 42; + int foo() { +return [this](this auto &&self) { auto p = &i; return *p; }(); + } +};
[gcc] Created branch 'meissner/heads/work209-libs' in namespace 'refs/users'
The branch 'meissner/heads/work209-libs' was created in namespace 'refs/users' pointing to: c7052d7c1b58... Add ChangeLog.meissner and REVISION.
[gcc(refs/users/meissner/heads/work209-orig)] Add REVISION.
https://gcc.gnu.org/g:5b373dd8e354381b1d48505cf4caa827654fb19c commit 5b373dd8e354381b1d48505cf4caa827654fb19c Author: Michael Meissner Date: Thu May 29 16:16:46 2025 -0400 Add REVISION. 2025-05-29 Michael Meissner gcc/ * REVISION: New file for branch. Diff: --- gcc/REVISION | 1 + 1 file changed, 1 insertion(+) diff --git a/gcc/REVISION b/gcc/REVISION new file mode 100644 index ..7a02cf78e562 --- /dev/null +++ b/gcc/REVISION @@ -0,0 +1 @@ +work209-orig branch
[gcc] Created branch 'meissner/heads/work209-bugs' in namespace 'refs/users'
The branch 'meissner/heads/work209-bugs' was created in namespace 'refs/users' pointing to: c7052d7c1b58... Add ChangeLog.meissner and REVISION.
[gcc(refs/users/meissner/heads/work209-dmf)] Add ChangeLog.dmf and update REVISION.
https://gcc.gnu.org/g:58acf4d19a0c9b2e0e814948660dd64c51423f76 commit 58acf4d19a0c9b2e0e814948660dd64c51423f76 Author: Michael Meissner Date: Thu May 29 16:20:11 2025 -0400 Add ChangeLog.dmf and update REVISION. 2025-05-29 Michael Meissner gcc/ * ChangeLog.dmf: New file for branch. * REVISION: Update. Diff: --- gcc/ChangeLog.dmf | 14 ++ gcc/REVISION | 2 +- 2 files changed, 15 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog.dmf b/gcc/ChangeLog.dmf new file mode 100644 index ..cac7ef35909b --- /dev/null +++ b/gcc/ChangeLog.dmf @@ -0,0 +1,14 @@ + Branch work209-dmf, baseline + +2025-05-29 Michael Meissner + +Add ChangeLog.dmf and update REVISION. + +2025-05-29 Michael Meissner + +gcc/ + + * ChangeLog.dmf: New file for branch. + * REVISION: Update. + + Clone branch diff --git a/gcc/REVISION b/gcc/REVISION index 68db0559d92a..1e4d6f097c1c 100644 --- a/gcc/REVISION +++ b/gcc/REVISION @@ -1 +1 @@ -work209 branch +work209-dmf branch
[gcc] Created branch 'meissner/heads/work209-dmf' in namespace 'refs/users'
The branch 'meissner/heads/work209-dmf' was created in namespace 'refs/users' pointing to: c7052d7c1b58... Add ChangeLog.meissner and REVISION.
[gcc(refs/users/meissner/heads/work209-sha)] Add ChangeLog.sha and update REVISION.
https://gcc.gnu.org/g:8e9eb1f374555b486b7eeb5e885ce332a524fdbe commit 8e9eb1f374555b486b7eeb5e885ce332a524fdbe Author: Michael Meissner Date: Thu May 29 16:22:26 2025 -0400 Add ChangeLog.sha and update REVISION. 2025-05-29 Michael Meissner gcc/ * ChangeLog.sha: New file for branch. * REVISION: Update. Diff: --- gcc/ChangeLog.sha | 14 ++ gcc/REVISION | 2 +- 2 files changed, 15 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog.sha b/gcc/ChangeLog.sha new file mode 100644 index ..e90915406965 --- /dev/null +++ b/gcc/ChangeLog.sha @@ -0,0 +1,14 @@ + Branch work209-sha, baseline + +2025-05-29 Michael Meissner + +Add ChangeLog.sha and update REVISION. + +2025-05-29 Michael Meissner + +gcc/ + + * ChangeLog.sha: New file for branch. + * REVISION: Update. + + Clone branch diff --git a/gcc/REVISION b/gcc/REVISION index 68db0559d92a..8ef73b21c770 100644 --- a/gcc/REVISION +++ b/gcc/REVISION @@ -1 +1 @@ -work209 branch +work209-sha branch
[gcc] Created branch 'meissner/heads/work209-test' in namespace 'refs/users'
The branch 'meissner/heads/work209-test' was created in namespace 'refs/users' pointing to: c7052d7c1b58... Add ChangeLog.meissner and REVISION.
[gcc] Created branch 'meissner/heads/work209-sha' in namespace 'refs/users'
The branch 'meissner/heads/work209-sha' was created in namespace 'refs/users' pointing to: c7052d7c1b58... Add ChangeLog.meissner and REVISION.
[gcc(refs/users/meissner/heads/work209-test)] Add ChangeLog.test and update REVISION.
https://gcc.gnu.org/g:edd09c824f823304679d4d9be1ef8caa14ccacb2 commit edd09c824f823304679d4d9be1ef8caa14ccacb2 Author: Michael Meissner Date: Thu May 29 16:23:41 2025 -0400 Add ChangeLog.test and update REVISION. 2025-05-29 Michael Meissner gcc/ * ChangeLog.test: New file for branch. * REVISION: Update. Diff: --- gcc/ChangeLog.test | 14 ++ gcc/REVISION | 2 +- 2 files changed, 15 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog.test b/gcc/ChangeLog.test new file mode 100644 index ..7bbf30c470d7 --- /dev/null +++ b/gcc/ChangeLog.test @@ -0,0 +1,14 @@ + Branch work209-test, baseline + +2025-05-29 Michael Meissner + +Add ChangeLog.test and update REVISION. + +2025-05-29 Michael Meissner + +gcc/ + + * ChangeLog.test: New file for branch. + * REVISION: Update. + + Clone branch diff --git a/gcc/REVISION b/gcc/REVISION index 68db0559d92a..77d38babf16b 100644 --- a/gcc/REVISION +++ b/gcc/REVISION @@ -1 +1 @@ -work209 branch +work209-test branch
[gcc(refs/users/meissner/heads/work209-libs)] Add ChangeLog.libs and update REVISION.
https://gcc.gnu.org/g:cdabfdf8e57cbd922459aef5e957a3a501b3c7b0 commit cdabfdf8e57cbd922459aef5e957a3a501b3c7b0 Author: Michael Meissner Date: Thu May 29 16:21:18 2025 -0400 Add ChangeLog.libs and update REVISION. 2025-05-29 Michael Meissner gcc/ * ChangeLog.libs: New file for branch. * REVISION: Update. Diff: --- gcc/ChangeLog.libs | 14 ++ gcc/REVISION | 2 +- 2 files changed, 15 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog.libs b/gcc/ChangeLog.libs new file mode 100644 index ..fcddb33ec98c --- /dev/null +++ b/gcc/ChangeLog.libs @@ -0,0 +1,14 @@ + Branch work209-libs, baseline + +2025-05-29 Michael Meissner + +Add ChangeLog.libs and update REVISION. + +2025-05-29 Michael Meissner + +gcc/ + + * ChangeLog.libs: New file for branch. + * REVISION: Update. + + Clone branch diff --git a/gcc/REVISION b/gcc/REVISION index 68db0559d92a..0fbccd69c69a 100644 --- a/gcc/REVISION +++ b/gcc/REVISION @@ -1 +1 @@ -work209 branch +work209-libs branch
[gcc r16-953] i386: Use Shuffles instead of shifts for Reduction in AMD znver4/5
https://gcc.gnu.org/g:5080d98a383de244a7b78ae50456fd41881268c2 commit r16-953-g5080d98a383de244a7b78ae50456fd41881268c2 Author: Pranav Gorantla Date: Thu May 29 15:02:24 2025 +0200 i386: Use Shuffles instead of shifts for Reduction in AMD znver4/5 In AMD znver4, znver5 targets vpshufd, vpsrldq have latencies 1,2 and throughput 4 (2 for znver4),2 respectively. It is better to generate shuffles instead of shifts wherever possible. In this patch we try to generate appropriate shuffle instruction to copy higher half to lower half instead of a simple right shift during horizontal vector reduction. gcc/ChangeLog: * config/i386/i386-expand.cc (emit_reduc_half): Use shuffles to generate reduc half for V4SI, similar modes. * config/i386/i386.h (TARGET_SSE_REDUCTION_PREFER_PSHUF): New Macro. * config/i386/x86-tune.def (X86_TUNE_SSE_REDUCTION_PREFER_PSHUF): New tuning. gcc/testsuite/ChangeLog: * gcc.target/i386/reduc-pshuf.c: New test. Diff: --- gcc/config/i386/i386-expand.cc | 27 +++ gcc/config/i386/i386.h | 4 +++- gcc/config/i386/x86-tune.def| 5 + gcc/testsuite/gcc.target/i386/reduc-pshuf.c | 16 4 files changed, 51 insertions(+), 1 deletion(-) diff --git a/gcc/config/i386/i386-expand.cc b/gcc/config/i386/i386-expand.cc index 7fd03c88630f..181e64a86bf6 100644 --- a/gcc/config/i386/i386-expand.cc +++ b/gcc/config/i386/i386-expand.cc @@ -18724,6 +18724,33 @@ emit_reduc_half (rtx dest, rtx src, int i) case E_V8HFmode: case E_V4SImode: case E_V2DImode: + if (TARGET_SSE_REDUCTION_PREFER_PSHUF) + { + if (i == 128) + { + d = gen_reg_rtx (V4SImode); + tem = gen_sse2_pshufd_1 ( + d, force_reg (V4SImode, gen_lowpart (V4SImode, src)), + GEN_INT (2), GEN_INT (3), GEN_INT (2), GEN_INT (3)); + break; + } + else if (i == 64) + { + d = gen_reg_rtx (V4SImode); + tem = gen_sse2_pshufd_1 ( + d, force_reg (V4SImode, gen_lowpart (V4SImode, src)), + GEN_INT (1), GEN_INT (1), GEN_INT (1), GEN_INT (1)); + break; + } + else if (i == 32) + { + d = gen_reg_rtx (V8HImode); + tem = gen_sse2_pshuflw_1 ( + d, force_reg (V8HImode, gen_lowpart (V8HImode, src)), + GEN_INT (1), GEN_INT (1), GEN_INT (1), GEN_INT (1)); + break; + } + } d = gen_reg_rtx (V1TImode); tem = gen_sse2_lshrv1ti3 (d, gen_lowpart (V1TImode, src), GEN_INT (i / 2)); diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h index ccc62fc3e7ca..d32d9ad997e6 100644 --- a/gcc/config/i386/i386.h +++ b/gcc/config/i386/i386.h @@ -490,7 +490,9 @@ extern unsigned char ix86_tune_features[X86_TUNE_LAST]; #define TARGET_SSE_MOVCC_USE_BLENDV \ ix86_tune_features[X86_TUNE_SSE_MOVCC_USE_BLENDV] #define TARGET_ALIGN_TIGHT_LOOPS \ -ix86_tune_features[X86_TUNE_ALIGN_TIGHT_LOOPS] + ix86_tune_features[X86_TUNE_ALIGN_TIGHT_LOOPS] +#define TARGET_SSE_REDUCTION_PREFER_PSHUF \ + ix86_tune_features[X86_TUNE_SSE_REDUCTION_PREFER_PSHUF] /* Feature tests against the various architecture variations. */ diff --git a/gcc/config/i386/x86-tune.def b/gcc/config/i386/x86-tune.def index e6044c6032e4..91cdca7fbfc2 100644 --- a/gcc/config/i386/x86-tune.def +++ b/gcc/config/i386/x86-tune.def @@ -572,6 +572,11 @@ DEF_TUNE (X86_TUNE_V2DF_REDUCTION_PREFER_HADDPD, DEF_TUNE (X86_TUNE_SSE_MOVCC_USE_BLENDV, "sse_movcc_use_blendv", ~m_CORE_ATOM) +/* X86_TUNE_V4SI_REDUCTION_PREFER_SHUFD: Prefer pshuf to reduce V16QI, + V8HI, V8HI, V4SI, V4FI, V2DI modes when lshr are costlier. */ +DEF_TUNE (X86_TUNE_SSE_REDUCTION_PREFER_PSHUF, + "sse_reduction_prefer_pshuf", m_ZNVER4 | m_ZNVER5) + /*/ /* AVX instruction selection tuning (some of SSE flags affects AVX, too) */ /*/ diff --git a/gcc/testsuite/gcc.target/i386/reduc-pshuf.c b/gcc/testsuite/gcc.target/i386/reduc-pshuf.c new file mode 100644 index ..e46d2bab9c5f --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/reduc-pshuf.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=znver5 " } */ + +#define N 32 +#define T short +T +foo (T *a) +{ + T sum = 0; + for (int i = 0; i < N; i++) +sum += a[i]; + return sum; +} + +/* { dg-final { scan-assembler-times "vpsrl" 0 } } */ +/* { dg-final { scan-assembler-times "vpshuf" 3 } } */
[gcc r16-955] libstdc++: Fix lwg4084.cc test FAIL on AIX
https://gcc.gnu.org/g:a8e22d3fcc079c02bc2bc91d57f5877fb87f52cb commit r16-955-ga8e22d3fcc079c02bc2bc91d57f5877fb87f52cb Author: Jonathan Wakely Date: Wed May 28 22:02:58 2025 +0100 libstdc++: Fix lwg4084.cc test FAIL on AIX On AIX printf formats a quiet NaN as "NaNQ" and it doesn't matter whether %f or %F is used. Similarly, it always prints "INF" for infinity, even when %f is used. Adjust a test that currently fails due to this AIX-specific (and non-conforming) behaviour. libstdc++-v3/ChangeLog: * testsuite/22_locale/num_put/put/char/lwg4084.cc [_AIX]: Adjust expected output for NaN and infinity. Diff: --- libstdc++-v3/testsuite/22_locale/num_put/put/char/lwg4084.cc | 8 1 file changed, 8 insertions(+) diff --git a/libstdc++-v3/testsuite/22_locale/num_put/put/char/lwg4084.cc b/libstdc++-v3/testsuite/22_locale/num_put/put/char/lwg4084.cc index b7c7da11f863..6ce4e8fe9f71 100644 --- a/libstdc++-v3/testsuite/22_locale/num_put/put/char/lwg4084.cc +++ b/libstdc++-v3/testsuite/22_locale/num_put/put/char/lwg4084.cc @@ -20,7 +20,11 @@ test_nan() out << ' ' << nan << ' ' << -nan; out << std::showpos; out << ' ' << nan << ' ' << -nan; +#ifdef _AIX // non-conforming + VERIFY( out.str() == " NaNQ -NaNQ NaNQ -NaNQ NaNQ -NaNQ +NaNQ -NaNQ" ); +#else VERIFY( out.str() == " nan -nan NAN -NAN NAN -NAN +NAN -NAN" ); +#endif } void @@ -36,7 +40,11 @@ test_inf() out << ' ' << inf << ' ' << -inf; out << std::showpos; out << ' ' << inf << ' ' << -inf; +#ifdef _AIX // non-conforming + VERIFY( out.str() == " INF -INF INF -INF INF -INF +INF -INF" ); +#else VERIFY( out.str() == " inf -inf INF -INF INF -INF +INF -INF" ); +#endif } int main()
[gcc r16-958] libstdc++: Compare keys and values separately in flat_map::operator==
https://gcc.gnu.org/g:ad96f0344adfc847874b34b43f30371979ae9963 commit r16-958-gad96f0344adfc847874b34b43f30371979ae9963 Author: Patrick Palka Date: Thu May 29 10:12:23 2025 -0400 libstdc++: Compare keys and values separately in flat_map::operator== Instead of effectively doing a zipped comparison of the keys and values, compare them separately to leverage the underlying containers' optimized equality implementations. libstdc++-v3/ChangeLog: * include/std/flat_map (_Flat_map_impl::operator==): Compare keys and values separately. Reviewed-by: Jonathan Wakely Diff: --- libstdc++-v3/include/std/flat_map | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/libstdc++-v3/include/std/flat_map b/libstdc++-v3/include/std/flat_map index cec7f36cff9f..4bd4963c2ad7 100644 --- a/libstdc++-v3/include/std/flat_map +++ b/libstdc++-v3/include/std/flat_map @@ -873,7 +873,10 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION [[nodiscard]] friend bool operator==(const _Derived& __x, const _Derived& __y) - { return std::equal(__x.begin(), __x.end(), __y.begin(), __y.end()); } + { + return __x._M_cont.keys == __y._M_cont.keys + && __x._M_cont.values == __y._M_cont.values; + } template [[nodiscard]]
[gcc r16-957] libstdc++: Fix tuple/pair confusion with std::erase_if(flat_map) [PR120465]
https://gcc.gnu.org/g:589b27ec5769410e036df57645ff1eb7c765f692 commit r16-957-g589b27ec5769410e036df57645ff1eb7c765f692 Author: Patrick Palka Date: Thu May 29 10:11:57 2025 -0400 libstdc++: Fix tuple/pair confusion with std::erase_if(flat_map) [PR120465] std::erase_if for flat_map/multimap is implemented via ranges::erase_if over a zip_view of the keys and values, the value_type of which is a tuple, but the given predicate needs to be called with a pair (flat_map's value_type). So use a projection to convert the tuple into a suitable pair. PR libstdc++/120465 libstdc++-v3/ChangeLog: * include/std/flat_map (_Flat_map_impl::_M_erase_if): Use a projection with ranges::remove_if to pass a pair instead of a tuple to the predicate. * testsuite/23_containers/flat_map/1.cc (test07): Strengthen to expect the argument passed to the predicate is a pair. * testsuite/23_containers/flat_multimap/1.cc (test07): Likewise. Co-authored-by: Jonathan Wakely Reviewed-by: Tomasz KamiĆski Reviewed-by: Jonathan Wakely Diff: --- libstdc++-v3/include/std/flat_map | 5 - libstdc++-v3/testsuite/23_containers/flat_map/1.cc | 3 ++- libstdc++-v3/testsuite/23_containers/flat_multimap/1.cc | 3 ++- 3 files changed, 8 insertions(+), 3 deletions(-) diff --git a/libstdc++-v3/include/std/flat_map b/libstdc++-v3/include/std/flat_map index 6593988d213c..cec7f36cff9f 100644 --- a/libstdc++-v3/include/std/flat_map +++ b/libstdc++-v3/include/std/flat_map @@ -895,7 +895,10 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION { auto __guard = _M_make_clear_guard(); auto __zv = views::zip(_M_cont.keys, _M_cont.values); - auto __sr = ranges::remove_if(__zv, __pred); + auto __sr = ranges::remove_if(__zv, __pred, + [](const auto& __e) { + return const_reference(__e); + }); auto __erased = __sr.size(); erase(end() - __erased, end()); __guard._M_disable(); diff --git a/libstdc++-v3/testsuite/23_containers/flat_map/1.cc b/libstdc++-v3/testsuite/23_containers/flat_map/1.cc index a9690208b09f..1b593135f225 100644 --- a/libstdc++-v3/testsuite/23_containers/flat_map/1.cc +++ b/libstdc++-v3/testsuite/23_containers/flat_map/1.cc @@ -247,8 +247,9 @@ void test07() { // PR libstdc++/119427 - std::erase_if(std::flat_foo) does not work + // PR libstdc++/120465 - erase_if for flat_map calls predicate with incorrect type std::flat_map m = {std::pair{1, 2}, {3, 4}, {5, 6}}; - auto n = std::erase_if(m, [](auto x) { auto [k,v] = x; return k == 1 || v == 6; }); + auto n = std::erase_if(m, [](auto x) { return x.first == 1 || x.second == 6; }); VERIFY( n == 2 ); VERIFY( std::ranges::equal(m, (std::pair[]){{3,4}}) ); } diff --git a/libstdc++-v3/testsuite/23_containers/flat_multimap/1.cc b/libstdc++-v3/testsuite/23_containers/flat_multimap/1.cc index 1c5c9a88ab6b..d746614401de 100644 --- a/libstdc++-v3/testsuite/23_containers/flat_multimap/1.cc +++ b/libstdc++-v3/testsuite/23_containers/flat_multimap/1.cc @@ -225,8 +225,9 @@ void test07() { // PR libstdc++/119427 - std::erase_if(std::flat_foo) does not work + // PR libstdc++/120465 - erase_if for flat_map calls predicate with incorrect type std::flat_multimap m = {std::pair{1, 2}, {3, 4}, {3, 3}, {5, 6}, {6, 6}}; - auto n = std::erase_if(m, [](auto x) { auto [k,v] = x; return k == 1 || v == 6; }); + auto n = std::erase_if(m, [](auto x) { return x.first == 1 || x.second == 6; }); VERIFY( n == 3 ); VERIFY( std::ranges::equal(m, (std::pair[]){{3,4},{3,3}}) ); }
[gcc r16-956] libstdc++: Fix another 17_intro/names.cc failure on AIX
https://gcc.gnu.org/g:8e7cf04d54f5ffb540fdd5406010bb162b9f472b commit r16-956-g8e7cf04d54f5ffb540fdd5406010bb162b9f472b Author: Jonathan Wakely Date: Tue May 27 21:50:24 2025 +0100 libstdc++: Fix another 17_intro/names.cc failure on AIX FAIL: 17_intro/names.cc -std=gnu++98 (test for excess errors) Also fix typo in experimental/names.cc where I did #undef for the wrong name in r16-901-gd1ced2a5ea6b09. libstdc++-v3/ChangeLog: * testsuite/17_intro/names.cc [_AIX] (a): Undefine. * testsuite/experimental/names.cc [_AIX] (ptr): Undefine. Diff: --- libstdc++-v3/testsuite/17_intro/names.cc | 2 ++ libstdc++-v3/testsuite/experimental/names.cc | 2 +- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/libstdc++-v3/testsuite/17_intro/names.cc b/libstdc++-v3/testsuite/17_intro/names.cc index a61e49dc8191..f32205d9c7f5 100644 --- a/libstdc++-v3/testsuite/17_intro/names.cc +++ b/libstdc++-v3/testsuite/17_intro/names.cc @@ -248,6 +248,8 @@ #undef r #undef x #undef y +// defines drand48_data::a +#undef a // defines _LC_weight_t::n #undef n // defines pollfd_ext::u on AIX 7.3 diff --git a/libstdc++-v3/testsuite/experimental/names.cc b/libstdc++-v3/testsuite/experimental/names.cc index 4bedd530ecc5..94ae76fc610b 100644 --- a/libstdc++-v3/testsuite/experimental/names.cc +++ b/libstdc++-v3/testsuite/experimental/names.cc @@ -25,7 +25,7 @@ #ifdef _AIX // declares endnetgrent_r with ptr parameter. -# undef n +# undef ptr #endif // Filesystem
[gcc r16-961] c++, coroutines: Fix identification of coroutine ramps [PR120453].
https://gcc.gnu.org/g:217b7f655227a52e5fe26729baa09dc6083ed577 commit r16-961-g217b7f655227a52e5fe26729baa09dc6083ed577 Author: Iain Sandoe Date: Thu May 29 11:00:18 2025 +0100 c++, coroutines: Fix identification of coroutine ramps [PR120453]. The existing implementation, incorrectly, tried to use DECL_RAMP_FN in check_return_expr to determine if we are handling a ramp func. However, that query is only set for the resume/destroy functions. Replace the use of DECL_RAMP_FN with a new query. PR c++/120453 gcc/cp/ChangeLog: * cp-tree.h (DECL_RAMP_P): New. * typeck.cc (check_return_expr): Use DECL_RAMP_P instead of DECL_RAMP_FN. gcc/testsuite/ChangeLog: * g++.dg/coroutines/pr120453.C: New test. Signed-off-by: Iain Sandoe Diff: --- gcc/cp/cp-tree.h | 4 ++ gcc/cp/typeck.cc | 2 +- gcc/testsuite/g++.dg/coroutines/pr120453.C | 95 ++ 3 files changed, 100 insertions(+), 1 deletion(-) diff --git a/gcc/cp/cp-tree.h b/gcc/cp/cp-tree.h index 19c0b452d868..d9fc80b92e58 100644 --- a/gcc/cp/cp-tree.h +++ b/gcc/cp/cp-tree.h @@ -5522,6 +5522,10 @@ decl_template_parm_check (const_tree t, const char *f, int l, const char *fn) #define DECL_RAMP_FN(NODE) \ (coro_get_ramp_function (NODE)) +/* For a FUNCTION_DECL this is true if it is a coroutine ramp. */ +#define DECL_RAMP_P(NODE) \ + DECL_COROUTINE_P (NODE) && !DECL_RAMP_FN (NODE) + /* True for an OMP_ATOMIC that has dependent parameters. These are stored as an expr in operand 1, and integer_zero_node or clauses in operand 0. */ #define OMP_ATOMIC_DEPENDENT_P(NODE) \ diff --git a/gcc/cp/typeck.cc b/gcc/cp/typeck.cc index af2cbaff8fdc..ac1eb397f011 100644 --- a/gcc/cp/typeck.cc +++ b/gcc/cp/typeck.cc @@ -11466,7 +11466,7 @@ check_return_expr (tree retval, bool *no_warning, bool *dangling) /* Don't check copy-initialization for NRV in a coroutine ramp; we implement this case as NRV, but it's specified as directly initializing the return value from get_return_object(). */ - if (DECL_RAMP_FN (current_function_decl) && named_return_value_okay_p) + if (DECL_RAMP_P (current_function_decl) && named_return_value_okay_p) converted = true; /* First convert the value to the function's return type, then diff --git a/gcc/testsuite/g++.dg/coroutines/pr120453.C b/gcc/testsuite/g++.dg/coroutines/pr120453.C new file mode 100644 index ..2f2c4ece008b --- /dev/null +++ b/gcc/testsuite/g++.dg/coroutines/pr120453.C @@ -0,0 +1,95 @@ +// PR120453 - reduced testcase amended to add a TaskBase move constructor +// and a LazyTask destructor, to more closely match the original code. +// { dg-additional-options "-w" } +namespace std { +template struct __coroutine_traits_impl; +template + requires requires { typename _Result; } +struct __coroutine_traits_impl<_Result>; +template struct coroutine_traits : _Result {}; +template struct coroutine_handle { + static coroutine_handle from_address(void *); + operator coroutine_handle<>(); + void *address(); +}; +struct suspend_never { + bool await_ready(); + void await_suspend(coroutine_handle<>); + void await_resume(); +}; +} // namespace std + +namespace QCoro { +namespace detail { +template +concept has_await_methods = requires(T t) { t; }; +} // namespace detail + +template +concept Awaitable = detail::has_await_methods; +namespace detail { +struct TaskFinalSuspend { + bool await_ready() noexcept; + template + void await_suspend(std::coroutine_handle) noexcept; + void await_resume() noexcept; +}; +struct TaskPromiseBase { + std::suspend_never initial_suspend(); + auto final_suspend() noexcept { return TaskFinalSuspend{}; } + template auto &&await_transform(T &&); +}; +struct TaskPromise : TaskPromiseBase { + void unhandled_exception(); +}; +template struct TaskAwaiterBase { + bool await_ready(); + void await_suspend(std::coroutine_handle<>); +}; +template class, typename> struct TaskBase { + TaskBase() = default; + TaskBase(TaskBase &&) = default; + void operator=(TaskBase &&); + auto operator co_await() const; + std::coroutine_handle<> mCoroutine; +}; +} // namespace detail +template struct Task : detail::TaskBase {}; +} // namespace QCoro + +namespace QCoro::detail { +template auto &&TaskPromiseBase::await_transform(T &&awaitable) { + return awaitable; +} + +template class TaskImpl, typename PromiseType> +auto TaskBase::operator co_await() const { + class TaskAwaiter : public TaskAwaiterBase { + public: +TaskAwaiter(std::coroutine_handle<>); +auto await_resume() {} + }; + return TaskAwaiter{mCoroutine}; +} + +} // namespace QCoro::detail + +namespace QCoro { +template class LazyTask ; +namespace detail { +struct LazyTaskPromise : TaskPromise { + LazyTask get_return_object(); +}; +} // namespace detail + +templa
[gcc r16-971] libgomp: Add OpenACC's acc_memcpy_device{, _async} routines [PR93226]
https://gcc.gnu.org/g:f4aa6b5a8d63050f5d61fcec222ed87be4c0a266 commit r16-971-gf4aa6b5a8d63050f5d61fcec222ed87be4c0a266 Author: Tobias Burnus Date: Thu May 29 22:47:06 2025 +0200 libgomp: Add OpenACC's acc_memcpy_device{,_async} routines [PR93226] libgomp/ChangeLog: PR libgomp/93226 * libgomp-plugin.h (GOMP_OFFLOAD_openacc_async_dev2dev): New prototype. * libgomp.h (struct acc_dispatch_t): Add dev2dev_func. (gomp_copy_dev2dev): New prototype. * libgomp.map (OACC_2.6.1): New; add acc_memcpy_device{,_async}. * libgomp.texi (acc_memcpy_device): New. * oacc-mem.c (memcpy_tofrom_device): Change to take from/to device boolean; use memcpy not memmove; add early return if size == 0 or same device + same ptr. (acc_memcpy_to_device, acc_memcpy_to_device_async, acc_memcpy_from_device, acc_memcpy_from_device_async): Update. (acc_memcpy_device, acc_memcpy_device_async): New. * openacc.f90 (acc_memcpy_device, acc_memcpy_device_async): Add interface. * openacc_lib.h (acc_memcpy_device, acc_memcpy_device_async): Likewise. * openacc.h (acc_memcpy_device, acc_memcpy_device_async): Add prototype. * plugin/plugin-gcn.c (GOMP_OFFLOAD_openacc_async_host2dev): Update comment. (GOMP_OFFLOAD_openacc_async_dev2host): Update call. (GOMP_OFFLOAD_openacc_async_dev2dev): New. * plugin/plugin-nvptx.c (cuda_memcpy_dev_sanity_check): New. (GOMP_OFFLOAD_dev2dev): Call it. (GOMP_OFFLOAD_openacc_async_dev2dev): New. * target.c (gomp_copy_dev2dev): New. (gomp_load_plugin_for_device): Load dev2dev and async_dev2dev. * testsuite/libgomp.oacc-c-c++-common/acc_memcpy_device-1.c: New test. * testsuite/libgomp.oacc-fortran/acc_memcpy_device-1.f90: New test. Diff: --- libgomp/libgomp-plugin.h | 2 + libgomp/libgomp.h | 4 + libgomp/libgomp.map| 6 ++ libgomp/libgomp.texi | 39 +++ libgomp/oacc-mem.c | 44 +--- libgomp/openacc.f90| 22 libgomp/openacc.h | 4 +- libgomp/openacc_lib.h | 24 + libgomp/plugin/plugin-gcn.c| 17 +++- libgomp/plugin/plugin-nvptx.c | 43 libgomp/target.c | 14 +++ .../acc_memcpy_device-1.c | 96 + .../libgomp.oacc-fortran/acc_memcpy_device-1.f90 | 113 + 13 files changed, 409 insertions(+), 19 deletions(-) diff --git a/libgomp/libgomp-plugin.h b/libgomp/libgomp-plugin.h index 924fc1f44b1a..50c89feaf734 100644 --- a/libgomp/libgomp-plugin.h +++ b/libgomp/libgomp-plugin.h @@ -200,6 +200,8 @@ extern bool GOMP_OFFLOAD_openacc_async_dev2host (int, void *, const void *, size struct goacc_asyncqueue *); extern bool GOMP_OFFLOAD_openacc_async_host2dev (int, void *, const void *, size_t, struct goacc_asyncqueue *); +extern bool GOMP_OFFLOAD_openacc_async_dev2dev (int, void *, const void *, size_t, + struct goacc_asyncqueue *); extern void *GOMP_OFFLOAD_openacc_cuda_get_current_device (void); extern void *GOMP_OFFLOAD_openacc_cuda_get_current_context (void); extern void *GOMP_OFFLOAD_openacc_cuda_get_stream (struct goacc_asyncqueue *); diff --git a/libgomp/libgomp.h b/libgomp/libgomp.h index 6030f9d0a2cb..ed4e23ae3e16 100644 --- a/libgomp/libgomp.h +++ b/libgomp/libgomp.h @@ -1360,6 +1360,7 @@ typedef struct acc_dispatch_t __typeof (GOMP_OFFLOAD_openacc_async_exec) *exec_func; __typeof (GOMP_OFFLOAD_openacc_async_dev2host) *dev2host_func; __typeof (GOMP_OFFLOAD_openacc_async_host2dev) *host2dev_func; +__typeof (GOMP_OFFLOAD_openacc_async_dev2dev) *dev2dev_func; } async; __typeof (GOMP_OFFLOAD_openacc_get_property) *get_property_func; @@ -1467,6 +1468,9 @@ extern void gomp_copy_host2dev (struct gomp_device_descr *, extern void gomp_copy_dev2host (struct gomp_device_descr *, struct goacc_asyncqueue *, void *, const void *, size_t); +extern void gomp_copy_dev2dev (struct gomp_device_descr *, + struct goacc_asyncqueue *, void *, const void *, + size_t); extern uintptr_t gomp_map_val (struct target_mem_desc *, void **, size_t); extern bool gomp_attach_pointer (struct gomp_device_descr *, struct goacc_asyncq
[gcc] Created branch 'meissner/heads/work210' in namespace 'refs/users'
The branch 'meissner/heads/work210' was created in namespace 'refs/users' pointing to: 2047aa4ce2ed... c++: xobj lambda 'this' capture [PR113563]
[gcc(refs/users/meissner/heads/work210)] Add ChangeLog.meissner and REVISION.
https://gcc.gnu.org/g:2157a9912ef15e4b95b05b61f88f20166a62e6b4 commit 2157a9912ef15e4b95b05b61f88f20166a62e6b4 Author: Michael Meissner Date: Thu May 29 16:51:24 2025 -0400 Add ChangeLog.meissner and REVISION. 2025-05-29 Michael Meissner gcc/ * REVISION: New file for branch. * ChangeLog.meissner: New file. gcc/c-family/ * ChangeLog.meissner: New file. gcc/c/ * ChangeLog.meissner: New file. gcc/cp/ * ChangeLog.meissner: New file. gcc/fortran/ * ChangeLog.meissner: New file. gcc/testsuite/ * ChangeLog.meissner: New file. libgcc/ * ChangeLog.meissner: New file. Diff: --- gcc/ChangeLog.meissner | 38 ++ gcc/REVISION | 1 + gcc/c-family/ChangeLog.meissner | 38 ++ gcc/c/ChangeLog.meissner | 38 ++ gcc/cp/ChangeLog.meissner| 38 ++ gcc/fortran/ChangeLog.meissner | 38 ++ gcc/testsuite/ChangeLog.meissner | 38 ++ libgcc/ChangeLog.meissner| 38 ++ libstdc++-v3/ChangeLog.meissner | 38 ++ 9 files changed, 305 insertions(+) diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner new file mode 100644 index ..e5799c529019 --- /dev/null +++ b/gcc/ChangeLog.meissner @@ -0,0 +1,38 @@ + Branch work210, baseline + +2025-05-29 Michael Meissner + +Add ChangeLog.meissner and REVISION. + +2025-05-29 Michael Meissner + +gcc/ + + * REVISION: New file for branch. + * ChangeLog.meissner: New file. + +gcc/c-family/ + + * ChangeLog.meissner: New file. + +gcc/c/ + + * ChangeLog.meissner: New file. + +gcc/cp/ + + * ChangeLog.meissner: New file. + +gcc/fortran/ + + * ChangeLog.meissner: New file. + +gcc/testsuite/ + + * ChangeLog.meissner: New file. + +libgcc/ + + * ChangeLog.meissner: New file. + + Clone branch diff --git a/gcc/REVISION b/gcc/REVISION new file mode 100644 index ..2cb696d34aa7 --- /dev/null +++ b/gcc/REVISION @@ -0,0 +1 @@ +work210 branch diff --git a/gcc/c-family/ChangeLog.meissner b/gcc/c-family/ChangeLog.meissner new file mode 100644 index ..e5799c529019 --- /dev/null +++ b/gcc/c-family/ChangeLog.meissner @@ -0,0 +1,38 @@ + Branch work210, baseline + +2025-05-29 Michael Meissner + +Add ChangeLog.meissner and REVISION. + +2025-05-29 Michael Meissner + +gcc/ + + * REVISION: New file for branch. + * ChangeLog.meissner: New file. + +gcc/c-family/ + + * ChangeLog.meissner: New file. + +gcc/c/ + + * ChangeLog.meissner: New file. + +gcc/cp/ + + * ChangeLog.meissner: New file. + +gcc/fortran/ + + * ChangeLog.meissner: New file. + +gcc/testsuite/ + + * ChangeLog.meissner: New file. + +libgcc/ + + * ChangeLog.meissner: New file. + + Clone branch diff --git a/gcc/c/ChangeLog.meissner b/gcc/c/ChangeLog.meissner new file mode 100644 index ..e5799c529019 --- /dev/null +++ b/gcc/c/ChangeLog.meissner @@ -0,0 +1,38 @@ + Branch work210, baseline + +2025-05-29 Michael Meissner + +Add ChangeLog.meissner and REVISION. + +2025-05-29 Michael Meissner + +gcc/ + + * REVISION: New file for branch. + * ChangeLog.meissner: New file. + +gcc/c-family/ + + * ChangeLog.meissner: New file. + +gcc/c/ + + * ChangeLog.meissner: New file. + +gcc/cp/ + + * ChangeLog.meissner: New file. + +gcc/fortran/ + + * ChangeLog.meissner: New file. + +gcc/testsuite/ + + * ChangeLog.meissner: New file. + +libgcc/ + + * ChangeLog.meissner: New file. + + Clone branch diff --git a/gcc/cp/ChangeLog.meissner b/gcc/cp/ChangeLog.meissner new file mode 100644 index ..e5799c529019 --- /dev/null +++ b/gcc/cp/ChangeLog.meissner @@ -0,0 +1,38 @@ + Branch work210, baseline + +2025-05-29 Michael Meissner + +Add ChangeLog.meissner and REVISION. + +2025-05-29 Michael Meissner + +gcc/ + + * REVISION: New file for branch. + * ChangeLog.meissner: New file. + +gcc/c-family/ + + * ChangeLog.meissner: New file. + +gcc/c/ + + * ChangeLog.meissner: New file. + +gcc/cp/ + + * ChangeLog.meissner: New file. + +gcc/fortran/ + + * ChangeLog.meissner: New file. + +gcc/testsuite/ + + * ChangeLog.meissner: New file. + +libgcc/ + + * ChangeLog.meissner: New file. + + Clone branch diff --git a/gcc/fortran/ChangeLog.meissner b/gcc/fortran/ChangeLog.meissner new file mode 100644 inde
[gcc(refs/users/meissner/heads/work210-orig)] Add REVISION.
https://gcc.gnu.org/g:2c712f78833c539a0f2c87449fb055665584cf46 commit 2c712f78833c539a0f2c87449fb055665584cf46 Author: Michael Meissner Date: Thu May 29 16:52:20 2025 -0400 Add REVISION. 2025-05-29 Michael Meissner gcc/ * REVISION: New file for branch. Diff: --- gcc/REVISION | 1 + 1 file changed, 1 insertion(+) diff --git a/gcc/REVISION b/gcc/REVISION new file mode 100644 index ..f4287347918f --- /dev/null +++ b/gcc/REVISION @@ -0,0 +1 @@ +work210-orig branch
[gcc] Created branch 'meissner/heads/work210-bugs' in namespace 'refs/users'
The branch 'meissner/heads/work210-bugs' was created in namespace 'refs/users' pointing to: 2157a9912ef1... Add ChangeLog.meissner and REVISION.