[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [RISC-V][PR target/118410] Improve code generation for some logical ops

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:512a79ec2725187235d9564db48ba47f0c7bb27d

commit 512a79ec2725187235d9564db48ba47f0c7bb27d
Author: Jeff Law 
Date:   Sat Apr 19 12:30:42 2025 -0600

[RISC-V][PR target/118410] Improve code generation for some logical ops

I'm posting this on behalf of Shreya Munnangi who is working as an intern 
with
me.  I've got her digging into prerequisites for removing mvconst_internal 
and
would prefer she focus on that rather than our patch process at this time.

--

We can use the orn, xnor, andn instructions on RISC-V to improve the code
generated logical operations when one operand is a constant C where
synthesizing ~C is cheaper than synthesizing C.

This is going to be an N -> N - 1 splitter rather than a 
define_insn_and_split.
A define_insn_and_split can obviously work, but has multiple undesirable
effects in general.

As a result of implementing as a simple define_split we're not supporting 
AND
at this time.  We need to clean up the mvconst_internal situation first 
after
which supporting AND is trivial.

This has been tested in Ventana's CI system as well as my tester. Obviously
we'll wait for the pre-commit tester to run before moving forward.

PR target/118410
gcc/
* config/riscv/bitmanip.md (logical with constant argument): New
splitter for cases where synthesizing ~C is cheaper than 
synthesizing
the original constant C.

gcc/testsuite/
* gcc.target/riscv/pr118410-1.c: New test.
* gcc.target/riscv/pr118410-2.c: Likewise.

Co-authored-by: Jeff Law  

(cherry picked from commit 874f4c164749f1ed5b60ddf1d4533c8f4ba627a1)

Diff:
---
 gcc/config/riscv/bitmanip.md| 38 +
 gcc/testsuite/gcc.target/riscv/pr118410-1.c |  9 +++
 gcc/testsuite/gcc.target/riscv/pr118410-2.c |  9 +++
 3 files changed, 56 insertions(+)

diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md
index 2a3884cfde01..d0919ece31f7 100644
--- a/gcc/config/riscv/bitmanip.md
+++ b/gcc/config/riscv/bitmanip.md
@@ -1263,3 +1263,41 @@
   expand_crc_using_clmul (mode, mode, operands);
   DONE;
 })
+
+;; If we have an XOR/IOR with a constant operand (C) and the we can
+;; synthesize ~C more efficiently than C, then synthesize ~C and use
+;; xnor/orn instead.
+;;
+;; The same can be done for AND, but mvconst_internal's issues get in
+;; the way.  That's future work.
+(define_split
+  [(set (match_operand:X 0 "register_operand")
+   (any_or:X (match_operand:X 1 "register_operand")
+ (match_operand:X 2 "const_int_operand")))
+   (clobber (match_operand:X 3 "register_operand"))]
+  "TARGET_ZBB
+   && (riscv_const_insns (operands[2], true)
+   > riscv_const_insns (GEN_INT (~INTVAL (operands[2])), true))"
+  [(const_int 0)]
+{
+  /* Get the inverted constant into the temporary register.  */
+  riscv_emit_move (operands[3], GEN_INT (~INTVAL (operands[2])));
+
+  /* For xnor, the NOT operation is in a different position.  So
+ we have to customize the split code we generate a bit.
+
+ It is expected that AND will be handled like IOR in the future.  */
+  if ( == XOR)
+{
+  rtx x = gen_rtx_XOR (mode, operands[1], operands[3]);
+  x = gen_rtx_NOT (mode, x);
+  emit_insn (gen_rtx_SET (operands[0], x));
+}
+  else
+{
+  rtx x = gen_rtx_NOT (mode, operands[3]);
+  x = gen_rtx_IOR (mode, x, operands[1]);
+  emit_insn (gen_rtx_SET (operands[0], x));
+}
+  DONE;
+})
diff --git a/gcc/testsuite/gcc.target/riscv/pr118410-1.c 
b/gcc/testsuite/gcc.target/riscv/pr118410-1.c
new file mode 100644
index ..4a8b847d4f4c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/pr118410-1.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */
+/* { dg-options "-march=rv64gcb -mabi=lp64d" { target { rv64} } } */
+/* { dg-options "-march=rv32gcb -mabi=ilp32" { target { rv32} } } */
+
+long orlow(long x) { return x | ((1L << 24) - 1); }
+
+/* { dg-final { scan-assembler-times "orn\t" 1 } } */
+/* { dg-final { scan-assembler-not "addi\t" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/pr118410-2.c 
b/gcc/testsuite/gcc.target/riscv/pr118410-2.c
new file mode 100644
index ..b63a1d9c4659
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/pr118410-2.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */
+/* { dg-options "-march=rv64gcb -mabi=lp64d" { target { rv64} } } */
+/* { dg-options "-march=rv32gcb -mabi=ilp32" { target { rv32} } } */
+
+long xorlow(long x) { return x ^ ((1L << 24) - 1); }
+
+/* { dg-final { scan-assembler-times "xnor\t" 1 } } */
+/* { dg-final { scan-assembler-not "addi\t" } } */

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Fix register move cost for SIBCALL_REGS/JALR_REGS

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:2bf7f4274e6d02515570496676a22f36ba3c7d15

commit 2bf7f4274e6d02515570496676a22f36ba3c7d15
Author: Zhijin Zeng 
Date:   Mon Apr 28 09:24:16 2025 +0800

RISC-V: Fix register move cost for SIBCALL_REGS/JALR_REGS

SIBCALL_REGS/JALR_REGS are also subset of GR_REGS and need to
be taken into acount in riscv_register_move_cost, otherwise it
will get a incorrect cost.

gcc/ChangeLog:

* config/riscv/riscv.cc (riscv_register_move_cost): Use
reg_class_subset_p to check the reg class.

(cherry picked from commit 102eccaf8e2f914d3afbf7acfcee19bc5b240eca)

Diff:
---
 gcc/config/riscv/riscv.cc | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index bad59e248d08..c53e0dd7a7d1 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -9650,10 +9650,10 @@ int
 riscv_register_move_cost (machine_mode mode,
  reg_class_t from, reg_class_t to)
 {
-  bool from_is_fpr = from == FP_REGS || from == RVC_FP_REGS;
-  bool from_is_gpr = from == GR_REGS || from == RVC_GR_REGS;
-  bool to_is_fpr = to == FP_REGS || to == RVC_FP_REGS;
-  bool to_is_gpr = to == GR_REGS || to == RVC_GR_REGS;
+  bool from_is_fpr = reg_class_subset_p (from, FP_REGS);
+  bool from_is_gpr = reg_class_subset_p (from, GR_REGS);
+  bool to_is_fpr = reg_class_subset_p (to, FP_REGS);
+  bool to_is_gpr = reg_class_subset_p (to, GR_REGS);
   if ((from_is_fpr && to_is_gpr) || (from_is_gpr && to_is_fpr))
 return tune_param->fmv_cost;

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [PATCH] RISC-V: Minimal support for sdtrig and ssstrict extensions.

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:71b176096c00f0f77b1734294ec30f209209cc46

commit 71b176096c00f0f77b1734294ec30f209209cc46
Author: Dongyan Chen 
Date:   Tue May 6 17:09:54 2025 -0600

[PATCH] RISC-V: Minimal support for sdtrig and ssstrict extensions.

This patch support sdtrig and ssstrict extensions[1].
To enable GCC to recognize and process sdtrig and ssstrict extensions 
correctly
at compile time.

[1] https://github.com/riscv/riscv-profiles/blob/main/src/rva23-profile.adoc

gcc/ChangeLog:

* common/config/riscv/riscv-common.cc: New extension.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/arch-47.c: New test.

(cherry picked from commit 82126b26d17ed2c5ee48ca51e3fed69e898c9a20)

Diff:
---
 gcc/common/config/riscv/riscv-common.cc  | 3 +++
 gcc/testsuite/gcc.target/riscv/arch-47.c | 5 +
 2 files changed, 8 insertions(+)

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index 58c7d205b336..0233e1a108be 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -432,6 +432,8 @@ static const struct riscv_ext_version 
riscv_ext_version_table[] =
   {"zcmp", ISA_SPEC_CLASS_NONE, 1, 0},
   {"zcmt", ISA_SPEC_CLASS_NONE, 1, 0},
 
+  {"sdtrig",  ISA_SPEC_CLASS_NONE, 1, 0},
+
   {"smaia", ISA_SPEC_CLASS_NONE, 1, 0},
   {"smepmp",ISA_SPEC_CLASS_NONE, 1, 0},
   {"smstateen", ISA_SPEC_CLASS_NONE, 1, 0},
@@ -440,6 +442,7 @@ static const struct riscv_ext_version 
riscv_ext_version_table[] =
   {"sscofpmf",  ISA_SPEC_CLASS_NONE, 1, 0},
   {"ssstateen", ISA_SPEC_CLASS_NONE, 1, 0},
   {"sstc",  ISA_SPEC_CLASS_NONE, 1, 0},
+  {"ssstrict",  ISA_SPEC_CLASS_NONE, 1, 0},
 
   {"svade",   ISA_SPEC_CLASS_NONE, 1, 0},
   {"svadu",   ISA_SPEC_CLASS_NONE, 1, 0},
diff --git a/gcc/testsuite/gcc.target/riscv/arch-47.c 
b/gcc/testsuite/gcc.target/riscv/arch-47.c
new file mode 100644
index ..06bc80fe7800
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/arch-47.c
@@ -0,0 +1,5 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_sdtrig_ssstrict -mabi=lp64" } */
+int foo()
+{
+}

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] Make end_sequence return the insn sequence

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:49278dd284fab03788b4e69ba385261ecf6bb05b

commit 49278dd284fab03788b4e69ba385261ecf6bb05b
Author: Richard Sandiford 
Date:   Fri May 16 13:24:01 2025 +0100

Make end_sequence return the insn sequence

The start_sequence/end_sequence interface was a big improvement over
the previous state, but one slightly awkward thing about it is that
you have to call get_insns before end_sequence in order to get the
insn sequence itself:

   To get the contents of the sequence just made, you must call
   `get_insns' *before* calling here.

We therefore have quite a lot of code like this:

  insns = get_insns ();
  end_sequence ();
  return insns;

It would seem simpler to write:

  return end_sequence ();

instead.

I can see three main potential objections to this:

(1) It isn't obvious whether ending the sequence would return the first
or the last instruction.  But although some code reads *both* the
first and the last instruction, I can't think of a specific case
where code would want *only* the last instruction.  All the emit
functions take the first instruction rather than the last.

(2) The "end" in end_sequence might imply the C++ meaning of an exclusive
endpoint iterator.  But for an insn sequence, the exclusive endpoint
is always the null pointer, so it would never need to be returned.
That said, we could rename the function to something like
"finish_sequence" or "complete_sequence" if this is an issue.

(3) There might have been an intention that start_sequence/end_sequence
could in future reclaim memory for unwanted sequences, and so an
explicit get_insns was used to indicate that the caller does want
the sequence.

But that sort of memory reclaimation has never been added,
and now that the codebase is C++, it would be easier to handle
using RAII.  I think reclaiming memory would be difficult to do in
any case, since some code records the individual instructions that
they emit, rather than using get_insns.

gcc/
* rtl.h (end_sequence): Return the sequence.
* emit-rtl.cc (end_sequence): Likewise.

(cherry picked from commit 84269eeecf3c31a7f6be1f210f5e6c38d0c01e31)

Diff:
---
 gcc/emit-rtl.cc | 14 --
 gcc/rtl.h   |  2 +-
 2 files changed, 9 insertions(+), 7 deletions(-)

diff --git a/gcc/emit-rtl.cc b/gcc/emit-rtl.cc
index 3e2c4309dee6..d86fb23b29a6 100644
--- a/gcc/emit-rtl.cc
+++ b/gcc/emit-rtl.cc
@@ -5722,22 +5722,22 @@ pop_topmost_sequence (void)
   end_sequence ();
 }
 
-/* After emitting to a sequence, restore previous saved state.
-
-   To get the contents of the sequence just made, you must call
-   `get_insns' *before* calling here.
+/* After emitting to a sequence, restore the previous saved state and return
+   the start of the completed sequence.
 
If the compiler might have deferred popping arguments while
generating this sequence, and this sequence will not be immediately
inserted into the instruction stream, use do_pending_stack_adjust
-   before calling get_insns.  That will ensure that the deferred
+   before calling this function.  That will ensure that the deferred
pops are inserted into this sequence, and not into some random
location in the instruction stream.  See INHIBIT_DEFER_POP for more
information about deferred popping of arguments.  */
 
-void
+rtx_insn *
 end_sequence (void)
 {
+  rtx_insn *insns = get_insns ();
+
   struct sequence_stack *tem = get_current_sequence ()->next;
 
   set_first_insn (tem->first);
@@ -5747,6 +5747,8 @@ end_sequence (void)
   memset (tem, 0, sizeof (*tem));
   tem->next = free_sequence_stack;
   free_sequence_stack = tem;
+
+  return insns;
 }
 
 /* Return true if currently emitting into a sequence.  */
diff --git a/gcc/rtl.h b/gcc/rtl.h
index 3b676c468805..62f01a1def04 100644
--- a/gcc/rtl.h
+++ b/gcc/rtl.h
@@ -3304,7 +3304,7 @@ extern rtx_insn *get_last_nonnote_insn (void);
 extern void start_sequence (void);
 extern void push_to_sequence (rtx_insn *);
 extern void push_to_sequence2 (rtx_insn *, rtx_insn *);
-extern void end_sequence (void);
+extern rtx_insn *end_sequence (void);
 #if TARGET_SUPPORTS_WIDE_INT == 0
 extern double_int rtx_to_double_int (const_rtx);
 #endif

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Adjust vx combine test case to avoid name conflict

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:8776c190ce92c478b83f5ad092bdc46b0e6a1f6a

commit 8776c190ce92c478b83f5ad092bdc46b0e6a1f6a
Author: Pan Li 
Date:   Tue May 13 11:12:53 2025 +0800

RISC-V: Adjust vx combine test case to avoid name conflict

Given we will put all vx combine for int8 in a single file,
we need to make sure the generate function for different
types and ops has different function name.  Thus, refactor
the test helper macros for avoiding possible function name
conflict.

The below test suites are passed for this patch series.
* The rv64gcv fully regression test.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c: Add
type and op name to generate test function name.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c: Ditto
* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c: Ditto
* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c: Ditto
* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c: Ditto
* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c: Ditto
* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c: Ditto
* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c: Ditto
* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c: Ditto
* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c: Ditto
* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c: Ditto
* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c: Ditto
* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c: Ditto
* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c: Ditto
* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c: Ditto
* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c: Ditto
* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c: Ditto
* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c: Ditto
* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c: Ditto
* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c: Ditto
* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c: Ditto
* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c: Ditto
* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c: Ditto
* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c: Ditto
* gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i16.c: Ditto
* gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i32.c: Ditto
* gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i64.c: Ditto
* gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i8.c: Ditto
* gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u16.c: Ditto
* gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u32.c: Ditto
* gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u64.c: Ditto
* gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u8.c: Ditto
* gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i16.c: Ditto
* gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i32.c: Ditto
* gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i64.c: Ditto
* gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i8.c: Ditto
* gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u16.c: Ditto
* gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u32.c: Ditto
* gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u64.c: Ditto
* gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u8.c: Ditto
* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c: Ditto
* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i32.c: Ditto
* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i64.c: Ditto
* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c: Ditto
* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-i16.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-i32.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-i64.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-i8.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h: Refine the
test helper macros to avoid conflict.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_run.h: Ditto.

Signed-off-by: Pan Li 
(cherry picked from commit 4f4eb9b7dd7dad0eec4eae8443a98eeded4fe070)

Diff:
---
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c  |  2 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c  |  2 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [RISC-V] Adjust rvv tests after recent jump threading change

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:1cc79df281ac98d1efcd431ec0da7ae91a1012b7

commit 1cc79df281ac98d1efcd431ec0da7ae91a1012b7
Author: Jeff Law 
Date:   Sun May 4 11:05:44 2025 -0600

[RISC-V] Adjust rvv tests after recent jump threading change

Richi's jump threading patch is resulting in new jump threading 
opportunities
triggering in various vsetvl related tests.  When those new threading
opportunities are realized on vector code we usually end up with a different
number of vsetvls due to the inherent block copying.

At first I was adjusting cases to work with the new jump threads, then 
realized
we could easily end up back here if we change the threading heuristics and
such.  So I just made these tests disable jump threading.  I didn't do it
pervasively, just for those that have been affected.

gcc/testsuite

* gcc.target/riscv/rvv/vsetvl/avl_prop-2.c: Disable jump threading
and adjust number of expected vsetvls as needed.
* gcc.target/riscv/rvv/vsetvl/avl_single-56.c: Likewise.
* gcc.target/riscv/rvv/vsetvl/avl_single-67.c: Likewise.
* gcc.target/riscv/rvv/vsetvl/avl_single-68.c: Likewise.
* gcc.target/riscv/rvv/vsetvl/avl_single-71.c: Likewise.

(cherry picked from commit c2962684e393007d8de59d37b8ac57b0b4843808)

Diff:
---
 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_prop-2.c| 4 ++--
 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-56.c | 2 +-
 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-67.c | 2 +-
 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-68.c | 2 +-
 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-71.c | 6 +++---
 5 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_prop-2.c 
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_prop-2.c
index 0379429a7548..edb12a126647 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_prop-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_prop-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-mrvv-vector-bits=scalable -march=rv64gc_zve32f -mabi=lp64d 
-O3 -mrvv-vector-bits=zvl" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv64gc_zve32f -mabi=lp64d 
-O3 -mrvv-vector-bits=zvl -fno-thread-jumps" } */
 
 int d0, sj, v0, rp, zi;
 
@@ -38,4 +38,4 @@ ka:
   goto ka;
 }
 
-/* { dg-final { scan-assembler-times {vsetivli\tzero,\s*1} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\tzero,\s*1} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-56.c 
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-56.c
index 5db1a402be60..3d3c5d6e9fbc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-56.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-56.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 
-fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 
-fno-schedule-insns -fno-schedule-insns2 -fno-thread-jumps" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-67.c 
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-67.c
index 3f22fc870d93..013d32c55a89 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-67.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-67.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 
-fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 
-fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2 -fno-thread-jumps" 
} */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-68.c 
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-68.c
index 64666d31f1ac..aef832546c78 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-68.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-68.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 
-fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 
-fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2 -fno-thread-jumps" 
} */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-71.c 
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-71.c
index 07a64b43a532..fa4328f97f32 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-71.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-71.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 
-fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-opti

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Separate the test running of rvv vx_vf

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:e6cdd9834132cf9a46557c659df1578231e2bdaf

commit e6cdd9834132cf9a46557c659df1578231e2bdaf
Author: Pan Li 
Date:   Thu May 8 10:00:50 2025 +0800

RISC-V: Separate the test running of rvv vx_vf

The default test running in rvv.exp takes the -fno-vect-cost-model
for most of these options.  It is not that suitable as the vx_vf
test depends on the cost-model.  Thus, separate the vx_vf test
cases without -fno-vect-cost-model in another options.

The below test suites are passed for this patch.
* The rv64gcv fully regression test.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/rvv.exp: Separate test running of
rvv vx_vf.

Signed-off-by: Pan Li 
(cherry picked from commit b81e970de6f6ec6e8d2afa850c9abe07280c91ff)

Diff:
---
 gcc/testsuite/gcc.target/riscv/rvv/rvv.exp | 15 +++
 1 file changed, 15 insertions(+)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp 
b/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp
index 4283d12ccb55..d76a2d7fe74e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp
+++ b/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp
@@ -130,6 +130,21 @@ foreach op $AUTOVEC_TEST_OPTS {
 "$op" ""
   dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/autovec/sat/*.\[cS\]]] \
 "$op" ""
+}
+
+# vx_vf tests
+set AUTOVEC_TEST_OPTS [list \
+  {-ftree-vectorize -O3 -mrvv-vector-bits=zvl -mrvv-max-lmul=m1 -ffast-math} \
+  {-ftree-vectorize -O3 -mrvv-vector-bits=zvl -mrvv-max-lmul=m2 -ffast-math} \
+  {-ftree-vectorize -O3 -mrvv-vector-bits=zvl -mrvv-max-lmul=m4 -ffast-math} \
+  {-ftree-vectorize -O3 -mrvv-vector-bits=zvl -mrvv-max-lmul=m8 -ffast-math} \
+  {-ftree-vectorize -O3 -mrvv-vector-bits=zvl -mrvv-max-lmul=dynamic 
-ffast-math} \
+  {-ftree-vectorize -O3 -mrvv-vector-bits=scalable -mrvv-max-lmul=m1 
-ffast-math} \
+  {-ftree-vectorize -O3 -mrvv-vector-bits=scalable -mrvv-max-lmul=m2 
-ffast-math} \
+  {-ftree-vectorize -O3 -mrvv-vector-bits=scalable -mrvv-max-lmul=m4 
-ffast-math} \
+  {-ftree-vectorize -O3 -mrvv-vector-bits=scalable -mrvv-max-lmul=m8 
-ffast-math} \
+  {-ftree-vectorize -O3 -mrvv-vector-bits=scalable -mrvv-max-lmul=dynamic 
-ffast-math} ]
+foreach op $AUTOVEC_TEST_OPTS {
   dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/autovec/vx_vf/*.\[cS\]]] 
\
 "$op" ""
 }

[gcc(refs/users/mikael/heads/refactor_descriptor_v05)] Correction régression {minloc,maxloc}_nan_1

[Mikael Morin via Gcc-cvs]

https://gcc.gnu.org/g:f288b88ddbeef9452170083380c27f78dd963de4

commit f288b88ddbeef9452170083380c27f78dd963de4
Author: Mikael Morin 
Date:   Sun May 18 16:47:43 2025 +0200

Correction régression {minloc,maxloc}_nan_1

Diff:
---
 libgfortran/generated/maxloc0_16_i1.c  |  6 ++
 libgfortran/generated/maxloc0_16_i16.c |  6 ++
 libgfortran/generated/maxloc0_16_i2.c  |  6 ++
 libgfortran/generated/maxloc0_16_i4.c  |  6 ++
 libgfortran/generated/maxloc0_16_i8.c  |  6 ++
 libgfortran/generated/maxloc0_16_m1.c  |  6 ++
 libgfortran/generated/maxloc0_16_m16.c |  6 ++
 libgfortran/generated/maxloc0_16_m2.c  |  6 ++
 libgfortran/generated/maxloc0_16_m4.c  |  6 ++
 libgfortran/generated/maxloc0_16_m8.c  |  6 ++
 libgfortran/generated/maxloc0_16_r10.c |  6 ++
 libgfortran/generated/maxloc0_16_r16.c |  6 ++
 libgfortran/generated/maxloc0_16_r17.c |  6 ++
 libgfortran/generated/maxloc0_16_r4.c  |  6 ++
 libgfortran/generated/maxloc0_16_r8.c  |  6 ++
 libgfortran/generated/maxloc0_4_i1.c   |  6 ++
 libgfortran/generated/maxloc0_4_i16.c  |  6 ++
 libgfortran/generated/maxloc0_4_i2.c   |  6 ++
 libgfortran/generated/maxloc0_4_i4.c   |  6 ++
 libgfortran/generated/maxloc0_4_i8.c   |  6 ++
 libgfortran/generated/maxloc0_4_m1.c   |  6 ++
 libgfortran/generated/maxloc0_4_m16.c  |  6 ++
 libgfortran/generated/maxloc0_4_m2.c   |  6 ++
 libgfortran/generated/maxloc0_4_m4.c   |  6 ++
 libgfortran/generated/maxloc0_4_m8.c   |  6 ++
 libgfortran/generated/maxloc0_4_r10.c  |  6 ++
 libgfortran/generated/maxloc0_4_r16.c  |  6 ++
 libgfortran/generated/maxloc0_4_r17.c  |  6 ++
 libgfortran/generated/maxloc0_4_r4.c   |  6 ++
 libgfortran/generated/maxloc0_4_r8.c   |  6 ++
 libgfortran/generated/maxloc0_8_i1.c   |  6 ++
 libgfortran/generated/maxloc0_8_i16.c  |  6 ++
 libgfortran/generated/maxloc0_8_i2.c   |  6 ++
 libgfortran/generated/maxloc0_8_i4.c   |  6 ++
 libgfortran/generated/maxloc0_8_i8.c   |  6 ++
 libgfortran/generated/maxloc0_8_m1.c   |  6 ++
 libgfortran/generated/maxloc0_8_m16.c  |  6 ++
 libgfortran/generated/maxloc0_8_m2.c   |  6 ++
 libgfortran/generated/maxloc0_8_m4.c   |  6 ++
 libgfortran/generated/maxloc0_8_m8.c   |  6 ++
 libgfortran/generated/maxloc0_8_r10.c  |  6 ++
 libgfortran/generated/maxloc0_8_r16.c  |  6 ++
 libgfortran/generated/maxloc0_8_r17.c  |  6 ++
 libgfortran/generated/maxloc0_8_r4.c   |  6 ++
 libgfortran/generated/maxloc0_8_r8.c   |  6 ++
 libgfortran/generated/minloc0_16_i1.c  |  6 ++
 libgfortran/generated/minloc0_16_i16.c |  6 ++
 libgfortran/generated/minloc0_16_i2.c  |  6 ++
 libgfortran/generated/minloc0_16_i4.c  |  6 ++
 libgfortran/generated/minloc0_16_i8.c  |  6 ++
 libgfortran/generated/minloc0_16_m1.c  |  6 ++
 libgfortran/generated/minloc0_16_m16.c |  6 ++
 libgfortran/generated/minloc0_16_m2.c  |  6 ++
 libgfortran/generated/minloc0_16_m4.c  |  6 ++
 libgfortran/generated/minloc0_16_m8.c  |  6 ++
 libgfortran/generated/minloc0_16_r10.c |  6 ++
 libgfortran/generated/minloc0_16_r16.c |  6 ++
 libgfortran/generated/minloc0_16_r17.c |  6 ++
 libgfortran/generated/minloc0_16_r4.c  |  6 ++
 libgfortran/generated/minloc0_16_r8.c  |  6 ++
 libgfortran/generated/minloc0_4_i1.c   |  6 ++
 libgfortran/generated/minloc0_4_i16.c  |  6 ++
 libgfortran/generated/minloc0_4_i2.c   |  6 ++
 libgfortran/generated/minloc0_4_i4.c   |  6 ++
 libgfortran/generated/minloc0_4_i8.c   |  6 ++
 libgfortran/generated/minloc0_4_m1.c   |  6 ++
 libgfortran/generated/minloc0_4_m16.c  |  6 ++
 libgfortran/generated/minloc0_4_m2.c   |  6 ++
 libgfortran/generated/minloc0_4_m4.c   |  6 ++
 libgfortran/generated/minloc0_4_m8.c   |  6 ++
 libgfortran/generated/minloc0_4_r10.c  |  6 ++
 libgfortran/generated/minloc0_4_r16.c  |  6 ++
 libgfortran/generated/minloc0_4_r17.c  |  6 ++
 libgfortran/generated/minloc0_4_r4.c   |  6 ++
 libgfortran/generated/minloc0_4_r8.c   |  6 ++
 libgfortran/generated/minloc0_8_i1.c   |  6 ++
 libgfortran/generated/minloc0_8_i16.c  |  6 ++
 libgfortran/generated/minloc0_8_i2.c   |  6 ++
 libgfortran/generated/minloc0_8_i4.c   |  6 ++
 libgfortran/generated/minloc0_8_i8.c   |  6 ++
 libgfortran/generated/minloc0_8_m1.c   |  6 ++
 libgfortran/generated/minloc0_8_m16.c  |  6 ++
 libgfortran/generated/minloc0_8_m2.c   |  6 ++
 libgfortran/generated/minloc0_8_m4.c   |  6 ++
 libgfortran/generated/minloc0_8_m8.c   |  6 ++
 libgfortran/generated/minloc0_8_r10.c  |  6 ++
 libgfortran/generated/minloc0_8_r16.c  |  6 ++
 libgfortran/generated/minloc0_8_r17.c  |  6 ++
 libgfortran/generated/minloc0_8_r4.c   |  6 ++
 libgfortran/generated/minloc0_8_r8.c   |  6 ++
 libgfortran/m4/iforeach.m4 | 12 +---
 91 files changed, 549 inser

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Regen riscv-ext.opt.urls

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:a4d3735c33c133d9eb7d029cf2525f575b7e3f85

commit a4d3735c33c133d9eb7d029cf2525f575b7e3f85
Author: Kito Cheng 
Date:   Wed May 14 23:19:17 2025 +0800

RISC-V: Regen riscv-ext.opt.urls

gcc/ChangeLog:

* config/riscv/riscv-ext.opt.urls: Regenerate.

(cherry picked from commit f05586727dfafd1af9fa303e5a99afdd94770373)

Diff:
---
 gcc/config/riscv/riscv-ext.opt.urls | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/gcc/config/riscv/riscv-ext.opt.urls 
b/gcc/config/riscv/riscv-ext.opt.urls
index e69de29bb2d1..c4f471079df9 100644
--- a/gcc/config/riscv/riscv-ext.opt.urls
+++ b/gcc/config/riscv/riscv-ext.opt.urls
@@ -0,0 +1,2 @@
+; Autogenerated by regenerate-opt-urls.py from gcc/config/riscv/riscv-ext.opt 
and generated HTML
+

[gcc r16-716] phiopt: Use mark_lhs_in_seq_for_dce instead of doing it inline

[Andrew Pinski via Gcc-cvs]

https://gcc.gnu.org/g:98129ff8c08056f6a7d395fbe46d577b856871e7

commit r16-716-g98129ff8c08056f6a7d395fbe46d577b856871e7
Author: Andrew Pinski 
Date:   Sat May 17 17:21:39 2025 -0700

phiopt: Use mark_lhs_in_seq_for_dce instead of doing it inline

Right now phiopt has the same code as mark_lhs_in_seq_for_dce
inlined into match_simplify_replacement. Instead let's use the
function in gimple-fold that does the same thing.

Bootstrapped and tested on x86_64-linux-gnu.

gcc/ChangeLog:

* gimple-fold.cc (mark_lhs_in_seq_for_dce): Make
non-static.
* gimple-fold.h (mark_lhs_in_seq_for_dce): Declare.
* tree-ssa-phiopt.cc (match_simplify_replacement): Use
mark_lhs_in_seq_for_dce instead of manually looping.

Signed-off-by: Andrew Pinski 

Diff:
---
 gcc/gimple-fold.cc |  2 +-
 gcc/gimple-fold.h  |  1 +
 gcc/tree-ssa-phiopt.cc | 13 +++--
 3 files changed, 5 insertions(+), 11 deletions(-)

diff --git a/gcc/gimple-fold.cc b/gcc/gimple-fold.cc
index b74fb8bb50cb..0f437616d770 100644
--- a/gcc/gimple-fold.cc
+++ b/gcc/gimple-fold.cc
@@ -6020,7 +6020,7 @@ has_use_on_stmt (tree name, gimple *stmt)
 
 /* Add the lhs of each statement of SEQ to DCE_WORKLIST. */
 
-static void
+void
 mark_lhs_in_seq_for_dce (bitmap dce_worklist, gimple_seq seq)
 {
   if (!dce_worklist)
diff --git a/gcc/gimple-fold.h b/gcc/gimple-fold.h
index afecbb8ceefc..8b1e246b0c07 100644
--- a/gcc/gimple-fold.h
+++ b/gcc/gimple-fold.h
@@ -264,6 +264,7 @@ gimple_build_round_up (gimple_seq *seq, tree type, tree 
old_size,
 
 extern bool gimple_stmt_nonnegative_warnv_p (gimple *, bool *, int = 0);
 extern bool gimple_stmt_integer_valued_real_p (gimple *, int = 0);
+extern void mark_lhs_in_seq_for_dce (bitmap, gimple_seq);
 
 /* In gimple-match.cc.  */
 extern tree gimple_simplify (enum tree_code, tree, tree,
diff --git a/gcc/tree-ssa-phiopt.cc b/gcc/tree-ssa-phiopt.cc
index 9724040fc3d2..8c5908e5bff9 100644
--- a/gcc/tree-ssa-phiopt.cc
+++ b/gcc/tree-ssa-phiopt.cc
@@ -1001,16 +1001,9 @@ match_simplify_replacement (basic_block cond_bb, 
basic_block middle_bb,
   if (seq)
 {
   // Mark the lhs of the new statements maybe for dce
-  gimple_stmt_iterator gsi1 = gsi_start (seq);
-  for (; !gsi_end_p (gsi1); gsi_next (&gsi1))
-   {
- gimple *stmt = gsi_stmt (gsi1);
- tree name = gimple_get_lhs (stmt);
- if (name && TREE_CODE (name) == SSA_NAME)
-   bitmap_set_bit (exprs_maybe_dce, SSA_NAME_VERSION (name));
-   }
-gsi_insert_seq_before (&gsi, seq, GSI_CONTINUE_LINKING);
-  }
+  mark_lhs_in_seq_for_dce (exprs_maybe_dce, seq);
+  gsi_insert_seq_before (&gsi, seq, GSI_CONTINUE_LINKING);
+}
 
   /* If there was a statement to move, move it to right before
  the original conditional.  */

[gcc(refs/users/mikael/heads/refactor_descriptor_v05)] Correction régression class_67

[Mikael Morin via Gcc-cvs]

https://gcc.gnu.org/g:cb16a9e756c1b6bbe15282a684a21c101ff79d89

commit cb16a9e756c1b6bbe15282a684a21c101ff79d89
Author: Mikael Morin 
Date:   Sun May 18 11:20:40 2025 +0200

Correction régression class_67

Diff:
---
 gcc/fortran/trans-expr.cc | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/gcc/fortran/trans-expr.cc b/gcc/fortran/trans-expr.cc
index ba32bd9bfd07..8b4ad9978755 100644
--- a/gcc/fortran/trans-expr.cc
+++ b/gcc/fortran/trans-expr.cc
@@ -1281,7 +1281,9 @@ gfc_conv_class_to_class (gfc_se *parmse, gfc_expr *e, 
gfc_typespec class_ts,
 }
 
   if ((ref == NULL || class_ref == ref)
-  && !(gfc_is_class_array_function (e) && parmse->class_vptr != NULL_TREE)
+  && !(gfc_is_class_array_function (e)
+  && (parmse->class_vptr != NULL_TREE
+  || parmse->class_container != NULL_TREE))
   && (!class_ts.u.derived->components->as
  || class_ts.u.derived->components->as->rank != -1))
 return;

[gcc(refs/users/mikael/heads/refactor_descriptor_v05)] gimple-exec: Prise en charge TARGET_MEM_REF sans index ni step.

[Mikael Morin via Gcc-cvs]

https://gcc.gnu.org/g:d2dd4bfabe8db40f740b18a6254035d2dc054627

commit d2dd4bfabe8db40f740b18a6254035d2dc054627
Author: Mikael Morin 
Date:   Sun May 18 10:43:40 2025 +0200

gimple-exec: Prise en charge TARGET_MEM_REF sans index ni step.

Diff:
---
 gcc/cgraphunit.cc | 67 +--
 1 file changed, 55 insertions(+), 12 deletions(-)

diff --git a/gcc/cgraphunit.cc b/gcc/cgraphunit.cc
index 816393414a23..adcb505a5890 100644
--- a/gcc/cgraphunit.cc
+++ b/gcc/cgraphunit.cc
@@ -3883,18 +3883,23 @@ exec_context::evaluate (tree expr) const
if (code == TARGET_MEM_REF)
  {
tree index = TREE_OPERAND (expr, 2);
-   data_value val_idx = evaluate (index);
-   gcc_assert (val_idx.classify () == VAL_CONSTANT);
-   wide_int wi_idx = val_idx.get_cst ();
-
tree step = TREE_OPERAND (expr, 3);
-   data_value val_step = evaluate (step);
-   gcc_assert (val_step.classify () == VAL_CONSTANT);
-   wide_int wi_step = val_step.get_cst ();
+   if (index || step)
+ {
+   gcc_assert (index && step);
 
-   wide_int additional_off = wi_idx * wi_step;
-   gcc_assert (wi::fits_uhwi_p (additional_off));
-   offset += additional_off.to_uhwi ();
+   data_value val_idx = evaluate (index);
+   gcc_assert (val_idx.classify () == VAL_CONSTANT);
+   wide_int wi_idx = val_idx.get_cst ();
+
+   data_value val_step = evaluate (step);
+   gcc_assert (val_step.classify () == VAL_CONSTANT);
+   wide_int wi_step = val_step.get_cst ();
+
+   wide_int additional_off = wi_idx * wi_step;
+   gcc_assert (wi::fits_uhwi_p (additional_off));
+   offset += additional_off.to_uhwi ();
+ }
  }
 
return storage_value.get_at (offset * CHAR_BIT + ptr_offset, bit_width);
@@ -4118,8 +4123,8 @@ exec_context::evaluate_binary (enum tree_code code, tree 
type, tree lhs, tree rh
   if (lhs_type == VAL_CONSTANT && rhs_type == VAL_CONSTANT)
 {
   gcc_assert (TREE_TYPE (lhs) == TREE_TYPE (rhs)
- || (TREE_CODE (rhs) == INTEGER_CST
- && TREE_CODE (TREE_TYPE (lhs)) == INTEGER_TYPE
+ || (TREE_CODE (TREE_TYPE (lhs)) == INTEGER_TYPE
+ && TREE_CODE (TREE_TYPE (rhs)) == INTEGER_TYPE
  && TYPE_PRECISION (TREE_TYPE (lhs))
 == TYPE_PRECISION (TREE_TYPE (rhs))
  && TYPE_UNSIGNED (TREE_TYPE (lhs))
@@ -7050,6 +7055,44 @@ exec_context_evaluate_tests ()
   wide_int wi5 = val5.get_cst ();
   ASSERT_PRED1 (wi::fits_uhwi_p, wi5);
   ASSERT_EQ (wi5.to_uhwi (), 19);
+
+
+  tree c19 = build_array_type_nelts (char_type_node, 19);
+  tree a19 = create_var (c19, "a19");
+  tree ssa101 = make_node (SSA_NAME);
+  TREE_TYPE (ssa101) = size_type_node;
+  tree ssa102 = make_node (SSA_NAME);
+  TREE_TYPE (ssa102) = size_type_node;
+
+  vec decls10{};
+  decls10.safe_push (a19);
+  decls10.safe_push (ssa101);
+  decls10.safe_push (ssa102);
+
+  context_builder builder10;
+  builder10.add_decls (&decls10);
+  exec_context ctx10 = builder10.build (mem, printer);
+
+  data_storage * strg19 = ctx10.find_reachable_var (a19);
+  gcc_assert (strg19 != nullptr);
+
+  tree ref19 = build5 (TARGET_MEM_REF, char_type_node,
+  build1 (ADDR_EXPR, ptr_type_node, a19),
+  build_zero_cst (ptr_type_node),
+  NULL_TREE, NULL_TREE, NULL_TREE);
+
+  wide_int cst23 = wi::shwi (23, CHAR_BIT);
+  data_value tmp19_0 (CHAR_BIT);
+  tmp19_0.set_cst (cst23);
+  strg19->set_at (tmp19_0, 0);
+
+  data_value val19_0 = ctx10.evaluate (ref19);
+
+  ASSERT_EQ (val19_0.get_bitwidth (), CHAR_BIT);
+  ASSERT_EQ (val19_0.classify (), VAL_CONSTANT);
+  wide_int wi19_0 = val19_0.get_cst ();
+  ASSERT_PRED1 (wi::fits_uhwi_p, wi19_0);
+  ASSERT_EQ  (wi19_0.to_uhwi (), 23);
 }

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Extract vector duplicate for expand_const_vector [NFC]

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:11dcc4942eb0edf04ebe897427a938640e56bea2

commit 11dcc4942eb0edf04ebe897427a938640e56bea2
Author: Pan Li 
Date:   Wed Apr 16 15:47:21 2025 +0800

RISC-V: Extract vector duplicate for expand_const_vector [NFC]

Consider the expand_const_vector is quit long (about 500 lines)
and complicated, we would like to extract the different case
into different functions.  For example, the const vector duplicate
will be extracted into expand_const_vector_duplicate, and then
expand_const_vector_duplicate_repeating and
expand_const_vector_duplicate_default for the underlying function.

The below test suites are passed for this patch.
* The rv64gcv fully regression test.

gcc/ChangeLog:

* config/riscv/riscv-v.cc (expand_const_vector_duplicate_repeating):
Add new func to take care of vector duplicate with repeating.
(expand_const_vector_duplicate_default): Add new func to take
care of default const vector duplicate.
(expand_const_vector_duplicate): Add new func to take care
of all const vector duplicate.
(expand_const_vector): Extract const vector duplicate into
separated function.

Signed-off-by: Pan Li 
(cherry picked from commit cf0283a8ed035e382a3870a8dce554acf7dfc82e)

Diff:
---
 gcc/config/riscv/riscv-v.cc | 180 +---
 1 file changed, 104 insertions(+), 76 deletions(-)

diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index e0af296449c3..96f0b94e6140 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -1236,6 +1236,109 @@ expand_const_vec_series (rtx target, rtx base, rtx step)
 emit_move_insn (target, result);
 }
 
+
+/* We handle the case that we can find a vector container to hold
+   element bitsize = NPATTERNS * ele_bitsize.
+
+ NPATTERNS = 8, element width = 8
+   v = { 0, 1, 2, 3, 4, 5, 6, 7, ... }
+ In this case, we can combine NPATTERNS element into a larger
+ element.  Use element width = 64 and broadcast a vector with
+ all element equal to 0x0706050403020100.  */
+
+static void
+expand_const_vector_duplicate_repeating (rtx target, rvv_builder *builder)
+{
+  machine_mode mode = GET_MODE (target);
+  rtx result = register_operand (target, mode) ? target : gen_reg_rtx (mode);
+  rtx ele = builder->get_merged_repeating_sequence ();
+  rtx dup;
+
+  if (lra_in_progress)
+{
+  dup = gen_reg_rtx (builder->new_mode ());
+  rtx ops[] = {dup, ele};
+  emit_vlmax_insn (code_for_pred_broadcast (builder->new_mode ()),
+  UNARY_OP, ops);
+}
+  else
+dup = expand_vector_broadcast (builder->new_mode (), ele);
+
+  emit_move_insn (result, gen_lowpart (mode, dup));
+
+  if (result != target)
+emit_move_insn (target, result);
+}
+
+/* We handle the case that we can't find a vector container to hold
+   element bitsize = NPATTERNS * ele_bitsize.
+
+ NPATTERNS = 8, element width = 16
+   v = { 0, 1, 2, 3, 4, 5, 6, 7, ... }
+ Since NPATTERNS * element width = 128, we can't find a container
+ to hold it.
+
+ In this case, we use NPATTERNS merge operations to generate such
+ vector.  */
+
+static void
+expand_const_vector_duplicate_default (rtx target, rvv_builder *builder)
+{
+  machine_mode mode = GET_MODE (target);
+  rtx result = register_operand (target, mode) ? target : gen_reg_rtx (mode);
+  unsigned int nbits = builder->npatterns () - 1;
+
+  /* Generate vid = { 0, 1, 2, 3, 4, 5, 6, 7, ... }.  */
+  rtx vid = gen_reg_rtx (builder->int_mode ());
+  rtx op[] = {vid};
+  emit_vlmax_insn (code_for_pred_series (builder->int_mode ()), NULLARY_OP, 
op);
+
+  /* Generate vid_repeat = { 0, 1, ... nbits, ... }  */
+  rtx vid_repeat = gen_reg_rtx (builder->int_mode ());
+  rtx and_ops[] = {vid_repeat, vid,
+  gen_int_mode (nbits, builder->inner_int_mode ())};
+  emit_vlmax_insn (code_for_pred_scalar (AND, builder->int_mode ()), BINARY_OP,
+  and_ops);
+
+  rtx tmp1 = gen_reg_rtx (builder->mode ());
+  rtx dup_ops[] = {tmp1, builder->elt (0)};
+  emit_vlmax_insn (code_for_pred_broadcast (builder->mode ()), UNARY_OP,
+  dup_ops);
+
+  for (unsigned int i = 1; i < builder->npatterns (); i++)
+{
+  /* Generate mask according to i.  */
+  rtx mask = gen_reg_rtx (builder->mask_mode ());
+  rtx const_vec = gen_const_vector_dup (builder->int_mode (), i);
+  expand_vec_cmp (mask, EQ, vid_repeat, const_vec);
+
+  /* Merge scalar to each i.  */
+  rtx tmp2 = gen_reg_rtx (builder->mode ());
+  rtx merge_ops[] = {tmp2, tmp1, builder->elt (i), mask};
+  insn_code icode = code_for_pred_merge_scalar (builder->mode ());
+  emit_vlmax_insn (icode, MERGE_OP, merge_ops);
+  tmp1 = tmp2;
+}
+
+  emit_move_insn (result, tmp1);
+
+  if (result != target)
+emit_move_insn (target, result);
+}
+

[gcc r16-715] Regenerate cobol/lang.opt.urls

[Mark Wielaard via Gcc-cvs]

https://gcc.gnu.org/g:f32946cc54a7de59498b42e3450ff124dffeb2d7

commit r16-715-gf32946cc54a7de59498b42e3450ff124dffeb2d7
Author: Mark Wielaard 
Date:   Sun May 18 16:20:10 2025 +0200

Regenerate cobol/lang.opt.urls

The Cobol frontend lang.opt got -M added, but lang.opt.urls wasn't
regenerated.

Fixes: 92b6485a75ca ("cobol: Eliminate exception "blob"; streamline some 
code generation.")

gcc/cobol/ChangeLog:

* lang.opt.urls: Regenerated.

Diff:
---
 gcc/cobol/lang.opt.urls | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/gcc/cobol/lang.opt.urls b/gcc/cobol/lang.opt.urls
index 69f52973c025..78fc491fa67f 100644
--- a/gcc/cobol/lang.opt.urls
+++ b/gcc/cobol/lang.opt.urls
@@ -10,6 +10,9 @@ UrlSuffix(gcc/Preprocessor-Options.html#index-D-1)
 I
 UrlSuffix(gcc/Directory-Options.html#index-I) 
LangUrlSuffix_D(gdc/Directory-Options.html#index-I)
 
+M
+UrlSuffix(gcc/Preprocessor-Options.html#index-M) 
LangUrlSuffix_D(gdc/Code-Generation.html#index-M)
+
 ffixed-form
 LangUrlSuffix_Fortran(gfortran/Fortran-Dialect-Options.html#index-ffixed-form)

[gcc r16-718] emit-rtl: Allow extra checks for paradoxical subregs [PR119966]

[Dimitar Dimitrov via Gcc-cvs]

https://gcc.gnu.org/g:eb2ea476db2182939f585df7d806225649ee4f62

commit r16-718-geb2ea476db2182939f585df7d806225649ee4f62
Author: Dimitar Dimitrov 
Date:   Sat May 3 22:38:30 2025 +0300

emit-rtl: Allow extra checks for paradoxical subregs [PR119966]

When a paradoxical subreg is detected, validate_subreg exits early, thus
skipping the important checks later in the function.

Fix by continuing with the checks instead of declaring early that the
paradoxical subreg is valid.

One of the newly allowed subsequent checks needed to be disabled for
paradoxical subregs.  It turned out that combine attempts to create
a paradoxical subreg of mem even for strict-alignment targets.
That is invalid and should eventually be rejected, but is
temporarily left allowed to prevent regressions for
armv8l-unknown-linux-gnueabihf.  See PR120329 for more details.

Tests I did:
 - No regressions were found for C and C++ for the following targets:
   - native x86_64-pc-linux-gnu
   - cross riscv64-unknown-linux-gnu
   - cross riscv32-none-elf
 - Sanity checked armv8l-unknown-linux-gnueabihf by cross-building
   up to including libgcc.  Linaro CI bot further confirmed there
   are no regressions.
 - Sanity checked powerpc64-unknown-linux-gnu by building native
   toolchain, but I could not setup qemu-user for DejaGnu testing.

PR target/119966

gcc/ChangeLog:

* emit-rtl.cc (validate_subreg): Do not exit immediately for
paradoxical subregs.  Filter subsequent tests which are
not valid for paradoxical subregs.

Co-authored-by: Richard Sandiford 
Signed-off-by: Dimitar Dimitrov 

Diff:
---
 gcc/emit-rtl.cc | 25 ++---
 1 file changed, 18 insertions(+), 7 deletions(-)

diff --git a/gcc/emit-rtl.cc b/gcc/emit-rtl.cc
index fc7b6c7e2977..6c838d7afcc6 100644
--- a/gcc/emit-rtl.cc
+++ b/gcc/emit-rtl.cc
@@ -969,10 +969,10 @@ validate_subreg (machine_mode omode, machine_mode imode,
 }
 
   /* Paradoxical subregs must have offset zero.  */
-  if (maybe_gt (osize, isize))
-return known_eq (offset, 0U);
+  if (maybe_gt (osize, isize) && !known_eq (offset, 0U))
+return false;
 
-  /* This is a normal subreg.  Verify that the offset is representable.  */
+  /* Verify that the offset is representable.  */
 
   /* For hard registers, we already have most of these rules collected in
  subreg_offset_representable_p.  */
@@ -988,9 +988,13 @@ validate_subreg (machine_mode omode, machine_mode imode,
 
   return subreg_offset_representable_p (regno, imode, offset, omode);
 }
-  /* Do not allow SUBREG with stricter alignment than the inner MEM.  */
+  /* Do not allow normal SUBREG with stricter alignment than the inner MEM.
+
+ PR120329: Combine can create paradoxical mem subregs even for
+ strict-alignment targets.  Allow it until combine is fixed.  */
   else if (reg && MEM_P (reg) && STRICT_ALIGNMENT
-  && MEM_ALIGN (reg) < GET_MODE_ALIGNMENT (omode))
+  && MEM_ALIGN (reg) < GET_MODE_ALIGNMENT (omode)
+  && known_le (osize, isize))
 return false;
 
   /* The outer size must be ordered wrt the register size, otherwise
@@ -999,7 +1003,7 @@ validate_subreg (machine_mode omode, machine_mode imode,
   if (!ordered_p (osize, regsize))
 return false;
 
-  /* For pseudo registers, we want most of the same checks.  Namely:
+  /* For normal pseudo registers, we want most of the same checks.  Namely:
 
  Assume that the pseudo register will be allocated to hard registers
  that can hold REGSIZE bytes each.  If OSIZE is not a multiple of REGSIZE,
@@ -1008,8 +1012,15 @@ validate_subreg (machine_mode omode, machine_mode imode,
  otherwise it is at the lowest offset.
 
  Given that we've already checked the mode and offset alignment,
- we only have to check subblock subregs here.  */
+ we only have to check subblock subregs here.
+
+ For paradoxical little-endian registers, this check is redundant.  The
+ offset has already been validated to be zero.
+
+ For paradoxical big-endian registers, this check is not valid
+ because the offset is zero.  */
   if (maybe_lt (osize, regsize)
+  && known_le (osize, isize)
   && ! (lra_in_progress && (FLOAT_MODE_P (imode) || FLOAT_MODE_P (omode
 {
   /* It is invalid for the target to pick a register size for a mode

[gcc r16-722] i386: Remove duplicate iterators in md

[Haochen Jiang via Gcc-cvs]

https://gcc.gnu.org/g:5bdb72212919e1335838d32cee81a7981b5a1da1

commit r16-722-g5bdb72212919e1335838d32cee81a7981b5a1da1
Author: Haochen Jiang 
Date:   Fri Mar 14 14:27:36 2025 +0800

i386: Remove duplicate iterators in md

There are several iterators no longer needed in md files since
after refactor in AVX10, they could directly use legacy AVX512
ones. Remove those duplicate iterators.

gcc/ChangeLog:

* config/i386/sse.md (VF1_VF2_AVX10_2): Removed.
(VF2_AVX10_2): Ditto.
(VI1248_AVX10_2): Ditto.
(VFH_AVX10_2): Ditto.
(VF1_AVX10_2): Ditto.
(VHF_AVX10_2): Ditto.
(VBF_AVX10_2): Ditto.
(VI8_AVX10_2): Ditto.
(VI2_AVX10_2): Ditto.
(VBF): New.
(div3): Use VBF instead of AVX10.2 ones.
(vec_cmp): Ditto.
(avx10_2_cvt2ps2phx_):
Use VHF_AVX512VL instead of AVX10.2 ones.
(vcvt): Ditto.
(vcvthf82ph): Ditto.
(VHF_AVX10_2_2): Remove not needed TARGET_AVX10_2.
(usdot_prod): Use VI2_AVX512F
instead of AVX10.2 ones.
(vdpphps_): Use VF1_AVX512VL instead of AVX10.2 ones.
(vdpphps__mask): Ditto.
(vdpphps__maskz): Ditto.
(vdpphps__maskz_1): Ditto.
(avx10_2_scalefbf16_): Use VBF instead of
AVX10.2 ones.
(3): Ditto.
(avx10_2_bf16_): Ditto.
(avx10_2_fmaddbf16__maskz); Ditto.
(avx10_2_fmaddbf16_): Ditto.
(avx10_2_fmaddbf16__mask): Ditto.
(avx10_2_fmaddbf16__mask3): Ditto.
(avx10_2_fnmaddbf16__maskz): Ditto.
(avx10_2_fnmaddbf16_): Ditto.
(avx10_2_fnmaddbf16__mask): Ditto.
(avx10_2_fnmaddbf16__mask3): Ditto.
(avx10_2_fmsubbf16__maskz); Ditto.
(avx10_2_fmsubbf16_): Ditto.
(avx10_2_fmsubbf16__mask): Ditto.
(avx10_2_fmsubbf16__mask3): Ditto.
(avx10_2_fnmsubbf16__maskz): Ditto.
(avx10_2_fnmsubbf16_): Ditto.
(avx10_2_fnmsubbf16__mask): Ditto.
(avx10_2_fnmsubbf16__mask3): Ditto.
(avx10_2_rsqrtbf16_): Ditto.
(avx10_2_sqrtbf16_): Ditto.
(avx10_2_rcpbf16_): Ditto.
(avx10_2_getexpbf16_): Ditto.
(avx10_2_bf16_): Ditto.
(avx10_2_fpclassbf16_): Ditto.
(avx10_2_cmpbf16_): Ditto.

(avx10_2_cvtbf162ibs):
Ditto.

(avx10_2_cvtph2ibs):
Use VHF_AVX512VL instead of AVX10.2 ones.

(avx10_2_cvttph2ibs):
Ditto.

(avx10_2_cvtps2ibs):
Use VF1_AVX512VL instead of AVX10.2 ones.

(avx10_2_cvttps2ibs):
Ditto.

(avx10_2_vcvtt2dqs):
Use VF instead of AVX10.2 ones.

(avx10_2_vcvttpd2qqs):
Use VF2 instead of AVX10.2 ones.

(avx10_2_vcvttps2qqs):
Use VI8 instead of AVX10.2 ones.
(avx10_2_minmaxbf16_): Use VBF instead of
AVX10.2 ones.
(avx10_2_minmaxp):
Use VFH_AVX512VL instead of AVX10.2 ones.
(avx10_2_vmovrs):
Use VI1248_AVX512VLBW instead of AVX10.2 ones.

Diff:
---
 gcc/config/i386/sse.md | 412 +++--
 1 file changed, 191 insertions(+), 221 deletions(-)

diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index a546479618a5..aea5e2cad7e1 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -375,10 +375,6 @@
(V4DF "TARGET_AVX512DQ && TARGET_AVX512VL")
(V2DF "TARGET_AVX512DQ && TARGET_AVX512VL")])
 
-(define_mode_iterator VF1_VF2_AVX10_2
-  [(V16SF "TARGET_AVX10_2") V8SF V4SF
-   (V8DF "TARGET_AVX10_2") V4DF V2DF])
-
 (define_mode_iterator VFH
   [(V32HF "TARGET_AVX512FP16")
(V16HF "TARGET_AVX512FP16 && TARGET_AVX512VL")
@@ -440,9 +436,6 @@
 (define_mode_iterator VF2
   [(V8DF "TARGET_AVX512F") (V4DF "TARGET_AVX") V2DF])
 
-(define_mode_iterator VF2_AVX10_2
-  [(V8DF "TARGET_AVX10_2") V4DF V2DF])
-
 ;; All DFmode & HFmode & BFmode vector float modes
 (define_mode_iterator VF2HB
   [(V32BF "TARGET_AVX10_2") (V16BF "TARGET_AVX10_2")
@@ -499,12 +492,6 @@
V16SI (V8SI "TARGET_AVX512VL") (V4SI "TARGET_AVX512VL")
V8DI (V4DI "TARGET_AVX512VL") (V2DI "TARGET_AVX512VL")])
 
-(define_mode_iterator VI1248_AVX10_2
-  [(V64QI "TARGET_AVX10_2") V32QI V16QI
-   (V32HI "TARGET_AVX10_2") V16HI V8HI
-   (V16SI "TARGET_AVX10_2") V8SI V4SI
-   (V8DI "TARGET_AVX10_2") V4DI V2DI])
-
 (define_mode_iterator VF_AVX512VL
   [V16SF (V8SF "TARGET_AVX512VL") (V4SF "TARGET_AVX512VL")
V8DF (V4DF "TARGET_AVX512VL") (V2DF "TARGET_AVX512VL")])
@@ -526,11 +513,6 @@
 (define_mode_iterator V8_AVX512VL_2
   [(V2DF "TARGET_AVX512VL") (V2DI "TARGET_AVX512VL")])
 
-(define_mode_iterator VFH_AVX10_2
-  [(V32HF "TARGET_AVX10_2") V16HF V8HF
-

[gcc r16-724] i386: Refactor AVX10.2 runtime test

[Haochen Jiang via Gcc-cvs]

https://gcc.gnu.org/g:34caeae39f67d8a2423e8b2086c433b44d504afb

commit r16-724-g34caeae39f67d8a2423e8b2086c433b44d504afb
Author: Haochen Jiang 
Date:   Mon Mar 24 17:02:44 2025 +0800

i386: Refactor AVX10.2 runtime test

Since everything is under avx10.2, we could use a header
file plus a file actually run all the tests for runtime
test.

gcc/testsuite/ChangeLog:

* gcc.target/i386/avx10-check.h: Remove AVX10_512BIT.
* gcc.target/i386/avx10-minmax-helper.h: Ditto.
* gcc.target/i386/avx10_2-vaddbf16-2.c: Add 512 test.
* gcc.target/i386/avx10_2-vcmpbf16-2.c: Ditto.
* gcc.target/i386/avx10_2-vcvt2ph2bf8-2.c: Ditto.
* gcc.target/i386/avx10_2-vcvt2ph2bf8s-2.c: Ditto.
* gcc.target/i386/avx10_2-vcvt2ph2hf8-2.c: Ditto.
* gcc.target/i386/avx10_2-vcvt2ph2hf8s-2.c: Ditto.
* gcc.target/i386/avx10_2-vcvt2ps2phx-2.c: Ditto.
* gcc.target/i386/avx10_2-vcvtbf162ibs-2.c: Ditto.
* gcc.target/i386/avx10_2-vcvtbf162iubs-2.c: Ditto.
* gcc.target/i386/avx10_2-vcvtbiasph2bf8-2.c: Ditto.
* gcc.target/i386/avx10_2-vcvtbiasph2bf8s-2.c: Ditto.
* gcc.target/i386/avx10_2-vcvtbiasph2hf8-2.c: Ditto.
* gcc.target/i386/avx10_2-vcvtbiasph2hf8s-2.c: Ditto.
* gcc.target/i386/avx10_2-vcvthf82ph-2.c: Ditto.
* gcc.target/i386/avx10_2-vcvtph2bf8-2.c: Ditto.
* gcc.target/i386/avx10_2-vcvtph2bf8s-2.c: Ditto.
* gcc.target/i386/avx10_2-vcvtph2hf8-2.c: Ditto.
* gcc.target/i386/avx10_2-vcvtph2hf8s-2.c: Ditto.
* gcc.target/i386/avx10_2-vcvtph2ibs-2.c: Ditto.
* gcc.target/i386/avx10_2-vcvtph2iubs-2.c: Ditto.
* gcc.target/i386/avx10_2-vcvtps2ibs-2.c: Ditto.
* gcc.target/i386/avx10_2-vcvtps2iubs-2.c: Ditto.
* gcc.target/i386/avx10_2-vcvttbf162ibs-2.c: Ditto.
* gcc.target/i386/avx10_2-vcvttbf162iubs-2.c: Ditto.
* gcc.target/i386/avx10_2-vcvttpd2dqs-2.c: Ditto.
* gcc.target/i386/avx10_2-vcvttpd2qqs-2.c: Ditto.
* gcc.target/i386/avx10_2-vcvttpd2udqs-2.c: Ditto.
* gcc.target/i386/avx10_2-vcvttpd2uqqs-2.c: Ditto.
* gcc.target/i386/avx10_2-vcvttph2ibs-2.c: Ditto.
* gcc.target/i386/avx10_2-vcvttph2iubs-2.c: Ditto.
* gcc.target/i386/avx10_2-vcvttps2dqs-2.c: Ditto.
* gcc.target/i386/avx10_2-vcvttps2ibs-2.c: Ditto.
* gcc.target/i386/avx10_2-vcvttps2iubs-2.c: Ditto.
* gcc.target/i386/avx10_2-vcvttps2qqs-2.c: Ditto.
* gcc.target/i386/avx10_2-vcvttps2udqs-2.c: Ditto.
* gcc.target/i386/avx10_2-vcvttps2uqqs-2.c: Ditto.
* gcc.target/i386/avx10_2-vdivbf16-2.c: Ditto.
* gcc.target/i386/avx10_2-vdpphps-2.c: Ditto.
* gcc.target/i386/avx10_2-vfmaddXXXbf16-2.c: Ditto.
* gcc.target/i386/avx10_2-vfmsubXXXbf16-2.c: Ditto.
* gcc.target/i386/avx10_2-vfnmaddXXXbf16-2.c: Ditto.
* gcc.target/i386/avx10_2-vfnmsubXXXbf16-2.c: Ditto.
* gcc.target/i386/avx10_2-vfpclassbf16-2.c: Ditto.
* gcc.target/i386/avx10_2-vgetexpbf16-2.c: Ditto.
* gcc.target/i386/avx10_2-vgetmantbf16-2.c: Ditto.
* gcc.target/i386/avx10_2-vmaxbf16-2.c: Ditto.
* gcc.target/i386/avx10_2-vminbf16-2.c: Ditto.
* gcc.target/i386/avx10_2-vminmaxbf16-2.c: Ditto.
* gcc.target/i386/avx10_2-vminmaxpd-2.c: Ditto.
* gcc.target/i386/avx10_2-vminmaxph-2.c: Ditto.
* gcc.target/i386/avx10_2-vminmaxps-2.c: Ditto.
* gcc.target/i386/avx10_2-vmpsadbw-2.c: Ditto.
* gcc.target/i386/avx10_2-vmulbf16-2.c: Ditto.
* gcc.target/i386/avx10_2-vpdpbssd-2.c: Ditto.
* gcc.target/i386/avx10_2-vpdpbssds-2.c: Ditto.
* gcc.target/i386/avx10_2-vpdpbsud-2.c: Ditto.
* gcc.target/i386/avx10_2-vpdpbsuds-2.c: Ditto.
* gcc.target/i386/avx10_2-vpdpbuud-2.c: Ditto.
* gcc.target/i386/avx10_2-vpdpbuuds-2.c: Ditto.
* gcc.target/i386/avx10_2-vpdpwsud-2.c: Ditto.
* gcc.target/i386/avx10_2-vpdpwsuds-2.c: Ditto.
* gcc.target/i386/avx10_2-vpdpwusd-2.c: Ditto.
* gcc.target/i386/avx10_2-vpdpwusds-2.c: Ditto.
* gcc.target/i386/avx10_2-vpdpwuud-2.c: Ditto.
* gcc.target/i386/avx10_2-vpdpwuuds-2.c: Ditto.
* gcc.target/i386/avx10_2-vrcpbf16-2.c: Ditto.
* gcc.target/i386/avx10_2-vreducebf16-2.c: Ditto.
* gcc.target/i386/avx10_2-vrndscalebf16-2.c: Ditto.
* gcc.target/i386/avx10_2-vrsqrtbf16-2.c: Ditto.
* gcc.target/i386/avx10_2-vscalefbf16-2.c: Ditto.
* gcc.target/i386/avx10_2-vsqrtbf16-2.c: Ditto.
* gcc.target/i386/avx10_2-vsubbf16-2.c: Ditto.
* gcc.target/i386/avx5

[gcc r16-726] RISC-V: Add new operand constraint: cR

[Kito Cheng via Gcc-cvs]

https://gcc.gnu.org/g:c9eb473fb9946f642506d24f4131d7c83855fd78

commit r16-726-gc9eb473fb9946f642506d24f4131d7c83855fd78
Author: Kito Cheng 
Date:   Mon May 12 14:36:07 2025 +0800

RISC-V: Add new operand constraint: cR

This commit introduces a new operand constraint `cR` for the RISC-V
architecture, which allows the use of an even-odd RVC general purpose 
register
(x8-x15) in inline asm.

Ref: https://github.com/riscv-non-isa/riscv-c-api-doc/pull/102

gcc/ChangeLog:

* config/riscv/constraints.md (cR): New constraint.
* doc/md.texi (Machine Constraints::RISC-V): Document the new cR
constraint.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/constraint-cR-pair.c: New test case.

Diff:
---
 gcc/config/riscv/constraints.md |  4 
 gcc/doc/md.texi |  3 +++
 gcc/testsuite/gcc.target/riscv/constraint-cR-pair.c | 13 +
 3 files changed, 20 insertions(+)

diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md
index 18556a591411..58355cf03f2f 100644
--- a/gcc/config/riscv/constraints.md
+++ b/gcc/config/riscv/constraints.md
@@ -43,6 +43,10 @@
 (define_register_constraint "cf" "TARGET_HARD_FLOAT ? RVC_FP_REGS : 
(TARGET_ZFINX ? RVC_GR_REGS : NO_REGS)"
   "RVC floating-point registers (f8-f15), if available, reuse GPR as FPR when 
use zfinx.")
 
+(define_register_constraint "cR" "RVC_GR_REGS"
+  "Even-odd RVC general purpose register (x8-x15)."
+  "regno % 2 == 0")
+
 ;; General constraints
 
 (define_constraint "I"
diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
index f6314af46923..1a1c1b730897 100644
--- a/gcc/doc/md.texi
+++ b/gcc/doc/md.texi
@@ -3694,6 +3694,9 @@ RVC general purpose register (x8-x15).
 RVC floating-point registers (f8-f15), if available, reuse GPR as FPR when use
 zfinx.
 
+@item cR
+Even-odd RVC general purpose register pair.
+
 @item R
 Even-odd general purpose register pair.
 
diff --git a/gcc/testsuite/gcc.target/riscv/constraint-cR-pair.c 
b/gcc/testsuite/gcc.target/riscv/constraint-cR-pair.c
new file mode 100644
index ..479246b632a7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/constraint-cR-pair.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-flto" } { "" } } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+void foo(int a0, int a1, int a2, int a3, int a4, int a5, int a6, int a7, int 
m0, int m1) {
+/*
+** foo:
+**   ...
+**   addi\s*t0,\s*(a[024]|s0),\s*(a[024]|s0)
+**   ...
+*/
+__asm__ volatile("addi t0, %0, %0" : : "cR" (m0) : "memory");
+}

[gcc r16-727] regcprop: Return from copy_value for unordered modes

[Jennifer Schmitz via Gcc-cvs]

https://gcc.gnu.org/g:2ec5082dd24cef5149ba645ee88a9acd8b4c290a

commit r16-727-g2ec5082dd24cef5149ba645ee88a9acd8b4c290a
Author: Jennifer Schmitz 
Date:   Thu May 15 07:16:15 2025 -0700

regcprop: Return from copy_value for unordered modes

The ICE in PR120276 resulted from a comparison of VNx4QI and V8QI using
partial_subreg_p in the function copy_value during the RTL pass
regcprop, failing the assertion in

inline bool
partial_subreg_p (machine_mode outermode, machine_mode innermode)
{
  /* Modes involved in a subreg must be ordered.  In particular, we must
 always know at compile time whether the subreg is paradoxical.  */
  poly_int64 outer_prec = GET_MODE_PRECISION (outermode);
  poly_int64 inner_prec = GET_MODE_PRECISION (innermode);
  gcc_checking_assert (ordered_p (outer_prec, inner_prec));
  return maybe_lt (outer_prec, inner_prec);
}

Returning from the function if the modes are not ordered before reaching
the call to partial_subreg_p resolves the ICE and passes bootstrap and
testing without regression.
OK for mainline?

Signed-off-by: Jennifer Schmitz 

gcc/
PR middle-end/120276
* regcprop.cc (copy_value): Return in case of unordered modes.

gcc/testsuite/
PR middle-end/120276
* gcc.dg/torture/pr120276.c: New test.

Diff:
---
 gcc/regcprop.cc |  4 
 gcc/testsuite/gcc.dg/torture/pr120276.c | 20 
 2 files changed, 24 insertions(+)

diff --git a/gcc/regcprop.cc b/gcc/regcprop.cc
index 4fa1305526cc..98ab3f77e835 100644
--- a/gcc/regcprop.cc
+++ b/gcc/regcprop.cc
@@ -332,6 +332,10 @@ copy_value (rtx dest, rtx src, struct value_data *vd)
   if (vd->e[sr].mode == VOIDmode)
 set_value_regno (sr, vd->e[dr].mode, vd);
 
+  else if (!ordered_p (GET_MODE_PRECISION (vd->e[sr].mode),
+  GET_MODE_PRECISION (GET_MODE (src
+return;
+
   /* If we are narrowing the input to a smaller number of hard regs,
  and it is in big endian, we are really extracting a high part.
  Since we generally associate a low part of a value with the value itself,
diff --git a/gcc/testsuite/gcc.dg/torture/pr120276.c 
b/gcc/testsuite/gcc.dg/torture/pr120276.c
new file mode 100644
index ..9717a7103e5e
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/torture/pr120276.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=armv8.2-a+sve" { target aarch64*-*-* } } */
+
+int a;
+char b[1];
+int c[18];
+void d(char *);
+void e() {
+  int f;
+  char *g;
+  a = 0;
+  for (; a < 18; a++) {
+int h = f = 0;
+for (; f < 4; f++) {
+  g[a * 4 + f] = c[a] >> h;
+  h += 8;
+}
+  }
+  d(b);
+}
\ No newline at end of file

[gcc r16-728] RISC-V: Support Zilsd code gen

[Kito Cheng via Gcc-cvs]

https://gcc.gnu.org/g:a3e78dda4d51bc37adcfa088237e2b8567e76da2

commit r16-728-ga3e78dda4d51bc37adcfa088237e2b8567e76da2
Author: Kito Cheng 
Date:   Mon May 12 02:38:39 2025 -0700

RISC-V: Support Zilsd code gen

This commit adds the code gen support for Zilsd, which is a
newly added extension for RISC-V. The Zilsd extension allows
for loading and storing 64-bit values using even-odd register
pairs.

We only try to do miminal code gen support for that, which means only
use the new instructions when the load store is 64 bits data, we can use
that to optimize the code gen of memcpy/memset/memmove and also the
prologue and epilogue of functions, but I think that probably should be
done in a follow up patch.

gcc/ChangeLog:

* config/riscv/riscv.cc (riscv_legitimize_move): Handle
load/store with odd-even reg pair.
(riscv_split_64bit_move_p): Don't split load/store if zilsd enabled.
(riscv_hard_regno_mode_ok): Only allow even reg can be used for
64 bits mode for zilsd.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/zilsd-code-gen.c: New test.

Diff:
---
 gcc/config/riscv/riscv.cc   | 39 +
 gcc/testsuite/gcc.target/riscv/zilsd-code-gen.c | 18 
 2 files changed, 57 insertions(+)

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 8d84bee46882..54395b8d3a74 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -3740,6 +3740,26 @@ riscv_legitimize_move (machine_mode mode, rtx dest, rtx 
src)
   return true;
 }
 
+  if (TARGET_ZILSD
+  && (GET_MODE_UNIT_SIZE (mode) == (UNITS_PER_WORD * 2))
+  && ((REG_P (dest) && MEM_P (src))
+ || (MEM_P (dest) && REG_P (src)))
+  && can_create_pseudo_p ())
+{
+  rtx reg = REG_P (dest) ? dest : src;
+  unsigned regno = REGNO (reg);
+  /* ZILSD requires an even-odd register pair, let RA to
+fix the constraint if the reg is hard reg and not even reg.  */
+  if ((regno < FIRST_PSEUDO_REGISTER)
+ && (regno % 2) != 0)
+   {
+ rtx tmp = gen_reg_rtx (GET_MODE (reg));
+ emit_move_insn (tmp, src);
+ emit_move_insn (dest, tmp);
+ return true;
+   }
+}
+
   /* RISC-V GCC may generate non-legitimate address due to we provide some
  pattern for optimize access PIC local symbol and it's make GCC generate
  unrecognizable instruction during optimizing.  */
@@ -4576,6 +4596,19 @@ riscv_split_64bit_move_p (rtx dest, rtx src)
   if (TARGET_64BIT)
 return false;
 
+  /* Zilsd provides load/store with even-odd register pair. */
+  if (TARGET_ZILSD
+  && (((REG_P (dest) && MEM_P (src))
+ || (MEM_P (dest) && REG_P (src)
+{
+  rtx reg = REG_P (dest) ? dest : src;
+  unsigned regno = REGNO (reg);
+  /* GCC may still generating some load/store with odd-even reg pair
+because the ABI handling, but that's fine, just split that later.  */
+  if (GP_REG_P (regno))
+   return (regno < FIRST_PSEUDO_REGISTER) && ((regno % 2) != 0);
+}
+
   /* There is no need to split if the FLI instruction in the `Zfa` extension 
can be used.  */
   if (satisfies_constraint_zfli (src))
 return false;
@@ -9798,6 +9831,12 @@ riscv_hard_regno_mode_ok (unsigned int regno, 
machine_mode mode)
   if (riscv_v_ext_mode_p (mode))
return false;
 
+  /* Zilsd require load/store with even-odd reg pair.  */
+  if (TARGET_ZILSD
+ && (GET_MODE_UNIT_SIZE (mode) == (UNITS_PER_WORD * 2))
+ && ((regno % 2) != 0))
+   return false;
+
   if (!GP_REG_P (regno + nregs - 1))
return false;
 }
diff --git a/gcc/testsuite/gcc.target/riscv/zilsd-code-gen.c 
b/gcc/testsuite/gcc.target/riscv/zilsd-code-gen.c
new file mode 100644
index ..9155622ea55a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zilsd-code-gen.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32i_zilsd -mabi=ilp32" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+long long foo1(long long *a)
+{
+return *a;
+}
+
+long long g;
+
+void foo2(long long a)
+{
+g = a;
+}
+
+/* { dg-final { scan-assembler-times "ld\t" 1 } } */
+/* { dg-final { scan-assembler-times "sd\t" 1 } } */

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add intrinsics support for SiFive Xsfvcp extensions.

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:86335353527ef510a9fe6229418f313f6764c00e

commit 86335353527ef510a9fe6229418f313f6764c00e
Author: yulong 
Date:   Tue Apr 29 21:12:02 2025 +0800

RISC-V: Add intrinsics support for SiFive Xsfvcp extensions.

This version is same as v5, but rebase to trunk, send out to trigger CI.

This commit adds intrinsics support for Xsfvcp extension.
Diff with V4: Delete the sifive_vector.h file.

Co-Authored by: Jiawei Chen 
Co-Authored by: Shihua Liao 
Co-Authored by: Yixuan Chen 

gcc/ChangeLog:

* config/riscv/constraints.md (Ou01): New constraint.
(Ou02): Ditto.
* config/riscv/generic-vector-ooo.md (vec_sf_vcp): New reservation.
* config/riscv/genrvv-type-indexer.cc (main): New type.
* config/riscv/riscv-c.cc (riscv_pragma_intrinsic): Add xsfvcp 
strings.
* config/riscv/riscv-vector-builtins-shapes.cc (struct 
sf_vcix_se_def):
New function.
(struct sf_vcix_def): Ditto.
(SHAPE): Ditto.
* config/riscv/riscv-vector-builtins-shapes.h: Ditto.
* config/riscv/riscv-vector-builtins-types.def (DEF_RVV_X2_U_OPS): 
New type.
(DEF_RVV_X2_WU_OPS): Ditto.
(vuint8mf8_t): Ditto.
(vuint8mf4_t): Ditto.
(vuint8mf2_t): Ditto.
(vuint8m1_t): Ditto.
(vuint8m2_t): Ditto.
(vuint8m4_t): Ditto.
(vuint16mf4_t): Ditto.
(vuint16mf2_t): Ditto.
(vuint16m1_t): Ditto.
(vuint16m2_t): Ditto.
(vuint16m4_t): Ditto.
(vuint32mf2_t): Ditto.
(vuint32m1_t): Ditto.
(vuint32m2_t): Ditto.
(vuint32m4_t): Ditto.
* config/riscv/riscv-vector-builtins.cc (DEF_RVV_X2_U_OPS): New 
builtins
def.
(DEF_RVV_X2_WU_OPS): Ditto.
(rvv_arg_type_info::get_scalar_float_type): Ditto.
(function_instance::modifies_global_state_p): Ditto.
* config/riscv/riscv-vector-builtins.def (v_x): New base type.
(i): Ditto.
(v_i): Ditto.
(xv): Ditto.
(iv): Ditto.
(fv): Ditto.
(vvv): Ditto.
(xvv): Ditto.
(ivv): Ditto.
(fvv): Ditto.
(vvw): Ditto.
(xvw): Ditto.
(ivw): Ditto.
(fvw): Ditto.
(v_vv): Ditto.
(v_xv): Ditto.
(v_iv): Ditto.
(v_fv): Ditto.
(v_vvv): Ditto.
(v_xvv): Ditto.
(v_ivv): Ditto.
(v_fvv): Ditto.
(v_vvw): Ditto.
(v_xvw): Ditto.
(v_ivw): Ditto.
(v_fvw): Ditto.
(x2_vector): Ditto.
(scalar_float): Ditto.
* config/riscv/riscv-vector-builtins.h (enum required_ext): New 
extension.
(required_ext_to_isa_name): Ditto.
(required_extensions_specified): Ditto.
(struct rvv_arg_type_info): Ditto.
(struct function_group_info): Ditto.
* config/riscv/riscv.md: New attr.
* config/riscv/sifive-vector-builtins-bases.cc (class sf_vc): New 
function.
(BASE): New base_name.
* config/riscv/sifive-vector-builtins-bases.h: New function_base.
* config/riscv/sifive-vector-builtins-functions.def
(REQUIRED_EXTENSIONS): New intrinsics def.
(sf_vc): Ditto.
* config/riscv/sifive-vector.md (@sf_vc_x_se): New RTL mode.
(@sf_vc_v_x_se): Ditto.
(@sf_vc_v_x): Ditto.
(@sf_vc_i_se): Ditto.
(@sf_vc_v_i_se): Ditto.
(@sf_vc_v_i): Ditto.
(@sf_vc_vv_se): Ditto.
(@sf_vc_v_vv_se): Ditto.
(@sf_vc_v_vv): Ditto.
(@sf_vc_xv_se): Ditto.
(@sf_vc_v_xv_se): Ditto.
(@sf_vc_v_xv): Ditto.
(@sf_vc_iv_se): Ditto.
(@sf_vc_v_iv_se): Ditto.
(@sf_vc_v_iv): Ditto.
(@sf_vc_fv_se): Ditto.
(@sf_vc_v_fv_se): Ditto.
(@sf_vc_v_fv): Ditto.
(@sf_vc_vvv_se): Ditto.
(@sf_vc_v_vvv_se): Ditto.
(@sf_vc_v_vvv): Ditto.
(@sf_vc_xvv_se): Ditto.
(@sf_vc_v_xvv_se): Ditto.
(@sf_vc_v_xvv): Ditto.
(@sf_vc_ivv_se): Ditto.
(@sf_vc_v_ivv_se): Ditto.
(@sf_vc_v_ivv): Ditto.
(@sf_vc_fvv_se): Ditto.
(@sf_vc_v_fvv_se): Ditto.
(@sf_vc_v_fvv): Ditto.
(@sf_vc_vvw_se): Ditto.
(@sf_vc_v_vvw_se): Ditto.
(@sf_vc_v_vvw): Ditto.
(@sf_vc_xvw_se): Ditto.
(@sf_vc_v_xvw_se): Ditto.
(@sf_vc_v_xvw): Ditto.
(@sf_vc_ivw_se): Ditto.
(@sf_vc_v_ivw_se): Ditto.
(@sf_vc_v_ivw): Ditto.
(@sf_vc_fvw_se): Dit

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add intrinsics testcases for SiFive Xsfvcp extensions.

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:2e800ed614cc8596c462576cddb0afa47114a62c

commit 2e800ed614cc8596c462576cddb0afa47114a62c
Author: yulong 
Date:   Tue Apr 29 21:12:03 2025 +0800

RISC-V: Add intrinsics testcases for SiFive Xsfvcp extensions.

This commit adds testcases for Xsfvcp.

Co-Authored by: Jiawei Chen 
Co-Authored by: Shihua Liao 
Co-Authored by: Yixuan Chen 

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/xsfvector/sf_vc_f.c: New test.
* gcc.target/riscv/rvv/xsfvector/sf_vc_i.c: New test.
* gcc.target/riscv/rvv/xsfvector/sf_vc_v.c: New test.
* gcc.target/riscv/rvv/xsfvector/sf_vc_x.c: New test.

(cherry picked from commit cc8b8c0b69200ab816a2626e29d91ac995f7438f)

Diff:
---
 .../gcc.target/riscv/rvv/xsfvector/sf_vc_f.c   |  88 +
 .../gcc.target/riscv/rvv/xsfvector/sf_vc_i.c   | 132 
 .../gcc.target/riscv/rvv/xsfvector/sf_vc_v.c   | 107 
 .../gcc.target/riscv/rvv/xsfvector/sf_vc_x.c   | 138 +
 4 files changed, 465 insertions(+)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_f.c 
b/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_f.c
new file mode 100644
index ..7667e56a4c5f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_f.c
@@ -0,0 +1,88 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_xsfvcp -mabi=lp64d -O3" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sifive_vector.h"
+
+typedef _Float16 float16_t;
+typedef float float32_t;
+typedef double float64_t;
+
+/*
+** test_sf_vc_v_fv_u16mf4:
+** ...
+** vsetivli\s+zero+,0+,e16+,mf4,ta,ma+
+** sf\.vc\.v\.fv\t[0-9]+,v[0-9]+,v[0-9]+,fa[0-9]+
+** ...
+*/
+vuint16mf4_t test_sf_vc_v_fv_u16mf4(vuint16mf4_t vs2, float16_t fs1, size_t 
vl) {
+return __riscv_sf_vc_v_fv_u16mf4(1, vs2, fs1, vl);
+}
+
+/*
+** test_sf_vc_v_fv_se_u16mf4:
+** ...
+** vsetivli\s+zero+,0+,e16+,mf4,ta,ma+
+** sf\.vc\.v\.fv\t[0-9]+,v[0-9]+,v[0-9]+,fa[0-9]+
+** ...
+*/
+vuint16mf4_t test_sf_vc_v_fv_se_u16mf4(vuint16mf4_t vs2, float16_t fs1, size_t 
vl) {
+return __riscv_sf_vc_v_fv_se_u16mf4(1, vs2, fs1, vl);
+}
+
+/*
+** test_sf_vc_fv_se_u16mf2:
+** ...
+** vsetivli\s+zero+,0+,e16+,mf2,ta,ma+
+** sf\.vc\.fv\t[0-9]+,[0-9]+,v[0-9]+,fa[0-9]+
+** ...
+*/
+void test_sf_vc_fv_se_u16mf2(vuint16mf2_t vs2, float16_t fs1, size_t vl) {
+__riscv_sf_vc_fv_se_u16mf2(1, 3, vs2, fs1, vl);
+}
+
+/*
+** test_sf_vc_v_fvv_u16m1:
+** ...
+** vsetivli\s+zero+,0+,e16+,m1,ta,ma+
+** sf\.vc\.v\.fvv\t[0-9]+,v[0-9]+,v[0-9]+,fa[0-9]+
+** ...
+*/
+vuint16m1_t test_sf_vc_v_fvv_u16m1(vuint16m1_t vd, vuint16m1_t vs2, float16_t 
fs1, size_t vl) {
+return __riscv_sf_vc_v_fvv_u16m1(1, vd, vs2, fs1, vl);
+}
+
+/*
+** test_sf_vc_v_fvv_se_u16m1:
+** ...
+** vsetivli\s+zero+,0+,e16+,m1,ta,ma+
+** sf\.vc\.v\.fvv\t[0-9]+,v[0-9]+,v[0-9]+,fa[0-9]+
+** ...
+*/
+vuint16m1_t test_sf_vc_v_fvv_se_u16m1(vuint16m1_t vd, vuint16m1_t vs2, 
float16_t fs1, size_t vl) {
+return __riscv_sf_vc_v_fvv_se_u16m1(1, vd, vs2, fs1, vl);
+}
+
+/*
+** test_sf_vc_fvv_se_u32m8:
+** ...
+** vsetivli\s+zero+,0+,e32+,m8,ta,ma+
+** sf\.vc\.fvv\t[0-9]+,v[0-9]+,v[0-9]+,fa[0-9]+
+** ...
+*/
+void test_sf_vc_fvv_se_u32m8(vuint32m8_t vd, vuint32m8_t vs2, float32_t fs1, 
size_t vl) {
+__riscv_sf_vc_fvv_se_u32m8(1, vd, vs2, fs1, vl);
+}
+
+
+/*
+** test_sf_vc_fvw_se_u32m2:
+** ...
+** vsetivli\s+zero+,0+,e32+,m2,ta,ma+
+** sf\.vc\.fvw\t[0-9]+,v[0-9]+,v[0-9]+,fa[0-9]+
+** ...
+*/
+void test_sf_vc_fvw_se_u32m2(vuint64m4_t vd, vuint32m2_t vs2, float32_t fs1, 
size_t vl) {
+__riscv_sf_vc_fvw_se_u32m2(1, vd, vs2, fs1, vl);
+}
+
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_i.c 
b/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_i.c
new file mode 100644
index ..5528cc52ac76
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_i.c
@@ -0,0 +1,132 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_xsfvcp -mabi=lp64d -O3" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sifive_vector.h"
+
+
+/*
+** test_sf_vc_v_i_u16m4:
+** ...
+** vsetivli\s+zero+,0+,e16+,m4,ta,ma+
+** sf\.vc\.v\.i\t[0-9]+,[0-9]+,v[0-9]+,[0-9]+
+** ...
+*/
+vuint16m4_t test_sf_vc_v_i_u16m4(size_t vl) {
+return __riscv_sf_vc_v_i_u16m4(1, 2, 4, vl);
+}
+
+/*
+** test_sf_vc_v_i_se_u16m4:
+** ...
+** vsetivli\s+zero+,0+,e16+,m4,ta,ma+
+** sf\.vc\.v\.i\t[0-9]+,[0-9]+,v[0-9]+,[0-9]+
+** ...
+*/
+vuint16m4_t test_sf_vc_v_i_se_u16m4(size_t vl) {
+return __riscv_sf_vc_v_i_se_u16m4(1, 2, 4, vl);
+}
+
+/*
+** test_sf_vc_i_se_u16mf4:
+** ...
+** vsetivli\s+zero+,0+,e16+,mf4,ta,ma+
+** sf\.vc\.i\t[0-9]+,[0-9]+,[0-9]+,[0-9]+
+** ...
+*/
+void test_sf_vc_i_se_u16mf4(size_t vl) {
+__riscv_sf_vc_i_se_u16mf4(1, 2, 3, 4, vl);
+}
+
+/*
+** test_sf_vc_v_iv_u32m2:
+** ...
+** vsetivli\s+zero+,0+,e32+,m2,ta,ma+
+** sf\.vc\.v\.iv\t[0-9]+,v[0-9]+,v[0-9]+

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Fix missing implied Zicsr from Zve32x

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:5561ed024de75fd73b8d11e578b54fa7fb21bd6e

commit 5561ed024de75fd73b8d11e578b54fa7fb21bd6e
Author: Jerry Zhang Jian 
Date:   Wed Apr 30 15:34:07 2025 +0800

RISC-V: Fix missing implied Zicsr from Zve32x

The Zve32x extension depends on the Zicsr extension.
Currently, enabling Zve32x alone does not automatically imply Zicsr in GCC.

gcc/ChangeLog:

* common/config/riscv/riscv-common.cc: Add Zve32x depends on Zicsr

gcc/testsuite/ChangeLog:

* gcc.target/riscv/predef-19.c: set the march to rv64im_zve32x
instead of rv64gc_zve32x to avoid Zicsr implied by g. Extra m is
added to avoid current 'V' extension requires 'M' extension

Signed-off-by: Jerry Zhang Jian 
(cherry picked from commit a992164c2899735525a7a267654473b7e527ef0d)

Diff:
---
 gcc/common/config/riscv/riscv-common.cc|  1 +
 gcc/testsuite/gcc.target/riscv/predef-19.c | 34 ++
 2 files changed, 8 insertions(+), 27 deletions(-)

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index 15df22d53770..145a0f2bd95f 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -137,6 +137,7 @@ static const riscv_implied_info_t riscv_implied_info[] =
   {"zve64f", "f"},
   {"zve64d", "d"},
 
+  {"zve32x", "zicsr"},
   {"zve32x", "zvl32b"},
   {"zve32f", "zve32x"},
   {"zve32f", "zvl32b"},
diff --git a/gcc/testsuite/gcc.target/riscv/predef-19.c 
b/gcc/testsuite/gcc.target/riscv/predef-19.c
index 2b90702192ba..ca3d57abca90 100644
--- a/gcc/testsuite/gcc.target/riscv/predef-19.c
+++ b/gcc/testsuite/gcc.target/riscv/predef-19.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O2 -march=rv64gc_zve32x -mabi=lp64d -mcmodel=medlow 
-misa-spec=2.2" } */
+/* { dg-options "-O2 -march=rv64im_zve32x -mabi=lp64 -mcmodel=medlow 
-misa-spec=2.2" } */
 
 int main () {
 
@@ -15,50 +15,30 @@ int main () {
 #error "__riscv_i"
 #endif
 
-#if !defined(__riscv_c)
-#error "__riscv_c"
-#endif
-
 #if defined(__riscv_e)
 #error "__riscv_e"
 #endif
 
-#if !defined(__riscv_a)
-#error "__riscv_a"
-#endif
-
 #if !defined(__riscv_m)
 #error "__riscv_m"
 #endif
 
-#if !defined(__riscv_f)
-#error "__riscv_f"
-#endif
-
-#if !defined(__riscv_d)
-#error "__riscv_d"
-#endif
-
-#if defined(__riscv_v)
-#error "__riscv_v"
+#if !defined(__riscv_zicsr)
+#error "__riscv_zicsr"
 #endif
 
-#if defined(__riscv_zvl128b)
-#error "__riscv_zvl128b"
+#if !defined(_riscv_zmmul)
+#error "__riscv_zmmul"
 #endif
 
-#if defined(__riscv_zvl64b)
-#error "__riscv_zvl64b"
+#if !defined(__riscv_zve32x)
+#error "__riscv_zve32x"
 #endif
 
 #if !defined(__riscv_zvl32b)
 #error "__riscv_zvl32b"
 #endif
 
-#if !defined(__riscv_zve32x)
-#error "__riscv_zve32x"
-#endif
-
 #if !defined(__riscv_vector)
 #error "__riscv_vector"
 #endif

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [PATCH] RISC-V: Do not free a riscv_arch_string when handling target-arch attribute

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:8b34e03a0527699f36e69fff4627ba60abe99cdc

commit 8b34e03a0527699f36e69fff4627ba60abe99cdc
Author: 翁愷邑 
Date:   Thu Apr 17 16:24:20 2025 -0600

[PATCH] RISC-V: Do not free a riscv_arch_string when handling target-arch 
attribute

The build_target_option_node() function may return a cached node when
fndecl having the same effective global_options. Therefore, freeing
memory used in target nodes can lead to a use-after-free issue, as a
target node may be shared by multiple fndecl.
This issue occurs in gcc.target/riscv/target-attr-16.c, where all
functions have the same march, but the last function tries to free its
old x_riscv_arch_string (which is shared) when processing the second
target attribute.However, the behavior of this issue depends on how the
OS handles malloc. It's very likely that xstrdup returns the old address
just freed, coincidentally hiding the issue. We can verify the issue by
forcing xstrdup to return a new address, e.g.,

-  if (opts->x_riscv_arch_string != default_opts->x_riscv_arch_string)
-free (CONST_CAST (void *, (const void *) opts->x_riscv_arch_string));
+  // Force it to use a new address, NFCI
+  const char *tmp = opts->x_riscv_arch_string;
   opts->x_riscv_arch_string = xstrdup (local_arch_str);

+  if (tmp != default_opts->x_riscv_arch_string)
+free (CONST_CAST (void *, (const void *) tmp));

This patch replaces xstrdup with ggc_strdup and let gc to take care of
unused strings.

gcc/ChangeLog:

* config/riscv/riscv-target-attr.cc
(riscv_target_attr_parser::update_settings):
Do not manually free any arch string.

(cherry picked from commit 2d6f1ca17f25b28da8f8d83622f0e029da2340e7)

Diff:
---
 gcc/config/riscv/riscv-target-attr.cc | 6 +-
 1 file changed, 1 insertion(+), 5 deletions(-)

diff --git a/gcc/config/riscv/riscv-target-attr.cc 
b/gcc/config/riscv/riscv-target-attr.cc
index 1d968655f95d..8ad3025579b2 100644
--- a/gcc/config/riscv/riscv-target-attr.cc
+++ b/gcc/config/riscv/riscv-target-attr.cc
@@ -257,11 +257,7 @@ riscv_target_attr_parser::update_settings (struct 
gcc_options *opts) const
 {
   std::string local_arch = m_subset_list->to_string (true);
   const char* local_arch_str = local_arch.c_str ();
-  struct cl_target_option *default_opts
-   = TREE_TARGET_OPTION (target_option_default_node);
-  if (opts->x_riscv_arch_string != default_opts->x_riscv_arch_string)
-   free (CONST_CAST (void *, (const void *) opts->x_riscv_arch_string));
-  opts->x_riscv_arch_string = xstrdup (local_arch_str);
+  opts->x_riscv_arch_string = ggc_strdup (local_arch_str);
 
   riscv_set_arch_by_subset_list (m_subset_list, opts);
 }

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [PATCH] [RISC-V] Tune for removal unnecessary sext in builtin overflows [PR108016]

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:ec8bf88125b77b8533eb9f8b74a0697a5ed99dee

commit ec8bf88125b77b8533eb9f8b74a0697a5ed99dee
Author: Alexey Merzlyakov 
Date:   Fri Apr 18 06:45:10 2025 -0600

[PATCH] [RISC-V] Tune for removal unnecessary sext in builtin overflows 
[PR108016]

It fixes one of the PR108016 mis-optimization.

The patch adjusts expanding for __builtin_add/sub_overflow() on RV64 targets
to avoid unnecessary sext.w instructions.

It replaces expanded for ADD/SUB_OVERFLOW code:
  r141:SI=r139:DI#0+r140:DI#0 .. r143:DI=sign_extend(r141:SI)
to the followong kind of chain ->
  r143:DI=sign_extend(r139:DI#0+r140:DI#0) .. r141:SI=r143:DI#0
so that sign_extend(a:SI+b:SI) to be emitted as addw (or subw) instruction,
while output r141:SI register will be placed at the end of chain without
extra dependencies, and thus could be easily optimized-out by further 
pipeline.

PR middle-end/108016
gcc/ChangeLog:

* config/riscv/riscv.md (addv4, uaddv4, subv4,
usubv4): Tunes for unnecessary sext.w elimination.

PR middle-end/108016
gcc/testsuite/ChangeLog:

* gcc.target/riscv/pr108016.c: New test.

(cherry picked from commit 529a43109fcd93f5aafda345da14679f538ada86)

Diff:
---
 gcc/config/riscv/riscv.md | 28 ++
 gcc/testsuite/gcc.target/riscv/pr108016.c | 33 +++
 2 files changed, 53 insertions(+), 8 deletions(-)

diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 26a247c2b966..eec96875f968 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -789,7 +789,7 @@
   rtx t5 = gen_reg_rtx (DImode);
   rtx t6 = gen_reg_rtx (DImode);
 
-  riscv_emit_binary (PLUS, operands[0], operands[1], operands[2]);
+  emit_insn (gen_addsi3_extended (t6, operands[1], operands[2]));
   if (GET_CODE (operands[1]) != CONST_INT)
emit_insn (gen_extend_insn (t4, operands[1], DImode, SImode, 0));
   else
@@ -799,7 +799,10 @@
   else
t5 = operands[2];
   emit_insn (gen_adddi3 (t3, t4, t5));
-  emit_insn (gen_extend_insn (t6, operands[0], DImode, SImode, 0));
+  rtx t7 = gen_lowpart (SImode, t6);
+  SUBREG_PROMOTED_VAR_P (t7) = 1;
+  SUBREG_PROMOTED_SET (t7, SRP_SIGNED);
+  emit_move_insn (operands[0], t7);
 
   riscv_expand_conditional_branch (operands[3], NE, t6, t3);
 }
@@ -835,8 +838,11 @@
emit_insn (gen_extend_insn (t3, operands[1], DImode, SImode, 0));
   else
t3 = operands[1];
-  riscv_emit_binary (PLUS, operands[0], operands[1], operands[2]);
-  emit_insn (gen_extend_insn (t4, operands[0], DImode, SImode, 0));
+  emit_insn (gen_addsi3_extended (t4, operands[1], operands[2]));
+  rtx t5 = gen_lowpart (SImode, t4);
+  SUBREG_PROMOTED_VAR_P (t5) = 1;
+  SUBREG_PROMOTED_SET (t5, SRP_SIGNED);
+  emit_move_insn (operands[0], t5);
 
   riscv_expand_conditional_branch (operands[3], LTU, t4, t3);
 }
@@ -966,7 +972,7 @@
   rtx t5 = gen_reg_rtx (DImode);
   rtx t6 = gen_reg_rtx (DImode);
 
-  riscv_emit_binary (MINUS, operands[0], operands[1], operands[2]);
+  emit_insn (gen_subsi3_extended (t6, operands[1], operands[2]));
   if (GET_CODE (operands[1]) != CONST_INT)
emit_insn (gen_extend_insn (t4, operands[1], DImode, SImode, 0));
   else
@@ -976,7 +982,10 @@
   else
t5 = operands[2];
   emit_insn (gen_subdi3 (t3, t4, t5));
-  emit_insn (gen_extend_insn (t6, operands[0], DImode, SImode, 0));
+  rtx t7 = gen_lowpart (SImode, t6);
+  SUBREG_PROMOTED_VAR_P (t7) = 1;
+  SUBREG_PROMOTED_SET (t7, SRP_SIGNED);
+  emit_move_insn (operands[0], t7);
 
   riscv_expand_conditional_branch (operands[3], NE, t6, t3);
 }
@@ -1015,8 +1024,11 @@
emit_insn (gen_extend_insn (t3, operands[1], DImode, SImode, 0));
   else
t3 = operands[1];
-  riscv_emit_binary (MINUS, operands[0], operands[1], operands[2]);
-  emit_insn (gen_extend_insn (t4, operands[0], DImode, SImode, 0));
+  emit_insn (gen_subsi3_extended (t4, operands[1], operands[2]));
+  rtx t5 = gen_lowpart (SImode, t4);
+  SUBREG_PROMOTED_VAR_P (t5) = 1;
+  SUBREG_PROMOTED_SET (t5, SRP_SIGNED);
+  emit_move_insn (operands[0], t5);
 
   riscv_expand_conditional_branch (operands[3], LTU, t3, t4);
 }
diff --git a/gcc/testsuite/gcc.target/riscv/pr108016.c 
b/gcc/testsuite/gcc.target/riscv/pr108016.c
new file mode 100644
index ..b60df42d02a6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/pr108016.c
@@ -0,0 +1,33 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+unsigned int addu (unsigned int a, unsigned int b)
+{
+  unsigned int out;
+  unsigned int overflow = __builtin_add_overflow (a, b, &out);
+  return overflow & out;
+}

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [RISC-V] Fix missed bext discovery

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:9c84211ac0e0012622da9a63f1fbb30d3f64caef

commit 9c84211ac0e0012622da9a63f1fbb30d3f64caef
Author: Jeff Law 
Date:   Fri Apr 18 12:19:30 2025 -0600

[RISC-V] Fix missed bext discovery

RISC-V has the ability to extract a single bit out of a register from a 
fixed
or variable position.

While looking at 502.gcc a little while ago I realize that we failed to use
bext inside bitmap_bit_p for its return value.

The core "problem" is that the RISC-V does not define SHIFT_COUNT_TRUNCATED
(for good reasons).  As a result the target is largely responsible for 
handling
elimination of shift count/bit position masking.

There's a follow-up patch I've been working on with an intern to improve
detection of bext in more cases.  This one stands independently though and 
is
probably the most important of the missed cases.

Will push to the trunk assuming pre-commit testing is green.  It's already 
been
through my tester as well as Ventana's internal testing.

gcc
* config/riscv/bitmanip.md (*bext_mask_pos): New pattern
for extracting a single bit at masked bit position.

gcc/testsuite

* gcc.target/riscv/bext-ext-2.c: New test

(cherry picked from commit 45a1038f3ca6ddceb8d159ccba6d99ed61951472)

Diff:
---
 gcc/config/riscv/bitmanip.md| 18 +++
 gcc/testsuite/gcc.target/riscv/bext-ext-2.c | 74 +
 2 files changed, 92 insertions(+)

diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md
index 5ed5e18cb36a..2a3884cfde01 100644
--- a/gcc/config/riscv/bitmanip.md
+++ b/gcc/config/riscv/bitmanip.md
@@ -908,6 +908,24 @@
   "bext\t%0,%1,%2"
   [(set_attr "type" "bitmanip")])
 
+;; We do not define SHIFT_COUNT_TRUNCATED, so we have to have variants
+;; that mask/extend the count if we want to eliminate those ops
+;;  
+;; We could (in theory) use GPR for the various modes, but I haven't
+;; seen those cases appear in practice.  Without a testcase I've
+;; elected to keep the modes X which is easy to reason about.
+(define_insn "*bext_mask_pos"
+  [(set (match_operand:X 0 "register_operand" "=r")
+   (zero_extract:X (match_operand:X 1 "register_operand" "r")
+   (const_int 1)
+   (and:X
+ (match_operand:X 2 "register_operand" "r")
+ (match_operand 3 "const_int_operand"]
+  "(TARGET_ZBS
+&& INTVAL (operands[3]) + 1 == GET_MODE_BITSIZE (mode))"
+  "bext\t%0,%1,%2"
+  [(set_attr "type" "bitmanip")])
+
 ;; This is a bext followed by a seqz.  Normally this would be a 3->2 split
 ;; But the and-not pattern with a constant operand is a define_insn_and_split,
 ;; so this looks like a 2->2 split, which combine rejects.  So implement it
diff --git a/gcc/testsuite/gcc.target/riscv/bext-ext-2.c 
b/gcc/testsuite/gcc.target/riscv/bext-ext-2.c
new file mode 100644
index ..aa170d06d0e7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/bext-ext-2.c
@@ -0,0 +1,74 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcb -mabi=lp64" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+struct obstack;
+struct bitmap_head_def;
+typedef struct bitmap_head_def *bitmap;
+struct obstack
+{
+  long chunk_size;
+  struct _obstack_chunk *chunk;
+  char *object_base;
+  char *next_free;
+  char *chunk_limit;
+  long int temp;
+  int alignment_mask;
+
+
+
+  struct _obstack_chunk *(*chunkfun) (void *, long);
+  void (*freefun) (void *, struct _obstack_chunk *);
+  void *extra_arg;
+  unsigned use_extra_arg:1;
+  unsigned maybe_empty_object:1;
+
+
+
+  unsigned alloc_failed:1;
+
+
+};
+
+typedef unsigned long BITMAP_WORD;
+typedef struct bitmap_obstack {
+  struct bitmap_element_def *elements;
+  struct bitmap_head_def *heads;
+  struct obstack obstack;
+} bitmap_obstack;
+typedef struct bitmap_element_def {
+  struct bitmap_element_def *next;
+  struct bitmap_element_def *prev;
+  unsigned int indx;
+  BITMAP_WORD bits[((128 + (8 
+  * 8 * 1u) - 1) / (8 
+  * 8 * 1u))];
+} bitmap_element;
+bitmap_element *bitmap_find_bit (bitmap, unsigned int);
+
+
+int
+bitmap_bit_p (bitmap head, int bit)
+{
+  bitmap_element *ptr;
+  unsigned bit_num;
+  unsigned word_num;
+
+  ptr = bitmap_find_bit (head, bit);
+  if (ptr == 0)
+return 0;
+
+  bit_num = bit % (8 
+ * 8 * 1u);
+  word_num = bit / (8 
+  * 8 * 1u) % ((128 + (8 
+ * 8 * 1u) - 1) / (8 
+ * 8 * 1u));
+
+  return (ptr->bits[word_num] >> bit_num) & 1;
+}
+
+/* { dg-final { scan-assembler-times "bext\t" 1 } } */
+/* { dg-final { scan-assembler-not "slr\t"} } */
+/* { dg-final { scan-assembler-not "andi\t"} } */
+

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Extract vector stepped for expand_const_vector [NFC]

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:f789cdaede74d5cbdb60bef631a14a6fb7025efb

commit f789cdaede74d5cbdb60bef631a14a6fb7025efb
Author: Pan Li 
Date:   Thu Apr 17 10:27:17 2025 +0800

RISC-V: Extract vector stepped for expand_const_vector [NFC]

Consider the expand_const_vector is quit long (about 500 lines)
and complicated, we would like to extract the different case
into different functions.  For example, the const vector stepped
will be extracted into expand_const_vector_stepped.

The below test suites are passed for this patch.
* The rv64gcv fully regression test.

gcc/ChangeLog:

* config/riscv/riscv-v.cc (expand_const_vector): Extract
const vector stepped into separated func.
(expand_const_vector_single_step_npatterns): Add new func
to take care of single step.
(expand_const_vector_interleaved_stepped_npatterns): Add new
func to take care of interleaved step.
(expand_const_vector_stepped): Add new func to take care of
const vector stepped.

Signed-off-by: Pan Li 
(cherry picked from commit ab22b8c630769330b4f37eb64d2bc285344a647a)

Diff:
---
 gcc/config/riscv/riscv-v.cc | 590 ++--
 1 file changed, 299 insertions(+), 291 deletions(-)

diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 96f0b94e6140..66c8b2921e26 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -1340,334 +1340,342 @@ expand_const_vector_duplicate (rtx target, 
rvv_builder *builder)
 }
 
 static void
-expand_const_vector (rtx target, rtx src)
+expand_const_vector_single_step_npatterns (rtx target, rvv_builder *builder)
 {
   machine_mode mode = GET_MODE (target);
   rtx result = register_operand (target, mode) ? target : gen_reg_rtx (mode);
-  rtx elt;
 
-  if (const_vec_duplicate_p (src, &elt))
-return expand_const_vec_duplicate (target, src, elt);
+  /* Describe the case by choosing NPATTERNS = 4 as an example.  */
+  insn_code icode;
 
-  /* Support scalable const series vector.  */
-  rtx base, step;
-  if (const_vec_series_p (src, &base, &step))
-return expand_const_vec_series (target, base, step);
+  /* Step 1: Generate vid = { 0, 1, 2, 3, 4, 5, 6, 7, ... }.  */
+  rtx vid = gen_reg_rtx (builder->mode ());
+  rtx vid_ops[] = {vid};
+  icode = code_for_pred_series (builder->mode ());
+  emit_vlmax_insn (icode, NULLARY_OP, vid_ops);
 
-  /* Handle variable-length vector.  */
-  unsigned int nelts_per_pattern = CONST_VECTOR_NELTS_PER_PATTERN (src);
-  unsigned int npatterns = CONST_VECTOR_NPATTERNS (src);
-  rvv_builder builder (mode, npatterns, nelts_per_pattern);
-  for (unsigned int i = 0; i < nelts_per_pattern; i++)
+  if (builder->npatterns_all_equal_p ())
 {
-  for (unsigned int j = 0; j < npatterns; j++)
-   builder.quick_push (CONST_VECTOR_ELT (src, i * npatterns + j));
-}
-  builder.finalize ();
+  /* Generate the variable-length vector following this rule:
+{ a, a, a + step, a + step, a + step * 2, a + step * 2, ...}
+  E.g. { 0, 0, 8, 8, 16, 16, ... } */
+
+  /* We want to create a pattern where value[idx] = floor (idx /
+NPATTERNS). As NPATTERNS is always a power of two we can
+rewrite this as = idx & -NPATTERNS.  */
+  /* Step 2: VID AND -NPATTERNS:
+{ 0&-4, 1&-4, 2&-4, 3 &-4, 4 &-4, 5 &-4, 6 &-4, 7 &-4, ... } */
+  rtx imm = gen_int_mode (-builder->npatterns (), builder->inner_mode ());
+  rtx tmp1 = gen_reg_rtx (builder->mode ());
+  rtx and_ops[] = {tmp1, vid, imm};
+  icode = code_for_pred_scalar (AND, builder->mode ());
+  emit_vlmax_insn (icode, BINARY_OP, and_ops);
+
+  /* Step 3: Convert to step size 1.  */
+  rtx tmp2 = gen_reg_rtx (builder->mode ());
+  /* log2 (npatterns) to get the shift amount to convert
+Eg.  { 0, 0, 0, 0, 4, 4, ... }
+into { 0, 0, 0, 0, 1, 1, ... }.  */
+  HOST_WIDE_INT shift_amt = exact_log2 (builder->npatterns ());
+  rtx shift = gen_int_mode (shift_amt, builder->inner_mode ());
+  rtx shift_ops[] = {tmp2, tmp1, shift};
+  icode = code_for_pred_scalar (ASHIFTRT, builder->mode ());
+  emit_vlmax_insn (icode, BINARY_OP, shift_ops);
+
+  /* Step 4: Multiply to step size n.  */
+  HOST_WIDE_INT step_size =
+   INTVAL (builder->elt (builder->npatterns ()))
+ - INTVAL (builder->elt (0));
+  rtx tmp3 = gen_reg_rtx (builder->mode ());
+  if (pow2p_hwi (step_size))
+   {
+ /* Power of 2 can be handled with a left shift.  */
+ HOST_WIDE_INT shift = exact_log2 (step_size);
+ rtx shift_amount = gen_int_mode (shift, Pmode);
+ insn_code icode = code_for_pred_scalar (ASHIFT, mode);
+ rtx ops[] = {tmp3, tmp2, shift_amount};
+ emit_vlmax_insn (icode, BINARY_OP, ops);
+   }
+  else
+   {
+ rtx mult_amt = gen_int_mode (step_size, builder

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [PATCH] [RISC-V]Support -mcpu for Xuantie cpu

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:3cbe4098f7865e3fb07aa0a6e35784e5bd583466

commit 3cbe4098f7865e3fb07aa0a6e35784e5bd583466
Author: Yixuan Chen 
Date:   Tue Apr 22 04:45:44 2025 -0600

[PATCH] [RISC-V]Support -mcpu for Xuantie cpu

Support -mcpu=xt-c908, xt-c908v, xt-c910, xt-c910v2, xt-c920, xt-c920v2
for Xuantie series cpu.
ref:https://www.xrvm.cn/community/download?id=4224248662731067392

without fmv_cost, vector_unaligned_access, use_divmod_expansion, 
overlap_op_by_pieces, fill the tune info with generic ooo for further 
modification.

gcc/ChangeLog:

* config/riscv/riscv-cores.def (RISCV_TUNE): Add xt-c908, xt-c908v,
xt-c910, xt-c910v2, xt-c920, xt-c920v2.
(RISCV_CORE): Add xt-c908, xt-c908v, xt-c910, xt-c910v2, xt-c920,
xt-c920v2.
* doc/invoke.texi: Add xt-c908, xt-c908v, xt-c910, xt-c910v2,
xt-c920, xt-c920v2.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/mcpu-xt-c908.c: test -mcpu=xt-c908.
* gcc.target/riscv/mcpu-xt-c910.c: test -mcpu=xt-c910.
* gcc.target/riscv/mcpu-xt-c920v2.c: test -mcpu=xt-c920v2.
* gcc.target/riscv/mcpu-xt-c908v.c: test -mcpu=xt-c908v.
* gcc.target/riscv/mcpu-xt-c910v2.c: test -mcpu=xt-c910v2.
* gcc.target/riscv/mcpu-xt-c920.c: test -mcpu=xt-c920.

(cherry picked from commit bd8a48500c1e775ab9cb4a737314cb800444ab4b)

Diff:
---
 gcc/config/riscv/riscv-cores.def| 48 +
 gcc/doc/invoke.texi |  5 ++-
 gcc/testsuite/gcc.target/riscv/mcpu-xt-c908.c   | 48 +
 gcc/testsuite/gcc.target/riscv/mcpu-xt-c908v.c  | 50 ++
 gcc/testsuite/gcc.target/riscv/mcpu-xt-c910.c   | 35 
 gcc/testsuite/gcc.target/riscv/mcpu-xt-c910v2.c | 51 ++
 gcc/testsuite/gcc.target/riscv/mcpu-xt-c920.c   | 34 +++
 gcc/testsuite/gcc.target/riscv/mcpu-xt-c920v2.c | 56 +
 8 files changed, 325 insertions(+), 2 deletions(-)

diff --git a/gcc/config/riscv/riscv-cores.def b/gcc/config/riscv/riscv-cores.def
index 2918496bcd06..e31afc3fe701 100644
--- a/gcc/config/riscv/riscv-cores.def
+++ b/gcc/config/riscv/riscv-cores.def
@@ -41,6 +41,12 @@ RISCV_TUNE("sifive-p400-series", sifive_p400, 
sifive_p400_tune_info)
 RISCV_TUNE("sifive-p600-series", sifive_p600, sifive_p600_tune_info)
 RISCV_TUNE("tt-ascalon-d8", generic_ooo, tt_ascalon_d8_tune_info)
 RISCV_TUNE("thead-c906", generic, thead_c906_tune_info)
+RISCV_TUNE("xt-c908", generic, generic_ooo_tune_info)
+RISCV_TUNE("xt-c908v", generic, generic_ooo_tune_info)
+RISCV_TUNE("xt-c910", generic, generic_ooo_tune_info)
+RISCV_TUNE("xt-c910v2", generic, generic_ooo_tune_info)
+RISCV_TUNE("xt-c920", generic, generic_ooo_tune_info)
+RISCV_TUNE("xt-c920v2", generic, generic_ooo_tune_info)
 RISCV_TUNE("xiangshan-nanhu", xiangshan, xiangshan_nanhu_tune_info)
 RISCV_TUNE("generic-ooo", generic_ooo, generic_ooo_tune_info)
 RISCV_TUNE("size", generic, optimize_size_tune_info)
@@ -93,6 +99,48 @@ RISCV_CORE("thead-c906",  
"rv64imafdc_xtheadba_xtheadbb_xtheadbs_xtheadcmo_"
  "xtheadmemidx_xtheadmempair_xtheadsync",
  "thead-c906")
 
+RISCV_CORE("xt-c908", "rv64imafdc_zicbom_zicbop_zicboz_zicntr_zicsr_"
+ "zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_"
+ "sstc_svinval_svnapot_svpbmt_xtheadba_xtheadbb_"
+ "xtheadbs_xtheadcmo_xtheadcondmov_xtheadfmemidx_"
+ "xtheadmac_xtheadmemidx_xtheadmempair_xtheadsync",
+ "xt-c908")
+RISCV_CORE("xt-c908v","rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicsr_"
+ "zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_"
+ "zvfh_sstc_svinval_svnapot_svpbmt__xtheadba_"
+ "xtheadbb_xtheadbs_xtheadcmo_xtheadcondmov_"
+ "xtheadfmemidx_xtheadmac_xtheadmemidx_"
+ "xtheadmempair_xtheadsync_xtheadvdot",
+ "xt-c908")
+RISCV_CORE("xt-c910", "rv64imafdc_zicntr_zicsr_zifencei_zihpm_zfh_"
+ "xtheadba_xtheadbb_xtheadbs_xtheadcmo_"
+ "xtheadcondmov_xtheadfmemidx_xtheadmac_"
+ "xtheadmemidx_xtheadmempair_xtheadsync",
+ "xt-c910")
+RISCV_CORE("xt-c910v2",   "rv64imafdc_zicbom_zicbop_zicboz_zicntr_zicond_"
+ "zicsr_zifencei _zihintntl_zihintpause_zihpm_"
+ "zawrs_zfa_zfbfmin_zfh_zca_zcb_zcd_zba_zbb_zbc_"
+ "zbs_sscofpmf_sstc_svinval_svnapot_svpbmt_"
+ "xtheadba_xtheadbb_xtheadbs_xtheadcmo_"
+

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [PATCH] riscv: Add support for riscv*-gnu (GNU/Hurd on RISC-V)

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:dd04c59701a2f416ed7b1c0a22a3ec9296240f8d

commit dd04c59701a2f416ed7b1c0a22a3ec9296240f8d
Author: Hakan Candar 
Date:   Fri Apr 18 07:08:44 2025 -0600

[PATCH] riscv: Add support for riscv*-gnu (GNU/Hurd on RISC-V)

This produces a toolchain that can successfully build binaries targeting
riscv*-gnu.

gcc/ChangeLog:
* config.gcc: Recognize riscv*-*-gnu* targets.
* config/riscv/gnu.h: New file.

(cherry picked from commit 869f2ab30ad53033ad6ac82569d74ce3a99fe510)

Diff:
---
 gcc/config.gcc | 14 
 gcc/config/riscv/gnu.h | 59 ++
 2 files changed, 73 insertions(+)

diff --git a/gcc/config.gcc b/gcc/config.gcc
index 40b50dc969ed..d98df883fce5 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -2540,6 +2540,20 @@ riscv*-*-linux*)
gcc_cv_initfini_array=yes
with_tls=${with_tls:-trad}
;;
+riscv*-*-gnu*)
+   tm_file="elfos.h gnu-user.h gnu.h glibc-stdint.h ${tm_file} riscv/gnu.h"
+   tmake_file="${tmake_file} riscv/t-riscv"
+   gnu_ld=yes
+   gas=yes
+   case $target in
+   riscv32be-*|riscv64be-*)
+   tm_defines="${tm_defines} TARGET_BIG_ENDIAN_DEFAULT=1"
+   ;;
+   esac
+   # Force .init_array support.  The configure script cannot always
+   # automatically detect that GAS supports it, yet we require it.
+   gcc_cv_initfini_array=yes
+   ;;
 riscv*-*-elf* | riscv*-*-rtems*)
tm_file="elfos.h newlib-stdint.h ${tm_file} riscv/elf.h"
case ${target} in
diff --git a/gcc/config/riscv/gnu.h b/gcc/config/riscv/gnu.h
new file mode 100644
index ..047399b10ff4
--- /dev/null
+++ b/gcc/config/riscv/gnu.h
@@ -0,0 +1,59 @@
+/* Definitions for RISC-V GNU/Hurd systems with ELF format.
+   Copyright (C) 1998-2025 Free Software Foundation, Inc.
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 3, or (at your option)
+any later version.
+
+GCC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GCC; see the file COPYING3.  If not see
+.  */
+
+#define TARGET_OS_CPP_BUILTINS()   \
+  do { \
+GNU_USER_TARGET_OS_CPP_BUILTINS(); \
+  } while (0)
+
+#define GNU_USER_DYNAMIC_LINKER "/lib/ld-riscv" XLEN_SPEC "-" ABI_SPEC ".so.1"
+
+#define ICACHE_FLUSH_FUNC "__riscv_flush_icache"
+
+#define CPP_SPEC "%{pthread:-D_REENTRANT}"
+
+#define LD_EMUL_SUFFIX \
+  "%{mabi=lp64d:}" \
+  "%{mabi=lp64f:_lp64f}" \
+  "%{mabi=lp64:_lp64}" \
+  "%{mabi=ilp32d:}" \
+  "%{mabi=ilp32f:_ilp32f}" \
+  "%{mabi=ilp32:_ilp32}"
+
+#define LINK_SPEC "\
+-melf" XLEN_SPEC DEFAULT_ENDIAN_SPEC "riscv" LD_EMUL_SUFFIX " \
+%{mno-relax:--no-relax} \
+-X \
+%{mbig-endian:-EB} \
+%{mlittle-endian:-EL} \
+%{shared} \
+  %{!shared: \
+%{!static: \
+  %{!static-pie: \
+   %{rdynamic:-export-dynamic} \
+   -dynamic-linker " GNU_USER_DYNAMIC_LINKER "}} \
+%{static:-static} %{static-pie:-static -pie --no-dynamic-linker -z text}}"
+
+#define STARTFILE_PREFIX_SPEC  \
+   "/lib" XLEN_SPEC "/" ABI_SPEC "/ "  \
+   "/usr/lib" XLEN_SPEC "/" ABI_SPEC "/ "  \
+   "/lib/ "\
+   "/usr/lib/ "
+
+#define RISCV_USE_CUSTOMISED_MULTI_LIB select_by_abi

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Extract vec_duplicate for expand_const_vector [NFC]

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:84be3beef5084731e5936395f22a87b8a10b4f5c

commit 84be3beef5084731e5936395f22a87b8a10b4f5c
Author: Pan Li 
Date:   Wed Apr 16 11:16:21 2025 +0800

RISC-V: Extract vec_duplicate for expand_const_vector [NFC]

Consider the expand_const_vector is quit long (about 500 lines)
and complicated, we would like to extract the different case
into different functions.  For example, the const vec_duplicate
will be extracted into expand_const_vec_duplicate.

The below test suites are passed for this patch.
* The rv64gcv fully regression test.

gcc/ChangeLog:

* config/riscv/riscv-v.cc (expand_const_vector): Extract
const vec_duplicate into separated function.
(expand_const_vec_duplicate): Add new func to take care
of the const vec_duplicate.

Signed-off-by: Pan Li 
(cherry picked from commit e6e42a709f3cd87e7a5efca72267cab57e0385cb)

Diff:
---
 gcc/config/riscv/riscv-v.cc | 92 -
 1 file changed, 50 insertions(+), 42 deletions(-)

diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index aae2d274336e..1eb14a24e3db 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -1171,61 +1171,69 @@ expand_vector_init_trailing_same_elem (rtx target,
 }
 
 static void
-expand_const_vector (rtx target, rtx src)
+expand_const_vec_duplicate (rtx target, rtx src, rtx elt)
 {
   machine_mode mode = GET_MODE (target);
   rtx result = register_operand (target, mode) ? target : gen_reg_rtx (mode);
-  rtx elt;
-  if (const_vec_duplicate_p (src, &elt))
+
+  if (GET_MODE_CLASS (mode) == MODE_VECTOR_BOOL)
+{
+  gcc_assert (rtx_equal_p (elt, const0_rtx)
+ || rtx_equal_p (elt, const1_rtx));
+
+  rtx ops[] = {result, src};
+  emit_vlmax_insn (code_for_pred_mov (mode), UNARY_MASK_OP, ops);
+}
+  else if (valid_vec_immediate_p (src))
 {
-  if (GET_MODE_CLASS (mode) == MODE_VECTOR_BOOL)
-   {
- gcc_assert (rtx_equal_p (elt, const0_rtx)
- || rtx_equal_p (elt, const1_rtx));
- rtx ops[] = {result, src};
- emit_vlmax_insn (code_for_pred_mov (mode), UNARY_MASK_OP, ops);
-   }
   /* Element in range -16 ~ 15 integer or 0.0 floating-point,
 we use vmv.v.i instruction.  */
-  else if (valid_vec_immediate_p (src))
+  rtx ops[] = {result, src};
+  emit_vlmax_insn (code_for_pred_mov (mode), UNARY_OP, ops);
+}
+  else
+{
+  /* Emit vec_duplicate split pattern before RA so that
+we could have a better optimization opportunity in LICM
+which will hoist vmv.v.x outside the loop and in fwprop && combine
+which will transform 'vv' into 'vx' instruction.
+
+The reason we don't emit vec_duplicate split pattern during
+RA since the split stage after RA is a too late stage to generate
+RVV instruction which need an additional register (We can't
+allocate a new register after RA) for VL operand of vsetvl
+instruction (vsetvl a5, zero).  */
+  if (lra_in_progress)
{
- rtx ops[] = {result, src};
- emit_vlmax_insn (code_for_pred_mov (mode), UNARY_OP, ops);
+ rtx ops[] = {result, elt};
+ emit_vlmax_insn (code_for_pred_broadcast (mode), UNARY_OP, ops);
}
   else
{
- /* Emit vec_duplicate split pattern before RA so that
-we could have a better optimization opportunity in LICM
-which will hoist vmv.v.x outside the loop and in fwprop && combine
-which will transform 'vv' into 'vx' instruction.
-
-The reason we don't emit vec_duplicate split pattern during
-RA since the split stage after RA is a too late stage to generate
-RVV instruction which need an additional register (We can't
-allocate a new register after RA) for VL operand of vsetvl
-instruction (vsetvl a5, zero).  */
- if (lra_in_progress)
-   {
- rtx ops[] = {result, elt};
- emit_vlmax_insn (code_for_pred_broadcast (mode), UNARY_OP, ops);
-   }
- else
-   {
- struct expand_operand ops[2];
- enum insn_code icode = optab_handler (vec_duplicate_optab, mode);
- gcc_assert (icode != CODE_FOR_nothing);
- create_output_operand (&ops[0], result, mode);
- create_input_operand (&ops[1], elt, GET_MODE_INNER (mode));
- expand_insn (icode, 2, ops);
- result = ops[0].value;
-   }
+ struct expand_operand ops[2];
+ enum insn_code icode = optab_handler (vec_duplicate_optab, mode);
+ gcc_assert (icode != CODE_FOR_nothing);
+ create_output_operand (&ops[0], result, mode);
+ create_input_operand (&ops[1], elt, GET_MODE_INNER (mode));
+ expand_insn (icode, 2, ops);
+   

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [RISC-V][PR target/119865] Don't free ggc allocated memory

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:f8d5c0a670b4cc7856f26a8722e60c082b26405b

commit f8d5c0a670b4cc7856f26a8722e60c082b26405b
Author: Jeff Law 
Date:   Sat Apr 19 12:35:29 2025 -0600

[RISC-V][PR target/119865] Don't free ggc allocated memory

Kaiweng's patch to stop freeing riscv_arch_string was correct, but 
incomplete
as there's another path that was freeing that node, which is just plain 
wrong
for a node allocated by the GC system.

This patch removes that call to free() which fixes the test.  I've spun it 
in
my tester and will obviously wait for the pre-commit system to render a 
verdict
before moving forward.

PR target/119865
gcc/
* config/riscv/riscv.cc (parse_features_for_version): Do not
explicitly free the architecture string.

(cherry picked from commit 1a64b224fa014e772fb30f6bd69ceb24da5827e6)

Diff:
---
 gcc/config/riscv/riscv.cc | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index d3656a7a4307..bad59e248d08 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -13136,9 +13136,6 @@ parse_features_for_version (tree decl,
  DECL_SOURCE_LOCATION (decl));
   gcc_assert (parse_res);
 
-  if (arch_string != default_opts->x_riscv_arch_string)
-free (CONST_CAST (void *, (const void *) arch_string));
-
   cl_target_option_restore (&global_options, &global_options_set,
&cur_target);
 }

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Extract vec_series for expand_const_vector [NFC]

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:8146b6eb1b61ab37a65397b7ee7abe5a49a173a0

commit 8146b6eb1b61ab37a65397b7ee7abe5a49a173a0
Author: Pan Li 
Date:   Wed Apr 16 14:43:23 2025 +0800

RISC-V: Extract vec_series for expand_const_vector [NFC]

Consider the expand_const_vector is quit long (about 500 lines)
and complicated, we would like to extract the different case
into different functions.  For example, the const vec_series
will be extracted into expand_const_vec_series.

The below test suites are passed for this patch.
* The rv64gcv fully regression test.

gcc/ChangeLog:

* config/riscv/riscv-v.cc (expand_const_vec_series): Add new
func to take care of the const vec_series.
(expand_const_vector): Extract const vec_series into separated
function.

Signed-off-by: Pan Li 
(cherry picked from commit cf366b62f48fc5c06b76a9a78320888a9591031b)

Diff:
---
 gcc/config/riscv/riscv-v.cc | 20 +---
 1 file changed, 13 insertions(+), 7 deletions(-)

diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 1eb14a24e3db..e0af296449c3 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -1224,6 +1224,18 @@ expand_const_vec_duplicate (rtx target, rtx src, rtx elt)
 emit_move_insn (target, result);
 }
 
+static void
+expand_const_vec_series (rtx target, rtx base, rtx step)
+{
+  machine_mode mode = GET_MODE (target);
+  rtx result = register_operand (target, mode) ? target : gen_reg_rtx (mode);
+
+  expand_vec_series (result, base, step);
+
+  if (result != target)
+emit_move_insn (target, result);
+}
+
 static void
 expand_const_vector (rtx target, rtx src)
 {
@@ -1237,13 +1249,7 @@ expand_const_vector (rtx target, rtx src)
   /* Support scalable const series vector.  */
   rtx base, step;
   if (const_vec_series_p (src, &base, &step))
-{
-  expand_vec_series (result, base, step);
-
-  if (result != target)
-   emit_move_insn (target, result);
-  return;
-}
+return expand_const_vec_series (target, base, step);
 
   /* Handle variable-length vector.  */
   unsigned int nelts_per_pattern = CONST_VECTOR_NELTS_PER_PATTERN (src);

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [PATCH] RISC-V: Imply C from Zca whenever possible [PR119122]

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:e7e5a1180b0e6b1be3ffd9c1222e492139607c67

commit e7e5a1180b0e6b1be3ffd9c1222e492139607c67
Author: Yuriy Kolerov 
Date:   Thu Apr 24 21:22:16 2025 -0600

[PATCH] RISC-V: Imply C from Zca whenever possible [PR119122]

GCC must imply C extension from Zca extension when it's
possible. It's necessary for achieving compatibility
between different march strings which in fact may be
the same.

E.g., if rv32ic multilib configuration is presented in
GCC, then GCC will not choose this configuration for
linking if -march=rv32i_zca is passed.

Here is a more practical example. From RISC-V
Instruction Set Manual:

Therefore common ISA strings can be updated as follows
to include the relevant Zc extensions, for example:
- RV32IMC becomes RV32IM_Zce
- RV32IMCF becomes RV32IMF_Zce

With current implication rules this will not work well
if rv32imc configuration is presented and a user
passes -march=rv32im_zce. This is how we can check
this with a simple empty test.c source file:

$ riscv64-unknown-elf-gcc -march=rv32ic -mabi=ilp32 -mriscv-attribute -S 
test.c
$ grep "attribute arch" test.s
.attribute arch, "rv32i2p1_c2p0_zca1p0"
$ riscv64-unknown-elf-gcc -march=rv32i_zce -mabi=ilp32 -mriscv-attribute -S 
test.c
$ grep "attribute arch" test.s
.attribute arch, 
"rv32i2p1_zicsr2p0_zca1p0_zcb1p0_zce1p0_zcmp1p0_zcmt1p0"

According to current GCC these march strings are
incompatible: the first one contains c2p0 and the
second on doesn't.

To introduce such implication rule we need to carefully
cover all possible combinations with these extensions:
zca, zcf, zcd, F and D.

According to the same manual:

As C defines the same instructions as Zca, Zcf and
Zcd, the rule is that:
- C always implies Zca
- C+F implies Zcf (RV32 only)
- C+D implies Zcd

Here is a full list of cases:

1. rv32i_zca implies C.
2. rv32if_zca_zcf implies C.
3. rv32ifd_zca_zcf_zcd implies C.
4. rv64i_zca implies C.
5. rv64ifd_zca_zcd implies C.

PR target/119122

gcc/ChangeLog:

* common/config/riscv/riscv-common.cc (riscv_implied_info): Add a 
rule
for Zca to C implication.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/arch-25.c: Fix dg-error expectation.
* gcc.target/riscv/attribute-c-1.c: New test.
* gcc.target/riscv/attribute-c-2.c: New test.
* gcc.target/riscv/attribute-c-3.c: New test.
* gcc.target/riscv/attribute-c-4.c: New test.
* gcc.target/riscv/attribute-c-5.c: New test.
* gcc.target/riscv/attribute-c-6.c: New test.
* gcc.target/riscv/attribute-c-7.c: New test.
* gcc.target/riscv/attribute-c-8.c: New test.
* gcc.target/riscv/attribute-zce-1.c: Update Zce tests.
* gcc.target/riscv/attribute-zce-2.c: Likewise.
* gcc.target/riscv/attribute-zce-3.c: Likewise
* gcc.target/riscv/attribute-zce-4.c: Likewise.

(cherry picked from commit 42ce61eaefc4db70e2e7ea2d8ef091daa458eb48)

Diff:
---
 gcc/common/config/riscv/riscv-common.cc  | 31 
 gcc/testsuite/gcc.target/riscv/arch-25.c |  2 +-
 gcc/testsuite/gcc.target/riscv/attribute-c-1.c   |  6 +
 gcc/testsuite/gcc.target/riscv/attribute-c-2.c   |  6 +
 gcc/testsuite/gcc.target/riscv/attribute-c-3.c   |  6 +
 gcc/testsuite/gcc.target/riscv/attribute-c-4.c   |  6 +
 gcc/testsuite/gcc.target/riscv/attribute-c-5.c   |  6 +
 gcc/testsuite/gcc.target/riscv/attribute-c-6.c   |  6 +
 gcc/testsuite/gcc.target/riscv/attribute-c-7.c   |  6 +
 gcc/testsuite/gcc.target/riscv/attribute-c-8.c   |  6 +
 gcc/testsuite/gcc.target/riscv/attribute-zce-1.c |  2 +-
 gcc/testsuite/gcc.target/riscv/attribute-zce-2.c |  2 +-
 gcc/testsuite/gcc.target/riscv/attribute-zce-3.c |  2 +-
 gcc/testsuite/gcc.target/riscv/attribute-zce-4.c |  2 +-
 14 files changed, 84 insertions(+), 5 deletions(-)

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index b34409adf39c..15df22d53770 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -218,6 +218,37 @@ static const riscv_implied_info_t riscv_implied_info[] =
{
  return subset_list->xlen () == 32 && subset_list->lookup ("f");
}},
+  {"zca", "c",
+   [] (const riscv_subset_list *subset_list) -> bool
+   {
+ /* For RV32 Zca implies C for one of these combinations of
+   extensions: Zca, F_Zca_Zcf and FD_Zca_Zcf_Zcd.  */
+ if (subset_list->xlen () == 32)
+   {
+if (subset_list->lookup ("d"))
+  return subset_list->lookup ("zcf") && subset_list->lo

[gcc/riscv/heads/gcc-15-with-riscv-opts] (83 commits) [RISC-V] Fix ICE due to bogus use of gen_rtvec

[Jeff Law via Gcc-cvs]

The branch 'riscv/heads/gcc-15-with-riscv-opts' was updated to point to:

 5159c19cb2a8... [RISC-V] Fix ICE due to bogus use of gen_rtvec

It previously pointed to:

 e968c7311c62... Alpha: Fix base block alignment calculation regression

Diff:

Summary of changes (added commits):
---

  5159c19... [RISC-V] Fix ICE due to bogus use of gen_rtvec
  8010f98... [RISC-V] Avoid setting output object more than once in IOR/
  99d801c... RISC-V: Since the loop increment i++ is unreachable, the lo
  6e73320... RISC-V: Avoid scalar unsigned SAT_ADD test data duplication
  84adfa2... Partial cherry-pick of 4dd13988c93c24ba3605f4b9cafc97515c34
  49278dd... Make end_sequence return the insn sequence
  9a8ca2f... RISC-V: Reuse test name for vx combine test data [NFC]
  76ecd76... RISC-V: Add test for vec_duplicate + vsub.vv combine case 1
  13a6e9f... RISC-V: Add test for vec_duplicate + vsub.vv combine case 1
  1a93ea8... RISC-V: Add test for vec_duplicate + vsub.vv combine case 1
  04f07ee... RISC-V: Add test for vec_duplicate + vsub.vv combine case 0
  c0cb19a... RISC-V: Add test for vec_duplicate + vsub.vv combine case 0
  7195b88... RISC-V: Add test for vec_duplicate + vsub.vv combine case 0
  8776c19... RISC-V: Adjust vx combine test case to avoid name conflict
  f6ae7c8... RISC-V: Rename vx_vadd-* testcase to vx-* for all vx combin
  6785ad3... RISC-V: Combine vec_duplicate + vsub.vv to vsub.vx on GR2VR
  103da6a... [RISC-V][PR target/120223] Don't use bset/binv for XTHEADBS
  5e6cb89... RISC-V: Fix uninit riscv_subset_list::m_allow_adding_dup is
  fa7576e... RISC-V: Add augmented hypervisor series extensions.
  b0fb9ba... RISC-V: Drop duplicate build rule for riscv-ext.opt [NFC]
  a4d3735... RISC-V: Regen riscv-ext.opt.urls
  8b77ff6... RISC-V: Drop riscv_ext_flag_table in favor of riscv_ext_inf
  1931c49... RISC-V: Drop riscv_ext_version_table in favor of riscv_ext_
  d5d13d9... RISC-V: Drop riscv_implied_info and riscv_combine_info in f
  1c2a373... RISC-V: Introduce riscv_ext_info_t to hold extension metada
  4d7dafb... RISC-V: Adjust riscv_can_inline_p
  ac1cfc5... RISC-V: Generate extension table in documentation from risc
  dff806e... RISC-V: Use riscv-ext.def to generate target options and va
  f63e8d3... RISC-V: Introduce riscv-ext*.def to define extensions
  194d03f... RISC-V: Add testcases for vector unsigned integer SAT_ADD f
  24f53c2... RISC-V: Add testcases for scalar unsigned integer SAT_ADD f
  9df770e... RISC-V: Minimal support for ssnpm, smnpm and smmpm extensio
  543db94... RISC-V: Support for zilsd and zclsd extensions.
  e63c207... testsuite: Fix RISC-V arch-52.c format issue.
  e887f88... RISC-V: Support RISC-V Profiles 23.
  7f87d18... RISC-V: Support RISC-V Profiles 20/22.
  7866e62... [V2][RISC-V] Synthesize more efficient IOR/XOR sequences
  ea263e8... [PATCH v2] RISC-V: Use vclmul for CRC expansion if availabl
  c118441... RISC-V: Add testcases for vec_duplicate + vadd.vv combine c
  621d370... RISC-V: Add testcases for vec_duplicate + vadd.vv combine c
  1072dae... RISC-V: Add testcases for vec_duplicate + vadd.vv combine c
  3045c15... RISC-V: Rename VX_BINARY test helper to VX_BINARY_CASE_0
  e6cdd98... RISC-V: Separate the test running of rvv vx_vf
  8ad5762... [RISC-V][PR target/120137][PR target/120154] Don't create o
  1953b5e... [PATCH] RISC-V: Minimal support for zama16b extension.
  832d5bc... [RISC-V] Avoid unnecessary andi with -1 argument
  71b1760... [PATCH] RISC-V: Minimal support for sdtrig and ssstrict ext
  a67f729... [PATCH] RISC-V: Recognized svadu and svade extension
  65d4610... [RISC-V][PR middle-end/114512] Recognize more bext idioms f
  9d9135a... RISC-V: Add testcases for vec_duplicate + vadd.vv combine w
  11b0993... RISC-V: Add testcases for vec_duplicate + vadd.vv combine w
  39e8197... RISC-V: Add testcases for vec_duplicate + vadd.vv combine w
  c5d906d... RISC-V: Combine vec_duplicate + vadd.vv to vadd.vx on GR2VR
  2ee71e5... RISC-V: Add gr2vr cost helper function
  9b6166d... RISC-V: Add new option --param=gpr2vr-cost= for rvv insn
  f792a2e... [RISC-V][PR target/119971] Avoid losing shift count masking
  b4ff83a... RISC-V: Fix gcc.target/riscv/predef-19.c [PR120054]
  6b9a261... RISC-V: Apply clang-format to genrvv-type-indexer.cc [NFC]
  10057e3... [V2][RISC-V] Trivial permutation constant derivation
  1cc79df... [RISC-V] Adjust rvv tests after recent jump threading chang
  f597a59... [PATCH] RISC-V: Implment H modifier for printing the next r
  f7d0410... [to-be-committed][RISC-V] Adjust testcases and finish regis
  1982909... RISC-V: Remove unnecessary frm restore volatile define_insn
  5179fed... RISC-V: Allow different dynamic floating point mode to be m
  5561ed0... RISC-V: Fix missing implied Zicsr from Zve32x
  2e800ed... RISC-V: Add intrinsics testcases for SiFive Xsfvcp extensio
  8633535... RISC-V: Add intrinsics support for SiFive Xsfvcp extensions
  2bf7f42... RISC-V: Fix register move cost for SIBCALL_REGS/

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [riscv] vec_dup immediate constants in pred_broadcast expand [PR118182]

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:9849e5ffa9cec8664b4ff4232b74ee0e33b4a537

commit 9849e5ffa9cec8664b4ff4232b74ee0e33b4a537
Author: Alexandre Oliva 
Date:   Mon Apr 21 22:48:55 2025 -0300

[riscv] vec_dup immediate constants in pred_broadcast expand [PR118182]

pr118182-2.c fails on gcc-14 because it lacks the late_combine passes,
particularly the one that runs after register allocation.

Even in the trunk, the predicate broadcast for the add reduction is
expanded and register-allocated as _zvfh, taking up an unneeded scalar
register to hold the constant to be vec_duplicated.

It is the late combine pass after register allocation that substitutes
this unneeded scalar register into the vec_duplicate, resolving to the
_zero or _imm insns.

It's easy enough and more efficient to expand pred_broadcast to the
insns that take the already-duplicated vector constant, when the
operands satisfy the predicates of the _zero or _imm insns.

for  gcc/ChangeLog

PR target/118182
* config/riscv/vector.md (@pred_broadcast): Expand to
_zero and _imm variants without vec_duplicate.

(cherry picked from commit 14fa625bcb91028cb97f3575d2e394401bbb4a3a)

Diff:
---
 gcc/config/riscv/vector.md | 22 --
 1 file changed, 20 insertions(+), 2 deletions(-)

diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 51eb64fb1226..3ab4d76e6c6a 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -2136,18 +2136,34 @@
 (match_operand 7 "const_int_operand")
 (reg:SI VL_REGNUM)
 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (vec_duplicate:V_VLS
-   (match_operand: 3 "direct_broadcast_operand"))
+ ;; (vec_duplicate:V_VLS ;; wrapper activated by wrap_vec_dup below.
+ (match_operand: 3 "direct_broadcast_operand") ;; )
  (match_operand:V_VLS 2 "vector_merge_operand")))]
   "TARGET_VECTOR"
 {
   /* Transform vmv.v.x/vfmv.v.f (avl = 1) into vmv.s.x since vmv.s.x/vfmv.s.f
  has better chances to do vsetvl fusion in vsetvl pass.  */
+  bool wrap_vec_dup = true;
+  rtx vec_cst = NULL_RTX;
   if (riscv_vector::splat_to_scalar_move_p (operands))
 {
   operands[1] = riscv_vector::gen_scalar_move_mask (mode);
   operands[3] = force_reg (mode, operands[3]);
 }
+  else if (immediate_operand (operands[3], mode)
+  && (vec_cst = gen_const_vec_duplicate (mode, operands[3]))
+  && (/* -> pred_broadcast_zero */
+  (vector_least_significant_set_mask_operand (operands[1],
+  mode)
+   && vector_const_0_operand (vec_cst, mode))
+  || (/* pred_broadcast_imm */
+  vector_all_trues_mask_operand (operands[1], mode)
+  && vector_const_int_or_double_0_operand (vec_cst,
+   mode
+{
+  operands[3] = vec_cst;
+  wrap_vec_dup = false;
+}
   /* Handle vmv.s.x instruction (Wb1 mask) which has memory scalar.  */
   else if (satisfies_constraint_Wdm (operands[3]))
 {
@@ -2191,6 +2207,8 @@
 ;
   else
 operands[3] = force_reg (mode, operands[3]);
+  if (wrap_vec_dup)
+operands[3] = gen_rtx_VEC_DUPLICATE (mode, operands[3]);
 })
 
 (define_insn_and_split "*pred_broadcast"

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [V2][RISC-V] Trivial permutation constant derivation

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:10057e3958cad6bde4963382422cd759e04feb7f

commit 10057e3958cad6bde4963382422cd759e04feb7f
Author: Jeff Law 
Date:   Sun May 4 16:59:51 2025 -0600

[V2][RISC-V] Trivial permutation constant derivation

This is a patch from late 2024 (just before stage1 freeze), but I never 
pushed
hard to the change, and thus never integrated it.

It's mostly unchanged except for updating insn in the hash table after 
finding
an optimizable case.  We were holding the deleted insn in the hash table 
rather
than the new insn.  Just something I noticed recently.

Bootstrapped and regression tested on my BPI and regression tested 
riscv32-elf
and riscv64-elf configurations.  We've used this since November internally, 
so
it's well exercised on spec as well.

gcc/
* config.gcc (riscv): Add riscv-vect-permcost.o to extra_objs.
* config/riscv/riscv-passes.def (pass_vector_permcost): Add new 
pass.
* config/riscv/riscv-protos.h (make_pass_vector_permconst): Declare.
* config/riscv/riscv-vect-permconst.cc: New file.
* config/riscv/t-riscv: Add build rule for riscv-vect-permcost.o

(cherry picked from commit 8094ab80e5623d240f48a4b932c06c08b9e124f2)

Diff:
---
 gcc/config.gcc   |   2 +-
 gcc/config/riscv/riscv-passes.def|   2 +
 gcc/config/riscv/riscv-protos.h  |   2 +
 gcc/config/riscv/riscv-vect-permconst.cc | 300 +++
 gcc/config/riscv/t-riscv |   7 +
 5 files changed, 312 insertions(+), 1 deletion(-)

diff --git a/gcc/config.gcc b/gcc/config.gcc
index d98df883fce5..2d4155b14e4d 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -550,7 +550,7 @@ pru-*-*)
 riscv*)
cpu_type=riscv
extra_objs="riscv-builtins.o riscv-c.o riscv-sr.o 
riscv-shorten-memrefs.o riscv-selftests.o riscv-string.o"
-   extra_objs="${extra_objs} riscv-v.o riscv-vsetvl.o riscv-vector-costs.o 
riscv-avlprop.o"
+   extra_objs="${extra_objs} riscv-v.o riscv-vsetvl.o riscv-vector-costs.o 
riscv-avlprop.o riscv-vect-permconst.o"
extra_objs="${extra_objs} riscv-vector-builtins.o 
riscv-vector-builtins-shapes.o riscv-vector-builtins-bases.o 
sifive-vector-builtins-bases.o"
extra_objs="${extra_objs} thead.o riscv-target-attr.o riscv-zicfilp.o"
d_target_objs="riscv-d.o"
diff --git a/gcc/config/riscv/riscv-passes.def 
b/gcc/config/riscv/riscv-passes.def
index 7e6a2a0e53d7..bc803c4678ed 100644
--- a/gcc/config/riscv/riscv-passes.def
+++ b/gcc/config/riscv/riscv-passes.def
@@ -21,3 +21,5 @@ INSERT_PASS_AFTER (pass_rtl_store_motion, 1, 
pass_shorten_memrefs);
 INSERT_PASS_AFTER (pass_split_all_insns, 1, pass_avlprop);
 INSERT_PASS_BEFORE (pass_fast_rtl_dce, 1, pass_vsetvl);
 INSERT_PASS_BEFORE (pass_shorten_branches, 1, pass_insert_landing_pad);
+INSERT_PASS_AFTER (pass_cse2, 1, pass_vector_permconst);
+
diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
index 2bedd878a04e..2e889903eb3a 100644
--- a/gcc/config/riscv/riscv-protos.h
+++ b/gcc/config/riscv/riscv-protos.h
@@ -201,6 +201,8 @@ rtl_opt_pass * make_pass_shorten_memrefs (gcc::context 
*ctxt);
 rtl_opt_pass * make_pass_avlprop (gcc::context *ctxt);
 rtl_opt_pass * make_pass_vsetvl (gcc::context *ctxt);
 rtl_opt_pass * make_pass_insert_landing_pad (gcc::context *ctxt);
+rtl_opt_pass * make_pass_vector_permconst (gcc::context *ctxt);
+
 
 /* Routines implemented in riscv-string.c.  */
 extern bool riscv_expand_block_compare (rtx, rtx, rtx, rtx);
diff --git a/gcc/config/riscv/riscv-vect-permconst.cc 
b/gcc/config/riscv/riscv-vect-permconst.cc
new file mode 100644
index ..feecc7ed6da0
--- /dev/null
+++ b/gcc/config/riscv/riscv-vect-permconst.cc
@@ -0,0 +1,300 @@
+/* Copyright (C) 2024 Free Software Foundation, Inc.
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 3, or(at your option)
+any later version.
+
+GCC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GCC; see the file COPYING3.  If not see
+.  */
+
+#define IN_TARGET_CODE 1
+#define INCLUDE_ALGORITHM
+#define INCLUDE_FUNCTIONAL
+#define INCLUDE_MEMORY
+
+#include "config.h"
+#include "system.h"
+#include "coretypes.h"
+#include "tm.h"
+#include "backend.h"
+#include "rtl.h"
+#include "target.h"
+#include "tree-pass.h"
+#include "df.h"
+#include "rtl-ssa.h"
+#include "cfgcleanup.h"
+#include "insn-attr.h"
+#include "tm-constrs.h"
+#include "insn-opinit.h"
+#include "cfgrtl.h"
+
+/* So the basic idea of this pass is t

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Apply clang-format to genrvv-type-indexer.cc [NFC]

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:6b9a26181b57b70d2fc478cd2cd7da5fd14f178f

commit 6b9a26181b57b70d2fc478cd2cd7da5fd14f178f
Author: Kito Cheng 
Date:   Mon May 5 10:16:14 2025 +0800

RISC-V: Apply clang-format to genrvv-type-indexer.cc [NFC]

Tweak the formatting of the genrvv-type-indexer.cc file to conform to
the style used by clang-format. This is a no-functional-change commit
that only modifies the formatting of the code.

gcc/Changelog:

* config/riscv/genrvv-type-indexer.cc: Apply clang-format to the
file.

(cherry picked from commit d3651f07bbf56837f019e366b75d01f197dab2f1)

Diff:
---
 gcc/config/riscv/genrvv-type-indexer.cc | 23 +++
 1 file changed, 15 insertions(+), 8 deletions(-)

diff --git a/gcc/config/riscv/genrvv-type-indexer.cc 
b/gcc/config/riscv/genrvv-type-indexer.cc
index 2fd429ad7348..f296089fbfe7 100644
--- a/gcc/config/riscv/genrvv-type-indexer.cc
+++ b/gcc/config/riscv/genrvv-type-indexer.cc
@@ -23,8 +23,14 @@ along with GCC; see the file COPYING3.  If not see
 #include 
 #include 
 
-#define BOOL_SIZE_LIST {1, 2, 4, 8, 16, 32, 64}
-#define EEW_SIZE_LIST {8, 16, 32, 64}
+#define BOOL_SIZE_LIST 
\
+  {
\
+1, 2, 4, 8, 16, 32, 64 
\
+  }
+#define EEW_SIZE_LIST  
\
+  {
\
+8, 16, 32, 64  
\
+  }
 #define LMUL1_LOG2 0
 
 std::string
@@ -167,7 +173,7 @@ floattype (unsigned sew, int lmul_log2)
 std::string
 expand_floattype (unsigned sew, int lmul_log2, unsigned nf)
 {
-  if (sew != 8 || nf!= 1
+  if (sew != 8 || nf != 1
   || (!valid_type (sew * 4, lmul_log2 + 2, /*float_t*/ true)))
 return "INVALID";
 
@@ -297,13 +303,13 @@ main (int argc, const char **argv)
 
   for (unsigned eew : EEW_SIZE_LIST)
fprintf (fp, "  /*SIGNED_EEW%d_LMUL1_INTERPRET*/ %s,\n", eew,
-inttype (eew, LMUL1_LOG2, /* unsigned_p */false).c_str ());
+inttype (eew, LMUL1_LOG2, /* unsigned_p */ false).c_str ());
 
   for (unsigned eew : EEW_SIZE_LIST)
fprintf (fp, "  /*UNSIGNED_EEW%d_LMUL1_INTERPRET*/ %s,\n", eew,
-inttype (eew, LMUL1_LOG2, /* unsigned_p */true).c_str ());
+inttype (eew, LMUL1_LOG2, /* unsigned_p */ true).c_str ());
 
-   fprintf (fp, "  /*X2*/ INVALID,\n");
+  fprintf (fp, "  /*X2*/ INVALID,\n");
 
   for (unsigned lmul_log2_offset : {1, 2, 3, 4, 5, 6})
{
@@ -428,8 +434,9 @@ main (int argc, const char **argv)
  fprintf (fp, "  /*UNSIGNED_EEW%d_LMUL1_INTERPRET*/ INVALID,\n",
   eew);
 
-   fprintf (fp, "  /*X2*/ %s,\n",
-inttype (sew * 2, lmul_log2 + 1, /*unsigned_p*/ 
true).c_str ());
+   fprintf (
+ fp, "  /*X2*/ %s,\n",
+ inttype (sew * 2, lmul_log2 + 1, /*unsigned_p*/ true).c_str ());
 
for (unsigned lmul_log2_offset : {1, 2, 3, 4, 5, 6})
  {

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [PATCH] RISC-V: Implment H modifier for printing the next register name

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:f597a596cf8cb7f89b7d1e944ddd4baaccff9019

commit f597a596cf8cb7f89b7d1e944ddd4baaccff9019
Author: Jin Ma 
Date:   Sun May 4 08:44:27 2025 -0600

[PATCH] RISC-V: Implment H modifier for printing the next register name

For RV32 inline assembly, when handling 64-bit integer data, it is
often necessary to process the lower and upper 32 bits separately.
Unfortunately, we can only output the current register name
(lower 32 bits) but not the next register name (upper 32 bits).

To address this, the modifier 'H' has been added to allow users
to handle the upper 32 bits of the data. While I believe the
modifier 'N' (representing the next register name) might be more
suitable for this functionality, 'N' is already in use.
Therefore, 'H' (representing the high register) was chosen instead.

Co-Authored-By: Dimitar Dimitrov 

gcc/ChangeLog:

* config/riscv/riscv.cc (riscv_print_operand): Add H.
* doc/extend.texi: Document for H.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/modifier-H-error-1.c: New test.
* gcc.target/riscv/modifier-H-error-2.c: New test.
* gcc.target/riscv/modifier-H.c: New test.

(cherry picked from commit 89e58171bae30eacf5e8a281eb4758b2712aeed2)

Diff:
---
 gcc/config/riscv/riscv.cc  | 22 ++
 gcc/doc/extend.texi|  1 +
 .../gcc.target/riscv/modifier-H-error-1.c  | 13 +
 .../gcc.target/riscv/modifier-H-error-2.c  | 11 +++
 gcc/testsuite/gcc.target/riscv/modifier-H.c| 22 ++
 5 files changed, 69 insertions(+)

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 064c12c49f3a..a0657323f65f 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -6879,6 +6879,7 @@ riscv_asm_output_opcode (FILE *asm_out_file, const char 
*p)
'T' Print shift-index of inverted single-bit mask OP.
'~' Print w if TARGET_64BIT is true; otherwise not print anything.
'N'  Print register encoding as integer (0-31).
+   'H'  Print the name of the next register for integer.
 
Note please keep this list and the list in riscv.md in sync.  */
 
@@ -7174,6 +7175,27 @@ riscv_print_operand (FILE *file, rtx op, int letter)
asm_fprintf (file, "%u", (regno - offset));
break;
   }
+case 'H':
+  {
+   if (!REG_P (op))
+ {
+   output_operand_lossage ("modifier 'H' require register operand");
+   break;
+ }
+   if (REGNO (op) > 31)
+ {
+   output_operand_lossage ("modifier 'H' is for integer registers 
only");
+   break;
+ }
+   if (REGNO (op) == 31)
+ {
+   output_operand_lossage ("modifier 'H' cannot be applied to R31");
+   break;
+ }
+
+   fputs (reg_names[REGNO (op) + 1], file);
+   break;
+  }
 default:
   switch (code)
{
diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
index 0978c4c41b25..212d24875584 100644
--- a/gcc/doc/extend.texi
+++ b/gcc/doc/extend.texi
@@ -12585,6 +12585,7 @@ The list below describes the supported modifiers and 
their effects for RISC-V.
 @item @code{z} @tab Print ''@code{zero}'' instead of 0 if the operand is an 
immediate with a value of zero.
 @item @code{i} @tab Print the character ''@code{i}'' if the operand is an 
immediate.
 @item @code{N} @tab Print the register encoding as integer (0 - 31).
+@item @code{H} @tab Print the name of the next register for integer.
 @end multitable
 
 @anchor{shOperandmodifiers}
diff --git a/gcc/testsuite/gcc.target/riscv/modifier-H-error-1.c 
b/gcc/testsuite/gcc.target/riscv/modifier-H-error-1.c
new file mode 100644
index ..43ecff6498e5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/modifier-H-error-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile { target { rv32 } } } */
+/* { dg-skip-if "" { *-*-* } { "-flto" } { "" } } */
+/* { dg-options "-march=rv32gc -mabi=ilp32d -O0" } */
+
+float foo ()
+{
+  float ret;
+  asm ("fld\t%H0,(a0)\n\t":"=f"(ret));
+
+  return ret;
+}
+
+/* { dg-error "modifier 'H' is for integer registers only" "" { target { 
"riscv*-*-*" } } 0 } */
diff --git a/gcc/testsuite/gcc.target/riscv/modifier-H-error-2.c 
b/gcc/testsuite/gcc.target/riscv/modifier-H-error-2.c
new file mode 100644
index ..db478b6ddf61
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/modifier-H-error-2.c
@@ -0,0 +1,11 @@
+/* { dg-do compile { target { rv32 } } } */
+/* { dg-skip-if "" { *-*-* } { "-flto" } { "" } } */
+/* { dg-options "-march=rv32gc -mabi=ilp32d -O0 " } */
+
+void foo ()
+{
+  register int x31 __asm__ ("x31");
+  asm ("li\t%H0,1\n\t":"=r"(x31));
+}
+
+/* { dg-error "modifier 'H' cannot be applied to R31" "" { target { 
"riscv*-*-*" } } 0 } */
diff --git a/gcc/testsuite/gcc.target/riscv/modifier-H.c 
b/gcc/testsuite/gcc.t

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [RISC-V][PR target/119971] Avoid losing shift count masking

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:f792a2e3714dceb4c1b3a8db2fa8b6066928d386

commit f792a2e3714dceb4c1b3a8db2fa8b6066928d386
Author: Jeff Law 
Date:   Mon May 5 17:14:29 2025 -0600

[RISC-V][PR target/119971] Avoid losing shift count masking

As is outlined in the PR, we have a few define_insn_and_split patterns which
optimize away explicit masking of shift/bit positions when the masking 
matches
what the hardware's behavior.

A small number of those define_insn_and_split patterns generate a single
instruction.  It's fairly elegant in that we were essentially just rewriting
the RTL to match an existing pattern.

In one case we'd do the rewriting and later turn a 32bit shift into a bset.
That's not safe because the masking of a 32bit shift uses 0x1f while 
masking on
bset uses 0x3f on rv64.   The net was incorrect code as seen in the BZ 
entry.

The fix is pretty simple.  There's no real reason we need to use a
define_insn_and_split.  It was just convenient.  Instead we can use a simple
define_insn.  That avoids a change in the masking behavior for the shift
count/bit position and the masking stays in the RTL.

I quickly scanned the entire port and didn't see any additional
define_insn_and_splits that obviously generated a single instruction outside
the shift/rotate space, though in the vector space that's nontrivial to
ascertain.

This was been run through my tester for the cross configurations, but not 
the
native bootstrap/regression test (yet).

PR target/119971
gcc/
* config/riscv/bitmanip.md (rotation with masked count): Rewrite
as define_insn patterns.  Fix formatting.
* config/riscv/riscv.md (shift with masked count): Similarly.

gcc/testsuite
* gcc.target/riscv/pr119971.c: New test.
* gcc.target/riscv/zbb-rol-ror-03.c: Adjust test slightly.

(cherry picked from commit 05d75c5bfcf923bc0258b79a08c5861590c5a2b9)

Diff:
---
 gcc/config/riscv/bitmanip.md| 59 +
 gcc/config/riscv/riscv.md   | 19 ++--
 gcc/testsuite/gcc.target/riscv/pr119971.c   | 24 ++
 gcc/testsuite/gcc.target/riscv/zbb-rol-ror-03.c |  2 +-
 4 files changed, 59 insertions(+), 45 deletions(-)

diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md
index d0919ece31f7..20d03dc8792d 100644
--- a/gcc/config/riscv/bitmanip.md
+++ b/gcc/config/riscv/bitmanip.md
@@ -423,39 +423,40 @@
   "rolw\t%0,%1,%2"
   [(set_attr "type" "bitmanip")])
 
-(define_insn_and_split "*3_mask"
-  [(set (match_operand:GPR 0 "register_operand" "= r")
-(bitmanip_rotate:GPR
-(match_operand:GPR 1 "register_operand" "  r")
-(match_operator 4 "subreg_lowpart_operator"
- [(and:GPR2
-   (match_operand:GPR2 2 "register_operand"  "r")
-   (match_operand 3 "" ""))])))]
+(define_insn "*3_mask"
+  [(set (match_operand:X 0 "register_operand" "=r")
+   (bitmanip_rotate:X
+ (match_operand:X 1 "register_operand" "r")
+ (match_operator 4 "subreg_lowpart_operator"
+   [(and:X (match_operand:X 2 "register_operand"  "r")
+   (match_operand 3 "" ""))])))]
   "TARGET_ZBB || TARGET_ZBKB"
-  "#"
-  "&& 1"
-  [(set (match_dup 0)
-(bitmanip_rotate:GPR (match_dup 1)
- (match_dup 2)))]
-  "operands[2] = gen_lowpart (QImode, operands[2]);"
+  "\t%0,%1,%2"
   [(set_attr "type" "bitmanip")
-   (set_attr "mode" "")])
+   (set_attr "mode" "")])
 
-(define_insn_and_split "*si3_sext_mask"
-  [(set (match_operand:DI 0 "register_operand" "= r")
-  (sign_extend:DI (bitmanip_rotate:SI
-(match_operand:SI 1 "register_operand" "  r")
-(match_operator 4 "subreg_lowpart_operator"
- [(and:GPR
-   (match_operand:GPR 2 "register_operand"  "r")
-   (match_operand 3 "const_si_mask_operand"))]]
+(define_insn "*3_mask_si"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+   (bitmanip_rotate:SI
+ (match_operand:SI 1 "register_operand" "r")
+ (match_operator 3 "subreg_lowpart_operator"
+   [(and:X (match_operand:SI 2 "register_operand"  "r")
+   (const_int 31))])))]
   "TARGET_64BIT && (TARGET_ZBB || TARGET_ZBKB)"
-  "#"
-  "&& 1"
-  [(set (match_dup 0)
-  (sign_extend:DI (bitmanip_rotate:SI (match_dup 1)
-   (match_dup 2]
-  "operands[2] = gen_lowpart (QImode, operands[2]);"
+  "w\t%0,%1,%2"
+  [(set_attr "type" "bitmanip")
+   (set_attr "mode" "SI")])
+
+(define_insn "*si3_sext_mask"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+   (sign_extend:DI
+ (bitmanip_rotate:SI
+   (match_operand:SI 1 "register_operand" "r")
+   (match_operator 3 "subreg_lowpart_operator"
+ [(and:X (match_operand:GPR 2 "regi

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Remove unnecessary frm restore volatile define_insn

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:19829091ddc47d7fdcd47cfcde5c7d2c0be20c13

commit 19829091ddc47d7fdcd47cfcde5c7d2c0be20c13
Author: Pan Li 
Date:   Sun May 4 09:26:02 2025 +0800

RISC-V: Remove unnecessary frm restore volatile define_insn

After we add the frm register to the global_regs, we may not need to
define_insn that volatile to emit the frm restore insns.  The
cooperatively-managed global register will help to handle this, instead
of emit the volatile define_insn explicitly.

gcc/ChangeLog:

* config/riscv/riscv.cc (riscv_emit_frm_mode_set): Refactor
the frm mode set by removing fsrmsi_restore_volatile.
* config/riscv/vector-iterators.md (unspecv): Remove as
unnecessary.
* config/riscv/vector.md (fsrmsi_restore_volatile): Ditto.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/base/float-point-dynamic-frm-49.c: Adjust
the asm dump check times.
* gcc.target/riscv/rvv/base/float-point-dynamic-frm-50.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-dynamic-frm-52.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-dynamic-frm-74.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-dynamic-frm-75.c: Ditto.

Signed-off-by: Pan Li 
(cherry picked from commit e5a4663bc6367920a1cce6babb367424790d9bc8)

Diff:
---
 gcc/config/riscv/riscv.cc  | 43 --
 gcc/config/riscv/vector-iterators.md   |  1 -
 gcc/config/riscv/vector.md | 13 ---
 .../riscv/rvv/base/float-point-dynamic-frm-49.c|  2 +-
 .../riscv/rvv/base/float-point-dynamic-frm-50.c|  2 +-
 .../riscv/rvv/base/float-point-dynamic-frm-52.c|  2 +-
 .../riscv/rvv/base/float-point-dynamic-frm-74.c|  2 +-
 .../riscv/rvv/base/float-point-dynamic-frm-75.c|  2 +-
 8 files changed, 28 insertions(+), 39 deletions(-)

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index ed635ab42f40..10e0f4adbdcf 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -12047,27 +12047,30 @@ riscv_emit_frm_mode_set (int mode, int prev_mode)
   if (prev_mode == riscv_vector::FRM_DYN_CALL)
 emit_insn (gen_frrmsi (backup_reg)); /* Backup frm when DYN_CALL.  */
 
-  if (mode != prev_mode)
-{
-  rtx frm = gen_int_mode (mode, SImode);
-
-  if (mode == riscv_vector::FRM_DYN_CALL
-   && prev_mode != riscv_vector::FRM_DYN && STATIC_FRM_P (cfun))
-   /* No need to emit when prev mode is DYN already.  */
-   emit_insn (gen_fsrmsi_restore_volatile (backup_reg));
-  else if (mode == riscv_vector::FRM_DYN_EXIT && STATIC_FRM_P (cfun)
-   && prev_mode != riscv_vector::FRM_DYN
-   && prev_mode != riscv_vector::FRM_DYN_CALL)
-   /* No need to emit when prev mode is DYN or DYN_CALL already.  */
-   emit_insn (gen_fsrmsi_restore_volatile (backup_reg));
-  else if (mode == riscv_vector::FRM_DYN
-   && prev_mode != riscv_vector::FRM_DYN_CALL)
-   /* Restore frm value from backup when switch to DYN mode.  */
-   emit_insn (gen_fsrmsi_restore (backup_reg));
-  else if (riscv_static_frm_mode_p (mode))
-   /* Set frm value when switch to static mode.  */
-   emit_insn (gen_fsrmsi_restore (frm));
+  if (mode == prev_mode)
+return;
+
+  if (riscv_static_frm_mode_p (mode))
+{
+  /* Set frm value when switch to static mode.  */
+  emit_insn (gen_fsrmsi_restore (gen_int_mode (mode, SImode)));
+  return;
 }
+
+  bool restore_p
+= /* No need to emit when prev mode is DYN.  */
+  (STATIC_FRM_P (cfun) && mode == riscv_vector::FRM_DYN_CALL
+   && prev_mode != riscv_vector::FRM_DYN)
+  /* No need to emit if prev mode is DYN or DYN_CALL.  */
+  || (STATIC_FRM_P (cfun) && mode == riscv_vector::FRM_DYN_EXIT
+ && prev_mode != riscv_vector::FRM_DYN
+ && prev_mode != riscv_vector::FRM_DYN_CALL)
+  /* Restore frm value when switch to DYN mode.  */
+  || (mode == riscv_vector::FRM_DYN
+ && prev_mode != riscv_vector::FRM_DYN_CALL);
+
+  if (restore_p)
+emit_insn (gen_fsrmsi_restore (backup_reg));
 }
 
 /* Implement Mode switching.  */
diff --git a/gcc/config/riscv/vector-iterators.md 
b/gcc/config/riscv/vector-iterators.md
index 5687e8a613c9..b4c869094f37 100644
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -124,7 +124,6 @@
 ])
 
 (define_c_enum "unspecv" [
-  UNSPECV_FRM_RESTORE_EXIT
   UNSPECV_SF_CV
 ])
 
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 5191ae488083..851ba4a9490a 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -1115,19 +1115,6 @@
(set_attr "mode" "SI")]
  )
 
-;; The volatile fsrmsi restore is used for the exit point for the
-;; dynamic mode switching. It will generate one volatile fsrm a5
-;; which won't be eliminated.
-(define_insn "fsrmsi_resto

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [to-be-committed][RISC-V] Adjust testcases and finish register move costing fix

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:f7d0410edf094d607da120f958c3d0b47d006e2c

commit f7d0410edf094d607da120f958c3d0b47d006e2c
Author: Jeff Law 
Date:   Sun May 4 08:28:56 2025 -0600

[to-be-committed][RISC-V] Adjust testcases and finish register move costing 
fix

The recent adjustment to more correctly cost register moves tripped a few
testsuite regressions.

I'm pretty torn on the thead test adjustments.  But in reality they only 
worked
because the register move costing was broken.  So I've reverted the scan-asm
part of those to a prior state for two of those tests.  The other was only
failing at -Og/-Oz which was added to the exclude list.

The other Zfa test is similar, but we can make the test behave with a 
suitable
-mtune option and thus preserve the test.

While investigating I also noted that vector moves aren't being handled
correctly for subclasses of the integer/fp register files.  So I fixed those
while I was in there.

Note this may have an impact on some of your work Pan.  I haven't followed 
the
changes from the last week or so due to illness.

Waiting on pre-commit's verdict, though it did spin through my tester
successfully, though not all of the regressions related to that change are
addressed (there's still one for rv32 I'll look at shortly).

gcc/
* config/riscv/riscv.cc (riscv_register_move_cost): Handle
subclasses with vector registers as well.

gcc/testsuite/

* gcc.target/riscv/xtheadfmemidx-xtheadfmv-medany.c: Adjust expected
output.
* gcc.target/riscv/xtheadfmemidx-zfa-medany.c: Likewise.
* gcc.target/riscv/xtheadfmv-fmv.c: Skip for -Os and -Oz.
* gcc.target/riscv/zfa-fmovh-fmovp.c: Use sifive-p400 tuning.

(cherry picked from commit 005424e3337a3234f95755e57ee41c061b6e4185)

Diff:
---
 gcc/config/riscv/riscv.cc   | 8 
 gcc/testsuite/gcc.target/riscv/xtheadfmemidx-xtheadfmv-medany.c | 4 +---
 gcc/testsuite/gcc.target/riscv/xtheadfmemidx-zfa-medany.c   | 4 +---
 gcc/testsuite/gcc.target/riscv/xtheadfmv-fmv.c  | 2 +-
 gcc/testsuite/gcc.target/riscv/zfa-fmovh-fmovp.c| 2 +-
 5 files changed, 8 insertions(+), 12 deletions(-)

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 10e0f4adbdcf..064c12c49f3a 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -9659,17 +9659,17 @@ riscv_register_move_cost (machine_mode mode,
 
   if (from == V_REGS)
 {
-  if (to == GR_REGS)
+  if (to_is_gpr)
return get_vector_costs ()->regmove->VR2GR;
-  else if (to == FP_REGS)
+  else if (to_is_fpr)
return get_vector_costs ()->regmove->VR2FR;
 }
 
   if (to == V_REGS)
 {
-  if (from == GR_REGS)
+  if (from_is_gpr)
return get_vector_costs ()->regmove->GR2VR;
-  else if (from == FP_REGS)
+  else if (from_is_fpr)
return get_vector_costs ()->regmove->FR2VR;
 }
 
diff --git a/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-xtheadfmv-medany.c 
b/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-xtheadfmv-medany.c
index 6746c3140578..38966fefad5d 100644
--- a/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-xtheadfmv-medany.c
+++ b/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-xtheadfmv-medany.c
@@ -35,6 +35,4 @@ double foo (int i, int j)
   return z;
 }
 
-/* { dg-final { scan-assembler-not {\mth\.flrd\M} } } */
-/* { dg-final { scan-assembler-times {\mlw\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mth\.fmv\.hw\.x\M} 3 } } */
+/* { dg-final { scan-assembler-times {\mth\.flrd\M} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-zfa-medany.c 
b/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-zfa-medany.c
index fb1ac2b735c3..f0d9c80d16f2 100644
--- a/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-zfa-medany.c
+++ b/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-zfa-medany.c
@@ -35,6 +35,4 @@ double foo (int i, int j)
   return z;
 }
 
-/* { dg-final { scan-assembler-not {\mth\.flrd\M} } } */
-/* { dg-final { scan-assembler-times {\mlw\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mfmvp\.d\.x\M} 3 } } */
+/* { dg-final { scan-assembler-times {\mth\.flrd\M} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/xtheadfmv-fmv.c 
b/gcc/testsuite/gcc.target/riscv/xtheadfmv-fmv.c
index 9b4e23784480..81b240eac577 100644
--- a/gcc/testsuite/gcc.target/riscv/xtheadfmv-fmv.c
+++ b/gcc/testsuite/gcc.target/riscv/xtheadfmv-fmv.c
@@ -1,6 +1,6 @@
 /* { dg-do compile { target { rv32 } } } */
 /* { dg-options "-march=rv32gc_xtheadfmv -mabi=ilp32d" } */
-/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Os" "-Oz"} } */
 
 double
 ll2d (long long ll)
diff --git a/gcc/testsuite/gcc.target/riscv/zfa-fmovh-fmovp.c 
b/gcc/testsuite/gcc.target/riscv/zfa-fmovh-fmovp.c
index 5a52adce36ac..150cfd7fc058 100644
--

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add gr2vr cost helper function

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:2ee71e58696e6b52f5f91d6daacc2a441c1b565e

commit 2ee71e58696e6b52f5f91d6daacc2a441c1b565e
Author: Pan Li 
Date:   Tue May 6 16:42:16 2025 +0800

RISC-V: Add gr2vr cost helper function

After we introduced the --param=gpr2vr-cost option to set the cost
value of when operation act from gpr to vr, we would like to introduce
a new helper function to get the cost of gp2vr.  And then make sure
all reference to gr2vr should go this helper function.

The helper function will pick up the GR2VR value if the above option is
not provided, or the default GR2VR will be returned.

gcc/ChangeLog:

* config/riscv/riscv-protos.h (get_gr2vr_cost): Add new decl to
get the cost of gr2vr.
* config/riscv/riscv-vector-costs.cc (costs::adjust_stmt_cost):
Leverage the helper function to get the cost of gr2vr.
* config/riscv/riscv.cc (riscv_register_move_cost): Ditto.
(riscv_builtin_vectorization_cost): Ditto.
(get_gr2vr_cost): Add new impl of the helper function.

Signed-off-by: Pan Li 
(cherry picked from commit 9e9eb78bf4b77a049be00fb9ab0047170f19c9ea)

Diff:
---
 gcc/config/riscv/riscv-protos.h|  1 +
 gcc/config/riscv/riscv-vector-costs.cc |  2 +-
 gcc/config/riscv/riscv.cc  | 19 +--
 3 files changed, 19 insertions(+), 3 deletions(-)

diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
index 2e889903eb3a..b0d5bbb8570b 100644
--- a/gcc/config/riscv/riscv-protos.h
+++ b/gcc/config/riscv/riscv-protos.h
@@ -836,6 +836,7 @@ struct riscv_tune_info {
 const struct riscv_tune_info *
 riscv_parse_tune (const char *, bool);
 const cpu_vector_cost *get_vector_costs ();
+int get_gr2vr_cost ();
 
 enum
 {
diff --git a/gcc/config/riscv/riscv-vector-costs.cc 
b/gcc/config/riscv/riscv-vector-costs.cc
index 167375ca7516..c28eecd1110e 100644
--- a/gcc/config/riscv/riscv-vector-costs.cc
+++ b/gcc/config/riscv/riscv-vector-costs.cc
@@ -1121,7 +1121,7 @@ costs::adjust_stmt_cost (enum vect_cost_for_stmt kind, 
loop_vec_info loop,
 {
 case scalar_to_vec:
   stmt_cost += (FLOAT_TYPE_P (vectype) ? costs->regmove->FR2VR
-   : costs->regmove->GR2VR);
+   : get_gr2vr_cost ());
   break;
 case vec_to_scalar:
   stmt_cost += (FLOAT_TYPE_P (vectype) ? costs->regmove->VR2FR
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index a0657323f65f..42d501a1291b 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -9690,7 +9690,7 @@ riscv_register_move_cost (machine_mode mode,
   if (to == V_REGS)
 {
   if (from_is_gpr)
-   return get_vector_costs ()->regmove->GR2VR;
+   return get_gr2vr_cost ();
   else if (from_is_fpr)
return get_vector_costs ()->regmove->FR2VR;
 }
@@ -12540,6 +12540,21 @@ get_vector_costs ()
   return costs;
 }
 
+/* Return the cost of operation that move from gpr to vr.
+   It will take the value of --param=gpr2vr_cost if it is provided.
+   Or the default regmove->GR2VR will be returned.  */
+
+int
+get_gr2vr_cost ()
+{
+  int cost = get_vector_costs ()->regmove->GR2VR;
+
+  if (gpr2vr_cost != GPR2VR_COST_UNPROVIDED)
+cost = gpr2vr_cost;
+
+  return cost;
+}
+
 /* Implement targetm.vectorize.builtin_vectorization_cost.  */
 
 static int
@@ -12606,7 +12621,7 @@ riscv_builtin_vectorization_cost (enum 
vect_cost_for_stmt type_of_cost,
{
  /* TODO: This is too pessimistic in case we can splat.  */
  int regmove_cost = fp ? costs->regmove->FR2VR
-   : costs->regmove->GR2VR;
+   : get_gr2vr_cost ();
  return (regmove_cost + common_costs->scalar_to_vec_cost)
* estimated_poly_value (TYPE_VECTOR_SUBPARTS (vectype));
}

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Allow different dynamic floating point mode to be merged [PR119832]

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:5179fed0c70da4bf756af61a3ec8bdb93524673c

commit 5179fed0c70da4bf756af61a3ec8bdb93524673c
Author: Kito Cheng 
Date:   Tue Apr 29 11:35:00 2025 +0800

RISC-V: Allow different dynamic floating point mode to be merged [PR119832]

Although we already try to set the mode needed to FRM_DYN after a function 
call,
there are still some corner cases where both FRM_DYN and FRM_DYN_CALL may 
appear
on incoming edges.

Therefore, we use TARGET_MODE_CONFLUENCE to tell GCC that FRM_DYN, 
FRM_DYN_CALL,
and FRM_DYN_EXIT modes are compatible.

gcc/ChangeLog:

PR target/119832
* config/riscv/riscv.cc (riscv_dynamic_frm_mode_p): New.
(riscv_mode_confluence): New.
(TARGET_MODE_CONFLUENCE): Define to riscv_mode_confluence.

gcc/testsuite/ChangeLog:

PR target/119832
* g++.target/riscv/pr119832.C: New test.

(cherry picked from commit e5d1f538bb7d2c7a7a4acf4a4516fa8933dc2888)

Diff:
---
 gcc/config/riscv/riscv.cc | 37 +++
 gcc/testsuite/g++.target/riscv/pr119832.C | 27 ++
 2 files changed, 64 insertions(+)

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index c53e0dd7a7d1..ed635ab42f40 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -12273,6 +12273,41 @@ riscv_mode_needed (int entity, rtx_insn *insn, 
HARD_REG_SET)
 }
 }
 
+/* Return TRUE if the rouding mode is dynamic.  */
+
+static bool
+riscv_dynamic_frm_mode_p (int mode)
+{
+  return mode == riscv_vector::FRM_DYN
+|| mode == riscv_vector::FRM_DYN_CALL
+|| mode == riscv_vector::FRM_DYN_EXIT;
+}
+
+/* Implement TARGET_MODE_CONFLUENCE.  */
+
+static int
+riscv_mode_confluence (int entity, int mode1, int mode2)
+{
+  switch (entity)
+{
+case RISCV_VXRM:
+  return VXRM_MODE_NONE;
+case RISCV_FRM:
+  {
+   /* FRM_DYN, FRM_DYN_CALL and FRM_DYN_EXIT are all compatible.
+  Although we already try to set the mode needed to FRM_DYN after a
+  function call, there are still some corner cases where both FRM_DYN
+  and FRM_DYN_CALL may appear on incoming edges.  */
+   if (riscv_dynamic_frm_mode_p (mode1)
+   && riscv_dynamic_frm_mode_p (mode2))
+ return riscv_vector::FRM_DYN;
+   return riscv_vector::FRM_NONE;
+  }
+default:
+  gcc_unreachable ();
+}
+}
+
 /* Return TRUE that an insn is asm.  */
 
 static bool
@@ -14356,6 +14391,8 @@ bool need_shadow_stack_push_pop_p ()
 #define TARGET_MODE_EMIT riscv_emit_mode_set
 #undef TARGET_MODE_NEEDED
 #define TARGET_MODE_NEEDED riscv_mode_needed
+#undef TARGET_MODE_CONFLUENCE
+#define TARGET_MODE_CONFLUENCE riscv_mode_confluence
 #undef TARGET_MODE_AFTER
 #define TARGET_MODE_AFTER riscv_mode_after
 #undef TARGET_MODE_ENTRY
diff --git a/gcc/testsuite/g++.target/riscv/pr119832.C 
b/gcc/testsuite/g++.target/riscv/pr119832.C
new file mode 100644
index ..f4dc480e6d59
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/pr119832.C
@@ -0,0 +1,27 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=rv64gcv -mabi=lp64 -ffast-math" } */
+
+struct ac  {
+  ~ac();
+  void u();
+};
+struct ae {
+  int s;
+  float *ag;
+};
+
+float c;
+
+void ak(ae *al, int n) {
+  ac d;
+  for (int i;i

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add new option --param=gpr2vr-cost= for rvv insn

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:9b6166da407a99002840f41515260dfc1b1f541f

commit 9b6166da407a99002840f41515260dfc1b1f541f
Author: Pan Li 
Date:   Tue May 6 16:26:06 2025 +0800

RISC-V: Add new option --param=gpr2vr-cost= for rvv insn

During investigate the combine from vec_dup and vop.vv into
vop.vx, we need to depend on the cost of the insn operate
from the gpr to vr, for example, vadd.vx.  Thus, for better
control and test, we introduce a new option, aka below:

--param=gpr2vr-cost=

To specific the cost value of the insn that operate from
the gpr to vr.

gcc/ChangeLog:

* config/riscv/riscv-opts.h (RVV_GR2VR_COST_UNPROVIDED): Add
new macro to indicate the param is not provided.
* config/riscv/riscv.opt: Add new option --pararm=gpr2vr-cost.

Signed-off-by: Pan Li 
(cherry picked from commit 17c1602d5e7b237357b94808399a68ab77d42640)

Diff:
---
 gcc/config/riscv/riscv-opts.h | 2 ++
 gcc/config/riscv/riscv.opt| 4 
 2 files changed, 6 insertions(+)

diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index 26fe228e0f82..9766b89b2dff 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -162,4 +162,6 @@ enum riscv_tls_type {
 #define TARGET_VECTOR_AUTOVEC_SEGMENT \
   (TARGET_VECTOR && riscv_mautovec_segment)
 
+#define GPR2VR_COST_UNPROVIDED -1
+
 #endif /* ! GCC_RISCV_OPTS_H */
diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
index 7515c8ea13dd..710248099b3c 100644
--- a/gcc/config/riscv/riscv.opt
+++ b/gcc/config/riscv/riscv.opt
@@ -579,6 +579,10 @@ Inline strlen calls if possible.
 Target RejectNegative Joined UInteger Var(riscv_strcmp_inline_limit) Init(64)
 Max number of bytes to compare as part of inlined strcmp/strncmp routines 
(default: 64).
 
+-param=gpr2vr-cost=
+Target RejectNegative Joined UInteger Var(gpr2vr_cost) 
Init(GPR2VR_COST_UNPROVIDED)
+Set the cost value of the rvv instruction when operate from GPR to VR.
+
 Enum
 Name(rvv_max_lmul) Type(enum rvv_max_lmul_enum)
 The RVV possible LMUL (-mrvv-max-lmul=):

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Fix gcc.target/riscv/predef-19.c [PR120054]

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:b4ff83abf7386acdec9b8c3c32e99a8b339be977

commit b4ff83abf7386acdec9b8c3c32e99a8b339be977
Author: Kito Cheng 
Date:   Mon May 5 10:08:22 2025 +0800

RISC-V: Fix gcc.target/riscv/predef-19.c [PR120054]

gcc/testsuite/ChangeLog:

PR target/120054
* gcc.target/riscv/predef-19.c: Adjust testcase.

(cherry picked from commit fcc74146e3e0bfd30f9ccc12359991d73fe928f9)

Diff:
---
 gcc/testsuite/gcc.target/riscv/predef-19.c | 4 
 1 file changed, 4 deletions(-)

diff --git a/gcc/testsuite/gcc.target/riscv/predef-19.c 
b/gcc/testsuite/gcc.target/riscv/predef-19.c
index ca3d57abca90..f2b4d9b30486 100644
--- a/gcc/testsuite/gcc.target/riscv/predef-19.c
+++ b/gcc/testsuite/gcc.target/riscv/predef-19.c
@@ -27,10 +27,6 @@ int main () {
 #error "__riscv_zicsr"
 #endif
 
-#if !defined(_riscv_zmmul)
-#error "__riscv_zmmul"
-#endif
-
 #if !defined(__riscv_zve32x)
 #error "__riscv_zve32x"
 #endif

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [RISC-V][PR middle-end/114512] Recognize more bext idioms for RISC-V

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:65d4610c7e794a3310ddfca0b16636e26e624685

commit 65d4610c7e794a3310ddfca0b16636e26e624685
Author: Shreya Munnangi 
Date:   Tue May 6 06:38:00 2025 -0600

[RISC-V][PR middle-end/114512] Recognize more bext idioms for RISC-V

This is Shreya's next chunk of work.  When I was looking for good bugs for 
her
to chase down I cam across PR114512.  While the bug isn't necessarily a 
RISC-V
specific bug, its testcases did show how we were failing to recognize 
certain
bit extraction idioms and how the lispy nature of RTL allows us to tackle 
these
issues in the combiner.

First, the bit position may be masked.  The RISC-V port does not define
SHIFT_COUNT_TRUNCATED for valid reasons.  So if we want to optimize away a 
mask
that matches what the hardware will do, we need suitable insns that include
that explicit masking.

In addition to needing to incorporate masking, the masking may happen in a
subword mode.  So we need to recognize the mask wrapped in a zero extension.

Those two captured the most common cases.

We can also have a single bit extraction implemented as a left shift of the 
bit
into the sign bit, then a right shift by the size of a word - 1.  These are
less common, but we did cover the case derived from the upstream bug report 
as
well as one class seen reviewing the instruction stream for spec2017.

Finally, extracting a single bit at a variable position from a constant as 
seen
with some regularity in spec2017.  In that scenario, combine's chosen split
point wasn't ideal (I forget what it selected, but it definitely wasn't
helpful).  So we've got a new splitter for this case as well.

Earlier versions of this have gone through my tester as well as a bootstrap 
and
regression cycle.  This version has just gone through a cycle in my tester 
(but
missed today's bootstrap cycle).

Waiting on the upstream pre-commit tester to render its verdict, but the 
plan
is to commit on Shreya's behalf once that's clean.

Co-authored-by: Jeff Law  

PR middle-end/114512
gcc/
* config/riscv/bitmanip.md (bext* patterns): New patterns for
bext recognition plus splitter for extracting variable bit from
a constant.
* config/riscv/predicates.md (bitpos_mask_operand): New predicate.

gcc/testsuite/
* gcc.target/riscv/pr114512.c: New test.

(cherry picked from commit 4cd741dcbd3729863ab005d7ec61a890e0a193f1)

Diff:
---
 gcc/config/riscv/bitmanip.md  |  74 
 gcc/config/riscv/predicates.md|   4 ++
 gcc/testsuite/gcc.target/riscv/pr114512.c | 109 ++
 3 files changed, 187 insertions(+)

diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md
index 20d03dc8792d..95df5331769e 100644
--- a/gcc/config/riscv/bitmanip.md
+++ b/gcc/config/riscv/bitmanip.md
@@ -1302,3 +1302,77 @@
 }
   DONE;
 })
+
+;; More forms of single bit extraction.  The RISC-V port does not
+;; define SHIFT_COUNT_TRUNCATED so we need forms where the bit position
+;; is masked.
+;;
+;; We could in theory use this for rv32 as well, but it probably does
+;; not occur in practice.  The bit position would need to be QI/HI mode,
+;; otherwise we would not need the zero extension.
+;;
+;; One could also argue that the zero extension is redundant and should
+;; have been optimized away during RTL simplification.
+(define_insn "*bextdi_position_ze_masked"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+   (zero_extract:DI (match_operand:DI 1 "register_operand" "r")
+(const_int 1)
+(zero_extend:DI
+ (and:SI (match_operand:SI 2 "register_operand" "r")
+ (const_int 63)]
+  "TARGET_64BIT && TARGET_ZBS"
+  "bext\t%0,%1,%2"
+  [(set_attr "type" "bitmanip")])
+
+;; Same as above, but without the extraneous zero_extend.
+(define_insn "*bextdi_position_ze_masked"
+  [(set (match_operand:X 0 "register_operand" "=r")
+   (zero_extract:X
+ (match_operand:X 1 "register_operand" "r")
+ (const_int 1)
+ (and:X (match_operand:SI 2 "register_operand" "r")
+(match_operand:SI 3 "bitpos_mask_operand" "n"]
+  "TARGET_64BIT && TARGET_ZBS"
+  "bext\t%0,%1,%2"
+  [(set_attr "type" "bitmanip")])
+
+
+;; Single bit extraction by first shifting it into the sign bit, then
+;; shifting it down to the low bit.
+(define_insn "*bext_position_masked"
+  [(set (match_operand:X 0 "register_operand" "=r")
+   (lshiftrt:X (ashift:X (match_operand:X 1 "register_operand" "r")
+ (match_operand:QI 2 "register_operand" "r"))
+   (match_operand:X 3 "bitpos_mask_operand" "n")))]
+  "TARGET_ZBS"
+  "bext\t%0,%1,%2"
+  [(set_attr "type" "bitmanip")])
+
+;;

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add testcases for vec_duplicate + vadd.vv combine when GR2VR cost 0

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:39e81979866a62ef67a2d0bbd7ce4c33a2e4011f

commit 39e81979866a62ef67a2d0bbd7ce4c33a2e4011f
Author: Pan Li 
Date:   Sat May 3 10:40:20 2025 +0800

RISC-V: Add testcases for vec_duplicate + vadd.vv combine when GR2VR cost 0

Add asm dump check and run test for vec_duplicate + vadd.vv combine
to vadd.vx.  Introduce new folder to hold all related testcases.

The below test suites are passed for this patch.
* The rv64gcv fully regression test.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/rvv.exp: Add new folder vx_vf for all
vec_dup + vv to vx testcases.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_run.h: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-i16.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-i32.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-i64.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-i8.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-u16.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-u32.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-u64.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-u8.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-i16.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-i32.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-i64.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-i8.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-u16.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-u32.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-u64.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-u8.c: New test.

Signed-off-by: Pan Li 
(cherry picked from commit 1276430a48e4f6bb592d9e3f8c92e62341f09446)

Diff:
---
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h |  17 +
 .../riscv/rvv/autovec/vx_vf/vx_binary_data.h   | 401 +
 .../riscv/rvv/autovec/vx_vf/vx_binary_run.h|  26 ++
 .../riscv/rvv/autovec/vx_vf/vx_vadd-1-i16.c|   8 +
 .../riscv/rvv/autovec/vx_vf/vx_vadd-1-i32.c|   8 +
 .../riscv/rvv/autovec/vx_vf/vx_vadd-1-i64.c|   8 +
 .../riscv/rvv/autovec/vx_vf/vx_vadd-1-i8.c |   8 +
 .../riscv/rvv/autovec/vx_vf/vx_vadd-1-u16.c|   8 +
 .../riscv/rvv/autovec/vx_vf/vx_vadd-1-u32.c|   8 +
 .../riscv/rvv/autovec/vx_vf/vx_vadd-1-u64.c|   8 +
 .../riscv/rvv/autovec/vx_vf/vx_vadd-1-u8.c |   8 +
 .../riscv/rvv/autovec/vx_vf/vx_vadd-run-1-i16.c|  14 +
 .../riscv/rvv/autovec/vx_vf/vx_vadd-run-1-i32.c|  14 +
 .../riscv/rvv/autovec/vx_vf/vx_vadd-run-1-i64.c|  14 +
 .../riscv/rvv/autovec/vx_vf/vx_vadd-run-1-i8.c |  14 +
 .../riscv/rvv/autovec/vx_vf/vx_vadd-run-1-u16.c|  14 +
 .../riscv/rvv/autovec/vx_vf/vx_vadd-run-1-u32.c|  14 +
 .../riscv/rvv/autovec/vx_vf/vx_vadd-run-1-u64.c|  14 +
 .../riscv/rvv/autovec/vx_vf/vx_vadd-run-1-u8.c |  14 +
 gcc/testsuite/gcc.target/riscv/rvv/rvv.exp |   2 +
 20 files changed, 622 insertions(+)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h
new file mode 100644
index ..66654eb90227
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h
@@ -0,0 +1,17 @@
+#ifndef HAVE_DEFINED_VX_VF_BINARY_H
+#define HAVE_DEFINED_VX_VF_BINARY_H
+
+#include 
+
+#define DEF_VX_BINARY(T, OP)\
+void\
+test_vx_binary (T * restrict out, T * restrict in, T x, unsigned n) \
+{   \
+  for (unsigned i = 0; i < n; i++)  \
+out[i] = in[i] OP x;\
+}
+#define DEF_VX_BINARY_WRAP(T, OP) DEF_VX_BINARY(T, OP)
+#define RUN_VX_BINARY(out, in, x, n)  test_vx_binary(out, in, x, n)
+#define RUN_VX_BINARY_WRAP(out, in, x, n) RUN_VX_BINARY(out, in, x, n)
+
+#endif
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h
new file mode 100644
index ..11a32cbbf0fc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h
@@ -0,0 +1,401 @@
+#ifndef HAVE_DEFINED_VX_BINARY_DATA_H
+#define HAVE_DEFINED_VX_BINARY_DATA_H
+
+#define N 16
+
+#define TEST_BINARY_DATA(T, NAME)  test_##T##_##NAME##_data
+#define TEST_B

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [PATCH] RISC-V: Recognized svadu and svade extension

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:a67f729717304f4bb533f305ee0f4aae7b1879b9

commit a67f729717304f4bb533f305ee0f4aae7b1879b9
Author: Mingzhu Yan 
Date:   Tue May 6 16:59:09 2025 -0600

[PATCH] RISC-V: Recognized svadu and svade extension

This patch support svadu and svade extension.
To enable GCC to recognize and process svadu and svade extension correctly 
at compile time.

gcc/ChangeLog:

* common/config/riscv/riscv-common.cc (riscv_ext_version_table): New
extension.
(riscv_ext_flag_table) Ditto.
* config/riscv/riscv.opt: New mask.

* doc/invoke.texi (RISC-V Options): New extension

gcc/testsuite/ChangeLog:

* gcc.target/riscv/arch-45.c: New test.
* gcc.target/riscv/arch-46.c: New test.

(cherry picked from commit aed2a447c7ff4282621aa7941f840cb2ddc90354)

Diff:
---
 gcc/common/config/riscv/riscv-common.cc  | 10 +++---
 gcc/config/riscv/riscv.opt   |  4 
 gcc/doc/invoke.texi  |  8 
 gcc/testsuite/gcc.target/riscv/arch-45.c |  5 +
 gcc/testsuite/gcc.target/riscv/arch-46.c |  5 +
 5 files changed, 29 insertions(+), 3 deletions(-)

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index 145a0f2bd95f..58c7d205b336 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -441,6 +441,8 @@ static const struct riscv_ext_version 
riscv_ext_version_table[] =
   {"ssstateen", ISA_SPEC_CLASS_NONE, 1, 0},
   {"sstc",  ISA_SPEC_CLASS_NONE, 1, 0},
 
+  {"svade",   ISA_SPEC_CLASS_NONE, 1, 0},
+  {"svadu",   ISA_SPEC_CLASS_NONE, 1, 0},
   {"svinval", ISA_SPEC_CLASS_NONE, 1, 0},
   {"svnapot", ISA_SPEC_CLASS_NONE, 1, 0},
   {"svpbmt",  ISA_SPEC_CLASS_NONE, 1, 0},
@@ -1764,9 +1766,11 @@ static const riscv_ext_flag_table_t 
riscv_ext_flag_table[] =
   RISCV_EXT_FLAG_ENTRY ("zcmp", x_riscv_zc_subext, MASK_ZCMP),
   RISCV_EXT_FLAG_ENTRY ("zcmt", x_riscv_zc_subext, MASK_ZCMT),
 
-  RISCV_EXT_FLAG_ENTRY ("svinval", x_riscv_sv_subext, MASK_SVINVAL),
-  RISCV_EXT_FLAG_ENTRY ("svnapot", x_riscv_sv_subext, MASK_SVNAPOT),
-  RISCV_EXT_FLAG_ENTRY ("svvptc", x_riscv_sv_subext, MASK_SVVPTC),
+  RISCV_EXT_FLAG_ENTRY ("svade",   x_riscv_sv_subext, MASK_SVADE),
+  RISCV_EXT_FLAG_ENTRY ("svadu",   x_riscv_sv_subext, MASK_SVADU),
+  RISCV_EXT_FLAG_ENTRY ("svinval", x_riscv_sv_subext, MASK_SVINVAL),
+  RISCV_EXT_FLAG_ENTRY ("svnapot", x_riscv_sv_subext, MASK_SVNAPOT),
+  RISCV_EXT_FLAG_ENTRY ("svvptc",  x_riscv_sv_subext, MASK_SVVPTC),
 
   RISCV_EXT_FLAG_ENTRY ("ztso", x_riscv_ztso_subext, MASK_ZTSO),
 
diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
index 710248099b3c..9e471be4055c 100644
--- a/gcc/config/riscv/riscv.opt
+++ b/gcc/config/riscv/riscv.opt
@@ -466,6 +466,10 @@ Mask(XCVBI) Var(riscv_xcv_subext)
 TargetVariable
 int riscv_sv_subext
 
+Mask(SVADE) Var(riscv_sv_subext)
+
+Mask(SVADU) Var(riscv_sv_subext)
+
 Mask(SVINVAL) Var(riscv_sv_subext)
 
 Mask(SVNAPOT) Var(riscv_sv_subext)
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index f420f9e2519a..a7c8d6a89078 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -31506,6 +31506,14 @@ to @samp{zvks} and @samp{zvkg}.
 @tab 1.0
 @tab Supervisor-mode timer interrupts extension.
 
+@item svade
+@tab 1.0
+@tab Cause exception when hardware updating of A/D bits is disabled
+
+@item svadu
+@tab 1.0
+@tab Hardware Updating of A/D Bits extension.
+
 @item svinval
 @tab 1.0
 @tab Fine-grained address-translation cache invalidation extension.
diff --git a/gcc/testsuite/gcc.target/riscv/arch-45.c 
b/gcc/testsuite/gcc.target/riscv/arch-45.c
new file mode 100644
index ..afffb9955785
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/arch-45.c
@@ -0,0 +1,5 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_svadu -mabi=lp64" } */
+int foo()
+{
+}
diff --git a/gcc/testsuite/gcc.target/riscv/arch-46.c 
b/gcc/testsuite/gcc.target/riscv/arch-46.c
new file mode 100644
index ..2a062172e754
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/arch-46.c
@@ -0,0 +1,5 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_svade -mabi=lp64" } */
+int foo()
+{
+}

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Combine vec_duplicate + vadd.vv to vadd.vx on GR2VR cost

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:c5d906ddb149012d82dadade77265d8046329f73

commit c5d906ddb149012d82dadade77265d8046329f73
Author: Pan Li 
Date:   Thu May 1 21:23:54 2025 +0800

RISC-V: Combine vec_duplicate + vadd.vv to vadd.vx on GR2VR cost

This patch would like to combine the vec_duplicate + vadd.vv to the
vadd.vx.  From example as below code.  The related pattern will depend
on the cost of vec_duplicate from GR2VR, it will:

* The pattern matching will be active by default.
* The cost of GR2VR will be added to the total cost of pattern, aka:
  vec_dup cost = gr2vr_cost
  vadd.vv v, (vec_dup (x)) = gr2vr_cost + 1

Then the late-combine will take action if the cost of GR2VR is zero,
and reject the combination if the GR2VR cost is greater than zero.

Assume we have example code like below, GR2VR cost is 0.

  #define DEF_VX_BINARY(T, OP)\
  void\
  test_vx_binary (T * restrict out, T * restrict in, T x, unsigned n) \
  {   \
for (unsigned i = 0; i < n; i++)  \
  out[i] = in[i] OP x;\
  }

  DEF_VX_BINARY(int32_t, +)

Before this patch:
  10   │ test_binary_vx_add:
  11   │ beq a3,zero,.L8
  12   │ vsetvli a5,zero,e32,m1,ta,ma // Deleted if GR2VR cost zero
  13   │ vmv.v.x v2,a2// Ditto.
  14   │ sllia3,a3,32
  15   │ srlia3,a3,32
  16   │ .L3:
  17   │ vsetvli a5,a3,e32,m1,ta,ma
  18   │ vle32.v v1,0(a1)
  19   │ sllia4,a5,2
  20   │ sub a3,a3,a5
  21   │ add a1,a1,a4
  22   │ vadd.vv v1,v2,v1
  23   │ vse32.v v1,0(a0)
  24   │ add a0,a0,a4
  25   │ bne a3,zero,.L3

After this patch:
  10   │ test_binary_vx_add:
  11   │ beq a3,zero,.L8
  12   │ sllia3,a3,32
  13   │ srlia3,a3,32
  14   │ .L3:
  15   │ vsetvli a5,a3,e32,m1,ta,ma
  16   │ vle32.v v1,0(a1)
  17   │ sllia4,a5,2
  18   │ sub a3,a3,a5
  19   │ add a1,a1,a4
  20   │ vadd.vx v1,v1,a2
  21   │ vse32.v v1,0(a0)
  22   │ add a0,a0,a4
  23   │ bne a3,zero,.L3

The below test suites are passed for this patch.
* The rv64gcv fully regression test.

gcc/ChangeLog:

* config/riscv/autovec-opt.md (*_vx_): Add new
combine to convert vec_duplicate + vadd.vv to vaddvx on GR2VR
cost.
* config/riscv/riscv.cc (riscv_rtx_costs): Take care of the cost
when vec_dup and vadd v, vec_dup(x).
* config/riscv/vector-iterators.md: Add new iterator for vx.

Signed-off-by: Pan Li 
(cherry picked from commit 2b5baada614af7a4d0ee49aa962c7e1f7be3)

Diff:
---
 gcc/config/riscv/autovec-opt.md  | 23 +++
 gcc/config/riscv/riscv.cc| 35 ++-
 gcc/config/riscv/vector-iterators.md |  4 
 3 files changed, 61 insertions(+), 1 deletion(-)

diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md
index 0c3b0cc7e05f..7cf7e8a92ba1 100644
--- a/gcc/config/riscv/autovec-opt.md
+++ b/gcc/config/riscv/autovec-opt.md
@@ -1673,3 +1673,26 @@
 DONE;
   }
   [(set_attr "type" "vandn")])
+
+
+;; 
=
+;; Combine vec_duplicate + op.vv to op.vx
+;; Include
+;; - vadd.vx
+;; 
=
+(define_insn_and_split "*_vx_"
+ [(set (match_operand:V_VLSI0 "register_operand")
+   (any_int_binop_no_shift_vx:V_VLSI
+(vec_duplicate:V_VLSI
+  (match_operand: 1 "register_operand"))
+(match_operand:V_VLSI  2 "")))]
+  "TARGET_VECTOR && can_create_pseudo_p ()"
+  "#"
+  "&& 1"
+  [(const_int 0)]
+  {
+rtx ops[] = {operands[0], operands[2], operands[1]};
+riscv_vector::emit_vlmax_insn (code_for_pred_scalar (, mode),
+  riscv_vector::BINARY_OP, ops);
+  }
+  [(set_attr "type" "vialu")])
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 42d501a1291b..3ee88db24fa5 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -3863,7 +3863,40 @@ riscv_rtx_costs (rtx x, machine_mode mode, int 
outer_code, int opno ATTRIBUTE_UN
  Cost Model need to be well analyzed and supported in the future. */
   if (riscv_v_ext_mode_p (mode))
 {
-  *total = COSTS_N_INSNS (1);
+  int gr2vr_cost = get_gr2vr_cost ();
+
+  switch (outer_code)
+   {
+   case SET:
+ {
+   switch (GET_CODE (x))
+ {
+ case VEC_DUPLICATE

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add testcases for vec_duplicate + vadd.vv combine when GR2VR cost 1

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:11b0993fb65e83a2298851de58ba264a3cac320b

commit 11b0993fb65e83a2298851de58ba264a3cac320b
Author: Pan Li 
Date:   Sat May 3 11:27:50 2025 +0800

RISC-V: Add testcases for vec_duplicate + vadd.vv combine when GR2VR cost 1

Add asm dump check and for vec_duplicate + vadd.vv combine to vadd.vx.
The late-combine will not take action when GR2VR cost is 1.

The below test suites are passed for this patch.
* The rv64gcv fully regression test.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-i16.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-i32.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-i64.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-i8.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-u16.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-u32.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-u64.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-u8.c: New test.

Signed-off-by: Pan Li 
(cherry picked from commit c10491efc108bd4fc2d983bcabb50506d09e2a17)

Diff:
---
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-i16.c | 8 
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-i32.c | 8 
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-i64.c | 8 
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-i8.c  | 8 
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-u16.c | 8 
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-u32.c | 8 
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-u64.c | 8 
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-u8.c  | 8 
 8 files changed, 64 insertions(+)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-i16.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-i16.c
new file mode 100644
index ..eb19938afe56
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-i16.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=1" } */
+
+#include "vx_binary.h"
+
+DEF_VX_BINARY(int16_t, +)
+
+/* { dg-final { scan-assembler-not {vadd.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-i32.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-i32.c
new file mode 100644
index ..24182c51811e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-i32.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=1" } */
+
+#include "vx_binary.h"
+
+DEF_VX_BINARY(int32_t, +)
+
+/* { dg-final { scan-assembler-not {vadd.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-i64.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-i64.c
new file mode 100644
index ..b3d3d4b7d209
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-i64.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=1" } */
+
+#include "vx_binary.h"
+
+DEF_VX_BINARY(int64_t, +)
+
+/* { dg-final { scan-assembler-not {vadd.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-i8.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-i8.c
new file mode 100644
index ..fb353151b53c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-i8.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=1" } */
+
+#include "vx_binary.h"
+
+DEF_VX_BINARY(int8_t, +)
+
+/* { dg-final { scan-assembler-not {vadd.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-u16.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-u16.c
new file mode 100644
index ..6ba265893f15
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-u16.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=1" } */
+
+#include "vx_binary.h"
+
+DEF_VX_BINARY(uint16_t, +)
+
+/* { dg-final { scan-assembler-not {vadd.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-u32.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-u32.c
new file mode 100644
index ..b60412cecfa1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-u32.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=1" } */
+
+#include "vx_binary.h"
+
+DEF_VX_BINARY(uint32_t, +)
+
+/* { dg-final { scan-assembler-not {vadd.vx} } } */
diff --git a/gcc/testsuite/g

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Rename VX_BINARY test helper to VX_BINARY_CASE_0

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:3045c158c7fc484d012aa38d00a01d0caf00ab00

commit 3045c158c7fc484d012aa38d00a01d0caf00ab00
Author: Pan Li 
Date:   Wed May 7 20:48:40 2025 +0800

RISC-V: Rename VX_BINARY test helper to VX_BINARY_CASE_0

This patch would like to rename the VX_BINARY within CASE_0 suffix, as
we have another case of VX_BINARY test code.  Aka case 1:

L1:
  vmv.v.x
  vadd.vv
  J L1

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h: Rename VX_BINARY
to VX_BINARY_CASE_0 for underlying case 1.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-i16.c: Take the
new name for test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-i32.c: Ditto
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-i64.c: Ditto
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-i8.c: Ditto
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-u16.c: Ditto
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-u32.c: Ditto
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-u64.c: Ditto
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-u8.c: Ditto
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-i16.c: Ditto
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-i32.c: Ditto
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-i64.c: Ditto
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-i8.c: Ditto
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-u16.c: Ditto
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-u32.c: Ditto
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-u64.c: Ditto
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-u8.c: Ditto
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-i16.c: Ditto
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-i32.c: Ditto
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-i64.c: Ditto
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-i8.c: Ditto
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-u16.c: Ditto
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-u32.c: Ditto
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-u64.c: Ditto
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-u8.c: Ditto
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-i16.c: Ditto
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-i32.c: Ditto
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-i64.c: Ditto
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-i8.c: Ditto
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-u16.c: Ditto
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-u32.c: Ditto
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-u64.c: Ditto
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-u8.c: Ditto

Signed-off-by: Pan Li 
(cherry picked from commit cd694ab6c758cdbcf5f8816a0f2bd70448681c6a)

Diff:
---
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h | 18 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-i16.c |  2 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-i32.c |  2 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-i64.c |  2 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-i8.c  |  2 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-u16.c |  2 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-u32.c |  2 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-u64.c |  2 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-u8.c  |  2 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-i16.c |  2 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-i32.c |  2 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-i64.c |  2 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-i8.c  |  2 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-u16.c |  2 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-u32.c |  2 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-u64.c |  2 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-u8.c  |  2 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-i16.c |  2 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-i32.c |  2 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-i64.c |  2 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-i8.c  |  2 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-u16.c |  2 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-u32.c |  2 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-u64.c |  2 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-u8.c  |  2 +-
 .../riscv/rvv/autovec/vx_vf/vx_vadd-run-1-i16.c|  4 ++--
 .../riscv/rvv/autovec/vx_vf/vx_vadd-run-1-i32.c|  4 ++--
 .../riscv/rvv/autovec/vx_vf/vx_vadd-run-1-i64.c|  4 ++--
 .../riscv/rvv/autovec/vx_vf/vx_vadd-run-1-i8.c |  4 ++--
 .../riscv/rvv/autovec/vx_vf/vx_vadd-run-1-u16

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add testcases for vec_duplicate + vadd.vv combine case 1 with GR2VR cost 1

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:621d37036de337277e1e942423cb7d98ddcae76f

commit 621d37036de337277e1e942423cb7d98ddcae76f
Author: Pan Li 
Date:   Thu May 8 11:21:35 2025 +0800

RISC-V: Add testcases for vec_duplicate + vadd.vv combine case 1 with GR2VR 
cost 1

Add asm dump check and for vec_duplicate + vadd.vv combine case 1 to vadd.vx
with the cost of GR2VR is 1.  The testcases is not that tidy according
to the result, but we will continue tuning the cost model for this.

The below test suites are passed for this patch.
* The rv64gcv fully regression test.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-i16.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-i32.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-i64.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-i8.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-u16.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-u32.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-u64.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-u8.c: New test.

Signed-off-by: Pan Li 
(cherry picked from commit 6a718d401d37880a5ed74210b1a75783e8ea9c38)

Diff:
---
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-i16.c | 8 
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-i32.c | 8 
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-i64.c | 8 
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-i8.c  | 8 
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-u16.c | 8 
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-u32.c | 8 
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-u64.c | 8 
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-u8.c  | 8 
 8 files changed, 64 insertions(+)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-i16.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-i16.c
new file mode 100644
index ..e5ec8884fc71
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-i16.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=1" } */
+
+#include "vx_binary.h"
+
+DEF_VX_BINARY_CASE_1(int16_t, +, VX_BINARY_BODY_X8)
+
+/* { dg-final { scan-assembler-not {vadd.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-i32.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-i32.c
new file mode 100644
index ..ed6c22d059f6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-i32.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=1" } */
+
+#include "vx_binary.h"
+
+DEF_VX_BINARY_CASE_1(int32_t, +, VX_BINARY_BODY_X4)
+
+/* { dg-final { scan-assembler {vadd.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-i64.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-i64.c
new file mode 100644
index ..ef44012e418f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-i64.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=1" } */
+
+#include "vx_binary.h"
+
+DEF_VX_BINARY_CASE_1(int64_t, +, VX_BINARY_BODY)
+
+/* { dg-final { scan-assembler {vadd.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-i8.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-i8.c
new file mode 100644
index ..d61f9dfbb2b9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-i8.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=1" } */
+
+#include "vx_binary.h"
+
+DEF_VX_BINARY_CASE_1(int8_t, +, VX_BINARY_BODY_X16)
+
+/* { dg-final { scan-assembler-not {vadd.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-u16.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-u16.c
new file mode 100644
index ..3d1ba7f07422
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-u16.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=1" } */
+
+#include "vx_binary.h"
+
+DEF_VX_BINARY_CASE_1(uint16_t, +, VX_BINARY_BODY_X8)
+
+/* { dg-final { scan-assembler {vadd.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-u32.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-u32.c
new file mode 100644
index ..2e9862be6b22
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-u32.c

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add testcases for vec_duplicate + vadd.vv combine case 1 with GR2VR cost 2

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:c118441b67c334fbb810bb6ffece8940706b75e0

commit c118441b67c334fbb810bb6ffece8940706b75e0
Author: Pan Li 
Date:   Thu May 8 11:25:04 2025 +0800

RISC-V: Add testcases for vec_duplicate + vadd.vv combine case 1 with GR2VR 
cost 2

Add asm dump check and for vec_duplicate + vadd.vv combine case 1 to vadd.vx
with the cost of GR2VR is 2.  The testcases is not that tidy according
to the result, but we will continue tuning the cost model for this.

The below test suites are passed for this patch.
* The rv64gcv fully regression test.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-i16.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-i32.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-i64.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-i8.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-u16.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-u32.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-u64.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-u8.c: New test.

Signed-off-by: Pan Li 
(cherry picked from commit 8dba9c7ec97ef6e5e891c77a0f0d536860172beb)

Diff:
---
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-i16.c | 8 
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-i32.c | 8 
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-i64.c | 8 
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-i8.c  | 8 
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-u16.c | 9 +
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-u32.c | 8 
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-u64.c | 8 
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-u8.c  | 8 
 8 files changed, 65 insertions(+)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-i16.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-i16.c
new file mode 100644
index ..d80f0c07d55d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-i16.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=2" } */
+
+#include "vx_binary.h"
+
+DEF_VX_BINARY_CASE_1(int16_t, +, VX_BINARY_BODY_X8)
+
+/* { dg-final { scan-assembler-not {vadd.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-i32.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-i32.c
new file mode 100644
index ..99f6614eb7e6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-i32.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=2" } */
+
+#include "vx_binary.h"
+
+DEF_VX_BINARY_CASE_1(int32_t, +, VX_BINARY_BODY_X4)
+
+/* { dg-final { scan-assembler {vadd.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-i64.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-i64.c
new file mode 100644
index ..ab06c51914ba
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-i64.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=2" } */
+
+#include "vx_binary.h"
+
+DEF_VX_BINARY_CASE_1(int64_t, +, VX_BINARY_BODY)
+
+/* { dg-final { scan-assembler-not {vadd.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-i8.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-i8.c
new file mode 100644
index ..7ead9d09b793
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-i8.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=2" } */
+
+#include "vx_binary.h"
+
+DEF_VX_BINARY_CASE_1(int8_t, +, VX_BINARY_BODY_X16)
+
+/* { dg-final { scan-assembler-not {vadd.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-u16.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-u16.c
new file mode 100644
index ..79b754b934ac
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-u16.c
@@ -0,0 +1,9 @@
+
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=2" } */
+
+#include "vx_binary.h"
+
+DEF_VX_BINARY_CASE_1(uint16_t, +, VX_BINARY_BODY_X8)
+
+/* { dg-final { scan-assembler {vadd.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-u32.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-u32.c
new file mode 100644
index ..2f70dcd11977
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [RISC-V] Avoid unnecessary andi with -1 argument

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:832d5bcef5e49b31358e61525f0d001e776cec34

commit 832d5bcef5e49b31358e61525f0d001e776cec34
Author: Jeff Law 
Date:   Tue May 6 19:20:14 2025 -0600

[RISC-V] Avoid unnecessary andi with -1 argument

I was preparing to do some testing of Shreya's next patch on spec and 
stumbled
across another "andi dst,src,-1" case.  I fixed some stuff like this in the
gcc-15 cycle, but this one slipped through.

It's probably about 100M instructions on deepsjeng.  So tiny, but there's no
good reason to leave the clearly extraneous instructions in the output.

As with the other cases, it's a post-reload splitter that's not being 
careful
enough about the code it generates.

This has gone through my tester successfully.  Waiting on the pre-commit 
tester
before going forward.

gcc/
* config/riscv/riscv.md 
(*branch_shiftedarith_equals_zero):
Avoid generating unnecessary andi.  Fix formatting.

gcc/testsuite
* g++.target/riscv/redundant-andi.C: New test.

(cherry picked from commit 2c46a74d4707bd1e67561ed8514c67efc6164832)

Diff:
---
 gcc/config/riscv/riscv.md   | 20 ++-
 gcc/testsuite/g++.target/riscv/redundant-andi.C | 26 +
 2 files changed, 41 insertions(+), 5 deletions(-)

diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 15c89ff4e3de..259997fef68f 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -3173,15 +3173,25 @@
   "#"
   "&& reload_completed"
   [(set (match_dup 4) (lshiftrt:X (subreg:X (match_dup 2) 0) (match_dup 6)))
-   (set (match_dup 4) (and:X (match_dup 4) (match_dup 7)))
+   (set (match_dup 4) (match_dup 8))
(set (pc) (if_then_else (match_op_dup 1 [(match_dup 4) (const_int 0)])
   (label_ref (match_dup 0)) (pc)))]
 {
-   HOST_WIDE_INT mask = INTVAL (operands[3]);
-   int trailing = ctz_hwi (mask);
+  HOST_WIDE_INT mask = INTVAL (operands[3]);
+  int trailing = ctz_hwi (mask);
+
+  operands[6] = GEN_INT (trailing);
+  operands[7] = GEN_INT (mask >> trailing);
 
-   operands[6] = GEN_INT (trailing);
-   operands[7] = GEN_INT (mask >> trailing);
+  /* This splits after reload, so there's little chance to clean things
+ up.  Rather than emit a ton of RTL here, we can just make a new
+ operand for that RHS and use it.  For the case where the AND would
+ have been redundant, we can make it a NOP move, which does get
+ cleaned up.  */
+  if (operands[7] == CONSTM1_RTX (word_mode))
+operands[8] = operands[4];
+  else
+operands[8] = gen_rtx_AND (word_mode, operands[4], operands[7]);
 }
 [(set_attr "type" "branch")])
 
diff --git a/gcc/testsuite/g++.target/riscv/redundant-andi.C 
b/gcc/testsuite/g++.target/riscv/redundant-andi.C
new file mode 100644
index ..fe560a78ce17
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/redundant-andi.C
@@ -0,0 +1,26 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=rv64gcb -mabi=lp64" { target rv64 } } */
+/* { dg-options "-O2 -march=rv32gcb -mabi=ilp32" { target rv32 } } */
+
+
+typedef int move_s;
+struct state_t
+{
+  int npieces[13];
+};
+typedef struct state_t state_t;
+int
+search (state_t *s, int alpha, int beta, int depth, int is_null, int cutnode,
+   int extend, int wpcs, int bpcs, move_s moves[240])
+{
+  int i;
+  if moves[i]) >> 19) & 0x0F) != 13
+  && (((moves[i]) >> 19) & 0x0F) != 1 && (((moves[i]) >> 19) & 0x0F) != 2)
+if ((wpcs + bpcs) == 1)
+  extend += 4;
+  return extend;
+}
+
+/* A splitter was generating an unnecessary andi instruction.  Verify it's
+   not in our output.  */
+/* { dg-final { scan-assembler-not "andi\t\[a-z\]\[0-9\],\[a-z\]\[0-9\],-1" } 
} */

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add testcases for vec_duplicate + vadd.vv combine when GR2VR cost 15

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:9d9135afb3f72c1dfd308aa2ea8ea633a987d1df

commit 9d9135afb3f72c1dfd308aa2ea8ea633a987d1df
Author: Pan Li 
Date:   Sat May 3 11:37:09 2025 +0800

RISC-V: Add testcases for vec_duplicate + vadd.vv combine when GR2VR cost 15

Add asm dump check and for vec_duplicate + vadd.vv combine to vadd.vx.
The late-combine will not take action when GR2VR cost is 15.

The below test suites are passed for this patch.
* The rv64gcv fully regression test.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-i16.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-i32.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-i64.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-i8.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-u16.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-u32.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-u64.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-u8.c: New test.

Signed-off-by: Pan Li 
(cherry picked from commit b3a32804bebb9520b327b7cbf3e8f8b4730f9bd6)

Diff:
---
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-i16.c | 8 
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-i32.c | 8 
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-i64.c | 8 
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-i8.c  | 8 
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-u16.c | 8 
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-u32.c | 8 
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-u64.c | 8 
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-u8.c  | 8 
 8 files changed, 64 insertions(+)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-i16.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-i16.c
new file mode 100644
index ..f3a262711a4a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-i16.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=15" } */
+
+#include "vx_binary.h"
+
+DEF_VX_BINARY(int16_t, +)
+
+/* { dg-final { scan-assembler-not {vadd.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-i32.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-i32.c
new file mode 100644
index ..490854cfbd7b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-i32.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=15" } */
+
+#include "vx_binary.h"
+
+DEF_VX_BINARY(int32_t, +)
+
+/* { dg-final { scan-assembler-not {vadd.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-i64.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-i64.c
new file mode 100644
index ..a7448dfa56b0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-i64.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=15" } */
+
+#include "vx_binary.h"
+
+DEF_VX_BINARY(int64_t, +)
+
+/* { dg-final { scan-assembler-not {vadd.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-i8.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-i8.c
new file mode 100644
index ..72c7cd803fac
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-i8.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=15" } */
+
+#include "vx_binary.h"
+
+DEF_VX_BINARY(int8_t, +)
+
+/* { dg-final { scan-assembler-not {vadd.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-u16.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-u16.c
new file mode 100644
index ..552b4ed7c2fa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-u16.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=15" } */
+
+#include "vx_binary.h"
+
+DEF_VX_BINARY(uint16_t, +)
+
+/* { dg-final { scan-assembler-not {vadd.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-u32.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-u32.c
new file mode 100644
index ..e319672fc044
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-u32.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=15" } */
+
+#include "vx_binary.h"
+
+DEF_VX_BINARY(uint32_t, +)
+
+/* { dg-final { scan-assembler-not {vadd.vx} } } */
diff --git a/gcc/tes

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [PATCH] RISC-V: Minimal support for zama16b extension.

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:1953b5ece3e2fc105d6760806b08a8ef0e368585

commit 1953b5ece3e2fc105d6760806b08a8ef0e368585
Author: Dongyan Chen 
Date:   Wed May 7 11:33:06 2025 -0600

[PATCH] RISC-V: Minimal support for zama16b extension.

This patch support zama16b extension[1].
To enable GCC to recognize and process zama16b extension correctly at 
compile time.

[1] https://github.com/riscv/riscv-profiles/blob/main/src/rva23-profile.adoc

gcc/ChangeLog:

* common/config/riscv/riscv-common.cc: New extension.
* config/riscv/riscv.opt: Ditto.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/arch-48.c: New test.

(cherry picked from commit 974b079741f902fcf4323dfcecbbffdb9f56f3bf)

Diff:
---
 gcc/common/config/riscv/riscv-common.cc  | 2 ++
 gcc/config/riscv/riscv.opt   | 2 ++
 gcc/testsuite/gcc.target/riscv/arch-48.c | 5 +
 3 files changed, 9 insertions(+)

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index 0233e1a108be..ca14eb96b253 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -327,6 +327,7 @@ static const struct riscv_ext_version 
riscv_ext_version_table[] =
   {"zalrsc", ISA_SPEC_CLASS_NONE, 1, 0},
   {"zabha", ISA_SPEC_CLASS_NONE, 1, 0},
   {"zacas", ISA_SPEC_CLASS_NONE, 1, 0},
+  {"zama16b", ISA_SPEC_CLASS_NONE, 1, 0},
 
   {"zba", ISA_SPEC_CLASS_NONE, 1, 0},
   {"zbb", ISA_SPEC_CLASS_NONE, 1, 0},
@@ -1657,6 +1658,7 @@ static const riscv_ext_flag_table_t 
riscv_ext_flag_table[] =
   RISCV_EXT_FLAG_ENTRY ("zalrsc",  x_riscv_za_subext, MASK_ZALRSC),
   RISCV_EXT_FLAG_ENTRY ("zabha",   x_riscv_za_subext, MASK_ZABHA),
   RISCV_EXT_FLAG_ENTRY ("zacas",   x_riscv_za_subext, MASK_ZACAS),
+  RISCV_EXT_FLAG_ENTRY ("zama16b", x_riscv_za_subext, MASK_ZAMA16B),
 
   RISCV_EXT_FLAG_ENTRY ("zba", x_riscv_zb_subext, MASK_ZBA),
   RISCV_EXT_FLAG_ENTRY ("zbb", x_riscv_zb_subext, MASK_ZBB),
diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
index 9e471be4055c..80593ee139c1 100644
--- a/gcc/config/riscv/riscv.opt
+++ b/gcc/config/riscv/riscv.opt
@@ -274,6 +274,8 @@ Mask(ZA64RS)  Var(riscv_za_subext)
 
 Mask(ZA128RS) Var(riscv_za_subext)
 
+Mask(ZAMA16B) Var(riscv_za_subext)
+
 TargetVariable
 int riscv_zb_subext
 
diff --git a/gcc/testsuite/gcc.target/riscv/arch-48.c 
b/gcc/testsuite/gcc.target/riscv/arch-48.c
new file mode 100644
index ..58a558ec1924
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/arch-48.c
@@ -0,0 +1,5 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zama16b -mabi=lp64" } */
+int foo()
+{
+}

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Drop riscv_implied_info and riscv_combine_info in favor of riscv_ext_info_t data

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:d5d13d9b68966c608b8eb25d519143f39d4378c5

commit d5d13d9b68966c608b8eb25d519143f39d4378c5
Author: Kito Cheng 
Date:   Wed May 7 21:21:01 2025 +0800

RISC-V: Drop riscv_implied_info and riscv_combine_info in favor of 
riscv_ext_info_t data

Consolidate implied-extension logic by removing the old `riscv_implied_info`
array and using the `implied_exts` field in the unified riscv_ext_info_t
structures generated from `riscv-ext.def`.

gcc/ChangeLog:

* common/config/riscv/riscv-common.cc
(riscv_implied_info::riscv_implied_info_t): Remove unused
variant.
(struct riscv_implied_info_t): Remove unsued field.
(riscv_implied_info::match): Remove unused variant, and adjust
the logic.
(get_riscv_ext_info): New.
(riscv_implied_info): Remove.
(riscv_ext_info_t::apply_implied_ext): New.
(riscv_combine_info). Remove.
(riscv_subset_list::handle_implied_ext): Use riscv_ext_info_t
rather than riscv_implied_info.
(riscv_subset_list::check_implied_ext): Ditto.
(riscv_subset_list::handle_combine_ext): Use riscv_ext_info_t
rather than riscv_combine_info.
(riscv_minimal_hwprobe_feature_bits): Use riscv_ext_info_t
rather than riscv_implied_info.

(cherry picked from commit 8aa02f1729b0b8d39d3a93c3e0f36139f80ec0cd)

Diff:
---
 gcc/common/config/riscv/riscv-common.cc | 351 ++--
 1 file changed, 66 insertions(+), 285 deletions(-)

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index 5430da76d11c..c6ae649802c7 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -95,32 +95,17 @@ struct riscv_implied_info_t
   constexpr riscv_implied_info_t (const char *implied_ext,
  riscv_implied_predicator_t predicator
  = nullptr)
-: ext (nullptr), implied_ext (implied_ext), predicator (predicator)
+: implied_ext (implied_ext), predicator (predicator)
   {}
 
-  constexpr riscv_implied_info_t (const char *ext, const char *implied_ext,
- riscv_implied_predicator_t predicator
- = nullptr)
-: ext (ext), implied_ext (implied_ext), predicator (predicator){};
-
-  bool match (const riscv_subset_list *subset_list, const char *ext_name) const
+  bool match (const riscv_subset_list *subset_list) const
   {
-if (ext_name && strcmp (ext_name, ext) != 0)
-  return false;
-
 if (predicator && !predicator (subset_list))
   return false;
 
 return true;
   }
 
-  bool match (const riscv_subset_list *subset_list,
- const riscv_subset_t *subset) const
-  {
-return match (subset_list, subset->name.c_str());
-  }
-
-  const char *ext;
   const char *implied_ext;
   riscv_implied_predicator_t predicator;
 };
@@ -230,203 +215,43 @@ static const std::unordered_map riscv_ext_infos
 #undef DEFINE_RISCV_EXT
 };
 
-/* Implied ISA info, must end with NULL sentinel.  */
-static const riscv_implied_info_t riscv_implied_info[] =
-{
-  {"m", "zmmul"},
-
-  {"d", "f"},
-  {"f", "zicsr"},
-  {"d", "zicsr"},
-
-  {"a", "zaamo"},
-  {"a", "zalrsc"},
-
-  {"c", "zca"},
-  {"c", "zcf",
-   [] (const riscv_subset_list *subset_list) -> bool
-   {
- return subset_list->xlen () == 32 && subset_list->lookup ("f");
-   }},
-  {"c", "zcd",
-   [] (const riscv_subset_list *subset_list) -> bool
-   {
- return subset_list->lookup ("d");
-   }},
-
-  {"zabha", "zaamo"},
-  {"zacas", "zaamo"},
-  {"zawrs", "zalrsc"},
-
-  {"zcmop", "zca"},
-
-  {"b", "zba"},
-  {"b", "zbb"},
-  {"b", "zbs"},
-
-  {"zdinx", "zfinx"},
-  {"zfinx", "zicsr"},
-  {"zdinx", "zicsr"},
-
-  {"zicfiss", "zicsr"},
-  {"zicfiss", "zimop"},
-  {"zicfilp", "zicsr"},
-
-  {"zclsd", "zilsd"},
-  {"zclsd", "zca"},
-
-  {"zk", "zkn"},
-  {"zk", "zkr"},
-  {"zk", "zkt"},
-  {"zkn", "zbkb"},
-  {"zkn", "zbkc"},
-  {"zkn", "zbkx"},
-  {"zkn", "zkne"},
-  {"zkn", "zknd"},
-  {"zkn", "zknh"},
-  {"zks", "zbkb"},
-  {"zks", "zbkc"},
-  {"zks", "zbkx"},
-  {"zks", "zksed"},
-  {"zks", "zksh"},
-
-  {"v", "zvl128b"},
-  {"v", "zve64d"},
-
-  {"zve32f", "f"},
-  {"zve64f", "f"},
-  {"zve64d", "d"},
-
-  {"zve32x", "zicsr"},
-  {"zve32x", "zvl32b"},
-  {"zve32f", "zve32x"},
-  {"zve32f", "zvl32b"},
-
-  {"zve64x", "zve32x"},
-  {"zve64x", "zvl64b"},
-  {"zve64f", "zve32f"},
-  {"zve64f", "zve64x"},
-  {"zve64f", "zvl64b"},
-  {"zve64d", "zve64f"},
-  {"zve64d", "zvl64b"},
-
-  {"zvl64b", "zvl32b"},
-  {"zvl128b", "zvl64b"},
-  {"zvl256b", "zvl128b"},
-  {"zvl512b", "zvl256b"},
-  {"zvl1024b", "zvl512b"},
-  {"zvl2048b", "zvl1024b"},
-  {"zvl4096b", "zvl2048b"},
-  {"zvl8192b", "zvl4096b"},
-  {"zvl16384b", "zvl8192b"},
-  {"zvl32768b", "zvl16384b"},
-  {"zvl65536b", "zvl32768

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Introduce riscv-ext*.def to define extensions

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:f63e8d39f3335c04eddd55f5e2e6bccd071f17c4

commit f63e8d39f3335c04eddd55f5e2e6bccd071f17c4
Author: Kito Cheng 
Date:   Wed May 7 18:02:10 2025 +0800

RISC-V: Introduce riscv-ext*.def to define extensions

Adding a new ISA extension to RISC-V GCC requires modifying several places:
1. riscv_ext_version_table for the extension version.
2. riscv.opt for the target option and variable.
3. riscv_ext_flag_table to bind the extension to its target option.
4. riscv_combine_info if this extension is just a macro extension.
5. riscv_implied_info if this extension implies other extensions.
6. invoke.texi for documentation (this one is often forgotten - even by 
me...).
7. riscv-ext-bitmask.def if this extension has been allocated a bitmask in
   `__riscv_feature_bits`.

And now, we've integrated all the information into riscv-ext.def and 
generate
(almost) everything from that!

Some of the fields, like URL, are not used yet. They are planned to be 
updated
later and used for improving the documentation.

Changes since v1:
- Rebase for including new extensions
- Fix MASK_VECTOR handling

gcc/ChangeLog:

* config/riscv/riscv-ext.def: New file; define extension metadata 
table.
* config/riscv/riscv-ext-corev.def: New.
* config/riscv/riscv-ext-sifive.def: New.
* config/riscv/riscv-ext-thead.def: New.
* config/riscv/riscv-ext-ventana.def: New.

(cherry picked from commit 48180266da19b0ad08e64fa9f1ade897f9b2ef58)

Diff:
---
 gcc/config/riscv/riscv-ext-corev.def   |   87 ++
 gcc/config/riscv/riscv-ext-sifive.def  |   87 ++
 gcc/config/riscv/riscv-ext-thead.def   |  191 
 gcc/config/riscv/riscv-ext-ventana.def |   35 +
 gcc/config/riscv/riscv-ext.def | 1824 
 5 files changed, 2224 insertions(+)

diff --git a/gcc/config/riscv/riscv-ext-corev.def 
b/gcc/config/riscv/riscv-ext-corev.def
new file mode 100644
index ..eb97399403cd
--- /dev/null
+++ b/gcc/config/riscv/riscv-ext-corev.def
@@ -0,0 +1,87 @@
+/* CORE-V extension definition file for RISC-V.
+   Copyright (C) 2025 Free Software Foundation, Inc.
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 3, or (at your option)
+any later version.
+
+GCC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GCC; see the file COPYING3.  If not see
+.
+
+Please run `make riscv-regen` in build folder to make sure updated anything.
+
+Format of DEFINE_RISCV_EXT, please refer to riscv-ext.def.  */
+
+DEFINE_RISCV_EXT(
+  /* NAME */ xcvalu,
+  /* UPPERCAE_NAME */ XCVALU,
+  /* FULL_NAME */ "Core-V miscellaneous ALU extension",
+  /* DESC */ "",
+  /* URL */ ,
+  /* DEP_EXTS */ ({}),
+  /* SUPPORTED_VERSIONS */ ({{1, 0}}),
+  /* FLAG_GROUP */ xcv,
+  /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED,
+  /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED,
+  /* EXTRA_EXTENSION_FLAGS */ 0)
+
+DEFINE_RISCV_EXT(
+  /* NAME */ xcvbi,
+  /* UPPERCAE_NAME */ XCVBI,
+  /* FULL_NAME */ "xcvbi extension",
+  /* DESC */ "",
+  /* URL */ ,
+  /* DEP_EXTS */ ({}),
+  /* SUPPORTED_VERSIONS */ ({{1, 0}}),
+  /* FLAG_GROUP */ xcv,
+  /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED,
+  /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED,
+  /* EXTRA_EXTENSION_FLAGS */ 0)
+
+DEFINE_RISCV_EXT(
+  /* NAME */ xcvelw,
+  /* UPPERCAE_NAME */ XCVELW,
+  /* FULL_NAME */ "Core-V event load word extension",
+  /* DESC */ "",
+  /* URL */ ,
+  /* DEP_EXTS */ ({}),
+  /* SUPPORTED_VERSIONS */ ({{1, 0}}),
+  /* FLAG_GROUP */ xcv,
+  /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED,
+  /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED,
+  /* EXTRA_EXTENSION_FLAGS */ 0)
+
+DEFINE_RISCV_EXT(
+  /* NAME */ xcvmac,
+  /* UPPERCAE_NAME */ XCVMAC,
+  /* FULL_NAME */ "Core-V multiply-accumulate extension",
+  /* DESC */ "",
+  /* URL */ ,
+  /* DEP_EXTS */ ({}),
+  /* SUPPORTED_VERSIONS */ ({{1, 0}}),
+  /* FLAG_GROUP */ xcv,
+  /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED,
+  /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED,
+  /* EXTRA_EXTENSION_FLAGS */ 0)
+
+DEFINE_RISCV_EXT(
+  /* NAME */ xcvsimd,
+  /* UPPERCAE_NAME */ XCVSIMD,
+  /* FULL_NAME */ "xcvsimd extension",
+  /* DESC */ "",
+  /* URL */ ,
+  /* DEP_EXTS */ ({}),
+  /* SUPPORTED_VERSIONS */ ({{1, 0}}),
+  /* FLAG_GROUP */ xcv,
+  /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED,
+  /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED,
+  /* EXTRA_EXTENSION_FLAGS */ 0)
diff --git a/gcc/

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Adjust riscv_can_inline_p

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:4d7dafbf4efe456e23f20e0cb325b6c04b8a6487

commit 4d7dafbf4efe456e23f20e0cb325b6c04b8a6487
Author: Kito Cheng 
Date:   Wed May 7 18:30:34 2025 +0800

RISC-V: Adjust riscv_can_inline_p

We don't hold any extenison flags in `target_flags`, so no need to
gather the extenison flags in `target_flags`.

gcc/ChangeLog:

* common/config/riscv/riscv-common.cc (riscv_can_inline_p): Drop
extension flags check from `target_flags`.
* config/riscv/riscv-subset.h (riscv_x_target_flags_isa_mask):
Remove.
* config/riscv/riscv.cc (riscv_x_target_flags_isa_mask): Remove.

(cherry picked from commit 590701c97748cd7f99f15fbd0d75076dd75bea3d)

Diff:
---
 gcc/common/config/riscv/riscv-common.cc | 17 -
 gcc/config/riscv/riscv-subset.h |  1 -
 gcc/config/riscv/riscv.cc   |  8 +++-
 3 files changed, 3 insertions(+), 23 deletions(-)

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index d84aa9d78dd3..ff34a315caf6 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -2036,23 +2036,6 @@ riscv_ext_is_subset (struct cl_target_option *opts,
   return true;
 }
 
-/* Return the mask of ISA extension in x_target_flags of gcc_options.  */
-
-int
-riscv_x_target_flags_isa_mask (void)
-{
-  int mask = 0;
-  const riscv_ext_flag_table_t *arch_ext_flag_tab;
-  for (arch_ext_flag_tab = &riscv_ext_flag_table[0];
-   arch_ext_flag_tab->ext;
-   ++arch_ext_flag_tab)
-{
-  if (arch_ext_flag_tab->var_ref == &gcc_options::x_target_flags)
-   mask |= arch_ext_flag_tab->mask;
-}
-  return mask;
-}
-
 /* Get the minimal feature bits in Linux hwprobe of the given ISA string.
 
Used for generating Function Multi-Versioning (FMV) dispatcher for RISC-V.
diff --git a/gcc/config/riscv/riscv-subset.h b/gcc/config/riscv/riscv-subset.h
index 7b3fdaeb3e40..c5d9fab4de9f 100644
--- a/gcc/config/riscv/riscv-subset.h
+++ b/gcc/config/riscv/riscv-subset.h
@@ -129,6 +129,5 @@ extern bool riscv_minimal_hwprobe_feature_bits (const char 
*,
location_t);
 extern bool
 riscv_ext_is_subset (struct cl_target_option *, struct cl_target_option *);
-extern int riscv_x_target_flags_isa_mask (void);
 
 #endif /* ! GCC_RISCV_SUBSET_H */
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 8b77a3539bc5..d28aee4b4398 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -7918,11 +7918,9 @@ riscv_can_inline_p (tree caller, tree callee)
   struct cl_target_option *callee_opts = TREE_TARGET_OPTION (callee_tree);
   struct cl_target_option *caller_opts = TREE_TARGET_OPTION (caller_tree);
 
-  int isa_flag_mask = riscv_x_target_flags_isa_mask ();
-
-  /* Callee and caller should have the same target options except for ISA.  */
-  int callee_target_flags = callee_opts->x_target_flags & ~isa_flag_mask;
-  int caller_target_flags = caller_opts->x_target_flags & ~isa_flag_mask;
+  /* Callee and caller should have the same target options.  */
+  int callee_target_flags = callee_opts->x_target_flags;
+  int caller_target_flags = caller_opts->x_target_flags;
 
   if (callee_target_flags != caller_target_flags)
 return false;

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Generate extension table in documentation from riscv-ext.def

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:ac1cfc515717bb6f3dfb5d1c9da88e3b132be6c2

commit ac1cfc515717bb6f3dfb5d1c9da88e3b132be6c2
Author: Kito Cheng 
Date:   Wed May 7 21:10:53 2025 +0800

RISC-V: Generate extension table in documentation from riscv-ext.def

Automatically build the ISA extension reference table in invoke.texi from
the unified riscv-ext.def metadata, ensuring documentation stays in sync
with extension definitions and reducing manual maintenance.

gcc/ChangeLog:

* doc/invoke.texi: Replace hand‑written extension table with
`@include riscv-ext.texi` to pull in auto‑generated entries.
* doc/riscv-ext.texi: New generated definition file
containing formatted documentation entries for each extension.
* Makefile.in: Add riscv-ext.texi to the list of files to be
processed by the Texinfo generator.
* config/riscv/gen-riscv-ext-texi.cc: New.
* config/riscv/t-riscv: Add rule for generating riscv-ext.texi.

(cherry picked from commit 124cbbbed5b8f7454f93f9a87e57fd4f3f2f78d2)

Diff:
---
 gcc/Makefile.in|   2 +-
 gcc/config/riscv/gen-riscv-ext-texi.cc |  88 +
 gcc/config/riscv/t-riscv   |  34 +-
 gcc/doc/invoke.texi| 495 +
 gcc/doc/riscv-ext.texi | 637 +
 5 files changed, 759 insertions(+), 497 deletions(-)

diff --git a/gcc/Makefile.in b/gcc/Makefile.in
index 55b4cd7dbed3..0fa5d0c925af 100644
--- a/gcc/Makefile.in
+++ b/gcc/Makefile.in
@@ -3702,7 +3702,7 @@ TEXI_GCC_FILES = gcc.texi gcc-common.texi gcc-vers.texi 
frontends.texi\
 contribute.texi compat.texi funding.texi gnu.texi gpl_v3.texi  \
 fdl.texi contrib.texi cppenv.texi cppopts.texi avr-mmcu.texi   \
 implement-c.texi implement-cxx.texi gcov-tool.texi gcov-dump.texi \
-lto-dump.texi
+lto-dump.texi riscv-ext.texi
 
 # we explicitly use $(srcdir)/doc/tm.texi here to avoid confusion with
 # the generated tm.texi; the latter might have a more recent timestamp,
diff --git a/gcc/config/riscv/gen-riscv-ext-texi.cc 
b/gcc/config/riscv/gen-riscv-ext-texi.cc
new file mode 100644
index ..e15fdbf36f6e
--- /dev/null
+++ b/gcc/config/riscv/gen-riscv-ext-texi.cc
@@ -0,0 +1,88 @@
+#include 
+#include 
+#include 
+#include 
+#include "riscv-opts.h"
+
+struct version_t
+{
+  int major;
+  int minor;
+  version_t (int major, int minor,
+enum riscv_isa_spec_class spec = ISA_SPEC_CLASS_NONE)
+: major (major), minor (minor)
+  {}
+  bool operator<(const version_t &other) const
+  {
+if (major != other.major)
+  return major < other.major;
+return minor < other.minor;
+  }
+
+  bool operator== (const version_t &other) const
+  {
+return major == other.major && minor == other.minor;
+  }
+};
+
+static void
+print_ext_doc_entry (const std::string &ext_name, const std::string &full_name,
+const std::string &desc,
+const std::vector &supported_versions)
+{
+  // Implementation of the function to print the documentation entry
+  // for the extension.
+  std::set unique_versions;
+  for (const auto &version : supported_versions)
+unique_versions.insert (version);
+  printf ("@item %s\n", ext_name.c_str ());
+  printf ("@tab");
+  for (const auto &version : unique_versions)
+{
+  printf (" %d.%d", version.major, version.minor);
+}
+  printf ("\n");
+  printf ("@tab %s", full_name.c_str ());
+  if (desc.size ())
+printf (", %s", desc.c_str ());
+  printf ("\n\n");
+}
+
+int
+main ()
+{
+  puts ("@c Copyright (C) 2025 Free Software Foundation, Inc.");
+  puts ("@c This is part of the GCC manual.");
+  puts ("@c For copying conditions, see the file gcc/doc/include/fdl.texi.");
+  puts ("");
+  puts ("@c This file is generated automatically using");
+  puts ("@c  gcc/config/riscv/gen-riscv-ext-texi.cc from:");
+  puts ("@c   gcc/config/riscv/riscv-ext.def");
+  puts ("@c   gcc/config/riscv/riscv-opts.h");
+  puts ("");
+  puts ("@c Please *DO NOT* edit manually.");
+  puts ("");
+  puts ("@multitable @columnfractions .10 .10 .80");
+  puts ("@headitem Extension Name @tab Supported Version @tab Description");
+  puts ("");
+
+  /* g extension is a very speical extension that no clear version...  */
+  puts ("@item g");
+  puts ("@tab -");
+  puts (
+"@tab General-purpose computing base extension, @samp{g} will expand to");
+  puts ("@samp{i}, @samp{m}, @samp{a}, @samp{f}, @samp{d}, @samp{zicsr} and");
+  puts ("@samp{zifencei}.");
+  puts ("");
+
+#define DEFINE_RISCV_EXT(NAME, UPPERCAE_NAME, FULL_NAME, DESC, URL, DEP_EXTS,  
\
+SUPPORTED_VERSIONS, FLAG_GROUP, BITMASK_GROUP_ID, \
+BITMASK_BIT_POSITION, EXTRA_EXTENSION_FLAGS)  \
+  print_ext_doc_entry (#NAME, FULL_NAME, DESC, 
\
+

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add testcases for scalar unsigned integer SAT_ADD form 7

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:24f53c2781a919deaf098a7514428e679d4866c0

commit 24f53c2781a919deaf098a7514428e679d4866c0
Author: Pan Li 
Date:   Mon Apr 28 20:35:09 2025 +0800

RISC-V: Add testcases for scalar unsigned integer SAT_ADD form 7

This patch will add testcase for unsigned integer SAT_ADD form 7:

  #define DEF_SAT_U_ADD_FMT_7(WT, T) \
  T __attribute__((noinline))\
  sat_u_add_##WT##_##T##_fmt_7(T x, T y) \
  {  \
T max = -1;  \
WT val = (WT)x + (WT)y;  \
return val > max ? max : (T)val; \
  }

  DEF_SAT_U_ADD_FMT_7(uint64_t, uint32_t)

The below test are passed for this patch.
* The rv64gcv fully regression test.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/sat/sat_arith.h: Add test helper macros.
* gcc.target/riscv/sat/sat_u_add-7-u16-from-u32.c: New test.
* gcc.target/riscv/sat/sat_u_add-7-u16-from-u64.c: New test.
* gcc.target/riscv/sat/sat_u_add-7-u32-from-u64.c: New test.
* gcc.target/riscv/sat/sat_u_add-7-u8-from-u16.c: New test.
* gcc.target/riscv/sat/sat_u_add-7-u8-from-u32.c: New test.
* gcc.target/riscv/sat/sat_u_add-7-u8-from-u64.c: New test.
* gcc.target/riscv/sat/sat_u_add-run-7-u16-from-u32.c: New test.
* gcc.target/riscv/sat/sat_u_add-run-7-u16-from-u64.c: New test.
* gcc.target/riscv/sat/sat_u_add-run-7-u32-from-u64.c: New test.
* gcc.target/riscv/sat/sat_u_add-run-7-u8-from-u16.c: New test.
* gcc.target/riscv/sat/sat_u_add-run-7-u8-from-u32.c: New test.
* gcc.target/riscv/sat/sat_u_add-run-7-u8-from-u64.c: New test.

Signed-off-by: Pan Li 
(cherry picked from commit f6535d433e250421f6c1f2f691c04e613d63a694)

Diff:
---
 gcc/testsuite/gcc.target/riscv/sat/sat_arith.h | 22 ++
 .../riscv/sat/sat_u_add-7-u16-from-u32.c   | 21 +
 .../riscv/sat/sat_u_add-7-u16-from-u64.c   | 21 +
 .../riscv/sat/sat_u_add-7-u32-from-u64.c   | 22 ++
 .../gcc.target/riscv/sat/sat_u_add-7-u8-from-u16.c | 19 
 .../gcc.target/riscv/sat/sat_u_add-7-u8-from-u32.c | 19 
 .../gcc.target/riscv/sat/sat_u_add-7-u8-from-u64.c | 19 
 .../riscv/sat/sat_u_add-run-7-u16-from-u32.c   | 26 ++
 .../riscv/sat/sat_u_add-run-7-u16-from-u64.c   | 26 ++
 .../riscv/sat/sat_u_add-run-7-u32-from-u64.c   | 26 ++
 .../riscv/sat/sat_u_add-run-7-u8-from-u16.c| 26 ++
 .../riscv/sat/sat_u_add-run-7-u8-from-u32.c| 26 ++
 .../riscv/sat/sat_u_add-run-7-u8-from-u64.c| 26 ++
 13 files changed, 299 insertions(+)

diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_arith.h 
b/gcc/testsuite/gcc.target/riscv/sat/sat_arith.h
index c8a135a5f0f7..2225d30d77e2 100644
--- a/gcc/testsuite/gcc.target/riscv/sat/sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/sat/sat_arith.h
@@ -53,12 +53,34 @@ sat_u_add_##T##_fmt_6 (T x, T y)\
   return (T)(x + y) < x ? -1 : (x + y); \
 }
 
+#define DEF_SAT_U_ADD_FMT_7(WT, T) \
+T __attribute__((noinline))\
+sat_u_add_##WT##_##T##_fmt_7(T x, T y) \
+{  \
+  T max = -1;  \
+  WT val = (WT)x + (WT)y;  \
+  return val > max ? max : (T)val; \
+}
+#define DEF_SAT_U_ADD_FMT_7_WRAP(WT, T) DEF_SAT_U_ADD_FMT_7(WT, T)
+
 #define RUN_SAT_U_ADD_FMT_1(T, x, y) sat_u_add_##T##_fmt_1(x, y)
 #define RUN_SAT_U_ADD_FMT_2(T, x, y) sat_u_add_##T##_fmt_2(x, y)
 #define RUN_SAT_U_ADD_FMT_3(T, x, y) sat_u_add_##T##_fmt_3(x, y)
 #define RUN_SAT_U_ADD_FMT_4(T, x, y) sat_u_add_##T##_fmt_4(x, y)
 #define RUN_SAT_U_ADD_FMT_5(T, x, y) sat_u_add_##T##_fmt_5(x, y)
 #define RUN_SAT_U_ADD_FMT_6(T, x, y) sat_u_add_##T##_fmt_6(x, y)
+#define RUN_SAT_U_ADD_FMT_7_FROM_U16(T, x, y) \
+  sat_u_add_uint16_t_##T##_fmt_7(x, y)
+#define RUN_SAT_U_ADD_FMT_7_FROM_U16_WRAP(T, x, y) \
+  RUN_SAT_U_ADD_FMT_7_FROM_U16(T, x, y)
+#define RUN_SAT_U_ADD_FMT_7_FROM_U32(T, x, y) \
+  sat_u_add_uint32_t_##T##_fmt_7(x, y)
+#define RUN_SAT_U_ADD_FMT_7_FROM_U32_WRAP(T, x, y) \
+  RUN_SAT_U_ADD_FMT_7_FROM_U32(T, x, y)
+#define RUN_SAT_U_ADD_FMT_7_FROM_U64(T, x, y) \
+  sat_u_add_uint64_t_##T##_fmt_7(x, y)
+#define RUN_SAT_U_ADD_FMT_7_FROM_U64_WRAP(T, x, y) \
+  RUN_SAT_U_ADD_FMT_7_FROM_U64(T, x, y)
 
 #define DEF_SAT_U_ADD_IMM_FMT_1(T, IMM)  \
 T __attribute__((noinline))  \
diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-7-u16-from-u32.c 
b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-7-u16-from-u32.c
new file mode 100644
index ..527f8de63517
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-7

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Drop riscv_ext_version_table in favor of riscv_ext_info_t data

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:1931c493c4ba1336f83d14c35ad1bedec6d3943f

commit 1931c493c4ba1336f83d14c35ad1bedec6d3943f
Author: Kito Cheng 
Date:   Thu May 8 16:23:29 2025 +0800

RISC-V: Drop riscv_ext_version_table in favor of riscv_ext_info_t data

This commit drops the riscv_ext_version_table and instead uses the
riscv_ext_info_t data structure to provide the version information
for RISC-V extensions.

gcc/ChangeLog:

* common/config/riscv/riscv-common.cc (riscv_ext_version_table):
Remove.
(standard_extensions_p): Use riscv_ext_info_t.
(get_default_version): Use riscv_ext_info_t.
(riscv_arch_help): Ditto.

(cherry picked from commit 897bb6d4347469e378aad9e00fc4b5c6fcb1e9ce)

Diff:
---
 gcc/common/config/riscv/riscv-common.cc | 272 +++-
 1 file changed, 22 insertions(+), 250 deletions(-)

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index c6ae649802c7..d50aff4ae344 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -269,225 +269,6 @@ struct riscv_profiles
   const char *profile_string;
 };
 
-/* All standard extensions defined in all supported ISA spec.  */
-static const struct riscv_ext_version riscv_ext_version_table[] =
-{
-  /* name, ISA spec, major version, minor_version.  */
-  {"e", ISA_SPEC_CLASS_20191213, 2, 0},
-  {"e", ISA_SPEC_CLASS_20190608, 2, 0},
-  {"e", ISA_SPEC_CLASS_2P2,  2, 0},
-
-  {"i", ISA_SPEC_CLASS_20191213, 2, 1},
-  {"i", ISA_SPEC_CLASS_20190608, 2, 1},
-  {"i", ISA_SPEC_CLASS_2P2,  2, 0},
-
-  {"m", ISA_SPEC_CLASS_20191213, 2, 0},
-  {"m", ISA_SPEC_CLASS_20190608, 2, 0},
-  {"m", ISA_SPEC_CLASS_2P2,  2, 0},
-
-  {"a", ISA_SPEC_CLASS_20191213, 2, 1},
-  {"a", ISA_SPEC_CLASS_20190608, 2, 0},
-  {"a", ISA_SPEC_CLASS_2P2,  2, 0},
-
-  {"f", ISA_SPEC_CLASS_20191213, 2, 2},
-  {"f", ISA_SPEC_CLASS_20190608, 2, 2},
-  {"f", ISA_SPEC_CLASS_2P2,  2, 0},
-
-  {"d", ISA_SPEC_CLASS_20191213, 2, 2},
-  {"d", ISA_SPEC_CLASS_20190608, 2, 2},
-  {"d", ISA_SPEC_CLASS_2P2,  2, 0},
-
-  {"c", ISA_SPEC_CLASS_20191213, 2, 0},
-  {"c", ISA_SPEC_CLASS_20190608, 2, 0},
-  {"c", ISA_SPEC_CLASS_2P2,  2, 0},
-
-  {"b",   ISA_SPEC_CLASS_NONE, 1, 0},
-
-  {"h",   ISA_SPEC_CLASS_NONE, 1, 0},
-
-  {"v",   ISA_SPEC_CLASS_NONE, 1, 0},
-
-  {"zicsr", ISA_SPEC_CLASS_20191213, 2, 0},
-  {"zicsr", ISA_SPEC_CLASS_20190608, 2, 0},
-
-  {"zifencei", ISA_SPEC_CLASS_20191213, 2, 0},
-  {"zifencei", ISA_SPEC_CLASS_20190608, 2, 0},
-
-  {"zicond", ISA_SPEC_CLASS_NONE, 1, 0},
-
-  {"za64rs",  ISA_SPEC_CLASS_NONE, 1, 0},
-  {"za128rs", ISA_SPEC_CLASS_NONE, 1, 0},
-  {"zawrs", ISA_SPEC_CLASS_NONE, 1, 0},
-  {"zaamo", ISA_SPEC_CLASS_NONE, 1, 0},
-  {"zalrsc", ISA_SPEC_CLASS_NONE, 1, 0},
-  {"zabha", ISA_SPEC_CLASS_NONE, 1, 0},
-  {"zacas", ISA_SPEC_CLASS_NONE, 1, 0},
-  {"zama16b", ISA_SPEC_CLASS_NONE, 1, 0},
-
-  {"zba", ISA_SPEC_CLASS_NONE, 1, 0},
-  {"zbb", ISA_SPEC_CLASS_NONE, 1, 0},
-  {"zbc", ISA_SPEC_CLASS_NONE, 1, 0},
-  {"zbs", ISA_SPEC_CLASS_NONE, 1, 0},
-
-  {"zfinx", ISA_SPEC_CLASS_NONE, 1, 0},
-  {"zdinx", ISA_SPEC_CLASS_NONE, 1, 0},
-  {"zhinx", ISA_SPEC_CLASS_NONE, 1, 0},
-  {"zhinxmin", ISA_SPEC_CLASS_NONE, 1, 0},
-
-  {"zbkb",  ISA_SPEC_CLASS_NONE, 1, 0},
-  {"zbkc",  ISA_SPEC_CLASS_NONE, 1, 0},
-  {"zbkx",  ISA_SPEC_CLASS_NONE, 1, 0},
-  {"zkne",  ISA_SPEC_CLASS_NONE, 1, 0},
-  {"zknd",  ISA_SPEC_CLASS_NONE, 1, 0},
-  {"zknh",  ISA_SPEC_CLASS_NONE, 1, 0},
-  {"zkr",   ISA_SPEC_CLASS_NONE, 1, 0},
-  {"zksed", ISA_SPEC_CLASS_NONE, 1, 0},
-  {"zksh",  ISA_SPEC_CLASS_NONE, 1, 0},
-  {"zkt",   ISA_SPEC_CLASS_NONE, 1, 0},
-
-  {"zihintntl", ISA_SPEC_CLASS_NONE, 1, 0},
-  {"zihintpause", ISA_SPEC_CLASS_NONE, 2, 0},
-
-  {"zicboz",ISA_SPEC_CLASS_NONE, 1, 0},
-  {"zicbom",ISA_SPEC_CLASS_NONE, 1, 0},
-  {"zicbop",ISA_SPEC_CLASS_NONE, 1, 0},
-  {"zic64b",   ISA_SPEC_CLASS_NONE, 1, 0},
-  {"ziccamoa", ISA_SPEC_CLASS_NONE, 1, 0},
-  {"ziccif",   ISA_SPEC_CLASS_NONE, 1, 0},
-  {"zicclsm",  ISA_SPEC_CLASS_NONE, 1, 0},
-  {"ziccrse",  ISA_SPEC_CLASS_NONE, 1, 0},
-
-  {"zicfiss", ISA_SPEC_CLASS_NONE, 1, 0},
-  {"zicfilp", ISA_SPEC_CLASS_NONE, 1, 0},
-
-  {"zimop", ISA_SPEC_CLASS_NONE, 1, 0},
-  {"zcmop", ISA_SPEC_CLASS_NONE, 1, 0},
-
-  {"zicntr", ISA_SPEC_CLASS_NONE, 2, 0},
-  {"zihpm",  ISA_SPEC_CLASS_NONE, 2, 0},
-
-  {"zilsd",  ISA_SPEC_CLASS_NONE, 1, 0},
-  {"zclsd",  ISA_SPEC_CLASS_NONE, 1, 0},
-
-  {"zk",ISA_SPEC_CLASS_NONE, 1, 0},
-  {"zkn",   ISA_SPEC_CLASS_NONE, 1, 0},
-  {"zks",   ISA_SPEC_CLASS_NONE, 1, 0},
-
-  {"ztso",  ISA_SPEC_CLASS_NONE, 1, 0},
-
-  {"zve32x", ISA_SPEC_CLASS_NONE, 1, 0},
-  {"zve32f", ISA_SPEC_CLASS_NONE, 1, 0},
-  {"zve64x", ISA_SPEC_CLASS_NONE, 1, 0},
-  {"zve64f", ISA_SPEC_CLASS_NONE, 1, 0},
-  {"zve64d", ISA_SPEC_CLASS_NONE, 1, 0},
-
-  {"zvbb", ISA_SPEC_CLASS_NONE, 1, 0},
-  {"zvbc", ISA_SPEC_CLASS_NONE, 1, 0},
-  {"zvkb", 

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Introduce riscv_ext_info_t to hold extension metadata

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:1c2a37393d26b08c0d89d7b89bc31253197417d4

commit 1c2a37393d26b08c0d89d7b89bc31253197417d4
Author: Kito Cheng 
Date:   Wed May 7 20:59:15 2025 +0800

RISC-V: Introduce riscv_ext_info_t to hold extension metadata

Define a new riscv_ext_info_t struct to aggregate all ISA extension fields
(name, version, flags, implied extensions, bitmask and extra flags) 
generated
from riscv-ext.def.

Also adjust riscv_ext_flag_table_t and riscv_implied_info_t to make it
able to not hold extension name, this part will refactor in later
patchs.

gcc/ChangeLog:

* common/config/riscv/riscv-common.cc (riscv_ext_info_t): New
struct.
(opt_var_ref_t): Adjust order.
(cl_opt_var_ref_t): Ditto.
(riscv_ext_flag_table_t): Adjust order, and add a new construct
that not hold the extension name.
(riscv_version_t): New struct.
(riscv_implied_info_t): Adjust order, and add a new construct that 
not
hold the extension name.
(apply_extra_extension_flags): New function.
(riscv_ext_infos): New.
(riscv_implied_info): Adjust.
* config/riscv/riscv-opts.h (EXT_FLAG_MACRO): New macro.
(BITMASK_NOT_YET_ALLOCATED): New macro.

(cherry picked from commit 312c407aac772f3535ff952ebc5ebff1057a593c)

Diff:
---
 gcc/common/config/riscv/riscv-common.cc | 191 +---
 gcc/config/riscv/riscv-opts.h   |   8 ++
 2 files changed, 185 insertions(+), 14 deletions(-)

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index ff34a315caf6..5430da76d11c 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -19,6 +19,7 @@ along with GCC; see the file COPYING3.  If not see
 
 #include 
 #include 
+#include 
 #include 
 
 #define INCLUDE_STRING
@@ -41,11 +42,62 @@ along with GCC; see the file COPYING3.  If not see
 #define TARGET_DEFAULT_TARGET_FLAGS (MASK_BIG_ENDIAN)
 #endif
 
+/* Type for pointer to member of gcc_options and cl_target_option.  */
+typedef int (gcc_options::*opt_var_ref_t);
+typedef int (cl_target_option::*cl_opt_var_ref_t);
+
+/* Types for recording extension to internal flag.  */
+struct riscv_ext_flag_table_t
+{
+  riscv_ext_flag_table_t (const char *ext, opt_var_ref_t var_ref,
+ cl_opt_var_ref_t cl_var_ref, int mask)
+   : ext (ext), var_ref (var_ref), cl_var_ref (cl_var_ref), mask (mask)
+  {}
+  riscv_ext_flag_table_t (opt_var_ref_t var_ref,
+ cl_opt_var_ref_t cl_var_ref, int mask)
+   : ext (nullptr), var_ref (var_ref), cl_var_ref (cl_var_ref), mask (mask)
+  {}
+
+  const char *ext;
+  opt_var_ref_t var_ref;
+  cl_opt_var_ref_t cl_var_ref;
+  int mask;
+
+  void clean (gcc_options *opts) const { opts->*var_ref &= ~mask; }
+
+  void set (gcc_options *opts) const { opts->*var_ref |= mask; }
+
+  bool check (cl_target_option *opts) const
+  {
+return (opts->*cl_var_ref & mask);
+  }
+};
+
+/* Type for hold RISC-V extension version.  */
+struct riscv_version_t
+{
+  riscv_version_t (int major_version, int minor_version,
+  enum riscv_isa_spec_class isa_spec_class
+  = ISA_SPEC_CLASS_NONE)
+: major_version (major_version), minor_version (minor_version),
+  isa_spec_class (isa_spec_class)
+  {}
+  int major_version;
+  int minor_version;
+  enum riscv_isa_spec_class isa_spec_class;
+};
+
 typedef bool (*riscv_implied_predicator_t) (const riscv_subset_list *);
 
 /* Type for implied ISA info.  */
 struct riscv_implied_info_t
 {
+  constexpr riscv_implied_info_t (const char *implied_ext,
+ riscv_implied_predicator_t predicator
+ = nullptr)
+: ext (nullptr), implied_ext (implied_ext), predicator (predicator)
+  {}
+
   constexpr riscv_implied_info_t (const char *ext, const char *implied_ext,
  riscv_implied_predicator_t predicator
  = nullptr)
@@ -53,7 +105,7 @@ struct riscv_implied_info_t
 
   bool match (const riscv_subset_list *subset_list, const char *ext_name) const
   {
-if (strcmp (ext_name, ext) != 0)
+if (ext_name && strcmp (ext_name, ext) != 0)
   return false;
 
 if (predicator && !predicator (subset_list))
@@ -73,6 +125,111 @@ struct riscv_implied_info_t
   riscv_implied_predicator_t predicator;
 };
 
+static void
+apply_extra_extension_flags (const char *ext,
+std::vector &flag_table);
+
+/* Class for hold the extension info.  */
+class riscv_ext_info_t
+{
+public:
+  riscv_ext_info_t (const char *ext,
+   const std::vector &implied_exts,
+   const std::vector &supported_versions,
+   const std::vector &flag_table,
+   int bitmask_group_id, in

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add augmented hypervisor series extensions.

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:fa7576e1c7e99079abf40c3a3cd73c502bbed93c

commit fa7576e1c7e99079abf40c3a3cd73c502bbed93c
Author: Jiawei 
Date:   Tue May 13 15:23:39 2025 +0800

RISC-V: Add augmented hypervisor series extensions.

The augmented hypervisor series extensions 'sha'[1] is a new profile-defined
extension series that captures the full set of features that are mandated to
be supported along with the 'H' extension.

[1] 
https://github.com/riscv/riscv-profiles/blob/main/src/rva23-profile.adoc#rva23s64-profile

Version log: Update implements， fix testcase format.

gcc/ChangeLog:

* config/riscv/riscv-ext.def: New extension defs.
* config/riscv/riscv-ext.opt: Ditto.
* doc/riscv-ext.texi: Ditto.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/arch-55.c: New test.

(cherry picked from commit 0cbace3b142c087335e245245e97f6605a6cd1f7)

Diff:
---
 gcc/config/riscv/riscv-ext.def   | 91 
 gcc/config/riscv/riscv-ext.opt   | 17 ++
 gcc/doc/riscv-ext.texi   | 28 ++
 gcc/testsuite/gcc.target/riscv/arch-55.c |  9 
 4 files changed, 145 insertions(+)

diff --git a/gcc/config/riscv/riscv-ext.def b/gcc/config/riscv/riscv-ext.def
index 34742d912f83..97b576617add 100644
--- a/gcc/config/riscv/riscv-ext.def
+++ b/gcc/config/riscv/riscv-ext.def
@@ -1571,6 +1571,97 @@ DEFINE_RISCV_EXT(
   /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED,
   /* EXTRA_EXTENSION_FLAGS */ 0)
 
+DEFINE_RISCV_EXT(
+  /* NAME */ sha,
+  /* UPPERCAE_NAME */ SHA,
+  /* FULL_NAME */ "The augmented hypervisor extension",
+  /* DESC */ "",
+  /* URL */ ,
+  /* DEP_EXTS */ ({"h", "shcounterenw", "shgatpa", "shtvala", "shvstvala", 
"shvstvecd", "shvsatpa", "ssstateen"}),
+  /* SUPPORTED_VERSIONS */ ({{1, 0}}),
+  /* FLAG_GROUP */ sh,
+  /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED,
+  /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED,
+  /* EXTRA_EXTENSION_FLAGS */ 0)
+
+DEFINE_RISCV_EXT(
+  /* NAME */ shcounterenw,
+  /* UPPERCAE_NAME */ SHCOUNTERENW,
+  /* FULL_NAME */ "Support writeable enables for any supported counter",
+  /* DESC */ "",
+  /* URL */ ,
+  /* DEP_EXTS */ ({"h", "zihpm"}),
+  /* SUPPORTED_VERSIONS */ ({{1, 0}}),
+  /* FLAG_GROUP */ sh,
+  /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED,
+  /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED,
+  /* EXTRA_EXTENSION_FLAGS */ 0)
+
+DEFINE_RISCV_EXT(
+  /* NAME */ shgatpa,
+  /* UPPERCAE_NAME */ SHGATPA,
+  /* FULL_NAME */ "SvNNx4 mode supported for all modes supported by satp",
+  /* DESC */ "",
+  /* URL */ ,
+  /* DEP_EXTS */ ({"h", "ssstateen"}),
+  /* SUPPORTED_VERSIONS */ ({{1, 0}}),
+  /* FLAG_GROUP */ sh,
+  /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED,
+  /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED,
+  /* EXTRA_EXTENSION_FLAGS */ 0)
+
+DEFINE_RISCV_EXT(
+  /* NAME */ shtvala,
+  /* UPPERCAE_NAME */ SHTVALA,
+  /* FULL_NAME */ "The htval register provides all needed values",
+  /* DESC */ "",
+  /* URL */ ,
+  /* DEP_EXTS */ ({"h"}),
+  /* SUPPORTED_VERSIONS */ ({{1, 0}}),
+  /* FLAG_GROUP */ sh,
+  /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED,
+  /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED,
+  /* EXTRA_EXTENSION_FLAGS */ 0)
+
+DEFINE_RISCV_EXT(
+  /* NAME */ shvstvala,
+  /* UPPERCAE_NAME */ SHVSTVALA,
+  /* FULL_NAME */ "The vstval register provides all needed values",
+  /* DESC */ "",
+  /* URL */ ,
+  /* DEP_EXTS */ ({"h"}),
+  /* SUPPORTED_VERSIONS */ ({{1, 0}}),
+  /* FLAG_GROUP */ sh,
+  /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED,
+  /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED,
+  /* EXTRA_EXTENSION_FLAGS */ 0)
+
+DEFINE_RISCV_EXT(
+  /* NAME */ shvstvecd,
+  /* UPPERCAE_NAME */ SHVSTVECD,
+  /* FULL_NAME */ "The vstvec register supports Direct mode",
+  /* DESC */ "",
+  /* URL */ ,
+  /* DEP_EXTS */ ({"h"}),
+  /* SUPPORTED_VERSIONS */ ({{1, 0}}),
+  /* FLAG_GROUP */ sh,
+  /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED,
+  /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED,
+  /* EXTRA_EXTENSION_FLAGS */ 0)
+
+DEFINE_RISCV_EXT(
+  /* NAME */ shvsatpa,
+  /* UPPERCAE_NAME */ SHVSATPA,
+  /* FULL_NAME */ "The vsatp register supports all modes supported by satp",
+  /* DESC */ "",
+  /* URL */ ,
+  /* DEP_EXTS */ ({"h"}),
+  /* SUPPORTED_VERSIONS */ ({{1, 0}}),
+  /* FLAG_GROUP */ sh,
+  /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED,
+  /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED,
+  /* EXTRA_EXTENSION_FLAGS */ 0)
+
 DEFINE_RISCV_EXT(
   /* NAME */ smaia,
   /* UPPERCAE_NAME */ SMAIA,
diff --git a/gcc/config/riscv/riscv-ext.opt b/gcc/config/riscv/riscv-ext.opt
index 0c56dc9b2710..9199aa31b420 100644
--- a/gcc/config/riscv/riscv-ext.opt
+++ b/gcc/config/riscv/riscv-ext.opt
@@ -28,6 +28,9 @@ int riscv_base_subext
 TargetVariable
 int riscv_sd_subext
 
+TargetVariable
+int riscv_sh_subext
+
 TargetVariable
 int riscv_sm_subext
 
@

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Fix uninit riscv_subset_list::m_allow_adding_dup issue

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:5e6cb89649ad4a4305d69e8f1cd030adad3a6b47

commit 5e6cb89649ad4a4305d69e8f1cd030adad3a6b47
Author: Kito Cheng 
Date:   Tue May 13 10:34:34 2025 +0800

RISC-V: Fix uninit riscv_subset_list::m_allow_adding_dup issue

We forgot to initialize m_allow_adding_dup in the constructor of
riscv_subset_list, then that will be a random value...that will lead
to a random behavior of the -march may accpet duplicate extension.

gcc/ChangeLog:

* common/config/riscv/riscv-common.cc
(riscv_subset_list::riscv_subset_list): Init m_allow_adding_dup.
Reviewed-by: Christoph Müllner 

(cherry picked from commit 991adf8b18c3fa03eff6cfbf396d9a15ef17f93c)

Diff:
---
 gcc/common/config/riscv/riscv-common.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index 3d3ca110699b..53ca03910b38 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -364,7 +364,7 @@ riscv_subset_t::riscv_subset_t ()
 
 riscv_subset_list::riscv_subset_list (const char *arch, location_t loc)
   : m_arch (arch), m_loc (loc), m_head (NULL), m_tail (NULL), m_xlen (0),
-m_subset_num (0)
+m_subset_num (0), m_allow_adding_dup (false)
 {
 }

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Drop duplicate build rule for riscv-ext.opt [NFC]

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:b0fb9ba6b2024256d26746875c58a441f47da19d

commit b0fb9ba6b2024256d26746875c58a441f47da19d
Author: Kito Cheng 
Date:   Wed May 14 23:19:38 2025 +0800

RISC-V: Drop duplicate build rule for riscv-ext.opt [NFC]

gcc/ChangeLog:

* config/riscv/t-riscv: Drop duplicate build rule for
riscv-ext.opt.

(cherry picked from commit eedaf969f4d24dad368de63ea40b1e694fd57c40)

Diff:
---
 gcc/config/riscv/t-riscv | 2 --
 1 file changed, 2 deletions(-)

diff --git a/gcc/config/riscv/t-riscv b/gcc/config/riscv/t-riscv
index e99d6689ba06..854daa96e73c 100644
--- a/gcc/config/riscv/t-riscv
+++ b/gcc/config/riscv/t-riscv
@@ -198,8 +198,6 @@ RISCV_EXT_DEFS = \
 
 $(srcdir)/config/riscv/riscv-ext.opt: $(RISCV_EXT_DEFS)
 
-$(srcdir)/config/riscv/riscv-ext.opt: s-riscv-ext.opt ; @true
-
 build/gen-riscv-ext-opt$(build_exeext): 
$(srcdir)/config/riscv/gen-riscv-ext-opt.cc \
$(RISCV_EXT_DEFS)
$(CXX_FOR_BUILD) $(CXXFLAGS_FOR_BUILD) $< -o $@

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Use riscv-ext.def to generate target options and variables

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:dff806ebade211593493b6824d59bf406af84d42

commit dff806ebade211593493b6824d59bf406af84d42
Author: Kito Cheng 
Date:   Wed May 7 18:28:18 2025 +0800

RISC-V: Use riscv-ext.def to generate target options and variables

Leverage the centralized riscv-ext.def definitions to auto-generate
the target option parsing and associated internal flags, replacing
manual listings in riscv.opt; `riscv_ext_flag_table` part will remove in
later patch.

gcc/ChangeLog:

* config/riscv/gen-riscv-ext-opt.cc: New.
* config/riscv/riscv.opt: Drop manual entries for target
options, and include riscv-ext.opt.
* config/riscv/riscv-ext.opt: New.
* config/riscv/riscv-ext.opt.urls: New.
* config.gcc: Add riscv-ext.opt to the list of target options files.
* common/config/riscv/riscv-common.cc (riscv_ext_flag_table): 
Adjsut target
option variable entry.
(riscv_set_arch_by_subset_list): Adjust target option variable.
* config/riscv/riscv-c.cc (riscv_ext_flag_table): Adjust target
option variable entry.
* config/riscv/riscv-vector-builtins.cc (pragma_intrinsic_flags):
Adjust variable name.
(riscv_pragma_intrinsic_flags_pollute): Adjust variable name.
(riscv_pragma_intrinsic_flags_restore): Ditto.
* config/riscv/t-riscv: Add the rule for generating
riscv-ext.opt.
* config/riscv/riscv-opts.h (TARGET_MIN_VLEN): Update.
(TARGET_MIN_VLEN_OPTS): Update.

(cherry picked from commit ea6154919a6416c2f75dcf025125f6926d06)

Diff:
---
 gcc/common/config/riscv/riscv-common.cc   | 102 
 gcc/config.gcc|   1 +
 gcc/config/riscv/gen-riscv-ext-opt.cc | 105 
 gcc/config/riscv/riscv-c.cc   |  16 +-
 gcc/config/riscv/riscv-ext.opt| 404 ++
 gcc/config/riscv/riscv-ext.opt.urls   |   0
 gcc/config/riscv/riscv-opts.h |  12 +-
 gcc/config/riscv/riscv-vector-builtins.cc |  20 +-
 gcc/config/riscv/riscv.opt| 336 +
 gcc/config/riscv/t-riscv  |  13 +
 10 files changed, 603 insertions(+), 406 deletions(-)

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index d3240f792401..d84aa9d78dd3 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -1777,14 +1777,14 @@ struct riscv_ext_flag_table_t {
 /* Mapping table between extension to internal flag.  */
 static const riscv_ext_flag_table_t riscv_ext_flag_table[] =
 {
-  RISCV_EXT_FLAG_ENTRY ("e", x_target_flags, MASK_RVE),
-  RISCV_EXT_FLAG_ENTRY ("m", x_target_flags, MASK_MUL),
-  RISCV_EXT_FLAG_ENTRY ("a", x_target_flags, MASK_ATOMIC),
-  RISCV_EXT_FLAG_ENTRY ("f", x_target_flags, MASK_HARD_FLOAT),
-  RISCV_EXT_FLAG_ENTRY ("d", x_target_flags, MASK_DOUBLE_FLOAT),
-  RISCV_EXT_FLAG_ENTRY ("c", x_target_flags, MASK_RVC),
-  RISCV_EXT_FLAG_ENTRY ("v", x_target_flags, MASK_FULL_V),
-  RISCV_EXT_FLAG_ENTRY ("v", x_target_flags, MASK_VECTOR),
+  RISCV_EXT_FLAG_ENTRY ("e", x_riscv_base_subext, MASK_RVE),
+  RISCV_EXT_FLAG_ENTRY ("m", x_riscv_base_subext, MASK_MUL),
+  RISCV_EXT_FLAG_ENTRY ("a", x_riscv_base_subext, MASK_ATOMIC),
+  RISCV_EXT_FLAG_ENTRY ("f", x_riscv_base_subext, MASK_HARD_FLOAT),
+  RISCV_EXT_FLAG_ENTRY ("d", x_riscv_base_subext, MASK_DOUBLE_FLOAT),
+  RISCV_EXT_FLAG_ENTRY ("c", x_riscv_base_subext, MASK_RVC),
+  RISCV_EXT_FLAG_ENTRY ("v", x_riscv_isa_flags, MASK_FULL_V),
+  RISCV_EXT_FLAG_ENTRY ("v", x_riscv_isa_flags, MASK_VECTOR),
 
   RISCV_EXT_FLAG_ENTRY ("zicsr",x_riscv_zi_subext, MASK_ZICSR),
   RISCV_EXT_FLAG_ENTRY ("zifencei", x_riscv_zi_subext, MASK_ZIFENCEI),
@@ -1828,22 +1828,22 @@ static const riscv_ext_flag_table_t 
riscv_ext_flag_table[] =
   RISCV_EXT_FLAG_ENTRY ("ziccrse", x_riscv_zi_subext, MASK_ZICCRSE),
   RISCV_EXT_FLAG_ENTRY ("zilsd",   x_riscv_zi_subext, MASK_ZILSD),
 
-  RISCV_EXT_FLAG_ENTRY ("zicboz", x_riscv_zicmo_subext, MASK_ZICBOZ),
-  RISCV_EXT_FLAG_ENTRY ("zicbom", x_riscv_zicmo_subext, MASK_ZICBOM),
-  RISCV_EXT_FLAG_ENTRY ("zicbop", x_riscv_zicmo_subext, MASK_ZICBOP),
-  RISCV_EXT_FLAG_ENTRY ("zic64b", x_riscv_zicmo_subext, MASK_ZIC64B),
+  RISCV_EXT_FLAG_ENTRY ("zicboz", x_riscv_zi_subext, MASK_ZICBOZ),
+  RISCV_EXT_FLAG_ENTRY ("zicbom", x_riscv_zi_subext, MASK_ZICBOM),
+  RISCV_EXT_FLAG_ENTRY ("zicbop", x_riscv_zi_subext, MASK_ZICBOP),
+  RISCV_EXT_FLAG_ENTRY ("zic64b", x_riscv_zi_subext, MASK_ZIC64B),
 
   RISCV_EXT_FLAG_ENTRY ("zicfiss", x_riscv_zi_subext, MASK_ZICFISS),
   RISCV_EXT_FLAG_ENTRY ("zicfilp", x_riscv_zi_subext, MASK_ZICFILP),
 
-  RISCV_EXT_FLAG_ENTRY ("zimop", x_riscv_mop_subext, MASK_ZIMOP),
-  RISCV_EXT_FLAG_ENTRY ("zcmop", x_riscv_mop_subext, MASK_ZCMOP),
+  RISCV_EXT_FLAG_ENTRY ("zimop", x_ri

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Minimal support for ssnpm, smnpm and smmpm extensions.

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:9df770e9932140bee41efb8849ab1ba057712199

commit 9df770e9932140bee41efb8849ab1ba057712199
Author: Dongyan Chen 
Date:   Mon May 12 17:19:24 2025 +0800

RISC-V: Minimal support for ssnpm, smnpm and smmpm extensions.

This patch support ssnpm, smnpm, smmpm, sspm and supm extensions[1].
To enable GCC to recognize and process ssnpm, smnpm, smmpm, sspm and
supm extensions correctly at compile time.


[1]https://github.com/riscv/riscv-j-extension/blob/master/zjpm/instructions.adoc

Changes for v5:
- Fix the testsuite error in arch-50.c.
Changes for v4:
- Fix the code based on the commit id 
9b13bea07706a7cae0185f8a860d67209308c050.
Changes for v3:
- Fix the error messages in gcc/testsuite/gcc.target/riscv/arch-46.c
Changes for v2:
- Add the sspm and supm extensions.
- Add the check_conflict_ext function to check the compatibility of ssnpm, 
smnpm, smmpm, sspm and supm extensions.
- Add the test cases for ssnpm, smnpm, smmpm, sspm and supm extensions.

gcc/ChangeLog:

* common/config/riscv/riscv-common.cc
(riscv_subset_list::check_conflict_ext): New extension.
* config/riscv/riscv.opt: Ditto.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/arch-ss-1.c: New test.
* gcc.target/riscv/arch-ss-2.c: New test.

(cherry picked from commit 7e5f5fd101f8686d34532f7afab9314f252e71cd)

Diff:
---
 gcc/common/config/riscv/riscv-common.cc| 36 ++
 gcc/config/riscv/riscv.opt | 19 
 gcc/testsuite/gcc.target/riscv/arch-ss-1.c |  5 +
 gcc/testsuite/gcc.target/riscv/arch-ss-2.c | 15 +
 4 files changed, 75 insertions(+)

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index c89931aaf869..d3240f792401 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -262,6 +262,10 @@ static const riscv_implied_info_t riscv_implied_info[] =
   {"ssstateen", "zicsr"},
   {"sstc", "zicsr"},
 
+  {"ssnpm", "zicsr"},
+  {"smnpm", "zicsr"},
+  {"smmpm", "zicsr"},
+
   {"xsfvcp", "zve32x"},
 
   {NULL, NULL}
@@ -457,6 +461,12 @@ static const struct riscv_ext_version 
riscv_ext_version_table[] =
   {"sstc",  ISA_SPEC_CLASS_NONE, 1, 0},
   {"ssstrict",  ISA_SPEC_CLASS_NONE, 1, 0},
 
+  {"ssnpm", ISA_SPEC_CLASS_NONE, 1, 0},
+  {"smnpm", ISA_SPEC_CLASS_NONE, 1, 0},
+  {"smmpm", ISA_SPEC_CLASS_NONE, 1, 0},
+  {"sspm",  ISA_SPEC_CLASS_NONE, 1, 0},
+  {"supm",  ISA_SPEC_CLASS_NONE, 1, 0},
+
   {"svade",   ISA_SPEC_CLASS_NONE, 1, 0},
   {"svadu",   ISA_SPEC_CLASS_NONE, 1, 0},
   {"svinval", ISA_SPEC_CLASS_NONE, 1, 0},
@@ -1454,6 +1464,26 @@ riscv_subset_list::check_conflict_ext ()
 error_at (m_loc, "%<-march=%s%>: zclsd extension supports in rv32 only",
  m_arch);
 
+  if (lookup ("ssnpm") && m_xlen == 32)
+error_at (m_loc, "%<-march=%s%>: ssnpm extension supports in rv64 only",
+ m_arch);
+
+  if (lookup ("smnpm") && m_xlen == 32)
+error_at (m_loc, "%<-march=%s%>: smnpm extension supports in rv64 only",
+ m_arch);
+
+  if (lookup ("smmpm") && m_xlen == 32)
+error_at (m_loc, "%<-march=%s%>: smmpm extension supports in rv64 only",
+ m_arch);
+
+  if (lookup ("sspm") && m_xlen == 32)
+error_at (m_loc, "%<-march=%s%>: sspm extension supports in rv64 only",
+ m_arch);
+
+  if (lookup ("supm") && m_xlen == 32)
+error_at (m_loc, "%<-march=%s%>: supm extension supports in rv64 only",
+ m_arch);
+
   if (lookup ("zfinx") && lookup ("f"))
 error_at (m_loc,
  "%<-march=%s%>: z*inx conflicts with floating-point "
@@ -1888,6 +1918,12 @@ static const riscv_ext_flag_table_t 
riscv_ext_flag_table[] =
   RISCV_EXT_FLAG_ENTRY ("svnapot", x_riscv_sv_subext, MASK_SVNAPOT),
   RISCV_EXT_FLAG_ENTRY ("svvptc",  x_riscv_sv_subext, MASK_SVVPTC),
 
+  RISCV_EXT_FLAG_ENTRY ("ssnpm", x_riscv_ss_subext, MASK_SSNPM),
+  RISCV_EXT_FLAG_ENTRY ("smnpm", x_riscv_sm_subext, MASK_SMNPM),
+  RISCV_EXT_FLAG_ENTRY ("smmpm", x_riscv_sm_subext, MASK_SMMPM),
+  RISCV_EXT_FLAG_ENTRY ("sspm", x_riscv_ss_subext, MASK_SSPM),
+  RISCV_EXT_FLAG_ENTRY ("supm", x_riscv_su_subext, MASK_SUPM),
+
   RISCV_EXT_FLAG_ENTRY ("ztso", x_riscv_ztso_subext, MASK_ZTSO),
 
   RISCV_EXT_FLAG_ENTRY ("xcvmac",  x_riscv_xcv_subext, MASK_XCVMAC),
diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
index ba5805e95452..9480dc54cbb5 100644
--- a/gcc/config/riscv/riscv.opt
+++ b/gcc/config/riscv/riscv.opt
@@ -482,6 +482,25 @@ Mask(SVNAPOT) Var(riscv_sv_subext)
 
 Mask(SVVPTC) Var(riscv_sv_subext)
 
+TargetVariable
+int riscv_ss_subext
+
+Mask(SSNPM) Var(riscv_ss_subext)
+
+Mask(SSPM) Var(riscv_ss_subext)
+
+TargetVariable
+int riscv_sm_subext
+
+Mask(SMNPM) Var(riscv_sm_subext)
+
+Mask(SMMPM) Var(riscv_sm_subext)
+
+Targe

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add testcases for vector unsigned integer SAT_ADD form 7

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:194d03f429fa776eba7ed9beed9bf121f5740672

commit 194d03f429fa776eba7ed9beed9bf121f5740672
Author: Pan Li 
Date:   Mon Apr 28 20:35:10 2025 +0800

RISC-V: Add testcases for vector unsigned integer SAT_ADD form 7

This patch will add testcase for unsigned integer SAT_ADD form 7:

  #define DEF_VEC_SAT_U_ADD_FMT_9(WT, T)
  \
  void __attribute__((noinline))
  \
  vec_sat_u_add_##WT##_##T##_fmt_9 (T *out, T *op_1, T *op_2, unsigned 
limit) \
  { 
  \
unsigned i; 
  \
T max = -1; 
  \
for (i = 0; i < limit; i++) 
  \
  { 
  \
T x = op_1[i];  
  \
T y = op_2[i];  
  \
WT val = (WT)x + (WT)y; 
  \
out[i] = val > max ? max : (T)val;  
  \
  } 
  \
  }

  DEF_VEC_SAT_U_ADD_FMT_9(uint64_t, uint32_t)

The below test are passed for this patch.
* The rv64gcv fully regression test.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/sat/vec_sat_arith.h: Add test helper 
macros.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-9-u16-from-u32.c: 
New test.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-9-u16-from-u64.c: 
New test.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-9-u32-from-u64.c: 
New test.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-9-u8-from-u16.c: 
New test.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-9-u8-from-u32.c: 
New test.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-9-u8-from-u64.c: 
New test.
* 
gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-9-u16-from-u32.c: New test.
* 
gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-9-u16-from-u64.c: New test.
* 
gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-9-u32-from-u64.c: New test.
* 
gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-9-u8-from-u16.c: New test.
* 
gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-9-u8-from-u32.c: New test.
* 
gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-9-u8-from-u64.c: New test.

Signed-off-by: Pan Li 
(cherry picked from commit c273a1c1846207082b60fe10c18f5c86dbcfd413)

Diff:
---
 .../riscv/rvv/autovec/sat/vec_sat_arith.h  | 31 +
 .../rvv/autovec/sat/vec_sat_u_add-9-u16-from-u32.c |  9 +++
 .../rvv/autovec/sat/vec_sat_u_add-9-u16-from-u64.c |  9 +++
 .../rvv/autovec/sat/vec_sat_u_add-9-u32-from-u64.c |  9 +++
 .../rvv/autovec/sat/vec_sat_u_add-9-u8-from-u16.c  |  9 +++
 .../rvv/autovec/sat/vec_sat_u_add-9-u8-from-u32.c  |  9 +++
 .../rvv/autovec/sat/vec_sat_u_add-9-u8-from-u64.c  |  9 +++
 .../autovec/sat/vec_sat_u_add-run-9-u16-from-u32.c | 76 ++
 .../autovec/sat/vec_sat_u_add-run-9-u16-from-u64.c | 76 ++
 .../autovec/sat/vec_sat_u_add-run-9-u32-from-u64.c | 76 ++
 .../autovec/sat/vec_sat_u_add-run-9-u8-from-u16.c  | 76 ++
 .../autovec/sat/vec_sat_u_add-run-9-u8-from-u32.c  | 76 ++
 .../autovec/sat/vec_sat_u_add-run-9-u8-from-u64.c  | 76 ++
 13 files changed, 541 insertions(+)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_arith.h 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_arith.h
index 7db892cc2e96..983c9b440abc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_arith.h
@@ -123,6 +123,22 @@ vec_sat_u_add_##T##_fmt_8 (T *out, T *op_1, T *op_2, 
unsigned limit) \
 }\
 }
 
+#define DEF_VEC_SAT_U_ADD_FMT_9(WT, T)  \
+void __attribute__((noinline))  \
+vec_sat_u_add_##WT##_##T##_fmt_9 (T *out, T *op_1, T *op_2, unsigned limit) \
+{   \
+  unsigned i;   \
+  T max = -1;   \
+  for (i = 0; i < limit; i++)   \
+{   \
+  

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Support RISC-V Profiles 20/22.

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:7f87d18ebf76b77d9808275a2f16e89ed8df4897

commit 7f87d18ebf76b77d9808275a2f16e89ed8df4897
Author: Jiawei 
Date:   Sat May 10 20:25:52 2025 +0800

RISC-V: Support RISC-V Profiles 20/22.

This patch introduces support for RISC-V Profiles RV20 and RV22 [1],
enabling developers to utilize these profiles through the -march option.

[1] https://github.com/riscv/riscv-profiles/releases/tag/v1.0

Version log:
Using lowercase letters to present Profiles.
Using '_' as divsor between Profiles and other RISC-V extension.
Add descriptions in invoke.texi.
Checking if there exist '_' between Profiles and additional extensions.
Using std::string to avoid memory problems.

gcc/ChangeLog:

* common/config/riscv/riscv-common.cc (struct riscv_profiles): New 
struct.
(riscv_subset_list::parse_profiles): New parser.
(riscv_subset_list::parse_base_ext): Ditto.
* config/riscv/riscv-subset.h: New def.
* doc/invoke.texi: New option descriptions.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/arch-49.c: New test.
* gcc.target/riscv/arch-50.c: New test.
* gcc.target/riscv/arch-51.c: New test.
* gcc.target/riscv/arch-52.c: New test.

(cherry picked from commit 43b450e3f72a53c744e77f55393962f1d349373a)

Diff:
---
 gcc/common/config/riscv/riscv-common.cc  | 85 ++--
 gcc/config/riscv/riscv-subset.h  |  2 +
 gcc/doc/invoke.texi  | 17 ---
 gcc/testsuite/gcc.target/riscv/arch-49.c |  5 ++
 gcc/testsuite/gcc.target/riscv/arch-50.c | 12 +
 gcc/testsuite/gcc.target/riscv/arch-51.c | 12 +
 gcc/testsuite/gcc.target/riscv/arch-52.c |  6 +++
 7 files changed, 130 insertions(+), 9 deletions(-)

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index ca14eb96b253..0fa2e21f272d 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -274,6 +274,12 @@ struct riscv_ext_version
   int minor_version;
 };
 
+struct riscv_profiles
+{
+  const char *profile_name;
+  const char *profile_string;
+};
+
 /* All standard extensions defined in all supported ISA spec.  */
 static const struct riscv_ext_version riscv_ext_version_table[] =
 {
@@ -502,6 +508,31 @@ static const struct riscv_ext_version riscv_combine_info[] 
=
   {NULL, ISA_SPEC_CLASS_NONE, 0, 0}
 };
 
+/* This table records the mapping form RISC-V Profiles into march string.  */
+static const riscv_profiles riscv_profiles_table[] =
+{
+  /* RVI20U only contains the base extension 'i' as mandatory extension.  */
+  {"rvi20u64", "rv64i"},
+  {"rvi20u32", "rv32i"},
+
+  /* RVA20U contains the 'i,m,a,f,d,c,zicsr,zicntr,ziccif,ziccrse,ziccamoa,
+ zicclsm,za128rs' as mandatory extensions.  */
+  {"rva20u64", "rv64imafdc_zicsr_zicntr_ziccif_ziccrse_ziccamoa"
+   "_zicclsm_za128rs"},
+
+  /* RVA22U contains the 'i,m,a,f,d,c,zicsr,zihintpause,zba,zbb,zbs,zicntr,
+ zihpm,ziccif,ziccrse,ziccamoa, zicclsm,zic64b,za64rs,zicbom,zicbop,zicboz,
+ zfhmin,zkt' as mandatory extensions.  */
+  {"rva22u64", "rv64imafdc_zicsr_zicntr_ziccif_ziccrse_ziccamoa"
+   "_zicclsm_zic64b_za64rs_zihintpause_zba_zbb_zbs_zicbom_zicbop"
+   "_zicboz_zfhmin_zkt"},
+
+  /* Currently we do not define S/M mode Profiles in gcc part.  */
+
+  /* Terminate the list.  */
+  {NULL, NULL}
+};
+
 static const riscv_cpu_info riscv_cpu_tables[] =
 {
 #define RISCV_CORE(CORE_NAME, ARCH, TUNE) \
@@ -1109,6 +1140,52 @@ riscv_subset_list::parsing_subset_version (const char 
*ext,
   return p;
 }
 
+/* Parsing RISC-V Profiles in -march string.
+   Return string with mandatory extensions of Profiles.  */
+std::string
+riscv_subset_list::parse_profiles (const char *arch)
+{
+  /* Checking if input string contains a Profiles.
+There are two cases use Profiles in -march option:
+
+1. Only use Profiles in '-march' as input
+2. Mixed Profiles with other extensions
+
+Use '_' to split Profiles and other extension.  */
+std::string p(arch);
+const size_t p_len = p.size();
+
+for (int i = 0; riscv_profiles_table[i].profile_name != nullptr; ++i)
+{
+  const std::string& p_name = riscv_profiles_table[i].profile_name;
+  const std::string& p_str = riscv_profiles_table[i].profile_string;
+  size_t pos = p.find(p_name);
+  /* Find profile at the begin.  */
+  if (pos == 0 && pos + p_name.size() <= p_len)
+   {
+ size_t after_pos = pos + p_name.size();
+ std::string after_part = p.substr(after_pos);
+
+ /* If there're only profile, return the profile_string directly.  */
+ if (after_part[0] == '\0')
+   return p_str;
+
+ /* If isn't '_' after profile, need to add it and mention the user.  
*/
+ if (after_part[0] != '_')
+ {
+   warning_at (m_loc, 0, "Should use \"%c

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [PATCH v2] RISC-V: Use vclmul for CRC expansion if available

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:ea263e8517348924e46c86b2377da13f40343668

commit ea263e8517348924e46c86b2377da13f40343668
Author: Anton Blanchard 
Date:   Sat May 10 07:07:39 2025 -0600

[PATCH v2] RISC-V: Use vclmul for CRC expansion if available

If the vector version of clmul (vclmul) is available and the scalar
one is not, use it for CRC expansion.

gcc/
* config/riscv/bitmanip.md (crc_rev4): Check
TARGET_ZVBC.
* config/riscv/riscv.cc (expand_crc_using_clmul): Emit code using
vclmul if TARGET_ZVBC.

gcc/testsuite

* gcc.target/riscv/rvv/base/crc-builtin-zvbc.c: New test.

(cherry picked from commit ab6e2d9f6f26a97e24f64a79eccbcb82b9317f82)

Diff:
---
 gcc/config/riscv/bitmanip.md   |   5 +-
 gcc/config/riscv/riscv.cc  | 108 +
 .../gcc.target/riscv/rvv/base/crc-builtin-zvbc.c   |  66 +
 3 files changed, 158 insertions(+), 21 deletions(-)

diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md
index 95df5331769e..c226c39f5801 100644
--- a/gcc/config/riscv/bitmanip.md
+++ b/gcc/config/riscv/bitmanip.md
@@ -1222,7 +1222,7 @@
  we can't keep it in 64 bit variable.)
  then use clmul instruction to implement the CRC,
  otherwise (TARGET_ZBKB) generate table based using brev.  */
-  if ((TARGET_ZBKC || TARGET_ZBC) && mode < word_mode)
+  if ((TARGET_ZBKC || TARGET_ZBC || TARGET_ZVBC) && mode < 
word_mode)
 expand_reversed_crc_using_clmul (mode, mode,
 operands);
   else if (TARGET_ZBKB)
@@ -1254,7 +1254,8 @@
  (match_operand:SUBX 3)]
  UNSPEC_CRC))]
   /* We don't support the case when data's size is bigger than CRC's size.  */
-  "(TARGET_ZBKC || TARGET_ZBC) && mode >= mode"
+  "(TARGET_ZBKC || TARGET_ZBC || TARGET_ZVBC)
+   && mode >= mode"
 {
   /* If we have the ZBC or ZBKC extension (ie, clmul) and
  it is possible to store the quotient within a single variable
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 3ee88db24fa5..a28e4f7abb87 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -14035,17 +14035,53 @@ expand_crc_using_clmul (scalar_mode crc_mode, 
scalar_mode data_mode,
   rtx data = gen_rtx_ZERO_EXTEND (word_mode, operands[2]);
   riscv_expand_op (XOR, word_mode, a0, crc, data);
 
-  if (TARGET_64BIT)
-emit_insn (gen_riscv_clmul_di (a0, a0, t0));
-  else
-emit_insn (gen_riscv_clmul_si (a0, a0, t0));
+  if (TARGET_ZBKC || TARGET_ZBC)
+{
+  if (TARGET_64BIT)
+   emit_insn (gen_riscv_clmul_di (a0, a0, t0));
+  else
+   emit_insn (gen_riscv_clmul_si (a0, a0, t0));
 
-  riscv_expand_op (LSHIFTRT, word_mode, a0, a0,
-  gen_int_mode (crc_size, word_mode));
-  if (TARGET_64BIT)
-emit_insn (gen_riscv_clmul_di (a0, a0, t1));
+  riscv_expand_op (LSHIFTRT, word_mode, a0, a0,
+  gen_int_mode (crc_size, word_mode));
+  if (TARGET_64BIT)
+   emit_insn (gen_riscv_clmul_di (a0, a0, t1));
+  else
+   emit_insn (gen_riscv_clmul_si (a0, a0, t1));
+}
   else
-emit_insn (gen_riscv_clmul_si (a0, a0, t1));
+{
+  machine_mode vmode;
+  if (!riscv_vector::get_vector_mode (DImode, 1).exists (&vmode))
+   gcc_unreachable ();
+
+  rtx vec = gen_reg_rtx (vmode);
+
+  insn_code icode1 = code_for_pred_broadcast (vmode);
+  rtx ops1[] = {vec, a0};
+  emit_nonvlmax_insn (icode1, UNARY_OP, ops1, CONST1_RTX (Pmode));
+
+  rtx rvv1di_reg = gen_rtx_SUBREG (RVVM1DImode, vec, 0);
+  insn_code icode2 = code_for_pred_vclmul_scalar (UNSPEC_VCLMUL,
+ E_RVVM1DImode);
+  rtx ops2[] = {rvv1di_reg, rvv1di_reg, t0};
+  emit_nonvlmax_insn (icode2, riscv_vector::BINARY_OP, ops2, CONST1_RTX
+ (Pmode));
+
+  rtx shift_amount = gen_int_mode (data_size, Pmode);
+  insn_code icode3 = code_for_pred_scalar (LSHIFTRT, vmode);
+  rtx ops3[] = {vec, vec, shift_amount};
+  emit_nonvlmax_insn (icode3, BINARY_OP, ops3, CONST1_RTX (Pmode));
+
+  insn_code icode4 = code_for_pred_vclmul_scalar (UNSPEC_VCLMULH,
+ E_RVVM1DImode);
+  rtx ops4[] = {rvv1di_reg, rvv1di_reg, t1};
+  emit_nonvlmax_insn (icode4, riscv_vector::BINARY_OP, ops4, CONST1_RTX
+ (Pmode));
+
+  rtx vec_low_lane = gen_lowpart (DImode, vec);
+  riscv_emit_move (a0, vec_low_lane);
+}
 
   if (crc_size > data_size)
 {
@@ -14094,19 +14130,53 @@ expand_reversed_crc_using_clmul (scalar_mode 
crc_mode, scalar_mode data_mode,
   rtx a0 = gen_reg_rtx (word_mode);
   riscv_expand_op (XOR, word_mode, a0, crc, data);
 
-  if (TARGET_64BIT)
-emit_insn (gen_riscv_clmul_di (a0, a0, t0));
-  else
-emit_insn (gen_riscv_clmul_si (a0, a0, t0));
+  if

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Support for zilsd and zclsd extensions.

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:543db94d75024a6ca09498983112e8cc48df7a2a

commit 543db94d75024a6ca09498983112e8cc48df7a2a
Author: Dongyan Chen 
Date:   Mon Mar 17 22:23:18 2025 +0800

RISC-V: Support for zilsd and zclsd extensions.

This patch support zilsd and zclsd[1] extensions.
To enable GCC to recognize and process zilsd and zclsd extension correctly 
at compile time.

[1] https://github.com/riscv/riscv-zilsd

Changes for v2:
- Remove the addition of zilsd extension in 
gcc/common/config/riscv/riscv-ext-bitmask.def
- Fix a bug with zilsd and zclsd extension dependency in 
gcc/common/config/riscv/riscv-common.cc

gcc/ChangeLog:

* common/config/riscv/riscv-common.cc
(riscv_subset_list::check_conflict_ext): New extension.
* config/riscv/riscv.opt: Ditto.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/arch-zilsd-1.c: New.
* gcc.target/riscv/arch-zilsd-2.c: New.
* gcc.target/riscv/arch-zilsd-3.c: New.

(cherry picked from commit d42f7244289ad8be1d3f7320528240bb849979e4)

Diff:
---
 gcc/common/config/riscv/riscv-common.cc   | 16 
 gcc/config/riscv/riscv.opt|  4 
 gcc/testsuite/gcc.target/riscv/arch-zilsd-1.c |  5 +
 gcc/testsuite/gcc.target/riscv/arch-zilsd-2.c |  7 +++
 gcc/testsuite/gcc.target/riscv/arch-zilsd-3.c |  9 +
 5 files changed, 41 insertions(+)

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index e06cd5fa5762..c89931aaf869 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -115,6 +115,9 @@ static const riscv_implied_info_t riscv_implied_info[] =
   {"zicfiss", "zimop"},
   {"zicfilp", "zicsr"},
 
+  {"zclsd", "zilsd"},
+  {"zclsd", "zca"},
+
   {"zk", "zkn"},
   {"zk", "zkr"},
   {"zk", "zkt"},
@@ -377,6 +380,9 @@ static const struct riscv_ext_version 
riscv_ext_version_table[] =
   {"zicntr", ISA_SPEC_CLASS_NONE, 2, 0},
   {"zihpm",  ISA_SPEC_CLASS_NONE, 2, 0},
 
+  {"zilsd",  ISA_SPEC_CLASS_NONE, 1, 0},
+  {"zclsd",  ISA_SPEC_CLASS_NONE, 1, 0},
+
   {"zk",ISA_SPEC_CLASS_NONE, 1, 0},
   {"zkn",   ISA_SPEC_CLASS_NONE, 1, 0},
   {"zks",   ISA_SPEC_CLASS_NONE, 1, 0},
@@ -1439,6 +1445,14 @@ riscv_subset_list::check_conflict_ext ()
   if (lookup ("zcf") && m_xlen == 64)
 error_at (m_loc, "%<-march=%s%>: zcf extension supports in rv32 only",
  m_arch);
+  
+  if (lookup ("zilsd") && m_xlen == 64)
+error_at (m_loc, "%<-march=%s%>: zilsd extension supports in rv32 only",
+ m_arch);
+
+  if (lookup ("zclsd") && m_xlen == 64)
+error_at (m_loc, "%<-march=%s%>: zclsd extension supports in rv32 only",
+ m_arch);
 
   if (lookup ("zfinx") && lookup ("f"))
 error_at (m_loc,
@@ -1782,6 +1796,7 @@ static const riscv_ext_flag_table_t 
riscv_ext_flag_table[] =
   RISCV_EXT_FLAG_ENTRY ("ziccif",  x_riscv_zi_subext, MASK_ZICCIF),
   RISCV_EXT_FLAG_ENTRY ("zicclsm", x_riscv_zi_subext, MASK_ZICCLSM),
   RISCV_EXT_FLAG_ENTRY ("ziccrse", x_riscv_zi_subext, MASK_ZICCRSE),
+  RISCV_EXT_FLAG_ENTRY ("zilsd",   x_riscv_zi_subext, MASK_ZILSD),
 
   RISCV_EXT_FLAG_ENTRY ("zicboz", x_riscv_zicmo_subext, MASK_ZICBOZ),
   RISCV_EXT_FLAG_ENTRY ("zicbom", x_riscv_zicmo_subext, MASK_ZICBOM),
@@ -1865,6 +1880,7 @@ static const riscv_ext_flag_table_t 
riscv_ext_flag_table[] =
   RISCV_EXT_FLAG_ENTRY ("zcd",  x_riscv_zc_subext, MASK_ZCD),
   RISCV_EXT_FLAG_ENTRY ("zcmp", x_riscv_zc_subext, MASK_ZCMP),
   RISCV_EXT_FLAG_ENTRY ("zcmt", x_riscv_zc_subext, MASK_ZCMT),
+  RISCV_EXT_FLAG_ENTRY ("zclsd", x_riscv_zc_subext, MASK_ZCLSD),
 
   RISCV_EXT_FLAG_ENTRY ("svade",   x_riscv_sv_subext, MASK_SVADE),
   RISCV_EXT_FLAG_ENTRY ("svadu",   x_riscv_sv_subext, MASK_SVADU),
diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
index 80593ee139c1..ba5805e95452 100644
--- a/gcc/config/riscv/riscv.opt
+++ b/gcc/config/riscv/riscv.opt
@@ -257,6 +257,8 @@ Mask(ZICFISS) Var(riscv_zi_subext)
 
 Mask(ZICFILP) Var(riscv_zi_subext)
 
+Mask(ZILSD)   Var(riscv_zi_subext)
+
 TargetVariable
 int riscv_za_subext
 
@@ -463,6 +465,8 @@ Mask(ZCMP) Var(riscv_zc_subext)
 
 Mask(ZCMT) Var(riscv_zc_subext)
 
+Mask(ZCLSD) Var(riscv_zc_subext)
+
 Mask(XCVBI) Var(riscv_xcv_subext)
 
 TargetVariable
diff --git a/gcc/testsuite/gcc.target/riscv/arch-zilsd-1.c 
b/gcc/testsuite/gcc.target/riscv/arch-zilsd-1.c
new file mode 100644
index ..452c04e42f6d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/arch-zilsd-1.c
@@ -0,0 +1,5 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zilsd_zclsd -mabi=ilp32d" } */
+int foo()
+{
+}
diff --git a/gcc/testsuite/gcc.target/riscv/arch-zilsd-2.c 
b/gcc/testsuite/gcc.target/riscv/arch-zilsd-2.c
new file mode 100644
index ..5d6185d0d365
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/arch-zilsd-2.c
@@ -0,0 +

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] testsuite: Fix RISC-V arch-52.c format issue.

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:e63c2075e730fa4e1374b828bdd86f18838406e4

commit e63c2075e730fa4e1374b828bdd86f18838406e4
Author: Jiawei 
Date:   Mon May 12 13:23:50 2025 +0800

testsuite: Fix RISC-V arch-52.c format issue.

Fix incorrect regular expression.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/arch-52.c: Fix regular expression.

(cherry picked from commit 63d26b0e1f11043552404d2ba6448ec74840fa48)

Diff:
---
 gcc/testsuite/gcc.target/riscv/arch-52.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/testsuite/gcc.target/riscv/arch-52.c 
b/gcc/testsuite/gcc.target/riscv/arch-52.c
index da6aea8fd94d..6133370b68ae 100644
--- a/gcc/testsuite/gcc.target/riscv/arch-52.c
+++ b/gcc/testsuite/gcc.target/riscv/arch-52.c
@@ -1,6 +1,6 @@
 /* { dg-do compile } */
 /* { dg-options "-march=rva22u64v -mabi=lp64" } */
-/* { dg-warning "*Should use \"_\" to contact Profiles with other extensions" 
} */
+/* { dg-warning "Should use \"_\" to contact Profiles with other extensions" 
"" { target *-*-* } 0 } */
 int
 foo ()
 {}

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Support RISC-V Profiles 23.

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:e887f88194ffa0fd62111d6f357063e6f83c65a1

commit e887f88194ffa0fd62111d6f357063e6f83c65a1
Author: Jiawei 
Date:   Sat May 10 19:26:35 2025 +0800

RISC-V: Support RISC-V Profiles 23.

This patch introduces support for RISC-V Profiles RV23A and RV23B [1],
enabling developers to utilize these profiles through the -march option.

[1] 
https://github.com/riscv/riscv-profiles/releases/tag/rva23-rvb23-ratified

Version log:
Update the testcases, using lowercase letter.

gcc/ChangeLog:

* common/config/riscv/riscv-common.cc: New profile.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/arch-53.c: New test.
* gcc.target/riscv/arch-54.c: New test.

(cherry picked from commit 66d17ba3cb47980455ee9d6b4123dce61aef2fa2)

Diff:
---
 gcc/common/config/riscv/riscv-common.cc  | 16 
 gcc/testsuite/gcc.target/riscv/arch-53.c | 11 +++
 gcc/testsuite/gcc.target/riscv/arch-54.c | 10 ++
 3 files changed, 37 insertions(+)

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index 0fa2e21f272d..e06cd5fa5762 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -527,6 +527,22 @@ static const riscv_profiles riscv_profiles_table[] =
"_zicclsm_zic64b_za64rs_zihintpause_zba_zbb_zbs_zicbom_zicbop"
"_zicboz_zfhmin_zkt"},
 
+  /* RVA23 contains all mandatory base ISA for RVA22U64 and the new extension
+ 'v,zihintntl,zvfhmin,zvbb,zvkt,zicond,zimop,zcmop,zfa,zawrs' as mandatory
+ extensions.  */
+  {"rva23u64", "rv64imafdcv_zicsr_zicntr_zihpm_ziccif_ziccrse_ziccamoa"
+   "_zicclsm_zic64b_za64rs_zihintpause_zba_zbb_zbs_zicbom_zicbop"
+   "_zicboz_zfhmin_zkt_zvfhmin_zvbb_zvkt_zihintntl_zicond_zimop_zcmop_zcb"
+   "_zfa_zawrs"},
+
+  /* RVB23 contains all mandatory base ISA for RVA22U64 and the new extension
+ 'zihintntl,zicond,zimop,zcmop,zfa,zawrs' as mandatory
+ extensions.  */
+  {"rvb23u64", "rv64imafdc_zicsr_zicntr_zihpm_ziccif_ziccrse_ziccamoa"
+   "_zicclsm_zic64b_za64rs_zihintpause_zba_zbb_zbs_zicbom_zicbop"
+   "_zicboz_zfhmin_zkt_zihintntl_zicond_zimop_zcmop_zcb"
+   "_zfa_zawrs"},
+
   /* Currently we do not define S/M mode Profiles in gcc part.  */
 
   /* Terminate the list.  */
diff --git a/gcc/testsuite/gcc.target/riscv/arch-53.c 
b/gcc/testsuite/gcc.target/riscv/arch-53.c
new file mode 100644
index ..8210978ee8ba
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/arch-53.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rva23u64 -mabi=lp64d" } */
+
+void foo(){}
+
+/* { dg-final { scan-assembler ".attribute arch, 
\"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0"
+"_b1p0_v1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0"
+_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0"
+_za64rs1p0_zaamo1p0_zalrsc1p0_zawrs1p0_zfa1p0_zfhmin1p0_zca1p0_zcb1p0_zcd1p0_zcmop1p0"
+_zba1p0_zbb1p0_zbs1p0_zkt1p0_zvbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0"
+_zvfhmin1p0_zvkb1p0_zvkt1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0\"" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/arch-54.c 
b/gcc/testsuite/gcc.target/riscv/arch-54.c
new file mode 100644
index ..6d242dfba506
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/arch-54.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rvb23u64 -mabi=lp64d" } */
+
+void foo(){}
+
+/* { dg-final { scan-assembler ".attribute arch, 
\"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0"
+"_b1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0"
+"_zicntr2p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_za64rs1p0"
+"_zaamo1p0_zalrsc1p0_zawrs1p0_zfa1p0_zfhmin1p0_zca1p0_zcb1p0_zcd1p0_zcmop1p0_zba1p0"
+"_zbb1p0_zbs1p0_zkt1p0\"" } } */

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add testcases for vec_duplicate + vadd.vv combine case 1 with GR2VR cost 0

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:1072dae78cb698415023be373ce18c24e434f972

commit 1072dae78cb698415023be373ce18c24e434f972
Author: Pan Li 
Date:   Thu May 8 11:19:11 2025 +0800

RISC-V: Add testcases for vec_duplicate + vadd.vv combine case 1 with GR2VR 
cost 0

Add asm dump check and for vec_duplicate + vadd.vv combine case 1 to 
vadd.vx.
The late-combine will take action when GR2VR cost is 0, because the vmv
and the vadd.vx will consume the same cost of GR2VR.  Aka:

Before:
L1:
  vmv.v.x
  vadd.vv
  J L1

After:
L1:
  vadd.vx
  J L1

The below test suites are passed for this patch.
* The rv64gcv fully regression test.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h: Add test
helper macros.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-i16.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-i32.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-i64.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-i8.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-u16.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-u32.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-u64.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-u8.c: New test.

Signed-off-by: Pan Li 
(cherry picked from commit 5ee51001ec056356eb8f6cbece73cff6d73003e5)

Diff:
---
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h | 44 ++
 .../riscv/rvv/autovec/vx_vf/vx_vadd-4-i16.c|  8 
 .../riscv/rvv/autovec/vx_vf/vx_vadd-4-i32.c|  8 
 .../riscv/rvv/autovec/vx_vf/vx_vadd-4-i64.c|  8 
 .../riscv/rvv/autovec/vx_vf/vx_vadd-4-i8.c |  8 
 .../riscv/rvv/autovec/vx_vf/vx_vadd-4-u16.c|  8 
 .../riscv/rvv/autovec/vx_vf/vx_vadd-4-u32.c|  8 
 .../riscv/rvv/autovec/vx_vf/vx_vadd-4-u64.c|  8 
 .../riscv/rvv/autovec/vx_vf/vx_vadd-4-u8.c |  8 
 9 files changed, 108 insertions(+)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h
index de5b70dd04b6..db802bdefd74 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h
@@ -14,4 +14,48 @@ test_vx_binary_case_0 (T * restrict out, T * restrict in, T 
x, unsigned n) \
 #define RUN_VX_BINARY_CASE_0(out, in, x, n)  test_vx_binary_case_0(out, 
in, x, n)
 #define RUN_VX_BINARY_CASE_0_WRAP(out, in, x, n) RUN_VX_BINARY_CASE_0(out, in, 
x, n)
 
+#define VX_BINARY_BODY(op)   \
+  out[k + 0] = in[k + 0] op tmp; \
+  out[k + 1] = in[k + 1] op tmp; \
+  k += 2;
+
+#define VX_BINARY_BODY_X4(op) \
+  VX_BINARY_BODY(op)  \
+  VX_BINARY_BODY(op)
+
+#define VX_BINARY_BODY_X8(op) \
+  VX_BINARY_BODY_X4(op)   \
+  VX_BINARY_BODY_X4(op)
+
+#define VX_BINARY_BODY_X16(op) \
+  VX_BINARY_BODY_X8(op)\
+  VX_BINARY_BODY_X8(op)
+
+#define VX_BINARY_BODY_X32(op) \
+  VX_BINARY_BODY_X16(op)   \
+  VX_BINARY_BODY_X16(op)
+
+#define VX_BINARY_BODY_X64(op) \
+  VX_BINARY_BODY_X32(op)   \
+  VX_BINARY_BODY_X32(op)
+
+#define VX_BINARY_BODY_X128(op) \
+  VX_BINARY_BODY_X64(op)\
+  VX_BINARY_BODY_X64(op)
+
+#define DEF_VX_BINARY_CASE_1(T, OP, BODY)  \
+void   \
+test_vx_binary_case_1 (T * restrict out, T * restrict in, T x, unsigned n) \
+{  \
+  unsigned k = 0;  \
+  T tmp = x + 3;   \
+   \
+  while (k < n)\
+{  \
+  tmp = tmp ^ 0x3f;\
+  BODY(OP) \
+}  \
+}
+#define DEF_VX_BINARY_CASE_1_WRAP(T, OP, BODY) DEF_VX_BINARY_CASE_1(T, OP, 
BODY)
+
 #endif
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-i16.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-i16.c
new file mode 100644
index ..9a26601165ed
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-i16.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+
+DEF_VX_BINARY_CASE_1(int16_t, +, VX_BINARY_BODY_X16)
+
+/* { dg-final { scan-assembler {va

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [RISC-V][PR target/120137][PR target/120154] Don't create out-of-range permutation constants

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:8ad57623b394796b3dd2a8f22d7535df430cb53d

commit 8ad57623b394796b3dd2a8f22d7535df430cb53d
Author: Jeff Law 
Date:   Wed May 7 15:06:58 2025 -0600

[RISC-V][PR target/120137][PR target/120154] Don't create out-of-range 
permutation constants

To make hashing sensible we canonicalize constant vectors in the hash table 
so
that their first entry always has the value zero.  That normalization can
result in a value that can't be represented in the element mode.

So before entering anything into the hash table we need to verify the
normalized entries will fit into the element's mode.

This fixes both 120137 and its duplicate 120154.  This has been tested in my
tester.  I'm just waiting for the pre-commit tester to render its verdict.

PR target/120137
PR target/120154
gcc/
* config/riscv/riscv-vect-permconst.cc (process_bb): Verify each
canonicalized element fits into the vector element mode.

gcc/testsuite/

* gcc.target/riscv/pr120137.c: New test.
* gcc.target/riscv/pr120154.c: New test.

(cherry picked from commit 49c44911df72f55e2004ffa9f5eb362de29ca188)

Diff:
---
 gcc/config/riscv/riscv-vect-permconst.cc  | 20 +++-
 gcc/testsuite/gcc.target/riscv/pr120137.c | 12 
 gcc/testsuite/gcc.target/riscv/pr120154.c | 22 ++
 3 files changed, 53 insertions(+), 1 deletion(-)

diff --git a/gcc/config/riscv/riscv-vect-permconst.cc 
b/gcc/config/riscv/riscv-vect-permconst.cc
index feecc7ed6da0..8e13cf8d5587 100644
--- a/gcc/config/riscv/riscv-vect-permconst.cc
+++ b/gcc/config/riscv/riscv-vect-permconst.cc
@@ -203,6 +203,24 @@ vector_permconst::process_bb (basic_block bb)
   if (bias < 0 || bias > 16384 / 8)
continue;
 
+  /* We need to verify that each element would be a valid value
+in the inner mode after applying the bias.  */
+  machine_mode inner = GET_MODE_INNER (GET_MODE (cvec));
+  HOST_WIDE_INT precision = GET_MODE_PRECISION (inner).to_constant ();
+  int i;
+  for (i = 0; i < CONST_VECTOR_NUNITS (cvec).to_constant (); i++)
+   {
+ HOST_WIDE_INT val = INTVAL (CONST_VECTOR_ELT (cvec, i)) - bias;
+ if (val != sext_hwi (val, precision))
+   break;
+   }
+
+  /* If the loop terminated early, then we found a case where the
+adjusted constant would not fit, so we can't record the constant
+for this case (it's unlikely to be useful anyway.  */
+  if (i != CONST_VECTOR_NUNITS (cvec).to_constant ())
+   continue;
+
   /* At this point we have a load of a constant integer vector from the
 constant pool.  That constant integer vector is hopefully a
 permutation constant.  We need to make a copy of the vector and
@@ -211,7 +229,7 @@ vector_permconst::process_bb (basic_block bb)
 XXX This violates structure sharing conventions.  */
   rtvec_def *nvec = gen_rtvec (CONST_VECTOR_NUNITS (cvec).to_constant ());
 
-  for (int i = 0; i < CONST_VECTOR_NUNITS (cvec).to_constant (); i++)
+  for (i = 0; i < CONST_VECTOR_NUNITS (cvec).to_constant (); i++)
nvec->elem[i] = GEN_INT (INTVAL (CONST_VECTOR_ELT (cvec, i)) - bias);
 
   rtx copy = gen_rtx_CONST_VECTOR (GET_MODE (cvec), nvec);
diff --git a/gcc/testsuite/gcc.target/riscv/pr120137.c 
b/gcc/testsuite/gcc.target/riscv/pr120137.c
new file mode 100644
index ..c55a1c1b5bf3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/pr120137.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl256b -mrvv-vector-bits=zvl -mabi=lp64" } */
+
+char b[13][13];
+void c() {
+  for (int d = 0; d < 13; ++d)
+for (int e = 0; e < 13; ++e)
+  b[d][e] = e == 0 ? -98 : 38;
+}
+
+
+
diff --git a/gcc/testsuite/gcc.target/riscv/pr120154.c 
b/gcc/testsuite/gcc.target/riscv/pr120154.c
new file mode 100644
index ..fd849ca154ae
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/pr120154.c
@@ -0,0 +1,22 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gv -mabi=lp64" } */
+
+
+
+typedef __attribute__((__vector_size__(4))) char V;
+
+V g;
+
+V
+bar(V a, V b)
+{
+  V s = a + b + g;
+  return s;
+}
+
+V
+foo()
+{
+  return bar((V){20}, (V){23, 150});
+}
+

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Drop riscv_ext_flag_table in favor of riscv_ext_info_t data

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:8b77ff652532617fd584e2eb8886d1ffcf8690f0

commit 8b77ff652532617fd584e2eb8886d1ffcf8690f0
Author: Kito Cheng 
Date:   Wed May 7 21:27:20 2025 +0800

RISC-V: Drop riscv_ext_flag_table in favor of riscv_ext_info_t data

Refactor extension flag handling by removing the old riscv_ext_flag_table 
and
sourcing all flag definitions directly from the flags field of the unified
riscv_ext_info_t structures generated from riscv-ext.def.

gcc/ChangeLog:

* common/config/riscv/riscv-common.cc 
(riscv_extra_ext_flag_table_t):
New.
(riscv_ext_flag_table): Rename to ...
(riscv_extra_ext_flag_table): this, and drop most of definitions
that can obtained from the flags field of the riscv_ext_info_t
structures.
(apply_extra_extension_flags): Use riscv_ext_info_t.
(riscv_ext_is_subset): Ditto.

(cherry picked from commit 90c6ccebd762ae920690fce20cd3f2b8e24357a7)

Diff:
---
 gcc/common/config/riscv/riscv-common.cc | 221 
 1 file changed, 27 insertions(+), 194 deletions(-)

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index d50aff4ae344..3d3ca110699b 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -47,21 +47,20 @@ typedef int (gcc_options::*opt_var_ref_t);
 typedef int (cl_target_option::*cl_opt_var_ref_t);
 
 /* Types for recording extension to internal flag.  */
-struct riscv_ext_flag_table_t
+struct riscv_extra_ext_flag_table_t
 {
-  riscv_ext_flag_table_t (const char *ext, opt_var_ref_t var_ref,
- cl_opt_var_ref_t cl_var_ref, int mask)
-   : ext (ext), var_ref (var_ref), cl_var_ref (cl_var_ref), mask (mask)
-  {}
-  riscv_ext_flag_table_t (opt_var_ref_t var_ref,
- cl_opt_var_ref_t cl_var_ref, int mask)
-   : ext (nullptr), var_ref (var_ref), cl_var_ref (cl_var_ref), mask (mask)
-  {}
-
   const char *ext;
   opt_var_ref_t var_ref;
   cl_opt_var_ref_t cl_var_ref;
   int mask;
+};
+
+/* Types for recording extension to internal flag.  */
+struct riscv_ext_flag_table_t
+{
+  opt_var_ref_t var_ref;
+  cl_opt_var_ref_t cl_var_ref;
+  int mask;
 
   void clean (gcc_options *opts) const { opts->*var_ref &= ~mask; }
 
@@ -1475,76 +1474,12 @@ riscv_arch_str (bool version_p)
 #define RISCV_EXT_FLAG_ENTRY(NAME, VAR, MASK) \
   {NAME, &gcc_options::VAR, &cl_target_option::VAR, MASK}
 
-/* Mapping table between extension to internal flag.  */
-static const riscv_ext_flag_table_t riscv_ext_flag_table[] =
+/* Mapping table between extension to internal flag,
+   this table is not needed to add manually unless there is speical rule.  */
+static const riscv_extra_ext_flag_table_t riscv_extra_ext_flag_table[] =
 {
-  RISCV_EXT_FLAG_ENTRY ("e", x_riscv_base_subext, MASK_RVE),
-  RISCV_EXT_FLAG_ENTRY ("m", x_riscv_base_subext, MASK_MUL),
-  RISCV_EXT_FLAG_ENTRY ("a", x_riscv_base_subext, MASK_ATOMIC),
-  RISCV_EXT_FLAG_ENTRY ("f", x_riscv_base_subext, MASK_HARD_FLOAT),
-  RISCV_EXT_FLAG_ENTRY ("d", x_riscv_base_subext, MASK_DOUBLE_FLOAT),
-  RISCV_EXT_FLAG_ENTRY ("c", x_riscv_base_subext, MASK_RVC),
-  RISCV_EXT_FLAG_ENTRY ("v", x_riscv_isa_flags, MASK_FULL_V),
-  RISCV_EXT_FLAG_ENTRY ("v", x_riscv_isa_flags, MASK_VECTOR),
-
-  RISCV_EXT_FLAG_ENTRY ("zicsr",x_riscv_zi_subext, MASK_ZICSR),
-  RISCV_EXT_FLAG_ENTRY ("zifencei", x_riscv_zi_subext, MASK_ZIFENCEI),
-  RISCV_EXT_FLAG_ENTRY ("zicond",   x_riscv_zi_subext, MASK_ZICOND),
-
-  RISCV_EXT_FLAG_ENTRY ("za64rs",  x_riscv_za_subext, MASK_ZA64RS),
-  RISCV_EXT_FLAG_ENTRY ("za128rs", x_riscv_za_subext, MASK_ZA128RS),
-  RISCV_EXT_FLAG_ENTRY ("zawrs",   x_riscv_za_subext, MASK_ZAWRS),
-  RISCV_EXT_FLAG_ENTRY ("zaamo",   x_riscv_za_subext, MASK_ZAAMO),
-  RISCV_EXT_FLAG_ENTRY ("zalrsc",  x_riscv_za_subext, MASK_ZALRSC),
-  RISCV_EXT_FLAG_ENTRY ("zabha",   x_riscv_za_subext, MASK_ZABHA),
-  RISCV_EXT_FLAG_ENTRY ("zacas",   x_riscv_za_subext, MASK_ZACAS),
-  RISCV_EXT_FLAG_ENTRY ("zama16b", x_riscv_za_subext, MASK_ZAMA16B),
-
-  RISCV_EXT_FLAG_ENTRY ("zba", x_riscv_zb_subext, MASK_ZBA),
-  RISCV_EXT_FLAG_ENTRY ("zbb", x_riscv_zb_subext, MASK_ZBB),
-  RISCV_EXT_FLAG_ENTRY ("zbc", x_riscv_zb_subext, MASK_ZBC),
-  RISCV_EXT_FLAG_ENTRY ("zbs", x_riscv_zb_subext, MASK_ZBS),
-
-  RISCV_EXT_FLAG_ENTRY ("zfinx",x_riscv_zinx_subext, MASK_ZFINX),
-  RISCV_EXT_FLAG_ENTRY ("zdinx",x_riscv_zinx_subext, MASK_ZDINX),
-  RISCV_EXT_FLAG_ENTRY ("zhinx",x_riscv_zinx_subext, MASK_ZHINX),
-  RISCV_EXT_FLAG_ENTRY ("zhinxmin", x_riscv_zinx_subext, MASK_ZHINXMIN),
-
-  RISCV_EXT_FLAG_ENTRY ("zbkb",  x_riscv_zk_subext, MASK_ZBKB),
-  RISCV_EXT_FLAG_ENTRY ("zbkc",  x_riscv_zk_subext, MASK_ZBKC),
-  RISCV_EXT_FLAG_ENTRY ("zbkx",  x_riscv_zk_subext, MASK_ZBKX),
-  RISCV_EXT_FLAG_ENTRY ("zknd",  x_riscv_zk_subext, MASK_ZKND),
-  RISCV_EXT_FLAG_ENTRY ("zkne",  x_riscv_

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [RISC-V][PR target/120223] Don't use bset/binv for XTHEADBS

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:103da6a7a8262f4fd2b81568bb15686dc5669760

commit 103da6a7a8262f4fd2b81568bb15686dc5669760
Author: Jeff Law 
Date:   Thu May 15 09:03:13 2025 -0600

[RISC-V][PR target/120223] Don't use bset/binv for XTHEADBS

Thead has the XTHEADBB extension which has a lot of overlap with Zbb.  I 
made
the incorrect assumption that XTHEADBS would largely be like Zbs when
generalizing Shreya's work.

As a result we can't use the operation synthesis code for IOR/XOR because we
don't have binv/bset like capabilities.  I should have double checked on
XTHEADBS, my bad.

Anyway, the fix is trivial.  Don't allow bset/binv based on XTHEADBS.

Already spun in my tester.  Spinning in the pre-commit CI system now.

PR target/120223
gcc/
* config/riscv/riscv.cc (synthesize_ior_xor): XTHEADBS does not have
single bit manipulations.

gcc/testsuite/

* gcc.target/riscv/pr120223.c: New test.

(cherry picked from commit 87d0daab1ec9d5c901295e8045cbd67f80b2fa23)

Diff:
---
 gcc/config/riscv/riscv.cc | 4 ++--
 gcc/testsuite/gcc.target/riscv/pr120223.c | 4 
 2 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index d28aee4b4398..d996965d0953 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -14227,7 +14227,7 @@ synthesize_ior_xor (rtx_code code, rtx operands[3])
 {
   /* Trivial cases that don't need synthesis.  */
   if (SMALL_OPERAND (INTVAL (operands[2]))
- || ((TARGET_ZBS || TARGET_XTHEADBS || TARGET_ZBKB)
+ || ((TARGET_ZBS || TARGET_ZBKB)
 && single_bit_mask_operand (operands[2], word_mode)))
 return false;
 
@@ -14264,7 +14264,7 @@ synthesize_ior_xor (rtx_code code, rtx operands[3])
   /* If we're flipping all but a small number of bits we can pre-flip
  the outliers, then flip all the bits, which would restore those
  bits that were pre-flipped. */
-  if ((TARGET_ZBS || TARGET_XTHEADBS || TARGET_ZBKB)
+  if ((TARGET_ZBS || TARGET_ZBKB)
   && budget < 0
   && code == XOR
   && popcount_hwi (~INTVAL (operands[2])) < original_budget)
diff --git a/gcc/testsuite/gcc.target/riscv/pr120223.c 
b/gcc/testsuite/gcc.target/riscv/pr120223.c
new file mode 100644
index ..fae21b6d1ece
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/pr120223.c
@@ -0,0 +1,4 @@
+/* { dg-do compile } */
+/* { dg-options "-mcpu=thead-c906" }  */
+long foo(long x) { return x ^ 0x8000; }
+

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vsub.vv combine case 0 with GR2VR cost 0

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:7195b881e26fd641735c9da502650bf3b1fd16c2

commit 7195b881e26fd641735c9da502650bf3b1fd16c2
Author: Pan Li 
Date:   Sun May 11 16:27:48 2025 +0800

RISC-V: Add test for vec_duplicate + vsub.vv combine case 0 with GR2VR cost 0

Add asm dump check and run test for vec_duplicate + vsub.vv
combine to vsub.vx.

The below test suites are passed for this patch.
* The rv64gcv fully regression test.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c: Add vector sub
vx combine asm check.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h: Add test
data for vector sub vx combine.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-i16.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-i32.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-i64.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-i8.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-u16.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-u32.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-u64.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-u8.c: New test.

Signed-off-by: Pan Li 
(cherry picked from commit 2e459a5466dc66f90f108418e4cbfd5d2d91daa1)

Diff:
---
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c  |   2 +
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c  |   2 +
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c  |   2 +
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c   |   2 +
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c  |   2 +
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c  |   2 +
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c  |   2 +
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c   |   2 +
 .../riscv/rvv/autovec/vx_vf/vx_binary_data.h   | 392 +
 .../riscv/rvv/autovec/vx_vf/vx_vsub-run-1-i16.c|  15 +
 .../riscv/rvv/autovec/vx_vf/vx_vsub-run-1-i32.c|  15 +
 .../riscv/rvv/autovec/vx_vf/vx_vsub-run-1-i64.c|  15 +
 .../riscv/rvv/autovec/vx_vf/vx_vsub-run-1-i8.c |  15 +
 .../riscv/rvv/autovec/vx_vf/vx_vsub-run-1-u16.c|  15 +
 .../riscv/rvv/autovec/vx_vf/vx_vsub-run-1-u32.c|  15 +
 .../riscv/rvv/autovec/vx_vf/vx_vsub-run-1-u64.c|  15 +
 .../riscv/rvv/autovec/vx_vf/vx_vsub-run-1-u8.c |  15 +
 17 files changed, 528 insertions(+)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c
index af93deef79bc..c6b25f1b8575 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c
@@ -4,5 +4,7 @@
 #include "vx_binary.h"
 
 DEF_VX_BINARY_CASE_0(int16_t, +, add)
+DEF_VX_BINARY_CASE_0(int16_t, -, sub)
 
 /* { dg-final { scan-assembler-times {vadd.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vsub.vx} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c
index 0cde8ba916b6..cb4ccfa17903 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c
@@ -4,5 +4,7 @@
 #include "vx_binary.h"
 
 DEF_VX_BINARY_CASE_0(int32_t, +, add)
+DEF_VX_BINARY_CASE_0(int32_t, -, sub)
 
 /* { dg-final { scan-assembler-times {vadd.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vsub.vx} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c
index 78d131e577ad..bf249846452b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c
@@ -4,5 +4,7 @@
 #include "vx_binary.h"
 
 DEF_VX_BINARY_CASE_0(int64_t, +, add)
+DEF_VX_BINARY_CASE_0(int64_t, -, sub)
 
 /* { dg-final { scan-assembler-times {vadd.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vsub.vx} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c
index 2d3408d3cad8..e830c753ae81 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c
@@ -4,5 +4,7 @@
 #include "vx_binary.h"
 
 DEF

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vsub.vv combine case 0 with GR2VR cost 1

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:c0cb19a9b46d4fbdb14006a6f9759c0f81672700

commit c0cb19a9b46d4fbdb14006a6f9759c0f81672700
Author: Pan Li 
Date:   Sun May 11 16:31:16 2025 +0800

RISC-V: Add test for vec_duplicate + vsub.vv combine case 0 with GR2VR cost 
1

Add asm dump check test for vec_duplicate + vsub.vv combine to vsub.vx

The below test suites are passed for this patch.
* The rv64gcv fully regression test.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c: Add test cases
for vsub vx combine with GR2VR cost 1.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c: Diito.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c: Diito.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c: Diito.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c: Diito.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c: Diito.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c: Diito.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c: Diito.

Signed-off-by: Pan Li 
(cherry picked from commit ee2dcc2236e28e8b86a9c953d4723364add61128)

Diff:
---
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c  | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c  | 2 ++
 8 files changed, 16 insertions(+)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c
index b7a5a1053373..49e9957cf15b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c
@@ -4,5 +4,7 @@
 #include "vx_binary.h"
 
 DEF_VX_BINARY_CASE_0(int16_t, +, add)
+DEF_VX_BINARY_CASE_0(int16_t, -, sub)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
+/* { dg-final { scan-assembler-not {vsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c
index 77ce9ab782b8..869f9fd7e246 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c
@@ -4,5 +4,7 @@
 #include "vx_binary.h"
 
 DEF_VX_BINARY_CASE_0(int32_t, +, add)
+DEF_VX_BINARY_CASE_0(int32_t, -, sub)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
+/* { dg-final { scan-assembler-not {vsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c
index ade54d346eb6..6ba714319975 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c
@@ -4,5 +4,7 @@
 #include "vx_binary.h"
 
 DEF_VX_BINARY_CASE_0(int64_t, +, add)
+DEF_VX_BINARY_CASE_0(int64_t, -, sub)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
+/* { dg-final { scan-assembler-not {vsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c
index 9bef0ef10d19..128a279dbb26 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c
@@ -4,5 +4,7 @@
 #include "vx_binary.h"
 
 DEF_VX_BINARY_CASE_0(int8_t, +, add)
+DEF_VX_BINARY_CASE_0(int8_t, -, sub)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
+/* { dg-final { scan-assembler-not {vsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c
index 52c92a7b3594..a2a35ccd8f17 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c
@@ -4,5 +4,7 @@
 #include "vx_binary.h"
 
 DEF_VX_BINARY_CASE_0(uint16_t, +, add)
+DEF_VX_BINARY_CASE_0(uint16_t, -, sub)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
+/* { dg-final { scan-assembler-not {vsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c
index 1ef2bf87b1bb..bd89bfa6fd09 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c
@@ -4,5 +4,7 @@
 #include "vx_binary.h"
 
 DEF_VX_BINARY_CASE_0(uint32_t, +, add)
+DEF_VX_BINARY_CASE_0(uint32_t, -, sub)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
+/* { dg-final { scan-assembler-not {vsub.vx} } } */
diff --git a/gcc/te

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Reuse test name for vx combine test data [NFC]

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:9a8ca2f4b34ed39f5d17ab7798864d46c7788f45

commit 9a8ca2f4b34ed39f5d17ab7798864d46c7788f45
Author: Pan Li 
Date:   Tue May 13 22:54:17 2025 +0800

RISC-V: Reuse test name for vx combine test data [NFC]

For run test, we have a name like add/sub to indicate
the testcase.  So we can reuse this to identify the
test data instead of a new one.

The below test suites are passed for this patch.
* The rv64gcv fully regression test.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h: Take
test name for the vx combine test data.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-i16.c: Leverage
the test name to identify the test data.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-i32.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-i64.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-i8.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-i16.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-i32.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-i64.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-i8.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-u8.c: Ditto.

Signed-off-by: Pan Li 
(cherry picked from commit 6eead9665eaf0d26aa162000df0aef142c55527e)

Diff:
---
 .../riscv/rvv/autovec/vx_vf/vx_binary_data.h   | 32 +++---
 .../riscv/rvv/autovec/vx_vf/vx_vadd-run-1-i16.c|  2 +-
 .../riscv/rvv/autovec/vx_vf/vx_vadd-run-1-i32.c|  2 +-
 .../riscv/rvv/autovec/vx_vf/vx_vadd-run-1-i64.c|  2 +-
 .../riscv/rvv/autovec/vx_vf/vx_vadd-run-1-i8.c |  4 +--
 .../riscv/rvv/autovec/vx_vf/vx_vadd-run-1-u16.c|  2 +-
 .../riscv/rvv/autovec/vx_vf/vx_vadd-run-1-u32.c|  2 +-
 .../riscv/rvv/autovec/vx_vf/vx_vadd-run-1-u64.c|  2 +-
 .../riscv/rvv/autovec/vx_vf/vx_vadd-run-1-u8.c |  2 +-
 .../riscv/rvv/autovec/vx_vf/vx_vsub-run-1-i16.c|  2 +-
 .../riscv/rvv/autovec/vx_vf/vx_vsub-run-1-i32.c|  2 +-
 .../riscv/rvv/autovec/vx_vf/vx_vsub-run-1-i64.c|  2 +-
 .../riscv/rvv/autovec/vx_vf/vx_vsub-run-1-i8.c |  2 +-
 .../riscv/rvv/autovec/vx_vf/vx_vsub-run-1-u16.c|  2 +-
 .../riscv/rvv/autovec/vx_vf/vx_vsub-run-1-u32.c|  2 +-
 .../riscv/rvv/autovec/vx_vf/vx_vsub-run-1-u64.c|  2 +-
 .../riscv/rvv/autovec/vx_vf/vx_vsub-run-1-u8.c |  2 +-
 17 files changed, 33 insertions(+), 33 deletions(-)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h
index c9ea22800c2b..7e68db92ef86 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h
@@ -6,7 +6,7 @@
 #define TEST_BINARY_DATA(T, NAME)  test_##T##_##NAME##_data
 #define TEST_BINARY_DATA_WRAP(T, NAME) TEST_BINARY_DATA(T, NAME)
 
-int8_t TEST_BINARY_DATA(int8_t, vadd)[][3][N] =
+int8_t TEST_BINARY_DATA(int8_t, add)[][3][N] =
 {
   {
 { 1 },
@@ -55,7 +55,7 @@ int8_t TEST_BINARY_DATA(int8_t, vadd)[][3][N] =
   },
 };
 
-int16_t TEST_BINARY_DATA(int16_t, vadd)[][3][N] =
+int16_t TEST_BINARY_DATA(int16_t, add)[][3][N] =
 {
   {
 { 1 },
@@ -104,7 +104,7 @@ int16_t TEST_BINARY_DATA(int16_t, vadd)[][3][N] =
   },
 };
 
-int32_t TEST_BINARY_DATA(int32_t, vadd)[][3][N] =
+int32_t TEST_BINARY_DATA(int32_t, add)[][3][N] =
 {
   {
 { 1 },
@@ -153,7 +153,7 @@ int32_t TEST_BINARY_DATA(int32_t, vadd)[][3][N] =
   },
 };
 
-int64_t TEST_BINARY_DATA(int64_t, vadd)[][3][N] =
+int64_t TEST_BINARY_DATA(int64_t, add)[][3][N] =
 {
   {
 { 1 },
@@ -202,7 +202,7 @@ int64_t TEST_BINARY_DATA(int64_t, vadd)[][3][N] =
   },
 };
 
-uint8_t TEST_BINARY_DATA(uint8_t, vadd)[][3][N] =
+uint8_t TEST_BINARY_DATA(uint8_t, add)[][3][N] =
 {
   {
 { 1 },
@@ -251,7 +251,7 @@ uint8_t TEST_BINARY_DATA(uint8_t, vadd)[][3][N] =
   },
 };
 
-uint16_t TEST_BINARY_DATA(uint16_t, vadd)[][3][N] =
+uint16_t TEST_BINARY_DATA(uint16_t, add)[][3][N] =
 {
   {
 { 1 },
@@ -300,7 +300,7 @@ uint16_t TEST_BINARY_DATA(uint16_t, vadd)[][3][N] =
   },
 };
 
-uint32_t TEST_BINARY_DATA(uint32_t, vadd)[][3][N] =
+uint32_t TEST_BINARY_DATA(uint32_t, add)[][3][N] =
 {
   {
 { 1 },
@@ -349,7 +349,7 @@ uint32_t TEST_BINAR

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] Partial cherry-pick of 4dd13988c93c24ba3605f4b9cafc97515c34f2ac, just the RISC-V backend bits.

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:84adfa2f4d281c7ae14c52d8b3ee92e7544afdbe

commit 84adfa2f4d281c7ae14c52d8b3ee92e7544afdbe
Author: Jeff Law 
Date:   Fri May 16 11:27:25 2025 -0600

Partial cherry-pick of 4dd13988c93c24ba3605f4b9cafc97515c34f2ac, just the 
RISC-V backend bits.

commit 4dd13988c93c24ba3605f4b9cafc97515c34f2ac
Author: Richard Sandiford 
Date:   Fri May 16 13:24:01 2025 +0100

Automatic replacement of get_insns/end_sequence pairs

This is the result of using a regexp to replace instances of:

   = get_insns ();
  end_sequence ();

with:

   = end_sequence ();

where the indentation is the same for both lines, and where there
might be blank lines inbetween.

Diff:
---
 gcc/config/riscv/riscv-shorten-memrefs.cc |  3 +--
 gcc/config/riscv/riscv-vsetvl.cc  |  6 ++
 gcc/config/riscv/riscv.cc | 10 +++---
 3 files changed, 6 insertions(+), 13 deletions(-)

diff --git a/gcc/config/riscv/riscv-shorten-memrefs.cc 
b/gcc/config/riscv/riscv-shorten-memrefs.cc
index 60f330e656e9..2e3d9f6a2c3c 100644
--- a/gcc/config/riscv/riscv-shorten-memrefs.cc
+++ b/gcc/config/riscv/riscv-shorten-memrefs.cc
@@ -189,8 +189,7 @@ pass_shorten_memrefs::transform (regno_map *m, basic_block 
bb)
}
}
}
-  rtx_insn *seq = get_insns ();
-  end_sequence ();
+  rtx_insn *seq = end_sequence ();
   emit_insn_before (seq, insn);
 }
 }
diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc
index a8c92565541a..4891b6c95e85 100644
--- a/gcc/config/riscv/riscv-vsetvl.cc
+++ b/gcc/config/riscv/riscv-vsetvl.cc
@@ -3419,8 +3419,7 @@ pre_vsetvl::emit_vsetvl ()
}
  start_sequence ();
  insert_vsetvl_insn (EMIT_DIRECT, footer_info);
- rtx_insn *rinsn = get_insns ();
- end_sequence ();
+ rtx_insn *rinsn = end_sequence ();
  default_rtl_profile ();
  insert_insn_on_edge (rinsn, eg);
  need_commit = true;
@@ -3451,8 +3450,7 @@ pre_vsetvl::emit_vsetvl ()
   start_sequence ();
 
   insert_vsetvl_insn (EMIT_DIRECT, info);
-  rtx_insn *rinsn = get_insns ();
-  end_sequence ();
+  rtx_insn *rinsn = end_sequence ();
   default_rtl_profile ();
 
   /* We should not get an abnormal edge here.  */
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index b1d44f7539e5..fd51472dbeaa 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -2856,9 +2856,7 @@ riscv_call_tls_get_addr (rtx sym, rtx result)
 gen_int_mode (RISCV_CC_BASE, SImode)));
   RTL_CONST_CALL_P (insn) = 1;
   use_reg (&CALL_INSN_FUNCTION_USAGE (insn), a0);
-  insn = get_insns ();
-
-  end_sequence ();
+  insn = end_sequence ();
 
   return insn;
 }
@@ -12180,8 +12178,7 @@ riscv_frm_emit_after_bb_end (rtx_insn *cur_insn)
{
  start_sequence ();
  emit_insn (gen_frrmsi (DYNAMIC_FRM_RTL (cfun)));
- rtx_insn *backup_insn = get_insns ();
- end_sequence ();
+ rtx_insn *backup_insn = end_sequence ();
 
  insert_insn_on_edge (backup_insn, eg);
}
@@ -12191,8 +12188,7 @@ riscv_frm_emit_after_bb_end (rtx_insn *cur_insn)
 {
   start_sequence ();
   emit_insn (gen_frrmsi (DYNAMIC_FRM_RTL (cfun)));
-  rtx_insn *backup_insn = get_insns ();
-  end_sequence ();
+  rtx_insn *backup_insn = end_sequence ();
 
   insert_insn_end_basic_block (backup_insn, bb);
 }

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Rename vx_vadd-* testcase to vx-* for all vx combine [NFC]

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:f6ae7c882d926e0b0b0478093c9660bfaaa7ef8e

commit f6ae7c882d926e0b0b0478093c9660bfaaa7ef8e
Author: Pan Li 
Date:   Tue May 13 10:00:35 2025 +0800

RISC-V: Rename vx_vadd-* testcase to vx-* for all vx combine [NFC]

We would like to arrange all vx combine asm check test into
one file for better management.  Thus, rename vx_vadd-* to
vx-*.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-i16.c: Move to...
* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c: ...here.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-i32.c: Move to...
* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c: ...here.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-i64.c: Move to...
* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c: ...here.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-i8.c: Move to...
* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c: ...here.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-u16.c: Move to...
* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c: ...here.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-u32.c: Move to...
* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c: ...here.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-u64.c: Move to...
* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c: ...here.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-u8.c: Move to...
* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c: ...here.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-i16.c: Move to...
* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c: ...here.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-i32.c: Move to...
* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c: ...here.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-i64.c: Move to...
* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c: ...here.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-i8.c: Move to...
* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c: ...here.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-u16.c: Move to...
* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c: ...here.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-u32.c: Move to...
* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c: ...here.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-u64.c: Move to...
* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c: ...here.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-u8.c: Move to...
* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c: ...here.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-i16.c: Move to...
* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c: ...here.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-i32.c: Move to...
* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c: ...here.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-i64.c: Move to...
* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c: ...here.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-i8.c: Move to...
* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c: ...here.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-u16.c: Move to...
* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c: ...here.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-u32.c: Move to...
* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c: ...here.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-u64.c: Move to...
* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c: ...here.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-u8.c: Move to...
* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c: ...here.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-i16.c: Move to...
* gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i16.c: ...here.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-i32.c: Move to...
* gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i32.c: ...here.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-i64.c: Move to...
* gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i64.c: ...here.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-i8.c: Move to...
* gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i8.c: ...here.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-u16.c: Move to...
* gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u16.c: ...here.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-u32.c: Move to...
* gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u32.c: ...here.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-u64.c: Move to...
* gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u64.c: ...here.
* gcc.target/riscv/rvv/a

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Combine vec_duplicate + vsub.vv to vsub.vx on GR2VR cost

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:6785ad35b45c2800262b63b1db05ceaa10dc0e0d

commit 6785ad35b45c2800262b63b1db05ceaa10dc0e0d
Author: Pan Li 
Date:   Sun May 11 16:20:28 2025 +0800

RISC-V: Combine vec_duplicate + vsub.vv to vsub.vx on GR2VR cost

This patch would like to combine the vec_duplicate + vsub.vv to the
vsub.vx.  From example as below code.  The related pattern will depend
on the cost of vec_duplicate from GR2VR.  Then the late-combine will
take action if the cost of GR2VR is zero, and reject the combination
if the GR2VR cost is greater than zero.

Assume we have example code like below, GR2VR cost is 0.

  #define DEF_VX_BINARY(T, OP)\
  void\
  test_vx_binary (T * restrict out, T * restrict in, T x, unsigned n) \
  {   \
for (unsigned i = 0; i < n; i++)  \
  out[i] = in[i] OP x;\
  }

  DEF_VX_BINARY(int32_t, -)

Before this patch:
  10   │ test_binary_vx_sub:
  11   │ beq a3,zero,.L8
  12   │ vsetvli a5,zero,e32,m1,ta,ma // Deleted if GR2VR cost zero
  13   │ vmv.v.x v2,a2// Ditto.
  14   │ sllia3,a3,32
  15   │ srlia3,a3,32
  16   │ .L3:
  17   │ vsetvli a5,a3,e32,m1,ta,ma
  18   │ vle32.v v1,0(a1)
  19   │ sllia4,a5,2
  20   │ sub a3,a3,a5
  21   │ add a1,a1,a4
  22   │ vsub.vv v1,v2,v1
  23   │ vse32.v v1,0(a0)
  24   │ add a0,a0,a4
  25   │ bne a3,zero,.L3

After this patch:
  10   │ test_binary_vx_sub:
  11   │ beq a3,zero,.L8
  12   │ sllia3,a3,32
  13   │ srlia3,a3,32
  14   │ .L3:
  15   │ vsetvli a5,a3,e32,m1,ta,ma
  16   │ vle32.v v1,0(a1)
  17   │ sllia4,a5,2
  18   │ sub a3,a3,a5
  19   │ add a1,a1,a4
  20   │ vsub.vx v1,v1,a2
  21   │ vse32.v v1,0(a0)
  22   │ add a0,a0,a4
  23   │ bne a3,zero,.L3

The below test suites are passed for this patch.
* The rv64gcv fully regression test.

gcc/ChangeLog:

* config/riscv/autovec-opt.md (*_vx_): Add new
pattern to convert vec_duplicate + vsub.vv to vsub.vx.
* config/riscv/riscv.cc (riscv_rtx_costs): Add minus as plus op.
* config/riscv/vector-iterators.md: Add minus to iterator
any_int_binop_no_shift_vx.

Signed-off-by: Pan Li 
(cherry picked from commit 8814d5d50c6d4103f35545ec934be64a82b70d23)

Diff:
---
 gcc/config/riscv/autovec-opt.md  | 17 +
 gcc/config/riscv/riscv.cc|  1 +
 gcc/config/riscv/vector-iterators.md |  2 +-
 3 files changed, 19 insertions(+), 1 deletion(-)

diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md
index 7cf7e8a92ba1..9c6bf06c3a9a 100644
--- a/gcc/config/riscv/autovec-opt.md
+++ b/gcc/config/riscv/autovec-opt.md
@@ -1696,3 +1696,20 @@
   riscv_vector::BINARY_OP, ops);
   }
   [(set_attr "type" "vialu")])
+
+(define_insn_and_split "*_vx_"
+ [(set (match_operand:V_VLSI0 "register_operand")
+   (any_int_binop_no_shift_vx:V_VLSI
+(match_operand:V_VLSI  2 "")
+(vec_duplicate:V_VLSI
+  (match_operand: 1 "register_operand"]
+  "TARGET_VECTOR && can_create_pseudo_p ()"
+  "#"
+  "&& 1"
+  [(const_int 0)]
+  {
+rtx ops[] = {operands[0], operands[2], operands[1]};
+riscv_vector::emit_vlmax_insn (code_for_pred_scalar (, mode),
+  riscv_vector::BINARY_OP, ops);
+  }
+  [(set_attr "type" "vialu")])
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index d996965d0953..b1d44f7539e5 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -3875,6 +3875,7 @@ riscv_rtx_costs (rtx x, machine_mode mode, int 
outer_code, int opno ATTRIBUTE_UN
*total = gr2vr_cost * COSTS_N_INSNS (1);
break;
  case PLUS:
+ case MINUS:
{
  rtx op_0 = XEXP (x, 0);
  rtx op_1 = XEXP (x, 1);
diff --git a/gcc/config/riscv/vector-iterators.md 
b/gcc/config/riscv/vector-iterators.md
index eae33409cb05..23cb940310f2 100644
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -4042,7 +4042,7 @@
 ])
 
 (define_code_iterator any_int_binop_no_shift_vx [
-  plus
+  plus minus
 ])
 
 (define_code_iterator any_int_unop [neg not])

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vsub.vv combine case 1 with GR2VR cost 2

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:76ecd7693326497809e517d0f19f06f59cd2aec2

commit 76ecd7693326497809e517d0f19f06f59cd2aec2
Author: Pan Li 
Date:   Tue May 13 22:47:13 2025 +0800

RISC-V: Add test for vec_duplicate + vsub.vv combine case 1 with GR2VR cost 
2

Add asm dump check test for vec_duplicate + vsub.vv combine to vsub.vx.

The below test suites are passed for this patch.
* The rv64gcv fully regression test.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c: Add test cases
for vsub vx combine case 1 with GR2VR cost 2.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i32.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i64.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u8.c: Ditto.

Signed-off-by: Pan Li 
(cherry picked from commit a484b523e3e4d78c810bb9a70a86a8fa567378b7)

Diff:
---
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i32.c | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i64.c | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c  | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u16.c | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u32.c | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u64.c | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u8.c  | 2 ++
 8 files changed, 16 insertions(+)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c
index 78f630f9e2bf..0e5ad322aa5f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c
@@ -4,5 +4,7 @@
 #include "vx_binary.h"
 
 DEF_VX_BINARY_CASE_1(int16_t, +, add, VX_BINARY_BODY_X8)
+DEF_VX_BINARY_CASE_1(int16_t, -, sub, VX_BINARY_BODY_X8)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
+/* { dg-final { scan-assembler {vsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i32.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i32.c
index e7ea3011688d..b46b74a0887f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i32.c
@@ -4,5 +4,7 @@
 #include "vx_binary.h"
 
 DEF_VX_BINARY_CASE_1(int32_t, +, add, VX_BINARY_BODY_X4)
+DEF_VX_BINARY_CASE_1(int32_t, -, sub, VX_BINARY_BODY_X4)
 
 /* { dg-final { scan-assembler {vadd.vx} } } */
+/* { dg-final { scan-assembler {vsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i64.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i64.c
index 699c70fc2896..13e64d7752b6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i64.c
@@ -4,5 +4,7 @@
 #include "vx_binary.h"
 
 DEF_VX_BINARY_CASE_1(int64_t, +, add, VX_BINARY_BODY)
+DEF_VX_BINARY_CASE_1(int64_t, -, sub, VX_BINARY_BODY)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
+/* { dg-final { scan-assembler-not {vsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c
index a8218aa14cee..1f58daaad38f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c
@@ -4,5 +4,7 @@
 #include "vx_binary.h"
 
 DEF_VX_BINARY_CASE_1(int8_t, +, add, VX_BINARY_BODY_X16)
+DEF_VX_BINARY_CASE_1(int8_t, -, sub, VX_BINARY_BODY_X16)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
+/* { dg-final { scan-assembler {vsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u16.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u16.c
index 21fc913cdc14..2249cb242fe8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u16.c
@@ -5,5 +5,7 @@
 #include "vx_binary.h"
 
 DEF_VX_BINARY_CASE_1(uint16_t, +, add, VX_BINARY_BODY_X8)
+DEF_VX_BINARY_CASE_1(uint16_t, -, sub, VX_BINARY_BODY_X8)
 
 /* { dg-final { scan-assembler {vadd.vx} } } */
+/* { dg-final { scan-assembler {vsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u32.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u32.c
index 11cce3a95ac7..d768fc72141c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u32.c
@@ -4,5 +4,7 @@
 #include "vx_binary.h"
 
 DEF_VX_BINARY_CASE_1(uint32_t, +, ad

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vsub.vv combine case 1 with GR2VR cost 1

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:13a6e9fcd051f3c3435b40c328ce7d6ddadcff0d

commit 13a6e9fcd051f3c3435b40c328ce7d6ddadcff0d
Author: Pan Li 
Date:   Tue May 13 22:38:57 2025 +0800

RISC-V: Add test for vec_duplicate + vsub.vv combine case 1 with GR2VR cost 
1

Add asm dump check test for vec_duplicate + vsub.vv combine to vsub.vx.

The below test suites are passed for this patch.
* The rv64gcv fully regression test.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i16.c: Add test cases
for vsub vx combine case 1 with GR2VR cost 1.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i32.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i64.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i8.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u8.c: Ditto.

Signed-off-by: Pan Li 
(cherry picked from commit 5f523f6255cc48643adab431839557dc3d73d70f)

Diff:
---
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i16.c | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i32.c | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i64.c | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i8.c  | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u16.c | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u32.c | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u64.c | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u8.c  | 2 ++
 8 files changed, 16 insertions(+)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i16.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i16.c
index 7f40b4b86f7c..05742671003f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i16.c
@@ -4,5 +4,7 @@
 #include "vx_binary.h"
 
 DEF_VX_BINARY_CASE_1(int16_t, +, add, VX_BINARY_BODY_X8)
+DEF_VX_BINARY_CASE_1(int16_t, -, sub, VX_BINARY_BODY_X8)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
+/* { dg-final { scan-assembler {vsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i32.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i32.c
index c8d23c7c93fe..f990e34355e8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i32.c
@@ -4,5 +4,7 @@
 #include "vx_binary.h"
 
 DEF_VX_BINARY_CASE_1(int32_t, +, add, VX_BINARY_BODY_X4)
+DEF_VX_BINARY_CASE_1(int32_t, -, sub, VX_BINARY_BODY_X4)
 
 /* { dg-final { scan-assembler {vadd.vx} } } */
+/* { dg-final { scan-assembler {vsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i64.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i64.c
index 219293b8c97d..3b189e31c6f4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i64.c
@@ -4,5 +4,7 @@
 #include "vx_binary.h"
 
 DEF_VX_BINARY_CASE_1(int64_t, +, add, VX_BINARY_BODY)
+DEF_VX_BINARY_CASE_1(int64_t, -, sub, VX_BINARY_BODY)
 
 /* { dg-final { scan-assembler {vadd.vx} } } */
+/* { dg-final { scan-assembler {vsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i8.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i8.c
index 00944475cd10..3590b88d7615 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i8.c
@@ -4,5 +4,7 @@
 #include "vx_binary.h"
 
 DEF_VX_BINARY_CASE_1(int8_t, +, add, VX_BINARY_BODY_X16)
+DEF_VX_BINARY_CASE_1(int8_t, -, sub, VX_BINARY_BODY_X16)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
+/* { dg-final { scan-assembler {vsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u16.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u16.c
index 723ac6132d17..994c7f24652a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u16.c
@@ -4,5 +4,7 @@
 #include "vx_binary.h"
 
 DEF_VX_BINARY_CASE_1(uint16_t, +, add, VX_BINARY_BODY_X8)
+DEF_VX_BINARY_CASE_1(uint16_t, -, sub, VX_BINARY_BODY_X8)
 
 /* { dg-final { scan-assembler {vadd.vx} } } */
+/* { dg-final { scan-assembler {vsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u32.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u32.c
index 08d1467b5516..2aceab5ff51d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u32.c
@@ -4,5 +4,7 @@
 #include "vx_binary.h"
 
 DEF_VX_BINARY_CASE_1(uint32_t, +, add, VX_BI

[gcc(refs/users/mikael/heads/refactor_descriptor_v05)] Correction régression allocate_with_source_11

[Mikael Morin via Gcc-cvs]

https://gcc.gnu.org/g:551a0e231b710ddf692cf8d7ce3f0c0845d2c510

commit 551a0e231b710ddf692cf8d7ce3f0c0845d2c510
Author: Mikael Morin 
Date:   Sun May 18 15:37:02 2025 +0200

Correction régression allocate_with_source_11

Diff:
---
 gcc/fortran/trans-expr.cc | 21 +
 1 file changed, 17 insertions(+), 4 deletions(-)

diff --git a/gcc/fortran/trans-expr.cc b/gcc/fortran/trans-expr.cc
index 138140382253..c8fcc9c5ed69 100644
--- a/gcc/fortran/trans-expr.cc
+++ b/gcc/fortran/trans-expr.cc
@@ -1318,10 +1318,23 @@ gfc_conv_class_to_class (gfc_se *parmse, gfc_expr *e, 
gfc_typespec class_ts,
 }
   else
 {
-  if (TREE_TYPE (parmse->expr) != TREE_TYPE (ctree))
-   parmse->expr = fold_build1_loc (input_location, VIEW_CONVERT_EXPR,
-   TREE_TYPE (ctree), parmse->expr);
-  gfc_add_modify (&block, ctree, parmse->expr);
+  tree val = parmse->expr;
+
+  if (TREE_CODE (TREE_TYPE (val)) == POINTER_TYPE)
+   val = build_fold_indirect_ref_loc (input_location, val);
+
+  if (GFC_CLASS_TYPE_P (TREE_TYPE (val)))
+   val = gfc_class_data_get (val);
+
+  if (TREE_CODE (TREE_TYPE (ctree)) == POINTER_TYPE
+ && TREE_CODE (TREE_TYPE (val)) != POINTER_TYPE)
+   val = gfc_build_addr_expr (NULL_TREE, val);
+
+  if (TREE_TYPE (val) != TREE_TYPE (ctree))
+   val = fold_build1_loc (input_location, VIEW_CONVERT_EXPR,
+  TREE_TYPE (ctree), val);
+
+  gfc_add_modify (&block, ctree, val);
 }
 
   /* Return the data component, except in the case of scalarized array

[gcc(refs/users/mikael/heads/refactor_descriptor_v05)] Correction partielle allocate_with_source_11

[Mikael Morin via Gcc-cvs]

https://gcc.gnu.org/g:051482b5e45076f1de061546b5ddd1ce251fc939

commit 051482b5e45076f1de061546b5ddd1ce251fc939
Author: Mikael Morin 
Date:   Sun May 18 15:02:49 2025 +0200

Correction partielle allocate_with_source_11

Diff:
---
 gcc/fortran/trans-expr.cc | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/gcc/fortran/trans-expr.cc b/gcc/fortran/trans-expr.cc
index 8b4ad9978755..138140382253 100644
--- a/gcc/fortran/trans-expr.cc
+++ b/gcc/fortran/trans-expr.cc
@@ -1357,6 +1357,10 @@ gfc_conv_class_to_class (gfc_se *parmse, gfc_expr *e, 
gfc_typespec class_ts,
   if (gfc_is_class_array_function (e)
   && parmse->class_vptr != NULL_TREE)
 tmp = parmse->class_vptr;
+  else if (parmse->class_container != NULL_TREE)
+/* Don't redundantly evaluate the expression if the required information
+   is already available.  */
+tmp = parmse->class_container;
   else if (class_ref == NULL
   && e->symtree && e->symtree->n.sym->ts.type == BT_CLASS)
 {
@@ -1370,10 +1374,6 @@ gfc_conv_class_to_class (gfc_se *parmse, gfc_expr *e, 
gfc_typespec class_ts,
 
   slen = build_zero_cst (size_type_node);
 }
-  else if (parmse->class_container != NULL_TREE)
-/* Don't redundantly evaluate the expression if the required information
-   is already available.  */
-tmp = parmse->class_container;
   else
 {
   /* Remove everything after the last class reference, convert the

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [RISC-V] Fix ICE due to bogus use of gen_rtvec

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:5159c19cb2a8375fe73e7ab90b118fa55a5e0bbd

commit 5159c19cb2a8375fe73e7ab90b118fa55a5e0bbd
Author: Jeff Law 
Date:   Sat May 17 09:37:01 2025 -0600

[RISC-V] Fix ICE due to bogus use of gen_rtvec

Found this while setting up the risc-v coordination branch off of gcc-15.  
Not
sure why I didn't use rtvec_alloc directly here since we're going to 
initialize
the whole vector ourselves.  Using gen_rtvec was just wrong as it's walking
down a non-existent varargs list.  Under the "right" circumstances it can 
walk
off a page and fault.

This was seen with a test already in the testsuite (I forget which test), 
so no
new regression test.

Tested in my tester and verified the failure on the coordination branch is
resolved a well.  Waiting on pre-commit CI to render a verdict.

gcc/
* config/riscv/riscv-vect-permconst.cc 
(vector_permconst:process_bb):
Use rtvec_alloc, not gen_rtvec since we don't want/need to 
initialize
the vector.

(cherry picked from commit 7ed37d5ea48f6a51c81f73f35a64ca00c0325fd7)

Diff:
---
 gcc/config/riscv/riscv-vect-permconst.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/config/riscv/riscv-vect-permconst.cc 
b/gcc/config/riscv/riscv-vect-permconst.cc
index 8e13cf8d5587..087f26aea8ae 100644
--- a/gcc/config/riscv/riscv-vect-permconst.cc
+++ b/gcc/config/riscv/riscv-vect-permconst.cc
@@ -227,7 +227,7 @@ vector_permconst::process_bb (basic_block bb)
 normalize it to zero.
 
 XXX This violates structure sharing conventions.  */
-  rtvec_def *nvec = gen_rtvec (CONST_VECTOR_NUNITS (cvec).to_constant ());
+  rtvec_def *nvec = rtvec_alloc (CONST_VECTOR_NUNITS (cvec).to_constant 
());
 
   for (i = 0; i < CONST_VECTOR_NUNITS (cvec).to_constant (); i++)
nvec->elem[i] = GEN_INT (INTVAL (CONST_VECTOR_ELT (cvec, i)) - bias);

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Avoid scalar unsigned SAT_ADD test data duplication

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:6e73320a5f1b2af6c099644e8f7cbdc6f11fec58

commit 6e73320a5f1b2af6c099644e8f7cbdc6f11fec58
Author: Pan Li 
Date:   Fri May 16 15:34:51 2025 +0800

RISC-V: Avoid scalar unsigned SAT_ADD test data duplication

Some of the previous scalar unsigned SAT_ADD test data are
duplicated in different test files.  This patch would like to
move them into a shared header file, to avoid the test data
duplication.

The below test suites are passed for this patch series.
* The rv64gcv fully regression test.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/sat/sat_arith.h: Add more helper macros.
* gcc.target/riscv/sat/sat_arith_data.h: Add the test data
for scalar unsigned SAT_ADD.
* gcc.target/riscv/sat/sat_u_add-run-1-u16.c: Leverage the test
data from the shared header file.
* gcc.target/riscv/sat/sat_u_add-run-1-u32.c: Ditto
* gcc.target/riscv/sat/sat_u_add-run-1-u64.c: Ditto
* gcc.target/riscv/sat/sat_u_add-run-1-u8.c: Ditto
* gcc.target/riscv/sat/sat_u_add-run-2-u16.c: Ditto
* gcc.target/riscv/sat/sat_u_add-run-2-u32.c: Ditto
* gcc.target/riscv/sat/sat_u_add-run-2-u64.c: Ditto
* gcc.target/riscv/sat/sat_u_add-run-2-u8.c: Ditto
* gcc.target/riscv/sat/sat_u_add-run-3-u16.c: Ditto
* gcc.target/riscv/sat/sat_u_add-run-3-u32.c: Ditto
* gcc.target/riscv/sat/sat_u_add-run-3-u64.c: Ditto
* gcc.target/riscv/sat/sat_u_add-run-3-u8.c: Ditto
* gcc.target/riscv/sat/sat_u_add-run-4-u16.c: Ditto
* gcc.target/riscv/sat/sat_u_add-run-4-u32.c: Ditto
* gcc.target/riscv/sat/sat_u_add-run-4-u64.c: Ditto
* gcc.target/riscv/sat/sat_u_add-run-4-u8.c: Ditto
* gcc.target/riscv/sat/sat_u_add-run-5-u16.c: Ditto
* gcc.target/riscv/sat/sat_u_add-run-5-u32.c: Ditto
* gcc.target/riscv/sat/sat_u_add-run-5-u64.c: Ditto
* gcc.target/riscv/sat/sat_u_add-run-5-u8.c: Ditto
* gcc.target/riscv/sat/sat_u_add-run-6-u16.c: Ditto
* gcc.target/riscv/sat/sat_u_add-run-6-u32.c: Ditto
* gcc.target/riscv/sat/sat_u_add-run-6-u64.c: Ditto
* gcc.target/riscv/sat/sat_u_add-run-6-u8.c: Ditto
* gcc.target/riscv/sat/sat_u_add-run-7-u16-from-u32.c: Ditto
* gcc.target/riscv/sat/sat_u_add-run-7-u16-from-u64.c: Ditto
* gcc.target/riscv/sat/sat_u_add-run-7-u32-from-u64.c: Ditto
* gcc.target/riscv/sat/sat_u_add-run-7-u8-from-u16.c: Ditto
* gcc.target/riscv/sat/sat_u_add-run-7-u8-from-u32.c: Ditto
* gcc.target/riscv/sat/sat_u_add-run-7-u8-from-u64.c: Ditto

Signed-off-by: Pan Li 
(cherry picked from commit 83477c3f6650429a7cdcb1b6da950c421aa2f77d)

Diff:
---
 gcc/testsuite/gcc.target/riscv/sat/sat_arith.h | 12 +
 .../gcc.target/riscv/sat/sat_arith_data.h  | 61 ++
 .../gcc.target/riscv/sat/sat_u_add-run-1-u16.c | 24 +++--
 .../gcc.target/riscv/sat/sat_u_add-run-1-u32.c | 24 +++--
 .../gcc.target/riscv/sat/sat_u_add-run-1-u64.c | 24 +++--
 .../gcc.target/riscv/sat/sat_u_add-run-1-u8.c  | 24 +++--
 .../gcc.target/riscv/sat/sat_u_add-run-2-u16.c | 24 +++--
 .../gcc.target/riscv/sat/sat_u_add-run-2-u32.c | 24 +++--
 .../gcc.target/riscv/sat/sat_u_add-run-2-u64.c | 24 +++--
 .../gcc.target/riscv/sat/sat_u_add-run-2-u8.c  | 24 +++--
 .../gcc.target/riscv/sat/sat_u_add-run-3-u16.c | 24 +++--
 .../gcc.target/riscv/sat/sat_u_add-run-3-u32.c | 24 +++--
 .../gcc.target/riscv/sat/sat_u_add-run-3-u64.c | 24 +++--
 .../gcc.target/riscv/sat/sat_u_add-run-3-u8.c  | 24 +++--
 .../gcc.target/riscv/sat/sat_u_add-run-4-u16.c | 24 +++--
 .../gcc.target/riscv/sat/sat_u_add-run-4-u32.c | 24 +++--
 .../gcc.target/riscv/sat/sat_u_add-run-4-u64.c | 24 +++--
 .../gcc.target/riscv/sat/sat_u_add-run-4-u8.c  | 24 +++--
 .../gcc.target/riscv/sat/sat_u_add-run-5-u16.c | 24 +++--
 .../gcc.target/riscv/sat/sat_u_add-run-5-u32.c | 24 +++--
 .../gcc.target/riscv/sat/sat_u_add-run-5-u64.c | 24 +++--
 .../gcc.target/riscv/sat/sat_u_add-run-5-u8.c  | 24 +++--
 .../gcc.target/riscv/sat/sat_u_add-run-6-u16.c | 24 +++--
 .../gcc.target/riscv/sat/sat_u_add-run-6-u32.c | 24 +++--
 .../gcc.target/riscv/sat/sat_u_add-run-6-u64.c | 24 +++--
 .../gcc.target/riscv/sat/sat_u_add-run-6-u8.c  | 24 +++--
 .../riscv/sat/sat_u_add-run-7-u16-from-u32.c   | 26 +++--
 .../riscv/sat/sat_u_add-run-7-u16-from-u64.c   | 26 +++--
 .../riscv/sat/sat_u_add-run-7-u32-from-u64.c   | 26 +++--
 .../riscv/sat/sat_u_add-run-7-u8-from-u16.c| 26 +++--
 .../riscv/sat/sat_u_add-run-7-u8-from-u32.c| 26 +++-

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [RISC-V] Avoid setting output object more than once in IOR/XOR synthesis

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:8010f9802a62912ee149ff44b07bd4cf80ec44fc

commit 8010f9802a62912ee149ff44b07bd4cf80ec44fc
Author: Jeff Law 
Date:   Sat May 17 07:16:50 2025 -0600

[RISC-V] Avoid setting output object more than once in IOR/XOR synthesis

While evaluating Shreya's logical AND synthesis work on spec2017 I ran into 
a
code quality regression where combine was failing to eliminate a redundant 
sign
extension.

I had a hunch the problem would be with the multiple sets of the same pseudo
register in the AND synthesis path.  I was right that the problem was 
multiple
sets of the same pseudo, but it was actually some of the splitters in the
RISC-V backend that were the culprit.  Those multiple sets caused the sign 
bit
tracking code to need to make conservative assumptions thus resulting in
failure to eliminate the unnecessary sign extension.

So before we start moving on the logical AND patch we're going to do some
cleanups.

There's multiple moving parts in play.  For example, we have splitters 
which do
multiple sets of the output register.  Fixing some of those independently 
would
result in a code quality regression.  Instead they need some adjustments to 
or
removal of mvconst_internal.  Of course getting rid of mvconst_internal will
trigger all kinds of code quality regressions right now which ultimately 
lead
back to the need to revamp the logical AND expander.  Point being we've got
some circular dependencies and breaking them may result in short term code
quality regressions.  I'll obviously try to avoid those as much as possible.

So to start the process this patch adjusts the recently added XOR/IOR 
synthesis
to avoid re-using the destination register.  While the reuse was clearly 
safe
from a semantic standpoint, various parts of the compiler can do a better 
job
for pseudos that are only set once.

Given this synthesis path should only be active during initial RTL 
generation,
we can create new pseudos at will, so we create a new one for each insn.  At
the end of the sequence we copy from the last set into the final 
destination.

This has various trivial impacts on the code generation, but the resulting 
code
looks no better or worse to me across spec2017.

This has been tested in my tester and is currently bootstrapping on my BPI.
Waiting on data from the pre-commit tester before moving forward...

gcc/
* config/riscv/riscv.cc (synthesize_ior_xor): Avoid writing
operands[0] more than once, use new pseudos instead.

(cherry picked from commit 6ecda1972a1e19d23e6dd238c7509c25acf5c914)

Diff:
---
 gcc/config/riscv/riscv.cc | 52 ---
 1 file changed, 36 insertions(+), 16 deletions(-)

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index b2794252291e..8d84bee46882 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -14267,17 +14267,21 @@ synthesize_ior_xor (rtx_code code, rtx operands[3])
 {
   /* Pre-flipping bits we want to preserve.  */
   rtx input = operands[1];
+  rtx output = NULL_RTX;
   ival = ~INTVAL (operands[2]);
   while (ival)
{
  HOST_WIDE_INT tmpval = HOST_WIDE_INT_UC (1) << ctz_hwi (ival);
  rtx x = GEN_INT (tmpval);
  x = gen_rtx_XOR (word_mode, input, x);
- emit_insn (gen_rtx_SET (operands[0], x));
- input = operands[0];
+ output = gen_reg_rtx (word_mode);
+ emit_insn (gen_rtx_SET (output, x));
+ input = output;
  ival &= ~tmpval;
}
 
+  gcc_assert (output);
+
   /* Now flip all the bits, which restores the bits we were
 preserving.  */
   rtx x = gen_rtx_NOT (word_mode, input);
@@ -14300,23 +14304,29 @@ synthesize_ior_xor (rtx_code code, rtx operands[3])
   int msb = BITS_PER_WORD - 1 - clz_hwi (ival);
   if (msb - lsb + 1 <= 11)
{
+ rtx output = gen_reg_rtx (word_mode);
+ rtx input = operands[1];
+
  /* Rotate the source right by LSB bits.  */
  rtx x = GEN_INT (lsb);
- x = gen_rtx_ROTATERT (word_mode, operands[1], x);
- emit_insn (gen_rtx_SET (operands[0], x));
+ x = gen_rtx_ROTATERT (word_mode, input, x);
+ emit_insn (gen_rtx_SET (output, x));
+ input = output;
 
  /* Shift the constant right by LSB bits.  */
  x = GEN_INT (ival >> lsb);
 
  /* Perform the IOR/XOR operation.  */
- x = gen_rtx_fmt_ee (code, word_mode, operands[0], x);
- emit_insn (gen_rtx_SET (operands[0], x));
+ x = gen_rtx_fmt_ee (code, word_mode, input, x);
+ output = gen_reg_rtx (word_mode);
+ emit_insn (gen_rtx_SET (output, x));
+ input = output;
 
  /* And rotate left to put everything back in place, we don't
 have rotate

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vsub.vv combine case 0 with GR2VR cost 15

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:04f07eebc1b0717952fe683e84243710a8f87242

commit 04f07eebc1b0717952fe683e84243710a8f87242
Author: Pan Li 
Date:   Sun May 11 16:32:51 2025 +0800

RISC-V: Add test for vec_duplicate + vsub.vv combine case 0 with GR2VR cost 
15

Add asm dump check test for vec_duplicate + vsub.vv combine to vsub.vx.

The below test suites are passed for this patch.
* The rv64gcv fully regression test.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c: Add test cases
for vsub vx combine with GR2VR cost 15.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c: Ditto.

Signed-off-by: Pan Li 
(cherry picked from commit f8cdcca76f28fae932079ebdf208b7586282369c)

Diff:
---
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c  | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c  | 2 ++
 8 files changed, 16 insertions(+)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c
index 7acd86972477..aa21e10130bf 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c
@@ -4,5 +4,7 @@
 #include "vx_binary.h"
 
 DEF_VX_BINARY_CASE_0(int16_t, +, add)
+DEF_VX_BINARY_CASE_0(int16_t, -, sub)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
+/* { dg-final { scan-assembler-not {vsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c
index 8476c1bd3b81..7c374694321b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c
@@ -4,5 +4,7 @@
 #include "vx_binary.h"
 
 DEF_VX_BINARY_CASE_0(int32_t, +, add)
+DEF_VX_BINARY_CASE_0(int32_t, -, sub)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
+/* { dg-final { scan-assembler-not {vsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c
index 37ee24f3e1a2..3efb0d7e92ef 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c
@@ -4,5 +4,7 @@
 #include "vx_binary.h"
 
 DEF_VX_BINARY_CASE_0(int64_t, +, add)
+DEF_VX_BINARY_CASE_0(int64_t, -, sub)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
+/* { dg-final { scan-assembler-not {vsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c
index 678c994a01c1..d823ed9cc9a2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c
@@ -4,5 +4,7 @@
 #include "vx_binary.h"
 
 DEF_VX_BINARY_CASE_0(int8_t, +, add)
+DEF_VX_BINARY_CASE_0(int8_t, -, sub)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
+/* { dg-final { scan-assembler-not {vsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c
index 30be625343db..1ab09c8d78ea 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c
@@ -4,5 +4,7 @@
 #include "vx_binary.h"
 
 DEF_VX_BINARY_CASE_0(uint16_t, +, add)
+DEF_VX_BINARY_CASE_0(uint16_t, -, sub)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
+/* { dg-final { scan-assembler-not {vsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c
index e32d16bf59e3..9247db701544 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c
@@ -4,5 +4,7 @@
 #include "vx_binary.h"
 
 DEF_VX_BINARY_CASE_0(uint32_t, +, add)
+DEF_VX_BINARY_CASE_0(uint32_t, -, sub)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
+/* { dg-final { scan-assembler-not {vsub.vx} } } */
diff --git a/gcc

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Since the loop increment i++ is unreachable, the loop body will never execute more than once

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:99d801c0191641da7b313517454cf8f6b9d39415

commit 99d801c0191641da7b313517454cf8f6b9d39415
Author: Jin Ma 
Date:   Fri May 16 15:27:13 2025 +0800

RISC-V: Since the loop increment i++ is unreachable, the loop body will 
never execute more than once

Reported-by: huangcunjian 

gcc/ChangeLog:

* config/riscv/riscv.cc (riscv_gpr_save_operation_p): Remove
break and fixbug for elt index.

(cherry picked from commit 55cfd1c8fa2ad2c5d91eadd14daa35f695779a2b)

Diff:
---
 gcc/config/riscv/riscv.cc | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index fd51472dbeaa..b2794252291e 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -11580,11 +11580,10 @@ riscv_gpr_save_operation_p (rtx op)
  /* Two CLOBBER and USEs, must check the order.  */
  unsigned expect_code = i < 3 ? CLOBBER : USE;
  if (GET_CODE (elt) != expect_code
- || !REG_P (XEXP (elt, 1))
- || (REGNO (XEXP (elt, 1)) != gpr_save_reg_order[i]))
+ || !REG_P (XEXP (elt, 0))
+ || (REGNO (XEXP (elt, 0)) != gpr_save_reg_order[i]))
return false;
}
-   break;
 }
   return true;
 }

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [V2][RISC-V] Synthesize more efficient IOR/XOR sequences

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:7866e62f125b108b76c994715fc6078618296d4c

commit 7866e62f125b108b76c994715fc6078618296d4c
Author: Shreya Munnangi 
Date:   Sat May 10 07:18:33 2025 -0600

[V2][RISC-V] Synthesize more efficient IOR/XOR sequences

So mvconst_internal's primary benefit is in constant synthesis not impacting
the combine budget in terms of the number of instructions it is willing to
combine together at any given time.  The downside is mvconst_internal breaks
combine's toplevel costing model and as a result many other patterns have 
to be
implemented as define_insn_and_splits rather than the often more natural
define_splits.

This primarily impacts logical operations where we want to see the constant
operand and potentially simplify the logical with other nearby logicals or
shifts.

We can reduce our reliance on mvconst_internal and generate better code for
various cases by generating better initial code for logical operations.

So let's assume we have a inclusive-or of a register with a nontrivial
constant.  Right now we will load the nontrivial constant into a new pseudo
(using multiple instructions), then emit a two register source ior 
operation.

For some cases we can just generate the code we want at expansion time.
Concretely let's take this testcase:

> unsigned long foo(unsigned long src) { return src | 0x8807; }

Right now we generate this code:

> li  a5,-15
> sllia5,a5,59
> addia5,a5,7
> or  a0,a0,a5

The first three instructions are synthesizing the constant.  The last
instruction performs the desired operation.  But we can do better:

> ori a0,a0,7
> bseti   a0,a0,59
> bseti   a0,a0,63

Notice how we never even bother to synthesize the constant.

IOR/XOR are pretty simple and this patch focuses exclusively on those. We 
use
[x]ori to set whatever low 11 bits we need, then bset/binv for a small 
number
of higher bits.  We use the cost of constant synthesis as our budget.

We also support a couple special cases.  First, we might be able to rotate 
the
source value such that all the bits we want to manipulate are in the low 11
bits.  So we rotate the source, manipulate the bits, then rotate things 
back to
where they belong.  I didn't see this trigger in spec, but I did trivially 
find
a testcase where it was likely faster.

Second, we can have cases where we want to invert most of the bits, but a 
small
number are supposed to be preserved.  We can pre-flip the bits we want to
preserve with binv, then invert the whole register with not (which puts the
bits to be preserved back in their original state).

I suspect there are likely a few more cases that could be improved, but the
patch should stand on its own now and getting it out of the way allows us to
focus on logical AND which is far tougher, but also more important in the 
task
of removing mvconst_internal.

As we're not removing mvconst_internal yet, this patch is mostly a nop. I 
did
look at spec before/after and didn't see anything particular interesting.  I
also temporarily removed mvconst_internal and looked at spec before/after to
hopefully ensure we weren't missing anything obvious in the XOR/IOR cases.
Obviously that latter test showed all kinds of regressions with AND.

We're still working through implementation details on the AND case and
determining what bridge patterns we're going to need to ensure we don't
regress.   But this XOR/IOR patch is in good enough shape that it can go
forward now.

Naturally this has been run through my tester (bootstrap & regression test 
is
in flight, but won't finish for many more hours).  Obviously I'm quite
interested in anything spit out by the pre-commit CI system.

gcc/

* config/riscv/iterators.md (OPTAB): New iterator.
* config/riscv/predicates.md (arith_or_zbs_operand): Remove.
(reg_or_const_int_operand): New predicate.
* config/riscv/riscv-protos.h (synthesize_ior_xor): Prototype.
* config/riscv/riscv.cc (synthesize_ior_xor): New function.
* config/riscv/riscv.md (ior/xor expander): Use synthesize_ior_xor.

gcc/testsuite/

* gcc.target/riscv/ior-synthesis-1.c: New test.
* gcc.target/riscv/ior-synthesis-2.c: New test.
* gcc.target/riscv/xor-synthesis-1.c: New test.
* gcc.target/riscv/xor-synthesis-2.c: New test.
* gcc.target/riscv/xor-synthesis-3.c: New test.

Co-authored-by: Jeff Law  

(cherry picked from commit 36daa0da95fba18d0d4eb4e10fa07ac3b76fa426)

Diff:
---
 gcc/config/riscv/iterators.md|   3 +
 gcc/co

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vsub.vv combine case 1 with GR2VR cost 0

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:1a93ea8c5c40ea8d1772c2251e134b4efe8e082f

commit 1a93ea8c5c40ea8d1772c2251e134b4efe8e082f
Author: Pan Li 
Date:   Tue May 13 22:32:03 2025 +0800

RISC-V: Add test for vec_duplicate + vsub.vv combine case 1 with GR2VR cost 0

Add asm dump check test for vec_duplicate + vsub.vv combine to vsub.vx.

The below test suites are passed for this patch.
* The rv64gcv fully regression test.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i16.c: Add test cases
for vsub vx combine case 1 with GR2VR cost 0.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i32.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i64.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i8.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u8.c: Ditto.

Signed-off-by: Pan Li 
(cherry picked from commit 621cb3dc9996a160e3e65bce4a8e61da26caafa7)

Diff:
---
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i16.c | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i32.c | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i64.c | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i8.c  | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u16.c | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u32.c | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u64.c | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u8.c  | 2 ++
 8 files changed, 16 insertions(+)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i16.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i16.c
index deae3765318b..0ae0566fcfb2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i16.c
@@ -4,5 +4,7 @@
 #include "vx_binary.h"
 
 DEF_VX_BINARY_CASE_1(int16_t, +, add, VX_BINARY_BODY_X16)
+DEF_VX_BINARY_CASE_1(int16_t, -, sub, VX_BINARY_BODY_X16)
 
 /* { dg-final { scan-assembler {vadd.vx} } } */
+/* { dg-final { scan-assembler {vsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i32.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i32.c
index 05021156391d..86085d12cf77 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i32.c
@@ -4,5 +4,7 @@
 #include "vx_binary.h"
 
 DEF_VX_BINARY_CASE_1(int32_t, +, add, VX_BINARY_BODY_X4)
+DEF_VX_BINARY_CASE_1(int32_t, -, sub, VX_BINARY_BODY_X4)
 
 /* { dg-final { scan-assembler {vadd.vx} } } */
+/* { dg-final { scan-assembler {vsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i64.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i64.c
index 27796b55e58b..9d89db3d489f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i64.c
@@ -4,5 +4,7 @@
 #include "vx_binary.h"
 
 DEF_VX_BINARY_CASE_1(int64_t, +, add, VX_BINARY_BODY)
+DEF_VX_BINARY_CASE_1(int64_t, -, sub, VX_BINARY_BODY)
 
 /* { dg-final { scan-assembler {vadd.vx} } } */
+/* { dg-final { scan-assembler {vsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i8.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i8.c
index d43a680be02a..40b02db8a013 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i8.c
@@ -4,5 +4,7 @@
 #include "vx_binary.h"
 
 DEF_VX_BINARY_CASE_1(int8_t, +, add, VX_BINARY_BODY_X16)
+DEF_VX_BINARY_CASE_1(int8_t, -, sub, VX_BINARY_BODY_X16)
 
 /* { dg-final { scan-assembler {vadd.vx} } } */
+/* { dg-final { scan-assembler {vsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u16.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u16.c
index 0f8baf912afb..ca2010685d85 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u16.c
@@ -4,5 +4,7 @@
 #include "vx_binary.h"
 
 DEF_VX_BINARY_CASE_1(uint16_t, +, add, VX_BINARY_BODY_X16)
+DEF_VX_BINARY_CASE_1(uint16_t, -, sub, VX_BINARY_BODY_X16)
 
 /* { dg-final { scan-assembler {vadd.vx} } } */
+/* { dg-final { scan-assembler {vsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u32.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u32.c
index 017cf9055b6b..6e2456c41e47 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u32.c
@@ -4,5 +4,7 @@
 #include "vx_binary.h"
 
 DEF_VX_BINARY_CASE_1(uint32_t, +, add, VX_BINARY_

[gcc r16-717] Partially lift restriction from loc_list_from_tree_1

[Eric Botcazou via Gcc-cvs]

https://gcc.gnu.org/g:809b46d2ccc9a4a0ab3a5b6015cbe9738b74b0a5

commit r16-717-g809b46d2ccc9a4a0ab3a5b6015cbe9738b74b0a5
Author: Eric Botcazou 
Date:   Sun May 18 19:10:26 2025 +0200

Partially lift restriction from loc_list_from_tree_1

The function accepts all handled_component_p expressions and decodes them by
means of get_inner_reference as expected, but bails out on bitfields:

/* TODO: We can extract value of the small expression via shifting
   even for nonzero bitpos.  */
if (list_ret == 0)
  return 0;
if (!multiple_p (bitpos, BITS_PER_UNIT, &bytepos)
|| !multiple_p (bitsize, BITS_PER_UNIT))
  {
expansion_failed (loc, NULL_RTX,
  "bitfield access");
return 0;
  }

This lifts the second part of the restriction, which helps for obscure cases
of packed discriminated record types in Ada, although this requires the very
latest GDB sources.

gcc/
* dwarf2out.cc (loc_list_from_tree_1) : Do not bail
out when the size is not a multiple of a byte.
Deal with bit-fields whose size is not a multiple of a byte when
dereferencing an address.

Diff:
---
 gcc/dwarf2out.cc | 40 
 1 file changed, 32 insertions(+), 8 deletions(-)

diff --git a/gcc/dwarf2out.cc b/gcc/dwarf2out.cc
index 9aecdb9fd5a1..713a55108aa2 100644
--- a/gcc/dwarf2out.cc
+++ b/gcc/dwarf2out.cc
@@ -19161,11 +19161,9 @@ loc_list_from_tree_1 (tree loc, int want_address,
   for nonzero bitpos.  */
if (list_ret == 0)
  return 0;
-   if (!multiple_p (bitpos, BITS_PER_UNIT, &bytepos)
-   || !multiple_p (bitsize, BITS_PER_UNIT))
+   if (!multiple_p (bitpos, BITS_PER_UNIT, &bytepos))
  {
-   expansion_failed (loc, NULL_RTX,
- "bitfield access");
+   expansion_failed (loc, NULL_RTX, "bitfield access");
return 0;
  }
 
@@ -19724,11 +19722,10 @@ loc_list_from_tree_1 (tree loc, int want_address,
   dw_die_ref type_die;
   dw_loc_descr_ref deref;
 
-  /* If the size is greater than DWARF2_ADDR_SIZE, bail out.  */
-  if (size > DWARF2_ADDR_SIZE || size == -1)
+  /* Bail out if the size is variable or greater than DWARF2_ADDR_SIZE.  */
+  if (size < 0 || size > DWARF2_ADDR_SIZE)
{
- expansion_failed (loc, NULL_RTX,
-   "DWARF address size mismatch");
+ expansion_failed (loc, NULL_RTX, "DWARF address size mismatch");
  return 0;
}
 
@@ -19757,6 +19754,33 @@ loc_list_from_tree_1 (tree loc, int want_address,
 new_loc_descr (dwarf_OP (DW_OP_convert), 0, 0));
}
 
+  /* Deal with bit-fields whose size is not a multiple of a byte.  */
+  if (TREE_CODE (loc) == COMPONENT_REF
+ && DECL_BIT_FIELD (TREE_OPERAND (loc, 1)))
+   {
+ const unsigned HOST_WIDE_INT bitsize
+   = tree_to_uhwi (DECL_SIZE (TREE_OPERAND (loc, 1)));
+ if (bitsize < (unsigned HOST_WIDE_INT)size * BITS_PER_UNIT)
+   {
+ if (TYPE_UNSIGNED (TREE_TYPE (loc)))
+   {
+ const unsigned HOST_WIDE_INT mask
+   = (HOST_WIDE_INT_1U << bitsize) - 1;
+ add_loc_descr (&deref, uint_loc_descriptor (mask));
+ add_loc_descr (&deref, new_loc_descr (DW_OP_and, 0, 0));
+   }
+ else
+   {
+ const unsigned HOST_WIDE_INT shift
+   = DWARF2_ADDR_SIZE * BITS_PER_UNIT - bitsize;
+ add_loc_descr (&deref, uint_loc_descriptor (shift));
+ add_loc_descr (&deref, new_loc_descr (DW_OP_shl, 0, 0));
+ add_loc_descr (&deref, uint_loc_descriptor (shift));
+ add_loc_descr (&deref, new_loc_descr (DW_OP_shra, 0, 0));
+   }
+   }
+   }
+
   if (ret)
add_loc_descr (&ret, deref);
   else