[gcc(refs/users/meissner/heads/work204-cmodel)] Update ChangeLog.*
https://gcc.gnu.org/g:6e92f6f221f2a4eb81973aa41575854961cd6f98 commit 6e92f6f221f2a4eb81973aa41575854961cd6f98 Author: Michael Meissner Date: Fri May 2 13:50:44 2025 -0400 Update ChangeLog.* Diff: --- gcc/ChangeLog.cmodel | 383 +++ 1 file changed, 383 insertions(+) diff --git a/gcc/ChangeLog.cmodel b/gcc/ChangeLog.cmodel index de19de309b5d..dd8d52b9ff29 100644 --- a/gcc/ChangeLog.cmodel +++ b/gcc/ChangeLog.cmodel @@ -1,5 +1,388 @@ + Branch work204-cmodel, patch #500 + +Allow pc-relative references to be used with -mcmodel=large + +2025-05-02 Michael Meissner + +gcc/ + + * config/rs6000/rs6000.cc (rs6000_option_override_internal): Allow + -mcmodel=large and pc-relative addressing. + * config/rs6000/rs6000.md (tocref): Don't split large code model + references if pc-relative addressing is used. + + Branch work204-cmodel, patch #411 (from paddis branch) + +RFC2677-Add xvrlw support. + +2025-04-30 Michael Meissner + +gcc/ + + * config/rs6000/altivec.md (xvrlw): New insn. + * config/rs6000/rs6000.h (TARGET_XVRLW): New macro. + +gcc/testsuite/ + + * gcc.target/powerpc/vector-rotate-left.c: New test. + + Branch work204-cmodel, patch #410 (from paddis branch) + +RFC2686-Add paddis support. + +2025-04-30 Michael Meissner + +gcc/ + + * config/rs6000/constraints.md (eU): New constraint. + (eV): Likewise. + * config/rs6000/predicates.md (paddis_operand): New predicate. + (paddis_paddi_operand): Likewise. + (add_operand): Add paddis support. + * config/rs6000/rs6000.cc (num_insns_constant_gpr): Add paddis support. + (num_insns_constant_multi): Likewise. + (print_operand): Add %B for paddis support. + * config/rs6000/rs6000.h (TARGET_PADDIS): New macro. + (SIGNED_INTEGER_32BIT_P): Likewise. + * config/rs6000/rs6000.md (isa attribute): Add paddis support. + (enabled attribute); Likewise. + (add3): Likewise. + (adddi3 splitter): New splitter for paddis. + (movdi_internal64): Add paddis support. + (movdi splitter): New splitter for paddis. + +gcc/testsuite/ + + * gcc.target/powerpc/prefixed-addis.c: New test. + + Branch work204-cmodel, patch #401 (from paddis branch) + +RFC2655-Add saturating subtract built-ins. + +This patch adds support for a saturating subtract built-in function that may be +added to a future PowerPC processor. Note, if it is added, the name of the +built-in function may change before GCC 13 is released. If the name changes, +we will submit a patch changing the name. + +I also added support for providing dense math built-in functions, even though +at present, we have not added any new built-in functions for dense math. It is +likely we will want to add new dense math built-in functions as the dense math +support is fleshed out. + +The patches have been tested on both little and big endian systems. Can I check +it into the master branch? + +2025-04-30 Michael Meissner + +gcc/ + + * config/rs6000/rs6000-builtin.cc (rs6000_invalid_builtin): Add support + for flagging invalid use of future built-in functions. + (rs6000_builtin_is_supported): Add support for future built-in + functions. + * config/rs6000/rs6000-builtins.def (__builtin_saturate_subtract32): New + built-in function for -mcpu=future. + (__builtin_saturate_subtract64): Likewise. + * config/rs6000/rs6000-gen-builtins.cc (enum bif_stanza): Add stanzas + for -mcpu=future built-ins. + (stanza_map): Likewise. + (enable_string): Likewise. + (struct attrinfo): Likewise. + (parse_bif_attrs): Likewise. + (write_decls): Likewise. + * config/rs6000/rs6000.md (sat_sub3): Add saturating subtract + built-in insn declarations. + (sat_sub3_dot): Likewise. + (sat_sub3_dot2): Likewise. + * doc/extend.texi (Future PowerPC built-ins): New section. + +gcc/testsuite/ + + * gcc.target/powerpc/subfus-1.c: New test. + * gcc.target/powerpc/subfus-2.c: Likewise. + + Branch work204-cmodel, patch #400 (from paddis branch) + +RFC2656-Support load/store vector with right length. + +This patch adds support for new instructions that may be added to the PowerPC +architecture in the future to enhance the load and store vector with length +instructions. + +The current instructions (lxvl, lxvll, stxvl, and stxvll) are inconvient to use +since the count for the number of bytes must be in the top 8 bits of the GPR +register, instead of the bottom 8 bits. This meant that code generating these +instructions typically had to do a shift left by 56 bits to get the count into +the right position. In a future version of the PowerPC architect
[gcc(refs/vendors/ibm/heads/gcc-15-branch)] ibm: Create the ibm/gcc-15-branch
https://gcc.gnu.org/g:066115a7a44ae32615ac66d5ed1580117a6df823 commit 066115a7a44ae32615ac66d5ed1580117a6df823 Author: Surya Kumari Jangala Date: Fri May 2 12:35:15 2025 -0500 ibm: Create the ibm/gcc-15-branch 2025-05-02 Surya Kumari Jangala Create ibm/gcc-15-branch which follows the releases/gcc-15 branch. Diff: --- gcc/ChangeLog.ibm | 3 +++ 1 file changed, 3 insertions(+) diff --git a/gcc/ChangeLog.ibm b/gcc/ChangeLog.ibm new file mode 100644 index ..adb49a9944b0 --- /dev/null +++ b/gcc/ChangeLog.ibm @@ -0,0 +1,3 @@ +2025-05-02 Surya Kumari Jangala + + Create ibm/gcc-15-branch which follows the releases/gcc-15 branch.
[gcc(refs/users/meissner/heads/work204-cmodel)] RFC2653-PowerPC: Add support for 1, 024 bit DMR registers.
https://gcc.gnu.org/g:0111e9b23dfd7f3033d1ae7b01c08d5c389b109f commit 0111e9b23dfd7f3033d1ae7b01c08d5c389b109f Author: Michael Meissner Date: Wed Apr 30 22:37:34 2025 -0400 RFC2653-PowerPC: Add support for 1,024 bit DMR registers. This patch is a prelimianry patch to add the full 1,024 bit dense math register (DMRs) for -mcpu=future. The MMA 512-bit accumulators map onto the top of the DMR register. This patch only adds the new 1,024 bit register support. It does not add support for any instructions that need 1,024 bit registers instead of 512 bit registers. I used the new mode 'TDOmode' to be the opaque mode used for 1,024 bit registers. The 'wD' constraint added in previous patches is used for these registers. I added support to do load and store of DMRs via the VSX registers, since there are no load/store dense math instructions. I added the new keyword '__dmr' to create 1,024 bit types that can be loaded into DMRs. At present, I don't have aliases for __dmr512 and __dmr1024 that we've discussed internally. The patches have been tested on both little and big endian systems. Can I check it into the master branch? 2025-04-30 Michael Meissner gcc/ * config/rs6000/mma.md (UNSPEC_DM_INSERT512_UPPER): New unspec. (UNSPEC_DM_INSERT512_LOWER): Likewise. (UNSPEC_DM_EXTRACT512): Likewise. (UNSPEC_DMR_RELOAD_FROM_MEMORY): Likewise. (UNSPEC_DMR_RELOAD_TO_MEMORY): Likewise. (movtdo): New define_expand and define_insn_and_split to implement 1,024 bit DMR registers. (movtdo_insert512_upper): New insn. (movtdo_insert512_lower): Likewise. (movtdo_extract512): Likewise. (reload_dmr_from_memory): Likewise. (reload_dmr_to_memory): Likewise. * config/rs6000/rs6000-builtin.cc (rs6000_type_string): Add DMR support. (rs6000_init_builtins): Add support for __dmr keyword. * config/rs6000/rs6000-call.cc (rs6000_return_in_memory): Add support for TDOmode. (rs6000_function_arg): Likewise. * config/rs6000/rs6000-modes.def (TDOmode): New mode. * config/rs6000/rs6000.cc (rs6000_hard_regno_nregs_internal): Add support for TDOmode. (rs6000_hard_regno_mode_ok_uncached): Likewise. (rs6000_hard_regno_mode_ok): Likewise. (rs6000_modes_tieable_p): Likewise. (rs6000_debug_reg_global): Likewise. (rs6000_setup_reg_addr_masks): Likewise. (rs6000_init_hard_regno_mode_ok): Add support for TDOmode. Setup reload hooks for DMR mode. (reg_offset_addressing_ok_p): Add support for TDOmode. (rs6000_emit_move): Likewise. (rs6000_secondary_reload_simple_move): Likewise. (rs6000_preferred_reload_class): Likewise. (rs6000_secondary_reload_class): Likewise. (rs6000_mangle_type): Add mangling for __dmr type. (rs6000_dmr_register_move_cost): Add support for TDOmode. (rs6000_split_multireg_move): Likewise. (rs6000_invalid_conversion): Likewise. * config/rs6000/rs6000.h (VECTOR_ALIGNMENT_P): Add TDOmode. (enum rs6000_builtin_type_index): Add DMR type nodes. (dmr_type_node): Likewise. (ptr_dmr_type_node): Likewise. gcc/testsuite/ * gcc.target/powerpc/dm-1024bit.c: New test. * lib/target-supports.exp (check_effective_target_ppc_dmr_ok): New target test. Diff: --- gcc/config/rs6000/mma.md | 154 ++ gcc/config/rs6000/rs6000-builtin.cc | 17 +++ gcc/config/rs6000/rs6000-call.cc | 10 +- gcc/config/rs6000/rs6000-modes.def| 4 + gcc/config/rs6000/rs6000.cc | 101 - gcc/config/rs6000/rs6000.h| 6 +- gcc/testsuite/gcc.target/powerpc/dm-1024bit.c | 63 +++ gcc/testsuite/lib/target-supports.exp | 35 ++ 8 files changed, 356 insertions(+), 34 deletions(-) diff --git a/gcc/config/rs6000/mma.md b/gcc/config/rs6000/mma.md index 683d2398ef90..1420fadd4355 100644 --- a/gcc/config/rs6000/mma.md +++ b/gcc/config/rs6000/mma.md @@ -92,6 +92,11 @@ UNSPEC_MMA_XXMFACC UNSPEC_MMA_XXMTACC UNSPEC_MMA_DMSETDMRZ + UNSPEC_DM_INSERT512_UPPER + UNSPEC_DM_INSERT512_LOWER + UNSPEC_DM_EXTRACT512 + UNSPEC_DMR_RELOAD_FROM_MEMORY + UNSPEC_DMR_RELOAD_TO_MEMORY ]) (define_c_enum "unspecv" @@ -742,3 +747,152 @@ " %A0,%x2,%x3,%4,%5,%6" [(set_attr "type" "mma") (set_attr "prefixed" "yes")]) + +;; TDOmode (__dmr keyword for 1,024 bit registers). +(define_expand "movtdo" + [(set (match_operand:TDO 0 "nonimmediate_operand") + (match_operand:
[gcc(refs/users/meissner/heads/work204-cmodel)] RFC2653-Add wD constraint.
https://gcc.gnu.org/g:36357abdb0554cbccbc70fc9e3e3cae230a3446b
commit 36357abdb0554cbccbc70fc9e3e3cae230a3446b
Author: Michael Meissner
Date: Wed Apr 30 22:36:45 2025 -0400
RFC2653-Add wD constraint.
This patch adds a new constraint ('wD') that matches the accumulator
registers
that overlap with VSX registers 0..31 on power10. Future patches will add
the
support for a separate accumulator register class that will be used when the
support for dense math registes is added.
2025-04-30 Michael Meissner
* config/rs6000/constraints.md (wD): New constraint.
* config/rs6000/mma.md (mma_): Prepare for alternate
accumulator
registers. Use wD constraint instead of 'd' constraint. Use
accumulator_operand instead of fpr_reg_operand.
(mma_): Likewise.
(mma_): Likewise.
(mma_): Likewise.
(mma_): Likewise.
(mma_): Likewise.
(mma_): Likewise.
(mma_): Likewise.
(mma_): Likewise.
(mma_): Likewise.
(mma_): Likewise.
(mma_): Likewise.
(mma_): Likewise.
(mma_"
- [(set (match_operand:XO 0 "fpr_reg_operand" "=&d")
- (unspec:XO [(match_operand:XO 1 "fpr_reg_operand" "0")]
+ [(set (match_operand:XO 0 "accumulator_operand" "=&wD")
+ (unspec:XO [(match_operand:XO 1 "accumulator_operand" "0")]
MMA_ACC))]
"TARGET_MMA"
" %A0"
@@ -523,7 +523,7 @@
[(set_attr "type" "mma")])
(define_insn "mma_"
- [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d")
+ [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
(unspec:XO [(match_operand:V16QI 1 "vsx_register_operand" "v,?wa")
(match_operand:V16QI 2 "vsx_register_operand" "v,?wa")]
MMA_VV))]
@@ -532,8 +532,8 @@
[(set_attr "type" "mma")])
(define_insn "mma_"
- [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d")
- (unspec:XO [(match_operand:XO 1 "fpr_reg_operand" "0,0")
+ [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
+ (unspec:XO [(match_operand:XO 1 "accumulator_operand" "0,0")
(match_operand:V16QI 2 "vsx_register_operand" "v,?wa")
(match_operand:V16QI 3 "vsx_register_operand" "v,?wa")]
MMA_AVV))]
@@ -542,7 +542,7 @@
[(set_attr "type" "mma")])
(define_insn "mma_"
- [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d")
+ [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
(unspec:XO [(match_operand:OO 1 "vsx_register_operand" "v,?wa")
(match_operand:V16QI 2 "vsx_register_operand" "v,?wa")]
MMA_PV))]
@@ -551,8 +551,8 @@
[(set_attr "type" "mma")])
(define_insn "mma_"
- [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d")
- (unspec:XO [(match_operand:XO 1 "fpr_reg_operand" "0,0")
+ [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
+ (unspec:XO [(match_operand:XO 1 "accumulator_operand" "0,0")
(match_operand:OO 2 "vsx_register_operand" "v,?wa")
(match_operand:V16QI 3 "vsx_register_operand" "v,?wa")]
MMA_APV))]
@@ -561,7 +561,7 @@
[(set_attr "type" "mma")])
(define_insn "mma_"
- [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d")
+ [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
(unspec:XO [(match_operand:V16QI 1 "vsx_register_operand" "v,?wa")
(match_operand:V16QI 2 "vsx_register_operand" "v,?wa")
(match_operand:SI 3 "const_0_to_15_operand" "n,n")
@@ -574,8 +574,8 @@
(set_attr "prefixed" "yes")])
(define_insn "mma_"
- [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d")
- (unspec:XO [(match_operand:XO 1 "fpr_reg_operand" "0,0")
+ [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
+ (unspec:XO [(match_operand:XO 1 "accumulator_operand" "0,0")
(match_operand:V16QI 2 "vsx_register_operand" "v,?wa")
(match_operand:V16QI 3 "vsx_register_operand" "v,?wa")
(match_operand:SI 4 "const_0_to_15_operand" "n,n")
@@ -588,7 +588,7 @@
(set_attr "prefixed" "yes")])
(define_insn "mma_"
- [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d")
+ [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
(unspec:XO [(match_operand:V16QI 1 "vsx_register_operand" "v,?wa")
(match_operand:V16QI 2 "vsx_register_operand" "v,?wa")
(match_operand:SI 3 "const_0_to_15_operand" "n,n")
@@ -601,8 +601,8 @@
(set_attr "prefixed" "yes")])
(define_insn "mma_"
- [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d")
- (unspec:XO [(match_operand:XO 1 "fpr_reg_operand" "0,0")
+ [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
+ (unspec:XO [(match_operand:XO 1 "accumulator_operand" "0,0")
[gcc r16-363] ranger: Improve nonnull_if_nonzero attribute [PR117023]
https://gcc.gnu.org/g:1e27e9a3184c948b499a21ff20181611514ed720
commit r16-363-g1e27e9a3184c948b499a21ff20181611514ed720
Author: Jakub Jelinek
Date: Fri May 2 19:40:55 2025 +0200
ranger: Improve nonnull_if_nonzero attribute [PR117023]
On Mon, Mar 31, 2025 at 11:30:20AM -0400, Andrew MacLeod wrote:
> Infer range processing was adjusted to allow a query to be specified,
> but during VRP folding, ranger w3as not providing a query. This results
> in contextual ranges being missed. Pass the cache in as the query
> which provide a read-only query of the current state.
Now that this patch is in, I've retested my patch and it works fine.
If we can determine a range for the arg2 argument and prove that it
doesn't include zero, we can imply nonzero for the arg1 argument.
2025-05-02 Jakub Jelinek
Andrew MacLeod
PR c/117023
* gimple-range-infer.cc (gimple_infer_range::gimple_infer_range):
For nonnull_if_nonzero attribute check also arg2 range if it doesn't
include zero and in that case call add_nonzero too.
* gcc.dg/tree-ssa/pr78154-2.c: New test.
Diff:
---
gcc/gimple-range-infer.cc | 9 ++--
gcc/testsuite/gcc.dg/tree-ssa/pr78154-2.c | 38 +++
2 files changed, 45 insertions(+), 2 deletions(-)
diff --git a/gcc/gimple-range-infer.cc b/gcc/gimple-range-infer.cc
index 3b1abbef5663..72f71b980598 100644
--- a/gcc/gimple-range-infer.cc
+++ b/gcc/gimple-range-infer.cc
@@ -208,8 +208,13 @@ gimple_infer_range::gimple_infer_range (gimple *s,
range_query *q,
continue;
if (integer_nonzerop (arg2))
add_nonzero (arg);
- // FIXME: Can one query here whether arg2 has
- // nonzero range if it is a SSA_NAME?
+ else
+ {
+ value_range r (TREE_TYPE (arg2));
+ if (q->range_of_expr (r, arg2, s)
+ && !r.contains_p (build_zero_cst (TREE_TYPE (arg2
+ add_nonzero (arg);
+ }
}
}
// Fallthru and walk load/store ops now.
diff --git a/gcc/testsuite/gcc.dg/tree-ssa/pr78154-2.c
b/gcc/testsuite/gcc.dg/tree-ssa/pr78154-2.c
new file mode 100644
index ..3b2cbd854299
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/tree-ssa/pr78154-2.c
@@ -0,0 +1,38 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -fdump-tree-evrp-slim -fdelete-null-pointer-checks" } */
+/* { dg-skip-if "" { keeps_null_pointer_checks } } */
+
+void foo (void *, __SIZE_TYPE__) __attribute__((nonnull_if_nonzero (1, 2)));
+void baz (void);
+
+void
+bar (void *a, void *b, void *c, void *d, void *e, __SIZE_TYPE__ n)
+{
+ foo (a, 42);
+ if (a == 0)
+__builtin_abort ();
+ if (n)
+{
+ foo (b, n);
+ if (b == 0)
+ __builtin_abort ();
+}
+ if (n >= 42)
+{
+ foo (c, n - 10);
+ if (c == 0)
+ __builtin_abort ();
+}
+ foo (d, 0);
+ if (d == 0)
+baz ();
+ if (n != 42)
+{
+ foo (e, n);
+ if (e == 0)
+ baz ();
+}
+}
+
+/* { dg-final { scan-tree-dump-not "__builtin_abort" "evrp" } } */
+/* { dg-final { scan-tree-dump-times "baz \\\(" 2 "evrp" } } */
[gcc(refs/users/meissner/heads/work204-cmodel)] Allow pc-relative references to be used with -mcmodel=large
https://gcc.gnu.org/g:a50d6756834db3cf74a96577fd816f67990b5c35
commit a50d6756834db3cf74a96577fd816f67990b5c35
Author: Michael Meissner
Date: Fri May 2 13:41:49 2025 -0400
Allow pc-relative references to be used with -mcmodel=large
2025-05-02 Michael Meissner
gcc/
* config/rs6000/rs6000.cc (rs6000_option_override_internal): Allow
-mcmodel=large and pc-relative addressing.
* config/rs6000/rs6000.md (tocref): Don't split large code
model
references if pc-relative addressing is used.
Diff:
---
gcc/config/rs6000/rs6000.cc | 10 --
gcc/config/rs6000/rs6000.md | 2 +-
2 files changed, 1 insertion(+), 11 deletions(-)
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 528220f30537..3db913c7bd78 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -4536,16 +4536,6 @@ rs6000_option_override_internal (bool global_init_p)
&& (rs6000_isa_flags_explicit & OPTION_MASK_PCREL) == 0)
rs6000_isa_flags |= OPTION_MASK_PCREL;
- /* -mpcrel requires -mcmodel=medium, but we can't check TARGET_CMODEL until
- after the subtarget override options are done. */
- else if (TARGET_PCREL && TARGET_CMODEL != CMODEL_MEDIUM)
-{
- if ((rs6000_isa_flags_explicit & OPTION_MASK_PCREL) != 0)
- error ("%qs requires %qs", "-mpcrel", "-mcmodel=medium");
-
- rs6000_isa_flags &= ~OPTION_MASK_PCREL;
-}
-
/* Enable -mmma by default on power10 systems. */
if (TARGET_POWER10 && (rs6000_isa_flags_explicit & OPTION_MASK_MMA) == 0)
rs6000_isa_flags |= OPTION_MASK_MMA;
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 6786030c6bb6..64fd82b08b40 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -11406,7 +11406,7 @@
(define_insn_and_split "*tocref"
[(set (match_operand:P 0 "gpc_reg_operand" "=b")
(match_operand:P 1 "small_toc_ref" "R"))]
- "TARGET_TOC
+ "TARGET_TOC && !TARGET_PCREL
&& legitimate_constant_pool_address_p (operands[1], QImode, false)"
"la %0,%a1"
"&& TARGET_CMODEL != CMODEL_SMALL && reload_completed"
[gcc(refs/users/meissner/heads/work204-cmodel)] RFC2653-Add support for dense math registers.
https://gcc.gnu.org/g:49847a5e8ed3a04e31a534e88170ed9ce193eb88 commit 49847a5e8ed3a04e31a534e88170ed9ce193eb88 Author: Michael Meissner Date: Wed Apr 30 22:37:13 2025 -0400 RFC2653-Add support for dense math registers. The MMA subsystem added the notion of accumulator registers as an optional feature of ISA 3.1 (power10). In ISA 3.1, these accumulators overlapped with the VSX registers 0..31, but logically the accumulator registers were separate from the FPR registers. In ISA 3.1, it was anticipated that in future systems, the accumulator registers may no overlap with the FPR registers. This patch adds the support for dense math registers as separate registers. This particular patch does not change the MMA support to use the accumulators within the dense math registers. This patch just adds the basic support for having separate DMRs. The next patch will switch the MMA support to use the accumulators if -mcpu=future is used. For testing purposes, I added an undocumented option '-mdense-math' to enable or disable the dense math support. This patch updates the wD constraint added in the previous patch. If MMA is selected but dense math is not selected (i.e. -mcpu=power10), the wD constraint will allow access to accumulators that overlap with VSX registers 0..31. If both MMA and dense math are selected (i.e. -mcpu=future), the wD constraint will only allow dense math registers. This patch modifies the existing %A output modifier. If MMA is selected but dense math is not selected, then %A output modifier converts the VSX register number to the accumulator number, by dividing it by 4. If both MMA and dense math are selected, then %A will map the separate DMR registers into 0..7. The intention is that user code using extended asm can be modified to run on both MMA without dense math and MMA with dense math: 1) If possible, don't use extended asm, but instead use the MMA built-in functions; 2) If you do need to write extended asm, change the d constraints targetting accumulators should now use wD; 3) Only use the built-in zero, assemble and disassemble functions create move data between vector quad types and dense math accumulators. I.e. do not use the xxmfacc, xxmtacc, and xxsetaccz directly in the extended asm code. The reason is these instructions assume there is a 1-to-1 correspondence between 4 adjacent FPR registers and an accumulator that overlaps with those instructions. With accumulators now being separate registers, there no longer is a 1-to-1 correspondence. It is possible that the mangling for DMRs and the GDB register numbers may produce other changes in the future. gcc/ 2025-04-30 Michael Meissner * config/rs6000/mma.md (UNSPEC_MMA_DMSETDMRZ): New unspec. (movxo): Add comments about dense math registers. (movxo_nodm): Rename from movxo and restrict the usage to machines without dense math registers. (movxo_dm): New insn for movxo support for machines with dense math registers. (mma_): Restrict usage to machines without dense math registers. (mma_xxsetaccz): Add a define_expand wrapper, and add support for dense math registers. (mma_dmsetaccz): New insn. * config/rs6000/predicates.md (dmr_operand): New predicate. (accumulator_operand): Add support for dense math registers. * config/rs6000/rs6000-builtin.cc (rs6000_gimple_fold_mma_builtin): Do not issue a de-prime instruction when disassembling a vector quad on a system with dense math registers. * config/rs6000/rs6000-c.cc (rs6000_define_or_undefine_macro): Define __DENSE_MATH__ if we have dense math registers. * config/rs6000/rs6000.cc (enum rs6000_reg_type): Add DMR_REG_TYPE. (enum rs6000_reload_reg_type): Add RELOAD_REG_DMR. (LAST_RELOAD_REG_CLASS): Add support for DMR registers and the wD constraint. (reload_reg_map): Likewise. (rs6000_reg_names): Likewise. (alt_reg_names): Likewise. (rs6000_hard_regno_nregs_internal): Likewise. (rs6000_hard_regno_mode_ok_uncached): Likewise. (rs6000_debug_reg_global): Likewise. (rs6000_setup_reg_addr_masks): Likewise. (rs6000_init_hard_regno_mode_ok): Likewise. (rs6000_secondary_reload_memory): Add support for DMR registers. (rs6000_secondary_reload_simple_move): Likewise. (rs6000_preferred_reload_class): Likewise. (rs6000_secondary_reload_class): Likewise. (print_operan
[gcc(refs/users/meissner/heads/work204-cmodel)] RFC2656-Support load/store vector with right length.
https://gcc.gnu.org/g:9b6c91b24ddcd586f9690228fd23867412592619
commit 9b6c91b24ddcd586f9690228fd23867412592619
Author: Michael Meissner
Date: Wed Apr 30 22:37:58 2025 -0400
RFC2656-Support load/store vector with right length.
This patch adds support for new instructions that may be added to the
PowerPC
architecture in the future to enhance the load and store vector with length
instructions.
The current instructions (lxvl, lxvll, stxvl, and stxvll) are inconvient to
use
since the count for the number of bytes must be in the top 8 bits of the GPR
register, instead of the bottom 8 bits. This meant that code generating
these
instructions typically had to do a shift left by 56 bits to get the count
into
the right position. In a future version of the PowerPC architecture, new
variants of these instructions might be added that expect the count to be in
the bottom 8 bits of the GPR register. These patches add this support to
GCC
if the user uses the -mcpu=future option.
I discovered that the code in rs6000-string.cc to generate ISA 3.1
lxvl/stxvl
future lxvll/stxvll instructions would generate these instructions on
32-bit.
However the patterns for these instructions is only done on 64-bit systems.
So
I added a check for 64-bit support before generating the instructions.
The patches have been tested on both little and big endian systems. Can I
check
it into the master branch?
2025-04-30 Michael Meissner
gcc/
* config/rs6000/rs6000-string.cc (expand_block_move): Do not
generate
lxvl and stxvl on 32-bit.
* config/rs6000/vsx.md (lxvl): If -mcpu=future, generate the lxvl
with
the shift count automaticaly used in the insn.
(lxvrl): New insn for -mcpu=future.
(lxvrll): Likewise.
(stxvl): If -mcpu=future, generate the stxvl with the shift count
automaticaly used in the insn.
(stxvrl): New insn for -mcpu=future.
(stxvrll): Likewise.
gcc/testsuite/
* gcc.target/powerpc/lxvrl.c: New test.
* lib/target-supports.exp
(check_effective_target_powerpc_future_ok):
New effective target.
Diff:
---
gcc/config/rs6000/rs6000-string.cc | 1 +
gcc/config/rs6000/vsx.md | 122 +--
gcc/testsuite/gcc.target/powerpc/lxvrl.c | 32
3 files changed, 134 insertions(+), 21 deletions(-)
diff --git a/gcc/config/rs6000/rs6000-string.cc
b/gcc/config/rs6000/rs6000-string.cc
index 703f77fa0bf1..814328140553 100644
--- a/gcc/config/rs6000/rs6000-string.cc
+++ b/gcc/config/rs6000/rs6000-string.cc
@@ -2786,6 +2786,7 @@ expand_block_move (rtx operands[], bool might_overlap)
if (TARGET_MMA && TARGET_BLOCK_OPS_UNALIGNED_VSX
&& TARGET_BLOCK_OPS_VECTOR_PAIR
+ && TARGET_POWERPC64
&& bytes >= 32
&& (align >= 256 || !STRICT_ALIGNMENT))
{
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index dd3573b80868..89523cf4a0e5 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -5712,20 +5712,32 @@
DONE;
})
-;; Load VSX Vector with Length
+;; Load VSX Vector with Length. If we have lxvrl, we don't have to do an
+;; explicit shift left into a pseudo.
(define_expand "lxvl"
- [(set (match_dup 3)
-(ashift:DI (match_operand:DI 2 "register_operand")
- (const_int 56)))
- (set (match_operand:V16QI 0 "vsx_register_operand")
- (unspec:V16QI
-[(match_operand:DI 1 "gpc_reg_operand")
- (mem:V16QI (match_dup 1))
- (match_dup 3)]
-UNSPEC_LXVL))]
+ [(use (match_operand:V16QI 0 "vsx_register_operand"))
+ (use (match_operand:DI 1 "gpc_reg_operand"))
+ (use (match_operand:DI 2 "gpc_reg_operand"))]
"TARGET_P9_VECTOR && TARGET_64BIT"
{
- operands[3] = gen_reg_rtx (DImode);
+ rtx shift_len = gen_rtx_ASHIFT (DImode, operands[2], GEN_INT (56));
+ rtx len;
+
+ if (TARGET_FUTURE)
+len = shift_len;
+ else
+{
+ len = gen_reg_rtx (DImode);
+ emit_insn (gen_rtx_SET (len, shift_len));
+}
+
+ rtx dest = operands[0];
+ rtx addr = operands[1];
+ rtx mem = gen_rtx_MEM (V16QImode, addr);
+ rtvec rv = gen_rtvec (3, addr, mem, len);
+ rtx lxvl = gen_rtx_UNSPEC (V16QImode, rv, UNSPEC_LXVL);
+ emit_insn (gen_rtx_SET (dest, lxvl));
+ DONE;
})
(define_insn "*lxvl"
@@ -5749,6 +5761,34 @@
"lxvll %x0,%1,%2"
[(set_attr "type" "vecload")])
+;; For lxvrl and lxvrll, use the combiner to eliminate the shift. The
+;; define_expand for lxvl will already incorporate the shift in generating the
+;; insn. The lxvll buitl-in function required the user to have already done
+;; the shift. Defining lxvrll this way, will optimize cases where the user has
+;; done the shift immediately before the built-in.
+(define_insn "*lxvrl"
+ [(set (matc
[gcc(refs/users/meissner/heads/work204-cmodel)] RFC2655-Add saturating subtract built-ins.
https://gcc.gnu.org/g:0e71cb662f9ef8a42096cdf41210bd453b1e10fe
commit 0e71cb662f9ef8a42096cdf41210bd453b1e10fe
Author: Michael Meissner
Date: Wed Apr 30 22:38:19 2025 -0400
RFC2655-Add saturating subtract built-ins.
This patch adds support for a saturating subtract built-in function that
may be
added to a future PowerPC processor. Note, if it is added, the name of the
built-in function may change before GCC 13 is released. If the name
changes,
we will submit a patch changing the name.
I also added support for providing dense math built-in functions, even
though
at present, we have not added any new built-in functions for dense math.
It is
likely we will want to add new dense math built-in functions as the dense
math
support is fleshed out.
The patches have been tested on both little and big endian systems. Can I
check
it into the master branch?
2025-04-30 Michael Meissner
gcc/
* config/rs6000/rs6000-builtin.cc (rs6000_invalid_builtin): Add
support
for flagging invalid use of future built-in functions.
(rs6000_builtin_is_supported): Add support for future built-in
functions.
* config/rs6000/rs6000-builtins.def
(__builtin_saturate_subtract32): New
built-in function for -mcpu=future.
(__builtin_saturate_subtract64): Likewise.
* config/rs6000/rs6000-gen-builtins.cc (enum bif_stanza): Add
stanzas
for -mcpu=future built-ins.
(stanza_map): Likewise.
(enable_string): Likewise.
(struct attrinfo): Likewise.
(parse_bif_attrs): Likewise.
(write_decls): Likewise.
* config/rs6000/rs6000.md (sat_sub3): Add saturating subtract
built-in insn declarations.
(sat_sub3_dot): Likewise.
(sat_sub3_dot2): Likewise.
* doc/extend.texi (Future PowerPC built-ins): New section.
gcc/testsuite/
* gcc.target/powerpc/subfus-1.c: New test.
* gcc.target/powerpc/subfus-2.c: Likewise.
Diff:
---
gcc/config/rs6000/rs6000-builtin.cc | 17
gcc/config/rs6000/rs6000-builtins.def | 10 +
gcc/config/rs6000/rs6000-gen-builtins.cc| 35 ++---
gcc/config/rs6000/rs6000.md | 60 +
gcc/doc/extend.texi | 24
gcc/testsuite/gcc.target/powerpc/subfus-1.c | 32 +++
gcc/testsuite/gcc.target/powerpc/subfus-2.c | 32 +++
7 files changed, 205 insertions(+), 5 deletions(-)
diff --git a/gcc/config/rs6000/rs6000-builtin.cc
b/gcc/config/rs6000/rs6000-builtin.cc
index ea8755b3ef8a..1885b1f636f3 100644
--- a/gcc/config/rs6000/rs6000-builtin.cc
+++ b/gcc/config/rs6000/rs6000-builtin.cc
@@ -139,6 +139,17 @@ rs6000_invalid_builtin (enum rs6000_gen_builtins fncode)
case ENB_MMA:
error ("%qs requires the %qs option", name, "-mmma");
break;
+case ENB_FUTURE:
+ error ("%qs requires the %qs option", name, "-mcpu=future");
+ break;
+case ENB_FUTURE_64:
+ error ("%qs requires the %qs option and either the %qs or %qs option",
+name, "-mcpu=future", "-m64", "-mpowerpc64");
+ break;
+case ENB_DM:
+ error ("%qs requires the %qs or %qs options", name, "-mcpu=future",
+"-mdense-math");
+ break;
default:
case ENB_ALWAYS:
gcc_unreachable ();
@@ -194,6 +205,12 @@ rs6000_builtin_is_supported (enum rs6000_gen_builtins
fncode)
return TARGET_HTM;
case ENB_MMA:
return TARGET_MMA;
+case ENB_FUTURE:
+ return TARGET_FUTURE;
+case ENB_FUTURE_64:
+ return TARGET_FUTURE && TARGET_POWERPC64;
+case ENB_DM:
+ return TARGET_DENSE_MATH;
default:
gcc_unreachable ();
}
diff --git a/gcc/config/rs6000/rs6000-builtins.def
b/gcc/config/rs6000/rs6000-builtins.def
index 555d7d589506..eef5f41f7615 100644
--- a/gcc/config/rs6000/rs6000-builtins.def
+++ b/gcc/config/rs6000/rs6000-builtins.def
@@ -137,6 +137,8 @@
; endian Needs special handling for endianness
; ibmldRestrict usage to the case when TFmode is IBM-128
; ibm128 Restrict usage to the case where __ibm128 is supported or if ibmld
+; future Restrict usage to future instructions
+; dm Restrict usage to dense math
;
; Each attribute corresponds to extra processing required when
; the built-in is expanded. All such special processing should
@@ -3924,3 +3926,11 @@
void __builtin_vsx_stxvp (v256, unsigned long, const v256 *);
STXVP nothing {mma,pair}
+
+[future]
+ const signed int __builtin_saturate_subtract32 (signed int, signed int);
+ SAT_SUBSI sat_subsi3 {}
+
+[future-64]
+ const signed long __builtin_saturate_subtract64 (signed long, signed long);
+ SAT_SUBDI sat_subdi3 {}
diff --git a/gcc/config/rs6000/rs6000-gen-builtins.cc
b/gcc/conf
[gcc(refs/users/meissner/heads/work204-cmodel)] RFC2686-Add paddis support.
https://gcc.gnu.org/g:4dc84ec5cb3a9e245acf0263e5cde581d14d5b1b
commit 4dc84ec5cb3a9e245acf0263e5cde581d14d5b1b
Author: Michael Meissner
Date: Wed Apr 30 22:39:10 2025 -0400
RFC2686-Add paddis support.
2025-04-30 Michael Meissner
gcc/
* config/rs6000/constraints.md (eU): New constraint.
(eV): Likewise.
* config/rs6000/predicates.md (paddis_operand): New predicate.
(paddis_paddi_operand): Likewise.
(add_operand): Add paddis support.
* config/rs6000/rs6000.cc (num_insns_constant_gpr): Add paddis
support.
(num_insns_constant_multi): Likewise.
(print_operand): Add %B for paddis support.
* config/rs6000/rs6000.h (TARGET_PADDIS): New macro.
(SIGNED_INTEGER_32BIT_P): Likewise.
* config/rs6000/rs6000.md (isa attribute): Add paddis support.
(enabled attribute); Likewise.
(add3): Likewise.
(adddi3 splitter): New splitter for paddis.
(movdi_internal64): Add paddis support.
(movdi splitter): New splitter for paddis.
gcc/testsuite/
* gcc.target/powerpc/prefixed-addis.c: New test.
Diff:
---
gcc/config/rs6000/constraints.md | 10 +++
gcc/config/rs6000/predicates.md | 52 +++-
gcc/config/rs6000/rs6000.cc | 25 ++
gcc/config/rs6000/rs6000.h| 4 +
gcc/config/rs6000/rs6000.md | 96 ---
gcc/testsuite/gcc.target/powerpc/prefixed-addis.c | 24 ++
6 files changed, 197 insertions(+), 14 deletions(-)
diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md
index 3da9ed086810..5440becb6e6c 100644
--- a/gcc/config/rs6000/constraints.md
+++ b/gcc/config/rs6000/constraints.md
@@ -222,6 +222,16 @@
"An IEEE 128-bit constant that can be loaded into VSX registers."
(match_operand 0 "easy_vector_constant_ieee128"))
+(define_constraint "eU"
+ "@internal integer constant that can be loaded with paddis"
+ (and (match_code "const_int")
+ (match_operand 0 "paddis_operand")))
+
+(define_constraint "eV"
+ "@internal integer constant that can be loaded with paddis + paddi"
+ (and (match_code "const_int")
+ (match_operand 0 "paddis_paddi_operand")))
+
;; Floating-point constraints. These two are defined so that insn
;; length attributes can be calculated exactly.
diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md
index c95b4336f062..c206860e4927 100644
--- a/gcc/config/rs6000/predicates.md
+++ b/gcc/config/rs6000/predicates.md
@@ -369,6 +369,53 @@
return SIGNED_INTEGER_34BIT_P (INTVAL (op));
})
+;; Return 1 if op is a 64-bit constant that uses the paddis instruction
+(define_predicate "paddis_operand"
+ (match_code "const_int")
+{
+ if (!TARGET_PADDIS && TARGET_POWERPC64)
+return 0;
+
+ /* If addi, addis, or paddi can handle the number, don't return true. */
+ HOST_WIDE_INT value = INTVAL (op);
+ if (SIGNED_INTEGER_34BIT_P (value))
+return false;
+
+ /* If the number is too large for padds, return false. */
+ if (!SIGNED_INTEGER_32BIT_P (value >> 32))
+return false;
+
+ /* If the bottom 32-bits are non-zero, paddis can't handle it. */
+ if ((value & HOST_WIDE_INT_C(0x)) != 0)
+return false;
+
+ return true;
+})
+
+;; Return 1 if op is a 64-bit constant that needs the paddis instruction and an
+;; addi/addis/paddi instruction combination.
+(define_predicate "paddis_paddi_operand"
+ (match_code "const_int")
+{
+ if (!TARGET_PADDIS && TARGET_POWERPC64)
+return 0;
+
+ /* If addi, addis, or paddi can handle the number, don't return true. */
+ HOST_WIDE_INT value = INTVAL (op);
+ if (SIGNED_INTEGER_34BIT_P (value))
+return false;
+
+ /* If the number is too large for padds, return false. */
+ if (!SIGNED_INTEGER_32BIT_P (value >> 32))
+return false;
+
+ /* If the bottom 32-bits are zero, we can use paddis alone to handle it. */
+ if ((value & HOST_WIDE_INT_C(0x)) == 0)
+return false;
+
+ return true;
+})
+
;; Return 1 if op is a register that is not special.
;; Disallow (SUBREG:SF (REG:SI)) and (SUBREG:SI (REG:SF)) on VSX systems where
;; you need to be careful in moving a SFmode to SImode and vice versa due to
@@ -1113,7 +1160,10 @@
(if_then_else (match_code "const_int")
(match_test "satisfies_constraint_I (op)
|| satisfies_constraint_L (op)
-|| satisfies_constraint_eI (op)")
+|| satisfies_constraint_eI (op)
+|| satisfies_constraint_eU (op)
+|| satisfies_constraint_eV (op)")
+
(match_operand 0 "gpc_reg_operand")))
;; Return 1 if the operand is either a non-special register, or 0, or -1.
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index c06b983f5262..528220f30537 100644
--- a/gcc/con
[gcc(refs/users/meissner/heads/work204-cmodel)] RFC2677-Add xvrlw support.
https://gcc.gnu.org/g:69355b56753c87b76d75a5aba106fa0fdbada049
commit 69355b56753c87b76d75a5aba106fa0fdbada049
Author: Michael Meissner
Date: Wed Apr 30 22:39:32 2025 -0400
RFC2677-Add xvrlw support.
2025-04-30 Michael Meissner
gcc/
* config/rs6000/altivec.md (xvrlw): New insn.
* config/rs6000/rs6000.h (TARGET_XVRLW): New macro.
gcc/testsuite/
* gcc.target/powerpc/vector-rotate-left.c: New test.
Diff:
---
gcc/config/rs6000/altivec.md | 14 +
gcc/config/rs6000/rs6000.h | 3 ++
.../gcc.target/powerpc/vector-rotate-left.c| 34 ++
3 files changed, 51 insertions(+)
diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
index 7edc288a6565..d158cf479d60 100644
--- a/gcc/config/rs6000/altivec.md
+++ b/gcc/config/rs6000/altivec.md
@@ -1982,6 +1982,20 @@
}
[(set_attr "type" "vecperm")])
+;; -mcpu=future adds a vector rotate left word variant. There is no vector
+;; byte/half-word/double-word/quad-word rotate left. This insn occurs before
+;; altivec_vrl and will match for -mcpu=future, while other cpus will
+;; match the generic insn.
+(define_insn "*xvrlw"
+ [(set (match_operand:V4SI 0 "register_operand" "=v,wa")
+ (rotate:V4SI (match_operand:V4SI 1 "register_operand" "v,wa")
+(match_operand:V4SI 2 "register_operand" "v,wa")))]
+ "TARGET_XVRLW"
+ "@
+ vrlw %0,%1,%2
+ xvrlw %x0,%x1,%x2"
+ [(set_attr "type" "vecsimple")])
+
(define_insn "altivec_vrl"
[(set (match_operand:VI2 0 "register_operand" "=v")
(rotate:VI2 (match_operand:VI2 1 "register_operand" "v")
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 1267169de509..76f1f87290f3 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -584,6 +584,9 @@ extern int rs6000_vector_align[];
/* Whether we have PADDIS support. */
#define TARGET_PADDIS TARGET_FUTURE
+/* Whether we have XVRLW support. */
+#define TARGET_XVRLW TARGET_FUTURE
+
/* Whether the various reciprocal divide/square root estimate instructions
exist, and whether we should automatically generate code for the instruction
by default. */
diff --git a/gcc/testsuite/gcc.target/powerpc/vector-rotate-left.c
b/gcc/testsuite/gcc.target/powerpc/vector-rotate-left.c
new file mode 100644
index ..5a5f37755077
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vector-rotate-left.c
@@ -0,0 +1,34 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_future_ok } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-mdejagnu-cpu=future -O2" } */
+
+/* Test whether the xvrl (vector word rotate left using VSX registers insead of
+ Altivec registers is generated. */
+
+#include
+
+typedef vector unsigned int v4si_t;
+
+v4si_t
+rotl_v4si_scalar (v4si_t x, unsigned long n)
+{
+ __asm__ (" # %x0" : "+f" (x));
+ return (x << n) | (x >> (32 - n)); /* xvrlw. */
+}
+
+v4si_t
+rotr_v4si_scalar (v4si_t x, unsigned long n)
+{
+ __asm__ (" # %x0" : "+f" (x));
+ return (x >> n) | (x << (32 - n)); /* xvrlw. */
+}
+
+v4si_t
+rotl_v4si_vector (v4si_t x, v4si_t y)
+{
+ __asm__ (" # %x0" : "+f" (x)); /* xvrlw. */
+ return vec_rl (x, y);
+}
+
+/* { dg-final { scan-assembler-times {\mxvrlw\M} 3 } } */
[gcc r15-9615] c: Fix up RAW_DATA_CST handling in check_constexpr_init [PR120057]
https://gcc.gnu.org/g:14c2a12748eea0eef714a125cb1a6c834fd60560
commit r15-9615-g14c2a12748eea0eef714a125cb1a6c834fd60560
Author: Jakub Jelinek
Date: Fri May 2 21:19:05 2025 +0200
c: Fix up RAW_DATA_CST handling in check_constexpr_init [PR120057]
The pr120057-1.c testcase is incorrectly rejected since
r15-4377 (and for a while it also ICEd after the error), i.e.
the optimization of large C initializers using RAW_DATA_CST.
Similarly, the embed-18.c testcase is incorrectly rejected since
the embed support has been introduced and RAW_DATA_CST used for that.
The callers of check_constexpr_init (store_init_value and
output_init_element) compute int_const_expr as
int_const_expr = (TREE_CODE (init) == INTEGER_CST
&& !TREE_OVERFLOW (init)
&& INTEGRAL_TYPE_P (TREE_TYPE (init)));
but that is only passed through down to check_constexpr_init.
I think tweaking those 2 callers to also allow RAW_DATA_CST for
int_const_expr when check_constexpr_init needs top special case it
no matter what would be larger, so the patch just changes
check_constexpr_init to deal with RAW_DATA_CST in the initializers.
For TYPE_UNSIGNED char precision integral types RAW_DATA_CST is
always valid, for !TYPE_UNSIGNED we need to check for 128-255 values
being turned into negative ones.
2025-05-02 Jakub Jelinek
PR c/120057
* c-typeck.cc (check_constexpr_init): Handle RAW_DATA_CST.
* gcc.dg/cpp/embed-18.c: New test.
* gcc.dg/pr120057-1.c: New test.
* gcc.dg/pr120057-2.c: New test.
(cherry picked from commit e81f2f4855876c5d85ab9870c5a150ee1a59ee73)
Diff:
---
gcc/c/c-typeck.cc | 20 ++--
gcc/testsuite/gcc.dg/cpp/embed-18.c | 7 +++
gcc/testsuite/gcc.dg/pr120057-1.c | 18 ++
gcc/testsuite/gcc.dg/pr120057-2.c | 11 +++
4 files changed, 54 insertions(+), 2 deletions(-)
diff --git a/gcc/c/c-typeck.cc b/gcc/c/c-typeck.cc
index 55d896e02df5..ea83451b06b8 100644
--- a/gcc/c/c-typeck.cc
+++ b/gcc/c/c-typeck.cc
@@ -9153,8 +9153,24 @@ check_constexpr_init (location_t loc, tree type, tree
init,
/* The initializer must be an integer constant expression,
representable in the target type. */
if (!int_const_expr)
- error_at (loc, "% integer initializer is not an "
- "integer constant expression");
+ {
+ if (TREE_CODE (init) == RAW_DATA_CST
+ && TYPE_PRECISION (type) == CHAR_BIT)
+ {
+ if (!TYPE_UNSIGNED (type))
+ for (unsigned int i = 0;
+i < (unsigned) RAW_DATA_LENGTH (init); ++i)
+ if (RAW_DATA_SCHAR_ELT (init, i) < 0)
+ {
+ error_at (loc, "% initializer not "
+ "representable in type of object");
+ break;
+ }
+ }
+ else
+ error_at (loc, "% integer initializer is not an "
+ "integer constant expression");
+ }
else if (!int_fits_type_p (init, type))
error_at (loc, "% initializer not representable in "
"type of object");
diff --git a/gcc/testsuite/gcc.dg/cpp/embed-18.c
b/gcc/testsuite/gcc.dg/cpp/embed-18.c
new file mode 100644
index ..198a6db55e19
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/cpp/embed-18.c
@@ -0,0 +1,7 @@
+/* PR c/120057 */
+/* { dg-do compile } */
+/* { dg-options "-std=c23 --embed-dir=${srcdir}/c-c++-common/cpp/embed-dir" }
*/
+
+constexpr unsigned char magna_carta[] = {
+#embed
+};
diff --git a/gcc/testsuite/gcc.dg/pr120057-1.c
b/gcc/testsuite/gcc.dg/pr120057-1.c
new file mode 100644
index ..8832de66a7f4
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/pr120057-1.c
@@ -0,0 +1,18 @@
+/* PR c/120057 */
+/* { dg-do compile } */
+/* { dg-options "-std=c23" } */
+
+constexpr char foo[65] = {
+ 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16,
+ 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16,
+ 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16,
+ 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16,
+ 1
+};
+constexpr char bar[66] = {
+ 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16,
+ 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16,
+ 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16,
+ 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16,
+ 1, 2
+};
diff --git a/gcc/testsuite/gcc.dg/pr120057-2.c
b/gcc/testsuite/gcc.dg/pr120057-2.c
new file mode 100644
index ..1372baf3dddc
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/pr120057-2.c
@@ -0,0 +1,11 @@
+/* PR c/120057 */
+/* { dg-do compile } */
+/* { dg-options "-std=c23" } */
+
+constexpr signed char foo[65] = {
+ 1, 2, 3, 4, 5, 6, 7, 8, 9, 129, 11, 12, 13, 14, 15, 16, /* { dg-error
"'constexpr'
[gcc r16-364] c: Fix up RAW_DATA_CST handling in check_constexpr_init [PR120057]
https://gcc.gnu.org/g:e81f2f4855876c5d85ab9870c5a150ee1a59ee73
commit r16-364-ge81f2f4855876c5d85ab9870c5a150ee1a59ee73
Author: Jakub Jelinek
Date: Fri May 2 21:19:05 2025 +0200
c: Fix up RAW_DATA_CST handling in check_constexpr_init [PR120057]
The pr120057-1.c testcase is incorrectly rejected since
r15-4377 (and for a while it also ICEd after the error), i.e.
the optimization of large C initializers using RAW_DATA_CST.
Similarly, the embed-18.c testcase is incorrectly rejected since
the embed support has been introduced and RAW_DATA_CST used for that.
The callers of check_constexpr_init (store_init_value and
output_init_element) compute int_const_expr as
int_const_expr = (TREE_CODE (init) == INTEGER_CST
&& !TREE_OVERFLOW (init)
&& INTEGRAL_TYPE_P (TREE_TYPE (init)));
but that is only passed through down to check_constexpr_init.
I think tweaking those 2 callers to also allow RAW_DATA_CST for
int_const_expr when check_constexpr_init needs top special case it
no matter what would be larger, so the patch just changes
check_constexpr_init to deal with RAW_DATA_CST in the initializers.
For TYPE_UNSIGNED char precision integral types RAW_DATA_CST is
always valid, for !TYPE_UNSIGNED we need to check for 128-255 values
being turned into negative ones.
2025-05-02 Jakub Jelinek
PR c/120057
* c-typeck.cc (check_constexpr_init): Handle RAW_DATA_CST.
* gcc.dg/cpp/embed-18.c: New test.
* gcc.dg/pr120057-1.c: New test.
* gcc.dg/pr120057-2.c: New test.
Diff:
---
gcc/c/c-typeck.cc | 20 ++--
gcc/testsuite/gcc.dg/cpp/embed-18.c | 7 +++
gcc/testsuite/gcc.dg/pr120057-1.c | 18 ++
gcc/testsuite/gcc.dg/pr120057-2.c | 11 +++
4 files changed, 54 insertions(+), 2 deletions(-)
diff --git a/gcc/c/c-typeck.cc b/gcc/c/c-typeck.cc
index 05fb129ada8d..0e1f842e22d3 100644
--- a/gcc/c/c-typeck.cc
+++ b/gcc/c/c-typeck.cc
@@ -9143,8 +9143,24 @@ check_constexpr_init (location_t loc, tree type, tree
init,
/* The initializer must be an integer constant expression,
representable in the target type. */
if (!int_const_expr)
- error_at (loc, "% integer initializer is not an "
- "integer constant expression");
+ {
+ if (TREE_CODE (init) == RAW_DATA_CST
+ && TYPE_PRECISION (type) == CHAR_BIT)
+ {
+ if (!TYPE_UNSIGNED (type))
+ for (unsigned int i = 0;
+i < (unsigned) RAW_DATA_LENGTH (init); ++i)
+ if (RAW_DATA_SCHAR_ELT (init, i) < 0)
+ {
+ error_at (loc, "% initializer not "
+ "representable in type of object");
+ break;
+ }
+ }
+ else
+ error_at (loc, "% integer initializer is not an "
+ "integer constant expression");
+ }
else if (!int_fits_type_p (init, type))
error_at (loc, "% initializer not representable in "
"type of object");
diff --git a/gcc/testsuite/gcc.dg/cpp/embed-18.c
b/gcc/testsuite/gcc.dg/cpp/embed-18.c
new file mode 100644
index ..198a6db55e19
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/cpp/embed-18.c
@@ -0,0 +1,7 @@
+/* PR c/120057 */
+/* { dg-do compile } */
+/* { dg-options "-std=c23 --embed-dir=${srcdir}/c-c++-common/cpp/embed-dir" }
*/
+
+constexpr unsigned char magna_carta[] = {
+#embed
+};
diff --git a/gcc/testsuite/gcc.dg/pr120057-1.c
b/gcc/testsuite/gcc.dg/pr120057-1.c
new file mode 100644
index ..8832de66a7f4
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/pr120057-1.c
@@ -0,0 +1,18 @@
+/* PR c/120057 */
+/* { dg-do compile } */
+/* { dg-options "-std=c23" } */
+
+constexpr char foo[65] = {
+ 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16,
+ 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16,
+ 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16,
+ 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16,
+ 1
+};
+constexpr char bar[66] = {
+ 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16,
+ 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16,
+ 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16,
+ 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16,
+ 1, 2
+};
diff --git a/gcc/testsuite/gcc.dg/pr120057-2.c
b/gcc/testsuite/gcc.dg/pr120057-2.c
new file mode 100644
index ..1372baf3dddc
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/pr120057-2.c
@@ -0,0 +1,11 @@
+/* PR c/120057 */
+/* { dg-do compile } */
+/* { dg-options "-std=c23" } */
+
+constexpr signed char foo[65] = {
+ 1, 2, 3, 4, 5, 6, 7, 8, 9, 129, 11, 12, 13, 14, 15, 16, /* { dg-error
"'constexpr' initializer not representable in type of object" } */
+ 1, 2, 3, 4, 5, 6, 7, 8
[gcc r16-359] Revert "[PATCH 30/61] MSA: Make MSA and microMIPS R5 unsupported"
https://gcc.gnu.org/g:a4a726ca9485b07fb56a1442b5f9e5679944ed06
commit r16-359-ga4a726ca9485b07fb56a1442b5f9e5679944ed06
Author: Jeff Law
Date: Fri May 2 08:12:23 2025 -0600
Revert "[PATCH 30/61] MSA: Make MSA and microMIPS R5 unsupported"
This reverts commit 727a43e0a66052235706379239359807230054e0.
Diff:
---
gcc/config/mips/mips.cc | 3 ---
1 file changed, 3 deletions(-)
diff --git a/gcc/config/mips/mips.cc b/gcc/config/mips/mips.cc
index 0d3d0263f2d4..24a28dcf817f 100644
--- a/gcc/config/mips/mips.cc
+++ b/gcc/config/mips/mips.cc
@@ -20678,9 +20678,6 @@ mips_option_override (void)
"-mcompact-branches=never");
}
- if (is_micromips && TARGET_MSA)
-error ("unsupported combination: %s", "-mmicromips -mmsa");
-
/* Require explicit relocs for MIPS R6 onwards. This enables simplification
of the compact branch and jump support through the backend. */
if (!TARGET_EXPLICIT_RELOCS && mips_isa_rev >= 6)
[gcc r16-360] libsanitizer: Fix build with glibc 2.42
https://gcc.gnu.org/g:1789c57dc97ea2f9819ef89e28bf17208b6208e7
commit r16-360-g1789c57dc97ea2f9819ef89e28bf17208b6208e7
Author: Florian Weimer
Date: Fri May 2 17:41:43 2025 +0200
libsanitizer: Fix build with glibc 2.42
The termio structure will be removed from glibc 2.42. It has
been deprecated since the late 80s/early 90s.
Cherry-picked from LLVM commit 59978b21ad9c65276ee8e14f26759691b8a65763
("[sanitizer_common] Remove interceptors for deprecated struct termio
(#137403)").
Co-Authored-By: Tom Stellard
libsanitizer/
* sanitizer_common/sanitizer_common_interceptors_ioctl.inc: Cherry
picked from LLVM commit 59978b21ad9c65276ee8e14f26759691b8a65763.
* sanitizer_common/sanitizer_platform_limits_posix.cpp: Likewise.
* sanitizer_common/sanitizer_platform_limits_posix.h: Likewise.
Diff:
---
.../sanitizer_common/sanitizer_common_interceptors_ioctl.inc | 8
libsanitizer/sanitizer_common/sanitizer_platform_limits_posix.cpp | 3 ---
libsanitizer/sanitizer_common/sanitizer_platform_limits_posix.h | 1 -
3 files changed, 12 deletions(-)
diff --git
a/libsanitizer/sanitizer_common/sanitizer_common_interceptors_ioctl.inc
b/libsanitizer/sanitizer_common/sanitizer_common_interceptors_ioctl.inc
index 49ec4097c900..dda11daa77f4 100644
--- a/libsanitizer/sanitizer_common/sanitizer_common_interceptors_ioctl.inc
+++ b/libsanitizer/sanitizer_common/sanitizer_common_interceptors_ioctl.inc
@@ -338,17 +338,9 @@ static void ioctl_table_fill() {
_(SOUND_PCM_WRITE_CHANNELS, WRITE, sizeof(int));
_(SOUND_PCM_WRITE_FILTER, WRITE, sizeof(int));
_(TCFLSH, NONE, 0);
-#if SANITIZER_GLIBC
- _(TCGETA, WRITE, struct_termio_sz);
-#endif
_(TCGETS, WRITE, struct_termios_sz);
_(TCSBRK, NONE, 0);
_(TCSBRKP, NONE, 0);
-#if SANITIZER_GLIBC
- _(TCSETA, READ, struct_termio_sz);
- _(TCSETAF, READ, struct_termio_sz);
- _(TCSETAW, READ, struct_termio_sz);
-#endif
_(TCSETS, READ, struct_termios_sz);
_(TCSETSF, READ, struct_termios_sz);
_(TCSETSW, READ, struct_termios_sz);
diff --git a/libsanitizer/sanitizer_common/sanitizer_platform_limits_posix.cpp
b/libsanitizer/sanitizer_common/sanitizer_platform_limits_posix.cpp
index c87d5ef42c92..7bbc6f2edac2 100644
--- a/libsanitizer/sanitizer_common/sanitizer_platform_limits_posix.cpp
+++ b/libsanitizer/sanitizer_common/sanitizer_platform_limits_posix.cpp
@@ -485,9 +485,6 @@ unsigned struct_ElfW_Phdr_sz = sizeof(Elf_Phdr);
unsigned struct_input_id_sz = sizeof(struct input_id);
unsigned struct_mtpos_sz = sizeof(struct mtpos);
unsigned struct_rtentry_sz = sizeof(struct rtentry);
-#if SANITIZER_GLIBC || SANITIZER_ANDROID
- unsigned struct_termio_sz = sizeof(struct termio);
-#endif
unsigned struct_vt_consize_sz = sizeof(struct vt_consize);
unsigned struct_vt_sizes_sz = sizeof(struct vt_sizes);
unsigned struct_vt_stat_sz = sizeof(struct vt_stat);
diff --git a/libsanitizer/sanitizer_common/sanitizer_platform_limits_posix.h
b/libsanitizer/sanitizer_common/sanitizer_platform_limits_posix.h
index c07f7cd0b0d0..a80df656826e 100644
--- a/libsanitizer/sanitizer_common/sanitizer_platform_limits_posix.h
+++ b/libsanitizer/sanitizer_common/sanitizer_platform_limits_posix.h
@@ -1029,7 +1029,6 @@ extern unsigned struct_hd_geometry_sz;
extern unsigned struct_input_absinfo_sz;
extern unsigned struct_input_id_sz;
extern unsigned struct_mtpos_sz;
-extern unsigned struct_termio_sz;
extern unsigned struct_vt_consize_sz;
extern unsigned struct_vt_sizes_sz;
extern unsigned struct_vt_stat_sz;
[gcc r15-9614] libsanitizer: Fix build with glibc 2.42
https://gcc.gnu.org/g:d32ece49d32b00448d967e7dbc6900fb25cbc775
commit r15-9614-gd32ece49d32b00448d967e7dbc6900fb25cbc775
Author: Florian Weimer
Date: Fri May 2 17:41:43 2025 +0200
libsanitizer: Fix build with glibc 2.42
The termio structure will be removed from glibc 2.42. It has
been deprecated since the late 80s/early 90s.
Cherry-picked from LLVM commit 59978b21ad9c65276ee8e14f26759691b8a65763
("[sanitizer_common] Remove interceptors for deprecated struct termio
(#137403)").
Co-Authored-By: Tom Stellard
libsanitizer/
* sanitizer_common/sanitizer_common_interceptors_ioctl.inc: Cherry
picked from LLVM commit 59978b21ad9c65276ee8e14f26759691b8a65763.
* sanitizer_common/sanitizer_platform_limits_posix.cpp: Likewise.
* sanitizer_common/sanitizer_platform_limits_posix.h: Likewise.
Diff:
---
.../sanitizer_common/sanitizer_common_interceptors_ioctl.inc | 8
libsanitizer/sanitizer_common/sanitizer_platform_limits_posix.cpp | 3 ---
libsanitizer/sanitizer_common/sanitizer_platform_limits_posix.h | 1 -
3 files changed, 12 deletions(-)
diff --git
a/libsanitizer/sanitizer_common/sanitizer_common_interceptors_ioctl.inc
b/libsanitizer/sanitizer_common/sanitizer_common_interceptors_ioctl.inc
index 49ec4097c900..dda11daa77f4 100644
--- a/libsanitizer/sanitizer_common/sanitizer_common_interceptors_ioctl.inc
+++ b/libsanitizer/sanitizer_common/sanitizer_common_interceptors_ioctl.inc
@@ -338,17 +338,9 @@ static void ioctl_table_fill() {
_(SOUND_PCM_WRITE_CHANNELS, WRITE, sizeof(int));
_(SOUND_PCM_WRITE_FILTER, WRITE, sizeof(int));
_(TCFLSH, NONE, 0);
-#if SANITIZER_GLIBC
- _(TCGETA, WRITE, struct_termio_sz);
-#endif
_(TCGETS, WRITE, struct_termios_sz);
_(TCSBRK, NONE, 0);
_(TCSBRKP, NONE, 0);
-#if SANITIZER_GLIBC
- _(TCSETA, READ, struct_termio_sz);
- _(TCSETAF, READ, struct_termio_sz);
- _(TCSETAW, READ, struct_termio_sz);
-#endif
_(TCSETS, READ, struct_termios_sz);
_(TCSETSF, READ, struct_termios_sz);
_(TCSETSW, READ, struct_termios_sz);
diff --git a/libsanitizer/sanitizer_common/sanitizer_platform_limits_posix.cpp
b/libsanitizer/sanitizer_common/sanitizer_platform_limits_posix.cpp
index c87d5ef42c92..7bbc6f2edac2 100644
--- a/libsanitizer/sanitizer_common/sanitizer_platform_limits_posix.cpp
+++ b/libsanitizer/sanitizer_common/sanitizer_platform_limits_posix.cpp
@@ -485,9 +485,6 @@ unsigned struct_ElfW_Phdr_sz = sizeof(Elf_Phdr);
unsigned struct_input_id_sz = sizeof(struct input_id);
unsigned struct_mtpos_sz = sizeof(struct mtpos);
unsigned struct_rtentry_sz = sizeof(struct rtentry);
-#if SANITIZER_GLIBC || SANITIZER_ANDROID
- unsigned struct_termio_sz = sizeof(struct termio);
-#endif
unsigned struct_vt_consize_sz = sizeof(struct vt_consize);
unsigned struct_vt_sizes_sz = sizeof(struct vt_sizes);
unsigned struct_vt_stat_sz = sizeof(struct vt_stat);
diff --git a/libsanitizer/sanitizer_common/sanitizer_platform_limits_posix.h
b/libsanitizer/sanitizer_common/sanitizer_platform_limits_posix.h
index c07f7cd0b0d0..a80df656826e 100644
--- a/libsanitizer/sanitizer_common/sanitizer_platform_limits_posix.h
+++ b/libsanitizer/sanitizer_common/sanitizer_platform_limits_posix.h
@@ -1029,7 +1029,6 @@ extern unsigned struct_hd_geometry_sz;
extern unsigned struct_input_absinfo_sz;
extern unsigned struct_input_id_sz;
extern unsigned struct_mtpos_sz;
-extern unsigned struct_termio_sz;
extern unsigned struct_vt_consize_sz;
extern unsigned struct_vt_sizes_sz;
extern unsigned struct_vt_stat_sz;
[gcc(refs/users/mikael/heads/refactor_descriptor_v05)] Correction régression maxval_char_2
https://gcc.gnu.org/g:2b847cde690bfe27d5dfc5a601117b76fbf19f34
commit 2b847cde690bfe27d5dfc5a601117b76fbf19f34
Author: Mikael Morin
Date: Wed Apr 30 22:56:30 2025 +0200
Correction régression maxval_char_2
Diff:
---
libgfortran/io/transfer.c | 24
1 file changed, 24 insertions(+)
diff --git a/libgfortran/io/transfer.c b/libgfortran/io/transfer.c
index 805bdcd8067b..043ca3606b2a 100644
--- a/libgfortran/io/transfer.c
+++ b/libgfortran/io/transfer.c
@@ -3934,6 +3934,18 @@ next_record_r (st_parameter_dt *dtp, int done)
if (!done && finished)
hit_eof (dtp);
+ if (unlikely (is_char4_unit(dtp)))
+ {
+ if (unlikely (record % sizeof (gfc_char4_t) != 0))
+ {
+ generate_error (&dtp->common,
+ LIBERROR_MISALIGNED_INTERNAL_UNIT, NULL);
+ break;
+ }
+ else
+ record /= sizeof (gfc_char4_t);
+ }
+
/* Now seek to this record. */
if (sseek (dtp->u.p.current_unit->s, record, SEEK_SET) < 0)
{
@@ -4270,6 +4282,18 @@ next_record_w (st_parameter_dt *dtp, int done)
if (finished)
dtp->u.p.current_unit->endfile = AT_ENDFILE;
+ if (unlikely (is_char4_unit(dtp)))
+ {
+ if (unlikely (record % sizeof (gfc_char4_t) != 0))
+ {
+ generate_error (&dtp->common,
+ LIBERROR_MISALIGNED_INTERNAL_UNIT, NULL);
+ break;
+ }
+ else
+ record /= sizeof (gfc_char4_t);
+ }
+
/* Now seek to this record */
if (sseek (dtp->u.p.current_unit->s, record, SEEK_SET) < 0)
{
[gcc(refs/users/mikael/heads/refactor_descriptor_v05)] Correction régressions realloc_on_assign_{10,11}
https://gcc.gnu.org/g:39a90d2eeaaf0c6ec77edf4e63d60c8f90fefa49
commit 39a90d2eeaaf0c6ec77edf4e63d60c8f90fefa49
Author: Mikael Morin
Date: Fri May 2 14:40:25 2025 +0200
Correction régressions realloc_on_assign_{10,11}
Diff:
---
gcc/fortran/trans-descriptor.cc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/fortran/trans-descriptor.cc b/gcc/fortran/trans-descriptor.cc
index b58c90e073af..5f40e0e5f8c2 100644
--- a/gcc/fortran/trans-descriptor.cc
+++ b/gcc/fortran/trans-descriptor.cc
@@ -2458,7 +2458,7 @@ gfc_conv_shift_descriptor (stmtblock_t *block, tree dest,
tree src,
int rank, tree zero_cond)
{
conv_shift_descriptor (block, src, dest, rank,
-cond_descr_lb (src, zero_cond));
+cond_descr_lb (dest, zero_cond));
}
[gcc(refs/users/mikael/heads/refactor_descriptor_v05)] Revert "Correction régression realloc_on_assign_10"
https://gcc.gnu.org/g:7ec5f152e6183b39072a74faa6c7e91c7ef6efbc
commit 7ec5f152e6183b39072a74faa6c7e91c7ef6efbc
Author: Mikael Morin
Date: Fri May 2 12:08:51 2025 +0200
Revert "Correction régression realloc_on_assign_10"
This reverts commit dc0220b64f510e20fb6316aeb2cfc7d3f5b6fda7.
Diff:
---
gcc/fortran/trans-descriptor.cc | 32 +---
gcc/fortran/trans-descriptor.h | 2 +-
gcc/fortran/trans-expr.cc | 2 +-
3 files changed, 31 insertions(+), 5 deletions(-)
diff --git a/gcc/fortran/trans-descriptor.cc b/gcc/fortran/trans-descriptor.cc
index 03a6d71bbabf..b58c90e073af 100644
--- a/gcc/fortran/trans-descriptor.cc
+++ b/gcc/fortran/trans-descriptor.cc
@@ -2155,10 +2155,27 @@ conv_shift_descriptor (stmtblock_t *block, tree desc,
int rank,
}
-void
-gfc_conv_shift_descriptor (stmtblock_t* block, tree dest, tree src, int rank)
+class cond_descr_lb : public lb_info_base
+{
+ tree desc;
+ tree cond;
+public:
+ cond_descr_lb (tree arg_desc, tree arg_cond)
+: desc (arg_desc), cond (arg_cond) { }
+
+ virtual tree lower_bound (stmtblock_t *block, int dim) const;
+ virtual bool zero_based_src () const { return true; }
+};
+
+
+tree
+cond_descr_lb::lower_bound (stmtblock_t *block ATTRIBUTE_UNUSED, int dim) const
{
- conv_shift_descriptor (block, src, dest, rank, unset_lb ());
+ tree lbound = gfc_conv_descriptor_lbound_get (desc, gfc_rank_cst[dim]);
+ lbound = fold_build3_loc (input_location, COND_EXPR,
+ gfc_array_index_type, cond,
+ gfc_index_one_node, lbound);
+ return lbound;
}
@@ -2436,6 +2453,15 @@ gfc_conv_remap_descriptor (stmtblock_t *block, tree
dest, tree src,
}
+void
+gfc_conv_shift_descriptor (stmtblock_t *block, tree dest, tree src,
+ int rank, tree zero_cond)
+{
+ conv_shift_descriptor (block, src, dest, rank,
+cond_descr_lb (src, zero_cond));
+}
+
+
void
gfc_copy_descriptor (stmtblock_t *block, tree dest, tree src,
gfc_expr *src_expr, bool subref)
diff --git a/gcc/fortran/trans-descriptor.h b/gcc/fortran/trans-descriptor.h
index 3244359c176e..e431aeb9a7a3 100644
--- a/gcc/fortran/trans-descriptor.h
+++ b/gcc/fortran/trans-descriptor.h
@@ -81,7 +81,7 @@ tree gfc_get_cfi_dim_sm (tree, tree);
tree gfc_build_desc_array_type (tree, tree, int, tree *, tree *);
void gfc_conv_shift_descriptor (stmtblock_t*, tree, const gfc_array_ref &);
void gfc_conv_shift_descriptor (stmtblock_t*, tree, int);
-void gfc_conv_shift_descriptor (stmtblock_t*, tree, tree, int);
+void gfc_conv_shift_descriptor (stmtblock_t*, tree, tree, int, tree);
void gfc_conv_shift_descriptor_subarray (stmtblock_t*, tree, gfc_expr *,
gfc_expr *);
void gfc_conv_shift_descriptor (stmtblock_t *, tree, int, tree *, tree *);
diff --git a/gcc/fortran/trans-expr.cc b/gcc/fortran/trans-expr.cc
index c070d417994a..f2727f2ea071 100644
--- a/gcc/fortran/trans-expr.cc
+++ b/gcc/fortran/trans-expr.cc
@@ -11487,7 +11487,7 @@ fcncall_realloc_result (gfc_se *se, int rank, tree
dtype)
/* Now reset the bounds returned from the function call to bounds based
on the lhs lbounds, except where the lhs is not allocated or the shapes
of 'variable and 'expr' are different. Set the offset accordingly. */
- gfc_conv_shift_descriptor (&se->post, desc, res_desc, rank);
+ gfc_conv_shift_descriptor (&se->post, desc, res_desc, rank, zero_cond);
}
[gcc(refs/users/mikael/heads/refactor_descriptor_v05)] Correction régression secnds
https://gcc.gnu.org/g:0d8c1cf1c1f803bb6798df302ae502fbb2f49cfd commit 0d8c1cf1c1f803bb6798df302ae502fbb2f49cfd Author: Mikael Morin Date: Fri May 2 11:23:02 2025 +0200 Correction régression secnds Diff: --- libgfortran/intrinsics/date_and_time.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/libgfortran/intrinsics/date_and_time.c b/libgfortran/intrinsics/date_and_time.c index f8e2e236801d..119122c84a45 100644 --- a/libgfortran/intrinsics/date_and_time.c +++ b/libgfortran/intrinsics/date_and_time.c @@ -316,10 +316,10 @@ secnds (GFC_REAL_4 *x) gfc_array_i4 *avalues = xmalloc (sizeof (gfc_array_i4) + sizeof (descriptor_dimension)); avalues->base_addr = &values[0]; - GFC_DESCRIPTOR_DTYPE (avalues).type = BT_REAL; + GFC_DESCRIPTOR_DTYPE (avalues).type = BT_INTEGER; GFC_DESCRIPTOR_DTYPE (avalues).elem_len = 4; GFC_DESCRIPTOR_DTYPE (avalues).rank = 1; - GFC_DESCRIPTOR_DIMENSION_SET(avalues, 0, 0, 7, 1); + GFC_DESCRIPTOR_DIMENSION_SET(avalues, 0, 0, 7, 4); date_and_time (NULL, NULL, NULL, avalues, 0, 0, 0);
[gcc(refs/users/mikael/heads/refactor_descriptor_v05)] Correction régression char_unpack_2
https://gcc.gnu.org/g:e5551d0f7ac3f36e207a6f71e6be78c0ffa4707e
commit e5551d0f7ac3f36e207a6f71e6be78c0ffa4707e
Author: Mikael Morin
Date: Wed Apr 30 19:54:14 2025 +0200
Correction régression char_unpack_2
Diff:
---
libgfortran/intrinsics/unpack_generic.c | 14 --
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/libgfortran/intrinsics/unpack_generic.c
b/libgfortran/intrinsics/unpack_generic.c
index 21624ce44b92..42842972f7ae 100644
--- a/libgfortran/intrinsics/unpack_generic.c
+++ b/libgfortran/intrinsics/unpack_generic.c
@@ -121,9 +121,6 @@ unpack_internal (gfc_array_char *ret, const gfc_array_char
*vector,
spacing);
extent[n] = GFC_DESCRIPTOR_EXTENT(ret,n);
empty = empty || extent[n] <= 0;
- rstride[n] = GFC_DESCRIPTOR_SPACING(ret, n);
- fstride[n] = GFC_DESCRIPTOR_SPACING(field, n);
- mstride[n] = GFC_DESCRIPTOR_SPACING(mask, n);
rs *= extent[n];
spacing *= extent[n];
}
@@ -138,12 +135,17 @@ unpack_internal (gfc_array_char *ret, const
gfc_array_char *vector,
count[n] = 0;
extent[n] = GFC_DESCRIPTOR_EXTENT(ret,n);
empty = empty || extent[n] <= 0;
- rstride[n] = GFC_DESCRIPTOR_SPACING(ret, n);
- fstride[n] = GFC_DESCRIPTOR_SPACING(field, n);
- mstride[n] = GFC_DESCRIPTOR_SPACING(mask, n);
}
}
+ bool scalar_field = GFC_DESCRIPTOR_RANK (field) == 0;
+ for (n = 0; n < dim; n++)
+{
+ rstride[n] = GFC_DESCRIPTOR_SPACING(ret, n);
+ mstride[n] = GFC_DESCRIPTOR_SPACING(mask, n);
+ fstride[n] = scalar_field ? 0 : GFC_DESCRIPTOR_SPACING(field, n);
+}
+
if (empty)
return;
[gcc(refs/users/mikael/heads/refactor_descriptor_v05)] Correction régression ISO_Fortran_binding_4
https://gcc.gnu.org/g:cc687fb345eb43f7b6106b53780c8718556ff56d
commit cc687fb345eb43f7b6106b53780c8718556ff56d
Author: Mikael Morin
Date: Fri May 2 15:47:25 2025 +0200
Correction régression ISO_Fortran_binding_4
Diff:
---
gcc/fortran/trans-descriptor.cc | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/gcc/fortran/trans-descriptor.cc b/gcc/fortran/trans-descriptor.cc
index dff7bbb87d83..f5401dc39294 100644
--- a/gcc/fortran/trans-descriptor.cc
+++ b/gcc/fortran/trans-descriptor.cc
@@ -2843,7 +2843,9 @@ gfc_set_gfc_from_cfi (stmtblock_t *unconditional_block,
tmp = fold_build2_loc (input_location, MULT_EXPR, TREE_TYPE (tmp2),
tmp2, tmp);
tmp = build3_loc (input_location, COND_EXPR, gfc_array_index_type, cond,
- gfc_get_cfi_desc_elem_len (cfi), tmp);
+ fold_convert (gfc_array_index_type,
+ gfc_get_cfi_desc_elem_len (cfi)),
+ tmp);
}
else
{
[gcc(refs/users/mikael/heads/refactor_descriptor_v05)] Correction régression char_pack_2
https://gcc.gnu.org/g:388f4efea3f0ccfaae4e8e8ddcd02c0028cb2b87 commit 388f4efea3f0ccfaae4e8e8ddcd02c0028cb2b87 Author: Mikael Morin Date: Fri May 2 14:58:17 2025 +0200 Correction régression char_pack_2 Diff: --- libgfortran/intrinsics/pack_generic.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libgfortran/intrinsics/pack_generic.c b/libgfortran/intrinsics/pack_generic.c index 65128b6ea02f..00b065742710 100644 --- a/libgfortran/intrinsics/pack_generic.c +++ b/libgfortran/intrinsics/pack_generic.c @@ -535,7 +535,7 @@ pack_s_internal (gfc_array_char *ret, const gfc_array_char *array, } /* Setup the array descriptor. */ - GFC_DESCRIPTOR_DIMENSION_SET(ret,0,0,total-1,1); + GFC_DESCRIPTOR_DIMENSION_SET(ret,0,0,total-1,size); ret->offset = 0;
[gcc(refs/users/mikael/heads/refactor_descriptor_v05)] Correction régression class_allocate_19
https://gcc.gnu.org/g:54cd73b0a54be8461d47ba705ea7c4a39ad7dc61
commit 54cd73b0a54be8461d47ba705ea7c4a39ad7dc61
Author: Mikael Morin
Date: Fri May 2 15:31:33 2025 +0200
Correction régression class_allocate_19
Diff:
---
gcc/fortran/trans-array.cc | 17 +
gcc/fortran/trans-descriptor.cc | 5 +++--
2 files changed, 16 insertions(+), 6 deletions(-)
diff --git a/gcc/fortran/trans-array.cc b/gcc/fortran/trans-array.cc
index b3c5aff9d303..a5b1c52719b7 100644
--- a/gcc/fortran/trans-array.cc
+++ b/gcc/fortran/trans-array.cc
@@ -5512,8 +5512,8 @@ gfc_set_delta (gfc_loopinfo *loop)
static tree
-descriptor_element_size (tree descriptor, tree expr3_elem_size,
-gfc_expr *expr3)
+descriptor_element_size (tree descriptor, gfc_typespec *explicit_ts,
+tree expr3_elem_size, gfc_expr *expr3)
{
tree type;
tree tmp;
@@ -5544,7 +5544,15 @@ descriptor_element_size (tree descriptor, tree
expr3_elem_size,
}
}
else
-tmp = TYPE_SIZE_UNIT (gfc_get_element_type (type));
+{
+ tree element_type;
+ if (explicit_ts)
+ element_type = gfc_typenode_for_spec (explicit_ts);
+ else
+ element_type = gfc_get_element_type (type);
+
+ tmp = TYPE_SIZE_UNIT (element_type);
+}
/* Convert to size_t. */
return fold_convert (size_type_node, tmp);
@@ -5778,7 +5786,8 @@ gfc_array_allocate (gfc_se * se, gfc_expr * expr, tree
status, tree errmsg,
gfc_init_block (&set_descriptor_block);
- element_size = descriptor_element_size (se->expr, expr3_elem_size, expr3);
+ element_size = descriptor_element_size (se->expr, explicit_ts,
+ expr3_elem_size, expr3);
tree empty_array_cond;
/* Take the corank only from the actual ref and not from the coref. The
diff --git a/gcc/fortran/trans-descriptor.cc b/gcc/fortran/trans-descriptor.cc
index 5f40e0e5f8c2..dff7bbb87d83 100644
--- a/gcc/fortran/trans-descriptor.cc
+++ b/gcc/fortran/trans-descriptor.cc
@@ -3281,9 +3281,10 @@ gfc_descr_init_count (tree descriptor, int rank, int
corank, gfc_expr ** lower,
else
gfc_conv_descriptor_dtype_set (pblock, descriptor, gfc_get_dtype (type));
+ gfc_conv_descriptor_elem_len_set (pblock, descriptor, element_size);
+
tree empty_cond = logical_false_node;
- spacing = gfc_conv_descriptor_elem_len_get (descriptor);
- spacing = fold_convert_loc (input_location, gfc_array_index_type, spacing);
+ spacing = fold_convert_loc (input_location, gfc_array_index_type,
element_size);
for (n = 0; n < rank; n++)
{
[gcc r16-358] Make ix86 cost of VEC_SELECT equivalent to SUBREG cost 1
https://gcc.gnu.org/g:c85148d036d17295bb2560e10020c924c83a5d13 commit r16-358-gc85148d036d17295bb2560e10020c924c83a5d13 Author: Jan Hubicka Date: Fri May 2 15:53:35 2025 +0200 Make ix86 cost of VEC_SELECT equivalent to SUBREG cost 1 This patch fixes regression of imagick with PGO and AVX512 where correcting size cost of SSE operations (to be 4 instead of 2 originally cut&pasted from x87) made late combine to eliminate zero registers introduced by rapd. The problem is that cost-model mistakely accounts VEC_SELECT as real instruction while it is optimized to nothing if src==dest (which is the case of these testcases). This register is used to eliminate false dependency between source and destination of int->fp conversions. While ix86_insn_cost hook already contains logic to incrase cost of the zero-extend the costs was not enough. gcc/ChangeLog: PR target/119900 * config/i386/i386.cc (ix86_can_change_mode_class): Add TODO comment. (ix86_rtx_costs): Make VEC_SELECT equivalent to SUBREG cost 1. Diff: --- gcc/config/i386/i386.cc | 39 --- 1 file changed, 36 insertions(+), 3 deletions(-) diff --git a/gcc/config/i386/i386.cc b/gcc/config/i386/i386.cc index cb348cb9cfb8..0c808c22b4f0 100644 --- a/gcc/config/i386/i386.cc +++ b/gcc/config/i386/i386.cc @@ -20978,7 +20978,11 @@ ix86_can_change_mode_class (machine_mode from, machine_mode to, return true; /* x87 registers can't do subreg at all, as all values are reformatted - to extended precision. */ + to extended precision. + + ??? middle-end queries mode changes for ALL_REGS and this makes + vec_series_lowpart_p to always return false. We probably should + restrict this to modes supported by i387 and check if it is enabled. */ if (MAYBE_FLOAT_CLASS_P (regclass)) return false; @@ -22756,13 +22760,41 @@ ix86_rtx_costs (rtx x, machine_mode mode, int outer_code_i, int opno, } return false; -case VEC_SELECT: case VEC_CONCAT: /* ??? Assume all of these vector manipulation patterns are recognizable. In which case they all pretty much have the -same cost. */ +same cost. +??? We should still recruse when computing cost. */ *total = cost->sse_op; return true; + +case VEC_SELECT: + /* Special case extracting lower part from the vector. + This by itself needs to code and most of SSE/AVX instructions have + packed and single forms where the single form may be represented + by such VEC_SELECT. + + Use cost 1 (despite the fact that functionally equivalent SUBREG has + cost 0). Making VEC_SELECT completely free, for example instructs CSE + to forward propagate VEC_SELECT into + + (set (reg eax) (reg src)) + + which then prevents fwprop and combining. See i.e. + gcc.target/i386/pr91103-1.c. + + ??? rtvec_series_p test should be, for valid patterns, equivalent to + vec_series_lowpart_p but is not, since the latter calls + can_cange_mode_class on ALL_REGS and this return false since x87 does + not support subregs at all. */ + if (rtvec_series_p (XVEC (XEXP (x, 1), 0), 0)) + *total = rtx_cost (XEXP (x, 0), GET_MODE (XEXP (x, 0)), + outer_code, opno, speed) + 1; + else + /* ??? We should still recruse when computing cost. */ + *total = cost->sse_op; + return true; + case VEC_DUPLICATE: *total = rtx_cost (XEXP (x, 0), GET_MODE (XEXP (x, 0)), @@ -22780,6 +22812,7 @@ ix86_rtx_costs (rtx x, machine_mode mode, int outer_code_i, int opno, if (TARGET_AVX512F && register_operand (mask, GET_MODE (mask))) *total = rtx_cost (XEXP (x, 0), mode, outer_code, opno, speed); else + /* ??? We should still recruse when computing cost. */ *total = cost->sse_op; return true;
[gcc r16-361] cobol, v2: Fix up cobol cross-compilation from 32-bit arches [PR119364]
https://gcc.gnu.org/g:4704b94fc76b51e79e6fcf63344f70da4d89d75c
commit r16-361-g4704b94fc76b51e79e6fcf63344f70da4d89d75c
Author: Jakub Jelinek
Date: Fri May 2 19:09:34 2025 +0200
cobol, v2: Fix up cobol cross-compilation from 32-bit arches [PR119364]
Right now it is not possible to even build cross-compilers from 32-bit
architectures to e.g. x86_64-linux or aarch64-linux, even from little-endian
ones.
The following patch attempts to fix that.
There were various issues seen e.g. trying to build i686-linux ->
x86_64-linux cross-compiler (so still 64-bit libgcobol, but the compiler
is 32-bit).
1) warning about >> 32 shift of size_t, on 32-bit arches size_t is 32-bit
and so the shift is UB; fixed by doing (new_size>>16)>>16 so that
it ors in >> 32 when new_size is 64-bit and 0 when it is 32-bit
2) enum cbl_field_attr_t was using size_t as underlying type, but has
various bitmasks which require full 64-bit type; changed this to uint64_t
underlying type and using unsigned long long in the structure; various
routines which operate with those attributes had to be changed also to
work with uint64_t instead of size_t
3) on i686-linux, config.h can #define _FILE_OFFSET_BITS 64 or similar
macros; as documented, those macros have to be defined before including
first C library header, but some sources included cobol-system.h which
includes config.h only after various other headers; this resulted in
link failures, as ino_t was sometimes unsigned long and sometines
unsigned long long, depending on whether config.h was included first or
not, and e.g. cobol_filename uses ino_t argument
4) lots of places used %ld or %lx *printf format specifers with size_t
arguments; that works only if size_t is unsigned long, but not when it
is unsigned int or unsigned long long or some other type; now while
ISO C99 has %zd or %zx to print size_t and C++14 includes C99 (or C11?),
while for the C++ headers the C++ compilers typically have full control
over it and so support everything in C++14 (e.g. libstdc++ in GCC 5.1+
or libc++ if not too old), for C library we are dependent on the system
C library (note, on the host for the compiler side). And not all hosts
support C99 in their C libraries; so instead of just changing it to
%zd or %zx, I'm changing it to what we use elsewhere in GCC,
HOST_SIZE_T_PRINT_{DEC,UNSIGNED,HEX_PURE} or GCC_PRISZ macros in the
*printf family format string and casts of the size_t arguments to
fmt_size_t. Note, if not using the C library *printf family (e.g. in
dbgmsg, sprintf, snprintf, fprintf, etc.) but the GCC diagnostic code
(e.g. err_msg, error, warning, yywarn, ...), then %zd/%zu is supported
and on the other side HOST_SIZE_T_PRINT_{DEC,UNSIGNED,HEX_PURE} etc.
macros shouldn't be used (for two reasons, because it is unnecessary
when %zd/%zu is guaranteed to be supported there because GCC has
control over that and more importantly because it breaks translations,
both extraction of the to be translated strings and we don't want to
have different messages, once with %lld, once with %ld, once with just %d
or %I64d depending on host, translators couldn't translate it all).
5) see above, there were already tons of %zd/%zu or %3zu etc. format
specifers in *printf format strings, this patch changes those too
6) I've noticed dbgmsg wasn't declared with printf attribute, which resulted
in bugs where format specifiers didn't match actually passed types of
arguments
2025-05-02 Jakub Jelinek
PR cobol/119364
libgcobol/
* valconv.cc (__gg__realloc_if_necessary): Use (new_size>>16)>>16;
instead of new_size>>32; to avoid warnings on 32-bit hosts.
* common-defs.h (enum cbl_field_attr_t): Use uint64_t
as underlying type rather than size_t.
* gcobolio.h (cblc_field_t): Change attr member type from size_t
to unsigned long long.
gcc/cobol/
* util.cc (is_numeric_edited): Use HOST_SIZE_T_PRINT_UNSIGNED
instead of "%zu" and cast corresponding argument to fmt_size_t.
(normalize_picture): Use GCC_PRISZ instead of "z" and pass address
of fmt_size_t var to sscanf and copy afterwards.
(cbl_refer_t::str): Use HOST_SIZE_T_PRINT_UNSIGNED instead of
"%zu" or GCC_PRISZ instead of "z" and cast corresponding argument
to fmt_size_t.
(struct move_corresponding_field): Likewise.
(valid_move): Likewise.
(ambiguous_reference): Likewise.
(parent_names): Likewise.
(find_corresponding::find_corresponding): Likewise.
(corresponding_fields): Likewise.
(unique_
[gcc r16-362] cobol: Fix up exception handling [PR119364]
https://gcc.gnu.org/g:c77d04506e6abdc45969d0ff146204be7485244a
commit r16-362-gc77d04506e6abdc45969d0ff146204be7485244a
Author: Jakub Jelinek
Date: Fri May 2 19:10:59 2025 +0200
cobol: Fix up exception handling [PR119364]
The following patch on top of the
https://gcc.gnu.org/pipermail/gcc-patches/2025-May/682500.html
fixes most of the remaining make check-cobol FAILs in the
i686-linux -> x86_64-linux cross-compiler.
Using the testing environment detailed in
https://gcc.gnu.org/pipermail/gcc-patches/2025-April/680403.html
with this patch I get just cobol.dg/group1/declarative_1.cob FAILs
in i686-linux -> x86_64-linux cross and no FAILs in x86_64-linux
native one.
The patch isn't needed just for cross-compilation with different
hosts, but also on x86_64-linux/aarch64-linux native, because without
it the FE is hashing padding bits which contain random garbage and making
code generation decisions based on that. That is very much against the
reproduceability requirements.
2025-05-02 Jakub Jelinek
PR cobol/119364
* structs.h (cbl_enabled_exception_type_node): New variable
declaration.
* structs.cc (cbl_enabled_exception_type_node): New variable.
(create_cbl_enabled_exception_t): New function.
(create_our_type_nodes): Initialize cbl_enabled_exception_type_node
using it.
* genapi.cc (stash_exceptions): Don't compare padding bits to
determine if the exceptions are the same as last time. Use
cbl_enabled_exception_type_node for target size and field offsets
and native_encode_expr to write each field into byte sequence.
Diff:
---
gcc/cobol/genapi.cc | 66 +---
gcc/cobol/structs.cc | 25
gcc/cobol/structs.h | 1 +
3 files changed, 73 insertions(+), 19 deletions(-)
diff --git a/gcc/cobol/genapi.cc b/gcc/cobol/genapi.cc
index eba10b0bdfe3..dca52ce080d5 100644
--- a/gcc/cobol/genapi.cc
+++ b/gcc/cobol/genapi.cc
@@ -13301,24 +13301,29 @@ static void
stash_exceptions( const cbl_enabled_exceptions_array_t *enabled )
{
// We need to create a static array of bytes
- size_t narg = enabled->nbytes();
- unsigned char *p = (unsigned char *)(enabled->ecs);
+ size_t nec = enabled->nec;
+ size_t sz = int_size_in_bytes(cbl_enabled_exception_type_node);
+ size_t narg = nec * sz;
+ cbl_enabled_exception_t *p = enabled->ecs;
- static size_t prior_narg = 0;
- static size_t max_narg = 128;
- static unsigned char *prior_p = (unsigned char *)xmalloc(max_narg);
+ static size_t prior_nec = 0;
+ static size_t max_nec = 0;
+ static cbl_enabled_exception_t *prior_p;
bool we_got_new_data = false;
- if( prior_narg != narg )
+ if( prior_nec != nec )
{
we_got_new_data = true;
}
else
{
-// The narg counts are the same.
-for(size_t i=0; i max_narg )
+ if( nec > max_nec )
{
-max_narg = narg;
-prior_p = (unsigned char *)xrealloc(prior_p, max_narg);
+max_nec = nec;
+prior_p = (cbl_enabled_exception_t *)
+ xrealloc(prior_p, max_nec * sizeof(cbl_enabled_exception_t));
}
- memcpy(prior_p, p, narg);
+ memcpy((unsigned char *)prior_p, (unsigned char *)p,
+ nec * sizeof(cbl_enabled_exception_t));
static int count = 1;
@@ -13355,12 +13362,33 @@ stash_exceptions( const
cbl_enabled_exceptions_array_t *enabled )
TREE_TYPE(constr) = array_of_chars_type;
TREE_STATIC(constr)= 1;
TREE_CONSTANT(constr) = 1;
-
-for(size_t i=0; i
[gcc r16-343] ++: Small build_vec_init improvement [PR117827]
https://gcc.gnu.org/g:c6efdffa7d5c68a14aa5de3a426a44ee05aaa1b9
commit r16-343-gc6efdffa7d5c68a14aa5de3a426a44ee05aaa1b9
Author: Jakub Jelinek
Date: Fri May 2 09:16:27 2025 +0200
++: Small build_vec_init improvement [PR117827]
As discussed in the
https://gcc.gnu.org/pipermail/gcc-patches/2025-January/674492.html
thread, the following patch attempts to improve build_vec_init generated
code. E.g. on g++.dg/eh/aggregate1.C test the patch has differences like:
D.2988 = &D.2950->e1;
D.2989 = D.2988;
D.2990 = 1;
try
{
goto ;
:
A::A (D.2989);
D.2990 = D.2990 + -1;
D.2989 = D.2989 + 1;
:
if (D.2990 >= 0) goto ; else goto
;
:
retval.4 = D.2988;
_13 = &D.2950->e2;
A::A (_13);
-D.2990 = 1;
+D.2988 = 0B;
D.2951 = D.2951 + -1;
}
catch
{
{
struct A * D.2991;
if (D.2988 != 0B) goto ; else goto
;
:
_11 = 1 - D.2990;
_12 = (sizetype) _11;
D.2991 = D.2988 + _12;
:
if (D.2991 == D.2988) goto ; else
goto ;
:
D.2991 = D.2991 + 18446744073709551615;
A::~A (D.2991);
goto ;
:
goto ;
:
:
}
}
in 3 spots. As you can see, both setting D.2990 (i.e. iterator) to
maxindex and setting D.2988 (i.e. rval) to nullptr have the same effect of
not actually destructing anything anymore in the cleanup, the
advantage of clearing rval is that setting something to zero is often less
expensive than potentially huge maxindex and that the cleanup tests that
value first.
2025-05-02 Jakub Jelinek
PR c++/117827
* init.cc (build_vec_init): Push to *cleanup_flags clearing of rval
instead of setting of iterator to maxindex.
Diff:
---
gcc/cp/init.cc | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/gcc/cp/init.cc b/gcc/cp/init.cc
index 062a4938a44c..80a37a14a806 100644
--- a/gcc/cp/init.cc
+++ b/gcc/cp/init.cc
@@ -4747,7 +4747,8 @@ build_vec_init (tree base, tree maxindex, tree init,
itself. But that breaks when gimplify_target_expr adds a clobber
cleanup that runs before the build_vec_init cleanup. */
if (cleanup_flags)
- vec_safe_push (*cleanup_flags, build_tree_list (iterator, maxindex));
+ vec_safe_push (*cleanup_flags,
+ build_tree_list (rval, build_zero_cst (ptype)));
}
/* Should we try to create a constant initializer? */
[gcc r16-349] gimple: Switch bit-test lowering testcases for the more powerful alg
https://gcc.gnu.org/g:8444c4cc7648f4396e2a3726677f909438e92c80
commit r16-349-g8444c4cc7648f4396e2a3726677f909438e92c80
Author: Filip Kastl
Date: Thu May 1 15:32:36 2025 +0200
gimple: Switch bit-test lowering testcases for the more powerful alg
This patch adds 2 testcases. One tests that GCC is able to create
bit-test clusters of size 64. The other one contains two switches which
GCC wouldn't completely cover with bit-test clusters before the changes
from this patch set.
gcc/testsuite/ChangeLog:
* gcc.dg/tree-ssa/switch-5.c: New test.
* gcc.dg/tree-ssa/switch-6.c: New test.
Signed-off-by: Filip Kastl
Diff:
---
gcc/testsuite/gcc.dg/tree-ssa/switch-5.c | 60
gcc/testsuite/gcc.dg/tree-ssa/switch-6.c | 51 +++
2 files changed, 111 insertions(+)
diff --git a/gcc/testsuite/gcc.dg/tree-ssa/switch-5.c
b/gcc/testsuite/gcc.dg/tree-ssa/switch-5.c
new file mode 100644
index ..b05742cf153c
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/tree-ssa/switch-5.c
@@ -0,0 +1,60 @@
+/* { dg-do compile { target { { x86_64-*-* aarch64-*-* ia64-*-* powerpc64-*-*
} && lp64 } } } */
+/* { dg-options "-O2 -fdump-tree-switchlower1" } */
+
+int f0();
+int f1();
+int f2();
+int f3();
+int f4();
+
+int foo(int a)
+{
+switch (a)
+{
+case 0:
+case 2:
+case 4:
+case 6:
+return f0();
+case 8:
+return f1();
+case 10:
+case 14:
+case 16:
+case 18:
+return f2();
+case 12:
+return f3();
+case 20:
+return f4();
+}
+return -1;
+}
+
+/* { dg-final { scan-tree-dump ";; GIMPLE switch case clusters: BT:0-8
BT:10-20" "switchlower1" } } */
+
+int bar(int a)
+{
+switch (a)
+{
+case 20:
+case 18:
+case 16:
+case 14:
+return f0();
+case 12:
+return f1();
+case 10:
+case 6:
+case 4:
+case 2:
+return f2();
+case 8:
+return f3();
+case 0:
+return f4();
+}
+return -1;
+}
+
+/* { dg-final { scan-tree-dump ";; GIMPLE switch case clusters: BT:0-10
BT:12-20" "switchlower1" } } */
diff --git a/gcc/testsuite/gcc.dg/tree-ssa/switch-6.c
b/gcc/testsuite/gcc.dg/tree-ssa/switch-6.c
new file mode 100644
index ..bbbc87462c40
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/tree-ssa/switch-6.c
@@ -0,0 +1,51 @@
+/* { dg-do compile { target { { x86_64-*-* aarch64-*-* ia64-*-* powerpc64-*-*
} && lp64 } } } */
+/* { dg-options "-O2 -fdump-tree-switchlower1 -fno-jump-tables" } */
+
+/* Test that bit-test switch lowering can create cluster of size 64 (there was
+ an of-by-one error causing it to only do 63 before). */
+
+int f();
+
+int foo(int a)
+{
+switch (a)
+{
+case 0:
+case 3:
+case 5:
+case 7:
+case 9:
+case 11:
+case 13:
+case 15:
+case 17:
+case 19:
+case 21:
+case 23:
+case 25:
+case 27:
+case 29:
+case 31:
+case 33:
+case 35:
+case 37:
+case 39:
+case 41:
+case 43:
+case 45:
+case 47:
+case 49:
+case 51:
+case 53:
+case 55:
+case 57:
+case 59:
+case 61:
+case 63:
+return f();
+default:
+return -1;
+}
+}
+
+/* { dg-final { scan-tree-dump ";; GIMPLE switch case clusters: BT:0-63"
"switchlower1" } } */
[gcc r16-347] gimple: Make bit-test switch lowering more powerful
https://gcc.gnu.org/g:1381a5114788a2e9234ff54e0cd7a3c810f0d02d
commit r16-347-g1381a5114788a2e9234ff54e0cd7a3c810f0d02d
Author: Filip Kastl
Date: Thu May 1 15:31:30 2025 +0200
gimple: Make bit-test switch lowering more powerful
A reasonable goal for bit-test lowering is to produce the least amount
of clusters for a given switch (a cluster is basically a group of cases
that can be handled by constantly many operations).
The current algorithm doesn't always give optimal solutions in that
sense. This patch should fix this. The important thing is basically
just to ask if a cluster is_beneficial() more proactively.
The patch also has a fix for a mistake which made bit-test lowering only
create BITS_IN_WORD - 1 big clusters. There are also some new comments
that go into more detail on the dynamic programming algorithm.
gcc/ChangeLog:
* tree-switch-conversion.cc (bit_test_cluster::find_bit_tests):
Modify the dynamic programming algorithm to take is_beneficial()
into account earlier. To do this efficiently, copy some logic
from is_beneficial() here. Add detailed comments about how the
DP algorithm works.
(bit_test_cluster::can_be_handled): Check that the cluster range
is >, not >= BITS_IN_WORD. Remove the
"vec &, unsigned, unsigned" overloaded variant since
we no longer need it.
(bit_test_cluster::is_beneficial): Add a comment that this
function is closely tied to m_max_case_bit_tests. Remove the
"vec &, unsigned, unsigned" overloaded variant since
we no longer need it.
* tree-switch-conversion.h: Remove the vec overloaded variants
of bit_test_cluster::is_beneficial and
bit_test_cluster::can_be_handled.
Signed-off-by: Filip Kastl
Diff:
---
gcc/tree-switch-conversion.cc | 153 ++
gcc/tree-switch-conversion.h | 10 ---
2 files changed, 67 insertions(+), 96 deletions(-)
diff --git a/gcc/tree-switch-conversion.cc b/gcc/tree-switch-conversion.cc
index a70274b03372..4f0be8c43f07 100644
--- a/gcc/tree-switch-conversion.cc
+++ b/gcc/tree-switch-conversion.cc
@@ -1783,58 +1783,98 @@ bit_test_cluster::find_bit_tests (vec
&clusters, int max_c)
if (!is_enabled () || max_c == 1)
return clusters.copy ();
+ /* Dynamic programming algorithm.
+
+ In: List of simple clusters
+ Out: List of simple clusters and bit test clusters such that each bit test
+ cluster can_be_handled() and is_beneficial()
+
+ Tries to merge consecutive clusters into bigger (bit test) ones. Tries to
+ end up with as few clusters as possible. */
+
unsigned l = clusters.length ();
auto_vec min;
min.reserve (l + 1);
- min.quick_push (min_cluster_item (0, 0, 0));
+ gcc_checking_assert (l > 0);
+ gcc_checking_assert (l <= INT_MAX);
- unsigned bits_in_word = GET_MODE_BITSIZE (word_mode);
+ int bits_in_word = GET_MODE_BITSIZE (word_mode);
- for (unsigned i = 1; i <= l; i++)
+ /* First phase: Compute the minimum number of clusters for each prefix of the
+ input list incrementally
+
+ min[i] = (count, j, _) means that the prefix ending with the (i-1)-th
+ element can be made to contain as few as count clusters and that in such
+ clustering the last cluster is made up of input clusters [j, i-1]
+ (inclusive). */
+ min.quick_push (min_cluster_item (0, 0, INT_MAX));
+ min.quick_push (min_cluster_item (1, 0, INT_MAX));
+ for (int i = 2; i <= (int) l; i++)
{
- /* Set minimal # of clusters with i-th item to infinite. */
- min.quick_push (min_cluster_item (INT_MAX, INT_MAX, INT_MAX));
+ auto_vec unique_labels;
/* Since each cluster contains at least one case number and one bit test
cluster can cover at most bits_in_word case numbers, we don't need to
look farther than bits_in_word clusters back. */
- unsigned j;
- if (i - 1 >= bits_in_word)
- j = i - 1 - bits_in_word;
- else
- j = 0;
- for (; j < i; j++)
+ for (int j = i - 1; j >= 0 && j >= i - bits_in_word; j--)
{
- if (min[j].m_count + 1 < min[i].m_count
- && can_be_handled (clusters, j, i - 1))
- min[i] = min_cluster_item (min[j].m_count + 1, j, INT_MAX);
- }
+ /* Consider creating a bit test cluster from input clusters [j, i-1]
+(inclusive) */
- gcc_checking_assert (min[i].m_count != INT_MAX);
+ simple_cluster *sc = static_cast (clusters[j]);
+ unsigned label = sc->m_case_bb->index;
+ if (!unique_labels.contains (label))
+ {
+ if (unique_labels.length () >= m_max_case_bit_tests)
+ /* is_beneficial() will be false for this and the following
+ iterations. */
+ break;
+
[gcc r16-348] gimple: Don't warn about using different algs for big switch lowering [PR117091]
https://gcc.gnu.org/g:c14560907a9586ad405f26ab937881eb08f39497 commit r16-348-gc14560907a9586ad405f26ab937881eb08f39497 Author: Filip Kastl Date: Thu May 1 15:32:07 2025 +0200 gimple: Don't warn about using different algs for big switch lowering [PR117091] We currently don't switch to a faster switch lowering algorithm when a switch is too big. This patch removes a warning about this. PR middle-end/117091 gcc/ChangeLog: * tree-switch-conversion.cc (switch_decision_tree::analyze_switch_statement): Remove warning about using different algorithms. Signed-off-by: Filip Kastl Diff: --- gcc/tree-switch-conversion.cc | 7 --- 1 file changed, 7 deletions(-) diff --git a/gcc/tree-switch-conversion.cc b/gcc/tree-switch-conversion.cc index 4f0be8c43f07..dea217a01efb 100644 --- a/gcc/tree-switch-conversion.cc +++ b/gcc/tree-switch-conversion.cc @@ -2257,13 +2257,6 @@ switch_decision_tree::analyze_switch_statement () reset_out_edges_aux (m_switch); - if (l > (unsigned) param_switch_lower_slow_alg_max_cases) -warning_at (gimple_location (m_switch), OPT_Wdisabled_optimization, - "Using faster switch lowering algorithms. " - "Number of switch cases (%d) exceeds " - "%<--param=switch-lower-slow-alg-max-cases=%d%> limit.", - l, param_switch_lower_slow_alg_max_cases); - /* Find bit-test clusters. */ vec output = bit_test_cluster::find_bit_tests (clusters, max_c);
[gcc r16-346] gimple: Merge slow and fast bit-test switch lowering [PR117091]
https://gcc.gnu.org/g:5274db0c9b8c0e2d2879b237eb2ab576543b6c37
commit r16-346-g5274db0c9b8c0e2d2879b237eb2ab576543b6c37
Author: Filip Kastl
Date: Thu May 1 15:30:52 2025 +0200
gimple: Merge slow and fast bit-test switch lowering [PR117091]
PR117091 showed that bit-test switch lowering can take a lot of time.
The algorithm was O(n^2). We therefore came up with a faster algorithm
(O(n * BITS_IN_WORD)) and made GCC choose between the slow and the fast
algorithm based on how big the switch is.
Here I combine the algorithms so that we get the results of the slower
algorithm in the faster asymptotic time.
PR middle-end/117091
gcc/ChangeLog:
* tree-switch-conversion.cc (bit_test_cluster::find_bit_tests_fast):
Remove function.
(bit_test_cluster::find_bit_tests_slow): Remove function.
(bit_test_cluster::find_bit_tests): We don't need to decide
between slow and fast so just put the modified (no longer) slow
algorithm here.
Signed-off-by: Filip Kastl
Diff:
---
gcc/tree-switch-conversion.cc | 107 +++---
1 file changed, 17 insertions(+), 90 deletions(-)
diff --git a/gcc/tree-switch-conversion.cc b/gcc/tree-switch-conversion.cc
index 39a8a893edde..a70274b03372 100644
--- a/gcc/tree-switch-conversion.cc
+++ b/gcc/tree-switch-conversion.cc
@@ -1773,92 +1773,38 @@ jump_table_cluster::is_beneficial (const vec
&,
return end - start + 1 >= case_values_threshold ();
}
-/* Find bit tests of given CLUSTERS, where all members of the vector are of
- type simple_cluster. Use a fast algorithm that might not find the optimal
- solution (minimal number of clusters on the output). New clusters are
- returned.
-
- You should call find_bit_tests () instead of calling this function
- directly. */
-
-vec
-bit_test_cluster::find_bit_tests_fast (vec &clusters)
-{
- unsigned l = clusters.length ();
- vec output;
-
- output.create (l);
-
- /* Look at sliding BITS_PER_WORD sized windows in the switch value space
- and determine if they are suitable for a bit test cluster. Worst case
- this can examine every value BITS_PER_WORD-1 times. */
- unsigned k;
- for (unsigned i = 0; i < l; i += k)
-{
- hash_set targets;
- cluster *start_cluster = clusters[i];
-
- /* Find the biggest k such that clusters i to i+k-1 can be turned into a
-one big bit test cluster. */
- k = 0;
- while (i + k < l)
- {
- cluster *end_cluster = clusters[i + k];
-
- /* Does value range fit into the BITS_PER_WORD window? */
- HOST_WIDE_INT w = cluster::get_range (start_cluster->get_low (),
- end_cluster->get_high ());
- if (w == 0 || w > BITS_PER_WORD)
- break;
-
- /* Check for max # of targets. */
- if (targets.elements () == m_max_case_bit_tests
- && !targets.contains (end_cluster->m_case_bb))
- break;
-
- targets.add (end_cluster->m_case_bb);
- k++;
- }
-
- if (is_beneficial (k, targets.elements ()))
- {
- output.safe_push (new bit_test_cluster (clusters, i, i + k - 1,
- i == 0 && k == l));
- }
- else
- {
- output.safe_push (clusters[i]);
- /* ??? Might be able to skip more. */
- k = 1;
- }
-}
-
- return output;
-}
-
/* Find bit tests of given CLUSTERS, where all members of the vector
- are of type simple_cluster. Use a slow (quadratic) algorithm that always
- finds the optimal solution (minimal number of clusters on the output). New
- clusters are returned.
-
- You should call find_bit_tests () instead of calling this function
- directly. */
+ are of type simple_cluster. MAX_C is the approx max number of cases per
+ label. New clusters are returned. */
vec
-bit_test_cluster::find_bit_tests_slow (vec &clusters)
+bit_test_cluster::find_bit_tests (vec &clusters, int max_c)
{
+ if (!is_enabled () || max_c == 1)
+return clusters.copy ();
+
unsigned l = clusters.length ();
auto_vec min;
min.reserve (l + 1);
min.quick_push (min_cluster_item (0, 0, 0));
+ unsigned bits_in_word = GET_MODE_BITSIZE (word_mode);
+
for (unsigned i = 1; i <= l; i++)
{
/* Set minimal # of clusters with i-th item to infinite. */
min.quick_push (min_cluster_item (INT_MAX, INT_MAX, INT_MAX));
- for (unsigned j = 0; j < i; j++)
+ /* Since each cluster contains at least one case number and one bit test
+cluster can cover at most bits_in_word case numbers, we don't need to
+look farther than bits_in_word clusters back. */
+ unsigned j;
+ if (i - 1 >= bits_in_word)
+ j = i - 1 - bits_in_word;
+ else
+ j = 0;
+ for (; j < i; j++)
{
[gcc r16-350] Remove TARGET_LRA_P override when defining to hook_bool_void_true
https://gcc.gnu.org/g:9d4cfdde79cf7900bef56773a003b3d5689ad1ce commit r16-350-g9d4cfdde79cf7900bef56773a003b3d5689ad1ce Author: Richard Biener Date: Fri May 2 08:40:46 2025 +0200 Remove TARGET_LRA_P override when defining to hook_bool_void_true Two targets were converted but retain the default. * config/arc/arc.cc (TARGET_LRA_P): Remove define. * config/gcn/gcn.cc (TARGET_LRA_P): Likewise. Diff: --- gcc/config/arc/arc.cc | 2 -- gcc/config/gcn/gcn.cc | 2 -- 2 files changed, 4 deletions(-) diff --git a/gcc/config/arc/arc.cc b/gcc/config/arc/arc.cc index be4bd612a092..3b4b038f6fe8 100644 --- a/gcc/config/arc/arc.cc +++ b/gcc/config/arc/arc.cc @@ -720,8 +720,6 @@ static rtx arc_legitimize_address_0 (rtx, rtx, machine_mode mode); #define TARGET_NO_SPECULATION_IN_DELAY_SLOTS_P \ arc_no_speculation_in_delay_slots_p -#undef TARGET_LRA_P -#define TARGET_LRA_P hook_bool_void_true #define TARGET_REGISTER_PRIORITY arc_register_priority /* Stores with scaled offsets have different displacement ranges. */ #define TARGET_DIFFERENT_ADDR_DISPLACEMENT_P hook_bool_void_true diff --git a/gcc/config/gcn/gcn.cc b/gcc/config/gcn/gcn.cc index 91ce8019480d..687bb4ee6c1d 100644 --- a/gcc/config/gcn/gcn.cc +++ b/gcc/config/gcn/gcn.cc @@ -7908,8 +7908,6 @@ gcn_dwarf_register_span (rtx rtl) #define TARGET_LEGITIMATE_CONSTANT_P gcn_legitimate_constant_p #undef TARGET_LIBC_HAS_FUNCTION #define TARGET_LIBC_HAS_FUNCTION gcn_libc_has_function -#undef TARGET_LRA_P -#define TARGET_LRA_P hook_bool_void_true #undef TARGET_MACHINE_DEPENDENT_REORG #define TARGET_MACHINE_DEPENDENT_REORG gcn_md_reorg #undef TARGET_MEMORY_MOVE_COST
[gcc r16-353] libstdc++: Add missing feature-test macro in
https://gcc.gnu.org/g:0e65fef8717f404cf9c85bff51bf87d534f87828 commit r16-353-g0e65fef8717f404cf9c85bff51bf87d534f87828 Author: Dhruv Chawla Date: Tue Apr 8 01:01:24 2025 -0700 libstdc++: Add missing feature-test macro in Per version.syn#2, is required to define __cpp_lib_addressof_constexpr as 201603L. Bootstrapped and tested on aarch64-linux-gnu. Signed-off-by: Dhruv Chawla libstdc++-v3/ChangeLog: * include/std/memory: Define __glibcxx_want_addressof_constexpr. * testsuite/20_util/headers/memory/version.cc: Test for macro value. Diff: --- libstdc++-v3/include/std/memory | 1 + libstdc++-v3/testsuite/20_util/headers/memory/version.cc | 4 2 files changed, 5 insertions(+) diff --git a/libstdc++-v3/include/std/memory b/libstdc++-v3/include/std/memory index 99f542dcddc6..78a1250d29a1 100644 --- a/libstdc++-v3/include/std/memory +++ b/libstdc++-v3/include/std/memory @@ -97,6 +97,7 @@ # include #endif +#define __glibcxx_want_addressof_constexpr #define __glibcxx_want_allocator_traits_is_always_equal #define __glibcxx_want_assume_aligned #define __glibcxx_want_atomic_shared_ptr diff --git a/libstdc++-v3/testsuite/20_util/headers/memory/version.cc b/libstdc++-v3/testsuite/20_util/headers/memory/version.cc index c82c9a018e0a..946955dd2123 100644 --- a/libstdc++-v3/testsuite/20_util/headers/memory/version.cc +++ b/libstdc++-v3/testsuite/20_util/headers/memory/version.cc @@ -6,3 +6,7 @@ #if __cpp_lib_allocator_traits_is_always_equal != 201411L # error "Feature-test macro __cpp_lib_allocator_traits_is_always_equal has wrong value in " #endif + +#if __cpp_lib_addressof_constexpr != 201603L +# error "Feature-test macro __cpp_lib_addressof_constexpr has wrong value in " +#endif
[gcc r16-344] aarch64: Optimize SVE extract last for VLS.
https://gcc.gnu.org/g:cdfa963cfc6849ff3ceb911f293201882aeef22e
commit r16-344-gcdfa963cfc6849ff3ceb911f293201882aeef22e
Author: Jennifer Schmitz
Date: Wed Mar 12 00:37:42 2025 -0700
aarch64: Optimize SVE extract last for VLS.
For the test case
int32_t foo (svint32_t x)
{
svbool_t pg = svpfalse ();
return svlastb_s32 (pg, x);
}
compiled with -O3 -mcpu=grace -msve-vector-bits=128, GCC produced:
foo:
pfalse p3.b
lastb w0, p3, z0.s
ret
when it could use a Neon lane extract instead:
foo:
umovw0, v0.s[3]
ret
Similar optimizations can be made for VLS with other vector widths.
We implemented this optimization by guarding the emission of
pfalse+lastb in the pattern vec_extract by
!val.is_constant ().
Thus, for last-extract operations with VLS, the patterns
*vec_extract_v128, *vec_extract_dup, or
*vec_extract_ext are used instead.
We added tests for 128-bit VLS and adjusted the tests for the other vector
widths.
The patch was bootstrapped and tested on aarch64-linux-gnu, no regression.
OK for mainline?
Signed-off-by: Jennifer Schmitz
gcc/
* config/aarch64/aarch64-sve.md (vec_extract):
Prevent the emission of pfalse+lastb for VLS.
gcc/testsuite/
* gcc.target/aarch64/sve/extract_last_128.c: New test.
* gcc.target/aarch64/sve/extract_1.c: Adjust expected outcome.
* gcc.target/aarch64/sve/extract_2.c: Likewise.
* gcc.target/aarch64/sve/extract_3.c: Likewise.
* gcc.target/aarch64/sve/extract_4.c: Likewise.
Diff:
---
gcc/config/aarch64/aarch64-sve.md | 7 +++--
gcc/testsuite/gcc.target/aarch64/sve/extract_1.c | 23 +++
gcc/testsuite/gcc.target/aarch64/sve/extract_2.c | 23 +++
gcc/testsuite/gcc.target/aarch64/sve/extract_3.c | 23 +++
gcc/testsuite/gcc.target/aarch64/sve/extract_4.c | 23 +++
.../gcc.target/aarch64/sve/extract_last_128.c | 33 ++
6 files changed, 77 insertions(+), 55 deletions(-)
diff --git a/gcc/config/aarch64/aarch64-sve.md
b/gcc/config/aarch64/aarch64-sve.md
index d4af3706294d..7bf12ff25ccd 100644
--- a/gcc/config/aarch64/aarch64-sve.md
+++ b/gcc/config/aarch64/aarch64-sve.md
@@ -2969,10 +2969,11 @@
{
poly_int64 val;
if (poly_int_rtx_p (operands[2], &val)
- && known_eq (val, GET_MODE_NUNITS (mode) - 1))
+ && known_eq (val, GET_MODE_NUNITS (mode) - 1)
+ && !val.is_constant ())
{
- /* The last element can be extracted with a LASTB and a false
- predicate. */
+ /* For VLA, extract the last element with a LASTB and a false
+ predicate. */
rtx sel = aarch64_pfalse_reg (mode);
emit_insn (gen_extract_last_ (operands[0], sel, operands[1]));
DONE;
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/extract_1.c
b/gcc/testsuite/gcc.target/aarch64/sve/extract_1.c
index 5d5edf26c19c..b5ca3b3e3987 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/extract_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/extract_1.c
@@ -56,40 +56,37 @@ typedef _Float16 vnx8hf __attribute__((vector_size (32)));
TEST_ALL (EXTRACT)
-/* { dg-final { scan-assembler-times {\tfmov\tx[0-9]+, d[0-9]+\n} 2 { target
aarch64_little_endian } } } */
-/* { dg-final { scan-assembler-times {\tumov\tx[0-9]+, v[0-9]+\.d\[0\]\n} 1 {
target aarch64_big_endian } } } */
+/* { dg-final { scan-assembler-times {\tfmov\tx[0-9]+, d[0-9]+\n} 3 { target
aarch64_little_endian } } } */
+/* { dg-final { scan-assembler-times {\tumov\tx[0-9]+, v[0-9]+\.d\[0\]\n} 2 {
target aarch64_big_endian } } } */
/* { dg-final { scan-assembler-times {\tumov\tx[0-9]+, v[0-9]+\.d\[1\]\n} 1 }
} */
/* { dg-final { scan-assembler-not {\tdup\td[0-9]+, v[0-9]+\.d\[0\]\n} } } */
/* { dg-final { scan-assembler-times {\tdup\td[0-9]+, v[0-9]+\.d\[1\]\n} 1 } }
*/
/* { dg-final { scan-assembler-times {\tdup\tz[0-9]+\.d, z[0-9]+\.d\[2\]\n} 2
} } */
-/* { dg-final { scan-assembler-times {\tlastb\tx[0-9]+, p[0-7], z[0-9]+\.d\n}
1 } } */
-/* { dg-final { scan-assembler-times {\tlastb\td[0-9]+, p[0-7], z[0-9]+\.d\n}
1 } } */
+/* { dg-final { scan-assembler-times {\tdup\tz[0-9]+\.d, z[0-9]+\.d\[3\]\n} 2
} } */
-/* { dg-final { scan-assembler-times {\tfmov\tw[0-9]+, s[0-9]+\n} 2 { target
aarch64_little_endian } } } */
-/* { dg-final { scan-assembler-times {\tumov\tw[0-9]+, v[0-9]+\.s\[0\]\n} 1 {
target aarch64_big_endian } } } */
+/* { dg-final { scan-assembler-times {\tfmov\tw[0-9]+, s[0-9]+\n} 3 { target
aarch64_little_endian } } } */
+/* { dg-final { scan-assembler-times {\tumov\tw[0-9]+, v[0-9]+\.s\[0\]\n} 2 {
target aarch64_big_endian } } } */
/* { dg-final { scan-assembler-times {\tumov\tw[0-9]+, v[0-9]+\.s\[1\]\n} 1 }
} */
/* { dg-final { scan-assembler-times {\tumov\tw[0-9]+, v[0-9]+\.s
[gcc r16-345] c: Fix crash in c-typeck.cc convert_arguments with indirect calls
https://gcc.gnu.org/g:02fa088f5b61fb5ddfff9e2dc0c0404450e7c6a4
commit r16-345-g02fa088f5b61fb5ddfff9e2dc0c0404450e7c6a4
Author: Florian Weimer
Date: Fri May 2 11:39:29 2025 +0200
c: Fix crash in c-typeck.cc convert_arguments with indirect calls
gcc/c/
PR c/120055
* c-typeck.cc (convert_arguments): Check if fundecl is null
before checking for builtin function declaration.
gcc/testsuite/
* gcc.dg/Wdeprecated-non-prototype-6.c: New test.
Diff:
---
gcc/c/c-typeck.cc | 2 +-
gcc/testsuite/gcc.dg/Wdeprecated-non-prototype-6.c | 14 ++
2 files changed, 15 insertions(+), 1 deletion(-)
diff --git a/gcc/c/c-typeck.cc b/gcc/c/c-typeck.cc
index c7a13bf2b2f4..05fb129ada8d 100644
--- a/gcc/c/c-typeck.cc
+++ b/gcc/c/c-typeck.cc
@@ -4337,7 +4337,7 @@ convert_arguments (location_t loc, vec
arg_loc, tree fntype,
}
if (!typetail && parmnum == 0 && !TYPE_NO_NAMED_ARGS_STDARG_P (fntype)
- && !fndecl_built_in_p (fundecl))
+ && !(fundecl && fndecl_built_in_p (fundecl)))
{
auto_diagnostic_group d;
bool warned;
diff --git a/gcc/testsuite/gcc.dg/Wdeprecated-non-prototype-6.c
b/gcc/testsuite/gcc.dg/Wdeprecated-non-prototype-6.c
new file mode 100644
index ..08f2995d5b26
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/Wdeprecated-non-prototype-6.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-std=gnu17 -Wdeprecated-non-prototype" } */
+
+void (*f1) ();
+void (*f2) ();
+void (*f3) (...);
+
+void
+g ()
+{
+ f1 ();
+ f2 (1); /* { dg-warning "does not allow arguments for function" } */
+ f3 (1);
+}
[gcc r16-351] libstdc++: Add some more makefile dependencies
https://gcc.gnu.org/g:a9ef2ae2e5a7e6d8febdac3806587a1ea33c commit r16-351-ga9ef2ae2e5a7e6d8febdac3806587a1ea33c Author: Jonathan Wakely Date: Thu Apr 10 12:56:43 2025 +0100 libstdc++: Add some more makefile dependencies Add more prerequisites for wchar and dual-abi targets in the src/c++11 directory, and simplify the existing ones (we don't need to add the main xxx.cc source file as a prerequisite of xxx.o because that's implicit, we only need to add the ones that Make can't determine on its own). Also add similar prerequisites for the dual-abi targets in the src/c++17 directory. libstdc++-v3/ChangeLog: * src/c++11/Makefile.am: Simplify existing prerequisites for wchar and dual-abi targets that are built from other sources. Add similar prerequisites for more wchar and dual-abi files. * src/c++11/Makefile.in: Regenerate. * src/c++17/Makefile.am [ENABLE_DUAL_ABI]: Add prerequisites for dual-abi targets that are built from other sources. * src/c++17/Makefile.in: Regenerate. Diff: --- libstdc++-v3/src/c++11/Makefile.am | 16 ++-- libstdc++-v3/src/c++11/Makefile.in | 18 +++--- libstdc++-v3/src/c++17/Makefile.am | 8 libstdc++-v3/src/c++17/Makefile.in | 6 ++ 4 files changed, 35 insertions(+), 13 deletions(-) diff --git a/libstdc++-v3/src/c++11/Makefile.am b/libstdc++-v3/src/c++11/Makefile.am index 26d6fa0e01ae..c240f0c183a3 100644 --- a/libstdc++-v3/src/c++11/Makefile.am +++ b/libstdc++-v3/src/c++11/Makefile.am @@ -168,14 +168,18 @@ localename.lo: localename.cc localename.o: localename.cc $(CXXCOMPILE) -fchar8_t -c $< -wstring-inst.lo: wstring-inst.cc string-inst.cc -wstring-inst.o: wstring-inst.cc string-inst.cc +# These files should be rebuilt if the .cc prerequisite changes. +wlocale-inst.lo wlocale-inst.o: locale-inst.cc +wstring-inst.lo wstring-inst.o: string-inst.cc if ENABLE_DUAL_ABI -cow-string-inst.lo: cow-string-inst.cc string-inst.cc -cow-string-inst.o: cow-string-inst.cc string-inst.cc -cow-wstring-inst.lo: cow-wstring-inst.cc string-inst.cc -cow-wstring-inst.o: cow-wstring-inst.cc string-inst.cc +# These files should be rebuilt if the .cc prerequisite changes. +cow-shim_facets.lo cow-shim_facets.o: cxx11-shim_facets.cc +cow-sstream-inst.lo cow-sstream-inst.o: sstream-inst.cc +cow-string-inst.lo cow-string-inst.o: string-inst.cc +cow-wstring-inst.lo cow-wstring-inst.o: string-inst.cc +cxx11-locale-inst.lo cxx11-locale-inst.o: locale-inst.cc +cxx11-wlocale-inst.lo cxx11-wlocale-inst.o: locale-inst.cc # Rewrite the type info for __ios_failure. rewrite_ios_failure_typeinfo = sed -e '/^_*_ZTISt13__ios_failure:/,/_ZTVN10__cxxabiv120__si_class_type_infoE/s/_ZTVN10__cxxabiv120__si_class_type_infoE/_ZTVSt19__iosfail_type_info/' diff --git a/libstdc++-v3/src/c++11/Makefile.in b/libstdc++-v3/src/c++11/Makefile.in index dafdb260ec16..9d04548f1571 100644 --- a/libstdc++-v3/src/c++11/Makefile.in +++ b/libstdc++-v3/src/c++11/Makefile.in @@ -896,13 +896,17 @@ localename.lo: localename.cc localename.o: localename.cc $(CXXCOMPILE) -fchar8_t -c $< -wstring-inst.lo: wstring-inst.cc string-inst.cc -wstring-inst.o: wstring-inst.cc string-inst.cc - -@enable_dual_abi_t...@cow-string-inst.lo: cow-string-inst.cc string-inst.cc -@ENABLE_DUAL_ABI_TRUE@cow-string-inst.o: cow-string-inst.cc string-inst.cc -@enable_dual_abi_t...@cow-wstring-inst.lo: cow-wstring-inst.cc string-inst.cc -@ENABLE_DUAL_ABI_TRUE@cow-wstring-inst.o: cow-wstring-inst.cc string-inst.cc +# These files should be rebuilt if the .cc prerequisite changes. +wlocale-inst.lo wlocale-inst.o: locale-inst.cc +wstring-inst.lo wstring-inst.o: string-inst.cc + +# These files should be rebuilt if the .cc prerequisite changes. +@ENABLE_DUAL_ABI_TRUE@cow-shim_facets.lo cow-shim_facets.o: cxx11-shim_facets.cc +@enable_dual_abi_t...@cow-sstream-inst.lo cow-sstream-inst.o: sstream-inst.cc +@enable_dual_abi_t...@cow-string-inst.lo cow-string-inst.o: string-inst.cc +@enable_dual_abi_t...@cow-wstring-inst.lo cow-wstring-inst.o: string-inst.cc +@enable_dual_abi_t...@cxx11-locale-inst.lo cxx11-locale-inst.o: locale-inst.cc +@enable_dual_abi_t...@cxx11-wlocale-inst.lo cxx11-wlocale-inst.o: locale-inst.cc @ENABLE_DUAL_ABI_TRUE@cxx11-ios_failure-lt.s: cxx11-ios_failure.cc @ENABLE_DUAL_ABI_TRUE@ $(LTCXXCOMPILE) -gno-as-loc-support -S $< -o tmp-cxx11-ios_failure-lt.s diff --git a/libstdc++-v3/src/c++17/Makefile.am b/libstdc++-v3/src/c++17/Makefile.am index a40350062b39..ce242e23b843 100644 --- a/libstdc++-v3/src/c++17/Makefile.am +++ b/libstdc++-v3/src/c++17/Makefile.am @@ -66,6 +66,14 @@ else libc__17convenience_la_SOURCES = endif +if ENABLE_DUAL_ABI +# These files should be rebuilt if the .cc prerequisite changes. +cow-string-inst.lo cow-string-inst.o: string-inst.cc +cow-fs_dir.lo cow-fs_dir.o: fs_dir.cc +cow-fs_ops.lo cow-fs_ops.o: fs_ops.cc +cow-
[gcc r16-352] libstdc++: Make __gnu_test::default_init_allocator usable in constexpr
https://gcc.gnu.org/g:869accb241c84f132ac0c9cd4e5ad9b4b7e6d536
commit r16-352-g869accb241c84f132ac0c9cd4e5ad9b4b7e6d536
Author: Jonathan Wakely
Date: Thu May 1 22:41:40 2025 +0100
libstdc++: Make __gnu_test::default_init_allocator usable in constexpr
If we make this test allocator usable in constant expressions then we'll
get an error if the 'state' data member isn't initialized. This makes it
a more reliable check that allocators are correctly value-initialized
when they're required to be.
libstdc++-v3/ChangeLog:
* testsuite/23_containers/vector/allocator/default_init.cc:
Add a check using constant evaluation.
* testsuite/23_containers/vector/bool/allocator/default_init.cc:
Likewise.
* testsuite/util/testsuite_allocator.h (default_init_allocator):
Make all member functions and equality ops constexpr.
Diff:
---
.../23_containers/vector/allocator/default_init.cc | 11 +++
.../23_containers/vector/bool/allocator/default_init.cc | 11 +++
libstdc++-v3/testsuite/util/testsuite_allocator.h | 17 ++---
3 files changed, 32 insertions(+), 7 deletions(-)
diff --git
a/libstdc++-v3/testsuite/23_containers/vector/allocator/default_init.cc
b/libstdc++-v3/testsuite/23_containers/vector/allocator/default_init.cc
index 195cd2dca544..486c44c9699d 100644
--- a/libstdc++-v3/testsuite/23_containers/vector/allocator/default_init.cc
+++ b/libstdc++-v3/testsuite/23_containers/vector/allocator/default_init.cc
@@ -59,6 +59,17 @@ void test02()
tmp->~test_type();
}
+#ifdef __cpp_lib_constexpr_vector
+constexpr bool
+test03()
+{
+ using alloc_type = default_init_allocator;
+ std::vector v;
+ return v.get_allocator().state == 0;
+}
+static_assert( test03() );
+#endif
+
int main()
{
test01();
diff --git
a/libstdc++-v3/testsuite/23_containers/vector/bool/allocator/default_init.cc
b/libstdc++-v3/testsuite/23_containers/vector/bool/allocator/default_init.cc
index 3914b7fe6c3a..c95cb6ba99f3 100644
--- a/libstdc++-v3/testsuite/23_containers/vector/bool/allocator/default_init.cc
+++ b/libstdc++-v3/testsuite/23_containers/vector/bool/allocator/default_init.cc
@@ -59,6 +59,17 @@ void test02()
tmp->~test_type();
}
+#ifdef __cpp_lib_constexpr_vector
+constexpr bool
+test03()
+{
+ using alloc_type = default_init_allocator;
+ std::vector v;
+ return v.get_allocator().state == 0;
+}
+static_assert( test03() );
+#endif
+
int main()
{
test01();
diff --git a/libstdc++-v3/testsuite/util/testsuite_allocator.h
b/libstdc++-v3/testsuite/util/testsuite_allocator.h
index be596bf00fb4..e5ffad2ba587 100644
--- a/libstdc++-v3/testsuite/util/testsuite_allocator.h
+++ b/libstdc++-v3/testsuite/util/testsuite_allocator.h
@@ -541,15 +541,16 @@ namespace __gnu_test
default_init_allocator() = default;
template
+ constexpr
default_init_allocator(const default_init_allocator& a)
: state(a.state)
{ }
- T*
+ constexpr T*
allocate(std::size_t n)
{ return std::allocator().allocate(n); }
- void
+ constexpr void
deallocate(T* p, std::size_t n)
{ std::allocator().deallocate(p, n); }
@@ -557,15 +558,17 @@ namespace __gnu_test
};
template
-bool operator==(const default_init_allocator& t,
- const default_init_allocator& u)
+constexpr bool
+operator==(const default_init_allocator& t,
+ const default_init_allocator& u)
{ return t.state == u.state; }
template
-bool operator!=(const default_init_allocator& t,
- const default_init_allocator& u)
+constexpr bool
+operator!=(const default_init_allocator& t,
+ const default_init_allocator& u)
{ return !(t == u); }
-#endif
+#endif // C++11
template
struct ExplicitConsAlloc : std::allocator
[gcc r16-355] c++: C++17/20 class layout divergence [PR120012]
https://gcc.gnu.org/g:e6e3b0772ed40cc65a544bbe744ece62d8b9713e
commit r16-355-ge6e3b0772ed40cc65a544bbe744ece62d8b9713e
Author: Jason Merrill
Date: Wed Apr 30 10:18:46 2025 -0400
c++: C++17/20 class layout divergence [PR120012]
C++20 made a class with only explicitly defaulted constructors no longer
aggregate, and this wrongly affected whether the class is considered "POD
for layout purposes" under the ABI.
Conveniently, we already have check_non_pod_aggregate to diagnose cases
where this makes a difference, due to PR103681 around a C++14 aggregate
change.
PR c++/120012
gcc/cp/ChangeLog:
* cp-tree.h (struct lang_type): Add non_aggregate_pod.
(CLASSTYPE_NON_AGGREGATE_POD): New.
* class.cc (check_bases_and_members): Set it.
(check_non_pod_aggregate): Diagnose it.
gcc/ChangeLog:
* doc/invoke.texi: Document C++20 aggregate fix.
* common.opt: Likewise.
gcc/testsuite/ChangeLog:
* g++.dg/abi/base-defaulted1.C: New test.
* g++.dg/abi/base-defaulted1a.C: New test.
Diff:
---
gcc/doc/invoke.texi | 3 +-
gcc/common.opt | 1 +
gcc/cp/cp-tree.h| 8 -
gcc/cp/class.cc | 54 +++--
gcc/testsuite/g++.dg/abi/base-defaulted1.C | 19 ++
gcc/testsuite/g++.dg/abi/base-defaulted1a.C | 23
6 files changed, 95 insertions(+), 13 deletions(-)
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index e7a9a03bace5..32bc45725de9 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -3015,7 +3015,8 @@ Version 20, which first appeared in G++ 15, fixes
manglings of lambdas
in static data member initializers.
Version 21, which first appeared in G++ 16, fixes unnecessary captures
-in noexcept lambdas (c++/119764).
+in noexcept lambdas (c++/119764) and layout of a base class
+with all explicitly defaulted constructors (c++/120012).
See also @option{-Wabi}.
diff --git a/gcc/common.opt b/gcc/common.opt
index 8a5b69d0767c..0e50305dde8e 100644
--- a/gcc/common.opt
+++ b/gcc/common.opt
@@ -1056,6 +1056,7 @@ Driver Undocumented
; Default in G++ 15.
;
; 21: Fix noexcept lambda capture pruning.
+; Fix C++20 layout of base with all explicitly defaulted constructors.
; Default in G++ 16.
;
; Additional positive integers will be assigned as new versions of
diff --git a/gcc/cp/cp-tree.h b/gcc/cp/cp-tree.h
index 856202c65dd6..af51d67ef9fe 100644
--- a/gcc/cp/cp-tree.h
+++ b/gcc/cp/cp-tree.h
@@ -2491,6 +2491,7 @@ struct GTY(()) lang_type {
unsigned unique_obj_representations_set : 1;
bool erroneous : 1;
bool non_pod_aggregate : 1;
+ bool non_aggregate_pod : 1;
/* When adding a flag here, consider whether or not it ought to
apply to a template instance if it applies to the template. If
@@ -2499,7 +2500,7 @@ struct GTY(()) lang_type {
/* There are some bits left to fill out a 32-bit word. Keep track
of this by updating the size of this bitfield whenever you add or
remove a flag. */
- unsigned dummy : 3;
+ unsigned dummy : 2;
tree primary_base;
vec *vcall_indices;
@@ -2826,6 +2827,11 @@ struct GTY(()) lang_type {
with a hash_set only filled in when abi_version_crosses (17). */
#define CLASSTYPE_NON_POD_AGGREGATE(NODE) \
(LANG_TYPE_CLASS_CHECK (NODE)->non_pod_aggregate)
+
+/* True if this class is layout-POD though it's not an aggregate in C++20 and
+ above (c++/120012). This could also be a hash_set. */
+#define CLASSTYPE_NON_AGGREGATE_POD(NODE) \
+ (LANG_TYPE_CLASS_CHECK (NODE)->non_aggregate_pod)
/* Additional macros for inheritance information. */
diff --git a/gcc/cp/class.cc b/gcc/cp/class.cc
index 2b694b98e565..6767ac10358b 100644
--- a/gcc/cp/class.cc
+++ b/gcc/cp/class.cc
@@ -6413,9 +6413,7 @@ check_bases_and_members (tree t)
Again, other conditions for being an aggregate are checked
elsewhere. */
CLASSTYPE_NON_AGGREGATE (t)
-|= ((cxx_dialect < cxx20
-? type_has_user_provided_or_explicit_constructor (t)
-: TYPE_HAS_USER_CONSTRUCTOR (t))
+|= (type_has_user_provided_or_explicit_constructor (t)
|| TYPE_POLYMORPHIC_P (t));
/* This is the C++98/03 definition of POD; it changed in C++0x, but we
retain the old definition internally for ABI reasons. */
@@ -6437,6 +6435,20 @@ check_bases_and_members (tree t)
CLASSTYPE_NON_LAYOUT_POD_P (t) = true;
}
+ /* P1008: Prohibit aggregates with user-declared constructors. */
+ if (cxx_dialect >= cxx20 && TYPE_HAS_USER_CONSTRUCTOR (t))
+{
+ CLASSTYPE_NON_AGGREGATE (t) = true;
+ if (!CLASSTYPE_NON_LAYOUT_POD_P (t))
+ {
+ /* c++/120012: The C++20 aggregate change affected layout. */
+ if (!abi_version_at_least (21))
+ CLASSTYPE_NON_LAYOUT_PO
[gcc r16-354] i386: -Wabi false positive with indirect call [PR60336]
https://gcc.gnu.org/g:4af5de21363cfdd2be227c05dfdee7e053337f6a
commit r16-354-g4af5de21363cfdd2be227c05dfdee7e053337f6a
Author: Jason Merrill
Date: Thu May 1 11:40:17 2025 -0400
i386: -Wabi false positive with indirect call [PR60336]
This warning relies on the TRANSLATION_UNIT_WARN_EMPTY_P flag (set in
cxx_init_decl_processing) to decide whether we want to warn about the GCC 8
empty class parameter passing fix, but in a call through a function pointer
we don't have a translation unit and so complain for any -Wabi flag, even
now long after this was likely to be relevant.
In that situation, let's check the TU for current_function_decl instead.
And if we still can't come up with a TU, default to not warning.
PR c++/60336
gcc/ChangeLog:
* config/i386/i386.cc (ix86_warn_parameter_passing_abi):
If no target, check the current TU.
gcc/testsuite/ChangeLog:
* g++.dg/abi/pr60336-8a.C: New test.
Diff:
---
gcc/config/i386/i386.cc | 11 ---
gcc/testsuite/g++.dg/abi/pr60336-8a.C | 15 +++
2 files changed, 23 insertions(+), 3 deletions(-)
diff --git a/gcc/config/i386/i386.cc b/gcc/config/i386/i386.cc
index 2f8403381384..cb348cb9cfb8 100644
--- a/gcc/config/i386/i386.cc
+++ b/gcc/config/i386/i386.cc
@@ -18084,9 +18084,14 @@ ix86_warn_parameter_passing_abi (cumulative_args_t
cum_v, tree type)
if (cum->decl && !TREE_PUBLIC (cum->decl))
return;
- const_tree ctx = get_ultimate_context (cum->decl);
- if (ctx != NULL_TREE
- && !TRANSLATION_UNIT_WARN_EMPTY_P (ctx))
+ tree decl = cum->decl;
+ if (!decl)
+/* If we don't know the target, look at the current TU. */
+decl = current_function_decl;
+
+ const_tree ctx = get_ultimate_context (decl);
+ if (ctx == NULL_TREE
+ || !TRANSLATION_UNIT_WARN_EMPTY_P (ctx))
return;
/* If the actual size of the type is zero, then there is no change
diff --git a/gcc/testsuite/g++.dg/abi/pr60336-8a.C
b/gcc/testsuite/g++.dg/abi/pr60336-8a.C
new file mode 100644
index ..a0518436e0eb
--- /dev/null
+++ b/gcc/testsuite/g++.dg/abi/pr60336-8a.C
@@ -0,0 +1,15 @@
+// { dg-do compile }
+// { dg-options "-O2 -Wabi=12" }
+
+struct dummy { struct{} a[7][3]; };
+
+extern void test1 (struct dummy, ...);
+extern void (*test2) (struct dummy, ...);
+
+void
+foo ()
+{
+ struct dummy a0;
+ test1 (a0, 42);
+ test2 (a0, 42);
+}
[gcc r16-365] simplify-rtl: Fix crash due to simplify_with_subreg_not [PR120059]
https://gcc.gnu.org/g:dba5d112691a3e10b722468d94fffeda0fdbb818
commit r16-365-gdba5d112691a3e10b722468d94fffeda0fdbb818
Author: Andrew Pinski
Date: Fri May 2 09:46:24 2025 -0700
simplify-rtl: Fix crash due to simplify_with_subreg_not [PR120059]
r16-286-gd84fbc516ea57d added a call to simplify_gen_subreg but didn't
check if the result of simplify_gen_subreg was non-null. simplify_gen_subreg
can return NULL if the subreg would be not valid. In the case below we had
a hard register for the SSE register xmm0 of mode SI and doing a subreg to
QI mode but QImode is not a valid mode for the SSE register so
simplify_gen_subreg
would return NULL.
This adds the obvious check.
Pushed as obvious after bootstrap/test on x86_64-linux-gnu.
PR rtl-optimization/120059
gcc/ChangeLog:
* simplify-rtx.cc (simplify_with_subreg_not): Check the result
of simplify_gen_subreg.
gcc/testsuite/ChangeLog:
* gcc.dg/torture/pr120059-1.c: New test.
Signed-off-by: Andrew Pinski
Diff:
---
gcc/simplify-rtx.cc | 4
gcc/testsuite/gcc.dg/torture/pr120059-1.c | 17 +
2 files changed, 21 insertions(+)
diff --git a/gcc/simplify-rtx.cc b/gcc/simplify-rtx.cc
index 7c4d8e6cfdbb..7bcbe11370fa 100644
--- a/gcc/simplify-rtx.cc
+++ b/gcc/simplify-rtx.cc
@@ -3063,6 +3063,10 @@ simplify_with_subreg_not (rtx_code binop, machine_mode
mode, rtx op0, rtx op1)
XEXP (SUBREG_REG (opn), 0),
GET_MODE (SUBREG_REG (opn)),
SUBREG_BYTE (opn));
+
+ if (!new_subreg)
+return NULL_RTX;
+
rtx new_not = simplify_gen_unary (NOT, mode, new_subreg, mode);
if (opn == op0)
return simplify_gen_binary (binop, mode, new_not, op1);
diff --git a/gcc/testsuite/gcc.dg/torture/pr120059-1.c
b/gcc/testsuite/gcc.dg/torture/pr120059-1.c
new file mode 100644
index ..36d0c5b00690
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/torture/pr120059-1.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-g" } */
+
+/* PR rtl-optimization/120059 */
+
+int a[4];
+int c, d;
+void f(void) {
+ for (int e = 0; e < 4; e++)
+a[e] = e | c;
+ int b = 0;
+ if ((a[0] & 1) && (a[0] & 4))
+b = 2;
+ if (a[0] & 16)
+b |= 1;
+ d = ~b;
+}
[gcc] Created branch 'ibm/heads/gcc-15-branch' in namespace 'refs/vendors'
The branch 'ibm/heads/gcc-15-branch' was created in namespace 'refs/vendors' pointing to: d32ece49d32b... libsanitizer: Fix build with glibc 2.42
[gcc r16-356] c++: fix some testcases
https://gcc.gnu.org/g:b7e77644d1b27810c5db1944644b6c5eca74cf93
commit r16-356-gb7e77644d1b27810c5db1944644b6c5eca74cf93
Author: Jason Merrill
Date: Fri May 2 09:33:39 2025 -0400
c++: fix some testcases
After r16-332 these tests started failing. constexpr-89285.C should have
always given this error, and the new nonlit19.C needs to remove the
destructor body to prevent -fimplicit-constexpr from making the testcase
well-formed.
gcc/testsuite/ChangeLog:
* g++.dg/cpp1y/constexpr-89285.C: Always diagnose reinterpret_cast.
* g++.dg/cpp23/constexpr-nonlit19.C: Remove ~A body.
Diff:
---
gcc/testsuite/g++.dg/cpp1y/constexpr-89285.C| 2 +-
gcc/testsuite/g++.dg/cpp23/constexpr-nonlit19.C | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/gcc/testsuite/g++.dg/cpp1y/constexpr-89285.C
b/gcc/testsuite/g++.dg/cpp1y/constexpr-89285.C
index efbf9bd15dde..d1aaecc1013b 100644
--- a/gcc/testsuite/g++.dg/cpp1y/constexpr-89285.C
+++ b/gcc/testsuite/g++.dg/cpp1y/constexpr-89285.C
@@ -10,7 +10,7 @@ struct B {
int *c = &x->a;
while (*c)
c = reinterpret_cast((reinterpret_cast(c) + *c));
-*c = reinterpret_cast(this) - reinterpret_cast(c); // {
dg-error "reinterpret_cast" "" { target c++20_down } }
+*c = reinterpret_cast(this) - reinterpret_cast(c); // {
dg-error "reinterpret_cast" }
}
};
struct C : A { // { dg-error "" "" { target c++14_down } }
diff --git a/gcc/testsuite/g++.dg/cpp23/constexpr-nonlit19.C
b/gcc/testsuite/g++.dg/cpp23/constexpr-nonlit19.C
index 1b73e2d8209d..834dc631778e 100644
--- a/gcc/testsuite/g++.dg/cpp23/constexpr-nonlit19.C
+++ b/gcc/testsuite/g++.dg/cpp23/constexpr-nonlit19.C
@@ -1,6 +1,6 @@
// { dg-do compile { target c++23 } }
-struct A { ~A() { } };
+struct A { ~A(); };
struct B {
constexpr B() {
[gcc r16-357] c++: CTAD and constexpr ctor [PR115207]
https://gcc.gnu.org/g:2d7a0d38e2f8e281ab2269cfe6c048410fa3c886
commit r16-357-g2d7a0d38e2f8e281ab2269cfe6c048410fa3c886
Author: Jason Merrill
Date: Fri May 2 08:35:38 2025 -0400
c++: CTAD and constexpr ctor [PR115207]
Here we failed to constant-evaluate the A constructor because DECL_SIZE
wasn't set on 'a' yet, so compare_address thinks we can't be sure it isn't
at the same address as 'i'.
Normally DECL_SIZE is set by build_decl calling layout_decl, but that
doesn't happen here because we don't have a type yet. So we need to
layout_decl again after deduction.
PR c++/115207
gcc/cp/ChangeLog:
* decl.cc (cp_finish_decl): Call layout_decl after CTAD.
gcc/testsuite/ChangeLog:
* g++.dg/cpp1z/class-deduction118.C: New test.
Diff:
---
gcc/cp/decl.cc | 3 +++
gcc/testsuite/g++.dg/cpp1z/class-deduction118.C | 11 +++
2 files changed, 14 insertions(+)
diff --git a/gcc/cp/decl.cc b/gcc/cp/decl.cc
index 84398e5952a1..03e8c98d4b68 100644
--- a/gcc/cp/decl.cc
+++ b/gcc/cp/decl.cc
@@ -8899,6 +8899,9 @@ cp_finish_decl (tree decl, tree init, bool
init_const_expr_p,
TREE_TYPE (decl) = error_mark_node;
return;
}
+
+ /* Now that we have a type, try these again. */
+ layout_decl (decl, 0);
cp_apply_type_quals_to_decl (cp_type_quals (type), decl);
/* Update the type of the corresponding TEMPLATE_DECL to match. */
diff --git a/gcc/testsuite/g++.dg/cpp1z/class-deduction118.C
b/gcc/testsuite/g++.dg/cpp1z/class-deduction118.C
new file mode 100644
index ..64d814beb7d6
--- /dev/null
+++ b/gcc/testsuite/g++.dg/cpp1z/class-deduction118.C
@@ -0,0 +1,11 @@
+// PR c++/115207
+// { dg-do compile { target c++17 } }
+
+template
+struct A {
+ T t;
+ constexpr A(T* p): t (p != &t) { }
+};
+
+const int i = 42;
+constexpr A a = &i;
