[gcc r16-309] c++: UNBOUND_CLASS_TEMPLATE context substitution [PR119981]
https://gcc.gnu.org/g:05ea8baf6ff96c77a9a2467d5c45b1ed575fca92
commit r16-309-g05ea8baf6ff96c77a9a2467d5c45b1ed575fca92
Author: Patrick Palka
Date: Wed Apr 30 10:54:23 2025 -0400
c++: UNBOUND_CLASS_TEMPLATE context substitution [PR119981]
In r15-123 and r14-11434 we unconditionally set processing_template_decl
when substituting the context of an UNBOUND_CLASS_TEMPLATE, in order to
handle instantiation of the dependently scoped friend declaration
template
template
friend class A::B;
where the scope A remains dependent after instantiation. But this
turns out to misbehave for the UNBOUND_CLASS_TEMPLATE in the below
testcase representing
g<[]{}>::template fn
since with the flag set substituting the args of test3 into the lambda
causes us to defer the substitution and yield a lambda that still looks
dependent, which in turn makes g<[]{}> still dependent and not suitable
for qualified name lookup.
This patch restricts setting processing_template_decl during
UNBOUND_CLASS_TEMPLATE substitution to the case where there are multiple
levels of introduced template parameters, as in the friend declaration.
(This means we need to substitute the template parameter list(s) first,
which makes sense since they lexically appear first.)
PR c++/119981
PR c++/119378
gcc/cp/ChangeLog:
* pt.cc (tsubst) : Substitute
into template parameter list first. When substituting the
context, only set processing_template_decl if there's more
than one level of introduced template parameters.
gcc/testsuite/ChangeLog:
* g++.dg/cpp2a/lambda-targ15.C: New test.
Reviewed-by: Jason Merrill
Diff:
---
gcc/cp/pt.cc | 20 +---
gcc/testsuite/g++.dg/cpp2a/lambda-targ15.C | 17 +
2 files changed, 30 insertions(+), 7 deletions(-)
diff --git a/gcc/cp/pt.cc b/gcc/cp/pt.cc
index e8d342f99f6d..26ed9de430c0 100644
--- a/gcc/cp/pt.cc
+++ b/gcc/cp/pt.cc
@@ -17181,18 +17181,24 @@ tsubst (tree t, tree args, tsubst_flags_t complain,
tree in_decl)
case UNBOUND_CLASS_TEMPLATE:
{
- ++processing_template_decl;
- tree ctx = tsubst_entering_scope (TYPE_CONTEXT (t), args,
- complain, in_decl);
- --processing_template_decl;
tree name = TYPE_IDENTIFIER (t);
+ if (name == error_mark_node)
+ return error_mark_node;
+
tree parm_list = DECL_TEMPLATE_PARMS (TYPE_NAME (t));
+ parm_list = tsubst_template_parms (parm_list, args, complain);
+ if (parm_list == error_mark_node)
+ return error_mark_node;
- if (ctx == error_mark_node || name == error_mark_node)
+ if (parm_list && TMPL_PARMS_DEPTH (parm_list) > 1)
+ ++processing_template_decl;
+ tree ctx = tsubst_entering_scope (TYPE_CONTEXT (t), args,
+ complain, in_decl);
+ if (parm_list && TMPL_PARMS_DEPTH (parm_list) > 1)
+ --processing_template_decl;
+ if (ctx == error_mark_node)
return error_mark_node;
- if (parm_list)
- parm_list = tsubst_template_parms (parm_list, args, complain);
return make_unbound_class_template (ctx, name, parm_list, complain);
}
diff --git a/gcc/testsuite/g++.dg/cpp2a/lambda-targ15.C
b/gcc/testsuite/g++.dg/cpp2a/lambda-targ15.C
new file mode 100644
index ..90160a52a6ef
--- /dev/null
+++ b/gcc/testsuite/g++.dg/cpp2a/lambda-targ15.C
@@ -0,0 +1,17 @@
+// PR c++/119981
+// { dg-do compile { target c++20 } }
+
+template class P>
+struct mp_copy_if{};
+
+template
+struct g {
+ template struct fn{};
+};
+
+template
+void test3() {
+ mp_copy_if::template fn> b;
+}
+
+template void test3();
[gcc r15-9605] c++: UNBOUND_CLASS_TEMPLATE context substitution [PR119981]
https://gcc.gnu.org/g:670250c904dd5c8a1e0a0d241c42d5657400cdc8
commit r15-9605-g670250c904dd5c8a1e0a0d241c42d5657400cdc8
Author: Patrick Palka
Date: Wed Apr 30 10:54:23 2025 -0400
c++: UNBOUND_CLASS_TEMPLATE context substitution [PR119981]
In r15-123 and r14-11434 we unconditionally set processing_template_decl
when substituting the context of an UNBOUND_CLASS_TEMPLATE, in order to
handle instantiation of the dependently scoped friend declaration
template
template
friend class A::B;
where the scope A remains dependent after instantiation. But this
turns out to misbehave for the UNBOUND_CLASS_TEMPLATE in the below
testcase representing
g<[]{}>::template fn
since with the flag set substituting the args of test3 into the lambda
causes us to defer the substitution and yield a lambda that still looks
dependent, which in turn makes g<[]{}> still dependent and not suitable
for qualified name lookup.
This patch restricts setting processing_template_decl during
UNBOUND_CLASS_TEMPLATE substitution to the case where there are multiple
levels of introduced template parameters, as in the friend declaration.
(This means we need to substitute the template parameter list(s) first,
which makes sense since they lexically appear first.)
PR c++/119981
PR c++/119378
gcc/cp/ChangeLog:
* pt.cc (tsubst) : Substitute
into template parameter list first. When substituting the
context, only set processing_template_decl if there's more
than one level of introduced template parameters.
gcc/testsuite/ChangeLog:
* g++.dg/cpp2a/lambda-targ15.C: New test.
Reviewed-by: Jason Merrill
(cherry picked from commit 05ea8baf6ff96c77a9a2467d5c45b1ed575fca92)
Diff:
---
gcc/cp/pt.cc | 20 +---
gcc/testsuite/g++.dg/cpp2a/lambda-targ15.C | 17 +
2 files changed, 30 insertions(+), 7 deletions(-)
diff --git a/gcc/cp/pt.cc b/gcc/cp/pt.cc
index a71705fd085b..1f972c79b998 100644
--- a/gcc/cp/pt.cc
+++ b/gcc/cp/pt.cc
@@ -17177,18 +17177,24 @@ tsubst (tree t, tree args, tsubst_flags_t complain,
tree in_decl)
case UNBOUND_CLASS_TEMPLATE:
{
- ++processing_template_decl;
- tree ctx = tsubst_entering_scope (TYPE_CONTEXT (t), args,
- complain, in_decl);
- --processing_template_decl;
tree name = TYPE_IDENTIFIER (t);
+ if (name == error_mark_node)
+ return error_mark_node;
+
tree parm_list = DECL_TEMPLATE_PARMS (TYPE_NAME (t));
+ parm_list = tsubst_template_parms (parm_list, args, complain);
+ if (parm_list == error_mark_node)
+ return error_mark_node;
- if (ctx == error_mark_node || name == error_mark_node)
+ if (parm_list && TMPL_PARMS_DEPTH (parm_list) > 1)
+ ++processing_template_decl;
+ tree ctx = tsubst_entering_scope (TYPE_CONTEXT (t), args,
+ complain, in_decl);
+ if (parm_list && TMPL_PARMS_DEPTH (parm_list) > 1)
+ --processing_template_decl;
+ if (ctx == error_mark_node)
return error_mark_node;
- if (parm_list)
- parm_list = tsubst_template_parms (parm_list, args, complain);
return make_unbound_class_template (ctx, name, parm_list, complain);
}
diff --git a/gcc/testsuite/g++.dg/cpp2a/lambda-targ15.C
b/gcc/testsuite/g++.dg/cpp2a/lambda-targ15.C
new file mode 100644
index ..90160a52a6ef
--- /dev/null
+++ b/gcc/testsuite/g++.dg/cpp2a/lambda-targ15.C
@@ -0,0 +1,17 @@
+// PR c++/119981
+// { dg-do compile { target c++20 } }
+
+template class P>
+struct mp_copy_if{};
+
+template
+struct g {
+ template struct fn{};
+};
+
+template
+void test3() {
+ mp_copy_if::template fn> b;
+}
+
+template void test3();
[gcc r16-299] RISC-V: Fix missing implied Zicsr from Zve32x
https://gcc.gnu.org/g:a992164c2899735525a7a267654473b7e527ef0d
commit r16-299-ga992164c2899735525a7a267654473b7e527ef0d
Author: Jerry Zhang Jian
Date: Wed Apr 30 15:34:07 2025 +0800
RISC-V: Fix missing implied Zicsr from Zve32x
The Zve32x extension depends on the Zicsr extension.
Currently, enabling Zve32x alone does not automatically imply Zicsr in GCC.
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: Add Zve32x depends on Zicsr
gcc/testsuite/ChangeLog:
* gcc.target/riscv/predef-19.c: set the march to rv64im_zve32x
instead of rv64gc_zve32x to avoid Zicsr implied by g. Extra m is
added to avoid current 'V' extension requires 'M' extension
Signed-off-by: Jerry Zhang Jian
Diff:
---
gcc/common/config/riscv/riscv-common.cc| 1 +
gcc/testsuite/gcc.target/riscv/predef-19.c | 34 ++
2 files changed, 8 insertions(+), 27 deletions(-)
diff --git a/gcc/common/config/riscv/riscv-common.cc
b/gcc/common/config/riscv/riscv-common.cc
index 15df22d53770..145a0f2bd95f 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -137,6 +137,7 @@ static const riscv_implied_info_t riscv_implied_info[] =
{"zve64f", "f"},
{"zve64d", "d"},
+ {"zve32x", "zicsr"},
{"zve32x", "zvl32b"},
{"zve32f", "zve32x"},
{"zve32f", "zvl32b"},
diff --git a/gcc/testsuite/gcc.target/riscv/predef-19.c
b/gcc/testsuite/gcc.target/riscv/predef-19.c
index 2b90702192ba..ca3d57abca90 100644
--- a/gcc/testsuite/gcc.target/riscv/predef-19.c
+++ b/gcc/testsuite/gcc.target/riscv/predef-19.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O2 -march=rv64gc_zve32x -mabi=lp64d -mcmodel=medlow
-misa-spec=2.2" } */
+/* { dg-options "-O2 -march=rv64im_zve32x -mabi=lp64 -mcmodel=medlow
-misa-spec=2.2" } */
int main () {
@@ -15,50 +15,30 @@ int main () {
#error "__riscv_i"
#endif
-#if !defined(__riscv_c)
-#error "__riscv_c"
-#endif
-
#if defined(__riscv_e)
#error "__riscv_e"
#endif
-#if !defined(__riscv_a)
-#error "__riscv_a"
-#endif
-
#if !defined(__riscv_m)
#error "__riscv_m"
#endif
-#if !defined(__riscv_f)
-#error "__riscv_f"
-#endif
-
-#if !defined(__riscv_d)
-#error "__riscv_d"
-#endif
-
-#if defined(__riscv_v)
-#error "__riscv_v"
+#if !defined(__riscv_zicsr)
+#error "__riscv_zicsr"
#endif
-#if defined(__riscv_zvl128b)
-#error "__riscv_zvl128b"
+#if !defined(_riscv_zmmul)
+#error "__riscv_zmmul"
#endif
-#if defined(__riscv_zvl64b)
-#error "__riscv_zvl64b"
+#if !defined(__riscv_zve32x)
+#error "__riscv_zve32x"
#endif
#if !defined(__riscv_zvl32b)
#error "__riscv_zvl32b"
#endif
-#if !defined(__riscv_zve32x)
-#error "__riscv_zve32x"
-#endif
-
#if !defined(__riscv_vector)
#error "__riscv_vector"
#endif
[gcc r16-301] AVR: target/119989 - Add missing clobbers to xload__libgcc.
https://gcc.gnu.org/g:4dc40eddbe69566869f7aafb78c31c4850b8aeb7
commit r16-301-g4dc40eddbe69566869f7aafb78c31c4850b8aeb7
Author: Georg-Johann Lay
Date: Wed Apr 30 08:43:51 2025 +0200
AVR: target/119989 - Add missing clobbers to xload__libgcc.
libgcc's __xload_1...4 is clobbering Z (and also R21 is some cases),
but avr.md had clobbers of respective GPRs only up to reload.
Outcome was that code reading from the same __memx address twice
could be wrong. This patch adds respective clobbers.
Forward-port from 2025-04-30 r14-11703
PR target/119989
gcc/
* config/avr/avr.md (xload__libgcc): Clobber R21, Z.
gcc/testsuite/
* gcc.target/avr/torture/pr119989.h: New file.
* gcc.target/avr/torture/pr119989-memx-1.c: New test.
* gcc.target/avr/torture/pr119989-memx-2.c: New test.
* gcc.target/avr/torture/pr119989-memx-3.c: New test.
* gcc.target/avr/torture/pr119989-memx-4.c: New test.
* gcc.target/avr/torture/pr119989-flashx-1.c: New test.
* gcc.target/avr/torture/pr119989-flashx-2.c: New test.
* gcc.target/avr/torture/pr119989-flashx-3.c: New test.
* gcc.target/avr/torture/pr119989-flashx-4.c: New test.
(cherry picked from commit 1ca1c1fc3b58ae5e1d3db4f5a2014132fe69f82a)
Diff:
---
gcc/config/avr/avr.md | 4 +++
.../gcc.target/avr/torture/pr119989-flashx-1.c | 7
.../gcc.target/avr/torture/pr119989-flashx-2.c | 7
.../gcc.target/avr/torture/pr119989-flashx-3.c | 7
.../gcc.target/avr/torture/pr119989-flashx-4.c | 7
.../gcc.target/avr/torture/pr119989-memx-1.c | 7
.../gcc.target/avr/torture/pr119989-memx-2.c | 7
.../gcc.target/avr/torture/pr119989-memx-3.c | 7
.../gcc.target/avr/torture/pr119989-memx-4.c | 7
gcc/testsuite/gcc.target/avr/torture/pr119989.h| 37 ++
10 files changed, 97 insertions(+)
diff --git a/gcc/config/avr/avr.md b/gcc/config/avr/avr.md
index 1c4e44dcfe41..01b8e4bce4cf 100644
--- a/gcc/config/avr/avr.md
+++ b/gcc/config/avr/avr.md
@@ -718,6 +718,8 @@
"&& reload_completed"
[(parallel [(set (reg:MOVMODE REG_22)
(match_dup 0))
+ (clobber (reg:QI REG_21))
+ (clobber (reg:HI REG_Z))
(clobber (reg:CC REG_CC))])]
{
operands[0] = SET_SRC (single_set (curr_insn));
@@ -727,6 +729,8 @@
[(set (reg:MOVMODE REG_22)
(mem:MOVMODE (lo_sum:PSI (reg:QI REG_21)
(reg:HI REG_Z
+ (clobber (reg:QI REG_21))
+ (clobber (reg:HI REG_Z))
(clobber (reg:CC REG_CC))]
"reload_completed
&& (avr_load_libgcc_insn_p (insn, ADDR_SPACE_MEMX, true)
diff --git a/gcc/testsuite/gcc.target/avr/torture/pr119989-flashx-1.c
b/gcc/testsuite/gcc.target/avr/torture/pr119989-flashx-1.c
new file mode 100644
index ..086d1eab0e24
--- /dev/null
+++ b/gcc/testsuite/gcc.target/avr/torture/pr119989-flashx-1.c
@@ -0,0 +1,7 @@
+/* { dg-do run { target { ! avr_tiny } } } */
+/* { dg-additional-options "-std=gnu99" } */
+
+typedef __UINT8_TYPE__ TYP;
+#define AS __flashx
+
+#include "pr119989.h"
diff --git a/gcc/testsuite/gcc.target/avr/torture/pr119989-flashx-2.c
b/gcc/testsuite/gcc.target/avr/torture/pr119989-flashx-2.c
new file mode 100644
index ..d053ab9c109a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/avr/torture/pr119989-flashx-2.c
@@ -0,0 +1,7 @@
+/* { dg-do run { target { ! avr_tiny } } } */
+/* { dg-additional-options "-std=gnu99" } */
+
+typedef __UINT16_TYPE__ TYP;
+#define AS __flashx
+
+#include "pr119989.h"
diff --git a/gcc/testsuite/gcc.target/avr/torture/pr119989-flashx-3.c
b/gcc/testsuite/gcc.target/avr/torture/pr119989-flashx-3.c
new file mode 100644
index ..1a5e8f0488ac
--- /dev/null
+++ b/gcc/testsuite/gcc.target/avr/torture/pr119989-flashx-3.c
@@ -0,0 +1,7 @@
+/* { dg-do run { target { ! avr_tiny } } } */
+/* { dg-additional-options "-std=gnu99" } */
+
+__extension__ typedef __uint24 TYP;
+#define AS __flashx
+
+#include "pr119989.h"
diff --git a/gcc/testsuite/gcc.target/avr/torture/pr119989-flashx-4.c
b/gcc/testsuite/gcc.target/avr/torture/pr119989-flashx-4.c
new file mode 100644
index ..63fb52c146ff
--- /dev/null
+++ b/gcc/testsuite/gcc.target/avr/torture/pr119989-flashx-4.c
@@ -0,0 +1,7 @@
+/* { dg-do run { target { ! avr_tiny } } } */
+/* { dg-additional-options "-std=gnu99" } */
+
+typedef __UINT32_TYPE__ TYP;
+#define AS __flashx
+
+#include "pr119989.h"
diff --git a/gcc/testsuite/gcc.target/avr/torture/pr119989-memx-1.c
b/gcc/testsuite/gcc.target/avr/torture/pr119989-memx-1.c
new file mode 100644
index ..45535178bdb3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/avr/torture/pr119989-memx-1.c
@@ -0,0 +1,7 @@
+/* { dg-do run { target { ! avr_tiny } } } */
+/* { dg-additional-options "-std=gnu99"
[gcc r14-11704] Fix GNAT build failure for x86/FreeBSD
https://gcc.gnu.org/g:51d76593947a2dba90f52b394fdf70602fa8ff6a commit r14-11704-g51d76593947a2dba90f52b394fdf70602fa8ff6a Author: Eric Botcazou Date: Wed Apr 30 12:41:36 2025 +0200 Fix GNAT build failure for x86/FreeBSD gcc/ada/ PR ada/112958 * Makefile.rtl (LIBGNAT_TARGET_PAIRS) [x86 FreeBSD]: Add specific version of s-dorepr.adb. * libgnat/s-dorepr__freebsd.adb: New file. Diff: --- gcc/ada/Makefile.rtl | 1 + gcc/ada/libgnat/s-dorepr__freebsd.adb | 172 ++ 2 files changed, 173 insertions(+) diff --git a/gcc/ada/Makefile.rtl b/gcc/ada/Makefile.rtl index 32cbdb69247b..d2715e698c4d 100644 --- a/gcc/ada/Makefile.rtl +++ b/gcc/ada/Makefile.rtl @@ -1730,6 +1730,7 @@ ifeq ($(strip $(filter-out %86 freebsd%,$(target_cpu) $(target_os))),) $(TRASYM_DWARF_UNIX_PAIRS) \ $(ATOMICS_TARGET_PAIRS) \ $(X86_TARGET_PAIRS) \ + s-dorepr.adbhttp://www.gnu.org/licenses/>. -- +-- -- +-- GNAT was originally developed by the GNAT team at New York University. -- +-- Extensive contributions were provided by Ada Core Technologies Inc. -- +-- -- +-- + +-- This is the x86/FreeBSD version of the separate package body + +with Interfaces; use Interfaces; + +separate (System.Double_Real) + +package body Product is + + procedure Split (N : Num; Hi : out Num; Lo : out Num); + -- Compute high part and low part of N + + --- + -- Split -- + --- + + -- We use a bit manipulation algorithm instead of Veltkamp's splitting + -- because it is faster and has the property that the magnitude of the + -- high part is never larger than that of the input number, which will + -- avoid spurious overflows in the Two_Prod algorithm. + + -- See the recent paper by Claude-Pierre Jeannerod, Jean-Michel Muller + -- and Paul Zimmermann: On various ways to split a floating-point number + -- ARITH 2018 - 25th IEEE Symposium on Computer Arithmetic, Jun 2018, + -- Amherst (MA), United States, pages 53-60. + + procedure Split (N : Num; Hi : out Num; Lo : out Num) is + X : Num; + + begin + -- Spill the input into the appropriate (maybe larger) bit container, + -- mask out the low bits and reload the modified value. + + case Num'Machine_Mantissa is + when 24 => +declare + Rep32 : aliased Interfaces.Unsigned_32; + Temp : Num := N with Address => Rep32'Address; + pragma Annotate (CodePeer, Modified, Rep32); + +begin + -- Mask out the low 12 bits + + Rep32 := Rep32 and 16#F000#; + + X := Temp; +end; + + when 53 => +declare + Rep64 : aliased array (1 .. 2) of Interfaces.Unsigned_64; + Temp : Num := N with Address => Rep64'Address; + pragma Annotate (CodePeer, Modified, Rep64); + +begin + -- Mask out the low 27 bits + + Rep64 (1) := Rep64 (1) and 16#F800#; + + X := Temp; +end; + + when 64 => +declare + Rep80 : aliased array (1 .. 2) of Interfaces.Unsigned_64; + Temp : Num := N with Address => Rep80'Address; + pragma Annotate (CodePeer, Modified, Rep80); + +begin + -- Mask out the low 32 bits + + if System.Default_Bit_Order = High_Order_First then + Rep80 (1) := Rep80 (1) and 16##; + Rep80 (2) := Rep80 (2) and 16##; + else + Rep80 (1) := Rep80 (1) and 16##; + end if; + + X := Temp; +end; + + when others => +raise Program_Error; + end case; + + -- Deal with denormalized numbers + + if X = 0.0 then + Hi := N; + Lo := 0.0; + else + Hi := X; + Lo := N - X; + end if; + end Split; + + -- + -- Two_Prod -- + -- + + function Two_Prod (A, B : Num) return Double_T is + P : constant Num := A * B; + + Ahi, Alo, Bhi, Blo, E : Num; + + begin + if Is_Infinity (P) or else Is_Zero (P) then + return (P, 0.0); + + else + Split (A, Ahi, Alo); + Split (B, Bhi, Blo); + + E := ((Ahi * Bhi - P) + Ahi * Blo + Alo * Bhi) + Alo * Blo; + + return (P, E); + end if; + end Two_Prod; + + - + -- Two_Sqr -- + - + + function Two_Sqr (A : Num) return Double_T is + Q : constant Num := A * A; + + Hi, Lo,
[gcc r13-9626] Fix GNAT build failure for x86/FreeBSD
https://gcc.gnu.org/g:2317297a745a5b73015074621df9290569fb67d3 commit r13-9626-g2317297a745a5b73015074621df9290569fb67d3 Author: Eric Botcazou Date: Wed Apr 30 12:41:36 2025 +0200 Fix GNAT build failure for x86/FreeBSD gcc/ada/ PR ada/112958 * Makefile.rtl (LIBGNAT_TARGET_PAIRS) [x86 FreeBSD]: Add specific version of s-dorepr.adb. * libgnat/s-dorepr__freebsd.adb: New file. Diff: --- gcc/ada/Makefile.rtl | 1 + gcc/ada/libgnat/s-dorepr__freebsd.adb | 172 ++ 2 files changed, 173 insertions(+) diff --git a/gcc/ada/Makefile.rtl b/gcc/ada/Makefile.rtl index 96306f8cc9ae..fed92be59fc5 100644 --- a/gcc/ada/Makefile.rtl +++ b/gcc/ada/Makefile.rtl @@ -1721,6 +1721,7 @@ ifeq ($(strip $(filter-out %86 freebsd%,$(target_cpu) $(target_os))),) $(TRASYM_DWARF_UNIX_PAIRS) \ $(ATOMICS_TARGET_PAIRS) \ $(X86_TARGET_PAIRS) \ + s-dorepr.adbhttp://www.gnu.org/licenses/>. -- +-- -- +-- GNAT was originally developed by the GNAT team at New York University. -- +-- Extensive contributions were provided by Ada Core Technologies Inc. -- +-- -- +-- + +-- This is the x86/FreeBSD version of the separate package body + +with Interfaces; use Interfaces; + +separate (System.Double_Real) + +package body Product is + + procedure Split (N : Num; Hi : out Num; Lo : out Num); + -- Compute high part and low part of N + + --- + -- Split -- + --- + + -- We use a bit manipulation algorithm instead of Veltkamp's splitting + -- because it is faster and has the property that the magnitude of the + -- high part is never larger than that of the input number, which will + -- avoid spurious overflows in the Two_Prod algorithm. + + -- See the recent paper by Claude-Pierre Jeannerod, Jean-Michel Muller + -- and Paul Zimmermann: On various ways to split a floating-point number + -- ARITH 2018 - 25th IEEE Symposium on Computer Arithmetic, Jun 2018, + -- Amherst (MA), United States, pages 53-60. + + procedure Split (N : Num; Hi : out Num; Lo : out Num) is + X : Num; + + begin + -- Spill the input into the appropriate (maybe larger) bit container, + -- mask out the low bits and reload the modified value. + + case Num'Machine_Mantissa is + when 24 => +declare + Rep32 : aliased Interfaces.Unsigned_32; + Temp : Num := N with Address => Rep32'Address; + pragma Annotate (CodePeer, Modified, Rep32); + +begin + -- Mask out the low 12 bits + + Rep32 := Rep32 and 16#F000#; + + X := Temp; +end; + + when 53 => +declare + Rep64 : aliased array (1 .. 2) of Interfaces.Unsigned_64; + Temp : Num := N with Address => Rep64'Address; + pragma Annotate (CodePeer, Modified, Rep64); + +begin + -- Mask out the low 27 bits + + Rep64 (1) := Rep64 (1) and 16#F800#; + + X := Temp; +end; + + when 64 => +declare + Rep80 : aliased array (1 .. 2) of Interfaces.Unsigned_64; + Temp : Num := N with Address => Rep80'Address; + pragma Annotate (CodePeer, Modified, Rep80); + +begin + -- Mask out the low 32 bits + + if System.Default_Bit_Order = High_Order_First then + Rep80 (1) := Rep80 (1) and 16##; + Rep80 (2) := Rep80 (2) and 16##; + else + Rep80 (1) := Rep80 (1) and 16##; + end if; + + X := Temp; +end; + + when others => +raise Program_Error; + end case; + + -- Deal with denormalized numbers + + if X = 0.0 then + Hi := N; + Lo := 0.0; + else + Hi := X; + Lo := N - X; + end if; + end Split; + + -- + -- Two_Prod -- + -- + + function Two_Prod (A, B : Num) return Double_T is + P : constant Num := A * B; + + Ahi, Alo, Bhi, Blo, E : Num; + + begin + if Is_Infinity (P) or else Is_Zero (P) then + return (P, 0.0); + + else + Split (A, Ahi, Alo); + Split (B, Bhi, Blo); + + E := ((Ahi * Bhi - P) + Ahi * Blo + Alo * Bhi) + Alo * Blo; + + return (P, E); + end if; + end Two_Prod; + + - + -- Two_Sqr -- + - + + function Two_Sqr (A : Num) return Double_T is + Q : constant Num := A * A; + + Hi, Lo,
[gcc r16-302] Fix GNAT build failure for x86/FreeBSD
https://gcc.gnu.org/g:85e4f21f9e90fc70b8c7c75ec8e4d0766008ac6e commit r16-302-g85e4f21f9e90fc70b8c7c75ec8e4d0766008ac6e Author: Eric Botcazou Date: Wed Apr 30 12:41:36 2025 +0200 Fix GNAT build failure for x86/FreeBSD gcc/ada/ PR ada/112958 * Makefile.rtl (LIBGNAT_TARGET_PAIRS) [x86 FreeBSD]: Add specific version of s-dorepr.adb. * libgnat/s-dorepr__freebsd.adb: New file. Diff: --- gcc/ada/Makefile.rtl | 1 + gcc/ada/libgnat/s-dorepr__freebsd.adb | 172 ++ 2 files changed, 173 insertions(+) diff --git a/gcc/ada/Makefile.rtl b/gcc/ada/Makefile.rtl index 61600adf1f32..cb41e6887cdf 100644 --- a/gcc/ada/Makefile.rtl +++ b/gcc/ada/Makefile.rtl @@ -1900,6 +1900,7 @@ ifeq ($(strip $(filter-out %86 freebsd%,$(target_cpu) $(target_os))),) $(TRASYM_DWARF_UNIX_PAIRS) \ $(ATOMICS_TARGET_PAIRS) \ $(X86_TARGET_PAIRS) \ + s-dorepr.adbhttp://www.gnu.org/licenses/>. -- +-- -- +-- GNAT was originally developed by the GNAT team at New York University. -- +-- Extensive contributions were provided by Ada Core Technologies Inc. -- +-- -- +-- + +-- This is the x86/FreeBSD version of the separate package body + +with Interfaces; use Interfaces; + +separate (System.Double_Real) + +package body Product is + + procedure Split (N : Num; Hi : out Num; Lo : out Num); + -- Compute high part and low part of N + + --- + -- Split -- + --- + + -- We use a bit manipulation algorithm instead of Veltkamp's splitting + -- because it is faster and has the property that the magnitude of the + -- high part is never larger than that of the input number, which will + -- avoid spurious overflows in the Two_Prod algorithm. + + -- See the recent paper by Claude-Pierre Jeannerod, Jean-Michel Muller + -- and Paul Zimmermann: On various ways to split a floating-point number + -- ARITH 2018 - 25th IEEE Symposium on Computer Arithmetic, Jun 2018, + -- Amherst (MA), United States, pages 53-60. + + procedure Split (N : Num; Hi : out Num; Lo : out Num) is + X : Num; + + begin + -- Spill the input into the appropriate (maybe larger) bit container, + -- mask out the low bits and reload the modified value. + + case Num'Machine_Mantissa is + when 24 => +declare + Rep32 : aliased Interfaces.Unsigned_32; + Temp : Num := N with Address => Rep32'Address; + pragma Annotate (CodePeer, Modified, Rep32); + +begin + -- Mask out the low 12 bits + + Rep32 := Rep32 and 16#F000#; + + X := Temp; +end; + + when 53 => +declare + Rep64 : aliased array (1 .. 2) of Interfaces.Unsigned_64; + Temp : Num := N with Address => Rep64'Address; + pragma Annotate (CodePeer, Modified, Rep64); + +begin + -- Mask out the low 27 bits + + Rep64 (1) := Rep64 (1) and 16#F800#; + + X := Temp; +end; + + when 64 => +declare + Rep80 : aliased array (1 .. 2) of Interfaces.Unsigned_64; + Temp : Num := N with Address => Rep80'Address; + pragma Annotate (CodePeer, Modified, Rep80); + +begin + -- Mask out the low 32 bits + + if System.Default_Bit_Order = High_Order_First then + Rep80 (1) := Rep80 (1) and 16##; + Rep80 (2) := Rep80 (2) and 16##; + else + Rep80 (1) := Rep80 (1) and 16##; + end if; + + X := Temp; +end; + + when others => +raise Program_Error; + end case; + + -- Deal with denormalized numbers + + if X = 0.0 then + Hi := N; + Lo := 0.0; + else + Hi := X; + Lo := N - X; + end if; + end Split; + + -- + -- Two_Prod -- + -- + + function Two_Prod (A, B : Num) return Double_T is + P : constant Num := A * B; + + Ahi, Alo, Bhi, Blo, E : Num; + + begin + if Is_Infinity (P) or else Is_Zero (P) then + return (P, 0.0); + + else + Split (A, Ahi, Alo); + Split (B, Bhi, Blo); + + E := ((Ahi * Bhi - P) + Ahi * Blo + Alo * Bhi) + Alo * Blo; + + return (P, E); + end if; + end Two_Prod; + + - + -- Two_Sqr -- + - + + function Two_Sqr (A : Num) return Double_T is + Q : constant Num := A * A; + + Hi, Lo, E
[gcc r15-9604] Fix GNAT build failure for x86/FreeBSD
https://gcc.gnu.org/g:01ebce59db2039c6d63b565295095fd6e3b02d57 commit r15-9604-g01ebce59db2039c6d63b565295095fd6e3b02d57 Author: Eric Botcazou Date: Wed Apr 30 12:41:36 2025 +0200 Fix GNAT build failure for x86/FreeBSD gcc/ada/ PR ada/112958 * Makefile.rtl (LIBGNAT_TARGET_PAIRS) [x86 FreeBSD]: Add specific version of s-dorepr.adb. * libgnat/s-dorepr__freebsd.adb: New file. Diff: --- gcc/ada/Makefile.rtl | 1 + gcc/ada/libgnat/s-dorepr__freebsd.adb | 172 ++ 2 files changed, 173 insertions(+) diff --git a/gcc/ada/Makefile.rtl b/gcc/ada/Makefile.rtl index 61600adf1f32..cb41e6887cdf 100644 --- a/gcc/ada/Makefile.rtl +++ b/gcc/ada/Makefile.rtl @@ -1900,6 +1900,7 @@ ifeq ($(strip $(filter-out %86 freebsd%,$(target_cpu) $(target_os))),) $(TRASYM_DWARF_UNIX_PAIRS) \ $(ATOMICS_TARGET_PAIRS) \ $(X86_TARGET_PAIRS) \ + s-dorepr.adbhttp://www.gnu.org/licenses/>. -- +-- -- +-- GNAT was originally developed by the GNAT team at New York University. -- +-- Extensive contributions were provided by Ada Core Technologies Inc. -- +-- -- +-- + +-- This is the x86/FreeBSD version of the separate package body + +with Interfaces; use Interfaces; + +separate (System.Double_Real) + +package body Product is + + procedure Split (N : Num; Hi : out Num; Lo : out Num); + -- Compute high part and low part of N + + --- + -- Split -- + --- + + -- We use a bit manipulation algorithm instead of Veltkamp's splitting + -- because it is faster and has the property that the magnitude of the + -- high part is never larger than that of the input number, which will + -- avoid spurious overflows in the Two_Prod algorithm. + + -- See the recent paper by Claude-Pierre Jeannerod, Jean-Michel Muller + -- and Paul Zimmermann: On various ways to split a floating-point number + -- ARITH 2018 - 25th IEEE Symposium on Computer Arithmetic, Jun 2018, + -- Amherst (MA), United States, pages 53-60. + + procedure Split (N : Num; Hi : out Num; Lo : out Num) is + X : Num; + + begin + -- Spill the input into the appropriate (maybe larger) bit container, + -- mask out the low bits and reload the modified value. + + case Num'Machine_Mantissa is + when 24 => +declare + Rep32 : aliased Interfaces.Unsigned_32; + Temp : Num := N with Address => Rep32'Address; + pragma Annotate (CodePeer, Modified, Rep32); + +begin + -- Mask out the low 12 bits + + Rep32 := Rep32 and 16#F000#; + + X := Temp; +end; + + when 53 => +declare + Rep64 : aliased array (1 .. 2) of Interfaces.Unsigned_64; + Temp : Num := N with Address => Rep64'Address; + pragma Annotate (CodePeer, Modified, Rep64); + +begin + -- Mask out the low 27 bits + + Rep64 (1) := Rep64 (1) and 16#F800#; + + X := Temp; +end; + + when 64 => +declare + Rep80 : aliased array (1 .. 2) of Interfaces.Unsigned_64; + Temp : Num := N with Address => Rep80'Address; + pragma Annotate (CodePeer, Modified, Rep80); + +begin + -- Mask out the low 32 bits + + if System.Default_Bit_Order = High_Order_First then + Rep80 (1) := Rep80 (1) and 16##; + Rep80 (2) := Rep80 (2) and 16##; + else + Rep80 (1) := Rep80 (1) and 16##; + end if; + + X := Temp; +end; + + when others => +raise Program_Error; + end case; + + -- Deal with denormalized numbers + + if X = 0.0 then + Hi := N; + Lo := 0.0; + else + Hi := X; + Lo := N - X; + end if; + end Split; + + -- + -- Two_Prod -- + -- + + function Two_Prod (A, B : Num) return Double_T is + P : constant Num := A * B; + + Ahi, Alo, Bhi, Blo, E : Num; + + begin + if Is_Infinity (P) or else Is_Zero (P) then + return (P, 0.0); + + else + Split (A, Ahi, Alo); + Split (B, Bhi, Blo); + + E := ((Ahi * Bhi - P) + Ahi * Blo + Alo * Bhi) + Alo * Blo; + + return (P, E); + end if; + end Two_Prod; + + - + -- Two_Sqr -- + - + + function Two_Sqr (A : Num) return Double_T is + Q : constant Num := A * A; + + Hi, Lo,
[gcc r12-11078] Fix GNAT build failure for x86/FreeBSD
https://gcc.gnu.org/g:d30dfa8586b5d12e341a7965ef7970a2b8402519 commit r12-11078-gd30dfa8586b5d12e341a7965ef7970a2b8402519 Author: Eric Botcazou Date: Wed Apr 30 12:41:36 2025 +0200 Fix GNAT build failure for x86/FreeBSD gcc/ada/ PR ada/112958 * Makefile.rtl (LIBGNAT_TARGET_PAIRS) [x86 FreeBSD]: Add specific version of s-dorepr.adb. * libgnat/s-dorepr__freebsd.adb: New file. Diff: --- gcc/ada/Makefile.rtl | 1 + gcc/ada/libgnat/s-dorepr__freebsd.adb | 172 ++ 2 files changed, 173 insertions(+) diff --git a/gcc/ada/Makefile.rtl b/gcc/ada/Makefile.rtl index aaf853e3a2a5..2d8e5d14137f 100644 --- a/gcc/ada/Makefile.rtl +++ b/gcc/ada/Makefile.rtl @@ -1805,6 +1805,7 @@ ifeq ($(strip $(filter-out %86 freebsd%,$(target_cpu) $(target_os))),) $(TRASYM_DWARF_UNIX_PAIRS) \ $(ATOMICS_TARGET_PAIRS) \ $(X86_TARGET_PAIRS) \ + s-dorepr.adbhttp://www.gnu.org/licenses/>. -- +-- -- +-- GNAT was originally developed by the GNAT team at New York University. -- +-- Extensive contributions were provided by Ada Core Technologies Inc. -- +-- -- +-- + +-- This is the x86/FreeBSD version of the separate package body + +with Interfaces; use Interfaces; + +separate (System.Double_Real) + +package body Product is + + procedure Split (N : Num; Hi : out Num; Lo : out Num); + -- Compute high part and low part of N + + --- + -- Split -- + --- + + -- We use a bit manipulation algorithm instead of Veltkamp's splitting + -- because it is faster and has the property that the magnitude of the + -- high part is never larger than that of the input number, which will + -- avoid spurious overflows in the Two_Prod algorithm. + + -- See the recent paper by Claude-Pierre Jeannerod, Jean-Michel Muller + -- and Paul Zimmermann: On various ways to split a floating-point number + -- ARITH 2018 - 25th IEEE Symposium on Computer Arithmetic, Jun 2018, + -- Amherst (MA), United States, pages 53-60. + + procedure Split (N : Num; Hi : out Num; Lo : out Num) is + X : Num; + + begin + -- Spill the input into the appropriate (maybe larger) bit container, + -- mask out the low bits and reload the modified value. + + case Num'Machine_Mantissa is + when 24 => +declare + Rep32 : aliased Interfaces.Unsigned_32; + Temp : Num := N with Address => Rep32'Address; + pragma Annotate (CodePeer, Modified, Rep32); + +begin + -- Mask out the low 12 bits + + Rep32 := Rep32 and 16#F000#; + + X := Temp; +end; + + when 53 => +declare + Rep64 : aliased array (1 .. 2) of Interfaces.Unsigned_64; + Temp : Num := N with Address => Rep64'Address; + pragma Annotate (CodePeer, Modified, Rep64); + +begin + -- Mask out the low 27 bits + + Rep64 (1) := Rep64 (1) and 16#F800#; + + X := Temp; +end; + + when 64 => +declare + Rep80 : aliased array (1 .. 2) of Interfaces.Unsigned_64; + Temp : Num := N with Address => Rep80'Address; + pragma Annotate (CodePeer, Modified, Rep80); + +begin + -- Mask out the low 32 bits + + if System.Default_Bit_Order = High_Order_First then + Rep80 (1) := Rep80 (1) and 16##; + Rep80 (2) := Rep80 (2) and 16##; + else + Rep80 (1) := Rep80 (1) and 16##; + end if; + + X := Temp; +end; + + when others => +raise Program_Error; + end case; + + -- Deal with denormalized numbers + + if X = 0.0 then + Hi := N; + Lo := 0.0; + else + Hi := X; + Lo := N - X; + end if; + end Split; + + -- + -- Two_Prod -- + -- + + function Two_Prod (A, B : Num) return Double_T is + P : constant Num := A * B; + + Ahi, Alo, Bhi, Blo, E : Num; + + begin + if Is_Infinity (P) or else Is_Zero (P) then + return (P, 0.0); + + else + Split (A, Ahi, Alo); + Split (B, Bhi, Blo); + + E := ((Ahi * Bhi - P) + Ahi * Blo + Alo * Bhi) + Alo * Blo; + + return (P, E); + end if; + end Two_Prod; + + - + -- Two_Sqr -- + - + + function Two_Sqr (A : Num) return Double_T is + Q : constant Num := A * A; + + Hi, Lo,
[gcc r15-9606] testsuite: Force -mcmodel=small for gcc.target/aarch64/pr115258.c
https://gcc.gnu.org/g:c9d4d3ba15c55e108f5f9a28d2609a698634a5db
commit r15-9606-gc9d4d3ba15c55e108f5f9a28d2609a698634a5db
Author: Richard Sandiford
Date: Wed Apr 30 16:29:54 2025 +0100
testsuite: Force -mcmodel=small for gcc.target/aarch64/pr115258.c
The test implicitly assumed the default code model and so failed
for -mcmodel=tiny.
gcc/testsuite/
* gcc.target/aarch64/pr115258.c: Add -mcmodel=small.
(cherry picked from commit 3584aab37f54bcd220c7061568af777e37f4f6ed)
Diff:
---
gcc/testsuite/gcc.target/aarch64/pr115258.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/testsuite/gcc.target/aarch64/pr115258.c
b/gcc/testsuite/gcc.target/aarch64/pr115258.c
index 9a489d4604c0..f60b50a0a3c0 100644
--- a/gcc/testsuite/gcc.target/aarch64/pr115258.c
+++ b/gcc/testsuite/gcc.target/aarch64/pr115258.c
@@ -1,4 +1,4 @@
-/* { dg-options "-O2" } */
+/* { dg-options "-O2 -mcmodel=small" } */
/* { dg-final { check-function-bodies "**" "" "" } } */
/*
[gcc r16-310] testsuite: Force -mcmodel=small for gcc.target/aarch64/pr115258.c
https://gcc.gnu.org/g:3584aab37f54bcd220c7061568af777e37f4f6ed
commit r16-310-g3584aab37f54bcd220c7061568af777e37f4f6ed
Author: Richard Sandiford
Date: Wed Apr 30 16:28:52 2025 +0100
testsuite: Force -mcmodel=small for gcc.target/aarch64/pr115258.c
The test implicitly assumed the default code model and so failed
for -mcmodel=tiny.
gcc/testsuite/
* gcc.target/aarch64/pr115258.c: Add -mcmodel=small.
Diff:
---
gcc/testsuite/gcc.target/aarch64/pr115258.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/testsuite/gcc.target/aarch64/pr115258.c
b/gcc/testsuite/gcc.target/aarch64/pr115258.c
index 9a489d4604c0..f60b50a0a3c0 100644
--- a/gcc/testsuite/gcc.target/aarch64/pr115258.c
+++ b/gcc/testsuite/gcc.target/aarch64/pr115258.c
@@ -1,4 +1,4 @@
-/* { dg-options "-O2" } */
+/* { dg-options "-O2 -mcmodel=small" } */
/* { dg-final { check-function-bodies "**" "" "" } } */
/*
[gcc r14-11705] testsuite: Force -mcmodel=small for gcc.target/aarch64/pr115258.c
https://gcc.gnu.org/g:fd9d35f68eabb7cdb250fde1d1ce2010384182a4
commit r14-11705-gfd9d35f68eabb7cdb250fde1d1ce2010384182a4
Author: Richard Sandiford
Date: Wed Apr 30 16:40:44 2025 +0100
testsuite: Force -mcmodel=small for gcc.target/aarch64/pr115258.c
The test implicitly assumed the default code model and so failed
for -mcmodel=tiny.
gcc/testsuite/
* gcc.target/aarch64/pr115258.c: Add -mcmodel=small.
(cherry picked from commit 3584aab37f54bcd220c7061568af777e37f4f6ed)
Diff:
---
gcc/testsuite/gcc.target/aarch64/pr115258.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/testsuite/gcc.target/aarch64/pr115258.c
b/gcc/testsuite/gcc.target/aarch64/pr115258.c
index 9a489d4604c0..f60b50a0a3c0 100644
--- a/gcc/testsuite/gcc.target/aarch64/pr115258.c
+++ b/gcc/testsuite/gcc.target/aarch64/pr115258.c
@@ -1,4 +1,4 @@
-/* { dg-options "-O2" } */
+/* { dg-options "-O2 -mcmodel=small" } */
/* { dg-final { check-function-bodies "**" "" "" } } */
/*
[gcc r14-11703] AVR: target/119989 - Add missing clobbers to xload__libgcc.
https://gcc.gnu.org/g:1ca1c1fc3b58ae5e1d3db4f5a2014132fe69f82a
commit r14-11703-g1ca1c1fc3b58ae5e1d3db4f5a2014132fe69f82a
Author: Georg-Johann Lay
Date: Wed Apr 30 08:43:51 2025 +0200
AVR: target/119989 - Add missing clobbers to xload__libgcc.
libgcc's __xload_1...4 is clobbering Z (and also R21 is some cases),
but avr.md had clobbers of respective GPRs only up to reload.
Outcome was that code reading from the same __memx address twice
could be wrong. This patch adds respective clobbers.
gcc/
* config/avr/avr.md (xload__libgcc): Clobber R21, Z.
gcc/testsuite/
* gcc.target/avr/torture/pr119989.h: New file.
* gcc.target/avr/torture/pr119989-memx-1.c: New test.
* gcc.target/avr/torture/pr119989-memx-2.c: New test.
* gcc.target/avr/torture/pr119989-memx-3.c: New test.
* gcc.target/avr/torture/pr119989-memx-4.c: New test.
Diff:
---
gcc/config/avr/avr.md | 4 +++
.../gcc.target/avr/torture/pr119989-memx-1.c | 6
.../gcc.target/avr/torture/pr119989-memx-2.c | 6
.../gcc.target/avr/torture/pr119989-memx-3.c | 6
.../gcc.target/avr/torture/pr119989-memx-4.c | 6
gcc/testsuite/gcc.target/avr/torture/pr119989.h| 37 ++
6 files changed, 65 insertions(+)
diff --git a/gcc/config/avr/avr.md b/gcc/config/avr/avr.md
index 823fc716f2c7..e07626dc1096 100644
--- a/gcc/config/avr/avr.md
+++ b/gcc/config/avr/avr.md
@@ -674,12 +674,16 @@
[(parallel [(set (reg:MOVMODE 22)
(mem:MOVMODE (lo_sum:PSI (reg:QI 21)
(reg:HI REG_Z
+ (clobber (reg:QI 21))
+ (clobber (reg:HI REG_Z))
(clobber (reg:CC REG_CC))])])
(define_insn "*xload__libgcc"
[(set (reg:MOVMODE 22)
(mem:MOVMODE (lo_sum:PSI (reg:QI 21)
(reg:HI REG_Z
+ (clobber (reg:QI 21))
+ (clobber (reg:HI REG_Z))
(clobber (reg:CC REG_CC))]
"avr_xload_libgcc_p (mode)
&& reload_completed"
diff --git a/gcc/testsuite/gcc.target/avr/torture/pr119989-memx-1.c
b/gcc/testsuite/gcc.target/avr/torture/pr119989-memx-1.c
new file mode 100644
index ..27b89e437bd0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/avr/torture/pr119989-memx-1.c
@@ -0,0 +1,6 @@
+/* { dg-do run { target { ! avr_tiny } } } */
+/* { dg-additional-options "-std=gnu99" } */
+
+typedef __UINT8_TYPE__ TYP;
+
+#include "pr119989.h"
diff --git a/gcc/testsuite/gcc.target/avr/torture/pr119989-memx-2.c
b/gcc/testsuite/gcc.target/avr/torture/pr119989-memx-2.c
new file mode 100644
index ..a8011a25b839
--- /dev/null
+++ b/gcc/testsuite/gcc.target/avr/torture/pr119989-memx-2.c
@@ -0,0 +1,6 @@
+/* { dg-do run { target { ! avr_tiny } } } */
+/* { dg-additional-options "-std=gnu99" } */
+
+typedef __UINT16_TYPE__ TYP;
+
+#include "pr119989.h"
diff --git a/gcc/testsuite/gcc.target/avr/torture/pr119989-memx-3.c
b/gcc/testsuite/gcc.target/avr/torture/pr119989-memx-3.c
new file mode 100644
index ..ea1c4b62c040
--- /dev/null
+++ b/gcc/testsuite/gcc.target/avr/torture/pr119989-memx-3.c
@@ -0,0 +1,6 @@
+/* { dg-do run { target { ! avr_tiny } } } */
+/* { dg-additional-options "-std=gnu99" } */
+
+__extension__ typedef __uint24 TYP;
+
+#include "pr119989.h"
diff --git a/gcc/testsuite/gcc.target/avr/torture/pr119989-memx-4.c
b/gcc/testsuite/gcc.target/avr/torture/pr119989-memx-4.c
new file mode 100644
index ..32b5cd3b55f3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/avr/torture/pr119989-memx-4.c
@@ -0,0 +1,6 @@
+/* { dg-do run { target { ! avr_tiny } } } */
+/* { dg-additional-options "-std=gnu99" } */
+
+typedef __UINT32_TYPE__ TYP;
+
+#include "pr119989.h"
diff --git a/gcc/testsuite/gcc.target/avr/torture/pr119989.h
b/gcc/testsuite/gcc.target/avr/torture/pr119989.h
new file mode 100644
index ..ab9d14a208b8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/avr/torture/pr119989.h
@@ -0,0 +1,37 @@
+const __memx TYP some_data[] = { 1, 2, 3, 4, 5 };
+const __memx TYP *IP;
+
+TYP DT, a, b;
+
+__attribute__((noipa))
+void do_test1 (void)
+{
+DT = *IP;
+DT = *IP--;
+}
+
+__attribute__((noipa))
+void do_test2 (void)
+{
+DT = *IP;
+__asm volatile ("" ::: "memory"); // Prevents unwanted optimization
+DT = *IP--;
+}
+
+TYP difference(void)
+{
+IP = &some_data[3];
+do_test1();
+a = DT;
+IP = &some_data[3];
+do_test2();
+b = DT;
+return a - b; // Expected: 0
+}
+
+int main (void)
+{
+if (difference () != 0)
+__builtin_exit (__LINE__);
+return 0;
+}
[gcc r16-295] Fix compilation failure on FreeBSD
https://gcc.gnu.org/g:4a02f3a1f96e9b339a203fc4647a76413a51440e commit r16-295-g4a02f3a1f96e9b339a203fc4647a76413a51440e Author: Eric Botcazou Date: Wed Apr 30 08:57:46 2025 +0200 Fix compilation failure on FreeBSD [changelog] PR ada/112958 * init.c (__gnat_error_handler) [__FreeBSD__]: Fix typo. Diff: --- gcc/ada/init.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gcc/ada/init.c b/gcc/ada/init.c index c0fb749dc834..1be90ec58121 100644 --- a/gcc/ada/init.c +++ b/gcc/ada/init.c @@ -1686,8 +1686,8 @@ __gnat_is_vms_v7 (void) #include #include -#ifdef __CHERI__ static void +#ifdef __CHERI__ __gnat_error_handler (int sig, siginfo_t *si, void *ucontext ATTRIBUTE_UNUSED)
[gcc r15-9601] Fix compilation failure on FreeBSD
https://gcc.gnu.org/g:17695fe9ca15046f32833c345ab2406b7c080416 commit r15-9601-g17695fe9ca15046f32833c345ab2406b7c080416 Author: Eric Botcazou Date: Wed Apr 30 08:57:46 2025 +0200 Fix compilation failure on FreeBSD [changelog] PR ada/112958 * init.c (__gnat_error_handler) [__FreeBSD__]: Fix typo. Diff: --- gcc/ada/init.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gcc/ada/init.c b/gcc/ada/init.c index c0fb749dc834..1be90ec58121 100644 --- a/gcc/ada/init.c +++ b/gcc/ada/init.c @@ -1686,8 +1686,8 @@ __gnat_is_vms_v7 (void) #include #include -#ifdef __CHERI__ static void +#ifdef __CHERI__ __gnat_error_handler (int sig, siginfo_t *si, void *ucontext ATTRIBUTE_UNUSED)
[gcc r12-11077] AVR: target/119989 - Add missing clobbers to xload__libgcc.
https://gcc.gnu.org/g:21aa0abcf1aba3a5f410b01628e8fc7f55ee8786
commit r12-11077-g21aa0abcf1aba3a5f410b01628e8fc7f55ee8786
Author: Georg-Johann Lay
Date: Wed Apr 30 08:43:51 2025 +0200
AVR: target/119989 - Add missing clobbers to xload__libgcc.
libgcc's __xload_1...4 is clobbering Z (and also R21 is some cases),
but avr.md had clobbers of respective GPRs only up to reload.
Outcome was that code reading from the same __memx address twice
could be wrong. This patch adds respective clobbers.
Backport from 2025-04-30 r14-11703
PR target/119989
gcc/
* config/avr/avr.md (xload__libgcc): Clobber R21, Z.
gcc/testsuite/
* gcc.target/avr/torture/pr119989.h: New file.
* gcc.target/avr/torture/pr119989-memx-1.c: New test.
* gcc.target/avr/torture/pr119989-memx-2.c: New test.
* gcc.target/avr/torture/pr119989-memx-3.c: New test.
* gcc.target/avr/torture/pr119989-memx-4.c: New test.
(cherry picked from commit 1ca1c1fc3b58ae5e1d3db4f5a2014132fe69f82a)
Diff:
---
gcc/config/avr/avr.md | 4 +++
.../gcc.target/avr/torture/pr119989-memx-1.c | 6
.../gcc.target/avr/torture/pr119989-memx-2.c | 6
.../gcc.target/avr/torture/pr119989-memx-3.c | 6
.../gcc.target/avr/torture/pr119989-memx-4.c | 6
gcc/testsuite/gcc.target/avr/torture/pr119989.h| 37 ++
6 files changed, 65 insertions(+)
diff --git a/gcc/config/avr/avr.md b/gcc/config/avr/avr.md
index 90ba2d0400e4..45531887084c 100644
--- a/gcc/config/avr/avr.md
+++ b/gcc/config/avr/avr.md
@@ -654,12 +654,16 @@
[(parallel [(set (reg:MOVMODE 22)
(mem:MOVMODE (lo_sum:PSI (reg:QI 21)
(reg:HI REG_Z
+ (clobber (reg:QI 21))
+ (clobber (reg:HI REG_Z))
(clobber (reg:CC REG_CC))])])
(define_insn "*xload__libgcc"
[(set (reg:MOVMODE 22)
(mem:MOVMODE (lo_sum:PSI (reg:QI 21)
(reg:HI REG_Z
+ (clobber (reg:QI 21))
+ (clobber (reg:HI REG_Z))
(clobber (reg:CC REG_CC))]
"avr_xload_libgcc_p (mode)
&& reload_completed"
diff --git a/gcc/testsuite/gcc.target/avr/torture/pr119989-memx-1.c
b/gcc/testsuite/gcc.target/avr/torture/pr119989-memx-1.c
new file mode 100644
index ..27b89e437bd0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/avr/torture/pr119989-memx-1.c
@@ -0,0 +1,6 @@
+/* { dg-do run { target { ! avr_tiny } } } */
+/* { dg-additional-options "-std=gnu99" } */
+
+typedef __UINT8_TYPE__ TYP;
+
+#include "pr119989.h"
diff --git a/gcc/testsuite/gcc.target/avr/torture/pr119989-memx-2.c
b/gcc/testsuite/gcc.target/avr/torture/pr119989-memx-2.c
new file mode 100644
index ..a8011a25b839
--- /dev/null
+++ b/gcc/testsuite/gcc.target/avr/torture/pr119989-memx-2.c
@@ -0,0 +1,6 @@
+/* { dg-do run { target { ! avr_tiny } } } */
+/* { dg-additional-options "-std=gnu99" } */
+
+typedef __UINT16_TYPE__ TYP;
+
+#include "pr119989.h"
diff --git a/gcc/testsuite/gcc.target/avr/torture/pr119989-memx-3.c
b/gcc/testsuite/gcc.target/avr/torture/pr119989-memx-3.c
new file mode 100644
index ..ea1c4b62c040
--- /dev/null
+++ b/gcc/testsuite/gcc.target/avr/torture/pr119989-memx-3.c
@@ -0,0 +1,6 @@
+/* { dg-do run { target { ! avr_tiny } } } */
+/* { dg-additional-options "-std=gnu99" } */
+
+__extension__ typedef __uint24 TYP;
+
+#include "pr119989.h"
diff --git a/gcc/testsuite/gcc.target/avr/torture/pr119989-memx-4.c
b/gcc/testsuite/gcc.target/avr/torture/pr119989-memx-4.c
new file mode 100644
index ..32b5cd3b55f3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/avr/torture/pr119989-memx-4.c
@@ -0,0 +1,6 @@
+/* { dg-do run { target { ! avr_tiny } } } */
+/* { dg-additional-options "-std=gnu99" } */
+
+typedef __UINT32_TYPE__ TYP;
+
+#include "pr119989.h"
diff --git a/gcc/testsuite/gcc.target/avr/torture/pr119989.h
b/gcc/testsuite/gcc.target/avr/torture/pr119989.h
new file mode 100644
index ..ab9d14a208b8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/avr/torture/pr119989.h
@@ -0,0 +1,37 @@
+const __memx TYP some_data[] = { 1, 2, 3, 4, 5 };
+const __memx TYP *IP;
+
+TYP DT, a, b;
+
+__attribute__((noipa))
+void do_test1 (void)
+{
+DT = *IP;
+DT = *IP--;
+}
+
+__attribute__((noipa))
+void do_test2 (void)
+{
+DT = *IP;
+__asm volatile ("" ::: "memory"); // Prevents unwanted optimization
+DT = *IP--;
+}
+
+TYP difference(void)
+{
+IP = &some_data[3];
+do_test1();
+a = DT;
+IP = &some_data[3];
+do_test2();
+b = DT;
+return a - b; // Expected: 0
+}
+
+int main (void)
+{
+if (difference () != 0)
+__builtin_exit (__LINE__);
+return 0;
+}
[gcc(refs/users/mikael/heads/refactor_descriptor_v05)] Correction régression array_temporaries_3
https://gcc.gnu.org/g:84b20be03139ef53b30dfc663263a6516fc76c08
commit 84b20be03139ef53b30dfc663263a6516fc76c08
Author: Mikael Morin
Date: Wed Apr 30 13:46:50 2025 +0200
Correction régression array_temporaries_3
Diff:
---
gcc/fortran/trans-array.cc | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/gcc/fortran/trans-array.cc b/gcc/fortran/trans-array.cc
index d9cf89cb4ebc..6d306a522953 100644
--- a/gcc/fortran/trans-array.cc
+++ b/gcc/fortran/trans-array.cc
@@ -2826,7 +2826,8 @@ gfc_add_loop_ss_code (gfc_loopinfo * loop, gfc_ss * ss,
bool subscript,
&& ss_info->expr->ts.type != BT_CLASS)
{
tree type = gfc_typenode_for_spec (&ss_info->expr->ts);
- if (TYPE_SIZE_UNIT (type) == NULL_TREE)
+ if (TYPE_SIZE_UNIT (type) == NULL_TREE
+ || !INTEGER_CST_P (TYPE_SIZE_UNIT (type)))
{
for (n = 0; n < ss_info->expr->rank; n++)
{
[gcc(refs/users/mikael/heads/refactor_descriptor_v05)] Correction régression array_assignment_5
https://gcc.gnu.org/g:31853d6e1e1d7e7a93f16648600d080b5752a371
commit 31853d6e1e1d7e7a93f16648600d080b5752a371
Author: Mikael Morin
Date: Wed Apr 30 12:29:42 2025 +0200
Correction régression array_assignment_5
Diff:
---
gcc/fortran/trans-array.cc | 38 +-
1 file changed, 25 insertions(+), 13 deletions(-)
diff --git a/gcc/fortran/trans-array.cc b/gcc/fortran/trans-array.cc
index f3915526daf3..d9cf89cb4ebc 100644
--- a/gcc/fortran/trans-array.cc
+++ b/gcc/fortran/trans-array.cc
@@ -2826,22 +2826,34 @@ gfc_add_loop_ss_code (gfc_loopinfo * loop, gfc_ss * ss,
bool subscript,
&& ss_info->expr->ts.type != BT_CLASS)
{
tree type = gfc_typenode_for_spec (&ss_info->expr->ts);
- tree spacing = fold_convert_loc (input_location,
-gfc_array_index_type,
-TYPE_SIZE_UNIT (type));
- spacing = gfc_evaluate_now (spacing, &outer_loop->pre);
-
- for (n = 0; n < ss_info->expr->rank; n++)
+ if (TYPE_SIZE_UNIT (type) == NULL_TREE)
+ {
+ for (n = 0; n < ss_info->expr->rank; n++)
+ {
+ tree spacing = gfc_conv_descriptor_spacing_get
(info->descriptor,
+
gfc_rank_cst[n]);
+ info->spacing[n] = gfc_evaluate_now (spacing,
&outer_loop->pre);
+ }
+ }
+ else
{
- info->spacing[n] = spacing;
+ tree spacing = fold_convert_loc (input_location,
+gfc_array_index_type,
+TYPE_SIZE_UNIT (type));
+ spacing = gfc_evaluate_now (spacing, &outer_loop->pre);
- tree extent = gfc_conv_descriptor_extent_get
(info->descriptor,
-
gfc_rank_cst[n]);
+ for (n = 0; n < ss_info->expr->rank; n++)
+ {
+ info->spacing[n] = spacing;
- spacing = fold_build2_loc (input_location, MULT_EXPR,
- gfc_array_index_type,
spacing,
- extent);
- spacing = gfc_evaluate_now (spacing, &outer_loop->pre);
+ tree extent = gfc_conv_descriptor_extent_get
(info->descriptor,
+
gfc_rank_cst[n]);
+
+ spacing = fold_build2_loc (input_location,
MULT_EXPR,
+ gfc_array_index_type,
spacing,
+ extent);
+ spacing = gfc_evaluate_now (spacing,
&outer_loop->pre);
+ }
}
}
}
[gcc(refs/users/mikael/heads/refactor_descriptor_v05)] Correction régression class_array_23
https://gcc.gnu.org/g:406b5150d65ac8e028f1dec0f92816bfc4f5323e
commit 406b5150d65ac8e028f1dec0f92816bfc4f5323e
Author: Mikael Morin
Date: Wed Apr 30 14:38:54 2025 +0200
Correction régression class_array_23
Diff:
---
gcc/fortran/trans-array.cc | 2 +-
gcc/fortran/trans-array.h | 2 +-
gcc/fortran/trans-descriptor.cc | 8 +++-
gcc/fortran/trans-descriptor.h | 4 ++--
gcc/fortran/trans-stmt.cc | 3 ++-
5 files changed, 13 insertions(+), 6 deletions(-)
diff --git a/gcc/fortran/trans-array.cc b/gcc/fortran/trans-array.cc
index 6d306a522953..79ca3f4f74c8 100644
--- a/gcc/fortran/trans-array.cc
+++ b/gcc/fortran/trans-array.cc
@@ -5652,7 +5652,7 @@ bool
gfc_array_allocate (gfc_se * se, gfc_expr * expr, tree status, tree errmsg,
tree errlen, tree label_finish, tree expr3_elem_size,
gfc_expr *expr3, tree e3_arr_desc, bool e3_has_nodescriptor,
- gfc_omp_namelist *omp_alloc, bool explicit_ts)
+ gfc_omp_namelist *omp_alloc, gfc_typespec * explicit_ts)
{
tree tmp;
tree pointer;
diff --git a/gcc/fortran/trans-array.h b/gcc/fortran/trans-array.h
index 5b2c6ecffdb4..c5f92b3f3cca 100644
--- a/gcc/fortran/trans-array.h
+++ b/gcc/fortran/trans-array.h
@@ -22,7 +22,7 @@ along with GCC; see the file COPYING3. If not see
se, which should contain an expression for the array descriptor. */
bool gfc_array_allocate (gfc_se *, gfc_expr *, tree, tree, tree, tree,
tree, gfc_expr *, tree, bool,
-gfc_omp_namelist *, bool);
+gfc_omp_namelist *, gfc_typespec *);
/* Allow the bounds of a loop to be set from a callee's array spec. */
void gfc_set_loop_bounds_from_array_spec (gfc_interface_mapping *,
diff --git a/gcc/fortran/trans-descriptor.cc b/gcc/fortran/trans-descriptor.cc
index 22a6fb6942e2..03a6d71bbabf 100644
--- a/gcc/fortran/trans-descriptor.cc
+++ b/gcc/fortran/trans-descriptor.cc
@@ -3186,7 +3186,7 @@ gfc_descr_init_count (tree descriptor, int rank, int
corank, gfc_expr ** lower,
stmtblock_t * descriptor_block, tree * overflow,
tree expr3_elem_size, gfc_expr *expr3, tree expr3_desc,
bool e3_has_nodescriptor, gfc_expr *expr,
- tree element_size, bool explicit_ts,
+ tree element_size, gfc_typespec * explicit_ts,
tree *empty_array_cond)
{
tree type;
@@ -3237,6 +3237,12 @@ gfc_descr_init_count (tree descriptor, int rank, int
corank, gfc_expr ** lower,
tree dtype_value = gfc_get_dtype_rank_type (rank, type);
gfc_conv_descriptor_dtype_set (pblock, descriptor, dtype_value);
}
+ else if (explicit_ts)
+{
+ type = gfc_typenode_for_spec (explicit_ts);
+ tree dtype_value = gfc_get_dtype_rank_type (rank, type);
+ gfc_conv_descriptor_dtype_set (pblock, descriptor, dtype_value);
+}
else if (expr3_desc && GFC_DESCRIPTOR_TYPE_P (TREE_TYPE (expr3_desc)))
{
tree dtype_value = gfc_conv_descriptor_dtype_get (expr3_desc);
diff --git a/gcc/fortran/trans-descriptor.h b/gcc/fortran/trans-descriptor.h
index 092a2b8abddc..3244359c176e 100644
--- a/gcc/fortran/trans-descriptor.h
+++ b/gcc/fortran/trans-descriptor.h
@@ -95,8 +95,8 @@ void gfc_set_descriptor (stmtblock_t *, tree, tree, gfc_expr
*, int, int,
tree gfc_descr_init_count (tree, int, int, gfc_expr **, gfc_expr **,
stmtblock_t *, stmtblock_t *, tree *, tree,
- gfc_expr *, tree, bool, gfc_expr *, tree, bool,
- tree *);
+ gfc_expr *, tree, bool, gfc_expr *, tree,
+ gfc_typespec *, tree *);
void
gfc_copy_descriptor_info (stmtblock_t *, tree, tree, int, gfc_ss *);
void
diff --git a/gcc/fortran/trans-stmt.cc b/gcc/fortran/trans-stmt.cc
index fdcc92555c9c..50167ce083b0 100644
--- a/gcc/fortran/trans-stmt.cc
+++ b/gcc/fortran/trans-stmt.cc
@@ -6929,7 +6929,8 @@ gfc_trans_allocate (gfc_code * code, gfc_omp_namelist
*omp_allocate)
label_finish, tmp, e3rhs ? e3rhs : code->expr3,
e3_is == E3_DESC ? expr3 : NULL_TREE,
e3_has_nodescriptor, omp_alloc_item,
- code->ext.alloc.ts.type != BT_UNKNOWN))
+ code->ext.alloc.ts.type != BT_UNKNOWN
+ ? &code->ext.alloc.ts : nullptr))
{
/* A scalar or derived type. First compute the size to
allocate.
[gcc r14-11706] c++: UNBOUND_CLASS_TEMPLATE context substitution [PR119981]
https://gcc.gnu.org/g:30432ffd9220cc949ef470c47455c6a64f2cdb69
commit r14-11706-g30432ffd9220cc949ef470c47455c6a64f2cdb69
Author: Patrick Palka
Date: Wed Apr 30 10:54:23 2025 -0400
c++: UNBOUND_CLASS_TEMPLATE context substitution [PR119981]
In r15-123 and r14-11434 we unconditionally set processing_template_decl
when substituting the context of an UNBOUND_CLASS_TEMPLATE, in order to
handle instantiation of the dependently scoped friend declaration
template
template
friend class A::B;
where the scope A remains dependent after instantiation. But this
turns out to misbehave for the UNBOUND_CLASS_TEMPLATE in the below
testcase representing
g<[]{}>::template fn
since with the flag set substituting the args of test3 into the lambda
causes us to defer the substitution and yield a lambda that still looks
dependent, which in turn makes g<[]{}> still dependent and not suitable
for qualified name lookup.
This patch restricts setting processing_template_decl during
UNBOUND_CLASS_TEMPLATE substitution to the case where there are multiple
levels of introduced template parameters, as in the friend declaration.
(This means we need to substitute the template parameter list(s) first,
which makes sense since they lexically appear first.)
PR c++/119981
PR c++/119378
gcc/cp/ChangeLog:
* pt.cc (tsubst) : Substitute
into template parameter list first. When substituting the
context, only set processing_template_decl if there's more
than one level of introduced template parameters.
gcc/testsuite/ChangeLog:
* g++.dg/cpp2a/lambda-targ15.C: New test.
Reviewed-by: Jason Merrill
(cherry picked from commit 05ea8baf6ff96c77a9a2467d5c45b1ed575fca92)
Diff:
---
gcc/cp/pt.cc | 20 +---
gcc/testsuite/g++.dg/cpp2a/lambda-targ15.C | 17 +
2 files changed, 30 insertions(+), 7 deletions(-)
diff --git a/gcc/cp/pt.cc b/gcc/cp/pt.cc
index b2b2fdca956a..7c896702353b 100644
--- a/gcc/cp/pt.cc
+++ b/gcc/cp/pt.cc
@@ -16954,18 +16954,24 @@ tsubst (tree t, tree args, tsubst_flags_t complain,
tree in_decl)
case UNBOUND_CLASS_TEMPLATE:
{
- ++processing_template_decl;
- tree ctx = tsubst_aggr_type (TYPE_CONTEXT (t), args, complain,
-in_decl, /*entering_scope=*/1);
- --processing_template_decl;
tree name = TYPE_IDENTIFIER (t);
+ if (name == error_mark_node)
+ return error_mark_node;
+
tree parm_list = DECL_TEMPLATE_PARMS (TYPE_NAME (t));
+ parm_list = tsubst_template_parms (parm_list, args, complain);
+ if (parm_list == error_mark_node)
+ return error_mark_node;
- if (ctx == error_mark_node || name == error_mark_node)
+ if (parm_list && TMPL_PARMS_DEPTH (parm_list) > 1)
+ ++processing_template_decl;
+ tree ctx = tsubst_aggr_type (TYPE_CONTEXT (t), args, complain,
+in_decl, /*entering_scope=*/1);
+ if (parm_list && TMPL_PARMS_DEPTH (parm_list) > 1)
+ --processing_template_decl;
+ if (ctx == error_mark_node)
return error_mark_node;
- if (parm_list)
- parm_list = tsubst_template_parms (parm_list, args, complain);
return make_unbound_class_template (ctx, name, parm_list, complain);
}
diff --git a/gcc/testsuite/g++.dg/cpp2a/lambda-targ15.C
b/gcc/testsuite/g++.dg/cpp2a/lambda-targ15.C
new file mode 100644
index ..90160a52a6ef
--- /dev/null
+++ b/gcc/testsuite/g++.dg/cpp2a/lambda-targ15.C
@@ -0,0 +1,17 @@
+// PR c++/119981
+// { dg-do compile { target c++20 } }
+
+template class P>
+struct mp_copy_if{};
+
+template
+struct g {
+ template struct fn{};
+};
+
+template
+void test3() {
+ mp_copy_if::template fn> b;
+}
+
+template void test3();
[gcc(refs/users/meissner/heads/work204-test)] Add ChangeLog.test and update REVISION.
https://gcc.gnu.org/g:6c72bd895d381ba96ca67bc8c2dfdd1f69343c20 commit 6c72bd895d381ba96ca67bc8c2dfdd1f69343c20 Author: Michael Meissner Date: Wed Apr 30 13:59:54 2025 -0400 Add ChangeLog.test and update REVISION. 2025-04-30 Michael Meissner gcc/ * ChangeLog.test: New file for branch. * REVISION: Update. Diff: --- gcc/ChangeLog.test | 5 + gcc/REVISION | 2 +- 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog.test b/gcc/ChangeLog.test new file mode 100644 index ..db6f66cd95d6 --- /dev/null +++ b/gcc/ChangeLog.test @@ -0,0 +1,5 @@ + Branch work204-test, baseline + +2025-04-30 Michael Meissner + + Clone branch diff --git a/gcc/REVISION b/gcc/REVISION index d4f18d737afd..73de791133d8 100644 --- a/gcc/REVISION +++ b/gcc/REVISION @@ -1 +1 @@ -work204 branch +work204-test branch
[gcc(refs/users/meissner/heads/work204)] Add support for -mcpu=future
https://gcc.gnu.org/g:268f13e7c15be4673edb307304182f91d1accf8d
commit 268f13e7c15be4673edb307304182f91d1accf8d
Author: Michael Meissner
Date: Wed Apr 30 15:27:24 2025 -0400
Add support for -mcpu=future
This patch adds the support that can be used in developing GCC support for
future PowerPC processors.
2025-04-30 Michael Meissner
* config.gcc (powerpc*-*-*): Add support for --with-cpu=future.
* config/rs6000/aix71.h (ASM_CPU_SPEC): Add support for
-mcpu=future.
* config/rs6000/aix72.h (ASM_CPU_SPEC): Likewise.
* config/rs6000/aix73.h (ASM_CPU_SPEC): Likewise.
* config/rs6000/driver-rs6000.cc (asm_names): Likewise.
* config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): If
-mcpu=future, define _ARCH_FUTURE.
* config/rs6000/rs6000-cpus.def (FUTURE_MASKS_SERVER): New macro.
(POWERPC_MASKS): Add OPTION_MASK_FUTURE.
(future cpu): Define.
* config/rs6000/rs6000-opts.h (enum processor_type): Add
PROCESSOR_FUTURE.
* config/rs6000/rs6000-tables.opt: Regenerate.
* config/rs6000/rs6000.cc (power10_cost): Update comment.
(get_arch_flags): Add support for future processor.
(rs6000_option_override_internal): Likewise.
(rs6000_machine_from_flags): Likewise.
(rs6000_reassociation_width): Likewise.
(rs6000_adjust_cost): Likewise.
(rs6000_issue_rate): Likewise.
(rs6000_sched_reorder): Likewise.
(rs6000_sched_reorder2): Likewise.
(rs6000_register_move_cost): Likewise.
(rs6000_opt_masks): Add -mfuture.
* config/rs6000/rs6000.h (ASM_CPU_SPEC): Likewise.
* config/rs6000/rs6000.md (cpu attribute): Likewise.
* config/rs6000/rs6000.opt (-mfuture): New internal option.
Diff:
---
gcc/config.gcc | 4 ++--
gcc/config/rs6000/aix71.h | 1 +
gcc/config/rs6000/aix72.h | 1 +
gcc/config/rs6000/aix73.h | 1 +
gcc/config/rs6000/driver-rs6000.cc | 2 ++
gcc/config/rs6000/rs6000-c.cc | 2 ++
gcc/config/rs6000/rs6000-cpus.def | 5 +
gcc/config/rs6000/rs6000-opts.h | 1 +
gcc/config/rs6000/rs6000-tables.opt | 11 +++
gcc/config/rs6000/rs6000.cc | 30 ++
gcc/config/rs6000/rs6000.h | 1 +
gcc/config/rs6000/rs6000.md | 2 +-
gcc/config/rs6000/rs6000.opt| 6 ++
13 files changed, 52 insertions(+), 15 deletions(-)
diff --git a/gcc/config.gcc b/gcc/config.gcc
index 6dbe880c9d45..43ea9157a5c6 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -536,7 +536,7 @@ powerpc*-*-*)
extra_headers="${extra_headers} ppu_intrinsics.h spu2vmx.h vec_types.h
si2vmx.h"
extra_headers="${extra_headers} amo.h"
case x$with_cpu in
-
xpowerpc64|xdefault64|x6[23]0|x970|xG5|xpower[3456789]|xpower1[01]|xpower6x|xrs64a|xcell|xa2|xe500mc64|xe5500|xe6500)
+
xpowerpc64|xdefault64|x6[23]0|x970|xG5|xpower[3456789]|xpower1[01]|xpower6x|xrs64a|xcell|xa2|xe500mc64|xe5500|xe6500|xfuture)
cpu_is_64bit=yes
;;
esac
@@ -5697,7 +5697,7 @@ case "${target}" in
tm_defines="${tm_defines} CONFIG_PPC405CR"
eval "with_$which=405"
;;
- "" | common | native \
+ "" | common | native | future \
| power[3456789] | power1[01] | power5+ | power6x \
| powerpc | powerpc64 | powerpc64le \
| rs64 \
diff --git a/gcc/config/rs6000/aix71.h b/gcc/config/rs6000/aix71.h
index 2b21dd7cd1e0..77651f5ea309 100644
--- a/gcc/config/rs6000/aix71.h
+++ b/gcc/config/rs6000/aix71.h
@@ -79,6 +79,7 @@ do {
\
#undef ASM_CPU_SPEC
#define ASM_CPU_SPEC \
"%{mcpu=native: %(asm_cpu_native); \
+ mcpu=future: -mfuture; \
mcpu=power11: -mpwr11; \
mcpu=power10: -mpwr10; \
mcpu=power9: -mpwr9; \
diff --git a/gcc/config/rs6000/aix72.h b/gcc/config/rs6000/aix72.h
index 53c0bde5ad4a..652f60c7f494 100644
--- a/gcc/config/rs6000/aix72.h
+++ b/gcc/config/rs6000/aix72.h
@@ -79,6 +79,7 @@ do {
\
#undef ASM_CPU_SPEC
#define ASM_CPU_SPEC \
"%{mcpu=native: %(asm_cpu_native); \
+ mcpu=future: -mfuture; \
mcpu=power11: -mpwr11; \
mcpu=power10: -mpwr10; \
mcpu=power9: -mpwr9; \
diff --git a/gcc/config/rs6000/aix73.h b/gcc/config/rs6000/aix73.h
index c7639368a264..3c66ac1d9171 100644
--- a/gcc/config/rs6000/aix73.h
+++ b/gcc/config/rs6000/aix73.h
@@ -79,6 +79,7 @@ do {
\
#undef ASM_CPU_SPEC
#define ASM_CPU_SPEC \
"%{mcpu=nati
[gcc(refs/users/mikael/heads/refactor_descriptor_v05)] Correction régression assumed_size.f90
https://gcc.gnu.org/g:211046cc53965f9e52ebc7cd579b1f475f973ef6 commit 211046cc53965f9e52ebc7cd579b1f475f973ef6 Author: Mikael Morin Date: Wed Apr 30 16:31:17 2025 +0200 Correction régression assumed_size.f90 Diff: --- gcc/fortran/trans-expr.cc | 20 +++- 1 file changed, 15 insertions(+), 5 deletions(-) diff --git a/gcc/fortran/trans-expr.cc b/gcc/fortran/trans-expr.cc index 612dea0c46a5..c070d417994a 100644 --- a/gcc/fortran/trans-expr.cc +++ b/gcc/fortran/trans-expr.cc @@ -5462,6 +5462,13 @@ gfc_conv_subref_array_arg (gfc_se *se, gfc_expr * expr, int g77, freeing of allocated memory is done at the right time. */ gfc_add_block_to_block (&parmse->pre, &loop.pre); + /* Remove the temporary from the first loop before cleanup, as we need it in + the second loop. */ + gfc_ss *tmp_ss = loop.temp_ss; + gcc_assert (loop.ss == tmp_ss); + loop.ss = loop.ss->loop_chain; + gfc_cleanup_loop (&loop); + /**Copy the temporary back again.*/ gfc_init_se (&lse, NULL); @@ -5469,7 +5476,7 @@ gfc_conv_subref_array_arg (gfc_se *se, gfc_expr * expr, int g77, /* Walk the argument expression. */ lss = gfc_walk_expr (expr); - rse.ss = loop.temp_ss; + rse.ss = tmp_ss; lse.ss = lss; /* Initialize the scalarizer. */ @@ -5488,11 +5495,15 @@ gfc_conv_subref_array_arg (gfc_se *se, gfc_expr * expr, int g77, /* Setup the scalarizing loops. */ gfc_conv_loop_setup (&loop2, &expr->where); + /* Add the temporary late, as it doesn't need to be set up again. */ + tmp_ss->info->data.array.data = tmp_ss->info->data.array.saved_data; + gfc_add_ss_to_loop (&loop2, tmp_ss); + gfc_copy_loopinfo_to_se (&lse, &loop2); gfc_copy_loopinfo_to_se (&rse, &loop2); gfc_mark_ss_chain_used (lss, 1); - gfc_mark_ss_chain_used (loop.temp_ss, 1); + gfc_mark_ss_chain_used (tmp_ss, 1); gfc_start_scalarized_body (&loop2, &body); @@ -5527,9 +5538,6 @@ class_array_fcn: gfc_add_block_to_block (&parmse->post, &loop.post); - gfc_cleanup_loop (&loop); - gfc_cleanup_loop (&loop2); - /* Pass the string length to the argument expression. */ if (expr->ts.type == BT_CHARACTER) parmse->string_length = expr->ts.u.cl->backend_decl; @@ -5540,6 +5548,8 @@ class_array_fcn: gfc_conv_shift_descriptor (&parmse->pre, parmse->expr, dimen, rse.loop->from, rse.loop->to); + gfc_cleanup_loop (&loop2); + /* We want either the address for the data or the address of the descriptor, depending on the mode of passing array arguments. */ if (g77)
[gcc(refs/users/mikael/heads/refactor_descriptor_v05)] Correction régression pointer_function_result_1
https://gcc.gnu.org/g:df1d679b9faa4228a7e1d17675a6074533b6a115
commit df1d679b9faa4228a7e1d17675a6074533b6a115
Author: Mikael Morin
Date: Wed Apr 30 18:52:14 2025 +0200
Correction régression pointer_function_result_1
Diff:
---
gcc/fortran/trans-array.cc | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/gcc/fortran/trans-array.cc b/gcc/fortran/trans-array.cc
index 79ca3f4f74c8..861b689704b0 100644
--- a/gcc/fortran/trans-array.cc
+++ b/gcc/fortran/trans-array.cc
@@ -2827,7 +2827,8 @@ gfc_add_loop_ss_code (gfc_loopinfo * loop, gfc_ss * ss,
bool subscript,
{
tree type = gfc_typenode_for_spec (&ss_info->expr->ts);
if (TYPE_SIZE_UNIT (type) == NULL_TREE
- || !INTEGER_CST_P (TYPE_SIZE_UNIT (type)))
+ || !INTEGER_CST_P (TYPE_SIZE_UNIT (type))
+ || gfc_expr_attr (ss_info->expr).pointer)
{
for (n = 0; n < ss_info->expr->rank; n++)
{
@@ -3607,7 +3608,8 @@ void
gfc_conv_tmp_array_ref (gfc_se * se)
{
se->string_length = se->ss->info->string_length;
- gfc_conv_scalarized_array_ref (se, NULL, true);
+ bool tmp_array = !gfc_expr_attr (se->ss->info->expr).pointer;
+ gfc_conv_scalarized_array_ref (se, NULL, tmp_array);
gfc_advance_se_ss_chain (se);
}
[gcc r15-9607] Always reflect lower bits from mask in subranges.
https://gcc.gnu.org/g:f685d317738524dc837dee94bb762f71ff30fb23
commit r15-9607-gf685d317738524dc837dee94bb762f71ff30fb23
Author: Andrew MacLeod
Date: Mon Apr 14 16:25:15 2025 -0400
Always reflect lower bits from mask in subranges.
During intersection, we expand the subranges to exclude the lower values
from a bitmask with trailing zeros. This leads to inconsistant evaluations
and in this case of this PR, that lead to an infinite cycle.
Always expand the lower subranges in set_range_from_bitmask instead.
PR tree-optimization/119712
gcc/
* value-range.cc (range_bitmask::adjust_range): Delete.
(irange::set_range_from_bitmask): Integrate adjust_range.
(irange::update_bitmask): Do nothing if bitmask doesnt change.
(irange:intersect_bitmask): Do not call adjust_range. Exit if there
is no second bitmask.
* value-range.h (adjust_range): Remove prototype.
gcc/testsuite/
* gcc.dg/pr119712.c: New.
* gcc.dg/pr83072-2.c: Adjust.
* gcc.dg/tree-ssa/phi-opt-value-5.c: Adjust.
* gcc.dg/tree-ssa/vrp122.c: Adjust
Diff:
---
gcc/testsuite/gcc.dg/pr119712.c | 27 +++
gcc/testsuite/gcc.dg/pr83072-2.c| 2 +-
gcc/testsuite/gcc.dg/tree-ssa/phi-opt-value-5.c | 4 +-
gcc/testsuite/gcc.dg/tree-ssa/vrp122.c | 4 +-
gcc/value-range.cc | 64 -
gcc/value-range.h | 1 -
6 files changed, 61 insertions(+), 41 deletions(-)
diff --git a/gcc/testsuite/gcc.dg/pr119712.c b/gcc/testsuite/gcc.dg/pr119712.c
new file mode 100644
index ..e845dd9ce55a
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/pr119712.c
@@ -0,0 +1,27 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+int a, b, c, d, e, f;
+int main() {
+ f--;
+ goto q;
+j:
+ if (-1642776935 * c + 7 >= 0)
+goto l;
+m:
+ if (4 * a - c - 21 >= 0)
+goto i;
+ return 0;
+i:
+ if (d)
+goto l;
+q:
+ c = 4 * c - 3;
+ if (c - f)
+ goto m;
+ goto j;
+l:
+ e = b + 1958960196 * c - 1016458303;
+ if (20 * e + 1 >= 0)
+ return 0;
+ goto j;
+}
diff --git a/gcc/testsuite/gcc.dg/pr83072-2.c b/gcc/testsuite/gcc.dg/pr83072-2.c
index dff6b50b717e..485e8041381e 100644
--- a/gcc/testsuite/gcc.dg/pr83072-2.c
+++ b/gcc/testsuite/gcc.dg/pr83072-2.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O2 -fdump-tree-evrp-details" } */
+/* { dg-options "-O2 -fdump-tree-evrp-details -fno-tree-forwprop" } */
int f1(int a, int b, int c){
if(c==0)__builtin_unreachable();
diff --git a/gcc/testsuite/gcc.dg/tree-ssa/phi-opt-value-5.c
b/gcc/testsuite/gcc.dg/tree-ssa/phi-opt-value-5.c
index 12ba475b24e2..ed8ee3ab72dc 100644
--- a/gcc/testsuite/gcc.dg/tree-ssa/phi-opt-value-5.c
+++ b/gcc/testsuite/gcc.dg/tree-ssa/phi-opt-value-5.c
@@ -31,9 +31,7 @@ int fdiv1(int a, int b)
return a != 0 ? c : 0;
}
-/* fdiv1 requires until later than phiopt2 to be able to detect that
- d is non-zero. to be able to remove the conditional. */
-/* { dg-final { scan-tree-dump-times "goto" 2 "phiopt2" } } */
+/* { dg-final { scan-tree-dump-not "goto" "phiopt2" } } */
/* { dg-final { scan-tree-dump-not "goto" "phiopt3" } } */
/* { dg-final { scan-tree-dump-not "goto" "optimized" } } */
diff --git a/gcc/testsuite/gcc.dg/tree-ssa/vrp122.c
b/gcc/testsuite/gcc.dg/tree-ssa/vrp122.c
index 5a4ca850beec..def2b892bd6b 100644
--- a/gcc/testsuite/gcc.dg/tree-ssa/vrp122.c
+++ b/gcc/testsuite/gcc.dg/tree-ssa/vrp122.c
@@ -1,5 +1,5 @@
// { dg-do compile }
-// { dg-options "-O2 -fdump-tree-evrp-details" }
+// { dg-options "-O2 -fdump-tree-ccp1-details" }
void gg(void);
int f(unsigned t)
@@ -16,4 +16,4 @@ int f(unsigned t)
return 0;
}
-// { dg-final { scan-tree-dump "Global Exported: g_.* MASK 0x1 VALUE 0x0"
"evrp" } }
+// { dg-final { scan-tree-dump "Global Exported: g_.*MASK.*0 VALUE 0x0" "ccp1"
} }
diff --git a/gcc/value-range.cc b/gcc/value-range.cc
index 5136674b361a..a770b41b474a 100644
--- a/gcc/value-range.cc
+++ b/gcc/value-range.cc
@@ -2251,37 +2251,9 @@ irange::invert ()
verify_range ();
}
-// Remove trailing ranges that this bitmask indicates can't exist.
-
-void
-irange_bitmask::adjust_range (irange &r) const
-{
- if (unknown_p () || r.undefined_p ())
-return;
-
- int_range_max range;
- tree type = r.type ();
- int prec = TYPE_PRECISION (type);
- // If there are trailing zeros, create a range representing those bits.
- gcc_checking_assert (m_mask != 0);
- int z = wi::ctz (m_mask);
- if (z)
-{
- wide_int ub = (wi::one (prec) << z) - 1;
- range = int_range<5> (type, wi::zero (prec), ub);
- // Then remove the specific value these bits contain from the range.
- wide_int v
[gcc/devel/omp/gcc-14] OpenMP: need_device_ptr and need_device_addr support for adjust_args
https://gcc.gnu.org/g:9a06e4d6a117497c2536bf89bb6c7536289e44bb
commit 9a06e4d6a117497c2536bf89bb6c7536289e44bb
Author: Sandra Loosemore
Date: Wed Apr 30 17:46:31 2025 +
OpenMP: need_device_ptr and need_device_addr support for adjust_args
This patch adds support for the "need_device_addr" modifier to the
"adjust args" clause for the "declare variant" directive, and
extends/re-works the support for "need_device_ptr" as well.
This patch builds on waffl3x's recently posted patch, "OpenMP: C/C++
adjust-args numeric ranges", here.
https://gcc.gnu.org/pipermail/gcc-patches/2025-April/681806.html
In C++, "need_device_addr" supports mapping reference arguments to
device pointers. In Fortran, it similarly supports arguments passed
by reference, the default for the language, in contrast to
"need_device_ptr" which is used to map arguments of c_ptr type. The
C++ support is straightforward, but Fortran has some additional
wrinkles involving arrays passed by descriptor (a new descriptor must
be constructed with a pointer to the array data which is the only part
mapped to the device), plus special cases for passing optional
arguments and a whole array instead of a reference to its first element.
gcc/cp/ChangeLog
* parser.cc (cp_finish_omp_declare_variant): Adjust error messages.
gcc/fortran/ChangeLog
* trans-openmp.cc (gfc_trans_omp_declare_variant): Disallow
polymorphic and optional arguments with need_device_addr for now,
but
don't reject need_device_addr entirely.
gcc/ChangeLog
* gimplify.cc (modify_call_for_omp_dispatch): Rework logic for
need_device_ptr and need_device_addr adjustments.
gcc/testsuite/Changelog
* c-c++-common/gomp/adjust-args-10.c: Ignore the new sorry since the
lack of proper diagnostic is already xfail'ed.
* g++.dg/gomp/adjust-args-1.C: Adjust output patterns.
* g++.dg/gomp/adjust-args-17.C: New.
* gcc.dg/gomp/adjust-args-3.c: New.
* gfortran.dg/gomp/adjust-args-14.f90: Don't expect this to fail
now.
libgomp/ChangeLog
* libgomp.texi: Mark need_device_addr as supported.
* testsuite/libgomp.c-c++-common/dispatch-3.c: New.
* testsuite/libgomp.c++/need-device-ptr.C: New.
* testsuite/libgomp.fortran/adjust-args-array-descriptor.f90: New.
* testsuite/libgomp.fortran/need-device-ptr.f90: New.
Co-Authored-By: Tobias Burnus
Diff:
---
gcc/cp/parser.cc | 7 +-
gcc/fortran/trans-openmp.cc| 44 --
gcc/gimplify.cc| 88 +--
gcc/testsuite/c-c++-common/gomp/adjust-args-10.c | 2 +
gcc/testsuite/g++.dg/gomp/adjust-args-1.C | 6 +-
gcc/testsuite/g++.dg/gomp/adjust-args-17.C | 44 ++
gcc/testsuite/gcc.dg/gomp/adjust-args-3.c | 47 ++
gcc/testsuite/gfortran.dg/gomp/adjust-args-14.f90 | 2 +-
libgomp/libgomp.texi | 1 +
libgomp/testsuite/libgomp.c++/need-device-ptr.C| 175 +
.../testsuite/libgomp.c-c++-common/dispatch-3.c| 35 +
.../adjust-args-array-descriptor.f90 | 89 +++
.../testsuite/libgomp.fortran/need-device-ptr.f90 | 132
13 files changed, 633 insertions(+), 39 deletions(-)
diff --git a/gcc/cp/parser.cc b/gcc/cp/parser.cc
index 747209fc77f1..e60687f4a4e6 100644
--- a/gcc/cp/parser.cc
+++ b/gcc/cp/parser.cc
@@ -51407,7 +51407,8 @@ cp_finish_omp_declare_variant (cp_parser *parser,
cp_token *pragma_tok,
else
{
error_at (adjust_op_tok->location,
- "expected % or %");
+ "expected %, % or "
+ "%");
/* We should be trying to recover here instead of immediately
failing, skipping to close paren and continuing. */
goto fail;
@@ -51418,8 +51419,8 @@ cp_finish_omp_declare_variant (cp_parser *parser,
cp_token *pragma_tok,
/* We should be trying to recover here instead of immediately
failing, skipping to close paren and continuing. */
error_at (adjust_op_tok->location,
- "expected % or % followed "
- "by %<:%>");
+ "expected %, % or "
+ "% followed by %<:%>");
goto fail;
}
/* cp_parser_omp_var_list_no_open used to handle this, we don't use
diff --git a/gcc/fortran/trans-openmp.cc b/gcc/fortran/trans-openmp.cc
index 73ec9324dea1..b22bdfdf309e 100644
--- a/gcc/fortran/trans-openmp.cc
+++ b/gcc/fortran/trans-openmp.cc
@@ -11968,6 +11968,34 @@ gfc_trans_omp_declare_variant
[gcc(refs/users/meissner/heads/work203-bugs)] Add ChangeLog.bugs and update REVISION.
https://gcc.gnu.org/g:84545af0e21cdb55243214ed12850ba5dd09b2ca commit 84545af0e21cdb55243214ed12850ba5dd09b2ca Author: Michael Meissner Date: Wed Apr 30 13:51:25 2025 -0400 Add ChangeLog.bugs and update REVISION. 2025-04-30 Michael Meissner gcc/ * ChangeLog.bugs: New file for branch. * REVISION: Update. Diff: --- gcc/ChangeLog.bugs | 5 + gcc/REVISION | 2 +- 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog.bugs b/gcc/ChangeLog.bugs new file mode 100644 index ..89d98bf354cf --- /dev/null +++ b/gcc/ChangeLog.bugs @@ -0,0 +1,5 @@ + Branch work203-bugs, baseline + +2025-04-30 Michael Meissner + + Clone branch diff --git a/gcc/REVISION b/gcc/REVISION index ca84be7e752d..2f93ed18974f 100644 --- a/gcc/REVISION +++ b/gcc/REVISION @@ -1 +1 @@ -work203 branch +work203-bugs branch
[gcc] Created branch 'meissner/heads/work203-bugs' in namespace 'refs/users'
The branch 'meissner/heads/work203-bugs' was created in namespace 'refs/users' pointing to: 1adaa3d9d5c1... Add ChangeLog.meissner and REVISION.
[gcc(refs/users/meissner/heads/work203)] Add ChangeLog.meissner and REVISION.
https://gcc.gnu.org/g:1adaa3d9d5c1beb0a6c262ba654d7ca0840900f8 commit 1adaa3d9d5c1beb0a6c262ba654d7ca0840900f8 Author: Michael Meissner Date: Wed Apr 30 13:50:34 2025 -0400 Add ChangeLog.meissner and REVISION. 2025-04-30 Michael Meissner gcc/ * REVISION: New file for branch. * ChangeLog.meissner: New file. gcc/c-family/ * ChangeLog.meissner: New file. gcc/c/ * ChangeLog.meissner: New file. gcc/cp/ * ChangeLog.meissner: New file. gcc/fortran/ * ChangeLog.meissner: New file. gcc/testsuite/ * ChangeLog.meissner: New file. libgcc/ * ChangeLog.meissner: New file. Diff: --- gcc/ChangeLog.meissner | 5 + gcc/REVISION | 1 + gcc/c-family/ChangeLog.meissner | 5 + gcc/c/ChangeLog.meissner | 5 + gcc/cp/ChangeLog.meissner| 5 + gcc/fortran/ChangeLog.meissner | 5 + gcc/testsuite/ChangeLog.meissner | 5 + libgcc/ChangeLog.meissner| 5 + libstdc++-v3/ChangeLog.meissner | 5 + 9 files changed, 41 insertions(+) diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner new file mode 100644 index ..34ba5830e3cb --- /dev/null +++ b/gcc/ChangeLog.meissner @@ -0,0 +1,5 @@ + Branch work203, baseline + +2025-04-30 Michael Meissner + + Clone branch diff --git a/gcc/REVISION b/gcc/REVISION new file mode 100644 index ..ca84be7e752d --- /dev/null +++ b/gcc/REVISION @@ -0,0 +1 @@ +work203 branch diff --git a/gcc/c-family/ChangeLog.meissner b/gcc/c-family/ChangeLog.meissner new file mode 100644 index ..34ba5830e3cb --- /dev/null +++ b/gcc/c-family/ChangeLog.meissner @@ -0,0 +1,5 @@ + Branch work203, baseline + +2025-04-30 Michael Meissner + + Clone branch diff --git a/gcc/c/ChangeLog.meissner b/gcc/c/ChangeLog.meissner new file mode 100644 index ..34ba5830e3cb --- /dev/null +++ b/gcc/c/ChangeLog.meissner @@ -0,0 +1,5 @@ + Branch work203, baseline + +2025-04-30 Michael Meissner + + Clone branch diff --git a/gcc/cp/ChangeLog.meissner b/gcc/cp/ChangeLog.meissner new file mode 100644 index ..34ba5830e3cb --- /dev/null +++ b/gcc/cp/ChangeLog.meissner @@ -0,0 +1,5 @@ + Branch work203, baseline + +2025-04-30 Michael Meissner + + Clone branch diff --git a/gcc/fortran/ChangeLog.meissner b/gcc/fortran/ChangeLog.meissner new file mode 100644 index ..34ba5830e3cb --- /dev/null +++ b/gcc/fortran/ChangeLog.meissner @@ -0,0 +1,5 @@ + Branch work203, baseline + +2025-04-30 Michael Meissner + + Clone branch diff --git a/gcc/testsuite/ChangeLog.meissner b/gcc/testsuite/ChangeLog.meissner new file mode 100644 index ..34ba5830e3cb --- /dev/null +++ b/gcc/testsuite/ChangeLog.meissner @@ -0,0 +1,5 @@ + Branch work203, baseline + +2025-04-30 Michael Meissner + + Clone branch diff --git a/libgcc/ChangeLog.meissner b/libgcc/ChangeLog.meissner new file mode 100644 index ..34ba5830e3cb --- /dev/null +++ b/libgcc/ChangeLog.meissner @@ -0,0 +1,5 @@ + Branch work203, baseline + +2025-04-30 Michael Meissner + + Clone branch diff --git a/libstdc++-v3/ChangeLog.meissner b/libstdc++-v3/ChangeLog.meissner new file mode 100644 index ..34ba5830e3cb --- /dev/null +++ b/libstdc++-v3/ChangeLog.meissner @@ -0,0 +1,5 @@ + Branch work203, baseline + +2025-04-30 Michael Meissner + + Clone branch
[gcc] Created branch 'meissner/heads/work203' in namespace 'refs/users'
The branch 'meissner/heads/work203' was created in namespace 'refs/users' pointing to: 3584aab37f54... testsuite: Force -mcmodel=small for gcc.target/aarch64/pr11
[gcc(refs/users/meissner/heads/work204)] Add ChangeLog.meissner and REVISION.
https://gcc.gnu.org/g:3a638f38232071f9dd00779e0b230741b8f5736f commit 3a638f38232071f9dd00779e0b230741b8f5736f Author: Michael Meissner Date: Wed Apr 30 13:54:40 2025 -0400 Add ChangeLog.meissner and REVISION. 2025-04-30 Michael Meissner gcc/ * REVISION: New file for branch. * ChangeLog.meissner: New file. gcc/c-family/ * ChangeLog.meissner: New file. gcc/c/ * ChangeLog.meissner: New file. gcc/cp/ * ChangeLog.meissner: New file. gcc/fortran/ * ChangeLog.meissner: New file. gcc/testsuite/ * ChangeLog.meissner: New file. libgcc/ * ChangeLog.meissner: New file. Diff: --- gcc/ChangeLog.meissner | 5 + gcc/REVISION | 1 + gcc/c-family/ChangeLog.meissner | 5 + gcc/c/ChangeLog.meissner | 5 + gcc/cp/ChangeLog.meissner| 5 + gcc/fortran/ChangeLog.meissner | 5 + gcc/testsuite/ChangeLog.meissner | 5 + libgcc/ChangeLog.meissner| 5 + libstdc++-v3/ChangeLog.meissner | 5 + 9 files changed, 41 insertions(+) diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner new file mode 100644 index ..28fa8231a61c --- /dev/null +++ b/gcc/ChangeLog.meissner @@ -0,0 +1,5 @@ + Branch work204, baseline + +2025-04-30 Michael Meissner + + Clone branch diff --git a/gcc/REVISION b/gcc/REVISION new file mode 100644 index ..d4f18d737afd --- /dev/null +++ b/gcc/REVISION @@ -0,0 +1 @@ +work204 branch diff --git a/gcc/c-family/ChangeLog.meissner b/gcc/c-family/ChangeLog.meissner new file mode 100644 index ..28fa8231a61c --- /dev/null +++ b/gcc/c-family/ChangeLog.meissner @@ -0,0 +1,5 @@ + Branch work204, baseline + +2025-04-30 Michael Meissner + + Clone branch diff --git a/gcc/c/ChangeLog.meissner b/gcc/c/ChangeLog.meissner new file mode 100644 index ..28fa8231a61c --- /dev/null +++ b/gcc/c/ChangeLog.meissner @@ -0,0 +1,5 @@ + Branch work204, baseline + +2025-04-30 Michael Meissner + + Clone branch diff --git a/gcc/cp/ChangeLog.meissner b/gcc/cp/ChangeLog.meissner new file mode 100644 index ..28fa8231a61c --- /dev/null +++ b/gcc/cp/ChangeLog.meissner @@ -0,0 +1,5 @@ + Branch work204, baseline + +2025-04-30 Michael Meissner + + Clone branch diff --git a/gcc/fortran/ChangeLog.meissner b/gcc/fortran/ChangeLog.meissner new file mode 100644 index ..28fa8231a61c --- /dev/null +++ b/gcc/fortran/ChangeLog.meissner @@ -0,0 +1,5 @@ + Branch work204, baseline + +2025-04-30 Michael Meissner + + Clone branch diff --git a/gcc/testsuite/ChangeLog.meissner b/gcc/testsuite/ChangeLog.meissner new file mode 100644 index ..28fa8231a61c --- /dev/null +++ b/gcc/testsuite/ChangeLog.meissner @@ -0,0 +1,5 @@ + Branch work204, baseline + +2025-04-30 Michael Meissner + + Clone branch diff --git a/libgcc/ChangeLog.meissner b/libgcc/ChangeLog.meissner new file mode 100644 index ..28fa8231a61c --- /dev/null +++ b/libgcc/ChangeLog.meissner @@ -0,0 +1,5 @@ + Branch work204, baseline + +2025-04-30 Michael Meissner + + Clone branch diff --git a/libstdc++-v3/ChangeLog.meissner b/libstdc++-v3/ChangeLog.meissner new file mode 100644 index ..28fa8231a61c --- /dev/null +++ b/libstdc++-v3/ChangeLog.meissner @@ -0,0 +1,5 @@ + Branch work204, baseline + +2025-04-30 Michael Meissner + + Clone branch
[gcc] Created branch 'meissner/heads/work204-bugs' in namespace 'refs/users'
The branch 'meissner/heads/work204-bugs' was created in namespace 'refs/users' pointing to: 3a638f382320... Add ChangeLog.meissner and REVISION.
[gcc] Created branch 'meissner/heads/work204' in namespace 'refs/users'
The branch 'meissner/heads/work204' was created in namespace 'refs/users' pointing to: 3584aab37f54... testsuite: Force -mcmodel=small for gcc.target/aarch64/pr11
[gcc(refs/users/meissner/heads/work204-bugs)] Add ChangeLog.bugs and update REVISION.
https://gcc.gnu.org/g:508b531ea7deb1830e3c427f8687abd38fc1b6d0 commit 508b531ea7deb1830e3c427f8687abd38fc1b6d0 Author: Michael Meissner Date: Wed Apr 30 13:55:30 2025 -0400 Add ChangeLog.bugs and update REVISION. 2025-04-30 Michael Meissner gcc/ * ChangeLog.bugs: New file for branch. * REVISION: Update. Diff: --- gcc/ChangeLog.bugs | 5 + gcc/REVISION | 2 +- 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog.bugs b/gcc/ChangeLog.bugs new file mode 100644 index ..01677977864f --- /dev/null +++ b/gcc/ChangeLog.bugs @@ -0,0 +1,5 @@ + Branch work204-bugs, baseline + +2025-04-30 Michael Meissner + + Clone branch diff --git a/gcc/REVISION b/gcc/REVISION index d4f18d737afd..0e2bd7e09059 100644 --- a/gcc/REVISION +++ b/gcc/REVISION @@ -1 +1 @@ -work204 branch +work204-bugs branch
[gcc(refs/users/meissner/heads/work204)] Add -mcpu=future tuning support.
https://gcc.gnu.org/g:9f2d754f09d8afa213d6dcbad6512a574914773a commit 9f2d754f09d8afa213d6dcbad6512a574914773a Author: Michael Meissner Date: Wed Apr 30 15:27:42 2025 -0400 Add -mcpu=future tuning support. This patch makes -mtune=future use the same tuning decision as -mtune=power11. 2025-04-24 Michael Meissner gcc/ * config/rs6000/power10.md (all reservations): Add future as an alterntive to power10 and power11. Diff: --- gcc/config/rs6000/power10.md | 145 ++- 1 file changed, 73 insertions(+), 72 deletions(-) diff --git a/gcc/config/rs6000/power10.md b/gcc/config/rs6000/power10.md index fd31b16b3314..bdd7e58145ba 100644 --- a/gcc/config/rs6000/power10.md +++ b/gcc/config/rs6000/power10.md @@ -1,4 +1,5 @@ -;; Scheduling description for the IBM Power10 and Power11 processors. +;; Scheduling description for the IBM Power10, Power11, and +;; potential future processors. ;; Copyright (C) 2020-2025 Free Software Foundation, Inc. ;; ;; Contributed by Pat Haugen (pthau...@us.ibm.com). @@ -97,12 +98,12 @@ (eq_attr "update" "no") (eq_attr "size" "!128") (eq_attr "prefixed" "no") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_any_power10,LU_power10") (define_insn_reservation "power10-fused-load" 4 (and (eq_attr "type" "fused_load_cmpi,fused_addis_load,fused_load_load") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_even_power10,LU_power10") (define_insn_reservation "power10-prefixed-load" 4 @@ -110,13 +111,13 @@ (eq_attr "update" "no") (eq_attr "size" "!128") (eq_attr "prefixed" "yes") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_even_power10,LU_power10") (define_insn_reservation "power10-load-update" 4 (and (eq_attr "type" "load") (eq_attr "update" "yes") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_even_power10,LU_power10+SXU_power10") (define_insn_reservation "power10-fpload-double" 4 @@ -124,7 +125,7 @@ (eq_attr "update" "no") (eq_attr "size" "64") (eq_attr "prefixed" "no") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_any_power10,LU_power10") (define_insn_reservation "power10-prefixed-fpload-double" 4 @@ -132,14 +133,14 @@ (eq_attr "update" "no") (eq_attr "size" "64") (eq_attr "prefixed" "yes") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_even_power10,LU_power10") (define_insn_reservation "power10-fpload-update-double" 4 (and (eq_attr "type" "fpload") (eq_attr "update" "yes") (eq_attr "size" "64") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_even_power10,LU_power10+SXU_power10") ; SFmode loads are cracked and have additional 3 cycles over DFmode @@ -148,27 +149,27 @@ (and (eq_attr "type" "fpload") (eq_attr "update" "no") (eq_attr "size" "32") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_even_power10,LU_power10") (define_insn_reservation "power10-fpload-update-single" 7 (and (eq_attr "type" "fpload") (eq_attr "update" "yes") (eq_attr "size" "32") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_even_power10,LU_power10+SXU_power10") (define_insn_reservation "power10-vecload" 4 (and (eq_attr "type" "vecload") (eq_attr "size" "!256") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_any_power10,LU_power10") ; lxvp (define_insn_reservation "power10-vecload-pair" 4 (and (eq_attr "type" "vecload") (eq_attr "size" "256") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_even_power10,LU_power10+SXU_power10") ; Store Unit @@ -178,12 +179,12 @@ (eq_attr "prefixed" "no") (eq_attr "size" "!128") (eq_attr "size" "!256") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_any_power10,STU_power10") (define_insn_reservation "power10-fused-store" 0 (and (eq_attr "type" "fused_store_store") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_even_power10,STU_power10") (define_insn_reservation "power10-prefixed-store" 0 @@ -191,52 +192,52 @@ (eq_attr "prefixed" "yes") (eq_attr "size" "!128") (eq_attr "size" "!256") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_even_power10,STU_power10") ; Update forms have 2 cycle lat
[gcc(refs/users/meissner/heads/work204)] Use vector pair load/store for memcpy with -mcpu=future
https://gcc.gnu.org/g:cdecb017755a25107acbcd8623b875464ba4ae95
commit cdecb017755a25107acbcd8623b875464ba4ae95
Author: Michael Meissner
Date: Wed Apr 30 15:28:56 2025 -0400
Use vector pair load/store for memcpy with -mcpu=future
In the development for the power10 processor, GCC did not enable using the
load
vector pair and store vector pair instructions when optimizing things like
memory copy. This patch enables using those instructions if -mcpu=future is
used.
2025-04-30 Michael Meissner
gcc/
* config/rs6000/rs6000-cpus.def (ISA_FUTURE_MASKS_SERVER): Enable
using
load vector pair and store vector pair instructions for memory copy
operations.
(POWERPC_MASKS): Make the bit for enabling using load vector pair
and
store vector pair operations set and reset when the PowerPC
processor is
changed.
* gcc/config/rs6000/rs6000.cc (rs6000_machine_from_flags): Disable
-mblock-ops-vector-pair from influcing .machine selection.
gcc/testsuite/
* gcc.target/powerpc/future-3.c: New test.
Diff:
---
gcc/config/rs6000/rs6000-cpus.def | 4 +++-
gcc/config/rs6000/rs6000.cc | 2 +-
gcc/testsuite/gcc.target/powerpc/future-3.c | 22 ++
3 files changed, 26 insertions(+), 2 deletions(-)
diff --git a/gcc/config/rs6000/rs6000-cpus.def
b/gcc/config/rs6000/rs6000-cpus.def
index 228d0b5e7b54..063591f5c094 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -84,7 +84,8 @@
| OPTION_MASK_POWER11)
#define FUTURE_MASKS_SERVER(POWER11_MASKS_SERVER \
-| OPTION_MASK_FUTURE)
+| OPTION_MASK_FUTURE \
+| OPTION_MASK_BLOCK_OPS_VECTOR_PAIR)
/* Flags that need to be turned off if -mno-vsx. */
#define OTHER_VSX_VECTOR_MASKS (OPTION_MASK_EFFICIENT_UNALIGNED_VSX\
@@ -114,6 +115,7 @@
/* Mask of all options to set the default isa flags based on -mcpu=. */
#define POWERPC_MASKS (OPTION_MASK_ALTIVEC\
+| OPTION_MASK_BLOCK_OPS_VECTOR_PAIR\
| OPTION_MASK_CMPB \
| OPTION_MASK_CRYPTO \
| OPTION_MASK_DFP \
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 9c6ebc0f5b2d..3f2c007a39c6 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -5908,7 +5908,7 @@ rs6000_machine_from_flags (void)
/* Disable the flags that should never influence the .machine selection. */
flags &= ~(OPTION_MASK_PPC_GFXOPT | OPTION_MASK_PPC_GPOPT | OPTION_MASK_ISEL
-| OPTION_MASK_ALTIVEC);
+| OPTION_MASK_ALTIVEC | OPTION_MASK_BLOCK_OPS_VECTOR_PAIR);
if ((flags & (FUTURE_MASKS_SERVER & ~ISA_3_1_MASKS_SERVER)) != 0)
return "future";
diff --git a/gcc/testsuite/gcc.target/powerpc/future-3.c
b/gcc/testsuite/gcc.target/powerpc/future-3.c
new file mode 100644
index ..afa8b96d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/future-3.c
@@ -0,0 +1,22 @@
+/* 32-bit doesn't generate vector pair instructions. */
+/* { dg-do compile { target lp64 } } */
+/* { dg-options "-mdejagnu-cpu=future -O2" } */
+
+/* Test to see that memcpy will use load/store vector pair with
+ -mcpu=future. */
+
+#ifndef SIZE
+#define SIZE 4
+#endif
+
+extern vector double to[SIZE], from[SIZE];
+
+void
+copy (void)
+{
+ __builtin_memcpy (to, from, sizeof (to));
+ return;
+}
+
+/* { dg-final { scan-assembler {\mlxvpx?\M} } } */
+/* { dg-final { scan-assembler {\mstxvpx?\M} } } */
[gcc(refs/users/meissner/heads/work204)] Add -mcpu=future tests.
https://gcc.gnu.org/g:503355195518a816e4cf4a0624aea103de003c49
commit 503355195518a816e4cf4a0624aea103de003c49
Author: Michael Meissner
Date: Wed Apr 30 15:28:11 2025 -0400
Add -mcpu=future tests.
This patch adds simple tests for -mcpu=future.
2025-04-30 Michael Meissner
gcc/testsuite/
* gcc.target/powerpc/future-1.c: New test.
* gcc.target/powerpc/future-2.c: Likewise.
Diff:
---
gcc/testsuite/gcc.target/powerpc/future-1.c | 13 +
gcc/testsuite/gcc.target/powerpc/future-2.c | 24
2 files changed, 37 insertions(+)
diff --git a/gcc/testsuite/gcc.target/powerpc/future-1.c
b/gcc/testsuite/gcc.target/powerpc/future-1.c
new file mode 100644
index ..f1b940d7bebf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/future-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mdejagnu-cpu=future -O2" } */
+
+/* Basic check to see if the compiler supports -mcpu=future and if it defines
+ _ARCH_PWR11. */
+
+#ifndef _ARCH_FUTURE
+#error "-mcpu=future is not supported"
+#endif
+
+void foo (void)
+{
+}
diff --git a/gcc/testsuite/gcc.target/powerpc/future-2.c
b/gcc/testsuite/gcc.target/powerpc/future-2.c
new file mode 100644
index ..5552cefa3c2e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/future-2.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+/* Check if we can set the future target via a target attribute. */
+
+__attribute__((__target__("cpu=power9")))
+void foo_p9 (void)
+{
+}
+
+__attribute__((__target__("cpu=power10")))
+void foo_p10 (void)
+{
+}
+
+__attribute__((__target__("cpu=power11")))
+void foo_p11 (void)
+{
+}
+
+__attribute__((__target__("cpu=future")))
+void foo_future (void)
+{
+}
[gcc(refs/users/meissner/heads/work204)] Add rs6000 architecture masks.
https://gcc.gnu.org/g:2fc35926401e7abb3f3786df825f178e5d65d06c commit 2fc35926401e7abb3f3786df825f178e5d65d06c Author: Michael Meissner Date: Wed Apr 30 15:31:06 2025 -0400 Add rs6000 architecture masks. This patch begins the journey to move architecture bits that are not user ISA options from rs6000_isa_flags to a new targt variable rs6000_arch_flags. The intention is to remove switches that are currently isa options, but the user should not be using this particular option. For example, we want users to use -mcpu=power10 and not just -mpower10. This patch also changes the target_clones support to use an architecture mask instead of isa bits. This patch also switches the handling of .machine to use architecture masks if they exist (power4 through power11). All of the other PowerPCs will continue to use the existing code for setting the .machine option. I have built both big endian and little endian bootstrap compilers and there were no regressions. In addition, I constructed a test case that used every archiecture define (like _ARCH_PWR4, etc.) and I also looked at the .machine directive generated. I ran this test for all supported combinations of -mcpu, big/little endian, and 32/64 bit support. Every single instance generated exactly the same code with the patches installed compared to the compiler before installing the patches. The only difference in this patch compared to the first version posted on November 6th is that I the correct attribution and copyright year (i.e. that I created rs6000-arch.def in 2024). Can I install this patch on the GCC 16 trunk? 2025-04-30 Michael Meissner gcc/ * config/rs6000/default64.h (TARGET_CPU_DEFAULT): Set default cpu name. * config/rs6000/rs6000-arch.def: New file. * config/rs6000/rs6000.cc (struct clone_map): Switch to using architecture masks instead of ISA masks. (rs6000_clone_map): Likewise. (rs6000_print_isa_options): Add an architecture flags argument, change all callers. (get_arch_flag): New function. (rs6000_debug_reg_global): Update rs6000_print_isa_options calls. (rs6000_option_override_internal): Likewise. (rs6000_machine_from_flags): Switch to using architecture masks instead of ISA masks. (struct rs6000_arch_mask): New structure. (rs6000_arch_masks): New table of architecutre masks and names. (rs6000_function_specific_save): Save architecture flags. (rs6000_function_specific_restore): Restore architecture flags. (rs6000_function_specific_print): Update rs6000_print_isa_options calls. (rs6000_print_options_internal): Add architecture flags options. (rs6000_clone_priority): Switch to using architecture masks instead of ISA masks. (rs6000_can_inline_p): Don't allow inling if the callee requires a newer architecture than the caller. * config/rs6000/rs6000.h: Use rs6000-arch.def to create the architecture masks. * config/rs6000/rs6000.opt (rs6000_arch_flags): New target variable. (x_rs6000_arch_flags): New save/restore field for rs6000_arch_flags. Diff: --- gcc/config/rs6000/default64.h | 11 ++ gcc/config/rs6000/rs6000-arch.def | 49 + gcc/config/rs6000/rs6000.cc | 222 +++--- gcc/config/rs6000/rs6000.h| 24 + gcc/config/rs6000/rs6000.opt | 8 ++ 5 files changed, 277 insertions(+), 37 deletions(-) diff --git a/gcc/config/rs6000/default64.h b/gcc/config/rs6000/default64.h index 7f6001ded852..188f5c1d1378 100644 --- a/gcc/config/rs6000/default64.h +++ b/gcc/config/rs6000/default64.h @@ -21,6 +21,7 @@ along with GCC; see the file COPYING3. If not see #define RS6000_CPU(NAME, CPU, FLAGS) #include "rs6000-cpus.def" #undef RS6000_CPU +#undef TARGET_CPU_DEFAULT #if (TARGET_DEFAULT & MASK_LITTLE_ENDIAN) #undef TARGET_DEFAULT @@ -28,10 +29,20 @@ along with GCC; see the file COPYING3. If not see | MASK_LITTLE_ENDIAN) #undef ASM_DEFAULT_SPEC #define ASM_DEFAULT_SPEC "-mpower8" +#define TARGET_CPU_DEFAULT "power8" + #else #undef TARGET_DEFAULT #define TARGET_DEFAULT (OPTION_MASK_PPC_GFXOPT | OPTION_MASK_PPC_GPOPT \ | OPTION_MASK_MFCRF | MASK_POWERPC64 | MASK_64BIT) #undef ASM_DEFAULT_SPEC #define ASM_DEFAULT_SPEC "-mpower4" + +#if (TARGET_DEFAULT & MASK_POWERPC64) +#define TARGET_CPU_DEFAULT "powerpc64" + +#else +#define TARGET_CPU_DEFAULT "powerpc" +#endif + #endif diff --git a/gcc/config/rs6000/rs6000-arch.def b/gcc/config/rs6000/rs6000-arch.def new file mode 100644 index ..c0dbc5834333 --- /dev/null +++ b/gcc/config/rs6000/rs6000-arch.def @
[gcc(refs/users/meissner/heads/work204)] Revert changes
https://gcc.gnu.org/g:ef1deb7b184717ca5b1dd56d9053fa7c59f67c96 commit ef1deb7b184717ca5b1dd56d9053fa7c59f67c96 Author: Michael Meissner Date: Wed Apr 30 15:26:08 2025 -0400 Revert changes Diff: --- gcc/config/rs6000/power10.md | 145 +-- 1 file changed, 72 insertions(+), 73 deletions(-) diff --git a/gcc/config/rs6000/power10.md b/gcc/config/rs6000/power10.md index bdd7e58145ba..fd31b16b3314 100644 --- a/gcc/config/rs6000/power10.md +++ b/gcc/config/rs6000/power10.md @@ -1,5 +1,4 @@ -;; Scheduling description for the IBM Power10, Power11, and -;; potential future processors. +;; Scheduling description for the IBM Power10 and Power11 processors. ;; Copyright (C) 2020-2025 Free Software Foundation, Inc. ;; ;; Contributed by Pat Haugen (pthau...@us.ibm.com). @@ -98,12 +97,12 @@ (eq_attr "update" "no") (eq_attr "size" "!128") (eq_attr "prefixed" "no") - (eq_attr "cpu" "power10,power11,future")) + (eq_attr "cpu" "power10,power11")) "DU_any_power10,LU_power10") (define_insn_reservation "power10-fused-load" 4 (and (eq_attr "type" "fused_load_cmpi,fused_addis_load,fused_load_load") - (eq_attr "cpu" "power10,power11,future")) + (eq_attr "cpu" "power10,power11")) "DU_even_power10,LU_power10") (define_insn_reservation "power10-prefixed-load" 4 @@ -111,13 +110,13 @@ (eq_attr "update" "no") (eq_attr "size" "!128") (eq_attr "prefixed" "yes") - (eq_attr "cpu" "power10,power11,future")) + (eq_attr "cpu" "power10,power11")) "DU_even_power10,LU_power10") (define_insn_reservation "power10-load-update" 4 (and (eq_attr "type" "load") (eq_attr "update" "yes") - (eq_attr "cpu" "power10,power11,future")) + (eq_attr "cpu" "power10,power11")) "DU_even_power10,LU_power10+SXU_power10") (define_insn_reservation "power10-fpload-double" 4 @@ -125,7 +124,7 @@ (eq_attr "update" "no") (eq_attr "size" "64") (eq_attr "prefixed" "no") - (eq_attr "cpu" "power10,power11,future")) + (eq_attr "cpu" "power10,power11")) "DU_any_power10,LU_power10") (define_insn_reservation "power10-prefixed-fpload-double" 4 @@ -133,14 +132,14 @@ (eq_attr "update" "no") (eq_attr "size" "64") (eq_attr "prefixed" "yes") - (eq_attr "cpu" "power10,power11,future")) + (eq_attr "cpu" "power10,power11")) "DU_even_power10,LU_power10") (define_insn_reservation "power10-fpload-update-double" 4 (and (eq_attr "type" "fpload") (eq_attr "update" "yes") (eq_attr "size" "64") - (eq_attr "cpu" "power10,power11,future")) + (eq_attr "cpu" "power10,power11")) "DU_even_power10,LU_power10+SXU_power10") ; SFmode loads are cracked and have additional 3 cycles over DFmode @@ -149,27 +148,27 @@ (and (eq_attr "type" "fpload") (eq_attr "update" "no") (eq_attr "size" "32") - (eq_attr "cpu" "power10,power11,future")) + (eq_attr "cpu" "power10,power11")) "DU_even_power10,LU_power10") (define_insn_reservation "power10-fpload-update-single" 7 (and (eq_attr "type" "fpload") (eq_attr "update" "yes") (eq_attr "size" "32") - (eq_attr "cpu" "power10,power11,future")) + (eq_attr "cpu" "power10,power11")) "DU_even_power10,LU_power10+SXU_power10") (define_insn_reservation "power10-vecload" 4 (and (eq_attr "type" "vecload") (eq_attr "size" "!256") - (eq_attr "cpu" "power10,power11,future")) + (eq_attr "cpu" "power10,power11")) "DU_any_power10,LU_power10") ; lxvp (define_insn_reservation "power10-vecload-pair" 4 (and (eq_attr "type" "vecload") (eq_attr "size" "256") - (eq_attr "cpu" "power10,power11,future")) + (eq_attr "cpu" "power10,power11")) "DU_even_power10,LU_power10+SXU_power10") ; Store Unit @@ -179,12 +178,12 @@ (eq_attr "prefixed" "no") (eq_attr "size" "!128") (eq_attr "size" "!256") - (eq_attr "cpu" "power10,power11,future")) + (eq_attr "cpu" "power10,power11")) "DU_any_power10,STU_power10") (define_insn_reservation "power10-fused-store" 0 (and (eq_attr "type" "fused_store_store") - (eq_attr "cpu" "power10,power11,future")) + (eq_attr "cpu" "power10,power11")) "DU_even_power10,STU_power10") (define_insn_reservation "power10-prefixed-store" 0 @@ -192,52 +191,52 @@ (eq_attr "prefixed" "yes") (eq_attr "size" "!128") (eq_attr "size" "!256") - (eq_attr "cpu" "power10,power11,future")) + (eq_attr "cpu" "power10,power11")) "DU_even_power10,STU_power10") ; Update forms have 2 cycle latency for updated addr reg (define_insn_reservation "power10-store-update" 2 (and (eq_attr "type" "store,fpstore") (eq_attr "update" "yes") - (eq_attr "cpu" "power10,power11,future")) + (eq_attr "cpu" "power10,power11")) "DU_any_power10,STU_power10") ; stxvp
[gcc(refs/users/meissner/heads/work204)] Change TARGET_POPCNTD to TARGET_POWER7.
https://gcc.gnu.org/g:30bfb83cbc21af120c9b62e367e62dd050545d2d
commit 30bfb83cbc21af120c9b62e367e62dd050545d2d
Author: Michael Meissner
Date: Wed Apr 30 15:11:29 2025 -0400
Change TARGET_POPCNTD to TARGET_POWER7.
This patch changes TARGET_POPCNTD to TARGET_POWER7. The -mpopcntd switch
is not
being changed, just the name of the macros used to determine if the PowerPC
processor supports ISA 2.6 (Power7).
2025-04-30 Michael Meissner
gcc/
* gcc/config/rs6000/dfp.md (cmp_internal1): Change
TARGET_POPCNTD
to TARGET_POWER7.
* gcc/config/rs6000/rs6000-builtin.cc (rs6000_builtin_is_supported):
Likewise.
* gcc/config/rs6000/rs6000-string.cc (expand_block_compare):
Likewise.
* gcc/config/rs6000/rs6000.cc (rs6000_hard_regno_mode_ok_uncached):
Likewise.
(rs6000_option_override_internal): Likewise.
(rs6000_rtx_costs): Likewise.
* gcc/config/rs6000/rs6000.h (TARGET_LDBRX): Likewise.
(TARGET_FCFID): Likewise.
(TARGET_LFIWZX): Likewise.
(TARGET_FCFIDS): Likewise.
(TARGET_FCFIDU): Likewise.
(TARGET_FCFIDUS): Likewise.
(TARGET_FCTIDUZ): Likewise.
(TARGET_FCTIWUZ): Likewise.
(TARGET_FCTIDUZ): Likewise.
(TARGET_POWER7): New macro.
(TARGET_EXTRA_BUILTINS): Change TARGET_POPCNTD to TARGET_POWER7.
(CTZ_DEFINED_VALUE_AT_ZERO): Likewise.
* gcc/config/rs6000/rs6000.md (enabled attribute): Likewise.
(lrintsi2): Likewise.
(lrintsi): Likewise.
(lrintsi_di): Likewise.
(cmpmemsi): Likewise.
(bpermd_): Likewise.
(addg6s): Likewise.
(cdtbcd): Likewise.
(cbcdtd): Likewise.
(div_): Likewise.
Diff:
---
gcc/config/rs6000/dfp.md| 2 +-
gcc/config/rs6000/rs6000-builtin.cc | 4 ++--
gcc/config/rs6000/rs6000-string.cc | 2 +-
gcc/config/rs6000/rs6000.cc | 8
gcc/config/rs6000/rs6000.h | 21 +++--
gcc/config/rs6000/rs6000.md | 20 ++--
6 files changed, 29 insertions(+), 28 deletions(-)
diff --git a/gcc/config/rs6000/dfp.md b/gcc/config/rs6000/dfp.md
index 59fa66ae15c8..5919149682b2 100644
--- a/gcc/config/rs6000/dfp.md
+++ b/gcc/config/rs6000/dfp.md
@@ -214,7 +214,7 @@
(define_insn "floatdidd2"
[(set (match_operand:DD 0 "gpc_reg_operand" "=d")
(float:DD (match_operand:DI 1 "gpc_reg_operand" "d")))]
- "TARGET_DFP && TARGET_POPCNTD"
+ "TARGET_DFP && TARGET_POWER7"
"dcffix %0,%1"
[(set_attr "type" "dfp")])
diff --git a/gcc/config/rs6000/rs6000-builtin.cc
b/gcc/config/rs6000/rs6000-builtin.cc
index dbb8520ab039..2366b2aee00a 100644
--- a/gcc/config/rs6000/rs6000-builtin.cc
+++ b/gcc/config/rs6000/rs6000-builtin.cc
@@ -161,9 +161,9 @@ rs6000_builtin_is_supported (enum rs6000_gen_builtins
fncode)
case ENB_P6_64:
return TARGET_POWER6 && TARGET_POWERPC64;
case ENB_P7:
- return TARGET_POPCNTD;
+ return TARGET_POWER7;
case ENB_P7_64:
- return TARGET_POPCNTD && TARGET_POWERPC64;
+ return TARGET_POWER7 && TARGET_POWERPC64;
case ENB_P8:
return TARGET_POWER8;
case ENB_P8V:
diff --git a/gcc/config/rs6000/rs6000-string.cc
b/gcc/config/rs6000/rs6000-string.cc
index 3d2911ca08a0..703f77fa0bf1 100644
--- a/gcc/config/rs6000/rs6000-string.cc
+++ b/gcc/config/rs6000/rs6000-string.cc
@@ -1949,7 +1949,7 @@ bool
expand_block_compare (rtx operands[])
{
/* TARGET_POPCNTD is already guarded at expand cmpmemsi. */
- gcc_assert (TARGET_POPCNTD);
+ gcc_assert (TARGET_POWER7);
/* For P8, this case is complicated to handle because the subtract
with carry instructions do not generate the 64-bit carry and so
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index baef2af3e57b..163e8ddebf55 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -1924,7 +1924,7 @@ rs6000_hard_regno_mode_ok_uncached (int regno,
machine_mode mode)
if(GET_MODE_SIZE (mode) == UNITS_PER_FP_WORD)
return 1;
- if (TARGET_POPCNTD && mode == SImode)
+ if (TARGET_POWER7 && mode == SImode)
return 1;
if (TARGET_P9_VECTOR && (mode == QImode || mode == HImode))
@@ -3918,7 +3918,7 @@ rs6000_option_override_internal (bool global_init_p)
rs6000_isa_flags |= (ISA_2_7_MASKS_SERVER & ~ignore_masks);
else if (TARGET_VSX)
rs6000_isa_flags |= (ISA_2_6_MASKS_SERVER & ~ignore_masks);
- else if (TARGET_POPCNTD)
+ else if (TARGET_POWER7)
rs6000_isa_flags |= (ISA_2_6_MASKS_EMBEDDED & ~ignore_masks);
else if (TARGET_DFP)
rs6000_isa_flags |= (ISA_2_5_MASKS_SERVER & ~ignore_masks);
@@ -4131,7 +4131,7 @@ rs6000_option_override_internal (bool global_init_p)
else if (TARGET_LONG_DOUBLE_128)
[gcc] Created branch 'meissner/heads/work204-dmf' in namespace 'refs/users'
The branch 'meissner/heads/work204-dmf' was created in namespace 'refs/users' pointing to: 3a638f382320... Add ChangeLog.meissner and REVISION.
[gcc(refs/users/meissner/heads/work204-cmodel)] Add ChangeLog.cmodel and update REVISION.
https://gcc.gnu.org/g:a36c6b6e956e10d68b74a70c78f516c81b959b7b commit a36c6b6e956e10d68b74a70c78f516c81b959b7b Author: Michael Meissner Date: Wed Apr 30 13:56:22 2025 -0400 Add ChangeLog.cmodel and update REVISION. 2025-04-30 Michael Meissner gcc/ * ChangeLog.cmodel: New file for branch. * REVISION: Update. Diff: --- gcc/ChangeLog.cmodel | 5 + gcc/REVISION | 2 +- 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog.cmodel b/gcc/ChangeLog.cmodel new file mode 100644 index ..de19de309b5d --- /dev/null +++ b/gcc/ChangeLog.cmodel @@ -0,0 +1,5 @@ + Branch work204-cmodel, baseline + +2025-04-30 Michael Meissner + + Clone branch diff --git a/gcc/REVISION b/gcc/REVISION index d4f18d737afd..69ecbb984c4b 100644 --- a/gcc/REVISION +++ b/gcc/REVISION @@ -1 +1 @@ -work204 branch +work204-cmodel branch
[gcc] Created branch 'meissner/heads/work204-cmodel' in namespace 'refs/users'
The branch 'meissner/heads/work204-cmodel' was created in namespace 'refs/users' pointing to: 3a638f382320... Add ChangeLog.meissner and REVISION.
[gcc] Created branch 'meissner/heads/work204-sha' in namespace 'refs/users'
The branch 'meissner/heads/work204-sha' was created in namespace 'refs/users' pointing to: 3a638f382320... Add ChangeLog.meissner and REVISION.
[gcc(refs/users/meissner/heads/work204-libs)] Add ChangeLog.libs and update REVISION.
https://gcc.gnu.org/g:a45443ff2f9c2a5326d60b62f9ccd44ef7a1f060 commit a45443ff2f9c2a5326d60b62f9ccd44ef7a1f060 Author: Michael Meissner Date: Wed Apr 30 13:58:08 2025 -0400 Add ChangeLog.libs and update REVISION. 2025-04-30 Michael Meissner gcc/ * ChangeLog.libs: New file for branch. * REVISION: Update. Diff: --- gcc/ChangeLog.libs | 5 + gcc/REVISION | 2 +- 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog.libs b/gcc/ChangeLog.libs new file mode 100644 index ..e5387e15c8a8 --- /dev/null +++ b/gcc/ChangeLog.libs @@ -0,0 +1,5 @@ + Branch work204-libs, baseline + +2025-04-30 Michael Meissner + + Clone branch diff --git a/gcc/REVISION b/gcc/REVISION index d4f18d737afd..b24f9dd0e8ca 100644 --- a/gcc/REVISION +++ b/gcc/REVISION @@ -1 +1 @@ -work204 branch +work204-libs branch
[gcc] Created branch 'meissner/heads/work204-submit' in namespace 'refs/users'
The branch 'meissner/heads/work204-submit' was created in namespace 'refs/users' pointing to: 3a638f382320... Add ChangeLog.meissner and REVISION.
[gcc(refs/users/meissner/heads/work204-submit)] Add ChangeLog.submit and update REVISION.
https://gcc.gnu.org/g:e975afa6ea95d0e238f5f9bce5f71a4f821715f1 commit e975afa6ea95d0e238f5f9bce5f71a4f821715f1 Author: Michael Meissner Date: Wed Apr 30 14:00:45 2025 -0400 Add ChangeLog.submit and update REVISION. 2025-04-30 Michael Meissner gcc/ * ChangeLog.submit: New file for branch. * REVISION: Update. Diff: --- gcc/ChangeLog.submit | 5 + gcc/REVISION | 2 +- 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog.submit b/gcc/ChangeLog.submit new file mode 100644 index ..386a58d75ee8 --- /dev/null +++ b/gcc/ChangeLog.submit @@ -0,0 +1,5 @@ + Branch work204-submit, baseline + +2025-04-30 Michael Meissner + + Clone branch diff --git a/gcc/REVISION b/gcc/REVISION index d4f18d737afd..d06051d2923f 100644 --- a/gcc/REVISION +++ b/gcc/REVISION @@ -1 +1 @@ -work204 branch +work204-submit branch
[gcc] Created branch 'meissner/heads/work204-paddis' in namespace 'refs/users'
The branch 'meissner/heads/work204-paddis' was created in namespace 'refs/users' pointing to: 3a638f382320... Add ChangeLog.meissner and REVISION.
[gcc(refs/users/meissner/heads/work204-dmf)] Add ChangeLog.dmf and update REVISION.
https://gcc.gnu.org/g:ad44f8e5a1d29bb3dd656d34799e985cc8284908 commit ad44f8e5a1d29bb3dd656d34799e985cc8284908 Author: Michael Meissner Date: Wed Apr 30 13:57:13 2025 -0400 Add ChangeLog.dmf and update REVISION. 2025-04-30 Michael Meissner gcc/ * ChangeLog.dmf: New file for branch. * REVISION: Update. Diff: --- gcc/ChangeLog.dmf | 5 + gcc/REVISION | 2 +- 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog.dmf b/gcc/ChangeLog.dmf new file mode 100644 index ..95d0646cc54f --- /dev/null +++ b/gcc/ChangeLog.dmf @@ -0,0 +1,5 @@ + Branch work204-dmf, baseline + +2025-04-30 Michael Meissner + + Clone branch diff --git a/gcc/REVISION b/gcc/REVISION index d4f18d737afd..1bb3527f0108 100644 --- a/gcc/REVISION +++ b/gcc/REVISION @@ -1 +1 @@ -work204 branch +work204-dmf branch
[gcc] Created branch 'meissner/heads/work204-libs' in namespace 'refs/users'
The branch 'meissner/heads/work204-libs' was created in namespace 'refs/users' pointing to: 3a638f382320... Add ChangeLog.meissner and REVISION.
[gcc(refs/users/meissner/heads/work204-sha)] Add ChangeLog.sha and update REVISION.
https://gcc.gnu.org/g:e6542a9af5f32a6423c8312ca06fd7300f4be87c commit e6542a9af5f32a6423c8312ca06fd7300f4be87c Author: Michael Meissner Date: Wed Apr 30 13:59:03 2025 -0400 Add ChangeLog.sha and update REVISION. 2025-04-30 Michael Meissner gcc/ * ChangeLog.sha: New file for branch. * REVISION: Update. Diff: --- gcc/ChangeLog.sha | 5 + gcc/REVISION | 2 +- 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog.sha b/gcc/ChangeLog.sha new file mode 100644 index ..a7e0cdc469a7 --- /dev/null +++ b/gcc/ChangeLog.sha @@ -0,0 +1,5 @@ + Branch work204-sha, baseline + +2025-04-30 Michael Meissner + + Clone branch diff --git a/gcc/REVISION b/gcc/REVISION index d4f18d737afd..4d2f7047958b 100644 --- a/gcc/REVISION +++ b/gcc/REVISION @@ -1 +1 @@ -work204 branch +work204-sha branch
[gcc] Created branch 'meissner/heads/work204-test' in namespace 'refs/users'
The branch 'meissner/heads/work204-test' was created in namespace 'refs/users' pointing to: 3a638f382320... Add ChangeLog.meissner and REVISION.
[gcc(refs/users/meissner/heads/work204-paddis)] Add ChangeLog.paddis and update REVISION.
https://gcc.gnu.org/g:30f6d9eff6efb9249e45c9c35cc2b8e3a78603e0 commit 30f6d9eff6efb9249e45c9c35cc2b8e3a78603e0 Author: Michael Meissner Date: Wed Apr 30 14:01:37 2025 -0400 Add ChangeLog.paddis and update REVISION. 2025-04-30 Michael Meissner gcc/ * ChangeLog.paddis: New file for branch. * REVISION: Update. Diff: --- gcc/ChangeLog.paddis | 5 + gcc/REVISION | 2 +- 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog.paddis b/gcc/ChangeLog.paddis new file mode 100644 index ..41c06f7e5c35 --- /dev/null +++ b/gcc/ChangeLog.paddis @@ -0,0 +1,5 @@ + Branch work204-paddis, baseline + +2025-04-30 Michael Meissner + + Clone branch diff --git a/gcc/REVISION b/gcc/REVISION index d4f18d737afd..ccc03cd9b8f4 100644 --- a/gcc/REVISION +++ b/gcc/REVISION @@ -1 +1 @@ -work204 branch +work204-paddis branch
[gcc] Created branch 'meissner/heads/work204-orig' in namespace 'refs/users'
The branch 'meissner/heads/work204-orig' was created in namespace 'refs/users' pointing to: 3584aab37f54... testsuite: Force -mcmodel=small for gcc.target/aarch64/pr11
[gcc(refs/users/meissner/heads/work204-orig)] Add REVISION.
https://gcc.gnu.org/g:36a93a66f9ade1e8bcae2817bbc69faa0f93e951 commit 36a93a66f9ade1e8bcae2817bbc69faa0f93e951 Author: Michael Meissner Date: Wed Apr 30 14:02:36 2025 -0400 Add REVISION. 2025-04-30 Michael Meissner gcc/ * REVISION: New file for branch. Diff: --- gcc/REVISION | 1 + 1 file changed, 1 insertion(+) diff --git a/gcc/REVISION b/gcc/REVISION new file mode 100644 index ..1988627ad908 --- /dev/null +++ b/gcc/REVISION @@ -0,0 +1 @@ +work204-orig branch
[gcc(refs/users/meissner/heads/work204)] Change TARGET_FPRND to TARGET_POWER5X.
https://gcc.gnu.org/g:dc94b44f4d965b95f337e575a047c3319cb6d8e6
commit dc94b44f4d965b95f337e575a047c3319cb6d8e6
Author: Michael Meissner
Date: Wed Apr 30 15:10:02 2025 -0400
Change TARGET_FPRND to TARGET_POWER5X.
This patch changes TARGET_POWER5X to TARGET_POWER5. The -mfprnd switch is
not
being changed, just the name of the macros used to determine if the PowerPC
processor supports ISA 2.4 (Power5x).
2025-04-30 Michael Meissner
gcc/
* gcc/config/rs6000/rs6000.cc (rs6000_option_override_internal):
Change TARGET_FPRND to TARGET_POWER5X.
* gcc/config/rs6000/rs6000.h (TARGET_POWERP5X): New macro.
* gcc/config/rs6000/rs6000.md (fmod3): Change TARGET_FPRND to
TARGET_POWER5X.
(remainder3): Likewise.
(fctiwuz_): Likewise.
(ceil2): Likewise.
(floor2): Likewise.
(round2): Likewise.
Diff:
---
gcc/config/rs6000/rs6000.cc | 4 ++--
gcc/config/rs6000/rs6000.h | 1 +
gcc/config/rs6000/rs6000.md | 14 +++---
3 files changed, 10 insertions(+), 9 deletions(-)
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 3328b7ed5cd2..f299223967bb 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -3924,7 +3924,7 @@ rs6000_option_override_internal (bool global_init_p)
rs6000_isa_flags |= (ISA_2_5_MASKS_SERVER & ~ignore_masks);
else if (TARGET_CMPB)
rs6000_isa_flags |= (ISA_2_5_MASKS_EMBEDDED & ~ignore_masks);
- else if (TARGET_FPRND)
+ else if (TARGET_POWER5X)
rs6000_isa_flags |= (ISA_2_4_MASKS & ~ignore_masks);
else if (TARGET_POWER5)
rs6000_isa_flags |= (ISA_2_2_MASKS & ~ignore_masks);
@@ -3951,7 +3951,7 @@ rs6000_option_override_internal (bool global_init_p)
rs6000_isa_flags &= ~OPTION_MASK_CRYPTO;
}
- if (!TARGET_FPRND && TARGET_VSX)
+ if (!TARGET_POWER5X && TARGET_VSX)
{
if (rs6000_isa_flags_explicit & OPTION_MASK_FPRND)
/* TARGET_VSX = 1 implies Power 7 and newer */
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index d9a0ffe9f5b2..3794e3c0658d 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -501,6 +501,7 @@ extern int rs6000_vector_align[];
/* Convert ISA bits like POPCNTB to PowerPC processors like POWER5. */
#define TARGET_POWER5 TARGET_POPCNTB
+#define TARGET_POWER5X TARGET_FPRND
/* In switching from using target_flags to using rs6000_isa_flags, the options
machinery creates OPTION_MASK_ instead of MASK_. The MASK_
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index c5bd273be8b3..045ce22a03c8 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -5171,7 +5171,7 @@
(use (match_operand:SFDF 1 "gpc_reg_operand"))
(use (match_operand:SFDF 2 "gpc_reg_operand"))]
"TARGET_HARD_FLOAT
- && TARGET_FPRND
+ && TARGET_POWER5X
&& flag_unsafe_math_optimizations"
{
rtx div = gen_reg_rtx (mode);
@@ -5189,7 +5189,7 @@
(use (match_operand:SFDF 1 "gpc_reg_operand"))
(use (match_operand:SFDF 2 "gpc_reg_operand"))]
"TARGET_HARD_FLOAT
- && TARGET_FPRND
+ && TARGET_POWER5X
&& flag_unsafe_math_optimizations"
{
rtx div = gen_reg_rtx (mode);
@@ -6689,7 +6689,7 @@
(define_insn "*friz"
[(set (match_operand:DF 0 "gpc_reg_operand" "=d,wa")
(float:DF (fix:DI (match_operand:DF 1 "gpc_reg_operand" "d,wa"]
- "TARGET_HARD_FLOAT && TARGET_FPRND
+ "TARGET_HARD_FLOAT && TARGET_POWER5X
&& flag_unsafe_math_optimizations && !flag_trapping_math && TARGET_FRIZ"
"@
friz %0,%1
@@ -6817,7 +6817,7 @@
[(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa")
(unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "d,wa")]
UNSPEC_FRIZ))]
- "TARGET_HARD_FLOAT && TARGET_FPRND"
+ "TARGET_HARD_FLOAT && TARGET_POWER5X"
"@
friz %0,%1
xsrdpiz %x0,%x1"
@@ -6827,7 +6827,7 @@
[(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa")
(unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "d,wa")]
UNSPEC_FRIP))]
- "TARGET_HARD_FLOAT && TARGET_FPRND"
+ "TARGET_HARD_FLOAT && TARGET_POWER5X"
"@
frip %0,%1
xsrdpip %x0,%x1"
@@ -6837,7 +6837,7 @@
[(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa")
(unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "d,wa")]
UNSPEC_FRIM))]
- "TARGET_HARD_FLOAT && TARGET_FPRND"
+ "TARGET_HARD_FLOAT && TARGET_POWER5X"
"@
frim %0,%1
xsrdpim %x0,%x1"
@@ -6848,7 +6848,7 @@
[(set (match_operand:SFDF 0 "gpc_reg_operand" "=")
(unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "")]
UNSPEC_FRIN))]
- "TARGET_HARD_FLOAT && TARGET_FPRND"
+ "TARGET_HARD_FLOAT && TARGET_POWER5X"
"frin %0,%1"
[(set_attr "type" "fp")])
[gcc(refs/users/meissner/heads/work204)] Change TARGET_MODULO to TARGET_POWER9.
https://gcc.gnu.org/g:e0ceb1493e96a318dfb52777ae722eb778d94ec9
commit e0ceb1493e96a318dfb52777ae722eb778d94ec9
Author: Michael Meissner
Date: Wed Apr 30 15:11:48 2025 -0400
Change TARGET_MODULO to TARGET_POWER9.
This patch changes TARGET_MODULO to TARGET_POWER9. The -mmodulo switch is
not
being changed, just the name of the macros used to determine if the PowerPC
processor supports ISA 3.0 (Power9).
2025-04-30 Michael Meissner
gcc/
* gcc/config/rs6000/rs6000-builtin.cc (rs6000_builtin_is_supported):
Change TARGET_MODULO to TARGET_POWER9.
* gcc/config/rs6000/rs6000.cc (rs6000_option_override_internal):
Likewise.
* gcc/config/rs6000/rs6000.h (TARGET_CTZ): Likewise.
(TARGET_EXTSWSLI): Likewise.
(TARGET_MADDLD): Likewise.
(TARGET_POWER9): New macro.
* gcc/config/rs6000/rs6000.md (enabled attribute): Change
TARGET_MODULO
to TARGET_POWER9.
(mod3): Likewise.
(umod3): Likewise.
(divide/modulo peephole2): Likewise.
Diff:
---
gcc/config/rs6000/rs6000-builtin.cc | 4 ++--
gcc/config/rs6000/rs6000.cc | 4 ++--
gcc/config/rs6000/rs6000.h | 7 ---
gcc/config/rs6000/rs6000.md | 14 +++---
4 files changed, 15 insertions(+), 14 deletions(-)
diff --git a/gcc/config/rs6000/rs6000-builtin.cc
b/gcc/config/rs6000/rs6000-builtin.cc
index 2366b2aee00a..d8ff7cf32dfd 100644
--- a/gcc/config/rs6000/rs6000-builtin.cc
+++ b/gcc/config/rs6000/rs6000-builtin.cc
@@ -169,9 +169,9 @@ rs6000_builtin_is_supported (enum rs6000_gen_builtins
fncode)
case ENB_P8V:
return TARGET_P8_VECTOR;
case ENB_P9:
- return TARGET_MODULO;
+ return TARGET_POWER9;
case ENB_P9_64:
- return TARGET_MODULO && TARGET_POWERPC64;
+ return TARGET_POWER9 && TARGET_POWERPC64;
case ENB_P9V:
return TARGET_P9_VECTOR;
case ENB_P10:
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 163e8ddebf55..fc5b8f407a26 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -3888,7 +3888,7 @@ rs6000_option_override_internal (bool global_init_p)
/* For the newer switches (vsx, dfp, etc.) set some of the older options,
unless the user explicitly used the -mno- to disable the code. */
- if (TARGET_P9_VECTOR || TARGET_MODULO || TARGET_P9_MISC)
+ if (TARGET_P9_VECTOR || TARGET_POWER9 || TARGET_P9_MISC)
rs6000_isa_flags |= (ISA_3_0_MASKS_SERVER & ~ignore_masks);
else if (TARGET_P9_MINMAX)
{
@@ -22377,7 +22377,7 @@ rs6000_rtx_costs (rtx x, machine_mode mode, int
outer_code,
*total = rs6000_cost->divsi;
}
/* Add in shift and subtract for MOD unless we have a mod instruction. */
- if ((!TARGET_MODULO
+ if ((!TARGET_POWER9
|| (RS6000_DISABLE_SCALAR_MODULO && SCALAR_INT_MODE_P (mode)))
&& (code == MOD || code == UMOD))
*total += COSTS_N_INSNS (2);
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index f1da5d31441a..c2f1910b0ea2 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -463,9 +463,9 @@ extern int rs6000_vector_align[];
#define TARGET_FCTIWUZ TARGET_POWER7
/* Only powerpc64 and powerpc476 support fctid. */
#define TARGET_FCTID (TARGET_POWERPC64 || rs6000_cpu == PROCESSOR_PPC476)
-#define TARGET_CTZ TARGET_MODULO
-#define TARGET_EXTSWSLI(TARGET_MODULO && TARGET_POWERPC64)
-#define TARGET_MADDLD TARGET_MODULO
+#define TARGET_CTZ TARGET_POWER9
+#define TARGET_EXTSWSLI(TARGET_POWER9 && TARGET_POWERPC64)
+#define TARGET_MADDLD TARGET_POWER9
/* TARGET_DIRECT_MOVE is redundant to TARGET_P8_VECTOR, so alias it to that.
*/
#define TARGET_DIRECT_MOVE TARGET_P8_VECTOR
@@ -504,6 +504,7 @@ extern int rs6000_vector_align[];
#define TARGET_POWER5X TARGET_FPRND
#define TARGET_POWER6 TARGET_CMPB
#define TARGET_POWER7 TARGET_POPCNTD
+#define TARGET_POWER9 TARGET_MODULO
/* In switching from using target_flags to using rs6000_isa_flags, the options
machinery creates OPTION_MASK_ instead of MASK_. The MASK_
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 87ec37a9f8e4..db1b6c2d1164 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -403,7 +403,7 @@
(const_int 1)
(and (eq_attr "isa" "p9")
- (match_test "TARGET_MODULO"))
+ (match_test "TARGET_POWER9"))
(const_int 1)
(and (eq_attr "isa" "p9v")
@@ -3457,7 +3457,7 @@
|| INTVAL (operands[2]) <= 0
|| (i = exact_log2 (INTVAL (operands[2]))) < 0)
{
- if (!TARGET_MODULO)
+ if (!TARGET_POWER9)
FAIL;
operands[2] = force_reg (mode, operands[2]);
@@ -3491,7 +3491,7 @@
[(set (match_operand:GPR 0 "gpc_reg_operand" "=&r,r")
(mod:GPR (match_oper
[gcc(refs/users/meissner/heads/work204)] Change TARGET_CMPB to TARGET_POWER6.
https://gcc.gnu.org/g:fbdcdf4e3ad9be93668a422763f4a2e9f70ca4fb
commit fbdcdf4e3ad9be93668a422763f4a2e9f70ca4fb
Author: Michael Meissner
Date: Wed Apr 30 15:10:22 2025 -0400
Change TARGET_CMPB to TARGET_POWER6.
This patch changes TARGET_CMPB to TARGET_POWER6. The -mcmpb switch is not
being
changed, just the name of the macros used to determine if the PowerPC
processor
supports ISA 2.5 (Power6).
2025-04-30 Michael Meissner
gcc/
* gcc/config/rs6000/rs6000-builtin.cc (rs6000_builtin_is_supported):
Change TARGET_CMPB to TARGET_POWER6.
* gcc/config/rs6000/rs6000.cc (rs6000_option_override_internal):
Likewise.
(rs6000_rtx_costs): Likewise.
(rs6000_emit_parity): Likewise.
* gcc/config/rs6000/rs6000.h (TARGET_FCFID): Likewise.
(TARGET_LFIWAX): Likewise.
(TARGET_POWER6): New macro.
(TARGET_EXTRA_BUILTINS): Change TARGET_CMPB to TARGET_POWER6.
* gcc/config/rs6000/rs6000.md (enabled attribute): Likewise.
(parity2_cmp): Likewise.
(cmpb3): Likewise.
(copysign3): Likewise.
(copysign3_fcpsgn): Likewise.
(cmpstrnsi): Likewise.
(cmpstrsi): Likewise.
Diff:
---
gcc/config/rs6000/rs6000-builtin.cc | 4 ++--
gcc/config/rs6000/rs6000.cc | 8
gcc/config/rs6000/rs6000.h | 7 ---
gcc/config/rs6000/rs6000.md | 16
4 files changed, 18 insertions(+), 17 deletions(-)
diff --git a/gcc/config/rs6000/rs6000-builtin.cc
b/gcc/config/rs6000/rs6000-builtin.cc
index 4ed2bc1ca89e..dbb8520ab039 100644
--- a/gcc/config/rs6000/rs6000-builtin.cc
+++ b/gcc/config/rs6000/rs6000-builtin.cc
@@ -157,9 +157,9 @@ rs6000_builtin_is_supported (enum rs6000_gen_builtins
fncode)
case ENB_P5:
return TARGET_POWER5;
case ENB_P6:
- return TARGET_CMPB;
+ return TARGET_POWER6;
case ENB_P6_64:
- return TARGET_CMPB && TARGET_POWERPC64;
+ return TARGET_POWER6 && TARGET_POWERPC64;
case ENB_P7:
return TARGET_POPCNTD;
case ENB_P7_64:
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index f299223967bb..baef2af3e57b 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -3922,7 +3922,7 @@ rs6000_option_override_internal (bool global_init_p)
rs6000_isa_flags |= (ISA_2_6_MASKS_EMBEDDED & ~ignore_masks);
else if (TARGET_DFP)
rs6000_isa_flags |= (ISA_2_5_MASKS_SERVER & ~ignore_masks);
- else if (TARGET_CMPB)
+ else if (TARGET_POWER6)
rs6000_isa_flags |= (ISA_2_5_MASKS_EMBEDDED & ~ignore_masks);
else if (TARGET_POWER5X)
rs6000_isa_flags |= (ISA_2_4_MASKS & ~ignore_masks);
@@ -4797,7 +4797,7 @@ rs6000_option_override_internal (bool global_init_p)
DERAT mispredict penalty. However the LVE and STVE altivec instructions
need indexed accesses and the type used is the scalar type of the element
being loaded or stored. */
-TARGET_AVOID_XFORM = (rs6000_tune == PROCESSOR_POWER6 && TARGET_CMPB
+TARGET_AVOID_XFORM = (rs6000_tune == PROCESSOR_POWER6 && TARGET_POWER6
&& !TARGET_ALTIVEC);
/* Set the -mrecip options. */
@@ -22396,7 +22396,7 @@ rs6000_rtx_costs (rtx x, machine_mode mode, int
outer_code,
return false;
case PARITY:
- *total = COSTS_N_INSNS (TARGET_CMPB ? 2 : 6);
+ *total = COSTS_N_INSNS (TARGET_POWER6 ? 2 : 6);
return false;
case NOT:
@@ -23223,7 +23223,7 @@ rs6000_emit_parity (rtx dst, rtx src)
tmp = gen_reg_rtx (mode);
/* Use the PPC ISA 2.05 prtyw/prtyd instruction if we can. */
- if (TARGET_CMPB)
+ if (TARGET_POWER6)
{
if (mode == SImode)
{
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 3794e3c0658d..5b8cf054f98a 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -449,12 +449,12 @@ extern int rs6000_vector_align[];
#define TARGET_FCFID (TARGET_POWERPC64 \
|| TARGET_PPC_GPOPT/* 970/power4 */\
|| TARGET_POWER5 /* ISA 2.02 */ \
-|| TARGET_CMPB /* ISA 2.05 */ \
+|| TARGET_POWER6 /* ISA 2.05 */ \
|| TARGET_POPCNTD) /* ISA 2.06 */
#define TARGET_FCTIDZ TARGET_FCFID
#define TARGET_STFIWX TARGET_PPC_GFXOPT
-#define TARGET_LFIWAX TARGET_CMPB
+#define TARGET_LFIWAX TARGET_POWER6
#define TARGET_LFIWZX TARGET_POPCNTD
#define TARGET_FCFIDS TARGET_POPCNTD
#define TARGET_FCFIDU TARGET_POPCNTD
@@ -502,6 +502,7 @@ extern int rs6000_vector_align[];
/* Convert ISA bits like POPCNTB to PowerPC processors like POWER5. */
#define TARGET_POWER5 TARGET_POPCNTB
#define TARGET_POWER5X TARGET_FPRND
+#define TARGET_POWER6
[gcc(refs/users/meissner/heads/work204)] Change TARGET_POPCNTB to TARGET_POWER5.
https://gcc.gnu.org/g:577e4eeccaa922d171475dabc72b5b536c8e9450 commit 577e4eeccaa922d171475dabc72b5b536c8e9450 Author: Michael Meissner Date: Wed Apr 30 15:08:35 2025 -0400 Change TARGET_POPCNTB to TARGET_POWER5. This patch changes TARGET_POPCNTB to TARGET_POWER5. The -mpopcntb switch is not being changed in this patch, just the name of the macros used to determine if the PowerPC processor supports ISA 2.2 (Power5). 2025-04-30 Michael Meissner gcc/ * gcc/config/rs6000/rs6000-builtin.cc (rs6000_builtin_is_supported): Change TARGET_POPCNTB to TARGET_POWER5. * gcc/config/rs6000/rs6000.cc (rs6000_option_override_internal): Likewise. * gcc/config/rs6000/rs6000.h (TARGET_FCFID): Likewise. (TARGET_POWER5): New macro. (TARGET_EXTRA_BUILTINS): Change TARGET_POPCNTB to TARGET_POWER5. (TARGET_FRE): Likewise. (TARGET_FRSQRTES): Likewise. * gcc/config/rs6000/rs6000.md (enabled attribute): Likewise. Diff: --- gcc/config/rs6000/rs6000-builtin.cc | 2 +- gcc/config/rs6000/rs6000.cc | 2 +- gcc/config/rs6000/rs6000.h | 11 +++ gcc/config/rs6000/rs6000.md | 2 +- 4 files changed, 10 insertions(+), 7 deletions(-) diff --git a/gcc/config/rs6000/rs6000-builtin.cc b/gcc/config/rs6000/rs6000-builtin.cc index 111802381acb..4ed2bc1ca89e 100644 --- a/gcc/config/rs6000/rs6000-builtin.cc +++ b/gcc/config/rs6000/rs6000-builtin.cc @@ -155,7 +155,7 @@ rs6000_builtin_is_supported (enum rs6000_gen_builtins fncode) case ENB_ALWAYS: return true; case ENB_P5: - return TARGET_POPCNTB; + return TARGET_POWER5; case ENB_P6: return TARGET_CMPB; case ENB_P6_64: diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index 12dbde2bc630..3328b7ed5cd2 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -3926,7 +3926,7 @@ rs6000_option_override_internal (bool global_init_p) rs6000_isa_flags |= (ISA_2_5_MASKS_EMBEDDED & ~ignore_masks); else if (TARGET_FPRND) rs6000_isa_flags |= (ISA_2_4_MASKS & ~ignore_masks); - else if (TARGET_POPCNTB) + else if (TARGET_POWER5) rs6000_isa_flags |= (ISA_2_2_MASKS & ~ignore_masks); else if (TARGET_ALTIVEC) rs6000_isa_flags |= (OPTION_MASK_PPC_GFXOPT & ~ignore_masks); diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index db6112a09e11..d9a0ffe9f5b2 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -448,7 +448,7 @@ extern int rs6000_vector_align[]; Enable 32-bit fcfid's on any of the switches for newer ISA machines. */ #define TARGET_FCFID (TARGET_POWERPC64 \ || TARGET_PPC_GPOPT/* 970/power4 */\ -|| TARGET_POPCNTB /* ISA 2.02 */ \ +|| TARGET_POWER5 /* ISA 2.02 */ \ || TARGET_CMPB /* ISA 2.05 */ \ || TARGET_POPCNTD) /* ISA 2.06 */ @@ -499,6 +499,9 @@ extern int rs6000_vector_align[]; #define TARGET_MINMAX (TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT \ && (TARGET_P9_MINMAX || !flag_trapping_math)) +/* Convert ISA bits like POPCNTB to PowerPC processors like POWER5. */ +#define TARGET_POWER5 TARGET_POPCNTB + /* In switching from using target_flags to using rs6000_isa_flags, the options machinery creates OPTION_MASK_ instead of MASK_. The MASK_ options that have not yet been replaced by their OPTION_MASK_ @@ -525,7 +528,7 @@ extern int rs6000_vector_align[]; #define TARGET_EXTRA_BUILTINS (TARGET_POWERPC64\ || TARGET_PPC_GPOPT /* 970/power4 */\ -|| TARGET_POPCNTB /* ISA 2.02 */ \ +|| TARGET_POWER5/* ISA 2.02 */ \ || TARGET_CMPB /* ISA 2.05 */ \ || TARGET_POPCNTD /* ISA 2.06 */ \ || TARGET_ALTIVEC \ @@ -541,9 +544,9 @@ extern int rs6000_vector_align[]; #define TARGET_FRES(TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT) #define TARGET_FRE (TARGET_HARD_FLOAT \ -&& (TARGET_POPCNTB || VECTOR_UNIT_VSX_P (DFmode))) +&& (TARGET_POWER5 || VECTOR_UNIT_VSX_P (DFmode))) -#define TARGET_FRSQRTES(TARGET_HARD_FLOAT && TARGET_POPCNTB \ +#define TARGET_FRSQRTES(TARGET_HARD_FLOAT && TARGET_POWER5 \ && TARGET_PPC_GFXOPT) #define TARGET_FRSQRTE (TARGET_HARD_FLOAT \ diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 9c718ca2a226..c5bd273be8b3 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs
[gcc(refs/users/meissner/heads/work204)] Add support for -mcpu=future
https://gcc.gnu.org/g:50c706a79bccc06df78504016d4e72ce32e08296 commit 50c706a79bccc06df78504016d4e72ce32e08296 Author: Michael Meissner Date: Wed Apr 30 15:22:58 2025 -0400 Add support for -mcpu=future This patch adds the support that can be used in developing GCC support for future PowerPC processors. 2025-04-30 Michael Meissner * config.gcc (powerpc*-*-*): Add support for --with-cpu=future. * config/rs6000/aix71.h (ASM_CPU_SPEC): Add support for -mcpu=future. * config/rs6000/aix72.h (ASM_CPU_SPEC): Likewise. * config/rs6000/aix73.h (ASM_CPU_SPEC): Likewise. * config/rs6000/driver-rs6000.cc (asm_names): Likewise. * config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): If -mcpu=future, define _ARCH_FUTURE. * config/rs6000/rs6000-cpus.def (FUTURE_MASKS_SERVER): New macro. (POWERPC_MASKS): Add OPTION_MASK_FUTURE. (future cpu): Define. * config/rs6000/rs6000-opts.h (enum processor_type): Add PROCESSOR_FUTURE. * config/rs6000/rs6000-tables.opt: Regenerate. * config/rs6000/rs6000.cc (power10_cost): Update comment. (get_arch_flags): Add support for future processor. (rs6000_option_override_internal): Likewise. (rs6000_machine_from_flags): Likewise. (rs6000_reassociation_width): Likewise. (rs6000_adjust_cost): Likewise. (rs6000_issue_rate): Likewise. (rs6000_sched_reorder): Likewise. (rs6000_sched_reorder2): Likewise. (rs6000_register_move_cost): Likewise. (rs6000_opt_masks): Add -mfuture. * config/rs6000/rs6000.h (ASM_CPU_SPEC): Likewise. * config/rs6000/rs6000.md (cpu attribute): Likewise. * config/rs6000/rs6000.opt (-mfuture): New internal option. Diff: --- gcc/config/rs6000/power10.md | 145 ++- 1 file changed, 73 insertions(+), 72 deletions(-) diff --git a/gcc/config/rs6000/power10.md b/gcc/config/rs6000/power10.md index fd31b16b3314..bdd7e58145ba 100644 --- a/gcc/config/rs6000/power10.md +++ b/gcc/config/rs6000/power10.md @@ -1,4 +1,5 @@ -;; Scheduling description for the IBM Power10 and Power11 processors. +;; Scheduling description for the IBM Power10, Power11, and +;; potential future processors. ;; Copyright (C) 2020-2025 Free Software Foundation, Inc. ;; ;; Contributed by Pat Haugen (pthau...@us.ibm.com). @@ -97,12 +98,12 @@ (eq_attr "update" "no") (eq_attr "size" "!128") (eq_attr "prefixed" "no") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_any_power10,LU_power10") (define_insn_reservation "power10-fused-load" 4 (and (eq_attr "type" "fused_load_cmpi,fused_addis_load,fused_load_load") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_even_power10,LU_power10") (define_insn_reservation "power10-prefixed-load" 4 @@ -110,13 +111,13 @@ (eq_attr "update" "no") (eq_attr "size" "!128") (eq_attr "prefixed" "yes") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_even_power10,LU_power10") (define_insn_reservation "power10-load-update" 4 (and (eq_attr "type" "load") (eq_attr "update" "yes") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_even_power10,LU_power10+SXU_power10") (define_insn_reservation "power10-fpload-double" 4 @@ -124,7 +125,7 @@ (eq_attr "update" "no") (eq_attr "size" "64") (eq_attr "prefixed" "no") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_any_power10,LU_power10") (define_insn_reservation "power10-prefixed-fpload-double" 4 @@ -132,14 +133,14 @@ (eq_attr "update" "no") (eq_attr "size" "64") (eq_attr "prefixed" "yes") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_even_power10,LU_power10") (define_insn_reservation "power10-fpload-update-double" 4 (and (eq_attr "type" "fpload") (eq_attr "update" "yes") (eq_attr "size" "64") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_even_power10,LU_power10+SXU_power10") ; SFmode loads are cracked and have additional 3 cycles over DFmode @@ -148,27 +149,27 @@ (and (eq_attr "type" "fpload") (eq_attr "update" "no") (eq_attr "size" "32") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_even_power10,LU_power10") (define_insn_reservation "power10-fpload-update-single" 7 (and (eq_attr "type" "fpload") (eq_attr "update" "yes") (eq_attr "size" "32") - (eq_att
[gcc(refs/users/mikael/heads/refactor_descriptor_v05)] Correction régression pr61775
https://gcc.gnu.org/g:72dab6026ad6b0f71b4f591251ad12a423b1a8fc
commit 72dab6026ad6b0f71b4f591251ad12a423b1a8fc
Author: Mikael Morin
Date: Wed Apr 30 19:01:47 2025 +0200
Correction régression pr61775
Diff:
---
gcc/fortran/trans-array.cc | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/gcc/fortran/trans-array.cc b/gcc/fortran/trans-array.cc
index 861b689704b0..b3c5aff9d303 100644
--- a/gcc/fortran/trans-array.cc
+++ b/gcc/fortran/trans-array.cc
@@ -3608,7 +3608,8 @@ void
gfc_conv_tmp_array_ref (gfc_se * se)
{
se->string_length = se->ss->info->string_length;
- bool tmp_array = !gfc_expr_attr (se->ss->info->expr).pointer;
+ bool tmp_array = !(se->ss->info->expr
+&& gfc_expr_attr (se->ss->info->expr).pointer);
gfc_conv_scalarized_array_ref (se, NULL, tmp_array);
gfc_advance_se_ss_chain (se);
}
[gcc] Created branch 'ibm/heads/peter-15-branch' in namespace 'refs/vendors'
The branch 'ibm/heads/peter-15-branch' was created in namespace 'refs/vendors' pointing to: c9d4d3ba15c5... testsuite: Force -mcmodel=small for gcc.target/aarch64/pr11
[gcc(refs/users/meissner/heads/work204)] Use architecture flags for defining _ARCH_PWR macros.
https://gcc.gnu.org/g:e3fed9c915f08f0db45a7ffa4630f8a800f27e73
commit e3fed9c915f08f0db45a7ffa4630f8a800f27e73
Author: Michael Meissner
Date: Wed Apr 30 15:33:01 2025 -0400
Use architecture flags for defining _ARCH_PWR macros.
For the newer architectures, this patch changes GCC to define the
_ARCH_PWR
macros using the new architecture flags instead of relying on isa options
like
-mpower10.
The -mpower8-internal, -mpower10, -mpower11, and -mfuture options were
removed.
The -mpower11 and -mfuture options were removed completely, since they were
just
added in GCC 15. The other two options were marked as WarnRemoved, and the
various ISA bits were removed.
TARGET_POWER8, TARGET_POWER10, TARGET_POWER11, and TARGET_FUTURE were
re-defined
to use the architeture bits instead of the ISA bits.
There are other internal isa bits that aren't removed with this patch
because
the built-in function support uses those bits.
I have built both big endian and little endian bootstrap compilers and there
were no regressions.
Can I install this patch on the GCC 16 trunk?
2025-04-30 Michael Meissner
gcc/
* config/rs6000/rs6000-c.cc (rs6000_target_modify_macros) Add
support to
use architecture flags instead of ISA flags for setting most of the
_ARCH_PWR* macros.
(rs6000_cpu_cpp_builtins): Update rs6000_target_modify_macros call.
* config/rs6000/rs6000-cpus.def (ISA_2_7_MASKS_SERVER): Remove
OPTION_MASK_POWER8.
(ISA_3_1_MASKS_SERVER): Remove OPTION_MASK_POWER10.
(POWER11_MASKS_SERVER): Remove OPTION_MASK_POWER11.
(FUTURE_MASKS_SERVER): Remove OPTION_MASK_FUTURE.
(POWERPC_MASKS): Remove OPTION_MASK_POWER8, OPTION_MASK_POWER10,
OPTION_MASK_POWER11, and OPTION_MASK_FUTURE.
* config/rs6000/rs6000-protos.h (rs6000_target_modify_macros):
Update
declaration.
(rs6000_target_modify_macros_ptr): Likewise.
* config/rs6000/rs6000.cc (rs6000_target_modify_macros_ptr):
Likewise.
(rs6000_option_override_internal): Use architecture flags instead
of ISA
flags.
(rs6000_opt_masks): Remove -mpower10, -mpower11, and -mfuture which
are
no longer in the ISA flags.
(rs6000_pragma_target_parse): Use architecture flags as well as ISA
flags.
* config/rs6000/rs6000.h (TARGET_POWER5): Redefine to use
architecture
flags.
(TARGET_POWER5X): Likewise.
(TARGET_POWER6): Likewise.
(TARGET_POWER7): Likewise.
(TARGET_POWER8): Likewise.
(TARGET_POWER9): Likewise.
(TARGET_POWER10): New macro.
(TARGET_POWER11): Likewise.
(TARGET_FUTURE): Likewise.
* config/rs6000/rs6000.opt (-mpower8-internal): Remove ISA flag
bits.
(-mpower10): Likewise.
(-mpower11): Likewise.
(-mfuture): Likewise.
Diff:
---
gcc/config/rs6000/rs6000-c.cc | 29 -
gcc/config/rs6000/rs6000-cpus.def | 10 +-
gcc/config/rs6000/rs6000-protos.h | 5 +++--
gcc/config/rs6000/rs6000.cc | 22 --
gcc/config/rs6000/rs6000.h| 19 +--
gcc/config/rs6000/rs6000.opt | 17 ++---
6 files changed, 47 insertions(+), 55 deletions(-)
diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc
index 6757a2477ad1..6d6838735b33 100644
--- a/gcc/config/rs6000/rs6000-c.cc
+++ b/gcc/config/rs6000/rs6000-c.cc
@@ -338,7 +338,8 @@ rs6000_define_or_undefine_macro (bool define_p, const char
*name)
#pragma GCC target, we need to adjust the macros dynamically. */
void
-rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags)
+rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags,
+HOST_WIDE_INT arch_flags)
{
if (TARGET_DEBUG_BUILTIN || TARGET_DEBUG_TARGET)
fprintf (stderr,
@@ -411,7 +412,7 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT
flags)
summary of the flags associated with particular cpu
definitions. */
- /* rs6000_isa_flags based options. */
+ /* rs6000_isa_flags and rs6000_arch_flags based options. */
rs6000_define_or_undefine_macro (define_p, "_ARCH_PPC");
if ((flags & OPTION_MASK_PPC_GPOPT) != 0)
rs6000_define_or_undefine_macro (define_p, "_ARCH_PPCSQ");
@@ -419,25 +420,27 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT
flags)
rs6000_define_or_undefine_macro (define_p, "_ARCH_PPCGR");
if ((flags & OPTION_MASK_POWERPC64) != 0)
rs6000_define_or_undefine_macro (define_p, "_ARCH_PPC64");
- if ((flags & OPTION_MASK_MFCRF) != 0)
+ if ((flags & OPTION_MASK_POWERPC64) != 0)
+rs6000_define_or_undefine_macro (define_p, "_ARCH_PPC64"
[gcc(refs/users/meissner/heads/work204-bugs)] Add ChangeLog.bugs and update REVISION.
https://gcc.gnu.org/g:7e9a1931a683e85afde13193fc21a13528483dce commit 7e9a1931a683e85afde13193fc21a13528483dce Author: Michael Meissner Date: Wed Apr 30 13:55:30 2025 -0400 Add ChangeLog.bugs and update REVISION. 2025-04-30 Michael Meissner gcc/ * ChangeLog.bugs: New file for branch. * REVISION: Update. Diff: --- gcc/ChangeLog.bugs | 5 + gcc/REVISION | 2 +- 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog.bugs b/gcc/ChangeLog.bugs new file mode 100644 index ..01677977864f --- /dev/null +++ b/gcc/ChangeLog.bugs @@ -0,0 +1,5 @@ + Branch work204-bugs, baseline + +2025-04-30 Michael Meissner + + Clone branch diff --git a/gcc/REVISION b/gcc/REVISION index d4f18d737afd..0e2bd7e09059 100644 --- a/gcc/REVISION +++ b/gcc/REVISION @@ -1 +1 @@ -work204 branch +work204-bugs branch
[gcc/meissner/heads/work204-bugs] (16 commits) Merge commit 'refs/users/meissner/heads/work204-bugs' of gi
The branch 'meissner/heads/work204-bugs' was updated to point to: 734b285b41d9... Merge commit 'refs/users/meissner/heads/work204-bugs' of gi It previously pointed to: 508b531ea7de... Add ChangeLog.bugs and update REVISION. Diff: Summary of changes (added commits): --- 734b285... Merge commit 'refs/users/meissner/heads/work204-bugs' of gi 7e9a193... Add ChangeLog.bugs and update REVISION. baa1f20... Update ChangeLog.* (*) e3fed9c... Use architecture flags for defining _ARCH_PWR macros. (*) 2fc3592... Add rs6000 architecture masks. (*) cdecb01... Use vector pair load/store for memcpy with -mcpu=future (*) 5033551... Add -mcpu=future tests. (*) 9f2d754... Add -mcpu=future tuning support. (*) 268f13e... Add support for -mcpu=future (*) ef1deb7... Revert changes (*) 50c706a... Add support for -mcpu=future (*) e0ceb14... Change TARGET_MODULO to TARGET_POWER9. (*) 30bfb83... Change TARGET_POPCNTD to TARGET_POWER7. (*) fbdcdf4... Change TARGET_CMPB to TARGET_POWER6. (*) dc94b44... Change TARGET_FPRND to TARGET_POWER5X. (*) 577e4ee... Change TARGET_POPCNTB to TARGET_POWER5. (*) (*) This commit already exists in another branch. Because the reference `refs/users/meissner/heads/work204-bugs' matches your hooks.email-new-commits-only configuration, no separate email is sent for this commit.
[gcc(refs/users/meissner/heads/work204-bugs)] Merge commit 'refs/users/meissner/heads/work204-bugs' of git+ssh://gcc.gnu.org/git/gcc into me/work2
https://gcc.gnu.org/g:734b285b41d9e4512d5a53dc934f1e69b65df7e0 commit 734b285b41d9e4512d5a53dc934f1e69b65df7e0 Merge: 7e9a1931a683 508b531ea7de Author: Michael Meissner Date: Wed Apr 30 16:30:45 2025 -0400 Merge commit 'refs/users/meissner/heads/work204-bugs' of git+ssh://gcc.gnu.org/git/gcc into me/work204-bugs Diff:
[gcc r15-9602] AVR: target/119989 - Add missing clobbers to xload__libgcc.
https://gcc.gnu.org/g:e268cb27332a1c39a5fc8426ae368c9878f3f241
commit r15-9602-ge268cb27332a1c39a5fc8426ae368c9878f3f241
Author: Georg-Johann Lay
Date: Wed Apr 30 08:43:51 2025 +0200
AVR: target/119989 - Add missing clobbers to xload__libgcc.
libgcc's __xload_1...4 is clobbering Z (and also R21 is some cases),
but avr.md had clobbers of respective GPRs only up to reload.
Outcome was that code reading from the same __memx address twice
could be wrong. This patch adds respective clobbers.
Forward-port from 2025-04-30 r14-11703
PR target/119989
gcc/
* config/avr/avr.md (xload__libgcc): Clobber R21, Z.
gcc/testsuite/
* gcc.target/avr/torture/pr119989.h: New file.
* gcc.target/avr/torture/pr119989-memx-1.c: New test.
* gcc.target/avr/torture/pr119989-memx-2.c: New test.
* gcc.target/avr/torture/pr119989-memx-3.c: New test.
* gcc.target/avr/torture/pr119989-memx-4.c: New test.
* gcc.target/avr/torture/pr119989-flashx-1.c: New test.
* gcc.target/avr/torture/pr119989-flashx-2.c: New test.
* gcc.target/avr/torture/pr119989-flashx-3.c: New test.
* gcc.target/avr/torture/pr119989-flashx-4.c: New test.
(cherry picked from commit 1ca1c1fc3b58ae5e1d3db4f5a2014132fe69f82a)
Diff:
---
gcc/config/avr/avr.md | 6 +++-
.../gcc.target/avr/torture/pr119989-flashx-1.c | 7
.../gcc.target/avr/torture/pr119989-flashx-2.c | 7
.../gcc.target/avr/torture/pr119989-flashx-3.c | 7
.../gcc.target/avr/torture/pr119989-flashx-4.c | 7
.../gcc.target/avr/torture/pr119989-memx-1.c | 7
.../gcc.target/avr/torture/pr119989-memx-2.c | 7
.../gcc.target/avr/torture/pr119989-memx-3.c | 7
.../gcc.target/avr/torture/pr119989-memx-4.c | 7
gcc/testsuite/gcc.target/avr/torture/pr119989.h| 37 ++
10 files changed, 98 insertions(+), 1 deletion(-)
diff --git a/gcc/config/avr/avr.md b/gcc/config/avr/avr.md
index 1c4e44dcfe41..14b3e77ae506 100644
--- a/gcc/config/avr/avr.md
+++ b/gcc/config/avr/avr.md
@@ -716,8 +716,10 @@
|| avr_load_libgcc_insn_p (insn, ADDR_SPACE_FLASHX, true)"
"#"
"&& reload_completed"
- [(parallel [(set (reg:MOVMODE REG_22)
+ [(parallel [(set (reg:MOVMODE 22)
(match_dup 0))
+ (clobber (reg:QI 21))
+ (clobber (reg:HI REG_Z))
(clobber (reg:CC REG_CC))])]
{
operands[0] = SET_SRC (single_set (curr_insn));
@@ -727,6 +729,8 @@
[(set (reg:MOVMODE REG_22)
(mem:MOVMODE (lo_sum:PSI (reg:QI REG_21)
(reg:HI REG_Z
+ (clobber (reg:QI 21))
+ (clobber (reg:HI REG_Z))
(clobber (reg:CC REG_CC))]
"reload_completed
&& (avr_load_libgcc_insn_p (insn, ADDR_SPACE_MEMX, true)
diff --git a/gcc/testsuite/gcc.target/avr/torture/pr119989-flashx-1.c
b/gcc/testsuite/gcc.target/avr/torture/pr119989-flashx-1.c
new file mode 100644
index ..086d1eab0e24
--- /dev/null
+++ b/gcc/testsuite/gcc.target/avr/torture/pr119989-flashx-1.c
@@ -0,0 +1,7 @@
+/* { dg-do run { target { ! avr_tiny } } } */
+/* { dg-additional-options "-std=gnu99" } */
+
+typedef __UINT8_TYPE__ TYP;
+#define AS __flashx
+
+#include "pr119989.h"
diff --git a/gcc/testsuite/gcc.target/avr/torture/pr119989-flashx-2.c
b/gcc/testsuite/gcc.target/avr/torture/pr119989-flashx-2.c
new file mode 100644
index ..d053ab9c109a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/avr/torture/pr119989-flashx-2.c
@@ -0,0 +1,7 @@
+/* { dg-do run { target { ! avr_tiny } } } */
+/* { dg-additional-options "-std=gnu99" } */
+
+typedef __UINT16_TYPE__ TYP;
+#define AS __flashx
+
+#include "pr119989.h"
diff --git a/gcc/testsuite/gcc.target/avr/torture/pr119989-flashx-3.c
b/gcc/testsuite/gcc.target/avr/torture/pr119989-flashx-3.c
new file mode 100644
index ..1a5e8f0488ac
--- /dev/null
+++ b/gcc/testsuite/gcc.target/avr/torture/pr119989-flashx-3.c
@@ -0,0 +1,7 @@
+/* { dg-do run { target { ! avr_tiny } } } */
+/* { dg-additional-options "-std=gnu99" } */
+
+__extension__ typedef __uint24 TYP;
+#define AS __flashx
+
+#include "pr119989.h"
diff --git a/gcc/testsuite/gcc.target/avr/torture/pr119989-flashx-4.c
b/gcc/testsuite/gcc.target/avr/torture/pr119989-flashx-4.c
new file mode 100644
index ..63fb52c146ff
--- /dev/null
+++ b/gcc/testsuite/gcc.target/avr/torture/pr119989-flashx-4.c
@@ -0,0 +1,7 @@
+/* { dg-do run { target { ! avr_tiny } } } */
+/* { dg-additional-options "-std=gnu99" } */
+
+typedef __UINT32_TYPE__ TYP;
+#define AS __flashx
+
+#include "pr119989.h"
diff --git a/gcc/testsuite/gcc.target/avr/torture/pr119989-memx-1.c
b/gcc/testsuite/gcc.target/avr/torture/pr119989-memx-1.c
new file mode 100644
index ..45535178bdb3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/avr/torture/pr11
[gcc r16-296] RISC-V: Add intrinsics support for SiFive Xsfvcp extensions.
https://gcc.gnu.org/g:37a6fbe652220dbb8aa38afd20443639a97bbd2f commit r16-296-g37a6fbe652220dbb8aa38afd20443639a97bbd2f Author: yulong Date: Tue Apr 29 21:12:02 2025 +0800 RISC-V: Add intrinsics support for SiFive Xsfvcp extensions. This version is same as v5, but rebase to trunk, send out to trigger CI. This commit adds intrinsics support for Xsfvcp extension. Diff with V4: Delete the sifive_vector.h file. Co-Authored by: Jiawei Chen Co-Authored by: Shihua Liao Co-Authored by: Yixuan Chen gcc/ChangeLog: * config/riscv/constraints.md (Ou01): New constraint. (Ou02): Ditto. * config/riscv/generic-vector-ooo.md (vec_sf_vcp): New reservation. * config/riscv/genrvv-type-indexer.cc (main): New type. * config/riscv/riscv-c.cc (riscv_pragma_intrinsic): Add xsfvcp strings. * config/riscv/riscv-vector-builtins-shapes.cc (struct sf_vcix_se_def): New function. (struct sf_vcix_def): Ditto. (SHAPE): Ditto. * config/riscv/riscv-vector-builtins-shapes.h: Ditto. * config/riscv/riscv-vector-builtins-types.def (DEF_RVV_X2_U_OPS): New type. (DEF_RVV_X2_WU_OPS): Ditto. (vuint8mf8_t): Ditto. (vuint8mf4_t): Ditto. (vuint8mf2_t): Ditto. (vuint8m1_t): Ditto. (vuint8m2_t): Ditto. (vuint8m4_t): Ditto. (vuint16mf4_t): Ditto. (vuint16mf2_t): Ditto. (vuint16m1_t): Ditto. (vuint16m2_t): Ditto. (vuint16m4_t): Ditto. (vuint32mf2_t): Ditto. (vuint32m1_t): Ditto. (vuint32m2_t): Ditto. (vuint32m4_t): Ditto. * config/riscv/riscv-vector-builtins.cc (DEF_RVV_X2_U_OPS): New builtins def. (DEF_RVV_X2_WU_OPS): Ditto. (rvv_arg_type_info::get_scalar_float_type): Ditto. (function_instance::modifies_global_state_p): Ditto. * config/riscv/riscv-vector-builtins.def (v_x): New base type. (i): Ditto. (v_i): Ditto. (xv): Ditto. (iv): Ditto. (fv): Ditto. (vvv): Ditto. (xvv): Ditto. (ivv): Ditto. (fvv): Ditto. (vvw): Ditto. (xvw): Ditto. (ivw): Ditto. (fvw): Ditto. (v_vv): Ditto. (v_xv): Ditto. (v_iv): Ditto. (v_fv): Ditto. (v_vvv): Ditto. (v_xvv): Ditto. (v_ivv): Ditto. (v_fvv): Ditto. (v_vvw): Ditto. (v_xvw): Ditto. (v_ivw): Ditto. (v_fvw): Ditto. (x2_vector): Ditto. (scalar_float): Ditto. * config/riscv/riscv-vector-builtins.h (enum required_ext): New extension. (required_ext_to_isa_name): Ditto. (required_extensions_specified): Ditto. (struct rvv_arg_type_info): Ditto. (struct function_group_info): Ditto. * config/riscv/riscv.md: New attr. * config/riscv/sifive-vector-builtins-bases.cc (class sf_vc): New function. (BASE): New base_name. * config/riscv/sifive-vector-builtins-bases.h: New function_base. * config/riscv/sifive-vector-builtins-functions.def (REQUIRED_EXTENSIONS): New intrinsics def. (sf_vc): Ditto. * config/riscv/sifive-vector.md (@sf_vc_x_se): New RTL mode. (@sf_vc_v_x_se): Ditto. (@sf_vc_v_x): Ditto. (@sf_vc_i_se): Ditto. (@sf_vc_v_i_se): Ditto. (@sf_vc_v_i): Ditto. (@sf_vc_vv_se): Ditto. (@sf_vc_v_vv_se): Ditto. (@sf_vc_v_vv): Ditto. (@sf_vc_xv_se): Ditto. (@sf_vc_v_xv_se): Ditto. (@sf_vc_v_xv): Ditto. (@sf_vc_iv_se): Ditto. (@sf_vc_v_iv_se): Ditto. (@sf_vc_v_iv): Ditto. (@sf_vc_fv_se): Ditto. (@sf_vc_v_fv_se): Ditto. (@sf_vc_v_fv): Ditto. (@sf_vc_vvv_se): Ditto. (@sf_vc_v_vvv_se): Ditto. (@sf_vc_v_vvv): Ditto. (@sf_vc_xvv_se): Ditto. (@sf_vc_v_xvv_se): Ditto. (@sf_vc_v_xvv): Ditto. (@sf_vc_ivv_se): Ditto. (@sf_vc_v_ivv_se): Ditto. (@sf_vc_v_ivv): Ditto. (@sf_vc_fvv_se): Ditto. (@sf_vc_v_fvv_se): Ditto. (@sf_vc_v_fvv): Ditto. (@sf_vc_vvw_se): Ditto. (@sf_vc_v_vvw_se): Ditto. (@sf_vc_v_vvw): Ditto. (@sf_vc_xvw_se): Ditto. (@sf_vc_v_xvw_se): Ditto. (@sf_vc_v_xvw): Ditto. (@sf_vc_ivw_se): Ditto. (@sf_vc_v_ivw_se): Ditto. (@sf_vc_v_ivw): Ditto. (@sf_vc_fvw
[gcc r16-297] RISC-V: Add intrinsics testcases for SiFive Xsfvcp extensions.
https://gcc.gnu.org/g:cc8b8c0b69200ab816a2626e29d91ac995f7438f
commit r16-297-gcc8b8c0b69200ab816a2626e29d91ac995f7438f
Author: yulong
Date: Tue Apr 29 21:12:03 2025 +0800
RISC-V: Add intrinsics testcases for SiFive Xsfvcp extensions.
This commit adds testcases for Xsfvcp.
Co-Authored by: Jiawei Chen
Co-Authored by: Shihua Liao
Co-Authored by: Yixuan Chen
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/xsfvector/sf_vc_f.c: New test.
* gcc.target/riscv/rvv/xsfvector/sf_vc_i.c: New test.
* gcc.target/riscv/rvv/xsfvector/sf_vc_v.c: New test.
* gcc.target/riscv/rvv/xsfvector/sf_vc_x.c: New test.
Diff:
---
.../gcc.target/riscv/rvv/xsfvector/sf_vc_f.c | 88 +
.../gcc.target/riscv/rvv/xsfvector/sf_vc_i.c | 132
.../gcc.target/riscv/rvv/xsfvector/sf_vc_v.c | 107
.../gcc.target/riscv/rvv/xsfvector/sf_vc_x.c | 138 +
4 files changed, 465 insertions(+)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_f.c
b/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_f.c
new file mode 100644
index ..7667e56a4c5f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_f.c
@@ -0,0 +1,88 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_xsfvcp -mabi=lp64d -O3" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sifive_vector.h"
+
+typedef _Float16 float16_t;
+typedef float float32_t;
+typedef double float64_t;
+
+/*
+** test_sf_vc_v_fv_u16mf4:
+** ...
+** vsetivli\s+zero+,0+,e16+,mf4,ta,ma+
+** sf\.vc\.v\.fv\t[0-9]+,v[0-9]+,v[0-9]+,fa[0-9]+
+** ...
+*/
+vuint16mf4_t test_sf_vc_v_fv_u16mf4(vuint16mf4_t vs2, float16_t fs1, size_t
vl) {
+return __riscv_sf_vc_v_fv_u16mf4(1, vs2, fs1, vl);
+}
+
+/*
+** test_sf_vc_v_fv_se_u16mf4:
+** ...
+** vsetivli\s+zero+,0+,e16+,mf4,ta,ma+
+** sf\.vc\.v\.fv\t[0-9]+,v[0-9]+,v[0-9]+,fa[0-9]+
+** ...
+*/
+vuint16mf4_t test_sf_vc_v_fv_se_u16mf4(vuint16mf4_t vs2, float16_t fs1, size_t
vl) {
+return __riscv_sf_vc_v_fv_se_u16mf4(1, vs2, fs1, vl);
+}
+
+/*
+** test_sf_vc_fv_se_u16mf2:
+** ...
+** vsetivli\s+zero+,0+,e16+,mf2,ta,ma+
+** sf\.vc\.fv\t[0-9]+,[0-9]+,v[0-9]+,fa[0-9]+
+** ...
+*/
+void test_sf_vc_fv_se_u16mf2(vuint16mf2_t vs2, float16_t fs1, size_t vl) {
+__riscv_sf_vc_fv_se_u16mf2(1, 3, vs2, fs1, vl);
+}
+
+/*
+** test_sf_vc_v_fvv_u16m1:
+** ...
+** vsetivli\s+zero+,0+,e16+,m1,ta,ma+
+** sf\.vc\.v\.fvv\t[0-9]+,v[0-9]+,v[0-9]+,fa[0-9]+
+** ...
+*/
+vuint16m1_t test_sf_vc_v_fvv_u16m1(vuint16m1_t vd, vuint16m1_t vs2, float16_t
fs1, size_t vl) {
+return __riscv_sf_vc_v_fvv_u16m1(1, vd, vs2, fs1, vl);
+}
+
+/*
+** test_sf_vc_v_fvv_se_u16m1:
+** ...
+** vsetivli\s+zero+,0+,e16+,m1,ta,ma+
+** sf\.vc\.v\.fvv\t[0-9]+,v[0-9]+,v[0-9]+,fa[0-9]+
+** ...
+*/
+vuint16m1_t test_sf_vc_v_fvv_se_u16m1(vuint16m1_t vd, vuint16m1_t vs2,
float16_t fs1, size_t vl) {
+return __riscv_sf_vc_v_fvv_se_u16m1(1, vd, vs2, fs1, vl);
+}
+
+/*
+** test_sf_vc_fvv_se_u32m8:
+** ...
+** vsetivli\s+zero+,0+,e32+,m8,ta,ma+
+** sf\.vc\.fvv\t[0-9]+,v[0-9]+,v[0-9]+,fa[0-9]+
+** ...
+*/
+void test_sf_vc_fvv_se_u32m8(vuint32m8_t vd, vuint32m8_t vs2, float32_t fs1,
size_t vl) {
+__riscv_sf_vc_fvv_se_u32m8(1, vd, vs2, fs1, vl);
+}
+
+
+/*
+** test_sf_vc_fvw_se_u32m2:
+** ...
+** vsetivli\s+zero+,0+,e32+,m2,ta,ma+
+** sf\.vc\.fvw\t[0-9]+,v[0-9]+,v[0-9]+,fa[0-9]+
+** ...
+*/
+void test_sf_vc_fvw_se_u32m2(vuint64m4_t vd, vuint32m2_t vs2, float32_t fs1,
size_t vl) {
+__riscv_sf_vc_fvw_se_u32m2(1, vd, vs2, fs1, vl);
+}
+
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_i.c
b/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_i.c
new file mode 100644
index ..5528cc52ac76
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_i.c
@@ -0,0 +1,132 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_xsfvcp -mabi=lp64d -O3" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sifive_vector.h"
+
+
+/*
+** test_sf_vc_v_i_u16m4:
+** ...
+** vsetivli\s+zero+,0+,e16+,m4,ta,ma+
+** sf\.vc\.v\.i\t[0-9]+,[0-9]+,v[0-9]+,[0-9]+
+** ...
+*/
+vuint16m4_t test_sf_vc_v_i_u16m4(size_t vl) {
+return __riscv_sf_vc_v_i_u16m4(1, 2, 4, vl);
+}
+
+/*
+** test_sf_vc_v_i_se_u16m4:
+** ...
+** vsetivli\s+zero+,0+,e16+,m4,ta,ma+
+** sf\.vc\.v\.i\t[0-9]+,[0-9]+,v[0-9]+,[0-9]+
+** ...
+*/
+vuint16m4_t test_sf_vc_v_i_se_u16m4(size_t vl) {
+return __riscv_sf_vc_v_i_se_u16m4(1, 2, 4, vl);
+}
+
+/*
+** test_sf_vc_i_se_u16mf4:
+** ...
+** vsetivli\s+zero+,0+,e16+,mf4,ta,ma+
+** sf\.vc\.i\t[0-9]+,[0-9]+,[0-9]+,[0-9]+
+** ...
+*/
+void test_sf_vc_i_se_u16mf4(size_t vl) {
+__riscv_sf_vc_i_se_u16mf4(1, 2, 3, 4, vl);
+}
+
+/*
+** test_sf_vc_v_iv_u32m2:
+** ...
+** vsetivli\s+zero+,0+,e32+,m2,ta,ma+
+** sf\.vc\.v\.iv\t[0-9]+,v[0-9]+,v[0-9]+,[0-9]+
+** ...
+*/
+vuint32m2_t test_sf_vc_v_iv_u32m2(vuint32m2_t vs
[gcc r16-298] AArch64: Fold LD1/ST1 with ptrue to LDR/STR for 128-bit VLS
https://gcc.gnu.org/g:83bb288faa39a0bf5ce2d62e21a090a130d8dda4
commit r16-298-g83bb288faa39a0bf5ce2d62e21a090a130d8dda4
Author: Jennifer Schmitz
Date: Thu Feb 13 04:34:30 2025 -0800
AArch64: Fold LD1/ST1 with ptrue to LDR/STR for 128-bit VLS
If -msve-vector-bits=128, SVE loads and stores (LD1 and ST1) with a
ptrue predicate can be replaced by neon instructions (LDR and STR),
thus avoiding the predicate altogether. This also enables formation of
LDP/STP pairs.
For example, the test cases
svfloat64_t
ptrue_load (float64_t *x)
{
svbool_t pg = svptrue_b64 ();
return svld1_f64 (pg, x);
}
void
ptrue_store (float64_t *x, svfloat64_t data)
{
svbool_t pg = svptrue_b64 ();
return svst1_f64 (pg, x, data);
}
were previously compiled to
(with -O2 -march=armv8.2-a+sve -msve-vector-bits=128):
ptrue_load:
ptrue p3.b, vl16
ld1dz0.d, p3/z, [x0]
ret
ptrue_store:
ptrue p3.b, vl16
st1dz0.d, p3, [x0]
ret
Now the are compiled to:
ptrue_load:
ldr q0, [x0]
ret
ptrue_store:
str q0, [x0]
ret
The implementation includes the if-statement
if (known_eq (GET_MODE_SIZE (mode), 16)
&& aarch64_classify_vector_mode (mode) == VEC_SVE_DATA)
which checks for 128-bit VLS and excludes partial modes with a
mode size < 128 (e.g. VNx2QI).
The patch was bootstrapped and tested on aarch64-linux-gnu, no regression.
OK for mainline?
Signed-off-by: Jennifer Schmitz
gcc/
* config/aarch64/aarch64.cc (aarch64_emit_sve_pred_move):
Fold LD1/ST1 with ptrue to LDR/STR for 128-bit VLS.
gcc/testsuite/
* gcc.target/aarch64/sve/ldst_ptrue_128_to_neon.c: New test.
* gcc.target/aarch64/sve/cond_arith_6.c: Adjust expected outcome.
* gcc.target/aarch64/sve/pcs/return_4_128.c: Likewise.
* gcc.target/aarch64/sve/pcs/return_5_128.c: Likewise.
* gcc.target/aarch64/sve/pcs/struct_3_128.c: Likewise.
Diff:
---
gcc/config/aarch64/aarch64.cc | 29 ---
.../gcc.target/aarch64/sve/cond_arith_6.c | 3 +-
.../aarch64/sve/ldst_ptrue_128_to_neon.c | 48 +++
.../gcc.target/aarch64/sve/pcs/return_4_128.c | 39 +--
.../gcc.target/aarch64/sve/pcs/return_5_128.c | 39 +--
.../gcc.target/aarch64/sve/pcs/struct_3_128.c | 56 --
6 files changed, 118 insertions(+), 96 deletions(-)
diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc
index f7bccf532f89..fff8d9da49d3 100644
--- a/gcc/config/aarch64/aarch64.cc
+++ b/gcc/config/aarch64/aarch64.cc
@@ -6416,13 +6416,30 @@ aarch64_stack_protect_canary_mem (machine_mode mode,
rtx decl_rtl,
void
aarch64_emit_sve_pred_move (rtx dest, rtx pred, rtx src)
{
- expand_operand ops[3];
machine_mode mode = GET_MODE (dest);
- create_output_operand (&ops[0], dest, mode);
- create_input_operand (&ops[1], pred, GET_MODE(pred));
- create_input_operand (&ops[2], src, mode);
- temporary_volatile_ok v (true);
- expand_insn (code_for_aarch64_pred_mov (mode), 3, ops);
+ if ((MEM_P (dest) || MEM_P (src))
+ && known_eq (GET_MODE_SIZE (mode), 16)
+ && aarch64_classify_vector_mode (mode) == VEC_SVE_DATA
+ && !BYTES_BIG_ENDIAN)
+{
+ if (MEM_P (src))
+ {
+ rtx tmp = force_reg (V16QImode, adjust_address (src, V16QImode, 0));
+ emit_move_insn (dest, lowpart_subreg (mode, tmp, V16QImode));
+ }
+ else
+ emit_move_insn (adjust_address (dest, V16QImode, 0),
+ force_lowpart_subreg (V16QImode, src, mode));
+}
+ else
+{
+ expand_operand ops[3];
+ create_output_operand (&ops[0], dest, mode);
+ create_input_operand (&ops[1], pred, GET_MODE(pred));
+ create_input_operand (&ops[2], src, mode);
+ temporary_volatile_ok v (true);
+ expand_insn (code_for_aarch64_pred_mov (mode), 3, ops);
+}
}
/* Expand a pre-RA SVE data move from SRC to DEST in which at least one
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/cond_arith_6.c
b/gcc/testsuite/gcc.target/aarch64/sve/cond_arith_6.c
index 4085ab124445..d5a12f1df077 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/cond_arith_6.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/cond_arith_6.c
@@ -8,7 +8,8 @@ f (float *x)
x[i] -= 1.0f;
}
-/* { dg-final { scan-assembler {\tld1w\tz} } } */
+/* { dg-final { scan-assembler {\tld1w\tz} { target aarch64_big_endian } } } */
+/* { dg-final { scan-assembler {\tldr\tq} { target aarch64_little_endian } } }
*/
/* { dg-final { scan-assembler {\tfcmgt\tp} } } */
/* { dg-final { scan-assembler {\tfsub\tz} } } */
/* { dg-final { scan-assembler {\tst1w\tz} } } */
diff --git a/gcc/tes
[gcc r15-9603] AVR: fxload__libgcc: Use REG_ prefix.
https://gcc.gnu.org/g:ffc40e9f2f6923966c235e09ec47de50f2de4c93
commit r15-9603-gffc40e9f2f6923966c235e09ec47de50f2de4c93
Author: Georg-Johann Lay
Date: Wed Apr 30 11:17:47 2025 +0200
AVR: fxload__libgcc: Use REG_ prefix.
gcc/
* config/avr/avr.md (fxload__libgcc): Use REG_ prefix for
magix register numbers (aligns with trunk).
Diff:
---
gcc/config/avr/avr.md | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/gcc/config/avr/avr.md b/gcc/config/avr/avr.md
index 14b3e77ae506..01b8e4bce4cf 100644
--- a/gcc/config/avr/avr.md
+++ b/gcc/config/avr/avr.md
@@ -716,9 +716,9 @@
|| avr_load_libgcc_insn_p (insn, ADDR_SPACE_FLASHX, true)"
"#"
"&& reload_completed"
- [(parallel [(set (reg:MOVMODE 22)
+ [(parallel [(set (reg:MOVMODE REG_22)
(match_dup 0))
- (clobber (reg:QI 21))
+ (clobber (reg:QI REG_21))
(clobber (reg:HI REG_Z))
(clobber (reg:CC REG_CC))])]
{
@@ -729,7 +729,7 @@
[(set (reg:MOVMODE REG_22)
(mem:MOVMODE (lo_sum:PSI (reg:QI REG_21)
(reg:HI REG_Z
- (clobber (reg:QI 21))
+ (clobber (reg:QI REG_21))
(clobber (reg:HI REG_Z))
(clobber (reg:CC REG_CC))]
"reload_completed
[gcc(refs/users/mikael/heads/refactor_descriptor_v05)] Correction régression realloc_on_assign_10
https://gcc.gnu.org/g:dc0220b64f510e20fb6316aeb2cfc7d3f5b6fda7
commit dc0220b64f510e20fb6316aeb2cfc7d3f5b6fda7
Author: Mikael Morin
Date: Tue Apr 29 15:27:11 2025 +0200
Correction régression realloc_on_assign_10
Diff:
---
gcc/fortran/trans-descriptor.cc | 32 +++-
gcc/fortran/trans-descriptor.h | 2 +-
gcc/fortran/trans-expr.cc | 2 +-
3 files changed, 5 insertions(+), 31 deletions(-)
diff --git a/gcc/fortran/trans-descriptor.cc b/gcc/fortran/trans-descriptor.cc
index a0236f30843d..22a6fb6942e2 100644
--- a/gcc/fortran/trans-descriptor.cc
+++ b/gcc/fortran/trans-descriptor.cc
@@ -2155,27 +2155,10 @@ conv_shift_descriptor (stmtblock_t *block, tree desc,
int rank,
}
-class cond_descr_lb : public lb_info_base
-{
- tree desc;
- tree cond;
-public:
- cond_descr_lb (tree arg_desc, tree arg_cond)
-: desc (arg_desc), cond (arg_cond) { }
-
- virtual tree lower_bound (stmtblock_t *block, int dim) const;
- virtual bool zero_based_src () const { return true; }
-};
-
-
-tree
-cond_descr_lb::lower_bound (stmtblock_t *block ATTRIBUTE_UNUSED, int dim) const
+void
+gfc_conv_shift_descriptor (stmtblock_t* block, tree dest, tree src, int rank)
{
- tree lbound = gfc_conv_descriptor_lbound_get (desc, gfc_rank_cst[dim]);
- lbound = fold_build3_loc (input_location, COND_EXPR,
- gfc_array_index_type, cond,
- gfc_index_one_node, lbound);
- return lbound;
+ conv_shift_descriptor (block, src, dest, rank, unset_lb ());
}
@@ -2453,15 +2436,6 @@ gfc_conv_remap_descriptor (stmtblock_t *block, tree
dest, tree src,
}
-void
-gfc_conv_shift_descriptor (stmtblock_t *block, tree dest, tree src,
- int rank, tree zero_cond)
-{
- conv_shift_descriptor (block, src, dest, rank,
-cond_descr_lb (src, zero_cond));
-}
-
-
void
gfc_copy_descriptor (stmtblock_t *block, tree dest, tree src,
gfc_expr *src_expr, bool subref)
diff --git a/gcc/fortran/trans-descriptor.h b/gcc/fortran/trans-descriptor.h
index 5cdf324cf8e3..092a2b8abddc 100644
--- a/gcc/fortran/trans-descriptor.h
+++ b/gcc/fortran/trans-descriptor.h
@@ -81,7 +81,7 @@ tree gfc_get_cfi_dim_sm (tree, tree);
tree gfc_build_desc_array_type (tree, tree, int, tree *, tree *);
void gfc_conv_shift_descriptor (stmtblock_t*, tree, const gfc_array_ref &);
void gfc_conv_shift_descriptor (stmtblock_t*, tree, int);
-void gfc_conv_shift_descriptor (stmtblock_t*, tree, tree, int, tree);
+void gfc_conv_shift_descriptor (stmtblock_t*, tree, tree, int);
void gfc_conv_shift_descriptor_subarray (stmtblock_t*, tree, gfc_expr *,
gfc_expr *);
void gfc_conv_shift_descriptor (stmtblock_t *, tree, int, tree *, tree *);
diff --git a/gcc/fortran/trans-expr.cc b/gcc/fortran/trans-expr.cc
index 364123ce3ed5..612dea0c46a5 100644
--- a/gcc/fortran/trans-expr.cc
+++ b/gcc/fortran/trans-expr.cc
@@ -11477,7 +11477,7 @@ fcncall_realloc_result (gfc_se *se, int rank, tree
dtype)
/* Now reset the bounds returned from the function call to bounds based
on the lhs lbounds, except where the lhs is not allocated or the shapes
of 'variable and 'expr' are different. Set the offset accordingly. */
- gfc_conv_shift_descriptor (&se->post, desc, res_desc, rank, zero_cond);
+ gfc_conv_shift_descriptor (&se->post, desc, res_desc, rank);
}
[gcc(refs/users/mikael/heads/refactor_descriptor_v05)] Restauration intrinsic stride (correction régression finalize_17)
https://gcc.gnu.org/g:6696b3e5358efba567fc8f64c150f154e51ebdec
commit 6696b3e5358efba567fc8f64c150f154e51ebdec
Author: Mikael Morin
Date: Tue Apr 29 18:40:50 2025 +0200
Restauration intrinsic stride (correction régression finalize_17)
Diff:
---
gcc/fortran/class.cc | 43 +++---
gcc/fortran/intrinsic.cc | 8
gcc/fortran/trans-intrinsic.cc | 32 +++
3 files changed, 64 insertions(+), 19 deletions(-)
diff --git a/gcc/fortran/class.cc b/gcc/fortran/class.cc
index 23d8701ac44f..e92760db51dd 100644
--- a/gcc/fortran/class.cc
+++ b/gcc/fortran/class.cc
@@ -1343,14 +1343,12 @@ finalization_scalarizer (gfc_symbol *array, gfc_symbol
*ptr,
offset = 0
do idx2 = 1, rank
offset = offset + mod (idx, sizes(idx2)) / sizes(idx2-1) * strides(idx2)
- end do
- offset = offset * byte_stride. */
+ end do */
static gfc_code*
finalization_get_offset (gfc_symbol *idx, gfc_symbol *idx2, gfc_symbol *offset,
gfc_symbol *strides, gfc_symbol *sizes,
-gfc_symbol *byte_stride, gfc_expr *rank,
-gfc_code *block, gfc_namespace *sub_ns)
+gfc_expr *rank, gfc_code *block, gfc_namespace *sub_ns)
{
gfc_iterator *iter;
gfc_expr *expr, *expr2;
@@ -1443,17 +1441,6 @@ finalization_get_offset (gfc_symbol *idx, gfc_symbol
*idx2, gfc_symbol *offset,
block->block->next->expr2->ts = idx->ts;
block->block->next->expr2->where = gfc_current_locus;
- /* After the loop: offset = offset * byte_stride. */
- block->next = gfc_get_code (EXEC_ASSIGN);
- block = block->next;
- block->expr1 = gfc_lval_expr_from_sym (offset);
- block->expr2 = gfc_get_expr ();
- block->expr2->expr_type = EXPR_OP;
- block->expr2->value.op.op = INTRINSIC_TIMES;
- block->expr2->value.op.op1 = gfc_lval_expr_from_sym (offset);
- block->expr2->value.op.op2 = gfc_lval_expr_from_sym (byte_stride);
- block->expr2->ts = block->expr2->value.op.op1->ts;
- block->expr2->where = gfc_current_locus;
return block;
}
@@ -1926,10 +1913,29 @@ generate_finalization_wrapper (gfc_symbol *derived,
gfc_namespace *ns,
last_code->ext.iterator = iter;
last_code->block = gfc_get_code (EXEC_DO);
- /* sizes(idx) = ... */
+ /* strides(idx) = _F._stride(array,dim=idx). */
last_code->block->next = gfc_get_code (EXEC_ASSIGN);
block = last_code->block->next;
+ block->expr1 = gfc_lval_expr_from_sym (strides);
+ block->expr1->ref = gfc_get_ref ();
+ block->expr1->ref->type = REF_ARRAY;
+ block->expr1->ref->u.ar.type = AR_ELEMENT;
+ block->expr1->ref->u.ar.dimen = 1;
+ block->expr1->ref->u.ar.dimen_type[0] = DIMEN_ELEMENT;
+ block->expr1->ref->u.ar.start[0] = gfc_lval_expr_from_sym (idx);
+ block->expr1->ref->u.ar.as = strides->as;
+
+ block->expr2 = gfc_build_intrinsic_call (sub_ns, GFC_ISYM_STRIDE, "stride",
+ gfc_current_locus, 2,
+ gfc_lval_expr_from_sym (array),
+ gfc_lval_expr_from_sym (idx));
+
+ /* sizes(idx) = sizes(idx-1) * size(array,dim=idx, kind=index_kind). */
+ block->next = gfc_get_code (EXEC_ASSIGN);
+ block = block->next;
+
+ /* sizes(idx) = ... */
block->expr1 = gfc_lval_expr_from_sym (sizes);
block->expr1->ref = gfc_get_ref ();
block->expr1->ref->type = REF_ARRAY;
@@ -2146,8 +2152,7 @@ generate_finalization_wrapper (gfc_symbol *derived,
gfc_namespace *ns,
/* Offset calculation. */
block = finalization_get_offset (idx, idx2, offset, strides, sizes,
- byte_stride, rank, block->block,
- sub_ns);
+ rank, block->block, sub_ns);
/* Create code for
CALL C_F_POINTER (TRANSFER (TRANSFER (C_LOC (array, cptr),
c_intptr)
@@ -2217,7 +,7 @@ finish_assumed_rank:
/* Offset calculation. */
block = finalization_get_offset (idx, idx2, offset, strides, sizes,
- byte_stride, rank, last_code->block,
+ rank, last_code->block,
sub_ns);
/* Create code for
diff --git a/gcc/fortran/intrinsic.cc b/gcc/fortran/intrinsic.cc
index 417d285ec308..30f532b5766b 100644
--- a/gcc/fortran/intrinsic.cc
+++ b/gcc/fortran/intrinsic.cc
@@ -3125,6 +3125,14 @@ add_functions (void)
make_generic ("size", GFC_ISYM_SIZE, GFC_STD_F95);
+ /* Obtain the stride for a given dimensions; to be used only internally.
+ "make_from_module" makes it inaccessible for external users. */
+ add_sym_2 (GFC_PREFIX ("stride"), GFC_ISYM_STRIDE, CLASS_INQUIRY, ACTUAL_NO,
+BT_INTEGER, gfc_index_integer_kind, GFC_STD_GNU,
+NULL, NULL, gfc_resolve_stride,
+ar, BT_REAL, dr, REQUIRED,
[gcc(refs/users/mikael/heads/refactor_descriptor_v05)] Correction régression pack_generic
https://gcc.gnu.org/g:03f62c04e928b83b882226d9170fd05dc8361209
commit 03f62c04e928b83b882226d9170fd05dc8361209
Author: Mikael Morin
Date: Tue Apr 29 15:57:12 2025 +0200
Correction régression pack_generic
Diff:
---
libgfortran/intrinsics/pack_generic.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/libgfortran/intrinsics/pack_generic.c
b/libgfortran/intrinsics/pack_generic.c
index ebe44ec62669..65128b6ea02f 100644
--- a/libgfortran/intrinsics/pack_generic.c
+++ b/libgfortran/intrinsics/pack_generic.c
@@ -159,7 +159,7 @@ pack_internal (gfc_array_char *ret, const gfc_array_char
*array,
if (ret->base_addr == NULL)
{
/* Setup the array descriptor. */
- GFC_DESCRIPTOR_DIMENSION_SET(ret, 0, 0, total-1, 1);
+ GFC_DESCRIPTOR_DIMENSION_SET(ret, 0, 0, total-1, size);
ret->offset = 0;
/* xmallocarray allocates a single byte for zero size. */
[gcc(refs/users/mikael/heads/refactor_descriptor_v05)] Correction régression matmul_bounds_20
https://gcc.gnu.org/g:fb23bc7bc9dd01f86a5cfed7841e8616a832ad8c
commit fb23bc7bc9dd01f86a5cfed7841e8616a832ad8c
Author: Mikael Morin
Date: Tue Apr 29 13:56:18 2025 +0200
Correction régression matmul_bounds_20
Diff:
---
gcc/fortran/trans-array.cc | 33 +
1 file changed, 33 insertions(+)
diff --git a/gcc/fortran/trans-array.cc b/gcc/fortran/trans-array.cc
index 3c28052afb85..b931184a3c40 100644
--- a/gcc/fortran/trans-array.cc
+++ b/gcc/fortran/trans-array.cc
@@ -2813,6 +2813,39 @@ gfc_add_loop_ss_code (gfc_loopinfo * loop, gfc_ss * ss,
bool subscript,
info->spacing[dim] = spacing;
}
}
+ else
+ {
+ bool missing_spacing;
+ for (int n = 0; n < ss_info->expr->rank; n++)
+ if (info->spacing[n] == NULL_TREE)
+ {
+ missing_spacing = true;
+ break;
+ }
+ if (missing_spacing
+ && ss_info->expr->ts.type != BT_CLASS)
+ {
+ tree type = gfc_typenode_for_spec (&ss_info->expr->ts);
+ tree spacing = fold_convert_loc (input_location,
+gfc_array_index_type,
+TYPE_SIZE_UNIT (type));
+ spacing = gfc_evaluate_now (spacing, &outer_loop->pre);
+
+ for (n = 0; n < ss_info->expr->rank; n++)
+ {
+ info->spacing[n] = spacing;
+
+ tree extent = gfc_conv_descriptor_extent_get
(info->descriptor,
+
gfc_rank_cst[n]);
+
+ spacing = fold_build2_loc (input_location, MULT_EXPR,
+ gfc_array_index_type,
spacing,
+ extent);
+ spacing = gfc_evaluate_now (spacing, &outer_loop->pre);
+ }
+ }
+ }
+
gfc_add_block_to_block (&outer_loop->post, &se.post);
gfc_add_block_to_block (&outer_loop->post, &se.finalblock);
ss_info->string_length = se.string_length;
[gcc(refs/users/mikael/heads/refactor_descriptor_v05)] Correction régression alloc_comp_result_1
https://gcc.gnu.org/g:86b472ea185c49acb7df99b275eb77321f9a4e42
commit 86b472ea185c49acb7df99b275eb77321f9a4e42
Author: Mikael Morin
Date: Tue Apr 29 15:42:48 2025 +0200
Correction régression alloc_comp_result_1
Diff:
---
gcc/fortran/trans-array.cc | 3 +++
1 file changed, 3 insertions(+)
diff --git a/gcc/fortran/trans-array.cc b/gcc/fortran/trans-array.cc
index b931184a3c40..748b31059491 100644
--- a/gcc/fortran/trans-array.cc
+++ b/gcc/fortran/trans-array.cc
@@ -8769,6 +8769,9 @@ structure_alloc_comps (gfc_symbol * der_type, tree decl,
tree dest,
{
/* Otherwise use the TYPE_DOMAIN information. */
tmp = array_type_nelts_minus_one (decl_type);
+ if (error_operand_p (tmp)
+ && GFC_ARRAY_TYPE_P (decl_type))
+ tmp = GFC_TYPE_ARRAY_SIZE (decl_type);
tmp = fold_convert (gfc_array_index_type, tmp);
}
[gcc(refs/users/mikael/heads/refactor_descriptor_v05)] Correction régression strarray_4
https://gcc.gnu.org/g:5d3ebfb00d4a5d5de6a1409da314d168a99dd7d5
commit 5d3ebfb00d4a5d5de6a1409da314d168a99dd7d5
Author: Mikael Morin
Date: Wed Apr 30 12:07:30 2025 +0200
Correction régression strarray_4
Diff:
---
gcc/fortran/trans-array.cc | 2 ++
gcc/fortran/trans-decl.cc | 17 -
2 files changed, 18 insertions(+), 1 deletion(-)
diff --git a/gcc/fortran/trans-array.cc b/gcc/fortran/trans-array.cc
index 748b31059491..f3915526daf3 100644
--- a/gcc/fortran/trans-array.cc
+++ b/gcc/fortran/trans-array.cc
@@ -6162,6 +6162,8 @@ gfc_trans_array_bounds (tree type, gfc_symbol * sym, tree
* poffset,
int dim;
+ gfc_trans_vla_type_sizes (sym, pblock);
+
as = IS_CLASS_COARRAY_OR_ARRAY (sym) ? CLASS_DATA (sym)->as : sym->as;
tree eltype = gfc_get_element_type (type);
diff --git a/gcc/fortran/trans-decl.cc b/gcc/fortran/trans-decl.cc
index 9b91cc29d395..99c53fab755a 100644
--- a/gcc/fortran/trans-decl.cc
+++ b/gcc/fortran/trans-decl.cc
@@ -4391,6 +4391,21 @@ gfc_trans_assign_aux_var (gfc_symbol * sym,
gfc_wrapped_block * block)
gfc_add_init_cleanup (block, gfc_finish_block (&init), NULL_TREE);
}
+
+static bool
+decl_ref_or_const_like_p (tree t)
+{
+ if (TREE_CONSTANT (t) || DECL_P (t))
+return true;
+
+ if (TREE_CODE (t) == SAVE_EXPR
+ || TREE_CODE (t) == NON_LVALUE_EXPR)
+return decl_ref_or_const_like_p (TREE_OPERAND (t, 0));
+ else
+return false;
+}
+
+
static void
gfc_trans_vla_one_sizepos (tree *tp, tree root_decl, stmtblock_t *body)
{
@@ -4398,7 +4413,7 @@ gfc_trans_vla_one_sizepos (tree *tp, tree root_decl,
stmtblock_t *body)
if (t == NULL || t == error_mark_node)
return;
- if (TREE_CONSTANT (t) || DECL_P (t))
+ if (decl_ref_or_const_like_p (t))
return;
if (contains_placeholder_p (t))
[gcc r13-9625] AVR: target/119989 - Add missing clobbers to xload__libgcc.
https://gcc.gnu.org/g:67d13d11edd070b57d9166e828dc0b734f4e524b
commit r13-9625-g67d13d11edd070b57d9166e828dc0b734f4e524b
Author: Georg-Johann Lay
Date: Wed Apr 30 08:43:51 2025 +0200
AVR: target/119989 - Add missing clobbers to xload__libgcc.
libgcc's __xload_1...4 is clobbering Z (and also R21 is some cases),
but avr.md had clobbers of respective GPRs only up to reload.
Outcome was that code reading from the same __memx address twice
could be wrong. This patch adds respective clobbers.
Backport from 2025-04-30 r14-11703
PR target/119989
gcc/
* config/avr/avr.md (xload__libgcc): Clobber R21, Z.
gcc/testsuite/
* gcc.target/avr/torture/pr119989.h: New file.
* gcc.target/avr/torture/pr119989-memx-1.c: New test.
* gcc.target/avr/torture/pr119989-memx-2.c: New test.
* gcc.target/avr/torture/pr119989-memx-3.c: New test.
* gcc.target/avr/torture/pr119989-memx-4.c: New test.
(cherry picked from commit 1ca1c1fc3b58ae5e1d3db4f5a2014132fe69f82a)
Diff:
---
gcc/config/avr/avr.md | 4 +++
.../gcc.target/avr/torture/pr119989-memx-1.c | 6
.../gcc.target/avr/torture/pr119989-memx-2.c | 6
.../gcc.target/avr/torture/pr119989-memx-3.c | 6
.../gcc.target/avr/torture/pr119989-memx-4.c | 6
gcc/testsuite/gcc.target/avr/torture/pr119989.h| 37 ++
6 files changed, 65 insertions(+)
diff --git a/gcc/config/avr/avr.md b/gcc/config/avr/avr.md
index 5d134afbf2c3..c071effcb048 100644
--- a/gcc/config/avr/avr.md
+++ b/gcc/config/avr/avr.md
@@ -657,12 +657,16 @@
[(parallel [(set (reg:MOVMODE 22)
(mem:MOVMODE (lo_sum:PSI (reg:QI 21)
(reg:HI REG_Z
+ (clobber (reg:QI 21))
+ (clobber (reg:HI REG_Z))
(clobber (reg:CC REG_CC))])])
(define_insn "*xload__libgcc"
[(set (reg:MOVMODE 22)
(mem:MOVMODE (lo_sum:PSI (reg:QI 21)
(reg:HI REG_Z
+ (clobber (reg:QI 21))
+ (clobber (reg:HI REG_Z))
(clobber (reg:CC REG_CC))]
"avr_xload_libgcc_p (mode)
&& reload_completed"
diff --git a/gcc/testsuite/gcc.target/avr/torture/pr119989-memx-1.c
b/gcc/testsuite/gcc.target/avr/torture/pr119989-memx-1.c
new file mode 100644
index ..27b89e437bd0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/avr/torture/pr119989-memx-1.c
@@ -0,0 +1,6 @@
+/* { dg-do run { target { ! avr_tiny } } } */
+/* { dg-additional-options "-std=gnu99" } */
+
+typedef __UINT8_TYPE__ TYP;
+
+#include "pr119989.h"
diff --git a/gcc/testsuite/gcc.target/avr/torture/pr119989-memx-2.c
b/gcc/testsuite/gcc.target/avr/torture/pr119989-memx-2.c
new file mode 100644
index ..a8011a25b839
--- /dev/null
+++ b/gcc/testsuite/gcc.target/avr/torture/pr119989-memx-2.c
@@ -0,0 +1,6 @@
+/* { dg-do run { target { ! avr_tiny } } } */
+/* { dg-additional-options "-std=gnu99" } */
+
+typedef __UINT16_TYPE__ TYP;
+
+#include "pr119989.h"
diff --git a/gcc/testsuite/gcc.target/avr/torture/pr119989-memx-3.c
b/gcc/testsuite/gcc.target/avr/torture/pr119989-memx-3.c
new file mode 100644
index ..ea1c4b62c040
--- /dev/null
+++ b/gcc/testsuite/gcc.target/avr/torture/pr119989-memx-3.c
@@ -0,0 +1,6 @@
+/* { dg-do run { target { ! avr_tiny } } } */
+/* { dg-additional-options "-std=gnu99" } */
+
+__extension__ typedef __uint24 TYP;
+
+#include "pr119989.h"
diff --git a/gcc/testsuite/gcc.target/avr/torture/pr119989-memx-4.c
b/gcc/testsuite/gcc.target/avr/torture/pr119989-memx-4.c
new file mode 100644
index ..32b5cd3b55f3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/avr/torture/pr119989-memx-4.c
@@ -0,0 +1,6 @@
+/* { dg-do run { target { ! avr_tiny } } } */
+/* { dg-additional-options "-std=gnu99" } */
+
+typedef __UINT32_TYPE__ TYP;
+
+#include "pr119989.h"
diff --git a/gcc/testsuite/gcc.target/avr/torture/pr119989.h
b/gcc/testsuite/gcc.target/avr/torture/pr119989.h
new file mode 100644
index ..ab9d14a208b8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/avr/torture/pr119989.h
@@ -0,0 +1,37 @@
+const __memx TYP some_data[] = { 1, 2, 3, 4, 5 };
+const __memx TYP *IP;
+
+TYP DT, a, b;
+
+__attribute__((noipa))
+void do_test1 (void)
+{
+DT = *IP;
+DT = *IP--;
+}
+
+__attribute__((noipa))
+void do_test2 (void)
+{
+DT = *IP;
+__asm volatile ("" ::: "memory"); // Prevents unwanted optimization
+DT = *IP--;
+}
+
+TYP difference(void)
+{
+IP = &some_data[3];
+do_test1();
+a = DT;
+IP = &some_data[3];
+do_test2();
+b = DT;
+return a - b; // Expected: 0
+}
+
+int main (void)
+{
+if (difference () != 0)
+__builtin_exit (__LINE__);
+return 0;
+}
[gcc r16-300] RISC-V: Allow different dynamic floating point mode to be merged [PR119832]
https://gcc.gnu.org/g:e5d1f538bb7d2c7a7a4acf4a4516fa8933dc2888
commit r16-300-ge5d1f538bb7d2c7a7a4acf4a4516fa8933dc2888
Author: Kito Cheng
Date: Tue Apr 29 11:35:00 2025 +0800
RISC-V: Allow different dynamic floating point mode to be merged [PR119832]
Although we already try to set the mode needed to FRM_DYN after a function
call,
there are still some corner cases where both FRM_DYN and FRM_DYN_CALL may
appear
on incoming edges.
Therefore, we use TARGET_MODE_CONFLUENCE to tell GCC that FRM_DYN,
FRM_DYN_CALL,
and FRM_DYN_EXIT modes are compatible.
gcc/ChangeLog:
PR target/119832
* config/riscv/riscv.cc (riscv_dynamic_frm_mode_p): New.
(riscv_mode_confluence): New.
(TARGET_MODE_CONFLUENCE): Define to riscv_mode_confluence.
gcc/testsuite/ChangeLog:
PR target/119832
* g++.target/riscv/pr119832.C: New test.
Diff:
---
gcc/config/riscv/riscv.cc | 37 +++
gcc/testsuite/g++.target/riscv/pr119832.C | 27 ++
2 files changed, 64 insertions(+)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index c53e0dd7a7d1..ed635ab42f40 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -12273,6 +12273,41 @@ riscv_mode_needed (int entity, rtx_insn *insn,
HARD_REG_SET)
}
}
+/* Return TRUE if the rouding mode is dynamic. */
+
+static bool
+riscv_dynamic_frm_mode_p (int mode)
+{
+ return mode == riscv_vector::FRM_DYN
+|| mode == riscv_vector::FRM_DYN_CALL
+|| mode == riscv_vector::FRM_DYN_EXIT;
+}
+
+/* Implement TARGET_MODE_CONFLUENCE. */
+
+static int
+riscv_mode_confluence (int entity, int mode1, int mode2)
+{
+ switch (entity)
+{
+case RISCV_VXRM:
+ return VXRM_MODE_NONE;
+case RISCV_FRM:
+ {
+ /* FRM_DYN, FRM_DYN_CALL and FRM_DYN_EXIT are all compatible.
+ Although we already try to set the mode needed to FRM_DYN after a
+ function call, there are still some corner cases where both FRM_DYN
+ and FRM_DYN_CALL may appear on incoming edges. */
+ if (riscv_dynamic_frm_mode_p (mode1)
+ && riscv_dynamic_frm_mode_p (mode2))
+ return riscv_vector::FRM_DYN;
+ return riscv_vector::FRM_NONE;
+ }
+default:
+ gcc_unreachable ();
+}
+}
+
/* Return TRUE that an insn is asm. */
static bool
@@ -14356,6 +14391,8 @@ bool need_shadow_stack_push_pop_p ()
#define TARGET_MODE_EMIT riscv_emit_mode_set
#undef TARGET_MODE_NEEDED
#define TARGET_MODE_NEEDED riscv_mode_needed
+#undef TARGET_MODE_CONFLUENCE
+#define TARGET_MODE_CONFLUENCE riscv_mode_confluence
#undef TARGET_MODE_AFTER
#define TARGET_MODE_AFTER riscv_mode_after
#undef TARGET_MODE_ENTRY
diff --git a/gcc/testsuite/g++.target/riscv/pr119832.C
b/gcc/testsuite/g++.target/riscv/pr119832.C
new file mode 100644
index ..f4dc480e6d59
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/pr119832.C
@@ -0,0 +1,27 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=rv64gcv -mabi=lp64 -ffast-math" } */
+
+struct ac {
+ ~ac();
+ void u();
+};
+struct ae {
+ int s;
+ float *ag;
+};
+
+float c;
+
+void ak(ae *al, int n) {
+ ac d;
+ for (int i;i
[gcc r16-303] tree-optimization/120003 - missed jump threading
https://gcc.gnu.org/g:1a13684dfc7286139064f7d7341462c9995cbd1c
commit r16-303-g1a13684dfc7286139064f7d7341462c9995cbd1c
Author: Richard Biener
Date: Wed Apr 30 11:52:17 2025 +0200
tree-optimization/120003 - missed jump threading
The following allows the entry and exit block of a jump thread path
to be equal, which can easily happen when there isn't a forwarder
on the interesting edge for an FSM thread conditional. We just
don't want to enlarge the path from such a block.
PR tree-optimization/120003
* tree-ssa-threadbackward.cc (back_threader::find_paths_to_names):
Allow block re-use but do not enlarge the path beyond such a
re-use.
* gcc.dg/tree-ssa/ssa-thread-23.c: New testcase.
* gcc.dg/tree-ssa/ssa-dom-thread-7.c: Adjust.
Diff:
---
gcc/testsuite/gcc.dg/tree-ssa/ssa-dom-thread-7.c | 4 ++--
gcc/testsuite/gcc.dg/tree-ssa/ssa-thread-23.c| 19 +++
gcc/tree-ssa-threadbackward.cc | 8 +++-
3 files changed, 24 insertions(+), 7 deletions(-)
diff --git a/gcc/testsuite/gcc.dg/tree-ssa/ssa-dom-thread-7.c
b/gcc/testsuite/gcc.dg/tree-ssa/ssa-dom-thread-7.c
index d84aceebc5d0..8be9878e0cfb 100644
--- a/gcc/testsuite/gcc.dg/tree-ssa/ssa-dom-thread-7.c
+++ b/gcc/testsuite/gcc.dg/tree-ssa/ssa-dom-thread-7.c
@@ -11,8 +11,8 @@
to change decisions in switch expansion which in turn can expose new
jump threading opportunities. Skip the later tests on aarch64. */
/* { dg-final { scan-tree-dump-not "Jumps threaded" "dom3" { target { !
aarch64*-*-* } } } } */
-/* { dg-final { scan-tree-dump "Jumps threaded: 9" "thread2" { target { !
aarch64*-*-* } } } } */
-/* { dg-final { scan-tree-dump "Jumps threaded: 17" "thread2" { target {
aarch64*-*-* } } } } */
+/* { dg-final { scan-tree-dump "Jumps threaded: 10" "thread2" { target { !
aarch64*-*-* } } } } */
+/* { dg-final { scan-tree-dump "Jumps threaded: 14" "thread2" { target {
aarch64*-*-* } } } } */
enum STATE {
S0=0,
diff --git a/gcc/testsuite/gcc.dg/tree-ssa/ssa-thread-23.c
b/gcc/testsuite/gcc.dg/tree-ssa/ssa-thread-23.c
new file mode 100644
index ..930360a33b57
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/tree-ssa/ssa-thread-23.c
@@ -0,0 +1,19 @@
+/* PR120003 */
+/* { dg-do compile } */
+/* { dg-options "-O2 -fdump-tree-cddce3-details" } */
+
+extern _Bool g(int);
+
+_Bool f()
+{
+ _Bool retval = 0;
+ for(int i=0; i<100; ++i)
+retval = retval || g(i);
+ return retval;
+}
+
+/* Jump threading after loop optimization should get the counting loop
+ separated from the loop until retval is true and CD-DCE elide it.
+ It's difficult to check for the fact that a true retval terminates
+ the loop so check CD-DCE eliminates one loop instead. */
+/* { dg-final { scan-tree-dump "fix_loop_structure: removing loop" "cddce3" }
} */
diff --git a/gcc/tree-ssa-threadbackward.cc b/gcc/tree-ssa-threadbackward.cc
index d0b74b2531df..3adb83e97126 100644
--- a/gcc/tree-ssa-threadbackward.cc
+++ b/gcc/tree-ssa-threadbackward.cc
@@ -349,9 +349,6 @@ back_threader::find_paths_to_names (basic_block bb, bitmap
interesting,
unsigned overall_paths,
back_threader_profitability &profit)
{
- if (m_visited_bbs.add (bb))
-return;
-
m_path.safe_push (bb);
// Try to resolve the path without looking back. Avoid resolving paths
@@ -377,7 +374,8 @@ back_threader::find_paths_to_names (basic_block bb, bitmap
interesting,
// Continue looking for ways to extend the path but limit the
// search space along a branch
else if ((overall_paths = overall_paths * EDGE_COUNT (bb->preds))
- <= (unsigned)param_max_jump_thread_paths)
+ <= (unsigned)param_max_jump_thread_paths
+ && !m_visited_bbs.add (bb))
{
// For further greedy searching we want to remove interesting
// names defined in BB but add ones on the PHI edges for the
@@ -489,6 +487,7 @@ back_threader::find_paths_to_names (basic_block bb, bitmap
interesting,
backtracking we have to restore it. */
for (int j : new_imports)
bitmap_clear_bit (m_imports, j);
+ m_visited_bbs.remove (bb);
}
else if (dump_file && (dump_flags & TDF_DETAILS))
fprintf (dump_file, " FAIL: Search space limit %d reached.\n",
@@ -496,7 +495,6 @@ back_threader::find_paths_to_names (basic_block bb, bitmap
interesting,
// Reset things to their original state.
m_path.pop ();
- m_visited_bbs.remove (bb);
}
// Search backwards from BB looking for paths where the final
[gcc r16-307] Revert "tree-optimization/119960 - failed external SLP promotion"
https://gcc.gnu.org/g:e12b09a67e41f470ea6ec5ad93c76ad44f0d28d5
commit r16-307-ge12b09a67e41f470ea6ec5ad93c76ad44f0d28d5
Author: Richard Biener
Date: Wed Apr 30 14:50:37 2025 +0200
Revert "tree-optimization/119960 - failed external SLP promotion"
This reverts commit 51ba233fe2db562390a6e0a3618420889761bc77.
Diff:
---
gcc/testsuite/gcc.dg/vect/bb-slp-pr119960-1.c | 15 ---
gcc/tree-vect-slp.cc | 63 +++
2 files changed, 7 insertions(+), 71 deletions(-)
diff --git a/gcc/testsuite/gcc.dg/vect/bb-slp-pr119960-1.c
b/gcc/testsuite/gcc.dg/vect/bb-slp-pr119960-1.c
deleted file mode 100644
index 955fc7e32208..
--- a/gcc/testsuite/gcc.dg/vect/bb-slp-pr119960-1.c
+++ /dev/null
@@ -1,15 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target vect_double } */
-
-double foo (double *dst, double *src, int b)
-{
- double y = src[1];
- if (b)
-{
- dst[0] = src[0];
- dst[1] = y;
-}
- return y;
-}
-
-/* { dg-final { scan-tree-dump "optimized: basic block part vectorized" "slp2"
{ target vect_double } } } */
diff --git a/gcc/tree-vect-slp.cc b/gcc/tree-vect-slp.cc
index ea30795f0647..19beeed8a3a9 100644
--- a/gcc/tree-vect-slp.cc
+++ b/gcc/tree-vect-slp.cc
@@ -7832,70 +7832,21 @@ vect_slp_analyze_node_operations_1 (vec_info *vinfo,
slp_tree node,
node, node_instance, cost_vec);
}
-static int
-sort_ints (const void *a_, const void *b_)
-{
- int a = *(const int *)a_;
- int b = *(const int *)b_;
- return a - b;
-}
-
/* Verify if we can externalize a set of internal defs. */
static bool
vect_slp_can_convert_to_external (const vec &stmts)
{
- /* Constant generation uses get_later_stmt which can only handle
- defs from the same BB or a set of defs that can be ordered
- with a dominance query. */
basic_block bb = NULL;
- bool all_same = true;
- auto_vec bbs;
- bbs.reserve_exact (stmts.length ());
for (stmt_vec_info stmt : stmts)
-{
- if (!stmt)
- return false;
- else if (!bb)
- bb = gimple_bb (stmt->stmt);
- else if (gimple_bb (stmt->stmt) != bb)
- all_same = false;
- bbs.quick_push (gimple_bb (stmt->stmt)->index);
-}
- if (all_same)
-return true;
-
- /* Produce a vector of unique BB indexes for the defs. */
- bbs.qsort (sort_ints);
- unsigned i, j;
- for (i = 1, j = 1; i < bbs.length (); ++i)
-if (bbs[i] != bbs[j-1])
- bbs[j++] = bbs[i];
- gcc_assert (j >= 2);
- bbs.truncate (j);
-
- if (bbs.length () == 2)
-return (dominated_by_p (CDI_DOMINATORS,
- BASIC_BLOCK_FOR_FN (cfun, bbs[0]),
- BASIC_BLOCK_FOR_FN (cfun, bbs[1]))
- || dominated_by_p (CDI_DOMINATORS,
- BASIC_BLOCK_FOR_FN (cfun, bbs[1]),
- BASIC_BLOCK_FOR_FN (cfun, bbs[0])));
-
- /* ??? For more than two BBs we can sort the vector and verify the
- result is a total order. But we can't use vec::qsort with a
- compare function using a dominance query since there's no way to
- signal failure and any fallback for an unordered pair would
- fail qsort_chk later.
- For now simply hope that ordering after BB index provides the
- best candidate total order. If required we can implement our
- own mergesort or export an entry without checking. */
- for (unsigned i = 1; i < bbs.length (); ++i)
-if (!dominated_by_p (CDI_DOMINATORS,
-BASIC_BLOCK_FOR_FN (cfun, bbs[i]),
-BASIC_BLOCK_FOR_FN (cfun, bbs[i-1])))
+if (!stmt)
+ return false;
+/* Constant generation uses get_later_stmt which can only handle
+ defs from the same BB. */
+else if (!bb)
+ bb = gimple_bb (stmt->stmt);
+else if (gimple_bb (stmt->stmt) != bb)
return false;
-
return true;
}
[gcc r16-308] tree-optimization/119960 - add validity checking to SLP scheduling
https://gcc.gnu.org/g:5f44fcdfe18e72f2900d2757375843e88d32c535
commit r16-308-g5f44fcdfe18e72f2900d2757375843e88d32c535
Author: Richard Biener
Date: Tue Apr 29 15:08:52 2025 +0200
tree-optimization/119960 - add validity checking to SLP scheduling
The following adds checks that when we search for a vector stmt
insert location we arrive at one where all required operand defs
are dominating the insert location. At the moment any such
failure only blows up during SSA verification.
There's the long-standing issue that we do not verify there
exists a valid schedule of the SLP graph from BB vectorization
into the existing CFG. We do not have the ability to insert
vector stmts on the dominance frontier "end", nor to insert
LC PHIs that would be eventually required.
This should be done all differently, computing the schedule
during analysis and failing if we can't schedule.
PR tree-optimization/119960
* tree-vect-slp.cc (vect_schedule_slp_node): Sanity
check dominance check on operand defs.
Diff:
---
gcc/tree-vect-slp.cc | 36
1 file changed, 28 insertions(+), 8 deletions(-)
diff --git a/gcc/tree-vect-slp.cc b/gcc/tree-vect-slp.cc
index 19beeed8a3a9..b5a9604d074e 100644
--- a/gcc/tree-vect-slp.cc
+++ b/gcc/tree-vect-slp.cc
@@ -11161,9 +11161,14 @@ vect_schedule_slp_node (vec_info *vinfo,
== cycle_phi_info_type);
gphi *phi = as_a
(vect_find_last_scalar_stmt_in_slp (child)->stmt);
- if (!last_stmt
- || vect_stmt_dominates_stmt_p (last_stmt, phi))
+ if (!last_stmt)
last_stmt = phi;
+ else if (vect_stmt_dominates_stmt_p (last_stmt, phi))
+ last_stmt = phi;
+ else if (vect_stmt_dominates_stmt_p (phi, last_stmt))
+ ;
+ else
+ gcc_unreachable ();
}
/* We are emitting all vectorized stmts in the same place and
the last one is the last.
@@ -11174,9 +11179,14 @@ vect_schedule_slp_node (vec_info *vinfo,
FOR_EACH_VEC_ELT (SLP_TREE_VEC_DEFS (child), j, vdef)
{
gimple *vstmt = SSA_NAME_DEF_STMT (vdef);
- if (!last_stmt
- || vect_stmt_dominates_stmt_p (last_stmt, vstmt))
+ if (!last_stmt)
+ last_stmt = vstmt;
+ else if (vect_stmt_dominates_stmt_p (last_stmt, vstmt))
last_stmt = vstmt;
+ else if (vect_stmt_dominates_stmt_p (vstmt, last_stmt))
+ ;
+ else
+ gcc_unreachable ();
}
}
else if (!SLP_TREE_VECTYPE (child))
@@ -11189,9 +11199,14 @@ vect_schedule_slp_node (vec_info *vinfo,
&& !SSA_NAME_IS_DEFAULT_DEF (def))
{
gimple *stmt = SSA_NAME_DEF_STMT (def);
- if (!last_stmt
- || vect_stmt_dominates_stmt_p (last_stmt, stmt))
+ if (!last_stmt)
+ last_stmt = stmt;
+ else if (vect_stmt_dominates_stmt_p (last_stmt, stmt))
last_stmt = stmt;
+ else if (vect_stmt_dominates_stmt_p (stmt, last_stmt))
+ ;
+ else
+ gcc_unreachable ();
}
}
else
@@ -11212,9 +11227,14 @@ vect_schedule_slp_node (vec_info *vinfo,
&& !SSA_NAME_IS_DEFAULT_DEF (vdef))
{
gimple *vstmt = SSA_NAME_DEF_STMT (vdef);
- if (!last_stmt
- || vect_stmt_dominates_stmt_p (last_stmt, vstmt))
+ if (!last_stmt)
+ last_stmt = vstmt;
+ else if (vect_stmt_dominates_stmt_p (last_stmt, vstmt))
last_stmt = vstmt;
+ else if (vect_stmt_dominates_stmt_p (vstmt, last_stmt))
+ ;
+ else
+ gcc_unreachable ();
}
}
}
[gcc r16-304] ipa/120006 - wrong code with IPA PTA
https://gcc.gnu.org/g:a85b89e26b1f50997701eb428c2dd71668f216ff
commit r16-304-ga85b89e26b1f50997701eb428c2dd71668f216ff
Author: Richard Biener
Date: Wed Apr 30 10:01:47 2025 +0200
ipa/120006 - wrong code with IPA PTA
When PTA gets support for special-handling more builtins in
find_func_aliases the corresponding code in find_func_clobbers
needs updating as well since for unhandled cases it assumes
the former will populate ESCAPED accordingly. The following
fixes a few omissions, the testcase runs into the missing strdup
handling. I believe the more advanced handling using modref
results and fnspecs opened a larger gap, the proper fix is to
merge both functions, gating the clobber/use part on a parameter
to avoid diverging.
PR ipa/120006
* tree-ssa-structalias.cc (find_func_clobbers): Handle
strdup, strndup, realloc, index, strchr, strrchr, memchr,
strstr, strpbrk builtins like find_func_aliases does.
* gcc.dg/torture/pr120006.c: New testcase.
Diff:
---
gcc/testsuite/gcc.dg/torture/pr120006.c | 31
gcc/tree-ssa-structalias.cc | 36 +
2 files changed, 67 insertions(+)
diff --git a/gcc/testsuite/gcc.dg/torture/pr120006.c
b/gcc/testsuite/gcc.dg/torture/pr120006.c
new file mode 100644
index ..c067f0ef9ca0
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/torture/pr120006.c
@@ -0,0 +1,31 @@
+/* { dg-do run } */
+/* { dg-additional-options "-fipa-pta" } */
+
+char *b;
+int f = 1;
+
+char *xstrdup(char *i) {
+ char *c = __builtin_strdup(i);
+ if (!c)
+__builtin_exit(1);
+ return c;
+}
+
+int main() {
+ char g;
+ char h[8];
+
+ for (int i = 0; i < 2; i++) {
+char c = *__builtin_strdup("");
+b = &g;
+
+if (f) {
+ h[0] = '-';
+ h[1] = 'a';
+ h[2] = '\0';
+ b = xstrdup(h);
+ }
+ }
+ if (__builtin_strcmp(b, "-a") != 0)
+__builtin_abort();
+}
diff --git a/gcc/tree-ssa-structalias.cc b/gcc/tree-ssa-structalias.cc
index f79b54284c64..3ad0c69930c7 100644
--- a/gcc/tree-ssa-structalias.cc
+++ b/gcc/tree-ssa-structalias.cc
@@ -5583,6 +5583,42 @@ find_func_clobbers (struct function *fn, gimple *origt)
process_ipa_clobber (fi, gimple_call_arg (t, 2));
return;
}
+ /* The following functions use what their first argument
+points to. */
+ case BUILT_IN_STRDUP:
+ case BUILT_IN_STRNDUP:
+ case BUILT_IN_REALLOC:
+ case BUILT_IN_INDEX:
+ case BUILT_IN_STRCHR:
+ case BUILT_IN_STRRCHR:
+ case BUILT_IN_MEMCHR:
+ {
+ tree src = gimple_call_arg (t, 0);
+ get_constraint_for_ptr_offset (src, NULL_TREE, &rhsc);
+ lhs = get_function_part_constraint (fi, fi_uses);
+ struct constraint_expr *rhsp;
+ FOR_EACH_VEC_ELT (rhsc, i, rhsp)
+ process_constraint (new_constraint (lhs, *rhsp));
+ return;
+ }
+ /* The following functions use what their first and second argument
+point to. */
+ case BUILT_IN_STRSTR:
+ case BUILT_IN_STRPBRK:
+ {
+ tree src = gimple_call_arg (t, 0);
+ get_constraint_for_ptr_offset (src, NULL_TREE, &rhsc);
+ lhs = get_function_part_constraint (fi, fi_uses);
+ struct constraint_expr *rhsp;
+ FOR_EACH_VEC_ELT (rhsc, i, rhsp)
+ process_constraint (new_constraint (lhs, *rhsp));
+ rhsc.truncate (0);
+ src = gimple_call_arg (t, 1);
+ get_constraint_for_ptr_offset (src, NULL_TREE, &rhsc);
+ FOR_EACH_VEC_ELT (rhsc, i, rhsp)
+ process_constraint (new_constraint (lhs, *rhsp));
+ return;
+ }
/* The following functions neither read nor clobber memory. */
case BUILT_IN_ASSUME_ALIGNED:
case BUILT_IN_FREE:
[gcc r16-305] tree-optimization/119960 - failed external SLP promotion
https://gcc.gnu.org/g:51ba233fe2db562390a6e0a3618420889761bc77
commit r16-305-g51ba233fe2db562390a6e0a3618420889761bc77
Author: Richard Biener
Date: Tue Apr 29 13:23:41 2025 +0200
tree-optimization/119960 - failed external SLP promotion
The following addresses a too conservative sanity check of SLP nodes
we want to promote external. The issue lies in code generation
for such external which relies on get_later_stmt to figure an
insert location. But get_later_stmt relies on the ability to
totally order stmts, specifically implementation-wise that they
are all from the same BB, which is what is verified at the moment.
The patch changes this to require stmts to be orderable by
dominance queries. For simplicity and seemingly enough for the
testcase in PR119960, this handles the case of two distinct BBs.
PR tree-optimization/119960
* tree-vect-slp.cc (vect_slp_can_convert_to_external):
Handle cases where defs from multiple BBs are ordered
by their dominance relation.
* gcc.dg/vect/bb-slp-pr119960-1.c: New testcase.
Diff:
---
gcc/testsuite/gcc.dg/vect/bb-slp-pr119960-1.c | 15 +++
gcc/tree-vect-slp.cc | 63 ---
2 files changed, 71 insertions(+), 7 deletions(-)
diff --git a/gcc/testsuite/gcc.dg/vect/bb-slp-pr119960-1.c
b/gcc/testsuite/gcc.dg/vect/bb-slp-pr119960-1.c
new file mode 100644
index ..955fc7e32208
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/vect/bb-slp-pr119960-1.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target vect_double } */
+
+double foo (double *dst, double *src, int b)
+{
+ double y = src[1];
+ if (b)
+{
+ dst[0] = src[0];
+ dst[1] = y;
+}
+ return y;
+}
+
+/* { dg-final { scan-tree-dump "optimized: basic block part vectorized" "slp2"
{ target vect_double } } } */
diff --git a/gcc/tree-vect-slp.cc b/gcc/tree-vect-slp.cc
index 19beeed8a3a9..ea30795f0647 100644
--- a/gcc/tree-vect-slp.cc
+++ b/gcc/tree-vect-slp.cc
@@ -7832,21 +7832,70 @@ vect_slp_analyze_node_operations_1 (vec_info *vinfo,
slp_tree node,
node, node_instance, cost_vec);
}
+static int
+sort_ints (const void *a_, const void *b_)
+{
+ int a = *(const int *)a_;
+ int b = *(const int *)b_;
+ return a - b;
+}
+
/* Verify if we can externalize a set of internal defs. */
static bool
vect_slp_can_convert_to_external (const vec &stmts)
{
+ /* Constant generation uses get_later_stmt which can only handle
+ defs from the same BB or a set of defs that can be ordered
+ with a dominance query. */
basic_block bb = NULL;
+ bool all_same = true;
+ auto_vec bbs;
+ bbs.reserve_exact (stmts.length ());
for (stmt_vec_info stmt : stmts)
-if (!stmt)
- return false;
-/* Constant generation uses get_later_stmt which can only handle
- defs from the same BB. */
-else if (!bb)
- bb = gimple_bb (stmt->stmt);
-else if (gimple_bb (stmt->stmt) != bb)
+{
+ if (!stmt)
+ return false;
+ else if (!bb)
+ bb = gimple_bb (stmt->stmt);
+ else if (gimple_bb (stmt->stmt) != bb)
+ all_same = false;
+ bbs.quick_push (gimple_bb (stmt->stmt)->index);
+}
+ if (all_same)
+return true;
+
+ /* Produce a vector of unique BB indexes for the defs. */
+ bbs.qsort (sort_ints);
+ unsigned i, j;
+ for (i = 1, j = 1; i < bbs.length (); ++i)
+if (bbs[i] != bbs[j-1])
+ bbs[j++] = bbs[i];
+ gcc_assert (j >= 2);
+ bbs.truncate (j);
+
+ if (bbs.length () == 2)
+return (dominated_by_p (CDI_DOMINATORS,
+ BASIC_BLOCK_FOR_FN (cfun, bbs[0]),
+ BASIC_BLOCK_FOR_FN (cfun, bbs[1]))
+ || dominated_by_p (CDI_DOMINATORS,
+ BASIC_BLOCK_FOR_FN (cfun, bbs[1]),
+ BASIC_BLOCK_FOR_FN (cfun, bbs[0])));
+
+ /* ??? For more than two BBs we can sort the vector and verify the
+ result is a total order. But we can't use vec::qsort with a
+ compare function using a dominance query since there's no way to
+ signal failure and any fallback for an unordered pair would
+ fail qsort_chk later.
+ For now simply hope that ordering after BB index provides the
+ best candidate total order. If required we can implement our
+ own mergesort or export an entry without checking. */
+ for (unsigned i = 1; i < bbs.length (); ++i)
+if (!dominated_by_p (CDI_DOMINATORS,
+BASIC_BLOCK_FOR_FN (cfun, bbs[i]),
+BASIC_BLOCK_FOR_FN (cfun, bbs[i-1])))
return false;
+
return true;
}
[gcc r16-306] tree-optimization/119960 - fix and guard get_later_stmt
https://gcc.gnu.org/g:a6cfde60d8c744b31b147022e797bbcc371ae092
commit r16-306-ga6cfde60d8c744b31b147022e797bbcc371ae092
Author: Richard Biener
Date: Tue Apr 29 14:52:27 2025 +0200
tree-optimization/119960 - fix and guard get_later_stmt
The following makes get_later_stmt handle stmts from different
basic-blocks in the case they are orderd and otherwise asserts.
* tree-vectorizer.h (get_later_stmt): Robustify against
stmts in different BBs, assert when they are unordered.
Diff:
---
gcc/tree-vectorizer.h | 20 +---
1 file changed, 17 insertions(+), 3 deletions(-)
diff --git a/gcc/tree-vectorizer.h b/gcc/tree-vectorizer.h
index 01d19c776561..94cbfde6c9a7 100644
--- a/gcc/tree-vectorizer.h
+++ b/gcc/tree-vectorizer.h
@@ -1870,11 +1870,25 @@ vect_orig_stmt (stmt_vec_info stmt_info)
inline stmt_vec_info
get_later_stmt (stmt_vec_info stmt1_info, stmt_vec_info stmt2_info)
{
- if (gimple_uid (vect_orig_stmt (stmt1_info)->stmt)
- > gimple_uid (vect_orig_stmt (stmt2_info)->stmt))
+ gimple *stmt1 = vect_orig_stmt (stmt1_info)->stmt;
+ gimple *stmt2 = vect_orig_stmt (stmt2_info)->stmt;
+ if (gimple_bb (stmt1) == gimple_bb (stmt2))
+{
+ if (gimple_uid (stmt1) > gimple_uid (stmt2))
+ return stmt1_info;
+ else
+ return stmt2_info;
+}
+ /* ??? We should be really calling this function only with stmts
+ in the same BB but we can recover if there's a domination
+ relationship between them. */
+ else if (dominated_by_p (CDI_DOMINATORS,
+ gimple_bb (stmt1), gimple_bb (stmt2)))
return stmt1_info;
- else
+ else if (dominated_by_p (CDI_DOMINATORS,
+ gimple_bb (stmt2), gimple_bb (stmt1)))
return stmt2_info;
+ gcc_unreachable ();
}
/* If STMT_INFO has been replaced by a pattern statement, return the
[gcc r15-9610] c++/modules: Catch exposures of TU-local values through inline references [PR119996]
https://gcc.gnu.org/g:3042862fbdba809473e3ea4ddc1697692b233d5f
commit r15-9610-g3042862fbdba809473e3ea4ddc1697692b233d5f
Author: Nathaniel Shead
Date: Tue Apr 29 17:31:55 2025 +1000
c++/modules: Catch exposures of TU-local values through inline references
[PR119996]
In r15-9136-g0210bedf481a9f we started erroring for inline variables
that exposed TU-local entities in their definition, as such variables
would need to have their definitions emitted in importers but would not
know about the TU-local entities they referenced.
A case we mised was potentially-constant references, which disable
streaming of their definitions in make_dependency so as to comply with
[expr.const] p9.2. This meant that we didn't see the definition
referencing a TU-local entity, leading to nonsensical results.
PR c++/119551
PR c++/119996
gcc/cp/ChangeLog:
* module.cc (depset::hash::make_dependency): Also mark inline
variables referencing TU-local values as exposures here.
(depset::hash::finalize_dependencies): Add error message for
inline variables.
gcc/testsuite/ChangeLog:
* g++.dg/modules/internal-13.C: New test.
Signed-off-by: Nathaniel Shead
Reviewed-by: Jason Merrill
(cherry picked from commit 22ccaded63e96e5a42f4e3676dbbb57aa05b36f9)
Diff:
---
gcc/cp/module.cc | 27 +---
gcc/testsuite/g++.dg/modules/internal-13.C | 33 ++
2 files changed, 53 insertions(+), 7 deletions(-)
diff --git a/gcc/cp/module.cc b/gcc/cp/module.cc
index a2e0d6d25718..7e3b24e2e42e 100644
--- a/gcc/cp/module.cc
+++ b/gcc/cp/module.cc
@@ -14062,9 +14062,10 @@ depset::hash::make_dependency (tree decl, entity_kind
ek)
streaming the definition in such cases. */
dep->clear_flag_bit ();
- if (DECL_DECLARED_CONSTEXPR_P (decl))
- /* Also, a constexpr variable initialized to a TU-local
- value is an exposure. */
+ if (DECL_DECLARED_CONSTEXPR_P (decl)
+ || DECL_INLINE_VAR_P (decl))
+ /* A constexpr variable initialized to a TU-local value,
+ or an inline value (PR c++/119996), is an exposure. */
dep->set_flag_bit ();
}
}
@@ -15025,12 +15026,24 @@ depset::hash::finalize_dependencies ()
break;
}
- if (!explained && VAR_P (decl) && DECL_DECLARED_CONSTEXPR_P (decl))
+ if (!explained
+ && VAR_P (decl)
+ && (DECL_DECLARED_CONSTEXPR_P (decl)
+ || DECL_INLINE_VAR_P (decl)))
{
auto_diagnostic_group d;
- error_at (DECL_SOURCE_LOCATION (decl),
- "%qD is declared % and is initialized to "
- "a TU-local value", decl);
+ if (DECL_DECLARED_CONSTEXPR_P (decl))
+ error_at (DECL_SOURCE_LOCATION (decl),
+ "%qD is declared % and is initialized to "
+ "a TU-local value", decl);
+ else
+ {
+ /* This can only occur with references. */
+ gcc_checking_assert (TYPE_REF_P (TREE_TYPE (decl)));
+ error_at (DECL_SOURCE_LOCATION (decl),
+ "%qD is a reference declared % and is "
+ "constant-initialized to a TU-local value", decl);
+ }
bool informed = is_tu_local_value (decl, DECL_INITIAL (decl),
/*explain=*/true);
gcc_checking_assert (informed);
diff --git a/gcc/testsuite/g++.dg/modules/internal-13.C
b/gcc/testsuite/g++.dg/modules/internal-13.C
new file mode 100644
index ..ce1454e17bc9
--- /dev/null
+++ b/gcc/testsuite/g++.dg/modules/internal-13.C
@@ -0,0 +1,33 @@
+// PR c++/119996
+// { dg-additional-options "-fmodules" }
+// { dg-module-cmi !M }
+// Similar to internal-11.C, but for potentially-constant variables.
+
+export module M;
+
+static int tu_local = 5;
+static int& foo() { return tu_local; }
+
+// For implementation reasons, we adjust [basic.link] p14.2 to restrict ignored
+// exposures to non-inline variables, since for inline variables without
+// dynamic initialisation we need to emit their initialiser for importer use.
+
+int& a = tu_local; // OK
+inline int& b = tu_local; // { dg-error "initialized to a TU-local value" }
+inline auto& bf = foo; // { dg-error "initialized to a TU-local value" }
+
+// But dynamic initialisers are fine, importers will just treat them as
external.
+inline int& c = foo(); // OK
+
+// For consistency, we follow the same rules with templates, noting that
+// we still need to emit definitions with dynamic ini
[gcc r16-321] combine: Special case set_noop_p in two spots
https://gcc.gnu.org/g:79aa2a283a8d3327ff4d6dca77e81d5b1ac3a01e
commit r16-321-g79aa2a283a8d3327ff4d6dca77e81d5b1ac3a01e
Author: Jakub Jelinek
Date: Thu May 1 08:29:03 2025 +0200
combine: Special case set_noop_p in two spots
Here is the incremental patch I was talking about.
For noop sets, we don't need to test much, they can go to i2
unless that would violate i3 JUMP condition.
With this the try_combine on the pr119291.c testcase doesn't fail,
but succeeds and we get
(insn 22 21 23 4 (set (pc)
(pc)) "pr119291.c":27:15 2147483647 {NOOP_MOVE}
(nil))
(insn 23 22 24 4 (set (reg/v:SI 117 [ e ])
(reg/v:SI 116 [ e ])) 96 {*movsi_internal}
(expr_list:REG_DEAD (reg/v:SI 116 [ e ])
(nil)))
(note 24 23 25 4 NOTE_INSN_DELETED)
(insn 25 24 26 4 (set (reg/v:SI 116 [ e ])
(const_int 0 [0])) "pr119291.c":28:13 96 {*movsi_internal}
(nil))
(note 26 25 27 4 NOTE_INSN_DELETED)
(insn 27 26 28 4 (set (reg:DI 128 [ _9 ])
(const_int 0 [0])) "pr119291.c":28:13 95 {*movdi_internal}
(nil))
after it.
2025-05-01 Jakub Jelinek
* combine.cc (try_combine): Sets which satisfy set_noop_p can go
to i2 unless i3 is a jump and the other set is not.
Diff:
---
gcc/combine.cc | 40
1 file changed, 20 insertions(+), 20 deletions(-)
diff --git a/gcc/combine.cc b/gcc/combine.cc
index 873c2bdd4698..67cf0447607f 100644
--- a/gcc/combine.cc
+++ b/gcc/combine.cc
@@ -4020,34 +4020,34 @@ try_combine (rtx_insn *i3, rtx_insn *i2, rtx_insn *i1,
rtx_insn *i0,
in i3, so we need to make sure that we won't wrongly hoist a SET
to i2 that would conflict with a death note present in there, or
would have its dest modified or used between i2 and i3. */
- if (!modified_between_p (SET_SRC (set1), i2, i3)
- && !(REG_P (SET_DEST (set1))
- && find_reg_note (i2, REG_DEAD, SET_DEST (set1)))
- && !(GET_CODE (SET_DEST (set1)) == SUBREG
- && find_reg_note (i2, REG_DEAD,
-SUBREG_REG (SET_DEST (set1
- && SET_DEST (set1) != pc_rtx
- && !reg_used_between_p (SET_DEST (set1), i2, i3)
+ if ((set_noop_p (set1)
+ || (!modified_between_p (SET_SRC (set1), i2, i3)
+ && !(REG_P (SET_DEST (set1))
+ && find_reg_note (i2, REG_DEAD, SET_DEST (set1)))
+ && !(GET_CODE (SET_DEST (set1)) == SUBREG
+ && find_reg_note (i2, REG_DEAD,
+ SUBREG_REG (SET_DEST (set1
+ && SET_DEST (set1) != pc_rtx
+ && !reg_used_between_p (SET_DEST (set1), i2, i3)))
/* If I3 is a jump, ensure that set0 is a jump so that
we do not create invalid RTL. */
- && (!JUMP_P (i3) || SET_DEST (set0) == pc_rtx)
-)
+ && (!JUMP_P (i3) || SET_DEST (set0) == pc_rtx))
{
newi2pat = set1;
newpat = set0;
}
- else if (!modified_between_p (SET_SRC (set0), i2, i3)
- && !(REG_P (SET_DEST (set0))
- && find_reg_note (i2, REG_DEAD, SET_DEST (set0)))
- && !(GET_CODE (SET_DEST (set0)) == SUBREG
- && find_reg_note (i2, REG_DEAD,
- SUBREG_REG (SET_DEST (set0
- && SET_DEST (set0) != pc_rtx
- && !reg_used_between_p (SET_DEST (set0), i2, i3)
+ else if ((set_noop_p (set0)
+ || (!modified_between_p (SET_SRC (set0), i2, i3)
+ && !(REG_P (SET_DEST (set0))
+&& find_reg_note (i2, REG_DEAD, SET_DEST (set0)))
+ && !(GET_CODE (SET_DEST (set0)) == SUBREG
+&& find_reg_note (i2, REG_DEAD,
+ SUBREG_REG (SET_DEST (set0
+ && SET_DEST (set0) != pc_rtx
+ && !reg_used_between_p (SET_DEST (set0), i2, i3)))
/* If I3 is a jump, ensure that set1 is a jump so that
we do not create invalid RTL. */
- && (!JUMP_P (i3) || SET_DEST (set1) == pc_rtx)
- )
+ && (!JUMP_P (i3) || SET_DEST (set1) == pc_rtx))
{
newi2pat = set0;
newpat = set1;
[gcc/meissner/heads/work204-sha] (16 commits) Merge commit 'refs/users/meissner/heads/work204-sha' of git
The branch 'meissner/heads/work204-sha' was updated to point to: cfb8b04b754e... Merge commit 'refs/users/meissner/heads/work204-sha' of git It previously pointed to: e6542a9af5f3... Add ChangeLog.sha and update REVISION. Diff: Summary of changes (added commits): --- cfb8b04... Merge commit 'refs/users/meissner/heads/work204-sha' of git 8445ba1... Add ChangeLog.sha and update REVISION. baa1f20... Update ChangeLog.* (*) e3fed9c... Use architecture flags for defining _ARCH_PWR macros. (*) 2fc3592... Add rs6000 architecture masks. (*) cdecb01... Use vector pair load/store for memcpy with -mcpu=future (*) 5033551... Add -mcpu=future tests. (*) 9f2d754... Add -mcpu=future tuning support. (*) 268f13e... Add support for -mcpu=future (*) ef1deb7... Revert changes (*) 50c706a... Add support for -mcpu=future (*) e0ceb14... Change TARGET_MODULO to TARGET_POWER9. (*) 30bfb83... Change TARGET_POPCNTD to TARGET_POWER7. (*) fbdcdf4... Change TARGET_CMPB to TARGET_POWER6. (*) dc94b44... Change TARGET_FPRND to TARGET_POWER5X. (*) 577e4ee... Change TARGET_POPCNTB to TARGET_POWER5. (*) (*) This commit already exists in another branch. Because the reference `refs/users/meissner/heads/work204-sha' matches your hooks.email-new-commits-only configuration, no separate email is sent for this commit.
[gcc r12-11079] sra: Clear grp_same_access_path of acesses created by total scalarization (PR118924)
https://gcc.gnu.org/g:d4d12a548f210371609e85f6d2f4f3ee0e2b04f2 commit r12-11079-gd4d12a548f210371609e85f6d2f4f3ee0e2b04f2 Author: Martin Jambor Date: Mon Apr 7 13:32:10 2025 +0200 sra: Clear grp_same_access_path of acesses created by total scalarization (PR118924) During analysis of PR 118924 it was discussed that total scalarization invents access paths (strings of COMPONENT_REFs and possibly even ARRAY_REFs) which did not exist in the program before which can have unintended effects on subsequent AA queries. Although not doing that does not mean that SRA cannot create such situations (see the bug for more info), it has been agreed that not doing this is generally better. This patch therfore makes SRA fall back on creating simple MEM_REFs when accessing components of an aggregate corresponding to what a SRA variable now represents. gcc/ChangeLog: 2025-03-26 Martin Jambor PR tree-optimization/118924 * tree-sra.cc (create_total_scalarization_access): Set grp_same_access_path flag to zero. (cherry picked from commit 40445711b8af113ef423d8bcac1a7ce1c47f62d7) Diff: --- gcc/tree-sra.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gcc/tree-sra.cc b/gcc/tree-sra.cc index 5a9eaf31b6e9..91af2aef8b4c 100644 --- a/gcc/tree-sra.cc +++ b/gcc/tree-sra.cc @@ -3130,7 +3130,7 @@ create_total_scalarization_access (struct access *parent, HOST_WIDE_INT pos, access->grp_write = parent->grp_write; access->grp_total_scalarization = 1; access->grp_hint = 1; - access->grp_same_access_path = path_comparable_for_same_access (expr); + access->grp_same_access_path = 0; access->reverse = reverse_storage_order_for_component_p (expr); access->next_sibling = next_sibling;
[gcc/meissner/heads/work204-cmodel] (16 commits) Merge commit 'refs/users/meissner/heads/work204-cmodel' of
The branch 'meissner/heads/work204-cmodel' was updated to point to: 33ab968f8f66... Merge commit 'refs/users/meissner/heads/work204-cmodel' of It previously pointed to: a36c6b6e956e... Add ChangeLog.cmodel and update REVISION. Diff: Summary of changes (added commits): --- 33ab968... Merge commit 'refs/users/meissner/heads/work204-cmodel' of e1f85bb... Add ChangeLog.cmodel and update REVISION. baa1f20... Update ChangeLog.* (*) e3fed9c... Use architecture flags for defining _ARCH_PWR macros. (*) 2fc3592... Add rs6000 architecture masks. (*) cdecb01... Use vector pair load/store for memcpy with -mcpu=future (*) 5033551... Add -mcpu=future tests. (*) 9f2d754... Add -mcpu=future tuning support. (*) 268f13e... Add support for -mcpu=future (*) ef1deb7... Revert changes (*) 50c706a... Add support for -mcpu=future (*) e0ceb14... Change TARGET_MODULO to TARGET_POWER9. (*) 30bfb83... Change TARGET_POPCNTD to TARGET_POWER7. (*) fbdcdf4... Change TARGET_CMPB to TARGET_POWER6. (*) dc94b44... Change TARGET_FPRND to TARGET_POWER5X. (*) 577e4ee... Change TARGET_POPCNTB to TARGET_POWER5. (*) (*) This commit already exists in another branch. Because the reference `refs/users/meissner/heads/work204-cmodel' matches your hooks.email-new-commits-only configuration, no separate email is sent for this commit.
[gcc(refs/users/meissner/heads/work204-cmodel)] Merge commit 'refs/users/meissner/heads/work204-cmodel' of git+ssh://gcc.gnu.org/git/gcc into me/wor
https://gcc.gnu.org/g:33ab968f8f66d392b9d07669bd0ff9326bd8bd7b commit 33ab968f8f66d392b9d07669bd0ff9326bd8bd7b Merge: e1f85bb68cee a36c6b6e956e Author: Michael Meissner Date: Wed Apr 30 16:35:31 2025 -0400 Merge commit 'refs/users/meissner/heads/work204-cmodel' of git+ssh://gcc.gnu.org/git/gcc into me/work204-cmodel Diff:
[gcc(refs/users/meissner/heads/work204-cmodel)] Add ChangeLog.cmodel and update REVISION.
https://gcc.gnu.org/g:e1f85bb68cee6486a8543eb2f3ddfc579764b153 commit e1f85bb68cee6486a8543eb2f3ddfc579764b153 Author: Michael Meissner Date: Wed Apr 30 13:56:22 2025 -0400 Add ChangeLog.cmodel and update REVISION. 2025-04-30 Michael Meissner gcc/ * ChangeLog.cmodel: New file for branch. * REVISION: Update. Diff: --- gcc/ChangeLog.cmodel | 5 + gcc/REVISION | 2 +- 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog.cmodel b/gcc/ChangeLog.cmodel new file mode 100644 index ..de19de309b5d --- /dev/null +++ b/gcc/ChangeLog.cmodel @@ -0,0 +1,5 @@ + Branch work204-cmodel, baseline + +2025-04-30 Michael Meissner + + Clone branch diff --git a/gcc/REVISION b/gcc/REVISION index d4f18d737afd..69ecbb984c4b 100644 --- a/gcc/REVISION +++ b/gcc/REVISION @@ -1 +1 @@ -work204 branch +work204-cmodel branch
[gcc r16-314] sarif output: introduce sarif_serialization_format
https://gcc.gnu.org/g:e504a59bd149f8def875f8924db8fa0c2a164c11
commit r16-314-ge504a59bd149f8def875f8924db8fa0c2a164c11
Author: David Malcolm
Date: Wed Apr 30 16:50:16 2025 -0400
sarif output: introduce sarif_serialization_format
The SARIF 2.1.0 spec says that although a "SARIF log file SHALL contain
a serialization of the SARIF object model into the JSON format ... in the
future, other serializations might be defined." (§3.1)
I've been experimenting with alternative serializations of SARIF (CBOR
and JSON5 for now). To help with these experiments, this patch adds a
new param "serialization" to -fdiagnostics-add-output='s "sarif" scheme.
For now this must have value "json", but will be helpful for any
followup patches.
gcc/ChangeLog:
* diagnostic-format-sarif.cc
(sarif_serialization_format_json::write_to_file): New.
(sarif_builder::m_formatted): Replace field with...
(sarif_builder::m_serialization_format): ...this.
(sarif_builder::sarif_builder): Update for field change.
(sarif_builder::flush_to_file): Call m_serialization_format's
write_to_file vfunc.
(sarif_output_format::sarif_output_format): Replace param
"formatted" with "serialization_format".
(sarif_stream_output_format::sarif_output_format): Likewise.
(sarif_file_output_format::sarif_file_output_format): Likewise.
(diagnostic_output_format_init_sarif_stderr): Make a
sarif_serialization_format_json and pass it to
diagnostic_output_format_init_sarif.
(diagnostic_output_format_open_sarif_file): Split out into...
(diagnostic_output_file::try_to_open): ...this, adding
"serialization_kind" param.
(diagnostic_output_format_init_sarif_file): Update for new param
to diagnostic_output_format_open_sarif_file. Make a
sarif_serialization_format_json and pass it to
diagnostic_output_format_init_sarif.
(diagnostic_output_format_init_sarif_stream): Make a
sarif_serialization_format_json and pass it to
diagnostic_output_format_init_sarif.
(make_sarif_sink): Replace param "formatted" with "serialization".
(selftest::test_make_location_object): Update for changes to
sarif_builder ctor.
* diagnostic-format-sarif.h (enum class sarif_serialization): New.
(diagnostic_output_format_open_sarif_file): Add param
"serialization_kind".
(class sarif_serialization_format): New.
(class sarif_serialization_format_json): New.
(make_sarif_sink): Replace param "formatted" with
"serialization_format".
* diagnostic-output-file.h (diagnostic_output_file::try_to_open):
New decl.
* diagnostic.h (enum diagnostics_output_format): Tweak comments.
* doc/invoke.texi (-fdiagnostics-add-output): Add "serialization"
param to sarif scheme.
* libgdiagnostics.cc (sarif_sink::sarif_sink): Update for change
to make_sarif_sink.
* opts-diagnostic.cc (sarif_scheme_handler::make_sink): Add
"serialization" param and pass it on to make_sarif_sink.
Signed-off-by: David Malcolm
Diff:
---
gcc/diagnostic-format-sarif.cc | 115 ++---
gcc/diagnostic-format-sarif.h | 42 ++-
gcc/diagnostic-output-file.h | 7 +++
gcc/diagnostic.h | 4 +-
gcc/doc/invoke.texi| 5 ++
gcc/libgdiagnostics.cc | 3 +-
gcc/opts-diagnostic.cc | 33 +++-
7 files changed, 173 insertions(+), 36 deletions(-)
diff --git a/gcc/diagnostic-format-sarif.cc b/gcc/diagnostic-format-sarif.cc
index f322991ab2ea..bc6abdff5e4e 100644
--- a/gcc/diagnostic-format-sarif.cc
+++ b/gcc/diagnostic-format-sarif.cc
@@ -634,6 +634,18 @@ private:
std::vector> m_results;
};
+/* Classes for abstracting away JSON vs other serialization formats. */
+
+// class sarif_serialization_format_json : public sarif_serialization_format
+
+void
+sarif_serialization_format_json::write_to_file (FILE *outf,
+ const json::value &top)
+{
+ top.dump (outf, m_formatted);
+ fprintf (outf, "\n");
+}
+
/* A class for managing SARIF output (for -fdiagnostics-format=sarif-stderr
and -fdiagnostics-format=sarif-file).
@@ -687,7 +699,7 @@ public:
pretty_printer &printer,
const line_maps *line_maps,
const char *main_input_filename_,
-bool formatted,
+std::unique_ptr
serialization_format,
const sarif_generation_options &sarif_gen_opts);
~sarif_builder ();
@@ -891,7 +903,7 @@ private:
int m_tabstop;
- bool m_formatted;
+ std::uniq
[gcc r16-315] prime-paths.cc: remove redundant semicolons
https://gcc.gnu.org/g:49d2c6ced2c894a8fe21ec0a21c1458cb3086ee8
commit r16-315-g49d2c6ced2c894a8fe21ec0a21c1458cb3086ee8
Author: David Malcolm
Date: Wed Apr 30 16:50:17 2025 -0400
prime-paths.cc: remove redundant semicolons
Fixes a couple of pedantic warnings.
gcc/ChangeLog:
* prime-paths.cc (limit_checked_add): Remove redundant trailing
';'.
(enters_through_p): Likewise.
Signed-off-by: David Malcolm
Diff:
---
gcc/prime-paths.cc | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/gcc/prime-paths.cc b/gcc/prime-paths.cc
index cde630cb5e08..838343c8427d 100644
--- a/gcc/prime-paths.cc
+++ b/gcc/prime-paths.cc
@@ -53,7 +53,7 @@ limit_checked_add (size_t approx)
{
approx_limit -= approx < approx_limit ? approx : approx_limit;
return approx_limit == 0;
-};
+}
/* Check if adding APPROX would exceed the path limit. This is necessary when
(pessimistically counted) trie insertions would exceed the limit and yields
@@ -1061,7 +1061,7 @@ enters_through_p (const struct graph *cfg, const vec
&path, int vertex)
if (cfg->vertices[last].component == cfg->vertices[vertex].component)
return false;
return edge_p (cfg, last, vertex);
-};
+}
/* Worker for scc_entry_prime_paths. CFG is the CFG for the function,
SCC_ENTRY_PATHS the accumulated scc_entry_paths for all the SCCs,
PRIME_PATHS
[gcc r16-312] analyzer: avoid saying "'0' is NULL"
https://gcc.gnu.org/g:039ba6580f5328acbca4f498f9d5d6055bf59ffa
commit r16-312-g039ba6580f5328acbca4f498f9d5d6055bf59ffa
Author: David Malcolm
Date: Wed Apr 30 16:50:15 2025 -0400
analyzer: avoid saying "'0' is NULL"
gcc/analyzer/ChangeLog:
* sm-malloc.cc (malloc_diagnostic::describe_state_change): Tweak
the "EXPR is NULL" message for the case where EXPR is a null
pointer.
gcc/testsuite/ChangeLog:
* c-c++-common/analyzer/data-model-path-1.c: Check for
"using NULL here" message.
*
c-c++-common/analyzer/null-deref-pr108251-smp_fetch_ssl_fc_has_early.c:
Likewise. Check for "return of NULL" message.
* c-c++-common/analyzer/null-deref-pr108400-SoftEtherVPN-WebUi.c:
Likewise.
* gcc.dg/analyzer/data-model-5.c: Likewise.
* gcc.dg/analyzer/data-model-5b.c: Likewise.
* gcc.dg/analyzer/data-model-5c.c: Likewise.
* gcc.dg/analyzer/torture/pr93647.c: Likewise.
Signed-off-by: David Malcolm
Diff:
---
gcc/analyzer/sm-malloc.cc| 9 +++--
gcc/testsuite/c-c++-common/analyzer/data-model-path-1.c | 2 +-
.../analyzer/null-deref-pr108251-smp_fetch_ssl_fc_has_early.c| 4 ++--
.../analyzer/null-deref-pr108400-SoftEtherVPN-WebUi.c| 2 +-
gcc/testsuite/gcc.dg/analyzer/data-model-5.c | 2 +-
gcc/testsuite/gcc.dg/analyzer/data-model-5b.c| 2 +-
gcc/testsuite/gcc.dg/analyzer/data-model-5c.c| 2 +-
gcc/testsuite/gcc.dg/analyzer/torture/pr93647.c | 2 +-
8 files changed, 15 insertions(+), 10 deletions(-)
diff --git a/gcc/analyzer/sm-malloc.cc b/gcc/analyzer/sm-malloc.cc
index 01862686d58e..333dfea47d34 100644
--- a/gcc/analyzer/sm-malloc.cc
+++ b/gcc/analyzer/sm-malloc.cc
@@ -785,8 +785,13 @@ public:
else
{
if (change.m_expr)
- pp_printf (&pp, "%qE is NULL",
-change.m_expr);
+ {
+ if (zerop (change.m_expr))
+ pp_printf (&pp, "using NULL here");
+ else
+ pp_printf (&pp, "%qE is NULL",
+change.m_expr);
+ }
else
pp_printf (&pp, "%qs is NULL",
"");
diff --git a/gcc/testsuite/c-c++-common/analyzer/data-model-path-1.c
b/gcc/testsuite/c-c++-common/analyzer/data-model-path-1.c
index d7058ea18e03..0609dc8cb4f7 100644
--- a/gcc/testsuite/c-c++-common/analyzer/data-model-path-1.c
+++ b/gcc/testsuite/c-c++-common/analyzer/data-model-path-1.c
@@ -3,7 +3,7 @@
static int *__attribute__((noinline))
callee (void)
{
- return NULL;
+ return NULL; /* { dg-message "using NULL here" } */
}
void test_1 (void)
diff --git
a/gcc/testsuite/c-c++-common/analyzer/null-deref-pr108251-smp_fetch_ssl_fc_has_early.c
b/gcc/testsuite/c-c++-common/analyzer/null-deref-pr108251-smp_fetch_ssl_fc_has_early.c
index c5f1fa42e6f1..4f04e46695e4 100644
---
a/gcc/testsuite/c-c++-common/analyzer/null-deref-pr108251-smp_fetch_ssl_fc_has_early.c
+++
b/gcc/testsuite/c-c++-common/analyzer/null-deref-pr108251-smp_fetch_ssl_fc_has_early.c
@@ -66,7 +66,7 @@ static inline struct connection *__objt_conn(enum obj_type *t)
static inline struct connection *objt_conn(enum obj_type *t)
{
if (!t || *t != OBJ_TYPE_CONN)
- return (struct connection *) ((void *)0);
+ return (struct connection *) ((void *)0); /* { dg-message "using NULL here"
} */
return __objt_conn(t);
}
struct session {
@@ -85,7 +85,7 @@ smp_fetch_ssl_fc_has_early(const struct arg *args, struct
sample *smp, const cha
SSL *ssl;
struct connection *conn;
- conn = objt_conn(smp->sess->origin);
+ conn = objt_conn(smp->sess->origin); /* { dg-message "return of NULL" } */
ssl = ssl_sock_get_ssl_object(conn);
if (!ssl)
return 0;
diff --git
a/gcc/testsuite/c-c++-common/analyzer/null-deref-pr108400-SoftEtherVPN-WebUi.c
b/gcc/testsuite/c-c++-common/analyzer/null-deref-pr108400-SoftEtherVPN-WebUi.c
index 9dcf7aa31f10..0ebeeff8348c 100644
---
a/gcc/testsuite/c-c++-common/analyzer/null-deref-pr108400-SoftEtherVPN-WebUi.c
+++
b/gcc/testsuite/c-c++-common/analyzer/null-deref-pr108400-SoftEtherVPN-WebUi.c
@@ -60,7 +60,7 @@ void WuExpireSessionKey(WEBUI *wu)
for(i=0; iContexts); i++)
{
- STRMAP_ENTRY *entry = (STRMAP_ENTRY*)LIST_DATA(wu->Contexts, i);
+ STRMAP_ENTRY *entry = (STRMAP_ENTRY*)LIST_DATA(wu->Contexts,
i); /* { dg-message "'entry' is NULL" } */
WU_CONTEXT *context = (WU_CONTEXT*)entry->Value; /* { dg-bogus
"dereference of NULL 'entry'" "PR analyzer/108400" { xfail *-*-* } } */
if(context->ExpireDate < Tick64())
{
diff --git a/gcc/testsuite/gcc.dg/analyzer/data-model-5.c
b/gcc/testsuite/gcc.dg/analyzer/data-model-5.c
index b71bad757a19..78e
[gcc r16-313] analyzer: add more test coverage for sprintf
https://gcc.gnu.org/g:8c80fc106482dd38c09f0e5a45b6d4dcb3498e50
commit r16-313-g8c80fc106482dd38c09f0e5a45b6d4dcb3498e50
Author: David Malcolm
Date: Wed Apr 30 16:50:16 2025 -0400
analyzer: add more test coverage for sprintf
gcc/testsuite/ChangeLog:
PR analyzer/107017
* c-c++-common/analyzer/sprintf-3.c: New test, covering use of
sprintf with specific format strings. Doesn't yet find problems
as the analyzer doesn't yet understand the format strings.
Signed-off-by: David Malcolm
Diff:
---
gcc/testsuite/c-c++-common/analyzer/sprintf-3.c | 44 +
1 file changed, 44 insertions(+)
diff --git a/gcc/testsuite/c-c++-common/analyzer/sprintf-3.c
b/gcc/testsuite/c-c++-common/analyzer/sprintf-3.c
new file mode 100644
index ..ac5169e71b87
--- /dev/null
+++ b/gcc/testsuite/c-c++-common/analyzer/sprintf-3.c
@@ -0,0 +1,44 @@
+/* See e.g. https://en.cppreference.com/w/c/io/fprintf
+ and https://www.man7.org/linux/man-pages/man3/sprintf.3.html */
+
+extern int
+sprintf(char* dst, const char* fmt, ...)
+ __attribute__((__nothrow__));
+
+#include "../../gcc.dg/analyzer/analyzer-decls.h"
+
+void test_text_ok (void)
+{
+ char buf[16];
+ sprintf (buf, "hello world");
+}
+
+void test_text_oob (void)
+{
+ char buf[3];
+ sprintf (buf, "hello world"); /* { dg-warning "out-of-bounds" "PR
analyzer/107017" { xfail *-*-* } } */
+}
+
+void test_percent_s_ok (void)
+{
+ char buf[16];
+ sprintf (buf, "%s", "foo");
+}
+
+void test_percent_s_oob (void)
+{
+ char buf[3];
+ sprintf (buf, "%s", "foo"); /* { dg-warning "out-of-bounds" "PR
analyzer/107017" { xfail *-*-* } } */
+}
+
+void test_percent_i_ok (void)
+{
+ char buf[16];
+ sprintf (buf, "%i", "42");
+}
+
+void test_percent_i_oob (void)
+{
+ char buf[4];
+ sprintf (buf, "%i", "1066"); /* { dg-warning "out-of-bounds" "PR
analyzer/107017" { xfail *-*-* } } */
+}
[gcc r14-11707] Fortran: pure subroutine with pure procedure as dummy [PR106948]
https://gcc.gnu.org/g:475cec322340e7082d85683dbaa44f00e4736bf6
commit r14-11707-g475cec322340e7082d85683dbaa44f00e4736bf6
Author: Harald Anlauf
Date: Tue Apr 15 20:43:05 2025 +0200
Fortran: pure subroutine with pure procedure as dummy [PR106948]
PR fortran/106948
gcc/fortran/ChangeLog:
* resolve.cc (gfc_pure_function): If a function has been resolved,
but esym is not yet set, look at its attributes to see whether it
is pure or elemental.
gcc/testsuite/ChangeLog:
* gfortran.dg/pure_formal_proc_4.f90: New test.
(cherry picked from commit 4e3060ee17e6eb8bab718d320199f713533dbbd6)
Diff:
---
gcc/fortran/resolve.cc | 7
gcc/testsuite/gfortran.dg/pure_formal_proc_4.f90 | 49
2 files changed, 56 insertions(+)
diff --git a/gcc/fortran/resolve.cc b/gcc/fortran/resolve.cc
index 6a47550b613e..4f4decd1bc39 100644
--- a/gcc/fortran/resolve.cc
+++ b/gcc/fortran/resolve.cc
@@ -3155,6 +3155,13 @@ gfc_pure_function (gfc_expr *e, const char **name)
|| e->value.function.isym->elemental;
*name = e->value.function.isym->name;
}
+ else if (e->symtree && e->symtree->n.sym && e->symtree->n.sym->attr.dummy)
+{
+ /* The function has been resolved, but esym is not yet set.
+This can happen with functions as dummy argument. */
+ pure = e->symtree->n.sym->attr.pure;
+ *name = e->symtree->n.sym->name;
+}
else
{
/* Implicit functions are not pure. */
diff --git a/gcc/testsuite/gfortran.dg/pure_formal_proc_4.f90
b/gcc/testsuite/gfortran.dg/pure_formal_proc_4.f90
new file mode 100644
index ..92640e2d2f4a
--- /dev/null
+++ b/gcc/testsuite/gfortran.dg/pure_formal_proc_4.f90
@@ -0,0 +1,49 @@
+! { dg-do compile }
+! PR fortran/106948 - check that passing of PURE procedures works
+!
+! Contributed by Jim Feng
+
+module a
+ implicit none
+
+ interface new
+pure module subroutine b(x, f)
+ integer, intent(inout) :: x
+ interface
+pure function f(x) result(r)
+ real, intent(in) :: x
+ real :: r
+end function f
+ end interface
+end subroutine b
+ end interface new
+end module a
+
+submodule(a) a_b
+ implicit none
+
+contains
+ module procedure b
+x = int(f(real(x)) * 0.15)
+ end procedure b
+end submodule a_b
+
+program test
+ use a
+ implicit none
+
+ integer :: x
+
+ x = 100
+ call new(x, g)
+ print *, x
+
+contains
+
+ pure function g(y) result(r)
+real, intent(in) :: y
+real :: r
+
+r = sqrt(y)
+ end function g
+end program test
[gcc r16-316] vectorizer: Fix riscv build [PR120042]
https://gcc.gnu.org/g:299d48ff4a34c00a6ef964b694fb9b1312683049
commit r16-316-g299d48ff4a34c00a6ef964b694fb9b1312683049
Author: Andrew Pinski
Date: Wed Apr 30 15:10:29 2025 -0700
vectorizer: Fix riscv build [PR120042]
r15-9859-ga6cfde60d8c added a call to dominated_by_p to tree-vectorizer.h
but dominance.h is not always included; and you get a build failure on
riscv building
riscv-vector-costs.cc.
Let's add the include of dominance.h to tree-vectorizer.h
Pushed as obvious after builds for riscv and x86_64.
gcc/ChangeLog:
PR target/120042
* tree-vectorizer.h: Include dominance.h.
Signed-off-by: Andrew Pinski
Diff:
---
gcc/tree-vectorizer.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/gcc/tree-vectorizer.h b/gcc/tree-vectorizer.h
index 94cbfde6c9a7..63991c3d9775 100644
--- a/gcc/tree-vectorizer.h
+++ b/gcc/tree-vectorizer.h
@@ -30,6 +30,7 @@ typedef struct _slp_tree *slp_tree;
#include "internal-fn.h"
#include "tree-ssa-operands.h"
#include "gimple-match.h"
+#include "dominance.h"
/* Used for naming of new temporaries. */
enum vect_var_kind {
[gcc(refs/users/meissner/heads/work204-sha)] RFC2653-Add wD constraint.
https://gcc.gnu.org/g:dfa66a67f05541c6dd0d3d560e86eeed6b664aa5
commit dfa66a67f05541c6dd0d3d560e86eeed6b664aa5
Author: Michael Meissner
Date: Wed Apr 30 20:14:54 2025 -0400
RFC2653-Add wD constraint.
This patch adds a new constraint ('wD') that matches the accumulator
registers
that overlap with VSX registers 0..31 on power10. Future patches will add
the
support for a separate accumulator register class that will be used when the
support for dense math registes is added.
2025-04-30 Michael Meissner
* config/rs6000/constraints.md (wD): New constraint.
* config/rs6000/mma.md (mma_): Prepare for alternate
accumulator
registers. Use wD constraint instead of 'd' constraint. Use
accumulator_operand instead of fpr_reg_operand.
(mma_): Likewise.
(mma_): Likewise.
(mma_): Likewise.
(mma_): Likewise.
(mma_): Likewise.
(mma_): Likewise.
(mma_): Likewise.
(mma_): Likewise.
(mma_): Likewise.
(mma_): Likewise.
(mma_): Likewise.
(mma_): Likewise.
(mma_"
- [(set (match_operand:XO 0 "fpr_reg_operand" "=&d")
- (unspec:XO [(match_operand:XO 1 "fpr_reg_operand" "0")]
+ [(set (match_operand:XO 0 "accumulator_operand" "=&wD")
+ (unspec:XO [(match_operand:XO 1 "accumulator_operand" "0")]
MMA_ACC))]
"TARGET_MMA"
" %A0"
@@ -523,7 +523,7 @@
[(set_attr "type" "mma")])
(define_insn "mma_"
- [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d")
+ [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
(unspec:XO [(match_operand:V16QI 1 "vsx_register_operand" "v,?wa")
(match_operand:V16QI 2 "vsx_register_operand" "v,?wa")]
MMA_VV))]
@@ -532,8 +532,8 @@
[(set_attr "type" "mma")])
(define_insn "mma_"
- [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d")
- (unspec:XO [(match_operand:XO 1 "fpr_reg_operand" "0,0")
+ [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
+ (unspec:XO [(match_operand:XO 1 "accumulator_operand" "0,0")
(match_operand:V16QI 2 "vsx_register_operand" "v,?wa")
(match_operand:V16QI 3 "vsx_register_operand" "v,?wa")]
MMA_AVV))]
@@ -542,7 +542,7 @@
[(set_attr "type" "mma")])
(define_insn "mma_"
- [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d")
+ [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
(unspec:XO [(match_operand:OO 1 "vsx_register_operand" "v,?wa")
(match_operand:V16QI 2 "vsx_register_operand" "v,?wa")]
MMA_PV))]
@@ -551,8 +551,8 @@
[(set_attr "type" "mma")])
(define_insn "mma_"
- [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d")
- (unspec:XO [(match_operand:XO 1 "fpr_reg_operand" "0,0")
+ [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
+ (unspec:XO [(match_operand:XO 1 "accumulator_operand" "0,0")
(match_operand:OO 2 "vsx_register_operand" "v,?wa")
(match_operand:V16QI 3 "vsx_register_operand" "v,?wa")]
MMA_APV))]
@@ -561,7 +561,7 @@
[(set_attr "type" "mma")])
(define_insn "mma_"
- [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d")
+ [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
(unspec:XO [(match_operand:V16QI 1 "vsx_register_operand" "v,?wa")
(match_operand:V16QI 2 "vsx_register_operand" "v,?wa")
(match_operand:SI 3 "const_0_to_15_operand" "n,n")
@@ -574,8 +574,8 @@
(set_attr "prefixed" "yes")])
(define_insn "mma_"
- [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d")
- (unspec:XO [(match_operand:XO 1 "fpr_reg_operand" "0,0")
+ [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
+ (unspec:XO [(match_operand:XO 1 "accumulator_operand" "0,0")
(match_operand:V16QI 2 "vsx_register_operand" "v,?wa")
(match_operand:V16QI 3 "vsx_register_operand" "v,?wa")
(match_operand:SI 4 "const_0_to_15_operand" "n,n")
@@ -588,7 +588,7 @@
(set_attr "prefixed" "yes")])
(define_insn "mma_"
- [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d")
+ [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
(unspec:XO [(match_operand:V16QI 1 "vsx_register_operand" "v,?wa")
(match_operand:V16QI 2 "vsx_register_operand" "v,?wa")
(match_operand:SI 3 "const_0_to_15_operand" "n,n")
@@ -601,8 +601,8 @@
(set_attr "prefixed" "yes")])
(define_insn "mma_"
- [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d")
- (unspec:XO [(match_operand:XO 1 "fpr_reg_operand" "0,0")
+ [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
+ (unspec:XO [(match_operand:XO 1 "accumulator_operand" "0,0")
[gcc(refs/users/meissner/heads/work204-sha)] RFC2653-PowerPC: Add support for 1, 024 bit DMR registers.
https://gcc.gnu.org/g:30fe1737bb405f2c31abbd540a59feb7b6073145 commit 30fe1737bb405f2c31abbd540a59feb7b6073145 Author: Michael Meissner Date: Wed Apr 30 20:16:03 2025 -0400 RFC2653-PowerPC: Add support for 1,024 bit DMR registers. This patch is a prelimianry patch to add the full 1,024 bit dense math register (DMRs) for -mcpu=future. The MMA 512-bit accumulators map onto the top of the DMR register. This patch only adds the new 1,024 bit register support. It does not add support for any instructions that need 1,024 bit registers instead of 512 bit registers. I used the new mode 'TDOmode' to be the opaque mode used for 1,024 bit registers. The 'wD' constraint added in previous patches is used for these registers. I added support to do load and store of DMRs via the VSX registers, since there are no load/store dense math instructions. I added the new keyword '__dmr' to create 1,024 bit types that can be loaded into DMRs. At present, I don't have aliases for __dmr512 and __dmr1024 that we've discussed internally. The patches have been tested on both little and big endian systems. Can I check it into the master branch? 2025-04-30 Michael Meissner gcc/ * config/rs6000/mma.md (UNSPEC_DM_INSERT512_UPPER): New unspec. (UNSPEC_DM_INSERT512_LOWER): Likewise. (UNSPEC_DM_EXTRACT512): Likewise. (UNSPEC_DMR_RELOAD_FROM_MEMORY): Likewise. (UNSPEC_DMR_RELOAD_TO_MEMORY): Likewise. (movtdo): New define_expand and define_insn_and_split to implement 1,024 bit DMR registers. (movtdo_insert512_upper): New insn. (movtdo_insert512_lower): Likewise. (movtdo_extract512): Likewise. (reload_dmr_from_memory): Likewise. (reload_dmr_to_memory): Likewise. * config/rs6000/rs6000-builtin.cc (rs6000_type_string): Add DMR support. (rs6000_init_builtins): Add support for __dmr keyword. * config/rs6000/rs6000-call.cc (rs6000_return_in_memory): Add support for TDOmode. (rs6000_function_arg): Likewise. * config/rs6000/rs6000-modes.def (TDOmode): New mode. * config/rs6000/rs6000.cc (rs6000_hard_regno_nregs_internal): Add support for TDOmode. (rs6000_hard_regno_mode_ok_uncached): Likewise. (rs6000_hard_regno_mode_ok): Likewise. (rs6000_modes_tieable_p): Likewise. (rs6000_debug_reg_global): Likewise. (rs6000_setup_reg_addr_masks): Likewise. (rs6000_init_hard_regno_mode_ok): Add support for TDOmode. Setup reload hooks for DMR mode. (reg_offset_addressing_ok_p): Add support for TDOmode. (rs6000_emit_move): Likewise. (rs6000_secondary_reload_simple_move): Likewise. (rs6000_preferred_reload_class): Likewise. (rs6000_secondary_reload_class): Likewise. (rs6000_mangle_type): Add mangling for __dmr type. (rs6000_dmr_register_move_cost): Add support for TDOmode. (rs6000_split_multireg_move): Likewise. (rs6000_invalid_conversion): Likewise. * config/rs6000/rs6000.h (VECTOR_ALIGNMENT_P): Add TDOmode. (enum rs6000_builtin_type_index): Add DMR type nodes. (dmr_type_node): Likewise. (ptr_dmr_type_node): Likewise. gcc/testsuite/ * gcc.target/powerpc/dm-1024bit.c: New test. * lib/target-supports.exp (check_effective_target_ppc_dmr_ok): New target test. Diff: --- gcc/config/rs6000/mma.md | 154 ++ gcc/config/rs6000/rs6000-builtin.cc | 17 +++ gcc/config/rs6000/rs6000-call.cc | 10 +- gcc/config/rs6000/rs6000-modes.def| 4 + gcc/config/rs6000/rs6000.cc | 101 - gcc/config/rs6000/rs6000.h| 6 +- gcc/testsuite/gcc.target/powerpc/dm-1024bit.c | 63 +++ gcc/testsuite/lib/target-supports.exp | 35 ++ 8 files changed, 356 insertions(+), 34 deletions(-) diff --git a/gcc/config/rs6000/mma.md b/gcc/config/rs6000/mma.md index 683d2398ef90..1420fadd4355 100644 --- a/gcc/config/rs6000/mma.md +++ b/gcc/config/rs6000/mma.md @@ -92,6 +92,11 @@ UNSPEC_MMA_XXMFACC UNSPEC_MMA_XXMTACC UNSPEC_MMA_DMSETDMRZ + UNSPEC_DM_INSERT512_UPPER + UNSPEC_DM_INSERT512_LOWER + UNSPEC_DM_EXTRACT512 + UNSPEC_DMR_RELOAD_FROM_MEMORY + UNSPEC_DMR_RELOAD_TO_MEMORY ]) (define_c_enum "unspecv" @@ -742,3 +747,152 @@ " %A0,%x2,%x3,%4,%5,%6" [(set_attr "type" "mma") (set_attr "prefixed" "yes")]) + +;; TDOmode (__dmr keyword for 1,024 bit registers). +(define_expand "movtdo" + [(set (match_operand:TDO 0 "nonimmediate_operand") + (match_operand:
