[gcc r15-8720] Add 'libgomp.c++/pr101544-1{, -O0}.C', 'libgomp.oacc-c++/pr101544-1.C' [PR101544]

[Thomas Schwinge via Gcc-cvs]

https://gcc.gnu.org/g:62312c778aaf7bc4b33d645188ec8a906fb5711b

commit r15-8720-g62312c778aaf7bc4b33d645188ec8a906fb5711b
Author: Thomas Schwinge 
Date:   Tue Jul 12 09:59:10 2022 +0200

Add 'libgomp.c++/pr101544-1{,-O0}.C', 'libgomp.oacc-c++/pr101544-1.C' 
[PR101544]

PR target/101544
libgomp/
* testsuite/libgomp.c++/pr101544-1.C: New.
* testsuite/libgomp.c++/pr101544-1-O0.C: Likewise.
* testsuite/libgomp.oacc-c++/pr101544-1.C: Likewise.

Diff:
---
 libgomp/testsuite/libgomp.c++/pr101544-1-O0.C   |  4 ++
 libgomp/testsuite/libgomp.c++/pr101544-1.C  | 83 +
 libgomp/testsuite/libgomp.oacc-c++/pr101544-1.C |  7 +++
 3 files changed, 94 insertions(+)

diff --git a/libgomp/testsuite/libgomp.c++/pr101544-1-O0.C 
b/libgomp/testsuite/libgomp.c++/pr101544-1-O0.C
new file mode 100644
index ..19a8cad23286
--- /dev/null
+++ b/libgomp/testsuite/libgomp.c++/pr101544-1-O0.C
@@ -0,0 +1,4 @@
+// { dg-additional-options -foffload-options=-lstdc++ }
+// { dg-additional-options -O0 }
+
+#include "pr101544-1.C"
diff --git a/libgomp/testsuite/libgomp.c++/pr101544-1.C 
b/libgomp/testsuite/libgomp.c++/pr101544-1.C
new file mode 100644
index ..8ea70a242bc5
--- /dev/null
+++ b/libgomp/testsuite/libgomp.c++/pr101544-1.C
@@ -0,0 +1,83 @@
+// { dg-additional-options -foffload-options=-lstdc++ }
+// See also '../libgomp.oacc-c++/pr101544-1.C'.
+#ifndef ALWAYS_INLINE
+# define ALWAYS_INLINE
+#endif
+
+//===--- declare_target_base_class.cpp 
--===//
+// 
+// OpenMP API Version 4.5 Nov 2015
+//
+// This test was suggested by members of NERSC. This test defines a declare
+// target region which includes only a base class and a 'concrete' device
+// pointer. 
+// 
+// Test suggestion comes from Chris Daily and Rahulkumar Gayatri from NERSC
+===--===//
+
+#include 
+#include 
+#include 
+
+#pragma omp declare target
+//#pragma acc routine //TODO error: '#pragma acc routine' not immediately 
followed by function declaration or definition
+class S {
+public:
+  //#pragma acc routine //TODO error: '#pragma acc routine' must be at file 
scope
+  ALWAYS_INLINE
+  S() : _devPtr(nullptr) {}
+  //#pragma acc routine //TODO error: '#pragma acc routine' must be at file 
scope
+  ALWAYS_INLINE
+  double sag(double x, double y) {
+return x + y;
+  }
+  S* cloneToDevice() {
+S* ptr;
+#pragma omp target map(ptr)
+#pragma acc serial copy(ptr)
+{
+  ptr = new S();
+}
+_devPtr = ptr;
+return ptr;
+  }
+private:
+  S* _devPtr;
+};
+//#pragma acc routine (S) //TODO error: 'class S' does not refer to a function
+//#pragma acc routine (S::S) //TODO error: '#pragma acc routine' names a set 
of overloads
+//#pragma acc routine (S::sag) //TODO error: '#pragma acc routine' names a set 
of overloads
+#pragma omp end declare target
+
+int main() {
+  int errors = 0;
+  
+  S s;
+  S* devPtr = s.cloneToDevice();
+
+  std::vector in(10, 0.0);
+  for(int i = 0; i < 10; i++) {
+in[i] = i;
+  }
+
+  std::vector out(10, 0.0);
+
+  double* inptr = in.data();
+  double* outptr = out.data();
+
+#pragma omp target teams distribute parallel for map(inptr[:10], outptr[:10]) 
is_device_ptr(devPtr)
+#pragma acc parallel loop copy(inptr[:10], outptr[:10]) deviceptr(devPtr)
+  for(int i = 0; i < 10; i++) {
+outptr[i] = devPtr->sag(inptr[i], inptr[i]);
+  }
+
+  for(int i = 0; i < 10; i++) {
+if (out[i] != i * 2)
+  {
+   ++errors;
+   std::cerr << "ERROR: " << "i = " << i << ": " << out[i] << " != " << (i 
* 2) << "\n";
+  }
+  }
+
+  return errors ? 1 : 0;
+}
diff --git a/libgomp/testsuite/libgomp.oacc-c++/pr101544-1.C 
b/libgomp/testsuite/libgomp.oacc-c++/pr101544-1.C
new file mode 100644
index ..004cd49353be
--- /dev/null
+++ b/libgomp/testsuite/libgomp.oacc-c++/pr101544-1.C
@@ -0,0 +1,7 @@
+// { dg-additional-options -foffload-options=-lstdc++ }
+// { dg-additional-options -fno-inline } for stable results regarding OpenACC 
'routine'.
+// But actually, as none of the '#pragma acc routine' syntax is accepted, 
force inlining:
+#define ALWAYS_INLINE __attribute__((always_inline))
+
+#include "../libgomp.c++/pr101544-1.C"
+//TODO { dg-prune-output {using 'vector_length \(32\)', ignoring 1} }

[gcc r15-8870] libgomp: Save OpenMP device number when initializing the interop object

[Tobias Burnus via Gcc-cvs]

https://gcc.gnu.org/g:4d5d1a7326c8509a4a6fc94eedc3ba22d68f806f

commit r15-8870-g4d5d1a7326c8509a4a6fc94eedc3ba22d68f806f
Author: Tobias Burnus 
Date:   Mon Mar 24 19:52:10 2025 +0100

libgomp: Save OpenMP device number when initializing the interop object

The interop object (opaque object to the user, used internally in libgomp)
already had a 'device_num' member, but it was missed to actually set it.

libgomp/ChangeLog:

* target.c (gomp_interop_internal): Set the 'device_num' member
when initializing an interop object.

Diff:
---
 libgomp/target.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/libgomp/target.c b/libgomp/target.c
index 36ed797b0a96..a64ee96af2a0 100644
--- a/libgomp/target.c
+++ b/libgomp/target.c
@@ -5324,6 +5324,7 @@ gomp_interop_internal (void *data)
}
  *obj =
(struct interop_obj_t *) calloc (1, sizeof (struct interop_obj_t));
+ (*obj)->device_num = devicep->target_id;
  devicep->interop_func (*obj, devicep->target_id,
 gomp_interop_flag_init, targetsync,
 prefer_type);

[gcc] Created branch 'meissner/heads/work196-dmf' in namespace 'refs/users'

[Michael Meissner via Gcc-cvs]

The branch 'meissner/heads/work196-dmf' was created in namespace 'refs/users' 
pointing to:

 bc61a0720b30... Add ChangeLog.meissner and REVISION.

[gcc] Created branch 'meissner/heads/work196-vpair' in namespace 'refs/users'

[Michael Meissner via Gcc-cvs]

The branch 'meissner/heads/work196-vpair' was created in namespace 'refs/users' 
pointing to:

 bc61a0720b30... Add ChangeLog.meissner and REVISION.

[gcc r15-8791] gccrs: remove bad type checking diagnostic

[Arthur Cohen via Gcc-cvs]

https://gcc.gnu.org/g:a34f4d5a817f777696a0b0ddf1328275c8a81538

commit r15-8791-ga34f4d5a817f777696a0b0ddf1328275c8a81538
Author: Philip Herron 
Date:   Tue Feb 4 17:15:15 2025 +

gccrs: remove bad type checking diagnostic

This was a bad diagnostic added when I was working on slices and iterators
also the name of the function is also bad. This is all about setting up
associated types based on the current context of the bounds assocated with
the associated trait bounds on this function.

The tell tale is that this didnt have an associated rust error code so
this is most definetly not the correct error diagnostic.

Fixes Rust-GCC#3403

gcc/rust/ChangeLog:

* typecheck/rust-tyty-subst.cc (SubstitutionRef::monomorphize): 
remove diagnostic

gcc/testsuite/ChangeLog:

* rust/compile/nr2/exclude: nr2 cant handle this
* rust/compile/issue-3403.rs: New test.

Signed-off-by: Philip Herron 

Diff:
---
 gcc/rust/typecheck/rust-tyty-subst.cc| 21 +-
 gcc/testsuite/rust/compile/issue-3403.rs | 38 
 gcc/testsuite/rust/compile/nr2/exclude   |  1 +
 3 files changed, 40 insertions(+), 20 deletions(-)

diff --git a/gcc/rust/typecheck/rust-tyty-subst.cc 
b/gcc/rust/typecheck/rust-tyty-subst.cc
index a12ad91192d3..eb9e9dc92783 100644
--- a/gcc/rust/typecheck/rust-tyty-subst.cc
+++ b/gcc/rust/typecheck/rust-tyty-subst.cc
@@ -934,27 +934,8 @@ SubstitutionRef::monomorphize ()
  auto associated
= Resolver::lookup_associated_impl_block (bound, binding,
  &ambigious);
- if (associated == nullptr && ambigious)
-   {
- // go for the first one? or error out?
- auto &mappings = Analysis::Mappings::get ();
- const auto &type_param = subst.get_generic_param ();
- const auto *trait_ref = bound.get ();
-
- rich_location r (line_table, type_param.get_locus ());
- r.add_range (bound.get_locus ());
- r.add_range (mappings.lookup_location (binding->get_ref ()));
-
- rust_error_at (r, "ambiguous type bound for trait %s and type %s",
-trait_ref->get_name ().c_str (),
-binding->get_name ().c_str ());
- return false;
-   }
-
  if (associated != nullptr)
-   {
- associated->setup_associated_types (binding, bound);
-   }
+   associated->setup_associated_types (binding, bound);
}
 }
 
diff --git a/gcc/testsuite/rust/compile/issue-3403.rs 
b/gcc/testsuite/rust/compile/issue-3403.rs
new file mode 100644
index ..ced6b4efd975
--- /dev/null
+++ b/gcc/testsuite/rust/compile/issue-3403.rs
@@ -0,0 +1,38 @@
+pub struct Foo {
+a: i32,
+// { dg-warning "field is never read" "" { target *-*-* } .-1 }
+}
+pub struct Bar(i32);
+
+#[lang = "sized"]
+trait Sized {}
+
+pub mod core {
+pub mod default {
+pub trait Default: Sized {
+fn default() -> Self;
+}
+
+impl Default for i32 {
+fn default() -> Self {
+0
+}
+}
+}
+}
+
+impl ::core::default::Default for Bar {
+#[inline]
+fn default() -> Bar {
+Bar(core::default::Default::default())
+}
+}
+
+impl ::core::default::Default for Foo {
+#[inline]
+fn default() -> Foo {
+Foo {
+a: core::default::Default::default(),
+}
+}
+}
diff --git a/gcc/testsuite/rust/compile/nr2/exclude 
b/gcc/testsuite/rust/compile/nr2/exclude
index 512419438db6..6f6280d3b661 100644
--- a/gcc/testsuite/rust/compile/nr2/exclude
+++ b/gcc/testsuite/rust/compile/nr2/exclude
@@ -123,4 +123,5 @@ derive-default1.rs
 issue-3402-1.rs
 for-loop1.rs
 for-loop2.rs
+issue-3403.rs
 # please don't delete the trailing newline

[gcc r15-8868] cobol: Move includes before system.h

[Iain D Sandoe via Gcc-cvs]

https://gcc.gnu.org/g:57fdc97dac1453849a76bdce265428d441a03de0

commit r15-8868-g57fdc97dac1453849a76bdce265428d441a03de0
Author: Iain Sandoe 
Date:   Sat Mar 15 22:37:58 2025 +

cobol: Move includes before system.h

This just moves an include ahead of cobol-system.h which
in turn includes system.h.

gcc/cobol/ChangeLog:

* cdf-copy.cc: Move host include before system.h

Signed-off-by: Iain Sandoe 

Diff:
---
 gcc/cobol/cdf-copy.cc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/gcc/cobol/cdf-copy.cc b/gcc/cobol/cdf-copy.cc
index 179dbacea930..c620c828a0bf 100644
--- a/gcc/cobol/cdf-copy.cc
+++ b/gcc/cobol/cdf-copy.cc
@@ -34,13 +34,13 @@
 //
 // We regret any confusion engendered.
 
+#include 
+
 #include "cobol-system.h"
 #include "cbldiag.h"
 #include "util.h"
 #include "copybook.h"
 
-#include 
-
 #define COUNT_OF(X) (sizeof(X) / sizeof(X[0]))
 
 /*

[gcc r15-8872] libstdc++: Add testcases for resolved bug [PR101527]

[Jonathan Wakely via Gcc-cvs]

https://gcc.gnu.org/g:f7c0b0fc4fdeaf034dc38356830625f7280d325d

commit r15-8872-gf7c0b0fc4fdeaf034dc38356830625f7280d325d
Author: Jonathan Wakely 
Date:   Mon Mar 24 21:36:16 2025 +

libstdc++: Add testcases for resolved bug [PR101527]

These tests were fixed by a front-end change r13-465-g4df735e01e3199 so
this just adds them to the testsuite to be sure we don't regress.

libstdc++-v3/ChangeLog:

PR libstdc++/101527
* testsuite/24_iterators/common_iterator/101527.cc: New test.
* testsuite/24_iterators/counted_iterator/101527.cc: New test.

Diff:
---
 .../testsuite/24_iterators/common_iterator/101527.cc   | 14 ++
 .../testsuite/24_iterators/counted_iterator/101527.cc  | 14 ++
 2 files changed, 28 insertions(+)

diff --git a/libstdc++-v3/testsuite/24_iterators/common_iterator/101527.cc 
b/libstdc++-v3/testsuite/24_iterators/common_iterator/101527.cc
new file mode 100644
index ..0a2a5e8dfcca
--- /dev/null
+++ b/libstdc++-v3/testsuite/24_iterators/common_iterator/101527.cc
@@ -0,0 +1,14 @@
+// { dg-do compile { target c++20 } }
+
+// PR libstdc++/101527
+// implementation of std::common_iterator and std::counted_iterator's
+// operator== seems to be wrong
+
+#include 
+
+bool test_pr101527()
+{
+  std::common_iterator it1;
+  std::common_iterator it2;
+  return it1 == it2;
+}
diff --git a/libstdc++-v3/testsuite/24_iterators/counted_iterator/101527.cc 
b/libstdc++-v3/testsuite/24_iterators/counted_iterator/101527.cc
new file mode 100644
index ..51c6e99cd77c
--- /dev/null
+++ b/libstdc++-v3/testsuite/24_iterators/counted_iterator/101527.cc
@@ -0,0 +1,14 @@
+// { dg-do compile { target c++20 } }
+
+// PR libstdc++/101527
+// implementation of std::common_iterator and std::counted_iterator's
+// operator== seems to be wrong
+
+#include 
+
+bool test_pr101527()
+{
+  std::counted_iterator it1;
+  std::counted_iterator it2;
+  return it1 == it2;
+}

[gcc r15-8871] Update gcc hr.po, sv.po

[Joseph Myers via Gcc-cvs]

https://gcc.gnu.org/g:14c924333d7d0b2b6be8eee35d7bc7c2cb17aba2

commit r15-8871-g14c924333d7d0b2b6be8eee35d7bc7c2cb17aba2
Author: Joseph Myers 
Date:   Mon Mar 24 20:05:34 2025 +

Update gcc hr.po, sv.po

* hr.po, sv.po: Update.

Diff:
---
 gcc/po/hr.po | 676 +--
 gcc/po/sv.po | 292 --
 2 files changed, 424 insertions(+), 544 deletions(-)

diff --git a/gcc/po/hr.po b/gcc/po/hr.po
index b4d8eaa63045..79a2f57acf1e 100644
--- a/gcc/po/hr.po
+++ b/gcc/po/hr.po
@@ -1,15 +1,15 @@
-# Translation of gcc to Croatian.
-# Copyright (C) 2025 Free Software Foundation, Inc.
+# Croatian translation of gcc messages.
+# Copyright © 2025 Free Software Foundation, Inc.
 # This file is distributed under the same license as the gcc package.
 #
 # Tomislav Krznar , 2012, 2022.
-# Božidar Putanec , 2022-2025.
+# Božidar Putanec , 2022, 2023, 2024, 2025.
 msgid ""
 msgstr ""
 "Project-Id-Version: gcc-15.1-b20250316\n"
 "Report-Msgid-Bugs-To: https://gcc.gnu.org/bugs/\n";
 "POT-Creation-Date: 2025-03-14 22:06+\n"
-"PO-Revision-Date: 2025-03-20 12:26-0700\n"
+"PO-Revision-Date: 2025-03-23 16:56-0700\n"
 "Last-Translator: Božidar Putanec \n"
 "Language-Team: Croatian \n"
 "Language: hr\n"
@@ -18,14 +18,11 @@ msgstr ""
 "Content-Transfer-Encoding: 8bit\n"
 "Plural-Forms: nplurals=3; plural=(n%10==1 && n%100!=11 ? 0 : n%10>=2 && 
n%10<=4 && (n%100<10 || n%100>=20) ? 1 : 2);\n"
 "X-Bugs: Report translation errors to the Language-Team address.\n"
-"X-Generator: Poedit 3.2.2\n"
-"X-Poedit-Basepath: ../sources/gcc-12-20220213\n"
-"X-Poedit-Bookmarks: 13750,0,-1,-1,-1,-1,-1,-1,-1,-1\n"
-"X-Poedit-SearchPath-0: .\n"
+"X-Generator: Vim9.1\n"
 
 #: cif-code.def:39
 msgid "function not considered for inlining"
-msgstr "funkcija nije kvalificirana za ‘inlining’ (umetanje)"
+msgstr "funkcija nije kvalificirana za ‘inlining’"
 
 #: cif-code.def:43
 msgid "caller is not optimized"
@@ -389,7 +386,7 @@ msgstr "nemojte istovremeno specificirati -march=... i 
-mcpu=..."
 #: config/i386/cygwin-w64.h:64 config/i386/cygwin.h:129
 #: config/i386/mingw-w64.h:125 config/mingw/mingw32.h:174
 msgid "shared and mdll are not compatible"
-msgstr ""
+msgstr "shared i mdll nisu kompatibilni"
 
 #: config/i386/darwin.h:93
 msgid "Darwin is not an mx32 platform"
@@ -451,7 +448,7 @@ msgstr ""
 
 #: config/rx/linux.h:53 config/rx/rx.h:82
 msgid "rx200 cpu does not have FPU hardware"
-msgstr ""
+msgstr "rx200 CPU nema FPU hardver"
 
 #: config/rx/rx.h:80
 msgid "-mas100-syntax is incompatible with -gdwarf"
@@ -477,7 +474,7 @@ msgstr "-fsanitize=address nije podržan u ovoj 
konfiguraciji"
 #: config/sparc/netbsd-elf.h:103 config/sparc/netbsd-elf.h:112
 #: config/sparc/sol2.h:240 config/sparc/sol2.h:246
 msgid "may not use both -m32 and -m64"
-msgstr ""
+msgstr "ne smije se koristiti istovremeno -m32 i -m64"
 
 #: config/vax/netbsd-elf.h:51
 msgid "the -shared option is not currently supported for VAX ELF"
@@ -547,7 +544,7 @@ msgstr ""
 #: common.opt:2673 common.opt:3440
 #, no-c-format
 msgid "Does nothing. Preserved for backward compatibility."
-msgstr ""
+msgstr "Ne čini ništa. Zadržano radi kompatibilnosti s prethodnim verzijama."
 
 #: fortran/lang.opt:218
 #, no-c-format
@@ -1229,7 +1226,7 @@ msgstr ""
 #: rust/lang.opt:59 c-family/c.opt:892 common.opt:660
 #, no-c-format
 msgid "Warn for infinitely recursive calls."
-msgstr ""
+msgstr "Upzori na rekurzivne pozive."
 
 #: rust/lang.opt:63
 #, no-c-format
@@ -1589,7 +1586,7 @@ msgstr ""
 #: c-family/c.opt:468
 #, no-c-format
 msgid "Warn about C constructs that are not in the common subset of C and C++."
-msgstr ""
+msgstr "Upozori na C konstrukte koji nisu u uobičajenum podskupu od od  C i 
C++."
 
 #: c-family/c.opt:475
 #, no-c-format
@@ -1961,7 +1958,7 @@ msgstr ""
 #: c-family/c.opt:798
 #, no-c-format
 msgid "Warn about function calls with format strings that write past the end 
of the destination region.  Same as -Wformat-overflow=1."
-msgstr "Upozori na pozive funkcija s format stringovima koji pišu iza kraja 
područja odredišta. Isto kao -Wformat-overflow=1."
+msgstr "Upozori na pozive funkcija s format stringovima koji pišu iza kraja 
područja odredišta. Jednako kao -Wformat-overflow=1."
 
 #: c-family/c.opt:803
 #, no-c-format
@@ -1981,7 +1978,7 @@ msgstr ""
 #: c-family/c.opt:816
 #, no-c-format
 msgid "Warn about calls to snprintf and similar functions that truncate 
output. Same as -Wformat-truncation=1."
-msgstr "Upozori na pozivanje snprintf i sličnih funkcija koje skraćuju izlaz. 
Isto kao  -Wformat-truncation=1."
+msgstr "Upozori na pozivanje snprintf i sličnih funkcija koje skraćuju izlaz. 
Jednako kao  -Wformat-truncation=1."
 
 #: c-family/c.opt:821
 #, no-c-format
@@ -3032,7 +3029,7 @@ msgstr ""
 #: c-family/c.opt:1950
 #, no-c-format
 msgid "Do not elide common elements in template comparisons."
-msgstr ""
+msgstr "Ne izostavlja zajedničke elemente prilikomm usporedbi predložaka."
 
 #: 

[gcc(refs/users/meissner/heads/work196-dmf)] Revert changes

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:546d81684ca6f0de06b0c1405a8473f3673b997d

commit 546d81684ca6f0de06b0c1405a8473f3673b997d
Author: Michael Meissner 
Date:   Mon Mar 24 19:50:55 2025 -0400

Revert changes

Diff:
---
 gcc/config/rs6000/altivec.md   | 14 
 gcc/config/rs6000/constraints.md   | 10 ---
 gcc/config/rs6000/predicates.md| 52 +---
 gcc/config/rs6000/rs6000.cc| 25 --
 gcc/config/rs6000/rs6000.h |  7 --
 gcc/config/rs6000/rs6000.md| 96 +++---
 gcc/testsuite/gcc.target/powerpc/prefixed-addis.c  | 24 --
 .../gcc.target/powerpc/vector-rotate-left.c| 34 
 8 files changed, 14 insertions(+), 248 deletions(-)

diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
index d158cf479d60..7edc288a6565 100644
--- a/gcc/config/rs6000/altivec.md
+++ b/gcc/config/rs6000/altivec.md
@@ -1982,20 +1982,6 @@
 }
   [(set_attr "type" "vecperm")])
 
-;; -mcpu=future adds a vector rotate left word variant.  There is no vector
-;; byte/half-word/double-word/quad-word rotate left.  This insn occurs before
-;; altivec_vrl and will match for -mcpu=future, while other cpus will
-;; match the generic insn.
-(define_insn "*xvrlw"
-  [(set (match_operand:V4SI 0 "register_operand" "=v,wa")
-   (rotate:V4SI (match_operand:V4SI 1 "register_operand" "v,wa")
-(match_operand:V4SI 2 "register_operand" "v,wa")))]
-  "TARGET_XVRLW"
-  "@
-   vrlw %0,%1,%2
-   xvrlw %x0,%x1,%x2"
-  [(set_attr "type" "vecsimple")])
-
 (define_insn "altivec_vrl"
   [(set (match_operand:VI2 0 "register_operand" "=v")
 (rotate:VI2 (match_operand:VI2 1 "register_operand" "v")
diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md
index 5440becb6e6c..3da9ed086810 100644
--- a/gcc/config/rs6000/constraints.md
+++ b/gcc/config/rs6000/constraints.md
@@ -222,16 +222,6 @@
   "An IEEE 128-bit constant that can be loaded into VSX registers."
   (match_operand 0 "easy_vector_constant_ieee128"))
 
-(define_constraint "eU"
-  "@internal integer constant that can be loaded with paddis"
-  (and (match_code "const_int")
-   (match_operand 0 "paddis_operand")))
-
-(define_constraint "eV"
-  "@internal integer constant that can be loaded with paddis + paddi"
-  (and (match_code "const_int")
-   (match_operand 0 "paddis_paddi_operand")))
-
 ;; Floating-point constraints.  These two are defined so that insn
 ;; length attributes can be calculated exactly.
 
diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md
index c206860e4927..c95b4336f062 100644
--- a/gcc/config/rs6000/predicates.md
+++ b/gcc/config/rs6000/predicates.md
@@ -369,53 +369,6 @@
   return SIGNED_INTEGER_34BIT_P (INTVAL (op));
 })
 
-;; Return 1 if op is a 64-bit constant that uses the paddis instruction
-(define_predicate "paddis_operand"
-  (match_code "const_int")
-{
-  if (!TARGET_PADDIS && TARGET_POWERPC64)
-return 0;
-
-  /* If addi, addis, or paddi can handle the number, don't return true.  */
-  HOST_WIDE_INT value = INTVAL (op);
-  if (SIGNED_INTEGER_34BIT_P (value))
-return false;
-
-  /* If the number is too large for padds, return false.  */
-  if (!SIGNED_INTEGER_32BIT_P (value >> 32))
-return false;
-
-  /* If the bottom 32-bits are non-zero, paddis can't handle it.  */
-  if ((value & HOST_WIDE_INT_C(0x)) != 0)
-return false;
-
-  return true;
-})
-
-;; Return 1 if op is a 64-bit constant that needs the paddis instruction and an
-;; addi/addis/paddi instruction combination.
-(define_predicate "paddis_paddi_operand"
-  (match_code "const_int")
-{
-  if (!TARGET_PADDIS && TARGET_POWERPC64)
-return 0;
-
-  /* If addi, addis, or paddi can handle the number, don't return true.  */
-  HOST_WIDE_INT value = INTVAL (op);
-  if (SIGNED_INTEGER_34BIT_P (value))
-return false;
-
-  /* If the number is too large for padds, return false.  */
-  if (!SIGNED_INTEGER_32BIT_P (value >> 32))
-return false;
-
-  /* If the bottom 32-bits are zero, we can use paddis alone to handle it.  */
-  if ((value & HOST_WIDE_INT_C(0x)) == 0)
-return false;
-
-  return true;
-})
-
 ;; Return 1 if op is a register that is not special.
 ;; Disallow (SUBREG:SF (REG:SI)) and (SUBREG:SI (REG:SF)) on VSX systems where
 ;; you need to be careful in moving a SFmode to SImode and vice versa due to
@@ -1160,10 +1113,7 @@
   (if_then_else (match_code "const_int")
 (match_test "satisfies_constraint_I (op)
 || satisfies_constraint_L (op)
-|| satisfies_constraint_eI (op)
-|| satisfies_constraint_eU (op)
-|| satisfies_constraint_eV (op)")
-
+|| satisfies_constraint_eI (op)")
 (match_operand 0 "gpc_reg_operand")))
 
 ;; Return 1 if the operand is either a non-special register, or 0, or -1.
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/conf

[gcc r15-8877] PR modula2/119449 MAX of SYSTEM.REAL64 cause an ICE

[Gaius Mulley via Gcc-cvs]

https://gcc.gnu.org/g:127a24ede2f82eafecb5eb142e21dbda38d06c18

commit r15-8877-g127a24ede2f82eafecb5eb142e21dbda38d06c18
Author: Gaius Mulley 
Date:   Tue Mar 25 02:08:05 2025 +

PR modula2/119449 MAX of SYSTEM.REAL64 cause an ICE

This bugfix implements MAX(REAL64) and MIN(REAL64) etc for
REAL64, REAL96 and REAL128.

gcc/m2/ChangeLog:

PR modula2/119449
* gm2-compiler/M2GCCDeclare.def (TryDeclareType): Remove tokenno
parameter.
* gm2-compiler/M2GCCDeclare.mod (TryDeclareType): Ditto.
* gm2-compiler/M2GenGCC.mod (FoldTBitsize): Remove op2 and
rename op1 as res and op3 as type.
(FoldStandardFunction): Call FoldTBitsize omitting op2.
* gm2-compiler/M2Quads.mod (GetTypeMin): Rewrite.
(GetTypeMinLower): New procedure function.
(GetTypeMax): Rewrite.
(GetTypeMaxLower): New procedure function.
* gm2-compiler/M2Range.mod (CheckCancelled): Comment out.
* gm2-compiler/M2System.mod (CreateMinMaxFor): Add realtype
parameter.
(MapType): Rewrite to use realtype.
(CreateType): Ditto.
(AttemptToCreateType): Ditto.
(MakeFixedSizedTypes): Add realtype boolean.
(InitPIMTypes): Ditto.
(InitISOTypes): Ditto.
(MakeExtraSystemTypes): Ditto.
* gm2-gcc/m2pp.cc (m2pp_nop_expr): Remove code.
* gm2-gcc/m2type.cc (IsGccRealType): New function.
(m2type_GetMinFrom): Rewrite.
(m2type_GetMaxFrom): Ditto.
(do_min_real): Declare static.
(do_max_real): Declare static.

gcc/testsuite/ChangeLog:

PR modula2/119449
* gm2/pim/pass/minmaxreal.mod: New test.
* gm2/pim/pass/minmaxreal2.mod: New test.
* gm2/pim/pass/minmaxreal3.mod: New test.

Signed-off-by: Gaius Mulley 

Diff:
---
 gcc/m2/gm2-compiler/M2GCCDeclare.def   |   2 +-
 gcc/m2/gm2-compiler/M2GCCDeclare.mod   |   6 +-
 gcc/m2/gm2-compiler/M2GenGCC.mod   |  13 ++-
 gcc/m2/gm2-compiler/M2Quads.mod|  56 ++---
 gcc/m2/gm2-compiler/M2Range.mod|   2 +
 gcc/m2/gm2-compiler/M2System.mod   | 123 -
 gcc/m2/gm2-gcc/m2pp.cc |   1 -
 gcc/m2/gm2-gcc/m2type.cc   |  29 ---
 gcc/testsuite/gm2/pim/pass/minmaxreal.mod  |   7 ++
 gcc/testsuite/gm2/pim/pass/minmaxreal2.mod |   8 ++
 gcc/testsuite/gm2/pim/pass/minmaxreal3.mod |  10 +++
 11 files changed, 168 insertions(+), 89 deletions(-)

diff --git a/gcc/m2/gm2-compiler/M2GCCDeclare.def 
b/gcc/m2/gm2-compiler/M2GCCDeclare.def
index 1d87d6b212af..b3a5790df972 100644
--- a/gcc/m2/gm2-compiler/M2GCCDeclare.def
+++ b/gcc/m2/gm2-compiler/M2GCCDeclare.def
@@ -98,7 +98,7 @@ PROCEDURE TryDeclareConstant (tokenno: CARDINAL; sym: 
CARDINAL) ;
 then enter it into the to do list.
 *)
 
-PROCEDURE TryDeclareType (tokenno: CARDINAL; type: CARDINAL) ;
+PROCEDURE TryDeclareType (type: CARDINAL) ;
 
 
 (*
diff --git a/gcc/m2/gm2-compiler/M2GCCDeclare.mod 
b/gcc/m2/gm2-compiler/M2GCCDeclare.mod
index 7dcf439985a1..b12add6b26e8 100644
--- a/gcc/m2/gm2-compiler/M2GCCDeclare.mod
+++ b/gcc/m2/gm2-compiler/M2GCCDeclare.mod
@@ -144,7 +144,7 @@ FROM M2Base IMPORT IsPseudoBaseProcedure, 
IsPseudoBaseFunction,
Boolean, True, False, Nil,
IsRealType, IsNeededAtRunTime, IsComplexType ;
 
-FROM M2System IMPORT IsPseudoSystemFunction, IsSystemType,
+FROM M2System IMPORT IsPseudoSystemFunction, IsSystemType, IsRealN,
  GetSystemTypeMinMax, Address, Word, Byte, Loc,
  System, IntegerN, CardinalN, WordN, RealN, SetN, ComplexN,
 CSizeT, CSSizeT, COffT ;
@@ -1918,7 +1918,7 @@ END IsAnyType ;
 then enter it into the to do list.
 *)
 
-PROCEDURE TryDeclareType (tokenno: CARDINAL; type: CARDINAL) ;
+PROCEDURE TryDeclareType (type: CARDINAL) ;
 BEGIN
IF (type#NulSym) AND IsAnyType (type)
THEN
@@ -2013,7 +2013,7 @@ BEGIN
  ELSIF IsConstructor(sym)
  THEN
 DeclareConstantFromTree(sym, PopConstructorTree(tokenno))
- ELSIF IsRealType(GetDType(sym))
+ ELSIF IsRealType (GetDType (sym)) OR IsRealN (GetDType (sym))
  THEN
 type := GetDType(sym) ;
 DeclareConstantFromTree(sym, 
BuildConvert(TokenToLocation(tokenno), Mod2Gcc(type), PopRealTree(), TRUE))
diff --git a/gcc/m2/gm2-compiler/M2GenGCC.mod b/gcc/m2/gm2-compiler/M2GenGCC.mod
index 3665751f4f97..a1e3c07809aa 100644
--- a/gcc/m2/gm2-compiler/M2GenGCC.mod
+++ b/gcc/m2/gm2-compiler/M2GenGCC.mod
@@ -4837,18 +4837,17 @@ END FoldBuiltinTypeInfo ;
 
 PROCEDURE FoldTBitsize  (tokenno: CARDINAL; p: WalkAction;
  quad: CARDINAL;
- op1, op2, op3: CARDINAL)

[gcc/devel/omp/gcc-14] libgomp/plugin/plugin-nvptx.c: Fix device used for stream creation

[Tobias Burnus via Gcc-cvs]

https://gcc.gnu.org/g:ea561defcb718dc6f3f03237be661f0697ef3095

commit ea561defcb718dc6f3f03237be661f0697ef3095
Author: Tobias Burnus 
Date:   Mon Mar 24 16:08:20 2025 +0100

libgomp/plugin/plugin-nvptx.c: Fix device used for stream creation

libgomp/ChangeLog:

* plugin/plugin-nvptx.c (GOMP_OFFLOAD_interop): Set context for
stream creation to use the specified device.

(cherry picked from commit 1c5a375c21a262eb636449f88e671a09e140404e)

Diff:
---
 libgomp/ChangeLog.omp |  8 
 libgomp/plugin/plugin-nvptx.c | 18 --
 2 files changed, 24 insertions(+), 2 deletions(-)

diff --git a/libgomp/ChangeLog.omp b/libgomp/ChangeLog.omp
index 931c55777fda..d0a2d53881dd 100644
--- a/libgomp/ChangeLog.omp
+++ b/libgomp/ChangeLog.omp
@@ -1,3 +1,11 @@
+2025-03-24  Tobias Burnus  
+
+   Backported from master:
+   2025-03-24  Tobias Burnus  
+
+   * plugin/plugin-nvptx.c (GOMP_OFFLOAD_interop): Set context for
+   stream creation to use the specified device.
+
 2025-03-21  Tobias Burnus  
 
Backported from master:
diff --git a/libgomp/plugin/plugin-nvptx.c b/libgomp/plugin/plugin-nvptx.c
index f49fef397203..75552fcc8af0 100644
--- a/libgomp/plugin/plugin-nvptx.c
+++ b/libgomp/plugin/plugin-nvptx.c
@@ -2508,12 +2508,26 @@ GOMP_OFFLOAD_interop (struct interop_obj_t *obj, int 
ord,
  break;
   }
 
-  obj->device_data = ptx_devices[ord];
+  struct ptx_device *ptx_dev = obj->device_data = ptx_devices[ord];
 
   if (targetsync)
 {
   CUstream stream = NULL;
-  CUDA_CALL_ASSERT (cuStreamCreate, &stream, CU_STREAM_DEFAULT);
+  CUdevice cur_ctx_dev;
+  CUresult res = CUDA_CALL_NOCHECK (cuCtxGetDevice, &cur_ctx_dev);
+  if (res != CUDA_SUCCESS && res != CUDA_ERROR_INVALID_CONTEXT)
+   GOMP_PLUGIN_fatal ("cuCtxGetDevice error: %s", cuda_error (res));
+  if (res != CUDA_ERROR_INVALID_CONTEXT && ptx_dev->dev == cur_ctx_dev)
+   CUDA_CALL_ASSERT (cuStreamCreate, &stream, CU_STREAM_DEFAULT);
+  else
+   {
+ CUcontext old_ctx;
+ assert (ptx_dev->ctx);
+ CUDA_CALL_ASSERT (cuCtxPushCurrent, ptx_dev->ctx);
+ CUDA_CALL_ASSERT (cuStreamCreate, &stream, CU_STREAM_DEFAULT);
+ if (res != CUDA_ERROR_INVALID_CONTEXT)
+   CUDA_CALL_ASSERT (cuCtxPopCurrent, &old_ctx);
+   }
   obj->stream = stream;
 }
 }

[gcc/devel/omp/gcc-14] libgomp: Save OpenMP device number when initializing the interop object

[Tobias Burnus via Gcc-cvs]

https://gcc.gnu.org/g:10041f146132993c328e3112e33e33c08f90ae06

commit 10041f146132993c328e3112e33e33c08f90ae06
Author: Tobias Burnus 
Date:   Mon Mar 24 19:52:10 2025 +0100

libgomp: Save OpenMP device number when initializing the interop object

The interop object (opaque object to the user, used internally in libgomp)
already had a 'device_num' member, but it was missed to actually set it.

libgomp/ChangeLog:

* target.c (gomp_interop_internal): Set the 'device_num' member
when initializing an interop object.

(cherry picked from commit 4d5d1a7326c8509a4a6fc94eedc3ba22d68f806f)

Diff:
---
 libgomp/target.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/libgomp/target.c b/libgomp/target.c
index 2647c3864c22..bdba51e30037 100644
--- a/libgomp/target.c
+++ b/libgomp/target.c
@@ -5911,6 +5911,7 @@ gomp_interop_internal (void *data)
}
  *obj =
(struct interop_obj_t *) calloc (1, sizeof (struct interop_obj_t));
+ (*obj)->device_num = devicep->target_id;
  devicep->interop_func (*obj, devicep->target_id,
 gomp_interop_flag_init, targetsync,
 prefer_type);

[gcc(refs/users/meissner/heads/work196-bugs)] PR 99293: Optimize splat of a V2DF/V2DI extract with constant element

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:d77b37b6f890d3c895dab38c93a90a7ccd4566a0

commit d77b37b6f890d3c895dab38c93a90a7ccd4566a0
Author: Michael Meissner 
Date:   Mon Mar 24 19:54:55 2025 -0400

PR 99293: Optimize splat of a V2DF/V2DI extract with constant element

We had optimizations for splat of a vector extract for the other vector
types, but we missed having one for V2DI and V2DF.  This patch adds a
combiner insn to do this optimization.

In looking at the source, we had similar optimizations for V4SI and V4SF
extract and splats, but we missed doing V2DI/V2DF.

Without the patch for the code:

vector long long splat_dup_l_0 (vector long long v)
{
  return __builtin_vec_splats (__builtin_vec_extract (v, 0));
}

the compiler generates (on a little endian power9):

splat_dup_l_0:
mfvsrld 9,34
mtvsrdd 34,9,9
blr

Now it generates:

splat_dup_l_0:
xxpermdi 34,34,34,3
blr

2025-03-24  Michael Meissner  

gcc/

PR target/99293
* config/rs6000/vsx.md (vsx_splat_extract_): New insn.

gcc/testsuite/

PR target/99293
* gcc.target/powerpc/builtins-1.c: Adjust insn count.
* gcc.target/powerpc/pr99293.c: New test.

Diff:
---
 gcc/config/rs6000/vsx.md  | 18 ++
 gcc/testsuite/gcc.target/powerpc/builtins-1.c |  2 +-
 gcc/testsuite/gcc.target/powerpc/pr99293.c| 22 ++
 3 files changed, 41 insertions(+), 1 deletion(-)

diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index dd3573b80868..d84a2a357a31 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -4798,6 +4798,24 @@
   "lxvdsx %x0,%y1"
   [(set_attr "type" "vecload")])
 
+;; Optimize SPLAT of an extract from a V2DF/V2DI vector with a constant element
+(define_insn "*vsx_splat_extract_"
+  [(set (match_operand:VSX_D 0 "vsx_register_operand" "=wa")
+   (vec_duplicate:VSX_D
+(vec_select:
+ (match_operand:VSX_D 1 "vsx_register_operand" "wa")
+ (parallel [(match_operand 2 "const_0_to_1_operand" "n")]]
+  "VECTOR_MEM_VSX_P (mode)"
+{
+  int which_word = INTVAL (operands[2]);
+  if (!BYTES_BIG_ENDIAN)
+which_word = 1 - which_word;
+
+  operands[3] = GEN_INT (which_word ? 3 : 0);
+  return "xxpermdi %x0,%x1,%x1,%3";
+}
+  [(set_attr "type" "vecperm")])
+
 ;; V4SI splat support
 (define_insn "vsx_splat_v4si"
   [(set (match_operand:V4SI 0 "vsx_register_operand" "=wa,wa")
diff --git a/gcc/testsuite/gcc.target/powerpc/builtins-1.c 
b/gcc/testsuite/gcc.target/powerpc/builtins-1.c
index 8410a5fd4319..4e7e5384675f 100644
--- a/gcc/testsuite/gcc.target/powerpc/builtins-1.c
+++ b/gcc/testsuite/gcc.target/powerpc/builtins-1.c
@@ -1035,4 +1035,4 @@ foo156 (vector unsigned short usa)
 /* { dg-final { scan-assembler-times {\mvmrglb\M} 3 } } */
 /* { dg-final { scan-assembler-times {\mvmrgew\M} 4 } } */
 /* { dg-final { scan-assembler-times {\mvsplth|xxsplth\M} 4 } } */
-/* { dg-final { scan-assembler-times {\mxxpermdi\M} 44 } } */
+/* { dg-final { scan-assembler-times {\mxxpermdi\M} 42 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/pr99293.c 
b/gcc/testsuite/gcc.target/powerpc/pr99293.c
new file mode 100644
index ..20adc1f27f65
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr99293.c
@@ -0,0 +1,22 @@
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O2 -mvsx" } */
+
+/* Test for PR 99263, which wants to do:
+   __builtin_vec_splats (__builtin_vec_extract (v, n))
+
+   where v is a V2DF or V2DI vector and n is either 0 or 1.  Previously the
+   compiler would do a direct move to the GPR registers to select the item and 
a
+   direct move from the GPR registers to do the splat.  */
+
+vector long long splat_dup_l_0 (vector long long v)
+{
+  return __builtin_vec_splats (__builtin_vec_extract (v, 0));
+}
+
+vector long long splat_dup_l_1 (vector long long v)
+{
+  return __builtin_vec_splats (__builtin_vec_extract (v, 1));
+}
+
+/* { dg-final { scan-assembler-times "xxpermdi" 2 } } */

[gcc(refs/users/meissner/heads/work196-bugs)] PR target/108958 -- use mtvsrdd to zero extend GPR DImode to VSX TImode

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:a159595052a9a4f3da5473deab71f8c258e09741

commit a159595052a9a4f3da5473deab71f8c258e09741
Author: Michael Meissner 
Date:   Mon Mar 24 19:56:46 2025 -0400

PR target/108958 -- use mtvsrdd to zero extend GPR DImode to VSX TImode

Previously GCC would zero externd a DImode GPR value to TImode by first zero
extending the DImode value into a GPR TImode value, and then do a MTVSRDD to
move this value to a VSX register.

This patch does the move directly, since if the middle argument to MTVSRDD 
is 0,
it does the zero extend.

If the DImode value is already in a vector register, it does a XXSPLTIB and
XXPERMDI to get the value into the bottom 64-bits of the register.

I have built GCC with the patches in this patch set applied on both little 
and
big endian PowerPC systems and there were no regressions.  Can I apply this
patch to GCC 15?

2025-03-24  Michael Meissner  

gcc/

PR target/108598
* gcc/config/rs6000/rs6000.md (zero_extendditi2): New insn.

gcc/testsuite/

PR target/108598
* gcc.target/powerpc/pr108958.c: New test.

Diff:
---
 gcc/config/rs6000/rs6000.md | 46 +
 gcc/testsuite/gcc.target/powerpc/pr108958.c | 27 +
 2 files changed, 73 insertions(+)

diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 4c2bc81caf56..65da0c653304 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -1026,6 +1026,52 @@
(set_attr "dot" "yes")
(set_attr "length" "4,8")])
 
+(define_insn_and_split "zero_extendditi2"
+  [(set (match_operand:TI 0 "gpc_reg_operand" "=r,wa,&wa")
+   (zero_extend:TI
+(match_operand:DI 1 "gpc_reg_operand" "rwa,r,wa")))]
+  "TARGET_P9_VECTOR && TARGET_POWERPC64"
+  "@
+  #
+  mtvsrdd %x0,0,%1
+  #"
+  "&& reload_completed
+   && (int_reg_operand (operands[0], TImode)
+   || vsx_register_operand (operands[1], DImode))"
+  [(set (match_dup 2)
+   (match_dup 3))
+   (set (match_dup 4)
+   (match_dup 5))]
+{
+  rtx op0 = operands[0];
+  rtx op1 = operands[1];
+  int r = reg_or_subregno (op0);
+
+  if (int_reg_operand (op0, TImode))
+{
+  int lo = BYTES_BIG_ENDIAN ? 1 : 0;
+  int hi = 1 - lo;
+
+  operands[2] = gen_rtx_REG (DImode, r + lo);
+  operands[3] = op1;
+  operands[4] = gen_rtx_REG (DImode, r + hi);
+  operands[5] = const0_rtx;
+}
+  else
+{
+  rtx op0_di = gen_rtx_REG (DImode, r);
+  rtx op0_v2di = gen_rtx_REG (V2DImode, r);
+  rtx lo = WORDS_BIG_ENDIAN ? op1 : op0_di;
+  rtx hi = WORDS_BIG_ENDIAN ? op0_di : op1;
+
+  operands[2] = op0_v2di;
+  operands[3] = CONST0_RTX (V2DImode);
+  operands[4] = op0_v2di;
+  operands[5] = gen_rtx_VEC_CONCAT (V2DImode, hi, lo);
+}
+}
+  [(set_attr "type" "*,mtvsr,vecperm")
+   (set_attr "length" "8,*,8")])
 
 (define_insn "extendqi2"
   [(set (match_operand:EXTQI 0 "gpc_reg_operand" "=r,?*v")
diff --git a/gcc/testsuite/gcc.target/powerpc/pr108958.c 
b/gcc/testsuite/gcc.target/powerpc/pr108958.c
index e69de29bb2d1..03eb58d069e7 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr108958.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr108958.c
@@ -0,0 +1,27 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target int128 } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-mdejagnu-cpu=power9 -O2" } */
+
+/* PR target/108958, use mtvsrdd to zero extend gpr to vsx register.  */
+
+void
+gpr_to_vsx (unsigned long long x, __uint128_t *p)
+{
+  /* mtvsrdd vsx,0,gpr.  */
+  __uint128_t y = x;
+  __asm__ (" # %x0" : "+wa" (y));
+  *p = y;
+}
+
+void
+gpr_to_gpr (unsigned long long x, __uint128_t *p)
+{
+  /* mr and li.  */
+  __uint128_t y = x;
+  __asm__ (" # %0" : "+r" (y));
+  *p = y;
+}
+
+/* { dg-final { scan-assembler-times {\mli\M}  1 } } */
+/* { dg-final { scan-assembler-times {\mmtvsrdd .*,0,.*\M} 1 } } */

[gcc(refs/users/meissner/heads/work196-dmf)] Update ChangeLog.*

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:3e99e606885e199e4619180a99b9c2463bf579bf

commit 3e99e606885e199e4619180a99b9c2463bf579bf
Author: Michael Meissner 
Date:   Mon Mar 24 19:53:16 2025 -0400

Update ChangeLog.*

Diff:
---
 gcc/ChangeLog.dmf | 329 ++
 1 file changed, 329 insertions(+)

diff --git a/gcc/ChangeLog.dmf b/gcc/ChangeLog.dmf
index fea7617a2a46..145e927a7a35 100644
--- a/gcc/ChangeLog.dmf
+++ b/gcc/ChangeLog.dmf
@@ -1,5 +1,334 @@
+ Branch work196-dmf, patch #121 was reverted 

+ Branch work196-dmf, patch #120 was reverted 

+
+ Branch work196-dmf, patch #111 
+
+RFC2655-Add saturating subtract built-ins.
+
+This patch adds support for a saturating subtract built-in function that may be
+added to a future PowerPC processor.  Note, if it is added, the name of the
+built-in function may change before GCC 13 is released.  If the name changes,
+we will submit a patch changing the name.
+
+I also added support for providing dense math built-in functions, even though
+at present, we have not added any new built-in functions for dense math.  It is
+likely we will want to add new dense math built-in functions as the dense math
+support is fleshed out.
+
+The patches have been tested on both little and big endian systems.  Can I 
check
+it into the master branch?
+
+2025-03-08   Michael Meissner  
+
+gcc/
+
+   * config/rs6000/rs6000-builtin.cc (rs6000_invalid_builtin): Add support
+   for flagging invalid use of future built-in functions.
+   (rs6000_builtin_is_supported): Add support for future built-in
+   functions.
+   * config/rs6000/rs6000-builtins.def (__builtin_saturate_subtract32): New
+   built-in function for -mcpu=future.
+   (__builtin_saturate_subtract64): Likewise.
+   * config/rs6000/rs6000-gen-builtins.cc (enum bif_stanza): Add stanzas
+   for -mcpu=future built-ins.
+   (stanza_map): Likewise.
+   (enable_string): Likewise.
+   (struct attrinfo): Likewise.
+   (parse_bif_attrs): Likewise.
+   (write_decls): Likewise.
+   * config/rs6000/rs6000.md (sat_sub3): Add saturating subtract
+   built-in insn declarations.
+   (sat_sub3_dot): Likewise.
+   (sat_sub3_dot2): Likewise.
+   * doc/extend.texi (Future PowerPC built-ins): New section.
+
+gcc/testsuite/
+
+   * gcc.target/powerpc/subfus-1.c: New test.
+   * gcc.target/powerpc/subfus-2.c: Likewise.
+
+ Branch work196-dmf, patch #110 
+
+RFC2656-Support load/store vector with right length.
+
+This patch adds support for new instructions that may be added to the PowerPC
+architecture in the future to enhance the load and store vector with length
+instructions.
+
+The current instructions (lxvl, lxvll, stxvl, and stxvll) are inconvient to use
+since the count for the number of bytes must be in the top 8 bits of the GPR
+register, instead of the bottom 8 bits.  This meant that code generating these
+instructions typically had to do a shift left by 56 bits to get the count into
+the right position.  In a future version of the PowerPC architecture, new
+variants of these instructions might be added that expect the count to be in
+the bottom 8 bits of the GPR register.  These patches add this support to GCC
+if the user uses the -mcpu=future option.
+
+I discovered that the code in rs6000-string.cc to generate ISA 3.1 lxvl/stxvl
+future lxvll/stxvll instructions would generate these instructions on 32-bit.
+However the patterns for these instructions is only done on 64-bit systems.  So
+I added a check for 64-bit support before generating the instructions.
+
+The patches have been tested on both little and big endian systems.  Can I 
check
+it into the master branch?
+
+2025-03-08   Michael Meissner  
+
+gcc/
+
+   * config/rs6000/rs6000-string.cc (expand_block_move): Do not generate
+   lxvl and stxvl on 32-bit.
+   * config/rs6000/vsx.md (lxvl): If -mcpu=future, generate the lxvl with
+   the shift count automaticaly used in the insn.
+   (lxvrl): New insn for -mcpu=future.
+   (lxvrll): Likewise.
+   (stxvl): If -mcpu=future, generate the stxvl with the shift count
+   automaticaly used in the insn.
+   (stxvrl): New insn for -mcpu=future.
+   (stxvrll): Likewise.
+
+gcc/testsuite/
+
+   * gcc.target/powerpc/lxvrl.c: New test.
+   * lib/target-supports.exp (check_effective_target_powerpc_future_ok):
+   New effective target.
+
+ Branch work196-dmf, patch #102 
+
+RFC2653-PowerPC: Add support for 1,024 bit DMR registers.
+
+This patch is a prelimianry patch to add the full 1,024 bit dense math register
+(DMRs) for -mcpu=future.  The MMA 512-bit accumulators map onto the top of the
+DMR register.
+
+This patch only adds the new 1,024 bit register support.  It does not add
+su

[gcc(refs/users/meissner/heads/work196-bugs)] Add ChangeLog.bugs and update REVISION.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:cd8e607a4492d12ac712ccf0a48dd6b81a1b14b2

commit cd8e607a4492d12ac712ccf0a48dd6b81a1b14b2
Author: Michael Meissner 
Date:   Mon Mar 24 18:44:16 2025 -0400

Add ChangeLog.bugs and update REVISION.

2025-03-24  Michael Meissner  

gcc/

* ChangeLog.bugs: New file for branch.
* REVISION: Update.

Diff:
---
 gcc/ChangeLog.bugs | 5 +
 gcc/REVISION   | 2 +-
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/gcc/ChangeLog.bugs b/gcc/ChangeLog.bugs
new file mode 100644
index ..d33fbedd3542
--- /dev/null
+++ b/gcc/ChangeLog.bugs
@@ -0,0 +1,5 @@
+ Branch work196-bugs, baseline 
+
+2025-03-24   Michael Meissner  
+
+   Clone branch
diff --git a/gcc/REVISION b/gcc/REVISION
index 4879f9dc9d4e..e333906086e6 100644
--- a/gcc/REVISION
+++ b/gcc/REVISION
@@ -1 +1 @@
-work196 branch
+work196-bugs branch

[gcc(refs/users/meissner/heads/work196-test)] Add ChangeLog.test and update REVISION.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:e13267099bf9135d7ea12dbf6b6d6fbd097027f6

commit e13267099bf9135d7ea12dbf6b6d6fbd097027f6
Author: Michael Meissner 
Date:   Mon Mar 24 18:47:11 2025 -0400

Add ChangeLog.test and update REVISION.

2025-03-24  Michael Meissner  

gcc/

* ChangeLog.test: New file for branch.
* REVISION: Update.

Diff:
---
 gcc/ChangeLog.test | 5 +
 gcc/REVISION   | 2 +-
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/gcc/ChangeLog.test b/gcc/ChangeLog.test
new file mode 100644
index ..6fd56aa9a576
--- /dev/null
+++ b/gcc/ChangeLog.test
@@ -0,0 +1,5 @@
+ Branch work196-test, baseline 
+
+2025-03-24   Michael Meissner  
+
+   Clone branch
diff --git a/gcc/REVISION b/gcc/REVISION
index 4879f9dc9d4e..907a8cab2302 100644
--- a/gcc/REVISION
+++ b/gcc/REVISION
@@ -1 +1 @@
-work196 branch
+work196-test branch

[gcc(refs/users/meissner/heads/work196-vpair)] Vector pair support.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:c1b56fc0f3881361883b5194628f05a65a2ea91f

commit c1b56fc0f3881361883b5194628f05a65a2ea91f
Author: Michael Meissner 
Date:   Mon Mar 24 20:51:52 2025 -0400

Vector pair support.

This patch adds a new include file (vector-pair.h) that adds support so that
users writing high performance libraries can change their code to allow the
generation of the vector pair load and store instructions on power10.

The intention is that if the library authors need to write special loops 
that
go over arrays that they could modify their code to use the functions 
provided
to change loops that can take advantage of the higher bandwidth for load 
vector
pair and store instructions.

This particular patch just adds a new include file (vector-pair.h) that
provides a bunch of functions that on a power10 system would use the vector
pair load operation, 2 floating point operations, and a vector pair store.  
It
does not add any new types, modes, or built-in function.

I have additional patches that can add built-in functions that the 
functions in
vector-pair.h could utilize so that the compiler can optimize and combine
operations.  I may submit those patches in the future, but I would like to
provide this patch to allow the library writer to optimize their code.

I've measured the performance of these new functions on a power10.  For 
default
unrolling, the percentage of change for the 3 methods over the normal vector
loop method:

116%Vector-pair.h function, default unroll
 93%Vector pair split built-in & 2 vector stores, default unroll
 86%Vector pair split & combine built-ins, default unroll

Using explicit 2 way unrolling the numbers are:

114%Vector-pair.h function, unroll 2
106%Vector pair split built-in & 2 vector stores, unroll 2
 98%Vector pair split & combine built-ins, unroll 2

These new functions provided in vector-pair.h use the vector pair load/store
instructions, and don't generate extra vector moves.  Using the existing
vector pair disassemble and assemble built-ins generate extra vector moves
which can hinder performance.

If I compile the loop code for power9, there is a minor speed up for default
unrolling and more of an improvement using the framework provided in the
vector-pair.h for explicit unrolling by 2:

101%Vector-pair.h function, default unroll for power9
107%Vector-pair.h function, unroll 2 for power9

Of course this is a synthetic benchmark run on a quiet power10 system.  
Results
would vary for real code on real systems.  However, I feel adding these
functions can allow the writers of high performance libraries to better
optimize their code.

As an example, if the library wants to code a simple fused multiply-add 
loop,
they might write the code as follows:

#include 
#include 
#include 

void
fma_vector (double * __restrict__ r,
const double * __restrict__ a,
const double * __restrict__ b,
size_t n)
{
  vector double * __restrict__ vr = (vector double * __restrict__)r;
  const vector double * __restrict__ va = (const vector double * 
__restrict__)a;
  const vector double * __restrict__ vb = (const vector double * 
__restrict__)b;
  size_t num_elements = sizeof (vector double) / sizeof (double);
  size_t nv = n / num_elements;
  size_t i;

  for (i = 0; i < nv; i++)
vr[i] = __builtin_vsx_xvmadddp (va[i], vb[i], vr[i]);

  for (i = nv * num_elements; i < n; i++)
r[i] = fma (a[i], b[i], r[i]);
}

The inner loop would look like:

.L3:
lxvx 0,3,9
lxvx 12,4,9
addi 10,9,16
addi 2,2,-2
lxvx 11,5,9
xvmaddadp 0,12,11
lxvx 12,4,10
lxvx 11,5,10
stxvx 0,3,9
lxvx 0,3,10
addi 9,9,32
xvmaddadp 0,12,11
stxvx 0,3,10
bdnz .L3

Now if you code the loop to use __builtin_vsx_disassemble_pair to do a 
vector
pair load, but then do 2 vector stores:

#include 
#include 
#include 

void
fma_mma_ld (double * __restrict__ r,
const double * __restrict__ a,
const double * __restrict__ b,
size_t n)
{
  __vector_pair * __restrict__ vp_r

[gcc(refs/users/meissner/heads/work196-bugs)] Fix PR 118541, do not generate unordered fp cmoves for IEEE compares.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:f2c3aa312fd5497d2f591ef6ae4af6db9a522893

commit f2c3aa312fd5497d2f591ef6ae4af6db9a522893
Author: Michael Meissner 
Date:   Mon Mar 24 20:42:55 2025 -0400

Fix PR 118541, do not generate unordered fp cmoves for IEEE compares.

This is version 4 of the patch.

In version 4, I made the following changes:

1:  I changed the use of enums to match current C++.

In version 3, I made the following changes:

1:  The new argument to rs6000_reverse_condition that says whether we 
should
allow ordered floating point compares to be reversed is now an
enumeration instead of a boolean.

2:  I tried to make the code in rs6000_reverse_condition clearer.

3:  I added checks in invert_fpmask_comparison_operator to prevent 
ordered
floating point compares from being reversed unless -ffast-math.

4:  I split the test cases into 4 separate tests (ordered vs. unordered
compare and -O2 vs. -Ofast).

In bug PR target/118541 on power9, power10, and power11 systems, for the
function:

extern double __ieee754_acos (double);

double
__acospi (double x)
{
  double ret = __ieee754_acos (x) / 3.14;
  return __builtin_isgreater (ret, 1.0) ? 1.0 : ret;
}

GCC currently generates the following code:

Power9  Power10 and Power11
==  ===
bl __ieee754_acos   bl __ieee754_acos@notoc
nop plfd 0,.LC0@pcrel
addis 9,2,.LC2@toc@ha   xxspltidp 12,1065353216
addi 1,1,32 addi 1,1,32
lfd 0,.LC2@toc@l(9) ld 0,16(1)
addis 9,2,.LC0@toc@ha   fdiv 0,1,0
ld 0,16(1)  mtlr 0
lfd 12,.LC0@toc@l(9)xscmpgtdp 1,0,12
fdiv 0,1,0  xxsel 1,0,12,1
mtlr 0  blr
xscmpgtdp 1,0,12
xxsel 1,0,12,1
blr

This is because ifcvt.c optimizes the conditional floating point move to 
use the
XSCMPGTDP instruction.

However, the XSCMPGTDP instruction will generate an interrupt if one of the
arguments is a signalling NaN and signalling NaNs can generate an interrupt.
The IEEE comparison functions (isgreater, etc.) require that the comparison 
not
raise an interrupt.

The following patch changes the PowerPC back end so that ifcvt.c will not 
change
the if/then test and move into a conditional move if the comparison is one 
of
the comparisons that do not raise an error with signalling NaNs and -Ofast 
is
not used.  If a normal comparison is used or -Ofast is used, GCC will 
continue
to generate XSCMPGTDP and XXSEL.

For the following code:

double
ordered_compare (double a, double b, double c, double d)
{
  return __builtin_isgreater (a, b) ? c : d;
}

/* Verify normal > does generate xscmpgtdp.  */

double
normal_compare (double a, double b, double c, double d)
{
  return a > b ? c : d;
}

with the following patch, GCC generates the following for power9, power10, 
and
power11:

ordered_compare:
fcmpu 0,1,2
fmr 1,4
bnglr 0
fmr 1,3
blr

normal_compare:
xscmpgtdp 1,1,2
xxsel 1,4,3,1
blr

I have built bootstrap compilers on big endian power9 systems and little 
endian
power9/power10 systems and there were no regressions.  Can I check this 
patch
into the GCC trunk, and after a waiting period, can I check this into the 
active
older branches?

2025-03-24  Michael Meissner  

gcc/

PR target/118541
* config/rs6000/predicates.md (invert_fpmask_comparison_operator): 
Do
not allow UNLT and UNLE unless -ffast-math.
* config/rs6000/rs6000-protos.h (enum rev_cond_ordered): New 
enumeration.
(rs6000_reverse_condition): Add argument.
* config/rs6000/rs6000.cc (rs6000_reverse_condition): Do not allow
ordered comparisons to be reversed for floating point conditional 
moves,
but allow ordered comparisons to be reversed on jumps.
(rs6000_emit_sCOND): Adjust rs6000_reverse_condition call.
* config/rs6000/rs6000.h (REVERSE_CONDITION): Likewise.
* config/rs6000/rs6000.md (reverse_branch_comparison): Name insn.
Adjust rs6000_reverse_condition calls.
   

[gcc(refs/users/meissner/heads/work196-bugs)] Update ChangeLog.*

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:b18703561d282b2d4c65142a2f56061e373935c3

commit b18703561d282b2d4c65142a2f56061e373935c3
Author: Michael Meissner 
Date:   Mon Mar 24 20:45:22 2025 -0400

Update ChangeLog.*

Diff:
---
 gcc/ChangeLog.bugs | 297 +
 1 file changed, 297 insertions(+)

diff --git a/gcc/ChangeLog.bugs b/gcc/ChangeLog.bugs
index d33fbedd3542..93c16b2fc075 100644
--- a/gcc/ChangeLog.bugs
+++ b/gcc/ChangeLog.bugs
@@ -1,5 +1,302 @@
+ Branch work196-bugs, patch #210 
+
+Fix PR 118541, do not generate unordered fp cmoves for IEEE compares.
+
+This is version 4 of the patch.
+
+In version 4, I made the following changes:
+
+1: I changed the use of enums to match current C++.
+
+In version 3, I made the following changes:
+
+1: The new argument to rs6000_reverse_condition that says whether we should
+   allow ordered floating point compares to be reversed is now an
+   enumeration instead of a boolean.
+
+2: I tried to make the code in rs6000_reverse_condition clearer.
+
+3: I added checks in invert_fpmask_comparison_operator to prevent ordered
+   floating point compares from being reversed unless -ffast-math.
+
+4: I split the test cases into 4 separate tests (ordered vs. unordered
+   compare and -O2 vs. -Ofast).
+
+In bug PR target/118541 on power9, power10, and power11 systems, for the
+function:
+
+extern double __ieee754_acos (double);
+
+double
+__acospi (double x)
+{
+  double ret = __ieee754_acos (x) / 3.14;
+  return __builtin_isgreater (ret, 1.0) ? 1.0 : ret;
+}
+
+GCC currently generates the following code:
+
+Power9  Power10 and Power11
+==  ===
+bl __ieee754_acos   bl __ieee754_acos@notoc
+nop plfd 0,.LC0@pcrel
+addis 9,2,.LC2@toc@ha   xxspltidp 12,1065353216
+addi 1,1,32 addi 1,1,32
+lfd 0,.LC2@toc@l(9) ld 0,16(1)
+addis 9,2,.LC0@toc@ha   fdiv 0,1,0
+ld 0,16(1)  mtlr 0
+lfd 12,.LC0@toc@l(9)xscmpgtdp 1,0,12
+fdiv 0,1,0  xxsel 1,0,12,1
+mtlr 0  blr
+xscmpgtdp 1,0,12
+xxsel 1,0,12,1
+blr
+
+This is because ifcvt.c optimizes the conditional floating point move to use 
the
+XSCMPGTDP instruction.
+
+However, the XSCMPGTDP instruction will generate an interrupt if one of the
+arguments is a signalling NaN and signalling NaNs can generate an interrupt.
+The IEEE comparison functions (isgreater, etc.) require that the comparison not
+raise an interrupt.
+
+The following patch changes the PowerPC back end so that ifcvt.c will not 
change
+the if/then test and move into a conditional move if the comparison is one of
+the comparisons that do not raise an error with signalling NaNs and -Ofast is
+not used.  If a normal comparison is used or -Ofast is used, GCC will continue
+to generate XSCMPGTDP and XXSEL.
+
+For the following code:
+
+double
+ordered_compare (double a, double b, double c, double d)
+{
+  return __builtin_isgreater (a, b) ? c : d;
+}
+
+/* Verify normal > does generate xscmpgtdp.  */
+
+double
+normal_compare (double a, double b, double c, double d)
+{
+  return a > b ? c : d;
+}
+
+with the following patch, GCC generates the following for power9, power10, and
+power11:
+
+ordered_compare:
+fcmpu 0,1,2
+fmr 1,4
+bnglr 0
+fmr 1,3
+blr
+
+normal_compare:
+xscmpgtdp 1,1,2
+xxsel 1,4,3,1
+blr
+
+I have built bootstrap compilers on big endian power9 systems and little endian
+power9/power10 systems and there were no regressions.  Can I check this patch
+into the GCC trunk, and after a waiting period, can I check this into the 
active
+older branches?
+
+2025-03-24  Michael Meissner  
+
+gcc/
+
+   PR target/118541
+   * config/rs6000/predicates.md (invert_fpmask_comparison_operator): Do
+   not allow UNLT and UNLE unless -ffast-math.
+   * config/rs6000/rs6000-protos.h (enum rev_cond_ordered): New 
enumeration.
+   (rs6000_reverse_condition): Add argument.
+   * config/rs6000/rs6000.cc (rs6000_reverse_condition): Do not allow
+   ordered comparisons to be reversed for floating point conditional moves,
+   but allow ordered comparisons to be reversed on jumps.
+   (rs6000_emit_sCOND): Adjust rs6000_reverse_condition call.
+   * config/rs6000/rs6000.h (REVERSE_CONDITION): Likewise.
+   * config/rs6000/rs6000.md (reverse_branch_comparison): Name insn.
+   Adjust rs6000_reverse_condition calls.
+

[gcc(refs/users/meissner/heads/work196-sha)] PR target/117251: Add PowerPC XXEVAL support to speed up SHA3 calculations

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:00bd1eac96ffba0d8affc403d899ff76ae52bc2a

commit 00bd1eac96ffba0d8affc403d899ff76ae52bc2a
Author: Michael Meissner 
Date:   Mon Mar 24 20:47:04 2025 -0400

PR target/117251: Add PowerPC XXEVAL support to speed up SHA3 calculations

The multibuff.c benchmark attached to the PR target/117251 compiled for 
Power10
PowerPC that implement SHA3 has a slowdown in the current trunk and GCC 14
compared to GCC 11 - GCC 13, due to excessive amounts of spilling.

The main function for the multibuf.c file has 3,747 lines, all of which are
using vector unsigned long long.  There are 696 vector rotates (all rotates 
are
constant), 1,824 vector xor's and 600 vector andc's.

In looking at it, the main thing that steps out is the reason for either
spilling or moving variables is the support in fusion.md (generated by
genfusion.pl) that tries to fuse the vec_andc feeding into vec_xor, and 
other
vec_xor's feeding into vec_xor.

On the powerpc for power10, there is a special fusion mode that happens if 
the
machine has a VANDC or VXOR instruction that is adjacent to a VXOR 
instruction
and the VANDC/VXOR feeds into the 2nd VXOR instruction.

While the Power10 has 64 vector registers (which uses the XXL prefix to do
logical operations), the fusion only works with the older Altivec 
instruction
set (which uses the V prefix).  The Altivec instruction only has 32 vector
registers (which are overlaid over the VSX vector registers 32-63).

By having the combiner patterns fuse_vandc_vxor and fuse_vxor_vxor to do 
this
fusion, it means that the register allocator has more register pressure for 
the
traditional Altivec registers instead of the VSX registers.

In addition, since there are vector rotates, these rotates only work on the
traditional Altivec registers, which adds to the Altivec register pressure.

Finally in addition to doing the explicit xor, andc, and rotates using the
Altivec registers, we have to also load vector constants for the rotate 
amount
and these registers also are allocated as Altivec registers.

Current trunk and GCC 12-14 have more vector spills than GCC 11, but GCC 11 
has
many more vector moves that the later compilers.  Thus even though it has 
way
less spills, the vector moves are why GCC 11 have the slowest results.

There is an instruction that was added in power10 (XXEVAL) that does provide
fusion between VSX vectors that includes ANDC->XOR and XOR->XOR fusion.

The latency of XXEVAL is slightly more than the fused VANDC/VXOR or 
VXOR/VXOR,
so I have written the patch to prefer doing the Altivec instructions if they
don't need a temporary register.

Here are the results for adding support for XXEVAL for the multibuff.c
benchmark attached to the PR.  Note that we essentially recover the speed 
with
this patch that were lost with GCC 14 and the current trunk:

  XXEVALTrunk   GCC14   GCC13   GCC12
GCC11
  ---   -   -   -
-
Benchmark time in seconds   5.53 6.156.265.575.61 
9.56

Fuse VANDC -> VXOR   209 600  600 600 600  
600
Fuse VXOR -> VXOR  0 240  240 120 120  
120
XXEVAL to fuse ANDC -> XOR   391   00   0   0   
 0
XXEVAL to fuse XOR -> XOR240   00   0   0   
 0

Spill vector to stack 78 364  364 172 184  
110
Load spilled vector from stack   431 962  962 713 723  
166
Vector moves  10 100  100  70  72
3,055

Vector rotate right  696 696  696 696 696  
696
XXLANDC or VANDC 209 600  600 600 600  
600
XXLXOR or VXOR   953   1,8241,824   1,824   1,824
1,825
XXEVAL   631   00   0   0   
 0

Load vector rotate constants  24  24   24  24  24   
24

Here are the results for adding support for XXEVAL for the singlebuff.c
benchmark attached to the PR.  Note that adding XXEVAL greatly speeds up 
this
particular benchmark:

  XXEVALTrunk   GCC14   GCC13   GCC12
GCC11
  ---   -   -   -
-
Benchmark time in seconds   4.46 5.405.405.355.36 
7.54

Fuse VANDC -> VXOR   210  600 600 600 600  
600
Fuse VXOR -> VXOR  0  240 240 120 120  
120
XXEVAL to fuse ANDC -> XOR   3900   0 

[gcc(refs/users/meissner/heads/work196-sha)] Add potential p-future XVRLD and XVRLDI instructions.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:9cd8fb51efd2b081dcbfd0505f129138519cab1e

commit 9cd8fb51efd2b081dcbfd0505f129138519cab1e
Author: Michael Meissner 
Date:   Mon Mar 24 20:47:47 2025 -0400

Add potential p-future XVRLD and XVRLDI instructions.

2025-03-24  Michael Meissner  

gcc/

* config/rs6000/altivec.md (altivec_vrl): Add support for a
possible XVRLD instruction in the future.
(altivec_vrl_immediate): New insns.
* config/rs6000/predicates.md (vector_shift_immediate): New 
predicate.
* config/rs6000/rs6000.h (TARGET_XVRLW): New macro.
* config/rs6000/rs6000.md (isa attribute): Add xvrlw.
(enabled attribute): Add support for xvrlw.

gcc/testsuite/

* gcc.target/powerpc/vector-rotate-left.c: New test.
* lib/target-supports.exp 
(check_effective_target_powerpc_future_ok):
Add support to test -mcpu=future.

Diff:
---
 gcc/config/rs6000/altivec.md   | 35 +++---
 gcc/config/rs6000/predicates.md| 26 
 gcc/config/rs6000/rs6000.h |  3 ++
 gcc/config/rs6000/rs6000.md|  6 +++-
 .../gcc.target/powerpc/vector-rotate-left.c| 34 +
 gcc/testsuite/lib/target-supports.exp  | 12 
 6 files changed, 111 insertions(+), 5 deletions(-)

diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
index 7edc288a6565..013960438b04 100644
--- a/gcc/config/rs6000/altivec.md
+++ b/gcc/config/rs6000/altivec.md
@@ -1982,12 +1982,39 @@
 }
   [(set_attr "type" "vecperm")])
 
+;; -mcpu=future adds a vector rotate left word variant.  There is no vector
+;; byte/half-word/double-word/quad-word rotate left.  This insn occurs before
+;; altivec_vrl and will match for -mcpu=future, while other cpus will
+;; match the generic insn.
+;; However for testing, allow other xvrl variants.  In particular, XVRLD for
+;; the sha3 tests for multibuf/singlebuf.
 (define_insn "altivec_vrl"
-  [(set (match_operand:VI2 0 "register_operand" "=v")
-(rotate:VI2 (match_operand:VI2 1 "register_operand" "v")
-   (match_operand:VI2 2 "register_operand" "v")))]
+  [(set (match_operand:VI2 0 "register_operand" "=v,wa")
+(rotate:VI2 (match_operand:VI2 1 "register_operand" "v,wa")
+   (match_operand:VI2 2 "register_operand" "v,wa")))]
   ""
-  "vrl %0,%1,%2"
+  "@
+   vrl %0,%1,%2
+   xvrl %x0,%x1,%x2"
+  [(set_attr "type" "vecsimple")
+   (set_attr "isa" "*,xvrlw")])
+
+(define_insn "*altivec_vrl_immediate"
+  [(set (match_operand:VI2 0 "register_operand" "=wa,wa,wa,wa")
+   (rotate:VI2 (match_operand:VI2 1 "register_operand" "wa,wa,wa,wa")
+   (match_operand:VI2 2 "vector_shift_immediate" 
"j,wM,wE,wS")))]
+  "TARGET_XVRLW && "
+{
+  rtx op2 = operands[2];
+  int value = 256;
+  int num_insns = -1;
+
+  if (!xxspltib_constant_p (op2, mode, &num_insns, &value))
+gcc_unreachable ();
+
+  operands[3] = GEN_INT (value & 0xff);
+  return "xvrli %x0,%x1,%3";
+}
   [(set_attr "type" "vecsimple")])
 
 (define_insn "altivec_vrlq"
diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md
index 6485ee3eeecc..276812573977 100644
--- a/gcc/config/rs6000/predicates.md
+++ b/gcc/config/rs6000/predicates.md
@@ -728,6 +728,32 @@
   return num_insns == 1;
 })
 
+;; Return 1 if the operand is a CONST_VECTOR whose elements are all the
+;; same and the elements can be an immediate shift or rotate factor
+(define_predicate "vector_shift_immediate"
+  (match_code "const_vector,vec_duplicate,const_int")
+{
+  int value = 256;
+  int num_insns = -1;
+
+  if (zero_constant (op, mode) || all_ones_constant (op, mode))
+return true;
+
+  if (!xxspltib_constant_p (op, mode, &num_insns, &value))
+return false;
+
+  switch (mode)
+{
+case V16QImode: return IN_RANGE (value, 0, 7);
+case V8HImode:  return IN_RANGE (value, 0, 15);
+case V4SImode:  return IN_RANGE (value, 0, 31);
+case V2DImode:  return IN_RANGE (value, 0, 63);
+default:break;
+}
+
+  return false;
+})
+  
 ;; Return 1 if the operand is a CONST_VECTOR and can be loaded into a
 ;; vector register without using memory.
 (define_predicate "easy_vector_constant"
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 9267612fbc9c..d414bc539207 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -575,6 +575,9 @@ extern int rs6000_vector_align[];
below.  */
 #define RS6000_FN_TARGET_INFO_HTM 1
 
+/* Whether we have XVRLW support.  */
+#define TARGET_XVRLW   TARGET_FUTURE
+
 /* Whether the various reciprocal divide/square root estimate instructions
exist, and whether we should automatically generate code for the instruction
by default.  */
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 3b

[gcc(refs/users/meissner/heads/work196-sha)] Update ChangeLog.*

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:cd10c577b5cc99cb01ce6524667f06cd8b239783

commit cd10c577b5cc99cb01ce6524667f06cd8b239783
Author: Michael Meissner 
Date:   Mon Mar 24 20:49:50 2025 -0400

Update ChangeLog.*

Diff:
---
 gcc/ChangeLog.sha | 168 ++
 1 file changed, 168 insertions(+)

diff --git a/gcc/ChangeLog.sha b/gcc/ChangeLog.sha
index a0b372938ef1..b9d148071682 100644
--- a/gcc/ChangeLog.sha
+++ b/gcc/ChangeLog.sha
@@ -1,5 +1,173 @@
+ Branch work196-sha, patch #401 
+
+Add potential p-future XVRLD and XVRLDI instructions.
+
+2025-03-24  Michael Meissner  
+
+gcc/
+
+   * config/rs6000/altivec.md (altivec_vrl): Add support for a
+   possible XVRLD instruction in the future.
+   (altivec_vrl_immediate): New insns.
+   * config/rs6000/predicates.md (vector_shift_immediate): New predicate.
+   * config/rs6000/rs6000.h (TARGET_XVRLW): New macro.
+   * config/rs6000/rs6000.md (isa attribute): Add xvrlw.
+   (enabled attribute): Add support for xvrlw.
+
+gcc/testsuite/
+
+   * gcc.target/powerpc/vector-rotate-left.c: New test.
+   * lib/target-supports.exp (check_effective_target_powerpc_future_ok):
+   Add support to test -mcpu=future.
+
+ Branch work196-sha, patch #400 
+
+PR target/117251: Add PowerPC XXEVAL support to speed up SHA3 calculations
+
+The multibuff.c benchmark attached to the PR target/117251 compiled for Power10
+PowerPC that implement SHA3 has a slowdown in the current trunk and GCC 14
+compared to GCC 11 - GCC 13, due to excessive amounts of spilling.
+
+The main function for the multibuf.c file has 3,747 lines, all of which are
+using vector unsigned long long.  There are 696 vector rotates (all rotates are
+constant), 1,824 vector xor's and 600 vector andc's.
+
+In looking at it, the main thing that steps out is the reason for either
+spilling or moving variables is the support in fusion.md (generated by
+genfusion.pl) that tries to fuse the vec_andc feeding into vec_xor, and other
+vec_xor's feeding into vec_xor.
+
+On the powerpc for power10, there is a special fusion mode that happens if the
+machine has a VANDC or VXOR instruction that is adjacent to a VXOR instruction
+and the VANDC/VXOR feeds into the 2nd VXOR instruction.
+
+While the Power10 has 64 vector registers (which uses the XXL prefix to do
+logical operations), the fusion only works with the older Altivec instruction
+set (which uses the V prefix).  The Altivec instruction only has 32 vector
+registers (which are overlaid over the VSX vector registers 32-63).
+
+By having the combiner patterns fuse_vandc_vxor and fuse_vxor_vxor to do this
+fusion, it means that the register allocator has more register pressure for the
+traditional Altivec registers instead of the VSX registers.
+
+In addition, since there are vector rotates, these rotates only work on the
+traditional Altivec registers, which adds to the Altivec register pressure.
+
+Finally in addition to doing the explicit xor, andc, and rotates using the
+Altivec registers, we have to also load vector constants for the rotate amount
+and these registers also are allocated as Altivec registers.
+
+Current trunk and GCC 12-14 have more vector spills than GCC 11, but GCC 11 has
+many more vector moves that the later compilers.  Thus even though it has way
+less spills, the vector moves are why GCC 11 have the slowest results.
+
+There is an instruction that was added in power10 (XXEVAL) that does provide
+fusion between VSX vectors that includes ANDC->XOR and XOR->XOR fusion.
+
+The latency of XXEVAL is slightly more than the fused VANDC/VXOR or VXOR/VXOR,
+so I have written the patch to prefer doing the Altivec instructions if they
+don't need a temporary register.
+
+Here are the results for adding support for XXEVAL for the multibuff.c
+benchmark attached to the PR.  Note that we essentially recover the speed with
+this patch that were lost with GCC 14 and the current trunk:
+
+  XXEVALTrunk   GCC14   GCC13   GCC12GCC11
+  ---   -   -   --
+Benchmark time in seconds   5.53 6.156.265.575.61 9.56
+
+Fuse VANDC -> VXOR   209 600  600 600 600  600
+Fuse VXOR -> VXOR  0 240  240 120 120  120
+XXEVAL to fuse ANDC -> XOR   391   00   0   00
+XXEVAL to fuse XOR -> XOR240   00   0   00
+
+Spill vector to stack 78 364  364 172 184  110
+Load spilled vector from stack   431 962  962 713 723  166
+Vector moves  10 100  100  70  723,055
+
+Vector rotate right  696 696  696 696 696  696
+XXLANDC or VANDC 209 600  600 600 

[gcc(refs/users/meissner/heads/work196-vpair)] Update ChangeLog.*

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:646a4d547c444b13a10452d222f3f430b6d9d4b2

commit 646a4d547c444b13a10452d222f3f430b6d9d4b2
Author: Michael Meissner 
Date:   Mon Mar 24 20:53:45 2025 -0400

Update ChangeLog.*

Diff:
---
 gcc/ChangeLog.vpair | 420 
 1 file changed, 420 insertions(+)

diff --git a/gcc/ChangeLog.vpair b/gcc/ChangeLog.vpair
index c4fbc1a7f8b0..e3311a6df36c 100644
--- a/gcc/ChangeLog.vpair
+++ b/gcc/ChangeLog.vpair
@@ -1,5 +1,425 @@
+ Branch work196-vpair, patch #300 
+
+Vector pair support.
+
+This patch adds a new include file (vector-pair.h) that adds support so that
+users writing high performance libraries can change their code to allow the
+generation of the vector pair load and store instructions on power10.
+
+The intention is that if the library authors need to write special loops that
+go over arrays that they could modify their code to use the functions provided
+to change loops that can take advantage of the higher bandwidth for load vector
+pair and store instructions.
+
+This particular patch just adds a new include file (vector-pair.h) that
+provides a bunch of functions that on a power10 system would use the vector
+pair load operation, 2 floating point operations, and a vector pair store.  It
+does not add any new types, modes, or built-in function.
+
+I have additional patches that can add built-in functions that the functions in
+vector-pair.h could utilize so that the compiler can optimize and combine
+operations.  I may submit those patches in the future, but I would like to
+provide this patch to allow the library writer to optimize their code.
+
+I've measured the performance of these new functions on a power10.  For default
+unrolling, the percentage of change for the 3 methods over the normal vector
+loop method:
+
+   116%Vector-pair.h function, default unroll
+93%Vector pair split built-in & 2 vector stores, default unroll
+86%Vector pair split & combine built-ins, default unroll
+
+Using explicit 2 way unrolling the numbers are:
+
+   114%Vector-pair.h function, unroll 2
+   106%Vector pair split built-in & 2 vector stores, unroll 2
+98%Vector pair split & combine built-ins, unroll 2
+
+These new functions provided in vector-pair.h use the vector pair load/store
+instructions, and don't generate extra vector moves.  Using the existing
+vector pair disassemble and assemble built-ins generate extra vector moves
+which can hinder performance.
+
+If I compile the loop code for power9, there is a minor speed up for default
+unrolling and more of an improvement using the framework provided in the
+vector-pair.h for explicit unrolling by 2:
+
+   101%Vector-pair.h function, default unroll for power9
+   107%Vector-pair.h function, unroll 2 for power9
+
+Of course this is a synthetic benchmark run on a quiet power10 system.  Results
+would vary for real code on real systems.  However, I feel adding these
+functions can allow the writers of high performance libraries to better
+optimize their code.
+
+As an example, if the library wants to code a simple fused multiply-add loop,
+they might write the code as follows:
+
+   #include 
+   #include 
+   #include 
+
+   void
+   fma_vector (double * __restrict__ r,
+   const double * __restrict__ a,
+   const double * __restrict__ b,
+   size_t n)
+   {
+ vector double * __restrict__ vr = (vector double * __restrict__)r;
+ const vector double * __restrict__ va = (const vector double * 
__restrict__)a;
+ const vector double * __restrict__ vb = (const vector double * 
__restrict__)b;
+ size_t num_elements = sizeof (vector double) / sizeof (double);
+ size_t nv = n / num_elements;
+ size_t i;
+
+ for (i = 0; i < nv; i++)
+   vr[i] = __builtin_vsx_xvmadddp (va[i], vb[i], vr[i]);
+
+ for (i = nv * num_elements; i < n; i++)
+   r[i] = fma (a[i], b[i], r[i]);
+   }
+
+The inner loop would look like:
+
+   .L3:
+   lxvx 0,3,9
+   lxvx 12,4,9
+   addi 10,9,16
+   addi 2,2,-2
+   lxvx 11,5,9
+   xvmaddadp 0,12,11
+   lxvx 12,4,10
+   lxvx 11,5,10
+   stxvx 0,3,9
+   lxvx 0,3,10
+   addi 9,9,32
+   xvmaddadp 0,12,11
+   stxvx 0,3,10
+   bdnz .L3
+
+Now if you code the loop to use __builtin_vsx_disassemble_pair to do a vector
+pair load, but then do 2 vector stores:
+
+
+   #include 
+   #include 
+   #include 
+
+   void
+   fma_mma_ld (double * __restrict__ r,
+   const double * __restrict__ a,
+   const double * __restrict__ b,
+   size_t n)
+   {
+ __vector_pair * __restrict__ vp_r

[gcc(refs/users/meissner/heads/work196-math)] Merge commit 'refs/users/meissner/heads/work196-math' of git+ssh://gcc.gnu.org/git/gcc into me/work1

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:5b27a9f6d7bb840570378abe94897428250f78fe

commit 5b27a9f6d7bb840570378abe94897428250f78fe
Merge: 56203bba1a63 e07838f07364
Author: Michael Meissner 
Date:   Mon Mar 24 19:29:00 2025 -0400

Merge commit 'refs/users/meissner/heads/work196-math' of 
git+ssh://gcc.gnu.org/git/gcc into me/work196-math

Diff:

[gcc(refs/users/meissner/heads/work196)] Change TARGET_POPCNTB to TARGET_POWER5.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:a7fbb5806370cde50ff726c2fd0884c0c1265ed6

commit a7fbb5806370cde50ff726c2fd0884c0c1265ed6
Author: Michael Meissner 
Date:   Mon Mar 24 19:06:03 2025 -0400

Change TARGET_POPCNTB to TARGET_POWER5.

This patch changes TARGET_POPCNTB to TARGET_POWER5.  The -mpopcntb switch 
is not
being changed in this patch, just the name of the macros used to determine 
if
the PowerPC processor supports ISA 2.2 (Power5).

2025-03-24  Michael Meissner  

gcc/

* gcc/config/rs6000/rs6000-builtin.cc (rs6000_builtin_is_supported):
Change TARGET_POPCNTB to TARGET_POWER5.
* gcc/config/rs6000/rs6000.cc (rs6000_option_override_internal):
Likewise.
* gcc/config/rs6000/rs6000.h (TARGET_FCFID): Likewise.
(TARGET_POWER5): New macro.
(TARGET_EXTRA_BUILTINS): Change TARGET_POPCNTB to TARGET_POWER5.
(TARGET_FRE): Likewise.
(TARGET_FRSQRTES): Likewise.
* gcc/config/rs6000/rs6000.md (enabled attribute): Likewise.

Diff:
---
 gcc/config/rs6000/rs6000-builtin.cc |  2 +-
 gcc/config/rs6000/rs6000.cc |  2 +-
 gcc/config/rs6000/rs6000.h  | 11 +++
 gcc/config/rs6000/rs6000.md |  2 +-
 4 files changed, 10 insertions(+), 7 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-builtin.cc 
b/gcc/config/rs6000/rs6000-builtin.cc
index 111802381acb..4ed2bc1ca89e 100644
--- a/gcc/config/rs6000/rs6000-builtin.cc
+++ b/gcc/config/rs6000/rs6000-builtin.cc
@@ -155,7 +155,7 @@ rs6000_builtin_is_supported (enum rs6000_gen_builtins 
fncode)
 case ENB_ALWAYS:
   return true;
 case ENB_P5:
-  return TARGET_POPCNTB;
+  return TARGET_POWER5;
 case ENB_P6:
   return TARGET_CMPB;
 case ENB_P6_64:
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 737c3d6f7c75..a5ed93702494 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -3926,7 +3926,7 @@ rs6000_option_override_internal (bool global_init_p)
 rs6000_isa_flags |= (ISA_2_5_MASKS_EMBEDDED & ~ignore_masks);
   else if (TARGET_FPRND)
 rs6000_isa_flags |= (ISA_2_4_MASKS & ~ignore_masks);
-  else if (TARGET_POPCNTB)
+  else if (TARGET_POWER5)
 rs6000_isa_flags |= (ISA_2_2_MASKS & ~ignore_masks);
   else if (TARGET_ALTIVEC)
 rs6000_isa_flags |= (OPTION_MASK_PPC_GFXOPT & ~ignore_masks);
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index db6112a09e11..d9a0ffe9f5b2 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -448,7 +448,7 @@ extern int rs6000_vector_align[];
Enable 32-bit fcfid's on any of the switches for newer ISA machines.  */
 #define TARGET_FCFID   (TARGET_POWERPC64   \
 || TARGET_PPC_GPOPT/* 970/power4 */\
-|| TARGET_POPCNTB  /* ISA 2.02 */  \
+|| TARGET_POWER5   /* ISA 2.02 */  \
 || TARGET_CMPB /* ISA 2.05 */  \
 || TARGET_POPCNTD) /* ISA 2.06 */
 
@@ -499,6 +499,9 @@ extern int rs6000_vector_align[];
 #define TARGET_MINMAX  (TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT \
 && (TARGET_P9_MINMAX || !flag_trapping_math))
 
+/* Convert ISA bits like POPCNTB to PowerPC processors like POWER5.  */
+#define TARGET_POWER5  TARGET_POPCNTB
+
 /* In switching from using target_flags to using rs6000_isa_flags, the options
machinery creates OPTION_MASK_ instead of MASK_.  The MASK_
options that have not yet been replaced by their OPTION_MASK_
@@ -525,7 +528,7 @@ extern int rs6000_vector_align[];
 
 #define TARGET_EXTRA_BUILTINS  (TARGET_POWERPC64\
 || TARGET_PPC_GPOPT /* 970/power4 */\
-|| TARGET_POPCNTB   /* ISA 2.02 */  \
+|| TARGET_POWER5/* ISA 2.02 */  \
 || TARGET_CMPB  /* ISA 2.05 */  \
 || TARGET_POPCNTD   /* ISA 2.06 */  \
 || TARGET_ALTIVEC   \
@@ -541,9 +544,9 @@ extern int rs6000_vector_align[];
 #define TARGET_FRES(TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT)
 
 #define TARGET_FRE (TARGET_HARD_FLOAT \
-&& (TARGET_POPCNTB || VECTOR_UNIT_VSX_P (DFmode)))
+&& (TARGET_POWER5 || VECTOR_UNIT_VSX_P (DFmode)))
 
-#define TARGET_FRSQRTES(TARGET_HARD_FLOAT && TARGET_POPCNTB \
+#define TARGET_FRSQRTES(TARGET_HARD_FLOAT && TARGET_POWER5 \
 && TARGET_PPC_GFXOPT)
 
 #define TARGET_FRSQRTE (TARGET_HARD_FLOAT \
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 9c718ca2a226..c5bd273be8b3 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs

[gcc(refs/users/meissner/heads/work196-bugs)] Merge commit 'refs/users/meissner/heads/work196-bugs' of git+ssh://gcc.gnu.org/git/gcc into me/work1

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:9240cc2e3381fe6c95b26c6cdd24aca1cd242bf7

commit 9240cc2e3381fe6c95b26c6cdd24aca1cd242bf7
Merge: cd8e607a4492 5e4fe73897f4
Author: Michael Meissner 
Date:   Mon Mar 24 19:25:22 2025 -0400

Merge commit 'refs/users/meissner/heads/work196-bugs' of 
git+ssh://gcc.gnu.org/git/gcc into me/work196-bugs

Diff:

[gcc(refs/users/meissner/heads/work196-bugs)] Add power9 and power10 float to logical optimizations.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:31f567fbc025a12e21e544806085c433d1883809

commit 31f567fbc025a12e21e544806085c433d1883809
Author: Michael Meissner 
Date:   Mon Mar 24 19:56:01 2025 -0400

Add power9 and power10 float to logical optimizations.

I was answering an email from a co-worker and I pointed him to work I had 
done
for the Power8 era that optimizes the 32-bit float math library in Glibc.  
In
doing so, I discovered with the Power9 and later computers, this 
optimization
is no longer taking place.

The glibc 32-bit floating point math functions have code that looks like:

union u {
  float f;
  uint32_t u32;
};

float
math_foo (float x, unsigned int mask)
{
  union u arg;
  float x2;

  arg.f = x;
  arg.u32 &= mask;

  x2 = arg.f;
  /* ... */
}

On power8 with the optimization it generates:

xscvdpspn 0,1
sldi 9,4,32
mtvsrd 32,9
xxland 1,0,32
xscvspdpn 1,1

I.e., it converts the SFmode to the memory format (instead of the DFmode 
that
is used within the register), converts the mask so that it is in the vector
register in the upper 32-bits, and does a XXLAND (i.e. there is only one 
direct
move from GPR to vector register).  Then after doing this, it converts the
upper 32-bits back to DFmode.

If the XSCVSPDN instruction took the value in the normal 32-bit scalar in a
vector register, we wouldn't have needed the SLDI of the mask.

On power9/power10/power11 it currently generates:

xscvdpspn 0,1
mfvsrwz 2,0
and 2,2,4
mtvsrws 1,2
xscvspdpn 1,1
blr

I.e convert to SFmode representation, move the value to a GPR, do an AND
operation, move the 32-bit value with a splat, and then convert it back to
DFmode format.

With this patch, it now generates:

xscvdpspn 0,1
mtvsrwz 32,2
xxland 32,0,32
xxspltw 1,32,1
xscvspdpn 1,1
blr

I.e. convert to SFmode representation, move the mask to the vector 
register, do
the operation using XXLAND.  Splat the value to get the value in the correct
location, and then convert back to DFmode.

I have built GCC with the patches in this patch set applied on both little 
and
big endian PowerPC systems and there were no regressions.  Can I apply this
patch to GCC 15?

2025-03-24  Michael Meissner  

gcc/

PR target/117487
* config/rs6000/vsx.md (SFmode logical peephoole): Update comments 
in
the original code that supports power8.  Add a new define_peephole2 
to
do the optimization on power9/power10.

Diff:
---
 gcc/config/rs6000/vsx.md| 142 +++-
 gcc/testsuite/gcc.target/powerpc/pr108958.c |   0
 2 files changed, 137 insertions(+), 5 deletions(-)

diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index d84a2a357a31..f47c4e2f7766 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -6282,7 +6282,7 @@
(SFBOOL_MFVSR_A  3) ;; move to gpr src
(SFBOOL_BOOL_D   4) ;; and/ior/xor dest
(SFBOOL_BOOL_A1  5) ;; and/ior/xor arg1
-   (SFBOOL_BOOL_A2  6) ;; and/ior/xor arg1
+   (SFBOOL_BOOL_A2  6) ;; and/ior/xor arg2
(SFBOOL_SHL_D7) ;; shift left dest
(SFBOOL_SHL_A8) ;; shift left arg
(SFBOOL_MTVSR_D  9) ;; move to vecter dest
@@ -6322,18 +6322,18 @@
 ;; GPR, and instead move the integer mask value to the vector register after a
 ;; shift and do the VSX logical operation.
 
-;; The insns for dealing with SFmode in GPR registers looks like:
+;; The insns for dealing with SFmode in GPR registers looks like on power8:
 ;; (set (reg:V4SF reg2) (unspec:V4SF [(reg:SF reg1)] UNSPEC_VSX_CVDPSPN))
 ;;
-;; (set (reg:DI reg3) (unspec:DI [(reg:V4SF reg2)] UNSPEC_P8V_RELOAD_FROM_VSX))
+;; (set (reg:DI reg3) (zero_extend:DI (reg:SI reg2)))
 ;;
-;; (set (reg:DI reg4) (and:DI (reg:DI reg3) (reg:DI reg3)))
+;; (set (reg:DI reg4) (and:SI (reg:SI reg3) (reg:SI mask)))
 ;;
 ;; (set (reg:DI reg5) (ashift:DI (reg:DI reg4) (const_int 32)))
 ;;
 ;; (set (reg:SF reg6) (unspec:SF [(reg:DI reg5)] UNSPEC_P8V_MTVSRD))
 ;;
-;; (set (reg:SF reg6) (unspec:SF [(reg:SF reg6)] UNSPEC_VSX_CVSPDPN))
+;; (set (reg:SF reg7) (unspec:SF [(reg:SF reg6)] UNSPEC_VSX_CVSPDPN))
 
 (define_peephole2
   [(match_scratch:DI SFBOOL_TMP_GPR "r")
@@ -6414,6 +6414,138 @@
   operands[SFBOOL_MTVSR_D_V4SF] = gen_rtx_REG (V4SFmode, regno_mtvsr_d);
 })
 
+;; Constants for 

[gcc(refs/users/meissner/heads/work196)] Change TARGET_MODULO to TARGET_POWER9.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:c91f9a88252ddc1a3b5d7c79b629f2545702f64c

commit c91f9a88252ddc1a3b5d7c79b629f2545702f64c
Author: Michael Meissner 
Date:   Mon Mar 24 19:09:31 2025 -0400

Change TARGET_MODULO to TARGET_POWER9.

This patch changes TARGET_MODULO to TARGET_POWER9.  The -mmodulo switch is 
not
being changed, just the name of the macros used to determine if the PowerPC
processor supports ISA 3.0 (Power9).

2025-03-24  Michael Meissner  

gcc/

* gcc/config/rs6000/rs6000-builtin.cc (rs6000_builtin_is_supported):
Change TARGET_MODULO to TARGET_POWER9.
* gcc/config/rs6000/rs6000.cc (rs6000_option_override_internal):
Likewise.
* gcc/config/rs6000/rs6000.h (TARGET_CTZ): Likewise.
(TARGET_EXTSWSLI): Likewise.
(TARGET_MADDLD): Likewise.
(TARGET_POWER9): New macro.
* gcc/config/rs6000/rs6000.md (enabled attribute): Change 
TARGET_MODULO
to TARGET_POWER9.
(mod3): Likewise.
(umod3): Likewise.
(divide/modulo peephole2): Likewise.

Diff:
---
 gcc/config/rs6000/rs6000-builtin.cc |  4 ++--
 gcc/config/rs6000/rs6000.cc |  4 ++--
 gcc/config/rs6000/rs6000.h  |  7 ---
 gcc/config/rs6000/rs6000.md | 14 +++---
 4 files changed, 15 insertions(+), 14 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-builtin.cc 
b/gcc/config/rs6000/rs6000-builtin.cc
index 2366b2aee00a..d8ff7cf32dfd 100644
--- a/gcc/config/rs6000/rs6000-builtin.cc
+++ b/gcc/config/rs6000/rs6000-builtin.cc
@@ -169,9 +169,9 @@ rs6000_builtin_is_supported (enum rs6000_gen_builtins 
fncode)
 case ENB_P8V:
   return TARGET_P8_VECTOR;
 case ENB_P9:
-  return TARGET_MODULO;
+  return TARGET_POWER9;
 case ENB_P9_64:
-  return TARGET_MODULO && TARGET_POWERPC64;
+  return TARGET_POWER9 && TARGET_POWERPC64;
 case ENB_P9V:
   return TARGET_P9_VECTOR;
 case ENB_P10:
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 503b07339647..8d97b265ac91 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -3888,7 +3888,7 @@ rs6000_option_override_internal (bool global_init_p)
 
   /* For the newer switches (vsx, dfp, etc.) set some of the older options,
  unless the user explicitly used the -mno- to disable the code.  */
-  if (TARGET_P9_VECTOR || TARGET_MODULO || TARGET_P9_MISC)
+  if (TARGET_P9_VECTOR || TARGET_POWER9 || TARGET_P9_MISC)
 rs6000_isa_flags |= (ISA_3_0_MASKS_SERVER & ~ignore_masks);
   else if (TARGET_P9_MINMAX)
 {
@@ -22377,7 +22377,7 @@ rs6000_rtx_costs (rtx x, machine_mode mode, int 
outer_code,
*total = rs6000_cost->divsi;
}
   /* Add in shift and subtract for MOD unless we have a mod instruction. */
-  if ((!TARGET_MODULO
+  if ((!TARGET_POWER9
   || (RS6000_DISABLE_SCALAR_MODULO && SCALAR_INT_MODE_P (mode)))
 && (code == MOD || code == UMOD))
*total += COSTS_N_INSNS (2);
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index f1da5d31441a..c2f1910b0ea2 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -463,9 +463,9 @@ extern int rs6000_vector_align[];
 #define TARGET_FCTIWUZ TARGET_POWER7
 /* Only powerpc64 and powerpc476 support fctid.  */
 #define TARGET_FCTID   (TARGET_POWERPC64 || rs6000_cpu == PROCESSOR_PPC476)
-#define TARGET_CTZ TARGET_MODULO
-#define TARGET_EXTSWSLI(TARGET_MODULO && TARGET_POWERPC64)
-#define TARGET_MADDLD  TARGET_MODULO
+#define TARGET_CTZ TARGET_POWER9
+#define TARGET_EXTSWSLI(TARGET_POWER9 && TARGET_POWERPC64)
+#define TARGET_MADDLD  TARGET_POWER9
 
 /* TARGET_DIRECT_MOVE is redundant to TARGET_P8_VECTOR, so alias it to that.  
*/
 #define TARGET_DIRECT_MOVE TARGET_P8_VECTOR
@@ -504,6 +504,7 @@ extern int rs6000_vector_align[];
 #define TARGET_POWER5X TARGET_FPRND
 #define TARGET_POWER6  TARGET_CMPB
 #define TARGET_POWER7  TARGET_POPCNTD
+#define TARGET_POWER9  TARGET_MODULO
 
 /* In switching from using target_flags to using rs6000_isa_flags, the options
machinery creates OPTION_MASK_ instead of MASK_.  The MASK_
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 87ec37a9f8e4..db1b6c2d1164 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -403,7 +403,7 @@
  (const_int 1)
 
  (and (eq_attr "isa" "p9")
- (match_test "TARGET_MODULO"))
+ (match_test "TARGET_POWER9"))
  (const_int 1)
 
  (and (eq_attr "isa" "p9v")
@@ -3457,7 +3457,7 @@
   || INTVAL (operands[2]) <= 0
   || (i = exact_log2 (INTVAL (operands[2]))) < 0)
 {
-  if (!TARGET_MODULO)
+  if (!TARGET_POWER9)
FAIL;
 
   operands[2] = force_reg (mode, operands[2]);
@@ -3491,7 +3491,7 @@
   [(set (match_operand:GPR 0 "gpc_reg_operand" "=&r,r")
 (mod:GPR (match_oper

[gcc(refs/users/meissner/heads/work196-dmf)] RFC2653-Add support for dense math registers.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:7feb61c5528eaf2098399d23e4ce351659be7c11

commit 7feb61c5528eaf2098399d23e4ce351659be7c11
Author: Michael Meissner 
Date:   Mon Mar 24 19:43:33 2025 -0400

RFC2653-Add support for dense math registers.

The MMA subsystem added the notion of accumulator registers as an optional
feature of ISA 3.1 (power10).  In ISA 3.1, these accumulators overlapped 
with
the VSX registers 0..31, but logically the accumulator registers were 
separate
from the FPR registers.  In ISA 3.1, it was anticipated that in future 
systems,
the accumulator registers may no overlap with the FPR registers.  This patch
adds the support for dense math registers as separate registers.

This particular patch does not change the MMA support to use the 
accumulators
within the dense math registers.  This patch just adds the basic support for
having separate DMRs.  The next patch will switch the MMA support to use the
accumulators if -mcpu=future is used.

For testing purposes, I added an undocumented option '-mdense-math' to 
enable
or disable the dense math support.

This patch updates the wD constraint added in the previous patch.  If MMA is
selected but dense math is not selected (i.e. -mcpu=power10), the wD 
constraint
will allow access to accumulators that overlap with VSX registers 0..31.  If
both MMA and dense math are selected (i.e. -mcpu=future), the wD constraint
will only allow dense math registers.

This patch modifies the existing %A output modifier.  If MMA is selected but
dense math is not selected, then %A output modifier converts the VSX 
register
number to the accumulator number, by dividing it by 4.  If both MMA and 
dense
math are selected, then %A will map the separate DMR registers into 0..7.

The intention is that user code using extended asm can be modified to run on
both MMA without dense math and MMA with dense math:

1)  If possible, don't use extended asm, but instead use the MMA 
built-in
functions;

2)  If you do need to write extended asm, change the d constraints
targetting accumulators should now use wD;

3)  Only use the built-in zero, assemble and disassemble functions 
create
move data between vector quad types and dense math accumulators.
I.e. do not use the xxmfacc, xxmtacc, and xxsetaccz directly in the
extended asm code.  The reason is these instructions assume there 
is a
1-to-1 correspondence between 4 adjacent FPR registers and an
accumulator that overlaps with those instructions.  With 
accumulators
now being separate registers, there no longer is a 1-to-1
correspondence.

It is possible that the mangling for DMRs and the GDB register numbers may
produce other changes in the future.

gcc/

2025-03-24   Michael Meissner  

* config/rs6000/mma.md (UNSPEC_MMA_DMSETDMRZ): New unspec.
(movxo): Add comments about dense math registers.
(movxo_nodm): Rename from movxo and restrict the usage to machines
without dense math registers.
(movxo_dm): New insn for movxo support for machines with dense math
registers.
(mma_): Restrict usage to machines without dense math 
registers.
(mma_xxsetaccz): Add a define_expand wrapper, and add support for 
dense
math registers.
(mma_dmsetaccz): New insn.
* config/rs6000/predicates.md (dmr_operand): New predicate.
(accumulator_operand): Add support for dense math registers.
* config/rs6000/rs6000-builtin.cc (rs6000_gimple_fold_mma_builtin): 
Do
not issue a de-prime instruction when disassembling a vector quad 
on a
system with dense math registers.
* config/rs6000/rs6000-c.cc (rs6000_define_or_undefine_macro): 
Define
__DENSE_MATH__ if we have dense math registers.
* config/rs6000/rs6000.cc (enum rs6000_reg_type): Add DMR_REG_TYPE.
(enum rs6000_reload_reg_type): Add RELOAD_REG_DMR.
(LAST_RELOAD_REG_CLASS): Add support for DMR registers and the wD
constraint.
(reload_reg_map): Likewise.
(rs6000_reg_names): Likewise.
(alt_reg_names): Likewise.
(rs6000_hard_regno_nregs_internal): Likewise.
(rs6000_hard_regno_mode_ok_uncached): Likewise.
(rs6000_debug_reg_global): Likewise.
(rs6000_setup_reg_addr_masks): Likewise.
(rs6000_init_hard_regno_mode_ok): Likewise.
(rs6000_secondary_reload_memory): Add support for DMR registers.
(rs6000_secondary_reload_simple_move): Likewise.
(rs6000_preferred_reload_class): Likewise.
(rs6000_secondary_reload_class): Likewise.
(print_operan

[gcc r15-8802] gccrs: Add name resolution and HIR lowering for ImplTraitType's

[Arthur Cohen via Gcc-cvs]

https://gcc.gnu.org/g:271a348960418b579787858072880f35da47c59c

commit r15-8802-g271a348960418b579787858072880f35da47c59c
Author: Philip Herron 
Date:   Sat Feb 15 21:22:16 2025 +

gccrs: Add name resolution and HIR lowering for ImplTraitType's

Our AST has ImplTraitType for multiple bounds and a singular
ImplTraitTypeOneBound, this patch desugars these into a simple
HIR::ImplTraitType. It also does the name resolution for this.

gcc/rust/ChangeLog:

* checks/errors/borrowck/rust-bir-builder-struct.h: remove 
HIR::ImplTraitTypeOneBound
* checks/errors/borrowck/rust-function-collector.h: likewise
* checks/errors/rust-const-checker.cc (ConstChecker::visit): 
likewise
* checks/errors/rust-const-checker.h: likewise
* checks/errors/rust-hir-pattern-analysis.cc 
(PatternChecker::visit): likewise
* checks/errors/rust-hir-pattern-analysis.h: likewise
* checks/errors/rust-unsafe-checker.cc (UnsafeChecker::visit): 
likewise
* checks/errors/rust-unsafe-checker.h: likewise
* hir/rust-ast-lower-type.cc (ASTLoweringType::translate): likewise
(ASTLoweringType::visit): likewise
* hir/rust-ast-lower-type.h: cleanup
* hir/rust-hir-dump.cc (Dump::visit): remove ImplTraitTypeOneBound
* hir/rust-hir-dump.h: likewise
* hir/tree/rust-hir-full-decls.h (class ImplTraitTypeOneBound): 
likewise
* hir/tree/rust-hir-type.h (class ImplTraitTypeOneBound): likewise
* hir/tree/rust-hir-visitor.h: likewise
* hir/tree/rust-hir.cc (ImplTraitTypeOneBound::as_string):  likewise
(ImplTraitTypeOneBound::accept_vis):  likewise
* resolve/rust-ast-resolve-type.cc (ResolveType::go): likewise
(ResolveType::visit): likewise
* resolve/rust-ast-resolve-type.h: add name resolution
* typecheck/rust-hir-type-check-type.h: likewise

Signed-off-by: Philip Herron 

Diff:
---
 .../errors/borrowck/rust-bir-builder-struct.h  |  4 --
 .../errors/borrowck/rust-function-collector.h  |  1 -
 gcc/rust/checks/errors/rust-const-checker.cc   |  4 --
 gcc/rust/checks/errors/rust-const-checker.h|  1 -
 .../checks/errors/rust-hir-pattern-analysis.cc |  4 --
 gcc/rust/checks/errors/rust-hir-pattern-analysis.h |  1 -
 gcc/rust/checks/errors/rust-unsafe-checker.cc  |  4 --
 gcc/rust/checks/errors/rust-unsafe-checker.h   |  1 -
 gcc/rust/hir/rust-ast-lower-type.cc| 36 ++
 gcc/rust/hir/rust-ast-lower-type.h |  3 ++
 gcc/rust/hir/rust-hir-dump.cc  |  9 
 gcc/rust/hir/rust-hir-dump.h   |  1 -
 gcc/rust/hir/tree/rust-hir-full-decls.h|  1 -
 gcc/rust/hir/tree/rust-hir-type.h  | 32 
 gcc/rust/hir/tree/rust-hir-visitor.h   |  3 --
 gcc/rust/hir/tree/rust-hir.cc  | 20 
 gcc/rust/resolve/rust-ast-resolve-type.cc  | 58 +-
 gcc/rust/resolve/rust-ast-resolve-type.h   | 52 +++
 gcc/rust/typecheck/rust-hir-type-check-type.h  |  3 --
 19 files changed, 103 insertions(+), 135 deletions(-)

diff --git a/gcc/rust/checks/errors/borrowck/rust-bir-builder-struct.h 
b/gcc/rust/checks/errors/borrowck/rust-bir-builder-struct.h
index 18ddc19db1dd..94fcecd40edb 100644
--- a/gcc/rust/checks/errors/borrowck/rust-bir-builder-struct.h
+++ b/gcc/rust/checks/errors/borrowck/rust-bir-builder-struct.h
@@ -250,10 +250,6 @@ protected:
   void visit (HIR::ImplTraitType &type) override { rust_unreachable (); }
   void visit (HIR::TraitObjectType &type) override { rust_unreachable (); }
   void visit (HIR::ParenthesisedType &type) override { rust_unreachable (); }
-  void visit (HIR::ImplTraitTypeOneBound &type) override
-  {
-rust_unreachable ();
-  }
   void visit (HIR::TupleType &type) override { rust_unreachable (); }
   void visit (HIR::NeverType &type) override { rust_unreachable (); }
   void visit (HIR::RawPointerType &type) override { rust_unreachable (); }
diff --git a/gcc/rust/checks/errors/borrowck/rust-function-collector.h 
b/gcc/rust/checks/errors/borrowck/rust-function-collector.h
index 5de503d441cc..cdb20e8504a4 100644
--- a/gcc/rust/checks/errors/borrowck/rust-function-collector.h
+++ b/gcc/rust/checks/errors/borrowck/rust-function-collector.h
@@ -180,7 +180,6 @@ public:
   void visit (HIR::ImplTraitType &type) override {}
   void visit (HIR::TraitObjectType &type) override {}
   void visit (HIR::ParenthesisedType &type) override {}
-  void visit (HIR::ImplTraitTypeOneBound &type) override {}
   void visit (HIR::TupleType &type) override {}
   void visit (HIR::NeverType &type) override {}
   void visit (HIR::RawPointerType &type) override {}
diff --git a/gcc/rust/checks/errors/rust-const-checker.cc 
b/gcc/rust/checks/errors/rust-const-checke

[gcc r15-8866] Remove buffer overflow in cobol driver

[Andreas Schwab via Gcc-cvs]

https://gcc.gnu.org/g:c6e7d9ca72cb424b7af9357d77209eb7dd14621a

commit r15-8866-gc6e7d9ca72cb424b7af9357d77209eb7dd14621a
Author: Andreas Schwab 
Date:   Mon Mar 24 11:39:29 2025 +0100

Remove buffer overflow in cobol driver

PR cobol/119390
* gcobolspec.cc (lang_specific_driver): Use pointer instead of
copying into fixed array.

Diff:
---
 gcc/cobol/gcobolspec.cc | 12 
 1 file changed, 4 insertions(+), 8 deletions(-)

diff --git a/gcc/cobol/gcobolspec.cc b/gcc/cobol/gcobolspec.cc
index 364c14c8a700..c84f4058c59d 100644
--- a/gcc/cobol/gcobolspec.cc
+++ b/gcc/cobol/gcobolspec.cc
@@ -498,15 +498,11 @@ lang_specific_driver (struct cl_decoded_option 
**in_decoded_options,
 
   if( prior_main )
 {
-char ach[128];
-if( entry_point )
-  {
-  strcpy(ach, entry_point);
-  }
+const char *ach;
+if (entry_point)
+ ach = entry_point;
 else
-  {
-  strcpy(ach, decoded_options[i].arg);
-  }
+ ach = decoded_options[i].arg;
 append_option(OPT_main_, ach, 1);
 prior_main = false;
 entry_point = NULL;

[gcc r15-8867] libgomp/plugin/plugin-nvptx.c: Fix device used for stream creation

[Tobias Burnus via Gcc-cvs]

https://gcc.gnu.org/g:1c5a375c21a262eb636449f88e671a09e140404e

commit r15-8867-g1c5a375c21a262eb636449f88e671a09e140404e
Author: Tobias Burnus 
Date:   Mon Mar 24 16:08:20 2025 +0100

libgomp/plugin/plugin-nvptx.c: Fix device used for stream creation

libgomp/ChangeLog:

* plugin/plugin-nvptx.c (GOMP_OFFLOAD_interop): Set context for
stream creation to use the specified device.

Diff:
---
 libgomp/plugin/plugin-nvptx.c | 18 --
 1 file changed, 16 insertions(+), 2 deletions(-)

diff --git a/libgomp/plugin/plugin-nvptx.c b/libgomp/plugin/plugin-nvptx.c
index 822c6a410e28..a5cf859db197 100644
--- a/libgomp/plugin/plugin-nvptx.c
+++ b/libgomp/plugin/plugin-nvptx.c
@@ -2483,12 +2483,26 @@ GOMP_OFFLOAD_interop (struct interop_obj_t *obj, int 
ord,
  break;
   }
 
-  obj->device_data = ptx_devices[ord];
+  struct ptx_device *ptx_dev = obj->device_data = ptx_devices[ord];
 
   if (targetsync)
 {
   CUstream stream = NULL;
-  CUDA_CALL_ASSERT (cuStreamCreate, &stream, CU_STREAM_DEFAULT);
+  CUdevice cur_ctx_dev;
+  CUresult res = CUDA_CALL_NOCHECK (cuCtxGetDevice, &cur_ctx_dev);
+  if (res != CUDA_SUCCESS && res != CUDA_ERROR_INVALID_CONTEXT)
+   GOMP_PLUGIN_fatal ("cuCtxGetDevice error: %s", cuda_error (res));
+  if (res != CUDA_ERROR_INVALID_CONTEXT && ptx_dev->dev == cur_ctx_dev)
+   CUDA_CALL_ASSERT (cuStreamCreate, &stream, CU_STREAM_DEFAULT);
+  else
+   {
+ CUcontext old_ctx;
+ assert (ptx_dev->ctx);
+ CUDA_CALL_ASSERT (cuCtxPushCurrent, ptx_dev->ctx);
+ CUDA_CALL_ASSERT (cuStreamCreate, &stream, CU_STREAM_DEFAULT);
+ if (res != CUDA_ERROR_INVALID_CONTEXT)
+   CUDA_CALL_ASSERT (cuCtxPopCurrent, &old_ctx);
+   }
   obj->stream = stream;
 }
 }

[gcc r15-8814] gccrs: expand: Allow built-in derives to generate multiple items

[Arthur Cohen via Gcc-cvs]

https://gcc.gnu.org/g:e79f430bf0e89f5e6dd71e3e2576c9cc0c18c385

commit r15-8814-ge79f430bf0e89f5e6dd71e3e2576c9cc0c18c385
Author: Arthur Cohen 
Date:   Tue Feb 4 09:58:14 2025 +0100

gccrs: expand: Allow built-in derives to generate multiple items

gcc/rust/ChangeLog:

* expand/rust-derive.cc (DeriveVisitor::derive): Return a vector of 
items.
* expand/rust-derive.h: Change return type.
* expand/rust-expand-visitor.cc: Insert all generated items into 
the AST.

Diff:
---
 gcc/rust/expand/rust-derive.cc | 16 
 gcc/rust/expand/rust-derive.h  |  8 ++--
 gcc/rust/expand/rust-expand-visitor.cc | 13 -
 3 files changed, 22 insertions(+), 15 deletions(-)

diff --git a/gcc/rust/expand/rust-derive.cc b/gcc/rust/expand/rust-derive.cc
index 1f89502f6395..cd162247ec45 100644
--- a/gcc/rust/expand/rust-derive.cc
+++ b/gcc/rust/expand/rust-derive.cc
@@ -31,34 +31,34 @@ DeriveVisitor::DeriveVisitor (location_t loc)
   : loc (loc), builder (Builder (loc))
 {}
 
-std::unique_ptr
+std::vector>
 DeriveVisitor::derive (Item &item, const Attribute &attr,
   BuiltinMacro to_derive)
 {
   switch (to_derive)
 {
 case BuiltinMacro::Clone:
-  return DeriveClone (attr.get_locus ()).go (item);
+  return vec (DeriveClone (attr.get_locus ()).go (item));
 case BuiltinMacro::Copy:
-  return DeriveCopy (attr.get_locus ()).go (item);
+  return vec (DeriveCopy (attr.get_locus ()).go (item));
 case BuiltinMacro::Debug:
   rust_warning_at (
attr.get_locus (), 0,
"derive(Debug) is not fully implemented yet and has no effect - only a "
"stub implementation will be generated");
-  return DeriveDebug (attr.get_locus ()).go (item);
+  return vec (DeriveDebug (attr.get_locus ()).go (item));
 case BuiltinMacro::Default:
-  return DeriveDefault (attr.get_locus ()).go (item);
+  return vec (DeriveDefault (attr.get_locus ()).go (item));
 case BuiltinMacro::Eq:
-  return DeriveEq (attr.get_locus ()).go (item);
+  return vec (DeriveEq (attr.get_locus ()).go (item));
 case BuiltinMacro::PartialEq:
-  return DerivePartialEq (attr.get_locus ()).go (item);
+  return vec (DerivePartialEq (attr.get_locus ()).go (item));
 case BuiltinMacro::Ord:
 case BuiltinMacro::PartialOrd:
 case BuiltinMacro::Hash:
 default:
   rust_sorry_at (attr.get_locus (), "unimplemented builtin derive macro");
-  return nullptr;
+  return {};
 };
 }
 
diff --git a/gcc/rust/expand/rust-derive.h b/gcc/rust/expand/rust-derive.h
index a494cc3c3124..d8cc0a480aba 100644
--- a/gcc/rust/expand/rust-derive.h
+++ b/gcc/rust/expand/rust-derive.h
@@ -34,8 +34,12 @@ namespace AST {
 class DeriveVisitor : public AST::ASTVisitor
 {
 public:
-  static std::unique_ptr derive (Item &item, const Attribute &derive,
-  BuiltinMacro to_derive);
+  /**
+   * Expand a built-in derive macro on an item. This may generate multiple 
items
+   * which all need to be integrated to the existing AST
+   */
+  static std::vector>
+  derive (Item &item, const Attribute &derive, BuiltinMacro to_derive);
 
 protected:
   DeriveVisitor (location_t loc);
diff --git a/gcc/rust/expand/rust-expand-visitor.cc 
b/gcc/rust/expand/rust-expand-visitor.cc
index 6e06fa516098..8ba9a15fddf4 100644
--- a/gcc/rust/expand/rust-expand-visitor.cc
+++ b/gcc/rust/expand/rust-expand-visitor.cc
@@ -43,7 +43,7 @@ ExpandVisitor::go (AST::Crate &crate)
   visit (crate);
 }
 
-static std::unique_ptr
+static std::vector>
 builtin_derive_item (AST::Item &item, const AST::Attribute &derive,
 BuiltinMacro to_derive)
 {
@@ -189,11 +189,12 @@ ExpandVisitor::expand_inner_items (
to_derive.get ().as_string ());
  if (maybe_builtin.has_value ())
{
- auto new_item
+ auto new_items
= builtin_derive_item (item, current,
   maybe_builtin.value ());
 
- it = items.insert (it, std::move (new_item));
+ for (auto &&new_item : new_items)
+   it = items.insert (it, std::move (new_item));
}
  else
{
@@ -276,12 +277,14 @@ ExpandVisitor::expand_inner_stmts (AST::BlockExpr &expr)
to_derive.get ().as_string ());
  if (maybe_builtin.has_value ())
{
- auto new_item
+ auto new_items
= builtin_derive_item (item, current,
   maybe_builtin.value ());
+
  // this inserts the derive *before* the item - is it a
 

[gcc r15-8840] gccrs: Keep definition provenance to skip enum variants

[Arthur Cohen via Gcc-cvs]

https://gcc.gnu.org/g:8b178586c7ec1be0391c98c1f2361e41e002c459

commit r15-8840-g8b178586c7ec1be0391c98c1f2361e41e002c459
Author: Pierre-Emmanuel Patry 
Date:   Tue Mar 4 16:41:48 2025 +0100

gccrs: Keep definition provenance to skip enum variants

Enum variants shouldn't be accessed directly even from within an enum.
This commit keeps the provenance for enum variants definition so we
can skip them when resolving a value within an enum definition.

gcc/rust/ChangeLog:

* resolve/rust-forever-stack.h: Add new function to insert enum
variants and add argument to resolver's get function to explicitely
skip enum variants.
* resolve/rust-forever-stack.hxx: Update function
definitions.
* resolve/rust-name-resolution-context.cc 
(NameResolutionContext::insert_variant):
Add function to insert enum variants.
* resolve/rust-name-resolution-context.h: Add function's prototype.
* resolve/rust-rib.cc (Rib::Definition::Definition): Add new 
boolean to
hint at enum variant provenance.
(Rib::Definition::is_variant): New getter for variant status.
(Rib::Definition::Shadowable): Update constructor to opt out of enum
variants.
(Rib::Definition::Globbed): Likewise.
(Rib::Definition::NonShadowable): Change constructor to forward enum
variant provenance status.
* resolve/rust-rib.h: Update function prototypes.
* resolve/rust-toplevel-name-resolver-2.0.cc 
(TopLevel::insert_enum_variant_or_error_out):
Add function to insert enum variants in the name resolver.
(TopLevel::visit): Update several enum variant's visitor function
with the new enum variant name resolving code.
* resolve/rust-toplevel-name-resolver-2.0.h: Update function
prototypes.

Signed-off-by: Pierre-Emmanuel Patry 

Diff:
---
 gcc/rust/resolve/rust-forever-stack.h  |  3 ++
 gcc/rust/resolve/rust-forever-stack.hxx| 18 ++--
 gcc/rust/resolve/rust-name-resolution-context.cc   |  6 +++
 gcc/rust/resolve/rust-name-resolution-context.h|  3 ++
 gcc/rust/resolve/rust-rib.cc   | 17 +--
 gcc/rust/resolve/rust-rib.h| 14 +-
 .../resolve/rust-toplevel-name-resolver-2.0.cc | 54 --
 gcc/rust/resolve/rust-toplevel-name-resolver-2.0.h | 17 ++-
 8 files changed, 106 insertions(+), 26 deletions(-)

diff --git a/gcc/rust/resolve/rust-forever-stack.h 
b/gcc/rust/resolve/rust-forever-stack.h
index 64e8a0f0f2c9..22efc9731977 100644
--- a/gcc/rust/resolve/rust-forever-stack.h
+++ b/gcc/rust/resolve/rust-forever-stack.h
@@ -591,6 +591,9 @@ public:
*/
   tl::expected insert (Identifier name, NodeId id);
 
+  tl::expected insert_variant (Identifier name,
+  NodeId id);
+
   /**
* Insert a new shadowable definition in the innermost `Rib` in this stack
*
diff --git a/gcc/rust/resolve/rust-forever-stack.hxx 
b/gcc/rust/resolve/rust-forever-stack.hxx
index 9e66c802d5f2..628b8c5b6fe8 100644
--- a/gcc/rust/resolve/rust-forever-stack.hxx
+++ b/gcc/rust/resolve/rust-forever-stack.hxx
@@ -173,6 +173,14 @@ ForeverStack::insert (Identifier name, 
NodeId node)
   Rib::Definition::Shadowable (node));
 }
 
+template <>
+inline tl::expected
+ForeverStack::insert_variant (Identifier name, NodeId node)
+{
+  return insert_inner (peek (), name.as_string (),
+  Rib::Definition::NonShadowable (node, true));
+}
+
 template 
 Rib &
 ForeverStack::peek ()
@@ -275,10 +283,12 @@ ForeverStack::get (const Identifier &name)
 
 return candidate.map_or (
   [&resolved_definition] (Rib::Definition found) {
-   // for most namespaces, we do not need to care about various ribs - they
-   // are available from all contexts if defined in the current scope, or
-   // an outermore one. so if we do have a candidate, we can return it
-   // directly and stop iterating
+   if (found.is_variant ())
+ return KeepGoing::Yes;
+   // for most namespaces, we do not need to care about various ribs -
+   // they are available from all contexts if defined in the current
+   // scope, or an outermore one. so if we do have a candidate, we can
+   // return it directly and stop iterating
resolved_definition = found;
 
return KeepGoing::No;
diff --git a/gcc/rust/resolve/rust-name-resolution-context.cc 
b/gcc/rust/resolve/rust-name-resolution-context.cc
index 1b3752138785..517a4836aafd 100644
--- a/gcc/rust/resolve/rust-name-resolution-context.cc
+++ b/gcc/rust/resolve/rust-name-resolution-context.cc
@@ -45,6 +45,12 @@ NameResolutionContext::insert (Identifier name, NodeId id, 
Namespace ns)
 }
 }
 
+tl::expected
+NameResolutionContext::insert_var

[gcc r15-8755] gccrs: Make foreverstack debug string const

[Arthur Cohen via Gcc-cvs]

https://gcc.gnu.org/g:48d524e2ee0142199a5eed50c7aa247cef849e5c

commit r15-8755-g48d524e2ee0142199a5eed50c7aa247cef849e5c
Author: Pierre-Emmanuel Patry 
Date:   Mon Jan 6 15:53:31 2025 +0100

gccrs: Make foreverstack debug string const

Those function should not change anything within the foreverstack, it
can therefore be made const.

gcc/rust/ChangeLog:

* resolve/rust-forever-stack.h: Make debug functions const.
* resolve/rust-forever-stack.hxx: Likewise.

Signed-off-by: Pierre-Emmanuel Patry 

Diff:
---
 gcc/rust/resolve/rust-forever-stack.h   | 6 +++---
 gcc/rust/resolve/rust-forever-stack.hxx | 6 +++---
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/gcc/rust/resolve/rust-forever-stack.h 
b/gcc/rust/resolve/rust-forever-stack.h
index 66e12668f71a..661478bab9b9 100644
--- a/gcc/rust/resolve/rust-forever-stack.h
+++ b/gcc/rust/resolve/rust-forever-stack.h
@@ -670,7 +670,7 @@ public:
   tl::optional to_rib (NodeId rib_id);
   tl::optional to_rib (NodeId rib_id) const;
 
-  std::string as_debug_string ();
+  std::string as_debug_string () const;
 
   /**
* Used to check if a module is a descendant of another module
@@ -752,9 +752,9 @@ private:
   std::reference_wrapper cursor_reference;
 
   void stream_rib (std::stringstream &stream, const Rib &rib,
-  const std::string &next, const std::string &next_next);
+  const std::string &next, const std::string &next_next) const;
   void stream_node (std::stringstream &stream, unsigned indentation,
-   const Node &node);
+   const Node &node) const;
 
   /* Helper types and functions for `resolve_path` */
 
diff --git a/gcc/rust/resolve/rust-forever-stack.hxx 
b/gcc/rust/resolve/rust-forever-stack.hxx
index d3d78894671a..1c83f6bda613 100644
--- a/gcc/rust/resolve/rust-forever-stack.hxx
+++ b/gcc/rust/resolve/rust-forever-stack.hxx
@@ -699,7 +699,7 @@ template 
 void
 ForeverStack::stream_rib (std::stringstream &stream, const Rib &rib,
 const std::string &next,
-const std::string &next_next)
+const std::string &next_next) const
 {
   if (rib.get_values ().empty ())
 {
@@ -718,7 +718,7 @@ ForeverStack::stream_rib (std::stringstream &stream, 
const Rib &rib,
 template 
 void
 ForeverStack::stream_node (std::stringstream &stream, unsigned indentation,
- const ForeverStack::Node &node)
+ const ForeverStack::Node &node) const
 {
   auto indent = std::string (indentation, ' ');
   auto next = std::string (indentation + 4, ' ');
@@ -750,7 +750,7 @@ ForeverStack::stream_node (std::stringstream &stream, 
unsigned indentation,
 
 template 
 std::string
-ForeverStack::as_debug_string ()
+ForeverStack::as_debug_string () const
 {
   std::stringstream stream;

[gcc r15-8687] c++/modules: Fix explicit instantiations and gnu_inlines [PR119154]

[Nathaniel Shead via Gcc-cvs]

https://gcc.gnu.org/g:9fcb9d39c36ae0c1b1681c68d314580ae0c820c4

commit r15-8687-g9fcb9d39c36ae0c1b1681c68d314580ae0c820c4
Author: Nathaniel Shead 
Date:   Sat Mar 22 23:04:12 2025 +1100

c++/modules: Fix explicit instantiations and gnu_inlines [PR119154]

My change in r15-8012 for PR c++/119154 exposed a bug with explicit
instantation declarations.  The change cleared DECL_INTERFACE_KNOWN for
all vague-linkage entities, including explicit instantiations.  When we
then perform lazy loading at EOF (due to processing deferred function
bodies), expand_or_defer_fn ends up calling import_export_decl which
will error because DECL_INTERFACE_KNOWN is still unset but no definition
is available in the file, violating some assertions.

It turns out that for function templates marked inline we would not
respect an 'extern template' imported in general, either; this patch
fixes both of these issues by always treating explicit instantiations as
external, and so marking DECL_INTERFACE_KNOWN eagerly.

For an explicit instantiation declaration we don't want to emit the body
of the function as it must be emitted in a different TU anyway.  And for
explicit instantiation definitions we similarly know that it will have
been emitted in the interface TU we streamed it in from, so there's
no need to emit it.

The same error can happen with lazy-loaded gnu_inlines at EOF; in some
cases they'll be marked DECL_COMDAT and pass through the vague_linkage_p
check anyway.  This patch reworks the handling of gnu_inlines to ensure
that both DECL_INTERFACE_KNOWN is always correctly set and that
importing a gnu_inline function over the top of an existing forward
declaration works correctly.

The other case that duplicate_decls handles (importing a regular
definition over the top of a gnu_inline function) doesn't seem like
something we need to handle specially in modules; we'll just use the
existing gnu_inline function and rely on the guarantee that there is a
single non-inline function definition provided elsewhere.

PR c++/119154

gcc/cp/ChangeLog:

* decl2.cc (vague_linkage_p): Revert gnu_linkage handling.
* module.cc (importer_interface): New enumeration.
(get_importer_interface): New function.
(trees_out::core_bools): Use it to determine interface.
(trees_in::is_matching_decl): Propagate gnu_inline handling onto
existing forward declarations.
(trees_in::read_var_def): Also note explicit instantiation
definitions of variable templates to be emitted.

gcc/testsuite/ChangeLog:

* g++.dg/modules/pr119154_a.C: Move to...
* g++.dg/modules/gnu-inline-1_a.C: ...here, and add decl.
* g++.dg/modules/pr119154_b.C: Move to...
* g++.dg/modules/gnu-inline-1_b.C: here, and add check.
* g++.dg/modules/gnu-inline-1_c.C: New test.
* g++.dg/modules/gnu-inline-1_d.C: New test.
* g++.dg/modules/gnu-inline-2_a.C: New test.
* g++.dg/modules/gnu-inline-2_b.C: New test.
* g++.dg/modules/extern-tpl-3_a.C: New test.
* g++.dg/modules/extern-tpl-3_b.C: New test.
* g++.dg/modules/extern-tpl-4_a.H: New test.
* g++.dg/modules/extern-tpl-4_b.C: New test.
* g++.dg/modules/extern-tpl-4_c.C: New test.

Signed-off-by: Nathaniel Shead 
Reviewed-by: Jason Merrill 

Diff:
---
 gcc/cp/decl2.cc   |  4 +-
 gcc/cp/module.cc  | 69 +--
 gcc/testsuite/g++.dg/modules/extern-tpl-3_a.C | 11 
 gcc/testsuite/g++.dg/modules/extern-tpl-3_b.C | 12 
 gcc/testsuite/g++.dg/modules/extern-tpl-4_a.H | 22 
 gcc/testsuite/g++.dg/modules/extern-tpl-4_b.C | 24 
 gcc/testsuite/g++.dg/modules/extern-tpl-4_c.C | 80 +++
 gcc/testsuite/g++.dg/modules/gnu-inline-1_a.C |  7 +++
 gcc/testsuite/g++.dg/modules/gnu-inline-1_b.C | 14 +
 gcc/testsuite/g++.dg/modules/gnu-inline-1_c.C | 16 ++
 gcc/testsuite/g++.dg/modules/gnu-inline-1_d.C | 16 ++
 gcc/testsuite/g++.dg/modules/gnu-inline-2_a.C | 11 
 gcc/testsuite/g++.dg/modules/gnu-inline-2_b.C | 14 +
 gcc/testsuite/g++.dg/modules/pr119154_a.C |  6 --
 gcc/testsuite/g++.dg/modules/pr119154_b.C | 10 
 15 files changed, 293 insertions(+), 23 deletions(-)

diff --git a/gcc/cp/decl2.cc b/gcc/cp/decl2.cc
index 4987987daed7..21156f1dd3b7 100644
--- a/gcc/cp/decl2.cc
+++ b/gcc/cp/decl2.cc
@@ -2482,9 +2482,7 @@ vague_linkage_p (tree decl)
  DECL_COMDAT.  */
   if (DECL_COMDAT (decl)
   || (TREE_CODE (decl) == FUNCTION_DECL
- && DECL_DECLARED_INLINE_P (decl)
- /* But gnu_inline functions are always external.  */
- && !lookup_attribute ("gnu_inline", DECL_ATTRIBUT

[gcc r15-8555] gccrs: constant evaluation like these are coercion sites

[Arthur Cohen via Gcc-cvs]

https://gcc.gnu.org/g:9a53a1d1abe2e97207a7bf9ed4db735c4bafb771

commit r15-8555-g9a53a1d1abe2e97207a7bf9ed4db735c4bafb771
Author: Philip Herron 
Date:   Mon Dec 2 16:17:54 2024 +

gccrs: constant evaluation like these are coercion sites

The code here was wrongly assuming the decl type from the folding of the
expression would be the type of the constant decl. This is not the case for
unsized coercions for slices, where the expression here is a reference to
an array then we require the coercion to fix the result up to the expected
type.

Fixes Rust-GCC#1525

gcc/rust/ChangeLog:

* backend/rust-compile-base.cc: apply coercion site to result
* backend/rust-compile-base.h: update prototype
* backend/rust-compile-implitem.cc (CompileTraitItem::visit): send 
in coercion info
* backend/rust-compile-item.cc (CompileItem::visit): likewise

gcc/testsuite/ChangeLog:

* rust/compile/issue-1525.rs: New test.

Signed-off-by: Philip Herron 

Diff:
---
 gcc/rust/backend/rust-compile-base.cc | 15 ---
 gcc/rust/backend/rust-compile-base.h  |  6 --
 gcc/rust/backend/rust-compile-implitem.cc | 11 +--
 gcc/rust/backend/rust-compile-item.cc | 29 +
 gcc/testsuite/rust/compile/issue-1525.rs  |  4 
 5 files changed, 50 insertions(+), 15 deletions(-)

diff --git a/gcc/rust/backend/rust-compile-base.cc 
b/gcc/rust/backend/rust-compile-base.cc
index fb4aace95559..bcc7fc4fcbf4 100644
--- a/gcc/rust/backend/rust-compile-base.cc
+++ b/gcc/rust/backend/rust-compile-base.cc
@@ -777,13 +777,18 @@ HIRCompileBase::compile_function (
 
 tree
 HIRCompileBase::compile_constant_item (
-  TyTy::BaseType *resolved_type, const Resolver::CanonicalPath &canonical_path,
-  HIR::Expr &const_value_expr, location_t locus)
+  HirId coercion_id, TyTy::BaseType *resolved_type,
+  TyTy::BaseType *expected_type, const Resolver::CanonicalPath &canonical_path,
+  HIR::Expr &const_value_expr, location_t locus, location_t expr_locus)
 {
   const std::string &ident = canonical_path.get ();
 
   tree type = TyTyResolveCompile::compile (ctx, resolved_type);
   tree const_type = build_qualified_type (type, TYPE_QUAL_CONST);
+
+  tree actual_type = TyTyResolveCompile::compile (ctx, expected_type);
+  tree actual_const_type = build_qualified_type (actual_type, TYPE_QUAL_CONST);
+
   bool is_block_expr
 = const_value_expr.get_expression_type () == HIR::Expr::ExprType::Block;
 
@@ -851,7 +856,11 @@ HIRCompileBase::compile_constant_item (
   tree call = build_call_array_loc (locus, const_type, fndecl, 0, NULL);
   tree folded_expr = fold_expr (call);
 
-  return named_constant_expression (const_type, ident, folded_expr, locus);
+  // coercion site
+  tree coerced = coercion_site (coercion_id, folded_expr, resolved_type,
+   expected_type, locus, expr_locus);
+
+  return named_constant_expression (actual_const_type, ident, coerced, locus);
 }
 
 tree
diff --git a/gcc/rust/backend/rust-compile-base.h 
b/gcc/rust/backend/rust-compile-base.h
index 5fb1d83f2eeb..9328a7f74830 100644
--- a/gcc/rust/backend/rust-compile-base.h
+++ b/gcc/rust/backend/rust-compile-base.h
@@ -90,9 +90,11 @@ protected:
   void compile_function_body (tree fndecl, HIR::BlockExpr &function_body,
  TyTy::BaseType *fn_return_ty);
 
-  tree compile_constant_item (TyTy::BaseType *resolved_type,
+  tree compile_constant_item (HirId coercion_id, TyTy::BaseType *resolved_type,
+ TyTy::BaseType *expected_type,
  const Resolver::CanonicalPath &canonical_path,
- HIR::Expr &const_value_expr, location_t locus);
+ HIR::Expr &const_value_expr, location_t locus,
+ location_t expr_locus);
 
   tree compile_function (const std::string &fn_name, HIR::SelfParam 
&self_param,
 std::vector &function_params,
diff --git a/gcc/rust/backend/rust-compile-implitem.cc 
b/gcc/rust/backend/rust-compile-implitem.cc
index 129e97879fa4..71b3e8d3002d 100644
--- a/gcc/rust/backend/rust-compile-implitem.cc
+++ b/gcc/rust/backend/rust-compile-implitem.cc
@@ -45,9 +45,16 @@ CompileTraitItem::visit (HIR::TraitItemConst &constant)
   rust_assert (canonical_path);
 
   HIR::Expr &const_value_expr = constant.get_expr ();
+  TyTy::BaseType *expr_type = nullptr;
+  bool ok = ctx->get_tyctx ()->lookup_type (
+const_value_expr.get_mappings ().get_hirid (), &expr_type);
+  rust_assert (ok);
+
   tree const_expr
-= compile_constant_item (resolved_type, *canonical_path, const_value_expr,
-constant.get_locus ());
+= compile_constant_item (constant.get_mappings ().get_hirid (), expr_type,
+resolved_type, *canonical_path, const_value_expr,
+con

[gcc r15-8789] gccrs: ast: Add DesugarForLoop class

[Arthur Cohen via Gcc-cvs]

https://gcc.gnu.org/g:01d7dd796f76e8dd093bdefc67060d6d407eb68e

commit r15-8789-g01d7dd796f76e8dd093bdefc67060d6d407eb68e
Author: Arthur Cohen 
Date:   Sun Dec 22 15:59:27 2024 +

gccrs: ast: Add DesugarForLoop class

gcc/rust/ChangeLog:

* ast/rust-desugar-for-loops.cc: New file.
* ast/rust-desugar-for-loops.h: New file.
* hir/rust-ast-lower-expr.cc (ASTLoweringExpr::visit): Make 
lowering of for-loops an
unreachable.
* Make-lang.in: Compile it.

gcc/testsuite/ChangeLog:

* rust/compile/for-loop1.rs: New test.
* rust/compile/for-loop2.rs: New test.
* rust/execute/torture/for-loop1.rs: New test.
* rust/execute/torture/for-loop2.rs: New test.
* rust/compile/nr2/exclude: Exclude for-loop1.rs

Diff:
---
 gcc/rust/Make-lang.in   |   1 +
 gcc/rust/ast/rust-desugar-for-loops.cc  | 204 +
 gcc/rust/ast/rust-desugar-for-loops.h   | 108 +
 gcc/rust/hir/rust-ast-lower-expr.cc |   2 +-
 gcc/testsuite/rust/compile/for-loop1.rs | 543 +++
 gcc/testsuite/rust/compile/for-loop2.rs | 545 
 gcc/testsuite/rust/compile/nr2/exclude  |   2 +
 gcc/testsuite/rust/execute/torture/for-loop1.rs | 545 
 gcc/testsuite/rust/execute/torture/for-loop2.rs | 544 +++
 9 files changed, 2493 insertions(+), 1 deletion(-)

diff --git a/gcc/rust/Make-lang.in b/gcc/rust/Make-lang.in
index dc03a72ec78a..5ddad2578059 100644
--- a/gcc/rust/Make-lang.in
+++ b/gcc/rust/Make-lang.in
@@ -235,6 +235,7 @@ GRS_OBJS = \
rust/rust-expand-format-args.o \
rust/rust-lang-item.o \
rust/rust-collect-lang-items.o \
+   rust/rust-desugar-for-loops.o \
 $(END)
 # removed object files from here
 
diff --git a/gcc/rust/ast/rust-desugar-for-loops.cc 
b/gcc/rust/ast/rust-desugar-for-loops.cc
new file mode 100644
index ..5e5cbbc6b383
--- /dev/null
+++ b/gcc/rust/ast/rust-desugar-for-loops.cc
@@ -0,0 +1,204 @@
+// Copyright (C) 2025 Free Software Foundation, Inc.
+
+// This file is part of GCC.
+
+// GCC is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 3, or (at your option) any later
+// version.
+
+// GCC is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+
+// You should have received a copy of the GNU General Public License
+// along with GCC; see the file COPYING3.  If not see
+// .
+
+#include "rust-desugar-for-loops.h"
+#include "rust-ast-visitor.h"
+#include "rust-ast.h"
+#include "rust-hir-map.h"
+#include "rust-path.h"
+#include "rust-pattern.h"
+#include "rust-stmt.h"
+#include "rust-expr.h"
+#include "rust-ast-builder.h"
+
+namespace Rust {
+namespace AST {
+
+DesugarForLoops::DesugarForLoops () {}
+
+void
+DesugarForLoops::go (AST::Crate &crate)
+{
+  DefaultASTVisitor::visit (crate);
+}
+
+static void
+replace_for_loop (std::unique_ptr &for_loop,
+ std::unique_ptr &&expanded)
+{
+  for_loop = std::move (expanded);
+}
+
+MatchArm
+DesugarForLoops::DesugarCtx::make_match_arm (std::unique_ptr &&path)
+{
+  auto patterns = std::vector> ();
+  patterns.emplace_back (std::move (path));
+
+  return MatchArm (std::move (patterns), loc);
+}
+
+MatchCase
+DesugarForLoops::DesugarCtx::make_break_arm ()
+{
+  auto arm = make_match_arm (std::unique_ptr (new PathInExpression (
+builder.path_in_expression (LangItem::Kind::OPTION_NONE;
+
+  auto break_expr = std::unique_ptr (
+new BreakExpr (Lifetime::error (), nullptr, {}, loc));
+
+  return MatchCase (std::move (arm), std::move (break_expr));
+}
+
+MatchCase
+DesugarForLoops::DesugarCtx::make_continue_arm ()
+{
+  auto val = builder.identifier_pattern (DesugarCtx::continue_pattern_id);
+
+  auto patterns = std::vector> ();
+  patterns.emplace_back (std::move (val));
+
+  auto pattern_item = std::unique_ptr (
+new TupleStructItemsNoRange (std::move (patterns)));
+  auto pattern = std::unique_ptr (new TupleStructPattern (
+builder.path_in_expression (LangItem::Kind::OPTION_SOME),
+std::move (pattern_item)));
+
+  auto val_arm = make_match_arm (std::move (pattern));
+
+  auto next = builder.identifier (DesugarCtx::next_value_id);
+
+  auto assignment = std::unique_ptr (
+new AssignmentExpr (std::move (next),
+   builder.identifier (DesugarCtx::continue_pattern_id),
+   {}, loc));
+
+  return MatchCase (std::move (val_arm), std::move (assignment));
+}
+
+std::unique_ptr
+DesugarForLoops::DesugarCtx::statementify (std::unique_ptr &&expr)
+{
+  re

[gcc r15-8748] gccrs: backend: Improve handling of lang-item PathInExpressions

[Arthur Cohen via Gcc-cvs]

https://gcc.gnu.org/g:75325a325123e0797f60d541ea8f8b5aa970bd76

commit r15-8748-g75325a325123e0797f60d541ea8f8b5aa970bd76
Author: Arthur Cohen 
Date:   Fri Jan 24 10:42:54 2025 +0100

gccrs: backend: Improve handling of lang-item PathInExpressions

gcc/rust/ChangeLog:

* backend/rust-compile-resolve-path.cc (ResolvePathRef::visit): 
Call into
resolve_path_like instead.
(ResolvePathRef::resolve_path_like): New.
(ResolvePathRef::resolve): Call into resolve_with_node_id.
* backend/rust-compile-resolve-path.h: Declare new functions and 
document them.

Diff:
---
 gcc/rust/backend/rust-compile-resolve-path.cc | 116 +++---
 gcc/rust/backend/rust-compile-resolve-path.h  |  16 
 2 files changed, 84 insertions(+), 48 deletions(-)

diff --git a/gcc/rust/backend/rust-compile-resolve-path.cc 
b/gcc/rust/backend/rust-compile-resolve-path.cc
index eb897b7ee206..6ede1bea22f4 100644
--- a/gcc/rust/backend/rust-compile-resolve-path.cc
+++ b/gcc/rust/backend/rust-compile-resolve-path.cc
@@ -32,32 +32,37 @@
 namespace Rust {
 namespace Compile {
 
-void
-ResolvePathRef::visit (HIR::QualifiedPathInExpression &expr)
+template 
+tree
+ResolvePathRef::resolve_path_like (T &expr)
 {
-  auto final_segment = HIR::PathIdentSegment::create_error ();
   if (expr.is_lang_item ())
-final_segment
-  = HIR::PathIdentSegment (LangItem::ToString (expr.get_lang_item ()));
-  else
-final_segment = expr.get_final_segment ().get_segment ();
+{
+  auto lang_item
+   = Analysis::Mappings::get ().get_lang_item_node (expr.get_lang_item ());
+
+  // FIXME: Is that correct? :/
+  auto final_segment
+   = HIR::PathIdentSegment (LangItem::ToString (expr.get_lang_item ()));
 
-  resolved
-= resolve (final_segment, expr.get_mappings (), expr.get_locus (), true);
+  return resolve_with_node_id (final_segment, expr.get_mappings (),
+  expr.get_locus (), true, lang_item);
+}
+
+  return resolve (expr.get_final_segment ().get_segment (),
+ expr.get_mappings (), expr.get_locus (), true);
 }
 
 void
-ResolvePathRef::visit (HIR::PathInExpression &expr)
+ResolvePathRef::visit (HIR::QualifiedPathInExpression &expr)
 {
-  auto final_segment = HIR::PathIdentSegment::create_error ();
-  if (expr.is_lang_item ())
-final_segment
-  = HIR::PathIdentSegment (LangItem::ToString (expr.get_lang_item ()));
-  else
-final_segment = expr.get_final_segment ().get_segment ();
+  resolved = resolve_path_like (expr);
+}
 
-  resolved
-= resolve (final_segment, expr.get_mappings (), expr.get_locus (), true);
+void
+ResolvePathRef::visit (HIR::PathInExpression &expr)
+{
+  resolved = resolve_path_like (expr);
 }
 
 tree
@@ -106,42 +111,17 @@ ResolvePathRef::attempt_constructor_expression_lookup (
 }
 
 tree
-ResolvePathRef::resolve (const HIR::PathIdentSegment &final_segment,
-const Analysis::NodeMapping &mappings,
-location_t expr_locus, bool is_qualified_path)
+ResolvePathRef::resolve_with_node_id (
+  const HIR::PathIdentSegment &final_segment,
+  const Analysis::NodeMapping &mappings, location_t expr_locus,
+  bool is_qualified_path, NodeId resolved_node_id)
 {
   TyTy::BaseType *lookup = nullptr;
   bool ok = ctx->get_tyctx ()->lookup_type (mappings.get_hirid (), &lookup);
   rust_assert (ok);
 
-  // need to look up the reference for this identifier
-
-  // this can fail because it might be a Constructor for something
-  // in that case the caller should attempt ResolvePathType::Compile
-  NodeId ref_node_id = UNKNOWN_NODEID;
-  if (flag_name_resolution_2_0)
-{
-  auto nr_ctx
-   = Resolver2_0::ImmutableNameResolutionContext::get ().resolver ();
-
-  auto resolved = nr_ctx.lookup (mappings.get_nodeid ());
-
-  if (!resolved)
-   return attempt_constructor_expression_lookup (lookup, ctx, mappings,
- expr_locus);
-
-  ref_node_id = *resolved;
-}
-  else
-{
-  if (!ctx->get_resolver ()->lookup_resolved_name (mappings.get_nodeid (),
-  &ref_node_id))
-   return attempt_constructor_expression_lookup (lookup, ctx, mappings,
- expr_locus);
-}
-
   tl::optional hid
-= ctx->get_mappings ().lookup_node_to_hir (ref_node_id);
+= ctx->get_mappings ().lookup_node_to_hir (resolved_node_id);
   if (!hid.has_value ())
 {
   rust_error_at (expr_locus, "reverse call path lookup failure");
@@ -207,9 +187,49 @@ ResolvePathRef::resolve (const HIR::PathIdentSegment 
&final_segment,
 {
   TREE_USED (resolved_item) = 1;
 }
+
   return resolved_item;
 }
 
+tree
+ResolvePathRef::resolve (const HIR::PathIdentSegment &final_segment,
+const Analysis::NodeMapping &mappings,
+l

[gcc r15-8766] gccrs: lang-items: Add structural_{peq, teq}

[Arthur Cohen via Gcc-cvs]

https://gcc.gnu.org/g:62a8f1539c0483d84fd1b313acc0d12560f20b62

commit r15-8766-g62a8f1539c0483d84fd1b313acc0d12560f20b62
Author: Arthur Cohen 
Date:   Thu Jan 30 14:19:03 2025 +0100

gccrs: lang-items: Add structural_{peq, teq}

These lang items are used when deriving Eq and PartialEq, and will be 
checked when compiling pattern matching.

gcc/rust/ChangeLog:

* util/rust-lang-item.cc: New items.
* util/rust-lang-item.h: Likewise.

gcc/testsuite/ChangeLog:

* rust/compile/structural-eq-peq.rs: New test.

Diff:
---
 gcc/rust/util/rust-lang-item.cc | 3 +++
 gcc/rust/util/rust-lang-item.h  | 3 +++
 gcc/testsuite/rust/compile/structural-eq-peq.rs | 9 +
 3 files changed, 15 insertions(+)

diff --git a/gcc/rust/util/rust-lang-item.cc b/gcc/rust/util/rust-lang-item.cc
index 145054ff9d72..92a76613b61d 100644
--- a/gcc/rust/util/rust-lang-item.cc
+++ b/gcc/rust/util/rust-lang-item.cc
@@ -112,6 +112,9 @@ const BiMap 
Rust::LangItem::lang_items = {{
   {"from_ok", Kind::TRY_FROM_OK},
 
   {"from", Kind::FROM_FROM},
+
+  {"structural_peq", Kind::STRUCTURAL_PEQ},
+  {"structural_teq", Kind::STRUCTURAL_TEQ},
 }};
 
 tl::optional
diff --git a/gcc/rust/util/rust-lang-item.h b/gcc/rust/util/rust-lang-item.h
index f30b93609b5e..29b972702bd1 100644
--- a/gcc/rust/util/rust-lang-item.h
+++ b/gcc/rust/util/rust-lang-item.h
@@ -144,6 +144,9 @@ public:
 
 // NOTE: This is not a lang item in later versions of Rust
 FROM_FROM,
+
+STRUCTURAL_PEQ,
+STRUCTURAL_TEQ,
   };
 
   static const BiMap lang_items;
diff --git a/gcc/testsuite/rust/compile/structural-eq-peq.rs 
b/gcc/testsuite/rust/compile/structural-eq-peq.rs
new file mode 100644
index ..d04c295037f5
--- /dev/null
+++ b/gcc/testsuite/rust/compile/structural-eq-peq.rs
@@ -0,0 +1,9 @@
+#[lang = "structural_peq"]
+pub trait StructuralPartialEq {
+// Empty.
+}
+
+#[lang = "structural_teq"]
+pub trait StructuralEq {
+// Empty.
+}

[gcc r15-8760] gccrs: lang-items: Add From::from

[Arthur Cohen via Gcc-cvs]

https://gcc.gnu.org/g:d1e920221043f03a2d6e84def6c380ee03ac79ec

commit r15-8760-gd1e920221043f03a2d6e84def6c380ee03ac79ec
Author: Arthur Cohen 
Date:   Thu Jan 23 11:46:48 2025 +

gccrs: lang-items: Add From::from

gcc/rust/ChangeLog:

* util/rust-lang-item.h: Declare it.
* util/rust-lang-item.cc: Use it.

Diff:
---
 gcc/rust/util/rust-lang-item.cc | 2 ++
 gcc/rust/util/rust-lang-item.h  | 3 +++
 2 files changed, 5 insertions(+)

diff --git a/gcc/rust/util/rust-lang-item.cc b/gcc/rust/util/rust-lang-item.cc
index b37a237c24e6..145054ff9d72 100644
--- a/gcc/rust/util/rust-lang-item.cc
+++ b/gcc/rust/util/rust-lang-item.cc
@@ -110,6 +110,8 @@ const BiMap 
Rust::LangItem::lang_items = {{
   {"into_result", Kind::TRY_INTO_RESULT},
   {"from_error", Kind::TRY_FROM_ERROR},
   {"from_ok", Kind::TRY_FROM_OK},
+
+  {"from", Kind::FROM_FROM},
 }};
 
 tl::optional
diff --git a/gcc/rust/util/rust-lang-item.h b/gcc/rust/util/rust-lang-item.h
index 851909d409c0..f30b93609b5e 100644
--- a/gcc/rust/util/rust-lang-item.h
+++ b/gcc/rust/util/rust-lang-item.h
@@ -141,6 +141,9 @@ public:
 TRY_INTO_RESULT,
 TRY_FROM_ERROR,
 TRY_FROM_OK,
+
+// NOTE: This is not a lang item in later versions of Rust
+FROM_FROM,
   };
 
   static const BiMap lang_items;

[gcc r15-8784] gccrs: Add test case to show issue is fixed

[Arthur Cohen via Gcc-cvs]

https://gcc.gnu.org/g:419965b1cab8f1595dec4b821dd6fa739ed38b69

commit r15-8784-g419965b1cab8f1595dec4b821dd6fa739ed38b69
Author: Philip Herron 
Date:   Mon Feb 3 20:43:57 2025 +

gccrs: Add test case to show issue is fixed

This was fixed as part of: "gccrs: Fix compilation of trait-items which map 
to impl items"

Fixes Rust-GCC#3402

gcc/testsuite/ChangeLog:

* rust/compile/nr2/exclude: nr2 cant handle this
* rust/compile/issue-3402-1.rs: New test.
* rust/compile/issue-3402-2.rs: New test.

Signed-off-by: Philip Herron 

Diff:
---
 gcc/testsuite/rust/compile/issue-3402-1.rs | 29 +
 gcc/testsuite/rust/compile/issue-3402-2.rs | 18 ++
 gcc/testsuite/rust/compile/nr2/exclude |  1 +
 3 files changed, 48 insertions(+)

diff --git a/gcc/testsuite/rust/compile/issue-3402-1.rs 
b/gcc/testsuite/rust/compile/issue-3402-1.rs
new file mode 100644
index ..ed603cecaada
--- /dev/null
+++ b/gcc/testsuite/rust/compile/issue-3402-1.rs
@@ -0,0 +1,29 @@
+pub struct Foo {
+a: i32,
+// { dg-warning "field is never read" "" { target *-*-* } .-1 }
+}
+pub struct Bar(i32);
+
+#[lang = "sized"]
+trait Sized {}
+
+pub mod core {
+pub mod default {
+pub trait Default: Sized {
+fn default() -> Self;
+}
+
+impl Default for i32 {
+fn default() -> Self {
+0
+}
+}
+}
+}
+
+impl ::core::default::Default for Bar {
+#[inline]
+fn default() -> Bar {
+Bar(core::default::Default::default())
+}
+}
diff --git a/gcc/testsuite/rust/compile/issue-3402-2.rs 
b/gcc/testsuite/rust/compile/issue-3402-2.rs
new file mode 100644
index ..b665af25b51f
--- /dev/null
+++ b/gcc/testsuite/rust/compile/issue-3402-2.rs
@@ -0,0 +1,18 @@
+pub struct Bar(i32);
+
+#[lang = "sized"]
+trait Sized {}
+
+pub trait A: Sized {
+fn foo() -> Self;
+}
+
+impl A for i32 {
+fn foo() -> Self {
+0
+}
+}
+
+pub fn bar() {
+let _ = Bar(A::foo());
+}
diff --git a/gcc/testsuite/rust/compile/nr2/exclude 
b/gcc/testsuite/rust/compile/nr2/exclude
index f8e280e341c6..1b34e9fe20ec 100644
--- a/gcc/testsuite/rust/compile/nr2/exclude
+++ b/gcc/testsuite/rust/compile/nr2/exclude
@@ -125,4 +125,5 @@ try-trait.rs
 derive-debug1.rs
 issue-3382.rs
 derive-default1.rs
+issue-3402-1.rs
 # please don't delete the trailing newline

[gcc r15-8731] gccrs: derive(Copy): Improve bounds when deriving Copy

[Arthur Cohen via Gcc-cvs]

https://gcc.gnu.org/g:9061a823a114f1cd8c81ffafcba4eca31b0d1c96

commit r15-8731-g9061a823a114f1cd8c81ffafcba4eca31b0d1c96
Author: Arthur Cohen 
Date:   Thu Jan 16 14:46:06 2025 +0100

gccrs: derive(Copy): Improve bounds when deriving Copy

gcc/rust/ChangeLog:

* expand/rust-derive-copy.cc: Always add an extra Copy bound on 
generic Copy impls.

Diff:
---
 gcc/rust/expand/rust-derive-copy.cc | 9 +++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/gcc/rust/expand/rust-derive-copy.cc 
b/gcc/rust/expand/rust-derive-copy.cc
index 31b4819c0429..1d5f72bd656c 100644
--- a/gcc/rust/expand/rust-derive-copy.cc
+++ b/gcc/rust/expand/rust-derive-copy.cc
@@ -52,7 +52,7 @@ DeriveCopy::copy_impl (
   // for example:
   //
   // #[derive(Copy)]
-  // struct Be { ... }
+  // struct Be { ... }
   //
   // we need to generate the impl block:
   //
@@ -87,7 +87,12 @@ DeriveCopy::copy_impl (
  = GenericArg::create_type (std::move (associated_type));
generic_args.push_back (std::move (type_arg));
 
-   auto impl_type_param = builder.new_type_param (type_param);
+   std::vector> extra_bounds;
+   extra_bounds.emplace_back (std::unique_ptr (
+ new TraitBound (builder.type_path (LangItem::Kind::COPY), loc)));
+
+   auto impl_type_param
+ = builder.new_type_param (type_param, std::move (extra_bounds));
impl_generics.push_back (std::move (impl_type_param));
  }
  break;

[gcc r15-8817] gccrs: derive(Eq): Create copies of Eq typepath to avoid NodeId confusion

[Arthur Cohen via Gcc-cvs]

https://gcc.gnu.org/g:a4d2184f4305f631eec342b0b5e7fb31981cd31d

commit r15-8817-ga4d2184f4305f631eec342b0b5e7fb31981cd31d
Author: Arthur Cohen 
Date:   Thu Feb 20 09:11:21 2025 +

gccrs: derive(Eq): Create copies of Eq typepath to avoid NodeId confusion

gcc/rust/ChangeLog:

* expand/rust-derive-eq.cc: Copy `Eq` typepath.

Diff:
---
 gcc/rust/expand/rust-derive-eq.cc | 6 +-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/gcc/rust/expand/rust-derive-eq.cc 
b/gcc/rust/expand/rust-derive-eq.cc
index 47a8350d2ffc..dc173defd67e 100644
--- a/gcc/rust/expand/rust-derive-eq.cc
+++ b/gcc/rust/expand/rust-derive-eq.cc
@@ -113,13 +113,17 @@ DeriveEq::eq_impls (
   std::unique_ptr &&fn, std::string name,
   const std::vector> &type_generics)
 {
+  // We create two copies of the type-path to avoid duplicate NodeIds
   auto eq = builder.type_path ({"core", "cmp", "Eq"}, true);
+  auto eq_bound
+= builder.trait_bound (builder.type_path ({"core", "cmp", "Eq"}, true));
+
   auto steq = builder.type_path (LangItem::Kind::STRUCTURAL_TEQ);
 
   auto trait_items = vec (std::move (fn));
 
   auto eq_generics
-= setup_impl_generics (name, type_generics, builder.trait_bound (eq));
+= setup_impl_generics (name, type_generics, std::move (eq_bound));
   auto steq_generics = setup_impl_generics (name, type_generics);
 
   auto eq_impl = builder.trait_impl (eq, std::move (eq_generics.self_type),

[gcc r15-8820] gccrs: Remove some member functions from SingleASTNode

[Arthur Cohen via Gcc-cvs]

https://gcc.gnu.org/g:3538d23b6ceddfb16d91454dc9ff4ea7f64c6705

commit r15-8820-g3538d23b6ceddfb16d91454dc9ff4ea7f64c6705
Author: Owen Avery 
Date:   Fri Feb 21 22:51:32 2025 -0500

gccrs: Remove some member functions from SingleASTNode

gcc/rust/ChangeLog:

* ast/rust-ast.h
(SingleASTNode::take_trait_item): Remove.
(SingleASTNode::take_impl_item): Remove.
(SingleASTNode::take_trait_impl_item): Remove.
* expand/rust-expand-visitor.cc
(ExpandVisitor::visit): Replace calls to aforementioned
functions with calls to SingleASTNode::take_assoc_item.

Signed-off-by: Owen Avery 

Diff:
---
 gcc/rust/ast/rust-ast.h| 17 -
 gcc/rust/expand/rust-expand-visitor.cc |  7 ---
 2 files changed, 4 insertions(+), 20 deletions(-)

diff --git a/gcc/rust/ast/rust-ast.h b/gcc/rust/ast/rust-ast.h
index 42be097f0567..4d7d23d23cc7 100644
--- a/gcc/rust/ast/rust-ast.h
+++ b/gcc/rust/ast/rust-ast.h
@@ -1996,13 +1996,6 @@ public:
 return std::move (item);
   }
 
-  std::unique_ptr take_trait_item ()
-  {
-rust_assert (!is_error ());
-return std::unique_ptr (
-  static_cast (assoc_item.release ()));
-  }
-
   std::unique_ptr take_external_item ()
   {
 rust_assert (!is_error ());
@@ -2015,16 +2008,6 @@ public:
 return std::move (assoc_item);
   }
 
-  std::unique_ptr take_impl_item ()
-  {
-return take_assoc_item ();
-  }
-
-  std::unique_ptr take_trait_impl_item ()
-  {
-return take_assoc_item ();
-  }
-
   std::unique_ptr take_type ()
   {
 rust_assert (!is_error ());
diff --git a/gcc/rust/expand/rust-expand-visitor.cc 
b/gcc/rust/expand/rust-expand-visitor.cc
index 2830d200f72d..1d131b181805 100644
--- a/gcc/rust/expand/rust-expand-visitor.cc
+++ b/gcc/rust/expand/rust-expand-visitor.cc
@@ -865,7 +865,7 @@ ExpandVisitor::visit (AST::Trait &trait)
 
   std::function (AST::SingleASTNode)>
 extractor
-= [] (AST::SingleASTNode node) { return node.take_trait_item (); };
+= [] (AST::SingleASTNode node) { return node.take_assoc_item (); };
 
   expand_macro_children (MacroExpander::ContextType::TRAIT,
 trait.get_trait_items (), extractor);
@@ -892,7 +892,8 @@ ExpandVisitor::visit (AST::InherentImpl &impl)
 expand_where_clause (impl.get_where_clause ());
 
   std::function (AST::SingleASTNode)>
-extractor = [] (AST::SingleASTNode node) { return node.take_impl_item (); 
};
+extractor
+= [] (AST::SingleASTNode node) { return node.take_assoc_item (); };
 
   expand_macro_children (MacroExpander::ContextType::IMPL,
 impl.get_impl_items (), extractor);
@@ -920,7 +921,7 @@ ExpandVisitor::visit (AST::TraitImpl &impl)
 
   std::function (AST::SingleASTNode)>
 extractor
-= [] (AST::SingleASTNode node) { return node.take_trait_impl_item (); };
+= [] (AST::SingleASTNode node) { return node.take_assoc_item (); };
 
   expand_macro_children (MacroExpander::ContextType::TRAIT_IMPL,
 impl.get_impl_items (), extractor);

[gcc r15-8769] gccrs: ast-builder: Add new methods for functions, traits and tuples.

[Arthur Cohen via Gcc-cvs]

https://gcc.gnu.org/g:554150f889ad2a00456c1d5c44bf12e025557aaa

commit r15-8769-g554150f889ad2a00456c1d5c44bf12e025557aaa
Author: Arthur Cohen 
Date:   Thu Jan 30 10:50:13 2025 +0100

gccrs: ast-builder: Add new methods for functions, traits and tuples.

gcc/rust/ChangeLog:

* ast/rust-ast-builder.cc: New methods.
* ast/rust-ast-builder.h: Declare them.

Diff:
---
 gcc/rust/ast/rust-ast-builder.cc | 62 
 gcc/rust/ast/rust-ast-builder.h  | 36 +--
 2 files changed, 96 insertions(+), 2 deletions(-)

diff --git a/gcc/rust/ast/rust-ast-builder.cc b/gcc/rust/ast/rust-ast-builder.cc
index 4d94f0da573c..3a3181f3752d 100644
--- a/gcc/rust/ast/rust-ast-builder.cc
+++ b/gcc/rust/ast/rust-ast-builder.cc
@@ -26,6 +26,7 @@
 #include "rust-path.h"
 #include "rust-system.h"
 #include "rust-token.h"
+#include 
 
 namespace Rust {
 namespace AST {
@@ -83,12 +84,46 @@ Builder::tuple_idx (std::string receiver, int idx) const
 new TupleIndexExpr (identifier (receiver), idx, {}, loc));
 }
 
+std::unique_ptr
+Builder::tuple (std::vector> &&values) const
+{
+  return std::unique_ptr (
+new TupleExpr (std::move (values), {}, {}, loc));
+}
+
+std::unique_ptr
+Builder::self_ref_param (bool mutability) const
+{
+  return std::make_unique (Lifetime::error (), mutability, loc);
+}
+
+std::unique_ptr
+Builder::function_param (std::unique_ptr &&pattern,
+std::unique_ptr &&type) const
+{
+  return std::unique_ptr (
+new FunctionParam (std::move (pattern), std::move (type), {}, loc));
+}
+
 FunctionQualifiers
 Builder::fn_qualifiers () const
 {
   return FunctionQualifiers (loc, Async::No, Const::No, Unsafety::Normal);
 }
 
+Function
+Builder::function (Identifier function_name,
+  std::vector> params,
+  std::unique_ptr return_type,
+  std::unique_ptr block,
+  FunctionQualifiers qualifiers, WhereClause where_clause,
+  Visibility visibility) const
+{
+  return Function (function_name, qualifiers, {}, std::move (params),
+  std::move (return_type), where_clause, std::move (block),
+  visibility, {}, loc);
+}
+
 PathExprSegment
 Builder::path_segment (std::string seg) const
 {
@@ -198,6 +233,14 @@ Builder::type_path (LangItem::Kind lang_item) const
   return type_path (type_path_segment (lang_item));
 }
 
+std::unique_ptr
+Builder::reference_type (std::unique_ptr &&inner_type,
+bool mutability) const
+{
+  return std::make_unique (mutability, std::move (inner_type),
+ loc);
+}
+
 PathInExpression
 Builder::path_in_expression (std::vector &&segments) const
 {
@@ -356,6 +399,25 @@ Builder::loop (std::vector> &&stmts)
   return std::unique_ptr (new LoopExpr (std::move (block), loc));
 }
 
+std::unique_ptr
+Builder::trait_bound (TypePath bound)
+{
+  return std::make_unique (bound, loc);
+}
+
+std::unique_ptr
+Builder::trait_impl (TypePath trait_path, std::unique_ptr target,
+std::vector> trait_items,
+std::vector> generics,
+WhereClause where_clause, Visibility visibility) const
+{
+  return std::unique_ptr (
+new TraitImpl (trait_path, /* unsafe */ false,
+  /* exclam */ false, std::move (trait_items),
+  std::move (generics), std::move (target), where_clause,
+  visibility, {}, {}, loc));
+}
+
 std::unique_ptr
 Builder::new_type (Type &type)
 {
diff --git a/gcc/rust/ast/rust-ast-builder.h b/gcc/rust/ast/rust-ast-builder.h
index 47e8f7f5bbb0..9c5c1645eb94 100644
--- a/gcc/rust/ast/rust-ast-builder.h
+++ b/gcc/rust/ast/rust-ast-builder.h
@@ -70,6 +70,10 @@ public:
   /* Create a tuple index expression (`receiver.0`) */
   std::unique_ptr tuple_idx (std::string receiver, int idx) const;
 
+  /* Create a tuple expression (`(a1, a2, a3)`) */
+  std::unique_ptr tuple (std::vector> &&values
+  = {}) const;
+
   /* Create a reference to an expression (`&of`) */
   std::unique_ptr ref (std::unique_ptr &&of,
 bool mut = false) const;
@@ -106,9 +110,25 @@ public:
   std::unique_ptr
   array (std::vector> &&members) const;
 
+  /* Self parameter for a function definition (`&self`) */
+  std::unique_ptr self_ref_param (bool mutability = false) const;
+  /* A regular named function parameter for a definition (`a: type`) */
+  std::unique_ptr function_param (std::unique_ptr &&pattern,
+std::unique_ptr &&type) const;
+
   /* Empty function qualifiers, with no specific qualifiers */
   FunctionQualifiers fn_qualifiers () const;
 
+  Function
+  function (Identifier function_name,
+   std::vector> params,
+   std::unique_ptr return_type, std::unique_ptr block,
+   FunctionQualifiers qualifiers
+   = FunctionQualifier

[gcc r15-8865] testsuite: d: Break up Wbuiltin_declaration_mismatch2.d into smaller tests

[Iain Buclaw via Gcc-cvs]

https://gcc.gnu.org/g:0d998b38a6fd280973fa6e91d3e34e544eef8fb2

commit r15-8865-g0d998b38a6fd280973fa6e91d3e34e544eef8fb2
Author: Iain Buclaw 
Date:   Mon Mar 24 14:07:49 2025 +0100

testsuite: d: Break up Wbuiltin_declaration_mismatch2.d into smaller tests

gcc/testsuite/ChangeLog:

* gdc.dg/Wbuiltin_declaration_mismatch2.d: Split test into ...
* gdc.dg/Wbuiltin_declaration_mismatch3.d: New test.
* gdc.dg/Wbuiltin_declaration_mismatch4.d: New test.
* gdc.dg/Wbuiltin_declaration_mismatch5.d: New test.
* gdc.dg/Wbuiltin_declaration_mismatch6.d: New test.

Diff:
---
 .../gdc.dg/Wbuiltin_declaration_mismatch2.d| 176 -
 .../gdc.dg/Wbuiltin_declaration_mismatch3.d|  61 +++
 .../gdc.dg/Wbuiltin_declaration_mismatch4.d|  51 ++
 .../gdc.dg/Wbuiltin_declaration_mismatch5.d|  53 +++
 .../gdc.dg/Wbuiltin_declaration_mismatch6.d|  61 +++
 5 files changed, 226 insertions(+), 176 deletions(-)

diff --git a/gcc/testsuite/gdc.dg/Wbuiltin_declaration_mismatch2.d 
b/gcc/testsuite/gdc.dg/Wbuiltin_declaration_mismatch2.d
index 0d12bcb8b079..8dcba79bfc3d 100644
--- a/gcc/testsuite/gdc.dg/Wbuiltin_declaration_mismatch2.d
+++ b/gcc/testsuite/gdc.dg/Wbuiltin_declaration_mismatch2.d
@@ -28,183 +28,7 @@ void test_load_store()
 storeUnaligned!fake4(null, f); // { dg-warning "mismatch in return type" }
 }
 
-void test_shuffle()
-{
-shuffle!(int, int, int)(0, 0, 0); // { dg-warning "mismatch in return 
type" }
-shuffle!(double, int, int)(0, 0, 0); // { dg-warning "mismatch in return 
type" }
-shuffle!(fake4, int, int)(f, 0, 0); // { dg-warning "mismatch in return 
type" }
-
-shuffle!(int4, int, int)(0, 0, 0); // { dg-warning "mismatch in argument 
2" }
-shuffle!(int4, double, int)(0, 0, 0); // { dg-warning "mismatch in 
argument 2" }
-shuffle!(int4, fake4, int)(0, f, 0); // { dg-warning "mismatch in argument 
2" }
-
-shuffle!(int4, int4, int)(0, 0, 0); // { dg-warning "mismatch in argument 
3" }
-shuffle!(int4, int4, double)(0, 0, 0); // { dg-warning "mismatch in 
argument 3" }
-shuffle!(int4, int4, fake4)(0, 0, f); // { dg-warning "mismatch in 
argument 3" }
-
-shuffle!(int4, int4, int4)(0, 0, 0);
-shuffle!(int4, short8, int4)(0, 0, 0); // { dg-error "mismatch in argument 
2" }
-shuffle!(int4, float4, int4)(0, 0, 0); // { dg-error "mismatch in argument 
2" }
-shuffle!(int4, byte16, int4)(0, 0, 0); // { dg-error "mismatch in argument 
2" }
-shuffle!(int4, int4, short8)(0, 0, 0); // { dg-error "mismatch in argument 
3" }
-shuffle!(int4, int4, float4)(0, 0, 0); // { dg-error "mismatch in argument 
3" }
-shuffle!(int4, int4, byte16)(0, 0, 0); // { dg-error "mismatch in argument 
3" }
-
-shuffle!(float4, int4, int4)(0, 0, 0); // { dg-error "mismatch in argument 
2" }
-shuffle!(float4, short8, int4)(0, 0, 0); // { dg-error "mismatch in 
argument 2" }
-shuffle!(float4, float4, int4)(0, 0, 0);
-shuffle!(float4, byte16, int4)(0, 0, 0); // { dg-error "mismatch in 
argument 2" }
-shuffle!(float4, float4, short8)(0, 0, 0); // { dg-error "mismatch in 
argument 3" }
-shuffle!(float4, float4, float4)(0, 0, 0); // { dg-error "mismatch in 
argument 3" }
-shuffle!(float4, float4, byte16)(0, 0, 0); // { dg-error "mismatch in 
argument 3" }
-
-shuffle!(short8, int4, int4)(0, 0, 0); // { dg-error "mismatch in argument 
2" }
-shuffle!(short8, short8, int4)(0, 0, 0); // { dg-error "mismatch in 
argument 3" }
-shuffle!(short8, float4, int4)(0, 0, 0); // { dg-error "mismatch in 
argument 2" }
-shuffle!(short8, byte16, int4)(0, 0, 0); // { dg-error "mismatch in 
argument 2" }
-shuffle!(short8, short8, short8)(0, 0, 0);
-shuffle!(short8, short8, float4)(0, 0, 0); // { dg-error "mismatch in 
argument 3" }
-shuffle!(short8, short8, byte16)(0, 0, 0); // { dg-error "mismatch in 
argument 3" }
-
-shuffle!(byte16, int4, int4)(0, 0, 0); // { dg-error "mismatch in argument 
2" }
-shuffle!(byte16, short8, int4)(0, 0, 0); // { dg-error "mismatch in 
argument 2" }
-shuffle!(byte16, float4, int4)(0, 0, 0); // { dg-error "mismatch in 
argument 2" }
-shuffle!(byte16, byte16, int4)(0, 0, 0); // { dg-error "mismatch in 
argument 3" }
-shuffle!(byte16, byte16, short8)(0, 0, 0); // { dg-error "mismatch in 
argument 3" }
-shuffle!(byte16, byte16, float4)(0, 0, 0); // { dg-error "mismatch in 
argument 3" }
-shuffle!(byte16, byte16, byte16)(0, 0, 0);
-}
-
-void test_shufflevector()
-{
-shufflevector!(int, int4, int, int, int, int)(0, 0, 0, 0, 0, 0); // { 
dg-warning "mismatch in argument 1" }
-shufflevector!(double, int4, int, int, int, int)(0, 0, 0, 0, 0, 0); // { 
dg-warning "mismatch in argument 1" }
-shufflevector!(fake4, int4, int, int, int, int)(f, 0, 0, 0, 0, 0); // { 
dg-warning "mismatch in argument 1" }
-
-shufflevector!(int4, int, int, int, int, int)(0, 0,

[gcc r15-8838] gccrs: nr2.0: Set the node id of the root node

[Arthur Cohen via Gcc-cvs]

https://gcc.gnu.org/g:f9dce5e97dd9a6a3f618ced89f5e05729b0d5fe8

commit r15-8838-gf9dce5e97dd9a6a3f618ced89f5e05729b0d5fe8
Author: Owen Avery 
Date:   Tue Feb 18 03:56:33 2025 -0500

gccrs: nr2.0: Set the node id of the root node

gcc/rust/ChangeLog:

* resolve/rust-forever-stack.h
(ForeverStack::ForeverStack): Set the node id of the root node
to that of the current crate.
* resolve/rust-forever-stack.hxx
(ForeverStack::find_starting_point): Use the node id of the root
node during resolution of crate segments.

gcc/testsuite/ChangeLog:

* rust/compile/nr2/exclude: Remove entries.

Signed-off-by: Owen Avery 

Diff:
---
 gcc/rust/resolve/rust-forever-stack.h   | 7 +--
 gcc/rust/resolve/rust-forever-stack.hxx | 7 +--
 gcc/testsuite/rust/compile/nr2/exclude  | 2 --
 3 files changed, 6 insertions(+), 10 deletions(-)

diff --git a/gcc/rust/resolve/rust-forever-stack.h 
b/gcc/rust/resolve/rust-forever-stack.h
index f1e5e8d2f2d1..64e8a0f0f2c9 100644
--- a/gcc/rust/resolve/rust-forever-stack.h
+++ b/gcc/rust/resolve/rust-forever-stack.h
@@ -547,13 +547,16 @@ template  class ForeverStack
 {
 public:
   ForeverStack ()
-// FIXME: Is that valid? Do we use the root? If yes, we should give the
-// crate's node id to ForeverStack's constructor
 : root (Node (Rib (Rib::Kind::Normal), UNKNOWN_NODEID)),
   cursor_reference (root)
   {
 rust_assert (root.is_root ());
 rust_assert (root.is_leaf ());
+
+// TODO: Should we be using the forever stack root as the crate scope?
+// TODO: Is this how we should be getting the crate node id?
+auto &mappings = Analysis::Mappings::get ();
+root.id = *mappings.crate_num_to_nodeid (mappings.get_current_crate ());
   }
 
   /**
diff --git a/gcc/rust/resolve/rust-forever-stack.hxx 
b/gcc/rust/resolve/rust-forever-stack.hxx
index 9ca8db2c09d3..c1407344b523 100644
--- a/gcc/rust/resolve/rust-forever-stack.hxx
+++ b/gcc/rust/resolve/rust-forever-stack.hxx
@@ -401,12 +401,7 @@ ForeverStack::find_starting_point (
   if (seg.is_crate_path_seg ())
{
  starting_point = root;
- // TODO: is this how we should be getting the crate node id?
- auto &mappings = Analysis::Mappings::get ();
- NodeId current_crate
-   = *mappings.crate_num_to_nodeid (mappings.get_current_crate ());
-
- insert_segment_resolution (outer_seg, current_crate);
+ insert_segment_resolution (outer_seg, starting_point.get ().id);
  iterator++;
  break;
}
diff --git a/gcc/testsuite/rust/compile/nr2/exclude 
b/gcc/testsuite/rust/compile/nr2/exclude
index 763387f35488..e179dc30004b 100644
--- a/gcc/testsuite/rust/compile/nr2/exclude
+++ b/gcc/testsuite/rust/compile/nr2/exclude
@@ -1,7 +1,6 @@
 break-rust2.rs
 canonical_paths1.rs
 cfg1.rs
-complex-path1.rs
 const_generics_3.rs
 const_generics_4.rs
 feature_rust_attri0.rs
@@ -29,7 +28,6 @@ pub_restricted_2.rs
 pub_restricted_3.rs
 redef_error2.rs
 redef_error5.rs
-self-path1.rs
 self-path2.rs
 sizeof-stray-infer-var-bug.rs
 struct-expr-parse.rs

[gcc r15-8845] gccrs: remove visitor which is not needed here

[Arthur Cohen via Gcc-cvs]

https://gcc.gnu.org/g:29b76999b69adadb52c0ecb06ed24a4f323e8626

commit r15-8845-g29b76999b69adadb52c0ecb06ed24a4f323e8626
Author: Philip Herron 
Date:   Tue Feb 18 17:44:05 2025 +

gccrs: remove visitor which is not needed here

Just a small refactor to remove a visitor which is not needed.

gcc/rust/ChangeLog:

* backend/rust-compile-resolve-path.cc (ResolvePathRef::Compile): 
remove visitor
(ResolvePathRef::ResolvePathRef): likewise
(ResolvePathRef::visit): likewise
* backend/rust-compile-resolve-path.h (class ResolvePathRef): 
likewise

Signed-off-by: Philip Herron 

Diff:
---
 gcc/rust/backend/rust-compile-resolve-path.cc | 28 +++-
 gcc/rust/backend/rust-compile-resolve-path.h  | 38 +++
 2 files changed, 20 insertions(+), 46 deletions(-)

diff --git a/gcc/rust/backend/rust-compile-resolve-path.cc 
b/gcc/rust/backend/rust-compile-resolve-path.cc
index c54cc09b67be..2b6880c9b1aa 100644
--- a/gcc/rust/backend/rust-compile-resolve-path.cc
+++ b/gcc/rust/backend/rust-compile-resolve-path.cc
@@ -32,6 +32,22 @@
 namespace Rust {
 namespace Compile {
 
+tree
+ResolvePathRef::Compile (HIR::QualifiedPathInExpression &expr, Context *ctx)
+{
+  ResolvePathRef resolver (ctx);
+  return resolver.resolve_path_like (expr);
+}
+
+tree
+ResolvePathRef::Compile (HIR::PathInExpression &expr, Context *ctx)
+{
+  ResolvePathRef resolver (ctx);
+  return resolver.resolve_path_like (expr);
+}
+
+ResolvePathRef::ResolvePathRef (Context *ctx) : HIRCompileBase (ctx) {}
+
 template 
 tree
 ResolvePathRef::resolve_path_like (T &expr)
@@ -53,18 +69,6 @@ ResolvePathRef::resolve_path_like (T &expr)
  expr.get_mappings (), expr.get_locus (), true);
 }
 
-void
-ResolvePathRef::visit (HIR::QualifiedPathInExpression &expr)
-{
-  resolved = resolve_path_like (expr);
-}
-
-void
-ResolvePathRef::visit (HIR::PathInExpression &expr)
-{
-  resolved = resolve_path_like (expr);
-}
-
 tree
 ResolvePathRef::attempt_constructor_expression_lookup (
   TyTy::BaseType *lookup, Context *ctx, const Analysis::NodeMapping &mappings,
diff --git a/gcc/rust/backend/rust-compile-resolve-path.h 
b/gcc/rust/backend/rust-compile-resolve-path.h
index 12cdc19cabad..79bfb86d6d25 100644
--- a/gcc/rust/backend/rust-compile-resolve-path.h
+++ b/gcc/rust/backend/rust-compile-resolve-path.h
@@ -20,46 +20,18 @@
 #define RUST_COMPILE_RESOLVE_PATH
 
 #include "rust-compile-base.h"
-#include "rust-hir-visitor.h"
 
 namespace Rust {
 namespace Compile {
 
-class ResolvePathRef : public HIRCompileBase, public HIR::HIRPatternVisitor
+class ResolvePathRef : public HIRCompileBase
 {
 public:
-  static tree Compile (HIR::QualifiedPathInExpression &expr, Context *ctx)
-  {
-ResolvePathRef resolver (ctx);
-expr.accept_vis (resolver);
-return resolver.resolved;
-  }
+  static tree Compile (HIR::QualifiedPathInExpression &expr, Context *ctx);
 
-  static tree Compile (HIR::PathInExpression &expr, Context *ctx)
-  {
-ResolvePathRef resolver (ctx);
-expr.accept_vis (resolver);
-return resolver.resolved;
-  }
+  static tree Compile (HIR::PathInExpression &expr, Context *ctx);
 
-  void visit (HIR::PathInExpression &expr) override;
-  void visit (HIR::QualifiedPathInExpression &expr) override;
-
-  // Empty visit for unused Pattern HIR nodes.
-  void visit (HIR::IdentifierPattern &) override {}
-  void visit (HIR::LiteralPattern &) override {}
-  void visit (HIR::RangePattern &) override {}
-  void visit (HIR::ReferencePattern &) override {}
-  void visit (HIR::SlicePattern &) override {}
-  void visit (HIR::AltPattern &) override {}
-  void visit (HIR::StructPattern &) override {}
-  void visit (HIR::TuplePattern &) override {}
-  void visit (HIR::TupleStructPattern &) override {}
-  void visit (HIR::WildcardPattern &) override {}
-
-  ResolvePathRef (Context *ctx)
-: HIRCompileBase (ctx), resolved (error_mark_node)
-  {}
+  ResolvePathRef (Context *ctx);
 
   /**
* Generic visitor for both PathInExpression and QualifiedPathInExpression
@@ -81,8 +53,6 @@ public:
const Analysis::NodeMapping &mappings, location_t locus,
bool is_qualified_path);
 
-  tree resolved;
-
 private:
   tree
   attempt_constructor_expression_lookup (TyTy::BaseType *lookup, Context *ctx,

[gcc r15-8801] gccrs: improve error diagnostic for bad type-resolution in CallExpr

[Arthur Cohen via Gcc-cvs]

https://gcc.gnu.org/g:093ae1547cbaf1b818b96d25d1d0235b69255c24

commit r15-8801-g093ae1547cbaf1b818b96d25d1d0235b69255c24
Author: Philip Herron 
Date:   Fri Feb 14 17:32:20 2025 +

gccrs: improve error diagnostic for bad type-resolution in CallExpr

We have the type information for the resolved call lets tell the user about
it in the diagnostic and apply the correct error code.

Fixes Rust-GCC#2035

gcc/rust/ChangeLog:

* typecheck/rust-hir-type-check-expr.cc (TypeCheckExpr::visit): 
improve error diag

gcc/testsuite/ChangeLog:

* rust/compile/generics4.rs: cleanup
* rust/compile/generics6.rs: likewise
* rust/compile/type-bindings1.rs: likewise
* rust/compile/unconstrained_type_param.rs: likewise
* rust/compile/issue-2035.rs: New test.

Signed-off-by: Philip Herron 

Diff:
---
 gcc/rust/typecheck/rust-hir-type-check-expr.cc | 13 +
 gcc/testsuite/rust/compile/generics4.rs|  1 -
 gcc/testsuite/rust/compile/generics6.rs|  1 -
 gcc/testsuite/rust/compile/issue-2035.rs   | 10 ++
 gcc/testsuite/rust/compile/type-bindings1.rs   |  1 -
 gcc/testsuite/rust/compile/unconstrained_type_param.rs |  1 -
 6 files changed, 19 insertions(+), 8 deletions(-)

diff --git a/gcc/rust/typecheck/rust-hir-type-check-expr.cc 
b/gcc/rust/typecheck/rust-hir-type-check-expr.cc
index 5c38cb42b39b..85d717535ed7 100644
--- a/gcc/rust/typecheck/rust-hir-type-check-expr.cc
+++ b/gcc/rust/typecheck/rust-hir-type-check-expr.cc
@@ -225,12 +225,17 @@ TypeCheckExpr::visit (HIR::CallExpr &expr)
   if (resolved_fn_trait_call)
 return;
 
-  bool valid_tyty = function_tyty->get_kind () == TyTy::TypeKind::FNDEF
-   || function_tyty->get_kind () == TyTy::TypeKind::FNPTR;
+  bool valid_tyty
+= function_tyty->is () || function_tyty->is ();
   if (!valid_tyty)
 {
-  rust_error_at (expr.get_locus (),
-"Failed to resolve expression of function call");
+  bool emit_error = !function_tyty->is ();
+  if (emit_error)
+   {
+ rich_location r (line_table, expr.get_locus ());
+ rust_error_at (r, ErrorCode::E0618, "expected function, found %<%s%>",
+function_tyty->get_name ().c_str ());
+   }
   return;
 }
 
diff --git a/gcc/testsuite/rust/compile/generics4.rs 
b/gcc/testsuite/rust/compile/generics4.rs
index 31b681abb10e..c4dbc432c07c 100644
--- a/gcc/testsuite/rust/compile/generics4.rs
+++ b/gcc/testsuite/rust/compile/generics4.rs
@@ -6,7 +6,6 @@ struct GenericStruct(T, usize);
 fn main() {
 let a2;
 a2 = GenericStruct::(1, 456); // { dg-error "generic item takes 
at most 1 type arguments but 2 were supplied" }
-   // { dg-error {Failed to resolve 
expression of function call} "" { target *-*-* } .-1 }
 
 let b2: i32 = a2.0;
 // { dg-error {Expected Tuple or ADT got: T\?} "" { target *-*-* } .-1 }
diff --git a/gcc/testsuite/rust/compile/generics6.rs 
b/gcc/testsuite/rust/compile/generics6.rs
index 33093cf706b9..d77c559db213 100644
--- a/gcc/testsuite/rust/compile/generics6.rs
+++ b/gcc/testsuite/rust/compile/generics6.rs
@@ -27,6 +27,5 @@ impl Foo {
 
 fn main() {
 let a: i32 = Foo::test(); // { dg-error "multiple applicable items in 
scope for: .test." }
-// { dg-error {Failed to resolve expression of function call} "" { target 
*-*-* } .-1 }
 }
 
diff --git a/gcc/testsuite/rust/compile/issue-2035.rs 
b/gcc/testsuite/rust/compile/issue-2035.rs
new file mode 100644
index ..c0817d532cc1
--- /dev/null
+++ b/gcc/testsuite/rust/compile/issue-2035.rs
@@ -0,0 +1,10 @@
+fn func(i: i32) {
+i();
+// { dg-error "expected function, found .i32. .E0618." "" { target *-*-* } 
.-1 }
+}
+
+fn main() {
+let i = 0i32;
+i();
+// { dg-error "expected function, found .i32. .E0618." "" { target *-*-* } 
.-1 }
+}
diff --git a/gcc/testsuite/rust/compile/type-bindings1.rs 
b/gcc/testsuite/rust/compile/type-bindings1.rs
index 358035bbc171..ef0b47128dfa 100644
--- a/gcc/testsuite/rust/compile/type-bindings1.rs
+++ b/gcc/testsuite/rust/compile/type-bindings1.rs
@@ -7,5 +7,4 @@ fn main() {
 let a;
 a = Foo::(123f32);
 // { dg-error "associated type bindings are not allowed here" "" { target 
*-*-* } .-1 }
-// { dg-error {Failed to resolve expression of function call} "" { target 
*-*-* } .-2 }
 }
diff --git a/gcc/testsuite/rust/compile/unconstrained_type_param.rs 
b/gcc/testsuite/rust/compile/unconstrained_type_param.rs
index 1cef0b983b0a..60554dac0e01 100644
--- a/gcc/testsuite/rust/compile/unconstrained_type_param.rs
+++ b/gcc/testsuite/rust/compile/unconstrained_type_param.rs
@@ -13,5 +13,4 @@ impl Foo {
 fn main() {
 let a = Foo::test();
 // { dg-error "expected" "" { target *-*-* } .-1 }
-// { dg-error "Failed to resolve expression of functio

[gcc r15-8861] gccrs: Modify multiple definition error

[Arthur Cohen via Gcc-cvs]

https://gcc.gnu.org/g:853f57877d56db503075c1ea3ffc29a005c6489c

commit r15-8861-g853f57877d56db503075c1ea3ffc29a005c6489c
Author: Owen Avery 
Date:   Sun Feb 23 16:45:41 2025 -0500

gccrs: Modify multiple definition error

gcc/rust/ChangeLog:

* resolve/rust-ast-resolve-expr.cc
(ResolveExpr::visit): Modify error message.
* resolve/rust-ast-resolve-implitem.h
(ResolveToplevelImplItem::visit): Likewise.
(ResolveTopLevelTraitItems::visit): Likewise.
(ResolveToplevelExternItem::visit): Likewise.
* resolve/rust-ast-resolve-stmt.cc
(ResolveStmt::visit): Likewise.
* resolve/rust-ast-resolve-stmt.h
(ResolveStmt::visit): Likewise.
* resolve/rust-ast-resolve-toplevel.h
(ResolveTopLevel::visit): Likewise.
* resolve/rust-ast-resolve-type.h
(ResolveGenericParams::visit): Likewise.

gcc/testsuite/ChangeLog:

* rust/compile/nr2/exclude: Remove entries.
* rust/compile/redef_error2.rs: Modify expected error.
* rust/compile/redef_error5.rs: Likewise.

Signed-off-by: Owen Avery 

Diff:
---
 gcc/rust/resolve/rust-ast-resolve-expr.cc|  8 +++
 gcc/rust/resolve/rust-ast-resolve-implitem.h | 18 
 gcc/rust/resolve/rust-ast-resolve-stmt.cc|  2 +-
 gcc/rust/resolve/rust-ast-resolve-stmt.h | 20 -
 gcc/rust/resolve/rust-ast-resolve-toplevel.h | 32 ++--
 gcc/rust/resolve/rust-ast-resolve-type.h |  2 +-
 gcc/testsuite/rust/compile/nr2/exclude   |  2 --
 gcc/testsuite/rust/compile/redef_error2.rs   |  2 +-
 gcc/testsuite/rust/compile/redef_error5.rs   |  2 +-
 9 files changed, 43 insertions(+), 45 deletions(-)

diff --git a/gcc/rust/resolve/rust-ast-resolve-expr.cc 
b/gcc/rust/resolve/rust-ast-resolve-expr.cc
index be960beccd50..dc7f76d652dd 100644
--- a/gcc/rust/resolve/rust-ast-resolve-expr.cc
+++ b/gcc/rust/resolve/rust-ast-resolve-expr.cc
@@ -287,7 +287,7 @@ ResolveExpr::visit (AST::BlockExpr &expr)
CanonicalPath::new_seg (label.get_node_id (), label_name),
label_lifetime_node_id, label.get_locus (), false, Rib::ItemType::Label,
[&] (const CanonicalPath &, NodeId, location_t locus) -> void {
- rust_error_at (label.get_locus (), "label redefined multiple times");
+ rust_error_at (label.get_locus (), "label defined multiple times");
  rust_error_at (locus, "was defined here");
});
 }
@@ -459,7 +459,7 @@ ResolveExpr::visit (AST::LoopExpr &expr)
CanonicalPath::new_seg (expr.get_node_id (), label_name),
label_lifetime_node_id, label.get_locus (), false, Rib::ItemType::Label,
[&] (const CanonicalPath &, NodeId, location_t locus) -> void {
- rust_error_at (label.get_locus (), "label redefined multiple times");
+ rust_error_at (label.get_locus (), "label defined multiple times");
  rust_error_at (locus, "was defined here");
});
 }
@@ -535,7 +535,7 @@ ResolveExpr::visit (AST::WhileLoopExpr &expr)
CanonicalPath::new_seg (label.get_node_id (), label_name),
label_lifetime_node_id, label.get_locus (), false, Rib::ItemType::Label,
[&] (const CanonicalPath &, NodeId, location_t locus) -> void {
- rust_error_at (label.get_locus (), "label redefined multiple times");
+ rust_error_at (label.get_locus (), "label defined multiple times");
  rust_error_at (locus, "was defined here");
});
 }
@@ -564,7 +564,7 @@ ResolveExpr::visit (AST::ForLoopExpr &expr)
CanonicalPath::new_seg (label.get_node_id (), label_name),
label_lifetime_node_id, label.get_locus (), false, Rib::ItemType::Label,
[&] (const CanonicalPath &, NodeId, location_t locus) -> void {
- rust_error_at (label.get_locus (), "label redefined multiple times");
+ rust_error_at (label.get_locus (), "label defined multiple times");
  rust_error_at (locus, "was defined here");
});
 }
diff --git a/gcc/rust/resolve/rust-ast-resolve-implitem.h 
b/gcc/rust/resolve/rust-ast-resolve-implitem.h
index 2ca12965d9b9..971bf8faee2e 100644
--- a/gcc/rust/resolve/rust-ast-resolve-implitem.h
+++ b/gcc/rust/resolve/rust-ast-resolve-implitem.h
@@ -51,7 +51,7 @@ public:
   [&] (const CanonicalPath &, NodeId, location_t locus) -> void {
rich_location r (line_table, type.get_locus ());
r.add_range (locus);
-   rust_error_at (r, "redefined multiple times");
+   rust_error_at (r, "defined multiple times");
   });
   }
 
@@ -67,7 +67,7 @@ public:
   [&] (const CanonicalPath &, NodeId, location_t locus) -> void {
rich_location r (line_table, constant.get_locus ());
r.add_range (locus);
-   rust_error_at (r, "redefined multiple times");
+   rust_error_at (r, "defined multiple times");
   });
   }
 
@@ -84,7 +84,7 @

[gcc r15-8860] gccrs: nr2.0: Adjust visitors for struct expressions

[Arthur Cohen via Gcc-cvs]

https://gcc.gnu.org/g:f1ccfd074bc3a95eb6289c08b44f79aed8ad7b84

commit r15-8860-gf1ccfd074bc3a95eb6289c08b44f79aed8ad7b84
Author: Owen Avery 
Date:   Sun Feb 9 03:28:43 2025 -0500

gccrs: nr2.0: Adjust visitors for struct expressions

gcc/rust/ChangeLog:

* ast/rust-ast-visitor.cc
(DefaultASTVisitor::visit): Make sure to always visit the struct
name.
* resolve/rust-late-name-resolver-2.0.cc
(Late::visit): Avoid visiting the struct name twice.

gcc/testsuite/ChangeLog:

* rust/compile/nr2/exclude: Remove entries.

Signed-off-by: Owen Avery 

Diff:
---
 gcc/rust/ast/rust-ast-visitor.cc|  2 ++
 gcc/rust/resolve/rust-late-name-resolver-2.0.cc | 20 +---
 gcc/testsuite/rust/compile/nr2/exclude  |  5 -
 3 files changed, 19 insertions(+), 8 deletions(-)

diff --git a/gcc/rust/ast/rust-ast-visitor.cc b/gcc/rust/ast/rust-ast-visitor.cc
index 077b41b5cacf..ba5f87bc2ebb 100644
--- a/gcc/rust/ast/rust-ast-visitor.cc
+++ b/gcc/rust/ast/rust-ast-visitor.cc
@@ -392,6 +392,7 @@ DefaultASTVisitor::visit (AST::StructExprStructFields &expr)
 {
   visit_outer_attrs (expr);
   visit_inner_attrs (expr);
+  visit (expr.get_struct_name ());
   if (expr.has_struct_base ())
 visit (expr.get_struct_base ());
   for (auto &field : expr.get_fields ())
@@ -403,6 +404,7 @@ DefaultASTVisitor::visit (AST::StructExprStructBase &expr)
 {
   visit_outer_attrs (expr);
   visit_inner_attrs (expr);
+  visit (expr.get_struct_name ());
   visit (expr.get_struct_base ());
 }
 
diff --git a/gcc/rust/resolve/rust-late-name-resolver-2.0.cc 
b/gcc/rust/resolve/rust-late-name-resolver-2.0.cc
index f4ad53a02ade..a8eb3b4fa12a 100644
--- a/gcc/rust/resolve/rust-late-name-resolver-2.0.cc
+++ b/gcc/rust/resolve/rust-late-name-resolver-2.0.cc
@@ -351,6 +351,10 @@ Late::visit (AST::StructStruct &s)
 void
 Late::visit (AST::StructExprStruct &s)
 {
+  visit_outer_attrs (s);
+  visit_inner_attrs (s);
+  DefaultResolver::visit (s.get_struct_name ());
+
   auto resolved
 = ctx.resolve_path (s.get_struct_name ().get_segments (), 
Namespace::Types);
 
@@ -361,24 +365,34 @@ Late::visit (AST::StructExprStruct &s)
 void
 Late::visit (AST::StructExprStructBase &s)
 {
+  visit_outer_attrs (s);
+  visit_inner_attrs (s);
+  DefaultResolver::visit (s.get_struct_name ());
+  visit (s.get_struct_base ());
+
   auto resolved
 = ctx.resolve_path (s.get_struct_name ().get_segments (), 
Namespace::Types);
 
   ctx.map_usage (Usage (s.get_struct_name ().get_node_id ()),
 Definition (resolved->get_node_id ()));
-  DefaultResolver::visit (s);
 }
 
 void
 Late::visit (AST::StructExprStructFields &s)
 {
+  visit_outer_attrs (s);
+  visit_inner_attrs (s);
+  DefaultResolver::visit (s.get_struct_name ());
+  if (s.has_struct_base ())
+visit (s.get_struct_base ());
+  for (auto &field : s.get_fields ())
+visit (field);
+
   auto resolved
 = ctx.resolve_path (s.get_struct_name ().get_segments (), 
Namespace::Types);
 
   ctx.map_usage (Usage (s.get_struct_name ().get_node_id ()),
 Definition (resolved->get_node_id ()));
-
-  DefaultResolver::visit (s);
 }
 
 // needed because Late::visit (AST::GenericArg &) is non-virtual
diff --git a/gcc/testsuite/rust/compile/nr2/exclude 
b/gcc/testsuite/rust/compile/nr2/exclude
index 0252028fb8f7..6b8cf9801c5a 100644
--- a/gcc/testsuite/rust/compile/nr2/exclude
+++ b/gcc/testsuite/rust/compile/nr2/exclude
@@ -32,7 +32,6 @@ struct-expr-parse.rs
 undeclared_label.rs
 use_1.rs
 while_break_expr.rs
-issue-3139-2.rs
 issue-2905-2.rs
 issue-266.rs
 derive_clone_enum3.rs
@@ -57,8 +56,4 @@ torture/name_resolve1.rs
 torture/nested_struct1.rs
 torture/struct_init_3.rs
 torture/uninit-intrinsic-1.rs
-torture/generics1.rs
-torture/generics10.rs
-torture/generics13.rs
-torture/generics6.rs
 # please don't delete the trailing newline

[gcc r15-8828] gccrs: name-resolution: early: Remove overzealous overrides

[Arthur Cohen via Gcc-cvs]

https://gcc.gnu.org/g:d5eaa52c1ab061119a195450f5af62973fc6ed42

commit r15-8828-gd5eaa52c1ab061119a195450f5af62973fc6ed42
Author: Arthur Cohen 
Date:   Mon Feb 24 12:18:39 2025 +0100

gccrs: name-resolution: early: Remove overzealous overrides

Some empty overrides were incorrectly being set-up instead of using the 
correct behavior
from DefaultASTVisitor.

gcc/rust/ChangeLog:

* resolve/rust-early-name-resolver.cc: Remove definitions.
* resolve/rust-early-name-resolver.h: Remove declarations.

Diff:
---
 gcc/rust/resolve/rust-early-name-resolver.cc | 24 
 gcc/rust/resolve/rust-early-name-resolver.h  |  7 +--
 2 files changed, 1 insertion(+), 30 deletions(-)

diff --git a/gcc/rust/resolve/rust-early-name-resolver.cc 
b/gcc/rust/resolve/rust-early-name-resolver.cc
index 42a4a17090f7..a8df631200c7 100644
--- a/gcc/rust/resolve/rust-early-name-resolver.cc
+++ b/gcc/rust/resolve/rust-early-name-resolver.cc
@@ -560,30 +560,6 @@ EarlyNameResolver::visit (AST::TupleStructPattern &pattern)
   pattern.get_items ().accept_vis (*this);
 }
 
-void
-EarlyNameResolver::visit (AST::TraitBound &)
-{}
-
-void
-EarlyNameResolver::visit (AST::ImplTraitType &)
-{}
-
-void
-EarlyNameResolver::visit (AST::TraitObjectType &)
-{}
-
-void
-EarlyNameResolver::visit (AST::ParenthesisedType &)
-{}
-
-void
-EarlyNameResolver::visit (AST::ImplTraitTypeOneBound &)
-{}
-
-void
-EarlyNameResolver::visit (AST::TraitObjectTypeOneBound &)
-{}
-
 void
 EarlyNameResolver::visit (AST::TupleType &)
 {}
diff --git a/gcc/rust/resolve/rust-early-name-resolver.h 
b/gcc/rust/resolve/rust-early-name-resolver.h
index 48562df2bcdc..26fc84d52dc0 100644
--- a/gcc/rust/resolve/rust-early-name-resolver.h
+++ b/gcc/rust/resolve/rust-early-name-resolver.h
@@ -36,6 +36,7 @@ public:
 
 private:
   using AST::DefaultASTVisitor::visit;
+
   /**
* Execute a lambda within a scope. This is equivalent to calling
* `enter_scope` before your code and `exit_scope` after. This ensures
@@ -181,12 +182,6 @@ private:
   virtual void visit (AST::StructPatternFieldIdent &field);
   virtual void visit (AST::StructPattern &pattern);
   virtual void visit (AST::TupleStructPattern &pattern);
-  virtual void visit (AST::TraitBound &bound);
-  virtual void visit (AST::ImplTraitType &type);
-  virtual void visit (AST::TraitObjectType &type);
-  virtual void visit (AST::ParenthesisedType &type);
-  virtual void visit (AST::ImplTraitTypeOneBound &type);
-  virtual void visit (AST::TraitObjectTypeOneBound &type);
   virtual void visit (AST::TupleType &type);
   virtual void visit (AST::RawPointerType &type);
   virtual void visit (AST::ReferenceType &type);

[gcc r15-8850] gccrs: Remove finalize import visitor

[Arthur Cohen via Gcc-cvs]

https://gcc.gnu.org/g:d7b9a0f08638cd9ba67f0c07f2cd85a227bb3cae

commit r15-8850-gd7b9a0f08638cd9ba67f0c07f2cd85a227bb3cae
Author: Pierre-Emmanuel Patry 
Date:   Thu Mar 13 15:18:58 2025 +0100

gccrs: Remove finalize import visitor

This visitor is not used anymore.

gcc/rust/ChangeLog:

* resolve/rust-finalize-imports-2.0.cc 
(FinalizeImports::FinalizeImports):
Remove constructor.
(FinalizeImports::go): Remove function.
(FinalizeImports::visit): Likewise.
* resolve/rust-finalize-imports-2.0.h (class FinalizeImports): 
Remove
FinalizeImports class.

Signed-off-by: Pierre-Emmanuel Patry 

Diff:
---
 gcc/rust/resolve/rust-finalize-imports-2.0.cc | 18 -
 gcc/rust/resolve/rust-finalize-imports-2.0.h  | 57 ---
 2 files changed, 75 deletions(-)

diff --git a/gcc/rust/resolve/rust-finalize-imports-2.0.cc 
b/gcc/rust/resolve/rust-finalize-imports-2.0.cc
index bd6002a09f4d..b0e86512ac20 100644
--- a/gcc/rust/resolve/rust-finalize-imports-2.0.cc
+++ b/gcc/rust/resolve/rust-finalize-imports-2.0.cc
@@ -125,23 +125,5 @@ GlobbingVisitor::visit (AST::UseDeclaration &use)
   // Handle cycles ?
 }
 
-FinalizeImports::FinalizeImports (Early::ImportMappings &&data,
- TopLevel &toplevel,
- NameResolutionContext &ctx)
-  : DefaultResolver (ctx), data (std::move (data)), toplevel (toplevel),
-ctx (ctx)
-{}
-
-void
-FinalizeImports::go (AST::Crate &crate)
-{
-  for (auto &item : crate.items)
-item->accept_vis (*this);
-}
-
-void
-FinalizeImports::visit (AST::UseDeclaration &use)
-{}
-
 } // namespace Resolver2_0
 } // namespace Rust
diff --git a/gcc/rust/resolve/rust-finalize-imports-2.0.h 
b/gcc/rust/resolve/rust-finalize-imports-2.0.h
index a06fe538846a..d587a5e5c46e 100644
--- a/gcc/rust/resolve/rust-finalize-imports-2.0.h
+++ b/gcc/rust/resolve/rust-finalize-imports-2.0.h
@@ -49,62 +49,5 @@ private:
   NameResolutionContext &ctx;
 };
 
-// TODO: Fix documentation
-// How do we do that?
-//
-// We want to resolve in the EarlyNameResolver, but we want to declare in the
-// TopLevel Should the TopLevel declare stubs? How does rustc do it? How to do
-// that for globbing? Should we do globbing afterwards once we've declared all
-// the Uses*?
-//
-// Basically, for each use declare it in a separate map - in the
-// EarlyNameResolver resolve and fix the ForeverStack? Emptying the maps each
-// time?
-//
-// e.g. TopLevel builds a std::vector use_trees_to_resolve;
-// Early goes through and resolves the SimplePath, then replaces the NodeId 
with
-// the resolved one? Do we even need to do that?
-//
-// rustc just creates an empty definition for the use tree.
-//
-// What about globbing? std::vector globules;
-// Early goes through and visits the module's path and calls the
-// GlobbingVisitor?
-//
-// the file `imports.rs` goes through and *finalizes* imports. So we can
-// probably add a FinalizeImport pass after the TopLevel and the Early.
-// - TopLevel takes care of declaring these use trees
-// - Early takes care of resolving them to definition points
-// - Finalize takes care of mapping the use's definition point to the actual
-// definition point
-// - We need to work more on that last bit to know exactly what is being
-// inserted, but probably it's going to mutate the ForeverStack - is that okay?
-// - Oh actually maybe no!
-// - TopLevel creates a map of UseTrees with paths to resolve. This should
-// probably be an ImportKind enum or whatever
-// - Early resolves them, creates a map of SimplePath with the associated
-// definition: Map
-// - Finalizes visits all UseTrees and inserts the Definitions found for
-// each ImportKind - easy!
-// - yay!
-
-class FinalizeImports : DefaultResolver
-{
-public:
-  FinalizeImports (Early::ImportMappings &&data, TopLevel &toplevel,
-  NameResolutionContext &ctx);
-
-  void go (AST::Crate &crate);
-
-  void visit (AST::UseDeclaration &) override;
-
-private:
-  using AST::DefaultASTVisitor::visit;
-
-  Early::ImportMappings data;
-  TopLevel &toplevel;
-  NameResolutionContext &ctx;
-};
-
 } // namespace Resolver2_0
 } // namespace Rust

[gcc r15-8804] gccrs: nr2.0: Resolve paths which start with Self

[Arthur Cohen via Gcc-cvs]

https://gcc.gnu.org/g:0da1380d6637758977a467473a659a1a5b80c72a

commit r15-8804-g0da1380d6637758977a467473a659a1a5b80c72a
Author: Owen Avery 
Date:   Tue Feb 4 05:02:38 2025 -0500

gccrs: nr2.0: Resolve paths which start with Self

gcc/rust/ChangeLog:

* resolve/rust-forever-stack.hxx
(ForeverStack::find_starting_point): Be more careful about
applying ForeverStack::find_closest_module.
(ForeverStack::resolve_segments): Allow traversal into parent
nodes when not in a module node or root node, which
ForeverStack::find_starting_point previously made moot through
use of ForeverStack::find_closest_module. Also, when a child
node lookup fails when resolving in the type namespace, attempt
a rib lookup as a fallback.
* resolve/rust-late-name-resolver-2.0.cc
(Late::visit): Avoid throwing a resolution error for type paths
when the typechecker may be able to finish the resolution. Also,
throw an error when a resolution is ambiguous.

gcc/testsuite/ChangeLog:

* rust/compile/nr2/exclude: Remove entries.

Signed-off-by: Owen Avery 

Diff:
---
 gcc/rust/resolve/rust-forever-stack.hxx | 60 -
 gcc/rust/resolve/rust-late-name-resolver-2.0.cc | 25 ---
 gcc/testsuite/rust/compile/nr2/exclude  | 35 ---
 3 files changed, 56 insertions(+), 64 deletions(-)

diff --git a/gcc/rust/resolve/rust-forever-stack.hxx 
b/gcc/rust/resolve/rust-forever-stack.hxx
index b51da51948f8..d2020554f74f 100644
--- a/gcc/rust/resolve/rust-forever-stack.hxx
+++ b/gcc/rust/resolve/rust-forever-stack.hxx
@@ -381,13 +381,6 @@ ForeverStack::find_starting_point (
 {
   auto iterator = segments.begin ();
 
-  // If we need to do path segment resolution, then we start
-  // at the closest module. In order to resolve something like `foo::bar!()`, 
we
-  // need to get back to the surrounding module, and look for a child module
-  // named `foo`.
-  if (segments.size () > 1)
-starting_point = find_closest_module (starting_point);
-
   for (; !is_last (iterator, segments); iterator++)
 {
   auto &outer_seg = *iterator;
@@ -416,12 +409,14 @@ ForeverStack::find_starting_point (
   if (seg.is_lower_self_seg ())
{
  // insert segment resolution and exit
+ starting_point = find_closest_module (starting_point);
  insert_segment_resolution (outer_seg, starting_point.get ().id);
  iterator++;
  break;
}
   if (seg.is_super_path_seg ())
{
+ starting_point = find_closest_module (starting_point);
  if (starting_point.get ().is_root ())
{
  rust_error_at (seg.get_locus (), ErrorCode::E0433,
@@ -469,27 +464,48 @@ ForeverStack::resolve_segments (
 
   tl::optional::Node &> child = tl::nullopt;
 
-  for (auto &kv : current_node->children)
+  while (true)
{
- auto &link = kv.first;
+ for (auto &kv : current_node->children)
+   {
+ auto &link = kv.first;
+
+ if (link.path.map_or (
+   [&str] (Identifier path) {
+ auto &path_str = path.as_string ();
+ return str == path_str;
+   },
+   false))
+   {
+ child = kv.second;
+ break;
+   }
+   }
 
- if (link.path.map_or (
-   [&str] (Identifier path) {
- auto &path_str = path.as_string ();
- return str == path_str;
-   },
-   false))
+ if (child.has_value ())
{
- child = kv.second;
  break;
}
-   }
 
-  if (!child.has_value ())
-   {
- rust_error_at (seg.get_locus (), ErrorCode::E0433,
-"failed to resolve path segment %qs", str.c_str ());
- return tl::nullopt;
+ if (N == Namespace::Types)
+   {
+ auto rib_lookup = current_node->rib.get (seg.as_string ());
+ if (rib_lookup && !rib_lookup->is_ambiguous ())
+   {
+ insert_segment_resolution (outer_seg,
+rib_lookup->get_node_id ());
+ return tl::nullopt;
+   }
+   }
+
+ if (!is_start (iterator, segments)
+ || current_node->rib.kind == Rib::Kind::Module
+ || current_node->is_root ())
+   {
+ return tl::nullopt;
+   }
+
+ current_node = ¤t_node->parent.value ();
}
 
   current_node = &child.value ();
diff --git a/gcc/rust/resolve/rust-late-name-resolver-2.0.cc 
b/gcc/rust/resolve/rust-late-name-resolver-2.0.cc
index c134ca033368..7253deb42d9c 100644
--- a/gcc/rust/resolve/rust-late-name-r

[gcc r14-11443] i386: Add -mavx10.1 back with 512 bit alias

[Haochen Jiang via Gcc-cvs]

https://gcc.gnu.org/g:5ba6fdc5476d33c57f4751cae93054fdbc7211c0

commit r14-11443-g5ba6fdc5476d33c57f4751cae93054fdbc7211c0
Author: Haochen Jiang 
Date:   Mon Mar 24 15:51:16 2025 +0800

i386: Add -mavx10.1 back with 512 bit alias

When AVX10.1 options are added into GCC 14, E-core is supposed to
support up to 256 bit vector width, while P-core up to 512 bit vector
width. Therefore, we added avx10.1-256 and avx10.1-512 options into
compiler and alias avx10.1 to 256 bit for compatibility since there
will be real platforms with 256 bit only support.

However, all the future platforms will now support 512 bit vector width,
including P-core and E-core. Therefore, we could alias avx10.1 directly
to 512 bit. However, avx10.1 alias to 256 bit has been there in GCC 14.1
and GCC 14.2, so we have to raise a warning since GCC 14.3 for this
behavior change.

While backporting the patch from GCC 15, we choose to only warn when
users use -mavx10.1 option in order not to interrupt the usage of other
options since -mavx10.1-256/512 and -mevex512 will be dropped in GCC 16.
There is no need to warn them this early in GCC 14 to overwhelm users.

gcc/ChangeLog:

* common/config/i386/i386-isas.h: Add avx10.1.
* config/i386/i386-c.cc (ix86_target_macros_internal): Ditto.
* config/i386/i386-options.cc
(ix86_valid_target_attribute_inner_p): Ditto.
* config/i386/i386.opt: Ditto.
* config/i386/i386.opt.urls: Ditto.
* doc/extend.texi: Ditto.
* doc/sourcebuild.texi: Ditto.

Diff:
---
 gcc/common/config/i386/i386-isas.h | 1 +
 gcc/config/i386/i386-c.cc  | 5 +
 gcc/config/i386/i386-options.cc| 1 +
 gcc/config/i386/i386.opt   | 5 +
 gcc/config/i386/i386.opt.urls  | 3 +++
 gcc/doc/extend.texi| 6 ++
 gcc/doc/sourcebuild.texi   | 3 +++
 7 files changed, 20 insertions(+), 4 deletions(-)

diff --git a/gcc/common/config/i386/i386-isas.h 
b/gcc/common/config/i386/i386-isas.h
index 017c795e211d..cdbc188620ad 100644
--- a/gcc/common/config/i386/i386-isas.h
+++ b/gcc/common/config/i386/i386-isas.h
@@ -195,4 +195,5 @@ ISA_NAMES_TABLE_START
   ISA_NAMES_TABLE_ENTRY("usermsr", FEATURE_USER_MSR, P_NONE, "-musermsr")
   ISA_NAMES_TABLE_ENTRY("avx10.1-256", FEATURE_AVX10_1_256, P_AVX10_1_256, 
"-mavx10.1-256")
   ISA_NAMES_TABLE_ENTRY("avx10.1-512", FEATURE_AVX10_1_512, P_AVX10_1_512, 
"-mavx10.1-512")
+  ISA_NAMES_TABLE_ENTRY("avx10.1", FEATURE_AVX10_1_512, P_AVX10_1_512, 
"-mavx10.1")
 ISA_NAMES_TABLE_END
diff --git a/gcc/config/i386/i386-c.cc b/gcc/config/i386/i386-c.cc
index 07f4936ba910..0103b8543a15 100644
--- a/gcc/config/i386/i386-c.cc
+++ b/gcc/config/i386/i386-c.cc
@@ -743,10 +743,7 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag,
   if (isa_flag2 & OPTION_MASK_ISA2_USER_MSR)
 def_or_undef (parse_in, "__USER_MSR__");
   if (isa_flag2 & OPTION_MASK_ISA2_AVX10_1_256)
-{
-  def_or_undef (parse_in, "__AVX10_1_256__");
-  def_or_undef (parse_in, "__AVX10_1__");
-}
+def_or_undef (parse_in, "__AVX10_1_256__");
   if (isa_flag2 & OPTION_MASK_ISA2_AVX10_1_512)
 def_or_undef (parse_in, "__AVX10_1_512__");
   if (isa_flag2 & OPTION_MASK_ISA2_APX_F)
diff --git a/gcc/config/i386/i386-options.cc b/gcc/config/i386/i386-options.cc
index 11c6ddf0f440..57c83a9aa1c7 100644
--- a/gcc/config/i386/i386-options.cc
+++ b/gcc/config/i386/i386-options.cc
@@ -1137,6 +1137,7 @@ ix86_valid_target_attribute_inner_p (tree fndecl, tree 
args, char *p_strings[],
 IX86_ATTR_ISA ("usermsr", OPT_musermsr),
 IX86_ATTR_ISA ("avx10.1-256", OPT_mavx10_1_256),
 IX86_ATTR_ISA ("avx10.1-512", OPT_mavx10_1_512),
+IX86_ATTR_ISA ("avx10.1", OPT_mavx10_1_512),
 
 /* enum options */
 IX86_ATTR_ENUM ("fpmath=", OPT_mfpmath_),
diff --git a/gcc/config/i386/i386.opt b/gcc/config/i386/i386.opt
index f99c4e3ae5d9..df95963dd9f0 100644
--- a/gcc/config/i386/i386.opt
+++ b/gcc/config/i386/i386.opt
@@ -1380,3 +1380,8 @@ mavx10.1-512
 Target Mask(ISA2_AVX10_1_512) Var(ix86_isa_flags2) Save
 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2,
 and AVX10.1-512 built-in functions and code generation.
+
+mavx10.1
+Target Alias(mavx10.1-512) Warn(%<-mavx10.1%> is aliased to 512 bit since 
GCC14.3)
+Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2,
+and AVX10.1-512 built-in functions and code generation.
diff --git a/gcc/config/i386/i386.opt.urls b/gcc/config/i386/i386.opt.urls
index 3ed766350020..81c5bb9a9270 100644
--- a/gcc/config/i386/i386.opt.urls
+++ b/gcc/config/i386/i386.opt.urls
@@ -615,3 +615,6 @@ UrlSuffix(gcc/x86-Options.html#index-mavx10_002e1-256)
 mavx10.1-512
 UrlSuffix(gcc/x86-Options.html#index-mavx10_002e1-512)
 
+mavx10.1
+UrlSuffix(gcc/x86-Options.html#index-mavx10_002e1)
+
diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
index 8bd30bb2a468..27fefb30041e 100644

[gcc r15-8683] Doc: Add "Additional Numeric Types" sectioning to extend.texi [PR42270]

[Sandra Loosemore via Gcc-cvs]

https://gcc.gnu.org/g:557e809455a886e8f59f57e5c7b0a940e028d130

commit r15-8683-g557e809455a886e8f59f57e5c7b0a940e028d130
Author: Sandra Loosemore 
Date:   Thu Mar 13 03:43:04 2025 +

Doc: Add "Additional Numeric Types" sectioning to extend.texi [PR42270]

This is part of an incremental effort to make the chapter on GCC
extensions better organized by grouping/rearranging sections by topic.

gcc/ChangeLog
PR other/42270
* doc/extend.texi (Additional Numeric Types): New section.
(__int128): Make it a subsection of the above.
(Long Long): Likewise.
(Complex): Likewise.
(Floating Types): Likewise.
(Half-Precision): Likewise.
(Decimal Float): Likewise.
(Fixed-Point): Likewise.

Diff:
---
 gcc/doc/extend.texi | 94 ++---
 1 file changed, 53 insertions(+), 41 deletions(-)

diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
index b919df914648..92ab031fc904 100644
--- a/gcc/doc/extend.texi
+++ b/gcc/doc/extend.texi
@@ -31,14 +31,8 @@ extensions, accepted by GCC in C90 mode and in C++.
 * Constructing Calls::  Dispatching a call to another function.
 * Typeof::  @code{typeof}: referring to the type of an expression.
 * Conditionals::Omitting the middle operand of a @samp{?:} expression.
-* __int128::   128-bit integers---@code{__int128}.
-* Long Long::   Double-word integers---@code{long long int}.
-* Complex:: Data types for complex numbers.
-* Floating Types::  Additional Floating Types.
-* Half-Precision::  Half-Precision Floating Point.
-* Decimal Float::   Decimal Floating Types.
+* Additional Numeric Types::  Additional sizes and formats, plus complex 
numbers.
 * Hex Floats::  Hexadecimal floating-point constants.
-* Fixed-Point:: Fixed-Point Types.
 * Named Address Spaces::Named address spaces.
 * Zero Length:: Zero-length arrays.
 * Empty Structures::Structures with no members.
@@ -928,8 +922,26 @@ the operand in the middle would perform the side effect 
twice.  Omitting
 the middle operand uses the value already computed without the undesirable
 effects of recomputing it.
 
+@node Additional Numeric Types
+@section Additional Numeric Types
+
+GCC supports additional numeric types, including larger integer types,
+integer and floating-point complex types,
+additional floating-point sizes and formats, decimal floating types,
+and fixed-point types.
+
+@menu
+* __int128::   128-bit integers---@code{__int128}.
+* Long Long::   Double-word integers---@code{long long int}.
+* Complex:: Data types for complex numbers.
+* Floating Types::  Additional Floating Types.
+* Half-Precision::  Half-Precision Floating Point.
+* Decimal Float::   Decimal Floating Types.
+* Fixed-Point:: Fixed-Point Types.
+@end menu
+
 @node __int128
-@section 128-bit Integers
+@subsection 128-bit Integers
 @cindex @code{__int128} data types
 
 As an extension the integer scalar type @code{__int128} is supported for
@@ -940,7 +952,7 @@ support in GCC for expressing an integer constant of type 
@code{__int128}
 for targets with @code{long long} integer less than 128 bits wide.
 
 @node Long Long
-@section Double-Word Integers
+@subsection Double-Word Integers
 @cindex @code{long long} data types
 @cindex double-word arithmetic
 @cindex multiprecision arithmetic
@@ -972,7 +984,7 @@ Likewise, if the function expects @code{long long int} and 
you pass
 @code{int}.  The best way to avoid such problems is to use prototypes.
 
 @node Complex
-@section Complex Numbers
+@subsection Complex Numbers
 @cindex complex numbers
 @cindex @code{_Complex} keyword
 @cindex @code{__complex__} keyword
@@ -1083,7 +1095,7 @@ infinities, NaNs and negative zeros are involved.
 @enddefbuiltin
 
 @node Floating Types
-@section Additional Floating Types
+@subsection Additional Floating Types
 @cindex additional floating types
 @cindex @code{_Float@var{n}} data types
 @cindex @code{_Float@var{n}x} data types
@@ -1169,7 +1181,7 @@ typedef _Complex float __attribute__((mode(IC))) 
_Complex_ibm128;
 @end smallexample
 
 @node Half-Precision
-@section Half-Precision Floating Point
+@subsection Half-Precision Floating Point
 @cindex half-precision floating point
 @cindex @code{__fp16} data type
 @cindex @code{__Float16} data type
@@ -1240,7 +1252,7 @@ It is useful for code that does not have @code{_Float16} 
and runs on the x87
 FPU.
 
 @node Decimal Float
-@section Decimal Floating Types
+@subsection Decimal Floating Types
 @cindex decimal floating types
 @cindex @code{_Decimal32} data type
 @cindex @code{_Decimal64} data type
@@ -1292,35 +1304,8 @@ the technical report.
 Types @code{_Decimal32}, @code{_Decimal64}, and @code{_Decimal128}
 are supported by the DWARF debug information format.
 
-@node Hex Floats
-@section Hex Floats
-@cindex hex floats
-
-I

[gcc r15-8876] i386: Fix AVX10.2 sat cvt intrinsic.

[Hu via Gcc-cvs]

https://gcc.gnu.org/g:90ab42f92b876b74056db297557e8c3d51cdd773

commit r15-8876-g90ab42f92b876b74056db297557e8c3d51cdd773
Author: Hu, Lin1 
Date:   Tue Mar 25 09:24:59 2025 +0800

i386: Fix AVX10.2 sat cvt intrinsic.

The patch aims to modify the missed fixed for vcvttph2iubs's testcase.

gcc/testsuite/ChangeLog:

* gcc.target/i386/avx10_2-512-vcvttph2iubs-2.c: Modify testcase.

Diff:
---
 .../gcc.target/i386/avx10_2-512-vcvttph2iubs-2.c   | 28 +-
 1 file changed, 22 insertions(+), 6 deletions(-)

diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvttph2iubs-2.c 
b/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvttph2iubs-2.c
index d057c83831a0..1db5a891c216 100644
--- a/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvttph2iubs-2.c
+++ b/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvttph2iubs-2.c
@@ -9,6 +9,7 @@
 #endif
 #include "avx10-helper.h"
 #include 
+#include 
 
 #define SIZE (AVX512F_LEN / 16)
 #include "avx512f-mask-type.h"
@@ -37,7 +38,7 @@ TEST (void)
   UNION_TYPE (AVX512F_LEN, h) s;
   UNION_TYPE (AVX512F_LEN, i_w) res1, res2, res3;
   MASK_TYPE mask = MASK_VALUE;
-  short res_ref[SIZE] = { 0 };
+  short res_ref[SIZE] = { 0 }, res_ref2[SIZE] = { 0 };
   int i, sign = 1;
 
   for (i = 0; i < SIZE; i++)
@@ -54,11 +55,7 @@ TEST (void)
   res3.x = INTRINSIC (_maskz_ipcvtts_ph_epu8) (mask, s.x);
 
   CALC (s.a, res_ref);
-
-#if AVX512F_LEN == 512
-  res1.x = INTRINSIC (_ipcvtts_roundph_epu8) (s.x, 8);
-  res2.x = INTRINSIC (_mask_ipcvtts_roundph_epu8) (res2.x, mask, s.x, 8);
-  res3.x = INTRINSIC (_maskz_ipcvtts_roundph_epu8) (mask, s.x, 8);
+  memcpy(res_ref2, res_ref, sizeof(res_ref));
 
   if (UNION_CHECK (AVX512F_LEN, i_w) (res1, res_ref))
 abort ();
@@ -70,5 +67,24 @@ TEST (void)
   MASK_ZERO (i_w) (res_ref, mask, SIZE);
   if (UNION_CHECK (AVX512F_LEN, i_w) (res3, res_ref))
 abort ();
+
+#if AVX512F_LEN == 512
+  for (i = 0; i < SIZE; i++)
+res2.a[i] = DEFAULT_VALUE;
+
+  res1.x = INTRINSIC (_ipcvtts_roundph_epu8) (s.x, 8);
+  res2.x = INTRINSIC (_mask_ipcvtts_roundph_epu8) (res2.x, mask, s.x, 8);
+  res3.x = INTRINSIC (_maskz_ipcvtts_roundph_epu8) (mask, s.x, 8);
+
+  if (UNION_CHECK (AVX512F_LEN, i_w) (res1, res_ref2))
+abort ();
+
+  MASK_MERGE (i_w) (res_ref2, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_w) (res2, res_ref2))
+abort ();
+
+  MASK_ZERO (i_w) (res_ref2, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_w) (res3, res_ref2))
+abort ();
 #endif
 }

[gcc(refs/users/meissner/heads/work196-sha)] Add ChangeLog.sha and update REVISION.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:448ed3adc3d070cbe1694eb94f7c3f3f307f2c09

commit 448ed3adc3d070cbe1694eb94f7c3f3f307f2c09
Author: Michael Meissner 
Date:   Mon Mar 24 18:46:18 2025 -0400

Add ChangeLog.sha and update REVISION.

2025-03-24  Michael Meissner  

gcc/

* ChangeLog.sha: New file for branch.
* REVISION: Update.

Diff:
---
 gcc/ChangeLog.sha | 5 +
 gcc/REVISION  | 2 +-
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/gcc/ChangeLog.sha b/gcc/ChangeLog.sha
new file mode 100644
index ..a0b372938ef1
--- /dev/null
+++ b/gcc/ChangeLog.sha
@@ -0,0 +1,5 @@
+ Branch work196-sha, baseline 
+
+2025-03-24   Michael Meissner  
+
+   Clone branch
diff --git a/gcc/REVISION b/gcc/REVISION
index 4879f9dc9d4e..0f1987bb7cb2 100644
--- a/gcc/REVISION
+++ b/gcc/REVISION
@@ -1 +1 @@
-work196 branch
+work196-sha branch

[gcc(refs/users/meissner/heads/work196-dmf)] RFC2653-PowerPC: Add support for 1, 024 bit DMR registers.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:9caad038f8ae242277d0300a6b27003422eb7292

commit 9caad038f8ae242277d0300a6b27003422eb7292
Author: Michael Meissner 
Date:   Mon Mar 24 19:44:44 2025 -0400

RFC2653-PowerPC: Add support for 1,024 bit DMR registers.

This patch is a prelimianry patch to add the full 1,024 bit dense math 
register
(DMRs) for -mcpu=future.  The MMA 512-bit accumulators map onto the top of 
the
DMR register.

This patch only adds the new 1,024 bit register support.  It does not add
support for any instructions that need 1,024 bit registers instead of 512 
bit
registers.

I used the new mode 'TDOmode' to be the opaque mode used for 1,024 bit
registers.  The 'wD' constraint added in previous patches is used for these
registers.  I added support to do load and store of DMRs via the VSX 
registers,
since there are no load/store dense math instructions.  I added the new 
keyword
'__dmr' to create 1,024 bit types that can be loaded into DMRs.  At 
present, I
don't have aliases for __dmr512 and __dmr1024 that we've discussed 
internally.

The patches have been tested on both little and big endian systems.  Can I 
check
it into the master branch?

2025-03-08   Michael Meissner  

gcc/

* config/rs6000/mma.md (UNSPEC_DM_INSERT512_UPPER): New unspec.
(UNSPEC_DM_INSERT512_LOWER): Likewise.
(UNSPEC_DM_EXTRACT512): Likewise.
(UNSPEC_DMR_RELOAD_FROM_MEMORY): Likewise.
(UNSPEC_DMR_RELOAD_TO_MEMORY): Likewise.
(movtdo): New define_expand and define_insn_and_split to implement 
1,024
bit DMR registers.
(movtdo_insert512_upper): New insn.
(movtdo_insert512_lower): Likewise.
(movtdo_extract512): Likewise.
(reload_dmr_from_memory): Likewise.
(reload_dmr_to_memory): Likewise.
* config/rs6000/rs6000-builtin.cc (rs6000_type_string): Add DMR
support.
(rs6000_init_builtins): Add support for __dmr keyword.
* config/rs6000/rs6000-call.cc (rs6000_return_in_memory): Add 
support
for TDOmode.
(rs6000_function_arg): Likewise.
* config/rs6000/rs6000-modes.def (TDOmode): New mode.
* config/rs6000/rs6000.cc (rs6000_hard_regno_nregs_internal): Add
support for TDOmode.
(rs6000_hard_regno_mode_ok_uncached): Likewise.
(rs6000_hard_regno_mode_ok): Likewise.
(rs6000_modes_tieable_p): Likewise.
(rs6000_debug_reg_global): Likewise.
(rs6000_setup_reg_addr_masks): Likewise.
(rs6000_init_hard_regno_mode_ok): Add support for TDOmode.  Setup 
reload
hooks for DMR mode.
(reg_offset_addressing_ok_p): Add support for TDOmode.
(rs6000_emit_move): Likewise.
(rs6000_secondary_reload_simple_move): Likewise.
(rs6000_preferred_reload_class): Likewise.
(rs6000_secondary_reload_class): Likewise.
(rs6000_mangle_type): Add mangling for __dmr type.
(rs6000_dmr_register_move_cost): Add support for TDOmode.
(rs6000_split_multireg_move): Likewise.
(rs6000_invalid_conversion): Likewise.
* config/rs6000/rs6000.h (VECTOR_ALIGNMENT_P): Add TDOmode.
(enum rs6000_builtin_type_index): Add DMR type nodes.
(dmr_type_node): Likewise.
(ptr_dmr_type_node): Likewise.

gcc/testsuite/

* gcc.target/powerpc/dm-1024bit.c: New test.
* lib/target-supports.exp (check_effective_target_ppc_dmr_ok): New
target test.

Diff:
---
 gcc/config/rs6000/mma.md  | 154 ++
 gcc/config/rs6000/rs6000-builtin.cc   |  17 +++
 gcc/config/rs6000/rs6000-call.cc  |  10 +-
 gcc/config/rs6000/rs6000-modes.def|   4 +
 gcc/config/rs6000/rs6000.cc   | 101 -
 gcc/config/rs6000/rs6000.h|   6 +-
 gcc/testsuite/gcc.target/powerpc/dm-1024bit.c |  63 +++
 gcc/testsuite/lib/target-supports.exp |  35 ++
 8 files changed, 356 insertions(+), 34 deletions(-)

diff --git a/gcc/config/rs6000/mma.md b/gcc/config/rs6000/mma.md
index 683d2398ef90..1420fadd4355 100644
--- a/gcc/config/rs6000/mma.md
+++ b/gcc/config/rs6000/mma.md
@@ -92,6 +92,11 @@
UNSPEC_MMA_XXMFACC
UNSPEC_MMA_XXMTACC
UNSPEC_MMA_DMSETDMRZ
+   UNSPEC_DM_INSERT512_UPPER
+   UNSPEC_DM_INSERT512_LOWER
+   UNSPEC_DM_EXTRACT512
+   UNSPEC_DMR_RELOAD_FROM_MEMORY
+   UNSPEC_DMR_RELOAD_TO_MEMORY
   ])
 
 (define_c_enum "unspecv"
@@ -742,3 +747,152 @@
   " %A0,%x2,%x3,%4,%5,%6"
   [(set_attr "type" "mma")
(set_attr "prefixed" "yes")])
+
+;; TDOmode (__dmr keyword for 1,024 bit registers).
+(define_expand "movtdo"
+  [(set (match_operand:TDO 0 "nonimmediate_operand")
+   (match_operand:

[gcc(refs/users/meissner/heads/work196-bugs)] Add ChangeLog.bugs and update REVISION.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:5e4fe73897f418161a5302d7567d8c293cbcc681

commit 5e4fe73897f418161a5302d7567d8c293cbcc681
Author: Michael Meissner 
Date:   Mon Mar 24 18:44:16 2025 -0400

Add ChangeLog.bugs and update REVISION.

2025-03-24  Michael Meissner  

gcc/

* ChangeLog.bugs: New file for branch.
* REVISION: Update.

Diff:
---
 gcc/ChangeLog.bugs | 5 +
 gcc/REVISION   | 2 +-
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/gcc/ChangeLog.bugs b/gcc/ChangeLog.bugs
new file mode 100644
index ..d33fbedd3542
--- /dev/null
+++ b/gcc/ChangeLog.bugs
@@ -0,0 +1,5 @@
+ Branch work196-bugs, baseline 
+
+2025-03-24   Michael Meissner  
+
+   Clone branch
diff --git a/gcc/REVISION b/gcc/REVISION
index 4879f9dc9d4e..e333906086e6 100644
--- a/gcc/REVISION
+++ b/gcc/REVISION
@@ -1 +1 @@
-work196 branch
+work196-bugs branch

[gcc/meissner/heads/work196-sha] (15 commits) Merge commit 'refs/users/meissner/heads/work196-sha' of git

[Michael Meissner via Gcc-cvs]

The branch 'meissner/heads/work196-sha' was updated to point to:

 5605e60391bd... Merge commit 'refs/users/meissner/heads/work196-sha' of git

It previously pointed to:

 448ed3adc3d0... Add ChangeLog.sha and update REVISION.

Diff:

Summary of changes (added commits):
---

  5605e60... Merge commit 'refs/users/meissner/heads/work196-sha' of git
  e76a94b... Add ChangeLog.sha and update REVISION.
  473e86a... Update ChangeLog.* (*)
  16afa73... Use architecture flags for defining _ARCH_PWR macros. (*)
  36b4a47... Add rs6000 architecture masks. (*)
  06745b4... Do not allow -mvsx to boost processor to power7. (*)
  7de48d5... Use vector pair load/store for memcpy with -mcpu=future (*)
  a2084f2... Add -mcpu=future tests. (*)
  ab39407... Add -mcpu=future tuning support. (*)
  81c30dc... Add support for -mcpu=future (*)
  c91f9a8... Change TARGET_MODULO to TARGET_POWER9. (*)
  54e6fc5... Change TARGET_POPCNTD to TARGET_POWER7. (*)
  66fe8ea... Change TARGET_CMPB to TARGET_POWER6. (*)
  afa2141... Change TARGET_FPRND to TARGET_POWER5X. (*)
  a7fbb58... Change TARGET_POPCNTB to TARGET_POWER5. (*)

(*) This commit already exists in another branch.
Because the reference `refs/users/meissner/heads/work196-sha' matches
your hooks.email-new-commits-only configuration,
no separate email is sent for this commit.

[gcc(refs/users/meissner/heads/work196)] Add ChangeLog.meissner and REVISION.

[Michael Meissner via Libstdc++-cvs]

https://gcc.gnu.org/g:bc61a0720b30cb3973f246f1857ca6855db9e4ab

commit bc61a0720b30cb3973f246f1857ca6855db9e4ab
Author: Michael Meissner 
Date:   Mon Mar 24 18:41:24 2025 -0400

Add ChangeLog.meissner and REVISION.

2025-03-24  Michael Meissner  

gcc/

* REVISION: New file for branch.
* ChangeLog.meissner: New file.

gcc/c-family/

* ChangeLog.meissner: New file.

gcc/c/

* ChangeLog.meissner: New file.

gcc/cp/

* ChangeLog.meissner: New file.

gcc/fortran/

* ChangeLog.meissner: New file.

gcc/testsuite/

* ChangeLog.meissner: New file.

libgcc/

* ChangeLog.meissner: New file.

Diff:
---
 gcc/ChangeLog.meissner   | 5 +
 gcc/REVISION | 1 +
 gcc/c-family/ChangeLog.meissner  | 5 +
 gcc/c/ChangeLog.meissner | 5 +
 gcc/cp/ChangeLog.meissner| 5 +
 gcc/fortran/ChangeLog.meissner   | 5 +
 gcc/testsuite/ChangeLog.meissner | 5 +
 libgcc/ChangeLog.meissner| 5 +
 libstdc++-v3/ChangeLog.meissner  | 5 +
 9 files changed, 41 insertions(+)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
new file mode 100644
index ..6e5f69d44be4
--- /dev/null
+++ b/gcc/ChangeLog.meissner
@@ -0,0 +1,5 @@
+ Branch work196, baseline 
+
+2025-03-24   Michael Meissner  
+
+   Clone branch
diff --git a/gcc/REVISION b/gcc/REVISION
new file mode 100644
index ..4879f9dc9d4e
--- /dev/null
+++ b/gcc/REVISION
@@ -0,0 +1 @@
+work196 branch
diff --git a/gcc/c-family/ChangeLog.meissner b/gcc/c-family/ChangeLog.meissner
new file mode 100644
index ..6e5f69d44be4
--- /dev/null
+++ b/gcc/c-family/ChangeLog.meissner
@@ -0,0 +1,5 @@
+ Branch work196, baseline 
+
+2025-03-24   Michael Meissner  
+
+   Clone branch
diff --git a/gcc/c/ChangeLog.meissner b/gcc/c/ChangeLog.meissner
new file mode 100644
index ..6e5f69d44be4
--- /dev/null
+++ b/gcc/c/ChangeLog.meissner
@@ -0,0 +1,5 @@
+ Branch work196, baseline 
+
+2025-03-24   Michael Meissner  
+
+   Clone branch
diff --git a/gcc/cp/ChangeLog.meissner b/gcc/cp/ChangeLog.meissner
new file mode 100644
index ..6e5f69d44be4
--- /dev/null
+++ b/gcc/cp/ChangeLog.meissner
@@ -0,0 +1,5 @@
+ Branch work196, baseline 
+
+2025-03-24   Michael Meissner  
+
+   Clone branch
diff --git a/gcc/fortran/ChangeLog.meissner b/gcc/fortran/ChangeLog.meissner
new file mode 100644
index ..6e5f69d44be4
--- /dev/null
+++ b/gcc/fortran/ChangeLog.meissner
@@ -0,0 +1,5 @@
+ Branch work196, baseline 
+
+2025-03-24   Michael Meissner  
+
+   Clone branch
diff --git a/gcc/testsuite/ChangeLog.meissner b/gcc/testsuite/ChangeLog.meissner
new file mode 100644
index ..6e5f69d44be4
--- /dev/null
+++ b/gcc/testsuite/ChangeLog.meissner
@@ -0,0 +1,5 @@
+ Branch work196, baseline 
+
+2025-03-24   Michael Meissner  
+
+   Clone branch
diff --git a/libgcc/ChangeLog.meissner b/libgcc/ChangeLog.meissner
new file mode 100644
index ..6e5f69d44be4
--- /dev/null
+++ b/libgcc/ChangeLog.meissner
@@ -0,0 +1,5 @@
+ Branch work196, baseline 
+
+2025-03-24   Michael Meissner  
+
+   Clone branch
diff --git a/libstdc++-v3/ChangeLog.meissner b/libstdc++-v3/ChangeLog.meissner
new file mode 100644
index ..6e5f69d44be4
--- /dev/null
+++ b/libstdc++-v3/ChangeLog.meissner
@@ -0,0 +1,5 @@
+ Branch work196, baseline 
+
+2025-03-24   Michael Meissner  
+
+   Clone branch

[gcc(refs/users/meissner/heads/work196)] Add -mcpu=future tests.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:a2084f2c8980d40867c307ac2792d32c8c0d87c7

commit a2084f2c8980d40867c307ac2792d32c8c0d87c7
Author: Michael Meissner 
Date:   Mon Mar 24 19:13:39 2025 -0400

Add -mcpu=future tests.

This patch adds simple tests for -mcpu=future.

2025-03-24  Michael Meissner  

gcc/testsuite/

* gcc.target/powerpc/future-1.c: New test.
* gcc.target/powerpc/future-2.c: Likewise.

Diff:
---
 gcc/testsuite/gcc.target/powerpc/future-1.c | 13 +
 gcc/testsuite/gcc.target/powerpc/future-2.c | 24 
 2 files changed, 37 insertions(+)

diff --git a/gcc/testsuite/gcc.target/powerpc/future-1.c 
b/gcc/testsuite/gcc.target/powerpc/future-1.c
new file mode 100644
index ..f1b940d7bebf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/future-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mdejagnu-cpu=future -O2" } */
+
+/* Basic check to see if the compiler supports -mcpu=future and if it defines
+   _ARCH_PWR11.  */
+
+#ifndef _ARCH_FUTURE
+#error "-mcpu=future is not supported"
+#endif
+
+void foo (void)
+{
+}
diff --git a/gcc/testsuite/gcc.target/powerpc/future-2.c 
b/gcc/testsuite/gcc.target/powerpc/future-2.c
new file mode 100644
index ..5552cefa3c2e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/future-2.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+/* Check if we can set the future target via a target attribute.  */
+
+__attribute__((__target__("cpu=power9")))
+void foo_p9 (void)
+{
+}
+
+__attribute__((__target__("cpu=power10")))
+void foo_p10 (void)
+{
+}
+
+__attribute__((__target__("cpu=power11")))
+void foo_p11 (void)
+{
+}
+
+__attribute__((__target__("cpu=future")))
+void foo_future (void)
+{
+}

[gcc(refs/users/meissner/heads/work196)] Add -mcpu=future tuning support.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:ab39407f193fc172af82ea31622d83f3e747f9af

commit ab39407f193fc172af82ea31622d83f3e747f9af
Author: Michael Meissner 
Date:   Mon Mar 24 19:12:16 2025 -0400

Add -mcpu=future tuning support.

This patch makes -mtune=future use the same tuning decision as 
-mtune=power11.

2025-03-24  Michael Meissner  

gcc/

* config/rs6000/power10.md (all reservations): Add future as an
alterntive to power10 and power11.

Diff:
---
 gcc/config/rs6000/power10.md | 145 ++-
 1 file changed, 73 insertions(+), 72 deletions(-)

diff --git a/gcc/config/rs6000/power10.md b/gcc/config/rs6000/power10.md
index fd31b16b3314..bdd7e58145ba 100644
--- a/gcc/config/rs6000/power10.md
+++ b/gcc/config/rs6000/power10.md
@@ -1,4 +1,5 @@
-;; Scheduling description for the IBM Power10 and Power11 processors.
+;; Scheduling description for the IBM Power10, Power11, and
+;; potential future processors.
 ;; Copyright (C) 2020-2025 Free Software Foundation, Inc.
 ;;
 ;; Contributed by Pat Haugen (pthau...@us.ibm.com).
@@ -97,12 +98,12 @@
(eq_attr "update" "no")
(eq_attr "size" "!128")
(eq_attr "prefixed" "no")
-   (eq_attr "cpu" "power10,power11"))
+   (eq_attr "cpu" "power10,power11,future"))
   "DU_any_power10,LU_power10")
 
 (define_insn_reservation "power10-fused-load" 4
   (and (eq_attr "type" "fused_load_cmpi,fused_addis_load,fused_load_load")
-   (eq_attr "cpu" "power10,power11"))
+   (eq_attr "cpu" "power10,power11,future"))
   "DU_even_power10,LU_power10")
 
 (define_insn_reservation "power10-prefixed-load" 4
@@ -110,13 +111,13 @@
(eq_attr "update" "no")
(eq_attr "size" "!128")
(eq_attr "prefixed" "yes")
-   (eq_attr "cpu" "power10,power11"))
+   (eq_attr "cpu" "power10,power11,future"))
   "DU_even_power10,LU_power10")
 
 (define_insn_reservation "power10-load-update" 4
   (and (eq_attr "type" "load")
(eq_attr "update" "yes")
-   (eq_attr "cpu" "power10,power11"))
+   (eq_attr "cpu" "power10,power11,future"))
   "DU_even_power10,LU_power10+SXU_power10")
 
 (define_insn_reservation "power10-fpload-double" 4
@@ -124,7 +125,7 @@
(eq_attr "update" "no")
(eq_attr "size" "64")
(eq_attr "prefixed" "no")
-   (eq_attr "cpu" "power10,power11"))
+   (eq_attr "cpu" "power10,power11,future"))
   "DU_any_power10,LU_power10")
 
 (define_insn_reservation "power10-prefixed-fpload-double" 4
@@ -132,14 +133,14 @@
(eq_attr "update" "no")
(eq_attr "size" "64")
(eq_attr "prefixed" "yes")
-   (eq_attr "cpu" "power10,power11"))
+   (eq_attr "cpu" "power10,power11,future"))
   "DU_even_power10,LU_power10")
 
 (define_insn_reservation "power10-fpload-update-double" 4
   (and (eq_attr "type" "fpload")
(eq_attr "update" "yes")
(eq_attr "size" "64")
-   (eq_attr "cpu" "power10,power11"))
+   (eq_attr "cpu" "power10,power11,future"))
   "DU_even_power10,LU_power10+SXU_power10")
 
 ; SFmode loads are cracked and have additional 3 cycles over DFmode
@@ -148,27 +149,27 @@
   (and (eq_attr "type" "fpload")
(eq_attr "update" "no")
(eq_attr "size" "32")
-   (eq_attr "cpu" "power10,power11"))
+   (eq_attr "cpu" "power10,power11,future"))
   "DU_even_power10,LU_power10")
 
 (define_insn_reservation "power10-fpload-update-single" 7
   (and (eq_attr "type" "fpload")
(eq_attr "update" "yes")
(eq_attr "size" "32")
-   (eq_attr "cpu" "power10,power11"))
+   (eq_attr "cpu" "power10,power11,future"))
   "DU_even_power10,LU_power10+SXU_power10")
 
 (define_insn_reservation "power10-vecload" 4
   (and (eq_attr "type" "vecload")
(eq_attr "size" "!256")
-   (eq_attr "cpu" "power10,power11"))
+   (eq_attr "cpu" "power10,power11,future"))
   "DU_any_power10,LU_power10")
 
 ; lxvp
 (define_insn_reservation "power10-vecload-pair" 4
   (and (eq_attr "type" "vecload")
(eq_attr "size" "256")
-   (eq_attr "cpu" "power10,power11"))
+   (eq_attr "cpu" "power10,power11,future"))
   "DU_even_power10,LU_power10+SXU_power10")
 
 ; Store Unit
@@ -178,12 +179,12 @@
(eq_attr "prefixed" "no")
(eq_attr "size" "!128")
(eq_attr "size" "!256")
-   (eq_attr "cpu" "power10,power11"))
+   (eq_attr "cpu" "power10,power11,future"))
   "DU_any_power10,STU_power10")
 
 (define_insn_reservation "power10-fused-store" 0
   (and (eq_attr "type" "fused_store_store")
-   (eq_attr "cpu" "power10,power11"))
+   (eq_attr "cpu" "power10,power11,future"))
   "DU_even_power10,STU_power10")
 
 (define_insn_reservation "power10-prefixed-store" 0
@@ -191,52 +192,52 @@
(eq_attr "prefixed" "yes")
(eq_attr "size" "!128")
(eq_attr "size" "!256")
-   (eq_attr "cpu" "power10,power11"))
+   (eq_attr "cpu" "power10,power11,future"))
   "DU_even_power10,STU_power10")
 
 ; Update forms have 2 cycle lat

[gcc(refs/users/meissner/heads/work196)] Use vector pair load/store for memcpy with -mcpu=future

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:7de48d5d9068983f49bc67ec8408fca3a1dd7617

commit 7de48d5d9068983f49bc67ec8408fca3a1dd7617
Author: Michael Meissner 
Date:   Mon Mar 24 19:14:35 2025 -0400

Use vector pair load/store for memcpy with -mcpu=future

In the development for the power10 processor, GCC did not enable using the 
load
vector pair and store vector pair instructions when optimizing things like
memory copy.  This patch enables using those instructions if -mcpu=future is
used.

2025-03-24  Michael Meissner  

gcc/

* config/rs6000/rs6000-cpus.def (ISA_FUTURE_MASKS_SERVER): Enable 
using
load vector pair and store vector pair instructions for memory copy
operations.
(POWERPC_MASKS): Make the bit for enabling using load vector pair 
and
store vector pair operations set and reset when the PowerPC 
processor is
changed.
* gcc/config/rs6000/rs6000.cc (rs6000_machine_from_flags): Disable
-mblock-ops-vector-pair from influcing .machine selection.

gcc/testsuite/

* gcc.target/powerpc/future-3.c: New test.

Diff:
---
 gcc/config/rs6000/rs6000-cpus.def   |  4 +++-
 gcc/config/rs6000/rs6000.cc |  2 +-
 gcc/testsuite/gcc.target/powerpc/future-3.c | 22 ++
 3 files changed, 26 insertions(+), 2 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-cpus.def 
b/gcc/config/rs6000/rs6000-cpus.def
index 228d0b5e7b54..063591f5c094 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -84,7 +84,8 @@
  | OPTION_MASK_POWER11)
 
 #define FUTURE_MASKS_SERVER(POWER11_MASKS_SERVER   \
-| OPTION_MASK_FUTURE)
+| OPTION_MASK_FUTURE   \
+| OPTION_MASK_BLOCK_OPS_VECTOR_PAIR)
 
 /* Flags that need to be turned off if -mno-vsx.  */
 #define OTHER_VSX_VECTOR_MASKS (OPTION_MASK_EFFICIENT_UNALIGNED_VSX\
@@ -114,6 +115,7 @@
 
 /* Mask of all options to set the default isa flags based on -mcpu=.  */
 #define POWERPC_MASKS  (OPTION_MASK_ALTIVEC\
+| OPTION_MASK_BLOCK_OPS_VECTOR_PAIR\
 | OPTION_MASK_CMPB \
 | OPTION_MASK_CRYPTO   \
 | OPTION_MASK_DFP  \
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 4cea1775f110..011f67d290e9 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -5908,7 +5908,7 @@ rs6000_machine_from_flags (void)
 
   /* Disable the flags that should never influence the .machine selection.  */
   flags &= ~(OPTION_MASK_PPC_GFXOPT | OPTION_MASK_PPC_GPOPT | OPTION_MASK_ISEL
-| OPTION_MASK_ALTIVEC);
+| OPTION_MASK_ALTIVEC | OPTION_MASK_BLOCK_OPS_VECTOR_PAIR);
 
   if ((flags & (FUTURE_MASKS_SERVER & ~ISA_3_1_MASKS_SERVER)) != 0)
 return "future";
diff --git a/gcc/testsuite/gcc.target/powerpc/future-3.c 
b/gcc/testsuite/gcc.target/powerpc/future-3.c
new file mode 100644
index ..afa8b96d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/future-3.c
@@ -0,0 +1,22 @@
+/* 32-bit doesn't generate vector pair instructions.  */
+/* { dg-do compile { target lp64 } } */
+/* { dg-options "-mdejagnu-cpu=future -O2" } */
+
+/* Test to see that memcpy will use load/store vector pair with
+   -mcpu=future.  */
+
+#ifndef SIZE
+#define SIZE 4
+#endif
+
+extern vector double to[SIZE], from[SIZE];
+
+void
+copy (void)
+{
+  __builtin_memcpy (to, from, sizeof (to));
+  return;
+}
+
+/* { dg-final { scan-assembler {\mlxvpx?\M}  } } */
+/* { dg-final { scan-assembler {\mstxvpx?\M} } } */

[gcc(refs/users/meissner/heads/work196)] Change TARGET_FPRND to TARGET_POWER5X.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:afa21416e1ccc0c9da3e3738fb6cc09950d44862

commit afa21416e1ccc0c9da3e3738fb6cc09950d44862
Author: Michael Meissner 
Date:   Mon Mar 24 19:06:56 2025 -0400

Change TARGET_FPRND to TARGET_POWER5X.

This patch changes TARGET_POWER5X to TARGET_POWER5.  The -mfprnd switch is 
not
being changed, just the name of the macros used to determine if the PowerPC
processor supports ISA 2.4 (Power5x).

2025-03-24  Michael Meissner  

gcc/

* gcc/config/rs6000/rs6000.cc (rs6000_option_override_internal):
Change TARGET_FPRND to TARGET_POWER5X.
* gcc/config/rs6000/rs6000.h (TARGET_POWERP5X): New macro.
* gcc/config/rs6000/rs6000.md (fmod3): Change TARGET_FPRND to
TARGET_POWER5X.
(remainder3): Likewise.
(fctiwuz_): Likewise.
(ceil2): Likewise.
(floor2): Likewise.
(round2): Likewise.

Diff:
---
 gcc/config/rs6000/rs6000.cc |  4 ++--
 gcc/config/rs6000/rs6000.h  |  1 +
 gcc/config/rs6000/rs6000.md | 14 +++---
 3 files changed, 10 insertions(+), 9 deletions(-)

diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index a5ed93702494..b2811d963fcf 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -3924,7 +3924,7 @@ rs6000_option_override_internal (bool global_init_p)
 rs6000_isa_flags |= (ISA_2_5_MASKS_SERVER & ~ignore_masks);
   else if (TARGET_CMPB)
 rs6000_isa_flags |= (ISA_2_5_MASKS_EMBEDDED & ~ignore_masks);
-  else if (TARGET_FPRND)
+  else if (TARGET_POWER5X)
 rs6000_isa_flags |= (ISA_2_4_MASKS & ~ignore_masks);
   else if (TARGET_POWER5)
 rs6000_isa_flags |= (ISA_2_2_MASKS & ~ignore_masks);
@@ -3951,7 +3951,7 @@ rs6000_option_override_internal (bool global_init_p)
   rs6000_isa_flags &= ~OPTION_MASK_CRYPTO;
 }
 
-  if (!TARGET_FPRND && TARGET_VSX)
+  if (!TARGET_POWER5X && TARGET_VSX)
 {
   if (rs6000_isa_flags_explicit & OPTION_MASK_FPRND)
/* TARGET_VSX = 1 implies Power 7 and newer */
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index d9a0ffe9f5b2..3794e3c0658d 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -501,6 +501,7 @@ extern int rs6000_vector_align[];
 
 /* Convert ISA bits like POPCNTB to PowerPC processors like POWER5.  */
 #define TARGET_POWER5  TARGET_POPCNTB
+#define TARGET_POWER5X TARGET_FPRND
 
 /* In switching from using target_flags to using rs6000_isa_flags, the options
machinery creates OPTION_MASK_ instead of MASK_.  The MASK_
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index c5bd273be8b3..045ce22a03c8 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -5171,7 +5171,7 @@
(use (match_operand:SFDF 1 "gpc_reg_operand"))
(use (match_operand:SFDF 2 "gpc_reg_operand"))]
   "TARGET_HARD_FLOAT
-   && TARGET_FPRND
+   && TARGET_POWER5X
&& flag_unsafe_math_optimizations"
 {
   rtx div = gen_reg_rtx (mode);
@@ -5189,7 +5189,7 @@
(use (match_operand:SFDF 1 "gpc_reg_operand"))
(use (match_operand:SFDF 2 "gpc_reg_operand"))]
   "TARGET_HARD_FLOAT
-   && TARGET_FPRND
+   && TARGET_POWER5X
&& flag_unsafe_math_optimizations"
 {
   rtx div = gen_reg_rtx (mode);
@@ -6689,7 +6689,7 @@
 (define_insn "*friz"
   [(set (match_operand:DF 0 "gpc_reg_operand" "=d,wa")
(float:DF (fix:DI (match_operand:DF 1 "gpc_reg_operand" "d,wa"]
-  "TARGET_HARD_FLOAT && TARGET_FPRND
+  "TARGET_HARD_FLOAT && TARGET_POWER5X
&& flag_unsafe_math_optimizations && !flag_trapping_math && TARGET_FRIZ"
   "@
friz %0,%1
@@ -6817,7 +6817,7 @@
   [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa")
(unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "d,wa")]
 UNSPEC_FRIZ))]
-  "TARGET_HARD_FLOAT && TARGET_FPRND"
+  "TARGET_HARD_FLOAT && TARGET_POWER5X"
   "@
friz %0,%1
xsrdpiz %x0,%x1"
@@ -6827,7 +6827,7 @@
   [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa")
(unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "d,wa")]
 UNSPEC_FRIP))]
-  "TARGET_HARD_FLOAT && TARGET_FPRND"
+  "TARGET_HARD_FLOAT && TARGET_POWER5X"
   "@
frip %0,%1
xsrdpip %x0,%x1"
@@ -6837,7 +6837,7 @@
   [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa")
(unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "d,wa")]
 UNSPEC_FRIM))]
-  "TARGET_HARD_FLOAT && TARGET_FPRND"
+  "TARGET_HARD_FLOAT && TARGET_POWER5X"
   "@
frim %0,%1
xsrdpim %x0,%x1"
@@ -6848,7 +6848,7 @@
   [(set (match_operand:SFDF 0 "gpc_reg_operand" "=")
(unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "")]
 UNSPEC_FRIN))]
-  "TARGET_HARD_FLOAT && TARGET_FPRND"
+  "TARGET_HARD_FLOAT && TARGET_POWER5X"
   "frin %0,%1"
   [(set_attr "type" "fp")])

[gcc(refs/users/meissner/heads/work196)] Use architecture flags for defining _ARCH_PWR macros.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:16afa7383548689c32a94b2e96730fb589d3f2a1

commit 16afa7383548689c32a94b2e96730fb589d3f2a1
Author: Michael Meissner 
Date:   Mon Mar 24 19:19:07 2025 -0400

Use architecture flags for defining _ARCH_PWR macros.

For the newer architectures, this patch changes GCC to define the 
_ARCH_PWR
macros using the new architecture flags instead of relying on isa options 
like
-mpower10.

The -mpower8-internal, -mpower10, -mpower11, and -mfuture options were 
removed.
The -mpower11 and -mfuture options were removed completely, since they were 
just
added in GCC 15. The other two options were marked as WarnRemoved, and the
various ISA bits were removed.

TARGET_POWER8, TARGET_POWER10, TARGET_POWER11, and TARGET_FUTURE were 
re-defined
to use the architeture bits instead of the ISA bits.

There are other internal isa bits that aren't removed with this patch 
because
the built-in function support uses those bits.

I have built both big endian and little endian bootstrap compilers and there
were no regressions.

Can I install this patch on the GCC 15 trunk?

2025-03-24  Michael Meissner  

gcc/

* config/rs6000/rs6000-c.cc (rs6000_target_modify_macros) Add 
support to
use architecture flags instead of ISA flags for setting most of the
_ARCH_PWR* macros.
(rs6000_cpu_cpp_builtins): Update rs6000_target_modify_macros call.
* config/rs6000/rs6000-cpus.def (ISA_2_7_MASKS_SERVER): Remove
OPTION_MASK_POWER8.
(ISA_3_1_MASKS_SERVER): Remove OPTION_MASK_POWER10.
(POWER11_MASKS_SERVER): Remove OPTION_MASK_POWER11.
(FUTURE_MASKS_SERVER): Remove OPTION_MASK_FUTURE.
(POWERPC_MASKS): Remove OPTION_MASK_POWER8, OPTION_MASK_POWER10,
OPTION_MASK_POWER11, and OPTION_MASK_FUTURE.
* config/rs6000/rs6000-protos.h (rs6000_target_modify_macros): 
Update
declaration.
(rs6000_target_modify_macros_ptr): Likewise.
* config/rs6000/rs6000.cc (rs6000_target_modify_macros_ptr): 
Likewise.
(rs6000_option_override_internal): Use architecture flags instead 
of ISA
flags.
(rs6000_opt_masks): Remove -mpower10, -mpower11, and -mfuture which 
are
no longer in the ISA flags.
(rs6000_pragma_target_parse): Use architecture flags as well as ISA
flags.
* config/rs6000/rs6000.h (TARGET_POWER5): Redefine to use 
architecture
flags.
(TARGET_POWER5X): Likewise.
(TARGET_POWER6): Likewise.
(TARGET_POWER7): Likewise.
(TARGET_POWER8): Likewise.
(TARGET_POWER9): Likewise.
(TARGET_POWER10): New macro.
(TARGET_POWER11): Likewise.
(TARGET_FUTURE): Likewise.
* config/rs6000/rs6000.opt (-mpower8-internal): Remove ISA flag 
bits.
(-mpower10): Likewise.
(-mpower11): Likewise.
(-mfuture): Likewise.

Diff:
---
 gcc/config/rs6000/rs6000-c.cc | 29 -
 gcc/config/rs6000/rs6000-cpus.def | 10 +-
 gcc/config/rs6000/rs6000-protos.h |  5 +++--
 gcc/config/rs6000/rs6000.cc   | 20 +++-
 gcc/config/rs6000/rs6000.h| 19 +--
 gcc/config/rs6000/rs6000.opt  | 17 ++---
 6 files changed, 46 insertions(+), 54 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc
index 6757a2477ad1..6d6838735b33 100644
--- a/gcc/config/rs6000/rs6000-c.cc
+++ b/gcc/config/rs6000/rs6000-c.cc
@@ -338,7 +338,8 @@ rs6000_define_or_undefine_macro (bool define_p, const char 
*name)
#pragma GCC target, we need to adjust the macros dynamically.  */
 
 void
-rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags)
+rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags,
+HOST_WIDE_INT arch_flags)
 {
   if (TARGET_DEBUG_BUILTIN || TARGET_DEBUG_TARGET)
 fprintf (stderr,
@@ -411,7 +412,7 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT 
flags)
summary of the flags associated with particular cpu
definitions.  */
 
-  /* rs6000_isa_flags based options.  */
+  /* rs6000_isa_flags and rs6000_arch_flags based options.  */
   rs6000_define_or_undefine_macro (define_p, "_ARCH_PPC");
   if ((flags & OPTION_MASK_PPC_GPOPT) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PPCSQ");
@@ -419,25 +420,27 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT 
flags)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PPCGR");
   if ((flags & OPTION_MASK_POWERPC64) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PPC64");
-  if ((flags & OPTION_MASK_MFCRF) != 0)
+  if ((flags & OPTION_MASK_POWERPC64) != 0)
+rs6000_define_or_undefine_macro (define_p, "_ARCH_PPC64");

[gcc(refs/users/meissner/heads/work196)] Change TARGET_CMPB to TARGET_POWER6.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:66fe8ea9ba61e32fd78253868be905aa0a227c78

commit 66fe8ea9ba61e32fd78253868be905aa0a227c78
Author: Michael Meissner 
Date:   Mon Mar 24 19:07:50 2025 -0400

Change TARGET_CMPB to TARGET_POWER6.

This patch changes TARGET_CMPB to TARGET_POWER6.  The -mcmpb switch is not 
being
changed, just the name of the macros used to determine if the PowerPC 
processor
supports ISA 2.5 (Power6).

2025-03-24  Michael Meissner  

gcc/

* gcc/config/rs6000/rs6000-builtin.cc (rs6000_builtin_is_supported):
Change TARGET_CMPB to TARGET_POWER6.
* gcc/config/rs6000/rs6000.cc (rs6000_option_override_internal):
Likewise.
(rs6000_rtx_costs): Likewise.
(rs6000_emit_parity): Likewise.
* gcc/config/rs6000/rs6000.h (TARGET_FCFID): Likewise.
(TARGET_LFIWAX): Likewise.
(TARGET_POWER6): New macro.
(TARGET_EXTRA_BUILTINS): Change TARGET_CMPB to TARGET_POWER6.
* gcc/config/rs6000/rs6000.md (enabled attribute): Likewise.
(parity2_cmp): Likewise.
(cmpb3): Likewise.
(copysign3): Likewise.
(copysign3_fcpsgn): Likewise.
(cmpstrnsi): Likewise.
(cmpstrsi): Likewise.

Diff:
---
 gcc/config/rs6000/rs6000-builtin.cc |  4 ++--
 gcc/config/rs6000/rs6000.cc |  8 
 gcc/config/rs6000/rs6000.h  |  7 ---
 gcc/config/rs6000/rs6000.md | 16 
 4 files changed, 18 insertions(+), 17 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-builtin.cc 
b/gcc/config/rs6000/rs6000-builtin.cc
index 4ed2bc1ca89e..dbb8520ab039 100644
--- a/gcc/config/rs6000/rs6000-builtin.cc
+++ b/gcc/config/rs6000/rs6000-builtin.cc
@@ -157,9 +157,9 @@ rs6000_builtin_is_supported (enum rs6000_gen_builtins 
fncode)
 case ENB_P5:
   return TARGET_POWER5;
 case ENB_P6:
-  return TARGET_CMPB;
+  return TARGET_POWER6;
 case ENB_P6_64:
-  return TARGET_CMPB && TARGET_POWERPC64;
+  return TARGET_POWER6 && TARGET_POWERPC64;
 case ENB_P7:
   return TARGET_POPCNTD;
 case ENB_P7_64:
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index b2811d963fcf..c01af37200ac 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -3922,7 +3922,7 @@ rs6000_option_override_internal (bool global_init_p)
 rs6000_isa_flags |= (ISA_2_6_MASKS_EMBEDDED & ~ignore_masks);
   else if (TARGET_DFP)
 rs6000_isa_flags |= (ISA_2_5_MASKS_SERVER & ~ignore_masks);
-  else if (TARGET_CMPB)
+  else if (TARGET_POWER6)
 rs6000_isa_flags |= (ISA_2_5_MASKS_EMBEDDED & ~ignore_masks);
   else if (TARGET_POWER5X)
 rs6000_isa_flags |= (ISA_2_4_MASKS & ~ignore_masks);
@@ -4797,7 +4797,7 @@ rs6000_option_override_internal (bool global_init_p)
  DERAT mispredict penalty.  However the LVE and STVE altivec instructions
  need indexed accesses and the type used is the scalar type of the element
  being loaded or stored.  */
-TARGET_AVOID_XFORM = (rs6000_tune == PROCESSOR_POWER6 && TARGET_CMPB
+TARGET_AVOID_XFORM = (rs6000_tune == PROCESSOR_POWER6 && TARGET_POWER6
  && !TARGET_ALTIVEC);
 
   /* Set the -mrecip options.  */
@@ -22396,7 +22396,7 @@ rs6000_rtx_costs (rtx x, machine_mode mode, int 
outer_code,
   return false;
 
 case PARITY:
-  *total = COSTS_N_INSNS (TARGET_CMPB ? 2 : 6);
+  *total = COSTS_N_INSNS (TARGET_POWER6 ? 2 : 6);
   return false;
 
 case NOT:
@@ -23223,7 +23223,7 @@ rs6000_emit_parity (rtx dst, rtx src)
   tmp = gen_reg_rtx (mode);
 
   /* Use the PPC ISA 2.05 prtyw/prtyd instruction if we can.  */
-  if (TARGET_CMPB)
+  if (TARGET_POWER6)
 {
   if (mode == SImode)
{
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 3794e3c0658d..5b8cf054f98a 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -449,12 +449,12 @@ extern int rs6000_vector_align[];
 #define TARGET_FCFID   (TARGET_POWERPC64   \
 || TARGET_PPC_GPOPT/* 970/power4 */\
 || TARGET_POWER5   /* ISA 2.02 */  \
-|| TARGET_CMPB /* ISA 2.05 */  \
+|| TARGET_POWER6   /* ISA 2.05 */  \
 || TARGET_POPCNTD) /* ISA 2.06 */
 
 #define TARGET_FCTIDZ  TARGET_FCFID
 #define TARGET_STFIWX  TARGET_PPC_GFXOPT
-#define TARGET_LFIWAX  TARGET_CMPB
+#define TARGET_LFIWAX  TARGET_POWER6
 #define TARGET_LFIWZX  TARGET_POPCNTD
 #define TARGET_FCFIDS  TARGET_POPCNTD
 #define TARGET_FCFIDU  TARGET_POPCNTD
@@ -502,6 +502,7 @@ extern int rs6000_vector_align[];
 /* Convert ISA bits like POPCNTB to PowerPC processors like POWER5.  */
 #define TARGET_POWER5  TARGET_POPCNTB
 #define TARGET_POWER5X TARGET_FPRND
+#define TARGET_POWER6

[gcc r15-8873] libstdc++: Fix some broken links in the manual

[Jonathan Wakely via Gcc-cvs]

https://gcc.gnu.org/g:1e4d81aab2542f529d23329fcc5e642eedd617d9

commit r15-8873-g1e4d81aab2542f529d23329fcc5e642eedd617d9
Author: Jonathan Wakely 
Date:   Mon Mar 24 21:28:47 2025 +

libstdc++: Fix some broken links in the manual

libstdc++-v3/ChangeLog:

* doc/xml/manual/policy_data_structures_biblio.xml: Fix two
broken links.
* doc/html/manual/policy_data_structures.html: Regenerate.

Diff:
---
 libstdc++-v3/doc/html/manual/policy_data_structures.html  | 4 ++--
 libstdc++-v3/doc/xml/manual/policy_data_structures_biblio.xml | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/libstdc++-v3/doc/html/manual/policy_data_structures.html 
b/libstdc++-v3/doc/html/manual/policy_data_structures.html
index 45e07814184d..ba140809bbe0 100644
--- a/libstdc++-v3/doc/html/manual/policy_data_structures.html
+++ b/libstdc++-v3/doc/html/manual/policy_data_structures.html
@@ -1037,7 +1037,7 @@
  . 
  Addison-Wesley Publishing Company
. [biblio.kt99fat_heaps] 
-   https://www.cs.princeton.edu/research/techreps/TR-597-99"; target="_top">
+   https://www.cs.princeton.edu/research/techreps/293"; target="_top">
  New Heap Data Structures

   . 
@@ -1185,7 +1185,7 @@
. 
  Addison-Wesley Publishing Company
. [biblio.nelson96stlpq] 
-   https://marknelson.us/posts/1996/01/01/priority-queues.html"; 
target="_top">Priority Queues and the STL
+   https://web.archive.org/web/20240806213010/https://marknelson.us/posts/1996/01/01/priority-queues.html";
 target="_top">Priority Queues and the STL

   . 
January 1996
diff --git a/libstdc++-v3/doc/xml/manual/policy_data_structures_biblio.xml 
b/libstdc++-v3/doc/xml/manual/policy_data_structures_biblio.xml
index 1450b8fc000e..928598d33c6b 100644
--- a/libstdc++-v3/doc/xml/manual/policy_data_structures_biblio.xml
+++ b/libstdc++-v3/doc/xml/manual/policy_data_structures_biblio.xml
@@ -737,7 +737,7 @@
 
   
http://www.w3.org/1999/xlink";
- 
xlink:href="https://www.cs.princeton.edu/research/techreps/TR-597-99";>
+ xlink:href="https://www.cs.princeton.edu/research/techreps/293";>
  New Heap Data Structures

   
@@ -1138,7 +1138,7 @@
 
   
http://www.w3.org/1999/xlink";
- 
xlink:href="https://marknelson.us/posts/1996/01/01/priority-queues.html";>Priority
 Queues and the STL
+ 
xlink:href="https://web.archive.org/web/20240806213010/https://marknelson.us/posts/1996/01/01/priority-queues.html";>Priority
 Queues and the STL

   
   

[gcc(refs/users/omachota/heads/rtl-ssa-dce)] rtl-ssa-dce: improve prelive conditions

[Ondrej Machota via Gcc-cvs]

https://gcc.gnu.org/g:914f83868c9d3641463aecf5d597512ee9b820be

commit 914f83868c9d3641463aecf5d597512ee9b820be
Author: Ondřej Machota 
Date:   Mon Mar 24 23:04:15 2025 +0100

rtl-ssa-dce: improve prelive conditions

Diff:
---
 gcc/dce.cc | 41 -
 1 file changed, 36 insertions(+), 5 deletions(-)

diff --git a/gcc/dce.cc b/gcc/dce.cc
index a769c1387346..f227fc214e99 100644
--- a/gcc/dce.cc
+++ b/gcc/dce.cc
@@ -1394,6 +1394,18 @@ bool side_effects_with_mem (const_rtx x)
   return false;
 }
 
+bool is_ssa_prelive(const_rtx insn) {
+  switch (GET_CODE(insn)) {
+case PREFETCH:
+case UNSPEC:
+case TRAP_IF:
+  return true;
+
+default:
+  return side_effects_p(insn);
+  }
+}
+
 bool is_rtx_insn_prelive(rtx_insn *insn) {
   gcc_assert(insn != nullptr);
 
@@ -1401,6 +1413,7 @@ bool is_rtx_insn_prelive(rtx_insn *insn) {
   // According to the docs, rtl ssa does not contain noteS and barrierS 
   if (!NONJUMP_INSN_P (insn))
   {
+// This handles jumps, debug_insns, call_insn, ...
 //std::cerr << "found jump instruction\n";
 //debug(insn);
 return true;
@@ -1437,6 +1450,8 @@ bool is_rtx_insn_prelive(rtx_insn *insn) {
   // if (sets_global_register(insn)) // check rtx_class with GET_RTX_CLASS if 
RTX_ISNS and convert if needed
   //   return true;
 
+  // TODO : asm_noperands???
+
   rtx body = PATTERN(insn);
   switch (GET_CODE(body)) {
 case CLOBBER: // gcc/gcc/testsuite/gcc.c-torture/compile/2605-1.c
@@ -1449,12 +1464,12 @@ bool is_rtx_insn_prelive(rtx_insn *insn) {
 
 case PARALLEL:
   for (int i = XVECLEN (body, 0) - 1; i >= 0; i--)
-if (!deletable_insn_p_1 (XVECEXP (body, 0, i)))
+if (is_ssa_prelive (XVECEXP (body, 0, i)))
   return true;
-return false;
+  return false;
 
 default:
-  return !deletable_insn_p_1 (body);
+  return is_ssa_prelive (body);
   }
 
   // See deletable_insn_p_1 for UNSPEC. TRAP_IF is caught by 
may_trap_or_fault_p
@@ -1514,6 +1529,8 @@ bool is_prelive(insn_info *insn)
   && def->regno() == REGNO (pic_offset_table_rtx)
   && REGNO (pic_offset_table_rtx) >= FIRST_PSEUDO_REGISTER))
   ) {
+// TODO : set_noop_p?
+
   // std::cerr << "hard reg marked: " << def->regno() << "in " << 
insn->uid() << "\n";
   // debug(rtl);
   return true;
@@ -1722,17 +1739,31 @@ rtl_ssa_dce()
 {
   rtl_ssa_dce_init();
   // debug(crtl->ssa);
+  // std::cout << "\033[31m" << "Before rtl ssa dce pass" << "\033[0m" << "\n";
+
   // for (rtx_insn * insn = get_insns (); insn != nullptr; insn = 
next_insn(insn)) {
-  //   debug(insn);
-  // }l
+// debug(insn);
+  // }
+
+  // std::cout << "\033[31m" << "Before rtl ssa dce pass end" << "\033[0m" << 
"\n";
+
 
   std::unordered_set marked = rtl_ssa_dce_mark();
   rtl_ssa_dce_sweep(marked);
   rtl_ssa_dce_done();
+  // std::cout << "\033[32m" << "After rtl ssa dce" << "\033[0m" << "\n";
+  // for (rtx_insn * insn = get_insns (); insn != nullptr; insn = 
next_insn(insn)) {
+// debug(insn);
+  // }
   if (delete_trivially_dead_insns(get_insns (), max_reg_num ())) {
+// std::cout << "\033[31m" << "Some insns deleted by 
delete_trivially_dead_insns" << "\033[0m" << "\n";
+// for (rtx_insn * insn = get_insns (); insn != nullptr; insn = 
next_insn(insn)) {
+  // debug(insn);
+// }
 std::cerr << "\033[31m" << "rtl_ssa_dce did not delete everything :(" << 
"\033[0m" << "\n";
   }
 
+  // std::cout << "rtl ssa dce FINISH\n";
   return 0;
 }

[gcc r15-8856] gccrs: Fix modules with same name as builtins causing ICE (#3315)

[Arthur Cohen via Gcc-cvs]

https://gcc.gnu.org/g:69f84cbe23ce5358895ddac847d5e907ca234e64

commit r15-8856-g69f84cbe23ce5358895ddac847d5e907ca234e64
Author: Liam Naddell 
Date:   Tue Feb 11 16:42:41 2025 -0500

gccrs: Fix modules with same name as builtins causing ICE (#3315)

gcc/rust/ChangeLog:

* resolve/rust-forever-stack.h (ForeverStack): Add a dedicated 
prelude node for
the Language prelude
* resolve/rust-forever-stack.hxx (ForeverStack): Add support code 
for the
prelude node
* resolve/rust-late-name-resolver-2.0.cc (Late::visit): Move
language prelude builtins to the prelude context
* resolve/rust-name-resolution-context.cc
(NameResolutionContext::scoped): Add code for handling
the prelude corner case
* resolve/rust-rib.h (Rib::Kind): Add a special Prelude rib type

gcc/testsuite/ChangeLog:

* rust/compile/issue-3315-1.rs: Add test for module with same name
as builtin
* rust/compile/issue-3315-2.rs: Test with utilization of i32
type
* rust/compile/nr2/exclude: issue-3315-2.rs Does not work with
NR2.0

Signed-off-by: Liam Naddell 

Diff:
---
 gcc/rust/resolve/rust-forever-stack.h| 12 
 gcc/rust/resolve/rust-forever-stack.hxx  | 82 +---
 gcc/rust/resolve/rust-late-name-resolver-2.0.cc  | 33 +-
 gcc/rust/resolve/rust-name-resolution-context.cc |  4 ++
 gcc/rust/resolve/rust-rib.h  |  5 ++
 gcc/testsuite/rust/compile/issue-3315-1.rs   |  8 +++
 gcc/testsuite/rust/compile/issue-3315-2.rs   |  7 ++
 gcc/testsuite/rust/compile/nr2/exclude   |  1 +
 8 files changed, 127 insertions(+), 25 deletions(-)

diff --git a/gcc/rust/resolve/rust-forever-stack.h 
b/gcc/rust/resolve/rust-forever-stack.h
index 22efc9731977..2a4c7348728b 100644
--- a/gcc/rust/resolve/rust-forever-stack.h
+++ b/gcc/rust/resolve/rust-forever-stack.h
@@ -548,6 +548,7 @@ template  class ForeverStack
 public:
   ForeverStack ()
 : root (Node (Rib (Rib::Kind::Normal), UNKNOWN_NODEID)),
+  prelude (Node (Rib (Rib::Kind::Prelude), UNKNOWN_NODEID, root)),
   cursor_reference (root)
   {
 rust_assert (root.is_root ());
@@ -657,6 +658,8 @@ public:
* the current map, an empty one otherwise.
*/
   tl::optional get (const Identifier &name);
+  tl::optional get_prelude (const Identifier &name);
+  tl::optional get_prelude (const std::string &name);
 
   /**
* Resolve a path to its definition in the current `ForeverStack`
@@ -721,6 +724,7 @@ private:
 {}
 
 bool is_root () const;
+bool is_prelude () const;
 bool is_leaf () const;
 
 void insert_child (Link link, Node child);
@@ -756,7 +760,15 @@ private:
   const Node &cursor () const;
   void update_cursor (Node &new_cursor);
 
+  /* The forever stack's actual nodes */
   Node root;
+  /*
+   * A special prelude node used currently for resolving language builtins
+   * It has the root node as a parent, and acts as a "special case" for name
+   * resolution
+   */
+  Node prelude;
+
   std::reference_wrapper cursor_reference;
 
   void stream_rib (std::stringstream &stream, const Rib &rib,
diff --git a/gcc/rust/resolve/rust-forever-stack.hxx 
b/gcc/rust/resolve/rust-forever-stack.hxx
index 90e0ceb9f811..a6e0b30a57b1 100644
--- a/gcc/rust/resolve/rust-forever-stack.hxx
+++ b/gcc/rust/resolve/rust-forever-stack.hxx
@@ -34,6 +34,13 @@ ForeverStack::Node::is_root () const
   return !parent.has_value ();
 }
 
+template 
+bool
+ForeverStack::Node::is_prelude () const
+{
+  return rib.kind == Rib::Kind::Prelude;
+}
+
 template 
 bool
 ForeverStack::Node::is_leaf () const
@@ -63,6 +70,16 @@ template 
 void
 ForeverStack::push_inner (Rib rib, Link link)
 {
+  if (rib.kind == Rib::Kind::Prelude)
+{
+  // If you push_inner into the prelude from outside the root, you will pop
+  // back into the root, which could screw up a traversal.
+  rust_assert (&cursor_reference.get () == &root);
+  // Prelude doesn't have an access path
+  rust_assert (!link.path);
+  update_cursor (this->prelude);
+  return;
+}
   // If the link does not exist, we create it and emplace a new `Node` with the
   // current node as its parent. `unordered_map::emplace` returns a pair with
   // the iterator and a boolean. If the value already exists, the iterator
@@ -300,6 +317,20 @@ ForeverStack::get (const Identifier &name)
   return resolved_definition;
 }
 
+template 
+tl::optional
+ForeverStack::get_prelude (const Identifier &name)
+{
+  return prelude.rib.get (name.as_string ());
+}
+
+template 
+tl::optional
+ForeverStack::get_prelude (const std::string &name)
+{
+  return prelude.rib.get (name);
+}
+
 template <>
 tl::optional inline ForeverStack::get (
   const Identifier &name)
@@ -399,7 +430,7 @@ ForeverStack::find_starting_point (
break;
 
   auto &seg 

[gcc(refs/users/meissner/heads/work196)] Update ChangeLog.*

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:473e86a316b91aad2e79758a1e2607390287e823

commit 473e86a316b91aad2e79758a1e2607390287e823
Author: Michael Meissner 
Date:   Mon Mar 24 19:24:30 2025 -0400

Update ChangeLog.*

Diff:
---
 gcc/ChangeLog.meissner | 435 +
 1 file changed, 435 insertions(+)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index 6e5f69d44be4..e933d4fcc2a5 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,5 +1,440 @@
+ Branch work196, patch #31 
+
+Use architecture flags for defining _ARCH_PWR macros.
+
+For the newer architectures, this patch changes GCC to define the _ARCH_PWR
+macros using the new architecture flags instead of relying on isa options like
+-mpower10.
+
+The -mpower8-internal, -mpower10, -mpower11, and -mfuture options were removed.
+The -mpower11 and -mfuture options were removed completely, since they were 
just
+added in GCC 15. The other two options were marked as WarnRemoved, and the
+various ISA bits were removed.
+
+TARGET_POWER8, TARGET_POWER10, TARGET_POWER11, and TARGET_FUTURE were 
re-defined
+to use the architeture bits instead of the ISA bits.
+
+There are other internal isa bits that aren't removed with this patch because
+the built-in function support uses those bits.
+
+I have built both big endian and little endian bootstrap compilers and there
+were no regressions.
+
+Can I install this patch on the GCC 15 trunk?
+
+2025-03-24  Michael Meissner  
+
+gcc/
+
+   * config/rs6000/rs6000-c.cc (rs6000_target_modify_macros) Add support to
+   use architecture flags instead of ISA flags for setting most of the
+   _ARCH_PWR* macros.
+   (rs6000_cpu_cpp_builtins): Update rs6000_target_modify_macros call.
+   * config/rs6000/rs6000-cpus.def (ISA_2_7_MASKS_SERVER): Remove
+   OPTION_MASK_POWER8.
+   (ISA_3_1_MASKS_SERVER): Remove OPTION_MASK_POWER10.
+   (POWER11_MASKS_SERVER): Remove OPTION_MASK_POWER11.
+   (FUTURE_MASKS_SERVER): Remove OPTION_MASK_FUTURE.
+   (POWERPC_MASKS): Remove OPTION_MASK_POWER8, OPTION_MASK_POWER10,
+   OPTION_MASK_POWER11, and OPTION_MASK_FUTURE.
+   * config/rs6000/rs6000-protos.h (rs6000_target_modify_macros): Update
+   declaration.
+   (rs6000_target_modify_macros_ptr): Likewise.
+   * config/rs6000/rs6000.cc (rs6000_target_modify_macros_ptr): Likewise.
+   (rs6000_option_override_internal): Use architecture flags instead of ISA
+   flags.
+   (rs6000_opt_masks): Remove -mpower10, -mpower11, and -mfuture which are
+   no longer in the ISA flags.
+   (rs6000_pragma_target_parse): Use architecture flags as well as ISA
+   flags.
+   * config/rs6000/rs6000.h (TARGET_POWER5): Redefine to use architecture
+   flags.
+   (TARGET_POWER5X): Likewise.
+   (TARGET_POWER6): Likewise.
+   (TARGET_POWER7): Likewise.
+   (TARGET_POWER8): Likewise.
+   (TARGET_POWER9): Likewise.
+   (TARGET_POWER10): New macro.
+   (TARGET_POWER11): Likewise.
+   (TARGET_FUTURE): Likewise.
+   * config/rs6000/rs6000.opt (-mpower8-internal): Remove ISA flag bits.
+   (-mpower10): Likewise.
+   (-mpower11): Likewise.
+   (-mfuture): Likewise.
+
+ Branch work196, patch #30 
+
+Add rs6000 architecture masks.
+
+This patch begins the journey to move architecture bits that are not user ISA
+options from rs6000_isa_flags to a new targt variable rs6000_arch_flags.  The
+intention is to remove switches that are currently isa options, but the user
+should not be using this particular option. For example, we want users to use
+-mcpu=power10 and not just -mpower10.
+
+This patch also changes the target_clones support to use an architecture mask
+instead of isa bits.
+
+This patch also switches the handling of .machine to use architecture masks if
+they exist (power4 through power11).  All of the other PowerPCs will continue 
to
+use the existing code for setting the .machine option.
+
+I have built both big endian and little endian bootstrap compilers and there
+were no regressions.
+
+In addition, I constructed a test case that used every archiecture define (like
+_ARCH_PWR4, etc.) and I also looked at the .machine directive generated.  I ran
+this test for all supported combinations of -mcpu, big/little endian, and 32/64
+bit support.  Every single instance generated exactly the same code with the
+patches installed compared to the compiler before installing the patches.
+
+The only difference in this patch compared to the first version posted on
+November 6th is that I the correct attribution and copyright year (i.e. that I
+created rs6000-arch.def in 2024).
+
+Can I install this patch on the GCC 15 trunk?
+
+2025-03-24  Michael Meissner  
+
+gcc/
+
+   * config/rs6000/default64.h (TARGET_CPU_DEFAULT): Set default cpu name.
+   * config/rs6000/rs6000-arch.def: New file.
+   * conf

[gcc/meissner/heads/work196-libs] (15 commits) Merge commit 'refs/users/meissner/heads/work196-libs' of gi

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 8e7a390f462d... Merge commit 'refs/users/meissner/heads/work196-libs' of gi

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 afbeccc3c7cd... Add ChangeLog.libs and update REVISION.

Diff:

Summary of changes (added commits):
---

  8e7a390... Merge commit 'refs/users/meissner/heads/work196-libs' of gi
  9e5cc45... Add ChangeLog.libs and update REVISION.
  473e86a... Update ChangeLog.* (*)
  16afa73... Use architecture flags for defining _ARCH_PWR macros. (*)
  36b4a47... Add rs6000 architecture masks. (*)
  06745b4... Do not allow -mvsx to boost processor to power7. (*)
  7de48d5... Use vector pair load/store for memcpy with -mcpu=future (*)
  a2084f2... Add -mcpu=future tests. (*)
  ab39407... Add -mcpu=future tuning support. (*)
  81c30dc... Add support for -mcpu=future (*)
  c91f9a8... Change TARGET_MODULO to TARGET_POWER9. (*)
  54e6fc5... Change TARGET_POPCNTD to TARGET_POWER7. (*)
  66fe8ea... Change TARGET_CMPB to TARGET_POWER6. (*)
  afa2141... Change TARGET_FPRND to TARGET_POWER5X. (*)
  a7fbb58... Change TARGET_POPCNTB to TARGET_POWER5. (*)

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[gcc(refs/users/meissner/heads/work196-libs)] Merge commit 'refs/users/meissner/heads/work196-libs' of git+ssh://gcc.gnu.org/git/gcc into me/work1

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commit 8e7a390f462d0f3f24e035673872106fcf7fb1e1
Merge: 9e5cc4537cf7 afbeccc3c7cd
Author: Michael Meissner 
Date:   Mon Mar 24 19:27:55 2025 -0400

Merge commit 'refs/users/meissner/heads/work196-libs' of 
git+ssh://gcc.gnu.org/git/gcc into me/work196-libs

Diff:

[gcc/meissner/heads/work196-dmf] (15 commits) Merge commit 'refs/users/meissner/heads/work196-dmf' of git

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The branch 'meissner/heads/work196-dmf' was updated to point to:

 69c7045d185a... Merge commit 'refs/users/meissner/heads/work196-dmf' of git

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 26199514c032... Add ChangeLog.dmf and update REVISION.

Diff:

Summary of changes (added commits):
---

  69c7045... Merge commit 'refs/users/meissner/heads/work196-dmf' of git
  1ee83e5... Add ChangeLog.dmf and update REVISION.
  473e86a... Update ChangeLog.* (*)
  16afa73... Use architecture flags for defining _ARCH_PWR macros. (*)
  36b4a47... Add rs6000 architecture masks. (*)
  06745b4... Do not allow -mvsx to boost processor to power7. (*)
  7de48d5... Use vector pair load/store for memcpy with -mcpu=future (*)
  a2084f2... Add -mcpu=future tests. (*)
  ab39407... Add -mcpu=future tuning support. (*)
  81c30dc... Add support for -mcpu=future (*)
  c91f9a8... Change TARGET_MODULO to TARGET_POWER9. (*)
  54e6fc5... Change TARGET_POPCNTD to TARGET_POWER7. (*)
  66fe8ea... Change TARGET_CMPB to TARGET_POWER6. (*)
  afa2141... Change TARGET_FPRND to TARGET_POWER5X. (*)
  a7fbb58... Change TARGET_POPCNTB to TARGET_POWER5. (*)

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[gcc/meissner/heads/work196-math] (15 commits) Merge commit 'refs/users/meissner/heads/work196-math' of gi

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 5b27a9f6d7bb... Merge commit 'refs/users/meissner/heads/work196-math' of gi

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 e07838f07364... Add ChangeLog.math and update REVISION.

Diff:

Summary of changes (added commits):
---

  5b27a9f... Merge commit 'refs/users/meissner/heads/work196-math' of gi
  56203bb... Add ChangeLog.math and update REVISION.
  473e86a... Update ChangeLog.* (*)
  16afa73... Use architecture flags for defining _ARCH_PWR macros. (*)
  36b4a47... Add rs6000 architecture masks. (*)
  06745b4... Do not allow -mvsx to boost processor to power7. (*)
  7de48d5... Use vector pair load/store for memcpy with -mcpu=future (*)
  a2084f2... Add -mcpu=future tests. (*)
  ab39407... Add -mcpu=future tuning support. (*)
  81c30dc... Add support for -mcpu=future (*)
  c91f9a8... Change TARGET_MODULO to TARGET_POWER9. (*)
  54e6fc5... Change TARGET_POPCNTD to TARGET_POWER7. (*)
  66fe8ea... Change TARGET_CMPB to TARGET_POWER6. (*)
  afa2141... Change TARGET_FPRND to TARGET_POWER5X. (*)
  a7fbb58... Change TARGET_POPCNTB to TARGET_POWER5. (*)

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[gcc(refs/users/meissner/heads/work196-libs)] Add ChangeLog.libs and update REVISION.

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https://gcc.gnu.org/g:9e5cc4537cf71e4e6d0efae76999b73ae2ffa668

commit 9e5cc4537cf71e4e6d0efae76999b73ae2ffa668
Author: Michael Meissner 
Date:   Mon Mar 24 18:45:10 2025 -0400

Add ChangeLog.libs and update REVISION.

2025-03-24  Michael Meissner  

gcc/

* ChangeLog.libs: New file for branch.
* REVISION: Update.

Diff:
---
 gcc/ChangeLog.libs | 5 +
 gcc/REVISION   | 2 +-
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/gcc/ChangeLog.libs b/gcc/ChangeLog.libs
new file mode 100644
index ..be94eb9080d3
--- /dev/null
+++ b/gcc/ChangeLog.libs
@@ -0,0 +1,5 @@
+ Branch work196-libs, baseline 
+
+2025-03-24   Michael Meissner  
+
+   Clone branch
diff --git a/gcc/REVISION b/gcc/REVISION
index 4879f9dc9d4e..4492c6b81930 100644
--- a/gcc/REVISION
+++ b/gcc/REVISION
@@ -1 +1 @@
-work196 branch
+work196-libs branch

[gcc(refs/users/meissner/heads/work196-sha)] Merge commit 'refs/users/meissner/heads/work196-sha' of git+ssh://gcc.gnu.org/git/gcc into me/work19

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https://gcc.gnu.org/g:5605e60391bdc556600bb1ad478aed2fbf6b3126

commit 5605e60391bdc556600bb1ad478aed2fbf6b3126
Merge: e76a94bcd793 448ed3adc3d0
Author: Michael Meissner 
Date:   Mon Mar 24 19:30:13 2025 -0400

Merge commit 'refs/users/meissner/heads/work196-sha' of 
git+ssh://gcc.gnu.org/git/gcc into me/work196-sha

Diff:

[gcc(refs/users/meissner/heads/work196-dmf)] Merge commit 'refs/users/meissner/heads/work196-dmf' of git+ssh://gcc.gnu.org/git/gcc into me/work19

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:69c7045d185a70f0b620add868ac841ff3842657

commit 69c7045d185a70f0b620add868ac841ff3842657
Merge: 1ee83e5949bc 26199514c032
Author: Michael Meissner 
Date:   Mon Mar 24 19:26:39 2025 -0400

Merge commit 'refs/users/meissner/heads/work196-dmf' of 
git+ssh://gcc.gnu.org/git/gcc into me/work196-dmf

Diff:

[gcc/meissner/heads/work196-test] (15 commits) Merge commit 'refs/users/meissner/heads/work196-test' of gi

[Michael Meissner via Gcc-cvs]

The branch 'meissner/heads/work196-test' was updated to point to:

 f43519cd0f21... Merge commit 'refs/users/meissner/heads/work196-test' of gi

It previously pointed to:

 428ef198f15f... Add ChangeLog.test and update REVISION.

Diff:

Summary of changes (added commits):
---

  f43519c... Merge commit 'refs/users/meissner/heads/work196-test' of gi
  e132670... Add ChangeLog.test and update REVISION.
  473e86a... Update ChangeLog.* (*)
  16afa73... Use architecture flags for defining _ARCH_PWR macros. (*)
  36b4a47... Add rs6000 architecture masks. (*)
  06745b4... Do not allow -mvsx to boost processor to power7. (*)
  7de48d5... Use vector pair load/store for memcpy with -mcpu=future (*)
  a2084f2... Add -mcpu=future tests. (*)
  ab39407... Add -mcpu=future tuning support. (*)
  81c30dc... Add support for -mcpu=future (*)
  c91f9a8... Change TARGET_MODULO to TARGET_POWER9. (*)
  54e6fc5... Change TARGET_POPCNTD to TARGET_POWER7. (*)
  66fe8ea... Change TARGET_CMPB to TARGET_POWER6. (*)
  afa2141... Change TARGET_FPRND to TARGET_POWER5X. (*)
  a7fbb58... Change TARGET_POPCNTB to TARGET_POWER5. (*)

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[gcc/meissner/heads/work196-bugs] (15 commits) Merge commit 'refs/users/meissner/heads/work196-bugs' of gi

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 9240cc2e3381... Merge commit 'refs/users/meissner/heads/work196-bugs' of gi

It previously pointed to:

 5e4fe73897f4... Add ChangeLog.bugs and update REVISION.

Diff:

Summary of changes (added commits):
---

  9240cc2... Merge commit 'refs/users/meissner/heads/work196-bugs' of gi
  cd8e607... Add ChangeLog.bugs and update REVISION.
  473e86a... Update ChangeLog.* (*)
  16afa73... Use architecture flags for defining _ARCH_PWR macros. (*)
  36b4a47... Add rs6000 architecture masks. (*)
  06745b4... Do not allow -mvsx to boost processor to power7. (*)
  7de48d5... Use vector pair load/store for memcpy with -mcpu=future (*)
  a2084f2... Add -mcpu=future tests. (*)
  ab39407... Add -mcpu=future tuning support. (*)
  81c30dc... Add support for -mcpu=future (*)
  c91f9a8... Change TARGET_MODULO to TARGET_POWER9. (*)
  54e6fc5... Change TARGET_POPCNTD to TARGET_POWER7. (*)
  66fe8ea... Change TARGET_CMPB to TARGET_POWER6. (*)
  afa2141... Change TARGET_FPRND to TARGET_POWER5X. (*)
  a7fbb58... Change TARGET_POPCNTB to TARGET_POWER5. (*)

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[gcc(refs/users/meissner/heads/work196-dmf)] Add ChangeLog.dmf and update REVISION.

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https://gcc.gnu.org/g:1ee83e5949bc1c50ac3e9be8503f07484b2fb7bf

commit 1ee83e5949bc1c50ac3e9be8503f07484b2fb7bf
Author: Michael Meissner 
Date:   Mon Mar 24 18:42:25 2025 -0400

Add ChangeLog.dmf and update REVISION.

2025-03-24  Michael Meissner  

gcc/

* ChangeLog.dmf: New file for branch.
* REVISION: Update.

Diff:
---
 gcc/ChangeLog.dmf | 5 +
 gcc/REVISION  | 2 +-
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/gcc/ChangeLog.dmf b/gcc/ChangeLog.dmf
new file mode 100644
index ..fea7617a2a46
--- /dev/null
+++ b/gcc/ChangeLog.dmf
@@ -0,0 +1,5 @@
+ Branch work196-dmf, baseline 
+
+2025-03-24   Michael Meissner  
+
+   Clone branch
diff --git a/gcc/REVISION b/gcc/REVISION
index 4879f9dc9d4e..55e716aba160 100644
--- a/gcc/REVISION
+++ b/gcc/REVISION
@@ -1 +1 @@
-work196 branch
+work196-dmf branch

[gcc(refs/users/meissner/heads/work196-test)] Merge commit 'refs/users/meissner/heads/work196-test' of git+ssh://gcc.gnu.org/git/gcc into me/work1

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:f43519cd0f21cae6ca91209dfd4ce61a3a777061

commit f43519cd0f21cae6ca91209dfd4ce61a3a777061
Merge: e13267099bf9 428ef198f15f
Author: Michael Meissner 
Date:   Mon Mar 24 19:31:37 2025 -0400

Merge commit 'refs/users/meissner/heads/work196-test' of 
git+ssh://gcc.gnu.org/git/gcc into me/work196-test

Diff:

[gcc/meissner/heads/work196-vpair] (15 commits) Merge commit 'refs/users/meissner/heads/work196-vpair' of g

[Michael Meissner via Gcc-cvs]

The branch 'meissner/heads/work196-vpair' was updated to point to:

 9298ab07192d... Merge commit 'refs/users/meissner/heads/work196-vpair' of g

It previously pointed to:

 0a3effa9c0aa... Add ChangeLog.vpair and update REVISION.

Diff:

Summary of changes (added commits):
---

  9298ab0... Merge commit 'refs/users/meissner/heads/work196-vpair' of g
  67c20f5... Add ChangeLog.vpair and update REVISION.
  473e86a... Update ChangeLog.* (*)
  16afa73... Use architecture flags for defining _ARCH_PWR macros. (*)
  36b4a47... Add rs6000 architecture masks. (*)
  06745b4... Do not allow -mvsx to boost processor to power7. (*)
  7de48d5... Use vector pair load/store for memcpy with -mcpu=future (*)
  a2084f2... Add -mcpu=future tests. (*)
  ab39407... Add -mcpu=future tuning support. (*)
  81c30dc... Add support for -mcpu=future (*)
  c91f9a8... Change TARGET_MODULO to TARGET_POWER9. (*)
  54e6fc5... Change TARGET_POPCNTD to TARGET_POWER7. (*)
  66fe8ea... Change TARGET_CMPB to TARGET_POWER6. (*)
  afa2141... Change TARGET_FPRND to TARGET_POWER5X. (*)
  a7fbb58... Change TARGET_POPCNTB to TARGET_POWER5. (*)

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[gcc(refs/users/meissner/heads/work196-vpair)] Add ChangeLog.vpair and update REVISION.

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https://gcc.gnu.org/g:67c20f5423f16c819778be26079dc947c5b11385

commit 67c20f5423f16c819778be26079dc947c5b11385
Author: Michael Meissner 
Date:   Mon Mar 24 18:43:24 2025 -0400

Add ChangeLog.vpair and update REVISION.

2025-03-24  Michael Meissner  

gcc/

* ChangeLog.vpair: New file for branch.
* REVISION: Update.

Diff:
---
 gcc/ChangeLog.vpair | 5 +
 gcc/REVISION| 2 +-
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/gcc/ChangeLog.vpair b/gcc/ChangeLog.vpair
new file mode 100644
index ..c4fbc1a7f8b0
--- /dev/null
+++ b/gcc/ChangeLog.vpair
@@ -0,0 +1,5 @@
+ Branch work196-vpair, baseline 
+
+2025-03-24   Michael Meissner  
+
+   Clone branch
diff --git a/gcc/REVISION b/gcc/REVISION
index 4879f9dc9d4e..55b73c436577 100644
--- a/gcc/REVISION
+++ b/gcc/REVISION
@@ -1 +1 @@
-work196 branch
+work196-vpair branch

[gcc(refs/users/meissner/heads/work196-vpair)] Merge commit 'refs/users/meissner/heads/work196-vpair' of git+ssh://gcc.gnu.org/git/gcc into me/work

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https://gcc.gnu.org/g:9298ab07192d12735cb35115e8992163d31209d3

commit 9298ab07192d12735cb35115e8992163d31209d3
Merge: 67c20f5423f1 0a3effa9c0aa
Author: Michael Meissner 
Date:   Mon Mar 24 19:38:42 2025 -0400

Merge commit 'refs/users/meissner/heads/work196-vpair' of 
git+ssh://gcc.gnu.org/git/gcc into me/work196-vpair

Diff:

[gcc(refs/users/meissner/heads/work196-dmf)] RFC2653-Add wD constraint.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:4972b7de87869ce4ba3ca4e456ae45d27627214c

commit 4972b7de87869ce4ba3ca4e456ae45d27627214c
Author: Michael Meissner 
Date:   Mon Mar 24 19:42:39 2025 -0400

RFC2653-Add wD constraint.

This patch adds a new constraint ('wD') that matches the accumulator 
registers
that overlap with VSX registers 0..31 on power10.  Future patches will add 
the
support for a separate accumulator register class that will be used when the
support for dense math registes is added.

2025-03-24   Michael Meissner  

* config/rs6000/constraints.md (wD): New constraint.
* config/rs6000/mma.md (mma_): Prepare for alternate 
accumulator
registers.  Use wD constraint instead of 'd' constraint.  Use
accumulator_operand instead of fpr_reg_operand.
(mma_): Likewise.
(mma_): Likewise.
(mma_): Likewise.
(mma_): Likewise.
(mma_): Likewise.
(mma_): Likewise.
(mma_): Likewise.
(mma_): Likewise.
(mma_): Likewise.
(mma_): Likewise.
(mma_): Likewise.
(mma_): Likewise.
(mma_"
-  [(set (match_operand:XO 0 "fpr_reg_operand" "=&d")
-   (unspec:XO [(match_operand:XO 1 "fpr_reg_operand" "0")]
+  [(set (match_operand:XO 0 "accumulator_operand" "=&wD")
+   (unspec:XO [(match_operand:XO 1 "accumulator_operand" "0")]
MMA_ACC))]
   "TARGET_MMA"
   " %A0"
@@ -523,7 +523,7 @@
   [(set_attr "type" "mma")])
 
 (define_insn "mma_"
-  [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d")
+  [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
(unspec:XO [(match_operand:V16QI 1 "vsx_register_operand" "v,?wa")
(match_operand:V16QI 2 "vsx_register_operand" "v,?wa")]
MMA_VV))]
@@ -532,8 +532,8 @@
   [(set_attr "type" "mma")])
 
 (define_insn "mma_"
-  [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d")
-   (unspec:XO [(match_operand:XO 1 "fpr_reg_operand" "0,0")
+  [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
+   (unspec:XO [(match_operand:XO 1 "accumulator_operand" "0,0")
(match_operand:V16QI 2 "vsx_register_operand" "v,?wa")
(match_operand:V16QI 3 "vsx_register_operand" "v,?wa")]
MMA_AVV))]
@@ -542,7 +542,7 @@
   [(set_attr "type" "mma")])
 
 (define_insn "mma_"
-  [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d")
+  [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
(unspec:XO [(match_operand:OO 1 "vsx_register_operand" "v,?wa")
(match_operand:V16QI 2 "vsx_register_operand" "v,?wa")]
MMA_PV))]
@@ -551,8 +551,8 @@
   [(set_attr "type" "mma")])
 
 (define_insn "mma_"
-  [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d")
-   (unspec:XO [(match_operand:XO 1 "fpr_reg_operand" "0,0")
+  [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
+   (unspec:XO [(match_operand:XO 1 "accumulator_operand" "0,0")
(match_operand:OO 2 "vsx_register_operand" "v,?wa")
(match_operand:V16QI 3 "vsx_register_operand" "v,?wa")]
MMA_APV))]
@@ -561,7 +561,7 @@
   [(set_attr "type" "mma")])
 
 (define_insn "mma_"
-  [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d")
+  [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
(unspec:XO [(match_operand:V16QI 1 "vsx_register_operand" "v,?wa")
(match_operand:V16QI 2 "vsx_register_operand" "v,?wa")
(match_operand:SI 3 "const_0_to_15_operand" "n,n")
@@ -574,8 +574,8 @@
(set_attr "prefixed" "yes")])
 
 (define_insn "mma_"
-  [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d")
-   (unspec:XO [(match_operand:XO 1 "fpr_reg_operand" "0,0")
+  [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
+   (unspec:XO [(match_operand:XO 1 "accumulator_operand" "0,0")
(match_operand:V16QI 2 "vsx_register_operand" "v,?wa")
(match_operand:V16QI 3 "vsx_register_operand" "v,?wa")
(match_operand:SI 4 "const_0_to_15_operand" "n,n")
@@ -588,7 +588,7 @@
(set_attr "prefixed" "yes")])
 
 (define_insn "mma_"
-  [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d")
+  [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
(unspec:XO [(match_operand:V16QI 1 "vsx_register_operand" "v,?wa")
(match_operand:V16QI 2 "vsx_register_operand" "v,?wa")
(match_operand:SI 3 "const_0_to_15_operand" "n,n")
@@ -601,8 +601,8 @@
(set_attr "prefixed" "yes")])
 
 (define_insn "mma_"
-  [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d")
-   (unspec:XO [(match_operand:XO 1 "fpr_reg_operand" "0,0")
+  [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
+   (unspec:XO [(match_operand:XO 1 "accumulator_operand" "0,0")
   

[gcc(refs/users/meissner/heads/work196-dmf)] RFC2656-Support load/store vector with right length.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:08cecfbbdb624f75f4d07d6c1f322a4068fd2a1a

commit 08cecfbbdb624f75f4d07d6c1f322a4068fd2a1a
Author: Michael Meissner 
Date:   Mon Mar 24 19:46:03 2025 -0400

RFC2656-Support load/store vector with right length.

This patch adds support for new instructions that may be added to the 
PowerPC
architecture in the future to enhance the load and store vector with length
instructions.

The current instructions (lxvl, lxvll, stxvl, and stxvll) are inconvient to 
use
since the count for the number of bytes must be in the top 8 bits of the GPR
register, instead of the bottom 8 bits.  This meant that code generating 
these
instructions typically had to do a shift left by 56 bits to get the count 
into
the right position.  In a future version of the PowerPC architecture, new
variants of these instructions might be added that expect the count to be in
the bottom 8 bits of the GPR register.  These patches add this support to 
GCC
if the user uses the -mcpu=future option.

I discovered that the code in rs6000-string.cc to generate ISA 3.1 
lxvl/stxvl
future lxvll/stxvll instructions would generate these instructions on 
32-bit.
However the patterns for these instructions is only done on 64-bit systems. 
 So
I added a check for 64-bit support before generating the instructions.

The patches have been tested on both little and big endian systems.  Can I 
check
it into the master branch?

2025-03-24   Michael Meissner  

gcc/

* config/rs6000/rs6000-string.cc (expand_block_move): Do not 
generate
lxvl and stxvl on 32-bit.
* config/rs6000/vsx.md (lxvl): If -mcpu=future, generate the lxvl 
with
the shift count automaticaly used in the insn.
(lxvrl): New insn for -mcpu=future.
(lxvrll): Likewise.
(stxvl): If -mcpu=future, generate the stxvl with the shift count
automaticaly used in the insn.
(stxvrl): New insn for -mcpu=future.
(stxvrll): Likewise.

gcc/testsuite/

* gcc.target/powerpc/lxvrl.c: New test.
* lib/target-supports.exp 
(check_effective_target_powerpc_future_ok):
New effective target.

Diff:
---
 gcc/config/rs6000/rs6000-string.cc   |   1 +
 gcc/config/rs6000/vsx.md | 122 +--
 gcc/testsuite/gcc.target/powerpc/lxvrl.c |  32 
 3 files changed, 134 insertions(+), 21 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-string.cc 
b/gcc/config/rs6000/rs6000-string.cc
index 703f77fa0bf1..814328140553 100644
--- a/gcc/config/rs6000/rs6000-string.cc
+++ b/gcc/config/rs6000/rs6000-string.cc
@@ -2786,6 +2786,7 @@ expand_block_move (rtx operands[], bool might_overlap)
 
   if (TARGET_MMA && TARGET_BLOCK_OPS_UNALIGNED_VSX
  && TARGET_BLOCK_OPS_VECTOR_PAIR
+ && TARGET_POWERPC64
  && bytes >= 32
  && (align >= 256 || !STRICT_ALIGNMENT))
{
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index dd3573b80868..89523cf4a0e5 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -5712,20 +5712,32 @@
   DONE;
 })
 
-;; Load VSX Vector with Length
+;; Load VSX Vector with Length.  If we have lxvrl, we don't have to do an
+;; explicit shift left into a pseudo.
 (define_expand "lxvl"
-  [(set (match_dup 3)
-(ashift:DI (match_operand:DI 2 "register_operand")
-   (const_int 56)))
-   (set (match_operand:V16QI 0 "vsx_register_operand")
-   (unspec:V16QI
-[(match_operand:DI 1 "gpc_reg_operand")
-  (mem:V16QI (match_dup 1))
- (match_dup 3)]
-UNSPEC_LXVL))]
+  [(use (match_operand:V16QI 0 "vsx_register_operand"))
+   (use (match_operand:DI 1 "gpc_reg_operand"))
+   (use (match_operand:DI 2 "gpc_reg_operand"))]
   "TARGET_P9_VECTOR && TARGET_64BIT"
 {
-  operands[3] = gen_reg_rtx (DImode);
+  rtx shift_len = gen_rtx_ASHIFT (DImode, operands[2], GEN_INT (56));
+  rtx len;
+
+  if (TARGET_FUTURE)
+len = shift_len;
+  else
+{
+  len = gen_reg_rtx (DImode);
+  emit_insn (gen_rtx_SET (len, shift_len));
+}
+
+  rtx dest = operands[0];
+  rtx addr = operands[1];
+  rtx mem = gen_rtx_MEM (V16QImode, addr);
+  rtvec rv = gen_rtvec (3, addr, mem, len);
+  rtx lxvl = gen_rtx_UNSPEC (V16QImode, rv, UNSPEC_LXVL);
+  emit_insn (gen_rtx_SET (dest, lxvl));
+  DONE;
 })
 
 (define_insn "*lxvl"
@@ -5749,6 +5761,34 @@
   "lxvll %x0,%1,%2"
   [(set_attr "type" "vecload")])
 
+;; For lxvrl and lxvrll, use the combiner to eliminate the shift.  The
+;; define_expand for lxvl will already incorporate the shift in generating the
+;; insn.  The lxvll buitl-in function required the user to have already done
+;; the shift.  Defining lxvrll this way, will optimize cases where the user has
+;; done the shift immediately before the built-in.
+(define_insn "*lxvrl"
+  [(set (matc

[gcc(refs/users/meissner/heads/work196-dmf)] RFC2677-Add xvrlw support.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:5a4a01bdf02df08ad46d9103f0cfb3b04fd81e74

commit 5a4a01bdf02df08ad46d9103f0cfb3b04fd81e74
Author: Michael Meissner 
Date:   Mon Mar 24 19:49:39 2025 -0400

RFC2677-Add xvrlw support.

2025-03-24  Michael Meissner  

gcc/

* config/rs6000/altivec.md (xvrlw): New insn.
* config/rs6000/rs6000.h (TARGET_XVRLW): New macro.

gcc/testsuite/

* gcc.target/powerpc/vector-rotate-left.c: New test.

Diff:
---
 gcc/config/rs6000/altivec.md   | 14 +
 gcc/config/rs6000/rs6000.h |  3 ++
 .../gcc.target/powerpc/vector-rotate-left.c| 34 ++
 3 files changed, 51 insertions(+)

diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
index 7edc288a6565..d158cf479d60 100644
--- a/gcc/config/rs6000/altivec.md
+++ b/gcc/config/rs6000/altivec.md
@@ -1982,6 +1982,20 @@
 }
   [(set_attr "type" "vecperm")])
 
+;; -mcpu=future adds a vector rotate left word variant.  There is no vector
+;; byte/half-word/double-word/quad-word rotate left.  This insn occurs before
+;; altivec_vrl and will match for -mcpu=future, while other cpus will
+;; match the generic insn.
+(define_insn "*xvrlw"
+  [(set (match_operand:V4SI 0 "register_operand" "=v,wa")
+   (rotate:V4SI (match_operand:V4SI 1 "register_operand" "v,wa")
+(match_operand:V4SI 2 "register_operand" "v,wa")))]
+  "TARGET_XVRLW"
+  "@
+   vrlw %0,%1,%2
+   xvrlw %x0,%x1,%x2"
+  [(set_attr "type" "vecsimple")])
+
 (define_insn "altivec_vrl"
   [(set (match_operand:VI2 0 "register_operand" "=v")
 (rotate:VI2 (match_operand:VI2 1 "register_operand" "v")
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 1267169de509..76f1f87290f3 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -584,6 +584,9 @@ extern int rs6000_vector_align[];
 /* Whether we have PADDIS support.  */
 #define TARGET_PADDIS  TARGET_FUTURE
 
+/* Whether we have XVRLW support.  */
+#define TARGET_XVRLW   TARGET_FUTURE
+
 /* Whether the various reciprocal divide/square root estimate instructions
exist, and whether we should automatically generate code for the instruction
by default.  */
diff --git a/gcc/testsuite/gcc.target/powerpc/vector-rotate-left.c 
b/gcc/testsuite/gcc.target/powerpc/vector-rotate-left.c
new file mode 100644
index ..5a5f37755077
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vector-rotate-left.c
@@ -0,0 +1,34 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_future_ok } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-mdejagnu-cpu=future -O2" } */
+
+/* Test whether the xvrl (vector word rotate left using VSX registers insead of
+   Altivec registers is generated.  */
+
+#include 
+
+typedef vector unsigned int  v4si_t;
+
+v4si_t
+rotl_v4si_scalar (v4si_t x, unsigned long n)
+{
+  __asm__ (" # %x0" : "+f" (x));
+  return (x << n) | (x >> (32 - n));   /* xvrlw.  */
+}
+
+v4si_t
+rotr_v4si_scalar (v4si_t x, unsigned long n)
+{
+  __asm__ (" # %x0" : "+f" (x));
+  return (x >> n) | (x << (32 - n));   /* xvrlw.  */
+}
+
+v4si_t
+rotl_v4si_vector (v4si_t x, v4si_t y)
+{
+  __asm__ (" # %x0" : "+f" (x));   /* xvrlw.  */
+  return vec_rl (x, y);
+}
+
+/* { dg-final { scan-assembler-times {\mxvrlw\M} 3  } } */

[gcc] Created branch 'meissner/heads/work196' in namespace 'refs/users'

[Michael Meissner via Gcc-cvs]

The branch 'meissner/heads/work196' was created in namespace 'refs/users' 
pointing to:

 1e4d81aab254... libstdc++: Fix some broken links in the manual

[gcc(refs/users/meissner/heads/work196-vpair)] Add ChangeLog.vpair and update REVISION.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:0a3effa9c0aa574a49b13fbe04c495caa0565d2a

commit 0a3effa9c0aa574a49b13fbe04c495caa0565d2a
Author: Michael Meissner 
Date:   Mon Mar 24 18:43:24 2025 -0400

Add ChangeLog.vpair and update REVISION.

2025-03-24  Michael Meissner  

gcc/

* ChangeLog.vpair: New file for branch.
* REVISION: Update.

Diff:
---
 gcc/ChangeLog.vpair | 5 +
 gcc/REVISION| 2 +-
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/gcc/ChangeLog.vpair b/gcc/ChangeLog.vpair
new file mode 100644
index ..c4fbc1a7f8b0
--- /dev/null
+++ b/gcc/ChangeLog.vpair
@@ -0,0 +1,5 @@
+ Branch work196-vpair, baseline 
+
+2025-03-24   Michael Meissner  
+
+   Clone branch
diff --git a/gcc/REVISION b/gcc/REVISION
index 4879f9dc9d4e..55b73c436577 100644
--- a/gcc/REVISION
+++ b/gcc/REVISION
@@ -1 +1 @@
-work196 branch
+work196-vpair branch

[gcc(refs/users/meissner/heads/work196-dmf)] Add ChangeLog.dmf and update REVISION.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:26199514c032f0e952d1e4ed97ae87747cd59430

commit 26199514c032f0e952d1e4ed97ae87747cd59430
Author: Michael Meissner 
Date:   Mon Mar 24 18:42:25 2025 -0400

Add ChangeLog.dmf and update REVISION.

2025-03-24  Michael Meissner  

gcc/

* ChangeLog.dmf: New file for branch.
* REVISION: Update.

Diff:
---
 gcc/ChangeLog.dmf | 5 +
 gcc/REVISION  | 2 +-
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/gcc/ChangeLog.dmf b/gcc/ChangeLog.dmf
new file mode 100644
index ..fea7617a2a46
--- /dev/null
+++ b/gcc/ChangeLog.dmf
@@ -0,0 +1,5 @@
+ Branch work196-dmf, baseline 
+
+2025-03-24   Michael Meissner  
+
+   Clone branch
diff --git a/gcc/REVISION b/gcc/REVISION
index 4879f9dc9d4e..55e716aba160 100644
--- a/gcc/REVISION
+++ b/gcc/REVISION
@@ -1 +1 @@
-work196 branch
+work196-dmf branch

[gcc] Created branch 'meissner/heads/work196-sha' in namespace 'refs/users'

[Michael Meissner via Gcc-cvs]

The branch 'meissner/heads/work196-sha' was created in namespace 'refs/users' 
pointing to:

 bc61a0720b30... Add ChangeLog.meissner and REVISION.

[gcc(refs/users/meissner/heads/work196-test)] Add ChangeLog.test and update REVISION.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:428ef198f15ffcf72d0baaa6c246807017c5a344

commit 428ef198f15ffcf72d0baaa6c246807017c5a344
Author: Michael Meissner 
Date:   Mon Mar 24 18:47:11 2025 -0400

Add ChangeLog.test and update REVISION.

2025-03-24  Michael Meissner  

gcc/

* ChangeLog.test: New file for branch.
* REVISION: Update.

Diff:
---
 gcc/ChangeLog.test | 5 +
 gcc/REVISION   | 2 +-
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/gcc/ChangeLog.test b/gcc/ChangeLog.test
new file mode 100644
index ..6fd56aa9a576
--- /dev/null
+++ b/gcc/ChangeLog.test
@@ -0,0 +1,5 @@
+ Branch work196-test, baseline 
+
+2025-03-24   Michael Meissner  
+
+   Clone branch
diff --git a/gcc/REVISION b/gcc/REVISION
index 4879f9dc9d4e..907a8cab2302 100644
--- a/gcc/REVISION
+++ b/gcc/REVISION
@@ -1 +1 @@
-work196 branch
+work196-test branch

[gcc] Created branch 'meissner/heads/work196-test' in namespace 'refs/users'

[Michael Meissner via Gcc-cvs]

The branch 'meissner/heads/work196-test' was created in namespace 'refs/users' 
pointing to:

 bc61a0720b30... Add ChangeLog.meissner and REVISION.

[gcc] Created branch 'meissner/heads/work196-orig' in namespace 'refs/users'

[Michael Meissner via Gcc-cvs]

The branch 'meissner/heads/work196-orig' was created in namespace 'refs/users' 
pointing to:

 1e4d81aab254... libstdc++: Fix some broken links in the manual

[gcc] Created branch 'meissner/heads/work196-math' in namespace 'refs/users'

[Michael Meissner via Gcc-cvs]

The branch 'meissner/heads/work196-math' was created in namespace 'refs/users' 
pointing to:

 bc61a0720b30... Add ChangeLog.meissner and REVISION.

[gcc r13-9448] c++: Don't mix timevar_start and auto_cond_timevar for TV_NAME_LOOKUP [PR116681]

[Simon Martin via Gcc-cvs]

https://gcc.gnu.org/g:73db20707fd60f303313fda3c9245a06037f312a

commit r13-9448-g73db20707fd60f303313fda3c9245a06037f312a
Author: Simon Martin 
Date:   Mon Mar 24 08:25:07 2025 +0100

c++: Don't mix timevar_start and auto_cond_timevar for TV_NAME_LOOKUP 
[PR116681]

We currently ICE upon the following testcase when using -ftime-report

=== cut here ===
template < int> using __conditional_t = int;
template < typename _Iter >
concept random_access_iterator = requires { new _Iter; };
template < typename _Iterator >
struct reverse_iterator {
  using iterator_concept =
__conditional_t< random_access_iterator< _Iterator>>;
};
void RemoveBottom() {
  int iter;
  for (reverse_iterator< int > iter;;)
  ;
}
=== cut here ===

The problem is that qualified_namespace_lookup does a plain start() of
the TV_NAME_LOOKUP timer (that asserts that the timer is not already
started). However this timer has already been cond_start()'d in the call
stack - by pushdecl - so the assert fails.

This patch simply ensures that we always conditionally start this timer
(which is done in all other places that use it).

PR c++/116681

gcc/cp/ChangeLog:

* name-lookup.cc (qualified_namespace_lookup): Use an
auto_cond_timer instead of using timevar_start and timevar_stop.

gcc/testsuite/ChangeLog:

* g++.dg/cpp2a/concepts-pr116681.C: New test.

(cherry picked from commit 005f7176e0f457a1e1a7398ddcb4a4972da28c62)

Diff:
---
 gcc/cp/name-lookup.cc  |  3 +--
 gcc/testsuite/g++.dg/cpp2a/concepts-pr116681.C | 20 
 2 files changed, 21 insertions(+), 2 deletions(-)

diff --git a/gcc/cp/name-lookup.cc b/gcc/cp/name-lookup.cc
index 89f28caf183d..16e3cc688f9d 100644
--- a/gcc/cp/name-lookup.cc
+++ b/gcc/cp/name-lookup.cc
@@ -6918,10 +6918,9 @@ tree lookup_qualified_name (tree t, const char *p, 
LOOK_want w, bool c)
 static bool
 qualified_namespace_lookup (tree scope, name_lookup *lookup)
 {
-  timevar_start (TV_NAME_LOOKUP);
+  auto_cond_timevar tv (TV_NAME_LOOKUP);
   query_oracle (lookup->name);
   bool found = lookup->search_qualified (ORIGINAL_NAMESPACE (scope));
-  timevar_stop (TV_NAME_LOOKUP);
   return found;
 }
 
diff --git a/gcc/testsuite/g++.dg/cpp2a/concepts-pr116681.C 
b/gcc/testsuite/g++.dg/cpp2a/concepts-pr116681.C
new file mode 100644
index ..f1b47797f1ed
--- /dev/null
+++ b/gcc/testsuite/g++.dg/cpp2a/concepts-pr116681.C
@@ -0,0 +1,20 @@
+// PR c++/116681
+// { dg-do compile { target c++20 } }
+// { dg-additional-options "-ftime-report" }
+// { dg-allow-blank-lines-in-output 1 }
+// { dg-prune-output "Time variable" }
+// { dg-prune-output "k" }
+// { dg-prune-output "\[0-9\]+%" }
+
+template < int> using __conditional_t = int;
+template < typename _Iter >
+concept random_access_iterator = requires { new _Iter; };
+template < typename _Iterator > struct reverse_iterator {
+  using iterator_concept = __conditional_t< random_access_iterator< _Iterator 
>>;
+};
+void RemoveBottom()
+{
+  int iter;
+  for (reverse_iterator< int > iter;;)
+  ;
+}