[gcc r15-7581] LoongArch: Fix the issue of function jump out of range caused by crtbeginS.o [PR118844].
https://gcc.gnu.org/g:ae14d7d04da8c6cb542269722638071f999f94d8 commit r15-7581-gae14d7d04da8c6cb542269722638071f999f94d8 Author: Lulu Cheng Date: Wed Feb 12 14:29:58 2025 +0800 LoongArch: Fix the issue of function jump out of range caused by crtbeginS.o [PR118844]. Due to the presence of R_LARCH_B26 in /usr/lib/gcc/loongarch64-linux-gnu/14/crtbeginS.o, its addressing range is [PC-128MiB, PC+128MiB-4]. This means that when the code segment size exceeds 128MB, linking with lld will definitely fail (ld will not fail because the order of the two is different). The linking order: lld: crtbeginS.o + .text + .plt ld : .plt + crtbeginS.o + .text To solve this issue, add '-mcmodel=extreme' when compiling crtbeginS.o. PR target/118844 libgcc/ChangeLog: * config/loongarch/t-crtstuff: Add '-mcmodel=extreme' to CRTSTUFF_T_CFLAGS_S. Diff: --- libgcc/config/loongarch/t-crtstuff | 6 ++ 1 file changed, 6 insertions(+) diff --git a/libgcc/config/loongarch/t-crtstuff b/libgcc/config/loongarch/t-crtstuff index b8c36eb66b78..2a2489b7ef4e 100644 --- a/libgcc/config/loongarch/t-crtstuff +++ b/libgcc/config/loongarch/t-crtstuff @@ -3,3 +3,9 @@ # to .eh_frame data from crtbeginT.o instead of the user-defined object # during static linking. CRTSTUFF_T_CFLAGS += -fno-omit-frame-pointer -fno-asynchronous-unwind-tables + +# As shown in the test case PR118844, when using lld for linking, +# it fails due to B26 in crtbeginS.o causing the link to exceed the range. +# Therefore, the issue was resolved by adding the compilation option +# "-mcmodel=extreme" when compiling crtbeginS.o. +CRTSTUFF_T_CFLAGS_S += -mcmodel=extreme
[gcc r15-7582] i386: Do not check vector size conflict when AVX512 is not explicitly set [PR 118815]
https://gcc.gnu.org/g:e15216046dba02ffa1c3ae367cdc86d5fd3df0be
commit r15-7582-ge15216046dba02ffa1c3ae367cdc86d5fd3df0be
Author: Haochen Jiang
Date: Mon Feb 10 16:53:27 2025 +0800
i386: Do not check vector size conflict when AVX512 is not explicitly set
[PR 118815]
When AVX512 is not explicitly set, we should not take EVEX512 bit into
consideration when checking vector size. It will solve the intrin header
file reporting warnings when compiling with -Wsystem-headers.
However, there is side effect on the usage for '-march=xxx -mavx10.1-256',
where xxx is with AVX512. It will not report warning on vector size for now.
Since it is a rare usage, we will take it.
gcc/ChangeLog:
PR target/118815
* config/i386/i386-options.cc (ix86_option_override_internal):
Do not check vector size conflict when AVX512 is not explicitly
set.
gcc/testsuite/ChangeLog:
PR target/118815
* gcc.target/i386/pr118815.c: New test.
Diff:
---
gcc/config/i386/i386-options.cc | 1 +
gcc/testsuite/gcc.target/i386/pr118815.c | 9 +
2 files changed, 10 insertions(+)
diff --git a/gcc/config/i386/i386-options.cc b/gcc/config/i386/i386-options.cc
index 3467ab0bbebc..7e85334d3d36 100644
--- a/gcc/config/i386/i386-options.cc
+++ b/gcc/config/i386/i386-options.cc
@@ -2711,6 +2711,7 @@ ix86_option_override_internal (bool main_args_p,
"using 512 as max vector size");
}
else if (TARGET_AVX512F_P (opts->x_ix86_isa_flags)
+ && (opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_AVX512F)
&& !(OPTION_MASK_ISA2_EVEX512
& opts->x_ix86_isa_flags2_explicit))
warning (0, "Vector size conflicts between AVX10.1 and AVX512, using "
diff --git a/gcc/testsuite/gcc.target/i386/pr118815.c
b/gcc/testsuite/gcc.target/i386/pr118815.c
new file mode 100644
index ..84308fce08a8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr118815.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=x86-64-v3" } */
+
+#pragma GCC push_options
+#pragma GCC target("avx10.2-256")
+
+void foo();
+
+#pragma GCC pop_options
[gcc r14-11314] i386: Do not check vector size conflict when AVX512 is not explicitly set [PR 118815]
https://gcc.gnu.org/g:31cbac836bb4f4c2172a91ee6164d8fdd32a8cb8 commit r14-11314-g31cbac836bb4f4c2172a91ee6164d8fdd32a8cb8 Author: Haochen Jiang Date: Mon Feb 10 16:53:27 2025 +0800 i386: Do not check vector size conflict when AVX512 is not explicitly set [PR 118815] When AVX512 is not explicitly set, we should not take EVEX512 bit into consideration when checking vector size. It will solve the intrin header file reporting warnings when compiling with -Wsystem-headers. However, there is side effect on the usage for '-march=xxx -mavx10.1-256', where xxx is with AVX512. It will not report warning on vector size for now. Since it is a rare usage, we will take it. gcc/ChangeLog: PR target/118815 * config/i386/i386-options.cc (ix86_option_override_internal): Do not check vector size conflict when AVX512 is not explicitly set. Diff: --- gcc/config/i386/i386-options.cc | 1 + 1 file changed, 1 insertion(+) diff --git a/gcc/config/i386/i386-options.cc b/gcc/config/i386/i386-options.cc index f6c450cc871c..a6eba1ca2b87 100644 --- a/gcc/config/i386/i386-options.cc +++ b/gcc/config/i386/i386-options.cc @@ -2725,6 +2725,7 @@ ix86_option_override_internal (bool main_args_p, "using 512 as max vector size"); } else if (TARGET_AVX512F_P (opts->x_ix86_isa_flags) + && (opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_AVX512F) && !(OPTION_MASK_ISA2_EVEX512 & opts->x_ix86_isa_flags2_explicit)) warning (0, "Vector size conflicts between AVX10.1 and AVX512, using "
[gcc r15-7584] i386: Re-alias avx10.2 to 512 bit and deprecate -mno-avx10.2-[256, 512]
https://gcc.gnu.org/g:9ea56e2a3e1e172873a3ed0be34c4d252b06de9e commit r15-7584-g9ea56e2a3e1e172873a3ed0be34c4d252b06de9e Author: Haochen Jiang Date: Tue Feb 11 11:29:43 2025 +0800 i386: Re-alias avx10.2 to 512 bit and deprecate -mno-avx10.2-[256,512] As mentioned in avx10.1 option deprecate patch, based on the feedback we got, we would like to re-alias avx10.x to 512 bit. For -mno- options, also mentioned in the previous patch, it is confusing what it is disabling when it comes to avx10. So we will only provide -mno-avx10.x options from AVX10.2, disabling the whole AVX10.x. gcc/ChangeLog: * common/config/i386/i386-common.cc (OPTION_MASK_ISA2_AVX10_1_UNSET): Adjust macro. (OPTION_MASK_ISA2_AVX10_2_256_UNSET): Removed. (OPTION_MASK_ISA2_AVX10_2_512_UNSET): Ditto. (OPTION_MASK_ISA2_AVX10_2_UNSET): New. (ix86_handle_option): Remove disable part for avx10.2-256. Rename avx10.2-512 switch case to avx10.2 and adjust disable part macro. * common/config/i386/i386-isas.h: Adjust avx10.2 and avx10.2-512. * config/i386/driver-i386.cc (host_detect_local_cpu): Do not append -mno-avx10.x-256 for -march=native. * config/i386/i386-options.cc (ix86_valid_target_attribute_inner_p): Adjust avx10.2 and avx10.2-512. * config/i386/i386.opt: Reject Negative for mavx10.2-256. Alias mavx10.2-512 to mavx10.2. Reject Negative for mavx10.2-512. * doc/extend.texi: Adjust documentation. * doc/sourcebuild.texi: Ditto. gcc/testsuite/ChangeLog: * gcc.target/i386/avx10_2-512-vminmaxbf16-2.c: Add missing avx10_2_512 check. * gcc.target/i386/avx10_2-512-vminmaxpd-2.c: Ditto. * gcc.target/i386/avx10_2-512-vminmaxph-2.c: Ditto. * gcc.target/i386/avx10_2-512-vminmaxps-2.c: Ditto. * gcc.target/i386/avx10-check.h: Change avx10.2 to avx10.2-256. * gcc.target/i386/avx10_2-bf16-1.c: Ditto. * gcc.target/i386/avx10_2-bf16-vector-cmp-1.c: Ditto. * gcc.target/i386/avx10_2-bf16-vector-fma-1.c: Ditto. * gcc.target/i386/avx10_2-bf16-vector-operations-1.c: Ditto. * gcc.target/i386/avx10_2-bf16-vector-smaxmin-1.c: Ditto. * gcc.target/i386/avx10_2-builtin-1.c: Ditto. * gcc.target/i386/avx10_2-builtin-2.c: Ditto. * gcc.target/i386/avx10_2-comibf-1.c: Ditto. * gcc.target/i386/avx10_2-comibf-2.c: Ditto. * gcc.target/i386/avx10_2-comibf-3.c: Ditto. * gcc.target/i386/avx10_2-comibf-4.c: Ditto. * gcc.target/i386/avx10_2-compare-1.c: Ditto. * gcc.target/i386/avx10_2-compare-1b.c: Ditto. * gcc.target/i386/avx10_2-convert-1.c: Ditto. * gcc.target/i386/avx10_2-media-1.c: Ditto. * gcc.target/i386/avx10_2-minmax-1.c: Ditto. * gcc.target/i386/avx10_2-movrs-1.c: Ditto. * gcc.target/i386/avx10_2-partial-bf16-vector-fast-math-1.c: Ditto. * gcc.target/i386/avx10_2-partial-bf16-vector-fma-1.c: Ditto. * gcc.target/i386/avx10_2-partial-bf16-vector-operations-1.c: Ditto. * gcc.target/i386/avx10_2-partial-bf16-vector-smaxmin-1.c: Ditto. * gcc.target/i386/avx10_2-rounding-1.c: Ditto. * gcc.target/i386/avx10_2-rounding-2.c: Ditto. * gcc.target/i386/avx10_2-rounding-3.c: Ditto. * gcc.target/i386/avx10_2-satcvt-1.c: Ditto. * gcc.target/i386/avx10_2-vaddbf16-2.c: Ditto. * gcc.target/i386/avx10_2-vcmpbf16-2.c: Ditto. * gcc.target/i386/avx10_2-vcomisbf16-1.c: Ditto. * gcc.target/i386/avx10_2-vcomisbf16-2.c: Ditto. * gcc.target/i386/avx10_2-vcvt2ph2bf8-2.c: Ditto. * gcc.target/i386/avx10_2-vcvt2ph2bf8s-2.c: Ditto. * gcc.target/i386/avx10_2-vcvt2ph2hf8-2.c: Ditto. * gcc.target/i386/avx10_2-vcvt2ph2hf8s-2.c: Ditto. * gcc.target/i386/avx10_2-vcvt2ps2phx-2.c: Ditto. * gcc.target/i386/avx10_2-vcvtbf162ibs-2.c: Ditto. * gcc.target/i386/avx10_2-vcvtbf162iubs-2.c: Ditto. * gcc.target/i386/avx10_2-vcvtbiasph2bf8-2.c: Ditto. * gcc.target/i386/avx10_2-vcvtbiasph2bf8s-2.c: Ditto. * gcc.target/i386/avx10_2-vcvtbiasph2hf8-2.c: Ditto. * gcc.target/i386/avx10_2-vcvtbiasph2hf8s-2.c: Ditto. * gcc.target/i386/avx10_2-vcvthf82ph-2.c: Ditto. * gcc.target/i386/avx10_2-vcvtph2bf8-2.c: Ditto. * gcc.target/i386/avx10_2-vcvtph2bf8s-2.c: Ditto. * gcc.target/i386/avx10_2-vcvtph2hf8-2.c: Ditto. * gcc.target/i386/avx10_2-vcvtph2hf8s-2.c: Ditto. * gcc.target/i386/avx10_2-vcvtph2ibs-2.c: Ditto.
[gcc r15-7578] AVR: ad target/118764 - Let -mcvt set built-in macro __AVR_CVT__
https://gcc.gnu.org/g:22a0cba3c5a24860205086e98c0dae56f50422c1
commit r15-7578-g22a0cba3c5a24860205086e98c0dae56f50422c1
Author: Georg-Johann Lay
Date: Sun Feb 16 17:20:39 2025 +0100
AVR: ad target/118764 - Let -mcvt set built-in macro __AVR_CVT__
gcc/
PR target/118764
* config/avr/avr-c.cc (avr_cpu_cpp_builtins)
[TARGET_CVT]: Define __AVR_CVT__.
* doc/invoke.texi (AVR Built-in Macros): Document __AVR_CVT__.
Diff:
---
gcc/config/avr/avr-c.cc | 3 +++
gcc/doc/invoke.texi | 6 +-
2 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/gcc/config/avr/avr-c.cc b/gcc/config/avr/avr-c.cc
index 6f49d3f98a0b..9176a49bc44e 100644
--- a/gcc/config/avr/avr-c.cc
+++ b/gcc/config/avr/avr-c.cc
@@ -420,6 +420,9 @@ avr_cpu_cpp_builtins (cpp_reader *pfile)
if (TARGET_RMW)
cpp_define (pfile, "__AVR_ISA_RMW__");
+ if (TARGET_CVT)
+cpp_define (pfile, "__AVR_CVT__");
+
cpp_define_formatted (pfile, "__AVR_SFR_OFFSET__=0x%x",
avr_arch->sfr_offset);
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index d1d633beb4bb..ca8e468f3f2d 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -24468,7 +24468,7 @@ XJMP exit
Instead, put @code{main} in section
@w{@uref{https://avrdudes.github.io/avr-libc/avr-libc-user-manual/mem_sections.html#sec_dot_init,@code{.init9}}}
so that no call is required.
-By setting this options the user asserts that @code{main} will not return.
+By setting this option the user asserts that @code{main} will not return.
This option can be used for devices with very limited resources in order
to save a few bytes of code and stack space. It will work as expected since
@@ -24834,6 +24834,10 @@ is defined to @code{atmega8}.
If @var{device} is not a device but only a core architecture like
@samp{avr51}, this macro is not defined.
+@item __AVR_CVT__
+The code is being compiled with option @code{-mcvt} to use a
+@emph{compact vector table}.
+
@item __AVR_XMEGA__
The device / architecture belongs to the XMEGA family of devices.
[gcc r15-7583] i386: Deprecate -m[no-]avx10.1 and make -mno-avx10.1-512 to disable the whole AVX10.1
https://gcc.gnu.org/g:e4f4a5c85e08fb5b9945ba72f07069b2ea7d34e7 commit r15-7583-ge4f4a5c85e08fb5b9945ba72f07069b2ea7d34e7 Author: Haochen Jiang Date: Tue Feb 11 11:29:34 2025 +0800 i386: Deprecate -m[no-]avx10.1 and make -mno-avx10.1-512 to disable the whole AVX10.1 Based on the feedback we got, we would like to re-alias avx10.x to 512 bit in the future. This leaves the current avx10.1 alias to 256 bit inconsistent. Since it has been there for GCC 14.1 and GCC 14.2, we decide to deprecate avx10.1 alias. The current proposal is not adding it back in the future, but it might change if necessary. For -mno- options, it is confusing what it is disabling when it comes to avx10. Since there is barely usage enabling AVX10 with 512 bit then disabling it, we will only provide -mno-avx10.x options in the future, disabling the whole AVX10.x. If someone really wants to disable 512 bit after enabling it, -mavx10.x-512 -mno-avx10.x -mavx10.x-256 is the only way to do that since we also do not want to break the usual expression on -m- options enabling everything mentioned. However, for avx10.1, since we deprecated avx10.1, there is no reason we should have -mno-avx10.1. Thus, we need to keep -mno-avx10.1-[256,512]. To avoid confusion, we will make -mno-avx10.1-512 to disable the whole AVX10.1 set to match the future -mno-avx10.x. gcc/ChangeLog: * common/config/i386/i386-common.cc (OPTION_MASK_ISA2_AVX2_UNSET): Change AVX10.1 unset macro. (OPTION_MASK_ISA2_AVX10_1_256_UNSET): Removed. (OPTION_MASK_ISA2_AVX10_1_512_UNSET): Removed. (OPTION_MASK_ISA2_AVX10_1_UNSET): New. (ix86_handle_option): Adjust AVX10.1 unset macro. * common/config/i386/i386-isas.h: Remove avx10.1. * config/i386/i386-options.cc (ix86_valid_target_attribute_inner_p): Ditto. (ix86_option_override_internal): Adjust warning message. * config/i386/i386.opt: Remove mavx10.1. * doc/extend.texi: Remove avx10.1 and adjust doc. * doc/sourcebuild.texi: Ditto. gcc/testsuite/ChangeLog: * gcc.target/i386/avx10-check.h: Change to avx10.1-256. * gcc.target/i386/avx10_1-1.c: Ditto. * gcc.target/i386/avx10_1-13.c: Ditto. * gcc.target/i386/avx10_1-14.c: Ditto. * gcc.target/i386/avx10_1-21.c: Ditto. * gcc.target/i386/avx10_1-22.c: Ditto. * gcc.target/i386/avx10_1-23.c: Ditto. * gcc.target/i386/avx10_1-24.c: Ditto. * gcc.target/i386/avx10_1-3.c: Ditto. * gcc.target/i386/avx10_1-5.c: Ditto. * gcc.target/i386/avx10_1-6.c: Ditto. * gcc.target/i386/avx10_1-8.c: Ditto. * gcc.target/i386/pr117946.c: Ditto. * gcc.target/i386/avx10_1-12.c: Adjust warning message. * gcc.target/i386/avx10_1-19.c: Ditto. * gcc.target/i386/avx10_1-17.c: Adjust to no-avx10.1-512. Diff: --- gcc/common/config/i386/i386-common.cc | 18 -- gcc/common/config/i386/i386-isas.h | 1 - gcc/config/i386/i386-options.cc | 3 +-- gcc/config/i386/i386.opt| 5 - gcc/doc/extend.texi | 11 --- gcc/doc/sourcebuild.texi| 5 + gcc/testsuite/gcc.target/i386/avx10-check.h | 2 +- gcc/testsuite/gcc.target/i386/avx10_1-1.c | 2 +- gcc/testsuite/gcc.target/i386/avx10_1-12.c | 2 +- gcc/testsuite/gcc.target/i386/avx10_1-13.c | 2 +- gcc/testsuite/gcc.target/i386/avx10_1-14.c | 2 +- gcc/testsuite/gcc.target/i386/avx10_1-17.c | 4 ++-- gcc/testsuite/gcc.target/i386/avx10_1-19.c | 2 +- gcc/testsuite/gcc.target/i386/avx10_1-21.c | 2 +- gcc/testsuite/gcc.target/i386/avx10_1-22.c | 2 +- gcc/testsuite/gcc.target/i386/avx10_1-23.c | 2 +- gcc/testsuite/gcc.target/i386/avx10_1-24.c | 2 +- gcc/testsuite/gcc.target/i386/avx10_1-3.c | 2 +- gcc/testsuite/gcc.target/i386/avx10_1-5.c | 2 +- gcc/testsuite/gcc.target/i386/avx10_1-6.c | 2 +- gcc/testsuite/gcc.target/i386/avx10_1-8.c | 2 +- gcc/testsuite/gcc.target/i386/pr117946.c| 2 +- 22 files changed, 31 insertions(+), 46 deletions(-) diff --git a/gcc/common/config/i386/i386-common.cc b/gcc/common/config/i386/i386-common.cc index 52ad1c5acd17..793d68456845 100644 --- a/gcc/common/config/i386/i386-common.cc +++ b/gcc/common/config/i386/i386-common.cc @@ -249,7 +249,7 @@ along with GCC; see the file COPYING3. If not see (OPTION_MASK_ISA2_AVXIFMA_UNSET | OPTION_MASK_ISA2_AVXVNNI_UNSET \ | OPTION_MASK_ISA2_AVXVNNIINT8_UNSET | OPTION_MASK_ISA2_AVXNECONVERT_UNSET \ | OPTION_MASK_ISA2_AVXVNNIINT16_UNSET | OPTION_MASK_ISA2_AVX512F_UNSET \ - | OPTION_MASK_ISA2_AVX10_1_256_UNSET) + | OPTION_MASK_ISA2_AVX10_1_UNSET) #define OPTION_MASK_ISA_AVX512F_UNSET \
[gcc r15-7585] i386: Regenerate i386.opt.urls
https://gcc.gnu.org/g:46276080e726421f6683db08e2bb42fd8d3367a6 commit r15-7585-g46276080e726421f6683db08e2bb42fd8d3367a6 Author: Haochen Jiang Date: Mon Feb 17 14:04:49 2025 +0800 i386: Regenerate i386.opt.urls We need to regenerate i386.opt.urls after removing -mavx10.1. gcc/ChangeLog: * config/i386/i386.opt.urls: Regenetated. Diff: --- gcc/config/i386/i386.opt.urls | 3 --- 1 file changed, 3 deletions(-) diff --git a/gcc/config/i386/i386.opt.urls b/gcc/config/i386/i386.opt.urls index 2f8ae60b1d06..5cb304d2a738 100644 --- a/gcc/config/i386/i386.opt.urls +++ b/gcc/config/i386/i386.opt.urls @@ -602,9 +602,6 @@ UrlSuffix(gcc/x86-Options.html#index-mavx10_002e1-256) mavx10.1-512 UrlSuffix(gcc/x86-Options.html#index-mavx10_002e1-512) -mavx10.1 -UrlSuffix(gcc/x86-Options.html#index-mavx10_002e1) - mavx10.2-256 UrlSuffix(gcc/x86-Options.html#index-mavx10_002e2-256)
[gcc r15-7575] Remove double output of attr->save.
https://gcc.gnu.org/g:db19dc70bac1d143977431736cd7141d1b98a2dc
commit r15-7575-gdb19dc70bac1d143977431736cd7141d1b98a2dc
Author: Thomas Koenig
Date: Sun Feb 16 12:24:13 2025 +0100
Remove double output of attr->save.
In the recent patch for dumping all attributes, there were
duplicates for attr->save, which is output via gfc_code2string
previously. This patch removes that double output.
gcc/fortran/ChangeLog:
* dump-parse-tree.cc (show_attr): Remove double output
of attr->save.
Diff:
---
gcc/fortran/dump-parse-tree.cc | 4
1 file changed, 4 deletions(-)
diff --git a/gcc/fortran/dump-parse-tree.cc b/gcc/fortran/dump-parse-tree.cc
index adc07da133e5..7726b708ad89 100644
--- a/gcc/fortran/dump-parse-tree.cc
+++ b/gcc/fortran/dump-parse-tree.cc
@@ -1017,10 +1017,6 @@ show_attr (symbol_attribute *attr, const char * module)
fputs (" AUTOMATIC", dumpfile);
if (attr->class_pointer)
fputs (" CLASS-POINTER", dumpfile);
- if (attr->save == SAVE_EXPLICIT)
-fputs (" SAVE-EXPLICIT", dumpfile);
- if (attr->save == SAVE_IMPLICIT)
-fputs (" SAVE-IMPLICIT", dumpfile);
if (attr->used_in_submodule)
fputs (" USED-IN-SUBMODULE", dumpfile);
if (attr->use_only)
[gcc r15-7574] c++: Add testcase for now fixed issue [PR117324]
https://gcc.gnu.org/g:6302f478433166f71464bc06caf5701c1800a7e7
commit r15-7574-g6302f478433166f71464bc06caf5701c1800a7e7
Author: Simon Martin
Date: Sun Feb 16 11:00:19 2025 +0100
c++: Add testcase for now fixed issue [PR117324]
The case in this PR does not ICE anymore after the fix for PR118319.
This patch simply adds the case to the testsuite.
PR c++/117324
gcc/testsuite/ChangeLog:
* g++.dg/parse/defarg19.C: New test.
Diff:
---
gcc/testsuite/g++.dg/parse/defarg19.C | 12
1 file changed, 12 insertions(+)
diff --git a/gcc/testsuite/g++.dg/parse/defarg19.C
b/gcc/testsuite/g++.dg/parse/defarg19.C
new file mode 100644
index ..df0819ae6a5e
--- /dev/null
+++ b/gcc/testsuite/g++.dg/parse/defarg19.C
@@ -0,0 +1,12 @@
+// PR c++/117324
+// { dg-do "compile" { target c++11 } }
+
+template
+struct ct1 {
+ friend void f(ct1, // { dg-error "specifies default" }
+ int = [](int p = [] {}) { return p; }(); ) // { dg-error
"expected|declares a non-template" }
+ {}
+};
+void test() {
+ f(ct1{}); // { dg-error "missing template arguments|not declared" "" {
target c++14_down } }
+}
[gcc r14-11315] i386: Deprecate -m[no-]avx10.1 and make -mno-avx10.1-512 to disable the whole AVX10.1
https://gcc.gnu.org/g:de562367d344758ea9264992e884f031d4435688 commit r14-11315-gde562367d344758ea9264992e884f031d4435688 Author: Haochen Jiang Date: Tue Feb 11 11:29:34 2025 +0800 i386: Deprecate -m[no-]avx10.1 and make -mno-avx10.1-512 to disable the whole AVX10.1 Based on the feedback we got, we would like to re-alias avx10.x to 512 bit in the future. This leaves the current avx10.1 alias to 256 bit inconsistent. Since it has been there for GCC 14.1 and GCC 14.2, we decide to deprecate avx10.1 alias. The current proposal is not adding it back in the future, but it might change if necessary. For -mno- options, it is confusing what it is disabling when it comes to avx10. Since there is barely usage enabling AVX10 with 512 bit then disabling it, we will only provide -mno-avx10.x options in the future, disabling the whole AVX10.x. If someone really wants to disable 512 bit after enabling it, -mavx10.x-512 -mno-avx10.x -mavx10.x-256 is the only way to do that since we also do not want to break the usual expression on -m- options enabling everything mentioned. However, for avx10.1, since we deprecated avx10.1, there is no reason we should have -mno-avx10.1. Thus, we need to keep -mno-avx10.1-[256,512]. To avoid confusion, we will make -mno-avx10.1-512 to disable the whole AVX10.1 set to match the future -mno-avx10.x. gcc/ChangeLog: * common/config/i386/i386-common.cc (OPTION_MASK_ISA2_AVX2_UNSET): Change AVX10.1 unset macro. (OPTION_MASK_ISA2_AVX10_1_256_UNSET): Removed. (OPTION_MASK_ISA2_AVX10_1_512_UNSET): Removed. (OPTION_MASK_ISA2_AVX10_1_UNSET): New. (ix86_handle_option): Adjust AVX10.1 unset macro. * common/config/i386/i386-isas.h: Remove avx10.1. * config/i386/i386-options.cc (ix86_valid_target_attribute_inner_p): Ditto. (ix86_option_override_internal): Adjust warning message. * config/i386/i386.opt: Remove mavx10.1. * config/i386/i386.opt.urls: Regenerated. * doc/extend.texi: Remove avx10.1 and adjust doc. * doc/sourcebuild.texi: Ditto. gcc/testsuite/ChangeLog: * gcc.target/i386/avx10_1-1.c: Change to avx10.1-256. * gcc.target/i386/avx10_1-13.c: Ditto. * gcc.target/i386/avx10_1-14.c: Ditto. * gcc.target/i386/avx10_1-21.c: Ditto. * gcc.target/i386/avx10_1-22.c: Ditto. * gcc.target/i386/avx10_1-23.c: Ditto. * gcc.target/i386/avx10_1-24.c: Ditto. * gcc.target/i386/avx10_1-3.c: Ditto. * gcc.target/i386/avx10_1-5.c: Ditto. * gcc.target/i386/avx10_1-6.c: Ditto. * gcc.target/i386/avx10_1-8.c: Ditto. * gcc.target/i386/avx10_1-12.c: Adjust warning message. * gcc.target/i386/avx10_1-19.c: Ditto. * gcc.target/i386/avx10_1-17.c: Adjust to no-avx10.1-512. Diff: --- gcc/common/config/i386/i386-common.cc | 15 +++ gcc/common/config/i386/i386-isas.h | 1 - gcc/config/i386/i386-options.cc| 3 +-- gcc/config/i386/i386.opt | 5 - gcc/config/i386/i386.opt.urls | 3 --- gcc/doc/extend.texi| 11 --- gcc/doc/sourcebuild.texi | 5 + gcc/testsuite/gcc.target/i386/avx10_1-1.c | 2 +- gcc/testsuite/gcc.target/i386/avx10_1-12.c | 2 +- gcc/testsuite/gcc.target/i386/avx10_1-13.c | 2 +- gcc/testsuite/gcc.target/i386/avx10_1-14.c | 2 +- gcc/testsuite/gcc.target/i386/avx10_1-17.c | 4 ++-- gcc/testsuite/gcc.target/i386/avx10_1-19.c | 2 +- gcc/testsuite/gcc.target/i386/avx10_1-21.c | 2 +- gcc/testsuite/gcc.target/i386/avx10_1-22.c | 2 +- gcc/testsuite/gcc.target/i386/avx10_1-23.c | 2 +- gcc/testsuite/gcc.target/i386/avx10_1-24.c | 2 +- gcc/testsuite/gcc.target/i386/avx10_1-3.c | 2 +- gcc/testsuite/gcc.target/i386/avx10_1-5.c | 2 +- gcc/testsuite/gcc.target/i386/avx10_1-6.c | 2 +- gcc/testsuite/gcc.target/i386/avx10_1-8.c | 2 +- 21 files changed, 28 insertions(+), 45 deletions(-) diff --git a/gcc/common/config/i386/i386-common.cc b/gcc/common/config/i386/i386-common.cc index e535a3d516db..73ba62467600 100644 --- a/gcc/common/config/i386/i386-common.cc +++ b/gcc/common/config/i386/i386-common.cc @@ -239,7 +239,7 @@ along with GCC; see the file COPYING3. If not see (OPTION_MASK_ISA2_AVXIFMA_UNSET | OPTION_MASK_ISA2_AVXVNNI_UNSET \ | OPTION_MASK_ISA2_AVXVNNIINT8_UNSET | OPTION_MASK_ISA2_AVXNECONVERT_UNSET \ | OPTION_MASK_ISA2_AVXVNNIINT16_UNSET | OPTION_MASK_ISA2_AVX512F_UNSET \ - | OPTION_MASK_ISA2_AVX10_1_256_UNSET) + | OPTION_MASK_ISA2_AVX10_1_UNSET) #define OPTION_MASK_ISA_AVX512F_UNSET \ (OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_AVX512CD_UNSET \ | OPTION_MASK_ISA_AVX512PF_UNSET | OPTION_MASK_ISA_AVX512
[gcc r14-11316] LoongArch: When -mfpu=none, '__loongarch_frecipe' shouldn't be defined [PR118843].
https://gcc.gnu.org/g:889fb66025cef4e434cc60e35add9f7406e38db7
commit r14-11316-g889fb66025cef4e434cc60e35add9f7406e38db7
Author: Lulu Cheng
Date: Wed Feb 12 11:50:50 2025 +0800
LoongArch: When -mfpu=none, '__loongarch_frecipe' shouldn't be defined
[PR118843].
PR target/118843
gcc/ChangeLog:
* config/loongarch/loongarch-c.cc
(loongarch_update_cpp_builtins): Fix macro definition issues.
gcc/testsuite/ChangeLog:
* gcc.target/loongarch/pr118843.c: New test.
(cherry picked from commit ee579b7c257468b9032ab4583ec455fa871d4428)
Diff:
---
gcc/config/loongarch/loongarch-c.cc | 7 +++
gcc/testsuite/gcc.target/loongarch/pr118843.c | 6 ++
2 files changed, 9 insertions(+), 4 deletions(-)
diff --git a/gcc/config/loongarch/loongarch-c.cc
b/gcc/config/loongarch/loongarch-c.cc
index c6763647cd13..591d1dabcdf9 100644
--- a/gcc/config/loongarch/loongarch-c.cc
+++ b/gcc/config/loongarch/loongarch-c.cc
@@ -85,9 +85,6 @@ loongarch_cpu_cpp_builtins (cpp_reader *pfile)
else
builtin_define ("__loongarch_frlen=0");
- if (TARGET_HARD_FLOAT && ISA_HAS_FRECIPE)
-builtin_define ("__loongarch_frecipe");
-
if (ISA_HAS_LSX)
{
builtin_define ("__loongarch_simd");
@@ -107,7 +104,9 @@ loongarch_cpu_cpp_builtins (cpp_reader *pfile)
int max_v_major = 1, max_v_minor = 0;
for (int i = 0; i < N_EVO_FEATURES; i++)
-if (la_target.isa.evolution & la_evo_feature_masks[i])
+if (la_target.isa.evolution & la_evo_feature_masks[i]
+ && (la_evo_feature_masks[i] != OPTION_MASK_ISA_FRECIPE
+ || TARGET_HARD_FLOAT))
{
builtin_define (la_evo_macro_name[i]);
diff --git a/gcc/testsuite/gcc.target/loongarch/pr118843.c
b/gcc/testsuite/gcc.target/loongarch/pr118843.c
new file mode 100644
index ..30372b8ffe6a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/loongarch/pr118843.c
@@ -0,0 +1,6 @@
+/* { dg-do preprocess } */
+/* { dg-options "-mfrecipe -mfpu=none" } */
+
+#ifdef __loongarch_frecipe
+#error __loongarch_frecipe should not be avaliable here
+#endif
[gcc r15-7586] Avoid shift wider than unsigned HOST_WIDE_INT on unsigned integer exponentiation.
https://gcc.gnu.org/g:b57e6e1b38cdaf7a982474d93ebede1cc30f1d46
commit r15-7586-gb57e6e1b38cdaf7a982474d93ebede1cc30f1d46
Author: Thomas Koenig
Date: Sun Feb 16 12:15:40 2025 +0100
Avoid shift wider than unsigned HOST_WIDE_INT on unsigned integer
exponentiation.
this patch is a variation of Jakub's patch in the PR, which
avoids overflow on the mask used for exponentiation and
fixes unsigned HOST_WIDE_INT. I tried testing this on
a POWER machine, but --with-build-config=bootstrap-ubsan
fails bootstrap there.
gcc/fortran/ChangeLog:
PR fortran/118862
* trans-expr.cc (gfc_conv_cst_int_power): Use functions for
unsigned wide integer.
(gfc_conv_cst_uint_power): Avoid generating the mask if it would
overflow an unsigned HOST_WIDE_INT. Format fixes.
Diff:
---
gcc/fortran/trans-expr.cc | 17 -
1 file changed, 8 insertions(+), 9 deletions(-)
diff --git a/gcc/fortran/trans-expr.cc b/gcc/fortran/trans-expr.cc
index 9d29fe751165..8a3e737a6a8f 100644
--- a/gcc/fortran/trans-expr.cc
+++ b/gcc/fortran/trans-expr.cc
@@ -3603,7 +3603,7 @@ gfc_conv_cst_int_power (gfc_se * se, tree lhs, tree rhs)
if (bit_size(rhs) < bit_size(lhs)) ! Checked here.
return lhs ** rhs;
- mask = (1 < bit_size(a) - 1) / 2;
+ mask = 1 << (bit_size(a) - 1) / 2;
return lhs ** (n & rhs);
}
if (rhs > bit_size(lhs)) ! Checked here.
@@ -3623,13 +3623,13 @@ gfc_conv_cst_uint_power (gfc_se * se, tree lhs, tree
rhs)
tree vartmp_odd[POWI_TABLE_SIZE], vartmp_even[POWI_TABLE_SIZE];
/* Anything ** 0 is one. */
- if (tree_int_cst_sgn (rhs) == 0)
+ if (integer_zerop (rhs))
{
se->expr = build_int_cst (type, 1);
return 1;
}
- if (!wi::fits_shwi_p (wrhs))
+ if (!wi::fits_uhwi_p (wrhs))
return 0;
n = wrhs.to_uhwi ();
@@ -3641,19 +3641,18 @@ gfc_conv_cst_uint_power (gfc_se * se, tree lhs, tree
rhs)
tmp, build_int_cst (type, 1));
lhs_prec = TYPE_PRECISION (type);
- rhs_prec = TYPE_PRECISION (TREE_TYPE(rhs));
+ rhs_prec = TYPE_PRECISION (TREE_TYPE (rhs));
- if (rhs_prec >= lhs_prec)
+ if (rhs_prec >= lhs_prec && lhs_prec <= HOST_BITS_PER_WIDE_INT)
{
- unsigned HOST_WIDE_INT mask;
- mask = (((unsigned HOST_WIDE_INT) 1) << (lhs_prec - 1)) - 1;
+ unsigned HOST_WIDE_INT mask = (HOST_WIDE_INT_1U << (lhs_prec - 1)) - 1;
n_odd = n & mask;
}
else
n_odd = n;
memset (vartmp_odd, 0, sizeof (vartmp_odd));
- vartmp_odd[0] = build_int_cst(type, 1);
+ vartmp_odd[0] = build_int_cst (type, 1);
vartmp_odd[1] = lhs;
odd_branch = gfc_conv_powi (se, n_odd, vartmp_odd);
even_branch = NULL_TREE;
@@ -3665,7 +3664,7 @@ gfc_conv_cst_uint_power (gfc_se * se, tree lhs, tree rhs)
if (n_odd != n)
{
memset (vartmp_even, 0, sizeof (vartmp_even));
- vartmp_even[0] = build_int_cst(type, 1);
+ vartmp_even[0] = build_int_cst (type, 1);
vartmp_even[1] = lhs;
even_branch = gfc_conv_powi (se, n, vartmp_even);
}
[gcc r15-7576] AVR: Diagnose unsupported built-ins in avr_resolve_overloaded_builtin.
https://gcc.gnu.org/g:7aee6b6a4a2b0f4cc5e2f3342051151e536e019a
commit r15-7576-g7aee6b6a4a2b0f4cc5e2f3342051151e536e019a
Author: Georg-Johann Lay
Date: Sat Feb 15 14:35:24 2025 +0100
AVR: Diagnose unsupported built-ins in avr_resolve_overloaded_builtin.
This patch executes avr_builtin_supported_p at a later time and in
avr_resolve_overloaded_builtin. This allows for better diagnostics
and avoids lto1 hiccups when a built-in decl is NULL_TREE.
gcc/
* config/avr/avr-protos.h (avr_builtin_supported_p): Remove.
* config/avr/avr.cc (avr_init_builtins): Don't initialize
non-available built-ins with NULL_TREE.
(avr_builtin_supported_p): Move to...
* config/avr/avr-c.cc: ...here.
(avr_resolve_overloaded_builtin): Run avr_builtin_supported_p.
Diff:
---
gcc/config/avr/avr-c.cc | 44
gcc/config/avr/avr-protos.h | 1 -
gcc/config/avr/avr.cc | 28 +++-
3 files changed, 43 insertions(+), 30 deletions(-)
diff --git a/gcc/config/avr/avr-c.cc b/gcc/config/avr/avr-c.cc
index f4236555bf6c..6f49d3f98a0b 100644
--- a/gcc/config/avr/avr-c.cc
+++ b/gcc/config/avr/avr-c.cc
@@ -45,16 +45,52 @@ enum avr_builtin_id
};
-/* Implement `TARGET_RESOLVE_OVERLOADED_PLUGIN'. */
+/* Some of our built-in functions are available for GNU-C only:
+ - Built-ins that use named address-spaces.
+ - Built-ins that use fixed-point types. */
+
+static bool
+avr_builtin_supported_p (location_t loc, avr_builtin_id bid)
+{
+ if (! lang_GNU_C () // Means "C" actually, not "GNU-C".
+ && bid >= AVR_FIRST_C_ONLY_BUILTIN_ID)
+{
+ if (loc != UNKNOWN_LOCATION)
+ error_at (loc, "built-in function is only supported for GNU-C");
+ return false;
+}
+
+ const bool uses_as = (bid == AVR_BUILTIN_FLASH_SEGMENT
+ || bid == AVR_BUILTIN_STRLEN_FLASH
+ || bid == AVR_BUILTIN_STRLEN_FLASHX
+ || bid == AVR_BUILTIN_STRLEN_MEMX);
+ if (AVR_TINY && uses_as)
+{
+ if (loc != UNKNOWN_LOCATION)
+ error_at (loc, "built-in function for named address-space is not"
+ " supported for reduced Tiny devices");
+ return false;
+}
+
+ return true;
+}
+
+
+/* Implement `TARGET_RESOLVE_OVERLOADED_BUILTIN'. */
static tree
avr_resolve_overloaded_builtin (location_t loc, tree fndecl, void *vargs, bool)
{
+ const avr_builtin_id bid = (avr_builtin_id) DECL_MD_FUNCTION_CODE (fndecl);
+
+ if (! avr_builtin_supported_p (loc, bid))
+return error_mark_node;
+
tree type0, type1, fold = NULL_TREE;
avr_builtin_id id = AVR_BUILTIN_COUNT;
vec &args = * (vec *) vargs;
- switch (DECL_MD_FUNCTION_CODE (fndecl))
+ switch (bid)
{
default:
break;
@@ -499,8 +535,8 @@ avr_cpu_cpp_builtins (cpp_reader *pfile)
/* Define builtin macros so that the user can easily query whether or
not a specific builtin is available. */
-#define DEF_BUILTIN(NAME, N_ARGS, TYPE, CODE, LIBNAME, ATTRS) \
- if (avr_builtin_supported_p (AVR_BUILTIN_ ## NAME))\
+#define DEF_BUILTIN(NAME, N_ARGS, TYPE, CODE, LIBNAME, ATTRS) \
+ if (avr_builtin_supported_p (UNKNOWN_LOCATION, AVR_BUILTIN_ ## NAME))
\
cpp_define (pfile, "__BUILTIN_AVR_" #NAME);
#include "builtins.def"
#undef DEF_BUILTIN
diff --git a/gcc/config/avr/avr-protos.h b/gcc/config/avr/avr-protos.h
index 6f37c48143ec..83137c7f6f63 100644
--- a/gcc/config/avr/avr-protos.h
+++ b/gcc/config/avr/avr-protos.h
@@ -21,7 +21,6 @@
extern bool avr_function_arg_regno_p (int r);
extern void avr_cpu_cpp_builtins (cpp_reader * pfile);
-extern bool avr_builtin_supported_p (unsigned id);
extern enum reg_class avr_regno_reg_class (int r);
extern void asm_globalize_label (FILE *file, const char *name);
extern void avr_adjust_reg_alloc_order (void);
diff --git a/gcc/config/avr/avr.cc b/gcc/config/avr/avr.cc
index e358a2e8b8da..7acd260aace7 100644
--- a/gcc/config/avr/avr.cc
+++ b/gcc/config/avr/avr.cc
@@ -15751,27 +15751,6 @@ avr_bdesc[AVR_BUILTIN_COUNT] =
};
-/* Some of our built-in function are available for GNU-C only:
- - Built-ins that use named address-spaces.
- - Built-ins that use fixed-point types. */
-
-bool
-avr_builtin_supported_p (unsigned id)
-{
- const bool uses_as = (id == AVR_BUILTIN_FLASH_SEGMENT
- || id == AVR_BUILTIN_STRLEN_FLASH
- || id == AVR_BUILTIN_STRLEN_FLASHX
- || id == AVR_BUILTIN_STRLEN_MEMX);
-
- // We don't support address-spaces on Reduced Tiny.
- if (AVR_TINY && uses_as)
-return false;
-
- return (lang_GNU_C ()
- || id < AVR_FIRST_C_ONLY_BUILTIN_ID);
-}
-
-
/* Implement `TARGET_BUILTIN_DECL'. */
static tree
@@ -15997,10 +15976,9 @@ avr_init_builtins (void)
char *name = (char *) alloca (1 + strlen (Name)); \
[gcc r15-7577] AVR: Don't asm output operations for unused result bytes.
https://gcc.gnu.org/g:d6a09ff8d81d22de2d8a701faa3fffe858638b1b
commit r15-7577-gd6a09ff8d81d22de2d8a701faa3fffe858638b1b
Author: Georg-Johann Lay
Date: Fri Feb 14 20:22:58 2025 +0100
AVR: Don't asm output operations for unused result bytes.
When REG_UNUSED notes indicate that some result bytes are not
used by the following code, then there's no need to asm out them.
The patch uses such notes for the asm out of AND, IOR, XOR, PLUS, MINUS.
gcc/
* config/avr/avr.cc (avr_result_regno_unused_p): New static
function.
(avr_out_bitop): Only output result bytes that are used.
(avr_out_plus_1): Same.
Diff:
---
gcc/config/avr/avr.cc | 58 ++-
1 file changed, 48 insertions(+), 10 deletions(-)
diff --git a/gcc/config/avr/avr.cc b/gcc/config/avr/avr.cc
index 7acd260aace7..d53453e25fdf 100644
--- a/gcc/config/avr/avr.cc
+++ b/gcc/config/avr/avr.cc
@@ -3506,6 +3506,25 @@ reg_unused_after (rtx_insn *insn, rtx reg)
}
+/* Return true when REGNO is set by INSN but not used by the following code.
+ The difference to reg_unused_after() is that reg_unused_after() returns
+ true for the entire result even when the result *IS* being used atfer. */
+
+static bool
+avr_result_regno_unused_p (rtx_insn *insn, unsigned regno)
+{
+ if (!insn || !single_set (insn) || regno >= REG_32)
+return false;
+
+ rtx dest = SET_DEST (single_set (insn));
+ if (!REG_P (dest) || !IN_RANGE (regno, REGNO (dest), END_REGNO (dest) - 1))
+return false;
+
+ return (avr_insn_has_reg_unused_note_p (insn, all_regs_rtx[regno])
+ || _reg_unused_after (insn, all_regs_rtx[regno], false));
+}
+
+
/* Fixme: This is a hack because secondary reloads don't works as expected.
Find an unused d-register to be used as scratch in INSN.
@@ -8720,7 +8739,7 @@ avr_out_add_msb (rtx_insn *insn, rtx *yop, rtx_code cmp,
int *plen)
/* Output addition of register XOP[0] and compile time constant XOP[2].
- INSN is a single_set insn or an insn pattern.
+ XINSN is a single_set insn or an insn pattern.
CODE == PLUS: perform addition by using ADD instructions or
CODE == MINUS: perform addition by using SUB instructions:
@@ -8746,9 +8765,13 @@ avr_out_add_msb (rtx_insn *insn, rtx *yop, rtx_code cmp,
int *plen)
fixed-point rounding, cf. `avr_out_round'. */
static void
-avr_out_plus_1 (rtx insn, rtx *xop, int *plen, rtx_code code,
+avr_out_plus_1 (rtx xinsn, rtx *xop, int *plen, rtx_code code,
rtx_code code_sat, int sign, bool out_label)
{
+ rtx_insn *insn = xinsn && INSN_P (xinsn)
+? as_a (xinsn)
+: nullptr;
+
/* MODE of the operation. */
machine_mode mode = GET_MODE (xop[0]);
@@ -8758,6 +8781,11 @@ avr_out_plus_1 (rtx insn, rtx *xop, int *plen, rtx_code
code,
/* Number of bytes to operate on. */
int n_bytes = GET_MODE_SIZE (mode);
+ int regno0 = REGNO (xop[0]);
+ if (optimize && code_sat == UNKNOWN)
+while (n_bytes && avr_result_regno_unused_p (insn, regno0 + n_bytes - 1))
+ n_bytes -= 1;
+
/* Value (0..0xff) held in clobber register op[3] or -1 if unknown. */
int clobber_val = -1;
@@ -8782,14 +8810,16 @@ avr_out_plus_1 (rtx insn, rtx *xop, int *plen, rtx_code
code,
if (REG_P (xop[2]))
{
- if (REGNO (xop[0]) != REGNO (xop[2])
+ if (optimize
+ && REGNO (xop[0]) != REGNO (xop[2])
&& reg_overlap_mentioned_p (xop[0], xop[2]))
{
/* PR118878: Paradoxical SUBREGs may result in overlapping
registers. The assumption is that the overlapping part
is unused garbage. */
gcc_assert (n_bytes <= 4);
- n_bytes = std::abs ((int) REGNO (xop[0]) - (int) REGNO (xop[2]));
+ int delta = (int) REGNO (xop[0]) - (int) REGNO (xop[2]);
+ n_bytes = std::min (n_bytes, std::abs (delta));
}
for (int i = 0; i < n_bytes; i++)
@@ -8898,8 +8928,8 @@ avr_out_plus_1 (rtx insn, rtx *xop, int *plen, rtx_code
code,
&& frame_pointer_needed
&& REGNO (xop[0]) == FRAME_POINTER_REGNUM)
{
- if (INSN_P (insn)
- && _reg_unused_after (as_a (insn), xop[0], false))
+ if (insn
+ && _reg_unused_after (insn, xop[0], false))
return;
if (AVR_HAVE_8BIT_SP)
@@ -8994,7 +9024,7 @@ avr_out_plus_1 (rtx insn, rtx *xop, int *plen, rtx_code
code,
We have to compute A = A B where A is a register and
B is a register or a non-zero compile time constant CONST.
A is register class "r" if unsigned && B is REG. Otherwise, A is in "d".
- B stands for the original operand $2 in INSN. In the case of B = CONST,
+ B stands for the original operand $2 in XINSN. In the case of B = CONST,
SIGN in { -1, 1 } is the sign of B. Otherwise, SIGN is 0.
CODE is the instruction flavor we use in the asm sequence to perform .
@@ -9624,13 +9654,17 @@ avr
[gcc r15-7579] [PR target/118248] Avoid bogus alloca call in RISC-V backend
https://gcc.gnu.org/g:68e74199c61c5ad81ffe37e41cd62d0d7415b3ab
commit r15-7579-g68e74199c61c5ad81ffe37e41cd62d0d7415b3ab
Author: Jakub Jelinek
Date: Sun Feb 16 11:19:20 2025 -0700
[PR target/118248] Avoid bogus alloca call in RISC-V backend
This is Jakub's patch and Ian's testcase for the slightly vexing fault
building
the D runtime with an s390x-x-riscv cross compiler.
The core issue is we're allocating a vector to hold temporary registers
unconditionally, including cases where the vector isn't needed because the
loop
isn't going to iterate.
In the cases where the vector isn't needed the length is computed with an
expression (x / y) - 1 where x / y will be zero. The alloca(-1) on the s390
platform triggers a fault. We haven't seen the fault with an x86 cross,
but we
can certainly see the bogus value being passed to alloca with a debugger.
Jakub patch just conditionalizes the whole block in a sensible way. So it
looks larger than it really is. I thought it might be better to do a bit of
manual CSE on this code to make it even more obvious, but I think we're
ultimately OK here.
Ian provided the testcase, collapsed down into equivalent C code. Again, it
doesn't fault on an x86-x-riscv, but I can see the incorrect behavior with a
debugger.
And a shout-out to Stefan for providing a docker based reproducer, it really
helped track this down.
PR target/118248
gcc/
* config/riscv/riscv-string.cc (riscv_block_move_straight): Only
allocate REGS buffer if it will be needed.
gcc/testsuite
* gcc.target/riscv/pr118248.c: New test.
Diff:
---
gcc/config/riscv/riscv-string.cc | 31 ++-
gcc/testsuite/gcc.target/riscv/pr118248.c | 26 ++
2 files changed, 44 insertions(+), 13 deletions(-)
diff --git a/gcc/config/riscv/riscv-string.cc b/gcc/config/riscv/riscv-string.cc
index 408eb07e87f3..90801899ec8e 100644
--- a/gcc/config/riscv/riscv-string.cc
+++ b/gcc/config/riscv/riscv-string.cc
@@ -804,7 +804,7 @@ static void
riscv_block_move_straight (rtx dest, rtx src, unsigned HOST_WIDE_INT length,
unsigned HOST_WIDE_INT align)
{
- unsigned HOST_WIDE_INT offset, delta;
+ unsigned HOST_WIDE_INT offset = 0, delta;
unsigned HOST_WIDE_INT bits;
int i;
enum machine_mode mode;
@@ -815,20 +815,25 @@ riscv_block_move_straight (rtx dest, rtx src, unsigned
HOST_WIDE_INT length,
mode = mode_for_size (bits, MODE_INT, 0).require ();
delta = bits / BITS_PER_UNIT;
- /* Allocate a buffer for the temporary registers. */
- regs = XALLOCAVEC (rtx, length / delta - 1);
-
- /* Load as many BITS-sized chunks as possible. Use a normal load if
- the source has enough alignment, otherwise use left/right pairs. */
- for (offset = 0, i = 0; offset + 2 * delta <= length; offset += delta, i++)
+ if (2 * delta <= length)
{
- regs[i] = gen_reg_rtx (mode);
- riscv_emit_move (regs[i], adjust_address (src, mode, offset));
-}
+ /* Allocate a buffer for the temporary registers. */
+ regs = XALLOCAVEC (rtx, length / delta - 1);
+
+ /* Load as many BITS-sized chunks as possible. Use a normal load if
+the source has enough alignment, otherwise use left/right pairs. */
+ for (offset = 0, i = 0; offset + 2 * delta <= length;
+ offset += delta, i++)
+ {
+ regs[i] = gen_reg_rtx (mode);
+ riscv_emit_move (regs[i], adjust_address (src, mode, offset));
+ }
- /* Copy the chunks to the destination. */
- for (offset = 0, i = 0; offset + 2 * delta <= length; offset += delta, i++)
-riscv_emit_move (adjust_address (dest, mode, offset), regs[i]);
+ /* Copy the chunks to the destination. */
+ for (offset = 0, i = 0; offset + 2 * delta <= length;
+ offset += delta, i++)
+ riscv_emit_move (adjust_address (dest, mode, offset), regs[i]);
+}
/* Mop up any left-over bytes. */
if (offset < length)
diff --git a/gcc/testsuite/gcc.target/riscv/pr118248.c
b/gcc/testsuite/gcc.target/riscv/pr118248.c
new file mode 100644
index ..05bf002abac8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/pr118248.c
@@ -0,0 +1,26 @@
+/* This does not fault with an x86 cross to risc-v, but does
+ with s390 cross to risc-v, probably due to rounding of the
+ argument to the alloca call within the risc-v backend. */
+/* { dg-do compile } */
+struct char100
+{
+char data[100];
+};
+
+struct s118248
+{
+void **vtbl;
+struct char100 data;
+};
+
+void sink(struct char100 *buf);
+
+struct s118248 *pr118248(struct s118248 *pthis)
+{
+struct char100 buf;
+sink(&buf);
+pthis->data = buf;
+return pthis;
+}
+
+
