[gcc(refs/users/meissner/heads/work191-bugs)] Update ChangeLog.*
https://gcc.gnu.org/g:450041aba3e374d040b406b61d0d2a68f49f3c81 commit 450041aba3e374d040b406b61d0d2a68f49f3c81 Author: Michael Meissner Date: Fri Jan 24 12:29:30 2025 -0500 Update ChangeLog.* Diff: --- gcc/ChangeLog.bugs | 7 ++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog.bugs b/gcc/ChangeLog.bugs index bba5ce2deb76..ebcb80cf743c 100644 --- a/gcc/ChangeLog.bugs +++ b/gcc/ChangeLog.bugs @@ -1,4 +1,4 @@ - Branch work191-bugs, patch #210 + Branch work191-bugs, patch #211 Fix PR 118541, do not generate unordered fp cmoves. @@ -15,6 +15,11 @@ gcc/ * config/rs6000/rs6000.h (REVERSE_CONDITION): Likewise. * config/rs6000/rs6000.md (reverse_branch_comparison): Likewise. +gcc/testsuite/ + + PR target/118541 + * gcc.target/powerpc/pr118541.c: New test. + Branch work191-bugs, patch #210 was reverted Branch work191-bugs, patch #202
[gcc r15-7183] testsuite: arm: Use -std=c17 for gcc.target/arm/thumb-bitfld1.c
https://gcc.gnu.org/g:41a6d4f8aa659dd88fce2d831306affc91ba4d53
commit r15-7183-g41a6d4f8aa659dd88fce2d831306affc91ba4d53
Author: Torbjörn SVENSSON
Date: Sun Jan 19 16:28:05 2025 +0100
testsuite: arm: Use -std=c17 for gcc.target/arm/thumb-bitfld1.c
Using -std=c17 avoids excess errors like:
.../thumb-bitfld1.c:15:1: warning: old-style function definition
[-Wold-style-definition]
gcc/testsuite/ChangeLog:
* gcc.target/arm/thumb-bitfld1.c: Use -std=c17.
Signed-off-by: Torbjörn SVENSSON
Diff:
---
gcc/testsuite/gcc.target/arm/thumb-bitfld1.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/testsuite/gcc.target/arm/thumb-bitfld1.c
b/gcc/testsuite/gcc.target/arm/thumb-bitfld1.c
index 37630f1a1f7a..3548e0976115 100644
--- a/gcc/testsuite/gcc.target/arm/thumb-bitfld1.c
+++ b/gcc/testsuite/gcc.target/arm/thumb-bitfld1.c
@@ -1,6 +1,6 @@
/* { dg-do compile } */
/* { dg-require-effective-target arm_thumb1_ok } */
-/* { dg-options "-O1 -mthumb" } */
+/* { dg-options "-O1 -mthumb -std=c17" } */
struct foo
{
[gcc r15-7182] testsuite: arm: Use -Os -fno-math-errno in vfp-1.c [PR116448]
https://gcc.gnu.org/g:062c04c45b2156b27ddc3b6541d8484e9db63bc3
commit r15-7182-g062c04c45b2156b27ddc3b6541d8484e9db63bc3
Author: Torbjörn SVENSSON
Date: Fri Jan 24 17:56:51 2025 +0100
testsuite: arm: Use -Os -fno-math-errno in vfp-1.c [PR116448]
gcc/testsuite/ChangeLog:
PR testsuite/116448
* gcc.target/arm/vfp-1.c: Use -Os -fno-math-errno.
Signed-off-by: Torbjörn SVENSSON
Diff:
---
gcc/testsuite/gcc.target/arm/vfp-1.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/testsuite/gcc.target/arm/vfp-1.c
b/gcc/testsuite/gcc.target/arm/vfp-1.c
index b4694c786305..5bb675e566e8 100644
--- a/gcc/testsuite/gcc.target/arm/vfp-1.c
+++ b/gcc/testsuite/gcc.target/arm/vfp-1.c
@@ -1,6 +1,6 @@
/* { dg-do compile } */
/* { dg-require-effective-target arm_fp_dp_ok } */
-/* { dg-options "-O2 -ffp-contract=off" } */
+/* { dg-options "-Os -fno-math-errno -ffp-contract=off" } */
/* { dg-add-options arm_fp_dp } */
/* { dg-skip-if "need fp instructions" { *-*-* } { "-mfloat-abi=soft" } { "" }
} */
[gcc r14-11243] testsuite: arm: Use -Os -fno-math-errno in vfp-1.c [PR116448]
https://gcc.gnu.org/g:1836a65efc4c76284a6b1e18a9542acb0b9e0517
commit r14-11243-g1836a65efc4c76284a6b1e18a9542acb0b9e0517
Author: Torbjörn SVENSSON
Date: Fri Jan 24 17:56:51 2025 +0100
testsuite: arm: Use -Os -fno-math-errno in vfp-1.c [PR116448]
gcc/testsuite/ChangeLog:
PR testsuite/116448
* gcc.target/arm/vfp-1.c: Use -Os -fno-math-errno.
Signed-off-by: Torbjörn SVENSSON
(cherry picked from commit 062c04c45b2156b27ddc3b6541d8484e9db63bc3)
Diff:
---
gcc/testsuite/gcc.target/arm/vfp-1.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/testsuite/gcc.target/arm/vfp-1.c
b/gcc/testsuite/gcc.target/arm/vfp-1.c
index b4694c786305..5bb675e566e8 100644
--- a/gcc/testsuite/gcc.target/arm/vfp-1.c
+++ b/gcc/testsuite/gcc.target/arm/vfp-1.c
@@ -1,6 +1,6 @@
/* { dg-do compile } */
/* { dg-require-effective-target arm_fp_dp_ok } */
-/* { dg-options "-O2 -ffp-contract=off" } */
+/* { dg-options "-Os -fno-math-errno -ffp-contract=off" } */
/* { dg-add-options arm_fp_dp } */
/* { dg-skip-if "need fp instructions" { *-*-* } { "-mfloat-abi=soft" } { "" }
} */
[gcc r15-7199] aarch64: Add +cpa feature flag
https://gcc.gnu.org/g:12b7220dc5beafaf9c738b473e046ed66e49a52a
commit r15-7199-g12b7220dc5beafaf9c738b473e046ed66e49a52a
Author: Andrew Carlotti
Date: Fri Jan 24 11:00:41 2025 +
aarch64: Add +cpa feature flag
This doesn't enable anything within the compiler, but this allows the
flag to be passed the assembler. There also doesn't appear to be a
kernel cpuinfo name yet.
gcc/ChangeLog:
* config/aarch64/aarch64-arches.def (V9_5A): Add CPA.
* config/aarch64/aarch64-option-extensions.def (CPA): New.
* doc/invoke.texi: Document +cpa.
Diff:
---
gcc/config/aarch64/aarch64-arches.def| 2 +-
gcc/config/aarch64/aarch64-option-extensions.def | 2 ++
gcc/doc/invoke.texi | 4 +++-
3 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/gcc/config/aarch64/aarch64-arches.def
b/gcc/config/aarch64/aarch64-arches.def
index dacb7b6f37a3..34a792d69510 100644
--- a/gcc/config/aarch64/aarch64-arches.def
+++ b/gcc/config/aarch64/aarch64-arches.def
@@ -46,6 +46,6 @@ AARCH64_ARCH("armv9.1-a", generic_armv9_a, V9_1A,
9, (V8_6A, V9A))
AARCH64_ARCH("armv9.2-a", generic_armv9_a, V9_2A, 9, (V8_7A, V9_1A))
AARCH64_ARCH("armv9.3-a", generic_armv9_a, V9_3A, 9, (V8_8A, V9_2A))
AARCH64_ARCH("armv9.4-a", generic_armv9_a, V9_4A, 9, (V8_9A, V9_3A))
-AARCH64_ARCH("armv9.5-a", generic_armv9_a, V9_5A, 9, (V9_4A,
FAMINMAX, LUT))
+AARCH64_ARCH("armv9.5-a", generic_armv9_a, V9_5A, 9, (V9_4A, CPA,
FAMINMAX, LUT))
#undef AARCH64_ARCH
diff --git a/gcc/config/aarch64/aarch64-option-extensions.def
b/gcc/config/aarch64/aarch64-option-extensions.def
index a1133accfce5..cc42bd518dca 100644
--- a/gcc/config/aarch64/aarch64-option-extensions.def
+++ b/gcc/config/aarch64/aarch64-option-extensions.def
@@ -275,6 +275,8 @@ AARCH64_OPT_EXTENSION("ssve-fp8dot2", SSVE_FP8DOT2,
(SSVE_FP8DOT4), (), (), "sme
AARCH64_OPT_EXTENSION("lut", LUT, (SIMD), (), (), "lut")
+AARCH64_OPT_EXTENSION("cpa", CPA, (), (), (), "")
+
#undef AARCH64_OPT_FMV_EXTENSION
#undef AARCH64_OPT_EXTENSION
#undef AARCH64_FMV_FEATURE
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index c8721064f91e..e54a287d 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -21672,7 +21672,7 @@ and the features that they enable by default:
@item @samp{armv9.2-a} @tab Armv9.2-A @tab @samp{armv9.1-a}, @samp{+wfxt},
@samp{+xs}
@item @samp{armv9.3-a} @tab Armv9.3-A @tab @samp{armv9.2-a}, @samp{+mops}
@item @samp{armv9.4-a} @tab Armv9.4-A @tab @samp{armv9.3-a}
-@item @samp{armv9.5-a} @tab Armv9.4-A @tab @samp{armv9.4-a}, @samp{+faminmax},
@samp{+lut}
+@item @samp{armv9.5-a} @tab Armv9.4-A @tab @samp{armv9.4-a}, @samp{cpa},
@samp{+faminmax}, @samp{+lut}
@item @samp{armv8-r} @tab Armv8-R @tab @samp{armv8-r}
@end multitable
@@ -22085,6 +22085,8 @@ extension in streaming mode.
Enable the Floating Point Absolute Maximum/Minimum extension.
@item lut
Enable the Lookup Table extension.
+@item cpa
+Enable the Checked Pointer Arithmetic instructions.
@item sve-b16b16
Enable the SVE non-widening brain floating-point (@code{bf16}) extension.
This only has an effect when @code{sve2} or @code{sme2} are also enabled.
[gcc(refs/users/meissner/heads/work191-bugs)] Fix PR 118541, do not generate unordered fp cmoves.
https://gcc.gnu.org/g:1335fcb077113c83f9eb4b40b996be41bee80a74
commit 1335fcb077113c83f9eb4b40b996be41bee80a74
Author: Michael Meissner
Date: Fri Jan 24 15:06:52 2025 -0500
Fix PR 118541, do not generate unordered fp cmoves.
2025-01-24 Michael Meissner
gcc/
PR target/118541
* config/rs6000/rs6000-protos.h (REVERSE_COND_ORDERED_OK): New
macro.
(REVERSE_COND_NO_ORDERED): Likewise.
(rs6000_reverse_condition): Add argument.
* config/rs6000/rs6000.cc (rs6000_reverse_condition): Do not allow
ordered comparisons to be reversed for floating point cmoves.
(rs6000_emit_sCOND): Adjust rs6000_reverse_condition call.
* config/rs6000/rs6000.h (REVERSE_CONDITION): Likewise.
* config/rs6000/rs6000.md (reverse_branch_comparison): Name insn.
Adjust rs6000_reverse_condition call.
gcc/testsuite/
PR target/118541
* gcc.target/powerpc/pr118541.c: New test.
Diff:
---
gcc/config/rs6000/rs6000-protos.h | 6 -
gcc/config/rs6000/rs6000.cc | 23
gcc/config/rs6000/rs6000.h | 10 +--
gcc/config/rs6000/rs6000.md | 24 ++---
gcc/testsuite/gcc.target/powerpc/pr118541.c | 42 +
5 files changed, 88 insertions(+), 17 deletions(-)
diff --git a/gcc/config/rs6000/rs6000-protos.h
b/gcc/config/rs6000/rs6000-protos.h
index 4619142d197b..112332660d3b 100644
--- a/gcc/config/rs6000/rs6000-protos.h
+++ b/gcc/config/rs6000/rs6000-protos.h
@@ -114,8 +114,12 @@ extern const char *rs6000_sibcall_template (rtx *,
unsigned int);
extern const char *rs6000_indirect_call_template (rtx *, unsigned int);
extern const char *rs6000_indirect_sibcall_template (rtx *, unsigned int);
extern const char *rs6000_pltseq_template (rtx *, int);
+
+#define REVERSE_COND_ORDERED_OKfalse
+#define REVERSE_COND_NO_ORDEREDtrue
+
extern enum rtx_code rs6000_reverse_condition (machine_mode,
- enum rtx_code);
+ enum rtx_code, bool);
extern rtx rs6000_emit_eqne (machine_mode, rtx, rtx, rtx);
extern rtx rs6000_emit_fp_cror (rtx_code, machine_mode, rtx);
extern void rs6000_emit_sCOND (machine_mode, rtx[]);
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index f9f9a0b931db..eaf79435ec32 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -15360,15 +15360,25 @@ rs6000_print_patchable_function_entry (FILE *file,
}
enum rtx_code
-rs6000_reverse_condition (machine_mode mode, enum rtx_code code)
+rs6000_reverse_condition (machine_mode mode,
+ enum rtx_code code,
+ bool no_ordered)
{
/* Reversal of FP compares takes care -- an ordered compare
- becomes an unordered compare and vice versa. */
+ becomes an unordered compare and vice versa.
+
+ However, this is not safe for ordered comparisons (i.e. for isgreater,
+ etc.) starting with the power9 because ifcvt.cc will want to create a fp
+ cmove, and the x{s,v}cmp{eq,gt,ge}{dp,qp} instructions will trap if one of
+ the arguments is a signalling NaN. */
+
if (mode == CCFPmode
&& (!flag_finite_math_only
|| code == UNLT || code == UNLE || code == UNGT || code == UNGE
|| code == UNEQ || code == LTGT))
-return reverse_condition_maybe_unordered (code);
+return (no_ordered
+ ? UNKNOWN
+ : reverse_condition_maybe_unordered (code));
else
return reverse_condition (code);
}
@@ -15980,11 +15990,14 @@ rs6000_emit_sCOND (machine_mode mode, rtx operands[])
rtx not_result = gen_reg_rtx (CCEQmode);
rtx not_op, rev_cond_rtx;
machine_mode cc_mode;
+ enum rtx_code rev;
cc_mode = GET_MODE (XEXP (condition_rtx, 0));
- rev_cond_rtx = gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode,
cond_code),
-SImode, XEXP (condition_rtx, 0),
const0_rtx);
+ rev = rs6000_reverse_condition (cc_mode, cond_code,
+ REVERSE_COND_ORDERED_OK);
+ rev_cond_rtx = gen_rtx_fmt_ee (rev, SImode, XEXP (condition_rtx, 0),
+const0_rtx);
not_op = gen_rtx_COMPARE (CCEQmode, rev_cond_rtx, const0_rtx);
emit_insn (gen_rtx_SET (not_result, not_op));
condition_rtx = gen_rtx_EQ (VOIDmode, not_result, const0_rtx);
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index ec08c96d0f67..c595d7138bcd 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -1812,11 +1812,17 @@ extern scalar_int_mode rs6000_pmode;
/* Can the condition code MODE be safely reversed? This is safe in
all cases on this port, because at present it doesn't use the
- trapping FP comparis
[gcc(refs/users/meissner/heads/work191-bugs)] Update ChangeLog.*
https://gcc.gnu.org/g:ac8f22c88a0804c657f134481044b51ec2d4af31 commit ac8f22c88a0804c657f134481044b51ec2d4af31 Author: Michael Meissner Date: Fri Jan 24 15:08:28 2025 -0500 Update ChangeLog.* Diff: --- gcc/ChangeLog.bugs | 8 +--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/gcc/ChangeLog.bugs b/gcc/ChangeLog.bugs index 2effbb957737..0e7e43a3afa8 100644 --- a/gcc/ChangeLog.bugs +++ b/gcc/ChangeLog.bugs @@ -1,4 +1,4 @@ - Branch work191-bugs, patch #212 + Branch work191-bugs, patch #213 Fix PR 118541, do not generate unordered fp cmoves. @@ -7,8 +7,9 @@ Fix PR 118541, do not generate unordered fp cmoves. gcc/ PR target/118541 - * config/rs6000/rs6000-protos.h (rs6000_reverse_condition): Add - argument. + * config/rs6000/rs6000-protos.h (REVERSE_COND_ORDERED_OK): New macro. + (REVERSE_COND_NO_ORDERED): Likewise. + (rs6000_reverse_condition): Add argument. * config/rs6000/rs6000.cc (rs6000_reverse_condition): Do not allow ordered comparisons to be reversed for floating point cmoves. (rs6000_emit_sCOND): Adjust rs6000_reverse_condition call. @@ -21,6 +22,7 @@ gcc/testsuite/ PR target/118541 * gcc.target/powerpc/pr118541.c: New test. + Branch work191-bugs, patch #212 was reverted Branch work191-bugs, patch #211 was reverted Branch work191-bugs, patch #210 was reverted
[gcc r14-11245] Fortran: do not copy back for parameter actual arguments [PR81978]
https://gcc.gnu.org/g:d4df61dc6ed90e6614db213119858adde939fc97
commit r14-11245-gd4df61dc6ed90e6614db213119858adde939fc97
Author: Harald Anlauf
Date: Sun Jan 19 21:06:56 2025 +0100
Fortran: do not copy back for parameter actual arguments [PR81978]
When an array is packed for passing as an actual argument, and the array
has the PARAMETER attribute (i.e., it is a named constant that can reside
in read-only memory), do not copy back (unpack) from the temporary.
PR fortran/81978
gcc/fortran/ChangeLog:
* trans-array.cc (gfc_conv_array_parameter): Do not copy back data
if actual array parameter has the PARAMETER attribute.
* trans-expr.cc (gfc_conv_subref_array_arg): Likewise.
gcc/testsuite/ChangeLog:
* gfortran.dg/pr81978.f90: New test.
(cherry picked from commit 0d1e62b83561baa185bf080515750a89dd3ac410)
Diff:
---
gcc/fortran/trans-array.cc| 10 +++-
gcc/fortran/trans-expr.cc | 11 +++-
gcc/testsuite/gfortran.dg/pr81978.f90 | 107 ++
3 files changed, 124 insertions(+), 4 deletions(-)
diff --git a/gcc/fortran/trans-array.cc b/gcc/fortran/trans-array.cc
index d9aaa9bceae4..61f641aa4918 100644
--- a/gcc/fortran/trans-array.cc
+++ b/gcc/fortran/trans-array.cc
@@ -8653,6 +8653,7 @@ gfc_conv_array_parameter (gfc_se * se, gfc_expr * expr,
bool g77,
bool good_allocatable;
bool ultimate_ptr_comp;
bool ultimate_alloc_comp;
+ bool readonly;
gfc_symbol *sym;
stmtblock_t block;
gfc_ref *ref;
@@ -9007,8 +9008,13 @@ gfc_conv_array_parameter (gfc_se * se, gfc_expr * expr,
bool g77,
gfc_start_block (&block);
- /* Copy the data back. */
- if (fsym == NULL || fsym->attr.intent != INTENT_IN)
+ /* Copy the data back. If input expr is read-only, e.g. a PARAMETER
+array, copying back modified values is undefined behavior. */
+ readonly = (expr->expr_type == EXPR_VARIABLE
+ && expr->symtree
+ && expr->symtree->n.sym->attr.flavor == FL_PARAMETER);
+
+ if ((fsym == NULL || fsym->attr.intent != INTENT_IN) && !readonly)
{
tmp = build_call_expr_loc (input_location,
gfor_fndecl_in_unpack, 2, desc, ptr);
diff --git a/gcc/fortran/trans-expr.cc b/gcc/fortran/trans-expr.cc
index 8e74fbfb257d..1efe435f397f 100644
--- a/gcc/fortran/trans-expr.cc
+++ b/gcc/fortran/trans-expr.cc
@@ -5028,6 +5028,7 @@ gfc_conv_subref_array_arg (gfc_se *se, gfc_expr * expr,
int g77,
gfc_se work_se;
gfc_se *parmse;
bool pass_optional;
+ bool readonly;
pass_optional = fsym && fsym->attr.optional && sym && sym->attr.optional;
@@ -5244,8 +5245,14 @@ gfc_conv_subref_array_arg (gfc_se *se, gfc_expr * expr,
int g77,
/* Wrap the whole thing up by adding the second loop to the post-block
and following it by the post-block of the first loop. In this way,
- if the temporary needs freeing, it is done after use! */
- if (intent != INTENT_IN)
+ if the temporary needs freeing, it is done after use!
+ If input expr is read-only, e.g. a PARAMETER array, copying back
+ modified values is undefined behavior. */
+ readonly = (expr->expr_type == EXPR_VARIABLE
+ && expr->symtree
+ && expr->symtree->n.sym->attr.flavor == FL_PARAMETER);
+
+ if ((intent != INTENT_IN) && !readonly)
{
gfc_add_block_to_block (&parmse->post, &loop2.pre);
gfc_add_block_to_block (&parmse->post, &loop2.post);
diff --git a/gcc/testsuite/gfortran.dg/pr81978.f90
b/gcc/testsuite/gfortran.dg/pr81978.f90
new file mode 100644
index ..b377eef7a16c
--- /dev/null
+++ b/gcc/testsuite/gfortran.dg/pr81978.f90
@@ -0,0 +1,107 @@
+! { dg-do run }
+! PR fortran/81978 - do not copy back for parameter actual arguments
+
+module test_mod
+ implicit none
+
+ type pp_struct
+ character(10) :: name
+ real :: value
+ end type pp_struct
+
+ type(pp_struct), parameter :: pp(4) = [ &
+ pp_struct('one', 1.), &
+ pp_struct('two', 2.), &
+ pp_struct('three', 3.), &
+ pp_struct('four', 4.) ]
+
+contains
+
+ subroutine match_word (names)
+character(*):: names(:)
+ end subroutine match_word
+
+ subroutine sub0 (a)
+real:: a(:)
+ end
+
+ subroutine sub1 (a, n)
+integer, intent(in) :: n
+real:: a(n)
+ end
+
+ subroutine subx (a)
+real:: a(..)
+ end
+end module
+
+program test
+ use test_mod
+ implicit none
+ integer :: i, n
+ integer, parameter :: m = 8
+ real,parameter :: x(m) = [(i,i=1,m)]
+
+ n = size (x)
+ call sub0 (x)
+ call sub1 (x, n)
+ call sub2 (x, n)
+ call subx (x)
+
+ i = 1
+ call sub0 (x(1::i))
+ call sub1 (x(1::i), n)
+ call sub2 (x(1::i), n)
+ call subx (x(1::i))
+
+ n = size (x(1::2))
+ call sub0 (x(1::2))
+ call sub1 (x(1::2), n)
+ call
[gcc(refs/users/meissner/heads/work191-bugs)] Revert changes
https://gcc.gnu.org/g:1d0b394d4cf3d0f128efbf76fbd58617b667493b
commit 1d0b394d4cf3d0f128efbf76fbd58617b667493b
Author: Michael Meissner
Date: Fri Jan 24 16:08:17 2025 -0500
Revert changes
Diff:
---
gcc/config/rs6000/rs6000-protos.h | 6 +
gcc/config/rs6000/rs6000.cc | 23
gcc/config/rs6000/rs6000.h | 10 ++-
gcc/config/rs6000/rs6000.md | 24 +++--
gcc/testsuite/gcc.target/powerpc/pr118541.c | 42 -
5 files changed, 17 insertions(+), 88 deletions(-)
diff --git a/gcc/config/rs6000/rs6000-protos.h
b/gcc/config/rs6000/rs6000-protos.h
index 112332660d3b..4619142d197b 100644
--- a/gcc/config/rs6000/rs6000-protos.h
+++ b/gcc/config/rs6000/rs6000-protos.h
@@ -114,12 +114,8 @@ extern const char *rs6000_sibcall_template (rtx *,
unsigned int);
extern const char *rs6000_indirect_call_template (rtx *, unsigned int);
extern const char *rs6000_indirect_sibcall_template (rtx *, unsigned int);
extern const char *rs6000_pltseq_template (rtx *, int);
-
-#define REVERSE_COND_ORDERED_OKfalse
-#define REVERSE_COND_NO_ORDEREDtrue
-
extern enum rtx_code rs6000_reverse_condition (machine_mode,
- enum rtx_code, bool);
+ enum rtx_code);
extern rtx rs6000_emit_eqne (machine_mode, rtx, rtx, rtx);
extern rtx rs6000_emit_fp_cror (rtx_code, machine_mode, rtx);
extern void rs6000_emit_sCOND (machine_mode, rtx[]);
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index eaf79435ec32..f9f9a0b931db 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -15360,25 +15360,15 @@ rs6000_print_patchable_function_entry (FILE *file,
}
enum rtx_code
-rs6000_reverse_condition (machine_mode mode,
- enum rtx_code code,
- bool no_ordered)
+rs6000_reverse_condition (machine_mode mode, enum rtx_code code)
{
/* Reversal of FP compares takes care -- an ordered compare
- becomes an unordered compare and vice versa.
-
- However, this is not safe for ordered comparisons (i.e. for isgreater,
- etc.) starting with the power9 because ifcvt.cc will want to create a fp
- cmove, and the x{s,v}cmp{eq,gt,ge}{dp,qp} instructions will trap if one of
- the arguments is a signalling NaN. */
-
+ becomes an unordered compare and vice versa. */
if (mode == CCFPmode
&& (!flag_finite_math_only
|| code == UNLT || code == UNLE || code == UNGT || code == UNGE
|| code == UNEQ || code == LTGT))
-return (no_ordered
- ? UNKNOWN
- : reverse_condition_maybe_unordered (code));
+return reverse_condition_maybe_unordered (code);
else
return reverse_condition (code);
}
@@ -15990,14 +15980,11 @@ rs6000_emit_sCOND (machine_mode mode, rtx operands[])
rtx not_result = gen_reg_rtx (CCEQmode);
rtx not_op, rev_cond_rtx;
machine_mode cc_mode;
- enum rtx_code rev;
cc_mode = GET_MODE (XEXP (condition_rtx, 0));
- rev = rs6000_reverse_condition (cc_mode, cond_code,
- REVERSE_COND_ORDERED_OK);
- rev_cond_rtx = gen_rtx_fmt_ee (rev, SImode, XEXP (condition_rtx, 0),
-const0_rtx);
+ rev_cond_rtx = gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode,
cond_code),
+SImode, XEXP (condition_rtx, 0),
const0_rtx);
not_op = gen_rtx_COMPARE (CCEQmode, rev_cond_rtx, const0_rtx);
emit_insn (gen_rtx_SET (not_result, not_op));
condition_rtx = gen_rtx_EQ (VOIDmode, not_result, const0_rtx);
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index c595d7138bcd..ec08c96d0f67 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -1812,17 +1812,11 @@ extern scalar_int_mode rs6000_pmode;
/* Can the condition code MODE be safely reversed? This is safe in
all cases on this port, because at present it doesn't use the
- trapping FP comparisons (fcmpo).
-
- However, this is not safe for ordered comparisons (i.e. for isgreater, etc.)
- starting with the power9 because ifcvt.cc will want to create a fp cmove,
- and the x{s,v}cmp{eq,gt,ge}{dp,qp} instructions will trap if one of the
- arguments is a signalling NaN. */
+ trapping FP comparisons (fcmpo). */
#define REVERSIBLE_CC_MODE(MODE) 1
/* Given a condition code and a mode, return the inverse condition. */
-#define REVERSE_CONDITION(CODE, MODE) \
- rs6000_reverse_condition (MODE, CODE, REVERSE_COND_NO_ORDERED)
+#define REVERSE_CONDITION(CODE, MODE) rs6000_reverse_condition (MODE, CODE)
/* Target cpu costs. */
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 5f7ff36617da..65da0c653304 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -13497
[gcc r15-7181] Fortran: Fix UTF-8 output with A edit descriptor.
https://gcc.gnu.org/g:4daf088123b2c4c3114a4b96d5353c3d72eb8ac9
commit r15-7181-g4daf088123b2c4c3114a4b96d5353c3d72eb8ac9
Author: Jerry DeLisle
Date: Thu Jan 23 12:58:14 2025 -0800
Fortran: Fix UTF-8 output with A edit descriptor.
This adjusts the source len for the case where the user has
specified a field width with the A descriptor.
PR libfortran/118571
libgfortran/ChangeLog:
* io/write.c (write_utf8_char4): Adjust the src_len to the
format width w_len when greater than zero.
gcc/testsuite/ChangeLog:
* gfortran.dg/utf8_3.f03: New test.
Diff:
---
gcc/testsuite/gfortran.dg/utf8_3.f03 | 57
libgfortran/io/write.c | 4 ++-
2 files changed, 60 insertions(+), 1 deletion(-)
diff --git a/gcc/testsuite/gfortran.dg/utf8_3.f03
b/gcc/testsuite/gfortran.dg/utf8_3.f03
new file mode 100644
index ..e1688149e5dc
--- /dev/null
+++ b/gcc/testsuite/gfortran.dg/utf8_3.f03
@@ -0,0 +1,57 @@
+! { dg-do run }
+! PR118571 UTF-8 output and the A edit descriptor.
+
+program test
+
+ use iso_fortran_env
+
+ implicit none
+
+ integer, parameter :: ucs4 = selected_char_kind('ISO_10646')
+
+ character(kind=ucs4, len=1), parameter :: alpha = char(int(z'03B1'), ucs4)
+ character(kind=ucs4, len=1), parameter :: beta = char(int(z'03B2'), ucs4)
+ character(kind=ucs4, len=1), parameter :: space = ucs4_' '
+
+ integer fd
+ character(kind=ucs4,len=:), allocatable :: str
+ character(kind=ucs4,len=25) :: instr, correct
+
+ fd = 42
+
+ open (fd, encoding='UTF-8', status="scratch")
+ open (output_unit, encoding='UTF-8')
+ str = repeat(space,6)//alpha//beta//alpha//beta
+
+ write(fd,'(I4,1X,A)') len_trim(str), str
+ rewind(fd)
+ read(fd,'(a)') instr
+ if (trim(instr) /= ucs4_' 10 '//trim(str)) stop 1
+
+ str = alpha // beta // alpha // beta
+ rewind(fd)
+ write(fd,'(I4,1X,">",A,"<")') len_trim(str(1:1)), str(1:1)
+ rewind(fd)
+ read(fd,'(a)') instr
+ if (trim(instr) /= ucs4_' 1 >'//alpha//ucs4_'<') stop 2
+
+ rewind(fd)
+ write(fd,*) len_trim(str(1:1)), str(1:1)
+ rewind(fd)
+ read(fd,'(a)') instr
+ if (trim(instr) /= ucs4_' 1 '//alpha) stop 3
+
+ rewind(fd)
+ write(fd,'(I4,1X,">",A1,"<")') len_trim(str(1:1)), str(1:1)
+ rewind(fd)
+ read(fd, '(a)') instr
+ if (trim(instr) /= ucs4_' 1 >'//alpha//ucs4_'<') stop 4
+
+ rewind(fd)
+ write(fd,'(I4,1X,">",A1,"<")') len_trim(str), str
+ rewind(fd)
+ read(fd, '(a)') instr
+ if (trim(instr) /= ucs4_' 4 >'//alpha//ucs4_'<') stop 5
+ close(fd)
+end program
+
diff --git a/libgfortran/io/write.c b/libgfortran/io/write.c
index 54312bf67e9c..b36c5bef09e9 100644
--- a/libgfortran/io/write.c
+++ b/libgfortran/io/write.c
@@ -177,7 +177,9 @@ write_utf8_char4 (st_parameter_dt *dtp, gfc_char4_t *source,
break;
}
- /* Now process the remaining characters, one at a time. */
+ /* Now process the remaining characters, one at a time. We need to
+ adjust the src_len if the user has specified a field width. */
+ src_len = w_len > 0 ? w_len : src_len;
for (j = k; j < src_len; j++)
{
c = source[j];
[gcc(refs/users/mikael/heads/refactor_descriptor_v01)] Correction regression contiguous-2.f90
https://gcc.gnu.org/g:4f41ab12922d80f19f9f56dba00c3468d2240812
commit 4f41ab12922d80f19f9f56dba00c3468d2240812
Author: Mikael Morin
Date: Fri Jan 24 16:55:57 2025 +0100
Correction regression contiguous-2.f90
Diff:
---
gcc/fortran/trans-decl.cc | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/gcc/fortran/trans-decl.cc b/gcc/fortran/trans-decl.cc
index 19348c167388..1a9eb3f00d17 100644
--- a/gcc/fortran/trans-decl.cc
+++ b/gcc/fortran/trans-decl.cc
@@ -7225,6 +7225,11 @@ gfc_conv_cfi_to_gfc (stmtblock_t *init, stmtblock_t
*finally,
stmtblock_t block2;
gfc_init_block (&block2);
+ do_copy_inout =
+ (sym->ts.type == BT_CHARACTER && !sym->ts.u.cl->length
+ && (sym->as->type == AS_ASSUMED_SIZE || sym->as->type == AS_EXPLICIT))
+ || sym->attr.contiguous;
+
gfc_set_gfc_from_cfi (&block, &block2, gfc_desc, cfi, rank, sym,
true, do_copy_inout, false);
@@ -7232,11 +7237,8 @@ gfc_conv_cfi_to_gfc (stmtblock_t *init, stmtblock_t
*finally,
handle noncontiguous arrays passed to an dummy with 'contiguous' attribute
and with character(len=*) + assumed-size/explicit-size arrays.
cf. Fortran 2018, 18.3.6, paragraph 5 (and for the caller: para. 6). */
- if ((sym->ts.type == BT_CHARACTER && !sym->ts.u.cl->length
- && (sym->as->type == AS_ASSUMED_SIZE || sym->as->type == AS_EXPLICIT))
- || sym->attr.contiguous)
+ if (do_copy_inout)
{
- do_copy_inout = true;
gcc_assert (!sym->attr.pointer);
stmtblock_t block2;
tree data;
[gcc(refs/users/meissner/heads/work191-bugs)] Revert changes
https://gcc.gnu.org/g:b694f5679d54d90867e90ff18fa0bf619caafc86
commit b694f5679d54d90867e90ff18fa0bf619caafc86
Author: Michael Meissner
Date: Fri Jan 24 14:43:55 2025 -0500
Revert changes
Diff:
---
gcc/config/rs6000/rs6000-protos.h | 9 +--
gcc/config/rs6000/rs6000.cc | 42 -
gcc/config/rs6000/rs6000.h | 10 ++-
gcc/config/rs6000/rs6000.md | 24 +++--
gcc/testsuite/gcc.target/powerpc/pr118541.c | 42 -
5 files changed, 23 insertions(+), 104 deletions(-)
diff --git a/gcc/config/rs6000/rs6000-protos.h
b/gcc/config/rs6000/rs6000-protos.h
index fc110fb0276b..4619142d197b 100644
--- a/gcc/config/rs6000/rs6000-protos.h
+++ b/gcc/config/rs6000/rs6000-protos.h
@@ -114,15 +114,8 @@ extern const char *rs6000_sibcall_template (rtx *,
unsigned int);
extern const char *rs6000_indirect_call_template (rtx *, unsigned int);
extern const char *rs6000_indirect_sibcall_template (rtx *, unsigned int);
extern const char *rs6000_pltseq_template (rtx *, int);
-
-enum reverse_cond_type {
- REVERSE_COND_NO_CMOVE,
- REVERSE_COND_MAYBE_CMOVE
-};
-
extern enum rtx_code rs6000_reverse_condition (machine_mode,
- enum rtx_code,
- enum reverse_cond_type);
+ enum rtx_code);
extern rtx rs6000_emit_eqne (machine_mode, rtx, rtx, rtx);
extern rtx rs6000_emit_fp_cror (rtx_code, machine_mode, rtx);
extern void rs6000_emit_sCOND (machine_mode, rtx[]);
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 99c7cc73e08c..f9f9a0b931db 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -15360,34 +15360,17 @@ rs6000_print_patchable_function_entry (FILE *file,
}
enum rtx_code
-rs6000_reverse_condition (machine_mode mode,
- enum rtx_code code,
- enum reverse_cond_type type)
+rs6000_reverse_condition (machine_mode mode, enum rtx_code code)
{
/* Reversal of FP compares takes care -- an ordered compare
- becomes an unordered compare and vice versa.
-
- However, this is not safe for ordered comparisons (i.e. for isgreater,
- etc.) starting with the power9 because ifcvt.cc will want to create a fp
- cmove, and the x{s,v}cmp{eq,gt,ge}{dp,qp} instructions will trap if one of
- the arguments is a signalling NaN. */
-
- if (mode == CCFPmode)
-{
- if (code == UNLT || code == UNLE || code == UNGT || code == UNGE
- || code == UNEQ || code == LTGT)
- {
- if (type == REVERSE_COND_MAYBE_CMOVE && !flag_finite_math_only)
- return UNKNOWN;
-
- return reverse_condition_maybe_unordered (code);
- }
-
- else if (!flag_finite_math_only)
- return reverse_condition_maybe_unordered (code);
-}
-
- return reverse_condition (code);
+ becomes an unordered compare and vice versa. */
+ if (mode == CCFPmode
+ && (!flag_finite_math_only
+ || code == UNLT || code == UNLE || code == UNGT || code == UNGE
+ || code == UNEQ || code == LTGT))
+return reverse_condition_maybe_unordered (code);
+ else
+return reverse_condition (code);
}
/* Check if C (as 64bit integer) can be rotated to a constant which constains
@@ -16000,11 +15983,8 @@ rs6000_emit_sCOND (machine_mode mode, rtx operands[])
cc_mode = GET_MODE (XEXP (condition_rtx, 0));
- enum rtx_code rev
- = rs6000_reverse_condition (cc_mode, cond_code, REVERSE_COND_NO_CMOVE);
-
- rev_cond_rtx = gen_rtx_fmt_ee (rev, SImode, XEXP (condition_rtx, 0),
-const0_rtx);
+ rev_cond_rtx = gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode,
cond_code),
+SImode, XEXP (condition_rtx, 0),
const0_rtx);
not_op = gen_rtx_COMPARE (CCEQmode, rev_cond_rtx, const0_rtx);
emit_insn (gen_rtx_SET (not_result, not_op));
condition_rtx = gen_rtx_EQ (VOIDmode, not_result, const0_rtx);
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 9894adf414b9..ec08c96d0f67 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -1812,17 +1812,11 @@ extern scalar_int_mode rs6000_pmode;
/* Can the condition code MODE be safely reversed? This is safe in
all cases on this port, because at present it doesn't use the
- trapping FP comparisons (fcmpo).
-
- However, this is not safe for ordered comparisons (i.e. for isgreater, etc.)
- starting with the power9 because ifcvt.cc will want to create a fp cmove,
- and the x{s,v}cmp{eq,gt,ge}{dp,qp} instructions will trap if one of the
- arguments is a signalling NaN. */
+ trapping FP comparisons (fcmpo). */
#define REVERSIBLE_CC_MODE(MODE) 1
/* Given a condition code and a mode, return the inverse condition. */
-#define REVERSE_C
[gcc r15-7189] aarch64: Rename info structs in aarch64-common.cc
https://gcc.gnu.org/g:5a674214b9fe96db4c1a033c585e40cd97592d5b
commit r15-7189-g5a674214b9fe96db4c1a033c585e40cd97592d5b
Author: Andrew Carlotti
Date: Wed Jan 8 22:58:05 2025 +
aarch64: Rename info structs in aarch64-common.cc
Also add a (currently unused) processor field to aarch64_processor_info,
and change name from "" to NULL for the terminating array entries.
gcc/ChangeLog:
* common/config/aarch64/aarch64-common.cc
(struct aarch64_option_extension): Rename to..
(struct aarch64_extension_info): ...this.
(all_extensions): Update type name.
(struct arch_to_arch_name): Rename to...
(struct aarch64_arch_info): ...this, and rename name field.
(all_architectures): Update type names, and move before...
(struct processor_name_to_arch): ...this. Rename to...
(struct aarch64_processor_info): ...this, rename name field and
add cpu field.
(all_cores): Update type name, and set new field.
(aarch64_parse_extension): Update names.
(aarch64_get_all_extension_candidates): Ditto.
(aarch64_rewrite_selected_cpu): Ditto.
Diff:
---
gcc/common/config/aarch64/aarch64-common.cc | 50 -
1 file changed, 27 insertions(+), 23 deletions(-)
diff --git a/gcc/common/config/aarch64/aarch64-common.cc
b/gcc/common/config/aarch64/aarch64-common.cc
index 75600548fdc6..3368af00b030 100644
--- a/gcc/common/config/aarch64/aarch64-common.cc
+++ b/gcc/common/config/aarch64/aarch64-common.cc
@@ -145,8 +145,9 @@ aarch64_handle_option (struct gcc_options *opts,
}
}
+
/* An ISA extension in the co-processor and main instruction set space. */
-struct aarch64_option_extension
+struct aarch64_extension_info
{
/* The extension name to pass on to the assembler. */
const char *name;
@@ -159,7 +160,7 @@ struct aarch64_option_extension
};
/* ISA extensions in AArch64. */
-static constexpr aarch64_option_extension all_extensions[] =
+static constexpr aarch64_extension_info all_extensions[] =
{
#define AARCH64_OPT_EXTENSION(NAME, IDENT, C, D, E, FEATURE_STRING) \
{NAME, AARCH64_FL_##IDENT, feature_deps::IDENT ().explicit_on, \
@@ -168,38 +169,41 @@ static constexpr aarch64_option_extension
all_extensions[] =
{NULL, 0, 0, 0}
};
-struct processor_name_to_arch
+struct aarch64_arch_info
{
- const char *processor_name;
+ const char *name;
aarch64_arch arch;
aarch64_feature_flags flags;
};
-struct arch_to_arch_name
+/* Map architecture revisions to their string representation. */
+static constexpr aarch64_arch_info all_architectures[] =
+{
+#define AARCH64_ARCH(NAME, B, ARCH_IDENT, D, E)\
+ {NAME, AARCH64_ARCH_##ARCH_IDENT, feature_deps::ARCH_IDENT ().enable},
+#include "config/aarch64/aarch64-arches.def"
+ {NULL, aarch64_no_arch, 0}
+};
+
+struct aarch64_processor_info
{
+ const char *name;
+ aarch64_cpu processor;
aarch64_arch arch;
- const char *arch_name;
aarch64_feature_flags flags;
};
/* Map processor names to the architecture revision they implement and
the default set of architectural feature flags they support. */
-static constexpr processor_name_to_arch all_cores[] =
+static constexpr aarch64_processor_info all_cores[] =
{
#define AARCH64_CORE(NAME, CORE_IDENT, C, ARCH_IDENT, E, F, G, H, I) \
- {NAME, AARCH64_ARCH_##ARCH_IDENT, feature_deps::cpu_##CORE_IDENT},
+ {NAME, AARCH64_CPU_##CORE_IDENT, AARCH64_ARCH_##ARCH_IDENT, \
+ feature_deps::cpu_##CORE_IDENT},
#include "config/aarch64/aarch64-cores.def"
- {"", aarch64_no_arch, 0}
+ {NULL, aarch64_no_cpu, aarch64_no_arch, 0}
};
-/* Map architecture revisions to their string representation. */
-static constexpr arch_to_arch_name all_architectures[] =
-{
-#define AARCH64_ARCH(NAME, B, ARCH_IDENT, D, E)\
- {AARCH64_ARCH_##ARCH_IDENT, NAME, feature_deps::ARCH_IDENT ().enable},
-#include "config/aarch64/aarch64-arches.def"
- {aarch64_no_arch, "", 0}
-};
/* Parse the architecture extension string STR and update ISA_FLAGS
with the architecture features turned on or off. Return a
@@ -212,7 +216,7 @@ aarch64_parse_extension (const char *str,
aarch64_feature_flags *isa_flags,
std::string *invalid_extension)
{
/* The extension string is parsed left to right. */
- const struct aarch64_option_extension *opt = NULL;
+ const struct aarch64_extension_info *opt = NULL;
/* Flag to say whether we are adding or removing an extension. */
int adding_ext = -1;
@@ -276,7 +280,7 @@ aarch64_parse_extension (const char *str,
aarch64_feature_flags *isa_flags,
void
aarch64_get_all_extension_candidates (auto_vec *candidates)
{
- const struct aarch64_option_extension *opt;
+ const struct aarch64_extension_info *opt;
for (opt = all_extensions; opt->name != NULL; opt++)
candidates->safe_push (opt->name);
}
@@ -396,16 +400,16 @@ aarch64_rewrit
[gcc r15-7195] aarch64: Refactor aarch64_rewrite_mcpu
https://gcc.gnu.org/g:c6ef35b4c3c092bf5e0171827ed918d4249575ca
commit r15-7195-gc6ef35b4c3c092bf5e0171827ed918d4249575ca
Author: Andrew Carlotti
Date: Thu Jan 23 19:07:09 2025 +
aarch64: Refactor aarch64_rewrite_mcpu
Use aarch64_validate_cpu instead of the existing duplicate (and worse)
version of the -mcpu parsing code.
The original code used fatal_error; I'm guessing that using error
instead should be ok.
gcc/ChangeLog:
* common/config/aarch64/aarch64-common.cc
(aarch64_rewrite_selected_cpu): Refactor and inline into...
(aarch64_rewrite_mcpu): this.
* config/aarch64/aarch64-protos.h
(aarch64_rewrite_selected_cpu): Delete.
Diff:
---
gcc/common/config/aarch64/aarch64-common.cc | 78 +++--
gcc/config/aarch64/aarch64-protos.h | 1 -
2 files changed, 17 insertions(+), 62 deletions(-)
diff --git a/gcc/common/config/aarch64/aarch64-common.cc
b/gcc/common/config/aarch64/aarch64-common.cc
index abb9565e13e1..427a1938902c 100644
--- a/gcc/common/config/aarch64/aarch64-common.cc
+++ b/gcc/common/config/aarch64/aarch64-common.cc
@@ -732,60 +732,29 @@ aarch64_rewrite_march (int argc, const char **argv)
return xstrdup (outstr.c_str ());
}
-/* Attempt to rewrite NAME, which has been passed on the command line
- as a -mcpu option to an equivalent -march value. If we can do so,
- return the new string, otherwise return an error. */
+/* Called by the driver to rewrite a name passed to the -mcpu argument
+ to an equivalent -march value to be passed to the assembler. The
+ names passed from the commend line will be in ARGV, we want
+ to use the right-most argument, which should be in
+ ARGV[ARGC - 1]. ARGC should always be greater than 0. */
const char *
-aarch64_rewrite_selected_cpu (const char *name)
+aarch64_rewrite_mcpu (int argc, const char **argv)
{
- std::string original_string (name);
- std::string extension_str;
- std::string processor;
- size_t extension_pos = original_string.find_first_of ('+');
-
- /* Strip and save the extension string. */
- if (extension_pos != std::string::npos)
-{
- processor = original_string.substr (0, extension_pos);
- extension_str = original_string.substr (extension_pos,
- std::string::npos);
-}
- else
-{
- /* No extensions. */
- processor = original_string;
-}
-
- const struct aarch64_processor_info* p_to_a;
- for (p_to_a = all_cores;
- p_to_a->arch != aarch64_no_arch;
- p_to_a++)
-{
- if (p_to_a->name == processor)
- break;
-}
-
- const struct aarch64_arch_info* a_to_an;
- for (a_to_an = all_architectures;
- a_to_an->arch != aarch64_no_arch;
- a_to_an++)
-{
- if (a_to_an->arch == p_to_a->arch)
- break;
-}
+ gcc_assert (argc);
+ const char *name = argv[argc - 1];
+ aarch64_cpu cpu;
+ aarch64_feature_flags flags;
- /* We couldn't find that processor name, or the processor name we
- found does not map to an architecture we understand. */
- if (p_to_a->arch == aarch64_no_arch
- || a_to_an->arch == aarch64_no_arch)
-fatal_error (input_location, "unknown value %qs for %<-mcpu%>", name);
+ aarch64_validate_mcpu (name, &cpu, &flags);
- aarch64_feature_flags extensions = p_to_a->flags;
- aarch64_parse_extension (extension_str.c_str (), &extensions, NULL);
+ const struct aarch64_processor_info *entry;
+ for (entry = all_cores; entry->processor != aarch64_no_cpu; entry++)
+if (entry->processor == cpu)
+ break;
- std::string outstr = aarch64_get_arch_string_for_assembler (a_to_an->arch,
- extensions);
+ std::string outstr = aarch64_get_arch_string_for_assembler (entry->arch,
+ flags);
/* We are going to memory leak here, nobody elsewhere
in the callchain is going to clean up after us. The alternative is
@@ -794,19 +763,6 @@ aarch64_rewrite_selected_cpu (const char *name)
return xstrdup (outstr.c_str ());
}
-/* Called by the driver to rewrite a name passed to the -mcpu
- argument in preparation to be passed to the assembler. The
- names passed from the commend line will be in ARGV, we want
- to use the right-most argument, which should be in
- ARGV[ARGC - 1]. ARGC should always be greater than 0. */
-
-const char *
-aarch64_rewrite_mcpu (int argc, const char **argv)
-{
- gcc_assert (argc);
- return aarch64_rewrite_selected_cpu (argv[argc - 1]);
-}
-
/* Checks to see if the host CPU may not be Cortex-A53 or an unknown Armv8-a
baseline CPU. */
diff --git a/gcc/config/aarch64/aarch64-protos.h
b/gcc/config/aarch64/aarch64-protos.h
index b27da1e25720..4235f4a0ca51 100644
--- a/gcc/config/aarch64/aarch64-protos.h
+++ b/gcc/config/aarch64/aarch64-protos.h
@@ -1210,7 +1210,6 @@ boo
[gcc r15-7184] c++: ICE with nested anonymous union [PR117153]
https://gcc.gnu.org/g:10850f92b2a618ef1b1ad399530943ef4847823d
commit r15-7184-g10850f92b2a618ef1b1ad399530943ef4847823d
Author: Marek Polacek
Date: Mon Nov 25 09:45:13 2024 -0500
c++: ICE with nested anonymous union [PR117153]
In a template, for
union {
union {
T d;
};
};
build_anon_union_vars crates a malformed COMPONENT_REF: we have no
DECL_NAME for the nested anon union so we create something like "object.".
Most of the front end doesn't seem to care, but if such a tree gets to
potential_constant_expression, it can cause a crash.
We can use FIELD directly for the COMPONENT_REF's member. tsubst_stmt
should build up a proper one in:
if (VAR_P (decl) && !DECL_NAME (decl)
&& ANON_AGGR_TYPE_P (TREE_TYPE (decl)))
/* Anonymous aggregates are a special case. */
finish_anon_union (decl);
PR c++/117153
gcc/cp/ChangeLog:
* decl2.cc (build_anon_union_vars): Use FIELD for the second operand
of a COMPONENT_REF.
gcc/testsuite/ChangeLog:
* g++.dg/other/anon-union6.C: New test.
* g++.dg/other/anon-union7.C: New test.
Reviewed-by: Jason Merrill
Diff:
---
gcc/cp/decl2.cc | 2 +-
gcc/testsuite/g++.dg/other/anon-union6.C | 13 +
gcc/testsuite/g++.dg/other/anon-union7.C | 16
3 files changed, 30 insertions(+), 1 deletion(-)
diff --git a/gcc/cp/decl2.cc b/gcc/cp/decl2.cc
index ffe1aa3a3244..9e61afd359fc 100644
--- a/gcc/cp/decl2.cc
+++ b/gcc/cp/decl2.cc
@@ -2032,7 +2032,7 @@ build_anon_union_vars (tree type, tree object)
if (processing_template_decl)
ref = build_min_nt_loc (UNKNOWN_LOCATION, COMPONENT_REF, object,
- DECL_NAME (field), NULL_TREE);
+ field, NULL_TREE);
else
ref = build_class_member_access_expr (object, field, NULL_TREE,
false, tf_warning_or_error);
diff --git a/gcc/testsuite/g++.dg/other/anon-union6.C
b/gcc/testsuite/g++.dg/other/anon-union6.C
new file mode 100644
index ..d1cde30f790d
--- /dev/null
+++ b/gcc/testsuite/g++.dg/other/anon-union6.C
@@ -0,0 +1,13 @@
+// PR c++/117153
+// { dg-do compile }
+
+template
+void f() {
+ union {
+union {
+ T d;
+};
+ };
+ (void) (d + 0);
+}
+template void f();
diff --git a/gcc/testsuite/g++.dg/other/anon-union7.C
b/gcc/testsuite/g++.dg/other/anon-union7.C
new file mode 100644
index ..e89334a5d0e7
--- /dev/null
+++ b/gcc/testsuite/g++.dg/other/anon-union7.C
@@ -0,0 +1,16 @@
+// PR c++/117153
+// { dg-do compile { target c++11 } }
+
+using U = union { union { int a; }; };
+
+U
+foo ()
+{
+ return {};
+}
+
+void
+g ()
+{
+ [[maybe_unused]] auto u = foo ();
+}
[gcc(refs/users/meissner/heads/work191-bugs)] Revert changes
https://gcc.gnu.org/g:26becaba071d511727e5ac6a89bb021c919cb345
commit 26becaba071d511727e5ac6a89bb021c919cb345
Author: Michael Meissner
Date: Fri Jan 24 13:49:49 2025 -0500
Revert changes
Diff:
---
gcc/config/rs6000/rs6000-protos.h | 9 +--
gcc/config/rs6000/rs6000.cc | 35 +++-
gcc/config/rs6000/rs6000.h | 10 ++-
gcc/config/rs6000/rs6000.md | 24 +++--
gcc/testsuite/gcc.target/powerpc/pr118541.c | 42 -
5 files changed, 22 insertions(+), 98 deletions(-)
diff --git a/gcc/config/rs6000/rs6000-protos.h
b/gcc/config/rs6000/rs6000-protos.h
index 3378824c4824..4619142d197b 100644
--- a/gcc/config/rs6000/rs6000-protos.h
+++ b/gcc/config/rs6000/rs6000-protos.h
@@ -114,15 +114,8 @@ extern const char *rs6000_sibcall_template (rtx *,
unsigned int);
extern const char *rs6000_indirect_call_template (rtx *, unsigned int);
extern const char *rs6000_indirect_sibcall_template (rtx *, unsigned int);
extern const char *rs6000_pltseq_template (rtx *, int);
-
-enum rev_cond_type {
- REV_COND_MAYBE_CMOVE,
- REV_COND_NOT_CMOVE
-};
-
extern enum rtx_code rs6000_reverse_condition (machine_mode,
- enum rtx_code,
- enum rev_cond_type);
+ enum rtx_code);
extern rtx rs6000_emit_eqne (machine_mode, rtx, rtx, rtx);
extern rtx rs6000_emit_fp_cror (rtx_code, machine_mode, rtx);
extern void rs6000_emit_sCOND (machine_mode, rtx[]);
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 1b787c4b1fa1..f9f9a0b931db 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -15360,31 +15360,17 @@ rs6000_print_patchable_function_entry (FILE *file,
}
enum rtx_code
-rs6000_reverse_condition (machine_mode mode,
- enum rtx_code code,
- enum rev_cond_type type)
+rs6000_reverse_condition (machine_mode mode, enum rtx_code code)
{
/* Reversal of FP compares takes care -- an ordered compare
- becomes an unordered compare and vice versa.
-
- However, this is not safe for ordered comparisons (i.e. for isgreater,
- etc.) starting with the power9 because ifcvt.cc will want to create a
- floating point conditional move, and the x{s,v}cmp{eq,gt,ge}{dp,qp}
- instructions will trap if one of the arguments is a signalling NaN. */
-
- if (mode == CCFPmode)
-{
- if (code == UNLT || code == UNLE || code == UNGT || code == UNGE
- || code == UNEQ || code == LTGT)
- return (type == REV_COND_MAYBE_CMOVE
- ? UNKNOWN
- : reverse_condition_maybe_unordered (code));
-
- if (!flag_finite_math_only)
- return reverse_condition_maybe_unordered (code);
-}
-
- return reverse_condition (code);
+ becomes an unordered compare and vice versa. */
+ if (mode == CCFPmode
+ && (!flag_finite_math_only
+ || code == UNLT || code == UNLE || code == UNGT || code == UNGE
+ || code == UNEQ || code == LTGT))
+return reverse_condition_maybe_unordered (code);
+ else
+return reverse_condition (code);
}
/* Check if C (as 64bit integer) can be rotated to a constant which constains
@@ -15997,8 +15983,7 @@ rs6000_emit_sCOND (machine_mode mode, rtx operands[])
cc_mode = GET_MODE (XEXP (condition_rtx, 0));
- rev_cond_rtx = gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode,
cond_code,
-
REV_COND_NOT_CMOVE),
+ rev_cond_rtx = gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode,
cond_code),
SImode, XEXP (condition_rtx, 0),
const0_rtx);
not_op = gen_rtx_COMPARE (CCEQmode, rev_cond_rtx, const0_rtx);
emit_insn (gen_rtx_SET (not_result, not_op));
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index fc3b323a85e7..ec08c96d0f67 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -1812,17 +1812,11 @@ extern scalar_int_mode rs6000_pmode;
/* Can the condition code MODE be safely reversed? This is safe in
all cases on this port, because at present it doesn't use the
- trapping FP comparisons (fcmpo).
-
- However, this is not safe for ordered comparisons (i.e. for isgreater, etc.)
- starting with the power9 because ifcvt.cc will want to create a fp cmove,
- and the x{s,v}cmp{eq,gt,ge}{dp,qp} instructions will trap if one of the
- arguments is a signalling NaN. */
+ trapping FP comparisons (fcmpo). */
#define REVERSIBLE_CC_MODE(MODE) 1
/* Given a condition code and a mode, return the inverse condition. */
-#define REVERSE_CONDITION(CODE, MODE) \
- rs6000_reverse_condition (MODE, CODE, REV_COND_MAYBE_CMOVE)
+#define REVERSE_CONDITION(CODE, MODE) rs6000_reverse_condition (MODE, CODE)
/* Target cpu costs. *
[gcc r15-7192] aarch64: Move arch/cpu parsing to aarch64-common.cc
https://gcc.gnu.org/g:ecb4565a473adf810ea6d4e11709efc41d968dff
commit r15-7192-gecb4565a473adf810ea6d4e11709efc41d968dff
Author: Andrew Carlotti
Date: Thu Jan 23 17:08:17 2025 +
aarch64: Move arch/cpu parsing to aarch64-common.cc
Aside from moving the functions, the only changes are to make them
non-static, and to use the existing info arrays within aarch64-common.cc
instead of the info arrays remaining in aarch64.cc.
gcc/ChangeLog:
* common/config/aarch64/aarch64-common.cc
(aarch64_get_all_extension_candidates): Move within file.
(aarch64_print_hint_candidates): Move from aarch64.cc.
(aarch64_print_hint_for_extensions): Ditto.
(aarch64_print_hint_for_arch): Ditto.
(aarch64_print_hint_for_core): Ditto.
(enum aarch_parse_opt_result): Ditto.
(aarch64_parse_arch): Ditto.
(aarch64_parse_cpu): Ditto.
(aarch64_parse_tune): Ditto.
(aarch64_validate_march): Ditto.
(aarch64_validate_mcpu): Ditto.
(aarch64_validate_mtune): Ditto.
* config/aarch64/aarch64-protos.h
(aarch64_rewrite_selected_cpu): Move within file.
(aarch64_print_hint_for_extensions): Share function prototype.
(aarch64_print_hint_for_arch): Ditto.
(aarch64_print_hint_for_core): Ditto.
(enum aarch_parse_opt_result): Ditto.
(aarch64_validate_march): Ditto.
(aarch64_validate_mcpu): Ditto.
(aarch64_validate_mtune): Ditto.
(aarch64_get_all_extension_candidates): Unshare prototype.
* config/aarch64/aarch64.cc
(aarch64_parse_arch): Move to aarch64-common.cc.
(aarch64_parse_cpu): Ditto.
(aarch64_parse_tune): Ditto.
(aarch64_print_hint_candidates): Ditto.
(aarch64_print_hint_for_core): Ditto.
(aarch64_print_hint_for_arch): Ditto.
(aarch64_print_hint_for_extensions): Ditto.
(aarch64_validate_mcpu): Ditto.
(aarch64_validate_march): Ditto.
(aarch64_validate_mtune): Ditto.
Diff:
---
gcc/common/config/aarch64/aarch64-common.cc | 334 +++-
gcc/config/aarch64/aarch64-protos.h | 20 +-
gcc/config/aarch64/aarch64.cc | 320 --
3 files changed, 346 insertions(+), 328 deletions(-)
diff --git a/gcc/common/config/aarch64/aarch64-common.cc
b/gcc/common/config/aarch64/aarch64-common.cc
index 3368af00b030..c3ea54ca3f77 100644
--- a/gcc/common/config/aarch64/aarch64-common.cc
+++ b/gcc/common/config/aarch64/aarch64-common.cc
@@ -205,6 +205,78 @@ static constexpr aarch64_processor_info all_cores[] =
};
+/* Print a list of CANDIDATES for an argument, and try to suggest a specific
+ close match. */
+
+inline static void
+aarch64_print_hint_candidates (const char *str,
+ const auto_vec & candidates)
+{
+ char *s;
+ const char *hint = candidates_list_and_hint (str, s, candidates);
+ if (hint)
+inform (input_location, "valid arguments are: %s;"
+" did you mean %qs?", s, hint);
+ else
+inform (input_location, "valid arguments are: %s", s);
+
+ XDELETEVEC (s);
+}
+
+/* Append all architecture extension candidates to the CANDIDATES vector. */
+
+void
+aarch64_get_all_extension_candidates (auto_vec *candidates)
+{
+ const struct aarch64_extension_info *opt;
+ for (opt = all_extensions; opt->name != NULL; opt++)
+candidates->safe_push (opt->name);
+}
+
+/* Print a hint with a suggestion for an extension name
+ that most closely resembles what the user passed in STR. */
+
+void
+aarch64_print_hint_for_extensions (const char *str)
+{
+ auto_vec candidates;
+ aarch64_get_all_extension_candidates (&candidates);
+ aarch64_print_hint_candidates (str, candidates);
+}
+
+/* Print a hint with a suggestion for an architecture name that most closely
+ resembles what the user passed in STR. */
+
+void
+aarch64_print_hint_for_arch (const char *str)
+{
+ auto_vec candidates;
+ const struct aarch64_arch_info *entry = all_architectures;
+ for (; entry->name != NULL; entry++)
+candidates.safe_push (entry->name);
+
+#ifdef HAVE_LOCAL_CPU_DETECT
+ /* Add also "native" as possible value. */
+ candidates.safe_push ("native");
+#endif
+
+ aarch64_print_hint_candidates (str, candidates);
+}
+
+/* Print a hint with a suggestion for a core name that most closely resembles
+ what the user passed in STR. */
+
+void
+aarch64_print_hint_for_core (const char *str)
+{
+ auto_vec candidates;
+ const struct aarch64_processor_info *entry = all_cores;
+ for (; entry->name != NULL; entry++)
+candidates.safe_push (entry->name);
+ aarch64_print_hint_candidates (str, candidates);
+}
+
+
/* Parse the architecture extension string STR and update ISA_FLAGS
with the architecture features turned o
[gcc r15-7187] aarch64: Replace duplicate cpu enums
https://gcc.gnu.org/g:997bba31ea8c1f7b4b7227e18afa8adb734ee946
commit r15-7187-g997bba31ea8c1f7b4b7227e18afa8adb734ee946
Author: Andrew Carlotti
Date: Wed Jan 8 20:06:09 2025 +
aarch64: Replace duplicate cpu enums
Replace `enum aarch64_processor` and `enum target_cpus` with
`enum aarch64_cpu`, and prefix the entries with `AARCH64_CPU_`.
Also rename aarch64_none to aarch64_no_cpu.
gcc/ChangeLog:
* config/aarch64/aarch64-opts.h
(enum aarch64_processor): Rename to...
(enum aarch64_cpu): ...this, and rename the entries.
* config/aarch64/aarch64.cc
(aarch64_type): Rename type and initial value.
(struct processor): Rename member types.
(all_architectures): Rename enum members.
(all_cores): Ditto.
(aarch64_get_tune_cpu): Rename type and enum member.
* config/aarch64/aarch64.h (enum target_cpus): Remove.
(TARGET_CPU_DEFAULT): Rename default value.
(aarch64_tune): Rename type.
* config/aarch64/aarch64.opt:
(selected_tune): Rename type and default value.
Diff:
---
gcc/config/aarch64/aarch64-opts.h | 6 +++---
gcc/config/aarch64/aarch64.cc | 18 +-
gcc/config/aarch64/aarch64.h | 11 ++-
gcc/config/aarch64/aarch64.opt| 2 +-
4 files changed, 15 insertions(+), 22 deletions(-)
diff --git a/gcc/config/aarch64/aarch64-opts.h
b/gcc/config/aarch64/aarch64-opts.h
index 3f0b1e9414c3..a6ca5cf016b0 100644
--- a/gcc/config/aarch64/aarch64-opts.h
+++ b/gcc/config/aarch64/aarch64-opts.h
@@ -38,13 +38,13 @@ typedef bbitmap<2> aarch64_feature_flags;
#endif
/* The various cores that implement AArch64. */
-enum aarch64_processor
+enum aarch64_cpu
{
#define AARCH64_CORE(NAME, INTERNAL_IDENT, SCHED, ARCH, FLAGS, COSTS, IMP,
PART, VARIANT) \
- INTERNAL_IDENT,
+ AARCH64_CPU_##INTERNAL_IDENT,
#include "aarch64-cores.def"
/* Used to mark the end of the processor table. */
- aarch64_none
+ aarch64_no_cpu
};
enum aarch64_arch
diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc
index e7a75411f071..4d3b28b4cdb4 100644
--- a/gcc/config/aarch64/aarch64.cc
+++ b/gcc/config/aarch64/aarch64.cc
@@ -357,7 +357,7 @@ static bool aarch64_print_address_internal (FILE*,
machine_mode, rtx,
aarch64_addr_query_type);
/* The processor for which instructions should be scheduled. */
-enum aarch64_processor aarch64_tune = cortexa53;
+enum aarch64_cpu aarch64_tune = AARCH64_CPU_cortexa53;
/* Global flag for PC relative loads. */
bool aarch64_pcrelative_literal_loads;
@@ -451,8 +451,8 @@ aarch64_tuning_override_functions[] =
struct processor
{
const char *name;
- aarch64_processor ident;
- aarch64_processor sched_core;
+ aarch64_cpu ident;
+ aarch64_cpu sched_core;
aarch64_arch arch;
aarch64_feature_flags flags;
const tune_params *tune;
@@ -462,20 +462,20 @@ struct processor
static CONSTEXPR const processor all_architectures[] =
{
#define AARCH64_ARCH(NAME, CORE, ARCH_IDENT, D, E) \
- {NAME, CORE, CORE, AARCH64_ARCH_##ARCH_IDENT, \
+ {NAME, AARCH64_CPU_##CORE, AARCH64_CPU_##CORE, AARCH64_ARCH_##ARCH_IDENT, \
feature_deps::ARCH_IDENT ().enable, NULL},
#include "aarch64-arches.def"
- {NULL, aarch64_none, aarch64_none, aarch64_no_arch, 0, NULL}
+ {NULL, aarch64_no_cpu, aarch64_no_cpu, aarch64_no_arch, 0, NULL}
};
/* Processor cores implementing AArch64. */
static const struct processor all_cores[] =
{
#define AARCH64_CORE(NAME, IDENT, SCHED, ARCH, E, COSTS, G, H, I) \
- {NAME, IDENT, SCHED, AARCH64_ARCH_##ARCH, \
+ {NAME, AARCH64_CPU_##IDENT, AARCH64_CPU_##SCHED, AARCH64_ARCH_##ARCH, \
feature_deps::cpu_##IDENT, &COSTS##_tunings},
#include "aarch64-cores.def"
- {NULL, aarch64_none, aarch64_none, aarch64_no_arch, 0, NULL}
+ {NULL, aarch64_no_cpu, aarch64_no_cpu, aarch64_no_arch, 0, NULL}
};
/* Internal representation of system registers. */
typedef struct {
@@ -18566,9 +18566,9 @@ initialize_aarch64_tls_size (struct gcc_options *opts)
/* Return the CPU corresponding to the enum CPU. */
static const struct processor *
-aarch64_get_tune_cpu (enum aarch64_processor cpu)
+aarch64_get_tune_cpu (enum aarch64_cpu cpu)
{
- gcc_assert (cpu != aarch64_none);
+ gcc_assert (cpu != aarch64_no_cpu);
return &all_cores[cpu];
}
diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h
index 1a19b27fd934..6f7a73fe1d7e 100644
--- a/gcc/config/aarch64/aarch64.h
+++ b/gcc/config/aarch64/aarch64.h
@@ -928,16 +928,9 @@ enum reg_class
/* CPU/ARCH option handling. */
#include "config/aarch64/aarch64-opts.h"
-enum target_cpus
-{
-#define AARCH64_CORE(NAME, INTERNAL_IDENT, SCHED, ARCH, FLAGS, COSTS, IMP,
PART, VARIANT) \
- TARGET_CPU_##INTERNAL_IDENT,
-#include "aarch64-cores.def"
-};
-
/* If there is no CPU defined at configure, use generic as default. */
#ifn
[gcc r15-7194] aarch64: Rewrite architecture strings for assembler
https://gcc.gnu.org/g:15e07e14372cfeb53cbdfb7cf96a8a49e402da68
commit r15-7194-g15e07e14372cfeb53cbdfb7cf96a8a49e402da68
Author: Andrew Carlotti
Date: Mon Nov 11 12:20:25 2024 +
aarch64: Rewrite architecture strings for assembler
Add infrastructure to allow rewriting the architecture strings passed to
the assembler (either as -march options or .arch directives). There was
already canonicalisation everywhere except for an -march driver option
passed directly to the compiler; this patch applies the same
canonicalisation there as well.
gcc/ChangeLog:
* common/config/aarch64/aarch64-common.cc
(aarch64_get_arch_string_for_assembler): New.
(aarch64_rewrite_march): New.
(aarch64_rewrite_selected_cpu): Call new function.
* config/aarch64/aarch64-elf.h (ASM_SPEC): Remove identity mapping.
* config/aarch64/aarch64-protos.h
(aarch64_get_arch_string_for_assembler): New.
* config/aarch64/aarch64.cc
(aarch64_declare_function_name): Call new function.
(aarch64_start_file): Ditto.
* config/aarch64/aarch64.h
(EXTRA_SPEC_FUNCTIONS): Use new macro name.
(MCPU_TO_MARCH_SPEC): Rename to...
(MARCH_REWRITE_SPEC): ...this, and extend the spec rule.
(aarch64_rewrite_march): New declaration.
(MCPU_TO_MARCH_SPEC_FUNCTIONS): Rename to...
(AARCH64_BASE_SPEC_FUNCTIONS): ...this, and add new function.
(ASM_CPU_SPEC): Use new macro name.
Diff:
---
gcc/common/config/aarch64/aarch64-common.cc | 49 ++---
gcc/config/aarch64/aarch64-elf.h| 1 -
gcc/config/aarch64/aarch64-protos.h | 2 ++
gcc/config/aarch64/aarch64.cc | 31 +++---
gcc/config/aarch64/aarch64.h| 15 +
5 files changed, 68 insertions(+), 30 deletions(-)
diff --git a/gcc/common/config/aarch64/aarch64-common.cc
b/gcc/common/config/aarch64/aarch64-common.cc
index 9923437761c9..abb9565e13e1 100644
--- a/gcc/common/config/aarch64/aarch64-common.cc
+++ b/gcc/common/config/aarch64/aarch64-common.cc
@@ -690,6 +690,48 @@ aarch64_get_extension_string_for_isa_flags
return outstr;
}
+/* Generate an arch string to be passed to the assembler. */
+
+std::string
+aarch64_get_arch_string_for_assembler (aarch64_arch arch,
+ aarch64_feature_flags flags)
+{
+ const struct aarch64_arch_info *entry;
+ for (entry = all_architectures; entry->arch != aarch64_no_arch; entry++)
+if (entry->arch == arch)
+ break;
+
+ std::string outstr = entry->name
+ + aarch64_get_extension_string_for_isa_flags (flags, entry->flags);
+
+ return outstr;
+}
+
+/* Called by the driver to rewrite a name passed to the -march
+ argument in preparation to be passed to the assembler. The
+ names passed from the commend line will be in ARGV, we want
+ to use the right-most argument, which should be in
+ ARGV[ARGC - 1]. ARGC should always be greater than 0. */
+
+const char *
+aarch64_rewrite_march (int argc, const char **argv)
+{
+ gcc_assert (argc);
+ const char *name = argv[argc - 1];
+ aarch64_arch arch;
+ aarch64_feature_flags flags;
+
+ aarch64_validate_march (name, &arch, &flags);
+
+ std::string outstr = aarch64_get_arch_string_for_assembler (arch, flags);
+
+ /* We are going to memory leak here, nobody elsewhere
+ in the callchain is going to clean up after us. The alternative is
+ to allocate a static buffer, and assert that it is big enough for our
+ modified string, which seems much worse! */
+ return xstrdup (outstr.c_str ());
+}
+
/* Attempt to rewrite NAME, which has been passed on the command line
as a -mcpu option to an equivalent -march value. If we can do so,
return the new string, otherwise return an error. */
@@ -733,7 +775,7 @@ aarch64_rewrite_selected_cpu (const char *name)
break;
}
- /* We couldn't find that proceesor name, or the processor name we
+ /* We couldn't find that processor name, or the processor name we
found does not map to an architecture we understand. */
if (p_to_a->arch == aarch64_no_arch
|| a_to_an->arch == aarch64_no_arch)
@@ -742,9 +784,8 @@ aarch64_rewrite_selected_cpu (const char *name)
aarch64_feature_flags extensions = p_to_a->flags;
aarch64_parse_extension (extension_str.c_str (), &extensions, NULL);
- std::string outstr = a_to_an->name
- + aarch64_get_extension_string_for_isa_flags (extensions,
- a_to_an->flags);
+ std::string outstr = aarch64_get_arch_string_for_assembler (a_to_an->arch,
+ extensions);
/* We are going to memory leak here, nobody elsewhere
in the callchain is going to clean up after us. The alternative is
diff --git a/gcc/config
[gcc r15-7191] aarch64: Inline aarch64_print_hint_for_core_or_arch
https://gcc.gnu.org/g:5c5b6a922ad3931039690cd79c8d1351361790f3
commit r15-7191-g5c5b6a922ad3931039690cd79c8d1351361790f3
Author: Andrew Carlotti
Date: Thu Jan 9 00:53:11 2025 +
aarch64: Inline aarch64_print_hint_for_core_or_arch
It seems odd that we add "native" to the list for -march but not for
-mcpu. This is probably a bug, but for now we'll preserve the existing
behaviour.
gcc/ChangeLog:
* config/aarch64/aarch64.cc
(aarch64_print_hint_candidates): New helper function.
(aarch64_print_hint_for_core_or_arch): Inline into callers.
(aarch64_print_hint_for_core): Inline callee and use new helper.
(aarch64_print_hint_for_arch): Ditto.
(aarch64_print_hint_for_extensions): Use new helper.
Diff:
---
gcc/config/aarch64/aarch64.cc | 50 +++
1 file changed, 22 insertions(+), 28 deletions(-)
diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc
index 56c9f66861b3..ae1235640d27 100644
--- a/gcc/config/aarch64/aarch64.cc
+++ b/gcc/config/aarch64/aarch64.cc
@@ -18891,25 +18891,13 @@ aarch64_override_options_internal (struct gcc_options
*opts)
aarch64_override_options_after_change_1 (opts);
}
-/* Print a hint with a suggestion for a core or architecture name that
- most closely resembles what the user passed in STR. ARCH is true if
- the user is asking for an architecture name. ARCH is false if the user
- is asking for a core name. */
+/* Print a list of CANDIDATES for an argument, and try to suggest a specific
+ close match. */
-static void
-aarch64_print_hint_for_core_or_arch (const char *str, bool arch)
+inline static void
+aarch64_print_hint_candidates (const char *str,
+ const auto_vec & candidates)
{
- auto_vec candidates;
- const struct processor *entry = arch ? all_architectures : all_cores;
- for (; entry->name != NULL; entry++)
-candidates.safe_push (entry->name);
-
-#ifdef HAVE_LOCAL_CPU_DETECT
- /* Add also "native" as possible value. */
- if (arch)
-candidates.safe_push ("native");
-#endif
-
char *s;
const char *hint = candidates_list_and_hint (str, s, candidates);
if (hint)
@@ -18927,7 +18915,11 @@ aarch64_print_hint_for_core_or_arch (const char *str,
bool arch)
inline static void
aarch64_print_hint_for_core (const char *str)
{
- aarch64_print_hint_for_core_or_arch (str, false);
+ auto_vec candidates;
+ const struct processor *entry = all_cores;
+ for (; entry->name != NULL; entry++)
+candidates.safe_push (entry->name);
+ aarch64_print_hint_candidates (str, candidates);
}
/* Print a hint with a suggestion for an architecture name that most closely
@@ -18936,7 +18928,17 @@ aarch64_print_hint_for_core (const char *str)
inline static void
aarch64_print_hint_for_arch (const char *str)
{
- aarch64_print_hint_for_core_or_arch (str, true);
+ auto_vec candidates;
+ const struct processor *entry = all_architectures;
+ for (; entry->name != NULL; entry++)
+candidates.safe_push (entry->name);
+
+#ifdef HAVE_LOCAL_CPU_DETECT
+ /* Add also "native" as possible value. */
+ candidates.safe_push ("native");
+#endif
+
+ aarch64_print_hint_candidates (str, candidates);
}
@@ -18948,15 +18950,7 @@ aarch64_print_hint_for_extensions (const char *str)
{
auto_vec candidates;
aarch64_get_all_extension_candidates (&candidates);
- char *s;
- const char *hint = candidates_list_and_hint (str, s, candidates);
- if (hint)
-inform (input_location, "valid arguments are: %s;"
-" did you mean %qs?", s, hint);
- else
-inform (input_location, "valid arguments are: %s", s);
-
- XDELETEVEC (s);
+ aarch64_print_hint_candidates (str, candidates);
}
/* Validate a command-line -mcpu option. Parse the cpu and extensions (if any)
[gcc r15-7186] aarch64: Improve mcpu/march conflict check
https://gcc.gnu.org/g:936463004836cb565f4fc4773dccedbfccf0028f
commit r15-7186-g936463004836cb565f4fc4773dccedbfccf0028f
Author: Andrew Carlotti
Date: Wed Jan 8 18:29:27 2025 +
aarch64: Improve mcpu/march conflict check
Features from a cpu or base architecture that were explicitly disabled
by a +nofeat option were being incorrectly added back in before checking
for conflicts between -mcpu and -march options. This patch instead
compares the returned feature masks directly.
gcc/ChangeLog:
* config/aarch64/aarch64.cc (aarch64_override_options): Compare
returned feature masks directly.
gcc/testsuite/ChangeLog:
* gcc.target/aarch64/target_attr_crypto_ice_1.c: Prune warning.
* gcc.target/aarch64/target_attr_crypto_ice_2.c: Ditto.
Diff:
---
gcc/config/aarch64/aarch64.cc | 7 ++-
gcc/testsuite/gcc.target/aarch64/target_attr_crypto_ice_1.c | 1 +
gcc/testsuite/gcc.target/aarch64/target_attr_crypto_ice_2.c | 1 +
3 files changed, 4 insertions(+), 5 deletions(-)
diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc
index 9c4e9bc8acde..e7a75411f071 100644
--- a/gcc/config/aarch64/aarch64.cc
+++ b/gcc/config/aarch64/aarch64.cc
@@ -19289,13 +19289,10 @@ aarch64_override_options (void)
cpu features would end up disabling an achitecture feature. In
otherwords the cpu features need to be a strict superset of the arch
features and if so prefer the -march ISA flags. */
- auto full_arch_flags = arch->flags | arch_isa;
- auto full_cpu_flags = cpu->flags | cpu_isa;
- if (~full_cpu_flags & full_arch_flags)
+ if (~cpu_isa & arch_isa)
{
std::string ext_diff
- = aarch64_get_extension_string_for_isa_flags (full_arch_flags,
- full_cpu_flags);
+ = aarch64_get_extension_string_for_isa_flags (arch_isa, cpu_isa);
warning (0, "switch %<-mcpu=%s%> conflicts with %<-march=%s%> switch "
"and resulted in options %qs being added",
aarch64_cpu_string,
diff --git a/gcc/testsuite/gcc.target/aarch64/target_attr_crypto_ice_1.c
b/gcc/testsuite/gcc.target/aarch64/target_attr_crypto_ice_1.c
index 3b354c061109..f13e5e2560cd 100644
--- a/gcc/testsuite/gcc.target/aarch64/target_attr_crypto_ice_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/target_attr_crypto_ice_1.c
@@ -1,5 +1,6 @@
/* { dg-do compile } */
/* { dg-options "-O2 -mcpu=thunderx+nofp -march=armv8-a" } */
+/* { dg-prune-output "warning: switch .* conflicts" } */
#include "arm_neon.h"
diff --git a/gcc/testsuite/gcc.target/aarch64/target_attr_crypto_ice_2.c
b/gcc/testsuite/gcc.target/aarch64/target_attr_crypto_ice_2.c
index d0a62b83351b..ab2549228a7f 100644
--- a/gcc/testsuite/gcc.target/aarch64/target_attr_crypto_ice_2.c
+++ b/gcc/testsuite/gcc.target/aarch64/target_attr_crypto_ice_2.c
@@ -1,5 +1,6 @@
/* { dg-do compile } */
/* { dg-options "-O2 -mcpu=thunderx+nofp -march=armv8-a" } */
+/* { dg-prune-output "warning: switch .* conflicts" } */
/* Make sure that we don't ICE when dealing with vector parameters
in a simd-tagged function within a non-simd translation unit. */
[gcc r15-7198] docs: Add +wfxt and +xs to armv9.2-a
https://gcc.gnu.org/g:25464e795eb35f859bdb353c806e93e6ae924ff0
commit r15-7198-g25464e795eb35f859bdb353c806e93e6ae924ff0
Author: Andrew Carlotti
Date: Fri Jan 10 19:22:20 2025 +
docs: Add +wfxt and +xs to armv9.2-a
I missed that the documentation doesn't include armv8.7-a
within armv9.2-a.
gcc/ChangeLog:
* doc/invoke.texi: Add +wfxt and +xs to armv9.2-a
Diff:
---
gcc/doc/invoke.texi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 819a68439342..c8721064f91e 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -21669,7 +21669,7 @@ and the features that they enable by default:
@item @samp{armv8.9-a} @tab Armv8.9-a @tab @samp{armv8.8-a}
@item @samp{armv9-a} @tab Armv9-A @tab @samp{armv8.5-a}, @samp{+sve},
@samp{+sve2}
@item @samp{armv9.1-a} @tab Armv9.1-A @tab @samp{armv9-a}, @samp{+bf16},
@samp{+i8mm}
-@item @samp{armv9.2-a} @tab Armv9.2-A @tab @samp{armv9.1-a}
+@item @samp{armv9.2-a} @tab Armv9.2-A @tab @samp{armv9.1-a}, @samp{+wfxt},
@samp{+xs}
@item @samp{armv9.3-a} @tab Armv9.3-A @tab @samp{armv9.2-a}, @samp{+mops}
@item @samp{armv9.4-a} @tab Armv9.4-A @tab @samp{armv9.3-a}
@item @samp{armv9.5-a} @tab Armv9.4-A @tab @samp{armv9.4-a}, @samp{+faminmax},
@samp{+lut}
[gcc r15-7197] aarch64: Add command line support for armv9.5-a
https://gcc.gnu.org/g:c7847680cf18aaa26d607de5b3678c50470b9e87
commit r15-7197-gc7847680cf18aaa26d607de5b3678c50470b9e87
Author: Andrew Carlotti
Date: Fri Jan 10 19:19:19 2025 +
aarch64: Add command line support for armv9.5-a
gcc/ChangeLog:
* config/aarch64/aarch64-arches.def (V9_5A): New.
* doc/invoke.texi: Document armv9.5-a option.
gcc/testsuite/ChangeLog:
* gcc.target/aarch64/simd/armv9p5.c: New test.
Diff:
---
gcc/config/aarch64/aarch64-arches.def | 1 +
gcc/doc/invoke.texi | 1 +
gcc/testsuite/gcc.target/aarch64/simd/armv9p5.c | 14 ++
3 files changed, 16 insertions(+)
diff --git a/gcc/config/aarch64/aarch64-arches.def
b/gcc/config/aarch64/aarch64-arches.def
index fd4881a8ebfb..dacb7b6f37a3 100644
--- a/gcc/config/aarch64/aarch64-arches.def
+++ b/gcc/config/aarch64/aarch64-arches.def
@@ -46,5 +46,6 @@ AARCH64_ARCH("armv9.1-a", generic_armv9_a, V9_1A,
9, (V8_6A, V9A))
AARCH64_ARCH("armv9.2-a", generic_armv9_a, V9_2A, 9, (V8_7A, V9_1A))
AARCH64_ARCH("armv9.3-a", generic_armv9_a, V9_3A, 9, (V8_8A, V9_2A))
AARCH64_ARCH("armv9.4-a", generic_armv9_a, V9_4A, 9, (V8_9A, V9_3A))
+AARCH64_ARCH("armv9.5-a", generic_armv9_a, V9_5A, 9, (V9_4A,
FAMINMAX, LUT))
#undef AARCH64_ARCH
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 2f5d60baadbe..819a68439342 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -21672,6 +21672,7 @@ and the features that they enable by default:
@item @samp{armv9.2-a} @tab Armv9.2-A @tab @samp{armv9.1-a}
@item @samp{armv9.3-a} @tab Armv9.3-A @tab @samp{armv9.2-a}, @samp{+mops}
@item @samp{armv9.4-a} @tab Armv9.4-A @tab @samp{armv9.3-a}
+@item @samp{armv9.5-a} @tab Armv9.4-A @tab @samp{armv9.4-a}, @samp{+faminmax},
@samp{+lut}
@item @samp{armv8-r} @tab Armv8-R @tab @samp{armv8-r}
@end multitable
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/armv9p5.c
b/gcc/testsuite/gcc.target/aarch64/simd/armv9p5.c
new file mode 100644
index ..6df47b8de1cc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/armv9p5.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=armv9.5-a" } */
+
+#include "arm_neon.h"
+
+int8x16_t foo (int8x16_t table, uint8x16_t indicies)
+{
+ return vluti2q_laneq_s8 (table, indicies, 1);
+}
+
+float32x4_t bar (float32x4_t a, float32x4_t b)
+{
+ return vaminq_f32 (a, b);
+}
[gcc r15-7196] aarch64: Make AARCH64_FL_CRYPTO always unset
https://gcc.gnu.org/g:b53781ce1e49fcaa18c2b7c0d4602c6ed780a9e9
commit r15-7196-gb53781ce1e49fcaa18c2b7c0d4602c6ed780a9e9
Author: Andrew Carlotti
Date: Thu Jan 9 19:33:25 2025 +
aarch64: Make AARCH64_FL_CRYPTO always unset
This feature flag bit only exists to support the +crypto alias. Outside
of option processing this bit needs to be set or unset consistently.
This patch goes with the latter option.
gcc/ChangeLog:
* common/config/aarch64/aarch64-common.cc: Assert that CRYPTO
bit is not set.
* config/aarch64/aarch64-feature-deps.h
(info.explicit_on): Unset CRYPTO bit.
(cpu_##CORE_IDENT): Ditto.
gcc/testsuite/ChangeLog:
* gcc.target/aarch64/crypto-alias-1.c: New test.
Diff:
---
gcc/common/config/aarch64/aarch64-common.cc | 4
gcc/config/aarch64/aarch64-feature-deps.h | 12
gcc/testsuite/gcc.target/aarch64/crypto-alias-1.c | 14 ++
3 files changed, 26 insertions(+), 4 deletions(-)
diff --git a/gcc/common/config/aarch64/aarch64-common.cc
b/gcc/common/config/aarch64/aarch64-common.cc
index 427a1938902c..ef4458fb6930 100644
--- a/gcc/common/config/aarch64/aarch64-common.cc
+++ b/gcc/common/config/aarch64/aarch64-common.cc
@@ -613,6 +613,10 @@ aarch64_get_extension_string_for_isa_flags
{
std::string outstr = "";
+ /* The CRYPTO bit should only be used to support the +crypto alias
+ during option processing, and should be cleared at all other times.
+ Verify this property for the supplied flags bitmask. */
+ gcc_assert (!(AARCH64_FL_CRYPTO & aarch64_isa_flags));
aarch64_feature_flags current_flags = default_arch_flags;
/* As a special case, do not assume that the assembler will enable CRC
diff --git a/gcc/config/aarch64/aarch64-feature-deps.h
b/gcc/config/aarch64/aarch64-feature-deps.h
index 67c3a5da8aa3..55a0dbfae610 100644
--- a/gcc/config/aarch64/aarch64-feature-deps.h
+++ b/gcc/config/aarch64/aarch64-feature-deps.h
@@ -56,7 +56,8 @@ get_enable (T1 i, Ts... args)
- explicit_on: the transitive closure of the features that an
explicit +FEATURE enables, including FLAG itself. This is
- always a superset of ENABLE
+ always a superset of ENABLE, except that the CRYPTO alias bit is
+ explicitly unset for consistency.
Also define a function FEATURE () that returns an info
(which is an empty structure, since all members are static).
@@ -69,7 +70,8 @@ template struct info;
template<> struct info { \
static constexpr auto flag = AARCH64_FL_##IDENT; \
static constexpr auto enable = flag | get_enable REQUIRES; \
-static constexpr auto explicit_on = enable | get_enable EXPLICIT_ON; \
+static constexpr auto explicit_on \
+ = (enable | get_enable EXPLICIT_ON) & ~AARCH64_FL_CRYPTO; \
}; \
constexpr aarch64_feature_flags info::flag; \
constexpr aarch64_feature_flags info::enable;
\
@@ -114,9 +116,11 @@ get_flags_off (aarch64_feature_flags mask)
#include "config/aarch64/aarch64-option-extensions.def"
/* Define cpu_ variables for each CPU, giving the transitive
- closure of all the features that the CPU supports. */
+ closure of all the features that the CPU supports. The CRYPTO bit is just
+ an alias, so explicitly unset it for consistency. */
#define AARCH64_CORE(A, CORE_IDENT, C, ARCH_IDENT, FEATURES, F, G, H, I) \
- constexpr auto cpu_##CORE_IDENT = ARCH_IDENT ().enable | get_enable FEATURES;
+ constexpr auto cpu_##CORE_IDENT \
+= (ARCH_IDENT ().enable | get_enable FEATURES) & ~AARCH64_FL_CRYPTO;
#include "config/aarch64/aarch64-cores.def"
/* Define fmv_deps_ variables for each FMV feature, giving the transitive
diff --git a/gcc/testsuite/gcc.target/aarch64/crypto-alias-1.c
b/gcc/testsuite/gcc.target/aarch64/crypto-alias-1.c
new file mode 100644
index ..e2662b44e2db
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/crypto-alias-1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-mcpu=ampere1" } */
+
+__attribute__ ((__always_inline__))
+__attribute__ ((target ("arch=armv8-a+crypto")))
+inline int bar()
+{
+ return 5;
+}
+
+int foo()
+{
+ return bar();
+}
[gcc(refs/users/meissner/heads/work191-bugs)] Fix PR 118541, do not generate unordered fp cmoves.
https://gcc.gnu.org/g:c5a8e825798ddc63a4faef5776dd36a2256027e4
commit c5a8e825798ddc63a4faef5776dd36a2256027e4
Author: Michael Meissner
Date: Fri Jan 24 14:14:10 2025 -0500
Fix PR 118541, do not generate unordered fp cmoves.
2025-01-24 Michael Meissner
gcc/
PR target/118541
* config/rs6000/rs6000-protos.h (rs6000_reverse_condition): Add
argument.
* config/rs6000/rs6000.cc (rs6000_reverse_condition): Do not allow
ordered comparisons to be reversed for floating point cmoves.
(rs6000_emit_sCOND): Adjust rs6000_reverse_condition call.
* config/rs6000/rs6000.h (REVERSE_CONDITION): Likewise.
* config/rs6000/rs6000.md (reverse_branch_comparison): Name insn.
Adjust rs6000_reverse_condition call.
gcc/testsuite/
PR target/118541
* gcc.target/powerpc/pr118541.c: New test.
Diff:
---
gcc/config/rs6000/rs6000-protos.h | 9 ++-
gcc/config/rs6000/rs6000.cc | 42 +
gcc/config/rs6000/rs6000.h | 10 +--
gcc/config/rs6000/rs6000.md | 24 ++---
gcc/testsuite/gcc.target/powerpc/pr118541.c | 42 +
5 files changed, 104 insertions(+), 23 deletions(-)
diff --git a/gcc/config/rs6000/rs6000-protos.h
b/gcc/config/rs6000/rs6000-protos.h
index 4619142d197b..fc110fb0276b 100644
--- a/gcc/config/rs6000/rs6000-protos.h
+++ b/gcc/config/rs6000/rs6000-protos.h
@@ -114,8 +114,15 @@ extern const char *rs6000_sibcall_template (rtx *,
unsigned int);
extern const char *rs6000_indirect_call_template (rtx *, unsigned int);
extern const char *rs6000_indirect_sibcall_template (rtx *, unsigned int);
extern const char *rs6000_pltseq_template (rtx *, int);
+
+enum reverse_cond_type {
+ REVERSE_COND_NO_CMOVE,
+ REVERSE_COND_MAYBE_CMOVE
+};
+
extern enum rtx_code rs6000_reverse_condition (machine_mode,
- enum rtx_code);
+ enum rtx_code,
+ enum reverse_cond_type);
extern rtx rs6000_emit_eqne (machine_mode, rtx, rtx, rtx);
extern rtx rs6000_emit_fp_cror (rtx_code, machine_mode, rtx);
extern void rs6000_emit_sCOND (machine_mode, rtx[]);
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index f9f9a0b931db..99c7cc73e08c 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -15360,17 +15360,34 @@ rs6000_print_patchable_function_entry (FILE *file,
}
enum rtx_code
-rs6000_reverse_condition (machine_mode mode, enum rtx_code code)
+rs6000_reverse_condition (machine_mode mode,
+ enum rtx_code code,
+ enum reverse_cond_type type)
{
/* Reversal of FP compares takes care -- an ordered compare
- becomes an unordered compare and vice versa. */
- if (mode == CCFPmode
- && (!flag_finite_math_only
- || code == UNLT || code == UNLE || code == UNGT || code == UNGE
- || code == UNEQ || code == LTGT))
-return reverse_condition_maybe_unordered (code);
- else
-return reverse_condition (code);
+ becomes an unordered compare and vice versa.
+
+ However, this is not safe for ordered comparisons (i.e. for isgreater,
+ etc.) starting with the power9 because ifcvt.cc will want to create a fp
+ cmove, and the x{s,v}cmp{eq,gt,ge}{dp,qp} instructions will trap if one of
+ the arguments is a signalling NaN. */
+
+ if (mode == CCFPmode)
+{
+ if (code == UNLT || code == UNLE || code == UNGT || code == UNGE
+ || code == UNEQ || code == LTGT)
+ {
+ if (type == REVERSE_COND_MAYBE_CMOVE && !flag_finite_math_only)
+ return UNKNOWN;
+
+ return reverse_condition_maybe_unordered (code);
+ }
+
+ else if (!flag_finite_math_only)
+ return reverse_condition_maybe_unordered (code);
+}
+
+ return reverse_condition (code);
}
/* Check if C (as 64bit integer) can be rotated to a constant which constains
@@ -15983,8 +16000,11 @@ rs6000_emit_sCOND (machine_mode mode, rtx operands[])
cc_mode = GET_MODE (XEXP (condition_rtx, 0));
- rev_cond_rtx = gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode,
cond_code),
-SImode, XEXP (condition_rtx, 0),
const0_rtx);
+ enum rtx_code rev
+ = rs6000_reverse_condition (cc_mode, cond_code, REVERSE_COND_NO_CMOVE);
+
+ rev_cond_rtx = gen_rtx_fmt_ee (rev, SImode, XEXP (condition_rtx, 0),
+const0_rtx);
not_op = gen_rtx_COMPARE (CCEQmode, rev_cond_rtx, const0_rtx);
emit_insn (gen_rtx_SET (not_result, not_op));
condition_rtx = gen_rtx_EQ (VOIDmode, not_result, const0_rtx);
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index ec08c96d0f67..9894adf414b
[gcc r15-7193] aarch64: Inline aarch64_get_all_extension_candidates
https://gcc.gnu.org/g:1edf47698a8204da74a6f154b7380f6016f2f78b
commit r15-7193-g1edf47698a8204da74a6f154b7380f6016f2f78b
Author: Andrew Carlotti
Date: Thu Jan 23 17:24:17 2025 +
aarch64: Inline aarch64_get_all_extension_candidates
gcc/ChangeLog:
* common/config/aarch64/aarch64-common.cc
(aarch64_get_all_extension_candidates): Inline into...
(aarch64_print_hint_for_extensions): ...this.
Diff:
---
gcc/common/config/aarch64/aarch64-common.cc | 15 ---
1 file changed, 4 insertions(+), 11 deletions(-)
diff --git a/gcc/common/config/aarch64/aarch64-common.cc
b/gcc/common/config/aarch64/aarch64-common.cc
index c3ea54ca3f77..9923437761c9 100644
--- a/gcc/common/config/aarch64/aarch64-common.cc
+++ b/gcc/common/config/aarch64/aarch64-common.cc
@@ -223,16 +223,6 @@ aarch64_print_hint_candidates (const char *str,
XDELETEVEC (s);
}
-/* Append all architecture extension candidates to the CANDIDATES vector. */
-
-void
-aarch64_get_all_extension_candidates (auto_vec *candidates)
-{
- const struct aarch64_extension_info *opt;
- for (opt = all_extensions; opt->name != NULL; opt++)
-candidates->safe_push (opt->name);
-}
-
/* Print a hint with a suggestion for an extension name
that most closely resembles what the user passed in STR. */
@@ -240,7 +230,10 @@ void
aarch64_print_hint_for_extensions (const char *str)
{
auto_vec candidates;
- aarch64_get_all_extension_candidates (&candidates);
+ const struct aarch64_extension_info *opt;
+ for (opt = all_extensions; opt->name != NULL; opt++)
+candidates.safe_push (opt->name);
+
aarch64_print_hint_candidates (str, candidates);
}
[gcc r15-7190] aarch64: Adjust option parsing parameter types.
https://gcc.gnu.org/g:1ba5027ebfe96b507d32f884a0ee8064cbbbc15d
commit r15-7190-g1ba5027ebfe96b507d32f884a0ee8064cbbbc15d
Author: Andrew Carlotti
Date: Wed Jan 8 23:52:01 2025 +
aarch64: Adjust option parsing parameter types.
Replace `const struct processor *` in output parameters with
`aarch64_arch` or `aarch64_cpu`.
Replace `std:string` parameter in aarch64_print_hint_for_extensions with
`char *`.
Also name the return parameters more clearly and consistently.
gcc/ChangeLog:
* config/aarch64/aarch64.cc
(aarch64_print_hint_for_extensions): Receive string as a char *.
(aarch64_parse_arch): Don't return a const struct processor *.
(aarch64_parse_cpu): Ditto.
(aarch64_parse_tune): Ditto.
(aarch64_validate_mtune): Ditto.
(aarch64_validate_mcpu): Ditto, and use temporary variables for
march/mcpu cross-check.
(aarch64_validate_march): Ditto.
(aarch64_override_options): Adjust for changed parameter types.
(aarch64_handle_attr_arch): Ditto.
(aarch64_handle_attr_cpu): Ditto.
(aarch64_handle_attr_tune): Ditto.
Diff:
---
gcc/config/aarch64/aarch64.cc | 174 ++
1 file changed, 93 insertions(+), 81 deletions(-)
diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc
index 4d3b28b4cdb4..56c9f66861b3 100644
--- a/gcc/config/aarch64/aarch64.cc
+++ b/gcc/config/aarch64/aarch64.cc
@@ -18224,16 +18224,16 @@ better_main_loop_than_p (const vector_costs
*uncast_other) const
static void initialize_aarch64_code_model (struct gcc_options *);
-/* Parse the TO_PARSE string and put the architecture struct that it
- selects into RES and the architectural features into ISA_FLAGS.
+/* Parse the TO_PARSE string and put the architecture that it
+ selects into RES_ARCH and the architectural features into RES_FLAGS.
Return an aarch_parse_opt_result describing the parse result.
- If there is an error parsing, RES and ISA_FLAGS are left unchanged.
+ If there is an error parsing, RES_ARCH and RES_FLAGS are left unchanged.
When the TO_PARSE string contains an invalid extension,
a copy of the string is created and stored to INVALID_EXTENSION. */
static enum aarch_parse_opt_result
-aarch64_parse_arch (const char *to_parse, const struct processor **res,
- aarch64_feature_flags *isa_flags,
+aarch64_parse_arch (const char *to_parse, aarch64_arch *res_arch,
+ aarch64_feature_flags *res_flags,
std::string *invalid_extension)
{
const char *ext;
@@ -18257,21 +18257,21 @@ aarch64_parse_arch (const char *to_parse, const
struct processor **res,
if (strlen (arch->name) == len
&& strncmp (arch->name, to_parse, len) == 0)
{
- auto isa_temp = arch->flags;
+ auto isa_flags = arch->flags;
if (ext != NULL)
{
/* TO_PARSE string contains at least one extension. */
enum aarch_parse_opt_result ext_res
- = aarch64_parse_extension (ext, &isa_temp, invalid_extension);
+ = aarch64_parse_extension (ext, &isa_flags, invalid_extension);
if (ext_res != AARCH_PARSE_OK)
return ext_res;
}
/* Extension parsing was successful. Confirm the result
arch and ISA flags. */
- *res = arch;
- *isa_flags = isa_temp;
+ *res_arch = arch->arch;
+ *res_flags = isa_flags;
return AARCH_PARSE_OK;
}
}
@@ -18280,16 +18280,16 @@ aarch64_parse_arch (const char *to_parse, const
struct processor **res,
return AARCH_PARSE_INVALID_ARG;
}
-/* Parse the TO_PARSE string and put the result tuning in RES and the
- architecture flags in ISA_FLAGS. Return an aarch_parse_opt_result
- describing the parse result. If there is an error parsing, RES and
- ISA_FLAGS are left unchanged.
+/* Parse the TO_PARSE string and put the result tuning in RES_CPU and the
+ architecture flags in RES_FLAGS. Return an aarch_parse_opt_result
+ describing the parse result. If there is an error parsing, RES_CPU and
+ RES_FLAGS are left unchanged.
When the TO_PARSE string contains an invalid extension,
a copy of the string is created and stored to INVALID_EXTENSION. */
static enum aarch_parse_opt_result
-aarch64_parse_cpu (const char *to_parse, const struct processor **res,
- aarch64_feature_flags *isa_flags,
+aarch64_parse_cpu (const char *to_parse, aarch64_cpu *res_cpu,
+ aarch64_feature_flags *res_flags,
std::string *invalid_extension)
{
const char *ext;
@@ -18312,21 +18312,21 @@ aarch64_parse_cpu (const char *to_parse, const struct
processor **res,
{
if (strlen (cpu->name) == len && strncmp (cpu->name, to_parse, len) == 0)
[gcc r15-7188] aarch64: Remove redundant generic cpu entry
https://gcc.gnu.org/g:362cdb70bc25598e17f79b604975d63ccad13a4f
commit r15-7188-g362cdb70bc25598e17f79b604975d63ccad13a4f
Author: Andrew Carlotti
Date: Wed Jan 8 20:27:17 2025 +
aarch64: Remove redundant generic cpu entry
The list of cores in aarch64-common.cc included an explicit "generic"
entry, despite this entry also being present in aarch64-cores.def.
gcc/ChangeLog:
* common/config/aarch64/aarch64-common.cc
(all_cores): Remove explicit generic entry.
Diff:
---
gcc/common/config/aarch64/aarch64-common.cc | 1 -
1 file changed, 1 deletion(-)
diff --git a/gcc/common/config/aarch64/aarch64-common.cc
b/gcc/common/config/aarch64/aarch64-common.cc
index 92df8b619305..75600548fdc6 100644
--- a/gcc/common/config/aarch64/aarch64-common.cc
+++ b/gcc/common/config/aarch64/aarch64-common.cc
@@ -189,7 +189,6 @@ static constexpr processor_name_to_arch all_cores[] =
#define AARCH64_CORE(NAME, CORE_IDENT, C, ARCH_IDENT, E, F, G, H, I) \
{NAME, AARCH64_ARCH_##ARCH_IDENT, feature_deps::cpu_##CORE_IDENT},
#include "config/aarch64/aarch64-cores.def"
- {"generic", AARCH64_ARCH_V8A, feature_deps::V8A ().enable},
{"", aarch64_no_arch, 0}
};
[gcc(refs/users/meissner/heads/work191-bugs)] Update ChangeLog.*
https://gcc.gnu.org/g:6e266df2d8f29e67238deef2b32bfe85dce5e786 commit 6e266df2d8f29e67238deef2b32bfe85dce5e786 Author: Michael Meissner Date: Fri Jan 24 14:15:25 2025 -0500 Update ChangeLog.* Diff: --- gcc/ChangeLog.bugs | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/gcc/ChangeLog.bugs b/gcc/ChangeLog.bugs index ebcb80cf743c..2effbb957737 100644 --- a/gcc/ChangeLog.bugs +++ b/gcc/ChangeLog.bugs @@ -1,4 +1,4 @@ - Branch work191-bugs, patch #211 + Branch work191-bugs, patch #212 Fix PR 118541, do not generate unordered fp cmoves. @@ -13,13 +13,15 @@ gcc/ ordered comparisons to be reversed for floating point cmoves. (rs6000_emit_sCOND): Adjust rs6000_reverse_condition call. * config/rs6000/rs6000.h (REVERSE_CONDITION): Likewise. - * config/rs6000/rs6000.md (reverse_branch_comparison): Likewise. + * config/rs6000/rs6000.md (reverse_branch_comparison): Name insn. + Adjust rs6000_reverse_condition call. gcc/testsuite/ PR target/118541 * gcc.target/powerpc/pr118541.c: New test. + Branch work191-bugs, patch #211 was reverted Branch work191-bugs, patch #210 was reverted Branch work191-bugs, patch #202
[gcc r15-7175] tree-optimization/118634 - improve cunroll dump
https://gcc.gnu.org/g:dc1e1b38ce60cd1da781c7dcd97a36add5482a00
commit r15-7175-gdc1e1b38ce60cd1da781c7dcd97a36add5482a00
Author: Richard Biener
Date: Fri Jan 24 09:13:17 2025 +0100
tree-optimization/118634 - improve cunroll dump
We no longer subtract the estimated eliminated number of instructions
from the estimated size after unrolling we print - this is a bit
confusing when comparing dumps to previous releases. The following
changes the dump from
Estimated size after unrolling: 42
to
Estimated size after unrolling: 42-12
for the testcase in the PR.
PR tree-optimization/118634
* tree-ssa-loop-ivcanon.cc (try_unroll_loop_completely):
Dump the number of estimated eliminated insns.
Diff:
---
gcc/tree-ssa-loop-ivcanon.cc | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/gcc/tree-ssa-loop-ivcanon.cc b/gcc/tree-ssa-loop-ivcanon.cc
index d07b3d593f59..ca6295c7de2f 100644
--- a/gcc/tree-ssa-loop-ivcanon.cc
+++ b/gcc/tree-ssa-loop-ivcanon.cc
@@ -855,8 +855,8 @@ try_unroll_loop_completely (class loop *loop,
if (dump_file && (dump_flags & TDF_DETAILS))
{
fprintf (dump_file, " Loop size: %d\n", (int) ninsns);
- fprintf (dump_file, " Estimated size after unrolling: %d\n",
- (int) unr_insns);
+ fprintf (dump_file, " Estimated size after unrolling: %d-%d\n",
+ (int) unr_insns, (int) est_eliminated);
}
/* If the code is going to shrink, we don't need to be extra
[gcc r15-7176] s390: Implement isfinite and isnormal optabs
https://gcc.gnu.org/g:b00bd29286345cc90afc61dcb16d1fa44976dae6
commit r15-7176-gb00bd29286345cc90afc61dcb16d1fa44976dae6
Author: Stefan Schulze Frielinghaus
Date: Fri Jan 24 12:53:44 2025 +0100
s390: Implement isfinite and isnormal optabs
Merge new optabs with the existing implementations for signbit and
isinf.
gcc/ChangeLog:
* config/s390/s390.h (S390_TDC_POSITIVE_ZERO): Remove.
(S390_TDC_NEGATIVE_ZERO): Remove.
(S390_TDC_POSITIVE_NORMALIZED_BFP_NUMBER): Remove.
(S390_TDC_NEGATIVE_NORMALIZED_BFP_NUMBER): Remove.
(S390_TDC_POSITIVE_DENORMALIZED_BFP_NUMBER): Remove.
(S390_TDC_NEGATIVE_DENORMALIZED_BFP_NUMBER): Remove.
(S390_TDC_POSITIVE_INFINITY): Remove.
(S390_TDC_NEGATIVE_INFINITY): Remove.
(S390_TDC_POSITIVE_QUIET_NAN): Remove.
(S390_TDC_NEGATIVE_QUIET_NAN): Remove.
(S390_TDC_POSITIVE_SIGNALING_NAN): Remove.
(S390_TDC_NEGATIVE_SIGNALING_NAN): Remove.
(S390_TDC_POSITIVE_DENORMALIZED_DFP_NUMBER): Remove.
(S390_TDC_NEGATIVE_DENORMALIZED_DFP_NUMBER): Remove.
(S390_TDC_POSITIVE_NORMALIZED_DFP_NUMBER): Remove.
(S390_TDC_NEGATIVE_NORMALIZED_DFP_NUMBER): Remove.
(S390_TDC_SIGNBIT_SET): Remove.
(S390_TDC_INFINITY): Remove.
* config/s390/s390.md (signbit2): Merge this one
(isinf2): and this one into
(2): new expander.
(isnormal2): New BFP expander.
(isnormal2): New DFP expander.
* config/s390/vector.md (signbittf2_vr): Merge this one
(isinftf2_vr): and this one into
(tf2_vr): new expander.
(signbittf2): Merge this one
(isinftf2): and this one into
(tf2): new expander.
gcc/testsuite/ChangeLog:
* gcc.target/s390/isfinite-isinf-isnormal-signbit-1.c: New test.
* gcc.target/s390/isfinite-isinf-isnormal-signbit-2.c: New test.
* gcc.target/s390/isfinite-isinf-isnormal-signbit-3.c: New test.
* gcc.target/s390/isfinite-isinf-isnormal-signbit.h: New test.
Diff:
---
gcc/config/s390/s390.h | 31 --
gcc/config/s390/s390.md| 114 +
gcc/config/s390/vector.md | 42 ++--
.../s390/isfinite-isinf-isnormal-signbit-1.c | 62 +++
.../s390/isfinite-isinf-isnormal-signbit-2.c | 13 +++
.../s390/isfinite-isinf-isnormal-signbit-3.c | 13 +++
.../s390/isfinite-isinf-isnormal-signbit.h | 23 +
7 files changed, 215 insertions(+), 83 deletions(-)
diff --git a/gcc/config/s390/s390.h b/gcc/config/s390/s390.h
index 957877b6a389..6f7195db04e1 100644
--- a/gcc/config/s390/s390.h
+++ b/gcc/config/s390/s390.h
@@ -305,37 +305,6 @@ extern const char *s390_host_detect_local_cpu (int argc,
const char **argv);
"%{!mesa:%{!mzarch:%{m31:-mesa}%{m64:-mzarch}}}",\
"%{!march=*:-march=z900}"
-/* Constants needed to control the TEST DATA CLASS (TDC) instruction. */
-#define S390_TDC_POSITIVE_ZERO (1 << 11)
-#define S390_TDC_NEGATIVE_ZERO (1 << 10)
-#define S390_TDC_POSITIVE_NORMALIZED_BFP_NUMBER(1 << 9)
-#define S390_TDC_NEGATIVE_NORMALIZED_BFP_NUMBER(1 << 8)
-#define S390_TDC_POSITIVE_DENORMALIZED_BFP_NUMBER (1 << 7)
-#define S390_TDC_NEGATIVE_DENORMALIZED_BFP_NUMBER (1 << 6)
-#define S390_TDC_POSITIVE_INFINITY (1 << 5)
-#define S390_TDC_NEGATIVE_INFINITY (1 << 4)
-#define S390_TDC_POSITIVE_QUIET_NAN(1 << 3)
-#define S390_TDC_NEGATIVE_QUIET_NAN(1 << 2)
-#define S390_TDC_POSITIVE_SIGNALING_NAN(1 << 1)
-#define S390_TDC_NEGATIVE_SIGNALING_NAN(1 << 0)
-
-/* The following values are different for DFP. */
-#define S390_TDC_POSITIVE_DENORMALIZED_DFP_NUMBER (1 << 9)
-#define S390_TDC_NEGATIVE_DENORMALIZED_DFP_NUMBER (1 << 8)
-#define S390_TDC_POSITIVE_NORMALIZED_DFP_NUMBER (1 << 7)
-#define S390_TDC_NEGATIVE_NORMALIZED_DFP_NUMBER (1 << 6)
-
-/* For signbit, the BFP-DFP-difference makes no difference. */
-#define S390_TDC_SIGNBIT_SET (S390_TDC_NEGATIVE_ZERO \
- | S390_TDC_NEGATIVE_NORMALIZED_BFP_NUMBER \
- | S390_TDC_NEGATIVE_DENORMALIZED_BFP_NUMBER\
- | S390_TDC_NEGATIVE_INFINITY \
- | S390_TDC_NEGATIVE_QUIET_NAN \
- | S390_TDC_NEGATIVE_SIGNALING_NAN )
-
-#define S390_TDC_INFINITY (S390_TDC_POSITIVE_INFINITY \
- | S390_TDC_NEGATIVE_INFINITY )
-
/* Target machine storage layout. */
/* Everything is big-endian. */
diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md
index 8ce93a048734..c164ea72c78b 100644
--- a/gcc/config/s390/s390.md
+++ b/gcc/config/s390/s390
[gcc r15-7177] tree-optimization/116010 - dr_may_alias regression
https://gcc.gnu.org/g:02fc12b04017d20345e208d65fd7a33d62f0cded
commit r15-7177-g02fc12b04017d20345e208d65fd7a33d62f0cded
Author: Richard Biener
Date: Fri Jan 24 13:20:12 2025 +0100
tree-optimization/116010 - dr_may_alias regression
r15-491-gc290e6a0b7a9de fixed a latent issue with dr_analyze_innermost
and dr_may_alias where not properly analyzed DRs would yield an invalid
answer. This caused some missed optimizations in case there is not
actually any evolution in the not analyzed base part. The following
recovers this by only handling base parts which reference SSA vars
as index in the conservative way.
The gfortran.dg/vect/vect-8.f90 testcase is difficult to deal with,
so the following merely bumps the maximum number of expected vectorized
loops
for both aarch64 and x86-64.
PR tree-optimization/116010
* tree-data-ref.cc (contains_ssa_ref_p_1): New function.
(contains_ssa_ref_p): Likewise.
(dr_may_alias_p): Avoid treating unanalyzed base parts without
SSA reference conservatively.
* gfortran.dg/vect/vect-8.f90: Adjust.
Diff:
---
gcc/testsuite/gfortran.dg/vect/vect-8.f90 | 4 ++--
gcc/tree-data-ref.cc | 26 +-
2 files changed, 27 insertions(+), 3 deletions(-)
diff --git a/gcc/testsuite/gfortran.dg/vect/vect-8.f90
b/gcc/testsuite/gfortran.dg/vect/vect-8.f90
index d4ce44feb4b9..614c2a30e1b7 100644
--- a/gcc/testsuite/gfortran.dg/vect/vect-8.f90
+++ b/gcc/testsuite/gfortran.dg/vect/vect-8.f90
@@ -706,6 +706,6 @@ CALL track('KERNEL ')
RETURN
END SUBROUTINE kernel
-! { dg-final { scan-tree-dump-times "vectorized 2\[56\] loops" 1 "vect" {
target aarch64*-*-* } } }
-! { dg-final { scan-tree-dump-times "vectorized 2\[34567\] loops" 1 "vect" {
target { vect_intdouble_cvt && { ! aarch64*-*-* } } } } }
+! { dg-final { scan-tree-dump-times "vectorized 2\[5678\] loops" 1 "vect" {
target aarch64*-*-* } } }
+! { dg-final { scan-tree-dump-times "vectorized 2\[345678\] loops" 1 "vect" {
target { vect_intdouble_cvt && { ! aarch64*-*-* } } } } }
! { dg-final { scan-tree-dump-times "vectorized 17 loops" 1 "vect" { target {
{ ! vect_intdouble_cvt } && { ! aarch64*-*-* } } } } }
diff --git a/gcc/tree-data-ref.cc b/gcc/tree-data-ref.cc
index 08c14fe29f22..5decfb1abf51 100644
--- a/gcc/tree-data-ref.cc
+++ b/gcc/tree-data-ref.cc
@@ -2978,6 +2978,29 @@ object_address_invariant_in_loop_p (const class loop
*loop, const_tree obj)
loop->num);
}
+/* Helper for contains_ssa_ref_p. */
+
+static bool
+contains_ssa_ref_p_1 (tree, tree *idx, void *data)
+{
+ if (TREE_CODE (*idx) == SSA_NAME)
+{
+ *(bool *)data = true;
+ return false;
+}
+ return true;
+}
+
+/* Returns true if the reference REF contains a SSA index. */
+
+static bool
+contains_ssa_ref_p (tree ref)
+{
+ bool res = false;
+ for_each_index (&ref, contains_ssa_ref_p_1, &res);
+ return res;
+}
+
/* Returns false if we can prove that data references A and B do not alias,
true otherwise. If LOOP_NEST is false no cross-iteration aliases are
considered. */
@@ -3080,7 +3103,8 @@ dr_may_alias_p (const struct data_reference *a, const
struct data_reference *b,
possibly left with a non-base in which case we didn't analyze
a possible evolution of the base when analyzing a loop. */
else if (loop_nest
- && (handled_component_p (addr_a) || handled_component_p (addr_b)))
+ && ((handled_component_p (addr_a) && contains_ssa_ref_p (addr_a))
+ || (handled_component_p (addr_b) && contains_ssa_ref_p
(addr_b
{
/* For true dependences we can apply TBAA. */
if (flag_strict_aliasing
[gcc r14-11244] c++: ICE with nested anonymous union [PR117153]
https://gcc.gnu.org/g:504fbafd45a526f4851e7655d78d678d0c9eecbe
commit r14-11244-g504fbafd45a526f4851e7655d78d678d0c9eecbe
Author: Marek Polacek
Date: Mon Nov 25 09:45:13 2024 -0500
c++: ICE with nested anonymous union [PR117153]
In a template, for
union {
union {
T d;
};
};
build_anon_union_vars crates a malformed COMPONENT_REF: we have no
DECL_NAME for the nested anon union so we create something like "object.".
Most of the front end doesn't seem to care, but if such a tree gets to
potential_constant_expression, it can cause a crash.
We can use FIELD directly for the COMPONENT_REF's member. tsubst_stmt
should build up a proper one in:
if (VAR_P (decl) && !DECL_NAME (decl)
&& ANON_AGGR_TYPE_P (TREE_TYPE (decl)))
/* Anonymous aggregates are a special case. */
finish_anon_union (decl);
PR c++/117153
gcc/cp/ChangeLog:
* decl2.cc (build_anon_union_vars): Use FIELD for the second operand
of a COMPONENT_REF.
gcc/testsuite/ChangeLog:
* g++.dg/other/anon-union6.C: New test.
* g++.dg/other/anon-union7.C: New test.
Reviewed-by: Jason Merrill
(cherry picked from commit 10850f92b2a618ef1b1ad399530943ef4847823d)
Diff:
---
gcc/cp/decl2.cc | 2 +-
gcc/testsuite/g++.dg/other/anon-union6.C | 13 +
gcc/testsuite/g++.dg/other/anon-union7.C | 16
3 files changed, 30 insertions(+), 1 deletion(-)
diff --git a/gcc/cp/decl2.cc b/gcc/cp/decl2.cc
index f6c760338cc2..139b5c15b3e8 100644
--- a/gcc/cp/decl2.cc
+++ b/gcc/cp/decl2.cc
@@ -1951,7 +1951,7 @@ build_anon_union_vars (tree type, tree object)
if (processing_template_decl)
ref = build_min_nt_loc (UNKNOWN_LOCATION, COMPONENT_REF, object,
- DECL_NAME (field), NULL_TREE);
+ field, NULL_TREE);
else
ref = build_class_member_access_expr (object, field, NULL_TREE,
false, tf_warning_or_error);
diff --git a/gcc/testsuite/g++.dg/other/anon-union6.C
b/gcc/testsuite/g++.dg/other/anon-union6.C
new file mode 100644
index ..d1cde30f790d
--- /dev/null
+++ b/gcc/testsuite/g++.dg/other/anon-union6.C
@@ -0,0 +1,13 @@
+// PR c++/117153
+// { dg-do compile }
+
+template
+void f() {
+ union {
+union {
+ T d;
+};
+ };
+ (void) (d + 0);
+}
+template void f();
diff --git a/gcc/testsuite/g++.dg/other/anon-union7.C
b/gcc/testsuite/g++.dg/other/anon-union7.C
new file mode 100644
index ..e89334a5d0e7
--- /dev/null
+++ b/gcc/testsuite/g++.dg/other/anon-union7.C
@@ -0,0 +1,16 @@
+// PR c++/117153
+// { dg-do compile { target c++11 } }
+
+using U = union { union { int a; }; };
+
+U
+foo ()
+{
+ return {};
+}
+
+void
+g ()
+{
+ [[maybe_unused]] auto u = foo ();
+}
[gcc(refs/users/meissner/heads/work191-bugs)] Fix PR 118541, do not generate unordered fp cmoves.
https://gcc.gnu.org/g:06b9f3906cd13c0f840803d90077d40a9598cc10
commit 06b9f3906cd13c0f840803d90077d40a9598cc10
Author: Michael Meissner
Date: Fri Jan 24 12:28:40 2025 -0500
Fix PR 118541, do not generate unordered fp cmoves.
2025-01-24 Michael Meissner
gcc/
PR target/118541
* config/rs6000/rs6000-protos.h (rs6000_reverse_condition): Add
argument.
* config/rs6000/rs6000.cc (rs6000_reverse_condition): Do not allow
ordered comparisons to be reversed for floating point cmoves.
(rs6000_emit_sCOND): Adjust rs6000_reverse_condition call.
* config/rs6000/rs6000.h (REVERSE_CONDITION): Likewise.
* config/rs6000/rs6000.md (reverse_branch_comparison): Likewise.
gcc/testsuite/
PR target/118541
* gcc.target/powerpc/pr118541.c: New test.
Diff:
---
gcc/config/rs6000/rs6000-protos.h | 9 ++-
gcc/config/rs6000/rs6000.cc | 35 +---
gcc/config/rs6000/rs6000.h | 10 +--
gcc/config/rs6000/rs6000.md | 24 ++---
gcc/testsuite/gcc.target/powerpc/pr118541.c | 42 +
5 files changed, 98 insertions(+), 22 deletions(-)
diff --git a/gcc/config/rs6000/rs6000-protos.h
b/gcc/config/rs6000/rs6000-protos.h
index 4619142d197b..3378824c4824 100644
--- a/gcc/config/rs6000/rs6000-protos.h
+++ b/gcc/config/rs6000/rs6000-protos.h
@@ -114,8 +114,15 @@ extern const char *rs6000_sibcall_template (rtx *,
unsigned int);
extern const char *rs6000_indirect_call_template (rtx *, unsigned int);
extern const char *rs6000_indirect_sibcall_template (rtx *, unsigned int);
extern const char *rs6000_pltseq_template (rtx *, int);
+
+enum rev_cond_type {
+ REV_COND_MAYBE_CMOVE,
+ REV_COND_NOT_CMOVE
+};
+
extern enum rtx_code rs6000_reverse_condition (machine_mode,
- enum rtx_code);
+ enum rtx_code,
+ enum rev_cond_type);
extern rtx rs6000_emit_eqne (machine_mode, rtx, rtx, rtx);
extern rtx rs6000_emit_fp_cror (rtx_code, machine_mode, rtx);
extern void rs6000_emit_sCOND (machine_mode, rtx[]);
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index f9f9a0b931db..1b787c4b1fa1 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -15360,17 +15360,31 @@ rs6000_print_patchable_function_entry (FILE *file,
}
enum rtx_code
-rs6000_reverse_condition (machine_mode mode, enum rtx_code code)
+rs6000_reverse_condition (machine_mode mode,
+ enum rtx_code code,
+ enum rev_cond_type type)
{
/* Reversal of FP compares takes care -- an ordered compare
- becomes an unordered compare and vice versa. */
- if (mode == CCFPmode
- && (!flag_finite_math_only
- || code == UNLT || code == UNLE || code == UNGT || code == UNGE
- || code == UNEQ || code == LTGT))
-return reverse_condition_maybe_unordered (code);
- else
-return reverse_condition (code);
+ becomes an unordered compare and vice versa.
+
+ However, this is not safe for ordered comparisons (i.e. for isgreater,
+ etc.) starting with the power9 because ifcvt.cc will want to create a
+ floating point conditional move, and the x{s,v}cmp{eq,gt,ge}{dp,qp}
+ instructions will trap if one of the arguments is a signalling NaN. */
+
+ if (mode == CCFPmode)
+{
+ if (code == UNLT || code == UNLE || code == UNGT || code == UNGE
+ || code == UNEQ || code == LTGT)
+ return (type == REV_COND_MAYBE_CMOVE
+ ? UNKNOWN
+ : reverse_condition_maybe_unordered (code));
+
+ if (!flag_finite_math_only)
+ return reverse_condition_maybe_unordered (code);
+}
+
+ return reverse_condition (code);
}
/* Check if C (as 64bit integer) can be rotated to a constant which constains
@@ -15983,7 +15997,8 @@ rs6000_emit_sCOND (machine_mode mode, rtx operands[])
cc_mode = GET_MODE (XEXP (condition_rtx, 0));
- rev_cond_rtx = gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode,
cond_code),
+ rev_cond_rtx = gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode,
cond_code,
+
REV_COND_NOT_CMOVE),
SImode, XEXP (condition_rtx, 0),
const0_rtx);
not_op = gen_rtx_COMPARE (CCEQmode, rev_cond_rtx, const0_rtx);
emit_insn (gen_rtx_SET (not_result, not_op));
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index ec08c96d0f67..fc3b323a85e7 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -1812,11 +1812,17 @@ extern scalar_int_mode rs6000_pmode;
/* Can the condition code MODE be safely reversed? This is safe in
all cases on this port, because
[gcc r15-7185] [PR118497][IRA]: Fix calculation of cost of assigning callee-saved hard reg
https://gcc.gnu.org/g:c4dae80357ccf2e035d8e9ec0a3bb319344c5b41
commit r15-7185-gc4dae80357ccf2e035d8e9ec0a3bb319344c5b41
Author: Vladimir N. Makarov
Date: Fri Jan 24 13:16:53 2025 -0500
[PR118497][IRA]: Fix calculation of cost of assigning callee-saved hard reg
Assembler code generated by GCC for PR118497 contains unnecessary
move insn. This happened as IRA assigns AX reg to a pseudo which
should be in BX reg later for a call. The pseudo did not get BX as
LRA decided that it requires to save BX although BX will be saved
anyway. The patch fixes the cost calculation. Usage of hard reg
nrefs from regstat or DF will result in numerous failures as such
nrefs include artificial reg refs. Therefore we add a calculation of
hard reg nrefs in IRA. Also we change regexp used for scanning the
assembler in test vartrack-1.c as with the patch LRA assigns
callee-saved hard reg BP instead of another callee-saved hard reg BX
expected by the test.
gcc/ChangeLog:
PR target/118497
* ira-int.h (target_ira_int): Add x_ira_hard_regno_nrefs.
(ira_hard_regno_nrefs): New macro.
* ira.cc (setup_hard_regno_aclass): Remove unused code. Modify
the comment.
(setup_hard_regno_nrefs): New function.
(ira): Call it.
* ira-color.cc (calculate_saved_nregs): Check
ira_hard_regno_nrefs.
gcc/testsuite/ChangeLog:
PR target/118497
* gcc.target/i386/pr118497.c: New.
* gcc.target/i386/vartrack-1.c: Modify the regexp.
Diff:
---
gcc/ira-color.cc | 1 +
gcc/ira-int.h | 5
gcc/ira.cc | 42 ++
gcc/testsuite/gcc.target/i386/pr118497.c | 16
gcc/testsuite/gcc.target/i386/vartrack-1.c | 12 -
5 files changed, 54 insertions(+), 22 deletions(-)
diff --git a/gcc/ira-color.cc b/gcc/ira-color.cc
index 23f68c007573..0699b349a1af 100644
--- a/gcc/ira-color.cc
+++ b/gcc/ira-color.cc
@@ -1752,6 +1752,7 @@ calculate_saved_nregs (int hard_regno, machine_mode mode)
ira_assert (hard_regno >= 0);
for (i = hard_regno_nregs (hard_regno, mode) - 1; i >= 0; i--)
if (!allocated_hardreg_p[hard_regno + i]
+ && ira_hard_regno_nrefs[hard_regno + i] == 0
&& !crtl->abi->clobbers_full_reg_p (hard_regno + i)
&& !LOCAL_REGNO (hard_regno + i))
nregs++;
diff --git a/gcc/ira-int.h b/gcc/ira-int.h
index aa8432416fce..49e086e4d4b1 100644
--- a/gcc/ira-int.h
+++ b/gcc/ira-int.h
@@ -936,6 +936,9 @@ public:
/* Flag of that the above array has been initialized. */
bool x_ira_prohibited_mode_move_regs_initialized_p;
+
+ /* Number of real occurences of hard regs before IRA. */
+ size_t x_ira_hard_regno_nrefs[FIRST_PSEUDO_REGISTER];
};
extern class target_ira_int default_target_ira_int;
@@ -983,6 +986,8 @@ extern class target_ira_int *this_target_ira_int;
(this_target_ira_int->x_ira_reg_class_superunion)
#define ira_prohibited_mode_move_regs \
(this_target_ira_int->x_ira_prohibited_mode_move_regs)
+#define ira_hard_regno_nrefs \
+ (this_target_ira_int->x_ira_hard_regno_nrefs)
/* ira.cc: */
diff --git a/gcc/ira.cc b/gcc/ira.cc
index ad522b00f8b5..885239d1b43c 100644
--- a/gcc/ira.cc
+++ b/gcc/ira.cc
@@ -1416,7 +1416,7 @@ find_reg_classes (void)
-/* Set up the array above. */
+/* Set up array ira_hard_regno_allocno_class. */
static void
setup_hard_regno_aclass (void)
{
@@ -1424,25 +1424,10 @@ setup_hard_regno_aclass (void)
for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
{
-#if 1
ira_hard_regno_allocno_class[i]
= (TEST_HARD_REG_BIT (no_unit_alloc_regs, i)
? NO_REGS
: ira_allocno_class_translate[REGNO_REG_CLASS (i)]);
-#else
- int j;
- enum reg_class cl;
- ira_hard_regno_allocno_class[i] = NO_REGS;
- for (j = 0; j < ira_allocno_classes_num; j++)
- {
- cl = ira_allocno_classes[j];
- if (ira_class_hard_reg_index[cl][i] >= 0)
- {
- ira_hard_regno_allocno_class[i] = cl;
- break;
- }
- }
-#endif
}
}
@@ -5549,6 +5534,30 @@ static int saved_flag_ira_share_spill_slots;
/* Set to true while in IRA. */
bool ira_in_progress = false;
+/* Set up array ira_hard_regno_nrefs. */
+static void
+setup_hard_regno_nrefs (void)
+{
+ int i;
+
+ for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
+{
+ ira_hard_regno_nrefs[i] = 0;
+ for (df_ref use = DF_REG_USE_CHAIN (i);
+ use != NULL;
+ use = DF_REF_NEXT_REG (use))
+ if (DF_REF_CLASS (use) != DF_REF_ARTIFICIAL
+ && !(DF_REF_INSN_INFO (use) && DEBUG_INSN_P (DF_REF_INSN (use
+ ira_hard_regno_nrefs[i]++;
+ for (df_ref def = DF_REG_DEF_CHAIN (i);
+ def != NULL;
+ def = DF_REF_NEXT_REG (def))
+
[gcc r13-9345] c++: ICE with nested anonymous union [PR117153]
https://gcc.gnu.org/g:988c0b796721d6e8be6a54abb48b695dae972dcf
commit r13-9345-g988c0b796721d6e8be6a54abb48b695dae972dcf
Author: Marek Polacek
Date: Mon Nov 25 09:45:13 2024 -0500
c++: ICE with nested anonymous union [PR117153]
In a template, for
union {
union {
T d;
};
};
build_anon_union_vars crates a malformed COMPONENT_REF: we have no
DECL_NAME for the nested anon union so we create something like "object.".
Most of the front end doesn't seem to care, but if such a tree gets to
potential_constant_expression, it can cause a crash.
We can use FIELD directly for the COMPONENT_REF's member. tsubst_stmt
should build up a proper one in:
if (VAR_P (decl) && !DECL_NAME (decl)
&& ANON_AGGR_TYPE_P (TREE_TYPE (decl)))
/* Anonymous aggregates are a special case. */
finish_anon_union (decl);
PR c++/117153
gcc/cp/ChangeLog:
* decl2.cc (build_anon_union_vars): Use FIELD for the second operand
of a COMPONENT_REF.
gcc/testsuite/ChangeLog:
* g++.dg/other/anon-union6.C: New test.
* g++.dg/other/anon-union7.C: New test.
Reviewed-by: Jason Merrill
(cherry picked from commit 10850f92b2a618ef1b1ad399530943ef4847823d)
Diff:
---
gcc/cp/decl2.cc | 2 +-
gcc/testsuite/g++.dg/other/anon-union6.C | 13 +
gcc/testsuite/g++.dg/other/anon-union7.C | 16
3 files changed, 30 insertions(+), 1 deletion(-)
diff --git a/gcc/cp/decl2.cc b/gcc/cp/decl2.cc
index 36e1f2ce3003..0ab7e502dc86 100644
--- a/gcc/cp/decl2.cc
+++ b/gcc/cp/decl2.cc
@@ -1854,7 +1854,7 @@ build_anon_union_vars (tree type, tree object)
if (processing_template_decl)
ref = build_min_nt_loc (UNKNOWN_LOCATION, COMPONENT_REF, object,
- DECL_NAME (field), NULL_TREE);
+ field, NULL_TREE);
else
ref = build_class_member_access_expr (object, field, NULL_TREE,
false, tf_warning_or_error);
diff --git a/gcc/testsuite/g++.dg/other/anon-union6.C
b/gcc/testsuite/g++.dg/other/anon-union6.C
new file mode 100644
index ..d1cde30f790d
--- /dev/null
+++ b/gcc/testsuite/g++.dg/other/anon-union6.C
@@ -0,0 +1,13 @@
+// PR c++/117153
+// { dg-do compile }
+
+template
+void f() {
+ union {
+union {
+ T d;
+};
+ };
+ (void) (d + 0);
+}
+template void f();
diff --git a/gcc/testsuite/g++.dg/other/anon-union7.C
b/gcc/testsuite/g++.dg/other/anon-union7.C
new file mode 100644
index ..e89334a5d0e7
--- /dev/null
+++ b/gcc/testsuite/g++.dg/other/anon-union7.C
@@ -0,0 +1,16 @@
+// PR c++/117153
+// { dg-do compile { target c++11 } }
+
+using U = union { union { int a; }; };
+
+U
+foo ()
+{
+ return {};
+}
+
+void
+g ()
+{
+ [[maybe_unused]] auto u = foo ();
+}
[gcc(refs/users/mikael/heads/refactor_descriptor_v01)] Correction régression bind-c-contiguous-1.f90
https://gcc.gnu.org/g:51323eb87cde1f6652a42d5db0f2e848d56094e9
commit 51323eb87cde1f6652a42d5db0f2e848d56094e9
Author: Mikael Morin
Date: Fri Jan 24 21:15:38 2025 +0100
Correction régression bind-c-contiguous-1.f90
Diff:
---
gcc/fortran/trans-decl.cc | 25 +
1 file changed, 13 insertions(+), 12 deletions(-)
diff --git a/gcc/fortran/trans-decl.cc b/gcc/fortran/trans-decl.cc
index 1a9eb3f00d17..baa36e88bf15 100644
--- a/gcc/fortran/trans-decl.cc
+++ b/gcc/fortran/trans-decl.cc
@@ -7212,16 +7212,6 @@ gfc_conv_cfi_to_gfc (stmtblock_t *init, stmtblock_t
*finally,
else
rank = build_int_cst (signed_char_type_node, sym->as->rank);
- if (!GFC_DESCRIPTOR_TYPE_P (TREE_TYPE (gfc_desc)))
-{
- tree offset, type;
- type = TREE_TYPE (gfc_desc);
- gfc_trans_array_bounds (type, sym, &offset, &block);
- if (VAR_P (GFC_TYPE_ARRAY_OFFSET (type)))
- gfc_add_modify (&block, GFC_TYPE_ARRAY_OFFSET (type), offset);
- goto done;
-}
-
stmtblock_t block2;
gfc_init_block (&block2);
@@ -7230,8 +7220,9 @@ gfc_conv_cfi_to_gfc (stmtblock_t *init, stmtblock_t
*finally,
&& (sym->as->type == AS_ASSUMED_SIZE || sym->as->type == AS_EXPLICIT))
|| sym->attr.contiguous;
- gfc_set_gfc_from_cfi (&block, &block2, gfc_desc, cfi, rank, sym,
- true, do_copy_inout, false);
+ if (GFC_DESCRIPTOR_TYPE_P (TREE_TYPE (gfc_desc)))
+gfc_set_gfc_from_cfi (&block, &block2, gfc_desc, cfi, rank, sym,
+ true, do_copy_inout, false);
/* With bind(C), the standard requires that both Fortran callers and callees
handle noncontiguous arrays passed to an dummy with 'contiguous' attribute
@@ -7389,6 +7380,16 @@ gfc_conv_cfi_to_gfc (stmtblock_t *init, stmtblock_t
*finally,
gfc_add_expr_to_block (&block, tmp);
}
+ if (!GFC_DESCRIPTOR_TYPE_P (TREE_TYPE (gfc_desc)))
+{
+ tree offset, type;
+ type = TREE_TYPE (gfc_desc);
+ gfc_trans_array_bounds (type, sym, &offset, &block);
+ if (VAR_P (GFC_TYPE_ARRAY_OFFSET (type)))
+ gfc_add_modify (&block, GFC_TYPE_ARRAY_OFFSET (type), offset);
+ goto done;
+}
+
if (sym->attr.allocatable || sym->attr.pointer)
{
tmp = gfc_get_cfi_desc_base_addr (cfi),
[gcc(refs/users/meissner/heads/work191-bugs)] Fix PR 118541, do not generate unordered fp cmoves.
https://gcc.gnu.org/g:4f8b53dbb6a7a68b54732bf922bd49dc552ee43a
commit 4f8b53dbb6a7a68b54732bf922bd49dc552ee43a
Author: Michael Meissner
Date: Fri Jan 24 16:53:23 2025 -0500
Fix PR 118541, do not generate unordered fp cmoves.
2025-01-24 Michael Meissner
gcc/
PR target/118541
* config/rs6000/rs6000-protos.h (REVERSE_COND_ORDERED_OK): New
macro.
(REVERSE_COND_NO_ORDERED): Likewise.
(rs6000_reverse_condition): Add argument.
* config/rs6000/rs6000.cc (rs6000_reverse_condition): Do not allow
ordered comparisons to be reversed for floating point cmoves.
(rs6000_emit_sCOND): Adjust rs6000_reverse_condition call.
* config/rs6000/rs6000.h (REVERSE_CONDITION): Likewise.
* config/rs6000/rs6000.md (reverse_branch_comparison): Name insn.
Adjust rs6000_reverse_condition call.
gcc/testsuite/
PR target/118541
* gcc.target/powerpc/pr118541.c: New test.
Diff:
---
gcc/config/rs6000/rs6000-protos.h | 6 +++-
gcc/config/rs6000/rs6000.cc | 23 +++
gcc/config/rs6000/rs6000.h | 10 +--
gcc/config/rs6000/rs6000.md | 24 ++--
gcc/testsuite/gcc.target/powerpc/pr118541.c | 43 +
5 files changed, 89 insertions(+), 17 deletions(-)
diff --git a/gcc/config/rs6000/rs6000-protos.h
b/gcc/config/rs6000/rs6000-protos.h
index 4619142d197b..112332660d3b 100644
--- a/gcc/config/rs6000/rs6000-protos.h
+++ b/gcc/config/rs6000/rs6000-protos.h
@@ -114,8 +114,12 @@ extern const char *rs6000_sibcall_template (rtx *,
unsigned int);
extern const char *rs6000_indirect_call_template (rtx *, unsigned int);
extern const char *rs6000_indirect_sibcall_template (rtx *, unsigned int);
extern const char *rs6000_pltseq_template (rtx *, int);
+
+#define REVERSE_COND_ORDERED_OKfalse
+#define REVERSE_COND_NO_ORDEREDtrue
+
extern enum rtx_code rs6000_reverse_condition (machine_mode,
- enum rtx_code);
+ enum rtx_code, bool);
extern rtx rs6000_emit_eqne (machine_mode, rtx, rtx, rtx);
extern rtx rs6000_emit_fp_cror (rtx_code, machine_mode, rtx);
extern void rs6000_emit_sCOND (machine_mode, rtx[]);
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index f9f9a0b931db..eaf79435ec32 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -15360,15 +15360,25 @@ rs6000_print_patchable_function_entry (FILE *file,
}
enum rtx_code
-rs6000_reverse_condition (machine_mode mode, enum rtx_code code)
+rs6000_reverse_condition (machine_mode mode,
+ enum rtx_code code,
+ bool no_ordered)
{
/* Reversal of FP compares takes care -- an ordered compare
- becomes an unordered compare and vice versa. */
+ becomes an unordered compare and vice versa.
+
+ However, this is not safe for ordered comparisons (i.e. for isgreater,
+ etc.) starting with the power9 because ifcvt.cc will want to create a fp
+ cmove, and the x{s,v}cmp{eq,gt,ge}{dp,qp} instructions will trap if one of
+ the arguments is a signalling NaN. */
+
if (mode == CCFPmode
&& (!flag_finite_math_only
|| code == UNLT || code == UNLE || code == UNGT || code == UNGE
|| code == UNEQ || code == LTGT))
-return reverse_condition_maybe_unordered (code);
+return (no_ordered
+ ? UNKNOWN
+ : reverse_condition_maybe_unordered (code));
else
return reverse_condition (code);
}
@@ -15980,11 +15990,14 @@ rs6000_emit_sCOND (machine_mode mode, rtx operands[])
rtx not_result = gen_reg_rtx (CCEQmode);
rtx not_op, rev_cond_rtx;
machine_mode cc_mode;
+ enum rtx_code rev;
cc_mode = GET_MODE (XEXP (condition_rtx, 0));
- rev_cond_rtx = gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode,
cond_code),
-SImode, XEXP (condition_rtx, 0),
const0_rtx);
+ rev = rs6000_reverse_condition (cc_mode, cond_code,
+ REVERSE_COND_ORDERED_OK);
+ rev_cond_rtx = gen_rtx_fmt_ee (rev, SImode, XEXP (condition_rtx, 0),
+const0_rtx);
not_op = gen_rtx_COMPARE (CCEQmode, rev_cond_rtx, const0_rtx);
emit_insn (gen_rtx_SET (not_result, not_op));
condition_rtx = gen_rtx_EQ (VOIDmode, not_result, const0_rtx);
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index ec08c96d0f67..c595d7138bcd 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -1812,11 +1812,17 @@ extern scalar_int_mode rs6000_pmode;
/* Can the condition code MODE be safely reversed? This is safe in
all cases on this port, because at present it doesn't use the
- trapping FP comparisons
[gcc r13-9344] rs6000: Fix ICE for invalid constants in built-in functions
https://gcc.gnu.org/g:2c42f598b4365fac40bbc32a795e42b87962c874
commit r13-9344-g2c42f598b4365fac40bbc32a795e42b87962c874
Author: Peter Bergner
Date: Thu Jan 16 10:53:27 2025 -0600
rs6000: Fix ICE for invalid constants in built-in functions
For invalid constant operand values used in built-in functions, return
const0_rtx to signify an error occurred during expansion.
2025-01-16 Peter Bergner
gcc/
* config/rs6000/rs6000-builtin.cc (rs6000_expand_builtin): Return
const0_rtx when there is an error.
gcc/testsuite/
* gcc.target/powerpc/mma-builtin-error.c: New test.
(cherry picked from commit 0696af74b3392e2178215607337b116d1bb53e34)
Diff:
---
gcc/config/rs6000/rs6000-builtin.cc | 8
gcc/testsuite/gcc.target/powerpc/mma-builtin-error.c | 11 +++
2 files changed, 15 insertions(+), 4 deletions(-)
diff --git a/gcc/config/rs6000/rs6000-builtin.cc
b/gcc/config/rs6000/rs6000-builtin.cc
index 3ed3930067dc..12bd3cec0d5c 100644
--- a/gcc/config/rs6000/rs6000-builtin.cc
+++ b/gcc/config/rs6000/rs6000-builtin.cc
@@ -3552,7 +3552,7 @@ rs6000_expand_builtin (tree exp, rtx target, rtx /*
subtarget */,
error ("argument %d must be a literal between 0 and %d,"
" inclusive",
bifaddr->restr_opnd[i], p);
- return CONST0_RTX (mode[0]);
+ return const0_rtx;
}
break;
}
@@ -3569,7 +3569,7 @@ rs6000_expand_builtin (tree exp, rtx target, rtx /*
subtarget */,
" inclusive",
bifaddr->restr_opnd[i], bifaddr->restr_val1[i],
bifaddr->restr_val2[i]);
- return CONST0_RTX (mode[0]);
+ return const0_rtx;
}
break;
}
@@ -3586,7 +3586,7 @@ rs6000_expand_builtin (tree exp, rtx target, rtx /*
subtarget */,
"between %d and %d, inclusive",
bifaddr->restr_opnd[i], bifaddr->restr_val1[i],
bifaddr->restr_val2[i]);
- return CONST0_RTX (mode[0]);
+ return const0_rtx;
}
break;
}
@@ -3602,7 +3602,7 @@ rs6000_expand_builtin (tree exp, rtx target, rtx /*
subtarget */,
"literal %d",
bifaddr->restr_opnd[i], bifaddr->restr_val1[i],
bifaddr->restr_val2[i]);
- return CONST0_RTX (mode[0]);
+ return const0_rtx;
}
break;
}
diff --git a/gcc/testsuite/gcc.target/powerpc/mma-builtin-error.c
b/gcc/testsuite/gcc.target/powerpc/mma-builtin-error.c
new file mode 100644
index ..a87a15709255
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/mma-builtin-error.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target power10_ok } */
+/* { dg-options "-O2 -mdejagnu-cpu=power10" } */
+
+typedef unsigned char vec_t __attribute__((vector_size(16)));
+
+void
+foo (__vector_quad *dst, vec_t vec0, vec_t vec1) /* { dg-error "argument 5
must be a literal between 0 and 15, inclusive" } */
+{
+ __builtin_mma_pmxvi8ger4 (dst, vec0, vec1, 15, 15, -1);
+}
[gcc r13-9343] rs6000: Fix loop limit for built-in constant checking
https://gcc.gnu.org/g:a54c3a72defe4bd7c33f20fc3d51496e160a8aa7
commit r13-9343-ga54c3a72defe4bd7c33f20fc3d51496e160a8aa7
Author: Peter Bergner
Date: Thu Jan 16 10:49:45 2025 -0600
rs6000: Fix loop limit for built-in constant checking
The loop checking for built-in constant operand restrictions was missing
some operands due to the loop limit being too small. Fixing that exposed
a testsuite failure which is caused by a typo in the pmxvi4ger8pp definition
where we had made the PMASK field too small.
2025-01-16 Peter Bergner
gcc/
* config/rs6000/rs6000-builtin.cc (rs6000_expand_builtin): Use
correct
array size for the loop limit.
* config/rs6000/rs6000-builtins.def: Fix field size for PMASK
operand.
(cherry picked from commit 1a2d63a78f99b7fdc2eff5bf9065682d5bbbaaca)
Diff:
---
gcc/config/rs6000/rs6000-builtin.cc | 2 +-
gcc/config/rs6000/rs6000-builtins.def | 4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/gcc/config/rs6000/rs6000-builtin.cc
b/gcc/config/rs6000/rs6000-builtin.cc
index 0cb6e742c6b2..3ed3930067dc 100644
--- a/gcc/config/rs6000/rs6000-builtin.cc
+++ b/gcc/config/rs6000/rs6000-builtin.cc
@@ -3534,7 +3534,7 @@ rs6000_expand_builtin (tree exp, rtx target, rtx /*
subtarget */,
}
/* Check for restricted constant arguments. */
- for (int i = 0; i < 2; i++)
+ for (size_t i = 0; i < ARRAY_SIZE (bifaddr->restr); i++)
{
switch (bifaddr->restr[i])
{
diff --git a/gcc/config/rs6000/rs6000-builtins.def
b/gcc/config/rs6000/rs6000-builtins.def
index f3dcb739245b..8f1a9efbc3d0 100644
--- a/gcc/config/rs6000/rs6000-builtins.def
+++ b/gcc/config/rs6000/rs6000-builtins.def
@@ -3862,11 +3862,11 @@
PMXVI4GER8_INTERNAL mma_pmxvi4ger8 {mma}
void __builtin_mma_pmxvi4ger8pp (v512 *, vuc, vuc, const int<4>, \
- const int<4>, const int<4>);
+ const int<4>, const int<8>);
PMXVI4GER8PP nothing {mma,quad,mmaint}
v512 __builtin_mma_pmxvi4ger8pp_internal (v512, vuc, vuc, const int<4>, \
-const int<4>, const int<4>);
+const int<4>, const int<8>);
PMXVI4GER8PP_INTERNAL mma_pmxvi4ger8pp {mma,quad}
void __builtin_mma_pmxvi8ger4 (v512 *, vuc, vuc, const int<4>, \
[gcc r15-7178] sarif-replay: respect prefix and suffix during installation [PR117670]
https://gcc.gnu.org/g:d49667be2c2953c33086a02cac8729a550990c8c commit r15-7178-gd49667be2c2953c33086a02cac8729a550990c8c Author: David Malcolm Date: Fri Jan 24 10:20:11 2025 -0500 sarif-replay: respect prefix and suffix during installation [PR117670] gcc/ChangeLog: PR sarif-replay/117670 * Makefile.in (SARIF_REPLAY_INSTALL_NAME): New. (install-libgdiagnostics): Use it,and exeext, rather than just sarif-replay. Signed-off-by: David Malcolm Diff: --- gcc/Makefile.in | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/gcc/Makefile.in b/gcc/Makefile.in index 51c25b06e081..a8e32e25cf54 100644 --- a/gcc/Makefile.in +++ b/gcc/Makefile.in @@ -4215,9 +4215,10 @@ libgdiagnostics.install-common: installdirs libgdiagnostics.install-headers endif endif +SARIF_REPLAY_INSTALL_NAME := $(shell echo sarif-replay|sed '$(program_transform_name)') install-libgdiagnostics: libgdiagnostics.install-common sarif-replay - -rm -f $(DESTDIR)$(bindir)/sarif-replay - -$(INSTALL_PROGRAM) sarif-replay $(DESTDIR)$(bindir)/sarif-replay + -rm -f $(DESTDIR)$(bindir)/$(SARIF_REPLAY_INSTALL_NAME)$(exeext) + -$(INSTALL_PROGRAM) sarif-replay $(DESTDIR)$(bindir)/$(SARIF_REPLAY_INSTALL_NAME)$(exeext) # Install the info files. # $(INSTALL_DATA) might be a relative pathname, so we can't cd into srcdir
[gcc r15-7179] jit: fix for write_reproducer [PR117886]
https://gcc.gnu.org/g:4d18acf8023ba0495007aa7a6f36d5509a51760b
commit r15-7179-g4d18acf8023ba0495007aa7a6f36d5509a51760b
Author: David Malcolm
Date: Fri Jan 24 10:20:16 2025 -0500
jit: fix for write_reproducer [PR117886]
The original generated .c reproducer for PR jit/117886 did not compile,
with:
main.c: In function ‘create_code’:
main.c:600:9: error: initialization of ‘gcc_jit_rvalue *’ from incompatible
pointer type ‘gcc_jit_lvalue *’ [-Wincompatible-pointer-types]
600 | local__1,
| ^~~~
The issue is that recording::ctor::write_reproducer was missing
creation of casts to gcc_jit_rvalue * for
gcc_jit_context_new_array_constructor and
gcc_jit_context_new_struct_constructor.
Fixed thusly.
gcc/jit/ChangeLog:
PR jit/117886
* jit-recording.cc (reproducer::get_identifier_as_rvalue): Handle
null memento.
(reproducer::get_identifier_as_lvalue): Likewise.
(reproducer::get_identifier_as_type): Likewise.
(recording::ctor::write_reproducer): Use get_identifier_as_rvalue
rather than get_identifier when writing out gcc_jit_rvalue *
expressions.
gcc/testsuite/ChangeLog:
PR jit/117886
* jit.dg/all-non-failing-tests.h: Add
test-pr117886-write-reproducer.c.
* jit.dg/test-pr117886-write-reproducer.c: New test.
Signed-off-by: David Malcolm
Diff:
---
gcc/jit/jit-recording.cc | 10 +-
gcc/testsuite/jit.dg/all-non-failing-tests.h | 10 ++
.../jit.dg/test-pr117886-write-reproducer.c| 103 +
3 files changed, 121 insertions(+), 2 deletions(-)
diff --git a/gcc/jit/jit-recording.cc b/gcc/jit/jit-recording.cc
index e6fef5bca076..8da3cb059156 100644
--- a/gcc/jit/jit-recording.cc
+++ b/gcc/jit/jit-recording.cc
@@ -406,6 +406,8 @@ reproducer::get_identifier (recording::memento *m)
const char *
reproducer::get_identifier_as_rvalue (recording::rvalue *m)
{
+ if (!m)
+return "NULL";
return m->access_as_rvalue (*this);
}
@@ -415,6 +417,8 @@ reproducer::get_identifier_as_rvalue (recording::rvalue *m)
const char *
reproducer::get_identifier_as_lvalue (recording::lvalue *m)
{
+ if (!m)
+return "NULL";
return m->access_as_lvalue (*this);
}
@@ -424,6 +428,8 @@ reproducer::get_identifier_as_lvalue (recording::lvalue *m)
const char *
reproducer::get_identifier_as_type (recording::type *m)
{
+ if (!m)
+return "NULL";
return m->access_as_type (*this);
}
@@ -6041,7 +6047,7 @@ recording::ctor::write_reproducer (reproducer &r)
r.write ("gcc_jit_rvalue *value = NULL;\n");
else
r.write ("gcc_jit_rvalue *value = %s;\n",
-r.get_identifier (m_values[0]));
+r.get_identifier_as_rvalue (m_values[0]));
if (m_fields.length () == 0)
r.write ("gcc_jit_field *field = NULL;\n");
@@ -6058,7 +6064,7 @@ recording::ctor::write_reproducer (reproducer &r)
{
r.write ("gcc_jit_rvalue *values[] = {\n");
for (size_t i = 0; i < m_values.length (); i++)
- r.write ("%s,\n", r.get_identifier (m_values[i]));
+ r.write ("%s,\n", r.get_identifier_as_rvalue (m_values[i]));
r.write (" };\n");
}
/* Write the array of fields. */
diff --git a/gcc/testsuite/jit.dg/all-non-failing-tests.h
b/gcc/testsuite/jit.dg/all-non-failing-tests.h
index b566925fd3dd..add5619aebd4 100644
--- a/gcc/testsuite/jit.dg/all-non-failing-tests.h
+++ b/gcc/testsuite/jit.dg/all-non-failing-tests.h
@@ -344,6 +344,13 @@
#undef create_code
#undef verify_code
+/* test-pr117886-write-reproducer.c. */
+#define create_code create_code_pr117886_write_reproducer
+#define verify_code verify_code_pr117886_write_reproducer
+#include "test-pr117886-write-reproducer.c"
+#undef create_code
+#undef verify_code
+
/* test-pure-attribute.c: This can't be in the testcases array as it needs
the `-O3` flag. */
@@ -603,6 +610,9 @@ const struct testcase testcases[] = {
{"pr95314_rvalue_reuse",
create_code_pr95314_rvalue_reuse,
verify_code_pr95314_rvalue_reuse},
+ {"pr117886_write_reproducer",
+ create_code_pr117886_write_reproducer,
+ verify_code_pr117886_write_reproducer},
{"reading_struct ",
create_code_reading_struct ,
verify_code_reading_struct },
diff --git a/gcc/testsuite/jit.dg/test-pr117886-write-reproducer.c
b/gcc/testsuite/jit.dg/test-pr117886-write-reproducer.c
new file mode 100644
index ..5018b0ea3eda
--- /dev/null
+++ b/gcc/testsuite/jit.dg/test-pr117886-write-reproducer.c
@@ -0,0 +1,103 @@
+/* Verify that we can generate and compile reproducers for
+ gcc_jit_context_new_array_constructor
+ when the values are lvalues */
+
+#include
+#include
+
+#include "libgccjit.h"
+#include "harness.h"
+
+/*
+ int foo[3
[gcc(refs/users/meissner/heads/work191-bugs)] Revert changes
https://gcc.gnu.org/g:f4694d012577b7a90e054c311eeffe7bf55d39d0
commit f4694d012577b7a90e054c311eeffe7bf55d39d0
Author: Michael Meissner
Date: Fri Jan 24 10:18:45 2025 -0500
Revert changes
Diff:
---
gcc/config/rs6000/rs6000.cc | 54 +
1 file changed, 5 insertions(+), 49 deletions(-)
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 6c218ac7d6f6..f9f9a0b931db 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -15362,20 +15362,13 @@ rs6000_print_patchable_function_entry (FILE *file,
enum rtx_code
rs6000_reverse_condition (machine_mode mode, enum rtx_code code)
{
- /* Reversal of FP compares takes care -- Do not allow an ordered compare to
- become an unordered compare if signaling NaNs are possible, since the
- unordered compare may trap. This happens on power9 when ?: is converted
- into a cmove. The xscmp{eq,gt,ge}{dp,qp} instructions will trap on a
- signalling NaN. */
+ /* Reversal of FP compares takes care -- an ordered compare
+ becomes an unordered compare and vice versa. */
if (mode == CCFPmode
- && (code == UNLT || code == UNLE || code == UNGT || code == UNGE
+ && (!flag_finite_math_only
+ || code == UNLT || code == UNLE || code == UNGT || code == UNGE
|| code == UNEQ || code == LTGT))
-{
- if (!flag_finite_math_only || flag_signaling_nans)
- return UNKNOWN;
-
- return reverse_condition_maybe_unordered (code);
-}
+return reverse_condition_maybe_unordered (code);
else
return reverse_condition (code);
}
@@ -16446,24 +16439,6 @@ rs6000_maybe_emit_fp_cmove (rtx dest, rtx op, rtx
true_cond, rtx false_cond)
if (!can_create_pseudo_p ())
return 0;
- /* Don't optimize comparisons with explicit unordered support (like
- isgreater), since the fpmask VSX instructions can generate an error with a
- signaling NaN. */
- if (!flag_finite_math_only || flag_signaling_nans)
-switch (code)
- {
- case LTGT:
- case UNGE:
- case UNGT:
- case UNEQ:
- case UNLE:
- case UNLT:
- return false;
-
- default:
- break;
- }
-
/* We allow the comparison to be either SFmode/DFmode and the true/false
condition to be either SFmode/DFmode. I.e. we allow:
@@ -16576,25 +16551,6 @@ rs6000_emit_cmove (rtx dest, rtx op, rtx true_cond,
rtx false_cond)
if (GET_MODE (false_cond) != result_mode)
return false;
- /* Don't allow optimizing comparisons with explicit unordered support (like
- isgreater), since the fpmask VSX instructions can generate an error with a
- signaling NaN. */
- if (FLOAT_MODE_P (compare_mode)
- && (!flag_finite_math_only || flag_signaling_nans))
-switch (code)
- {
- case LTGT:
- case UNGE:
- case UNGT:
- case UNEQ:
- case UNLE:
- case UNLT:
- return false;
-
- default:
- break;
- }
-
/* See if we can use the "C" minimum, "C" maximum, and compare and set mask
instructions. */
if (have_compare_and_set_mask (compare_mode)
[gcc r12-10929] rs6000: Fix loop limit for built-in constant checking
https://gcc.gnu.org/g:4e508cbb938a8936bc6aefd7823b55107aa4a7f9
commit r12-10929-g4e508cbb938a8936bc6aefd7823b55107aa4a7f9
Author: Peter Bergner
Date: Thu Jan 16 10:49:45 2025 -0600
rs6000: Fix loop limit for built-in constant checking
The loop checking for built-in constant operand restrictions was missing
some operands due to the loop limit being too small. Fixing that exposed
a testsuite failure which is caused by a typo in the pmxvi4ger8pp definition
where we had made the PMASK field too small.
2025-01-16 Peter Bergner
gcc/
* config/rs6000/rs6000-builtin.cc (rs6000_expand_builtin): Use
correct
array size for the loop limit.
* config/rs6000/rs6000-builtins.def: Fix field size for PMASK
operand.
(cherry picked from commit 1a2d63a78f99b7fdc2eff5bf9065682d5bbbaaca)
Diff:
---
gcc/config/rs6000/rs6000-builtin.cc | 2 +-
gcc/config/rs6000/rs6000-builtins.def | 4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/gcc/config/rs6000/rs6000-builtin.cc
b/gcc/config/rs6000/rs6000-builtin.cc
index f01f3aded362..d467db29e8e3 100644
--- a/gcc/config/rs6000/rs6000-builtin.cc
+++ b/gcc/config/rs6000/rs6000-builtin.cc
@@ -3584,7 +3584,7 @@ rs6000_expand_builtin (tree exp, rtx target, rtx /*
subtarget */,
}
/* Check for restricted constant arguments. */
- for (int i = 0; i < 2; i++)
+ for (size_t i = 0; i < ARRAY_SIZE (bifaddr->restr); i++)
{
switch (bifaddr->restr[i])
{
diff --git a/gcc/config/rs6000/rs6000-builtins.def
b/gcc/config/rs6000/rs6000-builtins.def
index d2c0565dc623..eca7ad2f5fae 100644
--- a/gcc/config/rs6000/rs6000-builtins.def
+++ b/gcc/config/rs6000/rs6000-builtins.def
@@ -3861,11 +3861,11 @@
PMXVI4GER8_INTERNAL mma_pmxvi4ger8 {mma}
void __builtin_mma_pmxvi4ger8pp (v512 *, vuc, vuc, const int<4>, \
- const int<4>, const int<4>);
+ const int<4>, const int<8>);
PMXVI4GER8PP nothing {mma,quad,mmaint}
v512 __builtin_mma_pmxvi4ger8pp_internal (v512, vuc, vuc, const int<4>, \
-const int<4>, const int<4>);
+const int<4>, const int<8>);
PMXVI4GER8PP_INTERNAL mma_pmxvi4ger8pp {mma,quad}
void __builtin_mma_pmxvi8ger4 (v512 *, vuc, vuc, const int<4>, \
[gcc r12-10930] rs6000: Fix ICE for invalid constants in built-in functions
https://gcc.gnu.org/g:4dbace39f1149984e6b85574d4665ce18240db8e
commit r12-10930-g4dbace39f1149984e6b85574d4665ce18240db8e
Author: Peter Bergner
Date: Thu Jan 16 10:53:27 2025 -0600
rs6000: Fix ICE for invalid constants in built-in functions
For invalid constant operand values used in built-in functions, return
const0_rtx to signify an error occurred during expansion.
2025-01-16 Peter Bergner
gcc/
* config/rs6000/rs6000-builtin.cc (rs6000_expand_builtin): Return
const0_rtx when there is an error.
gcc/testsuite/
* gcc.target/powerpc/mma-builtin-error.c: New test.
(cherry picked from commit 0696af74b3392e2178215607337b116d1bb53e34)
Diff:
---
gcc/config/rs6000/rs6000-builtin.cc | 8
gcc/testsuite/gcc.target/powerpc/mma-builtin-error.c | 11 +++
2 files changed, 15 insertions(+), 4 deletions(-)
diff --git a/gcc/config/rs6000/rs6000-builtin.cc
b/gcc/config/rs6000/rs6000-builtin.cc
index d467db29e8e3..a1549fe2a15f 100644
--- a/gcc/config/rs6000/rs6000-builtin.cc
+++ b/gcc/config/rs6000/rs6000-builtin.cc
@@ -3602,7 +3602,7 @@ rs6000_expand_builtin (tree exp, rtx target, rtx /*
subtarget */,
error ("argument %d must be a literal between 0 and %d,"
" inclusive",
bifaddr->restr_opnd[i], p);
- return CONST0_RTX (mode[0]);
+ return const0_rtx;
}
break;
}
@@ -3619,7 +3619,7 @@ rs6000_expand_builtin (tree exp, rtx target, rtx /*
subtarget */,
" inclusive",
bifaddr->restr_opnd[i], bifaddr->restr_val1[i],
bifaddr->restr_val2[i]);
- return CONST0_RTX (mode[0]);
+ return const0_rtx;
}
break;
}
@@ -3636,7 +3636,7 @@ rs6000_expand_builtin (tree exp, rtx target, rtx /*
subtarget */,
"between %d and %d, inclusive",
bifaddr->restr_opnd[i], bifaddr->restr_val1[i],
bifaddr->restr_val2[i]);
- return CONST0_RTX (mode[0]);
+ return const0_rtx;
}
break;
}
@@ -3652,7 +3652,7 @@ rs6000_expand_builtin (tree exp, rtx target, rtx /*
subtarget */,
"literal %d",
bifaddr->restr_opnd[i], bifaddr->restr_val1[i],
bifaddr->restr_val2[i]);
- return CONST0_RTX (mode[0]);
+ return const0_rtx;
}
break;
}
diff --git a/gcc/testsuite/gcc.target/powerpc/mma-builtin-error.c
b/gcc/testsuite/gcc.target/powerpc/mma-builtin-error.c
new file mode 100644
index ..a87a15709255
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/mma-builtin-error.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target power10_ok } */
+/* { dg-options "-O2 -mdejagnu-cpu=power10" } */
+
+typedef unsigned char vec_t __attribute__((vector_size(16)));
+
+void
+foo (__vector_quad *dst, vec_t vec0, vec_t vec1) /* { dg-error "argument 5
must be a literal between 0 and 15, inclusive" } */
+{
+ __builtin_mma_pmxvi8ger4 (dst, vec0, vec1, 15, 15, -1);
+}
[gcc(refs/users/meissner/heads/work191-bugs)] Fix PR 118541, do not generate unordered fp cmoves.
https://gcc.gnu.org/g:bba9b39a793faf48f2e6cf04289b1e48190b127f
commit bba9b39a793faf48f2e6cf04289b1e48190b127f
Author: Michael Meissner
Date: Fri Jan 24 10:50:35 2025 -0500
Fix PR 118541, do not generate unordered fp cmoves.
2025-01-24 Michael Meissner
gcc/
PR target/118541
* config/rs6000/rs6000-protos.h (rs6000_reverse_condition): Add
argument.
* config/rs6000/rs6000.cc (rs6000_reverse_condition): Do not allow
ordered comparisons to be reversed for floating point cmoves.
(rs6000_emit_sCOND): Adjust rs6000_reverse_condition call.
* config/rs6000/rs6000.h (REVERSE_CONDITION): Likewise.
* config/rs6000/rs6000.md (reverse_branch_comparison): Likewise.
Diff:
---
gcc/config/rs6000/rs6000-protos.h | 2 +-
gcc/config/rs6000/rs6000.cc | 19 +++
gcc/config/rs6000/rs6000.h| 10 --
gcc/config/rs6000/rs6000.md | 24 +++-
4 files changed, 39 insertions(+), 16 deletions(-)
diff --git a/gcc/config/rs6000/rs6000-protos.h
b/gcc/config/rs6000/rs6000-protos.h
index 4619142d197b..8f790d261d9a 100644
--- a/gcc/config/rs6000/rs6000-protos.h
+++ b/gcc/config/rs6000/rs6000-protos.h
@@ -115,7 +115,7 @@ extern const char *rs6000_indirect_call_template (rtx *,
unsigned int);
extern const char *rs6000_indirect_sibcall_template (rtx *, unsigned int);
extern const char *rs6000_pltseq_template (rtx *, int);
extern enum rtx_code rs6000_reverse_condition (machine_mode,
- enum rtx_code);
+ enum rtx_code, bool);
extern rtx rs6000_emit_eqne (machine_mode, rtx, rtx, rtx);
extern rtx rs6000_emit_fp_cror (rtx_code, machine_mode, rtx);
extern void rs6000_emit_sCOND (machine_mode, rtx[]);
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index f9f9a0b931db..276e2f886acc 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -15360,15 +15360,25 @@ rs6000_print_patchable_function_entry (FILE *file,
}
enum rtx_code
-rs6000_reverse_condition (machine_mode mode, enum rtx_code code)
+rs6000_reverse_condition (machine_mode mode,
+ enum rtx_code code,
+ bool no_ordered)
{
/* Reversal of FP compares takes care -- an ordered compare
- becomes an unordered compare and vice versa. */
+ becomes an unordered compare and vice versa.
+
+ However, this is not safe for ordered comparisons (i.e. for isgreater,
+ etc.) starting with the power9 because ifcvt.cc will want to create a fp
+ cmove, and the x{s,v}cmp{eq,gt,ge}{dp,qp} instructions will trap if one of
+ the arguments is a signalling NaN. */
+
if (mode == CCFPmode
&& (!flag_finite_math_only
|| code == UNLT || code == UNLE || code == UNGT || code == UNGE
|| code == UNEQ || code == LTGT))
-return reverse_condition_maybe_unordered (code);
+return (no_ordered
+ ? UNKNOWN
+ : reverse_condition_maybe_unordered (code));
else
return reverse_condition (code);
}
@@ -15983,7 +15993,8 @@ rs6000_emit_sCOND (machine_mode mode, rtx operands[])
cc_mode = GET_MODE (XEXP (condition_rtx, 0));
- rev_cond_rtx = gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode,
cond_code),
+ rev_cond_rtx = gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode,
cond_code,
+ false),
SImode, XEXP (condition_rtx, 0),
const0_rtx);
not_op = gen_rtx_COMPARE (CCEQmode, rev_cond_rtx, const0_rtx);
emit_insn (gen_rtx_SET (not_result, not_op));
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index ec08c96d0f67..98228ee5ac16 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -1812,11 +1812,17 @@ extern scalar_int_mode rs6000_pmode;
/* Can the condition code MODE be safely reversed? This is safe in
all cases on this port, because at present it doesn't use the
- trapping FP comparisons (fcmpo). */
+ trapping FP comparisons (fcmpo).
+
+ However, this is not safe for ordered comparisons (i.e. for isgreater, etc.)
+ starting with the power9 because ifcvt.cc will want to create a fp cmove,
+ and the x{s,v}cmp{eq,gt,ge}{dp,qp} instructions will trap if one of the
+ arguments is a signalling NaN. */
#define REVERSIBLE_CC_MODE(MODE) 1
/* Given a condition code and a mode, return the inverse condition. */
-#define REVERSE_CONDITION(CODE, MODE) rs6000_reverse_condition (MODE, CODE)
+#define REVERSE_CONDITION(CODE, MODE) \
+ rs6000_reverse_condition (MODE, CODE, true)
/* Target cpu costs. */
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 65da0c653304..cf4b10257903 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -13497,
[gcc(refs/users/meissner/heads/work191-bugs)] Update ChangeLog.*
https://gcc.gnu.org/g:cb62e37aac41df498f0f5c8bcad1ebab83b252b5 commit cb62e37aac41df498f0f5c8bcad1ebab83b252b5 Author: Michael Meissner Date: Fri Jan 24 10:52:11 2025 -0500 Update ChangeLog.* Diff: --- gcc/ChangeLog.bugs | 14 +- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/gcc/ChangeLog.bugs b/gcc/ChangeLog.bugs index 965f65f0523c..bba5ce2deb76 100644 --- a/gcc/ChangeLog.bugs +++ b/gcc/ChangeLog.bugs @@ -2,16 +2,20 @@ Fix PR 118541, do not generate unordered fp cmoves. -2025-01-23 Michael Meissner +2025-01-24 Michael Meissner gcc/ PR target/118541 + * config/rs6000/rs6000-protos.h (rs6000_reverse_condition): Add + argument. * config/rs6000/rs6000.cc (rs6000_reverse_condition): Do not allow - unordered floating point comparisons to be reversed if signaling NaNs - are a possibility. - (rs6000_maybe_emit_fp_cmove): Likewise. - (rs6000_emit_cmove): Likewise. + ordered comparisons to be reversed for floating point cmoves. + (rs6000_emit_sCOND): Adjust rs6000_reverse_condition call. + * config/rs6000/rs6000.h (REVERSE_CONDITION): Likewise. + * config/rs6000/rs6000.md (reverse_branch_comparison): Likewise. + + Branch work191-bugs, patch #210 was reverted Branch work191-bugs, patch #202
[gcc(refs/users/mikael/heads/refactor_descriptor_v01)] Correction régression contiguous-2.f90
https://gcc.gnu.org/g:c4bc5df18e6102645241397089c090117c7180b4
commit c4bc5df18e6102645241397089c090117c7180b4
Author: Mikael Morin
Date: Fri Jan 24 16:42:00 2025 +0100
Correction régression contiguous-2.f90
Diff:
---
gcc/fortran/trans-decl.cc | 32
1 file changed, 16 insertions(+), 16 deletions(-)
diff --git a/gcc/fortran/trans-decl.cc b/gcc/fortran/trans-decl.cc
index 96a8e8ca10fd..19348c167388 100644
--- a/gcc/fortran/trans-decl.cc
+++ b/gcc/fortran/trans-decl.cc
@@ -7212,6 +7212,22 @@ gfc_conv_cfi_to_gfc (stmtblock_t *init, stmtblock_t
*finally,
else
rank = build_int_cst (signed_char_type_node, sym->as->rank);
+ if (!GFC_DESCRIPTOR_TYPE_P (TREE_TYPE (gfc_desc)))
+{
+ tree offset, type;
+ type = TREE_TYPE (gfc_desc);
+ gfc_trans_array_bounds (type, sym, &offset, &block);
+ if (VAR_P (GFC_TYPE_ARRAY_OFFSET (type)))
+ gfc_add_modify (&block, GFC_TYPE_ARRAY_OFFSET (type), offset);
+ goto done;
+}
+
+ stmtblock_t block2;
+ gfc_init_block (&block2);
+
+ gfc_set_gfc_from_cfi (&block, &block2, gfc_desc, cfi, rank, sym,
+ true, do_copy_inout, false);
+
/* With bind(C), the standard requires that both Fortran callers and callees
handle noncontiguous arrays passed to an dummy with 'contiguous' attribute
and with character(len=*) + assumed-size/explicit-size arrays.
@@ -7371,22 +7387,6 @@ gfc_conv_cfi_to_gfc (stmtblock_t *init, stmtblock_t
*finally,
gfc_add_expr_to_block (&block, tmp);
}
- if (!GFC_DESCRIPTOR_TYPE_P (TREE_TYPE (gfc_desc)))
-{
- tree offset, type;
- type = TREE_TYPE (gfc_desc);
- gfc_trans_array_bounds (type, sym, &offset, &block);
- if (VAR_P (GFC_TYPE_ARRAY_OFFSET (type)))
- gfc_add_modify (&block, GFC_TYPE_ARRAY_OFFSET (type), offset);
- goto done;
-}
-
- stmtblock_t block2;
- gfc_init_block (&block2);
-
- gfc_set_gfc_from_cfi (&block, &block2, gfc_desc, cfi, rank, sym,
- true, do_copy_inout, false);
-
if (sym->attr.allocatable || sym->attr.pointer)
{
tmp = gfc_get_cfi_desc_base_addr (cfi),
[gcc(refs/users/meissner/heads/work191-bugs)] Revert changes
https://gcc.gnu.org/g:65c8727f5e0f938b50998c28565d1bba0c7394ba
commit 65c8727f5e0f938b50998c28565d1bba0c7394ba
Author: Michael Meissner
Date: Fri Jan 24 11:44:01 2025 -0500
Revert changes
Diff:
---
gcc/config/rs6000/rs6000-protos.h | 2 +-
gcc/config/rs6000/rs6000.cc | 19 ---
gcc/config/rs6000/rs6000.h| 10 ++
gcc/config/rs6000/rs6000.md | 24 +---
4 files changed, 16 insertions(+), 39 deletions(-)
diff --git a/gcc/config/rs6000/rs6000-protos.h
b/gcc/config/rs6000/rs6000-protos.h
index 8f790d261d9a..4619142d197b 100644
--- a/gcc/config/rs6000/rs6000-protos.h
+++ b/gcc/config/rs6000/rs6000-protos.h
@@ -115,7 +115,7 @@ extern const char *rs6000_indirect_call_template (rtx *,
unsigned int);
extern const char *rs6000_indirect_sibcall_template (rtx *, unsigned int);
extern const char *rs6000_pltseq_template (rtx *, int);
extern enum rtx_code rs6000_reverse_condition (machine_mode,
- enum rtx_code, bool);
+ enum rtx_code);
extern rtx rs6000_emit_eqne (machine_mode, rtx, rtx, rtx);
extern rtx rs6000_emit_fp_cror (rtx_code, machine_mode, rtx);
extern void rs6000_emit_sCOND (machine_mode, rtx[]);
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 276e2f886acc..f9f9a0b931db 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -15360,25 +15360,15 @@ rs6000_print_patchable_function_entry (FILE *file,
}
enum rtx_code
-rs6000_reverse_condition (machine_mode mode,
- enum rtx_code code,
- bool no_ordered)
+rs6000_reverse_condition (machine_mode mode, enum rtx_code code)
{
/* Reversal of FP compares takes care -- an ordered compare
- becomes an unordered compare and vice versa.
-
- However, this is not safe for ordered comparisons (i.e. for isgreater,
- etc.) starting with the power9 because ifcvt.cc will want to create a fp
- cmove, and the x{s,v}cmp{eq,gt,ge}{dp,qp} instructions will trap if one of
- the arguments is a signalling NaN. */
-
+ becomes an unordered compare and vice versa. */
if (mode == CCFPmode
&& (!flag_finite_math_only
|| code == UNLT || code == UNLE || code == UNGT || code == UNGE
|| code == UNEQ || code == LTGT))
-return (no_ordered
- ? UNKNOWN
- : reverse_condition_maybe_unordered (code));
+return reverse_condition_maybe_unordered (code);
else
return reverse_condition (code);
}
@@ -15993,8 +15983,7 @@ rs6000_emit_sCOND (machine_mode mode, rtx operands[])
cc_mode = GET_MODE (XEXP (condition_rtx, 0));
- rev_cond_rtx = gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode,
cond_code,
- false),
+ rev_cond_rtx = gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode,
cond_code),
SImode, XEXP (condition_rtx, 0),
const0_rtx);
not_op = gen_rtx_COMPARE (CCEQmode, rev_cond_rtx, const0_rtx);
emit_insn (gen_rtx_SET (not_result, not_op));
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 98228ee5ac16..ec08c96d0f67 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -1812,17 +1812,11 @@ extern scalar_int_mode rs6000_pmode;
/* Can the condition code MODE be safely reversed? This is safe in
all cases on this port, because at present it doesn't use the
- trapping FP comparisons (fcmpo).
-
- However, this is not safe for ordered comparisons (i.e. for isgreater, etc.)
- starting with the power9 because ifcvt.cc will want to create a fp cmove,
- and the x{s,v}cmp{eq,gt,ge}{dp,qp} instructions will trap if one of the
- arguments is a signalling NaN. */
+ trapping FP comparisons (fcmpo). */
#define REVERSIBLE_CC_MODE(MODE) 1
/* Given a condition code and a mode, return the inverse condition. */
-#define REVERSE_CONDITION(CODE, MODE) \
- rs6000_reverse_condition (MODE, CODE, true)
+#define REVERSE_CONDITION(CODE, MODE) rs6000_reverse_condition (MODE, CODE)
/* Target cpu costs. */
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index cf4b10257903..65da0c653304 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -13497,7 +13497,7 @@
;; If we are comparing the result of two comparisons, this can be done
;; using creqv or crxor.
-(define_insn_and_split "*reverse_branch_comparison"
+(define_insn_and_split ""
[(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
(compare:CCEQ (match_operator 1 "branch_comparison_operator"
[(match_operand 2 "cc_reg_operand" "y")
@@ -13519,25 +13519,19 @@
GET_MODE (operands[3]));
if (! positive_1)
-{
- enum rtx_code rev = rs6000_reverse_condition (GET_MODE (operands[
[gcc r15-7180] c++/modules: Fix linkage checks for exported using-decls
https://gcc.gnu.org/g:3469d0f6eaa6251882364ba304a3f67327f46a84
commit r15-7180-g3469d0f6eaa6251882364ba304a3f67327f46a84
Author: yxj-github-437 <2457369...@qq.com>
Date: Thu Jan 16 08:36:15 2025 +0800
c++/modules: Fix linkage checks for exported using-decls
This patch attempts to fix an error when build module std. The reason for
the error is __builtin_va_list (aka struct __va_list) has internal linkage.
so mark this builtin type as TREE_PUBLIC to make struct __va_list has
external linkage.
g++ -fmodules -std=c++23 -fsearch-include-path bits/std.cc -c
std.cc:3642:14:error: exporting ‘typedef __gnuc_va_list va_list’ that does
not have external linkage
3642 | using std::va_list;
| ^~~
: note: ‘struct __va_list’ declared here with internal linkage
gcc/ChangeLog:
* config/aarch64/aarch64.cc (aarch64_build_builtin_va_list): Mark
__builtin_va_list as TREE_PUBLIC.
* config/arm/arm.cc (arm_build_builtin_va_list): Likewise.
gcc/testsuite/ChangeLog:
* g++.dg/modules/builtin-8.C: New test.
Reviewed-by: Jason Merrill
Diff:
---
gcc/config/aarch64/aarch64.cc| 1 +
gcc/config/arm/arm.cc| 1 +
gcc/testsuite/g++.dg/modules/builtin-8.C | 9 +
3 files changed, 11 insertions(+)
diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc
index a1f5619a6152..9c4e9bc8acde 100644
--- a/gcc/config/aarch64/aarch64.cc
+++ b/gcc/config/aarch64/aarch64.cc
@@ -21584,6 +21584,7 @@ aarch64_build_builtin_va_list (void)
get_identifier ("__va_list"),
va_list_type);
DECL_ARTIFICIAL (va_list_name) = 1;
+ TREE_PUBLIC (va_list_name) = 1;
TYPE_NAME (va_list_type) = va_list_name;
TYPE_STUB_DECL (va_list_type) = va_list_name;
diff --git a/gcc/config/arm/arm.cc b/gcc/config/arm/arm.cc
index 1e0791dc8c25..86838ebde5f8 100644
--- a/gcc/config/arm/arm.cc
+++ b/gcc/config/arm/arm.cc
@@ -2906,6 +2906,7 @@ arm_build_builtin_va_list (void)
get_identifier ("__va_list"),
va_list_type);
DECL_ARTIFICIAL (va_list_name) = 1;
+ TREE_PUBLIC (va_list_name) = 1;
TYPE_NAME (va_list_type) = va_list_name;
TYPE_STUB_DECL (va_list_type) = va_list_name;
/* Create the __ap field. */
diff --git a/gcc/testsuite/g++.dg/modules/builtin-8.C
b/gcc/testsuite/g++.dg/modules/builtin-8.C
new file mode 100644
index ..ff91104e4a96
--- /dev/null
+++ b/gcc/testsuite/g++.dg/modules/builtin-8.C
@@ -0,0 +1,9 @@
+// { dg-additional-options -fmodules-ts }
+module;
+#include
+export module builtins;
+// { dg-module-cmi builtins }
+
+export {
+ using ::va_list;
+}
[gcc r15-7200] PR modula2/118589 Opaque type fields are visible outside implementation module
https://gcc.gnu.org/g:7be54613e8a1b1080f0480cf061baa73317a26d3
commit r15-7200-g7be54613e8a1b1080f0480cf061baa73317a26d3
Author: Gaius Mulley
Date: Sat Jan 25 00:05:48 2025 +
PR modula2/118589 Opaque type fields are visible outside implementation
module
This patch fixes a bug shown when a variable declared as an opaque type is
dereferenced outside the declaration module. The fix also improves error
recovery. In the error cases it ensures that an error symbol is created
and the appropriate virtual token is assigned. Finally there is a new
testsuite directory gm2.dg which contains tests to check against expected
error messages.
gcc/m2/ChangeLog:
PR modula2/118589
* gm2-compiler/M2MetaError.mod (symDesc): Add opaque type
description.
* gm2-compiler/M2Quads.mod (BuildDesignatorPointerError): New
procedure.
(BuildDesignatorPointer): Reimplement.
* gm2-compiler/P3Build.bnf (SubDesignator): Tidy up error message.
Use MetaErrorT2 rather than WriteForma1 and use the token pos from
the quad stack.
gcc/testsuite/ChangeLog:
PR modula2/118589
* lib/gm2-dg.exp (gm2.exp): load_lib.
* gm2.dg/pim/fail/badopaque.mod: New test.
* gm2.dg/pim/fail/badopaque2.mod: New test.
* gm2.dg/pim/fail/dg-pim-fail.exp: New test.
* gm2.dg/pim/fail/opaquedefs.def: New test.
* gm2.dg/pim/fail/opaquedefs.mod: New test.
Signed-off-by: Gaius Mulley
Diff:
---
gcc/m2/gm2-compiler/M2MetaError.mod | 7 ++-
gcc/m2/gm2-compiler/M2Quads.mod | 90 ++-
gcc/m2/gm2-compiler/P3Build.bnf | 7 +--
gcc/testsuite/gm2.dg/pim/fail/badopaque.mod | 15 +
gcc/testsuite/gm2.dg/pim/fail/badopaque2.mod | 17 +
gcc/testsuite/gm2.dg/pim/fail/dg-pim-fail.exp | 34 ++
gcc/testsuite/gm2.dg/pim/fail/opaquedefs.def | 7 +++
gcc/testsuite/gm2.dg/pim/fail/opaquedefs.mod | 13
gcc/testsuite/lib/gm2-dg.exp | 2 +
9 files changed, 157 insertions(+), 35 deletions(-)
diff --git a/gcc/m2/gm2-compiler/M2MetaError.mod
b/gcc/m2/gm2-compiler/M2MetaError.mod
index 11874861e66d..22bc77f6ad00 100644
--- a/gcc/m2/gm2-compiler/M2MetaError.mod
+++ b/gcc/m2/gm2-compiler/M2MetaError.mod
@@ -1611,7 +1611,12 @@ BEGIN
END
ELSIF IsType(sym)
THEN
- RETURN InitString('type')
+ IF IsHiddenType (sym)
+ THEN
+ RETURN InitString('opaque type')
+ ELSE
+ RETURN InitString('type')
+ END
ELSIF IsRecord(sym)
THEN
RETURN InitString('record')
diff --git a/gcc/m2/gm2-compiler/M2Quads.mod b/gcc/m2/gm2-compiler/M2Quads.mod
index fd3482b1f2d2..785a6e9885a8 100644
--- a/gcc/m2/gm2-compiler/M2Quads.mod
+++ b/gcc/m2/gm2-compiler/M2Quads.mod
@@ -63,6 +63,7 @@ FROM SymbolTable IMPORT ModeOfAddr, GetMode, PutMode,
GetSymName, IsUnknown,
GetScope, GetCurrentScope,
GetSubrange, SkipTypeAndSubrange,
GetModule, GetMainModule,
+GetModuleScope, GetCurrentModuleScope,
GetCurrentModule, GetFileModule, GetLocalSym,
GetStringLength, GetString,
GetArraySubscript, GetDimension,
@@ -115,7 +116,7 @@ FROM SymbolTable IMPORT ModeOfAddr, GetMode, PutMode,
GetSymName, IsUnknown,
PutDeclared,
MakeComponentRecord, MakeComponentRef,
IsSubscript, IsComponent, IsConstStringKnown,
-IsTemporary,
+IsTemporary, IsHiddenType,
IsAModula2Type,
PutLeftValueFrontBackType,
PushSize, PushValue, PopValue,
@@ -11427,6 +11428,24 @@ BEGIN
END BuildDesignatorError ;
+(*
+ BuildDesignatorPointerError - removes the designator from the stack and
replaces
+ it with an error symbol.
+*)
+
+PROCEDURE BuildDesignatorPointerError (type, rw: CARDINAL; tokpos: CARDINAL;
+ message: ARRAY OF CHAR) ;
+VAR
+ error: CARDINAL ;
+BEGIN
+ error := MakeError (tokpos, MakeKey (message)) ;
+ IF GetSType (type) # NulSym
+ THEN
+ type := GetSType (type)
+ END ;
+ PushTFrwtok (error, type, rw, tokpos)
+END BuildDesignatorPointerError ;
+
(*
BuildDesignatorArray - Builds the array referencing.
@@ -11819,13 +11838,13 @@ END DebugLocation ;
PROCEDURE BuildDesignatorPointer (ptrtok: CARDINAL) ;
VAR
combinedtok,
- exprtok: CARDINAL ;
+ destok: CARDINAL ;
rw,
Sym1, Type1,
Sym2, Type2: CARDINAL ;
BEGIN
- PopTFrwtok (Sym1, Type1, rw, exprtok) ;
- DebugLocation (exprtok, "expression") ;
+ PopTFrwtok (Sym1, Type1, rw, destok) ;
+ DebugL
[gcc r14-11246] Fortran: Fix UTF-8 output with A edit descriptor.
https://gcc.gnu.org/g:b69eb2c594f8595718d876dc9811e3820eb68da1
commit r14-11246-gb69eb2c594f8595718d876dc9811e3820eb68da1
Author: Jerry DeLisle
Date: Thu Jan 23 12:58:14 2025 -0800
Fortran: Fix UTF-8 output with A edit descriptor.
This adjusts the source len for the case where the user has
specified a field width with the A descriptor.
PR libfortran/118571
libgfortran/ChangeLog:
* io/write.c (write_utf8_char4): Adjust the src_len to the
format width w_len when greater than zero.
gcc/testsuite/ChangeLog:
* gfortran.dg/utf8_3.f03: New test.
(cherry picked from commit 4daf088123b2c4c3114a4b96d5353c3d72eb8ac9)
Diff:
---
gcc/testsuite/gfortran.dg/utf8_3.f03 | 57
libgfortran/io/write.c | 4 ++-
2 files changed, 60 insertions(+), 1 deletion(-)
diff --git a/gcc/testsuite/gfortran.dg/utf8_3.f03
b/gcc/testsuite/gfortran.dg/utf8_3.f03
new file mode 100644
index ..e1688149e5dc
--- /dev/null
+++ b/gcc/testsuite/gfortran.dg/utf8_3.f03
@@ -0,0 +1,57 @@
+! { dg-do run }
+! PR118571 UTF-8 output and the A edit descriptor.
+
+program test
+
+ use iso_fortran_env
+
+ implicit none
+
+ integer, parameter :: ucs4 = selected_char_kind('ISO_10646')
+
+ character(kind=ucs4, len=1), parameter :: alpha = char(int(z'03B1'), ucs4)
+ character(kind=ucs4, len=1), parameter :: beta = char(int(z'03B2'), ucs4)
+ character(kind=ucs4, len=1), parameter :: space = ucs4_' '
+
+ integer fd
+ character(kind=ucs4,len=:), allocatable :: str
+ character(kind=ucs4,len=25) :: instr, correct
+
+ fd = 42
+
+ open (fd, encoding='UTF-8', status="scratch")
+ open (output_unit, encoding='UTF-8')
+ str = repeat(space,6)//alpha//beta//alpha//beta
+
+ write(fd,'(I4,1X,A)') len_trim(str), str
+ rewind(fd)
+ read(fd,'(a)') instr
+ if (trim(instr) /= ucs4_' 10 '//trim(str)) stop 1
+
+ str = alpha // beta // alpha // beta
+ rewind(fd)
+ write(fd,'(I4,1X,">",A,"<")') len_trim(str(1:1)), str(1:1)
+ rewind(fd)
+ read(fd,'(a)') instr
+ if (trim(instr) /= ucs4_' 1 >'//alpha//ucs4_'<') stop 2
+
+ rewind(fd)
+ write(fd,*) len_trim(str(1:1)), str(1:1)
+ rewind(fd)
+ read(fd,'(a)') instr
+ if (trim(instr) /= ucs4_' 1 '//alpha) stop 3
+
+ rewind(fd)
+ write(fd,'(I4,1X,">",A1,"<")') len_trim(str(1:1)), str(1:1)
+ rewind(fd)
+ read(fd, '(a)') instr
+ if (trim(instr) /= ucs4_' 1 >'//alpha//ucs4_'<') stop 4
+
+ rewind(fd)
+ write(fd,'(I4,1X,">",A1,"<")') len_trim(str), str
+ rewind(fd)
+ read(fd, '(a)') instr
+ if (trim(instr) /= ucs4_' 4 >'//alpha//ucs4_'<') stop 5
+ close(fd)
+end program
+
diff --git a/libgfortran/io/write.c b/libgfortran/io/write.c
index 9d0a0d6102b3..bc22054fee96 100644
--- a/libgfortran/io/write.c
+++ b/libgfortran/io/write.c
@@ -177,7 +177,9 @@ write_utf8_char4 (st_parameter_dt *dtp, gfc_char4_t *source,
break;
}
- /* Now process the remaining characters, one at a time. */
+ /* Now process the remaining characters, one at a time. We need to
+ adjust the src_len if the user has specified a field width. */
+ src_len = w_len > 0 ? w_len : src_len;
for (j = k; j < src_len; j++)
{
c = source[j];
[gcc r15-7205] PR modula2/118010 m2 libc lseek procedure interface correction
https://gcc.gnu.org/g:d0acb7b2b26d4f821968043eafd286a1a3a37ca3
commit r15-7205-gd0acb7b2b26d4f821968043eafd286a1a3a37ca3
Author: Gaius Mulley
Date: Sat Jan 25 02:28:13 2025 +
PR modula2/118010 m2 libc lseek procedure interface correction
This patch corrects a typo in the definition of lseek in libc.
The second offset parameter should have been declared as COFF_T.
No errors are seen when bootstrapping using -Werror=odr
-Werror=lto-type-mismatch.
gcc/m2/ChangeLog:
PR modula2/118010
* gm2-compiler/P2SymBuild.mod (Debug): Comment out unused
procedure.
* gm2-libs/libc.def (lseek): Declare second parameter offset
as COFF_T.
Signed-off-by: Gaius Mulley
Diff:
---
gcc/m2/gm2-compiler/P2SymBuild.mod | 2 ++
gcc/m2/gm2-libs/libc.def | 2 +-
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/gcc/m2/gm2-compiler/P2SymBuild.mod
b/gcc/m2/gm2-compiler/P2SymBuild.mod
index 1b59f3d631b6..8f3b4995ac88 100644
--- a/gcc/m2/gm2-compiler/P2SymBuild.mod
+++ b/gcc/m2/gm2-compiler/P2SymBuild.mod
@@ -182,6 +182,7 @@ PROCEDURE stop ; BEGIN END stop ;
Debug - call stop if symbol name is name.
*)
+(*
PROCEDURE Debug (tok: CARDINAL; sym: CARDINAL; name: ARRAY OF CHAR) ;
BEGIN
IF MakeKey (name) = GetSymName (sym)
@@ -190,6 +191,7 @@ BEGIN
END ;
MetaErrorT1 (tok, 'procedure {%1Wa}', sym)
END Debug ;
+*)
(*
diff --git a/gcc/m2/gm2-libs/libc.def b/gcc/m2/gm2-libs/libc.def
index f1f13ddd9aeb..525d01645900 100644
--- a/gcc/m2/gm2-libs/libc.def
+++ b/gcc/m2/gm2-libs/libc.def
@@ -311,7 +311,7 @@ PROCEDURE creat (filename: ADDRESS; mode: CARDINAL) :
INTEGER;
off_t lseek(int fildes, off_t offset, int whence);
*)
-PROCEDURE lseek (fd: INTEGER; offset: CSSIZE_T; whence: INTEGER) : [ COFF_T ] ;
+PROCEDURE lseek (fd: INTEGER; offset: COFF_T; whence: INTEGER) : [ COFF_T ] ;
(*
[gcc r15-7202] c++: Fix mangling of otherwise unattached class-scope lambdas [PR118245]
https://gcc.gnu.org/g:8990070b4297b913025d564293f97c0440622976
commit r15-7202-g8990070b4297b913025d564293f97c0440622976
Author: Nathaniel Shead
Date: Thu Jan 23 19:22:04 2025 +1100
c++: Fix mangling of otherwise unattached class-scope lambdas [PR118245]
This is a step closer to implementing the suggested changes for
https://github.com/itanium-cxx-abi/cxx-abi/pull/85. Most lambdas
defined within a class should have an extra scope of that class so that
uses across different TUs are properly merged by the linker. This also
needs to happen during template instantiation.
While I was working on this I found some other cases where the mangling
of lambdas was incorrect and causing issues, notably the testcase
lambda-ctx3.C which currently emits the same mangling for the base class
and member lambdas, causing mysterious assembler errors since r14-9232.
One notable case not handled either here or in the ABI is what is
supposed to happen with such unattached lambdas declared in member
templates; see lambda-uneval22. I believe that by the C++ standard,
such lambdas should also dedup across TUs, but this isn't currently
implemented, and it's not clear exactly how such lambdas should mangle.
Since this should only affect usage of lambdas in unevaluated contexts
(a C++20 feature) this patch does not add an ABI flag to control this
behaviour.
PR c++/118245
gcc/cp/ChangeLog:
* cp-tree.h (LAMBDA_EXPR_EXTRA_SCOPE): Adjust comment.
* parser.cc (cp_parser_class_head): Start (and do not finish)
lambda scope for all valid types.
(cp_parser_class_specifier): Finish lambda scope after parsing
members instead.
* pt.cc (instantiate_class_template): Add lambda scoping.
gcc/testsuite/ChangeLog:
* g++.dg/abi/lambda-ctx3.C: New test.
* g++.dg/cpp2a/lambda-uneval22.C: New test.
* g++.dg/cpp2a/lambda-uneval23.C: New test.
Signed-off-by: Nathaniel Shead
Reviewed-by: Jason Merrill
Diff:
---
gcc/cp/cp-tree.h | 3 ++-
gcc/cp/parser.cc | 23 ++-
gcc/cp/pt.cc | 6 ++
gcc/testsuite/g++.dg/abi/lambda-ctx3.C | 27 +++
gcc/testsuite/g++.dg/cpp2a/lambda-uneval22.C | 21 +
gcc/testsuite/g++.dg/cpp2a/lambda-uneval23.C | 7 +++
6 files changed, 77 insertions(+), 10 deletions(-)
diff --git a/gcc/cp/cp-tree.h b/gcc/cp/cp-tree.h
index 5e8aefc12893..5d79cf927d92 100644
--- a/gcc/cp/cp-tree.h
+++ b/gcc/cp/cp-tree.h
@@ -1562,7 +1562,8 @@ enum cp_lambda_default_capture_mode_type {
(((struct tree_lambda_expr *)LAMBDA_EXPR_CHECK (NODE))->locus)
/* The mangling scope for the lambda: FUNCTION_DECL, PARM_DECL, VAR_DECL,
- FIELD_DECL or NULL_TREE. If this is NULL_TREE, we have no linkage. */
+ FIELD_DECL, TYPE_DECL, or NULL_TREE. If this is NULL_TREE, we have no
+ linkage. */
#define LAMBDA_EXPR_EXTRA_SCOPE(NODE) \
(((struct tree_lambda_expr *)LAMBDA_EXPR_CHECK (NODE))->extra_scope)
diff --git a/gcc/cp/parser.cc b/gcc/cp/parser.cc
index 03010089c3c6..2f88e5fcd914 100644
--- a/gcc/cp/parser.cc
+++ b/gcc/cp/parser.cc
@@ -27462,6 +27462,8 @@ cp_parser_class_specifier (cp_parser* parser)
if (!braces.require_open (parser))
{
pop_deferring_access_checks ();
+ if (type != error_mark_node)
+ finish_lambda_scope ();
return error_mark_node;
}
@@ -27526,7 +27528,10 @@ cp_parser_class_specifier (cp_parser* parser)
if (cp_parser_allow_gnu_extensions_p (parser))
attributes = cp_parser_gnu_attributes_opt (parser);
if (type != error_mark_node)
-type = finish_struct (type, attributes);
+{
+ type = finish_struct (type, attributes);
+ finish_lambda_scope ();
+}
if (nested_name_specifier_p)
pop_inner_scope (old_scope, scope);
@@ -28366,6 +28371,12 @@ cp_parser_class_head (cp_parser* parser,
if (flag_concepts)
type = associate_classtype_constraints (type);
+ /* Lambdas in bases and members must have the same mangling scope for ABI.
+ We open this scope now, and will close it in cp_parser_class_specifier
+ after parsing the member list. */
+ if (type && type != error_mark_node)
+start_lambda_scope (TYPE_NAME (type));
+
/* We will have entered the scope containing the class; the names of
base classes should be looked up in that context. For example:
@@ -28380,16 +28391,10 @@ cp_parser_class_head (cp_parser* parser,
if (cp_lexer_next_token_is (parser->lexer, CPP_COLON))
{
if (type)
- {
- pushclass (type);
- start_lambda_scope (TYPE_NAME (type));
- }
+ pushclass (type);
bases = cp_parser_base_clause (parser);
if (type)
- {
- finish_lambda_sco
[gcc r15-7203] c++/modules: Diagnose TU-local lambdas, give mangling scope to lambdas in concepts
https://gcc.gnu.org/g:4c01f40985eafccc3dd058441325b58009defd09
commit r15-7203-g4c01f40985eafccc3dd058441325b58009defd09
Author: Nathaniel Shead
Date: Sun Jan 5 23:45:05 2025 +1100
c++/modules: Diagnose TU-local lambdas, give mangling scope to lambdas in
concepts
This fills in a hole left in r15-6378-g9016c5ac94c557 with regards to
detection of TU-local lambdas. Now that LAMBDA_EXPR_EXTRA_SCOPE is
properly set for most lambdas we can use it to detect lambdas that are
TU-local.
CWG2988 suggests that lambdas in concept definitions should not be
considered TU-local, since they are always unevaluated and should never
be emitted. This patch gives these lambdas a mangling scope (though it
will never be actually used in name mangling).
PR c++/116568
gcc/cp/ChangeLog:
* cp-tree.h (finish_concept_definition): Adjust parameters.
(start_concept_definition): Declare.
* module.cc (depset::hash::is_tu_local_entity): Use
LAMBDA_EXPR_EXTRA_SCOPE to detect TU-local lambdas.
* parser.cc (cp_parser_concept_definition): Start a lambda scope
for concept definitions.
* pt.cc (tsubst_lambda_expr): Namespace-scope lambdas may now
have extra scope.
(finish_concept_definition): Split into...
(start_concept_definition): ...this new function.
gcc/testsuite/ChangeLog:
* g++.dg/modules/internal-4_b.C: Remove XFAIL, add lambda alias
testcase.
* g++.dg/modules/lambda-9.h: New test.
* g++.dg/modules/lambda-9_a.H: New test.
* g++.dg/modules/lambda-9_b.C: New test.
Signed-off-by: Nathaniel Shead
Reviewed-by: Jason Merrill
Diff:
---
gcc/cp/cp-tree.h| 3 ++-
gcc/cp/module.cc| 15 +--
gcc/cp/parser.cc| 14 +-
gcc/cp/pt.cc| 21 +++--
gcc/testsuite/g++.dg/modules/internal-4_b.C | 5 +++--
gcc/testsuite/g++.dg/modules/lambda-9.h | 3 +++
gcc/testsuite/g++.dg/modules/lambda-9_a.H | 4
gcc/testsuite/g++.dg/modules/lambda-9_b.C | 6 ++
8 files changed, 55 insertions(+), 16 deletions(-)
diff --git a/gcc/cp/cp-tree.h b/gcc/cp/cp-tree.h
index 5d79cf927d92..4aa9f9f9aa91 100644
--- a/gcc/cp/cp-tree.h
+++ b/gcc/cp/cp-tree.h
@@ -8689,7 +8689,8 @@ struct diagnosing_failed_constraint
extern cp_expr finish_constraint_or_expr (location_t, cp_expr, cp_expr);
extern cp_expr finish_constraint_and_expr (location_t, cp_expr, cp_expr);
extern cp_expr finish_constraint_primary_expr (cp_expr);
-extern tree finish_concept_definition (cp_expr, tree, tree);
+extern tree start_concept_definition (cp_expr);
+extern tree finish_concept_definition (tree, tree, tree);
extern tree combine_constraint_expressions (tree, tree);
extern tree append_constraint (tree, tree);
extern tree get_constraints (const_tree);
diff --git a/gcc/cp/module.cc b/gcc/cp/module.cc
index 17215594fd3f..1c1eb2e37e2d 100644
--- a/gcc/cp/module.cc
+++ b/gcc/cp/module.cc
@@ -11329,7 +11329,8 @@ trees_out::key_mergeable (int tag, merge_kind mk, tree
decl, tree inner,
gcc_checking_assert (TREE_CODE (scope) == VAR_DECL
|| TREE_CODE (scope) == FIELD_DECL
|| TREE_CODE (scope) == PARM_DECL
-|| TREE_CODE (scope) == TYPE_DECL);
+|| TREE_CODE (scope) == TYPE_DECL
+|| TREE_CODE (scope) == CONCEPT_DECL);
/* Lambdas attached to fields are keyed to the class. */
if (TREE_CODE (scope) == FIELD_DECL)
scope = TYPE_NAME (DECL_CONTEXT (scope));
@@ -13435,9 +13436,10 @@ depset::hash::is_tu_local_entity (tree decl, bool
explain/*=false*/)
tree main_decl = TYPE_MAIN_DECL (type);
if (!DECL_CLASS_SCOPE_P (main_decl)
&& !decl_function_context (main_decl)
- /* FIXME: Lambdas defined outside initializers. We'll need to more
-thoroughly set LAMBDA_TYPE_EXTRA_SCOPE to check this. */
- && !LAMBDA_TYPE_P (type))
+ /* LAMBDA_EXPR_EXTRA_SCOPE will be set for lambdas defined in
+contexts where they would not be TU-local. */
+ && !(LAMBDA_TYPE_P (type)
+ && LAMBDA_TYPE_EXTRA_SCOPE (type)))
{
if (explain)
inform (loc, "%qT has no name and is not defined within a class, "
@@ -20309,11 +20311,12 @@ maybe_key_decl (tree ctx, tree decl)
return;
/* We only need to deal with lambdas attached to var, field,
- parm, or type decls. */
+ parm, type, or concept decls. */
if (TREE_CODE (ctx) != VAR_DECL
&& TREE_CODE (ctx) != FIELD_DECL
[gcc r15-7204] c++/modules: Treat unattached lambdas as TU-local [PR116568]
https://gcc.gnu.org/g:80bd9eb48190f3554c4de74ccb3d0976831160b1
commit r15-7204-g80bd9eb48190f3554c4de74ccb3d0976831160b1
Author: Nathaniel Shead
Date: Sun Jan 5 23:01:44 2025 +1100
c++/modules: Treat unattached lambdas as TU-local [PR116568]
This fixes ICEs where unattached lambdas at class scope (for instance,
in member template instantiations) are streamed. This is only possible
in header units, as in named modules attempting to stream such lambdas
will be an error.
PR c++/116568
gcc/cp/ChangeLog:
* module.cc (trees_out::get_merge_kind): Treat all lambdas
without a mangling scope as un-mergeable.
gcc/testsuite/ChangeLog:
* g++.dg/modules/lambda-8.h: New test.
* g++.dg/modules/lambda-8_a.H: New test.
* g++.dg/modules/lambda-8_b.C: New test.
Signed-off-by: Nathaniel Shead
Reviewed-by: Jason Merrill
Diff:
---
gcc/cp/module.cc | 29 +
gcc/testsuite/g++.dg/modules/lambda-8.h | 8
gcc/testsuite/g++.dg/modules/lambda-8_a.H | 5 +
gcc/testsuite/g++.dg/modules/lambda-8_b.C | 7 +++
4 files changed, 37 insertions(+), 12 deletions(-)
diff --git a/gcc/cp/module.cc b/gcc/cp/module.cc
index 1c1eb2e37e2d..c89834c1abdf 100644
--- a/gcc/cp/module.cc
+++ b/gcc/cp/module.cc
@@ -11014,18 +11014,23 @@ trees_out::get_merge_kind (tree decl, depset *dep)
g++.dg/modules/lambda-6_a.C. */
if (DECL_IMPLICIT_TYPEDEF_P (STRIP_TEMPLATE (decl))
&& LAMBDA_TYPE_P (TREE_TYPE (decl)))
- if (tree scope = LAMBDA_TYPE_EXTRA_SCOPE (TREE_TYPE (decl)))
- {
- /* Lambdas attached to fields are keyed to its class. */
- if (TREE_CODE (scope) == FIELD_DECL)
- scope = TYPE_NAME (DECL_CONTEXT (scope));
- if (DECL_LANG_SPECIFIC (scope)
- && DECL_MODULE_KEYED_DECLS_P (scope))
- {
- mk = MK_keyed;
- break;
- }
- }
+ {
+ if (tree scope = LAMBDA_TYPE_EXTRA_SCOPE (TREE_TYPE (decl)))
+ {
+ /* Lambdas attached to fields are keyed to its class. */
+ if (TREE_CODE (scope) == FIELD_DECL)
+ scope = TYPE_NAME (DECL_CONTEXT (scope));
+ if (DECL_LANG_SPECIFIC (scope)
+ && DECL_MODULE_KEYED_DECLS_P (scope))
+ {
+ mk = MK_keyed;
+ break;
+ }
+ }
+ /* Lambdas not attached to any mangling scope are TU-local. */
+ mk = MK_unique;
+ break;
+ }
if (TREE_CODE (decl) == TEMPLATE_DECL
&& DECL_UNINSTANTIATED_TEMPLATE_FRIEND_P (decl))
diff --git a/gcc/testsuite/g++.dg/modules/lambda-8.h
b/gcc/testsuite/g++.dg/modules/lambda-8.h
new file mode 100644
index ..c4bb20dcf1f9
--- /dev/null
+++ b/gcc/testsuite/g++.dg/modules/lambda-8.h
@@ -0,0 +1,8 @@
+// PR c++/116568
+
+template struct S {
+ template using t = decltype([]{});
+};
+
+// 't' does not currently have a mangling scope, but should not ICE
+using t = S::t;
diff --git a/gcc/testsuite/g++.dg/modules/lambda-8_a.H
b/gcc/testsuite/g++.dg/modules/lambda-8_a.H
new file mode 100644
index ..d20958ee140f
--- /dev/null
+++ b/gcc/testsuite/g++.dg/modules/lambda-8_a.H
@@ -0,0 +1,5 @@
+// PR c++/116568
+// { dg-additional-options "-fmodules-ts -std=c++20" }
+// { dg-module-cmi {} }
+
+#include "lambda-8.h"
diff --git a/gcc/testsuite/g++.dg/modules/lambda-8_b.C
b/gcc/testsuite/g++.dg/modules/lambda-8_b.C
new file mode 100644
index ..7ace4944dd2d
--- /dev/null
+++ b/gcc/testsuite/g++.dg/modules/lambda-8_b.C
@@ -0,0 +1,7 @@
+// PR c++/116568
+// { dg-additional-options "-fmodules-ts -fno-module-lazy -std=c++20" }
+
+#include "lambda-8.h"
+import "lambda-8_a.H";
+
+// { dg-error "conflicting global module declaration" "" { target *-*-* } 0 }
[gcc r15-7174] Fix command flags for SVE2 faminmax
https://gcc.gnu.org/g:8bdf10fc2e9ac16a296f76a442c068216469b3a3
commit r15-7174-g8bdf10fc2e9ac16a296f76a442c068216469b3a3
Author: Saurabh Jha
Date: Tue Jan 21 15:59:39 2025 +
Fix command flags for SVE2 faminmax
Earlier, we were gating SVE2 faminmax behind sve+faminmax. This was
incorrect and this patch changes it so that it is gated behind
sve2+faminmax.
gcc/ChangeLog:
* config/aarch64/aarch64-sve2.md:
(*aarch64_pred_faminmax_fused): Fix to use the correct flags.
* config/aarch64/aarch64.h
(TARGET_SVE_FAMINMAX): Remove.
* config/aarch64/iterators.md: Fix iterators so that famax and
famin use correct flags.
gcc/testsuite/ChangeLog:
* gcc.target/aarch64/sve/faminmax_1.c: Fix test to use the
correct flags.
* gcc.target/aarch64/sve/faminmax_2.c: Fix test to use the
correct flags.
* gcc.target/aarch64/sve/faminmax_3.c: New test.
Diff:
---
gcc/config/aarch64/aarch64-sve2.md| 2 +-
gcc/config/aarch64/aarch64.h | 1 -
gcc/config/aarch64/iterators.md | 8
gcc/testsuite/gcc.target/aarch64/sve/faminmax_1.c | 2 +-
gcc/testsuite/gcc.target/aarch64/sve/faminmax_2.c | 2 +-
gcc/testsuite/gcc.target/aarch64/sve/faminmax_3.c | 11 +++
6 files changed, 18 insertions(+), 8 deletions(-)
diff --git a/gcc/config/aarch64/aarch64-sve2.md
b/gcc/config/aarch64/aarch64-sve2.md
index 60bc03b2650c..3e08e092cd04 100644
--- a/gcc/config/aarch64/aarch64-sve2.md
+++ b/gcc/config/aarch64/aarch64-sve2.md
@@ -2950,7 +2950,7 @@
(match_operand:SVE_FULL_F 3 "register_operand")]
UNSPEC_COND_FABS)]
SVE_COND_SMAXMIN))]
- "TARGET_SVE_FAMINMAX"
+ "TARGET_FAMINMAX && TARGET_SVE2_OR_SME2"
{@ [ cons: =0 , 1 , 2 , 3 ; attrs: movprfx ]
[ w, Upl , %0 , w ; * ]
\t%0., %1/m, %0., %3.
[ ?&w , Upl , w , w ; yes] movprfx\t%0,
%2\;\t%0., %1/m, %0., %3.
diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h
index 5cbf442130bc..1a19b27fd934 100644
--- a/gcc/config/aarch64/aarch64.h
+++ b/gcc/config/aarch64/aarch64.h
@@ -472,7 +472,6 @@ constexpr auto AARCH64_FL_DEFAULT_ISA_MODE ATTRIBUTE_UNUSED
/* Floating Point Absolute Maximum/Minimum extension instructions are
enabled through +faminmax. */
#define TARGET_FAMINMAX AARCH64_HAVE_ISA (FAMINMAX)
-#define TARGET_SVE_FAMINMAX (TARGET_SVE && TARGET_FAMINMAX)
/* Lookup table (LUTI) extension instructions are enabled through +lut. */
#define TARGET_LUT AARCH64_HAVE_ISA (LUT)
diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md
index e843c66cf268..9fbd74939882 100644
--- a/gcc/config/aarch64/iterators.md
+++ b/gcc/config/aarch64/iterators.md
@@ -3340,8 +3340,8 @@
(define_int_iterator SVE_COND_FP_BINARY
[UNSPEC_COND_FADD
- (UNSPEC_COND_FAMAX "TARGET_SVE_FAMINMAX")
- (UNSPEC_COND_FAMIN "TARGET_SVE_FAMINMAX")
+ (UNSPEC_COND_FAMAX "TARGET_FAMINMAX && TARGET_SVE2_OR_SME2")
+ (UNSPEC_COND_FAMIN "TARGET_FAMINMAX && TARGET_SVE2_OR_SME2")
UNSPEC_COND_FDIV
UNSPEC_COND_FMAX
UNSPEC_COND_FMAXNM
@@ -3381,8 +3381,8 @@
UNSPEC_COND_SMIN])
(define_int_iterator SVE_COND_FP_BINARY_REG
- [(UNSPEC_COND_FAMAX "TARGET_SVE_FAMINMAX")
- (UNSPEC_COND_FAMIN "TARGET_SVE_FAMINMAX")
+ [(UNSPEC_COND_FAMAX "TARGET_FAMINMAX && TARGET_SVE2_OR_SME2")
+ (UNSPEC_COND_FAMIN "TARGET_FAMINMAX && TARGET_SVE2_OR_SME2")
UNSPEC_COND_FDIV
UNSPEC_COND_FMULX])
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/faminmax_1.c
b/gcc/testsuite/gcc.target/aarch64/sve/faminmax_1.c
index 3b65ccea0656..154dbd9de846 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/faminmax_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/faminmax_1.c
@@ -3,7 +3,7 @@
#include "arm_sve.h"
-#pragma GCC target "+sve+faminmax"
+#pragma GCC target "+sve2+faminmax"
#define TEST_FAMAX(TYPE) \
void fn_famax_##TYPE (TYPE * restrict a, \
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/faminmax_2.c
b/gcc/testsuite/gcc.target/aarch64/sve/faminmax_2.c
index d80f6eca8f82..44ecef1e0878 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/faminmax_2.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/faminmax_2.c
@@ -3,7 +3,7 @@
#include "arm_sve.h"
-#pragma GCC target "+sve+faminmax"
+#pragma GCC target "+sve2+faminmax"
#define TEST_WITH_SVMAX(TYPE) \
TYPE fn_fmax_##TYPE (TYPE x, TYPE y) { \
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/faminmax_3.c
b/gcc/testsuite/gcc.target/aarch64/sve/faminmax_3.c
new file mode 100644
index ..2b01fa48b8e9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve/faminmax_3.c
@@ -0,0 +1,11 @@
+/* {
[gcc(refs/users/mikael/heads/refactor_descriptor_v01)] Factorisation initialisation depuis cfi
https://gcc.gnu.org/g:ce33b7f2f202eed5a2ef8da85029d06ef589a68c
commit ce33b7f2f202eed5a2ef8da85029d06ef589a68c
Author: Mikael Morin
Date: Fri Jan 24 16:01:58 2025 +0100
Factorisation initialisation depuis cfi
Diff:
---
gcc/fortran/trans-decl.cc | 201 +---
gcc/fortran/trans-expr.cc | 209 +++---
gcc/fortran/trans.h | 2 +
3 files changed, 183 insertions(+), 229 deletions(-)
diff --git a/gcc/fortran/trans-decl.cc b/gcc/fortran/trans-decl.cc
index dad15858fa6a..96a8e8ca10fd 100644
--- a/gcc/fortran/trans-decl.cc
+++ b/gcc/fortran/trans-decl.cc
@@ -7009,7 +7009,7 @@ gfc_conv_cfi_to_gfc (stmtblock_t *init, stmtblock_t
*finally,
stmtblock_t block;
gfc_init_block (&block);
tree cfi = build_fold_indirect_ref_loc (input_location, cfi_desc);
- tree idx, etype, tmp, tmp2, size_var = NULL_TREE, rank = NULL_TREE;
+ tree idx, tmp, tmp2, size_var = NULL_TREE, rank = NULL_TREE;
bool do_copy_inout = false;
/* When allocatable + intent out, free the cfi descriptor. */
@@ -7201,106 +7201,10 @@ gfc_conv_cfi_to_gfc (stmtblock_t *init, stmtblock_t
*finally,
goto done;
}
- if (GFC_DESCRIPTOR_TYPE_P (TREE_TYPE (gfc_desc)))
-{
- /* gfc->dtype = ... (from declaration, not from cfi). */
- etype = gfc_get_element_type (TREE_TYPE (gfc_desc));
- gfc_add_modify (&block, gfc_conv_descriptor_dtype (gfc_desc),
- gfc_get_dtype_rank_type (sym->as->rank, etype));
- /* gfc->data = cfi->base_addr. */
- gfc_conv_descriptor_data_set (&block, gfc_desc,
- gfc_get_cfi_desc_base_addr (cfi));
-}
-
- if (sym->ts.type == BT_ASSUMED)
-{
- /* For type(*), take elem_len + dtype.type from the actual argument. */
- gfc_add_modify (&block, gfc_conv_descriptor_elem_len (gfc_desc),
- gfc_get_cfi_desc_elem_len (cfi));
- tree cond;
- tree ctype = gfc_get_cfi_desc_type (cfi);
- ctype = fold_build2_loc (input_location, BIT_AND_EXPR, TREE_TYPE (ctype),
- ctype, build_int_cst (TREE_TYPE (ctype),
-CFI_type_mask));
- tree type = gfc_conv_descriptor_type (gfc_desc);
-
- /* if (CFI_type_cptr) BT_VOID else BT_UNKNOWN */
- /* Note: BT_VOID is could also be CFI_type_funcptr, but assume c_ptr. */
- cond = fold_build2_loc (input_location, EQ_EXPR, boolean_type_node,
ctype,
- build_int_cst (TREE_TYPE (ctype), CFI_type_cptr));
- tmp = fold_build2_loc (input_location, MODIFY_EXPR, void_type_node, type,
-build_int_cst (TREE_TYPE (type), BT_VOID));
- tmp2 = fold_build2_loc (input_location, MODIFY_EXPR, void_type_node,
- type,
- build_int_cst (TREE_TYPE (type), BT_UNKNOWN));
- tmp2 = fold_build3_loc (input_location, COND_EXPR, void_type_node, cond,
- tmp, tmp2);
- /* if (CFI_type_struct) BT_DERIVED else < tmp2 > */
- cond = fold_build2_loc (input_location, EQ_EXPR, boolean_type_node,
ctype,
- build_int_cst (TREE_TYPE (ctype),
-CFI_type_struct));
- tmp = fold_build2_loc (input_location, MODIFY_EXPR, void_type_node, type,
-build_int_cst (TREE_TYPE (type), BT_DERIVED));
- tmp2 = fold_build3_loc (input_location, COND_EXPR, void_type_node, cond,
- tmp, tmp2);
- /* if (CFI_type_Character) BT_CHARACTER else < tmp2 > */
- /* Note: this is kind=1, CFI_type_ucs4_char is handled in the 'else if'
-before (see below, as generated bottom up). */
- cond = fold_build2_loc (input_location, EQ_EXPR, boolean_type_node,
ctype,
- build_int_cst (TREE_TYPE (ctype),
- CFI_type_Character));
- tmp = fold_build2_loc (input_location, MODIFY_EXPR, void_type_node, type,
-build_int_cst (TREE_TYPE (type), BT_CHARACTER));
- tmp2 = fold_build3_loc (input_location, COND_EXPR, void_type_node, cond,
- tmp, tmp2);
- /* if (CFI_type_ucs4_char) BT_CHARACTER else < tmp2 > */
- /* Note: gfc->elem_len = cfi->elem_len/4. */
- /* However, assuming that CFI_type_ucs4_char cannot be recovered, leave
-gfc->elem_len == cfi->elem_len, which helps with operations which use
-sizeof() in Fortran and cfi->elem_len in C. */
- tmp = gfc_get_cfi_desc_type (cfi);
- cond = fold_build2_loc (input_location, EQ_EXPR, boolean_type_node, tmp,
- build_int_cst (TREE_TYPE (tmp),
-CFI_type_ucs4_char));
- tmp = fold_build2_loc (input_location, MODIFY_EXPR, void_type_node, type,
-bui
[gcc(refs/users/mikael/heads/refactor_descriptor_v01)] utilisation booléen allocatable
https://gcc.gnu.org/g:94d5412377b8011f80e3a14a1d7be8c52f2adf8f
commit 94d5412377b8011f80e3a14a1d7be8c52f2adf8f
Author: Mikael Morin
Date: Thu Jan 23 21:38:24 2025 +0100
utilisation booléen allocatable
Diff:
---
gcc/fortran/trans-expr.cc | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/gcc/fortran/trans-expr.cc b/gcc/fortran/trans-expr.cc
index 95b168fe76a8..518a5a127cf0 100644
--- a/gcc/fortran/trans-expr.cc
+++ b/gcc/fortran/trans-expr.cc
@@ -5938,12 +5938,12 @@ set_dtype_for_unallocated (gfc_se *parmse, gfc_expr *e)
static void
set_gfc_from_cfi (stmtblock_t *block, tree gfc, tree cfi, tree rank,
- gfc_symbol *c_sym)
+ bool allocatable)
{
tree tmp = gfc_get_cfi_desc_base_addr (cfi);
gfc_conv_descriptor_data_set (block, gfc, tmp);
- if (c_sym->attr.allocatable)
+ if (allocatable)
{
/* gfc->span = cfi->elem_len. */
tmp = fold_convert (gfc_array_index_type,
@@ -6396,7 +6396,7 @@ done:
tmp = gfc_get_cfi_desc_base_addr (cfi);
gfc_conv_descriptor_data_set (&block, gfc, tmp);
- set_gfc_from_cfi (&block2, gfc, cfi, rank, fsym);
+ set_gfc_from_cfi (&block2, gfc, cfi, rank, fsym->attr.allocatable);
}
if (e->ts.type == BT_CHARACTER && !e->ts.u.cl->length)
