[gcc r13-9333] c++: Friend classes don't shadow enclosing template class paramater [PR118255]
https://gcc.gnu.org/g:b5d697817bbbc3f40ed74950d287a2c253318d36
commit r13-9333-gb5d697817bbbc3f40ed74950d287a2c253318d36
Author: Simon Martin
Date: Sun Jan 5 10:36:47 2025 +0100
c++: Friend classes don't shadow enclosing template class paramater
[PR118255]
We currently reject the following code
=== code here ===
template struct S { friend class non_template; };
class non_template {};
S<0> s;
=== code here ===
While EDG agrees with the current behaviour, clang and MSVC don't (see
https://godbolt.org/z/69TGaabhd), and I believe that this code is valid,
since the friend clause does not actually declare a type, so it cannot
shadow anything. The fact that we didn't error out if the non_template
class was declared before S backs this up as well.
This patch fixes this by skipping the call to check_template_shadow for
hidden bindings.
PR c++/118255
gcc/cp/ChangeLog:
* name-lookup.cc (pushdecl): Don't call check_template_shadow
for hidden bindings.
gcc/testsuite/ChangeLog:
* g++.dg/lookup/pr99116-1.C: Adjust test expectation.
* g++.dg/template/friend84.C: New test.
(cherry picked from commit b5a069203fc074ab75d994c4a7e0f2db6a0a00fd)
Diff:
---
gcc/cp/name-lookup.cc| 5 -
gcc/testsuite/g++.dg/lookup/pr99116-1.C | 2 +-
gcc/testsuite/g++.dg/template/friend84.C | 26 ++
3 files changed, 31 insertions(+), 2 deletions(-)
diff --git a/gcc/cp/name-lookup.cc b/gcc/cp/name-lookup.cc
index 1ea25f076b85..89f28caf183d 100644
--- a/gcc/cp/name-lookup.cc
+++ b/gcc/cp/name-lookup.cc
@@ -3743,7 +3743,10 @@ pushdecl (tree decl, bool hiding)
if (old && anticipated_builtin_p (old))
old = OVL_CHAIN (old);
- check_template_shadow (decl);
+ if (hiding)
+ ; /* Hidden bindings don't shadow anything. */
+ else
+ check_template_shadow (decl);
if (DECL_DECLARES_FUNCTION_P (decl))
{
diff --git a/gcc/testsuite/g++.dg/lookup/pr99116-1.C
b/gcc/testsuite/g++.dg/lookup/pr99116-1.C
index 01b483ea9153..efee3e4aca36 100644
--- a/gcc/testsuite/g++.dg/lookup/pr99116-1.C
+++ b/gcc/testsuite/g++.dg/lookup/pr99116-1.C
@@ -2,7 +2,7 @@
template struct Z {
- friend struct T; // { dg-error "shadows template parameter" }
+ friend struct T; // { dg-bogus "shadows template parameter" }
};
struct Y {
diff --git a/gcc/testsuite/g++.dg/template/friend84.C
b/gcc/testsuite/g++.dg/template/friend84.C
new file mode 100644
index ..64ea41a552ba
--- /dev/null
+++ b/gcc/testsuite/g++.dg/template/friend84.C
@@ -0,0 +1,26 @@
+// PR c++/118255
+// { dg-do "compile" }
+
+// The PR's case, that used to error out.
+template
+struct S {
+ friend class non_template; // { dg-bogus "shadows template parameter" }
+};
+
+class non_template {};
+S<0> s;
+
+// We already accepted cases where the friend is already declared.
+template
+struct T {
+ friend class non_template;
+};
+T<0> t;
+
+// We should reject (re)declarations.
+template
+struct U {
+ class non_template {}; // { dg-error "shadows template parameter" }
+ void non_template () {} // { dg-error "shadows template parameter" }
+};
+U<0> u;
[gcc r15-7032] Regenerate sparc.opt.urls
https://gcc.gnu.org/g:90dc847eda19d4dad818a896fa9fe5ccb7ef9343
commit r15-7032-g90dc847eda19d4dad818a896fa9fe5ccb7ef9343
Author: Mark Wielaard
Date: Sun Jan 19 18:49:19 2025 +0100
Regenerate sparc.opt.urls
sparc added a -mvis3b option, but the sparc.opt.url file wasn't
regenerated.
Fixes: d309844d6fe0 ("Fix bootstrap failure on SPARC with -O3
-mcpu=niagara4")
gcc/ChangeLog:
* config/sparc/sparc.opt.urls: Regenerated.
Diff:
---
gcc/config/sparc/sparc.opt.urls | 3 +++
1 file changed, 3 insertions(+)
diff --git a/gcc/config/sparc/sparc.opt.urls b/gcc/config/sparc/sparc.opt.urls
index 2a6ffa258e08..1188f88fdaab 100644
--- a/gcc/config/sparc/sparc.opt.urls
+++ b/gcc/config/sparc/sparc.opt.urls
@@ -36,6 +36,9 @@ UrlSuffix(gcc/SPARC-Options.html#index-mvis2)
mvis3
UrlSuffix(gcc/SPARC-Options.html#index-mvis3)
+mvis3b
+UrlSuffix(gcc/SPARC-Options.html#index-mvis3b)
+
mvis4
UrlSuffix(gcc/SPARC-Options.html#index-mvis4)
[gcc r14-11226] c++: Friend classes don't shadow enclosing template class paramater [PR118255]
https://gcc.gnu.org/g:b1f9fb0e133e9654caecb4a6b133ce559f21ca6a
commit r14-11226-gb1f9fb0e133e9654caecb4a6b133ce559f21ca6a
Author: Simon Martin
Date: Sun Jan 5 10:36:47 2025 +0100
c++: Friend classes don't shadow enclosing template class paramater
[PR118255]
We currently reject the following code
=== code here ===
template struct S { friend class non_template; };
class non_template {};
S<0> s;
=== code here ===
While EDG agrees with the current behaviour, clang and MSVC don't (see
https://godbolt.org/z/69TGaabhd), and I believe that this code is valid,
since the friend clause does not actually declare a type, so it cannot
shadow anything. The fact that we didn't error out if the non_template
class was declared before S backs this up as well.
This patch fixes this by skipping the call to check_template_shadow for
hidden bindings.
PR c++/118255
gcc/cp/ChangeLog:
* name-lookup.cc (pushdecl): Don't call check_template_shadow
for hidden bindings.
gcc/testsuite/ChangeLog:
* g++.dg/lookup/pr99116-1.C: Adjust test expectation.
* g++.dg/template/friend84.C: New test.
(cherry picked from commit b5a069203fc074ab75d994c4a7e0f2db6a0a00fd)
Diff:
---
gcc/cp/name-lookup.cc| 5 -
gcc/testsuite/g++.dg/lookup/pr99116-1.C | 2 +-
gcc/testsuite/g++.dg/template/friend84.C | 26 ++
3 files changed, 31 insertions(+), 2 deletions(-)
diff --git a/gcc/cp/name-lookup.cc b/gcc/cp/name-lookup.cc
index b752598564a3..309f8fdadcb3 100644
--- a/gcc/cp/name-lookup.cc
+++ b/gcc/cp/name-lookup.cc
@@ -4001,7 +4001,10 @@ pushdecl (tree decl, bool hiding)
if (old && anticipated_builtin_p (old))
old = OVL_CHAIN (old);
- check_template_shadow (decl);
+ if (hiding)
+ ; /* Hidden bindings don't shadow anything. */
+ else
+ check_template_shadow (decl);
if (DECL_DECLARES_FUNCTION_P (decl))
{
diff --git a/gcc/testsuite/g++.dg/lookup/pr99116-1.C
b/gcc/testsuite/g++.dg/lookup/pr99116-1.C
index 01b483ea9153..efee3e4aca36 100644
--- a/gcc/testsuite/g++.dg/lookup/pr99116-1.C
+++ b/gcc/testsuite/g++.dg/lookup/pr99116-1.C
@@ -2,7 +2,7 @@
template struct Z {
- friend struct T; // { dg-error "shadows template parameter" }
+ friend struct T; // { dg-bogus "shadows template parameter" }
};
struct Y {
diff --git a/gcc/testsuite/g++.dg/template/friend84.C
b/gcc/testsuite/g++.dg/template/friend84.C
new file mode 100644
index ..64ea41a552ba
--- /dev/null
+++ b/gcc/testsuite/g++.dg/template/friend84.C
@@ -0,0 +1,26 @@
+// PR c++/118255
+// { dg-do "compile" }
+
+// The PR's case, that used to error out.
+template
+struct S {
+ friend class non_template; // { dg-bogus "shadows template parameter" }
+};
+
+class non_template {};
+S<0> s;
+
+// We already accepted cases where the friend is already declared.
+template
+struct T {
+ friend class non_template;
+};
+T<0> t;
+
+// We should reject (re)declarations.
+template
+struct U {
+ class non_template {}; // { dg-error "shadows template parameter" }
+ void non_template () {} // { dg-error "shadows template parameter" }
+};
+U<0> u;
[gcc r15-7033] i386/testsuite: Fix gcc.target/i386/pr118067*.c tests
https://gcc.gnu.org/g:7026436fb67854c7c83f0672ed0271c34d6e3d50
commit r15-7033-g7026436fb67854c7c83f0672ed0271c34d6e3d50
Author: Uros Bizjak
Date: Sun Jan 19 20:23:20 2025 +0100
i386/testsuite: Fix gcc.target/i386/pr118067*.c tests
These tests use int128 type, so require target int128 instead of ! ia32.
Also, use -mtune= instead of deprecated -mcpu= to avoid compiler warning.
PR rtl-optimization/118067
gcc/testsuite/ChangeLog:
* gcc.target/i386/pr118067.c (dg-compile): Use target int128.
* gcc.target/i386/pr118067-2.c (dg-compile): Ditto.
(dg-options): Use -mtune= instead of deprecated -mcpu= option.
Diff:
---
gcc/testsuite/gcc.target/i386/pr118067-2.c | 4 ++--
gcc/testsuite/gcc.target/i386/pr118067.c | 2 +-
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/gcc/testsuite/gcc.target/i386/pr118067-2.c
b/gcc/testsuite/gcc.target/i386/pr118067-2.c
index 831871db0b43..24f6e6f430dd 100644
--- a/gcc/testsuite/gcc.target/i386/pr118067-2.c
+++ b/gcc/testsuite/gcc.target/i386/pr118067-2.c
@@ -1,5 +1,5 @@
-/* { dg-do compile { target { ! ia32 } } } */
-/* { dg-options "-O -fno-split-wide-types -mavx512f -mcpu=k8" } */
+/* { dg-do compile { target int128 } } */
+/* { dg-options "-O -fno-split-wide-types -mavx512f -mtune=k8" } */
typedef unsigned short U __attribute__((__vector_size__(64)));
typedef int V __attribute__((__vector_size__(64)));
diff --git a/gcc/testsuite/gcc.target/i386/pr118067.c
b/gcc/testsuite/gcc.target/i386/pr118067.c
index 7a7f072a5d8a..ca9f5ddf50e8 100644
--- a/gcc/testsuite/gcc.target/i386/pr118067.c
+++ b/gcc/testsuite/gcc.target/i386/pr118067.c
@@ -1,4 +1,4 @@
-/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-do compile { target int128 } } */
/* { dg-options "-O -fno-split-wide-types -mavx512f" } */
typedef unsigned short U __attribute__((__vector_size__(64)));
[gcc r14-11227] i386: Disable SImode/DImode moves from/to mask regs without avx512bw [PR118067]
https://gcc.gnu.org/g:94338cdf59531edb9ac944011c95d777b113ae93
commit r14-11227-g94338cdf59531edb9ac944011c95d777b113ae93
Author: Uros Bizjak
Date: Fri Dec 20 16:16:15 2024 +0100
i386: Disable SImode/DImode moves from/to mask regs without avx512bw
[PR118067]
SImode and DImode moves from/to mask registers are valid only with AVX512BW,
so mark relevant alternatives in *movsi_internal and *movdi_internal as
such.
Even with the patch, the testcase still fails, but now with:
pr118067.c: In function ‘foo’:
pr118067.c:13:1: internal compiler error: maximum number of generated
reload insns per insn achieved (90)
13 | }
| ^
0x2c3b581 internal_error(char const*, ...)
../../git/gcc/gcc/diagnostic-global-context.cc:517
0xb68938 lra_constraints(bool)
../../git/gcc/gcc/lra-constraints.cc:5411
0xb51a0d lra(_IO_FILE*, int)
../../git/gcc/gcc/lra.cc:2449
0xaf9f4d do_reload
../../git/gcc/gcc/ira.cc:5977
0xafa462 execute
../../git/gcc/gcc/ira.cc:6165
PR target/118067
gcc/ChangeLog:
* config/i386/i386.md (*movdi_internal):
Disable alternatives from/to mask registers without AVX512BW.
(*movsi_internal): Ditto.
(cherry picked from commit 219ddae16f9d724baeff86934f8981aa5ef7b95f)
Diff:
---
gcc/config/i386/i386.md | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index a72f6687296e..adeb7cc54b2e 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -2485,7 +2485,7 @@
[(set (match_operand:DI 0 "nonimmediate_operand"
"=r ,o ,r,r ,r,m ,*y,*y,?*y,?m,?r,?*y,?Yv,?v,?v,m
,m,?jc,?*Yd,?r,?v,?*y,?*x,*k,*k ,*r,*m,*k")
(match_operand:DI 1 "general_operand"
-"riFo,riF,Z,rem,i,re,C ,*y,Bk ,*y,*y,r ,C ,?v,Bk,?v,v,*Yd,jc ,?v,r ,*x
,*y ,*r,*kBk,*k,*k,CBC"))]
+"riFo,riF,Z,rem,i,re,C ,*y,Bk ,*y,*y,r ,C ,?v,Bk,?v,v,*Yd,jc ,?v,r ,*x
,*y ,*r,*kBk,*k,*k,CBC"))]
"!(MEM_P (operands[0]) && MEM_P (operands[1]))
&& ix86_hardreg_mov_ok (operands[0], operands[1])"
{
@@ -2547,12 +2547,16 @@
[(set (attr "isa")
(cond [(eq_attr "alternative" "0,1,17,18")
(const_string "nox64")
- (eq_attr "alternative" "2,3,4,5,10,11,23,25")
+ (eq_attr "alternative" "2,3,4,5,10,11")
(const_string "x64")
(eq_attr "alternative" "19,20")
(const_string "x64_sse2")
+ (eq_attr "alternative" "23,25")
+ (const_string "x64_avx512bw")
(eq_attr "alternative" "21,22")
(const_string "sse2")
+ (eq_attr "alternative" "24,26,27")
+ (const_string "avx512bw")
]
(const_string "*")))
(set (attr "type")
@@ -2721,7 +2725,7 @@
[(set (match_operand:SI 0 "nonimmediate_operand"
"=r,m ,*y,*y,?*y,?m,?r,?*y,?Yv,?v,?v,m ,?r,?v,*k,*k ,*rm,*k")
(match_operand:SI 1 "general_operand"
-"g ,re,C ,*y,Bk ,*y,*y,r ,C ,?v,Bk,?v,?v,r ,*r,*kBk,*k ,CBC"))]
+"g ,re,C ,*y,Bk ,*y,*y,r ,C ,?v,Bk,?v,?v,r ,*r,*kBk,*k ,CBC"))]
"!(MEM_P (operands[0]) && MEM_P (operands[1]))
&& ix86_hardreg_mov_ok (operands[0], operands[1])"
{
@@ -2775,6 +2779,8 @@
[(set (attr "isa")
(cond [(eq_attr "alternative" "12,13")
(const_string "sse2")
+ (eq_attr "alternative" "14,15,16,17")
+ (const_string "avx512bw")
]
(const_string "*")))
(set (attr "type")
[gcc r14-11228] i386: Reorder *movdi_internal ISA attribute by ascending alternative index
https://gcc.gnu.org/g:9a1daeb9cd5fb9093c031af85d9efa59ea5cd61a commit r14-11228-g9a1daeb9cd5fb9093c031af85d9efa59ea5cd61a Author: Uros Bizjak Date: Sun Jan 19 22:29:21 2025 +0100 i386: Reorder *movdi_internal ISA attribute by ascending alternative index Reorder ISA attribute by ascending alternative index. No functional change. gcc/ChangeLog: * config/i386/i386.md (*movdi_internal): Reorder ISA attribute by ascending alternative index. (cherry picked from commit 9d4b1e3772547c8c836638d09fc9a84c3c73e277) Diff: --- gcc/config/i386/i386.md | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index adeb7cc54b2e..a7508d47d9b1 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -2551,10 +2551,10 @@ (const_string "x64") (eq_attr "alternative" "19,20") (const_string "x64_sse2") - (eq_attr "alternative" "23,25") - (const_string "x64_avx512bw") (eq_attr "alternative" "21,22") (const_string "sse2") + (eq_attr "alternative" "23,25") + (const_string "x64_avx512bw") (eq_attr "alternative" "24,26,27") (const_string "avx512bw") ]
[gcc r15-7034] i386: Reorder *movdi_internal ISA attribute by ascending alternative index
https://gcc.gnu.org/g:9d4b1e3772547c8c836638d09fc9a84c3c73e277 commit r15-7034-g9d4b1e3772547c8c836638d09fc9a84c3c73e277 Author: Uros Bizjak Date: Sun Jan 19 22:29:21 2025 +0100 i386: Reorder *movdi_internal ISA attribute by ascending alternative index Reorder ISA attribute by ascending alternative index. No functional change. gcc/ChangeLog: * config/i386/i386.md (*movdi_internal): Reorder ISA attribute by ascending alternative index. Diff: --- gcc/config/i386/i386.md | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 362b0ddcf40e..5fbd0848df5b 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -2646,10 +2646,10 @@ (const_string "x64") (eq_attr "alternative" "19,20") (const_string "x64_sse2") - (eq_attr "alternative" "23,25") - (const_string "x64_avx512bw") (eq_attr "alternative" "21,22") (const_string "sse2") + (eq_attr "alternative" "23,25") + (const_string "x64_avx512bw") (eq_attr "alternative" "24,26,27") (const_string "avx512bw") ]
[gcc r15-7036] i386: Fix wrong insn generated by shld/shrd ndd split [PR118510]
https://gcc.gnu.org/g:af4fb245e12f2dd8e2c32167c9acfaceb4b6af6a
commit r15-7036-gaf4fb245e12f2dd8e2c32167c9acfaceb4b6af6a
Author: Hongyu Wang
Date: Fri Jan 17 09:04:17 2025 +0800
i386: Fix wrong insn generated by shld/shrd ndd split [PR118510]
For shld/shrd_ndd_2 insn, the spiltter outputs wrong pattern that
mixed parallel for clobber and set. Use register_operand as dest
and ajdust output template to fix.
gcc/ChangeLog:
PR target/118510
* config/i386/i386.md (*x86_64_shld_ndd_2): Use register_operand
for operand[0] and adjust the output template to directly
generate ndd form shld pattern.
(*x86_shld_ndd_2): Likewise.
(*x86_64_shrd_ndd_2): Likewise.
(*x86_shrd_ndd_2): Likewise.
gcc/testsuite/ChangeLog:
PR target/118510
* gcc.target/i386/pr118510.c: New test.
Diff:
---
gcc/config/i386/i386.md | 44 +---
gcc/testsuite/gcc.target/i386/pr118510.c | 14 ++
2 files changed, 26 insertions(+), 32 deletions(-)
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 5fbd0848df5b..c977e86b72e8 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -15596,7 +15596,7 @@
(clobber (reg:CC FLAGS_REG))])])
(define_insn_and_split "*x86_64_shld_ndd_2"
- [(set (match_operand:DI 0 "nonimmediate_operand")
+ [(set (match_operand:DI 0 "register_operand")
(ior:DI (ashift:DI (match_operand:DI 1 "nonimmediate_operand")
(match_operand:QI 3 "nonmemory_operand"))
(lshiftrt:DI (match_operand:DI 2 "register_operand")
@@ -15606,7 +15606,7 @@
&& ix86_pre_reload_split ()"
"#"
"&& 1"
- [(parallel [(set (match_dup 4)
+ [(parallel [(set (match_dup 0)
(ior:DI (ashift:DI (match_dup 1)
(and:QI (match_dup 3) (const_int 63)))
(subreg:DI
@@ -15615,12 +15615,7 @@
(minus:QI (const_int 64)
(and:QI (match_dup 3)
(const_int 63 0)))
- (clobber (reg:CC FLAGS_REG))
- (set (match_dup 0) (match_dup 4))])]
-{
- operands[4] = gen_reg_rtx (DImode);
- emit_move_insn (operands[4], operands[0]);
-})
+ (clobber (reg:CC FLAGS_REG))])])
(define_insn "x86_shld"
[(set (match_operand:SI 0 "nonimmediate_operand" "+r*m")
@@ -15832,7 +15827,7 @@
(clobber (reg:CC FLAGS_REG))])])
(define_insn_and_split "*x86_shld_ndd_2"
- [(set (match_operand:SI 0 "nonimmediate_operand")
+ [(set (match_operand:SI 0 "register_operand")
(ior:SI (ashift:SI (match_operand:SI 1 "nonimmediate_operand")
(match_operand:QI 3 "nonmemory_operand"))
(lshiftrt:SI (match_operand:SI 2 "register_operand")
@@ -15842,7 +15837,7 @@
&& ix86_pre_reload_split ()"
"#"
"&& 1"
- [(parallel [(set (match_dup 4)
+ [(parallel [(set (match_dup 0)
(ior:SI (ashift:SI (match_dup 1)
(and:QI (match_dup 3) (const_int 31)))
(subreg:SI
@@ -15851,12 +15846,7 @@
(minus:QI (const_int 32)
(and:QI (match_dup 3)
(const_int 31 0)))
- (clobber (reg:CC FLAGS_REG))
- (set (match_dup 0) (match_dup 4))])]
-{
- operands[4] = gen_reg_rtx (SImode);
- emit_move_insn (operands[4], operands[0]);
-})
+ (clobber (reg:CC FLAGS_REG))])])
(define_expand "@x86_shift_adj_1"
[(set (reg:CCZ FLAGS_REG)
@@ -16991,7 +16981,7 @@
(clobber (reg:CC FLAGS_REG))])])
(define_insn_and_split "*x86_64_shrd_ndd_2"
- [(set (match_operand:DI 0 "nonimmediate_operand")
+ [(set (match_operand:DI 0 "register_operand")
(ior:DI (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand")
(match_operand:QI 3 "nonmemory_operand"))
(ashift:DI (match_operand:DI 2 "register_operand")
@@ -17001,7 +16991,7 @@
&& ix86_pre_reload_split ()"
"#"
"&& 1"
- [(parallel [(set (match_dup 4)
+ [(parallel [(set (match_dup 0)
(ior:DI (lshiftrt:DI (match_dup 1)
(and:QI (match_dup 3) (const_int 63)))
(subreg:DI
@@ -17010,12 +17000,7 @@
(minus:QI (const_int 64)
(and:QI (match_dup 3)
(const_int 63 0)))
- (clobber (reg:CC FLAGS_REG))
- (set (match_dup 0) (match_dup 4))])]
-{
- operands[4] = gen_reg_rtx (DImode);
- emit_move_insn (operands[4], operands[0]);
-})
+ (cl
[gcc r15-7037] RISC-V: Add sifive_vector.h
https://gcc.gnu.org/g:43a6001ff58d1e0da791b5f7f4c51aa2ed1e4493
commit r15-7037-g43a6001ff58d1e0da791b5f7f4c51aa2ed1e4493
Author: Kito Cheng
Date: Wed Jan 15 16:13:05 2025 +0800
RISC-V: Add sifive_vector.h
sifive_vector.h is a vendor specfic header, it should include before
using sifive vector intrinsic, it's just include riscv_vector.h for now,
we will separate the implementation by adding new pragma in future.
gcc/ChangeLog:
* config.gcc (riscv*): Install sifive_vector.h.
* config/riscv/sifive_vector.h: New.
Diff:
---
gcc/config.gcc | 2 +-
gcc/config/riscv/sifive_vector.h | 32
2 files changed, 33 insertions(+), 1 deletion(-)
diff --git a/gcc/config.gcc b/gcc/config.gcc
index 87fed8231182..371143e4f8d4 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -555,7 +555,7 @@ riscv*)
extra_objs="${extra_objs} riscv-vector-builtins.o
riscv-vector-builtins-shapes.o riscv-vector-builtins-bases.o
sifive-vector-builtins-bases.o"
extra_objs="${extra_objs} thead.o riscv-target-attr.o riscv-zicfilp.o"
d_target_objs="riscv-d.o"
- extra_headers="riscv_vector.h riscv_crypto.h riscv_bitmanip.h
riscv_th_vector.h riscv_cmo.h"
+ extra_headers="riscv_vector.h riscv_crypto.h riscv_bitmanip.h
riscv_th_vector.h riscv_cmo.h sifive_vector.h"
target_gtfiles="$target_gtfiles
\$(srcdir)/config/riscv/riscv-vector-builtins.cc"
target_gtfiles="$target_gtfiles
\$(srcdir)/config/riscv/riscv-vector-builtins.h"
;;
diff --git a/gcc/config/riscv/sifive_vector.h b/gcc/config/riscv/sifive_vector.h
new file mode 100644
index ..02d314e3b4ab
--- /dev/null
+++ b/gcc/config/riscv/sifive_vector.h
@@ -0,0 +1,32 @@
+/* SiFive Vector Extension intrinsics include file.
+ Copyright (C) 2025 Free Software Foundation, Inc.
+
+ This file is part of GCC.
+
+ GCC is free software; you can redistribute it and/or modify it
+ under the terms of the GNU General Public License as published
+ by the Free Software Foundation; either version 3, or (at your
+ option) any later version.
+
+ GCC is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ Under Section 7 of GPL version 3, you are granted additional
+ permissions described in the GCC Runtime Library Exception, version
+ 3.1, as published by the Free Software Foundation.
+
+ You should have received a copy of the GNU General Public License and
+ a copy of the GCC Runtime Library Exception along with this program;
+ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
+
