[gcc r14-10829] match.pd: Further fma negation fixes [PR116891]
https://gcc.gnu.org/g:6603ec4d113dba8dc286140cb440a89dcb411a6e
commit r14-10829-g6603ec4d113dba8dc286140cb440a89dcb411a6e
Author: Jakub Jelinek
Date: Tue Oct 15 19:38:46 2024 +0200
match.pd: Further fma negation fixes [PR116891]
On Mon, Oct 14, 2024 at 08:53:29AM +0200, Jakub Jelinek wrote:
> > PR middle-end/116891
> > * match.pd ((negate (IFN_FNMS@3 @0 @1 @2)) -> (IFN_FMA @0 @1 @2)):
> > Only enable for !HONOR_SIGN_DEPENDENT_ROUNDING.
>
> Guess it would be nice to have a testcase which FAILs without the patch
and
> PASSes with it, but it can be added later.
I've added such a testcase now, and additionally found the fix only fixed
one of the 4 problematic similar cases.
Here is a patch which fixes the others too and adds the testcases.
fma-pr116891.c FAILed without your patch, FAILs with your patch too (but
only due to the bar/baz/qux checks) and PASSes with the patch.
2024-10-15 Jakub Jelinek
PR middle-end/116891
* match.pd ((negate (fmas@3 @0 @1 @2)) -> (IFN_FNMS @0 @1 @2)):
Only enable for !HONOR_SIGN_DEPENDENT_ROUNDING.
((negate (IFN_FMS@3 @0 @1 @2)) -> (IFN_FNMA @0 @1 @2)): Likewise.
((negate (IFN_FNMA@3 @0 @1 @2)) -> (IFN_FMS @0 @1 @2)): Likewise.
* gcc.dg/pr116891.c: New test.
* gcc.target/i386/fma-pr116891.c: New test.
(cherry picked from commit 4366f0c7e296ea0d7279343c9b0a1d597588a1da)
Diff:
---
gcc/match.pd | 6 ++--
gcc/testsuite/gcc.dg/pr116891.c | 47
gcc/testsuite/gcc.target/i386/fma-pr116891.c | 19 +++
3 files changed, 69 insertions(+), 3 deletions(-)
diff --git a/gcc/match.pd b/gcc/match.pd
index 449a56c43b36..f16fdd2d7760 100644
--- a/gcc/match.pd
+++ b/gcc/match.pd
@@ -8668,7 +8668,7 @@ DEFINE_INT_AND_FLOAT_ROUND_FN (RINT)
(IFN_FNMS @0 @1 @2))
(simplify
(negate (fmas@3 @0 @1 @2))
- (if (single_use (@3))
+ (if (!HONOR_SIGN_DEPENDENT_ROUNDING (type) && single_use (@3))
(IFN_FNMS @0 @1 @2
(simplify
@@ -8682,7 +8682,7 @@ DEFINE_INT_AND_FLOAT_ROUND_FN (RINT)
(IFN_FNMA @0 @1 @2))
(simplify
(negate (IFN_FMS@3 @0 @1 @2))
- (if (single_use (@3))
+ (if (!HONOR_SIGN_DEPENDENT_ROUNDING (type) && single_use (@3))
(IFN_FNMA @0 @1 @2)))
(simplify
@@ -8696,7 +8696,7 @@ DEFINE_INT_AND_FLOAT_ROUND_FN (RINT)
(IFN_FMS @0 @1 @2))
(simplify
(negate (IFN_FNMA@3 @0 @1 @2))
- (if (single_use (@3))
+ (if (!HONOR_SIGN_DEPENDENT_ROUNDING (type) && single_use (@3))
(IFN_FMS @0 @1 @2)))
(simplify
diff --git a/gcc/testsuite/gcc.dg/pr116891.c b/gcc/testsuite/gcc.dg/pr116891.c
new file mode 100644
index ..446e5ec5a4aa
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/pr116891.c
@@ -0,0 +1,47 @@
+/* PR middle-end/116891 */
+/* { dg-do run } */
+/* { dg-require-effective-target fenv } */
+/* { dg-require-effective-target hard_float } */
+/* { dg-require-effective-target c99_runtime } */
+/* { dg-options "-O2 -frounding-math" } */
+
+#include
+
+__attribute__((noipa)) double
+foo (double x, double y, double z)
+{
+ return -__builtin_fma (-x, y, -z);
+}
+
+__attribute__((noipa)) double
+bar (double x, double y, double z)
+{
+ return -__builtin_fma (-x, y, z);
+}
+
+__attribute__((noipa)) double
+baz (double x, double y, double z)
+{
+ return -__builtin_fma (x, y, -z);
+}
+
+__attribute__((noipa)) double
+qux (double x, double y, double z)
+{
+ return -__builtin_fma (x, y, z);
+}
+
+int
+main ()
+{
+#if defined (FE_DOWNWARD) && __DBL_MANT_DIG__ == 53 && __DBL_MAX_EXP__ == 1024
+ fesetround (FE_DOWNWARD);
+ double a = foo (-0x1.p256, 0x1.p256, 0x1.p-256);
+ if (a != -__builtin_nextafter (0x1p256 * 0x1p256, 0.))
+__builtin_abort ();
+ if (a != bar (-0x1.p256, 0x1.p256, -0x1.p-256)
+ || a != baz (0x1.p256, 0x1.p256, 0x1.p-256)
+ || a != qux (0x1.p256, 0x1.p256, -0x1.p-256))
+__builtin_abort ();
+#endif
+}
diff --git a/gcc/testsuite/gcc.target/i386/fma-pr116891.c
b/gcc/testsuite/gcc.target/i386/fma-pr116891.c
new file mode 100644
index ..34689f44c419
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/fma-pr116891.c
@@ -0,0 +1,19 @@
+/* PR middle-end/116891 */
+/* { dg-do run } */
+/* { dg-require-effective-target fenv } */
+/* { dg-require-effective-target hard_float } */
+/* { dg-require-effective-target c99_runtime } */
+/* { dg-require-effective-target fma } */
+/* { dg-options "-O2 -mfma -frounding-math" } */
+
+#include
+#include "fma-check.h"
+
+#define main() do_main ()
+#include "../../gcc.dg/pr116891.c"
+
+static void
+fma_test (void)
+{
+ do_main ();
+}
[gcc r14-10828] middle-end/116891 - fix (negate (IFN_FNMS@3 @0 @1 @2)) -> (IFN_FMA @0 @1 @2)
https://gcc.gnu.org/g:ffce44e8be1fda467ea7aea02f40c22d03fdd206 commit r14-10828-gffce44e8be1fda467ea7aea02f40c22d03fdd206 Author: Richard Biener Date: Mon Oct 14 08:11:22 2024 +0200 middle-end/116891 - fix (negate (IFN_FNMS@3 @0 @1 @2)) -> (IFN_FMA @0 @1 @2) Transforming -fma (-a, b, -c) to fma (a, b, c) is only valid when not rounding towards -inf or +inf as the sign of the multiplication changes. PR middle-end/116891 * match.pd ((negate (IFN_FNMS@3 @0 @1 @2)) -> (IFN_FMA @0 @1 @2)): Only enable for !HONOR_SIGN_DEPENDENT_ROUNDING. (cherry picked from commit c53bd48c6920bc1f4039b6682aafbf414a600e47) Diff: --- gcc/match.pd | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gcc/match.pd b/gcc/match.pd index 62edaf1267e3..449a56c43b36 100644 --- a/gcc/match.pd +++ b/gcc/match.pd @@ -8710,7 +8710,7 @@ DEFINE_INT_AND_FLOAT_ROUND_FN (RINT) (IFN_FMA @0 @1 @2)) (simplify (negate (IFN_FNMS@3 @0 @1 @2)) - (if (single_use (@3)) + (if (!HONOR_SIGN_DEPENDENT_ROUNDING (type) && single_use (@3)) (IFN_FMA @0 @1 @2 /* CLZ simplifications. */
[gcc r15-4562] libcpp: Add -Wleading-whitespace= warning
https://gcc.gnu.org/g:d4499a232aa68e2bfa28cb93f6eeafda2d93f2de
commit r15-4562-gd4499a232aa68e2bfa28cb93f6eeafda2d93f2de
Author: Jakub Jelinek
Date: Wed Oct 23 09:58:06 2024 +0200
libcpp: Add -Wleading-whitespace= warning
The following patch on top of the r15-4346 patch adds
-Wleading-whitespace= warning option.
This warning doesn't care how much one actually indents which line
in the source (that is something that can't be easily done in the
preprocessor without doing syntactic analysis), but just simple checks
on what kind of whitespace is used in the indentation.
I think it is still useful to get warnings about such issues early,
while git diagnoses some of it in patches (e.g. the tab after space
case), getting the warnings earlier might help avoiding such issues
sooner.
There are projects which ban use of tabs and require just spaces,
others which require indentation just with horizontal tabs, and finally
projects which want indentation with tabs for multiples of tabstop size
followed by spaces (fewer than tabstop size), like GCC.
For all 3 kinds the warning diagnoses indentation with '\v' or '\f'
characters (unless line contains just whitespace), and for the last one
also cases where a space in the indentation is followed by horizontal
tab or where there are N or more consecutive spaces in the indentation
(for -ftabstop=N).
BTW, for additional testing I've enabled the warnings (without -Werror
for them) in stage3. There are many warnings (both trailing and leading
whitespace), some of them something that can be easily fixed in the headers
or source files, but others with whitespace issues in generated sources,
so if we enable the warnings, either we'd need to adjust the generators
or disable the warnings in (some of the) generated files.
2024-10-23 Jakub Jelinek
libcpp/
* include/cpplib.h (struct cpp_options): Add
cpp_warn_leading_whitespace and cpp_tabstop members.
(enum cpp_warning_reason): Add CPP_W_LEADING_WHITESPACE.
* internal.h (struct _cpp_line_note): Document new
line note kinds.
* init.cc (cpp_create_reader): Set cpp_tabstop to 8.
* lex.cc (find_leading_whitespace_issues): New function.
(_cpp_clean_line): Use it.
(_cpp_process_line_notes): Handle 'L', 'S' and 'T' line notes.
(lex_raw_string): Clear type on 'L', 'S' and 'T' line notes
inside of raw string literals.
gcc/
* doc/invoke.texi (Wleading-whitespace=): Document.
gcc/c-family/
* c.opt (Wleading-whitespace=): New option.
* c-opts.cc (c_common_post_options): Set cpp_opts->cpp_tabstop
to global_dc->m_tabstop.
gcc/testsuite/
* c-c++-common/cpp/Wleading-whitespace-1.c: New test.
* c-c++-common/cpp/Wleading-whitespace-2.c: New test.
* c-c++-common/cpp/Wleading-whitespace-3.c: New test.
* c-c++-common/cpp/Wleading-whitespace-4.c: New test.
Diff:
---
gcc/c-family/c-opts.cc | 2 +
gcc/c-family/c.opt | 19
gcc/doc/invoke.texi| 25 -
.../c-c++-common/cpp/Wleading-whitespace-1.c | 59 +++
.../c-c++-common/cpp/Wleading-whitespace-2.c | 60
.../c-c++-common/cpp/Wleading-whitespace-3.c | 64
.../c-c++-common/cpp/Wleading-whitespace-4.c | 41
libcpp/include/cpplib.h| 7 ++
libcpp/init.cc | 1 +
libcpp/internal.h | 3 +-
libcpp/lex.cc | 109 -
11 files changed, 387 insertions(+), 3 deletions(-)
diff --git a/gcc/c-family/c-opts.cc b/gcc/c-family/c-opts.cc
index afb963de0619..6be65fb2f734 100644
--- a/gcc/c-family/c-opts.cc
+++ b/gcc/c-family/c-opts.cc
@@ -1147,6 +1147,8 @@ c_common_post_options (const char **pfilename)
flag_char8_t = (cxx_dialect >= cxx20) || flag_isoc23;
cpp_opts->unsigned_utf8char = flag_char8_t ? 1 : cpp_opts->unsigned_char;
+ cpp_opts->cpp_tabstop = global_dc->m_tabstop;
+
if (flag_extern_tls_init)
{
if (!TARGET_SUPPORTS_ALIASES || !SUPPORTS_WEAK)
diff --git a/gcc/c-family/c.opt b/gcc/c-family/c.opt
index d5608ec363cf..af79e4f726b7 100644
--- a/gcc/c-family/c.opt
+++ b/gcc/c-family/c.opt
@@ -928,6 +928,25 @@ Wjump-misses-init
C ObjC Var(warn_jump_misses_init) Warning LangEnabledby(C ObjC,Wc++-compat)
Warn when a jump misses a variable initialization.
+Enum
+Name(warn_leading_whitespace_kind) Type(int) UnknownError(argument %qs to
%<-Wleading-whitespace=%> not recognized)
+
+EnumValue
+Enum(warn_leading_whitespace_kind) String(none) Value(0)
+
+EnumValue
+Enum(warn_leading_whitespace_kind) S
[gcc r15-4563] c-family: Regenerate c.opt.urls
https://gcc.gnu.org/g:89c92804ea307ec807cc74c1cff4d3503452587a commit r15-4563-g89c92804ea307ec807cc74c1cff4d3503452587a Author: Jakub Jelinek Date: Wed Oct 23 10:18:46 2024 +0200 c-family: Regenerate c.opt.urls Forgot to regenerate urls after -Wleading-whitespace addition. 2024-10-23 Jakub Jelinek * c.opt.urls: Regenerate. Diff: --- gcc/c-family/c.opt.urls | 3 +++ 1 file changed, 3 insertions(+) diff --git a/gcc/c-family/c.opt.urls b/gcc/c-family/c.opt.urls index d045af14c3f0..1fe939856df6 100644 --- a/gcc/c-family/c.opt.urls +++ b/gcc/c-family/c.opt.urls @@ -490,6 +490,9 @@ UrlSuffix(gcc/Warning-Options.html#index-Winvalid-utf8) Wjump-misses-init UrlSuffix(gcc/Warning-Options.html#index-Wjump-misses-init) +Wleading-whitespace= +UrlSuffix(gcc/Warning-Options.html#index-Wleading-whitespace_003d) + Wliteral-suffix UrlSuffix(gcc/C_002b_002b-Dialect-Options.html#index-Wliteral-suffix)
[gcc r15-4564] tree-sra: Avoid SRAing arguments to a function returning_twice (PR 117142)
https://gcc.gnu.org/g:29d8f1f0b7ad3c69b3bdb130325300d5f73aa784
commit r15-4564-g29d8f1f0b7ad3c69b3bdb130325300d5f73aa784
Author: Martin Jambor
Date: Wed Oct 23 11:30:32 2024 +0200
tree-sra: Avoid SRAing arguments to a function returning_twice (PR 117142)
PR 117142 shows that the current SRA probably never worked reliably
with arguments passed to a function returning twice, because it then
creates statements before the call which however needs to be at the
beginning of a basic block.
While it should be possible to make at least the case of passing
arguments by value work with SRA (the statements would need to be put
just on the non-abnormal edges leading to the BB), this would mean
large surgery of function sra_modify_expr and I guess the time would
better be spent re-organizing the whole pass.
gcc/ChangeLog:
2024-10-21 Martin Jambor
PR tree-optimization/117142
* tree-sra.cc (build_access_from_call_arg): Disqualify any
candidate passed to a function returning twice.
gcc/testsuite/ChangeLog:
2024-10-21 Martin Jambor
PR tree-optimization/117142
* gcc.dg/tree-ssa/pr117142.c: New test.
Diff:
---
gcc/testsuite/gcc.dg/tree-ssa/pr117142.c | 14 ++
gcc/tree-sra.cc | 9 +
2 files changed, 23 insertions(+)
diff --git a/gcc/testsuite/gcc.dg/tree-ssa/pr117142.c
b/gcc/testsuite/gcc.dg/tree-ssa/pr117142.c
new file mode 100644
index ..fc62c1e58f2e
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/tree-ssa/pr117142.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-O1" } */
+
+struct a {
+ int b;
+};
+void c(int, int);
+void __attribute__((returns_twice))
+bar1(struct a);
+void bar(struct a) {
+ struct a d;
+ bar1(d);
+ c(d.b, d.b);
+}
diff --git a/gcc/tree-sra.cc b/gcc/tree-sra.cc
index 64e2f007d680..c0915dce5c4a 100644
--- a/gcc/tree-sra.cc
+++ b/gcc/tree-sra.cc
@@ -1397,6 +1397,15 @@ static bool
build_access_from_call_arg (tree expr, gimple *stmt, bool can_be_returned,
enum out_edge_check *oe_check)
{
+ if (gimple_call_flags (stmt) & ECF_RETURNS_TWICE)
+{
+ tree base = expr;
+ if (TREE_CODE (expr) == ADDR_EXPR)
+ base = get_base_address (TREE_OPERAND (expr, 0));
+ disqualify_base_of_expr (base, "Passed to a returns_twice call.");
+ return false;
+}
+
if (TREE_CODE (expr) == ADDR_EXPR)
{
tree base = get_base_address (TREE_OPERAND (expr, 0));
[gcc r15-4565] Fortran: Minor follow-up cleanup to error.cc
https://gcc.gnu.org/g:0ecc45a88d772268a3bd83af02759857da0826d4
commit r15-4565-g0ecc45a88d772268a3bd83af02759857da0826d4
Author: Tobias Burnus
Date: Wed Oct 23 12:25:00 2024 +0200
Fortran: Minor follow-up cleanup to error.cc
Follow up to r15-4268-g459c6018d2308d, which removed dead code,
but missing that terminal_width was only set but not used.
gcc/fortran/ChangeLog:
* error.cc (terminal_width, gfc_get_terminal_width): Remove.
(gfc_error_init_1): Do not call one to set the other.
Diff:
---
gcc/fortran/error.cc | 12
1 file changed, 12 deletions(-)
diff --git a/gcc/fortran/error.cc b/gcc/fortran/error.cc
index 4e60b148a34c..b27cbede1645 100644
--- a/gcc/fortran/error.cc
+++ b/gcc/fortran/error.cc
@@ -39,8 +39,6 @@ static int suppress_errors = 0;
static bool warnings_not_errors = false;
-static int terminal_width;
-
/* True if the error/warnings should be buffered. */
static bool buffered_p;
@@ -141,21 +139,11 @@ gfc_query_suppress_errors (void)
}
-/* Determine terminal width (for trimming source lines in output). */
-
-static int
-gfc_get_terminal_width (void)
-{
- return isatty (STDERR_FILENO) ? get_terminal_width () : INT_MAX;
-}
-
-
/* Per-file error initialization. */
void
gfc_error_init_1 (void)
{
- terminal_width = gfc_get_terminal_width ();
gfc_buffer_error (false);
}
[gcc r14-10830] c-family: Fix up -Wsizeof-pointer-memaccess ICEs [PR117230]
https://gcc.gnu.org/g:20c180cf65e81257d40d6e0f3d798b5ec5364b11
commit r14-10830-g20c180cf65e81257d40d6e0f3d798b5ec5364b11
Author: Jakub Jelinek
Date: Tue Oct 22 20:30:41 2024 +0200
c-family: Fix up -Wsizeof-pointer-memaccess ICEs [PR117230]
In the following testcases, we ICE on all 4 function calls.
The problem is using TYPE_PRECISION on vector types (but guess it
would be similarly problematic on structures/unions/arrays).
The test only differentiates between suggestion what to do, whether
to supply explicit size because sizeof (*p) for
{,{,un}signed }char *p is not very likely what the user want, or
dereferencing the pointer, so I think limiting that suggestion
to integral types is ok.
2024-10-22 Jakub Jelinek
PR c/117230
* c-warn.cc (sizeof_pointer_memaccess_warning): Only compare
TYPE_PRECISION of TREE_TYPE (type) to precision of char if
TREE_TYPE (type) is integral type.
* c-c++-common/Wsizeof-pointer-memaccess5.c: New test.
(cherry picked from commit 5fd1c0c1b6968d55e3f997d67a4c149edf20c012)
Diff:
---
gcc/c-family/c-warn.cc | 20 +--
.../c-c++-common/Wsizeof-pointer-memaccess5.c | 29 ++
2 files changed, 41 insertions(+), 8 deletions(-)
diff --git a/gcc/c-family/c-warn.cc b/gcc/c-family/c-warn.cc
index 8fc0d8a53b35..63c8187c4e5b 100644
--- a/gcc/c-family/c-warn.cc
+++ b/gcc/c-family/c-warn.cc
@@ -944,8 +944,9 @@ sizeof_pointer_memaccess_warning (location_t
*sizeof_arg_loc, tree callee,
"argument to % in %qD call is the same "
"expression as the destination; did you mean to "
"remove the addressof?", callee);
- else if ((TYPE_PRECISION (TREE_TYPE (type))
- == TYPE_PRECISION (char_type_node))
+ else if ((INTEGRAL_TYPE_P (TREE_TYPE (type))
+ && (TYPE_PRECISION (TREE_TYPE (type))
+ == TYPE_PRECISION (char_type_node)))
|| strop)
warning_at (loc, OPT_Wsizeof_pointer_memaccess,
"argument to % in %qD call is the same "
@@ -984,8 +985,9 @@ sizeof_pointer_memaccess_warning (location_t
*sizeof_arg_loc, tree callee,
"argument to % in %qD call is the same "
"expression as the source; did you mean to "
"remove the addressof?", callee);
- else if ((TYPE_PRECISION (TREE_TYPE (type))
- == TYPE_PRECISION (char_type_node))
+ else if ((INTEGRAL_TYPE_P (TREE_TYPE (type))
+ && (TYPE_PRECISION (TREE_TYPE (type))
+ == TYPE_PRECISION (char_type_node)))
|| strop)
warning_at (loc, OPT_Wsizeof_pointer_memaccess,
"argument to % in %qD call is the same "
@@ -1024,8 +1026,9 @@ sizeof_pointer_memaccess_warning (location_t
*sizeof_arg_loc, tree callee,
"argument to % in %qD call is the same "
"expression as the first source; did you mean to "
"remove the addressof?", callee);
- else if ((TYPE_PRECISION (TREE_TYPE (type))
- == TYPE_PRECISION (char_type_node))
+ else if ((INTEGRAL_TYPE_P (TREE_TYPE (type))
+ && (TYPE_PRECISION (TREE_TYPE (type))
+ == TYPE_PRECISION (char_type_node)))
|| strop)
warning_at (loc, OPT_Wsizeof_pointer_memaccess,
"argument to % in %qD call is the same "
@@ -1064,8 +1067,9 @@ sizeof_pointer_memaccess_warning (location_t
*sizeof_arg_loc, tree callee,
"argument to % in %qD call is the same "
"expression as the second source; did you mean to "
"remove the addressof?", callee);
- else if ((TYPE_PRECISION (TREE_TYPE (type))
- == TYPE_PRECISION (char_type_node))
+ else if ((INTEGRAL_TYPE_P (TREE_TYPE (type))
+ && (TYPE_PRECISION (TREE_TYPE (type))
+ == TYPE_PRECISION (char_type_node)))
|| strop)
warning_at (loc, OPT_Wsizeof_pointer_memaccess,
"argument to % in %qD call is the same "
diff --git a/gcc/testsuite/c-c++-common/Wsizeof-pointer-memaccess5.c
b/gcc/testsuite/c-c++-common/Wsizeof-pointer-memaccess5.c
new file mode 100644
index ..aaa7da04a2c3
--- /dev/null
+++ b/gcc/testsuite/c-c++-common/Wsizeof-pointer-memaccess5.c
@@ -0,0 +1,29 @@
+/* PR c/117230 */
+/* { dg-do compile } */
+/* { dg-options "-Wsizeof-pointer-memaccess" } */
+
+typedef int V __attribute__((vector_size (sizeof (int;
+
+void
+foo (V *a, char *b)
+{
+ __builtin_memcpy (b, a, sizeof (a)); /* { dg-warning "argument to
'sizeo
[gcc r14-10831] Fix ICE due to isa mismatch for the builtins.
https://gcc.gnu.org/g:b718f6ec1674c0db30f26c65b7a9215e9388dd6c commit r14-10831-gb718f6ec1674c0db30f26c65b7a9215e9388dd6c Author: liuhongt Date: Tue Oct 22 01:54:40 2024 -0700 Fix ICE due to isa mismatch for the builtins. gcc/ChangeLog: PR target/117240 * config/i386/i386-builtin.def: Add avx/avx512f to vaes ymm/zmm builtins. gcc/testsuite/ChangeLog: * gcc.target/i386/pr117240_avx.c: New test. * gcc.target/i386/pr117240_avx512f.c: New test. (cherry picked from commit 403e361d5aa620e77c9832578b2409a0fdd79d96) Diff: --- gcc/config/i386/i386-builtin.def | 16 gcc/testsuite/gcc.target/i386/pr117240_avx.c | 10 ++ gcc/testsuite/gcc.target/i386/pr117240_avx512f.c | 10 ++ 3 files changed, 28 insertions(+), 8 deletions(-) diff --git a/gcc/config/i386/i386-builtin.def b/gcc/config/i386/i386-builtin.def index ab73e20121aa..fdd9dba6e542 100644 --- a/gcc/config/i386/i386-builtin.def +++ b/gcc/config/i386/i386-builtin.def @@ -2832,17 +2832,17 @@ BDESC (0, OPTION_MASK_ISA2_RDPID, CODE_FOR_rdpid, "__builtin_ia32_rdpid", IX86_B /* VAES. */ BDESC (OPTION_MASK_ISA_AVX512VL, OPTION_MASK_ISA2_VAES, CODE_FOR_vaesdec_v16qi, "__builtin_ia32_vaesdec_v16qi", IX86_BUILTIN_VAESDEC16, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI) -BDESC (0, OPTION_MASK_ISA2_VAES, CODE_FOR_vaesdec_v32qi, "__builtin_ia32_vaesdec_v32qi", IX86_BUILTIN_VAESDEC32, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI) -BDESC (0, OPTION_MASK_ISA2_VAES | OPTION_MASK_ISA2_EVEX512, CODE_FOR_vaesdec_v64qi, "__builtin_ia32_vaesdec_v64qi", IX86_BUILTIN_VAESDEC64, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI) +BDESC (OPTION_MASK_ISA_AVX, OPTION_MASK_ISA2_VAES, CODE_FOR_vaesdec_v32qi, "__builtin_ia32_vaesdec_v32qi", IX86_BUILTIN_VAESDEC32, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI) +BDESC (OPTION_MASK_ISA_AVX512F, OPTION_MASK_ISA2_VAES | OPTION_MASK_ISA2_EVEX512, CODE_FOR_vaesdec_v64qi, "__builtin_ia32_vaesdec_v64qi", IX86_BUILTIN_VAESDEC64, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI) BDESC (OPTION_MASK_ISA_AVX512VL, OPTION_MASK_ISA2_VAES, CODE_FOR_vaesdeclast_v16qi, "__builtin_ia32_vaesdeclast_v16qi", IX86_BUILTIN_VAESDECLAST16, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI) -BDESC (0, OPTION_MASK_ISA2_VAES, CODE_FOR_vaesdeclast_v32qi, "__builtin_ia32_vaesdeclast_v32qi", IX86_BUILTIN_VAESDECLAST32, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI) -BDESC (0, OPTION_MASK_ISA2_VAES | OPTION_MASK_ISA2_EVEX512, CODE_FOR_vaesdeclast_v64qi, "__builtin_ia32_vaesdeclast_v64qi", IX86_BUILTIN_VAESDECLAST64, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI) +BDESC (OPTION_MASK_ISA_AVX, OPTION_MASK_ISA2_VAES, CODE_FOR_vaesdeclast_v32qi, "__builtin_ia32_vaesdeclast_v32qi", IX86_BUILTIN_VAESDECLAST32, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI) +BDESC (OPTION_MASK_ISA_AVX512F, OPTION_MASK_ISA2_VAES | OPTION_MASK_ISA2_EVEX512, CODE_FOR_vaesdeclast_v64qi, "__builtin_ia32_vaesdeclast_v64qi", IX86_BUILTIN_VAESDECLAST64, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI) BDESC (OPTION_MASK_ISA_AVX512VL, OPTION_MASK_ISA2_VAES, CODE_FOR_vaesenc_v16qi, "__builtin_ia32_vaesenc_v16qi", IX86_BUILTIN_VAESENC16, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI) -BDESC (0, OPTION_MASK_ISA2_VAES, CODE_FOR_vaesenc_v32qi, "__builtin_ia32_vaesenc_v32qi", IX86_BUILTIN_VAESENC32, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI) -BDESC (0, OPTION_MASK_ISA2_VAES | OPTION_MASK_ISA2_EVEX512, CODE_FOR_vaesenc_v64qi, "__builtin_ia32_vaesenc_v64qi", IX86_BUILTIN_VAESENC64, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI) +BDESC (OPTION_MASK_ISA_AVX, OPTION_MASK_ISA2_VAES, CODE_FOR_vaesenc_v32qi, "__builtin_ia32_vaesenc_v32qi", IX86_BUILTIN_VAESENC32, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI) +BDESC (OPTION_MASK_ISA_AVX512F, OPTION_MASK_ISA2_VAES | OPTION_MASK_ISA2_EVEX512, CODE_FOR_vaesenc_v64qi, "__builtin_ia32_vaesenc_v64qi", IX86_BUILTIN_VAESENC64, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI) BDESC (OPTION_MASK_ISA_AVX512VL, OPTION_MASK_ISA2_VAES, CODE_FOR_vaesenclast_v16qi, "__builtin_ia32_vaesenclast_v16qi", IX86_BUILTIN_VAESENCLAST16, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI) -BDESC (0, OPTION_MASK_ISA2_VAES, CODE_FOR_vaesenclast_v32qi, "__builtin_ia32_vaesenclast_v32qi", IX86_BUILTIN_VAESENCLAST32, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI) -BDESC (0, OPTION_MASK_ISA2_VAES | OPTION_MASK_ISA2_EVEX512, CODE_FOR_vaesenclast_v64qi, "__builtin_ia32_vaesenclast_v64qi", IX86_BUILTIN_VAESENCLAST64, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI) +BDESC (OPTION_MASK_ISA_AVX, OPTION_MASK_ISA2_VAES, CODE_FOR_vaesenclast_v32qi, "__builtin_ia32_vaesenclast_v32qi", IX86_BUILTIN_VAESENCLAST32, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI) +BDESC (OPTION_MASK_ISA_AVX512F, OPTION_MASK_ISA2_VAES | OPTION_MASK_ISA2_EVEX512, CODE_FOR_vaesenclast_v64qi, "__builtin_ia32_vaesenclast_v64qi", IX86_BUILTIN_VAESENCLAST64, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI) /* BF16 */ BDESC (0, OPTION_MASK_ISA2_AVX512BF16 | OPTION_MASK_ISA2_EVEX512
[gcc r13-9145] Fix ICE due to isa mismatch for the builtins.
https://gcc.gnu.org/g:2452387468423882c0732e0fad3a83e887574ccc commit r13-9145-g2452387468423882c0732e0fad3a83e887574ccc Author: liuhongt Date: Tue Oct 22 01:54:40 2024 -0700 Fix ICE due to isa mismatch for the builtins. gcc/ChangeLog: PR target/117240 * config/i386/i386-builtin.def: Add avx/avx512f to vaes ymm/zmm builtins. gcc/testsuite/ChangeLog: * gcc.target/i386/pr117240_avx.c: New test. * gcc.target/i386/pr117240_avx512f.c: New test. (cherry picked from commit 403e361d5aa620e77c9832578b2409a0fdd79d96) Diff: --- gcc/config/i386/i386-builtin.def | 16 gcc/testsuite/gcc.target/i386/pr117240_avx.c | 10 ++ gcc/testsuite/gcc.target/i386/pr117240_avx512f.c | 10 ++ 3 files changed, 28 insertions(+), 8 deletions(-) diff --git a/gcc/config/i386/i386-builtin.def b/gcc/config/i386/i386-builtin.def index 0037fb34891a..63861a6d8329 100644 --- a/gcc/config/i386/i386-builtin.def +++ b/gcc/config/i386/i386-builtin.def @@ -2802,17 +2802,17 @@ BDESC (0, OPTION_MASK_ISA2_RDPID, CODE_FOR_rdpid, "__builtin_ia32_rdpid", IX86_B /* VAES. */ BDESC (OPTION_MASK_ISA_AVX512VL, OPTION_MASK_ISA2_VAES, CODE_FOR_vaesdec_v16qi, "__builtin_ia32_vaesdec_v16qi", IX86_BUILTIN_VAESDEC16, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI) -BDESC (0, OPTION_MASK_ISA2_VAES, CODE_FOR_vaesdec_v32qi, "__builtin_ia32_vaesdec_v32qi", IX86_BUILTIN_VAESDEC32, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI) -BDESC (0, OPTION_MASK_ISA2_VAES, CODE_FOR_vaesdec_v64qi, "__builtin_ia32_vaesdec_v64qi", IX86_BUILTIN_VAESDEC64, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI) +BDESC (OPTION_MASK_ISA_AVX, OPTION_MASK_ISA2_VAES, CODE_FOR_vaesdec_v32qi, "__builtin_ia32_vaesdec_v32qi", IX86_BUILTIN_VAESDEC32, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI) +BDESC (OPTION_MASK_ISA_AVX512F, OPTION_MASK_ISA2_VAES, CODE_FOR_vaesdec_v64qi, "__builtin_ia32_vaesdec_v64qi", IX86_BUILTIN_VAESDEC64, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI) BDESC (OPTION_MASK_ISA_AVX512VL, OPTION_MASK_ISA2_VAES, CODE_FOR_vaesdeclast_v16qi, "__builtin_ia32_vaesdeclast_v16qi", IX86_BUILTIN_VAESDECLAST16, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI) -BDESC (0, OPTION_MASK_ISA2_VAES, CODE_FOR_vaesdeclast_v32qi, "__builtin_ia32_vaesdeclast_v32qi", IX86_BUILTIN_VAESDECLAST32, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI) -BDESC (0, OPTION_MASK_ISA2_VAES, CODE_FOR_vaesdeclast_v64qi, "__builtin_ia32_vaesdeclast_v64qi", IX86_BUILTIN_VAESDECLAST64, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI) +BDESC (OPTION_MASK_ISA_AVX, OPTION_MASK_ISA2_VAES, CODE_FOR_vaesdeclast_v32qi, "__builtin_ia32_vaesdeclast_v32qi", IX86_BUILTIN_VAESDECLAST32, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI) +BDESC (OPTION_MASK_ISA_AVX512F, OPTION_MASK_ISA2_VAES, CODE_FOR_vaesdeclast_v64qi, "__builtin_ia32_vaesdeclast_v64qi", IX86_BUILTIN_VAESDECLAST64, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI) BDESC (OPTION_MASK_ISA_AVX512VL, OPTION_MASK_ISA2_VAES, CODE_FOR_vaesenc_v16qi, "__builtin_ia32_vaesenc_v16qi", IX86_BUILTIN_VAESENC16, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI) -BDESC (0, OPTION_MASK_ISA2_VAES, CODE_FOR_vaesenc_v32qi, "__builtin_ia32_vaesenc_v32qi", IX86_BUILTIN_VAESENC32, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI) -BDESC (0, OPTION_MASK_ISA2_VAES, CODE_FOR_vaesenc_v64qi, "__builtin_ia32_vaesenc_v64qi", IX86_BUILTIN_VAESENC64, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI) +BDESC (OPTION_MASK_ISA_AVX, OPTION_MASK_ISA2_VAES, CODE_FOR_vaesenc_v32qi, "__builtin_ia32_vaesenc_v32qi", IX86_BUILTIN_VAESENC32, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI) +BDESC (OPTION_MASK_ISA_AVX512F, OPTION_MASK_ISA2_VAES, CODE_FOR_vaesenc_v64qi, "__builtin_ia32_vaesenc_v64qi", IX86_BUILTIN_VAESENC64, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI) BDESC (OPTION_MASK_ISA_AVX512VL, OPTION_MASK_ISA2_VAES, CODE_FOR_vaesenclast_v16qi, "__builtin_ia32_vaesenclast_v16qi", IX86_BUILTIN_VAESENCLAST16, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI) -BDESC (0, OPTION_MASK_ISA2_VAES, CODE_FOR_vaesenclast_v32qi, "__builtin_ia32_vaesenclast_v32qi", IX86_BUILTIN_VAESENCLAST32, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI) -BDESC (0, OPTION_MASK_ISA2_VAES, CODE_FOR_vaesenclast_v64qi, "__builtin_ia32_vaesenclast_v64qi", IX86_BUILTIN_VAESENCLAST64, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI) +BDESC (OPTION_MASK_ISA_AVX, OPTION_MASK_ISA2_VAES, CODE_FOR_vaesenclast_v32qi, "__builtin_ia32_vaesenclast_v32qi", IX86_BUILTIN_VAESENCLAST32, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI) +BDESC (OPTION_MASK_ISA_AVX512F, OPTION_MASK_ISA2_VAES, CODE_FOR_vaesenclast_v64qi, "__builtin_ia32_vaesenclast_v64qi", IX86_BUILTIN_VAESENCLAST64, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI) /* BF16 */ BDESC (0, OPTION_MASK_ISA2_AVX512BF16, CODE_FOR_avx512f_cvtne2ps2bf16_v32bf, "__builtin_ia32_cvtne2ps2bf16_v32bf", IX86_BUILTIN_CVTNE2PS2BF16_V32BF, UNKNOWN, (int) V32BF_FTYPE_V16SF_V16SF) diff --git a/gcc/testsuite/gcc.target/i386/pr117240_avx.c b/gcc/testsuite/gcc.target/i386/pr1
[gcc r15-4566] Fix ICE due to isa mismatch for the builtins.
https://gcc.gnu.org/g:403e361d5aa620e77c9832578b2409a0fdd79d96 commit r15-4566-g403e361d5aa620e77c9832578b2409a0fdd79d96 Author: liuhongt Date: Tue Oct 22 01:54:40 2024 -0700 Fix ICE due to isa mismatch for the builtins. gcc/ChangeLog: PR target/117240 * config/i386/i386-builtin.def: Add avx/avx512f to vaes ymm/zmm builtins. gcc/testsuite/ChangeLog: * gcc.target/i386/pr117240_avx.c: New test. * gcc.target/i386/pr117240_avx512f.c: New test. Diff: --- gcc/config/i386/i386-builtin.def | 16 gcc/testsuite/gcc.target/i386/pr117240_avx.c | 10 ++ gcc/testsuite/gcc.target/i386/pr117240_avx512f.c | 10 ++ 3 files changed, 28 insertions(+), 8 deletions(-) diff --git a/gcc/config/i386/i386-builtin.def b/gcc/config/i386/i386-builtin.def index 151ccf4f252a..1eb631db7109 100644 --- a/gcc/config/i386/i386-builtin.def +++ b/gcc/config/i386/i386-builtin.def @@ -2819,17 +2819,17 @@ BDESC (0, OPTION_MASK_ISA2_RDPID, CODE_FOR_rdpid, "__builtin_ia32_rdpid", IX86_B /* VAES. */ BDESC (OPTION_MASK_ISA_AVX512VL, OPTION_MASK_ISA2_VAES, CODE_FOR_vaesdec_v16qi, "__builtin_ia32_vaesdec_v16qi", IX86_BUILTIN_VAESDEC16, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI) -BDESC (0, OPTION_MASK_ISA2_VAES, CODE_FOR_vaesdec_v32qi, "__builtin_ia32_vaesdec_v32qi", IX86_BUILTIN_VAESDEC32, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI) -BDESC (0, OPTION_MASK_ISA2_VAES | OPTION_MASK_ISA2_EVEX512, CODE_FOR_vaesdec_v64qi, "__builtin_ia32_vaesdec_v64qi", IX86_BUILTIN_VAESDEC64, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI) +BDESC (OPTION_MASK_ISA_AVX, OPTION_MASK_ISA2_VAES, CODE_FOR_vaesdec_v32qi, "__builtin_ia32_vaesdec_v32qi", IX86_BUILTIN_VAESDEC32, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI) +BDESC (OPTION_MASK_ISA_AVX512F, OPTION_MASK_ISA2_VAES | OPTION_MASK_ISA2_EVEX512, CODE_FOR_vaesdec_v64qi, "__builtin_ia32_vaesdec_v64qi", IX86_BUILTIN_VAESDEC64, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI) BDESC (OPTION_MASK_ISA_AVX512VL, OPTION_MASK_ISA2_VAES, CODE_FOR_vaesdeclast_v16qi, "__builtin_ia32_vaesdeclast_v16qi", IX86_BUILTIN_VAESDECLAST16, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI) -BDESC (0, OPTION_MASK_ISA2_VAES, CODE_FOR_vaesdeclast_v32qi, "__builtin_ia32_vaesdeclast_v32qi", IX86_BUILTIN_VAESDECLAST32, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI) -BDESC (0, OPTION_MASK_ISA2_VAES | OPTION_MASK_ISA2_EVEX512, CODE_FOR_vaesdeclast_v64qi, "__builtin_ia32_vaesdeclast_v64qi", IX86_BUILTIN_VAESDECLAST64, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI) +BDESC (OPTION_MASK_ISA_AVX, OPTION_MASK_ISA2_VAES, CODE_FOR_vaesdeclast_v32qi, "__builtin_ia32_vaesdeclast_v32qi", IX86_BUILTIN_VAESDECLAST32, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI) +BDESC (OPTION_MASK_ISA_AVX512F, OPTION_MASK_ISA2_VAES | OPTION_MASK_ISA2_EVEX512, CODE_FOR_vaesdeclast_v64qi, "__builtin_ia32_vaesdeclast_v64qi", IX86_BUILTIN_VAESDECLAST64, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI) BDESC (OPTION_MASK_ISA_AVX512VL, OPTION_MASK_ISA2_VAES, CODE_FOR_vaesenc_v16qi, "__builtin_ia32_vaesenc_v16qi", IX86_BUILTIN_VAESENC16, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI) -BDESC (0, OPTION_MASK_ISA2_VAES, CODE_FOR_vaesenc_v32qi, "__builtin_ia32_vaesenc_v32qi", IX86_BUILTIN_VAESENC32, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI) -BDESC (0, OPTION_MASK_ISA2_VAES | OPTION_MASK_ISA2_EVEX512, CODE_FOR_vaesenc_v64qi, "__builtin_ia32_vaesenc_v64qi", IX86_BUILTIN_VAESENC64, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI) +BDESC (OPTION_MASK_ISA_AVX, OPTION_MASK_ISA2_VAES, CODE_FOR_vaesenc_v32qi, "__builtin_ia32_vaesenc_v32qi", IX86_BUILTIN_VAESENC32, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI) +BDESC (OPTION_MASK_ISA_AVX512F, OPTION_MASK_ISA2_VAES | OPTION_MASK_ISA2_EVEX512, CODE_FOR_vaesenc_v64qi, "__builtin_ia32_vaesenc_v64qi", IX86_BUILTIN_VAESENC64, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI) BDESC (OPTION_MASK_ISA_AVX512VL, OPTION_MASK_ISA2_VAES, CODE_FOR_vaesenclast_v16qi, "__builtin_ia32_vaesenclast_v16qi", IX86_BUILTIN_VAESENCLAST16, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI) -BDESC (0, OPTION_MASK_ISA2_VAES, CODE_FOR_vaesenclast_v32qi, "__builtin_ia32_vaesenclast_v32qi", IX86_BUILTIN_VAESENCLAST32, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI) -BDESC (0, OPTION_MASK_ISA2_VAES | OPTION_MASK_ISA2_EVEX512, CODE_FOR_vaesenclast_v64qi, "__builtin_ia32_vaesenclast_v64qi", IX86_BUILTIN_VAESENCLAST64, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI) +BDESC (OPTION_MASK_ISA_AVX, OPTION_MASK_ISA2_VAES, CODE_FOR_vaesenclast_v32qi, "__builtin_ia32_vaesenclast_v32qi", IX86_BUILTIN_VAESENCLAST32, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI) +BDESC (OPTION_MASK_ISA_AVX512F, OPTION_MASK_ISA2_VAES | OPTION_MASK_ISA2_EVEX512, CODE_FOR_vaesenclast_v64qi, "__builtin_ia32_vaesenclast_v64qi", IX86_BUILTIN_VAESENCLAST64, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI) /* BF16 */ BDESC (0, OPTION_MASK_ISA2_AVX512BF16 | OPTION_MASK_ISA2_EVEX512, CODE_FOR_avx512f_cvtne2ps2bf16_v32bf, "__builtin_ia32_cvtne2ps2bf16_v32bf",
[gcc r15-4578] Implement operator_pointer_diff::fold_range
https://gcc.gnu.org/g:774ad67fba458dd1beaa0f2d3e389aac46ca18b5
commit r15-4578-g774ad67fba458dd1beaa0f2d3e389aac46ca18b5
Author: Andrew MacLeod
Date: Mon Oct 21 16:32:00 2024 -0400
Implement operator_pointer_diff::fold_range
prange has no default fold_range processing like irange does, so each
pointer specific operator needs to implement its own fold routine.
PR tree-optimization/117222
gcc/
* range-op-ptr.cc (operator_pointer_diff::fold_range): New.
(operator_pointer_diff::op1_op2_relation_effect): Remove irange
variant.
(operator_pointer_diff::update_bitmask): Likewise.
gcc/testsuite
* g++.dg/pr117222.C: New.
Diff:
---
gcc/range-op-ptr.cc | 37 -
gcc/testsuite/g++.dg/pr117222.C | 16
2 files changed, 36 insertions(+), 17 deletions(-)
diff --git a/gcc/range-op-ptr.cc b/gcc/range-op-ptr.cc
index 24e206c00cdd..07a551618f98 100644
--- a/gcc/range-op-ptr.cc
+++ b/gcc/range-op-ptr.cc
@@ -567,25 +567,38 @@ pointer_or_operator::wi_fold (irange &r, tree type,
class operator_pointer_diff : public range_operator
{
+ using range_operator::fold_range;
using range_operator::update_bitmask;
using range_operator::op1_op2_relation_effect;
- virtual bool op1_op2_relation_effect (irange &lhs_range,
- tree type,
- const irange &op1_range,
- const irange &op2_range,
- relation_kind rel) const;
+ virtual bool fold_range (irange &r, tree type,
+ const prange &op1,
+ const prange &op2,
+ relation_trio trio) const final override;
virtual bool op1_op2_relation_effect (irange &lhs_range,
tree type,
const prange &op1_range,
const prange &op2_range,
relation_kind rel) const final override;
- void update_bitmask (irange &r, const irange &lh, const irange &rh) const
-{ update_known_bitmask (r, POINTER_DIFF_EXPR, lh, rh); }
void update_bitmask (irange &r,
const prange &lh, const prange &rh) const final override
{ update_known_bitmask (r, POINTER_DIFF_EXPR, lh, rh); }
} op_pointer_diff;
+bool
+operator_pointer_diff::fold_range (irange &r, tree type,
+ const prange &op1,
+ const prange &op2,
+ relation_trio trio) const
+{
+ gcc_checking_assert (r.supports_type_p (type));
+
+ r.set_varying (type);
+ relation_kind rel = trio.op1_op2 ();
+ op1_op2_relation_effect (r, type, op1, op2, rel);
+ update_bitmask (r, op1, op2);
+ return true;
+}
+
bool
operator_pointer_diff::op1_op2_relation_effect (irange &lhs_range, tree type,
const prange &op1_range,
@@ -602,16 +615,6 @@ operator_pointer_diff::op1_op2_relation_effect (irange
&lhs_range, tree type,
return minus_op1_op2_relation_effect (lhs_range, type, op1, op2, rel);
}
-bool
-operator_pointer_diff::op1_op2_relation_effect (irange &lhs_range, tree type,
- const irange &op1_range,
- const irange &op2_range,
- relation_kind rel) const
-{
- return minus_op1_op2_relation_effect (lhs_range, type, op1_range, op2_range,
- rel);
-}
-
bool
operator_identity::fold_range (prange &r, tree type ATTRIBUTE_UNUSED,
const prange &lh ATTRIBUTE_UNUSED,
diff --git a/gcc/testsuite/g++.dg/pr117222.C b/gcc/testsuite/g++.dg/pr117222.C
new file mode 100644
index ..60cf6e30ed54
--- /dev/null
+++ b/gcc/testsuite/g++.dg/pr117222.C
@@ -0,0 +1,16 @@
+// { dg-do compile }
+// { dg-require-effective-target c++11 }
+// { dg-options "-O3 -fdump-tree-evrp" }
+
+#include
+int main()
+{
+std::vector c {1,2,3,0};
+while(c.size() > 0 && c.back() == 0)
+{
+auto sz = c.size() -1;
+c.resize(sz);
+}
+return 0;
+}
+/* { dg-final { scan-tree-dump "Global Exported.*\[-INF, -1\]\[1, +INF\]"
"evrp" } } */
[gcc(refs/users/meissner/heads/work182-sha)] Add potential p-future XVRLD and XVRLDI instructions.
https://gcc.gnu.org/g:2b340357813089fb211cb2fca80c002f111c18d3
commit 2b340357813089fb211cb2fca80c002f111c18d3
Author: Michael Meissner
Date: Wed Oct 23 13:26:49 2024 -0400
Add potential p-future XVRLD and XVRLDI instructions.
2024-10-16 Michael Meissner
gcc/
* config/rs6000/altivec.md (altivec_vrl): Add support for a
possible XVRLD instruction in the future.
(altivec_vrl_immediate): New insns.
* config/rs6000/predicates.md (vector_shift_immediate): New
predicate.
* config/rs6000/rs6000.h (TARGET_XVRLW): New macro.
* config/rs6000/rs6000.md (isa attribute): Add xvrlw.
(enabled attribute): Add support for xvrlw.
Diff:
---
gcc/config/rs6000/altivec.md| 35 +++
gcc/config/rs6000/predicates.md | 26 ++
gcc/config/rs6000/rs6000.h | 3 +++
gcc/config/rs6000/rs6000.md | 6 +-
4 files changed, 65 insertions(+), 5 deletions(-)
diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
index 00dad4b91f1c..d4ee50322ca1 100644
--- a/gcc/config/rs6000/altivec.md
+++ b/gcc/config/rs6000/altivec.md
@@ -1983,12 +1983,39 @@
}
[(set_attr "type" "vecperm")])
+;; -mcpu=future adds a vector rotate left word variant. There is no vector
+;; byte/half-word/double-word/quad-word rotate left. This insn occurs before
+;; altivec_vrl and will match for -mcpu=future, while other cpus will
+;; match the generic insn.
+;; However for testing, allow other xvrl variants. In particular, XVRLD for
+;; the sha3 tests for multibuf/singlebuf.
(define_insn "altivec_vrl"
- [(set (match_operand:VI2 0 "register_operand" "=v")
-(rotate:VI2 (match_operand:VI2 1 "register_operand" "v")
- (match_operand:VI2 2 "register_operand" "v")))]
+ [(set (match_operand:VI2 0 "register_operand" "=v,wa")
+(rotate:VI2 (match_operand:VI2 1 "register_operand" "v,wa")
+ (match_operand:VI2 2 "register_operand" "v,wa")))]
""
- "vrl %0,%1,%2"
+ "@
+ vrl %0,%1,%2
+ xvrl %x0,%x1,%x2"
+ [(set_attr "type" "vecsimple")
+ (set_attr "isa" "*,xvrlw")])
+
+(define_insn "*altivec_vrl_immediate"
+ [(set (match_operand:VI2 0 "register_operand" "=wa,wa,wa,wa")
+ (rotate:VI2 (match_operand:VI2 1 "register_operand" "wa,wa,wa,wa")
+ (match_operand:VI2 2 "vector_shift_immediate"
"j,wM,wE,wS")))]
+ "TARGET_XVRLW && "
+{
+ rtx op2 = operands[2];
+ int value = 256;
+ int num_insns = -1;
+
+ if (!xxspltib_constant_p (op2, mode, &num_insns, &value))
+gcc_unreachable ();
+
+ operands[3] = GEN_INT (value & 0xff);
+ return "xvrli %x0,%x1,%3";
+}
[(set_attr "type" "vecsimple")])
(define_insn "altivec_vrlq"
diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md
index 1d95e34557e5..fccfbd7e4904 100644
--- a/gcc/config/rs6000/predicates.md
+++ b/gcc/config/rs6000/predicates.md
@@ -728,6 +728,32 @@
return num_insns == 1;
})
+;; Return 1 if the operand is a CONST_VECTOR whose elements are all the
+;; same and the elements can be an immediate shift or rotate factor
+(define_predicate "vector_shift_immediate"
+ (match_code "const_vector,vec_duplicate,const_int")
+{
+ int value = 256;
+ int num_insns = -1;
+
+ if (zero_constant (op, mode) || all_ones_constant (op, mode))
+return true;
+
+ if (!xxspltib_constant_p (op, mode, &num_insns, &value))
+return false;
+
+ switch (mode)
+{
+case V16QImode: return IN_RANGE (value, 0, 7);
+case V8HImode: return IN_RANGE (value, 0, 15);
+case V4SImode: return IN_RANGE (value, 0, 31);
+case V2DImode: return IN_RANGE (value, 0, 63);
+default:break;
+}
+
+ return false;
+})
+
;; Return 1 if the operand is a CONST_VECTOR and can be loaded into a
;; vector register without using memory.
(define_predicate "easy_vector_constant"
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 8cfd9faf77dc..1a168c2c9596 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -581,6 +581,9 @@ extern int rs6000_vector_align[];
below. */
#define RS6000_FN_TARGET_INFO_HTM 1
+/* Whether we have XVRLW support. */
+#define TARGET_XVRLW TARGET_FUTURE
+
/* Whether the various reciprocal divide/square root estimate instructions
exist, and whether we should automatically generate code for the instruction
by default. */
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 68fbfec95546..420f20d4524b 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -369,7 +369,7 @@
(const (symbol_ref "(enum attr_cpu) rs6000_tune")))
;; The ISA we implement.
-(define_attr "isa" "any,p5,p6,p7,p7v,p8,p8v,p9,p9v,p9kf,p9tf,p10,xxeval"
+(define_attr "isa" "any,p5,p6,p7,p7v,p8,p8v,p9,p9v,p9kf,p9tf,p10,xxeval,xvrlw"
(const_string "any"))
;; Is this alternative enabled for
[gcc(refs/users/meissner/heads/work182-sha)] Add missing test.
https://gcc.gnu.org/g:df1fee6dbf33ca6aa5aae3157efa0f74dcb02dbf
commit df1fee6dbf33ca6aa5aae3157efa0f74dcb02dbf
Author: Michael Meissner
Date: Wed Oct 23 13:30:07 2024 -0400
Add missing test.
2024-10-16 Michael Meissner
gcc/testsuite/
* gcc.target/powerpc/vector-rotate-left.c: New test.
Diff:
---
.../gcc.target/powerpc/vector-rotate-left.c| 34 ++
1 file changed, 34 insertions(+)
diff --git a/gcc/testsuite/gcc.target/powerpc/vector-rotate-left.c
b/gcc/testsuite/gcc.target/powerpc/vector-rotate-left.c
new file mode 100644
index ..5a5f37755077
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vector-rotate-left.c
@@ -0,0 +1,34 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_future_ok } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-mdejagnu-cpu=future -O2" } */
+
+/* Test whether the xvrl (vector word rotate left using VSX registers insead of
+ Altivec registers is generated. */
+
+#include
+
+typedef vector unsigned int v4si_t;
+
+v4si_t
+rotl_v4si_scalar (v4si_t x, unsigned long n)
+{
+ __asm__ (" # %x0" : "+f" (x));
+ return (x << n) | (x >> (32 - n)); /* xvrlw. */
+}
+
+v4si_t
+rotr_v4si_scalar (v4si_t x, unsigned long n)
+{
+ __asm__ (" # %x0" : "+f" (x));
+ return (x >> n) | (x << (32 - n)); /* xvrlw. */
+}
+
+v4si_t
+rotl_v4si_vector (v4si_t x, v4si_t y)
+{
+ __asm__ (" # %x0" : "+f" (x)); /* xvrlw. */
+ return vec_rl (x, y);
+}
+
+/* { dg-final { scan-assembler-times {\mxvrlw\M} 3 } } */
[gcc r15-4574] libstdc++: Replace std::__to_address in C++20 branch in
https://gcc.gnu.org/g:de2dc62379b7a2c93e11b03804380af072fd249b
commit r15-4574-gde2dc62379b7a2c93e11b03804380af072fd249b
Author: Jonathan Wakely
Date: Tue Oct 22 21:23:06 2024 +0100
libstdc++: Replace std::__to_address in C++20 branch in
As noted by Patrick, r15-4546-g85e5b80ee2de80 should have changed the
usage of std::__to_address to std::to_address in the C++20-specific
branch that works on types satisfying std::contiguous_iterator.
libstdc++-v3/ChangeLog:
* include/bits/basic_string.h (assign(Iter, Iter)): Call
std::to_address instead of __to_address.
Reviewed-by: Patrick Palka
Diff:
---
libstdc++-v3/include/bits/basic_string.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/libstdc++-v3/include/bits/basic_string.h
b/libstdc++-v3/include/bits/basic_string.h
index 16e356e06786..28b3e5361855 100644
--- a/libstdc++-v3/include/bits/basic_string.h
+++ b/libstdc++-v3/include/bits/basic_string.h
@@ -1748,7 +1748,7 @@ _GLIBCXX_BEGIN_NAMESPACE_CXX11
{
__glibcxx_requires_valid_range(__first, __last);
return _M_replace(size_type(0), size(),
- std::__to_address(__first), __last - __first);
+ std::to_address(__first), __last - __first);
}
#endif
else
[gcc r15-4572] AArch64: Remove redundant check in aarch64_simd_mov
https://gcc.gnu.org/g:2ac01a4efceacb9f2f9433db636545885296da0a
commit r15-4572-g2ac01a4efceacb9f2f9433db636545885296da0a
Author: Wilco Dijkstra
Date: Thu Oct 17 14:33:44 2024 +
AArch64: Remove redundant check in aarch64_simd_mov
The split condition in aarch64_simd_mov uses
aarch64_simd_special_constant_p.
While doing the split, it checks the mode before calling
aarch64_maybe_generate_simd_constant. This risky since it may result in
unexpectedly calling aarch64_split_simd_move instead of
aarch64_maybe_generate_simd_constant. Since the mode is already checked,
remove the spurious explicit mode check.
gcc/ChangeLog:
* config/aarch64/aarch64-simd.md (aarch64_simd_mov):
Remove redundant mode check.
Diff:
---
gcc/config/aarch64/aarch64-simd.md | 1 -
1 file changed, 1 deletion(-)
diff --git a/gcc/config/aarch64/aarch64-simd.md
b/gcc/config/aarch64/aarch64-simd.md
index 8826f9d68885..04851524fdea 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -208,7 +208,6 @@
else
{
if (FP_REGNUM_P (REGNO (operands[0]))
- && mode == V2DImode
&& aarch64_maybe_generate_simd_constant (operands[0], operands[1],
mode))
;
[gcc r15-4579] aarch64: Improve scalar mode popcount expansion by using SVE [PR113860]
https://gcc.gnu.org/g:9ffcf1f193b477f417a4c1960cd32696a23b99b4
commit r15-4579-g9ffcf1f193b477f417a4c1960cd32696a23b99b4
Author: Pengxuan Zheng
Date: Mon Oct 14 05:37:49 2024 -0700
aarch64: Improve scalar mode popcount expansion by using SVE [PR113860]
This is similar to the recent improvements to the Advanced SIMD popcount
expansion by using SVE. We can utilize SVE to generate more efficient code
for
scalar mode popcount too.
Changes since v1:
* v2: Add a new VNx1BI mode and a new test case for V1DI.
* v3: Abandon VNx1BI changes and add a new variant of aarch64_ptrue_reg.
PR target/113860
gcc/ChangeLog:
* config/aarch64/aarch64-protos.h (aarch64_ptrue_reg): New function.
* config/aarch64/aarch64-simd.md (popcount2): Update pattern
to
also support V1DI mode.
* config/aarch64/aarch64.cc (aarch64_ptrue_reg): New function.
* config/aarch64/aarch64.md (popcount2): Add TARGET_SVE
support.
* config/aarch64/iterators.md (VDQHSD_V1DI): New mode iterator.
(SVE_VDQ_I): Add V1DI.
(bitsize): Likewise.
(VPRED): Likewise.
(VEC_POP_MODE): New mode attribute.
(vec_pop_mode): Likewise.
gcc/testsuite/ChangeLog:
* gcc.target/aarch64/popcnt-sve.c: Update test.
* gcc.target/aarch64/popcnt11.c: New test.
* gcc.target/aarch64/popcnt12.c: New test.
Signed-off-by: Pengxuan Zheng
Diff:
---
gcc/config/aarch64/aarch64-protos.h | 1 +
gcc/config/aarch64/aarch64-simd.md| 15 +--
gcc/config/aarch64/aarch64.cc | 21 ++
gcc/config/aarch64/aarch64.md | 9 +
gcc/config/aarch64/iterators.md | 16 ++--
gcc/testsuite/gcc.target/aarch64/popcnt-sve.c | 10 ++---
gcc/testsuite/gcc.target/aarch64/popcnt11.c | 58 +++
gcc/testsuite/gcc.target/aarch64/popcnt12.c | 20 +
8 files changed, 139 insertions(+), 11 deletions(-)
diff --git a/gcc/config/aarch64/aarch64-protos.h
b/gcc/config/aarch64/aarch64-protos.h
index 06aa0aac0df6..75f30a52e617 100644
--- a/gcc/config/aarch64/aarch64-protos.h
+++ b/gcc/config/aarch64/aarch64-protos.h
@@ -917,6 +917,7 @@ rtx aarch64_expand_sve_dupq (rtx, machine_mode, rtx);
void aarch64_expand_mov_immediate (rtx, rtx);
rtx aarch64_stack_protect_canary_mem (machine_mode, rtx, aarch64_salt_type);
rtx aarch64_ptrue_reg (machine_mode);
+rtx aarch64_ptrue_reg (machine_mode, unsigned int);
rtx aarch64_pfalse_reg (machine_mode);
bool aarch64_sve_same_pred_for_ptest_p (rtx *, rtx *);
void aarch64_emit_sve_pred_move (rtx, rtx, rtx);
diff --git a/gcc/config/aarch64/aarch64-simd.md
b/gcc/config/aarch64/aarch64-simd.md
index 04851524fdea..68839246fd8a 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -3516,19 +3516,28 @@
)
(define_expand "popcount2"
- [(set (match_operand:VDQHSD 0 "register_operand")
- (popcount:VDQHSD (match_operand:VDQHSD 1 "register_operand")))]
+ [(set (match_operand:VDQHSD_V1DI 0 "register_operand")
+ (popcount:VDQHSD_V1DI
+ (match_operand:VDQHSD_V1DI 1 "register_operand")))]
"TARGET_SIMD"
{
if (TARGET_SVE)
{
- rtx p = aarch64_ptrue_reg (mode);
+ rtx p = aarch64_ptrue_reg (mode, == 64 ? 8 : 16);
emit_insn (gen_aarch64_pred_popcount (operands[0],
p,
operands[1]));
DONE;
}
+if (mode == V1DImode)
+ {
+ rtx out = gen_reg_rtx (DImode);
+ emit_insn (gen_popcountdi2 (out, gen_lowpart (DImode, operands[1])));
+ emit_move_insn (operands[0], gen_lowpart (mode, out));
+ DONE;
+ }
+
/* Generate a byte popcount. */
machine_mode mode = == 64 ? V8QImode : V16QImode;
machine_mode mode2 = == 64 ? V2SImode : V4SImode;
diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc
index 3e1d67431566..e6d957d275d1 100644
--- a/gcc/config/aarch64/aarch64.cc
+++ b/gcc/config/aarch64/aarch64.cc
@@ -3630,6 +3630,27 @@ aarch64_ptrue_reg (machine_mode mode)
return gen_lowpart (mode, reg);
}
+/* Return an all-true (restricted to the leading VL bits) predicate register of
+ mode MODE. */
+
+rtx
+aarch64_ptrue_reg (machine_mode mode, unsigned int vl)
+{
+ gcc_assert (aarch64_sve_pred_mode_p (mode));
+
+ rtx_vector_builder builder (VNx16BImode, vl, 2);
+
+ for (int i = 0; i < vl; i++)
+builder.quick_push (CONST1_RTX (BImode));
+
+ for (int i = 0; i < vl; i++)
+builder.quick_push (CONST0_RTX (BImode));
+
+ rtx const_vec = builder.build ();
+ rtx reg = force_reg (VNx16BImode, const_vec);
+ return gen_lowpart (mode, reg);
+}
+
/* Return an all-false predicate register of mode MODE. */
rtx
diff --git a/gcc/config/aarch64/aarch64.
[gcc r15-4571] AArch64: Fix copysign patterns
https://gcc.gnu.org/g:7c7c895c2f34d2a5c0cd2139c5e76c13c6c030c9
commit r15-4571-g7c7c895c2f34d2a5c0cd2139c5e76c13c6c030c9
Author: Wilco Dijkstra
Date: Tue Oct 15 16:22:23 2024 +
AArch64: Fix copysign patterns
The current copysign pattern has a mismatch in the predicates and
constraints -
operand[2] is a register_operand but also has an alternative X which allows
any
operand. Since it is a floating point operation, having an integer
alternative
makes no sense. Change the expander to always use vector immediates which
results in better code and sharing of immediates between copysign and
xorsign.
gcc/ChangeLog:
* config/aarch64/aarch64.md (copysign3): Widen immediate
to
vector.
(copysign3_insn): Use VQ_INT_EQUIV in operand 3.
* config/aarch64/iterators.md (VQ_INT_EQUIV): New iterator.
(vq_int_equiv): Likewise.
gcc/testsuite/ChangeLog:
* gcc.target/aarch64/copysign_3.c: New test.
* gcc.target/aarch64/copysign_4.c: New test.
* gcc.target/aarch64/fneg-abs_2.c: Fixup test.
* gcc.target/aarch64/sve/fneg-abs_2.c: Likewise.
Diff:
---
gcc/config/aarch64/aarch64.md | 48 +--
gcc/config/aarch64/iterators.md | 8
gcc/testsuite/gcc.target/aarch64/copysign_3.c | 16
gcc/testsuite/gcc.target/aarch64/copysign_4.c | 17
gcc/testsuite/gcc.target/aarch64/fneg-abs_2.c | 2 +-
gcc/testsuite/gcc.target/aarch64/sve/fneg-abs_2.c | 2 +-
6 files changed, 62 insertions(+), 31 deletions(-)
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index c54b29cd64b9..ec9c73149881 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -7218,13 +7218,12 @@
}
)
-;; For copysign (x, y), we want to generate:
+;; For copysignf (x, y), we want to generate:
;;
-;; LDR d2, #(1 << 63)
-;; BSL v2.8b, [y], [x]
+;; moviv31.4s, 0x80, lsl 24
+;; bit v0.16b, v1.16b, v31.16b
;;
-;; or another, equivalent, sequence using one of BSL/BIT/BIF. Because
-;; we expect these operations to nearly always operate on
+;; Because we expect these operations to nearly always operate on
;; floating-point values, we do not want the operation to be
;; simplified into a bit-field insert operation that operates on the
;; integer side, since typically that would involve three inter-bank
@@ -7239,32 +7238,25 @@
(match_operand:GPF 2 "nonmemory_operand")]
"TARGET_SIMD"
{
- rtx signbit_const = GEN_INT (HOST_WIDE_INT_M1U
- << (GET_MODE_BITSIZE (mode) - 1));
- /* copysign (x, -1) should instead be expanded as orr with the sign
- bit. */
+ rtx sign = GEN_INT (HOST_WIDE_INT_M1U << (GET_MODE_BITSIZE (mode) -
1));
+ rtx v_bitmask = gen_const_vec_duplicate (mode, sign);
+ v_bitmask = force_reg (mode, v_bitmask);
+
+ /* copysign (x, -1) should instead be expanded as orr with the signbit. */
rtx op2_elt = unwrap_const_vec_duplicate (operands[2]);
+
if (GET_CODE (op2_elt) == CONST_DOUBLE
&& real_isneg (CONST_DOUBLE_REAL_VALUE (op2_elt)))
{
- rtx v_bitmask
- = force_reg (V2mode,
-gen_const_vec_duplicate (V2mode,
- signbit_const));
-
- emit_insn (gen_iorv23 (
- lowpart_subreg (V2mode, operands[0], mode),
- lowpart_subreg (V2mode, operands[1], mode),
+ emit_insn (gen_ior3 (
+ lowpart_subreg (mode, operands[0], mode),
+ lowpart_subreg (mode, operands[1], mode),
v_bitmask));
DONE;
}
-
- machine_mode int_mode = mode;
- rtx bitmask = gen_reg_rtx (int_mode);
- emit_move_insn (bitmask, signbit_const);
operands[2] = force_reg (mode, operands[2]);
emit_insn (gen_copysign3_insn (operands[0], operands[1], operands[2],
- bitmask));
+ v_bitmask));
DONE;
}
)
@@ -7273,23 +7265,21 @@
[(set (match_operand:GPF 0 "register_operand")
(unspec:GPF [(match_operand:GPF 1 "register_operand")
(match_operand:GPF 2 "register_operand")
-(match_operand: 3 "register_operand")]
+(match_operand: 3 "register_operand")]
UNSPEC_COPYSIGN))]
"TARGET_SIMD"
{@ [ cons: =0 , 1 , 2 , 3 ; attrs: type ]
[ w, w , w , 0 ; neon_bsl ] bsl\t%0., %2.,
%1.
[ w, 0 , w , w ; neon_bsl ] bit\t%0., %2.,
%3.
[ w, w , 0 , w ; neon_bsl ] bif\t%0., %1.,
%3.
- [ r, r , 0 , X ; bfm ] bfxil\t%0, %1, #0,
}
)
-
-;; For xorsign (x, y), we want to generate:
+;; For xorsignf (x, y), we want to generate:
;;
-;; LDR d2, #1<<63
-;; AND v3.8B, v1.8B, v2.8B
-;; EOR v0.8B, v0.8B, v3.8B
+;; moviv31.4s, 0x80, lsl 24
+;; and v31.16b, v31.16b, v1.16b
+;;
[gcc r15-4573] Fortran: Generic processing of assumed rank objects (f202y) [PR116733]
https://gcc.gnu.org/g:c5fa2108ce0f3030cb28f47a18bc974c4224b66d commit r15-4573-gc5fa2108ce0f3030cb28f47a18bc974c4224b66d Author: Paul Thomas Date: Wed Oct 23 14:34:20 2024 +0100 Fortran: Generic processing of assumed rank objects (f202y) [PR116733] 2024-10-23 Paul Thomas gcc/fortran PR fortran/116733 * array.cc : White space corrections. * expr.cc (gfc_check_pointer_assign): Permit assumed rank target with -std=f202y. Add constraints that the data pointer object must have rank remapping specified and the that the data target be contiguous. * gfortran.h : Add a gfc_array_ref field 'ar' to the structure 'gfc_association_list'. * interface.cc (gfc_compare_actual_formal): If -Wsurprising is set, emit a warning if an assumed size array is passed to an assumed rank dummy. * intrinsic.cc (do_ts29113_check): Permit an assumed rank arg. for reshape if -std=f202y and the argument is contiguous. * invoke.texi : Introduce -std=f202y. Whitespace errors. * lang.opt : Accept -std=f202y. * libgfortran.h : Define GFC_STD_F202Y. * match.cc (gfc_match_associate): If -std=f202y an assumed rank selector is allowed if it is contiguous and the associate name has rank remapping specified. * options.cc (gfc_init_options): -std=f202y is equivalent to -std=f2023 with experimental f202y features. White space issues * parse.cc (parse_associate): If the selector is assumed rank, use the 'ar' field of the association list to build an array specification. * primary.cc (gfc_match_varspec): Do not resolve the assumed rank selector of a class associate name at this stage to avoid the rank change. * resolve.cc (find_array_spec): If an array_ref dimension is -1 reset it with the rank in the object's array_spec. (gfc_expression_rank): Do not check dimen types for an assumed rank variable expression. (resolve_variable): Do not emit the assumed rank context error if the context is pointer assignment and the variable is a target. (resolve_assoc_var): Resolve the bounds and check for missing bounds in the rank remap of an associate name with an assumed rank selector. Do not correct the rank of an associate name with an assumed rank selector. (resolve_symbol): Allow the reference to an assumed rank object if -std-f202y is enabled and the current operation is EXEC_BLOCK. * st.cc (gfc_free_association_list): Free bounds expressions of the 'ar' field, if present. * trans-array.cc (gfc_conv_ss_startstride): If -std=f202y and bounds checking activated, do not apply the assertion. * trans-expr.cc (gfc_trans_pointer_assignment): An assumed rank target has its offset set to zero. * trans-stmt.cc (trans_associate_var): If the selector is assumed rank, call gfc_trans_pointer_assignment using the 'ar' field in the association list as the array reference for expr1. The data target, expr2, is a copy of the selector expression. gcc/testsuite/ PR fortran/116733 * gfortran.dg/associate_3.f03: Change error message. * gfortran.dg/f202y/f202y.exp: Enable tests of f202y features. * gfortran.dg/f202y/generic_assumed_rank_1.f90: New test. * gfortran.dg/f202y/generic_assumed_rank_2.f90: New test. * gfortran.dg/f202y/generic_assumed_rank_3.f90: New test. Diff: --- gcc/fortran/array.cc | 6 +- gcc/fortran/expr.cc| 26 ++- gcc/fortran/gfortran.h | 2 + gcc/fortran/interface.cc | 10 +++ gcc/fortran/intrinsic.cc | 17 - gcc/fortran/invoke.texi| 31 gcc/fortran/lang.opt | 8 +- gcc/fortran/libgfortran.h | 1 + gcc/fortran/match.cc | 53 +- gcc/fortran/options.cc | 27 --- gcc/fortran/parse.cc | 27 ++- gcc/fortran/primary.cc | 1 + gcc/fortran/resolve.cc | 36 +++-- gcc/fortran/st.cc | 16 gcc/fortran/trans-array.cc | 9 ++- gcc/fortran/trans-expr.cc | 65 + gcc/fortran/trans-stmt.cc | 56 +- gcc/testsuite/gfortran.dg/a
[gcc r15-4575] diagnostics: implement buffering for non-textual formats [PR105916]
https://gcc.gnu.org/g:f565063a0602ad3b48ac687f575dea7a90cd4105
commit r15-4575-gf565063a0602ad3b48ac687f575dea7a90cd4105
Author: David Malcolm
Date: Wed Oct 23 10:54:42 2024 -0400
diagnostics: implement buffering for non-textual formats [PR105916]
PR fortran/105916 reports stray diagnostics appearing in JSON and SARIF
output from gfortran.
In order to handle various awkard parsing issues, the Fortran frontend
implements buffering of diagnostics, so that diagnostics reported to
global_dc can be either:
(a) immediately issued, or
(b) speculatively reported to global_dc, and stored in a buffer, to
either be issued later or discarded.
This buffering code in gcc/fortran/error.cc directly manipulates
implementation details of the diagnostic_context such as the
pretty_printer's buffer, and the counts of how many diagnostics have
been issued. The issue is that this manipulation of pretty_printer's
buffer doesn't work for formats such as JSON and SARIF where diagnostics
are handled in a different way (such as by accumulating json::object
instances in an array).
This patch moves responsibility for such buffering of diagnostics from
fortran's error.cc to the diagnostic subsystem. It introduces a new
class diagnostic_buffer representing a particular buffer of diagnostics
that have been reported but not yet issued. Each diagnostic output
format implements buffering in a different way, and so there is a
new class hierarchy, diagnostic_per_format_buffer, representing the
various format-specific ways that buffering is to be implemented. This
is hidden as an implementation detail of diagnostic_buffer.
The patch also updates how diagnostics of each kind (e.g. warnings vs
errors) are counted, so that if buffering is enabled, the count is
incremented within the buffer, and the counts in the diagnostic_context
are only updated if and when the buffer is flushed; checking for
max_errors is similarly updated to support both buffered and unbuffered
cases.
For ease of debugging, the patch extends the "dump" functions within the
diagnostics subsystem, so that e.g. global_dc->dump () now prints the
buffering status, e.g.:
(gdb) call global_dc->dump()
diagnostic_context:
counts:
(none)
output format:
sarif_output_format
printer:
m_show_color: false
m_url_format: bel
m_buffer:
m_formatted_obstack current object: length 0:
m_chunk_obstack current object: length 0:
diagnostic buffer:
m_per_format_buffer:
counts:
error: 1
diagnostic_sarif_format_buffer:
result[0]:
{"ruleId": "error",
"level": "error",
"message": {"text": "Function ‘program’ requires an argument list at (1)"},
"locations": [{"physicalLocation": {"artifactLocation": {"uri":
"../../src/gcc/testsuite/gfortran.dg/pr105954.f90",
"uriBaseId":
"PWD"},
"region": {"startLine": 6,
"startColumn": 8,
"endColumn": 9},
"contextRegion": {"startLine": 6,
"snippet": {"text": "program p\n"]}
which shows that no diagnostics have been issued yet, but the active
diagnostic_buffer has a single error buffered within it, in SARIF form.
Similarly, it's possible to use "dump" on a diagnostic_buffer to directly
query its contents; here's the same example, this time with the text
output format:
(gdb) call error_buffer.buffer.dump()
m_per_format_buffer:
counts:
error: 1
diagnostic_text_format_buffer:
m_formatted_obstack current object: length 232:
: 1b 5b 30 31 6d 1b 5b 4b 2e 2e 2f 2e 2e 2f 73 72 |
.[01m.[K../../sr
0010: 63 2f 67 63 63 2f 74 65 73 74 73 75 69 74 65 2f |
c/gcc/testsuite/
0020: 67 66 6f 72 74 72 61 6e 2e 64 67 2f 70 72 31 30 |
gfortran.dg/pr10
0030: 35 39 35 34 2e 66 39 30 3a 36 3a 38 3a 1b 5b 6d |
5954.f90:6:8:.[m
0040: 1b 5b 4b 0a 0a 20 20 20 20 36 20 7c 20 70 72 6f | .[K..
6 | pro
0050: 67 72 61 6d 20 70 0a 20 20 20 20 20 20 7c 20 20 | gram p.
|
0060: 20 20 20 20 20 20 1b 5b 30 31 3b 33 31 6d 1b 5b |
.[01;31m.[
0070: 4b 31 1b 5b 6d 1b 5b 4b 0a 1b 5b 30 31 3b 33 31 |
K1.[m.[K..[01;31
0080: 6d 1b 5b 4b 45 72 72 6f 72 3a 1b 5b 6d 1b 5b 4b |
m.[KError:.[m.[K
0090: 20 46 75 6e 63 74 69 6f 6e 20 e2 80 98 1b 5b 30 | Function
[0
00a0: 31 6d 1b 5b 4b 70 72 6f 67 72 61 6d 1b 5b 6d 1b |
1m.[Kprogram.[m.
00b0: 5b 4b e2 80 99 20 72 65
[gcc r15-4577] libstdc++: Add -D_GLIBCXX_ASSERTIONS default for -O0 to API history
https://gcc.gnu.org/g:4b0f238855f8fa79acf7cca84b523ca8513bf68d commit r15-4577-g4b0f238855f8fa79acf7cca84b523ca8513bf68d Author: Jonathan Wakely Date: Wed Oct 23 16:01:04 2024 +0100 libstdc++: Add -D_GLIBCXX_ASSERTIONS default for -O0 to API history libstdc++-v3/ChangeLog: * doc/xml/manual/evolution.xml: Document that assertions are enabled for unoptimized builds. * doc/html/*: Regenerate. Diff: --- libstdc++-v3/doc/html/index.html | 2 +- libstdc++-v3/doc/html/manual/api.html | 2 ++ libstdc++-v3/doc/html/manual/appendix.html | 2 +- libstdc++-v3/doc/html/manual/appendix_porting.html | 2 +- libstdc++-v3/doc/html/manual/index.html| 2 +- libstdc++-v3/doc/xml/manual/evolution.xml | 8 6 files changed, 14 insertions(+), 4 deletions(-) diff --git a/libstdc++-v3/doc/html/index.html b/libstdc++-v3/doc/html/index.html index 395908f17a1a..e96f2cb27047 100644 --- a/libstdc++-v3/doc/html/index.html +++ b/libstdc++-v3/doc/html/index.html @@ -142,7 +142,7 @@ Existing tests C++11 Requirements Test Sequence Descriptions -ABI Policy and GuidelinesThe C++ InterfaceVersioningGoalsHistoryPrerequisitesConfiguringChecking ActiveAllowed ChangesProhibited ChangesImplementationTestingSingle ABI TestingMultiple ABI TestingOutstanding IssuesAPI Evolution and Deprecation History3.03.13.23.33.44.04.14.24.34.44.54.64.74.84.955.3677.27.38910111212.31313.3class="constant">14class="section">Backwards >Compatibilityhref="manual/backwards.html#backwards.first">Firstclass="section">href="manual/backwards.html#backwards.second">Secondclass="section">href="manual/backwards.html#backwards.third">Third class="section">href="manual/backwards.html#backwards.third.headers">Pre-ISO headers >removedhref="manual/backwards.html#backwards.third.hash">Extension headers hash_map, >hash_set moved to ext or backwardsclass="section">href="manual/backwards.html#backwards.third.nocreate_noreplace">No class="code">ios::nocreate/ios::noreplace. +ABI Policy and GuidelinesThe C++ InterfaceVersioningGoalsHistoryPrerequisitesConfiguringChecking ActiveAllowed ChangesProhibited ChangesImplementationTestingSingle ABI TestingMultiple ABI TestingOutstanding IssuesAPI Evolution and Deprecation History3.03.13.23.33.44.04.14.24.34.44.54.64.74.84.955.3677.27.38910111212.31313.3class="constant">14href="manual/api.html#api.rel_151">class="constant">15class="section">Backwards >Compatibilityhref="manual/backwards.html#backwards.first">Firstclass="section">href="manual/backwards.html#backwards.second">Secondclass="section">href="manual/backwards.html#backwards.third">Third class="section">href="manual/backwards.html#backwards.third.headers">Pre-ISO headers >removedhref="manual/backwards.html#backwards.third.hash">Extension headers hash_map, >hash_set moved to ext or backwardsclass="section">No ios::nocreate/ios::noreplace. No stream::attach(int fd) diff --git a/libstdc++-v3/doc/html/manual/api.html b/libstdc++-v3/doc/html/manual/api.html index 59ed4c888628..799f6eae2a23 100644 --- a/libstdc++-v3/doc/html/manual/api.html +++ b/libstdc++-v3/doc/html/manual/api.html @@ -496,4 +496,6 @@ to be used with std::basic_istream. The extension allowing std::basic_string to be instantiated with an allocator that doesn't match the string's character type is no longer allowed in C++20 mode. +15 +Enabled debug assertions by default for unoptimized builds. Prev Up NextABI Policy and Guidelines Home Backwards Compatibility \ No newline at end of file diff --git a/libstdc++-v3/doc/html/manual/appendix.html b/libstdc++-v3/doc/html/manual/appendix.html index affd5839f435..69a0e0018f37 100644 --- a/libstdc++-v3/doc/html/manual/appendix.html +++ b/libstdc++-v3/doc/html/manual/appendix.html @@ -16,7 +16,7 @@ Existing tests C++11 Requirements Test Sequence Descriptions -ABI Policy and GuidelinesThe C++ InterfaceVersioningGoalsHistoryPrerequisitesConfiguringChecking ActiveAllowed ChangesProhibited Changes< dt>ImplementationTestingSingle ABI TestingMultiple ABI TestingOutstanding IssuesAPI Evolution and Deprecation History3.03.13.23.3< /span>3.44.04.14.24.34.44.54.64.74.84.955.3677.27.38910111212.31313.314Backwards CompatibilityFirstSecondThirdPre-ISO headers removedExtension headers hash_map, hash_set moved to ext or backwardsNo ios::nocreate/ios::noreplace. +ABI Policy and GuidelinesThe C++ InterfaceVersioningGoalsHistoryPrerequisitesConfiguringChecking ActiveAllowed ChangesProhibited Changes< dt>ImplementationTestingSingle ABI TestingMultiple ABI TestingOutstanding IssuesAPI Evolution and Deprecation History3.03.13.23.3< /span>3.44.04.14.24.34.44.54.64.74.84.955.3677.27.38910111212.31313.31415Backwards Compatibility FirstSecondThirdPre-ISO headers removedExtension headers hash_map, hash_set moved to ext or backwardsNo ios::nocreate/ios::noreplace. No stream::attach(int fd) diff
[gcc r15-4576] libstdc++: Add GLIBCXX_TESTSUITE_STDS example to docs
https://gcc.gnu.org/g:5a661ecdfb22dd6fd1524ee8619be4bc046a1b2a
commit r15-4576-g5a661ecdfb22dd6fd1524ee8619be4bc046a1b2a
Author: Jonathan Wakely
Date: Tue Oct 22 21:18:51 2024 +0100
libstdc++: Add GLIBCXX_TESTSUITE_STDS example to docs
libstdc++-v3/ChangeLog:
* doc/xml/manual/test.xml: Add GLIBCXX_TESTSUITE_STDS example.
* doc/html/manual/test.html: Regenerate.
Diff:
---
libstdc++-v3/doc/html/manual/test.html | 5 +++--
libstdc++-v3/doc/xml/manual/test.xml | 5 +++--
2 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/libstdc++-v3/doc/html/manual/test.html
b/libstdc++-v3/doc/html/manual/test.html
index 3657997fad46..1c7af1193daf 100644
--- a/libstdc++-v3/doc/html/manual/test.html
+++ b/libstdc++-v3/doc/html/manual/test.html
@@ -352,12 +352,13 @@ cat 27_io/objects/char/3_xin.in |
a.out-std, similar to
the G++ tests.
Adding set v3_std_list { 11 17 23 } to
- ~/.dejagnurc or a file named by the
+ ~/.dejagnurc or to a file named by the
DEJAGNU environment variable will cause every
test to
be run three times, using a different -std
each time.
Alternatively, a list of standard versions to test with can be specified
as a comma-separated list in the GLIBCXX_TESTSUITE_STDS
- environment variable.
+ environment variable, e.g. GLIBCXX_TESTSUITE_STDS=11,17,23
+ is equivalent to the v3_std_list value above.
To run the libstdc++ test suite under the
debug mode, use
diff --git a/libstdc++-v3/doc/xml/manual/test.xml
b/libstdc++-v3/doc/xml/manual/test.xml
index 40926946fe7a..6b7f1b04a2ac 100644
--- a/libstdc++-v3/doc/xml/manual/test.xml
+++ b/libstdc++-v3/doc/xml/manual/test.xml
@@ -600,12 +600,13 @@ cat 27_io/objects/char/3_xin.in | a.out
Since GCC 14, the libstdc++ testsuite has built-in support for running
tests with more than one -std, similar to the G++ tests.
Adding set v3_std_list { 11 17 23 } to
- ~/.dejagnurc or a file named by the
+ ~/.dejagnurc or to a file named by the
DEJAGNU environment variable will cause every test to
be run three times, using a different -std each time.
Alternatively, a list of standard versions to test with can be specified
as a comma-separated list in the GLIBCXX_TESTSUITE_STDS
- environment variable.
+ environment variable, e.g. GLIBCXX_TESTSUITE_STDS=11,17,23
+ is equivalent to the v3_std_list value above.
[gcc r15-4570] doc: remove obsolete deprecated info
https://gcc.gnu.org/g:2b666dc4d1c96e0ea3597fe7e502a70198a66c03
commit r15-4570-g2b666dc4d1c96e0ea3597fe7e502a70198a66c03
Author: Jason Merrill
Date: Tue Oct 15 09:04:23 2024 -0400
doc: remove obsolete deprecated info
These formerly deprecated features eventually made it into the C++ standard.
gcc/ChangeLog:
* doc/extend.texi (Deprecated Features): Remove text about some
no-longer-deprecated features.
Diff:
---
gcc/doc/extend.texi | 10 --
1 file changed, 10 deletions(-)
diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
index 42bd567119de..6c2d6a610cd6 100644
--- a/gcc/doc/extend.texi
+++ b/gcc/doc/extend.texi
@@ -30169,16 +30169,6 @@ The use of default arguments in function pointers,
function typedefs
and other places where they are not permitted by the standard is
deprecated and will be removed from a future version of G++.
-G++ allows floating-point literals to appear in integral constant expressions,
-e.g.@: @samp{ enum E @{ e = int(2.2 * 3.7) @} }
-This extension is deprecated and will be removed from a future version.
-
-G++ allows static data members of const floating-point type to be declared
-with an initializer in a class definition. The standard only allows
-initializers for static members of const integral types and const
-enumeration types so this extension has been deprecated and will be removed
-from a future version.
-
G++ allows attributes to follow a parenthesized direct initializer,
e.g.@: @samp{ int f (0) __attribute__ ((something)); } This extension
has been ignored since G++ 3.3 and is deprecated.
[gcc r15-4567] AArch64: Improve SIMD immediate generation (1/3)
https://gcc.gnu.org/g:bcbf4fa46ae2919cf281322bd39f4810b7c18c9d
commit r15-4567-gbcbf4fa46ae2919cf281322bd39f4810b7c18c9d
Author: Wilco Dijkstra
Date: Tue Oct 8 13:32:09 2024 +
AArch64: Improve SIMD immediate generation (1/3)
Cleanup the various interfaces related to SIMD immediate generation.
Introduce
new functions that make it clear which operation (AND, OR, MOV) we are
testing
for rather than guessing the final instruction. Reduce the use of overly
long
names, unused and default parameters for clarity. No changes to internals
or
generated code.
gcc/ChangeLog:
* config/aarch64/aarch64-protos.h (enum simd_immediate_check): Move
to aarch64.cc.
(aarch64_output_simd_mov_immediate): Remove.
(aarch64_output_simd_mov_imm): New prototype.
(aarch64_output_simd_orr_imm): Likewise.
(aarch64_output_simd_and_imm): Likewise.
(aarch64_simd_valid_immediate): Remove.
(aarch64_simd_valid_and_imm): New prototype.
(aarch64_simd_valid_mov_imm): Likewise.
(aarch64_simd_valid_orr_imm): Likewise.
* config/aarch64/aarch64-simd.md: Use aarch64_output_simd_mov_imm.
* config/aarch64/aarch64.cc (enum simd_immediate_check): Moved from
aarch64-protos.h.
Use AARCH64_CHECK_AND rather than AARCH64_CHECk_BIC.
(aarch64_expand_sve_const_vector): Use aarch64_simd_valid_mov_imm.
(aarch64_expand_mov_immediate): Likewise.
(aarch64_can_const_movi_rtx_p): Likewise.
(aarch64_secondary_reload): Likewise.
(aarch64_legitimate_constant_p): Likewise.
(aarch64_advsimd_valid_immediate): Simplify checks on 'which' param.
(aarch64_sve_valid_immediate): Add extra param for move vs logical.
(aarch64_simd_valid_immediate): Rename to aarch64_simd_valid_imm.
(aarch64_simd_valid_mov_imm): New function.
(aarch64_simd_valid_orr_imm): Likewise.
(aarch64_simd_valid_and_imm): Likewise.
(aarch64_mov_operand_p): Use aarch64_simd_valid_mov_imm.
(aarch64_simd_scalar_immediate_valid_for_move): Likewise.
(aarch64_simd_make_constant): Likewise.
(aarch64_expand_vector_init_fallback): Likewise.
(aarch64_output_simd_mov_immediate): Rename to
aarch64_output_simd_imm.
(aarch64_output_simd_orr_imm): New function.
(aarch64_output_simd_and_imm): Likewise.
(aarch64_output_simd_mov_imm): Likewise.
(aarch64_output_scalar_simd_mov_immediate): Use
aarch64_output_simd_mov_imm.
(aarch64_output_sve_mov_immediate): Use aarch64_simd_valid_imm.
(aarch64_output_sve_ptrues): Likewise.
* config/aarch64/constraints.md (Do): Use
aarch64_simd_valid_orr_imm.
(Db): Use aarch64_simd_valid_and_imm.
* config/aarch64/predicates.md (aarch64_reg_or_bic_imm): Use
aarch64_simd_valid_orr_imm.
(aarch64_reg_or_and_imm): Use aarch64_simd_valid_and_imm.
Diff:
---
gcc/config/aarch64/aarch64-protos.h | 21 ++
gcc/config/aarch64/aarch64-simd.md | 11 ++-
gcc/config/aarch64/aarch64.cc | 144 +---
gcc/config/aarch64/constraints.md | 10 +--
gcc/config/aarch64/predicates.md| 8 +-
5 files changed, 118 insertions(+), 76 deletions(-)
diff --git a/gcc/config/aarch64/aarch64-protos.h
b/gcc/config/aarch64/aarch64-protos.h
index d03c1fe798b2..e789ca935834 100644
--- a/gcc/config/aarch64/aarch64-protos.h
+++ b/gcc/config/aarch64/aarch64-protos.h
@@ -665,16 +665,6 @@ enum aarch64_extra_tuning_flags
AARCH64_EXTRA_TUNE_ALL = (1u << AARCH64_EXTRA_TUNE_index_END) - 1
};
-/* Enum to distinguish which type of check is to be done in
- aarch64_simd_valid_immediate. This is used as a bitmask where
- AARCH64_CHECK_MOV has both bits set. Thus AARCH64_CHECK_MOV will
- perform all checks. Adding new types would require changes accordingly. */
-enum simd_immediate_check {
- AARCH64_CHECK_ORR = 1 << 0,
- AARCH64_CHECK_BIC = 1 << 1,
- AARCH64_CHECK_MOV = AARCH64_CHECK_ORR | AARCH64_CHECK_BIC
-};
-
extern struct tune_params aarch64_tune_params;
/* The available SVE predicate patterns, known in the ACLE as "svpattern". */
@@ -834,8 +824,10 @@ char *aarch64_output_sve_rdvl (rtx);
char *aarch64_output_sve_addvl_addpl (rtx);
char *aarch64_output_sve_vector_inc_dec (const char *, rtx);
char *aarch64_output_scalar_simd_mov_immediate (rtx, scalar_int_mode);
-char *aarch64_output_simd_mov_immediate (rtx, unsigned,
- enum simd_immediate_check w = AARCH64_CHECK_MOV);
+char *aarch64_output_simd_mov_imm (rtx, unsigned);
+char *aarch64_output_simd_orr_imm (rtx, unsigned);
+char *aarch64_output_simd_and_imm (rtx, unsigned);
+
char *aarch64_output_sve_mov_immediate (rtx);
char *aarch64_output_sve_ptrues (rtx);
bool aarch64_pad_reg_upwar
[gcc r15-4568] AArch64: Improve SIMD immediate generation (2/3)
https://gcc.gnu.org/g:756890d66cf4971fc11187ccdf5893681aa661a1
commit r15-4568-g756890d66cf4971fc11187ccdf5893681aa661a1
Author: Wilco Dijkstra
Date: Tue Oct 8 15:55:25 2024 +
AArch64: Improve SIMD immediate generation (2/3)
Allow use of SVE immediates when generating AdvSIMD code and SVE is
available.
First check for a valid AdvSIMD immediate, and if SVE is available, try
using
an SVE move or bitmask immediate.
gcc/ChangeLog:
* config/aarch64/aarch64-simd.md (ior3):
Use aarch64_reg_or_orr_imm predicate. Combine SVE/AdvSIMD
immediates
and use aarch64_output_simd_orr_imm.
* config/aarch64/aarch64.cc (struct simd_immediate_info): Add
SVE_MOV.
(aarch64_sve_valid_immediate): Use SVE_MOV for SVE move immediates.
(aarch64_simd_valid_imm): Enable SVE SIMD immediates when possible.
(aarch64_output_simd_imm): Support emitting SVE SIMD immediates.
* config/aarch64/predicates.md (aarch64_orr_imm_sve_advsimd):
Remove.
gcc/testsuite/ChangeLog:
* gcc.target/aarch64/sve/acle/asm/insr_s64.c: Allow SVE MOV imm.
* gcc.target/aarch64/sve/acle/asm/insr_u64.c: Likewise.
* gcc.target/aarch64/sve/fneg-abs_1.c: Update to check for ORRI.
* gcc.target/aarch64/sve/fneg-abs_2.c: Likewise.
* gcc.target/aarch64/sve/simd_imm_mov.c: New test.
Diff:
---
gcc/config/aarch64/aarch64-simd.md | 10 +++---
gcc/config/aarch64/aarch64.cc | 41 +-
gcc/config/aarch64/predicates.md | 5 ---
.../gcc.target/aarch64/sve/acle/asm/insr_s64.c | 4 +--
.../gcc.target/aarch64/sve/acle/asm/insr_u64.c | 4 +--
gcc/testsuite/gcc.target/aarch64/sve/fneg-abs_1.c | 6 ++--
gcc/testsuite/gcc.target/aarch64/sve/fneg-abs_2.c | 4 +--
.../gcc.target/aarch64/sve/simd_imm_mov.c | 39
8 files changed, 85 insertions(+), 28 deletions(-)
diff --git a/gcc/config/aarch64/aarch64-simd.md
b/gcc/config/aarch64/aarch64-simd.md
index b031b52c8fb1..bf4863441de1 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -1135,13 +1135,11 @@
(define_insn "ior3"
[(set (match_operand:VDQ_I 0 "register_operand")
(ior:VDQ_I (match_operand:VDQ_I 1 "register_operand")
- (match_operand:VDQ_I 2 "aarch64_orr_imm_sve_advsimd")))]
+ (match_operand:VDQ_I 2 "aarch64_reg_or_orr_imm")))]
"TARGET_SIMD"
- {@ [ cons: =0 , 1 , 2; attrs: arch ]
- [ w, w , w ; simd ] orr\t%0., %1.,
%2.
- [ w, 0 , vsl; sve ] orr\t%Z0., %Z0., #%2
- [ w, 0 , Do ; simd ] \
- << aarch64_output_simd_orr_imm (operands[2], );
+ {@ [ cons: =0 , 1 , 2 ]
+ [ w, w , w ] orr\t%0., %1., %2.
+ [ w, 0 , Do ] << aarch64_output_simd_orr_imm (operands[2],
);
}
[(set_attr "type" "neon_logic")]
)
diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc
index 4db224ff0421..614f99e799ca 100644
--- a/gcc/config/aarch64/aarch64.cc
+++ b/gcc/config/aarch64/aarch64.cc
@@ -140,7 +140,7 @@ enum simd_immediate_check {
/* Information about a legitimate vector immediate operand. */
struct simd_immediate_info
{
- enum insn_type { MOV, MVN, INDEX, PTRUE };
+ enum insn_type { MOV, MVN, INDEX, PTRUE, SVE_MOV };
enum modifier_type { LSL, MSL };
simd_immediate_info () {}
@@ -22982,14 +22982,16 @@ aarch64_sve_valid_immediate (unsigned HOST_WIDE_INT
ival, scalar_int_mode mode,
{
/* DUP with no shift. */
if (info)
- *info = simd_immediate_info (mode, val);
+ *info = simd_immediate_info (mode, val,
+simd_immediate_info::SVE_MOV);
return true;
}
if ((val & 0xff) == 0 && IN_RANGE (val, -0x8000, 0x7f00))
{
/* DUP with LSL #8. */
if (info)
- *info = simd_immediate_info (mode, val);
+ *info = simd_immediate_info (mode, val,
+simd_immediate_info::SVE_MOV);
return true;
}
}
@@ -22997,7 +22999,7 @@ aarch64_sve_valid_immediate (unsigned HOST_WIDE_INT
ival, scalar_int_mode mode,
{
/* DUPM. */
if (info)
- *info = simd_immediate_info (mode, val);
+ *info = simd_immediate_info (mode, val, simd_immediate_info::SVE_MOV);
return true;
}
return false;
@@ -23322,8 +23324,13 @@ aarch64_simd_valid_imm (rtx op, simd_immediate_info
*info,
if (vec_flags & VEC_SVE_DATA)
return aarch64_sve_valid_immediate (ival, imode, info, which);
- else
-return aarch64_advsimd_valid_immediate (val64, imode, info, which);
+
+ if (aarch64_advsimd_valid_immediate (val64, imode, info, which))
+return true;
+
+ if (TARGET_SVE)
+return aarch64_sve_valid_immediate (iv
[gcc r15-4569] AArch64: Add support for SIMD xor immediate (3/3)
https://gcc.gnu.org/g:22a37534c640ca5ff2f0e947dfe60df59fb6bba1
commit r15-4569-g22a37534c640ca5ff2f0e947dfe60df59fb6bba1
Author: Wilco Dijkstra
Date: Mon Oct 14 16:53:44 2024 +
AArch64: Add support for SIMD xor immediate (3/3)
Add support for SVE xor immediate when generating AdvSIMD code and SVE is
available.
gcc/ChangeLog:
* config/aarch64/aarch64.cc (enum simd_immediate_check): Add
AARCH64_CHECK_XOR.
(aarch64_simd_valid_xor_imm): New function.
(aarch64_output_simd_imm): Add AARCH64_CHECK_XOR support.
(aarch64_output_simd_xor_imm): New function.
* config/aarch64/aarch64-protos.h (aarch64_output_simd_xor_imm): New
prototype.
(aarch64_simd_valid_xor_imm): New prototype.
* config/aarch64/aarch64-simd.md (xor3):
Use aarch64_reg_or_xor_imm predicate and add an immediate
alternative.
* config/aarch64/predicates.md (aarch64_reg_or_xor_imm): Add new
predicate.
gcc/testsuite/ChangeLog:
* gcc.target/aarch64/sve/simd_imm.c: New test.
Diff:
---
gcc/config/aarch64/aarch64-protos.h | 2 ++
gcc/config/aarch64/aarch64-simd.md | 12 ++---
gcc/config/aarch64/aarch64.cc | 22 ++--
gcc/config/aarch64/predicates.md| 5
gcc/testsuite/gcc.target/aarch64/sve/simd_imm.c | 35 +
5 files changed, 70 insertions(+), 6 deletions(-)
diff --git a/gcc/config/aarch64/aarch64-protos.h
b/gcc/config/aarch64/aarch64-protos.h
index e789ca935834..06aa0aac0df6 100644
--- a/gcc/config/aarch64/aarch64-protos.h
+++ b/gcc/config/aarch64/aarch64-protos.h
@@ -827,6 +827,7 @@ char *aarch64_output_scalar_simd_mov_immediate (rtx,
scalar_int_mode);
char *aarch64_output_simd_mov_imm (rtx, unsigned);
char *aarch64_output_simd_orr_imm (rtx, unsigned);
char *aarch64_output_simd_and_imm (rtx, unsigned);
+char *aarch64_output_simd_xor_imm (rtx, unsigned);
char *aarch64_output_sve_mov_immediate (rtx);
char *aarch64_output_sve_ptrues (rtx);
@@ -844,6 +845,7 @@ bool aarch64_sve_ptrue_svpattern_p (rtx, struct
simd_immediate_info *);
bool aarch64_simd_valid_and_imm (rtx);
bool aarch64_simd_valid_mov_imm (rtx);
bool aarch64_simd_valid_orr_imm (rtx);
+bool aarch64_simd_valid_xor_imm (rtx);
bool aarch64_valid_sysreg_name_p (const char *);
const char *aarch64_retrieve_sysreg (const char *, bool, bool);
rtx aarch64_check_zero_based_sve_index_immediate (rtx);
diff --git a/gcc/config/aarch64/aarch64-simd.md
b/gcc/config/aarch64/aarch64-simd.md
index bf4863441de1..8826f9d68885 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -1144,12 +1144,16 @@
[(set_attr "type" "neon_logic")]
)
+;; For EOR (vector, register) and SVE EOR (vector, immediate)
(define_insn "xor3"
- [(set (match_operand:VDQ_I 0 "register_operand" "=w")
-(xor:VDQ_I (match_operand:VDQ_I 1 "register_operand" "w")
-(match_operand:VDQ_I 2 "register_operand" "w")))]
+ [(set (match_operand:VDQ_I 0 "register_operand")
+(xor:VDQ_I (match_operand:VDQ_I 1 "register_operand")
+ (match_operand:VDQ_I 2 "aarch64_reg_or_xor_imm")))]
"TARGET_SIMD"
- "eor\t%0., %1., %2."
+ {@ [ cons: =0 , 1 , 2 ]
+ [ w, w , w ] eor\t%0., %1., %2.
+ [ w, 0 , Do ] << aarch64_output_simd_xor_imm (operands[2],
);
+ }
[(set_attr "type" "neon_logic")]
)
diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc
index 614f99e799ca..3e1d67431566 100644
--- a/gcc/config/aarch64/aarch64.cc
+++ b/gcc/config/aarch64/aarch64.cc
@@ -134,7 +134,8 @@ constexpr auto AARCH64_STATE_OUT = 1U << 2;
enum simd_immediate_check {
AARCH64_CHECK_MOV,
AARCH64_CHECK_ORR,
- AARCH64_CHECK_AND
+ AARCH64_CHECK_AND,
+ AARCH64_CHECK_XOR
};
/* Information about a legitimate vector immediate operand. */
@@ -23354,6 +23355,13 @@ aarch64_simd_valid_and_imm (rtx op)
return aarch64_simd_valid_imm (op, NULL, AARCH64_CHECK_AND);
}
+/* Return true if OP is a valid SIMD xor immediate for SVE. */
+bool
+aarch64_simd_valid_xor_imm (rtx op)
+{
+ return aarch64_simd_valid_imm (op, NULL, AARCH64_CHECK_XOR);
+}
+
/* Check whether X is a VEC_SERIES-like constant that starts at 0 and
has a step in the range of INDEX. Return the index expression if so,
otherwise return null. */
@@ -25460,10 +25468,12 @@ aarch64_output_simd_imm (rtx const_vector, unsigned
width,
}
else
{
- /* AARCH64_CHECK_ORR or AARCH64_CHECK_AND. */
+ /* AARCH64_CHECK_ORR, AARCH64_CHECK_AND or AARCH64_CHECK_XOR. */
mnemonic = "orr";
if (which == AARCH64_CHECK_AND)
mnemonic = info.insn == simd_immediate_info::MVN ? "bic" : "and";
+ else if (which == AARCH64_CHECK_XOR)
+ mnemonic = "eor";
if (info.insn == simd_immediate_info::SVE_MOV)
{
@
[gcc r15-4584] aarch64: Fix warning in aarch64_ptrue_reg
https://gcc.gnu.org/g:820464ef382fa7fb54b7f1e2f05ed9763ba8decd commit r15-4584-g820464ef382fa7fb54b7f1e2f05ed9763ba8decd Author: Andrew Pinski Date: Wed Oct 23 16:39:21 2024 -0700 aarch64: Fix warning in aarch64_ptrue_reg After r15-4579-g9ffcf1f193b477, we get the following warning/error while bootstrapping on aarch64: ``` ../../gcc/gcc/config/aarch64/aarch64.cc: In function ‘rtx_def* aarch64_ptrue_reg(machine_mode, unsigned int)’: ../../gcc/gcc/config/aarch64/aarch64.cc:3643:21: error: comparison of integer expressions of different signedness: ‘int’ and ‘unsigned int’ [-Werror=sign-compare] 3643 | for (int i = 0; i < vl; i++) | ~~^~~~ ``` This changes the type of i to unsigned to match the type of vl. Pushed as obvious after a bootstrap/test on aarch64-linux-gnu. gcc/ChangeLog: * config/aarch64/aarch64.cc (aarch64_ptrue_reg): Fix type of induction variable i. Signed-off-by: Andrew Pinski Diff: --- gcc/config/aarch64/aarch64.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc index e6d957d275d1..7fbe3a7380c7 100644 --- a/gcc/config/aarch64/aarch64.cc +++ b/gcc/config/aarch64/aarch64.cc @@ -3640,10 +3640,10 @@ aarch64_ptrue_reg (machine_mode mode, unsigned int vl) rtx_vector_builder builder (VNx16BImode, vl, 2); - for (int i = 0; i < vl; i++) + for (unsigned i = 0; i < vl; i++) builder.quick_push (CONST1_RTX (BImode)); - for (int i = 0; i < vl; i++) + for (unsigned i = 0; i < vl; i++) builder.quick_push (CONST0_RTX (BImode)); rtx const_vec = builder.build ();
[gcc r15-4583] match: Reject non-const internal functions [PR117260]
https://gcc.gnu.org/g:36e3e68250bf54909218298d1141138579803631
commit r15-4583-g36e3e68250bf54909218298d1141138579803631
Author: Andrew Pinski
Date: Tue Oct 22 09:05:38 2024 -0700
match: Reject non-const internal functions [PR117260]
When internal functions support was added to match
(r6-4979-gc9e926ce2bdc8b),
the check for ECF_CONST was the builtin function side. Though before
r15-4503-g8d6d6d537fdc,
there was no use of maybe_push_res_to_seq with non-const internal functions
so the check
would not make a difference.
This adds the check for internal functions just as there is a check for
builtins.
Note I didn't add a testcase because there was no non-const internal
function
which could be used on x86_64 in a decent manor.
Bootstrapped and tested on x86_64-linux-gnu.
gcc/ChangeLog:
PR tree-optimization/117260
* gimple-match-exports.cc (maybe_push_res_to_seq): Reject non-const
internal functions.
Signed-off-by: Andrew Pinski
Diff:
---
gcc/gimple-match-exports.cc | 5 +
1 file changed, 5 insertions(+)
diff --git a/gcc/gimple-match-exports.cc b/gcc/gimple-match-exports.cc
index d3e626a1a245..77d225825cfa 100644
--- a/gcc/gimple-match-exports.cc
+++ b/gcc/gimple-match-exports.cc
@@ -522,6 +522,11 @@ maybe_push_res_to_seq (gimple_match_op *res_op, gimple_seq
*seq, tree res)
{
/* Generate the given function if we can. */
internal_fn ifn = as_internal_fn (fn);
+
+ /* We can't and should not emit calls to non-const functions. */
+ if (!(internal_fn_flags (ifn) & ECF_CONST))
+ return NULL_TREE;
+
new_stmt = build_call_internal (ifn, res_op);
if (!new_stmt)
return NULL_TREE;
[gcc r15-4580] jit: reset state in varasm.cc [PR117275]
https://gcc.gnu.org/g:779c0390e3b57d1eebd41bbfe43d1f329c91de6c
commit r15-4580-g779c0390e3b57d1eebd41bbfe43d1f329c91de6c
Author: David Malcolm
Date: Wed Oct 23 14:26:38 2024 -0400
jit: reset state in varasm.cc [PR117275]
PR jit/117275 reports various jit test failures seen on
powerpc64le-unknown-linux-gnu due to hitting this assertion
in varasm.cc on the 2nd compilation in a process:
#2 0x763e67d0 in assemble_external_libcall (fun=0x72a4b1d8)
at ../../src/gcc/varasm.cc:2650
2650 gcc_assert (!pending_assemble_externals_processed);
(gdb) p pending_assemble_externals_processed
$1 = true
We're not properly resetting state in varasm.cc after a compile
for libgccjit.
Fixed thusly.
gcc/ChangeLog:
PR jit/117275
* toplev.cc (toplev::finalize): Call varasm_cc_finalize.
* varasm.cc (varasm_cc_finalize): New.
* varasm.h (varasm_cc_finalize): New decl.
Signed-off-by: David Malcolm
Diff:
---
gcc/toplev.cc | 1 +
gcc/varasm.cc | 53 +
gcc/varasm.h | 2 ++
3 files changed, 56 insertions(+)
diff --git a/gcc/toplev.cc b/gcc/toplev.cc
index 5df59b79c803..62034c32b4af 100644
--- a/gcc/toplev.cc
+++ b/gcc/toplev.cc
@@ -2433,6 +2433,7 @@ toplev::finalize (void)
ira_costs_cc_finalize ();
tree_cc_finalize ();
reginfo_cc_finalize ();
+ varasm_cc_finalize ();
/* save_decoded_options uses opts_obstack, so these must
be cleaned up together. */
diff --git a/gcc/varasm.cc b/gcc/varasm.cc
index 8e492e37fb08..c25400554216 100644
--- a/gcc/varasm.cc
+++ b/gcc/varasm.cc
@@ -8854,4 +8854,57 @@ handle_vtv_comdat_section (section *sect, const_tree
decl ATTRIBUTE_UNUSED)
switch_to_comdat_section(sect, DECL_NAME (decl));
}
+void
+varasm_cc_finalize ()
+{
+ first_global_object_name = nullptr;
+ weak_global_object_name = nullptr;
+
+ const_labelno = 0;
+ size_directive_output = 0;
+
+ last_assemble_variable_decl = NULL_TREE;
+ first_function_block_is_cold = false;
+ saw_no_split_stack = false;
+ text_section = nullptr;
+ data_section = nullptr;
+ readonly_data_section = nullptr;
+ sdata_section = nullptr;
+ ctors_section = nullptr;
+ dtors_section = nullptr;
+ bss_section = nullptr;
+ sbss_section = nullptr;
+ tls_comm_section = nullptr;
+ comm_section = nullptr;
+ lcomm_section = nullptr;
+ bss_noswitch_section = nullptr;
+ exception_section = nullptr;
+ eh_frame_section = nullptr;
+ in_section = nullptr;
+ in_cold_section_p = false;
+ cold_function_name = NULL_TREE;
+ unnamed_sections = nullptr;
+ section_htab = nullptr;
+ object_block_htab = nullptr;
+ anchor_labelno = 0;
+ shared_constant_pool = nullptr;
+ pending_assemble_externals = NULL_TREE;
+ pending_libcall_symbols = nullptr;
+
+#ifdef ASM_OUTPUT_EXTERNAL
+ pending_assemble_externals_processed = false;
+ pending_assemble_externals_set = nullptr;
+#endif
+
+ weak_decls = NULL_TREE;
+ initial_trampoline = nullptr;
+ const_desc_htab = nullptr;
+ weakref_targets = NULL_TREE;
+ alias_pairs = nullptr;
+ tm_clone_hash = nullptr;
+ trampolines_created = 0;
+ elf_init_array_section = nullptr;
+ elf_fini_array_section = nullptr;
+}
+
#include "gt-varasm.h"
diff --git a/gcc/varasm.h b/gcc/varasm.h
index d9311dc370bb..f00ac7f3e5c9 100644
--- a/gcc/varasm.h
+++ b/gcc/varasm.h
@@ -81,4 +81,6 @@ extern rtx assemble_trampoline_template (void);
extern void switch_to_comdat_section (section *, tree);
+extern void varasm_cc_finalize ();
+
#endif // GCC_VARASM_H
[gcc r15-4582] ginclude: stdalign.h should define __xxx_is_defined macros for C++
https://gcc.gnu.org/g:5467f5b5ca6f2302573649b4a4f897793a9a6e7f
commit r15-4582-g5467f5b5ca6f2302573649b4a4f897793a9a6e7f
Author: Jonathan Wakely
Date: Tue Oct 22 16:26:27 2024 +0100
ginclude: stdalign.h should define __xxx_is_defined macros for C++
The __alignas_is_defined macro has been required by C++ since C++11, and
C++ Library DR 4036 clarified that __alignof_is_defined should be
defined too. The whole header was deprecated for C++23 (see
LWG 3827) and is likely to be removed for C++26 (see P3348), but we can
deal with that later.
The macros alignas and alignof should not be defined, as they're
keywords in C++.
gcc/ChangeLog:
* ginclude/stdalign.h (__alignas_is_defined): Define for C++.
(__alignof_is_defined): Likewise.
libstdc++-v3/ChangeLog:
* testsuite/18_support/headers/cstdalign/macros.cc: New test.
Diff:
---
gcc/ginclude/stdalign.h| 6 --
.../18_support/headers/cstdalign/macros.cc | 24 ++
2 files changed, 28 insertions(+), 2 deletions(-)
diff --git a/gcc/ginclude/stdalign.h b/gcc/ginclude/stdalign.h
index 5f82f2d68f27..980b1bba4e2c 100644
--- a/gcc/ginclude/stdalign.h
+++ b/gcc/ginclude/stdalign.h
@@ -26,12 +26,14 @@ see the files COPYING3 and COPYING.RUNTIME respectively.
If not, see
#ifndef _STDALIGN_H
#define _STDALIGN_H
-#if (!defined __cplusplus \
- && !(defined __STDC_VERSION__ && __STDC_VERSION__ > 201710L))
+#if !(defined __STDC_VERSION__ && __STDC_VERSION__ > 201710L)
+#ifndef __cplusplus
#define alignas _Alignas
#define alignof _Alignof
+#endif
+/* These are defined for C++, but deprecated in C++23. */
#define __alignas_is_defined 1
#define __alignof_is_defined 1
diff --git a/libstdc++-v3/testsuite/18_support/headers/cstdalign/macros.cc
b/libstdc++-v3/testsuite/18_support/headers/cstdalign/macros.cc
new file mode 100644
index ..c50c921cd59a
--- /dev/null
+++ b/libstdc++-v3/testsuite/18_support/headers/cstdalign/macros.cc
@@ -0,0 +1,24 @@
+// { dg-options "-D_GLIBCXX_USE_DEPRECATED=1 -Wno-deprecated" }
+// { dg-do preprocess { target c++11 } }
+
+#include
+
+#ifndef __alignas_is_defined
+# error "The header fails to define a macro named
__alignas_is_defined"
+#elif __alignas_is_defined != 1
+# error "__alignas_is_defined is not defined to 1 in "
+#endif
+
+#ifndef __alignof_is_defined
+# error "The header fails to define a macro named
__alignof_is_defined"
+#elif __alignof_is_defined != 1
+# error "__alignof_is_defined is not defined to 1 in "
+#endif
+
+#ifdef alignas
+# error "The header defines a macro named alignas"
+#endif
+
+#ifdef alignof
+# error "The header defines a macro named alignof"
+#endif
[gcc r12-10784] Fix ICE due to isa mismatch for the builtins.
https://gcc.gnu.org/g:ab84a8a4b78990942e006e9f060dc2705f2c6d8f commit r12-10784-gab84a8a4b78990942e006e9f060dc2705f2c6d8f Author: liuhongt Date: Tue Oct 22 01:54:40 2024 -0700 Fix ICE due to isa mismatch for the builtins. gcc/ChangeLog: PR target/117240 * config/i386/i386-builtin.def: Add avx/avx512f to vaes ymm/zmm builtins. gcc/testsuite/ChangeLog: * gcc.target/i386/pr117240_avx.c: New test. * gcc.target/i386/pr117240_avx512f.c: New test. (cherry picked from commit 403e361d5aa620e77c9832578b2409a0fdd79d96) Diff: --- gcc/config/i386/i386-builtin.def | 24 gcc/testsuite/gcc.target/i386/pr117240_avx.c | 10 ++ gcc/testsuite/gcc.target/i386/pr117240_avx512f.c | 10 ++ 3 files changed, 32 insertions(+), 12 deletions(-) diff --git a/gcc/config/i386/i386-builtin.def b/gcc/config/i386/i386-builtin.def index 4a180cad4671..64db1becca82 100644 --- a/gcc/config/i386/i386-builtin.def +++ b/gcc/config/i386/i386-builtin.def @@ -2751,18 +2751,18 @@ BDESC (0, OPTION_MASK_ISA2_AVX5124VNNIW, CODE_FOR_avx5124vnniw_vp4dpwssds_mask, BDESC (0, OPTION_MASK_ISA2_RDPID, CODE_FOR_rdpid, "__builtin_ia32_rdpid", IX86_BUILTIN_RDPID, UNKNOWN, (int) UNSIGNED_FTYPE_VOID) /* VAES. */ -BDESC (0, OPTION_MASK_ISA2_VAES, CODE_FOR_vaesdec_v16qi, "__builtin_ia32_vaesdec_v16qi", IX86_BUILTIN_VAESDEC16, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI) -BDESC (0, OPTION_MASK_ISA2_VAES, CODE_FOR_vaesdec_v32qi, "__builtin_ia32_vaesdec_v32qi", IX86_BUILTIN_VAESDEC32, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI) -BDESC (0, OPTION_MASK_ISA2_VAES, CODE_FOR_vaesdec_v64qi, "__builtin_ia32_vaesdec_v64qi", IX86_BUILTIN_VAESDEC64, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI) -BDESC (0, OPTION_MASK_ISA2_VAES, CODE_FOR_vaesdeclast_v16qi, "__builtin_ia32_vaesdeclast_v16qi", IX86_BUILTIN_VAESDECLAST16, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI) -BDESC (0, OPTION_MASK_ISA2_VAES, CODE_FOR_vaesdeclast_v32qi, "__builtin_ia32_vaesdeclast_v32qi", IX86_BUILTIN_VAESDECLAST32, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI) -BDESC (0, OPTION_MASK_ISA2_VAES, CODE_FOR_vaesdeclast_v64qi, "__builtin_ia32_vaesdeclast_v64qi", IX86_BUILTIN_VAESDECLAST64, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI) -BDESC (0, OPTION_MASK_ISA2_VAES, CODE_FOR_vaesenc_v16qi, "__builtin_ia32_vaesenc_v16qi", IX86_BUILTIN_VAESENC16, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI) -BDESC (0, OPTION_MASK_ISA2_VAES, CODE_FOR_vaesenc_v32qi, "__builtin_ia32_vaesenc_v32qi", IX86_BUILTIN_VAESENC32, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI) -BDESC (0, OPTION_MASK_ISA2_VAES, CODE_FOR_vaesenc_v64qi, "__builtin_ia32_vaesenc_v64qi", IX86_BUILTIN_VAESENC64, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI) -BDESC (0, OPTION_MASK_ISA2_VAES, CODE_FOR_vaesenclast_v16qi, "__builtin_ia32_vaesenclast_v16qi", IX86_BUILTIN_VAESENCLAST16, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI) -BDESC (0, OPTION_MASK_ISA2_VAES, CODE_FOR_vaesenclast_v32qi, "__builtin_ia32_vaesenclast_v32qi", IX86_BUILTIN_VAESENCLAST32, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI) -BDESC (0, OPTION_MASK_ISA2_VAES, CODE_FOR_vaesenclast_v64qi, "__builtin_ia32_vaesenclast_v64qi", IX86_BUILTIN_VAESENCLAST64, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI) +BDESC (OPTION_MASK_ISA_AVX512VL, OPTION_MASK_ISA2_VAES, CODE_FOR_vaesdec_v16qi, "__builtin_ia32_vaesdec_v16qi", IX86_BUILTIN_VAESDEC16, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI) +BDESC (OPTION_MASK_ISA_AVX, OPTION_MASK_ISA2_VAES, CODE_FOR_vaesdec_v32qi, "__builtin_ia32_vaesdec_v32qi", IX86_BUILTIN_VAESDEC32, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI) +BDESC (OPTION_MASK_ISA_AVX512F, OPTION_MASK_ISA2_VAES, CODE_FOR_vaesdec_v64qi, "__builtin_ia32_vaesdec_v64qi", IX86_BUILTIN_VAESDEC64, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI) +BDESC (OPTION_MASK_ISA_AVX512VL, OPTION_MASK_ISA2_VAES, CODE_FOR_vaesdeclast_v16qi, "__builtin_ia32_vaesdeclast_v16qi", IX86_BUILTIN_VAESDECLAST16, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI) +BDESC (OPTION_MASK_ISA_AVX, OPTION_MASK_ISA2_VAES, CODE_FOR_vaesdeclast_v32qi, "__builtin_ia32_vaesdeclast_v32qi", IX86_BUILTIN_VAESDECLAST32, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI) +BDESC (OPTION_MASK_ISA_AVX512F, OPTION_MASK_ISA2_VAES, CODE_FOR_vaesdeclast_v64qi, "__builtin_ia32_vaesdeclast_v64qi", IX86_BUILTIN_VAESDECLAST64, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI) +BDESC (OPTION_MASK_ISA_AVX512VL, OPTION_MASK_ISA2_VAES, CODE_FOR_vaesenc_v16qi, "__builtin_ia32_vaesenc_v16qi", IX86_BUILTIN_VAESENC16, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI) +BDESC (OPTION_MASK_ISA_AVX, OPTION_MASK_ISA2_VAES, CODE_FOR_vaesenc_v32qi, "__builtin_ia32_vaesenc_v32qi", IX86_BUILTIN_VAESENC32, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI) +BDESC (OPTION_MASK_ISA_AVX512F, OPTION_MASK_ISA2_VAES, CODE_FOR_vaesenc_v64qi, "__builtin_ia32_vaesenc_v64qi", IX86_BUILTIN_VAESENC64, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI) +BDESC (OPTION_MASK_ISA_AVX512VL, OPTION_MASK_ISA2_VAES, CODE_FOR_vaesenclast
[gcc(refs/users/meissner/heads/work182-sha)] Update ChangeLog.*
https://gcc.gnu.org/g:7c35e95432f13e7d9a0cfa8ffc70cdfea2a2314e commit 7c35e95432f13e7d9a0cfa8ffc70cdfea2a2314e Author: Michael Meissner Date: Wed Oct 23 13:31:23 2024 -0400 Update ChangeLog.* Diff: --- gcc/ChangeLog.sha | 26 ++ 1 file changed, 26 insertions(+) diff --git a/gcc/ChangeLog.sha b/gcc/ChangeLog.sha index 402ab7534d33..fe43d0cb19a8 100644 --- a/gcc/ChangeLog.sha +++ b/gcc/ChangeLog.sha @@ -1,3 +1,29 @@ + Branch work182-sha, patch #402 + +Add missing test. + +2024-10-16 Michael Meissner + +gcc/testsuite/ + + * gcc.target/powerpc/vector-rotate-left.c: New test. + + Branch work182-sha, patch #401 + +Add potential p-future XVRLD and XVRLDI instructions. + +2024-10-16 Michael Meissner + +gcc/ + + * config/rs6000/altivec.md (altivec_vrl): Add support for a + possible XVRLD instruction in the future. + (altivec_vrl_immediate): New insns. + * config/rs6000/predicates.md (vector_shift_immediate): New predicate. + * config/rs6000/rs6000.h (TARGET_XVRLW): New macro. + * config/rs6000/rs6000.md (isa attribute): Add xvrlw. + (enabled attribute): Add support for xvrlw. + Branch work182-sha, patch #400 Initial support for adding xxeval fusion support.
[gcc r15-4589] [PATCH] RISC-V: override alignment of function/jump/loop
https://gcc.gnu.org/g:078f7c4f1fcf4d7099d855afb02dbaf71bebddbf
commit r15-4589-g078f7c4f1fcf4d7099d855afb02dbaf71bebddbf
Author: Wang Pengcheng
Date: Wed Oct 23 23:11:53 2024 -0600
[PATCH] RISC-V: override alignment of function/jump/loop
Just like what AArch64 has done.
Signed-off-by: Wang Pengcheng
gcc/ChangeLog:
* config/riscv/riscv.cc (struct riscv_tune_param): Add new
tune options.
(riscv_override_options_internal): Override the default alignment
when not optimizing for size.
Diff:
---
gcc/config/riscv/riscv.cc | 15 +++
1 file changed, 15 insertions(+)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 3ac40234345a..7d6fc1429b55 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -295,6 +295,9 @@ struct riscv_tune_param
bool overlap_op_by_pieces;
unsigned int fusible_ops;
const struct cpu_vector_cost *vec_costs;
+ const char *function_align = nullptr;
+ const char *jump_align = nullptr;
+ const char *loop_align = nullptr;
};
@@ -10283,6 +10286,18 @@ riscv_override_options_internal (struct gcc_options
*opts)
? &optimize_size_tune_info
: cpu->tune_param;
+ /* If not optimizing for size, set the default
+ alignment to what the target wants. */
+ if (!opts->x_optimize_size)
+{
+ if (opts->x_flag_align_loops && !opts->x_str_align_loops)
+ opts->x_str_align_loops = tune_param->loop_align;
+ if (opts->x_flag_align_jumps && !opts->x_str_align_jumps)
+ opts->x_str_align_jumps = tune_param->jump_align;
+ if (opts->x_flag_align_functions && !opts->x_str_align_functions)
+ opts->x_str_align_functions = tune_param->function_align;
+}
+
/* Use -mtune's setting for slow_unaligned_access, even when optimizing
for size. For architectures that trap and emulate unaligned accesses,
the performance cost is too great, even for -Os. Similarly, if
[gcc r15-4586] RISC-V: Add testcases for form 4 of signed vector SAT_ADD
https://gcc.gnu.org/g:03b469ee4768118807a3c74891c3c426b0c145ef
commit r15-4586-g03b469ee4768118807a3c74891c3c426b0c145ef
Author: Pan Li
Date: Mon Sep 23 13:43:50 2024 +0800
RISC-V: Add testcases for form 4 of signed vector SAT_ADD
Form 4:
#define DEF_VEC_SAT_S_ADD_FMT_4(T, UT, MIN, MAX) \
void __attribute__((noinline)) \
vec_sat_s_add_##T##_fmt_4 (T *out, T *op_1, T *op_2, unsigned limit) \
{\
unsigned i;\
for (i = 0; i < limit; i++)\
{\
T x = op_1[i]; \
T y = op_2[i]; \
T sum; \
bool overflow = __builtin_add_overflow (x, y, &sum); \
out[i] = !overflow ? sum : x < 0 ? MIN : MAX; \
}\
}
DEF_VEC_SAT_S_ADD_FMT_4 (int8_t, uint8_t, INT8_MIN, INT8_MAX)
The below test are passed for this patch.
* The rv64gcv fully regression test.
It is test only patch and obvious up to a point, will commit it
directly if no comments in next 48H.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/vec_sat_arith.h: Add test helper
macros.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-13.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-14.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-15.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-16.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-run-13.c: New
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-run-14.c: New
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-run-15.c: New
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-run-16.c: New
test.
Signed-off-by: Pan Li
Signed-off-by: Pan Li
Diff:
---
.../riscv/rvv/autovec/binop/vec_sat_s_add-13.c | 9 +
.../riscv/rvv/autovec/binop/vec_sat_s_add-14.c | 9 +
.../riscv/rvv/autovec/binop/vec_sat_s_add-15.c | 9 +
.../riscv/rvv/autovec/binop/vec_sat_s_add-16.c | 9 +
.../riscv/rvv/autovec/binop/vec_sat_s_add-run-13.c | 17 +
.../riscv/rvv/autovec/binop/vec_sat_s_add-run-14.c | 17 +
.../riscv/rvv/autovec/binop/vec_sat_s_add-run-15.c | 17 +
.../riscv/rvv/autovec/binop/vec_sat_s_add-run-16.c | 17 +
.../gcc.target/riscv/rvv/autovec/vec_sat_arith.h | 22 ++
9 files changed, 126 insertions(+)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-13.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-13.c
new file mode 100644
index ..ec3f8aee434f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-13.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+
+#include "../vec_sat_arith.h"
+
+DEF_VEC_SAT_S_ADD_FMT_4(int8_t, uint8_t, INT8_MIN, INT8_MAX)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
+/* { dg-final { scan-assembler-times {vsadd\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-14.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-14.c
new file mode 100644
index ..5542616c90ab
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-14.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+
+#include "../vec_sat_arith.h"
+
+DEF_VEC_SAT_S_ADD_FMT_4(int16_t, uint16_t, INT16_MIN, INT16_MAX)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
+/* { dg-final { scan-assembler-times {vsadd\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-15.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-15.c
new file mode 100644
index ..091bfd15edf3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-15.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+
+#include "../vec_sat_arith.h"
+
+DEF_VEC_SAT_S_ADD_FMT_4(int32_t, uint32_t, INT32_MIN, INT32_MAX)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } }
[gcc r15-4588] libffi: LoongArch: Fix soft-float builds of libffi
https://gcc.gnu.org/g:a616b7e1db7319c587b9c65fe9548c59c67d1234
commit r15-4588-ga616b7e1db7319c587b9c65fe9548c59c67d1234
Author: Yang Yujie
Date: Sat Jan 27 15:09:46 2024 +0800
libffi: LoongArch: Fix soft-float builds of libffi
This patch correspond to the upstream PR:
https://github.com/libffi/libffi/pull/817
And has been merged.
libffi/ChangeLog:
* src/loongarch64/ffi.c: Avoid defining floats
in struct call_context if the ABI is soft-float.
Diff:
---
libffi/src/loongarch64/ffi.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/libffi/src/loongarch64/ffi.c b/libffi/src/loongarch64/ffi.c
index 140be3bc3dc4..01c2e18a395f 100644
--- a/libffi/src/loongarch64/ffi.c
+++ b/libffi/src/loongarch64/ffi.c
@@ -58,7 +58,9 @@
*/
typedef struct call_context
{
+#if !defined(__loongarch_soft_float)
ABI_FLOAT fa[8];
+#endif
size_t a[10];
} call_context;
[gcc r15-4581] top-level: Add pull request template for Forgejo
https://gcc.gnu.org/g:f342d66d6990b9559dde13e616a2921a7bfae176 commit r15-4581-gf342d66d6990b9559dde13e616a2921a7bfae176 Author: Jonathan Wakely Date: Wed Oct 23 15:20:27 2024 +0100 top-level: Add pull request template for Forgejo ChangeLog: * .forgejo/PULL_REQUEST_TEMPLATE.md: New file. Diff: --- .forgejo/PULL_REQUEST_TEMPLATE.md | 9 + 1 file changed, 9 insertions(+) diff --git a/.forgejo/PULL_REQUEST_TEMPLATE.md b/.forgejo/PULL_REQUEST_TEMPLATE.md new file mode 100644 index ..fc645f11305c --- /dev/null +++ b/.forgejo/PULL_REQUEST_TEMPLATE.md @@ -0,0 +1,9 @@ +Thanks for taking the time to contribute to GCC! + +Please be advised that https://forge.sourceware.org/ is currently a trial +that is being used by the GCC community to experiment with a new workflow +based on pull requests. + +Pull requests sent here may be forgotten or ignored. Patches that you want to +propose for inclusion in GCC should use the existing email-based workflow, +see https://gcc.gnu.org/contribute.html
[gcc r15-4587] testsuite: Fix up pr116488.c and pr117226.c tests [PR116488]
https://gcc.gnu.org/g:8df549fc2c0297970cb3bcadba7929088af96522
commit r15-4587-g8df549fc2c0297970cb3bcadba7929088af96522
Author: Jakub Jelinek
Date: Wed Oct 23 21:21:13 2024 -0600
testsuite: Fix up pr116488.c and pr117226.c tests [PR116488]
Hi!
On Mon, Oct 21, 2024 at 01:39:52PM -0600, Jeff Law wrote:
> * gcc.dg/torture/pr116488.c: New test.
> * gcc.dg/torture/pr117226.c: New test.
These two tests FAIL on powerpc64le-linux (and I assume on all other
-funsigned-char defaulting targets).
The following patch fixes that, tested on powerpc64le-linux and
x86_64-linux (-m32/-m64); on x86_64 also tested before/after with
-funsigned-char.
Ok for trunk?
2024-10-22 Jakub Jelinek
PR rtl-optimization/116488
PR rtl-optimization/117226
* gcc.dg/torture/pr116488.c (c, e): Change type from char to
signed char.
* gcc.dg/torture/pr117226.c (main): Change f type from char to
signed char.
Diff:
---
gcc/testsuite/gcc.dg/torture/pr116488.c | 2 +-
gcc/testsuite/gcc.dg/torture/pr117226.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/gcc/testsuite/gcc.dg/torture/pr116488.c
b/gcc/testsuite/gcc.dg/torture/pr116488.c
index 9ead1298eb14..90457bb93158 100644
--- a/gcc/testsuite/gcc.dg/torture/pr116488.c
+++ b/gcc/testsuite/gcc.dg/torture/pr116488.c
@@ -1,7 +1,7 @@
/* { dg-do run } */
/* { dg-additional-options "-fno-forward-propagate" } */
int a, b;
-char c, e;
+signed char c, e;
unsigned char d;
__attribute__ ((noinline,noclone,noipa))
void f(int g, short h) {
diff --git a/gcc/testsuite/gcc.dg/torture/pr117226.c
b/gcc/testsuite/gcc.dg/torture/pr117226.c
index 2bb35a12b2b9..ac71a81e81fa 100644
--- a/gcc/testsuite/gcc.dg/torture/pr117226.c
+++ b/gcc/testsuite/gcc.dg/torture/pr117226.c
@@ -5,7 +5,7 @@
int a = 128, b, d;
long e = -2, c;
int main() {
- char f = a;
+ signed char f = a;
int g = f;
c = (g < 0) - e;
unsigned char h = g;
