[gcc r15-3889] testsuite: fix comment-only directive typos

[Sam James via Gcc-cvs]

https://gcc.gnu.org/g:98aac7c67f776601143f5d25353a304f72e87f54

commit r15-3889-g98aac7c67f776601143f5d25353a304f72e87f54
Author: Sam James 
Date:   Mon Aug 5 05:01:17 2024 +0100

testsuite: fix comment-only directive typos

Doing this to avoid FPs from grepping but also to avoid the potential
for people learning bad habits.

gcc/testsuite/ChangeLog:

* gfortran.dg/coarray/caf.exp: Fix 'dg-do-run' typo.
* lib/gfortran-dg.exp: Ditto.
* lib/gm2-dg.exp: Ditto.
* lib/go-dg.exp: Ditto.

Diff:
---
 gcc/testsuite/gfortran.dg/coarray/caf.exp | 2 +-
 gcc/testsuite/lib/gfortran-dg.exp | 2 +-
 gcc/testsuite/lib/gm2-dg.exp  | 2 +-
 gcc/testsuite/lib/go-dg.exp   | 2 +-
 4 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/gcc/testsuite/gfortran.dg/coarray/caf.exp 
b/gcc/testsuite/gfortran.dg/coarray/caf.exp
index 31c13cd34e5e..9e608ecf83d0 100644
--- a/gcc/testsuite/gfortran.dg/coarray/caf.exp
+++ b/gcc/testsuite/gfortran.dg/coarray/caf.exp
@@ -78,7 +78,7 @@ foreach test [lsort [glob -nocomplain 
$srcdir/$subdir/*.\[fF\]{,90,95,03,08} ]]
 }
 
 # Enable if you want to test several options:
-## look if this is dg-do-run test, in which case
+## look if this is dg-do run test, in which case
 ## we cycle through the option list, otherwise we don't
 #if [expr [search_for $test "dg-do run"]] {
 #  set option_list $torture_with_loops
diff --git a/gcc/testsuite/lib/gfortran-dg.exp 
b/gcc/testsuite/lib/gfortran-dg.exp
index 2edc09e5c995..726941c757f2 100644
--- a/gcc/testsuite/lib/gfortran-dg.exp
+++ b/gcc/testsuite/lib/gfortran-dg.exp
@@ -146,7 +146,7 @@ proc gfortran-dg-runtest { testcases flags 
default-extra-flags } {
continue
 }
 
-   # look if this is dg-do-run test, in which case
+   # look if this is dg-do run test, in which case
# we cycle through the option list, otherwise we don't
if [expr [search_for $test "dg-do run"]] {
set option_list $torture_with_loops
diff --git a/gcc/testsuite/lib/gm2-dg.exp b/gcc/testsuite/lib/gm2-dg.exp
index 7230143f80e8..0fa26846df84 100644
--- a/gcc/testsuite/lib/gm2-dg.exp
+++ b/gcc/testsuite/lib/gm2-dg.exp
@@ -59,7 +59,7 @@ proc gm2-dg-runtest { testcases flags default-extra-flags } {
continue
 }
 
-   # look if this is dg-do-run test, in which case
+   # look if this is dg-do run test, in which case
# we cycle through the option list, otherwise we don't
if [expr [search_for $test "dg-do run"]] {
set option_list $TORTURE_OPTIONS
diff --git a/gcc/testsuite/lib/go-dg.exp b/gcc/testsuite/lib/go-dg.exp
index d22835066252..bbc70a2301fd 100644
--- a/gcc/testsuite/lib/go-dg.exp
+++ b/gcc/testsuite/lib/go-dg.exp
@@ -47,7 +47,7 @@ proc go-dg-runtest { testcases flags default-extra-flags } {
continue
 }
 
-   # look if this is dg-do-run test, in which case
+   # look if this is dg-do run test, in which case
# we cycle through the option list, otherwise we don't
if [expr [search_for $test "dg-do run"]] {
set option_list $TORTURE_OPTIONS

[gcc r15-3890] testsuite: fix hyphen typos

[Sam James via Gcc-cvs]

https://gcc.gnu.org/g:34bf6aa41ba5390ce26eb40208f10186d0ab17c4

commit r15-3890-g34bf6aa41ba5390ce26eb40208f10186d0ab17c4
Author: Sam James 
Date:   Fri Aug 2 06:38:34 2024 +0100

testsuite: fix hyphen typos

gcc/testsuite/ChangeLog:

* g++.dg/modules/reparent-1_c.C: Fix whitespace around '-' in dg 
directive.
* gfortran.dg/initialization_25.f90: Ditto.

Diff:
---
 gcc/testsuite/g++.dg/modules/reparent-1_c.C | 2 +-
 gcc/testsuite/gfortran.dg/initialization_25.f90 | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/gcc/testsuite/g++.dg/modules/reparent-1_c.C 
b/gcc/testsuite/g++.dg/modules/reparent-1_c.C
index e4e984c87a9d..d3f7f51e335b 100644
--- a/gcc/testsuite/g++.dg/modules/reparent-1_c.C
+++ b/gcc/testsuite/g++.dg/modules/reparent-1_c.C
@@ -6,4 +6,4 @@ int main ()
   v (0); // { dg-error "too many arguments" }
 }
 
-// { dg -regexp {In module foo, imported at [^\n]*/reparent-1_b.C:14,\nof 
module bar, imported at [^\n]*/reparent-1_c.C:2:\n[^\n]*/reparent-1_a.C:6:13: 
note: declared here\n} }
+// { dg-regexp {In module foo, imported at [^\n]*/reparent-1_b.C:14,\nof 
module bar, imported at [^\n]*/reparent-1_c.C:2:\n[^\n]*/reparent-1_a.C:6:13: 
note: declared here\n} }
diff --git a/gcc/testsuite/gfortran.dg/initialization_25.f90 
b/gcc/testsuite/gfortran.dg/initialization_25.f90
index 66c447e2f1cb..c8edb163be04 100644
--- a/gcc/testsuite/gfortran.dg/initialization_25.f90
+++ b/gcc/testsuite/gfortran.dg/initialization_25.f90
@@ -1,12 +1,12 @@
 ! { dg-do compile }
 !
 ! PR fortran/35779 - unrelated error message
-! Tescase contributed by
+! Testcase contributed by
 ! Dick Hendrickson 
 !
 ! Initial patch was reverted as it broke nested loops (see 
initialization_26.f90).
 !
 
 !   INTEGER :: J1
-!   INTEGER,PARAMETER :: I2(10) = (/(J1,J1=its_bad,1,-1)/) ! { dg - error 
"does not reduce" }
+!   INTEGER,PARAMETER :: I2(10) = (/(J1,J1=its_bad,1,-1)/) ! { dg-error "does 
not reduce" }
 END

[gcc r15-3891] pretty-print: Fix up allocate_object

[Jakub Jelinek via Gcc-cvs]

https://gcc.gnu.org/g:9dc1ab9062e93ae178830d66d5850406777a477d

commit r15-3891-g9dc1ab9062e93ae178830d66d5850406777a477d
Author: Jakub Jelinek 
Date:   Thu Sep 26 11:55:13 2024 +0200

pretty-print: Fix up allocate_object

On Thu, Aug 29, 2024 at 06:58:12PM -0400, David Malcolm wrote:
> The following patch rewrites the internals of pp_format.

> The tokens and token lists are allocated on the chunk_obstack, and so
> there's no additional heap activity required, with the memory reclaimed
> when the chunk_obstack is freed after phase 3 of formatting.

> +static void *
> +allocate_object (size_t sz, obstack &s)
> +{
> +  /* We must not be half-way through an object.  */
> +  gcc_assert (obstack_base (&s) == obstack_next_free (&s));
> +
> +  obstack_grow (&s, obstack_base (&s), sz);
> +  void *buf = obstack_finish (&s);
> +  return buf;
>  }

I think this is wrong.  I hoped it would be the reason of the
unexpected libstdc++ warnings on certain architectures after
seeing
==4027220== Source and destination overlap in memcpy(0x4627154, 0x4627154, 
12)
==4027220==at 0x404B93E: memcpy (vg_replace_strmem.c:1123)
==4027220==by 0xAAD5618: allocate_object(unsigned int, obstack&) 
(pretty-print.cc:1183)
==4027220==by 0xAAD8C0E: operator new (pretty-print.cc:1210)
==4027220==by 0xAAD8C0E: make (pretty-print-format-impl.h:305)
==4027220==by 0xAAD8C0E: format_phase_1 (pretty-print.cc:1659)
==4027220==by 0xAAD8C0E: pretty_printer::format(text_info&) 
(pretty-print.cc:1618)
==4027220==by 0xAAA840E: pp_format (pretty-print.h:583)
==4027220==by 0xAAA840E: 
diagnostic_context::report_diagnostic(diagnostic_info*) (diagnostic.cc:1260)
==4027220==by 0xAAA8703: 
diagnostic_context::diagnostic_impl(rich_location*, diagnostic_metadata const*, 
diagnostic_option_id, char const*, char**, diagnostic_t) (diagnostic.cc:1404)
==4027220==by 0xAAB8682: warning(diagnostic_option_id, char const*, 
...) (diagnostic-global-context.cc:166)
==4027220==by 0x97725F5: warn_deprecated_use(tree_node*, tree_node*) 
(tree.cc:12485)
==4027220==by 0x8B6694B: mark_used(tree_node*, int) (decl2.cc:6121)
==4027220==by 0x8C9E25E: tsubst_expr(tree_node*, tree_node*, int, 
tree_node*) [clone .part.0] (pt.cc:21626)
==4027220==by 0x8C9E5E6: tsubst_expr(tree_node*, tree_node*, int, 
tree_node*) [clone .part.0] (pt.cc:20935)
==4027220==by 0x8C9E1D7: tsubst_expr(tree_node*, tree_node*, int, 
tree_node*) [clone .part.0] (pt.cc:20424)
==4027220==by 0x8C9DF2E: tsubst_expr(tree_node*, tree_node*, int, 
tree_node*) [clone .part.0] (pt.cc:20496)
==4027220==
etc. valgrind warnings, unfortunately it is not, but still
I think this is a bug.
If the obstack has enough space in it, i.e. if obstack_room (&s) >= sz,
then obstack_grow from obstack_base will copy uninitialized bytes
through memcpy (obstack_base (&s), obstack_base (&s), sz);
(which pedantically isn't valid due to the overlap, and so
the reason why valgrind complains, but in reality I think most
implementations can handle it fine, after all, we also use it for
structure assignments which could have full or no overlap but never
partial).
If obstack_room (&s) < sz, then obstack_grow will first
_obstack_newchunk (&s, sz); which will allocate new memory and
copy the existing data of the object (but the above assertion
guartantees it will copy 0 bytes) and then the memcpy copies
sz bytes from the old base to the new (if unlucky, that could crash
as there could be end of page and unmapped next page in between).

I think we should use obstack_blank instead of obstack_grow, which
does everything obstack_grow does, except for the memcpy of the
uninitialized data.

2024-09-25  Jakub Jelinek  

* pretty-print.cc (allocate_object): Use obstack_blank rather than
obstack_grow.

Diff:
---
 gcc/pretty-print.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/pretty-print.cc b/gcc/pretty-print.cc
index 0cd9b4d0a416..68c145e2d532 100644
--- a/gcc/pretty-print.cc
+++ b/gcc/pretty-print.cc
@@ -1180,7 +1180,7 @@ allocate_object (size_t sz, obstack &s)
   /* We must not be half-way through an object.  */
   gcc_assert (obstack_base (&s) == obstack_next_free (&s));
 
-  obstack_grow (&s, obstack_base (&s), sz);
+  obstack_blank (&s, sz);
   void *buf = obstack_finish (&s);
   return buf;
 }

[gcc r15-3888] doc: Remove MinGW note on binutils 2.16

[Gerald Pfeifer via Gcc-cvs]

https://gcc.gnu.org/g:27003e5d6eadcddde617b89f11bab47ab75cc203

commit r15-3888-g27003e5d6eadcddde617b89f11bab47ab75cc203
Author: Gerald Pfeifer 
Date:   Wed Sep 25 21:43:29 2024 +0800

doc: Remove MinGW note on binutils 2.16

Binutils 2.16 is 13 years old; no need to specifically refer to it as a
requirement.

gcc:
PR target/69374
* doc/install.texi (Specific) <*-*-mingw32>: Remove note regarding
binutils 2.16.

Diff:
---
 gcc/doc/install.texi | 4 
 1 file changed, 4 deletions(-)

diff --git a/gcc/doc/install.texi b/gcc/doc/install.texi
index e339d736969a..08de972c8ec7 100644
--- a/gcc/doc/install.texi
+++ b/gcc/doc/install.texi
@@ -5211,10 +5211,6 @@ GCC will build with and support only MinGW runtime 3.12 
and later.
 Earlier versions of headers are incompatible with the new default semantics
 of @code{extern inline} in @code{-std=c99} and @code{-std=gnu99} modes.
 
-To support emitting DWARF debugging info you need to use GNU binutils
-version 2.16 or above containing support for the @code{.secrel32}
-assembler pseudo-op.
-
 @html
 
 @end html

[gcc r15-3894] libstdc++: Suppress an attribute suggestion warning [PR116853].

[Iain D Sandoe via Libstdc++-cvs]

https://gcc.gnu.org/g:d797202caa34f008399dc65e10cc723f52fcbcc5

commit r15-3894-gd797202caa34f008399dc65e10cc723f52fcbcc5
Author: Iain Sandoe 
Date:   Thu Sep 26 11:07:41 2024 +0100

libstdc++: Suppress an attribute suggestion warning [PR116853].

This warning is triggering during the build and breaking bootstrap on
at least two targets.  The warning appears valid, but the final fix for
it is not yet clear.

In the meantime, to restore bootstrap, the following patch ignores the
warning in the relevant code section.

PR libstdc++/116853

libstdc++-v3/ChangeLog:

* include/bits/basic_string.h: Ignore suggest-attribute=format
warning when using posix vsnprintf in to_string() implementations.

Signed-off-by: Iain Sandoe 

Diff:
---
 libstdc++-v3/include/bits/basic_string.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/libstdc++-v3/include/bits/basic_string.h 
b/libstdc++-v3/include/bits/basic_string.h
index 976577f8f22d..e9b17ea48b5a 100644
--- a/libstdc++-v3/include/bits/basic_string.h
+++ b/libstdc++-v3/include/bits/basic_string.h
@@ -4399,6 +4399,8 @@ _GLIBCXX_BEGIN_NAMESPACE_CXX11
 return __str;
   }
 #elif _GLIBCXX_USE_C99_STDIO
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wsuggest-attribute=format"
   // NB: (v)snprintf vs sprintf.
 
   _GLIBCXX_NODISCARD
@@ -4430,6 +4432,7 @@ _GLIBCXX_BEGIN_NAMESPACE_CXX11
 return __gnu_cxx::__to_xstring(&std::vsnprintf, __n,
   "%Lf", __val);
   }
+#pragma GCC diagnostic pop
 #endif // _GLIBCXX_USE_C99_STDIO
 
 #if defined(_GLIBCXX_USE_WCHAR_T) && _GLIBCXX_USE_C99_WCHAR

[gcc r15-3895] Fortran/OpenMP: Middle-end support for mapping of DT with allocatable components

[Tobias Burnus via Gcc-cvs]

https://gcc.gnu.org/g:e4a58b6f28383cb40e4fa287cc7dad43bafb85b2

commit r15-3895-ge4a58b6f28383cb40e4fa287cc7dad43bafb85b2
Author: Tobias Burnus 
Date:   Thu Sep 26 14:01:20 2024 +0200

Fortran/OpenMP: Middle-end support for mapping of DT with allocatable 
components

gcc/ChangeLog:

* langhooks-def.h (lhd_omp_deep_mapping_p,
lhd_omp_deep_mapping_cnt, lhd_omp_deep_mapping): New.
(LANG_HOOKS_OMP_DEEP_MAPPING_P, LANG_HOOKS_OMP_DEEP_MAPPING_CNT,
LANG_HOOKS_OMP_DEEP_MAPPING): Define.
(LANG_HOOKS_DECLS): Use it.
* langhooks.cc (lhd_omp_deep_mapping_p, lhd_omp_deep_mapping_cnt,
lhd_omp_deep_mapping): New stubs.
* langhooks.h (struct lang_hooks_for_decls): Add new hooks
* omp-expand.cc (expand_omp_target): Handle dynamic-size
addr/sizes/kinds arrays.
* omp-low.cc (build_sender_ref, fixup_child_record_type,
scan_sharing_clauses, lower_omp_target): Update to handle
new hooks and dynamic-size addr/sizes/kinds arrays.

Diff:
---
 gcc/langhooks-def.h |  10 +++
 gcc/langhooks.cc|  24 ++
 gcc/langhooks.h |  15 
 gcc/omp-expand.cc   |  18 -
 gcc/omp-low.cc  | 224 ++--
 5 files changed, 265 insertions(+), 26 deletions(-)

diff --git a/gcc/langhooks-def.h b/gcc/langhooks-def.h
index 179ed393fd29..f207ff96f0df 100644
--- a/gcc/langhooks-def.h
+++ b/gcc/langhooks-def.h
@@ -86,6 +86,10 @@ extern enum omp_clause_defaultmap_kind 
lhd_omp_predetermined_mapping (tree);
 extern tree lhd_omp_assignment (tree, tree, tree);
 extern void lhd_omp_finish_clause (tree, gimple_seq *, bool);
 extern tree lhd_omp_array_size (tree, gimple_seq *);
+extern bool lhd_omp_deep_mapping_p (const gimple *, tree);
+extern tree lhd_omp_deep_mapping_cnt (const gimple *, tree, gimple_seq *);
+extern void lhd_omp_deep_mapping (const gimple *, tree, unsigned HOST_WIDE_INT,
+ tree, tree, tree, tree, tree, gimple_seq *);
 struct gimplify_omp_ctx;
 extern void lhd_omp_firstprivatize_type_sizes (struct gimplify_omp_ctx *,
   tree);
@@ -272,6 +276,9 @@ extern tree lhd_unit_size_without_reusable_padding (tree);
 #define LANG_HOOKS_OMP_CLAUSE_LINEAR_CTOR NULL
 #define LANG_HOOKS_OMP_CLAUSE_DTOR hook_tree_tree_tree_null
 #define LANG_HOOKS_OMP_FINISH_CLAUSE lhd_omp_finish_clause
+#define LANG_HOOKS_OMP_DEEP_MAPPING_P lhd_omp_deep_mapping_p
+#define LANG_HOOKS_OMP_DEEP_MAPPING_CNT lhd_omp_deep_mapping_cnt
+#define LANG_HOOKS_OMP_DEEP_MAPPING lhd_omp_deep_mapping
 #define LANG_HOOKS_OMP_ALLOCATABLE_P hook_bool_tree_false
 #define LANG_HOOKS_OMP_SCALAR_P lhd_omp_scalar_p
 #define LANG_HOOKS_OMP_SCALAR_TARGET_P hook_bool_tree_false
@@ -306,6 +313,9 @@ extern tree lhd_unit_size_without_reusable_padding (tree);
   LANG_HOOKS_OMP_CLAUSE_LINEAR_CTOR, \
   LANG_HOOKS_OMP_CLAUSE_DTOR, \
   LANG_HOOKS_OMP_FINISH_CLAUSE, \
+  LANG_HOOKS_OMP_DEEP_MAPPING_P, \
+  LANG_HOOKS_OMP_DEEP_MAPPING_CNT, \
+  LANG_HOOKS_OMP_DEEP_MAPPING, \
   LANG_HOOKS_OMP_ALLOCATABLE_P, \
   LANG_HOOKS_OMP_SCALAR_P, \
   LANG_HOOKS_OMP_SCALAR_TARGET_P, \
diff --git a/gcc/langhooks.cc b/gcc/langhooks.cc
index b28c01deed21..54fc94e4364e 100644
--- a/gcc/langhooks.cc
+++ b/gcc/langhooks.cc
@@ -645,6 +645,30 @@ lhd_omp_array_size (tree, gimple_seq *)
   return NULL_TREE;
 }
 
+/* Returns true when additional mappings for a decl are needed.  */
+
+bool
+lhd_omp_deep_mapping_p (const gimple *, tree)
+{
+  return false;
+}
+
+/* Returns number of additional mappings for a decl.  */
+
+tree
+lhd_omp_deep_mapping_cnt (const gimple *, tree, gimple_seq *)
+{
+  return NULL_TREE;
+}
+
+/* Do the additional mappings.  */
+
+void
+lhd_omp_deep_mapping (const gimple *, tree, unsigned HOST_WIDE_INT, tree, tree,
+ tree, tree, tree, gimple_seq *)
+{
+}
+
 /* Return true if DECL is a scalar variable (for the purpose of
implicit firstprivatization & mapping). Only if alloc_ptr_ok
are allocatables and pointers accepted. */
diff --git a/gcc/langhooks.h b/gcc/langhooks.h
index cd944673cd62..87c3c58a6b34 100644
--- a/gcc/langhooks.h
+++ b/gcc/langhooks.h
@@ -313,6 +313,21 @@ struct lang_hooks_for_decls
   /* Do language specific checking on an implicitly determined clause.  */
   void (*omp_finish_clause) (tree clause, gimple_seq *pre_p, bool);
 
+  /* Additional language-specific mappings for a decl; returns true
+ if those may occur.  */
+  bool (*omp_deep_mapping_p) (const gimple *ctx_stmt, tree clause);
+
+  /* Additional language-specific mappings for a decl; returns the
+ number of additional mappings needed.  */
+  tree (*omp_deep_mapping_cnt) (const gimple *ctx_stmt, tree clause,
+   gimple_seq *seq);
+
+  /* Do the actual additional language-specific mappings for a decl. */
+  void (*omp_deep_mapping) (const gimple *stmt, tree clause,
+   

[gcc r15-3897] Add virtual destructor to AbstractExpr

[Marc Poulhi?s via Gcc-cvs]

https://gcc.gnu.org/g:6f76ce80fa25559c9e1bd575190be80c1159d398

commit r15-3897-g6f76ce80fa25559c9e1bd575190be80c1159d398
Author: Owen Avery 
Date:   Tue Sep 3 16:11:58 2024 -0400

Add virtual destructor to AbstractExpr

gcc/rust/ChangeLog:

* checks/errors/borrowck/rust-bir.h
(class AbstractExpr): Add virtual destructor.

Signed-off-by: Owen Avery 

Diff:
---
 gcc/rust/checks/errors/borrowck/rust-bir.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/gcc/rust/checks/errors/borrowck/rust-bir.h 
b/gcc/rust/checks/errors/borrowck/rust-bir.h
index 4c298f147736..ed1f44686bc3 100644
--- a/gcc/rust/checks/errors/borrowck/rust-bir.h
+++ b/gcc/rust/checks/errors/borrowck/rust-bir.h
@@ -139,6 +139,8 @@ class AbstractExpr : public Visitable
 public:
   explicit AbstractExpr (ExprKind kind) : kind (kind) {}
   WARN_UNUSED_RESULT ExprKind get_kind () const { return kind; }
+
+  virtual ~AbstractExpr () {}
 };
 
 class InitializerExpr : public VisitableImpl

[gcc r15-3898] doc: Remove index reference to removed documentation in fortran manual

[Mikael Morin via Gcc-cvs]

https://gcc.gnu.org/g:e9f341426567442a70747f89b6b954a005ca287a

commit r15-3898-ge9f341426567442a70747f89b6b954a005ca287a
Author: Mikael Morin 
Date:   Thu Sep 26 14:23:06 2024 +0200

doc: Remove index reference to removed documentation in fortran manual

Fortran option -M used to be an alias for -J.  After some deprecation time,
it was reused for another purpose at revision
r0-100725-gd8ddea4044ee8212d5fe305e8e2a547700cd7b8f.
That revision removed the documentation parts of -J mentioning -M, but left
a reference to -M in the index.

This change removes the remaining reference.

gcc/fortran/ChangeLog:

* invoke.texi (-M): Remove index reference to removed documentation.

Diff:
---
 gcc/fortran/invoke.texi | 1 -
 1 file changed, 1 deletion(-)

diff --git a/gcc/fortran/invoke.texi b/gcc/fortran/invoke.texi
index fbb5a0efa108..a9ac87d3a32f 100644
--- a/gcc/fortran/invoke.texi
+++ b/gcc/fortran/invoke.texi
@@ -1414,7 +1414,6 @@ gcc,Using the GNU Compiler Collection (GCC)}, for 
information on the
 @option{-I} option.
 
 @opindex J@var{dir}
-@opindex M@var{dir}
 @cindex paths, search
 @cindex module search path
 @item -J@var{dir}

[gcc r15-3899] testsuite: XFAIL gfortran.dg/initialization_25.f90 properly

[Sam James via Gcc-cvs]

https://gcc.gnu.org/g:819098dc71f2079aedc15a904ab5f17f0788d991

commit r15-3899-g819098dc71f2079aedc15a904ab5f17f0788d991
Author: Sam James 
Date:   Thu Sep 26 15:43:33 2024 +0100

testsuite: XFAIL gfortran.dg/initialization_25.f90 properly

The test was disabled/XFAIL'd informally in r0-100012-gcdc6637d7c78ec,
but r15-3890-g34bf6aa41ba539 didn't realize this, causing a FAIL.

Fix that by marking it as XFAIL per the original intent.

gcc/testsuite/ChangeLog:
PR fortran/35779
PR fortran/116858

* gfortran.dg/initialization_25.f90: Mark as XFAIL.

Diff:
---
 gcc/testsuite/gfortran.dg/initialization_25.f90 | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/gcc/testsuite/gfortran.dg/initialization_25.f90 
b/gcc/testsuite/gfortran.dg/initialization_25.f90
index c8edb163be04..cae3bbd27d53 100644
--- a/gcc/testsuite/gfortran.dg/initialization_25.f90
+++ b/gcc/testsuite/gfortran.dg/initialization_25.f90
@@ -5,8 +5,8 @@
 ! Dick Hendrickson 
 !
 ! Initial patch was reverted as it broke nested loops (see 
initialization_26.f90).
-!
+! XFAIL is for PR35779
 
 !   INTEGER :: J1
-!   INTEGER,PARAMETER :: I2(10) = (/(J1,J1=its_bad,1,-1)/) ! { dg-error "does 
not reduce" }
+!   INTEGER,PARAMETER :: I2(10) = (/(J1,J1=its_bad,1,-1)/) ! { dg-error "does 
not reduce" { xfail *-*-* } }
 END

[gcc r15-3900] libgomp.texi: Fix deprecation note for omp_{get, set}_nested + OMP_NESTED

[Tobias Burnus via Gcc-cvs]

https://gcc.gnu.org/g:9ec258bf65e6ae856491f607a987fe15b5385866

commit r15-3900-g9ec258bf65e6ae856491f607a987fe15b5385866
Author: Tobias Burnus 
Date:   Thu Sep 26 17:25:34 2024 +0200

libgomp.texi: Fix deprecation note for omp_{get,set}_nested + OMP_NESTED

libgomp/ChangeLog:

* libgomp.texi (omp_get_nested,omp_set_nested, OMP_NESTED): Fix
note about deprecation - correct is 5.0 not 5.2.

Diff:
---
 libgomp/libgomp.texi | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/libgomp/libgomp.texi b/libgomp/libgomp.texi
index 29f5419cd0f1..22eff1d7b557 100644
--- a/libgomp/libgomp.texi
+++ b/libgomp/libgomp.texi
@@ -937,7 +937,7 @@ active nested regions to the maximum supported.  Disabling 
nested parallel
 regions sets the maximum number of active nested regions to one.
 
 Note that the @code{omp_set_nested} API routine was deprecated
-in the OpenMP specification 5.2 in favor of @code{omp_set_max_active_levels}.
+in the OpenMP specification 5.0 in favor of @code{omp_set_max_active_levels}.
 
 @item @emph{C/C++}:
 @multitable @columnfractions .20 .80
@@ -984,7 +984,7 @@ regions with @code{omp_set_max_active_levels} to one to 
disable, or
 above one to enable.
 
 Note that the @code{omp_get_nested} API routine was deprecated
-in the OpenMP specification 5.2 in favor of @code{omp_get_max_active_levels}.
+in the OpenMP specification 5.0 in favor of @code{omp_get_max_active_levels}.
 
 @item @emph{C/C++}:
 @multitable @columnfractions .20 .80
@@ -3934,7 +3934,7 @@ setting.  If both are undefined, nested parallel regions 
are enabled if
 more than one item, otherwise they are disabled by default.
 
 Note that the @code{OMP_NESTED} environment variable was deprecated in
-the OpenMP specification 5.2 in favor of @code{OMP_MAX_ACTIVE_LEVELS}.
+the OpenMP specification 5.0 in favor of @code{OMP_MAX_ACTIVE_LEVELS}.
 
 @item @emph{See also}:
 @ref{omp_set_max_active_levels}, @ref{omp_set_nested},

[gcc r15-3892] libstdc++: Remove noexcept-specifier from MCF __cxa_guard_acquire [PR116857]

[Jonathan Wakely via Libstdc++-cvs]

https://gcc.gnu.org/g:efdda203f52b9b55ef9acc8ad668bbd0570a8de6

commit r15-3892-gefdda203f52b9b55ef9acc8ad668bbd0570a8de6
Author: Jonathan Wakely 
Date:   Thu Sep 26 12:12:13 2024 +0100

libstdc++: Remove noexcept-specifier from MCF __cxa_guard_acquire [PR116857]

This function definition should not be marked as non-throwing, because
the declaration in  is potentially throwing.

Also fix whitespace.

libstdc++-v3/ChangeLog:

PR libstdc++/116857
* libsupc++/guard.cc (__cxa_guard_acquire): Remove
_GLIBCXX_NOTHROW to match declaration in .

Diff:
---
 libstdc++-v3/libsupc++/guard.cc | 20 ++--
 1 file changed, 10 insertions(+), 10 deletions(-)

diff --git a/libstdc++-v3/libsupc++/guard.cc b/libstdc++-v3/libsupc++/guard.cc
index 364797817f72..707083e09d06 100644
--- a/libstdc++-v3/libsupc++/guard.cc
+++ b/libstdc++-v3/libsupc++/guard.cc
@@ -36,22 +36,22 @@
 namespace __cxxabiv1 {
 
 extern "C" int
-__cxa_guard_acquire (__guard* g) _GLIBCXX_NOTHROW
-  {
-return __MCF_cxa_guard_acquire(g);
-  }
+__cxa_guard_acquire (__guard* g)
+{
+  return __MCF_cxa_guard_acquire(g);
+}
 
 extern "C" void
 __cxa_guard_release (__guard* g) _GLIBCXX_NOTHROW
-  {
-__MCF_cxa_guard_release(g);
-  }
+{
+  __MCF_cxa_guard_release(g);
+}
 
 extern "C" void
 __cxa_guard_abort (__guard* g) _GLIBCXX_NOTHROW
-  {
-__MCF_cxa_guard_abort(g);
-  }
+{
+  __MCF_cxa_guard_abort(g);
+}
 
 }  // namespace __cxxabiv1

[gcc r15-3893] libstdc++: Fix std::basic_stracktrace to not assume allocators throw std::bad_alloc

[Jonathan Wakely via Libstdc++-cvs]

https://gcc.gnu.org/g:c45844eb7dadcd48e3ce8a45c270382f7ad1

commit r15-3893-gc45844eb7dadcd48e3ce8a45c270382f7ad1
Author: Jonathan Wakely 
Date:   Tue Sep 24 12:44:09 2024 +0100

libstdc++: Fix std::basic_stracktrace to not assume allocators throw 
std::bad_alloc

The standard allows allocators to throw any kind of exception, not only
something that can be caught as std::bad_alloc. std::basic_stracktrace
was assuming std::bad_alloc.

libstdc++-v3/ChangeLog:

* include/std/stacktrace (basic_stacktrace::_Impl::_M_allocate):
Do not assume allocators only throw std::bad_alloc.

Diff:
---
 libstdc++-v3/include/std/stacktrace | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/libstdc++-v3/include/std/stacktrace 
b/libstdc++-v3/include/std/stacktrace
index de7446064c74..58d0c2a0fc22 100644
--- a/libstdc++-v3/include/std/stacktrace
+++ b/libstdc++-v3/include/std/stacktrace
@@ -560,7 +560,7 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
  if constexpr (is_same_v>)
{
  // For std::allocator we use nothrow-new directly so we
- // don't need to handle bad_alloc exceptions.
+ // don't need to handle exceptions from __alloc.allocate(n).
  auto __p = __detail::__get_temporary_buffer(__n);
  if (__p == nullptr) [[unlikely]]
return nullptr;
@@ -572,7 +572,7 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
{
  _M_frames = __alloc.allocate(__n);
}
- __catch (const std::bad_alloc&)
+ __catch (...)
{
  return nullptr;
}

[gcc r15-3896] tree-optimization/114855 - speed up dom_oracle::register_transitives

[Richard Biener via Gcc-cvs]

https://gcc.gnu.org/g:942bbb2357656019caa3f8ebd2d23b09222f039a

commit r15-3896-g942bbb2357656019caa3f8ebd2d23b09222f039a
Author: Richard Biener 
Date:   Wed Sep 25 10:38:12 2024 +0200

tree-optimization/114855 - speed up dom_oracle::register_transitives

dom_oracle::register_transitives contains an unbound dominator walk
which for the testcase in PR114855 dominates the profile.  The following
fixes the unbound work done by assigning a constant work budget to the
loop, bounding the number of dominators visited but also the number of
relations processed.  This gets both dom_oracle::register_transitives and
get_immediate_dominator off the profile.

I'll note that we're still doing an unbound dominator walk via
equiv_set in find_equiv_dom at the start of the function and when
we register a relation that also looks up the same way.  At least
for the testcase at hand this isn't an issue.

I've also amended the guard to register_transitives with the
per-basic-block limit for the number of relations registered not
being exhausted.

PR tree-optimization/114855
* params.opt (--param transitive-relations-work-bound): New.
* doc/invoke.texi (--param transitive-relations-work-bound):
Document.
* value-relation.cc (dom_oracle::register_transitives):
Assing an overall work budget, bounding the dominator walk and
the number of relations processed.
(dom_oracle::record): Only register_transitives when the
number of already registered relations does not yet exceed
the per-BB limit.

Diff:
---
 gcc/doc/invoke.texi   |  3 +++
 gcc/params.opt|  4 
 gcc/value-relation.cc | 55 ++-
 3 files changed, 44 insertions(+), 18 deletions(-)

diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index bdbbea53666e..bd1208a62ee1 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -17144,6 +17144,9 @@ in the outgoing range calculator.
 @item relation-block-limit
 Maximum number of relations the oracle will register in a basic block.
 
+@item transitive-relations-work-bound
+Work bound when discovering transitive relations from existing relations.
+
 @item min-pagesize
 Minimum page size for warning purposes.
 
diff --git a/gcc/params.opt b/gcc/params.opt
index 949b47544980..a08e4c1042da 100644
--- a/gcc/params.opt
+++ b/gcc/params.opt
@@ -924,6 +924,10 @@ outgoing range calculator.
 Common Joined UInteger Var(param_relation_block_limit) Init(200) 
IntegerRange(0, ) Param Optimization
 Maximum number of relations the oracle will register in a basic block.
 
+-param=transitive-relations-work-bound=
+Common Joined UInteger Var(param_transitive_relations_work_bound) Init(256) 
IntegerRange(0, ) Param Optimization
+Work bound when discovering transitive relations from existing relations.
+
 -param=rpo-vn-max-loop-depth=
 Common Joined UInteger Var(param_rpo_vn_max_loop_depth) Init(7) 
IntegerRange(2, 65536) Param Optimization
 Maximum depth of a loop nest to fully value-number optimistically.
diff --git a/gcc/value-relation.cc b/gcc/value-relation.cc
index d6ad2dd984f6..d8a2ed920a82 100644
--- a/gcc/value-relation.cc
+++ b/gcc/value-relation.cc
@@ -1093,7 +1093,9 @@ dom_oracle::record (basic_block bb, relation_kind k, tree 
op1, tree op2)
   bool check = bitmap_bit_p (m_relation_set, SSA_NAME_VERSION (op1))
   || bitmap_bit_p (m_relation_set, SSA_NAME_VERSION (op2));
   relation_chain *ptr = set_one_relation (bb, k, op1, op2);
-  if (ptr && check)
+  if (ptr && check
+ && (m_relations[bb->index].m_num_relations
+ < param_relation_block_limit))
register_transitives (bb, *ptr);
 }
 }
@@ -1204,7 +1206,13 @@ dom_oracle::register_transitives (basic_block root_bb,
   const_bitmap equiv1 = equiv_set (relation.op1 (), root_bb);
   const_bitmap equiv2 = equiv_set (relation.op2 (), root_bb);
 
-  for (bb = root_bb; bb; bb = get_immediate_dominator (CDI_DOMINATORS, bb))
+  const unsigned work_budget = param_transitive_relations_work_bound;
+  unsigned avail_budget = work_budget;
+  for (bb = root_bb; bb;
+   /* Advancing to the next immediate dominator eats from the budget,
+ if none is left after that there's no point to continue.  */
+   bb = (--avail_budget > 0
+? get_immediate_dominator (CDI_DOMINATORS, bb) : nullptr))
 {
   int bbi = bb->index;
   if (bbi >= (int)m_relations.length())
@@ -1247,27 +1255,38 @@ dom_oracle::register_transitives (basic_block root_bb,
 
  // Ignore if both NULL (not relevant relation) or the same,
  if (r1 == r2)
-   continue;
+   ;
 
- // Any operand not an equivalence, just take the real operand.
- if (!r1)
-   r1 = relation.op1 ();
- if (!r2)
-   r2 = relation.op2 ();
-
- va

[gcc r14-10713] s390: Fix TF to FPRX2 conversion [PR115860]

[Stefan Schulze Frielinghaus via Gcc-cvs]

https://gcc.gnu.org/g:3eb3fbc89c638a72611efdc54110b8113f79ee8d

commit r14-10713-g3eb3fbc89c638a72611efdc54110b8113f79ee8d
Author: Stefan Schulze Frielinghaus 
Date:   Thu Sep 26 19:38:02 2024 +0200

s390: Fix TF to FPRX2 conversion [PR115860]

Currently subregs originating from *tf_to_fprx2_0 and *tf_to_fprx2_1
survive register allocation.  This in turn leads to wrong register
renaming.  Keeping the current approach would mean we need two insns for
*tf_to_fprx2_0 and *tf_to_fprx2_1, respectively.  Something along the
lines

(define_insn "*tf_to_fprx2_0"
  [(set (subreg:DF (match_operand:FPRX2 0 "nonimmediate_operand" "=f") 0)
(unspec:DF [(match_operand:TF 1 "general_operand" "v")]
   UNSPEC_TF_TO_FPRX2_0))]
  "TARGET_VXE"
  "#")

(define_insn "*tf_to_fprx2_0"
  [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
(unspec:DF [(match_operand:TF 1 "general_operand" "v")]
   UNSPEC_TF_TO_FPRX2_0))]
  "TARGET_VXE"
  "vpdi\t%v0,%v1,%v0,1
  [(set_attr "op_type" "VRR")])

and similar for *tf_to_fprx2_1.  Note, pre register allocation operand 0
has mode FPRX2 and afterwards DF once subregs have been eliminated.

Since we always copy a whole vector register into a floating-point
register pair, another way to fix this is to merge *tf_to_fprx2_0 and
*tf_to_fprx2_1 into a single insn which means we don't have to use
subregs at all.  The downside of this is that the assembler template
contains two instructions, now.  The upside is that we don't have to
come up with some artificial insn before RA which might be more
readable/maintainable.  That is implemented by this patch.

In commit r11-4872-ge627cda5686592, the output operand specifier %V was
introduced which is used in tf_to_fprx2 only, now.  Instead of coming up
with its counterpart %F for floating-point registers, which would also
only be used in tf_to_fprx2, I print the operands directly.  This
renders %V unused which is why it is removed by this patch.

gcc/ChangeLog:

PR target/115860
* config/s390/s390.cc (print_operand): Remove operand specifier
%V.
* config/s390/s390.md (UNSPEC_TF_TO_FPRX2): New.
* config/s390/vector.md (*tf_to_fprx2_0): Remove.
(*tf_to_fprx2_1): Remove.
(tf_to_fprx2): New.

gcc/testsuite/ChangeLog:

* gcc.target/s390/vector/long-double-asm-abi.c: Adapt
scan-assembler directive.
* gcc.target/s390/vector/long-double-to-i64.c: Adapt
scan-assembler directive.
* gcc.target/s390/pr115860-1.c: New test.

(cherry picked from commit 46c2538435dfc50dd5c67c4e03ce387d1f6ebe9b)

Diff:
---
 gcc/config/s390/s390.cc|  5 +-
 gcc/config/s390/s390.md|  2 +
 gcc/config/s390/vector.md  | 75 --
 gcc/testsuite/gcc.target/s390/pr115860-1.c | 26 
 .../gcc.target/s390/vector/long-double-asm-abi.c   |  2 +-
 .../gcc.target/s390/vector/long-double-to-i64.c|  2 -
 6 files changed, 72 insertions(+), 40 deletions(-)

diff --git a/gcc/config/s390/s390.cc b/gcc/config/s390/s390.cc
index 2619a9ac9861..a1c0a57a795f 100644
--- a/gcc/config/s390/s390.cc
+++ b/gcc/config/s390/s390.cc
@@ -8466,7 +8466,6 @@ print_operand_address (FILE *file, rtx addr)
 CONST_VECTOR: Generate a bitmask for vgbm instruction.
 'x': print integer X as if it's an unsigned halfword.
 'v': print register number as vector register (v1 instead of f1).
-'V': print the second word of a TFmode operand as vector register.
 */
 
 void
@@ -8659,13 +8658,13 @@ print_operand (FILE *file, rtx x, int code)
 case REG:
   /* Print FP regs as fx instead of vx when they are accessed
 through non-vector mode.  */
-  if ((code == 'v' || code == 'V')
+  if (code == 'v'
  || VECTOR_NOFP_REG_P (x)
  || (FP_REG_P (x) && VECTOR_MODE_P (GET_MODE (x)))
  || (VECTOR_REG_P (x)
  && (GET_MODE_SIZE (GET_MODE (x)) /
  s390_class_max_nregs (FP_REGS, GET_MODE (x))) > 8))
-   fprintf (file, "%%v%s", reg_names[REGNO (x) + (code == 'V')] + 2);
+   fprintf (file, "%%v%s", reg_names[REGNO (x)] + 2);
   else
fprintf (file, "%s", reg_names[REGNO (x)]);
   break;
diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md
index 17d31643dbc6..72e05be9b182 100644
--- a/gcc/config/s390/s390.md
+++ b/gcc/config/s390/s390.md
@@ -241,6 +241,8 @@
UNSPEC_VEC_VFMIN
UNSPEC_VEC_VFMAX
 
+   UNSPEC_TF_TO_FPRX2
+
UNSPEC_NNPA_VCLFNHS_V8HI
UNSPEC_NNPA_VCLFNLS_V8HI
UNSPEC_NNPA_VCRNFS_V8HI
diff --git a/gcc/config/s390/vector.md b/gcc/config/s390/vector.md
index 55dc35a71bf5..35defb7043a4 100644
--- a/gcc/config/s390/vector.md
+

[gcc r14-10712] s390: Fix AQ and AR constraints

[Stefan Schulze Frielinghaus via Gcc-cvs]

https://gcc.gnu.org/g:1670d3259dec8abf445ed4f282dcbf3a1e0d3032

commit r14-10712-g1670d3259dec8abf445ed4f282dcbf3a1e0d3032
Author: Stefan Schulze Frielinghaus 
Date:   Thu Sep 26 19:38:02 2024 +0200

s390: Fix AQ and AR constraints

Ensure for AQ and AR constraints that the resulting displacement after
adding any positive offset less than the size of the object being
referenced is still valid.

gcc/ChangeLog:

* config/s390/s390.cc (s390_mem_constraint): Check displacement
for AQ and AR constraints.

(cherry picked from commit 1a71ff3b89aadc7fa0af0bca269d74bb23c1a957)

Diff:
---
 gcc/config/s390/s390.cc | 12 
 1 file changed, 12 insertions(+)

diff --git a/gcc/config/s390/s390.cc b/gcc/config/s390/s390.cc
index 4be95788094c..2619a9ac9861 100644
--- a/gcc/config/s390/s390.cc
+++ b/gcc/config/s390/s390.cc
@@ -3552,6 +3552,18 @@ s390_mem_constraint (const char *str, rtx op)
   if ((reload_completed || reload_in_progress)
  ? !offsettable_memref_p (op) : !offsettable_nonstrict_memref_p (op))
return 0;
+  /* offsettable_memref_p ensures only that any positive offset added to
+the address forms a valid general address.  For AQ and AR constraints
+we also have to verify that the resulting displacement after adding
+any positive offset less than the size of the object being referenced
+is still valid.  */
+  if (str[1] == 'Q' || str[1] == 'R')
+   {
+ int o = GET_MODE_SIZE (GET_MODE (op)) - 1;
+ rtx tmp = adjust_address (op, QImode, o);
+ if (!s390_check_qrst_address (str[1], XEXP (tmp, 0), true))
+   return 0;
+   }
   return s390_check_qrst_address (str[1], XEXP (op, 0), true);
 case 'B':
   /* Check for non-literal-pool variants of memory constraints.  */

[gcc r15-3904] libstdc++: Fix freebsd/dragonfly build [PR116859]

[Jakub Jelinek via Libstdc++-cvs]

https://gcc.gnu.org/g:e23e5370d5855fc18b9f6f3fb680fcd2971e7a79

commit r15-3904-ge23e5370d5855fc18b9f6f3fb680fcd2971e7a79
Author: Jakub Jelinek 
Date:   Thu Sep 26 23:45:22 2024 +0200

libstdc++: Fix freebsd/dragonfly build [PR116859]

As reported in the PR, the system headers libstdc++ changes result in
-Werror=expansion-to-defined errors on FreeBSD and supposedly on DragonFly
too.

The following patch fixes those by performing the preprocessor test right
away, rather than using defined in the macro definitions.

I think neither __ISO_C_VISIBLE nor __LONG_LONG_SUPPORTED should normally
change during compilation.

2024-09-26  Jakub Jelinek  

PR libstdc++/116859
* config/os/bsd/freebsd/os_defines.h
(_GLIBCXX_USE_C99_LONG_LONG_DYNAMIC,
_GLIBCXX_USE_C99_FLOAT_TRANSCENDENTALS_DYNAMIC): Avoid
-Wexpansion-to-defined warnings.
* config/os/bsd/dragonfly/os_defines.h
(_GLIBCXX_USE_C99_LONG_LONG_DYNAMIC): Likewise.

Diff:
---
 libstdc++-v3/config/os/bsd/dragonfly/os_defines.h |  6 +-
 libstdc++-v3/config/os/bsd/freebsd/os_defines.h   | 12 ++--
 2 files changed, 15 insertions(+), 3 deletions(-)

diff --git a/libstdc++-v3/config/os/bsd/dragonfly/os_defines.h 
b/libstdc++-v3/config/os/bsd/dragonfly/os_defines.h
index 5c48ca9ee656..e030fa3dc872 100644
--- a/libstdc++-v3/config/os/bsd/dragonfly/os_defines.h
+++ b/libstdc++-v3/config/os/bsd/dragonfly/os_defines.h
@@ -36,6 +36,10 @@
 #define _GLIBCXX_USE_C99_CHECK 1
 #define _GLIBCXX_USE_C99_DYNAMIC (!(__ISO_C_VISIBLE >= 1999))
 #define _GLIBCXX_USE_C99_LONG_LONG_CHECK 1
-#define _GLIBCXX_USE_C99_LONG_LONG_DYNAMIC (_GLIBCXX_USE_C99_DYNAMIC || 
!defined __LONG_LONG_SUPPORTED)
+#if _GLIBCXX_USE_C99_DYNAMIC || !defined __LONG_LONG_SUPPORTED
+#define _GLIBCXX_USE_C99_LONG_LONG_DYNAMIC 1
+#else
+#define _GLIBCXX_USE_C99_LONG_LONG_DYNAMIC 0
+#endif
 
 #endif
diff --git a/libstdc++-v3/config/os/bsd/freebsd/os_defines.h 
b/libstdc++-v3/config/os/bsd/freebsd/os_defines.h
index 6c931821329e..0d63ae6cec4c 100644
--- a/libstdc++-v3/config/os/bsd/freebsd/os_defines.h
+++ b/libstdc++-v3/config/os/bsd/freebsd/os_defines.h
@@ -36,8 +36,16 @@
 #define _GLIBCXX_USE_C99_CHECK 1
 #define _GLIBCXX_USE_C99_DYNAMIC (!(__ISO_C_VISIBLE >= 1999))
 #define _GLIBCXX_USE_C99_LONG_LONG_CHECK 1
-#define _GLIBCXX_USE_C99_LONG_LONG_DYNAMIC (_GLIBCXX_USE_C99_DYNAMIC || 
!defined __LONG_LONG_SUPPORTED)
+#if _GLIBCXX_USE_C99_DYNAMIC || !defined __LONG_LONG_SUPPORTED
+#define _GLIBCXX_USE_C99_LONG_LONG_DYNAMIC 1
+#else
+#define _GLIBCXX_USE_C99_LONG_LONG_DYNAMIC 0
+#endif
 #define _GLIBCXX_USE_C99_FLOAT_TRANSCENDENTALS_CHECK 1
-#define _GLIBCXX_USE_C99_FLOAT_TRANSCENDENTALS_DYNAMIC defined _XOPEN_SOURCE
+#ifdef _XOPEN_SOURCE
+#define _GLIBCXX_USE_C99_FLOAT_TRANSCENDENTALS_DYNAMIC 1
+#else
+#define _GLIBCXX_USE_C99_FLOAT_TRANSCENDENTALS_DYNAMIC 0
+#endif
 
 #endif

[gcc(refs/users/meissner/heads/work179-orig)] Add REVISION.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:3da2a9bf2e85fb338cef798b88e8c7c3097689e5

commit 3da2a9bf2e85fb338cef798b88e8c7c3097689e5
Author: Michael Meissner 
Date:   Thu Sep 26 17:31:08 2024 -0400

Add REVISION.

2024-09-26  Michael Meissner  

gcc/

* REVISION: New file for branch.

Diff:
---
 gcc/REVISION | 1 +
 1 file changed, 1 insertion(+)

diff --git a/gcc/REVISION b/gcc/REVISION
new file mode 100644
index ..72933aa3fae2
--- /dev/null
+++ b/gcc/REVISION
@@ -0,0 +1 @@
+work179-orig branch

[gcc] Created branch 'meissner/heads/work179' in namespace 'refs/users'

[Michael Meissner via Gcc-cvs]

The branch 'meissner/heads/work179' was created in namespace 'refs/users' 
pointing to:

 ee9f00606f18... libstdc++: Preserve signbit of nan when converting float to

[gcc(refs/users/meissner/heads/work179-bugs)] PR 99293: Optimize splat of a V2DF/V2DI extract with constant element

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:d2cd951d300235e244020d6190e4e2cb0accff24

commit d2cd951d300235e244020d6190e4e2cb0accff24
Author: Michael Meissner 
Date:   Thu Sep 26 18:33:15 2024 -0400

PR 99293: Optimize splat of a V2DF/V2DI extract with constant element

We had optimizations for splat of a vector extract for the other vector
types, but we missed having one for V2DI and V2DF.  This patch adds a
combiner insn to do this optimization.

In looking at the source, we had similar optimizations for V4SI and V4SF
extract and splats, but we missed doing V2DI/V2DF.

Without the patch for the code:

vector long long splat_dup_l_0 (vector long long v)
{
  return __builtin_vec_splats (__builtin_vec_extract (v, 0));
}

the compiler generates (on a little endian power9):

splat_dup_l_0:
mfvsrld 9,34
mtvsrdd 34,9,9
blr

Now it generates:

splat_dup_l_0:
xxpermdi 34,34,34,3
blr

2024-09-26  Michael Meissner  

gcc/

* config/rs6000/vsx.md (vsx_splat_extract_): New insn.

gcc/testsuite/

* gcc.target/powerpc/builtins-1.c: Adjust insn count.
* gcc.target/powerpc/pr99293.c: New test.

Diff:
---
 gcc/config/rs6000/vsx.md  | 18 ++
 gcc/testsuite/gcc.target/powerpc/builtins-1.c |  2 +-
 gcc/testsuite/gcc.target/powerpc/pr99293.c| 22 ++
 3 files changed, 41 insertions(+), 1 deletion(-)

diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index b2fc39acf4e8..73f20a86e56a 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -4796,6 +4796,24 @@
   "lxvdsx %x0,%y1"
   [(set_attr "type" "vecload")])
 
+;; Optimize SPLAT of an extract from a V2DF/V2DI vector with a constant element
+(define_insn "*vsx_splat_extract_"
+  [(set (match_operand:VSX_D 0 "vsx_register_operand" "=wa")
+   (vec_duplicate:VSX_D
+(vec_select:
+ (match_operand:VSX_D 1 "vsx_register_operand" "wa")
+ (parallel [(match_operand 2 "const_0_to_1_operand" "n")]]
+  "VECTOR_MEM_VSX_P (mode)"
+{
+  int which_word = INTVAL (operands[2]);
+  if (!BYTES_BIG_ENDIAN)
+which_word = 1 - which_word;
+
+  operands[3] = GEN_INT (which_word ? 3 : 0);
+  return "xxpermdi %x0,%x1,%x1,%3";
+}
+  [(set_attr "type" "vecperm")])
+
 ;; V4SI splat support
 (define_insn "vsx_splat_v4si"
   [(set (match_operand:V4SI 0 "vsx_register_operand" "=wa,wa")
diff --git a/gcc/testsuite/gcc.target/powerpc/builtins-1.c 
b/gcc/testsuite/gcc.target/powerpc/builtins-1.c
index 8410a5fd4319..4e7e5384675f 100644
--- a/gcc/testsuite/gcc.target/powerpc/builtins-1.c
+++ b/gcc/testsuite/gcc.target/powerpc/builtins-1.c
@@ -1035,4 +1035,4 @@ foo156 (vector unsigned short usa)
 /* { dg-final { scan-assembler-times {\mvmrglb\M} 3 } } */
 /* { dg-final { scan-assembler-times {\mvmrgew\M} 4 } } */
 /* { dg-final { scan-assembler-times {\mvsplth|xxsplth\M} 4 } } */
-/* { dg-final { scan-assembler-times {\mxxpermdi\M} 44 } } */
+/* { dg-final { scan-assembler-times {\mxxpermdi\M} 42 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/pr99293.c 
b/gcc/testsuite/gcc.target/powerpc/pr99293.c
new file mode 100644
index ..20adc1f27f65
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr99293.c
@@ -0,0 +1,22 @@
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O2 -mvsx" } */
+
+/* Test for PR 99263, which wants to do:
+   __builtin_vec_splats (__builtin_vec_extract (v, n))
+
+   where v is a V2DF or V2DI vector and n is either 0 or 1.  Previously the
+   compiler would do a direct move to the GPR registers to select the item and 
a
+   direct move from the GPR registers to do the splat.  */
+
+vector long long splat_dup_l_0 (vector long long v)
+{
+  return __builtin_vec_splats (__builtin_vec_extract (v, 0));
+}
+
+vector long long splat_dup_l_1 (vector long long v)
+{
+  return __builtin_vec_splats (__builtin_vec_extract (v, 1));
+}
+
+/* { dg-final { scan-assembler-times "xxpermdi" 2 } } */

[gcc(refs/users/meissner/heads/work179-bugs)] Update ChangeLog.*

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:83616cfc9d98f9e7657dc628f414c6c2d44ad521

commit 83616cfc9d98f9e7657dc628f414c6c2d44ad521
Author: Michael Meissner 
Date:   Thu Sep 26 18:35:58 2024 -0400

Update ChangeLog.*

Diff:
---
 gcc/ChangeLog.bugs | 52 +++-
 1 file changed, 51 insertions(+), 1 deletion(-)

diff --git a/gcc/ChangeLog.bugs b/gcc/ChangeLog.bugs
index 0f361fb7d770..8b658088f151 100644
--- a/gcc/ChangeLog.bugs
+++ b/gcc/ChangeLog.bugs
@@ -1,6 +1,56 @@
+ Branch work179-bugs, patch #200 
+
+PR 99293: Optimize splat of a V2DF/V2DI extract with constant element
+
+We had optimizations for splat of a vector extract for the other vector
+types, but we missed having one for V2DI and V2DF.  This patch adds a
+combiner insn to do this optimization.
+
+In looking at the source, we had similar optimizations for V4SI and V4SF
+extract and splats, but we missed doing V2DI/V2DF.
+
+Without the patch for the code:
+
+   vector long long splat_dup_l_0 (vector long long v)
+   {
+ return __builtin_vec_splats (__builtin_vec_extract (v, 0));
+   }
+
+the compiler generates (on a little endian power9):
+
+   splat_dup_l_0:
+   mfvsrld 9,34
+   mtvsrdd 34,9,9
+   blr
+
+Now it generates:
+
+   splat_dup_l_0:
+   xxpermdi 34,34,34,3
+   blr
+
+2024-09-26  Michael Meissner  
+
+gcc/
+
+   * config/rs6000/vsx.md (vsx_splat_extract_): New insn.
+
+gcc/testsuite/
+
+   * gcc.target/powerpc/builtins-1.c: Adjust insn count.
+   * gcc.target/powerpc/pr99293.c: New test.
+
  Branch work179-bugs, baseline 
 
+Add ChangeLog.bugs and update REVISION.
+
+2024-09-26  Michael Meissner  
+
+gcc/
+
+   * ChangeLog.bugs: New file for branch.
+   * REVISION: Update.
+
 2024-09-26   Michael Meissner  
 
Clone branch
-

[gcc r15-3903] libstdc++: Preserve signbit of nan when converting float to double [PR113578]

[Jonathan Wakely via Libstdc++-cvs]

https://gcc.gnu.org/g:ee9f00606f184be37d6f9df74cc7e222157c7fee

commit r15-3903-gee9f00606f184be37d6f9df74cc7e222157c7fee
Author: Jonathan Wakely 
Date:   Tue Jan 30 14:47:34 2024 +

libstdc++: Preserve signbit of nan when converting float to double 
[PR113578]

LWG 117 specifies that inserting a float into an ostream should cast it
to double, because there's no std::num_put::put member that takes a
float. However, on RISC-V converting a NaN float to double loses the
sign, which means that negative NaN floats are printed as positive.

This has been reported as LWG 4101 and there is good support for fixing
the standard to preserve the sign bit when printing negative NaN values.

This change uses copysign((double)f, (double)std::bit_cast(f)) to
get a double that preserves the sign. The bit_cast gives us an integer
with the same signbit, and casting that to the target type preserves
the signbit. We don't care about the value, as copysign only uses the
signbit.

The inserters for extended floating-point types need the same treatment,
so add a new _S_cast_flt helper to do the signbit-preserving conversion
generically.

So far only RISC-V has been confirmed to need this treatment, but we
might need to extend it to other targets later.

libstdc++-v3/ChangeLog:

PR libstdc++/113578
* include/std/ostream (_S_cast_flt): New static member function
to restore signbit after casting to double or long double.
(operator<<(float), operator<<(_Float16), operator<<(_Float32))
(operator<<(_Float64), operator(_Float128))
(operator<<(__bfloat16_t)): Use _S_cast_flt.
testsuite/27_io/basic_ostream/inserters_arithmetic/lwg4101.cc:
New test.

Co-authored-by: Andrew Waterman 

Diff:
---
 libstdc++-v3/include/std/ostream   | 43 +++---
 .../basic_ostream/inserters_arithmetic/lwg4101.cc  | 14 +++
 2 files changed, 51 insertions(+), 6 deletions(-)

diff --git a/libstdc++-v3/include/std/ostream b/libstdc++-v3/include/std/ostream
index d8462efe764d..a1cb7ce1765e 100644
--- a/libstdc++-v3/include/std/ostream
+++ b/libstdc++-v3/include/std/ostream
@@ -235,7 +235,7 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
   {
// _GLIBCXX_RESOLVE_LIB_DEFECTS
// 117. basic_ostream uses nonexistent num_put member functions.
-   return _M_insert(static_cast(__f));
+   return _M_insert(_S_cast_flt(__f));
   }
 
   __ostream_type&
@@ -248,7 +248,7 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
   __ostream_type&
   operator<<(_Float16 __f)
   {
-   return _M_insert(static_cast(__f));
+   return _M_insert(_S_cast_flt(__f));
   }
 #endif
 
@@ -257,7 +257,7 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
   __ostream_type&
   operator<<(_Float32 __f)
   {
-   return _M_insert(static_cast(__f));
+   return _M_insert(_S_cast_flt(__f));
   }
 #endif
 
@@ -266,7 +266,7 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
   __ostream_type&
   operator<<(_Float64 __f)
   {
-   return _M_insert(static_cast(__f));
+   return _M_insert(_S_cast_flt(__f));
   }
 #endif
 
@@ -275,7 +275,7 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
   __ostream_type&
   operator<<(_Float128 __f)
   {
-   return _M_insert(static_cast(__f));
+   return _M_insert(_S_cast_flt(__f));
   }
 #endif
 
@@ -284,7 +284,7 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
   __ostream_type&
   operator<<(__gnu_cxx::__bfloat16_t __f)
   {
-   return _M_insert(static_cast(__f));
+   return _M_insert(_S_cast_flt(__f));
   }
 #endif
 
@@ -475,7 +475,38 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
   _M_write(const char_type* __s, streamsize __n)
   { std::__ostream_insert(*this, __s, __n); }
 #endif
+
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wc++17-extensions" // for if-constexpr
+  template
+   static _To
+   _S_cast_flt(_From __f)
+   {
+ _To __d = static_cast<_To>(__f);
+ // _GLIBCXX_RESOLVE_LIB_DEFECTS
+ // 4101: LWG 117 loses the sign for negative NaN on some arches.
+#if defined __riscv
+ _To __sign;
+#if __cpp_constexpr && __has_builtin(__builtin_bit_cast)
+ if constexpr (sizeof(__f) == sizeof(short))
+   __sign = static_cast<_To>(__builtin_bit_cast(short, __f));
+ else if constexpr (sizeof(__f) == sizeof(int))
+   __sign = static_cast<_To>(__builtin_bit_cast(int, __f));
+ else if constexpr (sizeof(__f) == sizeof(long long))
+   __sign = static_cast<_To>(__builtin_bit_cast(long long, __f));
+ else
+#endif
+ __sign = __builtin_signbit(__f) ? _To(-1.0) : _To(+1.0);
+
+ if _GLIBCXX17_CONSTEXPR (__is_same(_To, double))
+   __d = __builtin_copysign(__d, __sign);
+ else if _GLIBCXX17_CONSTEXPR (__is_same(_To, long double))
+

[gcc(refs/users/meissner/heads/work179-dmf)] Add ChangeLog.dmf and update REVISION.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:56aef5963db070be51b8224a5e4ab44139fb3723

commit 56aef5963db070be51b8224a5e4ab44139fb3723
Author: Michael Meissner 
Date:   Thu Sep 26 17:22:56 2024 -0400

Add ChangeLog.dmf and update REVISION.

2024-09-26  Michael Meissner  

gcc/

* ChangeLog.dmf: New file for branch.
* REVISION: Update.

Diff:
---
 gcc/ChangeLog.dmf | 6 ++
 gcc/REVISION  | 2 +-
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/gcc/ChangeLog.dmf b/gcc/ChangeLog.dmf
new file mode 100644
index ..a0df4b147451
--- /dev/null
+++ b/gcc/ChangeLog.dmf
@@ -0,0 +1,6 @@
+ Branch work179-dmf, baseline 
+
+2024-09-26   Michael Meissner  
+
+   Clone branch
+
diff --git a/gcc/REVISION b/gcc/REVISION
index 3f5e8bfabc6b..b1e1ca189330 100644
--- a/gcc/REVISION
+++ b/gcc/REVISION
@@ -1 +1 @@
-work179 branch
+work179-dmf branch

[gcc(refs/users/meissner/heads/work179-dmf)] Merge commit 'refs/users/meissner/heads/work179-dmf' of git+ssh://gcc.gnu.org/git/gcc into me/work17

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:e06cd809bf5390c1501b8bbc75647043b4f249c0

commit e06cd809bf5390c1501b8bbc75647043b4f249c0
Merge: 56aef5963db0 8470e45643a8
Author: Michael Meissner 
Date:   Thu Sep 26 18:00:02 2024 -0400

Merge commit 'refs/users/meissner/heads/work179-dmf' of 
git+ssh://gcc.gnu.org/git/gcc into me/work179-dmf

Diff:

[gcc/meissner/heads/work179-libs] (14 commits) Merge commit 'refs/users/meissner/heads/work179-libs' of gi

[Michael Meissner via Gcc-cvs]

The branch 'meissner/heads/work179-libs' was updated to point to:

 a5e0d5d20ce1... Merge commit 'refs/users/meissner/heads/work179-libs' of gi

It previously pointed to:

 27a1b94afdc0... Add ChangeLog.libs and update REVISION.

Diff:

Summary of changes (added commits):
---

  a5e0d5d... Merge commit 'refs/users/meissner/heads/work179-libs' of gi
  da2bca5... Add ChangeLog.libs and update REVISION.
  42a052d... Update ChangeLog.* (*)
  694e6ba... Add -mcpu=future tuning support. (*)
  3ddfde5... Add support for -mcpu=future (*)
  c619658... Update tests to work with architecture flags changes. (*)
  58a18a3... Change TARGET_MODULO to TARGET_POWER9 (*)
  c375562... Change TARGET_POPCNTD to TARGET_POWER7 (*)
  489e6e2... Change TARGET_CMPB to TARGET_POWER6 (*)
  251c4aa... Change TARGET_FPRND to TARGET_POWER5X (*)
  fa4fe45... Change TARGET_POPCNTB to TARGET_POWER5 (*)
  02aa84a... Do not allow -mvsx to boost processor to power7. (*)
  34e7c57... Use architecture flags for defining _ARCH_PWR macros. (*)
  1aa6493... Add rs6000 architecture masks. (*)

(*) This commit already exists in another branch.
Because the reference `refs/users/meissner/heads/work179-libs' matches
your hooks.email-new-commits-only configuration,
no separate email is sent for this commit.

[gcc(refs/users/meissner/heads/work179-libs)] Add ChangeLog.libs and update REVISION.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:da2bca5b21ca9fa000e3bc52b6ad4f96f34ed9f7

commit da2bca5b21ca9fa000e3bc52b6ad4f96f34ed9f7
Author: Michael Meissner 
Date:   Thu Sep 26 17:28:53 2024 -0400

Add ChangeLog.libs and update REVISION.

2024-09-26  Michael Meissner  

gcc/

* ChangeLog.libs: New file for branch.
* REVISION: Update.

Diff:
---
 gcc/ChangeLog.libs | 6 ++
 gcc/REVISION   | 2 +-
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/gcc/ChangeLog.libs b/gcc/ChangeLog.libs
new file mode 100644
index ..79f3765e1c03
--- /dev/null
+++ b/gcc/ChangeLog.libs
@@ -0,0 +1,6 @@
+ Branch work179-libs, baseline 
+
+2024-09-26   Michael Meissner  
+
+   Clone branch
+
diff --git a/gcc/REVISION b/gcc/REVISION
index 3f5e8bfabc6b..6b22264932c2 100644
--- a/gcc/REVISION
+++ b/gcc/REVISION
@@ -1 +1 @@
-work179 branch
+work179-libs branch

[gcc(refs/users/meissner/heads/work179-libs)] Merge commit 'refs/users/meissner/heads/work179-libs' of git+ssh://gcc.gnu.org/git/gcc into me/work1

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:a5e0d5d20ce19a6417e0b3bf84e2bc77885cbc4f

commit a5e0d5d20ce19a6417e0b3bf84e2bc77885cbc4f
Merge: da2bca5b21ca 27a1b94afdc0
Author: Michael Meissner 
Date:   Thu Sep 26 18:01:14 2024 -0400

Merge commit 'refs/users/meissner/heads/work179-libs' of 
git+ssh://gcc.gnu.org/git/gcc into me/work179-libs

Diff:

[gcc(refs/users/meissner/heads/work179-tar)] Add ChangeLog.tar and update REVISION.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:3292408c8e6ee43702ecf6cd30d41b59793bbd91

commit 3292408c8e6ee43702ecf6cd30d41b59793bbd91
Author: Michael Meissner 
Date:   Thu Sep 26 17:25:55 2024 -0400

Add ChangeLog.tar and update REVISION.

2024-09-26  Michael Meissner  

gcc/

* ChangeLog.tar: New file for branch.
* REVISION: Update.

Diff:
---
 gcc/ChangeLog.tar | 6 ++
 gcc/REVISION  | 2 +-
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/gcc/ChangeLog.tar b/gcc/ChangeLog.tar
new file mode 100644
index ..fbc82a323070
--- /dev/null
+++ b/gcc/ChangeLog.tar
@@ -0,0 +1,6 @@
+ Branch work179-tar, baseline 
+
+2024-09-26   Michael Meissner  
+
+   Clone branch
+
diff --git a/gcc/REVISION b/gcc/REVISION
index 3f5e8bfabc6b..e0242fb5a986 100644
--- a/gcc/REVISION
+++ b/gcc/REVISION
@@ -1 +1 @@
-work179 branch
+work179-tar branch

[gcc/meissner/heads/work179-tar] (14 commits) Merge commit 'refs/users/meissner/heads/work179-tar' of git

[Michael Meissner via Gcc-cvs]

The branch 'meissner/heads/work179-tar' was updated to point to:

 8211f9f3f49e... Merge commit 'refs/users/meissner/heads/work179-tar' of git

It previously pointed to:

 1435fde96339... Add ChangeLog.tar and update REVISION.

Diff:

Summary of changes (added commits):
---

  8211f9f... Merge commit 'refs/users/meissner/heads/work179-tar' of git
  3292408... Add ChangeLog.tar and update REVISION.
  42a052d... Update ChangeLog.* (*)
  694e6ba... Add -mcpu=future tuning support. (*)
  3ddfde5... Add support for -mcpu=future (*)
  c619658... Update tests to work with architecture flags changes. (*)
  58a18a3... Change TARGET_MODULO to TARGET_POWER9 (*)
  c375562... Change TARGET_POPCNTD to TARGET_POWER7 (*)
  489e6e2... Change TARGET_CMPB to TARGET_POWER6 (*)
  251c4aa... Change TARGET_FPRND to TARGET_POWER5X (*)
  fa4fe45... Change TARGET_POPCNTB to TARGET_POWER5 (*)
  02aa84a... Do not allow -mvsx to boost processor to power7. (*)
  34e7c57... Use architecture flags for defining _ARCH_PWR macros. (*)
  1aa6493... Add rs6000 architecture masks. (*)

(*) This commit already exists in another branch.
Because the reference `refs/users/meissner/heads/work179-tar' matches
your hooks.email-new-commits-only configuration,
no separate email is sent for this commit.

[gcc(refs/users/meissner/heads/work179-tar)] Merge commit 'refs/users/meissner/heads/work179-tar' of git+ssh://gcc.gnu.org/git/gcc into me/work17

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:8211f9f3f49e51f8beb01aee1006c16322aaad3a

commit 8211f9f3f49e51f8beb01aee1006c16322aaad3a
Merge: 3292408c8e6e 1435fde96339
Author: Michael Meissner 
Date:   Thu Sep 26 18:03:26 2024 -0400

Merge commit 'refs/users/meissner/heads/work179-tar' of 
git+ssh://gcc.gnu.org/git/gcc into me/work179-tar

Diff:

[gcc r15-3909] testsuite/gfortran.dg/open_errors_2.f90: Remove now-redundant file deletion

[Hans-Peter Nilsson via Gcc-cvs]

https://gcc.gnu.org/g:3471ae37200bd8154084334204a6f72a5bbae974

commit r15-3909-g3471ae37200bd8154084334204a6f72a5bbae974
Author: Hans-Peter Nilsson 
Date:   Thu Sep 26 23:07:01 2024 +0200

testsuite/gfortran.dg/open_errors_2.f90: Remove now-redundant file deletion

Now that fort.N files are removed by the testsuite
framework, remove this single "manual" file deletion.
(Also, it should have been "remote_file target delete",
since it's the target that creates the file, not the build
framework, which might matter to some setups.)

* gfortran.dg/open_errors_2.f90: Remove now-redundant file deletion.

Diff:
---
 gcc/testsuite/gfortran.dg/open_errors_2.f90 | 1 -
 1 file changed, 1 deletion(-)

diff --git a/gcc/testsuite/gfortran.dg/open_errors_2.f90 
b/gcc/testsuite/gfortran.dg/open_errors_2.f90
index 72d63bb3a39f..dbe9112bc6fd 100644
--- a/gcc/testsuite/gfortran.dg/open_errors_2.f90
+++ b/gcc/testsuite/gfortran.dg/open_errors_2.f90
@@ -16,4 +16,3 @@
   rewind(522)
   close(522)
 end program
-! { dg-final { remote_file build delete "fort.345" } }

[gcc/meissner/heads/work179-test] (14 commits) Merge commit 'refs/users/meissner/heads/work179-test' of gi

[Michael Meissner via Gcc-cvs]

The branch 'meissner/heads/work179-test' was updated to point to:

 2c3d0f560d2d... Merge commit 'refs/users/meissner/heads/work179-test' of gi

It previously pointed to:

 7e24e5072cb3... Add ChangeLog.test and update REVISION.

Diff:

Summary of changes (added commits):
---

  2c3d0f5... Merge commit 'refs/users/meissner/heads/work179-test' of gi
  40c13da... Add ChangeLog.test and update REVISION.
  42a052d... Update ChangeLog.* (*)
  694e6ba... Add -mcpu=future tuning support. (*)
  3ddfde5... Add support for -mcpu=future (*)
  c619658... Update tests to work with architecture flags changes. (*)
  58a18a3... Change TARGET_MODULO to TARGET_POWER9 (*)
  c375562... Change TARGET_POPCNTD to TARGET_POWER7 (*)
  489e6e2... Change TARGET_CMPB to TARGET_POWER6 (*)
  251c4aa... Change TARGET_FPRND to TARGET_POWER5X (*)
  fa4fe45... Change TARGET_POPCNTB to TARGET_POWER5 (*)
  02aa84a... Do not allow -mvsx to boost processor to power7. (*)
  34e7c57... Use architecture flags for defining _ARCH_PWR macros. (*)
  1aa6493... Add rs6000 architecture masks. (*)

(*) This commit already exists in another branch.
Because the reference `refs/users/meissner/heads/work179-test' matches
your hooks.email-new-commits-only configuration,
no separate email is sent for this commit.

[gcc(refs/users/meissner/heads/work179-test)] Add ChangeLog.test and update REVISION.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:40c13da38a8ad43c0f68dd69a3464df7dc52e167

commit 40c13da38a8ad43c0f68dd69a3464df7dc52e167
Author: Michael Meissner 
Date:   Thu Sep 26 17:29:58 2024 -0400

Add ChangeLog.test and update REVISION.

2024-09-26  Michael Meissner  

gcc/

* ChangeLog.test: New file for branch.
* REVISION: Update.

Diff:
---
 gcc/ChangeLog.test | 6 ++
 gcc/REVISION   | 2 +-
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/gcc/ChangeLog.test b/gcc/ChangeLog.test
new file mode 100644
index ..7edfd3ba5e76
--- /dev/null
+++ b/gcc/ChangeLog.test
@@ -0,0 +1,6 @@
+ Branch work179-test, baseline 
+
+2024-09-26   Michael Meissner  
+
+   Clone branch
+
diff --git a/gcc/REVISION b/gcc/REVISION
index 3f5e8bfabc6b..c9c7a7b181ec 100644
--- a/gcc/REVISION
+++ b/gcc/REVISION
@@ -1 +1 @@
-work179 branch
+work179-test branch

[gcc(refs/users/meissner/heads/work179-test)] Merge commit 'refs/users/meissner/heads/work179-test' of git+ssh://gcc.gnu.org/git/gcc into me/work1

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:2c3d0f560d2d7a87dc6127064480e557dde337dc

commit 2c3d0f560d2d7a87dc6127064480e557dde337dc
Merge: 40c13da38a8a 7e24e5072cb3
Author: Michael Meissner 
Date:   Thu Sep 26 18:05:24 2024 -0400

Merge commit 'refs/users/meissner/heads/work179-test' of 
git+ssh://gcc.gnu.org/git/gcc into me/work179-test

Diff:

[gcc(refs/users/meissner/heads/work179-vpair)] Add ChangeLog.vpair and update REVISION.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:09fc2b3d534d586ddcbb13fc70c9262b1bea8e46

commit 09fc2b3d534d586ddcbb13fc70c9262b1bea8e46
Author: Michael Meissner 
Date:   Thu Sep 26 17:24:17 2024 -0400

Add ChangeLog.vpair and update REVISION.

2024-09-26  Michael Meissner  

gcc/

* ChangeLog.vpair: New file for branch.
* REVISION: Update.

Diff:
---
 gcc/ChangeLog.vpair | 6 ++
 gcc/REVISION| 2 +-
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/gcc/ChangeLog.vpair b/gcc/ChangeLog.vpair
new file mode 100644
index ..7c411bb99148
--- /dev/null
+++ b/gcc/ChangeLog.vpair
@@ -0,0 +1,6 @@
+ Branch work179-vpair, baseline 
+
+2024-09-26   Michael Meissner  
+
+   Clone branch
+
diff --git a/gcc/REVISION b/gcc/REVISION
index 3f5e8bfabc6b..5b4edbbca081 100644
--- a/gcc/REVISION
+++ b/gcc/REVISION
@@ -1 +1 @@
-work179 branch
+work179-vpair branch

[gcc/meissner/heads/work179-vpair] (14 commits) Merge commit 'refs/users/meissner/heads/work179-vpair' of g

[Michael Meissner via Gcc-cvs]

The branch 'meissner/heads/work179-vpair' was updated to point to:

 50794c4d103c... Merge commit 'refs/users/meissner/heads/work179-vpair' of g

It previously pointed to:

 132564fd6b6f... Add ChangeLog.vpair and update REVISION.

Diff:

Summary of changes (added commits):
---

  50794c4... Merge commit 'refs/users/meissner/heads/work179-vpair' of g
  09fc2b3... Add ChangeLog.vpair and update REVISION.
  42a052d... Update ChangeLog.* (*)
  694e6ba... Add -mcpu=future tuning support. (*)
  3ddfde5... Add support for -mcpu=future (*)
  c619658... Update tests to work with architecture flags changes. (*)
  58a18a3... Change TARGET_MODULO to TARGET_POWER9 (*)
  c375562... Change TARGET_POPCNTD to TARGET_POWER7 (*)
  489e6e2... Change TARGET_CMPB to TARGET_POWER6 (*)
  251c4aa... Change TARGET_FPRND to TARGET_POWER5X (*)
  fa4fe45... Change TARGET_POPCNTB to TARGET_POWER5 (*)
  02aa84a... Do not allow -mvsx to boost processor to power7. (*)
  34e7c57... Use architecture flags for defining _ARCH_PWR macros. (*)
  1aa6493... Add rs6000 architecture masks. (*)

(*) This commit already exists in another branch.
Because the reference `refs/users/meissner/heads/work179-vpair' matches
your hooks.email-new-commits-only configuration,
no separate email is sent for this commit.

[gcc(refs/users/meissner/heads/work179-vpair)] Merge commit 'refs/users/meissner/heads/work179-vpair' of git+ssh://gcc.gnu.org/git/gcc into me/work

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:50794c4d103c427d3a37754b87845549d7b64c94

commit 50794c4d103c427d3a37754b87845549d7b64c94
Merge: 09fc2b3d534d 132564fd6b6f
Author: Michael Meissner 
Date:   Thu Sep 26 18:06:51 2024 -0400

Merge commit 'refs/users/meissner/heads/work179-vpair' of 
git+ssh://gcc.gnu.org/git/gcc into me/work179-vpair

Diff:

[gcc r15-3910] c++: Update decl_linkage for C++11

[Nathaniel Shead via Gcc-cvs]

https://gcc.gnu.org/g:af4471cb422a867f1877c7c08bb63fa75afe

commit r15-3910-gaf4471cb422a867f1877c7c08bb63fa75afe
Author: Nathaniel Shead 
Date:   Mon Aug 19 16:38:41 2024 +1000

c++: Update decl_linkage for C++11

Currently modules code uses a variety of ad-hoc methods to attempt to
determine whether an entity has internal linkage, which leads to
inconsistencies and some correctness issues as different edge cases are
neglected.  While investigating this I discovered 'decl_linkage', but it
doesn't seem to have been updated to account for the C++11 clarification
that all entities declared in an anonymous namespace are internal.

I'm not convinced that even in C++98 it was intended that e.g. types in
anonymous namespaces should be external, but some tests in the testsuite
rely on this, so for compatibility I restricted those modifications to
C++11 and later.

This should have relatively minimal impact as not much seems to actually
rely on decl_linkage, but does change the mangling of symbols in
anonymous namespaces slightly.  Previously, we had

  namespace {
int x;  // mangled as '_ZN12_GLOBAL__N_11xE'
static int y;  // mangled as '_ZN12_GLOBAL__N_1L1yE'
  }

but with this patch the x is now mangled like y (with the extra 'L').
For contrast, Clang currently mangles neither x nor y with the 'L'.
Since this only affects internal-linkage entities I don't believe this
should break ABI in any observable fashion.

gcc/cp/ChangeLog:

* name-lookup.cc (do_namespace_alias): Propagate TREE_PUBLIC for
namespace aliases.
* tree.cc (decl_linkage): Update rules for C++11.

gcc/testsuite/ChangeLog:

* g++.dg/modules/mod-sym-4.C: Update test to account for
non-static internal-linkage variables new mangling.

Signed-off-by: Nathaniel Shead 
Reviewed-by: Jason Merrill 

Diff:
---
 gcc/cp/name-lookup.cc|  1 +
 gcc/cp/tree.cc   | 92 
 gcc/testsuite/g++.dg/modules/mod-sym-4.C |  4 +-
 3 files changed, 60 insertions(+), 37 deletions(-)

diff --git a/gcc/cp/name-lookup.cc b/gcc/cp/name-lookup.cc
index c7a693e02d59..50e169eca43e 100644
--- a/gcc/cp/name-lookup.cc
+++ b/gcc/cp/name-lookup.cc
@@ -6610,6 +6610,7 @@ do_namespace_alias (tree alias, tree name_space)
   DECL_NAMESPACE_ALIAS (alias) = name_space;
   DECL_EXTERNAL (alias) = 1;
   DECL_CONTEXT (alias) = FROB_CONTEXT (current_scope ());
+  TREE_PUBLIC (alias) = TREE_PUBLIC (DECL_CONTEXT (alias));
   set_originating_module (alias);
 
   pushdecl (alias);
diff --git a/gcc/cp/tree.cc b/gcc/cp/tree.cc
index e8d8b2ab6f70..0a7a56cc6e2e 100644
--- a/gcc/cp/tree.cc
+++ b/gcc/cp/tree.cc
@@ -5841,7 +5841,7 @@ char_type_p (tree type)
  || same_type_p (type, wchar_type_node));
 }
 
-/* Returns the kind of linkage associated with the indicated DECL.  Th
+/* Returns the kind of linkage associated with the indicated DECL.  The
value returned is as specified by the language standard; it is
independent of implementation details regarding template
instantiation, etc.  For example, it is possible that a declaration
@@ -5858,53 +5858,75 @@ decl_linkage (tree decl)
  linkage first, and then transform that into a concrete
  implementation.  */
 
-  /* Things that don't have names have no linkage.  */
-  if (!DECL_NAME (decl))
-return lk_none;
+  /* An explicit type alias has no linkage.  */
+  if (TREE_CODE (decl) == TYPE_DECL
+  && !DECL_IMPLICIT_TYPEDEF_P (decl)
+  && !DECL_SELF_REFERENCE_P (decl))
+{
+  /* But this could be a typedef name for linkage purposes, in which
+case we're interested in the linkage of the main decl.  */
+  if (decl == TYPE_NAME (TYPE_MAIN_VARIANT (TREE_TYPE (decl
+   decl = TYPE_MAIN_DECL (TREE_TYPE (decl));
+  else
+   return lk_none;
+}
 
-  /* Fields have no linkage.  */
-  if (TREE_CODE (decl) == FIELD_DECL)
+  /* Namespace-scope entities with no name usually have no linkage.  */
+  if (NAMESPACE_SCOPE_P (decl)
+  && (!DECL_NAME (decl) || IDENTIFIER_ANON_P (DECL_NAME (decl
+{
+  if (TREE_CODE (decl) == TYPE_DECL && !TYPE_ANON_P (TREE_TYPE (decl)))
+   /* This entity has a typedef name for linkage purposes.  */;
+  else if (TREE_CODE (decl) == NAMESPACE_DECL && cxx_dialect >= cxx11)
+   /* An anonymous namespace has internal linkage since C++11.  */
+   return lk_internal;
+  else
+   return lk_none;
+}
+
+  /* Fields and parameters have no linkage.  */
+  if (TREE_CODE (decl) == FIELD_DECL || TREE_CODE (decl) == PARM_DECL)
 return lk_none;
 
-  /* Things in local scope do not have linkage.  */
+  /* Things in block scope do not have linkage.  */
   if (decl_function_context (decl))
 return lk_none;
 
+  /* Things in class scope have the linkage 

[gcc r15-3911] c++/modules: Use decl_linkage in maybe_record_mergeable_decl

[Nathaniel Shead via Gcc-cvs]

https://gcc.gnu.org/g:ad08ef098a8c8bb9c148d0a32e91456fdf58ffc1

commit r15-3911-gad08ef098a8c8bb9c148d0a32e91456fdf58ffc1
Author: Nathaniel Shead 
Date:   Wed Sep 4 02:42:58 2024 +1000

c++/modules: Use decl_linkage in maybe_record_mergeable_decl

This avoids any possible inconsistencies (current or future) about
whether a declaration is internal or not.

gcc/cp/ChangeLog:

* name-lookup.cc (maybe_record_mergeable_decl): Use decl_linkage
instead of ad-hoc checks.

Signed-off-by: Nathaniel Shead 
Reviewed-by: Jason Merrill 

Diff:
---
 gcc/cp/name-lookup.cc | 9 +
 1 file changed, 1 insertion(+), 8 deletions(-)

diff --git a/gcc/cp/name-lookup.cc b/gcc/cp/name-lookup.cc
index 50e169eca43e..c0f89f98d87e 100644
--- a/gcc/cp/name-lookup.cc
+++ b/gcc/cp/name-lookup.cc
@@ -3725,17 +3725,10 @@ maybe_record_mergeable_decl (tree *slot, tree name, 
tree decl)
   if (TREE_CODE (*slot) != BINDING_VECTOR)
 return;
 
-  if (!TREE_PUBLIC (CP_DECL_CONTEXT (decl)))
-/* Member of internal namespace.  */
+  if (decl_linkage (decl) == lk_internal)
 return;
 
   tree not_tmpl = STRIP_TEMPLATE (decl);
-  if ((TREE_CODE (not_tmpl) == FUNCTION_DECL
-   || VAR_P (not_tmpl))
-  && DECL_THIS_STATIC (not_tmpl))
-/* Internal linkage.  */
-return;
-
   bool is_attached = (DECL_LANG_SPECIFIC (not_tmpl)
  && DECL_MODULE_ATTACH_P (not_tmpl));
   tree *gslot = get_fixed_binding_slot

[gcc r15-3912] c++/modules: Fix linkage checks for exported using-decls

[Nathaniel Shead via Gcc-cvs]

https://gcc.gnu.org/g:d0762e93ce1ed046e1dd9477ebe0ad941c298677

commit r15-3912-gd0762e93ce1ed046e1dd9477ebe0ad941c298677
Author: Nathaniel Shead 
Date:   Wed Sep 4 01:18:19 2024 +1000

c++/modules: Fix linkage checks for exported using-decls

This fixes some inconsistencies with what kinds of linkage various
entities are assumed to have.  This also fixes handling of exported
using-decls binding to GM entities and type aliases to better align with
the standard's requirements.

gcc/cp/ChangeLog:

* name-lookup.cc (check_can_export_using_decl): Handle internal
linkage GM entities (but ignore in header units); use linkage
of entity ultimately referred to by aliases.

gcc/testsuite/ChangeLog:

* g++.dg/modules/using-10.C: Add tests for no-linkage, fix
expected linkage of aliases.
* g++.dg/modules/using-12.C: Likewise.
* g++.dg/modules/using-27.C: New test.
* g++.dg/modules/using-28_a.C: New test.
* g++.dg/modules/using-28_b.C: New test.
* g++.dg/modules/using-29.H: New test.

Signed-off-by: Nathaniel Shead 
Reviewed-by: Jason Merrill 

Diff:
---
 gcc/cp/name-lookup.cc | 57 ++-
 gcc/testsuite/g++.dg/modules/using-10.C   | 56 +++---
 gcc/testsuite/g++.dg/modules/using-12.C   | 42 ---
 gcc/testsuite/g++.dg/modules/using-27.C   | 14 
 gcc/testsuite/g++.dg/modules/using-28_a.C | 12 +++
 gcc/testsuite/g++.dg/modules/using-28_b.C |  8 +
 gcc/testsuite/g++.dg/modules/using-29.H   |  6 
 7 files changed, 154 insertions(+), 41 deletions(-)

diff --git a/gcc/cp/name-lookup.cc b/gcc/cp/name-lookup.cc
index c0f89f98d87e..eb365b259d92 100644
--- a/gcc/cp/name-lookup.cc
+++ b/gcc/cp/name-lookup.cc
@@ -5206,38 +5206,47 @@ pushdecl_outermost_localscope (tree x)
 static bool
 check_can_export_using_decl (tree binding)
 {
-  tree decl = STRIP_TEMPLATE (binding);
-
-  /* Linkage is determined by the owner of an enumerator.  */
-  if (TREE_CODE (decl) == CONST_DECL)
-decl = TYPE_NAME (DECL_CONTEXT (decl));
+  /* Declarations in header units are always OK.  */
+  if (header_module_p ())
+return true;
 
-  /* If the using decl is exported, the things it refers
- to must also be exported (or not have module attachment).  */
-  if (!DECL_MODULE_EXPORT_P (decl)
-  && (DECL_LANG_SPECIFIC (decl)
- && DECL_MODULE_ATTACH_P (decl)))
+  /* We want the linkage of the underlying entity, so strip typedefs.
+ If the underlying entity is a builtin type then we're OK.  */
+  tree entity = binding;
+  if (TREE_CODE (entity) == TYPE_DECL)
 {
-  bool internal_p = !TREE_PUBLIC (decl);
+  entity = TYPE_MAIN_DECL (TREE_TYPE (entity));
+  if (!entity)
+   return true;
+}
 
-  /* A template in an anonymous namespace doesn't constrain TREE_PUBLIC
-until it's instantiated, so double-check its context.  */
-  if (!internal_p && TREE_CODE (binding) == TEMPLATE_DECL)
-   internal_p = decl_internal_context_p (decl);
+  linkage_kind linkage = decl_linkage (entity);
+  tree not_tmpl = STRIP_TEMPLATE (entity);
 
+  /* Attachment is determined by the owner of an enumerator.  */
+  if (TREE_CODE (not_tmpl) == CONST_DECL)
+not_tmpl = TYPE_NAME (DECL_CONTEXT (not_tmpl));
+
+  /* If the using decl is exported, the things it refers to must
+ have external linkage.  decl_linkage returns lk_external for
+ module linkage so also check for attachment.  */
+  if (linkage != lk_external
+  || (DECL_LANG_SPECIFIC (not_tmpl)
+ && DECL_MODULE_ATTACH_P (not_tmpl)
+ && !DECL_MODULE_EXPORT_P (not_tmpl)))
+{
   auto_diagnostic_group d;
   error ("exporting %q#D that does not have external linkage",
 binding);
-  if (TREE_CODE (decl) == TYPE_DECL && !DECL_IMPLICIT_TYPEDEF_P (decl))
-   /* An un-exported explicit type alias has no linkage.  */
-   inform (DECL_SOURCE_LOCATION (binding),
-   "%q#D declared here with no linkage", binding);
-  else if (internal_p)
-   inform (DECL_SOURCE_LOCATION (binding),
-   "%q#D declared here with internal linkage", binding);
+  if (linkage == lk_none)
+   inform (DECL_SOURCE_LOCATION (entity),
+   "%q#D declared here with no linkage", entity);
+  else if (linkage == lk_internal)
+   inform (DECL_SOURCE_LOCATION (entity),
+   "%q#D declared here with internal linkage", entity);
   else
-   inform (DECL_SOURCE_LOCATION (binding),
-   "%q#D declared here with module linkage", binding);
+   inform (DECL_SOURCE_LOCATION (entity),
+   "%q#D declared here with module linkage", entity);
   return false;
 }
 
diff --git a/gcc/testsuite/g++.dg/modules/using-10.C 
b/gcc/testsuite/g++.dg/modules/using-10.C
index d468a36f5d

[gcc r15-3913] c++/modules: Allow imported references in constant expressions

[Nathaniel Shead via Gcc-cvs]

https://gcc.gnu.org/g:1a0b33ebc57ebcc9595b19050f5c36c1f9d39e3e

commit r15-3913-g1a0b33ebc57ebcc9595b19050f5c36c1f9d39e3e
Author: Nathaniel Shead 
Date:   Thu Sep 12 20:06:39 2024 +1000

c++/modules: Allow imported references in constant expressions

Currently the streaming code uses TREE_CONSTANT to determine whether an
entity will have a definition that is interesting to stream out.  This
is not sufficient, however; we also need to write the definition of
references, since although not TREE_CONSTANT they can still be usable in
constant expressions.

As such this patch uses the existing decl_maybe_constant_var function
which correctly handles this case.

gcc/cp/ChangeLog:

* module.cc (has_definition): Use decl_maybe_constant_var
instead of TREE_CONSTANT.

gcc/testsuite/ChangeLog:

* g++.dg/modules/cexpr-5_a.C: New test.
* g++.dg/modules/cexpr-5_b.C: New test.

Signed-off-by: Nathaniel Shead 
Reviewed-by: Jason Merrill 

Diff:
---
 gcc/cp/module.cc |  2 +-
 gcc/testsuite/g++.dg/modules/cexpr-5_a.C | 13 +
 gcc/testsuite/g++.dg/modules/cexpr-5_b.C |  9 +
 3 files changed, 23 insertions(+), 1 deletion(-)

diff --git a/gcc/cp/module.cc b/gcc/cp/module.cc
index f5df9e875d3a..65b37b4b5544 100644
--- a/gcc/cp/module.cc
+++ b/gcc/cp/module.cc
@@ -11829,7 +11829,7 @@ has_definition (tree decl)
   since there's no TU to emit them in otherwise.  */
return true;
 
- if (!TREE_CONSTANT (decl))
+ if (!decl_maybe_constant_var_p (decl))
return false;
 
  return true;
diff --git a/gcc/testsuite/g++.dg/modules/cexpr-5_a.C 
b/gcc/testsuite/g++.dg/modules/cexpr-5_a.C
new file mode 100644
index ..3a9f00523f65
--- /dev/null
+++ b/gcc/testsuite/g++.dg/modules/cexpr-5_a.C
@@ -0,0 +1,13 @@
+// { dg-additional-options "-fmodules-ts" }
+// { dg-module-cmi M }
+
+export module M;
+
+int x = 123;
+void f() {}
+
+int& xr = x;
+auto& fr = f;
+
+constexpr int& cxr = xr;
+constexpr auto& cfr = fr;
diff --git a/gcc/testsuite/g++.dg/modules/cexpr-5_b.C 
b/gcc/testsuite/g++.dg/modules/cexpr-5_b.C
new file mode 100644
index ..4b1b901104bc
--- /dev/null
+++ b/gcc/testsuite/g++.dg/modules/cexpr-5_b.C
@@ -0,0 +1,9 @@
+// { dg-additional-options "-fmodules-ts" }
+
+module M;
+
+constexpr auto& use_xr = xr;
+constexpr auto& use_fr = fr;
+
+static_assert(&cxr == &use_xr);
+static_assert(&cfr == &use_fr);

[gcc(refs/users/meissner/heads/work179)] Add ChangeLog.meissner and REVISION.

[Michael Meissner via Libstdc++-cvs]

https://gcc.gnu.org/g:5eacddda9eaaacb82a489abcf314980b00f51227

commit 5eacddda9eaaacb82a489abcf314980b00f51227
Author: Michael Meissner 
Date:   Thu Sep 26 17:21:42 2024 -0400

Add ChangeLog.meissner and REVISION.

2024-09-26  Michael Meissner  

gcc/

* REVISION: New file for branch.
* ChangeLog.meissner: New file.

gcc/c-family/

* ChangeLog.meissner: New file.

gcc/c/

* ChangeLog.meissner: New file.

gcc/cp/

* ChangeLog.meissner: New file.

gcc/fortran/

* ChangeLog.meissner: New file.

gcc/testsuite/

* ChangeLog.meissner: New file.

libgcc/

* ChangeLog.meissner: New file.

Diff:
---
 gcc/ChangeLog.meissner   | 6 ++
 gcc/REVISION | 1 +
 gcc/c-family/ChangeLog.meissner  | 6 ++
 gcc/c/ChangeLog.meissner | 6 ++
 gcc/cp/ChangeLog.meissner| 6 ++
 gcc/fortran/ChangeLog.meissner   | 6 ++
 gcc/testsuite/ChangeLog.meissner | 6 ++
 libgcc/ChangeLog.meissner| 6 ++
 libstdc++-v3/ChangeLog.meissner  | 6 ++
 9 files changed, 49 insertions(+)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
new file mode 100644
index ..fbfd92e81273
--- /dev/null
+++ b/gcc/ChangeLog.meissner
@@ -0,0 +1,6 @@
+ Branch work179, baseline 
+
+2024-09-26   Michael Meissner  
+
+   Clone branch
+
diff --git a/gcc/REVISION b/gcc/REVISION
new file mode 100644
index ..3f5e8bfabc6b
--- /dev/null
+++ b/gcc/REVISION
@@ -0,0 +1 @@
+work179 branch
diff --git a/gcc/c-family/ChangeLog.meissner b/gcc/c-family/ChangeLog.meissner
new file mode 100644
index ..fbfd92e81273
--- /dev/null
+++ b/gcc/c-family/ChangeLog.meissner
@@ -0,0 +1,6 @@
+ Branch work179, baseline 
+
+2024-09-26   Michael Meissner  
+
+   Clone branch
+
diff --git a/gcc/c/ChangeLog.meissner b/gcc/c/ChangeLog.meissner
new file mode 100644
index ..fbfd92e81273
--- /dev/null
+++ b/gcc/c/ChangeLog.meissner
@@ -0,0 +1,6 @@
+ Branch work179, baseline 
+
+2024-09-26   Michael Meissner  
+
+   Clone branch
+
diff --git a/gcc/cp/ChangeLog.meissner b/gcc/cp/ChangeLog.meissner
new file mode 100644
index ..fbfd92e81273
--- /dev/null
+++ b/gcc/cp/ChangeLog.meissner
@@ -0,0 +1,6 @@
+ Branch work179, baseline 
+
+2024-09-26   Michael Meissner  
+
+   Clone branch
+
diff --git a/gcc/fortran/ChangeLog.meissner b/gcc/fortran/ChangeLog.meissner
new file mode 100644
index ..fbfd92e81273
--- /dev/null
+++ b/gcc/fortran/ChangeLog.meissner
@@ -0,0 +1,6 @@
+ Branch work179, baseline 
+
+2024-09-26   Michael Meissner  
+
+   Clone branch
+
diff --git a/gcc/testsuite/ChangeLog.meissner b/gcc/testsuite/ChangeLog.meissner
new file mode 100644
index ..fbfd92e81273
--- /dev/null
+++ b/gcc/testsuite/ChangeLog.meissner
@@ -0,0 +1,6 @@
+ Branch work179, baseline 
+
+2024-09-26   Michael Meissner  
+
+   Clone branch
+
diff --git a/libgcc/ChangeLog.meissner b/libgcc/ChangeLog.meissner
new file mode 100644
index ..fbfd92e81273
--- /dev/null
+++ b/libgcc/ChangeLog.meissner
@@ -0,0 +1,6 @@
+ Branch work179, baseline 
+
+2024-09-26   Michael Meissner  
+
+   Clone branch
+
diff --git a/libstdc++-v3/ChangeLog.meissner b/libstdc++-v3/ChangeLog.meissner
new file mode 100644
index ..fbfd92e81273
--- /dev/null
+++ b/libstdc++-v3/ChangeLog.meissner
@@ -0,0 +1,6 @@
+ Branch work179, baseline 
+
+2024-09-26   Michael Meissner  
+
+   Clone branch
+

[gcc] Created branch 'meissner/heads/work179-vpair' in namespace 'refs/users'

[Michael Meissner via Gcc-cvs]

The branch 'meissner/heads/work179-vpair' was created in namespace 'refs/users' 
pointing to:

 5eacddda9eaa... Add ChangeLog.meissner and REVISION.

[gcc] Created branch 'meissner/heads/work179-dmf' in namespace 'refs/users'

[Michael Meissner via Gcc-cvs]

The branch 'meissner/heads/work179-dmf' was created in namespace 'refs/users' 
pointing to:

 5eacddda9eaa... Add ChangeLog.meissner and REVISION.

[gcc(refs/users/meissner/heads/work179-vpair)] Add ChangeLog.vpair and update REVISION.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:132564fd6b6fc8b6c4e3e9958f4a41ba49951867

commit 132564fd6b6fc8b6c4e3e9958f4a41ba49951867
Author: Michael Meissner 
Date:   Thu Sep 26 17:24:17 2024 -0400

Add ChangeLog.vpair and update REVISION.

2024-09-26  Michael Meissner  

gcc/

* ChangeLog.vpair: New file for branch.
* REVISION: Update.

Diff:
---
 gcc/ChangeLog.vpair | 6 ++
 gcc/REVISION| 2 +-
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/gcc/ChangeLog.vpair b/gcc/ChangeLog.vpair
new file mode 100644
index ..7c411bb99148
--- /dev/null
+++ b/gcc/ChangeLog.vpair
@@ -0,0 +1,6 @@
+ Branch work179-vpair, baseline 
+
+2024-09-26   Michael Meissner  
+
+   Clone branch
+
diff --git a/gcc/REVISION b/gcc/REVISION
index 3f5e8bfabc6b..5b4edbbca081 100644
--- a/gcc/REVISION
+++ b/gcc/REVISION
@@ -1 +1 @@
-work179 branch
+work179-vpair branch

[gcc] Created branch 'meissner/heads/work179-tar' in namespace 'refs/users'

[Michael Meissner via Gcc-cvs]

The branch 'meissner/heads/work179-tar' was created in namespace 'refs/users' 
pointing to:

 5eacddda9eaa... Add ChangeLog.meissner and REVISION.

[gcc(refs/users/meissner/heads/work179-bugs)] Add ChangeLog.bugs and update REVISION.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:079c521b611d1bff9681a5dae25d0e5d44dc0050

commit 079c521b611d1bff9681a5dae25d0e5d44dc0050
Author: Michael Meissner 
Date:   Thu Sep 26 17:27:26 2024 -0400

Add ChangeLog.bugs and update REVISION.

2024-09-26  Michael Meissner  

gcc/

* ChangeLog.bugs: New file for branch.
* REVISION: Update.

Diff:
---
 gcc/ChangeLog.bugs | 6 ++
 gcc/REVISION   | 2 +-
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/gcc/ChangeLog.bugs b/gcc/ChangeLog.bugs
new file mode 100644
index ..0f361fb7d770
--- /dev/null
+++ b/gcc/ChangeLog.bugs
@@ -0,0 +1,6 @@
+ Branch work179-bugs, baseline 
+
+2024-09-26   Michael Meissner  
+
+   Clone branch
+
diff --git a/gcc/REVISION b/gcc/REVISION
index 3f5e8bfabc6b..17f24a8d4513 100644
--- a/gcc/REVISION
+++ b/gcc/REVISION
@@ -1 +1 @@
-work179 branch
+work179-bugs branch

[gcc] Created branch 'meissner/heads/work179-bugs' in namespace 'refs/users'

[Michael Meissner via Gcc-cvs]

The branch 'meissner/heads/work179-bugs' was created in namespace 'refs/users' 
pointing to:

 5eacddda9eaa... Add ChangeLog.meissner and REVISION.

[gcc] Created branch 'meissner/heads/work179-libs' in namespace 'refs/users'

[Michael Meissner via Gcc-cvs]

The branch 'meissner/heads/work179-libs' was created in namespace 'refs/users' 
pointing to:

 5eacddda9eaa... Add ChangeLog.meissner and REVISION.

[gcc] Created branch 'meissner/heads/work179-test' in namespace 'refs/users'

[Michael Meissner via Gcc-cvs]

The branch 'meissner/heads/work179-test' was created in namespace 'refs/users' 
pointing to:

 5eacddda9eaa... Add ChangeLog.meissner and REVISION.

[gcc(refs/users/meissner/heads/work179-libs)] Add ChangeLog.libs and update REVISION.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:27a1b94afdc06f631a5cce316eaa76847f9c725b

commit 27a1b94afdc06f631a5cce316eaa76847f9c725b
Author: Michael Meissner 
Date:   Thu Sep 26 17:28:53 2024 -0400

Add ChangeLog.libs and update REVISION.

2024-09-26  Michael Meissner  

gcc/

* ChangeLog.libs: New file for branch.
* REVISION: Update.

Diff:
---
 gcc/ChangeLog.libs | 6 ++
 gcc/REVISION   | 2 +-
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/gcc/ChangeLog.libs b/gcc/ChangeLog.libs
new file mode 100644
index ..79f3765e1c03
--- /dev/null
+++ b/gcc/ChangeLog.libs
@@ -0,0 +1,6 @@
+ Branch work179-libs, baseline 
+
+2024-09-26   Michael Meissner  
+
+   Clone branch
+
diff --git a/gcc/REVISION b/gcc/REVISION
index 3f5e8bfabc6b..6b22264932c2 100644
--- a/gcc/REVISION
+++ b/gcc/REVISION
@@ -1 +1 @@
-work179 branch
+work179-libs branch

[gcc(refs/users/meissner/heads/work179-test)] Add ChangeLog.test and update REVISION.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:7e24e5072cb3dfc6c52a11b5edaa3255d6063e68

commit 7e24e5072cb3dfc6c52a11b5edaa3255d6063e68
Author: Michael Meissner 
Date:   Thu Sep 26 17:29:58 2024 -0400

Add ChangeLog.test and update REVISION.

2024-09-26  Michael Meissner  

gcc/

* ChangeLog.test: New file for branch.
* REVISION: Update.

Diff:
---
 gcc/ChangeLog.test | 6 ++
 gcc/REVISION   | 2 +-
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/gcc/ChangeLog.test b/gcc/ChangeLog.test
new file mode 100644
index ..7edfd3ba5e76
--- /dev/null
+++ b/gcc/ChangeLog.test
@@ -0,0 +1,6 @@
+ Branch work179-test, baseline 
+
+2024-09-26   Michael Meissner  
+
+   Clone branch
+
diff --git a/gcc/REVISION b/gcc/REVISION
index 3f5e8bfabc6b..c9c7a7b181ec 100644
--- a/gcc/REVISION
+++ b/gcc/REVISION
@@ -1 +1 @@
-work179 branch
+work179-test branch

[gcc] Created branch 'meissner/heads/work179-orig' in namespace 'refs/users'

[Michael Meissner via Gcc-cvs]

The branch 'meissner/heads/work179-orig' was created in namespace 'refs/users' 
pointing to:

 ee9f00606f18... libstdc++: Preserve signbit of nan when converting float to

[gcc(refs/users/meissner/heads/work179-dmf)] Add ChangeLog.dmf and update REVISION.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:8470e45643a8fc01f45a8e1952b9134e55b78ffc

commit 8470e45643a8fc01f45a8e1952b9134e55b78ffc
Author: Michael Meissner 
Date:   Thu Sep 26 17:22:56 2024 -0400

Add ChangeLog.dmf and update REVISION.

2024-09-26  Michael Meissner  

gcc/

* ChangeLog.dmf: New file for branch.
* REVISION: Update.

Diff:
---
 gcc/ChangeLog.dmf | 6 ++
 gcc/REVISION  | 2 +-
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/gcc/ChangeLog.dmf b/gcc/ChangeLog.dmf
new file mode 100644
index ..a0df4b147451
--- /dev/null
+++ b/gcc/ChangeLog.dmf
@@ -0,0 +1,6 @@
+ Branch work179-dmf, baseline 
+
+2024-09-26   Michael Meissner  
+
+   Clone branch
+
diff --git a/gcc/REVISION b/gcc/REVISION
index 3f5e8bfabc6b..b1e1ca189330 100644
--- a/gcc/REVISION
+++ b/gcc/REVISION
@@ -1 +1 @@
-work179 branch
+work179-dmf branch

[gcc(refs/users/meissner/heads/work179-tar)] Add ChangeLog.tar and update REVISION.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:1435fde963395e70a083b3cf8329e7e0f8379824

commit 1435fde963395e70a083b3cf8329e7e0f8379824
Author: Michael Meissner 
Date:   Thu Sep 26 17:25:55 2024 -0400

Add ChangeLog.tar and update REVISION.

2024-09-26  Michael Meissner  

gcc/

* ChangeLog.tar: New file for branch.
* REVISION: Update.

Diff:
---
 gcc/ChangeLog.tar | 6 ++
 gcc/REVISION  | 2 +-
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/gcc/ChangeLog.tar b/gcc/ChangeLog.tar
new file mode 100644
index ..fbc82a323070
--- /dev/null
+++ b/gcc/ChangeLog.tar
@@ -0,0 +1,6 @@
+ Branch work179-tar, baseline 
+
+2024-09-26   Michael Meissner  
+
+   Clone branch
+
diff --git a/gcc/REVISION b/gcc/REVISION
index 3f5e8bfabc6b..e0242fb5a986 100644
--- a/gcc/REVISION
+++ b/gcc/REVISION
@@ -1 +1 @@
-work179 branch
+work179-tar branch

[gcc(refs/users/meissner/heads/work179)] Add support for -mcpu=future

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:3ddfde53fc11a44f960b1a55a783a5863f12b0c7

commit 3ddfde53fc11a44f960b1a55a783a5863f12b0c7
Author: Michael Meissner 
Date:   Thu Sep 26 17:51:29 2024 -0400

Add support for -mcpu=future

This patch adds the support that can be used in developing GCC support for
future PowerPC processors.

2024-09-26  Michael Meissner  

* config.gcc (powerpc*-*-*): Add support for --with-cpu=future.
* config/rs6000/aix71.h (ASM_CPU_SPEC): Add support for 
-mcpu=future.
* config/rs6000/aix72.h (ASM_CPU_SPEC): Likewise.
* config/rs6000/aix73.h (ASM_CPU_SPEC): Likewise.
* config/rs6000/driver-rs6000.cc (asm_names): Likewise.
* config/rs6000/rs6000-arch.def: Add future cpu.
* config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): If
-mcpu=future, define _ARCH_FUTURE.
* config/rs6000/rs6000-cpus.def (FUTURE_MASKS_SERVER): New macro.
(future cpu): Define.
* config/rs6000/rs6000-opts.h (enum processor_type): Add
PROCESSOR_FUTURE.
* config/rs6000/rs6000-tables.opt: Regenerate.
* config/rs6000/rs6000.cc (power10_cost): Update comment.
(get_arch_flags): Add support for future processor.
(rs6000_option_override_internal): Likewise.
(rs6000_machine_from_flags): Likewise.
(rs6000_reassociation_width): Likewise.
(rs6000_adjust_cost): Likewise.
(rs6000_issue_rate): Likewise.
(rs6000_sched_reorder): Likewise.
(rs6000_sched_reorder2): Likewise.
(rs6000_register_move_cost): Likewise.
* config/rs6000/rs6000.h (ASM_CPU_SPEC): Likewise.
(TARGET_POWER11): New macro.
* config/rs6000/rs6000.md (cpu attribute): Likewise.

Diff:
---
 gcc/config.gcc  |  4 ++--
 gcc/config/rs6000/aix71.h   |  1 +
 gcc/config/rs6000/aix72.h   |  1 +
 gcc/config/rs6000/aix73.h   |  1 +
 gcc/config/rs6000/driver-rs6000.cc  |  2 ++
 gcc/config/rs6000/rs6000-arch.def   |  1 +
 gcc/config/rs6000/rs6000-c.cc   |  2 ++
 gcc/config/rs6000/rs6000-cpus.def   |  3 +++
 gcc/config/rs6000/rs6000-opts.h |  1 +
 gcc/config/rs6000/rs6000-tables.opt | 11 +++
 gcc/config/rs6000/rs6000.cc | 34 ++
 gcc/config/rs6000/rs6000.h  |  2 ++
 gcc/config/rs6000/rs6000.md |  2 +-
 13 files changed, 50 insertions(+), 15 deletions(-)

diff --git a/gcc/config.gcc b/gcc/config.gcc
index f09ce9f63a01..0b794e977f6a 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -539,7 +539,7 @@ powerpc*-*-*)
extra_headers="${extra_headers} ppu_intrinsics.h spu2vmx.h vec_types.h 
si2vmx.h"
extra_headers="${extra_headers} amo.h"
case x$with_cpu in
-   
xpowerpc64|xdefault64|x6[23]0|x970|xG5|xpower[3456789]|xpower1[01]|xpower6x|xrs64a|xcell|xa2|xe500mc64|xe5500|xe6500)
+   
xpowerpc64|xdefault64|x6[23]0|x970|xG5|xpower[3456789]|xpower1[01]|xpower6x|xrs64a|xcell|xa2|xe500mc64|xe5500|xe6500|xfuture)
cpu_is_64bit=yes
;;
esac
@@ -5646,7 +5646,7 @@ case "${target}" in
tm_defines="${tm_defines} CONFIG_PPC405CR"
eval "with_$which=405"
;;
-   "" | common | native \
+   "" | common | native | future \
| power[3456789] | power1[01] | power5+ | power6x \
| powerpc | powerpc64 | powerpc64le \
| rs64 \
diff --git a/gcc/config/rs6000/aix71.h b/gcc/config/rs6000/aix71.h
index 41037b3852d7..570ddcc451db 100644
--- a/gcc/config/rs6000/aix71.h
+++ b/gcc/config/rs6000/aix71.h
@@ -79,6 +79,7 @@ do {  
\
 #undef ASM_CPU_SPEC
 #define ASM_CPU_SPEC \
 "%{mcpu=native: %(asm_cpu_native); \
+  mcpu=future: -mfuture; \
   mcpu=power11: -mpwr11; \
   mcpu=power10: -mpwr10; \
   mcpu=power9: -mpwr9; \
diff --git a/gcc/config/rs6000/aix72.h b/gcc/config/rs6000/aix72.h
index fe59f8319b48..242ca94bd065 100644
--- a/gcc/config/rs6000/aix72.h
+++ b/gcc/config/rs6000/aix72.h
@@ -79,6 +79,7 @@ do {  
\
 #undef ASM_CPU_SPEC
 #define ASM_CPU_SPEC \
 "%{mcpu=native: %(asm_cpu_native); \
+  mcpu=future: -mfuture; \
   mcpu=power11: -mpwr11; \
   mcpu=power10: -mpwr10; \
   mcpu=power9: -mpwr9; \
diff --git a/gcc/config/rs6000/aix73.h b/gcc/config/rs6000/aix73.h
index 1318b0b3662d..2bd6b4bb3c4f 100644
--- a/gcc/config/rs6000/aix73.h
+++ b/gcc/config/rs6000/aix73.h
@@ -79,6 +79,7 @@ do {  
\
 #undef ASM_CPU_SPEC
 #define ASM_CPU_SPEC \
 "%{mcpu=native: %(asm_cpu_native); \
+  mcpu=future: -mfuture; \
   mcpu=power11: -

[gcc(refs/users/meissner/heads/work179)] Update ChangeLog.*

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:42a052d69e1738c774bf10262b69a9256dcf97ad

commit 42a052d69e1738c774bf10262b69a9256dcf97ad
Author: Michael Meissner 
Date:   Thu Sep 26 17:57:05 2024 -0400

Update ChangeLog.*

Diff:
---
 gcc/ChangeLog.meissner | 449 -
 1 file changed, 448 insertions(+), 1 deletion(-)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index fbfd92e81273..a6241af36bb8 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,6 +1,453 @@
+ Branch work179, patch #21 
+
+Add -mcpu=future tuning support.
+
+This patch makes -mtune=future use the same tuning decision as -mtune=power11.
+
+2024-09-26  Michael Meissner  
+
+gcc/
+
+   * config/rs6000/power10.md (all reservations): Add future as an
+   alterntive to power10 and power11.
+
+ Branch work179, patch #20 
+
+Add support for -mcpu=future
+
+This patch adds the support that can be used in developing GCC support for
+future PowerPC processors.
+
+2024-09-26  Michael Meissner  
+
+   * config.gcc (powerpc*-*-*): Add support for --with-cpu=future.
+   * config/rs6000/aix71.h (ASM_CPU_SPEC): Add support for -mcpu=future.
+   * config/rs6000/aix72.h (ASM_CPU_SPEC): Likewise.
+   * config/rs6000/aix73.h (ASM_CPU_SPEC): Likewise.
+   * config/rs6000/driver-rs6000.cc (asm_names): Likewise.
+   * config/rs6000/rs6000-arch.def: Add future cpu.
+   * config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): If
+   -mcpu=future, define _ARCH_FUTURE.
+   * config/rs6000/rs6000-cpus.def (FUTURE_MASKS_SERVER): New macro.
+   (future cpu): Define.
+   * config/rs6000/rs6000-opts.h (enum processor_type): Add
+   PROCESSOR_FUTURE.
+   * config/rs6000/rs6000-tables.opt: Regenerate.
+   * config/rs6000/rs6000.cc (power10_cost): Update comment.
+   (get_arch_flags): Add support for future processor.
+   (rs6000_option_override_internal): Likewise.
+   (rs6000_machine_from_flags): Likewise.
+   (rs6000_reassociation_width): Likewise.
+   (rs6000_adjust_cost): Likewise.
+   (rs6000_issue_rate): Likewise.
+   (rs6000_sched_reorder): Likewise.
+   (rs6000_sched_reorder2): Likewise.
+   (rs6000_register_move_cost): Likewise.
+   * config/rs6000/rs6000.h (ASM_CPU_SPEC): Likewise.
+   (TARGET_POWER11): New macro.
+   * config/rs6000/rs6000.md (cpu attribute): Likewise.
+
+ Branch work179, patch #9 
+
+Update tests to work with architecture flags changes.
+
+Two tests used -mvsx to raise the processor level to at least power7.  These
+tests were rewritten to add cpu=power7 support.
+
+I have built both big endian and little endian bootstrap compilers and there
+were no regressions.
+
+In addition, I constructed a test case that used every archiecture define (like
+_ARCH_PWR4, etc.) and I also looked at the .machine directive generated.  I ran
+this test for all supported combinations of -mcpu, big/little endian, and 32/64
+bit support.  Every single instance generated exactly the same code with the
+patches installed compared to the compiler before installing the patches.
+
+Can I install this patch on the GCC 15 trunk?
+
+2024-09-26  Michael Meissner  
+
+gcc/testsuite/
+
+   * gcc.target/powerpc/ppc-target-4.c: Rewrite the test to add cpu=power7
+   when we need to add VSX support.  Add test for adding cpu=power7 no-vsx
+   to generate only Altivec instructions.
+   * gcc.target/powerpc/pr115688.c: Add cpu=power7 when requesting VSX
+   instructions.
+
+ Branch work179, patch #8 
+
+Change TARGET_MODULO to TARGET_POWER9
+
+As part of the architecture flags patches, this patch changes the use of
+TARGET_MODULO to TARGET_POWER9.  The modulo instructions were added in power9 
(ISA
+3.0).  Note, I did not change the uses of TARGET_MODULO where it was explicitly
+generating different code if the machine had a modulo instruction.
+
+I have built both big endian and little endian bootstrap compilers and there
+were no regressions.
+
+In addition, I constructed a test case that used every archiecture define (like
+_ARCH_PWR4, etc.) and I also looked at the .machine directive generated.  I ran
+this test for all supported combinations of -mcpu, big/little endian, and 32/64
+bit support.  Every single instance generated exactly the same code with the
+patches installed compared to the compiler before installing the patches.
+
+Can I install this patch on the GCC 15 trunk?
+
+2024-09-26  Michael Meissner  
+
+   * config/rs6000/rs6000-builtin.cc (rs6000_builtin_is_supported): Use
+   TARGET_POWER9 instead of TARGET_MODULO.
+   * config/rs6000/rs6000.h (TARGET_CTZ): Likewise.
+   (TARGET_EXTSWSLI): Likewise.
+   (TARGET_MADDLD): Likewise.
+   * config/rs6000/rs6000.md (enabled attribute): Likewise.
+
+

[gcc/meissner/heads/work179-bugs] (14 commits) Merge commit 'refs/users/meissner/heads/work179-bugs' of gi

[Michael Meissner via Gcc-cvs]

The branch 'meissner/heads/work179-bugs' was updated to point to:

 c4d9b8e47ce0... Merge commit 'refs/users/meissner/heads/work179-bugs' of gi

It previously pointed to:

 079c521b611d... Add ChangeLog.bugs and update REVISION.

Diff:

Summary of changes (added commits):
---

  c4d9b8e... Merge commit 'refs/users/meissner/heads/work179-bugs' of gi
  a8e789b... Add ChangeLog.bugs and update REVISION.
  42a052d... Update ChangeLog.* (*)
  694e6ba... Add -mcpu=future tuning support. (*)
  3ddfde5... Add support for -mcpu=future (*)
  c619658... Update tests to work with architecture flags changes. (*)
  58a18a3... Change TARGET_MODULO to TARGET_POWER9 (*)
  c375562... Change TARGET_POPCNTD to TARGET_POWER7 (*)
  489e6e2... Change TARGET_CMPB to TARGET_POWER6 (*)
  251c4aa... Change TARGET_FPRND to TARGET_POWER5X (*)
  fa4fe45... Change TARGET_POPCNTB to TARGET_POWER5 (*)
  02aa84a... Do not allow -mvsx to boost processor to power7. (*)
  34e7c57... Use architecture flags for defining _ARCH_PWR macros. (*)
  1aa6493... Add rs6000 architecture masks. (*)

(*) This commit already exists in another branch.
Because the reference `refs/users/meissner/heads/work179-bugs' matches
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no separate email is sent for this commit.

[gcc(refs/users/meissner/heads/work179-bugs)] Add ChangeLog.bugs and update REVISION.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:a8e789bdc4ddcf1c32d5f78a3f01145127235a05

commit a8e789bdc4ddcf1c32d5f78a3f01145127235a05
Author: Michael Meissner 
Date:   Thu Sep 26 17:27:26 2024 -0400

Add ChangeLog.bugs and update REVISION.

2024-09-26  Michael Meissner  

gcc/

* ChangeLog.bugs: New file for branch.
* REVISION: Update.

Diff:
---
 gcc/ChangeLog.bugs | 6 ++
 gcc/REVISION   | 2 +-
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/gcc/ChangeLog.bugs b/gcc/ChangeLog.bugs
new file mode 100644
index ..0f361fb7d770
--- /dev/null
+++ b/gcc/ChangeLog.bugs
@@ -0,0 +1,6 @@
+ Branch work179-bugs, baseline 
+
+2024-09-26   Michael Meissner  
+
+   Clone branch
+
diff --git a/gcc/REVISION b/gcc/REVISION
index 3f5e8bfabc6b..17f24a8d4513 100644
--- a/gcc/REVISION
+++ b/gcc/REVISION
@@ -1 +1 @@
-work179 branch
+work179-bugs branch

[gcc(refs/users/meissner/heads/work179-bugs)] Merge commit 'refs/users/meissner/heads/work179-bugs' of git+ssh://gcc.gnu.org/git/gcc into me/work1

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:c4d9b8e47ce07480fa2aa1a875402d0a3c896254

commit c4d9b8e47ce07480fa2aa1a875402d0a3c896254
Merge: a8e789bdc4dd 079c521b611d
Author: Michael Meissner 
Date:   Thu Sep 26 17:57:51 2024 -0400

Merge commit 'refs/users/meissner/heads/work179-bugs' of 
git+ssh://gcc.gnu.org/git/gcc into me/work179-bugs

Diff:

[gcc/meissner/heads/work179-dmf] (14 commits) Merge commit 'refs/users/meissner/heads/work179-dmf' of git

[Michael Meissner via Gcc-cvs]

The branch 'meissner/heads/work179-dmf' was updated to point to:

 e06cd809bf53... Merge commit 'refs/users/meissner/heads/work179-dmf' of git

It previously pointed to:

 8470e45643a8... Add ChangeLog.dmf and update REVISION.

Diff:

Summary of changes (added commits):
---

  e06cd80... Merge commit 'refs/users/meissner/heads/work179-dmf' of git
  56aef59... Add ChangeLog.dmf and update REVISION.
  42a052d... Update ChangeLog.* (*)
  694e6ba... Add -mcpu=future tuning support. (*)
  3ddfde5... Add support for -mcpu=future (*)
  c619658... Update tests to work with architecture flags changes. (*)
  58a18a3... Change TARGET_MODULO to TARGET_POWER9 (*)
  c375562... Change TARGET_POPCNTD to TARGET_POWER7 (*)
  489e6e2... Change TARGET_CMPB to TARGET_POWER6 (*)
  251c4aa... Change TARGET_FPRND to TARGET_POWER5X (*)
  fa4fe45... Change TARGET_POPCNTB to TARGET_POWER5 (*)
  02aa84a... Do not allow -mvsx to boost processor to power7. (*)
  34e7c57... Use architecture flags for defining _ARCH_PWR macros. (*)
  1aa6493... Add rs6000 architecture masks. (*)

(*) This commit already exists in another branch.
Because the reference `refs/users/meissner/heads/work179-dmf' matches
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[gcc(refs/users/meissner/heads/work179)] Change TARGET_POPCNTD to TARGET_POWER7

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:c3755622a412dfdf841470b9af77826ec3cb21c5

commit c3755622a412dfdf841470b9af77826ec3cb21c5
Author: Michael Meissner 
Date:   Thu Sep 26 17:44:26 2024 -0400

Change TARGET_POPCNTD to TARGET_POWER7

As part of the architecture flags patches, this patch changes the use of
TARGET_POPCNTD to TARGET_POWER7.  The POPCNTD instruction was added in 
power7
(ISA 2.06).

I have built both big endian and little endian bootstrap compilers and there
were no regressions.

In addition, I constructed a test case that used every archiecture define 
(like
_ARCH_PWR4, etc.) and I also looked at the .machine directive generated.  I 
ran
this test for all supported combinations of -mcpu, big/little endian, and 
32/64
bit support.  Every single instance generated exactly the same code with the
patches installed compared to the compiler before installing the patches.

Can I install this patch on the GCC 15 trunk?

2024-09-26  Michael Meissner  

* config/rs6000/dfp.md (floatdidd2): Change TARGET_POPCNTD to
TARGET_POWER7.
* config/rs6000/rs6000-builtin.cc (rs6000_builtin_is_supported):
Likewise.
* config/rs6000/rs6000-string.cc (expand_block_compare_gpr): 
Likewise.
* config/rs6000/rs6000.cc (rs6000_hard_regno_mode_ok_uncached):
Likewise.
(rs6000_rtx_costs): Likewise.
(rs6000_emit_popcount): Likewise.
* config/rs6000/rs6000.h (TARGET_LDBRX): Likewise.
(TARGET_LFIWZX): Likewise.
(TARGET_FCFIDS): Likewise.
(TARGET_FCFIDU): Likewise.
(TARGET_FCFIDUS): Likewise.
(TARGET_FCTIDUZ): Likewise.
(TARGET_FCTIWUZ): Likewise.
(CTZ_DEFINED_VALUE_AT_ZERO): Likewise.
* config/rs6000/rs6000.md (enabled attribute): Likewise.
(ctz2): Likewise.
(popcntd2): Likewise.
(lrintsi2): Likewise.
(lrintsi): Likewise.
(lrintsi_di): Likewise.
(cmpmemsi): Likewise.
(bpermd_"): Likewise.
(addg6s): Likewise.
(cdtbcd): Likewise.
(cbcdtd): Likewise.
(div_): Likewise.

Diff:
---
 gcc/config/rs6000/dfp.md|  2 +-
 gcc/config/rs6000/rs6000-builtin.cc |  4 ++--
 gcc/config/rs6000/rs6000-string.cc  |  4 ++--
 gcc/config/rs6000/rs6000.cc |  6 +++---
 gcc/config/rs6000/rs6000.h  | 16 
 gcc/config/rs6000/rs6000.md | 24 
 6 files changed, 28 insertions(+), 28 deletions(-)

diff --git a/gcc/config/rs6000/dfp.md b/gcc/config/rs6000/dfp.md
index fa9d7dd45dd3..b8189390d410 100644
--- a/gcc/config/rs6000/dfp.md
+++ b/gcc/config/rs6000/dfp.md
@@ -214,7 +214,7 @@
 (define_insn "floatdidd2"
   [(set (match_operand:DD 0 "gpc_reg_operand" "=d")
(float:DD (match_operand:DI 1 "gpc_reg_operand" "d")))]
-  "TARGET_DFP && TARGET_POPCNTD"
+  "TARGET_DFP && TARGET_POWER7"
   "dcffix %0,%1"
   [(set_attr "type" "dfp")])
 
diff --git a/gcc/config/rs6000/rs6000-builtin.cc 
b/gcc/config/rs6000/rs6000-builtin.cc
index 76421bd1de0b..dae43b672ea7 100644
--- a/gcc/config/rs6000/rs6000-builtin.cc
+++ b/gcc/config/rs6000/rs6000-builtin.cc
@@ -161,9 +161,9 @@ rs6000_builtin_is_supported (enum rs6000_gen_builtins 
fncode)
 case ENB_P6_64:
   return TARGET_POWER6 && TARGET_POWERPC64;
 case ENB_P7:
-  return TARGET_POPCNTD;
+  return TARGET_POWER7;
 case ENB_P7_64:
-  return TARGET_POPCNTD && TARGET_POWERPC64;
+  return TARGET_POWER7 && TARGET_POWERPC64;
 case ENB_P8:
   return TARGET_POWER8;
 case ENB_P8V:
diff --git a/gcc/config/rs6000/rs6000-string.cc 
b/gcc/config/rs6000/rs6000-string.cc
index 55b4133b1a34..3674c4bd9847 100644
--- a/gcc/config/rs6000/rs6000-string.cc
+++ b/gcc/config/rs6000/rs6000-string.cc
@@ -1948,8 +1948,8 @@ expand_block_compare_gpr(unsigned HOST_WIDE_INT bytes, 
unsigned int base_align,
 bool
 expand_block_compare (rtx operands[])
 {
-  /* TARGET_POPCNTD is already guarded at expand cmpmemsi.  */
-  gcc_assert (TARGET_POPCNTD);
+  /* TARGET_POWER7 is already guarded at expand cmpmemsi.  */
+  gcc_assert (TARGET_POWER7);
 
   /* For P8, this case is complicated to handle because the subtract
  with carry instructions do not generate the 64-bit carry and so
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index dd51d75c4957..7d20e757c7c4 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -1999,7 +1999,7 @@ rs6000_hard_regno_mode_ok_uncached (int regno, 
machine_mode mode)
  if(GET_MODE_SIZE (mode) == UNITS_PER_FP_WORD)
return 1;
 
- if (TARGET_POPCNTD && mode == SImode)
+ if (TARGET_POWER7 && mode == SImode)
return 1;
 
  if (TARGET_P9_VECTOR && (mode == QImode || mode == HImode))
@@ -22473,7 +22473,7 @@ rs6000_rtx

[gcc r15-3905] c++: tweak for -Wrange-loop-construct [PR116731]

[Marek Polacek via Gcc-cvs]

https://gcc.gnu.org/g:6ac4e2f4b2ca9980670e7d3815a9140730df1005

commit r15-3905-g6ac4e2f4b2ca9980670e7d3815a9140730df1005
Author: Marek Polacek 
Date:   Tue Sep 17 16:58:37 2024 -0400

c++: tweak for -Wrange-loop-construct [PR116731]

This PR reports that the warning would be better off using a check
for trivially constructible rather than trivially copyable.

LLVM accepted a similar fix:
https://github.com/llvm/llvm-project/issues/47355

PR c++/116731

gcc/cp/ChangeLog:

* parser.cc (warn_for_range_copy): Check if TYPE is trivially
constructible, not copyable.

gcc/testsuite/ChangeLog:

* g++.dg/warn/Wrange-loop-construct3.C: New test.

Reviewed-by: Jason Merrill 

Diff:
---
 gcc/cp/parser.cc   |  8 +--
 gcc/testsuite/g++.dg/warn/Wrange-loop-construct3.C | 57 ++
 2 files changed, 62 insertions(+), 3 deletions(-)

diff --git a/gcc/cp/parser.cc b/gcc/cp/parser.cc
index 6d3be94bf448..f50534f5f395 100644
--- a/gcc/cp/parser.cc
+++ b/gcc/cp/parser.cc
@@ -14394,11 +14394,13 @@ warn_for_range_copy (tree decl, tree expr)
   else if (!CP_TYPE_CONST_P (type))
 return;
 
-  /* Since small trivially copyable types are cheap to copy, we suppress the
- warning for them.  64B is a common size of a cache line.  */
+  /* Since small trivially constructible types are cheap to construct, we
+ suppress the warning for them.  64B is a common size of a cache line.  */
+  tree vec = make_tree_vec (1);
+  TREE_VEC_ELT (vec, 0) = TREE_TYPE (expr);
   if (TREE_CODE (TYPE_SIZE_UNIT (type)) != INTEGER_CST
   || (tree_to_uhwi (TYPE_SIZE_UNIT (type)) <= 64
- && trivially_copyable_p (type)))
+ && is_trivially_xible (INIT_EXPR, type, vec)))
 return;
 
   /* If we can initialize a reference directly, suggest that to avoid the
diff --git a/gcc/testsuite/g++.dg/warn/Wrange-loop-construct3.C 
b/gcc/testsuite/g++.dg/warn/Wrange-loop-construct3.C
new file mode 100644
index ..3d9d0c9088e6
--- /dev/null
+++ b/gcc/testsuite/g++.dg/warn/Wrange-loop-construct3.C
@@ -0,0 +1,57 @@
+// PR c++/116731
+// { dg-do compile { target c++11 } }
+// { dg-options "-Wrange-loop-construct" }
+
+void
+f0 ()
+{
+  struct S {
+char a[64];
+S& operator=(const S&) { return *this; };
+  };
+
+  S arr[8];
+  for (const auto r : arr)
+(void) r;
+}
+
+void
+f1 ()
+{
+  struct S {
+char a[65];
+S& operator=(const S&) { return *this; };
+  };
+
+  S arr[8];
+  for (const auto r : arr) // { dg-warning "creates a copy" }
+(void) r;
+}
+
+void
+f2 ()
+{
+  struct S {
+char a[64];
+S& operator=(const S&) { return *this; };
+~S() { }
+  };
+
+  S arr[8];
+  for (const auto r : arr) // { dg-warning "creates a copy" }
+(void) r;
+}
+
+void
+f3 ()
+{
+  struct S {
+char a[65];
+S& operator=(const S&) { return *this; };
+~S() { }
+  };
+
+  S arr[8];
+  for (const auto r : arr) // { dg-warning "creates a copy" }
+(void) r;
+}

[gcc(refs/users/meissner/heads/work179)] Change TARGET_MODULO to TARGET_POWER9

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:58a18a33b3c25d10c739afe01d4a06531f2d9f06

commit 58a18a33b3c25d10c739afe01d4a06531f2d9f06
Author: Michael Meissner 
Date:   Thu Sep 26 17:46:21 2024 -0400

Change TARGET_MODULO to TARGET_POWER9

As part of the architecture flags patches, this patch changes the use of
TARGET_MODULO to TARGET_POWER9.  The modulo instructions were added in 
power9 (ISA
3.0).  Note, I did not change the uses of TARGET_MODULO where it was 
explicitly
generating different code if the machine had a modulo instruction.

I have built both big endian and little endian bootstrap compilers and there
were no regressions.

In addition, I constructed a test case that used every archiecture define 
(like
_ARCH_PWR4, etc.) and I also looked at the .machine directive generated.  I 
ran
this test for all supported combinations of -mcpu, big/little endian, and 
32/64
bit support.  Every single instance generated exactly the same code with the
patches installed compared to the compiler before installing the patches.

Can I install this patch on the GCC 15 trunk?

2024-09-26  Michael Meissner  

* config/rs6000/rs6000-builtin.cc (rs6000_builtin_is_supported): Use
TARGET_POWER9 instead of TARGET_MODULO.
* config/rs6000/rs6000.h (TARGET_CTZ): Likewise.
(TARGET_EXTSWSLI): Likewise.
(TARGET_MADDLD): Likewise.
* config/rs6000/rs6000.md (enabled attribute): Likewise.

Diff:
---
 gcc/config/rs6000/rs6000-builtin.cc | 4 ++--
 gcc/config/rs6000/rs6000.h  | 6 +++---
 gcc/config/rs6000/rs6000.md | 2 +-
 3 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-builtin.cc 
b/gcc/config/rs6000/rs6000-builtin.cc
index dae43b672ea7..b6093b3cb64c 100644
--- a/gcc/config/rs6000/rs6000-builtin.cc
+++ b/gcc/config/rs6000/rs6000-builtin.cc
@@ -169,9 +169,9 @@ rs6000_builtin_is_supported (enum rs6000_gen_builtins 
fncode)
 case ENB_P8V:
   return TARGET_P8_VECTOR;
 case ENB_P9:
-  return TARGET_MODULO;
+  return TARGET_POWER9;
 case ENB_P9_64:
-  return TARGET_MODULO && TARGET_POWERPC64;
+  return TARGET_POWER9 && TARGET_POWERPC64;
 case ENB_P9V:
   return TARGET_P9_VECTOR;
 case ENB_P10:
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 3a03c32f..89ca1bad80f3 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -461,9 +461,9 @@ extern int rs6000_vector_align[];
 #define TARGET_FCTIWUZ TARGET_POWER7
 /* Only powerpc64 and powerpc476 support fctid.  */
 #define TARGET_FCTID   (TARGET_POWERPC64 || rs6000_cpu == PROCESSOR_PPC476)
-#define TARGET_CTZ TARGET_MODULO
-#define TARGET_EXTSWSLI(TARGET_MODULO && TARGET_POWERPC64)
-#define TARGET_MADDLD  TARGET_MODULO
+#define TARGET_CTZ TARGET_POWER9
+#define TARGET_EXTSWSLI(TARGET_POWER9 && TARGET_POWERPC64)
+#define TARGET_MADDLD  TARGET_POWER9
 
 /* TARGET_DIRECT_MOVE is redundant to TARGET_P8_VECTOR, so alias it to that.  
*/
 #define TARGET_DIRECT_MOVE TARGET_P8_VECTOR
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index bff898a4eff1..fc0d454e9a42 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -403,7 +403,7 @@
  (const_int 1)
 
  (and (eq_attr "isa" "p9")
- (match_test "TARGET_MODULO"))
+ (match_test "TARGET_POWER9"))
  (const_int 1)
 
  (and (eq_attr "isa" "p9v")

[gcc(refs/users/meissner/heads/work179)] Use architecture flags for defining _ARCH_PWR macros.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:34e7c57757dbc50b3e6323b4817473abd46cee2b

commit 34e7c57757dbc50b3e6323b4817473abd46cee2b
Author: Michael Meissner 
Date:   Thu Sep 26 17:36:18 2024 -0400

Use architecture flags for defining _ARCH_PWR macros.

For the newer architectures, this patch changes GCC to define the 
_ARCH_PWR
macros using the new architecture flags instead of relying on isa options 
like
-mpower10.

The -mpower8-internal, -mpower10, and -mpower11 options were removed.  The
-mpower11 option was removed completely, since it was just added in GCC 15. 
 The
other two options were marked as WarnRemoved, and the various ISA bits were
removed.

TARGET_POWER8 and TARGET_POWER10 were re-defined to use the architeture bits
instead of the ISA bits.

There are other internal isa bits that aren't removed with this patch 
because
the built-in function support uses those bits.

I have built both big endian and little endian bootstrap compilers and there
were no regressions.

In addition, I constructed a test case that used every archiecture define 
(like
_ARCH_PWR4, etc.) and I also looked at the .machine directive generated.  I 
ran
this test for all supported combinations of -mcpu, big/little endian, and 
32/64
bit support.  Every single instance generated exactly the same code with the
patches installed compared to the compiler before installing the patches.

Can I install this patch on the GCC 15 trunk?

2024-09-26  Michael Meissner  

gcc/

* config/rs6000/rs6000-c.cc (rs6000_target_modify_macros) Add 
support to
use architecture flags instead of ISA flags for setting most of the
_ARCH_PWR* macros.
(rs6000_cpu_cpp_builtins): Update rs6000_target_modify_macros call.
* config/rs6000/rs6000-cpus.def (ISA_2_7_MASKS_SERVER): Remove
OPTION_MASK_POWER8.
(ISA_3_1_MASKS_SERVER): Remove OPTION_MASK_POWER10.
(POWER11_MASKS_SERVER): Remove OPTION_MASK_POWER11.
(POWERPC_MASKS): Remove OPTION_MASK_POWER8, OPTION_MASK_POWER10, and
OPTION_MASK_POWER11.
* config/rs6000/rs6000-protos.h (rs6000_target_modify_macros): 
Update
declaration.
(rs6000_target_modify_macros_ptr): Likewise.
* config/rs6000/rs6000.cc (rs6000_target_modify_macros_ptr): 
Likewise.
(rs6000_option_override_internal): Use architecture flags instead 
of ISA
flags.
(rs6000_opt_masks): Remove -mpower10 and -mpower11, which are no 
longer
in the ISA flags.
(rs6000_pragma_target_parse): Use architecture flags as well as ISA
flags.
* config/rs6000/rs6000.h (TARGET_POWER4): New macro.
(TARGET_POWER5): Likewise.
(TARGET_POWER5X): Likewise.
(TARGET_POWER6): Likewise.
(TARGET_POWER7): Likewise.
(TARGET_POWER8): Likewise.
(TARGET_POWER9): Likewise.
(TARGET_POWER10): Likewise.
(TARGET_POWER11): Likewise.
* config/rs6000/rs6000.opt (-mpower8-internal): Remove ISA flag 
bits.
(-mpower10): Likewise.
(-mpower11): Likewise.

Diff:
---
 gcc/config/rs6000/rs6000-c.cc | 27 +++
 gcc/config/rs6000/rs6000-cpus.def |  8 +---
 gcc/config/rs6000/rs6000-protos.h |  5 +++--
 gcc/config/rs6000/rs6000.cc   | 19 +++
 gcc/config/rs6000/rs6000.h| 20 
 gcc/config/rs6000/rs6000.opt  | 11 ++-
 6 files changed, 52 insertions(+), 38 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc
index 04882c396bfe..c8f33289fa38 100644
--- a/gcc/config/rs6000/rs6000-c.cc
+++ b/gcc/config/rs6000/rs6000-c.cc
@@ -338,7 +338,8 @@ rs6000_define_or_undefine_macro (bool define_p, const char 
*name)
#pragma GCC target, we need to adjust the macros dynamically.  */
 
 void
-rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags)
+rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags,
+HOST_WIDE_INT arch_flags)
 {
   if (TARGET_DEBUG_BUILTIN || TARGET_DEBUG_TARGET)
 fprintf (stderr,
@@ -411,7 +412,7 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT 
flags)
summary of the flags associated with particular cpu
definitions.  */
 
-  /* rs6000_isa_flags based options.  */
+  /* rs6000_isa_flags and rs6000_arch_flags based options.  */
   rs6000_define_or_undefine_macro (define_p, "_ARCH_PPC");
   if ((flags & OPTION_MASK_PPC_GPOPT) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PPCSQ");
@@ -419,23 +420,25 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT 
flags)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PPCGR");
   if ((flags & OPTION_MASK_POWERPC64) != 0)
 rs6000_define_or_undefin

[gcc(refs/users/meissner/heads/work179)] Do not allow -mvsx to boost processor to power7.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:02aa84a0fc7b5c5827eda85ac841bcba242e521a

commit 02aa84a0fc7b5c5827eda85ac841bcba242e521a
Author: Michael Meissner 
Date:   Thu Sep 26 17:38:33 2024 -0400

Do not allow -mvsx to boost processor to power7.

This patch restructures the code so that -mvsx for example will not silently
convert the processor to power7.  The user must now use -mcpu=power7 or 
higher.
This means if the user does -mvsx and the default processor does not have 
VSX
support, it will be an error.

I have built both big endian and little endian bootstrap compilers and there
were no regressions.

In addition, I constructed a test case that used every archiecture define 
(like
_ARCH_PWR4, etc.) and I also looked at the .machine directive generated.  I 
ran
this test for all supported combinations of -mcpu, big/little endian, and 
32/64
bit support.  Every single instance generated exactly the same code with the
patches installed compared to the compiler before installing the patches.

Can I install this patch on the GCC 15 trunk?

2024-09-26  Michael Meissner  

gcc/

* config/rs6000/rs6000.cc (report_architecture_mismatch): New 
function.
Report an error if the user used an option such as -mvsx when the
default processor would not allow the option.
(rs6000_option_override_internal): Move some ISA checking code into
report_architecture_mismatch.

Diff:
---
 gcc/config/rs6000/rs6000.cc | 129 +++-
 1 file changed, 79 insertions(+), 50 deletions(-)

diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 8388542b7210..a944ffde28a6 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -1173,6 +1173,7 @@ const int INSN_NOT_AVAILABLE = -1;
 static void rs6000_print_isa_options (FILE *, int, const char *,
  HOST_WIDE_INT, HOST_WIDE_INT);
 static HOST_WIDE_INT rs6000_disable_incompatible_switches (void);
+static void report_architecture_mismatch (void);
 
 static enum rs6000_reg_type register_to_reg_type (rtx, bool *);
 static bool rs6000_secondary_reload_move (enum rs6000_reg_type,
@@ -3695,7 +3696,6 @@ rs6000_option_override_internal (bool global_init_p)
   bool ret = true;
 
   HOST_WIDE_INT set_masks;
-  HOST_WIDE_INT ignore_masks;
   int cpu_index = -1;
   int tune_index;
   struct cl_target_option *main_target_opt
@@ -3964,59 +3964,13 @@ rs6000_option_override_internal (bool global_init_p)
 dwarf_offset_size = POINTER_SIZE_UNITS;
 #endif
 
-  /* Handle explicit -mno-{altivec,vsx} and turn off all of
- the options that depend on those flags.  */
-  ignore_masks = rs6000_disable_incompatible_switches ();
-
-  /* For the newer switches (vsx, dfp, etc.) set some of the older options,
- unless the user explicitly used the -mno- to disable the code.  */
-  if (TARGET_P9_VECTOR || TARGET_MODULO || TARGET_P9_MISC)
-rs6000_isa_flags |= (ISA_3_0_MASKS_SERVER & ~ignore_masks);
-  else if (TARGET_P9_MINMAX)
-{
-  if (cpu_index >= 0)
-   {
- if (cpu_index == PROCESSOR_POWER9)
-   {
- /* legacy behavior: allow -mcpu=power9 with certain
-capabilities explicitly disabled.  */
- rs6000_isa_flags |= (ISA_3_0_MASKS_SERVER & ~ignore_masks);
-   }
- else
-   error ("power9 target option is incompatible with %<%s=%> "
-  "for  less than power9", "-mcpu");
-   }
-  else if ((ISA_3_0_MASKS_SERVER & rs6000_isa_flags_explicit)
-  != (ISA_3_0_MASKS_SERVER & rs6000_isa_flags
-  & rs6000_isa_flags_explicit))
-   /* Enforce that none of the ISA_3_0_MASKS_SERVER flags
-  were explicitly cleared.  */
-   error ("%qs incompatible with explicitly disabled options",
-  "-mpower9-minmax");
-  else
-   rs6000_isa_flags |= ISA_3_0_MASKS_SERVER;
-}
-  else if (TARGET_P8_VECTOR || TARGET_POWER8 || TARGET_CRYPTO)
-rs6000_isa_flags |= (ISA_2_7_MASKS_SERVER & ~ignore_masks);
-  else if (TARGET_VSX)
-rs6000_isa_flags |= (ISA_2_6_MASKS_SERVER & ~ignore_masks);
-  else if (TARGET_POPCNTD)
-rs6000_isa_flags |= (ISA_2_6_MASKS_EMBEDDED & ~ignore_masks);
-  else if (TARGET_DFP)
-rs6000_isa_flags |= (ISA_2_5_MASKS_SERVER & ~ignore_masks);
-  else if (TARGET_CMPB)
-rs6000_isa_flags |= (ISA_2_5_MASKS_EMBEDDED & ~ignore_masks);
-  else if (TARGET_FPRND)
-rs6000_isa_flags |= (ISA_2_4_MASKS & ~ignore_masks);
-  else if (TARGET_POPCNTB)
-rs6000_isa_flags |= (ISA_2_2_MASKS & ~ignore_masks);
-  else if (TARGET_ALTIVEC)
-rs6000_isa_flags |= (OPTION_MASK_PPC_GFXOPT & ~ignore_masks);
+  /* Report trying to use things like -mmodulo to imply -mcpu=power9.  */
+  report_architecture_mismatch ();
 
   /* Disable VSX and Altivec silently if the user switched cpus to power7 in a
  target a

[gcc(refs/users/meissner/heads/work179)] Add rs6000 architecture masks.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:1aa6493b1f12fc75ac27b06aeb7052bcc70a8b60

commit 1aa6493b1f12fc75ac27b06aeb7052bcc70a8b60
Author: Michael Meissner 
Date:   Thu Sep 26 17:34:33 2024 -0400

Add rs6000 architecture masks.

This patch begins the journey to move architecture bits that are not user 
ISA
options from rs6000_isa_flags to a new targt variable rs6000_arch_flags.  
The
intention is to remove switches that are currently isa options, but the user
should not be using this particular option. For example, we want users to 
use
-mcpu=power10 and not just -mpower10.

This patch also changes the target_clones support to use an architecture 
mask
instead of isa bits.

This patch also switches the handling of .machine to use architecture masks 
if
they exist (power4 through power11).  All of the other PowerPCs will 
continue to
use the existing code for setting the .machine option.

I have built both big endian and little endian bootstrap compilers and there
were no regressions.

In addition, I constructed a test case that used every archiecture define 
(like
_ARCH_PWR4, etc.) and I also looked at the .machine directive generated.  I 
ran
this test for all supported combinations of -mcpu, big/little endian, and 
32/64
bit support.  Every single instance generated exactly the same code with the
patches installed compared to the compiler before installing the patches.

Can I install this patch on the GCC 15 trunk?

2024-09-26  Michael Meissner  

gcc/

* config/rs6000/rs6000-arch.def: New file.
* config/rs6000/rs6000.cc (struct clone_map): Switch to using
architecture masks instead of ISA masks.
(rs6000_clone_map): Likewise.
(rs6000_print_isa_options): Add an architecture flags argument, 
change
all callers.
(get_arch_flag): New function.
(rs6000_debug_reg_global): Update rs6000_print_isa_options calls.
(rs6000_option_override_internal): Likewise.
(rs6000_machine_from_flags): Switch to using architecture masks 
instead
of ISA masks.
(struct rs6000_arch_mask): New structure.
(rs6000_arch_masks): New table of architecutre masks and names.
(rs6000_function_specific_save): Save architecture flags.
(rs6000_function_specific_restore): Restore architecture flags.
(rs6000_function_specific_print): Update rs6000_print_isa_options 
calls.
(rs6000_print_options_internal): Add architecture flags options.
(rs6000_clone_priority): Switch to using architecture masks instead 
of
ISA masks.
(rs6000_can_inline_p): Don't allow inling if the callee requires a 
newer
architecture than the caller.
* config/rs6000/rs6000.h: Use rs6000-arch.def to create the 
architecture
masks.
* config/rs6000/rs6000.opt (rs6000_arch_flags): New target variable.
(x_rs6000_arch_flags): New save/restore field for rs6000_arch_flags.

Diff:
---
 gcc/config/rs6000/rs6000-arch.def |  48 +
 gcc/config/rs6000/rs6000.cc   | 215 +++---
 gcc/config/rs6000/rs6000.h|  24 +
 gcc/config/rs6000/rs6000.opt  |   8 ++
 4 files changed, 259 insertions(+), 36 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-arch.def 
b/gcc/config/rs6000/rs6000-arch.def
new file mode 100644
index ..e5b6e9581331
--- /dev/null
+++ b/gcc/config/rs6000/rs6000-arch.def
@@ -0,0 +1,48 @@
+/* IBM RS/6000 CPU architecture features by processor type.
+   Copyright (C) 1991-2024 Free Software Foundation, Inc.
+   Contributed by Richard Kenner (ken...@vlsi1.ultra.nyu.edu)
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with GCC; see the file COPYING3.  If not see
+   .  */
+
+/* This file defines architecture features that are based on the -mcpu=
+   option, and not on user options that can be turned on or off.  The intention
+   is for newer processors (power7 and above) to not add new ISA bits for the
+   particular processor, but add these bits.  Otherwise we have to add a bunch
+   of hidden options, just so we have the proper ISA bits.
+
+   For example, in the past we added -mpower8-internal, so that on power8,
+   power9, and power10 would inherit the optio

[gcc(refs/users/meissner/heads/work179)] Change TARGET_FPRND to TARGET_POWER5X

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:251c4aa549cdf2fd85b60ec494b8006f8fc90c3e

commit 251c4aa549cdf2fd85b60ec494b8006f8fc90c3e
Author: Michael Meissner 
Date:   Thu Sep 26 17:41:05 2024 -0400

Change TARGET_FPRND to TARGET_POWER5X

As part of the architecture flags patches, this patch changes the use of
TARGET_FPRND to TARGET_POWER5X.  The FPRND instruction was added in power5+.

I have built both big endian and little endian bootstrap compilers and there
were no regressions.

In addition, I constructed a test case that used every archiecture define 
(like
_ARCH_PWR4, etc.) and I also looked at the .machine directive generated.  I 
ran
this test for all supported combinations of -mcpu, big/little endian, and 
32/64
bit support.  Every single instance generated exactly the same code with the
patches installed compared to the compiler before installing the patches.

Can I install this patch on the GCC 15 trunk?

2024-09-26  Michael Meissner  

* config/rs6000/rs6000.cc (report_architecture_mismatch): Use
TARGET_POWER5X instead of TARGET_FPRND.
* config/rs6000/rs6000.md (fmod3): Use TARGET_POWER5X instead 
of
TARGET_FPRND.
(remainder3): Likewise.
(fctiwuz_): Likewise.
(btrunc2): Likewise.
(ceil2): Likewise.
(floor2): Likewise.
(round): Likewise.

Diff:
---
 gcc/config/rs6000/rs6000.cc |  2 +-
 gcc/config/rs6000/rs6000.md | 14 +++---
 2 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index a944ffde28a6..dd51d75c4957 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -25428,7 +25428,7 @@ report_architecture_mismatch (void)
 rs6000_isa_flags |= (ISA_2_5_MASKS_SERVER & ~ignore_masks);
   else if (TARGET_CMPB)
 rs6000_isa_flags |= (ISA_2_5_MASKS_EMBEDDED & ~ignore_masks);
-  else if (TARGET_FPRND)
+  else if (TARGET_POWER5X)
 rs6000_isa_flags |= (ISA_2_4_MASKS & ~ignore_masks);
   else if (TARGET_POPCNTB)
 rs6000_isa_flags |= (ISA_2_2_MASKS & ~ignore_masks);
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 10d13bf812d2..7f9fe609a031 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -5171,7 +5171,7 @@
(use (match_operand:SFDF 1 "gpc_reg_operand"))
(use (match_operand:SFDF 2 "gpc_reg_operand"))]
   "TARGET_HARD_FLOAT
-   && TARGET_FPRND
+   && TARGET_POWER5X
&& flag_unsafe_math_optimizations"
 {
   rtx div = gen_reg_rtx (mode);
@@ -5189,7 +5189,7 @@
(use (match_operand:SFDF 1 "gpc_reg_operand"))
(use (match_operand:SFDF 2 "gpc_reg_operand"))]
   "TARGET_HARD_FLOAT
-   && TARGET_FPRND
+   && TARGET_POWER5X
&& flag_unsafe_math_optimizations"
 {
   rtx div = gen_reg_rtx (mode);
@@ -6687,7 +6687,7 @@
 (define_insn "*friz"
   [(set (match_operand:DF 0 "gpc_reg_operand" "=d,wa")
(float:DF (fix:DI (match_operand:DF 1 "gpc_reg_operand" "d,wa"]
-  "TARGET_HARD_FLOAT && TARGET_FPRND
+  "TARGET_HARD_FLOAT && TARGET_POWER5X
&& flag_unsafe_math_optimizations && !flag_trapping_math && TARGET_FRIZ"
   "@
friz %0,%1
@@ -6815,7 +6815,7 @@
   [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa")
(unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "d,wa")]
 UNSPEC_FRIZ))]
-  "TARGET_HARD_FLOAT && TARGET_FPRND"
+  "TARGET_HARD_FLOAT && TARGET_POWER5X"
   "@
friz %0,%1
xsrdpiz %x0,%x1"
@@ -6825,7 +6825,7 @@
   [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa")
(unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "d,wa")]
 UNSPEC_FRIP))]
-  "TARGET_HARD_FLOAT && TARGET_FPRND"
+  "TARGET_HARD_FLOAT && TARGET_POWER5X"
   "@
frip %0,%1
xsrdpip %x0,%x1"
@@ -6835,7 +6835,7 @@
   [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa")
(unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "d,wa")]
 UNSPEC_FRIM))]
-  "TARGET_HARD_FLOAT && TARGET_FPRND"
+  "TARGET_HARD_FLOAT && TARGET_POWER5X"
   "@
frim %0,%1
xsrdpim %x0,%x1"
@@ -6846,7 +6846,7 @@
   [(set (match_operand:SFDF 0 "gpc_reg_operand" "=")
(unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "")]
 UNSPEC_FRIN))]
-  "TARGET_HARD_FLOAT && TARGET_FPRND"
+  "TARGET_HARD_FLOAT && TARGET_POWER5X"
   "frin %0,%1"
   [(set_attr "type" "fp")])

[gcc(refs/users/meissner/heads/work179)] Change TARGET_CMPB to TARGET_POWER6

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:489e6e266c8d233627ab21f1c0e3254d634d02a7

commit 489e6e266c8d233627ab21f1c0e3254d634d02a7
Author: Michael Meissner 
Date:   Thu Sep 26 17:42:02 2024 -0400

Change TARGET_CMPB to TARGET_POWER6

As part of the architecture flags patches, this patch changes the use of
TARGET_FPRND to TARGET_POWER6.  The CMPB instruction was added in power6 
(ISA
2.05).

I have built both big endian and little endian bootstrap compilers and there
were no regressions.

In addition, I constructed a test case that used every archiecture define 
(like
_ARCH_PWR4, etc.) and I also looked at the .machine directive generated.  I 
ran
this test for all supported combinations of -mcpu, big/little endian, and 
32/64
bit support.  Every single instance generated exactly the same code with the
patches installed compared to the compiler before installing the patches.

Can I install this patch on the GCC 15 trunk?

2024-09-03  Michael Meissner  

* config/rs6000/rs6000-builtin.cc (rs6000_builtin_is_supported): Use
TARGET_POWER6 instead of TARGET_CMPB.
* config/rs6000/rs6000.h (TARGET_FCFID): Merge tests for popcntb, 
cmpb,
and popcntd into a single test for TARGET_POWER5.
(TARGET_LFIWAX): Use TARGET_POWER6 instead of TARGET_CMPB.
* config/rs6000/rs6000.md (enabled attribute): Likewise.
(parity2_cmp): Likewise.
(cmpb): Likewise.
(copysign3): Likewise.
(copysign3_fcpsgn): Likewise.
(cmpstrnsi): Likewise.
(cmpstrsi): Likewise.

Diff:
---
 gcc/config/rs6000/rs6000-builtin.cc |  4 ++--
 gcc/config/rs6000/rs6000.h  |  6 ++
 gcc/config/rs6000/rs6000.md | 16 
 3 files changed, 12 insertions(+), 14 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-builtin.cc 
b/gcc/config/rs6000/rs6000-builtin.cc
index 98a0545030cd..76421bd1de0b 100644
--- a/gcc/config/rs6000/rs6000-builtin.cc
+++ b/gcc/config/rs6000/rs6000-builtin.cc
@@ -157,9 +157,9 @@ rs6000_builtin_is_supported (enum rs6000_gen_builtins 
fncode)
 case ENB_P5:
   return TARGET_POWER5;
 case ENB_P6:
-  return TARGET_CMPB;
+  return TARGET_POWER6;
 case ENB_P6_64:
-  return TARGET_CMPB && TARGET_POWERPC64;
+  return TARGET_POWER6 && TARGET_POWERPC64;
 case ENB_P7:
   return TARGET_POPCNTD;
 case ENB_P7_64:
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 4500724d895c..d22693eb2bfb 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -448,13 +448,11 @@ extern int rs6000_vector_align[];
Enable 32-bit fcfid's on any of the switches for newer ISA machines.  */
 #define TARGET_FCFID   (TARGET_POWERPC64   \
 || TARGET_PPC_GPOPT/* 970/power4 */\
-|| TARGET_POPCNTB  /* ISA 2.02 */  \
-|| TARGET_CMPB /* ISA 2.05 */  \
-|| TARGET_POPCNTD) /* ISA 2.06 */
+|| TARGET_POWER5)  /* ISA 2.02 and above */ \
 
 #define TARGET_FCTIDZ  TARGET_FCFID
 #define TARGET_STFIWX  TARGET_PPC_GFXOPT
-#define TARGET_LFIWAX  TARGET_CMPB
+#define TARGET_LFIWAX  TARGET_POWER6
 #define TARGET_LFIWZX  TARGET_POPCNTD
 #define TARGET_FCFIDS  TARGET_POPCNTD
 #define TARGET_FCFIDU  TARGET_POPCNTD
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 7f9fe609a031..0c303087e944 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -383,7 +383,7 @@
  (const_int 1)
 
  (and (eq_attr "isa" "p6")
- (match_test "TARGET_CMPB"))
+ (match_test "TARGET_POWER6"))
  (const_int 1)
 
  (and (eq_attr "isa" "p7")
@@ -2544,7 +2544,7 @@
 (define_insn "parity2_cmpb"
   [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
(unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")] 
UNSPEC_PARITY))]
-  "TARGET_CMPB"
+  "TARGET_POWER6"
   "prty %0,%1"
   [(set_attr "type" "popcnt")])
 
@@ -2597,7 +2597,7 @@
   [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
(unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")
 (match_operand:GPR 2 "gpc_reg_operand" "r")] UNSPEC_CMPB))]
-  "TARGET_CMPB"
+  "TARGET_POWER6"
   "cmpb %0,%1,%2"
   [(set_attr "type" "cmp")])
 
@@ -5401,7 +5401,7 @@
&& ((TARGET_PPC_GFXOPT
 && !HONOR_NANS (mode)
 && !HONOR_SIGNED_ZEROS (mode))
-   || TARGET_CMPB
+   || TARGET_POWER6
|| VECTOR_UNIT_VSX_P (mode))"
 {
   /* Middle-end canonicalizes -fabs (x) to copysign (x, -1),
@@ -5422,7 +5422,7 @@
   if (!gpc_reg_operand (operands[2], mode))
 operands[2] = copy_to_mode_reg (mode, operands[2]);
 
-  if (TARGET_CMPB || VECTOR_UNIT_VSX_P (mode))
+  if (TARGET_POWER6 || VECTOR_UNIT_VSX_P (mode))
 {
   emit_insn (gen_copysign3_fcpsg

[gcc(refs/users/meissner/heads/work179)] Change TARGET_POPCNTB to TARGET_POWER5

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:fa4fe45ef63d4907ce2b8042fab8de582fc21044

commit fa4fe45ef63d4907ce2b8042fab8de582fc21044
Author: Michael Meissner 
Date:   Thu Sep 26 17:39:47 2024 -0400

Change TARGET_POPCNTB to TARGET_POWER5

As part of the architecture flags patches, this patch changes the use of
TARGET_POPCNTB to TARGET_POWER5.  The POPCNTB instruction was added in ISA 
2.02
(power5).

I have built both big endian and little endian bootstrap compilers and there
were no regressions.

In addition, I constructed a test case that used every archiecture define 
(like
_ARCH_PWR4, etc.) and I also looked at the .machine directive generated.  I 
ran
this test for all supported combinations of -mcpu, big/little endian, and 
32/64
bit support.  Every single instance generated exactly the same code with the
patches installed compared to the compiler before installing the patches.

Can I install this patch on the GCC 15 trunk?

2024-09-26  Michael Meissner  

* config/rs6000/rs6000-builtin.cc (rs6000_builtin_is_supported): Use
TARGET_POWER5 instead of TARGET_POPCNTB.
* config/rs6000/rs6000.h (TARGET_EXTRA_BUILTINS): Use TARGET_POWER5
instead of TARGET_POPCNTB.  Eliminate TARGET_CMPB and TARGET_POPCNTD
tests since TARGET_POWER5 will always be true for those tests.
(TARGET_FRE): Use TARGET_POWER5 instead of TARGET_POPCNTB.
(TARGET_FRSQRTES): Likewise.
* config/rs6000/rs6000.md (enabled attribute): Likewise.
(popcount): Use TARGET_POWER5 instead of TARGET_POPCNTB.  Drop
test for TARGET_POPCNTD (i.e power7), since TARGET_POPCNTB will 
always
be set if TARGET_POPCNTD is set.
(popcntb2): Use TARGET_POWER5 instead of TARGET_POPCNTB.
(parity2): Likewise.
(parity2_cmpb): Remove TARGET_POPCNTB test, since it will 
always
be true when TARGET_CMPB (i.e. power6) is set.

Diff:
---
 gcc/config/rs6000/rs6000-builtin.cc |  2 +-
 gcc/config/rs6000/rs6000.h  |  8 +++-
 gcc/config/rs6000/rs6000.md | 10 +-
 3 files changed, 9 insertions(+), 11 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-builtin.cc 
b/gcc/config/rs6000/rs6000-builtin.cc
index 9bdbae1ecf94..98a0545030cd 100644
--- a/gcc/config/rs6000/rs6000-builtin.cc
+++ b/gcc/config/rs6000/rs6000-builtin.cc
@@ -155,7 +155,7 @@ rs6000_builtin_is_supported (enum rs6000_gen_builtins 
fncode)
 case ENB_ALWAYS:
   return true;
 case ENB_P5:
-  return TARGET_POPCNTB;
+  return TARGET_POWER5;
 case ENB_P6:
   return TARGET_CMPB;
 case ENB_P6_64:
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 7ad8baca177a..4500724d895c 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -547,9 +547,7 @@ extern int rs6000_vector_align[];
 
 #define TARGET_EXTRA_BUILTINS  (TARGET_POWERPC64\
 || TARGET_PPC_GPOPT /* 970/power4 */\
-|| TARGET_POPCNTB   /* ISA 2.02 */  \
-|| TARGET_CMPB  /* ISA 2.05 */  \
-|| TARGET_POPCNTD   /* ISA 2.06 */  \
+|| TARGET_POWER5/* ISA 2.02 & above */ \
 || TARGET_ALTIVEC   \
 || TARGET_VSX   \
 || TARGET_HARD_FLOAT)
@@ -563,9 +561,9 @@ extern int rs6000_vector_align[];
 #define TARGET_FRES(TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT)
 
 #define TARGET_FRE (TARGET_HARD_FLOAT \
-&& (TARGET_POPCNTB || VECTOR_UNIT_VSX_P (DFmode)))
+&& (TARGET_POWER5 || VECTOR_UNIT_VSX_P (DFmode)))
 
-#define TARGET_FRSQRTES(TARGET_HARD_FLOAT && TARGET_POPCNTB \
+#define TARGET_FRSQRTES(TARGET_HARD_FLOAT && TARGET_POWER5 \
 && TARGET_PPC_GFXOPT)
 
 #define TARGET_FRSQRTE (TARGET_HARD_FLOAT \
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 8eda2f7bb0d7..10d13bf812d2 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -379,7 +379,7 @@
  (const_int 1)
 
  (and (eq_attr "isa" "p5")
- (match_test "TARGET_POPCNTB"))
+ (match_test "TARGET_POWER5"))
  (const_int 1)
 
  (and (eq_attr "isa" "p6")
@@ -2510,7 +2510,7 @@
 (define_expand "popcount2"
   [(set (match_operand:GPR 0 "gpc_reg_operand")
(popcount:GPR (match_operand:GPR 1 "gpc_reg_operand")))]
-  "TARGET_POPCNTB || TARGET_POPCNTD"
+  "TARGET_POWER5"
 {
   rs6000_emit_popcount (operands[0], operands[1]);
   DONE;
@@ -2520,7 +2520,7 @@
   [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
(unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")]
UNS

[gcc(refs/users/meissner/heads/work179)] Update tests to work with architecture flags changes.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:c619658969b18d44c753d971fa36ec994e94d378

commit c619658969b18d44c753d971fa36ec994e94d378
Author: Michael Meissner 
Date:   Thu Sep 26 17:48:50 2024 -0400

Update tests to work with architecture flags changes.

Two tests used -mvsx to raise the processor level to at least power7.  These
tests were rewritten to add cpu=power7 support.

I have built both big endian and little endian bootstrap compilers and there
were no regressions.

In addition, I constructed a test case that used every archiecture define 
(like
_ARCH_PWR4, etc.) and I also looked at the .machine directive generated.  I 
ran
this test for all supported combinations of -mcpu, big/little endian, and 
32/64
bit support.  Every single instance generated exactly the same code with the
patches installed compared to the compiler before installing the patches.

Can I install this patch on the GCC 15 trunk?

2024-09-26  Michael Meissner  

gcc/testsuite/

* gcc.target/powerpc/ppc-target-4.c: Rewrite the test to add 
cpu=power7
when we need to add VSX support.  Add test for adding cpu=power7 
no-vsx
to generate only Altivec instructions.
* gcc.target/powerpc/pr115688.c: Add cpu=power7 when requesting VSX
instructions.

Diff:
---
 gcc/testsuite/gcc.target/powerpc/ppc-target-4.c | 38 +++--
 gcc/testsuite/gcc.target/powerpc/pr115688.c |  3 +-
 2 files changed, 31 insertions(+), 10 deletions(-)

diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-target-4.c 
b/gcc/testsuite/gcc.target/powerpc/ppc-target-4.c
index feef76db4618..5e2ecf34f249 100644
--- a/gcc/testsuite/gcc.target/powerpc/ppc-target-4.c
+++ b/gcc/testsuite/gcc.target/powerpc/ppc-target-4.c
@@ -2,7 +2,7 @@
 /* { dg-skip-if "" { powerpc*-*-darwin* } } */
 /* { dg-require-effective-target powerpc_fprs } */
 /* { dg-options "-O2 -ffast-math -mdejagnu-cpu=power5 -mno-altivec 
-mabi=altivec -fno-unroll-loops" } */
-/* { dg-final { scan-assembler-times "vaddfp" 1 } } */
+/* { dg-final { scan-assembler-times "vaddfp" 2 } } */
 /* { dg-final { scan-assembler-times "xvaddsp" 1 } } */
 /* { dg-final { scan-assembler-times "fadds" 1 } } */
 
@@ -18,10 +18,6 @@
 #error "__VSX__ should not be defined."
 #endif
 
-#pragma GCC target("altivec,vsx")
-#include 
-#pragma GCC reset_options
-
 #pragma GCC push_options
 #pragma GCC target("altivec,no-vsx")
 
@@ -33,6 +29,7 @@
 #error "__VSX__ should not be defined."
 #endif
 
+/* Altivec build, generate vaddfp.  */
 void
 av_add (vector float *a, vector float *b, vector float *c)
 {
@@ -40,10 +37,11 @@ av_add (vector float *a, vector float *b, vector float *c)
   unsigned long n = SIZE / 4;
 
   for (i = 0; i < n; i++)
-a[i] = vec_add (b[i], c[i]);
+a[i] = b[i] + c[i];
 }
 
-#pragma GCC target("vsx")
+/* cpu=power7 must be used to enable VSX.  */
+#pragma GCC target("cpu=power7,vsx")
 
 #ifndef __ALTIVEC__
 #error "__ALTIVEC__ should be defined."
@@ -53,6 +51,7 @@ av_add (vector float *a, vector float *b, vector float *c)
 #error "__VSX__ should be defined."
 #endif
 
+/* VSX build on power7, generate xsaddsp.  */
 void
 vsx_add (vector float *a, vector float *b, vector float *c)
 {
@@ -60,11 +59,31 @@ vsx_add (vector float *a, vector float *b, vector float *c)
   unsigned long n = SIZE / 4;
 
   for (i = 0; i < n; i++)
-a[i] = vec_add (b[i], c[i]);
+a[i] = b[i] + c[i];
+}
+
+#pragma GCC target("cpu=power7,no-vsx")
+
+#ifndef __ALTIVEC__
+#error "__ALTIVEC__ should be defined."
+#endif
+
+#ifdef __VSX__
+#error "__VSX__ should not be defined."
+#endif
+
+/* Altivec build on power7 with no VSX, generate vaddfp.  */
+void
+av2_add (vector float *a, vector float *b, vector float *c)
+{
+  unsigned long i;
+  unsigned long n = SIZE / 4;
+
+  for (i = 0; i < n; i++)
+a[i] = b[i] + c[i];
 }
 
 #pragma GCC pop_options
-#pragma GCC target("no-vsx,no-altivec")
 
 #ifdef __ALTIVEC__
 #error "__ALTIVEC__ should not be defined."
@@ -74,6 +93,7 @@ vsx_add (vector float *a, vector float *b, vector float *c)
 #error "__VSX__ should not be defined."
 #endif
 
+/* Default power5 build, generate scalar fadds.  */
 void
 norm_add (float *a, float *b, float *c)
 {
diff --git a/gcc/testsuite/gcc.target/powerpc/pr115688.c 
b/gcc/testsuite/gcc.target/powerpc/pr115688.c
index 5222e66ef170..00c7c301436a 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr115688.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr115688.c
@@ -7,7 +7,8 @@
 
 /* Verify there is no ICE under 32 bit env.  */
 
-__attribute__((target("vsx")))
+/* cpu=power7 must be used to enable VSX.  */
+__attribute__((target("cpu=power7,vsx")))
 int test (void)
 {
   return 0;

[gcc(refs/users/meissner/heads/work179)] Add -mcpu=future tuning support.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:694e6ba895128ce9ab7a41caccf37ad82123691c

commit 694e6ba895128ce9ab7a41caccf37ad82123691c
Author: Michael Meissner 
Date:   Thu Sep 26 17:53:31 2024 -0400

Add -mcpu=future tuning support.

This patch makes -mtune=future use the same tuning decision as 
-mtune=power11.

2024-09-26  Michael Meissner  

gcc/

* config/rs6000/power10.md (all reservations): Add future as an
alterntive to power10 and power11.

Diff:
---
 gcc/config/rs6000/power10.md | 144 +--
 1 file changed, 72 insertions(+), 72 deletions(-)

diff --git a/gcc/config/rs6000/power10.md b/gcc/config/rs6000/power10.md
index 2310c4603457..e42b057dc45b 100644
--- a/gcc/config/rs6000/power10.md
+++ b/gcc/config/rs6000/power10.md
@@ -1,4 +1,4 @@
-;; Scheduling description for the IBM Power10 and Power11 processors.
+;; Scheduling description for the IBM Power10, Power11, and Future processors.
 ;; Copyright (C) 2020-2024 Free Software Foundation, Inc.
 ;;
 ;; Contributed by Pat Haugen (pthau...@us.ibm.com).
@@ -97,12 +97,12 @@
(eq_attr "update" "no")
(eq_attr "size" "!128")
(eq_attr "prefixed" "no")
-   (eq_attr "cpu" "power10,power11"))
+   (eq_attr "cpu" "power10,power11,future"))
   "DU_any_power10,LU_power10")
 
 (define_insn_reservation "power10-fused-load" 4
   (and (eq_attr "type" "fused_load_cmpi,fused_addis_load,fused_load_load")
-   (eq_attr "cpu" "power10,power11"))
+   (eq_attr "cpu" "power10,power11,future"))
   "DU_even_power10,LU_power10")
 
 (define_insn_reservation "power10-prefixed-load" 4
@@ -110,13 +110,13 @@
(eq_attr "update" "no")
(eq_attr "size" "!128")
(eq_attr "prefixed" "yes")
-   (eq_attr "cpu" "power10,power11"))
+   (eq_attr "cpu" "power10,power11,future"))
   "DU_even_power10,LU_power10")
 
 (define_insn_reservation "power10-load-update" 4
   (and (eq_attr "type" "load")
(eq_attr "update" "yes")
-   (eq_attr "cpu" "power10,power11"))
+   (eq_attr "cpu" "power10,power11,future"))
   "DU_even_power10,LU_power10+SXU_power10")
 
 (define_insn_reservation "power10-fpload-double" 4
@@ -124,7 +124,7 @@
(eq_attr "update" "no")
(eq_attr "size" "64")
(eq_attr "prefixed" "no")
-   (eq_attr "cpu" "power10,power11"))
+   (eq_attr "cpu" "power10,power11,future"))
   "DU_any_power10,LU_power10")
 
 (define_insn_reservation "power10-prefixed-fpload-double" 4
@@ -132,14 +132,14 @@
(eq_attr "update" "no")
(eq_attr "size" "64")
(eq_attr "prefixed" "yes")
-   (eq_attr "cpu" "power10,power11"))
+   (eq_attr "cpu" "power10,power11,future"))
   "DU_even_power10,LU_power10")
 
 (define_insn_reservation "power10-fpload-update-double" 4
   (and (eq_attr "type" "fpload")
(eq_attr "update" "yes")
(eq_attr "size" "64")
-   (eq_attr "cpu" "power10,power11"))
+   (eq_attr "cpu" "power10,power11,future"))
   "DU_even_power10,LU_power10+SXU_power10")
 
 ; SFmode loads are cracked and have additional 3 cycles over DFmode
@@ -148,27 +148,27 @@
   (and (eq_attr "type" "fpload")
(eq_attr "update" "no")
(eq_attr "size" "32")
-   (eq_attr "cpu" "power10,power11"))
+   (eq_attr "cpu" "power10,power11,future"))
   "DU_even_power10,LU_power10")
 
 (define_insn_reservation "power10-fpload-update-single" 7
   (and (eq_attr "type" "fpload")
(eq_attr "update" "yes")
(eq_attr "size" "32")
-   (eq_attr "cpu" "power10,power11"))
+   (eq_attr "cpu" "power10,power11,future"))
   "DU_even_power10,LU_power10+SXU_power10")
 
 (define_insn_reservation "power10-vecload" 4
   (and (eq_attr "type" "vecload")
(eq_attr "size" "!256")
-   (eq_attr "cpu" "power10,power11"))
+   (eq_attr "cpu" "power10,power11,future"))
   "DU_any_power10,LU_power10")
 
 ; lxvp
 (define_insn_reservation "power10-vecload-pair" 4
   (and (eq_attr "type" "vecload")
(eq_attr "size" "256")
-   (eq_attr "cpu" "power10,power11"))
+   (eq_attr "cpu" "power10,power11,future"))
   "DU_even_power10,LU_power10+SXU_power10")
 
 ; Store Unit
@@ -178,12 +178,12 @@
(eq_attr "prefixed" "no")
(eq_attr "size" "!128")
(eq_attr "size" "!256")
-   (eq_attr "cpu" "power10,power11"))
+   (eq_attr "cpu" "power10,power11,future"))
   "DU_any_power10,STU_power10")
 
 (define_insn_reservation "power10-fused-store" 0
   (and (eq_attr "type" "fused_store_store")
-   (eq_attr "cpu" "power10,power11"))
+   (eq_attr "cpu" "power10,power11,future"))
   "DU_even_power10,STU_power10")
 
 (define_insn_reservation "power10-prefixed-store" 0
@@ -191,52 +191,52 @@
(eq_attr "prefixed" "yes")
(eq_attr "size" "!128")
(eq_attr "size" "!256")
-   (eq_attr "cpu" "power10,power11"))
+   (eq_attr "cpu" "power10,power11,future"))
   "DU_even_power10,STU_power10")
 
 ; Update forms have 2 cycle latency for updat

[gcc r15-3901] libstdc++: Add [[nodiscard]] to iostream members

[Jonathan Wakely via Gcc-cvs]

https://gcc.gnu.org/g:240285eb307d289d56977f5300bcf0a1253af854

commit r15-3901-g240285eb307d289d56977f5300bcf0a1253af854
Author: Jonathan Wakely 
Date:   Thu Sep 26 12:14:54 2024 +0100

libstdc++: Add [[nodiscard]] to iostream members

These are all pure functions and MSVC also marks all of these as
nodiscard except for std::basic_ios::tie() const, but that's been
confirmed as an accidental omission.

libstdc++-v3/ChangeLog:

* include/bits/basic_ios.h (basic_ios::operator bool()):
Add [[nodiscard]] attribute.
(basic_ios::operator!(), basic_ios::rdstate())
(basic_ios::good(), basic_ios::eof(), basic_ios::fail())
(basic_ios::bad(), basic_ios::exceptions(), basic_ios::tie())
(basic_ios::rdbuf(), basic_ios::fill()): Likewise.
* include/bits/ios_base.h (ios_base::flags()): Likewise.
(ios_base::precision(), ios_base::width(), ios_base::getloc()):
Likewise.
* include/std/fstream (basic_filebuf::is_open)
(basic_ifstream::rdbuf(), basic_ifstream::is_open)
(basic_ofstream::rdbuf(), basic_ofstream::is_open)
(basic_fstream::rdbuf(), basic_fstream::is_open): Likewise.
* include/std/spanstream (basic_spanbuf::span())
(basic_ispanstream::span(), basic_ispanstream::rdbuf())
(basic_ospanstream::span(), basic_ospanstream::rdbuf())
(basic_spanstream::span(), basic_spanstream::rdbuf()):
Likewise.
* include/std/sstream (basic_stringbuf::str())
(basic_istringstream::rdbuf(), basic_istringstream::str())
(basic_ostringstream::rdbuf(), basic_ostringstream::str())
(basic_stringstream::rdbuf(), basic_stringstream::str()):
Likewise.
* testsuite/27_io/basic_istream/extractors_arithmetic/char/01.cc:
Suppress -Wunused-result warnings.
* testsuite/27_io/basic_istream/extractors_arithmetic/wchar_t/01.cc:
Likewise.

Diff:
---
 libstdc++-v3/include/bits/basic_ios.h | 11 +++
 libstdc++-v3/include/bits/ios_base.h  |  4 
 libstdc++-v3/include/std/fstream  | 10 ++
 libstdc++-v3/include/std/spanstream   |  7 +++
 libstdc++-v3/include/std/sstream  | 15 +++
 .../27_io/basic_istream/extractors_arithmetic/char/01.cc  |  4 ++--
 .../basic_istream/extractors_arithmetic/wchar_t/01.cc |  4 ++--
 7 files changed, 51 insertions(+), 4 deletions(-)

diff --git a/libstdc++-v3/include/bits/basic_ios.h 
b/libstdc++-v3/include/bits/basic_ios.h
index a2d8060edd22..8954ad16d63b 100644
--- a/libstdc++-v3/include/bits/basic_ios.h
+++ b/libstdc++-v3/include/bits/basic_ios.h
@@ -120,6 +120,7 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
*  if (!a_stream) ... and while (a_stream) ...
   */
 #if __cplusplus >= 201103L
+  _GLIBCXX_NODISCARD
   explicit operator bool() const
   { return !this->fail(); }
 #else
@@ -127,6 +128,7 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
   { return this->fail() ? 0 : const_cast(this); }
 #endif
 
+  _GLIBCXX_NODISCARD
   bool
   operator!() const
   { return this->fail(); }
@@ -139,6 +141,7 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
*  See std::ios_base::iostate for the possible bit values.  Most
*  users will call one of the interpreting wrappers, e.g., good().
   */
+  _GLIBCXX_NODISCARD
   iostate
   rdstate() const
   { return _M_streambuf_state; }
@@ -182,6 +185,7 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
*
*  A wrapper around rdstate.
   */
+  _GLIBCXX_NODISCARD
   bool
   good() const
   { return this->rdstate() == 0; }
@@ -192,6 +196,7 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
*
*  Note that other iostate flags may also be set.
   */
+  _GLIBCXX_NODISCARD
   bool
   eof() const
   { return (this->rdstate() & eofbit) != 0; }
@@ -203,6 +208,7 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
*  Checking the badbit in fail() is historical practice.
*  Note that other iostate flags may also be set.
   */
+  _GLIBCXX_NODISCARD
   bool
   fail() const
   { return (this->rdstate() & (badbit | failbit)) != 0; }
@@ -213,6 +219,7 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
*
*  Note that other iostate flags may also be set.
   */
+  _GLIBCXX_NODISCARD
   bool
   bad() const
   { return (this->rdstate() & badbit) != 0; }
@@ -224,6 +231,7 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
*  This changes nothing in the stream.  See the one-argument version
*  of exceptions(iostate) for the meaning of the return value.
   */
+  _GLIBCXX_NODISCARD
   iostate
   exceptions() const
   { return _M_exception; }
@@ -297,6 +305,7 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
 

[gcc r15-3902] libstdc++: Fix comments in tests that mention basic_filebuf

[Jonathan Wakely via Libstdc++-cvs]

https://gcc.gnu.org/g:5ad6ff2b4a0a6b7495d580d36283a7e8fd78e47d

commit r15-3902-g5ad6ff2b4a0a6b7495d580d36283a7e8fd78e47d
Author: Jonathan Wakely 
Date:   Sat Sep 21 00:08:23 2024 +0100

libstdc++: Fix comments in  tests that mention basic_filebuf

libstdc++-v3/ChangeLog:

* testsuite/27_io/basic_istringstream/cons/2020.cc: Fix comment
referring to basic_filebuf.
* testsuite/27_io/basic_istringstream/requirements/base_classes.cc:
Likewise.
* testsuite/27_io/basic_ostringstream/cons/2020.cc: Likewise.
* testsuite/27_io/basic_ostringstream/requirements/base_classes.cc:
Likewise.
* testsuite/27_io/basic_stringbuf/cons/2020.cc: Likewise.
* 
testsuite/27_io/basic_stringbuf/requirements/explicit_instantiation/2.cc:
Likewise.
* 
testsuite/27_io/basic_stringbuf/requirements/explicit_instantiation/4.cc:
Likewise.
* testsuite/27_io/basic_stringstream/cons/2020.cc: Likewise.
* testsuite/27_io/basic_stringstream/requirements/base_classes.cc:
Likewise.

Diff:
---
 .../testsuite/27_io/basic_istringstream/cons/2020.cc |  6 +++---
 .../27_io/basic_istringstream/requirements/base_classes.cc   |  2 +-
 .../testsuite/27_io/basic_ostringstream/cons/2020.cc |  6 +++---
 .../27_io/basic_ostringstream/requirements/base_classes.cc   |  2 +-
 libstdc++-v3/testsuite/27_io/basic_stringbuf/cons/2020.cc|  4 ++--
 .../basic_stringbuf/requirements/explicit_instantiation/2.cc | 12 ++--
 .../basic_stringbuf/requirements/explicit_instantiation/4.cc |  2 +-
 libstdc++-v3/testsuite/27_io/basic_stringstream/cons/2020.cc |  6 +++---
 .../27_io/basic_stringstream/requirements/base_classes.cc|  2 +-
 9 files changed, 17 insertions(+), 25 deletions(-)

diff --git a/libstdc++-v3/testsuite/27_io/basic_istringstream/cons/2020.cc 
b/libstdc++-v3/testsuite/27_io/basic_istringstream/cons/2020.cc
index 7b475abe1e00..dc2c5f0be730 100644
--- a/libstdc++-v3/testsuite/27_io/basic_istringstream/cons/2020.cc
+++ b/libstdc++-v3/testsuite/27_io/basic_istringstream/cons/2020.cc
@@ -1,4 +1,4 @@
-// 1999-01-17 bkoz test functionality of basic_filebuf for char_type == char
+// 1999-01-17 bkoz test functionality of basic_istringstream for char_type == 
char
 
 // Copyright (C) 1997-2024 Free Software Foundation, Inc.
 //
@@ -17,8 +17,8 @@
 // with this library; see the file COPYING3.  If not see
 // .
 
-// 27.8.1.1 - Template class basic_filebuf 
-// NB: This file is for testing basic_filebuf with NO OTHER INCLUDES.
+// 27.8.1.1 - Template class basic_istringstream
+// NB: This file is for testing basic_istringstream with NO OTHER INCLUDES.
 
 #include 
 #include 
diff --git 
a/libstdc++-v3/testsuite/27_io/basic_istringstream/requirements/base_classes.cc 
b/libstdc++-v3/testsuite/27_io/basic_istringstream/requirements/base_classes.cc
index c9ccf66f7a1c..03778a437575 100644
--- 
a/libstdc++-v3/testsuite/27_io/basic_istringstream/requirements/base_classes.cc
+++ 
b/libstdc++-v3/testsuite/27_io/basic_istringstream/requirements/base_classes.cc
@@ -18,7 +18,7 @@
 // with this library; see the file COPYING3.  If not see
 // .
 
-// 27.8.1.1 - Template class basic_filebuf 
+// 27.8.1.1 - Template class basic_istringstream
 
 #include 
 #include 
diff --git a/libstdc++-v3/testsuite/27_io/basic_ostringstream/cons/2020.cc 
b/libstdc++-v3/testsuite/27_io/basic_ostringstream/cons/2020.cc
index 95e89a9d08e4..5a398af30d9b 100644
--- a/libstdc++-v3/testsuite/27_io/basic_ostringstream/cons/2020.cc
+++ b/libstdc++-v3/testsuite/27_io/basic_ostringstream/cons/2020.cc
@@ -1,4 +1,4 @@
-// 1999-01-17 bkoz test functionality of basic_filebuf for char_type == char
+// 1999-01-17 bkoz test functionality of basic_ostringstream for char_type == 
char
 
 // Copyright (C) 1997-2024 Free Software Foundation, Inc.
 //
@@ -17,8 +17,8 @@
 // with this library; see the file COPYING3.  If not see
 // .
 
-// 27.8.1.1 - Template class basic_filebuf 
-// NB: This file is for testing basic_filebuf with NO OTHER INCLUDES.
+// 27.8.1.1 - Template class basic_ostringstream
+// NB: This file is for testing basic_ostringstream with NO OTHER INCLUDES.
 
 #include 
 #include 
diff --git 
a/libstdc++-v3/testsuite/27_io/basic_ostringstream/requirements/base_classes.cc 
b/libstdc++-v3/testsuite/27_io/basic_ostringstream/requirements/base_classes.cc
index 07b587275635..58a78a2d44b3 100644
--- 
a/libstdc++-v3/testsuite/27_io/basic_ostringstream/requirements/base_classes.cc
+++ 
b/libstdc++-v3/testsuite/27_io/basic_ostringstream/requirements/base_classes.cc
@@ -18,7 +18,7 @@
 // with this library; see the file COPYING3.  If not see
 // .
 
-// 27.8.1.1 - Template class basic_filebuf 
+// 27.8.1.1 - Template class basic_ostringstream
 
 #include 
 #include 
diff --git a/libs

[gcc r15-3906] libgcc, libstdc++: Make declarations no longer TU-local [PR115126]

[Nathaniel Shead via Gcc-cvs]

https://gcc.gnu.org/g:6a4d1c374eed177eceb12a50f3b25bd20f8b347a

commit r15-3906-g6a4d1c374eed177eceb12a50f3b25bd20f8b347a
Author: Nathaniel Shead 
Date:   Tue Sep 24 23:53:59 2024 +1000

libgcc, libstdc++: Make declarations no longer TU-local [PR115126]

In C++20, modules streaming check for exposures of TU-local entities.
In general exposing internal linkage functions in a header is liable to
cause ODR violations in C++, and this is now detected in a module
context.

This patch goes through and removes 'static' from many declarations
exposed through libstdc++ to prevent code like the following from
failing:

  export module M;
  extern "C++" {
#include 
  }

Since gthreads is used from C as well, we need to choose whether to use
'inline' or 'static inline' depending on whether we're compiling for C
or C++ (since the semantics of 'inline' are different between the
languages).  Additionally we need to remove static global variables, so
we migrate these to function-local statics to avoid the ODR issues.

There doesn't seem to be a good workaround for weakrefs, so I've left
them as-is and will work around it in the modules streaming code to
consider them as not TU-local.

The same issue occurs in the objective-C specific parts of gthreads, but
I'm not familiar with the surrounding context and we don't currently
test modules with Objective C++ anyway so I've left it as-is.

PR libstdc++/115126

libgcc/ChangeLog:

* gthr-posix.h (__GTHREAD_ALWAYS_INLINE): New macro.
(__GTHREAD_INLINE): New macro.
(__gthread_active): Convert from variable to (hidden) function.
(__gthread_active_p): Mark as __GTHREAD_INLINE instead of
static; make visibility("hidden") when it has a static local
variable.
(__gthread_trigger): Mark as __GTHREAD_INLINE instead of static.
(__gthread_create): Likewise.
(__gthread_join): Likewise.
(__gthread_detach): Likewise.
(__gthread_equal): Likewise.
(__gthread_self): Likewise.
(__gthread_yield): Likewise.
(__gthread_once): Likewise.
(__gthread_key_create): Likewise.
(__gthread_key_delete): Likewise.
(__gthread_getspecific): Likewise.
(__gthread_setspecific): Likewise.
(__gthread_mutex_init_function): Likewise.
(__gthread_mutex_destroy): Likewise.
(__gthread_mutex_lock): Likewise.
(__gthread_mutex_trylock): Likewise.
(__gthread_mutex_timedlock): Likewise.
(__gthread_mutex_unlock): Likewise.
(__gthread_recursive_mutex_init_function): Likewise.
(__gthread_recursive_mutex_lock): Likewise.
(__gthread_recursive_mutex_trylock): Likewise.
(__gthread_recursive_mutex_timedlock): Likewise.
(__gthread_recursive_mutex_unlock): Likewise.
(__gthread_recursive_mutex_destroy): Likewise.
(__gthread_cond_init_function): Likewise.
(__gthread_cond_broadcast): Likewise.
(__gthread_cond_signal): Likewise.
(__gthread_cond_wait): Likewise.
(__gthread_cond_timedwait): Likewise.
(__gthread_cond_wait_recursive): Likewise.
(__gthread_cond_destroy): Likewise.
(__gthread_rwlock_rdlock): Likewise.
(__gthread_rwlock_tryrdlock): Likewise.
(__gthread_rwlock_wrlock): Likewise.
(__gthread_rwlock_trywrlock): Likewise.
(__gthread_rwlock_unlock): Likewise.
* gthr-single.h: (__GTHREAD_ALWAYS_INLINE): New macro.
(__GTHREAD_INLINE): New macro.
(__gthread_active_p): Mark as __GTHREAD_INLINE instead of static.
(__gthread_once): Likewise.
(__gthread_key_create): Likewise.
(__gthread_key_delete): Likewise.
(__gthread_getspecific): Likewise.
(__gthread_setspecific): Likewise.
(__gthread_mutex_destroy): Likewise.
(__gthread_mutex_lock): Likewise.
(__gthread_mutex_trylock): Likewise.
(__gthread_mutex_unlock): Likewise.
(__gthread_recursive_mutex_lock): Likewise.
(__gthread_recursive_mutex_trylock): Likewise.
(__gthread_recursive_mutex_unlock): Likewise.
(__gthread_recursive_mutex_destroy): Likewise.

libstdc++-v3/ChangeLog:

* include/bits/shared_ptr.h (std::__is_shared_ptr): Remove
unnecessary 'static'.
* include/bits/unique_ptr.h (std::__is_unique_ptr): Likewise.
* include/std/future (std::__create_task_state): Likewise.
* include/std/shared_mutex (_GLIBCXX_GTRHW): Likewise.
(__glibcxx_rwlock_init): Likewise.
(__glibcxx_r

[gcc r15-3907] libstdc++: Add missing 'inline' to always_inline function

[Jonathan Wakely via Libstdc++-cvs]

https://gcc.gnu.org/g:48e1b89f14f5eab9eb3f61830f608d92c4ee54b6

commit r15-3907-g48e1b89f14f5eab9eb3f61830f608d92c4ee54b6
Author: Jonathan Wakely 
Date:   Thu Sep 26 23:36:46 2024 +0100

libstdc++: Add missing 'inline' to always_inline function

This fixes a -Wattributes warning for the COW std::string which was
previously suppressed due to being in a system header.

libstdc++-v3/ChangeLog:

* include/bits/cow_string.h (__resize_for_overwrite): Add
inline keyword to function with always_inline attribute.

Diff:
---
 libstdc++-v3/include/bits/cow_string.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/libstdc++-v3/include/bits/cow_string.h 
b/libstdc++-v3/include/bits/cow_string.h
index 2298844f38d3..b78aa74fbfaf 100644
--- a/libstdc++-v3/include/bits/cow_string.h
+++ b/libstdc++-v3/include/bits/cow_string.h
@@ -3765,7 +3765,7 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
   template
   template
 [[__gnu__::__always_inline__]]
-void
+inline void
 basic_string<_CharT, _Traits, _Alloc>::
 __resize_and_overwrite(const size_type __n, _Operation __op)
 { resize_and_overwrite<_Operation&>(__n, __op); }