[gcc r15-3210] tree-optimization/116460 - ICE with DCE in forwprop
https://gcc.gnu.org/g:172637cf0d9b7b2798f83b9c5f9598b449675cb0
commit r15-3210-g172637cf0d9b7b2798f83b9c5f9598b449675cb0
Author: Richard Biener
Date: Mon Aug 26 13:50:00 2024 +0200
tree-optimization/116460 - ICE with DCE in forwprop
The following avoids removing stmts with defs that might still have
uses in the IL before calling simple_dce_from_worklist which might
remove those as that will wreck debug stmt generation. Instead first
perform use-based DCE and then remove stmts which may have uses in
code that CFG cleanup will remove. This requires tracking stmts
in to_remove by their SSA def so we can check whether it was removed
before without running into the issue that PHIs can be ggc_free()d
upon removal. So this adds to_remove_defs in addition to to_remove
which has to stay to track GIMPLE_NOPs we want to elide.
PR tree-optimization/116460
* tree-ssa-forwprop.cc (pass_forwprop::execute): First do
simple_dce_from_worklist and then remove stmts in to_remove.
Track defs to be removed in to_remove_defs.
* g++.dg/torture/pr116460.C: New testcase.
Diff:
---
gcc/testsuite/g++.dg/torture/pr116460.C | 609
gcc/tree-ssa-forwprop.cc| 38 +-
2 files changed, 637 insertions(+), 10 deletions(-)
diff --git a/gcc/testsuite/g++.dg/torture/pr116460.C
b/gcc/testsuite/g++.dg/torture/pr116460.C
new file mode 100644
index ..3c7d6372fba2
--- /dev/null
+++ b/gcc/testsuite/g++.dg/torture/pr116460.C
@@ -0,0 +1,609 @@
+// { dg-do compile }
+// { dg-additional-options "-g" }
+
+namespace std {
+typedef __SIZE_TYPE__ size_t;
+typedef __PTRDIFF_TYPE__ ptrdiff_t;
+void __throw_length_error(const char *) __attribute__((__noreturn__,
__cold__));
+}
+extern "C++" {
+namespace std __attribute__((__visibility__("default"))) {
+ template struct __is_integer {
+enum { __value = 1 };
+ };
+ template struct __is_nonvolatile_trivially_copyable {
+enum { __value = __is_trivially_copyable(_Tp) };
+ };
+ template struct __memcpyable {};
+ template
+ struct __memcpyable<_Tp *, _Tp *> : __is_nonvolatile_trivially_copyable<_Tp>
{
+ };
+ template
+ struct __memcpyable<_Tp *, const _Tp *>
+ : __is_nonvolatile_trivially_copyable<_Tp> {};
+ template struct __is_move_iterator {
+enum { __value = 0 };
+ };
+ template inline _Iterator __miter_base(_Iterator __it) {
+return __it;
+ }
+} // namespace )
+}
+namespace __gnu_cxx __attribute__((__visibility__("default"))) {
+ template
+ struct __is_integer_nonstrict : public std::__is_integer<_Tp> {
+using std::__is_integer<_Tp>::__value;
+enum { __width = __value ? sizeof(_Tp) * 8 : 0 };
+ };
+ template struct __numeric_traits_integer {
+static const bool __is_signed = (_Value)(-1) < 0;
+static const int __digits =
+__is_integer_nonstrict<_Value>::__width - __is_signed;
+static const _Value __max =
+__is_signed ? (_Value)1 << (__digits - 1)) - 1) << 1) + 1)
+: ~(_Value)0;
+ };
+ template
+ struct __numeric_traits : public __numeric_traits_integer<_Value> {};
+} // namespace )
+namespace std __attribute__((__visibility__("default"))) {
+ template struct integral_constant {
+static constexpr _Tp value = __v;
+using type = integral_constant<_Tp, __v>;
+ };
+ template using __bool_constant = integral_constant;
+ using true_type = __bool_constant;
+ using false_type = __bool_constant;
+ template struct enable_if {};
+ template struct enable_if { using type = _Tp; };
+ template
+ using __enable_if_t = typename enable_if<_Cond, _Tp>::type;
+ template struct __conditional {
+template using type = _Tp;
+ };
+ template
+ using __conditional_t =
+ typename __conditional<_Cond>::template type<_If, _Else>;
+ namespace __detail {
+ template auto __and_fn(...) -> false_type;
+ }
+ template
+ struct __and_ : decltype(__detail::__and_fn<_Bn...>(0)) {};
+ template struct __not_ : __bool_constant
{};
+ template using __void_t = void;
+ template
+ struct is_trivial : public __bool_constant<__is_trivial(_Tp)> {};
+ template _Up __declval(int);
+ template auto declval() noexcept->decltype(__declval<_Tp>(0));
+ template
+ using __is_constructible_impl =
+ __bool_constant<__is_constructible(_Tp, _Args...)>;
+ template
+ struct __add_lvalue_reference_helper {
+using type = _Tp &;
+ };
+ template
+ using __add_lval_ref_t = typename __add_lvalue_reference_helper<_Tp>::type;
+ template
+ struct is_copy_constructible
+ : public __is_constructible_impl<_Tp, __add_lval_ref_t> {};
+ template
+ struct __add_rvalue_reference_helper {
+using type = _Tp;
+ };
+ template
+ using __add_rval_ref_t = typename __add_rvalue_reference_helper<_Tp>::type;
+ template
+ struct is_move_constructible
+ : public __is_constructible_impl<_Tp, __add_rval_ref_t<_Tp
[gcc r15-3211] c++, coroutines: The frame pointer is used in the helpers [PR116482].
https://gcc.gnu.org/g:8d6d6c864442a1cc987b3e6bcb1d903ceb975e4a
commit r15-3211-g8d6d6c864442a1cc987b3e6bcb1d903ceb975e4a
Author: Iain Sandoe
Date: Mon Aug 26 14:09:40 2024 +0100
c++, coroutines: The frame pointer is used in the helpers [PR116482].
We have a bogus warning about the coroutine state frame pointers
being apparently unused in the resume and destroy functions. Fixed
by making the parameters DECL_ARTIFICIAL.
PR c++/116482
gcc/cp/ChangeLog:
* coroutines.cc
(coro_build_actor_or_destroy_function): Make the parameter
decls DECL_ARTIFICIAL.
gcc/testsuite/ChangeLog:
* g++.dg/coroutines/pr116482.C: New test.
Signed-off-by: Iain Sandoe
Diff:
---
gcc/cp/coroutines.cc | 1 +
gcc/testsuite/g++.dg/coroutines/pr116482.C | 30 ++
2 files changed, 31 insertions(+)
diff --git a/gcc/cp/coroutines.cc b/gcc/cp/coroutines.cc
index 5bfd7943fb81..31dc39afeee2 100644
--- a/gcc/cp/coroutines.cc
+++ b/gcc/cp/coroutines.cc
@@ -4065,6 +4065,7 @@ coro_build_actor_or_destroy_function (tree orig, tree
fn_type,
tree id = get_identifier ("frame_ptr");
tree fp = build_lang_decl (PARM_DECL, id, coro_frame_ptr);
+ DECL_ARTIFICIAL (fp) = true;
DECL_CONTEXT (fp) = fn;
DECL_ARG_TYPE (fp) = type_passed_as (coro_frame_ptr);
DECL_ARGUMENTS (fn) = fp;
diff --git a/gcc/testsuite/g++.dg/coroutines/pr116482.C
b/gcc/testsuite/g++.dg/coroutines/pr116482.C
new file mode 100644
index ..702d1e235bb7
--- /dev/null
+++ b/gcc/testsuite/g++.dg/coroutines/pr116482.C
@@ -0,0 +1,30 @@
+// Override default options.
+// { dg-options "-std=c++20 -fno-exceptions -Wall -Wextra" }
+
+#include
+
+struct SuspendNever {
+bool await_ready();
+void await_suspend(std::coroutine_handle<>);
+void await_resume();
+};
+
+struct Coroutine;
+
+struct PromiseType {
+Coroutine get_return_object();
+SuspendNever initial_suspend();
+SuspendNever final_suspend();
+#if __cpp_exceptions
+void unhandled_exception() { /*std::terminate();*/ };
+#endif
+void return_void();
+};
+
+struct Coroutine {
+using promise_type = PromiseType;
+};
+
+Coroutine __async_test_input_basic() {
+co_return;
+}
[gcc r15-3212] lra: Don't apply eliminations to allocated registers [PR116321]
https://gcc.gnu.org/g:9db997e5ac4a206b9428eb2447fcdc90e37725f4
commit r15-3212-g9db997e5ac4a206b9428eb2447fcdc90e37725f4
Author: Richard Sandiford
Date: Tue Aug 27 09:48:28 2024 +0100
lra: Don't apply eliminations to allocated registers [PR116321]
The sequence of events in this PR is that:
- the function has many addresses in which only a single hard base
register is acceptable. Let's call the hard register H.
- IRA allocates that register to one of the pseudo base registers.
Let's call the pseudo register P.
- Some of the other addresses that require H occur when P is still live.
- LRA therefore has to spill P.
- When it reallocates P, LRA chooses to use FRAME_POINTER_REGNUM,
which has been eliminated to the stack pointer. (This is ok,
since the frame register is free.)
- Spilling P causes LRA to reprocess the instruction that uses P.
- When reprocessing the address that has P as its base, LRA first
applies the new allocation, to get FRAME_POINTER_REGNUM,
and then applies the elimination, to get the stack pointer.
The last step seems wrong: the elimination should only apply to
pre-existing uses of FRAME_POINTER_REGNUM, not to uses that result
from allocating pseudos. Applying both means that we get the wrong
register number, and therefore the wrong class.
The PR is about an existing testcase that fails with LRA on m86k.
gcc/
PR middle-end/116321
* lra-constraints.cc (get_hard_regno): Only apply eliminations
to existing hard registers.
(get_reg_class): Likewise.
Diff:
---
gcc/lra-constraints.cc | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/gcc/lra-constraints.cc b/gcc/lra-constraints.cc
index 90cbe6c012b7..fdcc07764a2e 100644
--- a/gcc/lra-constraints.cc
+++ b/gcc/lra-constraints.cc
@@ -200,12 +200,13 @@ get_hard_regno (rtx x)
reg = SUBREG_REG (x);
if (! REG_P (reg))
return -1;
- if (! HARD_REGISTER_NUM_P (hard_regno = REGNO (reg)))
-hard_regno = lra_get_regno_hard_regno (hard_regno);
+ int regno = REGNO (reg);
+ if (HARD_REGISTER_NUM_P (regno))
+hard_regno = lra_get_elimination_hard_regno (regno);
+ else
+hard_regno = lra_get_regno_hard_regno (regno);
if (hard_regno < 0)
return -1;
- if (HARD_REGISTER_NUM_P (REGNO (reg)))
-hard_regno = lra_get_elimination_hard_regno (hard_regno);
if (SUBREG_P (x))
hard_regno += subreg_regno_offset (hard_regno, GET_MODE (reg),
SUBREG_BYTE (x), GET_MODE (x));
@@ -221,13 +222,12 @@ get_reg_class (int regno)
{
int hard_regno;
- if (! HARD_REGISTER_NUM_P (hard_regno = regno))
+ if (HARD_REGISTER_NUM_P (regno))
+hard_regno = lra_get_elimination_hard_regno (regno);
+ else
hard_regno = lra_get_regno_hard_regno (regno);
if (hard_regno >= 0)
-{
- hard_regno = lra_get_elimination_hard_regno (hard_regno);
- return REGNO_REG_CLASS (hard_regno);
-}
+return REGNO_REG_CLASS (hard_regno);
if (regno >= new_regno_start)
return lra_get_allocno_class (regno);
return NO_REGS;
[gcc r15-3213] Handle arithmetic on eliminated address indices [PR116413]
https://gcc.gnu.org/g:708ee71808ea61758e73d0e36274b4194b28576a
commit r15-3213-g708ee71808ea61758e73d0e36274b4194b28576a
Author: Richard Sandiford
Date: Tue Aug 27 09:48:28 2024 +0100
Handle arithmetic on eliminated address indices [PR116413]
This patch fixes gcc.c-torture/compile/opout.c for m68k with LRA
enabled. The test has:
...
z (a, b)
{
return (int) &a + (int) &b + (int) x + (int) z;
}
so it adds the address of two incoming arguments. This ends up
being treated as an LEA in which the "index" is the incoming
argument pointer, which the LEA multiplies by 2. The incoming
argument pointer is then eliminated, leading to:
(plus:SI (plus:SI (ashift:SI (plus:SI (reg/f:SI 24 %argptr)
(const_int -4 [0xfffc]))
(const_int 1 [0x1]))
(reg/f:SI 41 [ _6 ]))
(const_int 20 [0x14]))
In the address_info scheme, the innermost plus has to be treated
as the index "term", since that's the thing that's subject to
index_reg_class.
gcc/
PR middle-end/116413
* rtl.h (address_info): Update commentary.
* rtlanal.cc (valid_base_or_index_term_p): New function, split
out from...
(get_base_term, get_index_term): ...here. Handle elimination
PLUSes.
Diff:
---
gcc/rtl.h | 14 --
gcc/rtlanal.cc | 29 +
2 files changed, 33 insertions(+), 10 deletions(-)
diff --git a/gcc/rtl.h b/gcc/rtl.h
index 2370d6081614..1ef6432fd9c1 100644
--- a/gcc/rtl.h
+++ b/gcc/rtl.h
@@ -2225,11 +2225,21 @@ struct address_info {
reloading.
- *BASE is a variable expression representing a base address.
- It contains exactly one REG, SUBREG or MEM, pointed to by BASE_TERM.
+ It contains exactly one "term", pointed to by BASE_TERM.
+ This term can be one of the following:
+
+ (1) a REG, or a SUBREG of a REG
+ (2) an eliminated REG (a PLUS of (1) and a constant)
+ (3) a MEM, or a SUBREG of a MEM
+ (4) a SCRATCH
+
+ This term is the one that base_reg_class constrains.
- *INDEX is a variable expression representing an index value.
It may be a scaled expression, such as a MULT. It has exactly
- one REG, SUBREG or MEM, pointed to by INDEX_TERM.
+ one "term", pointed to by INDEX_TERM. The possible terms are
+ the same as for BASE. This term is the one that index_reg_class
+ constrains.
- *DISP is a constant, possibly mutated. DISP_TERM points to the
unmutated RTX_CONST_OBJ. */
diff --git a/gcc/rtlanal.cc b/gcc/rtlanal.cc
index 71207ee4f417..8afbb32f2206 100644
--- a/gcc/rtlanal.cc
+++ b/gcc/rtlanal.cc
@@ -6494,6 +6494,25 @@ binary_scale_code_p (enum rtx_code code)
|| code == ROTATERT);
}
+/* Return true if X appears to be a valid base or index term. */
+static bool
+valid_base_or_index_term_p (rtx x)
+{
+ if (GET_CODE (x) == SCRATCH)
+return true;
+ /* Handle what appear to be eliminated forms of a register. If we reach
+ here, the elimination occurs outside of the outermost PLUS tree,
+ and so the elimination offset cannot be treated as a displacement
+ of the main address. Instead, we need to treat the whole PLUS as
+ the base or index term. The address can only be made legitimate by
+ reloading the PLUS. */
+ if (GET_CODE (x) == PLUS && CONST_SCALAR_INT_P (XEXP (x, 1)))
+x = XEXP (x, 0);
+ if (GET_CODE (x) == SUBREG)
+x = SUBREG_REG (x);
+ return REG_P (x) || MEM_P (x);
+}
+
/* If *INNER can be interpreted as a base, return a pointer to the inner term
(see address_info). Return null otherwise. */
@@ -6502,10 +6521,7 @@ get_base_term (rtx *inner)
{
if (GET_CODE (*inner) == LO_SUM)
inner = strip_address_mutations (&XEXP (*inner, 0));
- if (REG_P (*inner)
- || MEM_P (*inner)
- || GET_CODE (*inner) == SUBREG
- || GET_CODE (*inner) == SCRATCH)
+ if (valid_base_or_index_term_p (*inner))
return inner;
return 0;
}
@@ -6519,10 +6535,7 @@ get_index_term (rtx *inner)
/* At present, only constant scales are allowed. */
if (binary_scale_code_p (GET_CODE (*inner)) && CONSTANT_P (XEXP (*inner, 1)))
inner = strip_address_mutations (&XEXP (*inner, 0));
- if (REG_P (*inner)
- || MEM_P (*inner)
- || GET_CODE (*inner) == SUBREG
- || GET_CODE (*inner) == SCRATCH)
+ if (valid_base_or_index_term_p (*inner))
return inner;
return 0;
}
[gcc r15-3214] Un-XFAIL 'gcc.dg/signbit-5.c' for GCN
https://gcc.gnu.org/g:2daf6187c7289d012365419e10995042139cf8f5
commit r15-3214-g2daf6187c7289d012365419e10995042139cf8f5
Author: Thomas Schwinge
Date: Tue Aug 27 12:37:29 2024 +0200
Un-XFAIL 'gcc.dg/signbit-5.c' for GCN
It XPASSes after recent commit 5a3387938d4d95717cac29eecd0ba53e0ef9094d
"testsuite: Add -fwrapv to signbit-5.c".
gcc/testsuite/
* gcc.dg/signbit-5.c: Un-XFAIL for GCN.
Diff:
---
gcc/testsuite/gcc.dg/signbit-5.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/gcc/testsuite/gcc.dg/signbit-5.c b/gcc/testsuite/gcc.dg/signbit-5.c
index e65c8910c825..57e29e3ca63e 100644
--- a/gcc/testsuite/gcc.dg/signbit-5.c
+++ b/gcc/testsuite/gcc.dg/signbit-5.c
@@ -3,7 +3,6 @@
/* This test does not work when the truth type does not match vector type. */
/* { dg-additional-options "-march=armv8-a" { target aarch64_sve } } */
-/* { dg-xfail-run-if "truth type does not match vector type" { amdgcn-*-* } }
*/
#include
[gcc r15-3215] testsuite: Fix ending of comment in test cases
https://gcc.gnu.org/g:442e3cd20cb9504e8c65815c8a8ad0cfa3e4efa8
commit r15-3215-g442e3cd20cb9504e8c65815c8a8ad0cfa3e4efa8
Author: Torbjörn SVENSSON
Date: Tue Aug 27 12:53:37 2024 +0200
testsuite: Fix ending of comment in test cases
gcc/testsuite/ChangeLog:
* gcc.dg/pr108757-1.c: Fixed dg-comment.
* gcc.dg/pr71071.c: Likewise.
* gcc.dg/tree-ssa/noreturn-1.c: Likewise.
* gcc.dg/tree-ssa/pr56727.c: Likewise.
* gcc.target/arc/loop-2.cpp: Likewise.
* gcc.target/arc/loop-3.c: Likewise.
* gcc.target/arc/pr9001107555.c: Likewise.
* gcc.target/arm/armv8_1m-fp16-move-1.c: Likewise.
* gcc.target/arm/armv8_1m-fp32-move-1.c: Likewise.
* gcc.target/arm/armv8_1m-fp64-move-1.c: Likewise.
* gcc.target/i386/amxint8-asmatt-1.c: Likewise.
* gcc.target/i386/amxint8-asmintel-1.c: Likewise.
* gcc.target/i386/avx512bw-vpermt2w-1.c: Likewise.
* gcc.target/i386/avx512vbmi-vpermt2b-1.c: Likewise.
* gcc.target/i386/endbr_immediate.c: Likewise.
* gcc.target/i386/pr96539.c: Likewise.
* gcc.target/i386/sse2-pr98461-2.c: Likewise.
* gcc.target/m68k/pr39726.c: Likewise.
* gcc.target/m68k/pr52076-1.c: Likewise.
* gcc.target/m68k/pr52076-2.c: Likewise.
* gcc.target/nvptx/v2si-vec-set-extract.c: Likewise.
Signed-off-by: Torbjörn SVENSSON
Diff:
---
gcc/testsuite/gcc.dg/pr108757-1.c | 2 +-
gcc/testsuite/gcc.dg/pr71071.c| 2 +-
gcc/testsuite/gcc.dg/tree-ssa/noreturn-1.c| 2 +-
gcc/testsuite/gcc.dg/tree-ssa/pr56727.c | 2 +-
gcc/testsuite/gcc.target/arc/loop-2.cpp | 2 +-
gcc/testsuite/gcc.target/arc/loop-3.c | 2 +-
gcc/testsuite/gcc.target/arc/pr9001107555.c | 2 +-
gcc/testsuite/gcc.target/arm/armv8_1m-fp16-move-1.c | 2 +-
gcc/testsuite/gcc.target/arm/armv8_1m-fp32-move-1.c | 2 +-
gcc/testsuite/gcc.target/arm/armv8_1m-fp64-move-1.c | 2 +-
gcc/testsuite/gcc.target/i386/amxint8-asmatt-1.c | 2 +-
gcc/testsuite/gcc.target/i386/amxint8-asmintel-1.c| 2 +-
gcc/testsuite/gcc.target/i386/avx512bw-vpermt2w-1.c | 2 +-
gcc/testsuite/gcc.target/i386/avx512vbmi-vpermt2b-1.c | 2 +-
gcc/testsuite/gcc.target/i386/endbr_immediate.c | 2 +-
gcc/testsuite/gcc.target/i386/pr96539.c | 2 +-
gcc/testsuite/gcc.target/i386/sse2-pr98461-2.c| 2 +-
gcc/testsuite/gcc.target/m68k/pr39726.c | 2 +-
gcc/testsuite/gcc.target/m68k/pr52076-1.c | 2 +-
gcc/testsuite/gcc.target/m68k/pr52076-2.c | 2 +-
gcc/testsuite/gcc.target/nvptx/v2si-vec-set-extract.c | 2 +-
21 files changed, 21 insertions(+), 21 deletions(-)
diff --git a/gcc/testsuite/gcc.dg/pr108757-1.c
b/gcc/testsuite/gcc.dg/pr108757-1.c
index 7908f4bdcb8e..712dc4c30e92 100644
--- a/gcc/testsuite/gcc.dg/pr108757-1.c
+++ b/gcc/testsuite/gcc.dg/pr108757-1.c
@@ -13,6 +13,6 @@ typedef int INT;
#define IMIN INT_MIN
#include "pr108757.h"
-/* { dg-final { scan-tree-dump-not " = x_\[0-9\]+\\(D\\) \\+ " "optimized" } }
*
+/* { dg-final { scan-tree-dump-not " = x_\[0-9\]+\\(D\\) \\+ " "optimized" } }
*/
/* { dg-final { scan-tree-dump-not " = x_\[0-9\]+\\(D\\) \\- " "optimized" } }
*/
/* { dg-final { scan-tree-dump-not " = b_\[0-9\]+ \\+ " "optimized" } } */
diff --git a/gcc/testsuite/gcc.dg/pr71071.c b/gcc/testsuite/gcc.dg/pr71071.c
index 582f1f15a432..3e83dc9f1b7b 100644
--- a/gcc/testsuite/gcc.dg/pr71071.c
+++ b/gcc/testsuite/gcc.dg/pr71071.c
@@ -1,5 +1,5 @@
/* PR bootstrap/71071 */
-/* { dg-do compile } *
+/* { dg-do compile } */
/* { dg-options "-O2" } */
struct S { unsigned b : 1; } a;
diff --git a/gcc/testsuite/gcc.dg/tree-ssa/noreturn-1.c
b/gcc/testsuite/gcc.dg/tree-ssa/noreturn-1.c
index ae7ee42fabcb..35f3d9802175 100644
--- a/gcc/testsuite/gcc.dg/tree-ssa/noreturn-1.c
+++ b/gcc/testsuite/gcc.dg/tree-ssa/noreturn-1.c
@@ -1,4 +1,4 @@
-/* { dg-do compile } *
+/* { dg-do compile } */
/* { dg-options "-O2 -fdump-tree-ssa -std=gnu11" } */
/* { dg-final { scan-tree-dump-times "__builtin_unreachable" 4 "ssa" } } */
diff --git a/gcc/testsuite/gcc.dg/tree-ssa/pr56727.c
b/gcc/testsuite/gcc.dg/tree-ssa/pr56727.c
index 3080ce183b8a..da2c9ab31f21 100644
--- a/gcc/testsuite/gcc.dg/tree-ssa/pr56727.c
+++ b/gcc/testsuite/gcc.dg/tree-ssa/pr56727.c
@@ -1,4 +1,4 @@
-/* { dg-do compile { target fpic } } *
+/* { dg-do compile { target fpic } } */
/* { dg-require-alias "" } */
/* { dg-options "-O2 -fPIC -fdump-tree-optimized" } */
void do_not_optimize(int b)
diff --git a/gcc/testsuite/gcc.target/arc/loop-2.cpp
b/gcc/testsuite/gcc.target/arc/loop-2.cpp
index d1dc917ba479..9cfb3274e213 100644
--- a/gcc/testsuite/gcc.target/arc/loop-2.cpp
+++ b/gcc/testsuite/gcc.target/arc/loop-2.cpp
@@ -1,4 +1,4 @@
-/* { dg-options "-O2" } *
+/* { dg-options
[gcc/devel/nothrow-detection] Fix handling of types
https://gcc.gnu.org/g:c16d4a0ae162abc00d97bb73e598ca00d16cf555
commit c16d4a0ae162abc00d97bb73e598ca00d16cf555
Author: Jan Hubicka
Date: Tue Aug 27 13:50:32 2024 +0200
Fix handling of types
* ipa-devirt.cc (odr_equivalent_or_derived_p): New.
* ipa-utils.h (odr_equivalent_or_derived_p): Declare.
* tree-eh.cc (same_or_derived_type): New.
(match_lp): Use it.
Diff:
---
gcc/ipa-devirt.cc | 24
gcc/ipa-utils.h | 1 +
gcc/tree-eh.cc| 26 +-
3 files changed, 50 insertions(+), 1 deletion(-)
diff --git a/gcc/ipa-devirt.cc b/gcc/ipa-devirt.cc
index a7ce434bffb4..d6cfcf2c676c 100644
--- a/gcc/ipa-devirt.cc
+++ b/gcc/ipa-devirt.cc
@@ -1211,6 +1211,30 @@ skip_in_fields_list_p (tree t)
return false;
}
+/* Return true if T2 is derived form T1. */
+
+bool
+odr_equivalent_or_derived_p (tree t1, tree t2)
+{
+ if (in_lto_p)
+{
+ if (odr_types_equivalent_p (t1, t2))
+ return true;
+}
+ else
+{
+ if (TYPE_MAIN_VARIANT (t1) == TYPE_MAIN_VARIANT (t2))
+ return true;
+}
+ if (!TYPE_BINFO (t2))
+return false;
+ for (unsigned int i = 0; i < BINFO_N_BASE_BINFOS (TYPE_BINFO (t2)); i++)
+if (odr_equivalent_or_derived_p
+(t1, BINFO_TYPE (BINFO_BASE_BINFO (TYPE_BINFO (t2), i
+return true;
+ return false;
+}
+
/* Compare T1 and T2, report ODR violations if WARN is true and set
WARNED to true if anything is reported. Return true if types match.
If true is returned, the types are also compatible in the sense of
diff --git a/gcc/ipa-utils.h b/gcc/ipa-utils.h
index d1da9c31e09e..908b425e98c5 100644
--- a/gcc/ipa-utils.h
+++ b/gcc/ipa-utils.h
@@ -106,6 +106,7 @@ cgraph_node *try_speculative_devirtualization (tree,
HOST_WIDE_INT,
void warn_types_mismatch (tree t1, tree t2, location_t loc1 = UNKNOWN_LOCATION,
location_t loc2 = UNKNOWN_LOCATION);
bool odr_or_derived_type_p (const_tree t);
+bool odr_equivalent_or_derived_p (tree t1, tree t2);
bool odr_types_equivalent_p (tree type1, tree type2);
bool odr_type_violation_reported_p (tree type);
tree prevailing_odr_type (tree type);
diff --git a/gcc/tree-eh.cc b/gcc/tree-eh.cc
index eec1e6af70d7..ab8e00972b06 100644
--- a/gcc/tree-eh.cc
+++ b/gcc/tree-eh.cc
@@ -47,6 +47,8 @@ along with GCC; see the file COPYING3. If not see
#include "attribs.h"
#include "asan.h"
#include "gimplify.h"
+#include "print-tree.h"
+#include "ipa-utils.h"
/* In some instances a tree and a gimple need to be stored in a same table,
i.e. in hash tables. This is a structure to do this. */
@@ -2270,6 +2272,25 @@ make_eh_dispatch_edges (geh_dispatch *stmt)
return true;
}
+bool
+same_or_derived_type (tree t1, tree t2)
+{
+ t1 = TYPE_MAIN_VARIANT (t1);
+ t2 = TYPE_MAIN_VARIANT (t2);
+ if (t1 == t2)
+return true;
+ while ((TREE_CODE (t1) == POINTER_TYPE || TREE_CODE (t1) == REFERENCE_TYPE)
+&& TREE_CODE (t1) == TREE_CODE (t2))
+ {
+t1 = TYPE_MAIN_VARIANT (TREE_TYPE (t1));
+t2 = TYPE_MAIN_VARIANT (TREE_TYPE (t2));
+ }
+ if (t1 == t2)
+return true;
+ if (!AGGREGATE_TYPE_P (t1) || !AGGREGATE_TYPE_P (t2))
+return false;
+ return odr_equivalent_or_derived_p (t1, t2);
+}
// Check if a landing pad can handle any of the given exception types
bool match_lp(eh_landing_pad lp, vec *exception_types) {
@@ -2282,11 +2303,14 @@ bool match_lp(eh_landing_pad lp, vec
*exception_types) {
while (catch_handler) {
tree type_list = catch_handler->type_list;
+ if (!type_list)
+ return true;
+
for (tree t = type_list; t; t = TREE_CHAIN(t)) {
tree type = TREE_VALUE(t);
for (unsigned i = 0; i < exception_types->length(); ++i) {
// match found or a catch-all handler (NULL)
-if (type == (*exception_types)[i] || !type) {
+if (!type || same_or_derived_type ((*exception_types)[i],
type)) {
return true;
}
}
[gcc r15-3216] c++: Add correct copyright dates to output of gen-cxxapi-file.py
https://gcc.gnu.org/g:ff4aa45535bc0103e4417e72386089a5421fe520
commit r15-3216-gff4aa45535bc0103e4417e72386089a5421fe520
Author: Jonathan Wakely
Date: Tue Aug 27 12:17:03 2024 +0100
c++: Add correct copyright dates to output of gen-cxxapi-file.py
This ensures the generated output says something like 2022-2024 rather
than just 2024.
gcc/cp/ChangeLog:
* gen-cxxapi-file.py: Fix copyright dates in generated output.
Diff:
---
gcc/cp/gen-cxxapi-file.py | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/cp/gen-cxxapi-file.py b/gcc/cp/gen-cxxapi-file.py
index 31ed5b16ce45..6d08f46069bb 100644
--- a/gcc/cp/gen-cxxapi-file.py
+++ b/gcc/cp/gen-cxxapi-file.py
@@ -95,7 +95,7 @@ def hints(script, content):
%struct-type
%{{
/* This file is auto-generated by {:s}. */
-/* Copyright (C) {:s} Free Software Foundation, Inc.
+/* Copyright (C) 2022-{:s} Free Software Foundation, Inc.
This file is part of GCC.
[gcc r15-3217] c++: Add most missing C++20 and C++23 names to cxxapi-data.csv
https://gcc.gnu.org/g:470a27859d8a47a99f389f1dc6edb82c08b16e21 commit r15-3217-g470a27859d8a47a99f389f1dc6edb82c08b16e21 Author: Jonathan Wakely Date: Tue Aug 27 12:19:47 2024 +0100 c++: Add most missing C++20 and C++23 names to cxxapi-data.csv This includes uncommenting the atomic_flag non-member functions, which were added by PR libstdc++/103934. Also generate a hint for std::ignore, which was recently tweaked to be more generally useful by P2968R2, which r15-2324 implemented. gcc/cp/ChangeLog: * cxxapi-data.csv: Add C++20 and C++23 names from , , , , , and . Set cxx11 dialect for std::ignore in . Uncomment atomic_flag functions from . * std-name-hint.gperf: Regenerate. * std-name-hint.h: Regenerate. Diff: --- gcc/cp/cxxapi-data.csv | 96 ++- gcc/cp/std-name-hint.gperf | 82 ++ gcc/cp/std-name-hint.h | 2029 3 files changed, 1295 insertions(+), 912 deletions(-) diff --git a/gcc/cp/cxxapi-data.csv b/gcc/cp/cxxapi-data.csv index 1cbf774acd7c..bd397fb2acb8 100644 --- a/gcc/cp/cxxapi-data.csv +++ b/gcc/cp/cxxapi-data.csv @@ -197,16 +197,16 @@ ,atomic_uintmax_t,1,cxx20 ,atomic_signed_lock_free,1,cxx11,__cpp_lib_atomic_lock_free_type_aliases ,atomic_unsigned_lock_free,1,cxx11,__cpp_lib_atomic_lock_free_type_aliases -# libstdc++/103934 ,atomic_flag_test,1,no -# libstdc++/103934 ,atomic_flag_test_explicit,1,no +,atomic_flag_test,1,no +,atomic_flag_test_explicit,1,no ,atomic_flag_test_and_set,1,no ,atomic_flag_test_and_set_explicit,1,no ,atomic_flag_clear,1,no ,atomic_flag_clear_explicit,1,no -# libstdc++/103934 ,atomic_flag_wait,1,no -# libstdc++/103934 ,atomic_flag_wait_explicit,1,no -# libstdc++/103934 ,atomic_flag_notify_one,1,no -# libstdc++/103934 ,atomic_flag_notify_all,1,no +,atomic_flag_wait,1,no +,atomic_flag_wait_explicit,1,no +,atomic_flag_notify_one,1,no +,atomic_flag_notify_all,1,no ,atomic_thread_fence,1,no ,atomic_signal_fence,1,no ,barrier,1,no @@ -238,7 +238,48 @@ ,to_chars,1,no ,from_chars_result,1,no ,from_chars,1,no -# TODO +,chrono::duration,1,cxx11 +,chrono::nanoseconds,1,cxx11 +,chrono::microseconds,1,cxx11 +,chrono::milliseconds,1,cxx11 +,chrono::seconds,1,cxx11 +,chrono::minutes,1,cxx11 +,chrono::hours,1,cxx11 +,chrono::days,1,cxx20 +,chrono::weeks,1,cxx20 +,chrono::months,1,cxx20 +,chrono::years,1,cxx20 +,chrono::duration_cast,1,cxx11 +,chrono::time_point,1,cxx11 +,chrono::time_point_cast,1,cxx11 +,chrono::system_clock,1,cxx11 +,chrono::steady_clock,1,cxx11 +,chrono::high_resolution_clock,1,cxx11 +,chrono::utc_clock,1,cxx20 +,chrono::tai_clock,1,cxx20 +,chrono::gps_clock,1,cxx20 +,chrono::file_clock,1,cxx20 +,chrono::local_t,1,cxx20 +,chrono::clock_cast,1,cxx20 +,chrono::time_zone,1,cxx20 +,chrono::zoned_time,1,cxx20 +,chrono::tzdb,1,cxx20 +,chrono::tzdb_list,1,cxx20 +,chrono::get_tzdb,1,cxx20 +,chrono::get_tzdb_list,1,cxx20 +,chrono::reload_tzdb,1,cxx20 +,chrono::remote_version,1,cxx20 +,chrono::locate_zone,1,cxx20 +,chrono::leap_second,1,cxx20 +,chrono::leap_second_info,1,cxx20 +,chrono::get_leap_second_info,1,cxx20 +# c++/106851 ,chrono::abs,1,cxx17 +# c++/106851 ,chrono::floor,1,cxx17 +# c++/106851 ,chrono::ceil,1,cxx17 +,chrono::round,1,cxx17 +,chrono::from_stream,1,cxx20 +,chrono::parse,1,cxx20 +# TODO the rest # TODO ,weak_equality,1,cxx20 ,strong_equality,1,cxx20 @@ -311,6 +352,33 @@ # ,sorted_equivalent,1,no # ,erase_if,1,no # ,uses_allocator,1,no +,format,1,cxx20 +,format_to,1,cxx20 +,format_to_n,1,cxx20 +,formatted_size,1,cxx20 +,vformat,1,cxx20 +,vformat_to,1,cxx20 +,formatter,1,cxx20 +,range_formatter,1,cxx23 +,range_format,1,cxx23 +,formattable,1,cxx23 +,format_error,1,cxx20 +,basic_format_parse_context,1,cxx20 +,format_parse_context,1,cxx20 +,wformat_parse_context,1,cxx20 +,basic_format_context,1,cxx20 +,format_context,1,cxx20 +,wformat_context,1,cxx20 +,basic_format_string,1,cxx20 +,format_string,1,cxx20 +,wformat_string,1,cxx20 +,basic_format_arg,1,cxx20 +,basic_format_args,1,cxx20 +,format_args,1,cxx20 +,wformat_args,1,cxx20 +,make_format_args,1,cxx20 +,make_wformat_args,1,cxx20 +,runtime_format,1,cxx26 ,forward_list,1,cxx11 ,operator==,1,no ,operator<=>,1,no @@ -361,6 +429,8 @@ ,shared_future,1,no ,packaged_task,1,cxx11 ,async,1,cxx11 +,generator,1,cxx23 +# c++/106851 ,pmr::generator,1,no ,initializer_list,1,no ,begin,1,no ,end,1,no @@ -433,6 +503,9 @@ ,ostreambuf_iterator,1,cxx98 ,prev,1,cxx11 ,reverse_iterator,1,cxx98 +,common_iterator,1,cxx20 +,counted_iterator,1,cxx20 +,const_iterator,1,cxx23 # TODO the rest ,latch,1,no ,list,1,cxx98 @@ -590,6 +663,8 @@ ,flush_emit,1,cxx20 ,operator<<,1,no # TODO +,print,1,cxx23 +,println,1,cxx23 ,queue,1,cxx98 ,operator==,1,no ,operator!=,1,no @@ -720,6 +795,11 @@ ,range_error,1,cxx98 ,overflow_error,1,cxx98 ,underflow_error,1,cxx98 +,float16_t,1,cxx23 +,float32_t,1,cxx23 +,float64_t,1,cxx23 +,float128_
[gcc r15-3218] libstdc++: Do not use std::vector::reference default ctor [PR115098]
https://gcc.gnu.org/g:75ef21665cb924265b818b08babbc7ec3108c876
commit r15-3218-g75ef21665cb924265b818b08babbc7ec3108c876
Author: Jonathan Wakely
Date: Tue Aug 27 13:30:42 2024 +0100
libstdc++: Do not use std::vector::reference default ctor [PR115098]
This default constructor was made private by r15-3124-gb25b101bc38000 so
the pretty printer tests need a fix to stop using it. There's no
conforming way to get a default-constructed 'reference' now, e.g. trying
to access an element of a default-constructed std::vector will
trigger an assertion. Remove the tests, but leave a comment in the
printer code about handling it.
libstdc++-v3/ChangeLog:
PR libstdc++/115098
* python/libstdcxx/v6/printers.py (StdBitReferencePrinter): Add
comment.
* testsuite/libstdc++-prettyprinters/simple.cc: Do not default
construct std::vector::reference.
* testsuite/libstdc++-prettyprinters/simple11.cc: Likewise.
Diff:
---
libstdc++-v3/python/libstdcxx/v6/printers.py| 3 +++
libstdc++-v3/testsuite/libstdc++-prettyprinters/simple.cc | 3 ---
libstdc++-v3/testsuite/libstdc++-prettyprinters/simple11.cc | 3 ---
3 files changed, 3 insertions(+), 6 deletions(-)
diff --git a/libstdc++-v3/python/libstdcxx/v6/printers.py
b/libstdc++-v3/python/libstdcxx/v6/printers.py
index a6c2ed4599fa..921049378627 100644
--- a/libstdc++-v3/python/libstdcxx/v6/printers.py
+++ b/libstdc++-v3/python/libstdcxx/v6/printers.py
@@ -613,6 +613,9 @@ class StdBitReferencePrinter(printer_base):
def to_string(self):
if not self._val['_M_p']:
+# PR libstdc++/115098 removed the reference default constructor
+# that this case relates to. New code should never need this,
+# but we still handle it for compatibility with old binaries.
return 'invalid std::vector::reference'
return bool(self._val['_M_p'].dereference() & (self._val['_M_mask']))
diff --git a/libstdc++-v3/testsuite/libstdc++-prettyprinters/simple.cc
b/libstdc++-v3/testsuite/libstdc++-prettyprinters/simple.cc
index 7bdc6548f727..c6d18d3fe03c 100644
--- a/libstdc++-v3/testsuite/libstdc++-prettyprinters/simple.cc
+++ b/libstdc++-v3/testsuite/libstdc++-prettyprinters/simple.cc
@@ -153,9 +153,6 @@ main()
std::vector::reference br5 = *vbIt5;
// { dg-final { note-test br5 {true} } }
- std::vector::reference br0;
-// { dg-final { note-test br0 {invalid std::vector::reference} } }
-
__gnu_cxx::slist sll;
sll.push_front(23);
sll.push_front(47);
diff --git a/libstdc++-v3/testsuite/libstdc++-prettyprinters/simple11.cc
b/libstdc++-v3/testsuite/libstdc++-prettyprinters/simple11.cc
index 3658e3ef4eb4..7fd0c4d76b2a 100644
--- a/libstdc++-v3/testsuite/libstdc++-prettyprinters/simple11.cc
+++ b/libstdc++-v3/testsuite/libstdc++-prettyprinters/simple11.cc
@@ -146,9 +146,6 @@ main()
std::vector::reference br5 = *vbIt5;
// { dg-final { note-test br5 {true} } }
- std::vector::reference br0;
-// { dg-final { note-test br0 {invalid std::vector::reference} } }
-
__gnu_cxx::slist sll;
sll.push_front(23);
sll.push_front(47);
[gcc r15-3219] final: go down ASHIFT in walk_alter_subreg
https://gcc.gnu.org/g:359209bdc7245f8768b5044acded8509545e4990 commit r15-3219-g359209bdc7245f8768b5044acded8509545e4990 Author: Michael Matz Date: Thu Aug 22 17:03:56 2024 +0200 final: go down ASHIFT in walk_alter_subreg when experimenting with m68k plus LRA one of the changes in the backend is to accept ASHIFTs (not only MULT) as scale code for address indices. When then not turning on LRA but using reload those addresses are presented to it which chokes on them. While reload is going away the change to make them work doesn't really hurt (and generally seems useful, as MULT and ASHIFT really are no different). So just add it. PR target/116413 * final.cc (walk_alter_subreg): Recurse on AHIFT. Diff: --- gcc/final.cc | 1 + 1 file changed, 1 insertion(+) diff --git a/gcc/final.cc b/gcc/final.cc index eb9e065d9f0a..5d911586de5b 100644 --- a/gcc/final.cc +++ b/gcc/final.cc @@ -3146,6 +3146,7 @@ walk_alter_subreg (rtx *xp, bool *changed) case PLUS: case MULT: case AND: +case ASHIFT: XEXP (x, 0) = walk_alter_subreg (&XEXP (x, 0), changed); XEXP (x, 1) = walk_alter_subreg (&XEXP (x, 1), changed); break;
[gcc r15-3221] LRA: Fix setup_sp_offset
https://gcc.gnu.org/g:e223ac9c225352e3aeea7180a3b56a96ecdbe2fd
commit r15-3221-ge223ac9c225352e3aeea7180a3b56a96ecdbe2fd
Author: Michael Matz
Date: Thu Aug 22 17:21:42 2024 +0200
LRA: Fix setup_sp_offset
This is part of making m68k work with LRA. See PR116429.
In short: setup_sp_offset is internally inconsistent. It wants to
setup the sp_offset for newly generated instructions. sp_offset for
an instruction is always the state of the sp-offset right before that
instruction. For that it starts at the (assumed correct) sp_offset
of the instruction right after the given (new) sequence, and then
iterates that sequence forward simulating its effects on sp_offset.
That can't ever be right: either it needs to start at the front
and simulate forward, or start at the end and simulate backward.
The former seems to be the more natural way. Funnily the local
variable holding that instruction is also called 'before'.
This changes it to the first variant: start before the sequence,
do one simulation step to get the sp-offset state in front of the
sequence and then continue simulating.
More details: in the problematic testcase we start with this
situation (sp_off before 550 is 0):
550: [--sp] = 0 sp_off = 0 {pushexthisi_const}
551: [--sp] = 37sp_off = -4 {pushexthisi_const}
552: [--sp] = r37 sp_off = -8 {movsi_m68k2}
554: [--sp] = r116 - r37sp_off = -12 {subsi3}
556: call sp_off = -16
insn 554 doesn't match its constraints and needs some reloads:
Creating newreg=262, assigning class DATA_REGS to r262
554: r262:SI=r262:SI-r37:SI
REG_ARGS_SIZE 0x10
Inserting insn reload before:
996: r262:SI=r116:SI
Inserting insn reload after:
997: [--%sp:SI]=r262:SI
Considering alt=0 of insn 997: (0) =g (1) damSKT
1 Non pseudo reload: reject++
overall=1,losers=0,rld_nregs=0
Choosing alt 0 in insn 997: (0) =g (1) damSKT {*movsi_m68k2}
(sp_off=-16)
Note how insn 997 (the after-reload) now has sp_off=-16 already. It all
goes downhill from there. We end up with these insns:
552: [--sp] = r37 sp_off = -8 {movsi_m68k2}
996: r262 = r116sp_off = -12
554: r262 = r262 - r37 sp_off = -12
997: [--sp] = r262 sp_off = -16 (!!! should be -12)
556: call sp_off = -16
The call insn sp_off remains at the correct -16, but internally it's already
inconsistent here. If the sp_off before an insn is -16, and that insn
pre_decs sp, then the after-insn sp_off should be -20.
PR target/116429
* lra.cc (setup_sp_offset): Start with sp_offset from
before the new sequence, not from after.
Diff:
---
gcc/lra.cc | 13 -
1 file changed, 8 insertions(+), 5 deletions(-)
diff --git a/gcc/lra.cc b/gcc/lra.cc
index fb32e134004a..b84384b21454 100644
--- a/gcc/lra.cc
+++ b/gcc/lra.cc
@@ -1863,14 +1863,17 @@ push_insns (rtx_insn *from, rtx_insn *to)
}
/* Set up and return sp offset for insns in range [FROM, LAST]. The offset is
- taken from the next BB insn after LAST or zero if there in such
- insn. */
+ taken from the BB insn before FROM after simulating its effects,
+ or zero if there is no such insn. */
static poly_int64
setup_sp_offset (rtx_insn *from, rtx_insn *last)
{
- rtx_insn *before = next_nonnote_nondebug_insn_bb (last);
- poly_int64 offset = (before == NULL_RTX || ! INSN_P (before)
- ? 0 : lra_get_insn_recog_data (before)->sp_offset);
+ rtx_insn *before = prev_nonnote_nondebug_insn_bb (from);
+ poly_int64 offset = 0;
+
+ if (before && INSN_P (before))
+offset = lra_update_sp_offset (PATTERN (before),
+ lra_get_insn_recog_data (before)->sp_offset);
for (rtx_insn *insn = from; insn != NEXT_INSN (last); insn = NEXT_INSN
(insn))
{
[gcc r15-3220] LRA: Don't use 0 as initialization for sp_offset
https://gcc.gnu.org/g:542773888190ef67dca194f4861abab104fa9b5b
commit r15-3220-g542773888190ef67dca194f4861abab104fa9b5b
Author: Michael Matz
Date: Thu Aug 22 17:09:11 2024 +0200
LRA: Don't use 0 as initialization for sp_offset
this is part of making m68k work with LRA. See PR116374.
m68k has the property that sometimes the elimation offset
between %sp and %argptr is zero. During setting up elimination
infrastructure it's changes between sp_offset and previous_offset
that feed into insns_with_changed_offsets that ultimately will
setup looking at the instructions so marked.
But the initial values for sp_offset and previous_offset are
also zero. So if the targets INITIAL_ELIMINATION_OFFSET (called
in update_reg_eliminate) is zero then nothing changes, the
instructions in question don't get into the list to consider and
the sp_offset tracking goes wrong.
Solve this by initializing those member with -1 instead of zero.
An initial offset of that value seems very unlikely, as it's
in word-sized increments. This then also reveals a problem in
eliminate_regs_in_insn where it always uses sp_offset-previous_offset
as offset adjustment, even in the first_p pass. That was harmless
when previous_offset was uninitialized as zero. But all the other
code uses a different idiom of checking for first_p (or rather
update_p which is !replace_p&&!first_p), and using sp_offset directly.
So use that as well in eliminate_regs_in_insn.
PR target/116374
* lra-eliminations.cc (init_elim_table): Use -1 as initializer.
(update_reg_eliminate): Accept -1 as not-yet-used marker.
(eliminate_regs_in_insn): Use previous_sp_offset only when
not first_p.
Diff:
---
gcc/lra-eliminations.cc | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/gcc/lra-eliminations.cc b/gcc/lra-eliminations.cc
index 5bed259cffeb..96772f2904a6 100644
--- a/gcc/lra-eliminations.cc
+++ b/gcc/lra-eliminations.cc
@@ -969,7 +969,8 @@ eliminate_regs_in_insn (rtx_insn *insn, bool replace_p,
bool first_p,
if (! replace_p)
{
if (known_eq (update_sp_offset, 0))
- offset += (ep->offset - ep->previous_offset);
+ offset += (!first_p
+ ? ep->offset - ep->previous_offset : ep->offset);
if (ep->to_rtx == stack_pointer_rtx)
{
if (first_p)
@@ -1212,7 +1213,7 @@ update_reg_eliminate (bitmap insns_with_changed_offsets)
if (lra_dump_file != NULL)
fprintf (lra_dump_file, "Using elimination %d to %d now\n",
ep1->from, ep1->to);
- lra_assert (known_eq (ep1->previous_offset, 0));
+ lra_assert (known_eq (ep1->previous_offset, -1));
ep1->previous_offset = ep->offset;
}
else
@@ -1283,7 +1284,7 @@ init_elim_table (void)
for (ep = reg_eliminate, ep1 = reg_eliminate_1;
ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
{
- ep->offset = ep->previous_offset = 0;
+ ep->offset = ep->previous_offset = -1;
ep->from = ep1->from;
ep->to = ep1->to;
value_p = (targetm.can_eliminate (ep->from, ep->to)
[gcc r15-3222] Extend check-function-bodies to allow label and directives
https://gcc.gnu.org/g:d6bb1e257fc414d21bc31faa7ddecbc93a197e3c
commit r15-3222-gd6bb1e257fc414d21bc31faa7ddecbc93a197e3c
Author: H.J. Lu
Date: Tue Aug 27 07:03:22 2024 -0700
Extend check-function-bodies to allow label and directives
As PR target/116174 shown, we may need to verify labels and the directive
order. Extend check-function-bodies to support matched output lines to
allow label and directives.
gcc/
* doc/sourcebuild.texi (check-function-bodies): Add an optional
argument for matched output lines.
gcc/testsuite/
* gcc.target/i386/pr116174.c: Use check-function-bodies.
* lib/scanasm.exp (parse_function_bodies): Append the line if
$up_config(matched) matches the line.
(check-function-bodies): Add an argument for matched. Set
up_config(matched) to $matched. Append the expected line without
$config(line_prefix) to function_regexp if it starts with ".L".
Signed-off-by: H.J. Lu
Diff:
---
gcc/doc/sourcebuild.texi | 9 ++---
gcc/testsuite/gcc.target/i386/pr116174.c | 18 +++---
gcc/testsuite/lib/scanasm.exp| 15 +--
3 files changed, 34 insertions(+), 8 deletions(-)
diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi
index 1a31f00fb651..3c55f1037953 100644
--- a/gcc/doc/sourcebuild.texi
+++ b/gcc/doc/sourcebuild.texi
@@ -3530,7 +3530,7 @@ assembly output.
Passes if @var{symbol} is not defined as a hidden symbol in the test's
assembly output.
-@item check-function-bodies @var{prefix} @var{terminator} [@var{options} [@{
target/xfail @var{selector} @}]]
+@item check-function-bodies @var{prefix} @var{terminator} [@var{options} [@{
target/xfail @var{selector} @} [@var{matched}]]]
Looks through the source file for comments that give the expected assembly
output for selected functions. Each line of expected output starts with the
prefix string @var{prefix} and the expected output for a function as a whole
@@ -3557,8 +3557,11 @@ Depending on the configuration (see
@code{configure_check-function-bodies} in
@file{gcc/testsuite/lib/scanasm.exp}), the test may discard from the
compiler's assembly output directives such as @code{.cfi_startproc},
-local label definitions such as @code{.LFB0}, and more.
-It then matches the result against the expected
+local label definitions such as @code{.LFB0}, and more. This behavior
+can be overridden using the optional @var{matched} argument, which
+specifies a regexp for lines that should not be discarded in this way.
+
+The test then matches the result against the expected
output for a function as a single regular expression. This means that
later lines can use backslashes to refer back to @samp{(@dots{})}
captures on earlier lines. For example:
diff --git a/gcc/testsuite/gcc.target/i386/pr116174.c
b/gcc/testsuite/gcc.target/i386/pr116174.c
index 8877d0b51af1..686aeb9ff314 100644
--- a/gcc/testsuite/gcc.target/i386/pr116174.c
+++ b/gcc/testsuite/gcc.target/i386/pr116174.c
@@ -1,6 +1,20 @@
/* { dg-do compile { target *-*-linux* } } */
-/* { dg-options "-O2 -fcf-protection=branch" } */
+/* { dg-options "-O2 -g0 -fcf-protection=branch" } */
+/* Keep labels and directives ('.p2align', '.cfi_startproc').
+/* { dg-final { check-function-bodies "**" "" "" { target "*-*-*" } {^\t?\.}
} } */
+/*
+**foo:
+**.LFB0:
+** .cfi_startproc
+** (
+** endbr64
+** .p2align 5
+** |
+** endbr32
+** )
+**...
+*/
char *
foo (char *dest, const char *src)
{
@@ -8,5 +22,3 @@ foo (char *dest, const char *src)
/* nothing */;
return --dest;
}
-
-/* { dg-final { scan-assembler "\t\.cfi_startproc\n\tendbr(32|64)\n" } } */
diff --git a/gcc/testsuite/lib/scanasm.exp b/gcc/testsuite/lib/scanasm.exp
index 42c719c512c7..737eefc655e9 100644
--- a/gcc/testsuite/lib/scanasm.exp
+++ b/gcc/testsuite/lib/scanasm.exp
@@ -952,6 +952,9 @@ proc parse_function_bodies { config filename result } {
verbose "parse_function_bodies: $function_name:\n$function_body"
set up_result($function_name) $function_body
set in_function 0
+ } elseif { $up_config(matched) ne "" \
+ && [regexp $up_config(matched) $line] } {
+ append function_body $line "\n"
} elseif { [regexp $up_config(fluff) $line] } {
verbose "parse_function_bodies: $function_name: ignoring fluff
line: $line"
} else {
@@ -982,7 +985,7 @@ proc check_function_body { functions name body_regexp } {
# Check the implementations of functions against expected output. Used as:
#
-# { dg-do { check-function-bodies PREFIX TERMINATOR[ OPTION[ SELECTOR]] } }
+# { dg-do { check-function-bodies PREFIX TERMINATOR[ OPTION[ SELECTOR
[MATCHED]]] } }
#
# See sourcebuild.texi for details.
@@ -990,7 +993,7 @@ proc check-function-bodies { args } {
if { [llength $args] < 2
[gcc r15-3223] pr116174.c: Add the missing */
https://gcc.gnu.org/g:ee986126807e68b996d02f5d792268df799b32fb
commit r15-3223-gee986126807e68b996d02f5d792268df799b32fb
Author: H.J. Lu
Date: Tue Aug 27 07:21:02 2024 -0700
pr116174.c: Add the missing */
* gcc.target/i386/pr116174.c: Add the missing */.
Signed-off-by: H.J. Lu
Diff:
---
gcc/testsuite/gcc.target/i386/pr116174.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/testsuite/gcc.target/i386/pr116174.c
b/gcc/testsuite/gcc.target/i386/pr116174.c
index 686aeb9ff314..3c8000f2aad1 100644
--- a/gcc/testsuite/gcc.target/i386/pr116174.c
+++ b/gcc/testsuite/gcc.target/i386/pr116174.c
@@ -1,6 +1,6 @@
/* { dg-do compile { target *-*-linux* } } */
/* { dg-options "-O2 -g0 -fcf-protection=branch" } */
-/* Keep labels and directives ('.p2align', '.cfi_startproc').
+/* Keep labels and directives ('.p2align', '.cfi_startproc'). */
/* { dg-final { check-function-bodies "**" "" "" { target "*-*-*" } {^\t?\.}
} } */
/*
[gcc r15-3224] arm: Always use vmov.f64 instead of vmov.f32 with MVE
https://gcc.gnu.org/g:37c21d4c6ad0afe2aacdd6384b9efa96f5754169 commit r15-3224-g37c21d4c6ad0afe2aacdd6384b9efa96f5754169 Author: Christophe Lyon Date: Wed Aug 21 13:58:08 2024 + arm: Always use vmov.f64 instead of vmov.f32 with MVE With MVE, vmov.f64 is always supported (no need for +fp.dp extension). This patch updates two patterns: - in movdi_vfp, we incorrectly checked TARGET_VFP_SINGLE || TARGET_HAVE_MVE instead of TARGET_VFP_SINGLE && !TARGET_HAVE_MVE, and didn't take into account these two possibilities when computing the length attribute. - in thumb2_movdf_vfp, we checked only TARGET_VFP_SINGLE. No need to update movdf_vfp, since it is enabled only for TARGET_ARM (which is not the case when MVE is enabled). The patch also updates gcc.target/arm/armv8_1m-fp64-move-1.c, to accept only vmov.f64 instead of vmov.f32. Tested on arm-none-eabi with: qemu/-mthumb/-mtune=cortex-m55/-mfloat-abi=hard/-mfpu=auto qemu/-mthumb/-mtune=cortex-m55/-mfloat-abi=hard/-mfpu=auto/-march=armv8.1-m.main+mve qemu/-mthumb/-mtune=cortex-m55/-mfloat-abi=hard/-mfpu=auto/-march=armv8.1-m.main+mve.fp qemu/-mthumb/-mtune=cortex-m55/-mfloat-abi=hard/-mfpu=auto/-march=armv8.1-m.main+mve.fp+fp.dp 2024-08-21 Christophe Lyon gcc/ * config/arm/vfp.md (movdi_vfp, thumb2_movdf_vfp): Handle MVE case. gcc/testsuite/ * gcc.target/arm/armv8_1m-fp64-move-1.c: Update expected code. Diff: --- gcc/config/arm/vfp.md | 8 gcc/testsuite/gcc.target/arm/armv8_1m-fp64-move-1.c | 8 +--- 2 files changed, 5 insertions(+), 11 deletions(-) diff --git a/gcc/config/arm/vfp.md b/gcc/config/arm/vfp.md index 773f55664a95..3212d9c7aa17 100644 --- a/gcc/config/arm/vfp.md +++ b/gcc/config/arm/vfp.md @@ -367,7 +367,7 @@ case 8: return \"vmov%?\\t%Q0, %R0, %P1\\t%@ int\"; case 9: - if (TARGET_VFP_SINGLE || TARGET_HAVE_MVE) + if (TARGET_VFP_SINGLE && !TARGET_HAVE_MVE) return \"vmov%?.f32\\t%0, %1\\t%@ int\;vmov%?.f32\\t%p0, %p1\\t%@ int\"; else return \"vmov%?.f64\\t%P0, %P1\\t%@ int\"; @@ -385,7 +385,7 @@ (symbol_ref "arm_count_output_move_double_insns (operands) * 4") (eq_attr "alternative" "9") (if_then_else - (match_test "TARGET_VFP_SINGLE") + (match_test "TARGET_VFP_SINGLE && !TARGET_HAVE_MVE") (const_int 8) (const_int 4))] (const_int 4))) @@ -744,7 +744,7 @@ case 6: case 7: case 9: return output_move_double (operands, true, NULL); case 8: - if (TARGET_VFP_SINGLE) + if (TARGET_VFP_SINGLE && !TARGET_HAVE_MVE) return \"vmov%?.f32\\t%0, %1\;vmov%?.f32\\t%p0, %p1\"; else return \"vmov%?.f64\\t%P0, %P1\"; @@ -758,7 +758,7 @@ (set (attr "length") (cond [(eq_attr "alternative" "6,7,9") (const_int 8) (eq_attr "alternative" "8") (if_then_else -(match_test "TARGET_VFP_SINGLE") +(match_test "TARGET_VFP_SINGLE && !TARGET_HAVE_MVE") (const_int 8) (const_int 4))] (const_int 4))) diff --git a/gcc/testsuite/gcc.target/arm/armv8_1m-fp64-move-1.c b/gcc/testsuite/gcc.target/arm/armv8_1m-fp64-move-1.c index 39e8c4063247..b7e82f60149c 100644 --- a/gcc/testsuite/gcc.target/arm/armv8_1m-fp64-move-1.c +++ b/gcc/testsuite/gcc.target/arm/armv8_1m-fp64-move-1.c @@ -33,13 +33,7 @@ w_r () /* ** w_w: -** ( -** vmov.f32s2, s0 -** vmov.f32s3, s1 -** | -** vmov.f32s3, s1 -** vmov.f32s2, s0 -** ) +** vmov.f64d1, d0 ** bx lr */ void
[gcc r15-3225] RISC-V: Fix vid const vector expander for non-npatterns size steps
https://gcc.gnu.org/g:c89038c7ae8bba7160ae2963647ce90171b5dd2c
commit r15-3225-gc89038c7ae8bba7160ae2963647ce90171b5dd2c
Author: Patrick O'Neill
Date: Wed Aug 21 23:48:24 2024 -0700
RISC-V: Fix vid const vector expander for non-npatterns size steps
Prior to this patch the expander would emit vectors like:
{ 0, 0, 5, 5, 10, 10, ...}
as:
{ 0, 0, 2, 2, 4, 4, ...}
This patch sets the step size to the requested value.
gcc/ChangeLog:
* config/riscv/riscv-v.cc (expand_const_vector): Fix STEP size in
expander.
Signed-off-by: Patrick O'Neill
Diff:
---
gcc/config/riscv/riscv-v.cc | 48 +++--
1 file changed, 42 insertions(+), 6 deletions(-)
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index c89603669e3a..a3039a2cb199 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -1312,25 +1312,61 @@ expand_const_vector (rtx target, rtx src)
/* Generate the variable-length vector following this rule:
{ a, a, a + step, a + step, a + step * 2, a + step * 2, ...}
E.g. { 0, 0, 8, 8, 16, 16, ... } */
- /* We want to create a pattern where value[ix] = floor (ix /
+
+ /* We want to create a pattern where value[idx] = floor (idx /
NPATTERNS). As NPATTERNS is always a power of two we can
-rewrite this as = ix & -NPATTERNS. */
+rewrite this as = idx & -NPATTERNS. */
/* Step 2: VID AND -NPATTERNS:
{ 0&-4, 1&-4, 2&-4, 3 &-4, 4 &-4, 5 &-4, 6 &-4, 7 &-4, ... }
*/
rtx imm
= gen_int_mode (-builder.npatterns (), builder.inner_mode ());
- rtx tmp = gen_reg_rtx (builder.mode ());
- rtx and_ops[] = {tmp, vid, imm};
+ rtx tmp1 = gen_reg_rtx (builder.mode ());
+ rtx and_ops[] = {tmp1, vid, imm};
icode = code_for_pred_scalar (AND, builder.mode ());
emit_vlmax_insn (icode, BINARY_OP, and_ops);
+
+ /* Step 3: Convert to step size 1. */
+ rtx tmp2 = gen_reg_rtx (builder.mode ());
+ /* log2 (npatterns) to get the shift amount to convert
+Eg. { 0, 0, 0, 0, 4, 4, ... }
+into { 0, 0, 0, 0, 1, 1, ... }. */
+ HOST_WIDE_INT shift_amt = exact_log2 (builder.npatterns ()) ;
+ rtx shift = gen_int_mode (shift_amt, builder.inner_mode ());
+ rtx shift_ops[] = {tmp2, tmp1, shift};
+ icode = code_for_pred_scalar (ASHIFTRT, builder.mode ());
+ emit_vlmax_insn (icode, BINARY_OP, shift_ops);
+
+ /* Step 4: Multiply to step size n. */
+ HOST_WIDE_INT step_size =
+ INTVAL (builder.elt (builder.npatterns ()))
+ - INTVAL (builder.elt (0));
+ rtx tmp3 = gen_reg_rtx (builder.mode ());
+ if (pow2p_hwi (step_size))
+ {
+ /* Power of 2 can be handled with a left shift. */
+ HOST_WIDE_INT shift = exact_log2 (step_size);
+ rtx shift_amount = gen_int_mode (shift, Pmode);
+ insn_code icode = code_for_pred_scalar (ASHIFT, mode);
+ rtx ops[] = {tmp3, tmp2, shift_amount};
+ emit_vlmax_insn (icode, BINARY_OP, ops);
+ }
+ else
+ {
+ rtx mult_amt = gen_int_mode (step_size, builder.inner_mode
());
+ insn_code icode = code_for_pred_scalar (MULT, builder.mode
());
+ rtx ops[] = {tmp3, tmp2, mult_amt};
+ emit_vlmax_insn (icode, BINARY_OP, ops);
+ }
+
+ /* Step 5: Add starting value to all elements. */
HOST_WIDE_INT init_val = INTVAL (builder.elt (0));
if (init_val == 0)
- emit_move_insn (target, tmp);
+ emit_move_insn (target, tmp3);
else
{
rtx dup = gen_const_vector_dup (builder.mode (), init_val);
- rtx add_ops[] = {target, tmp, dup};
+ rtx add_ops[] = {target, tmp3, dup};
icode = code_for_pred (PLUS, builder.mode ());
emit_vlmax_insn (icode, BINARY_OP, add_ops);
}
[gcc r15-3226] RISC-V: Reorder insn cost match order to match corresponding expander match order
https://gcc.gnu.org/g:ac1f3a8901344759dc7c247d3749c74a0bb524b0
commit r15-3226-gac1f3a8901344759dc7c247d3749c74a0bb524b0
Author: Patrick O'Neill
Date: Tue Aug 20 11:38:20 2024 -0700
RISC-V: Reorder insn cost match order to match corresponding expander match
order
The corresponding expander (riscv-v.cc:expand_const_vector) matches
const_vec_duplicate_p before const_vec_series_p. Reorder to match this
behavior when calculating costs.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_const_insns): Relocate.
Signed-off-by: Patrick O'Neill
Diff:
---
gcc/config/riscv/riscv.cc | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 1f544c1287ec..ca86754ec8bf 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -2142,15 +2142,6 @@ riscv_const_insns (rtx x, bool allow_new_pseudos)
...etc. */
if (riscv_v_ext_mode_p (GET_MODE (x)))
{
- /* const series vector. */
- rtx base, step;
- if (const_vec_series_p (x, &base, &step))
- {
- /* This is not accurate, we will need to adapt the COST
-* accurately according to BASE && STEP. */
- return 1;
- }
-
rtx elt;
if (const_vec_duplicate_p (x, &elt))
{
@@ -2186,6 +2177,15 @@ riscv_const_insns (rtx x, bool allow_new_pseudos)
return 1 + 4; /*vmv.v.x + memory access. */
}
}
+
+ /* const series vector. */
+ rtx base, step;
+ if (const_vec_series_p (x, &base, &step))
+ {
+ /* This cost is not accurate, we will need to adapt the COST
+ accurately according to BASE && STEP. */
+ return 1;
+ }
}
/* TODO: We may support more const vector in the future. */
[gcc r15-3227] RISC-V: Handle case when constant vector construction target rtx is not a register
https://gcc.gnu.org/g:a3dc5d2100a3d17a2d67805de6d0373847bca780
commit r15-3227-ga3dc5d2100a3d17a2d67805de6d0373847bca780
Author: Patrick O'Neill
Date: Tue Aug 20 11:29:12 2024 -0700
RISC-V: Handle case when constant vector construction target rtx is not a
register
This manifests in RTL that is optimized away which causes runtime failures
in the testsuite. Update all patterns to use a temp result register if
required.
gcc/ChangeLog:
* config/riscv/riscv-v.cc (expand_const_vector): Use tmp register if
needed.
Signed-off-by: Patrick O'Neill
Diff:
---
gcc/config/riscv/riscv-v.cc | 73 +
1 file changed, 41 insertions(+), 32 deletions(-)
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index a3039a2cb199..aea4b9b872b1 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -1150,26 +1150,29 @@ static void
expand_const_vector (rtx target, rtx src)
{
machine_mode mode = GET_MODE (target);
+ rtx result = register_operand (target, mode) ? target : gen_reg_rtx (mode);
if (GET_MODE_CLASS (mode) == MODE_VECTOR_BOOL)
{
rtx elt;
gcc_assert (
const_vec_duplicate_p (src, &elt)
&& (rtx_equal_p (elt, const0_rtx) || rtx_equal_p (elt, const1_rtx)));
- rtx ops[] = {target, src};
+ rtx ops[] = {result, src};
emit_vlmax_insn (code_for_pred_mov (mode), UNARY_MASK_OP, ops);
+
+ if (result != target)
+ emit_move_insn (target, result);
return;
}
rtx elt;
if (const_vec_duplicate_p (src, &elt))
{
- rtx tmp = register_operand (target, mode) ? target : gen_reg_rtx (mode);
/* Element in range -16 ~ 15 integer or 0.0 floating-point,
we use vmv.v.i instruction. */
if (satisfies_constraint_vi (src) || satisfies_constraint_Wc0 (src))
{
- rtx ops[] = {tmp, src};
+ rtx ops[] = {result, src};
emit_vlmax_insn (code_for_pred_mov (mode), UNARY_OP, ops);
}
else
@@ -1186,7 +1189,7 @@ expand_const_vector (rtx target, rtx src)
instruction (vsetvl a5, zero). */
if (lra_in_progress)
{
- rtx ops[] = {tmp, elt};
+ rtx ops[] = {result, elt};
emit_vlmax_insn (code_for_pred_broadcast (mode), UNARY_OP, ops);
}
else
@@ -1194,15 +1197,15 @@ expand_const_vector (rtx target, rtx src)
struct expand_operand ops[2];
enum insn_code icode = optab_handler (vec_duplicate_optab, mode);
gcc_assert (icode != CODE_FOR_nothing);
- create_output_operand (&ops[0], tmp, mode);
+ create_output_operand (&ops[0], result, mode);
create_input_operand (&ops[1], elt, GET_MODE_INNER (mode));
expand_insn (icode, 2, ops);
- tmp = ops[0].value;
+ result = ops[0].value;
}
}
- if (tmp != target)
- emit_move_insn (target, tmp);
+ if (result != target)
+ emit_move_insn (target, result);
return;
}
@@ -1210,7 +1213,10 @@ expand_const_vector (rtx target, rtx src)
rtx base, step;
if (const_vec_series_p (src, &base, &step))
{
- expand_vec_series (target, base, step);
+ expand_vec_series (result, base, step);
+
+ if (result != target)
+ emit_move_insn (target, result);
return;
}
@@ -1243,7 +1249,7 @@ expand_const_vector (rtx target, rtx src)
all element equal to 0x0706050403020100. */
rtx ele = builder.get_merged_repeating_sequence ();
rtx dup = expand_vector_broadcast (builder.new_mode (), ele);
- emit_move_insn (target, gen_lowpart (mode, dup));
+ emit_move_insn (result, gen_lowpart (mode, dup));
}
else
{
@@ -1272,8 +1278,8 @@ expand_const_vector (rtx target, rtx src)
emit_vlmax_insn (code_for_pred_scalar (AND, builder.int_mode ()),
BINARY_OP, and_ops);
- rtx tmp = gen_reg_rtx (builder.mode ());
- rtx dup_ops[] = {tmp, builder.elt (0)};
+ rtx tmp1 = gen_reg_rtx (builder.mode ());
+ rtx dup_ops[] = {tmp1, builder.elt (0)};
emit_vlmax_insn (code_for_pred_broadcast (builder.mode ()), UNARY_OP,
dup_ops);
for (unsigned int i = 1; i < builder.npatterns (); i++)
@@ -1285,12 +1291,12 @@ expand_const_vector (rtx target, rtx src)
/* Merge scalar to each i. */
rtx tmp2 = gen_reg_rtx (builder.mode ());
- rtx merge_ops[] = {tmp2, tmp, builder.elt (i), mask};
+ rtx merge_ops[] = {tmp2, tmp1, builder.elt (i), mask};
insn_code icode = code_for_pred_merge_scalar (builder.mode ());
emit_vlmax_insn (icode, MERGE_OP, merge_ops);
- tmp = tmp2;
+ tmp1 = tmp2;
}
-
[gcc r15-3229] RISC-V: Handle 0.0 floating point pattern costing to match const_vector expander
https://gcc.gnu.org/g:282bbc9381c563c746a43bf35e93d349188cc8e8
commit r15-3229-g282bbc9381c563c746a43bf35e93d349188cc8e8
Author: Patrick O'Neill
Date: Tue Aug 20 12:01:22 2024 -0700
RISC-V: Handle 0.0 floating point pattern costing to match const_vector
expander
The comment previously here stated that the Wc0/Wc1 cases are handled by
the vi constraint but that is not true for the 0.0 Wc0 case.
gcc/ChangeLog:
* config/riscv/riscv-v.h (valid_vec_immediate_p): Add new helper.
* config/riscv/riscv-v.cc (valid_vec_immediate_p): Ditto.
(expand_const_vector): Use new helper.
* config/riscv/riscv.cc (riscv_const_insns): Handle 0.0
floating-point
case.
Signed-off-by: Patrick O'Neill
Diff:
---
gcc/config/riscv/riscv-v.cc | 11 ++-
gcc/config/riscv/riscv-v.h | 2 ++
gcc/config/riscv/riscv.cc | 8 +++-
3 files changed, 15 insertions(+), 6 deletions(-)
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 897b31c069e4..32349677dc28 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -794,6 +794,15 @@ const_vec_all_in_range_p (rtx vec, poly_int64 minval,
poly_int64 maxval)
return true;
}
+/* Returns true if the vector's elements are all duplicates in
+ range -16 ~ 15 integer or 0.0 floating-point. */
+
+bool
+valid_vec_immediate_p (rtx x)
+{
+ return (satisfies_constraint_vi (x) || satisfies_constraint_Wc0 (x));
+}
+
/* Return a const vector of VAL. The VAL can be either const_int or
const_poly_int. */
@@ -1119,7 +1128,7 @@ expand_const_vector (rtx target, rtx src)
{
/* Element in range -16 ~ 15 integer or 0.0 floating-point,
we use vmv.v.i instruction. */
- if (satisfies_constraint_vi (src) || satisfies_constraint_Wc0 (src))
+ if (valid_vec_immediate_p (src))
{
rtx ops[] = {result, src};
emit_vlmax_insn (code_for_pred_mov (mode), UNARY_OP, ops);
diff --git a/gcc/config/riscv/riscv-v.h b/gcc/config/riscv/riscv-v.h
index 4635b5415c78..e7b095f094e6 100644
--- a/gcc/config/riscv/riscv-v.h
+++ b/gcc/config/riscv/riscv-v.h
@@ -83,6 +83,8 @@ private:
unsigned int m_inner_bytes_size;
};
+extern bool valid_vec_immediate_p(rtx);
+
} // namespace riscv_vector
#endif // GCC_RISCV_V_H
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 771ab52625f8..e9b1b9bc3add 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -2158,11 +2158,9 @@ riscv_const_insns (rtx x, bool allow_new_pseudos)
if (maybe_gt (GET_MODE_SIZE (smode), UNITS_PER_WORD)
&& !immediate_operand (elt, Pmode))
return 0;
- /* Constants from -16 to 15 can be loaded with vmv.v.i.
- The Wc0, Wc1 constraints are already covered by the
- vi constraint so we do not need to check them here
- separately. */
- if (satisfies_constraint_vi (x))
+ /* Constants in range -16 ~ 15 integer or 0.0 floating-point
+ can be emitted using vmv.v.i. */
+ if (valid_vec_immediate_p (x))
return 1;
/* Any int/FP constants can always be broadcast from a
[gcc r15-3231] RISC-V: Move helper functions above expand_const_vector
https://gcc.gnu.org/g:691f682fe24d07ff5854f1f53d81909320110c9c
commit r15-3231-g691f682fe24d07ff5854f1f53d81909320110c9c
Author: Patrick O'Neill
Date: Mon Aug 19 12:40:14 2024 -0700
RISC-V: Move helper functions above expand_const_vector
These subroutines will be used in expand_const_vector in a future patch.
Relocate so expand_const_vector can use them.
gcc/ChangeLog:
* config/riscv/riscv-v.cc (expand_vector_init_insert_elems):
Relocate.
(expand_vector_init_trailing_same_elem): Ditto.
Signed-off-by: Patrick O'Neill
Diff:
---
gcc/config/riscv/riscv-v.cc | 132 ++--
1 file changed, 66 insertions(+), 66 deletions(-)
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index cb2380ad6643..9b6c3a21e2d3 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -1104,6 +1104,72 @@ expand_vec_series (rtx dest, rtx base, rtx step, rtx vid)
emit_move_insn (dest, result);
}
+/* Subroutine of riscv_vector_expand_vector_init.
+ Works as follows:
+ (a) Initialize TARGET by broadcasting element NELTS_REQD - 1 of BUILDER.
+ (b) Skip leading elements from BUILDER, which are the same as
+ element NELTS_REQD - 1.
+ (c) Insert earlier elements in reverse order in TARGET using vslide1down.
*/
+
+static void
+expand_vector_init_insert_elems (rtx target, const rvv_builder &builder,
+int nelts_reqd)
+{
+ machine_mode mode = GET_MODE (target);
+ rtx dup = expand_vector_broadcast (mode, builder.elt (0));
+ emit_move_insn (target, dup);
+ int ndups = builder.count_dups (0, nelts_reqd - 1, 1);
+ for (int i = ndups; i < nelts_reqd; i++)
+{
+ unsigned int unspec
+ = FLOAT_MODE_P (mode) ? UNSPEC_VFSLIDE1DOWN : UNSPEC_VSLIDE1DOWN;
+ insn_code icode = code_for_pred_slide (unspec, mode);
+ rtx ops[] = {target, target, builder.elt (i)};
+ emit_vlmax_insn (icode, BINARY_OP, ops);
+}
+}
+
+/* Subroutine of expand_vec_init to handle case
+ when all trailing elements of builder are same.
+ This works as follows:
+ (a) Use expand_insn interface to broadcast last vector element in TARGET.
+ (b) Insert remaining elements in TARGET using insr.
+
+ ??? The heuristic used is to do above if number of same trailing elements
+ is greater than leading_ndups, loosely based on
+ heuristic from mostly_zeros_p. May need fine-tuning. */
+
+static bool
+expand_vector_init_trailing_same_elem (rtx target,
+ const rtx_vector_builder &builder,
+ int nelts_reqd)
+{
+ int leading_ndups = builder.count_dups (0, nelts_reqd - 1, 1);
+ int trailing_ndups = builder.count_dups (nelts_reqd - 1, -1, -1);
+ machine_mode mode = GET_MODE (target);
+
+ if (trailing_ndups > leading_ndups)
+{
+ rtx dup = expand_vector_broadcast (mode, builder.elt (nelts_reqd - 1));
+ for (int i = nelts_reqd - trailing_ndups - 1; i >= 0; i--)
+ {
+ unsigned int unspec
+ = FLOAT_MODE_P (mode) ? UNSPEC_VFSLIDE1UP : UNSPEC_VSLIDE1UP;
+ insn_code icode = code_for_pred_slide (unspec, mode);
+ rtx tmp = gen_reg_rtx (mode);
+ rtx ops[] = {tmp, dup, builder.elt (i)};
+ emit_vlmax_insn (icode, BINARY_OP, ops);
+ /* slide1up need source and dest to be different REG. */
+ dup = tmp;
+ }
+
+ emit_move_insn (target, dup);
+ return true;
+}
+
+ return false;
+}
+
static void
expand_const_vector (rtx target, rtx src)
{
@@ -2338,31 +2404,6 @@ preferred_simd_mode (scalar_mode mode)
return word_mode;
}
-/* Subroutine of riscv_vector_expand_vector_init.
- Works as follows:
- (a) Initialize TARGET by broadcasting element NELTS_REQD - 1 of BUILDER.
- (b) Skip leading elements from BUILDER, which are the same as
- element NELTS_REQD - 1.
- (c) Insert earlier elements in reverse order in TARGET using vslide1down.
*/
-
-static void
-expand_vector_init_insert_elems (rtx target, const rvv_builder &builder,
-int nelts_reqd)
-{
- machine_mode mode = GET_MODE (target);
- rtx dup = expand_vector_broadcast (mode, builder.elt (0));
- emit_move_insn (target, dup);
- int ndups = builder.count_dups (0, nelts_reqd - 1, 1);
- for (int i = ndups; i < nelts_reqd; i++)
-{
- unsigned int unspec
- = FLOAT_MODE_P (mode) ? UNSPEC_VFSLIDE1DOWN : UNSPEC_VSLIDE1DOWN;
- insn_code icode = code_for_pred_slide (unspec, mode);
- rtx ops[] = {target, target, builder.elt (i)};
- emit_vlmax_insn (icode, BINARY_OP, ops);
-}
-}
-
/* Use merge approach to initialize the vector with repeating sequence.
v = {a, b, a, b, a, b, a, b}.
@@ -2487,47 +2528,6 @@ expand_vector_init_merge_combine_sequence (rtx target,
emit_vlmax_insn (icode, MERGE_OP, merge_ops);
}
-/* Subroutine of expand_vec_init to handle case
-
[gcc r15-3228] RISC-V: Emit costs for bool and stepped const vectors
https://gcc.gnu.org/g:771256bcb9ddc478dd0a8ecf929dfda5334f0ff3
commit r15-3228-g771256bcb9ddc478dd0a8ecf929dfda5334f0ff3
Author: Patrick O'Neill
Date: Tue Aug 20 11:51:50 2024 -0700
RISC-V: Emit costs for bool and stepped const vectors
These cases are handled in the expander
(riscv-v.cc:expand_const_vector). We need the vector builder to detect
these cases so extract that out into a new riscv-v.h header file.
gcc/ChangeLog:
* config/riscv/riscv-v.cc (class rvv_builder): Move to riscv-v.h.
* config/riscv/riscv.cc (riscv_const_insns): Emit placeholder costs
for
bool/stepped const vectors.
* config/riscv/riscv-v.h: New file.
Signed-off-by: Patrick O'Neill
Diff:
---
gcc/config/riscv/riscv-v.cc | 53 +--
gcc/config/riscv/riscv-v.h | 88 +
gcc/config/riscv/riscv.cc | 42 ++
3 files changed, 131 insertions(+), 52 deletions(-)
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index aea4b9b872b1..897b31c069e4 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -51,6 +51,7 @@
#include "targhooks.h"
#include "predict.h"
#include "errors.h"
+#include "riscv-v.h"
using namespace riscv_vector;
@@ -436,58 +437,6 @@ emit_nonvlmax_insn (unsigned icode, unsigned insn_flags,
rtx *ops, rtx vl)
e.emit_insn ((enum insn_code) icode, ops);
}
-class rvv_builder : public rtx_vector_builder
-{
-public:
- rvv_builder () : rtx_vector_builder () {}
- rvv_builder (machine_mode mode, unsigned int npatterns,
- unsigned int nelts_per_pattern)
-: rtx_vector_builder (mode, npatterns, nelts_per_pattern)
- {
-m_inner_mode = GET_MODE_INNER (mode);
-m_inner_bits_size = GET_MODE_BITSIZE (m_inner_mode);
-m_inner_bytes_size = GET_MODE_SIZE (m_inner_mode);
-m_mask_mode = get_mask_mode (mode);
-
-gcc_assert (
- int_mode_for_size (inner_bits_size (), 0).exists (&m_inner_int_mode));
-m_int_mode
- = get_vector_mode (m_inner_int_mode, GET_MODE_NUNITS (mode)).require ();
- }
-
- bool can_duplicate_repeating_sequence_p ();
- bool is_repeating_sequence ();
- rtx get_merged_repeating_sequence ();
-
- bool repeating_sequence_use_merge_profitable_p ();
- bool combine_sequence_use_slideup_profitable_p ();
- bool combine_sequence_use_merge_profitable_p ();
- rtx get_merge_scalar_mask (unsigned int, machine_mode) const;
-
- bool single_step_npatterns_p () const;
- bool npatterns_all_equal_p () const;
- bool interleaved_stepped_npatterns_p () const;
- bool npatterns_vid_diff_repeated_p () const;
-
- machine_mode new_mode () const { return m_new_mode; }
- scalar_mode inner_mode () const { return m_inner_mode; }
- scalar_int_mode inner_int_mode () const { return m_inner_int_mode; }
- machine_mode mask_mode () const { return m_mask_mode; }
- machine_mode int_mode () const { return m_int_mode; }
- unsigned int inner_bits_size () const { return m_inner_bits_size; }
- unsigned int inner_bytes_size () const { return m_inner_bytes_size; }
-
-private:
- scalar_mode m_inner_mode;
- scalar_int_mode m_inner_int_mode;
- machine_mode m_new_mode;
- scalar_int_mode m_new_inner_mode;
- machine_mode m_mask_mode;
- machine_mode m_int_mode;
- unsigned int m_inner_bits_size;
- unsigned int m_inner_bytes_size;
-};
-
/* Return true if the vector duplicated by a super element which is the fusion
of consecutive elements.
diff --git a/gcc/config/riscv/riscv-v.h b/gcc/config/riscv/riscv-v.h
new file mode 100644
index ..4635b5415c78
--- /dev/null
+++ b/gcc/config/riscv/riscv-v.h
@@ -0,0 +1,88 @@
+/* Subroutines used for code generation for RISC-V 'V' Extension for
+ GNU compiler.
+ Copyright (C) 2022-2024 Free Software Foundation, Inc.
+ Contributed by Juzhe Zhong (juzhe.zh...@rivai.ai), RiVAI Technologies Ltd.
+
+ This file is part of GCC.
+
+ GCC is free software; you can redistribute it and/or modify it
+ under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ GCC is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with GCC; see the file COPYING3. If not see
+
[gcc r15-3230] RISC-V: Allow non-duplicate bool patterns in expand_const_vector
https://gcc.gnu.org/g:1cd890279668bf94c93004bdbb757a1342931914
commit r15-3230-g1cd890279668bf94c93004bdbb757a1342931914
Author: Patrick O'Neill
Date: Tue Aug 20 12:50:51 2024 -0700
RISC-V: Allow non-duplicate bool patterns in expand_const_vector
Currently we assert when encountering a non-duplicate boolean vector.
This patch allows non-duplicate vectors to fall through to the
gcc_unreachable and assert there.
This will be useful when adding a catch-all pattern to emit costs and
handle arbitary vectors.
gcc/ChangeLog:
* config/riscv/riscv-v.cc (expand_const_vector): Allow non-duplicate
to fall through other patterns before asserting.
Signed-off-by: Patrick O'Neill
Diff:
---
gcc/config/riscv/riscv-v.cc | 23 ---
1 file changed, 8 insertions(+), 15 deletions(-)
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 32349677dc28..cb2380ad6643 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -1109,26 +1109,19 @@ expand_const_vector (rtx target, rtx src)
{
machine_mode mode = GET_MODE (target);
rtx result = register_operand (target, mode) ? target : gen_reg_rtx (mode);
- if (GET_MODE_CLASS (mode) == MODE_VECTOR_BOOL)
-{
- rtx elt;
- gcc_assert (
- const_vec_duplicate_p (src, &elt)
- && (rtx_equal_p (elt, const0_rtx) || rtx_equal_p (elt, const1_rtx)));
- rtx ops[] = {result, src};
- emit_vlmax_insn (code_for_pred_mov (mode), UNARY_MASK_OP, ops);
-
- if (result != target)
- emit_move_insn (target, result);
- return;
-}
-
rtx elt;
if (const_vec_duplicate_p (src, &elt))
{
+ if (GET_MODE_CLASS (mode) == MODE_VECTOR_BOOL)
+ {
+ gcc_assert (rtx_equal_p (elt, const0_rtx)
+ || rtx_equal_p (elt, const1_rtx));
+ rtx ops[] = {result, src};
+ emit_vlmax_insn (code_for_pred_mov (mode), UNARY_MASK_OP, ops);
+ }
/* Element in range -16 ~ 15 integer or 0.0 floating-point,
we use vmv.v.i instruction. */
- if (valid_vec_immediate_p (src))
+ else if (valid_vec_immediate_p (src))
{
rtx ops[] = {result, src};
emit_vlmax_insn (code_for_pred_mov (mode), UNARY_OP, ops);
[gcc r15-3232] c++: Don't show constructor internal name in error message [PR105483]
https://gcc.gnu.org/g:02dff52c60e5b89d290147f142f655c7817154c2
commit r15-3232-g02dff52c60e5b89d290147f142f655c7817154c2
Author: Simon Martin
Date: Mon Aug 26 14:09:46 2024 +0200
c++: Don't show constructor internal name in error message [PR105483]
We mention 'X::__ct' instead of 'X::X' in the "names the constructor,
not the type" error for this invalid code:
=== cut here ===
struct X {};
void g () {
X::X x;
}
=== cut here ===
The problem is that we use %<%T::%D%> to build the error message, while
%qE does exactly what we need since we have DECL_CONSTRUCTOR_P. This is
what this patch does.
It also skips until the end of the statement and returns error_mark_node
for this and the preceding if block, to avoid emitting extra (useless)
errors.
PR c++/105483
gcc/cp/ChangeLog:
* parser.cc (cp_parser_expression_statement): Use %qE instead of
incorrect %<%T::%D%>. Skip to end of statement and return
error_mark_node in case of error.
gcc/testsuite/ChangeLog:
* g++.dg/parse/error36.C: Adjust test expectation.
* g++.dg/tc1/dr147.C: Likewise.
* g++.old-deja/g++.other/typename1.C: Likewise.
* g++.dg/diagnostic/pr105483.C: New test.
Diff:
---
gcc/cp/parser.cc | 14 +-
gcc/testsuite/g++.dg/diagnostic/pr105483.C | 7 +++
gcc/testsuite/g++.dg/parse/error36.C | 4 ++--
gcc/testsuite/g++.dg/tc1/dr147.C | 2 +-
gcc/testsuite/g++.old-deja/g++.other/typename1.C | 2 +-
5 files changed, 20 insertions(+), 9 deletions(-)
diff --git a/gcc/cp/parser.cc b/gcc/cp/parser.cc
index 28ebf2beb60a..a722641be347 100644
--- a/gcc/cp/parser.cc
+++ b/gcc/cp/parser.cc
@@ -13232,18 +13232,22 @@ cp_parser_expression_statement (cp_parser* parser,
tree in_statement_expr)
if (cp_lexer_next_token_is_not (parser->lexer, CPP_SEMICOLON)
&& !cp_parser_uncommitted_to_tentative_parse_p (parser))
{
+ bool has_errored = true;
if (TREE_CODE (statement) == SCOPE_REF)
error_at (token->location, "need % before %qE because "
"%qT is a dependent scope",
statement, TREE_OPERAND (statement, 0));
else if (is_overloaded_fn (statement)
&& DECL_CONSTRUCTOR_P (get_first_fn (statement)))
+ /* A::A a; */
+ error_at (token->location, "%qE names the constructor, not the type",
+ get_first_fn (statement));
+ else
+ has_errored = false;
+ if (has_errored)
{
- /* A::A a; */
- tree fn = get_first_fn (statement);
- error_at (token->location,
- "%<%T::%D%> names the constructor, not the type",
- DECL_CONTEXT (fn), DECL_NAME (fn));
+ cp_parser_skip_to_end_of_statement (parser);
+ return error_mark_node;
}
}
diff --git a/gcc/testsuite/g++.dg/diagnostic/pr105483.C
b/gcc/testsuite/g++.dg/diagnostic/pr105483.C
new file mode 100644
index ..b935bacea11b
--- /dev/null
+++ b/gcc/testsuite/g++.dg/diagnostic/pr105483.C
@@ -0,0 +1,7 @@
+// PR c++/105483
+// { dg-do compile }
+
+struct X { };
+void g () {
+ X::X x; // { dg-error "'X::X' names the constructor" }
+}
diff --git a/gcc/testsuite/g++.dg/parse/error36.C
b/gcc/testsuite/g++.dg/parse/error36.C
index bf57a6b68ce8..73b550e3f2ad 100644
--- a/gcc/testsuite/g++.dg/parse/error36.C
+++ b/gcc/testsuite/g++.dg/parse/error36.C
@@ -12,7 +12,7 @@ void f(T t)
{
typedef A::foo type; // { dg-error "typename" }
A::bar b; // { dg-error "typename" "typename" }
-} // { dg-error "expected ';'" "expected" { target *-*-* } .-1 }
+}
// PR c++/36353
template struct B
@@ -20,7 +20,7 @@ template struct B
void f()
{
A::baz z; // { dg-error "typename" "typename" }
- } // { dg-error "expected ';'" "expected" { target *-*-* } .-1 }
+ }
};
// PR c++/40738
diff --git a/gcc/testsuite/g++.dg/tc1/dr147.C b/gcc/testsuite/g++.dg/tc1/dr147.C
index 6b656491e816..ced18d1879cc 100644
--- a/gcc/testsuite/g++.dg/tc1/dr147.C
+++ b/gcc/testsuite/g++.dg/tc1/dr147.C
@@ -21,7 +21,7 @@ void A::f()
void f()
{
A::A a; // { dg-error "constructor" "constructor" }
-} // { dg-error "" "error cascade" { target *-*-* } .-1 } error cascade
+}
}
namespace N2 {
diff --git a/gcc/testsuite/g++.old-deja/g++.other/typename1.C
b/gcc/testsuite/g++.old-deja/g++.other/typename1.C
index 4e1a4a834ddd..0f0f68b1cee2 100644
--- a/gcc/testsuite/g++.old-deja/g++.other/typename1.C
+++ b/gcc/testsuite/g++.old-deja/g++.other/typename1.C
@@ -14,4 +14,4 @@ template
void f()
{
Vector::iterator i = 0; // { dg-error "typename" "typename" } missing
typename
-} // { dg-error "expected" "expected" { target *-*-* } .-1 }
+}
[gcc r15-3233] m68k: Accept ASHIFT like MULT in address operand
https://gcc.gnu.org/g:a83e519ab2d4e7df2756411cd9d21c6f1b583429
commit r15-3233-ga83e519ab2d4e7df2756411cd9d21c6f1b583429
Author: Andreas Schwab
Date: Tue Aug 27 21:01:00 2024 +0200
m68k: Accept ASHIFT like MULT in address operand
When LRA pulls an address operand out of a MEM it caninoicalizes a
containing MULT into ASHIFT. Adjust the address decomposer to recognize
this form.
PR target/116413
* config/m68k/m68k.cc (m68k_decompose_index): Accept ASHIFT like
MULT.
(m68k_rtx_costs) [PLUS]: Likewise.
(m68k_legitimize_address): Likewise.
Diff:
---
gcc/config/m68k/m68k.cc | 58 ++---
1 file changed, 40 insertions(+), 18 deletions(-)
diff --git a/gcc/config/m68k/m68k.cc b/gcc/config/m68k/m68k.cc
index 21c94981d220..7986e92c5116 100644
--- a/gcc/config/m68k/m68k.cc
+++ b/gcc/config/m68k/m68k.cc
@@ -1503,12 +1503,14 @@ m68k_legitimize_address (rtx x, rtx oldx, machine_mode
mode)
#define COPY_ONCE(Y) if (!copied) { Y = copy_rtx (Y); copied = ch = 1; }
- if (GET_CODE (XEXP (x, 0)) == MULT)
+ if (GET_CODE (XEXP (x, 0)) == MULT
+ || GET_CODE (XEXP (x, 0)) == ASHIFT)
{
COPY_ONCE (x);
XEXP (x, 0) = force_operand (XEXP (x, 0), 0);
}
- if (GET_CODE (XEXP (x, 1)) == MULT)
+ if (GET_CODE (XEXP (x, 1)) == MULT
+ || GET_CODE (XEXP (x, 1)) == ASHIFT)
{
COPY_ONCE (x);
XEXP (x, 1) = force_operand (XEXP (x, 1), 0);
@@ -2069,16 +2071,29 @@ m68k_decompose_index (rtx x, bool strict_p, struct
m68k_address *address)
/* Check for a scale factor. */
scale = 1;
- if ((TARGET_68020 || TARGET_COLDFIRE)
- && GET_CODE (x) == MULT
- && GET_CODE (XEXP (x, 1)) == CONST_INT
- && (INTVAL (XEXP (x, 1)) == 2
- || INTVAL (XEXP (x, 1)) == 4
- || (INTVAL (XEXP (x, 1)) == 8
- && (TARGET_COLDFIRE_FPU || !TARGET_COLDFIRE
+ if (TARGET_68020 || TARGET_COLDFIRE)
{
- scale = INTVAL (XEXP (x, 1));
- x = XEXP (x, 0);
+ if (GET_CODE (x) == MULT
+ && GET_CODE (XEXP (x, 1)) == CONST_INT
+ && (INTVAL (XEXP (x, 1)) == 2
+ || INTVAL (XEXP (x, 1)) == 4
+ || (INTVAL (XEXP (x, 1)) == 8
+ && (TARGET_COLDFIRE_FPU || !TARGET_COLDFIRE
+ {
+ scale = INTVAL (XEXP (x, 1));
+ x = XEXP (x, 0);
+ }
+ /* LRA uses ASHIFT instead of MULT outside of MEM. */
+ else if (GET_CODE (x) == ASHIFT
+ && GET_CODE (XEXP (x, 1)) == CONST_INT
+ && (INTVAL (XEXP (x, 1)) == 1
+ || INTVAL (XEXP (x, 1)) == 2
+ || (INTVAL (XEXP (x, 1)) == 3
+ && (TARGET_COLDFIRE_FPU || !TARGET_COLDFIRE
+ {
+ scale = 1 << INTVAL (XEXP (x, 1));
+ x = XEXP (x, 0);
+ }
}
/* Check for a word extension. */
@@ -2246,8 +2261,10 @@ m68k_decompose_address (machine_mode mode, rtx x,
??? do_tablejump creates these addresses before placing the target
label, so we have to assume that unplaced labels are jump table
references. It seems unlikely that we would ever generate indexed
- accesses to unplaced labels in other cases. */
+ accesses to unplaced labels in other cases. Do not accept it in
+ PIC mode, since the label address will need to be loaded from memory. */
if (GET_CODE (x) == PLUS
+ && !flag_pic
&& m68k_jump_table_ref_p (XEXP (x, 1))
&& m68k_decompose_index (XEXP (x, 0), strict_p, address))
{
@@ -3068,12 +3085,17 @@ m68k_rtx_costs (rtx x, machine_mode mode, int
outer_code,
/* An lea costs about three times as much as a simple add. */
if (mode == SImode
&& GET_CODE (XEXP (x, 1)) == REG
- && GET_CODE (XEXP (x, 0)) == MULT
- && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
- && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
- && (INTVAL (XEXP (XEXP (x, 0), 1)) == 2
- || INTVAL (XEXP (XEXP (x, 0), 1)) == 4
- || INTVAL (XEXP (XEXP (x, 0), 1)) == 8))
+ && ((GET_CODE (XEXP (x, 0)) == MULT
+ && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
+ && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
+ && (INTVAL (XEXP (XEXP (x, 0), 1)) == 2
+ || INTVAL (XEXP (XEXP (x, 0), 1)) == 4
+ || INTVAL (XEXP (XEXP (x, 0), 1)) == 8))
+ || (GET_CODE (XEXP (x, 0)) == ASHIFT
+ && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
+ && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
+ && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (x, 0), 1))
+ <= 3
{
/* lea an@(dx:l:i),am */
*total = COSTS_N_INSNS (TARGET_COLDFIRE ? 2 : 3);
[gcc r15-3234] c++/coroutines: fix actor cases not being added to the current switch [PR109867]
https://gcc.gnu.org/g:ff0cba200af72f2514ebc987a99027f314d4cc99
commit r15-3234-gff0cba200af72f2514ebc987a99027f314d4cc99
Author: Arsen Arsenović
Date: Wed Jul 24 20:43:01 2024 +0200
c++/coroutines: fix actor cases not being added to the current switch
[PR109867]
Previously, we were building and inserting case_labels manually, which
led to them not being added into the currently running switch via
c_add_case_label. This led to false diagnostics that the user could not
act on.
PR c++/109867
gcc/cp/ChangeLog:
* coroutines.cc (expand_one_await_expression): Replace uses of
build_case_label with finish_case_label.
(build_actor_fn): Ditto.
(create_anon_label_with_ctx): Remove now-unused function.
gcc/testsuite/ChangeLog:
* g++.dg/coroutines/torture/pr109867.C: New test.
Reviewed-by: Iain Sandoe
Diff:
---
gcc/cp/coroutines.cc | 52 +-
gcc/testsuite/g++.dg/coroutines/torture/pr109867.C | 23 ++
2 files changed, 34 insertions(+), 41 deletions(-)
diff --git a/gcc/cp/coroutines.cc b/gcc/cp/coroutines.cc
index 31dc39afeee2..f243fe9adae2 100644
--- a/gcc/cp/coroutines.cc
+++ b/gcc/cp/coroutines.cc
@@ -1708,20 +1708,6 @@ coro_build_artificial_var (location_t loc, const char
*name, tree type,
type, ctx, init);
}
-/* Helpers for label creation:
- 1. Create a named label in the specified context. */
-
-static tree
-create_anon_label_with_ctx (location_t loc, tree ctx)
-{
- tree lab = build_decl (loc, LABEL_DECL, NULL_TREE, void_type_node);
-
- DECL_CONTEXT (lab) = ctx;
- DECL_ARTIFICIAL (lab) = true;
- DECL_IGNORED_P (lab) = true;
- TREE_USED (lab) = true;
- return lab;
-}
/* 2. Create a named label in the specified context. */
@@ -1935,22 +1921,16 @@ expand_one_await_expression (tree *stmt, tree
*await_expr, void *d)
data->coro_fp);
r = cp_build_init_expr (cond, r);
finish_switch_cond (r, sw);
- r = build_case_label (integer_zero_node, NULL_TREE,
- create_anon_label_with_ctx (loc, actor));
- add_stmt (r); /* case 0: */
+ finish_case_label (loc, integer_zero_node, NULL_TREE); /* case 0: */
/* Implement the suspend, a scope exit without clean ups. */
r = build_call_expr_internal_loc (loc, IFN_CO_SUSPN, void_type_node, 1,
is_cont ? cont : susp);
r = coro_build_cvt_void_expr_stmt (r, loc);
add_stmt (r); /* goto ret; */
- r = build_case_label (integer_one_node, NULL_TREE,
- create_anon_label_with_ctx (loc, actor));
- add_stmt (r); /* case 1: */
+ finish_case_label (loc, integer_one_node, NULL_TREE); /* case 1: */
r = build1_loc (loc, GOTO_EXPR, void_type_node, resume_label);
add_stmt (r); /* goto resume; */
- r = build_case_label (NULL_TREE, NULL_TREE,
- create_anon_label_with_ctx (loc, actor));
- add_stmt (r); /* default:; */
+ finish_case_label (loc, NULL_TREE, NULL_TREE); /* default:; */
r = build1_loc (loc, GOTO_EXPR, void_type_node, destroy_label);
add_stmt (r); /* goto destroy; */
@@ -2291,9 +2271,7 @@ build_actor_fn (location_t loc, tree coro_frame_type,
tree actor, tree fnbody,
tree destroy_dispatcher = begin_switch_stmt ();
finish_switch_cond (rat, destroy_dispatcher);
- tree ddeflab = build_case_label (NULL_TREE, NULL_TREE,
- create_anon_label_with_ctx (loc, actor));
- add_stmt (ddeflab);
+ tree ddeflab = finish_case_label (loc, NULL_TREE, NULL_TREE);
tree b = build_call_expr_loc (loc, builtin_decl_explicit (BUILT_IN_TRAP), 0);
b = coro_build_cvt_void_expr_stmt (b, loc);
add_stmt (b);
@@ -2304,18 +2282,15 @@ build_actor_fn (location_t loc, tree coro_frame_type,
tree actor, tree fnbody,
frame itself. */
tree del_promise_label
= create_named_label_with_ctx (loc, "coro.delete.promise", actor);
- b = build_case_label (build_int_cst (short_unsigned_type_node, 1), NULL_TREE,
- create_anon_label_with_ctx (loc, actor));
- add_stmt (b);
+ finish_case_label (loc, build_int_cst (short_unsigned_type_node, 1),
+NULL_TREE);
add_stmt (build_stmt (loc, GOTO_EXPR, del_promise_label));
short unsigned lab_num = 3;
for (unsigned destr_pt = 0; destr_pt < body_count; destr_pt++)
{
tree l_num = build_int_cst (short_unsigned_type_node, lab_num);
- b = build_case_label (l_num, NULL_TREE,
- create_anon_label_with_ctx (loc, actor));
- add_stmt (b);
+ finish_case_label (loc, l_num, NULL_TREE);
b = build_call_expr_internal_loc (loc, IFN_CO_ACTOR, void_type_node, 1,
l_num);
b = coro_build_cvt_void_expr_stmt (b, loc);
@@ -2333,15 +2308,12 @@ build_actor_fn (location_t loc
[gcc r15-3235] Update gcc zh_CN.po
https://gcc.gnu.org/g:48032f28ad4bc5e810c303229bcaa223a0c4d09f
commit r15-3235-g48032f28ad4bc5e810c303229bcaa223a0c4d09f
Author: Joseph Myers
Date: Tue Aug 27 21:20:43 2024 +
Update gcc zh_CN.po
* zh_CN.po: Update.
Diff:
---
gcc/po/zh_CN.po | 351 +++-
1 file changed, 146 insertions(+), 205 deletions(-)
diff --git a/gcc/po/zh_CN.po b/gcc/po/zh_CN.po
index 133c36a8ec47..b80a0281e24d 100644
--- a/gcc/po/zh_CN.po
+++ b/gcc/po/zh_CN.po
@@ -6,6 +6,7 @@
# Mingye Wang (Arthur2e5) , 2015, 2016.
# Boyuan Yang <073p...@gmail.com>, 2019, 2023, 2024.
# Zixing Zhou , 2023.
+# Zhanhaoxiang Zhang , 2024.
#
# Fellow translatiors:
# Many of the fuzzy strings are caused by an addition of a period (".")
@@ -35,8 +36,8 @@ msgstr ""
"Project-Id-Version: gcc 14.2.0\n"
"Report-Msgid-Bugs-To: https://gcc.gnu.org/bugs/\n";
"POT-Creation-Date: 2024-07-25 16:23+\n"
-"PO-Revision-Date: 2024-08-02 12:22-0400\n"
-"Last-Translator: Boyuan Yang <073p...@gmail.com>\n"
+"PO-Revision-Date: 2024-08-27 16:17+0800\n"
+"Last-Translator: Zhanhaoxiang Zhang \n"
"Language-Team: Chinese (simplified) \n"
"Language: zh_CN\n"
"MIME-Version: 1.0\n"
@@ -44,7 +45,7 @@ msgstr ""
"Content-Transfer-Encoding: 8bit\n"
"Plural-Forms: nplurals=1; plural=0;\n"
"X-Bugs: Report translation errors to the Language-Team address.\n"
-"X-Generator: Poedit 3.4.4\n"
+"X-Generator: Poedit 3.4.2\n"
#: cif-code.def:39
msgid "function not considered for inlining"
@@ -8005,46 +8006,39 @@ msgid "Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1,
SSE4.2, AVX, AVX2 and AVX512
msgstr "支持 MMX、SSE、SSE2、SSE3、SSSE3、SSE4.1、SSE4.2、AVX、AVX2、AVX512F 和 AVX512VBMI
内建函数及代码生成。"
#: config/i386/i386.opt:778
-#, fuzzy, no-c-format
-#| msgid "Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and
AVX512F and AVX512IFMA built-in functions and code generation."
+#, no-c-format
msgid "Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F
and AVX5124FMAPS built-in functions and code generation."
-msgstr "支持 MMX、SSE、SSE2、SSE3、SSSE3、SSE4.1、SSE4.2、AVX、AVX2、AVX512F 和 AVX512IFMA
内建函数及代码生成。"
+msgstr "支持 MMX、SSE、SSE2、SSE3、SSSE3、SSE4.1、SSE4.2、AVX、AVX2、AVX512F 和
AVX5124FMAPS 内建函数及代码生成。"
#: config/i386/i386.opt:782
-#, fuzzy, no-c-format
-#| msgid "Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and
AVX512F and AVX512VBMI built-in functions and code generation."
+#, no-c-format
msgid "Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F
and AVX5124VNNIW built-in functions and code generation."
-msgstr "支持 MMX、SSE、SSE2、SSE3、SSSE3、SSE4.1、SSE4.2、AVX、AVX2、AVX512F 和 AVX512VBMI
内建函数及代码生成。"
+msgstr "支持 MMX、SSE、SSE2、SSE3、SSSE3、SSE4.1、SSE4.2、AVX、AVX2、AVX512F 和
AVX5124VNNIW 内建函数及代码生成。"
#: config/i386/i386.opt:786
-#, fuzzy, no-c-format
-#| msgid "Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and
AVX512F and AVX512DQ built-in functions and code generation."
+#, no-c-format
msgid "Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F
and AVX512VPOPCNTDQ built-in functions and code generation."
-msgstr "支持 MMX、SSE、SSE2、SSE3、SSSE3、SSE4.1、SSE4.2、AVX、AVX2、AVX512F 和 AVX512DQ
内建函数及代码生成。"
+msgstr "支持 MMX、SSE、SSE2、SSE3、SSSE3、SSE4.1、SSE4.2、AVX、AVX2、AVX512F 和
AVX512VPOPCNTDQ 内建函数及代码生成。"
#: config/i386/i386.opt:790
-#, fuzzy, no-c-format
-#| msgid "Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and
AVX512F and AVX512VBMI built-in functions and code generation."
+#, no-c-format
msgid "Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F
and AVX512VBMI2 built-in functions and code generation."
-msgstr "支持 MMX、SSE、SSE2、SSE3、SSSE3、SSE4.1、SSE4.2、AVX、AVX2、AVX512F 和 AVX512VBMI
内建函数及代码生成。"
+msgstr "支持 MMX、SSE、SSE2、SSE3、SSSE3、SSE4.1、SSE4.2、AVX、AVX2、AVX512F 和
AVX512VBMI2 内建函数及代码生成。"
#: config/i386/i386.opt:794
-#, fuzzy, no-c-format
-#| msgid "Support BMI built-in functions and code generation."
+#, no-c-format
msgid "Support AVX512VNNI built-in functions and code generation."
-msgstr "支持 BMI 内建函数及代码生成"
+msgstr "支持 AVX512VNNI 内建函数及代码生成。"
#: config/i386/i386.opt:798
-#, fuzzy, no-c-format
-#| msgid "Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and
AVX512F and AVX512IFMA built-in functions and code generation."
+#, no-c-format
msgid "Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F
and AVX512BITALG built-in functions and code generation."
-msgstr "支持 MMX、SSE、SSE2、SSE3、SSSE3、SSE4.1、SSE4.2、AVX、AVX2、AVX512F 和 AVX512IFMA
内建函数及代码生成。"
+msgstr "支持 MMX、SSE、SSE2、SSE3、SSSE3、SSE4.1、SSE4.2、AVX、AVX2、AVX512F 和
AVX512BITALG 内建函数及代码生成。"
#: config/i386/i386.opt:802
-#, fuzzy, no-c-format
-#| msgid "Support BMI built-in functions and code generation."
+#, no-c-format
msgid "Support AVX512VP2INTERSECT built-in functions and code generation."
-msgstr "支持 BMI 内建函数及代码生成"
+msgstr "支持 AVX512VP2INTERSECT 内建函数及代码生成。"
#: config/i386/i386.opt:806
[gcc r14-10614] Update gcc zh_CN.po
https://gcc.gnu.org/g:90b123253dd28e03cbec03e8c71cafc366a3f602
commit r14-10614-g90b123253dd28e03cbec03e8c71cafc366a3f602
Author: Joseph Myers
Date: Tue Aug 27 21:21:58 2024 +
Update gcc zh_CN.po
* zh_CN.po: Update.
Diff:
---
gcc/po/zh_CN.po | 351 +++-
1 file changed, 146 insertions(+), 205 deletions(-)
diff --git a/gcc/po/zh_CN.po b/gcc/po/zh_CN.po
index 133c36a8ec47..b80a0281e24d 100644
--- a/gcc/po/zh_CN.po
+++ b/gcc/po/zh_CN.po
@@ -6,6 +6,7 @@
# Mingye Wang (Arthur2e5) , 2015, 2016.
# Boyuan Yang <073p...@gmail.com>, 2019, 2023, 2024.
# Zixing Zhou , 2023.
+# Zhanhaoxiang Zhang , 2024.
#
# Fellow translatiors:
# Many of the fuzzy strings are caused by an addition of a period (".")
@@ -35,8 +36,8 @@ msgstr ""
"Project-Id-Version: gcc 14.2.0\n"
"Report-Msgid-Bugs-To: https://gcc.gnu.org/bugs/\n";
"POT-Creation-Date: 2024-07-25 16:23+\n"
-"PO-Revision-Date: 2024-08-02 12:22-0400\n"
-"Last-Translator: Boyuan Yang <073p...@gmail.com>\n"
+"PO-Revision-Date: 2024-08-27 16:17+0800\n"
+"Last-Translator: Zhanhaoxiang Zhang \n"
"Language-Team: Chinese (simplified) \n"
"Language: zh_CN\n"
"MIME-Version: 1.0\n"
@@ -44,7 +45,7 @@ msgstr ""
"Content-Transfer-Encoding: 8bit\n"
"Plural-Forms: nplurals=1; plural=0;\n"
"X-Bugs: Report translation errors to the Language-Team address.\n"
-"X-Generator: Poedit 3.4.4\n"
+"X-Generator: Poedit 3.4.2\n"
#: cif-code.def:39
msgid "function not considered for inlining"
@@ -8005,46 +8006,39 @@ msgid "Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1,
SSE4.2, AVX, AVX2 and AVX512
msgstr "支持 MMX、SSE、SSE2、SSE3、SSSE3、SSE4.1、SSE4.2、AVX、AVX2、AVX512F 和 AVX512VBMI
内建函数及代码生成。"
#: config/i386/i386.opt:778
-#, fuzzy, no-c-format
-#| msgid "Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and
AVX512F and AVX512IFMA built-in functions and code generation."
+#, no-c-format
msgid "Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F
and AVX5124FMAPS built-in functions and code generation."
-msgstr "支持 MMX、SSE、SSE2、SSE3、SSSE3、SSE4.1、SSE4.2、AVX、AVX2、AVX512F 和 AVX512IFMA
内建函数及代码生成。"
+msgstr "支持 MMX、SSE、SSE2、SSE3、SSSE3、SSE4.1、SSE4.2、AVX、AVX2、AVX512F 和
AVX5124FMAPS 内建函数及代码生成。"
#: config/i386/i386.opt:782
-#, fuzzy, no-c-format
-#| msgid "Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and
AVX512F and AVX512VBMI built-in functions and code generation."
+#, no-c-format
msgid "Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F
and AVX5124VNNIW built-in functions and code generation."
-msgstr "支持 MMX、SSE、SSE2、SSE3、SSSE3、SSE4.1、SSE4.2、AVX、AVX2、AVX512F 和 AVX512VBMI
内建函数及代码生成。"
+msgstr "支持 MMX、SSE、SSE2、SSE3、SSSE3、SSE4.1、SSE4.2、AVX、AVX2、AVX512F 和
AVX5124VNNIW 内建函数及代码生成。"
#: config/i386/i386.opt:786
-#, fuzzy, no-c-format
-#| msgid "Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and
AVX512F and AVX512DQ built-in functions and code generation."
+#, no-c-format
msgid "Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F
and AVX512VPOPCNTDQ built-in functions and code generation."
-msgstr "支持 MMX、SSE、SSE2、SSE3、SSSE3、SSE4.1、SSE4.2、AVX、AVX2、AVX512F 和 AVX512DQ
内建函数及代码生成。"
+msgstr "支持 MMX、SSE、SSE2、SSE3、SSSE3、SSE4.1、SSE4.2、AVX、AVX2、AVX512F 和
AVX512VPOPCNTDQ 内建函数及代码生成。"
#: config/i386/i386.opt:790
-#, fuzzy, no-c-format
-#| msgid "Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and
AVX512F and AVX512VBMI built-in functions and code generation."
+#, no-c-format
msgid "Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F
and AVX512VBMI2 built-in functions and code generation."
-msgstr "支持 MMX、SSE、SSE2、SSE3、SSSE3、SSE4.1、SSE4.2、AVX、AVX2、AVX512F 和 AVX512VBMI
内建函数及代码生成。"
+msgstr "支持 MMX、SSE、SSE2、SSE3、SSSE3、SSE4.1、SSE4.2、AVX、AVX2、AVX512F 和
AVX512VBMI2 内建函数及代码生成。"
#: config/i386/i386.opt:794
-#, fuzzy, no-c-format
-#| msgid "Support BMI built-in functions and code generation."
+#, no-c-format
msgid "Support AVX512VNNI built-in functions and code generation."
-msgstr "支持 BMI 内建函数及代码生成"
+msgstr "支持 AVX512VNNI 内建函数及代码生成。"
#: config/i386/i386.opt:798
-#, fuzzy, no-c-format
-#| msgid "Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and
AVX512F and AVX512IFMA built-in functions and code generation."
+#, no-c-format
msgid "Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F
and AVX512BITALG built-in functions and code generation."
-msgstr "支持 MMX、SSE、SSE2、SSE3、SSSE3、SSE4.1、SSE4.2、AVX、AVX2、AVX512F 和 AVX512IFMA
内建函数及代码生成。"
+msgstr "支持 MMX、SSE、SSE2、SSE3、SSSE3、SSE4.1、SSE4.2、AVX、AVX2、AVX512F 和
AVX512BITALG 内建函数及代码生成。"
#: config/i386/i386.opt:802
-#, fuzzy, no-c-format
-#| msgid "Support BMI built-in functions and code generation."
+#, no-c-format
msgid "Support AVX512VP2INTERSECT built-in functions and code generation."
-msgstr "支持 BMI 内建函数及代码生成"
+msgstr "支持 AVX512VP2INTERSECT 内建函数及代码生成。"
#: config/i386/i386.opt:80
[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Remove testcase XFAIL
https://gcc.gnu.org/g:fa76531046b57a540ccf88a67e7636353dfe43e0
commit fa76531046b57a540ccf88a67e7636353dfe43e0
Author: Edwin Lu
Date: Mon Aug 19 13:10:15 2024 -0700
RISC-V: Remove testcase XFAIL
The testcase has been modified to include the -fwrapv flag which now
causes the test to pass. Remove the xfail exception
gcc/testsuite/ChangeLog:
* gcc.dg/signbit-5.c: Remove riscv xfail exception
Signed-off-by: Edwin Lu
(cherry picked from commit 3676816caa510de226b357be1c68cf798da63576)
Diff:
---
gcc/testsuite/gcc.dg/signbit-5.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/gcc/testsuite/gcc.dg/signbit-5.c b/gcc/testsuite/gcc.dg/signbit-5.c
index 2bca640f930b..e65c8910c825 100644
--- a/gcc/testsuite/gcc.dg/signbit-5.c
+++ b/gcc/testsuite/gcc.dg/signbit-5.c
@@ -4,7 +4,6 @@
/* This test does not work when the truth type does not match vector type. */
/* { dg-additional-options "-march=armv8-a" { target aarch64_sve } } */
/* { dg-xfail-run-if "truth type does not match vector type" { amdgcn-*-* } }
*/
-/* { dg-xfail-run-if "truth type does not match vector type" { riscv_v } } */
#include
[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Fix one typo in .SAT_TRUNC test func name [NFC]
https://gcc.gnu.org/g:f93c8ea4f748225910a1cb25e95adc081e0d7be7
commit f93c8ea4f748225910a1cb25e95adc081e0d7be7
Author: Pan Li
Date: Tue Aug 20 21:08:23 2024 +0800
RISC-V: Fix one typo in .SAT_TRUNC test func name [NFC]
Fix one typo `sat_truc` to `sat_trunc`, as well as `SAT_TRUC` to
`SAT_TRUNC`.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/sat_arith.h: Fix SAT_TRUNC typo.
* gcc.target/riscv/sat_u_trunc-1.c: Ditto.
* gcc.target/riscv/sat_u_trunc-13.c: Ditto.
* gcc.target/riscv/sat_u_trunc-14.c: Ditto.
* gcc.target/riscv/sat_u_trunc-15.c: Ditto.
* gcc.target/riscv/sat_u_trunc-2.c: Ditto.
* gcc.target/riscv/sat_u_trunc-3.c: Ditto.
* gcc.target/riscv/sat_u_trunc-4.c: Ditto.
* gcc.target/riscv/sat_u_trunc-5.c: Ditto.
* gcc.target/riscv/sat_u_trunc-6.c: Ditto.
* gcc.target/riscv/sat_u_trunc-7.c: Ditto.
* gcc.target/riscv/sat_u_trunc-8.c: Ditto.
* gcc.target/riscv/sat_u_trunc-9.c: Ditto.
* gcc.target/riscv/sat_u_trunc-run-1.c: Ditto.
* gcc.target/riscv/sat_u_trunc-run-13.c: Ditto.
* gcc.target/riscv/sat_u_trunc-run-14.c: Ditto.
* gcc.target/riscv/sat_u_trunc-run-15.c: Ditto.
* gcc.target/riscv/sat_u_trunc-run-2.c: Ditto.
* gcc.target/riscv/sat_u_trunc-run-3.c: Ditto.
* gcc.target/riscv/sat_u_trunc-run-4.c: Ditto.
* gcc.target/riscv/sat_u_trunc-run-5.c: Ditto.
* gcc.target/riscv/sat_u_trunc-run-6.c: Ditto.
* gcc.target/riscv/sat_u_trunc-run-7.c: Ditto.
* gcc.target/riscv/sat_u_trunc-run-8.c: Ditto.
* gcc.target/riscv/sat_u_trunc-run-9.c: Ditto.
Signed-off-by: Pan Li
(cherry picked from commit 1b72e07696a062e628c35e4bd25926c11ac18297)
Diff:
---
gcc/testsuite/gcc.target/riscv/sat_arith.h | 30 +++---
gcc/testsuite/gcc.target/riscv/sat_u_trunc-1.c | 4 +--
gcc/testsuite/gcc.target/riscv/sat_u_trunc-13.c| 4 +--
gcc/testsuite/gcc.target/riscv/sat_u_trunc-14.c| 4 +--
gcc/testsuite/gcc.target/riscv/sat_u_trunc-15.c| 4 +--
gcc/testsuite/gcc.target/riscv/sat_u_trunc-2.c | 4 +--
gcc/testsuite/gcc.target/riscv/sat_u_trunc-3.c | 4 +--
gcc/testsuite/gcc.target/riscv/sat_u_trunc-4.c | 4 +--
gcc/testsuite/gcc.target/riscv/sat_u_trunc-5.c | 4 +--
gcc/testsuite/gcc.target/riscv/sat_u_trunc-6.c | 4 +--
gcc/testsuite/gcc.target/riscv/sat_u_trunc-7.c | 4 +--
gcc/testsuite/gcc.target/riscv/sat_u_trunc-8.c | 4 +--
gcc/testsuite/gcc.target/riscv/sat_u_trunc-9.c | 4 +--
gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-1.c | 4 +--
.../gcc.target/riscv/sat_u_trunc-run-13.c | 4 +--
.../gcc.target/riscv/sat_u_trunc-run-14.c | 4 +--
.../gcc.target/riscv/sat_u_trunc-run-15.c | 4 +--
gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-2.c | 4 +--
gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-3.c | 4 +--
gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-4.c | 4 +--
gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-5.c | 4 +--
gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-6.c | 4 +--
gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-7.c | 4 +--
gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-8.c | 4 +--
gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-9.c | 4 +--
25 files changed, 63 insertions(+), 63 deletions(-)
diff --git a/gcc/testsuite/gcc.target/riscv/sat_arith.h
b/gcc/testsuite/gcc.target/riscv/sat_arith.h
index cf055410fd1f..91853b60f592 100644
--- a/gcc/testsuite/gcc.target/riscv/sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/sat_arith.h
@@ -218,40 +218,40 @@ sat_u_sub_##T##_fmt_12 (T x, T y) \
/* Saturation Truncate (unsigned and signed)
*/
/**/
-#define DEF_SAT_U_TRUC_FMT_1(NT, WT) \
+#define DEF_SAT_U_TRUNC_FMT_1(NT, WT)\
NT __attribute__((noinline)) \
-sat_u_truc_##WT##_to_##NT##_fmt_1 (WT x) \
+sat_u_trunc_##WT##_to_##NT##_fmt_1 (WT x) \
{\
bool overflow = x > (WT)(NT)(-1); \
return ((NT)x) | (NT)-overflow;\
}
-#define DEF_SAT_U_TRUC_FMT_1_WRAP(NT, WT) DEF_SAT_U_TRUC_FMT_1(NT, WT)
+#define DEF_SAT_U_TRUNC_FMT_1_WRAP(NT, WT) DEF_SAT_U_TRUNC_FMT_1(NT, WT)
-#define DEF_SAT_U_TRUC_FMT_2(NT, WT) \
+#define DEF_SAT_U_TRUNC_FMT_2(NT, WT)\
NT __attribute__((noinline)) \
-sat_u_truc_##WT##_to_##NT##_fmt_2 (WT x) \
+sat_u_trunc_##WT##_to_##NT##_fmt_2 (WT x) \
{\
WT max = (WT)(NT)-1; \
return x > max ? (NT) max : (NT)x; \
}
-#define DEF_SAT_U_TRUC_FMT_2_WRAP(NT, WT) DEF_SAT_U_TRUC_FMT_2(NT, WT)
+#define DEF_SAT_U_TRUNC_FMT_2_WRAP(NT, WT) DEF_SAT_U_TRUNC_FMT_2(NT, WT)
[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [PR rtl-optimization/116437] Fix RTL checking issue in ext-dce
https://gcc.gnu.org/g:9660ade008244720fc3653865c7beaae09d6e3da
commit 9660ade008244720fc3653865c7beaae09d6e3da
Author: Jeff Law
Date: Wed Aug 21 16:52:23 2024 -0600
[PR rtl-optimization/116437] Fix RTL checking issue in ext-dce
Another RTL checking failure in ext-dce. An easy one to fix this time.
When we optimize an extension we have to go back and cleanup with
SUBREG_PROMOTED state. So we record the destination register into a bitmap
as
we make changes, then later do a single pass over the IL fixing any
associated
subreg expressions.
The optimization is changing the SET_SRC and largely ignores the
destination.
The LHS could be a REG, SUBREG, or ZERO_EXTRACT. If the LHS is a SUBREG or
ZERO_EXTRACT we can just strip them.
Bootstrapped and ran the testsuite with an RTL checking compiler and
verified
no ext-dce RTL checking failures tripped. Also bootstrapped and regression
tested x86_64 in the usual way.
Pushing to the trunk.
PR rtl-optimization/116437
gcc/
* ext-dce.cc (ext_dce_try_optimize_insn): Handle SUBREG and
ZERO_EXTRACT destinations.
(cherry picked from commit cdc9cd4afe8949276a0c50215eb7f23e2086044f)
Diff:
---
gcc/ext-dce.cc | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/gcc/ext-dce.cc b/gcc/ext-dce.cc
index 60ae09e45dbf..0122b3a0d15b 100644
--- a/gcc/ext-dce.cc
+++ b/gcc/ext-dce.cc
@@ -422,8 +422,13 @@ ext_dce_try_optimize_insn (rtx_insn *insn, rtx set)
{
int ok = validate_change (insn, &SET_SRC (set), new_pattern, false);
+ rtx x = SET_DEST (set);
+ while (SUBREG_P (x) || GET_CODE (x) == ZERO_EXTRACT)
+ x = XEXP (x, 0);
+
+ gcc_assert (REG_P (x));
if (ok)
- bitmap_set_bit (changed_pseudos, REGNO (SET_DEST (set)));
+ bitmap_set_bit (changed_pseudos, REGNO (x));
if (dump_file)
{
[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for unsigned vector .SAT_TRUNC form 2
https://gcc.gnu.org/g:c8eec5d1eb5db3ed9ec0a781fe94867f69d3
commit c8eec5d1eb5db3ed9ec0a781fe94867f69d3
Author: Pan Li
Date: Wed Aug 21 17:43:12 2024 +0800
RISC-V: Add testcases for unsigned vector .SAT_TRUNC form 2
This patch would like to add test cases for the unsigned vector
.SAT_TRUNC form 2. Aka:
Form 2:
#define DEF_VEC_SAT_U_TRUNC_FMT_2(NT, WT) \
void __attribute__((noinline))\
vec_sat_u_trunc_##NT##_##WT##_fmt_2 (NT *out, WT *in, unsigned limit) \
{ \
unsigned i; \
for (i = 0; i < limit; i++) \
{ \
WT max = (WT)(NT)-1;\
out[i] = in[i] > max ? (NT)max : (NT)in[i]; \
} \
}
DEF_VEC_SAT_U_TRUNC_FMT_2 (uint32_t, uint64_t)
The below test is passed for this patch.
* The rv64gcv regression test.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/vec_sat_arith.h: Add test helper
macros.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-10.c: New test.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-11.c: New test.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-12.c: New test.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-7.c: New test.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-8.c: New test.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-9.c: New test.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-run-10.c: New
test.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-run-11.c: New
test.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-run-12.c: New
test.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-run-7.c: New
test.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-run-8.c: New
test.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-run-9.c: New
test.
Signed-off-by: Pan Li
(cherry picked from commit 1e99e1ba79964f47f8850871d025209dfab73693)
Diff:
---
.../riscv/rvv/autovec/unop/vec_sat_u_trunc-10.c| 19 ++
.../riscv/rvv/autovec/unop/vec_sat_u_trunc-11.c| 21
.../riscv/rvv/autovec/unop/vec_sat_u_trunc-12.c| 19 ++
.../riscv/rvv/autovec/unop/vec_sat_u_trunc-7.c | 19 ++
.../riscv/rvv/autovec/unop/vec_sat_u_trunc-8.c | 21
.../riscv/rvv/autovec/unop/vec_sat_u_trunc-9.c | 23 ++
.../rvv/autovec/unop/vec_sat_u_trunc-run-10.c | 16 +++
.../rvv/autovec/unop/vec_sat_u_trunc-run-11.c | 16 +++
.../rvv/autovec/unop/vec_sat_u_trunc-run-12.c | 16 +++
.../riscv/rvv/autovec/unop/vec_sat_u_trunc-run-7.c | 16 +++
.../riscv/rvv/autovec/unop/vec_sat_u_trunc-run-8.c | 16 +++
.../riscv/rvv/autovec/unop/vec_sat_u_trunc-run-9.c | 16 +++
.../gcc.target/riscv/rvv/autovec/vec_sat_arith.h | 18 +
13 files changed, 236 insertions(+)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-10.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-10.c
new file mode 100644
index ..f5084e503ebd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-10.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-skip-if "" { *-*-* } { "-flto" } } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "../vec_sat_arith.h"
+
+/*
+** vec_sat_u_trunc_uint16_t_uint32_t_fmt_2:
+** ...
+** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*mf2,\s*ta,\s*ma
+** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
+** vse16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** ...
+*/
+DEF_VEC_SAT_U_TRUNC_FMT_2 (uint16_t, uint32_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-11.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-11.c
new file mode 100644
index ..e2ab880a1aca
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-11.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+
[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for unsigned vector .SAT_TRUNC form 3
https://gcc.gnu.org/g:327021ed2a74817b2c9986e87358d84a0d921b00
commit 327021ed2a74817b2c9986e87358d84a0d921b00
Author: Pan Li
Date: Wed Aug 21 17:57:47 2024 +0800
RISC-V: Add testcases for unsigned vector .SAT_TRUNC form 3
This patch would like to add test cases for the unsigned vector
.SAT_TRUNC form 3. Aka:
Form 3:
#define DEF_VEC_SAT_U_TRUNC_FMT_3(NT, WT) \
void __attribute__((noinline))\
vec_sat_u_trunc_##NT##_##WT##_fmt_3 (NT *out, WT *in, unsigned limit) \
{ \
unsigned i; \
for (i = 0; i < limit; i++) \
{ \
WT max = (WT)(NT)-1;\
out[i] = in[i] <= max ? (NT)in[i] : (NT)max;\
} \
}
DEF_VEC_SAT_U_TRUNC_FMT_3 (uint32_t, uint64_t)
The below test is passed for this patch.
* The rv64gcv regression test.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/vec_sat_arith.h: Add test helper
macros.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-13.c: New test.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-14.c: New test.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-15.c: New test.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-16.c: New test.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-17.c: New test.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-18.c: New test.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-run-13.c: New
test.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-run-14.c: New
test.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-run-15.c: New
test.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-run-16.c: New
test.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-run-17.c: New
test.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-run-18.c: New
test.
Signed-off-by: Pan Li
(cherry picked from commit 91f213908c0443b0249490b03b8046509f6e7e9d)
Diff:
---
.../riscv/rvv/autovec/unop/vec_sat_u_trunc-13.c| 19 ++
.../riscv/rvv/autovec/unop/vec_sat_u_trunc-14.c| 21
.../riscv/rvv/autovec/unop/vec_sat_u_trunc-15.c| 23 ++
.../riscv/rvv/autovec/unop/vec_sat_u_trunc-16.c| 19 ++
.../riscv/rvv/autovec/unop/vec_sat_u_trunc-17.c| 21
.../riscv/rvv/autovec/unop/vec_sat_u_trunc-18.c| 19 ++
.../rvv/autovec/unop/vec_sat_u_trunc-run-13.c | 16 +++
.../rvv/autovec/unop/vec_sat_u_trunc-run-14.c | 16 +++
.../rvv/autovec/unop/vec_sat_u_trunc-run-15.c | 16 +++
.../rvv/autovec/unop/vec_sat_u_trunc-run-16.c | 16 +++
.../rvv/autovec/unop/vec_sat_u_trunc-run-17.c | 16 +++
.../rvv/autovec/unop/vec_sat_u_trunc-run-18.c | 16 +++
.../gcc.target/riscv/rvv/autovec/vec_sat_arith.h | 18 +
13 files changed, 236 insertions(+)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-13.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-13.c
new file mode 100644
index ..49bdbdc36062
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-13.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-skip-if "" { *-*-* } { "-flto" } } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "../vec_sat_arith.h"
+
+/*
+** vec_sat_u_trunc_uint8_t_uint16_t_fmt_3:
+** ...
+** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*mf2,\s*ta,\s*ma
+** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
+** vse8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** ...
+*/
+DEF_VEC_SAT_U_TRUNC_FMT_3 (uint8_t, uint16_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-14.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-14.c
new file mode 100644
index ..3ff696edcfee
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-14.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [PR rtl-optimization/116420] Fix interesting block bitmap DF dataflow
https://gcc.gnu.org/g:9843c449d1ff93e0dc402f08eae0362302989049
commit 9843c449d1ff93e0dc402f08eae0362302989049
Author: Jeff Law
Date: Thu Aug 22 12:48:49 2024 -0600
[PR rtl-optimization/116420] Fix interesting block bitmap DF dataflow
The DF framework provides us a way to run dataflow problems on sub-graphs.
Naturally a bitmap of interesting blocks is passed into those routines.
At a
confluence point, the DF framework will not mark a block for re-processing
if
it's not in that set of interesting blocks.
When ext-dce sets up that set of interesting blocks it's using the wrong
counter. ie, it's using n_basic_blocks rather than last_basic_block. If
there
are holes in the block indices, some number of blocks won't get marked as
interesting.
In this case the block needing reprocessing has an index higher than
n_basic_blocks. It never gets reprocessed and the newly found live chunks
don't propagate further up the CFG -- ultimately resulting in a pseudo
appearing to have only the low 8 bits live, when in fact the low 32 bits are
actually live.
Fixed in the obvious way, by using last_basic_block instead.
Bootstrapped and regression tested on x86_64. Pushing to the trunk.
PR rtl-optimization/116420
gcc/
* ext-dce.cc (ext_dce_init): Fix loop iteration when setting up the
interesting block for DF to analyze.
gcc/testsuite
* gcc.dg/torture/pr116420.c: New test.
(cherry picked from commit c9377734b798d8d311dfd3a5618dc49407703b93)
Diff:
---
gcc/ext-dce.cc | 2 +-
gcc/testsuite/gcc.dg/torture/pr116420.c | 17 +
2 files changed, 18 insertions(+), 1 deletion(-)
diff --git a/gcc/ext-dce.cc b/gcc/ext-dce.cc
index 0122b3a0d15b..fbe9719a8d5b 100644
--- a/gcc/ext-dce.cc
+++ b/gcc/ext-dce.cc
@@ -988,7 +988,7 @@ ext_dce_init (void)
all_blocks = BITMAP_ALLOC (NULL);
changed_pseudos = BITMAP_ALLOC (NULL);
- for (int i = 0; i < n_basic_blocks_for_fn (cfun); i++)
+ for (int i = 0; i < last_basic_block_for_fn (cfun); i++)
if (i != ENTRY_BLOCK && i != EXIT_BLOCK)
bitmap_set_bit (all_blocks, i);
diff --git a/gcc/testsuite/gcc.dg/torture/pr116420.c
b/gcc/testsuite/gcc.dg/torture/pr116420.c
new file mode 100644
index ..9a784f594291
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/torture/pr116420.c
@@ -0,0 +1,17 @@
+/* { dg-do run } */
+/* { dg-additional-options "-fno-forward-propagate -fno-tree-ch" } */
+int a, d, e;
+char b = -1, c, f;
+int main() {
+ int g;
+ for (; d < 1; d++) {
+g = b;
+for (; c; c = g)
+ ;
+ }
+ f = g;
+ for (; e < 1; e++)
+if (g >= a)
+ __builtin_abort();
+ return 0;
+}
[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Fix vector cfi notes for stack-clash protection
https://gcc.gnu.org/g:204928bdf68a333ff8ca232397fb6a29b91bbc6a
commit 204928bdf68a333ff8ca232397fb6a29b91bbc6a
Author: Raphael Moreira Zinsly
Date: Wed Aug 21 18:08:54 2024 -0300
RISC-V: Fix vector cfi notes for stack-clash protection
The stack-clash code is generating wrong cfi directives in
riscv_v_adjust_scalable_frame because REG_CFA_DEF_CFA has a different
encoding than REG_FRAME_RELATED_EXPR, this patch fixes the offset sign
in prologue and starts using REG_CFA_DEF_CFA in the epilogue.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_v_adjust_scalable_frame): Add
epilogue code for stack-clash and fix prologue cfi note.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/stack-check-cfa-3.c: Fix the expected output.
(cherry picked from commit a025081991cca1734fb642e6609772cfce8be4d1)
Diff:
---
gcc/config/riscv/riscv.cc | 18 --
gcc/testsuite/gcc.target/riscv/stack-check-cfa-3.c | 3 ++-
2 files changed, 18 insertions(+), 3 deletions(-)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index e2a1737694a1..d7f8a2174225 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -7974,8 +7974,22 @@ riscv_v_adjust_scalable_frame (rtx target, poly_int64
offset, bool epilogue)
/* If doing stack clash protection then we use a loop to allocate and probe
the stack. */
- if (flag_stack_clash_protection && !epilogue)
+ if (flag_stack_clash_protection)
{
+ if (epilogue)
+ {
+ insn = emit_insn (gen_add3_insn (target, target, adjust_size));
+
+ if (!frame_pointer_needed)
+ {
+ add_reg_note (insn, REG_CFA_DEF_CFA,
+ plus_constant (Pmode, stack_pointer_rtx, -offset));
+ RTX_FRAME_RELATED_P (insn) = 1;
+ }
+
+ return;
+ }
+
HOST_WIDE_INT min_probe_threshold
= (1 << param_stack_clash_protection_guard_size) -
STACK_CLASH_CALLER_GUARD;
@@ -8008,7 +8022,7 @@ riscv_v_adjust_scalable_frame (rtx target, poly_int64
offset, bool epilogue)
if (!frame_pointer_needed)
{
add_reg_note (insn, REG_CFA_DEF_CFA,
- plus_constant (Pmode, stack_pointer_rtx, -offset));
+ plus_constant (Pmode, stack_pointer_rtx, offset));
RTX_FRAME_RELATED_P (insn) = 1;
}
diff --git a/gcc/testsuite/gcc.target/riscv/stack-check-cfa-3.c
b/gcc/testsuite/gcc.target/riscv/stack-check-cfa-3.c
index e45f7bb7df51..225dfae661d2 100644
--- a/gcc/testsuite/gcc.target/riscv/stack-check-cfa-3.c
+++ b/gcc/testsuite/gcc.target/riscv/stack-check-cfa-3.c
@@ -10,4 +10,5 @@
/* { dg-final { scan-assembler-times {mv\tt3,sp} 1 } } */
/* { dg-final { scan-assembler-times {\.cfi_def_cfa [0-9]+, 0} 1 } } */
-/* { dg-final { scan-assembler-times {\.cfi_escape
0xf,0xa,0x72,0,0x92,0xa2,0x38,0,0x9,0xec,0x1e,0x22} 1 } } */
+/* { dg-final { scan-assembler-times {\.cfi_escape
0xf,0x9,0x72,0,0x92,0xa2,0x38,0,0x3a,0x1e,0x22} 1 } } */
+/* { dg-final { scan-assembler-times {\.cfi_escape
0xf,0xa,0x72,0,0x92,0xa2,0x38,0,0x9,0xf6,0x1e,0x22} 1 } } */
[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Expand vec abs without masking.
https://gcc.gnu.org/g:57cc189f5f5b50711fd37ee08308157fec0033f9
commit 57cc189f5f5b50711fd37ee08308157fec0033f9
Author: Robin Dapp
Date: Fri Aug 9 15:05:39 2024 +0200
RISC-V: Expand vec abs without masking.
Standard abs synthesis during expand is max (a, -a). This
expansion has the advantage of avoiding masking and is thus potentially
faster than the a < 0 ? -a : a synthesis.
gcc/ChangeLog:
* config/riscv/autovec.md (abs2): Expand via max (a, -a).
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/unop/abs-rv32gcv.c: Adjust test
expectation.
* gcc.target/riscv/rvv/autovec/unop/abs-rv64gcv.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls/abs-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_unary-1.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_unary-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_unary-3.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_unary-4.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_unary-5.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_unary-6.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_unary-7.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_unary-8.c: Ditto.
(cherry picked from commit c22d57cdc52d990eb7d353fa82c67882bc824d40)
Diff:
---
gcc/config/riscv/autovec.md| 26 +++---
.../riscv/rvv/autovec/cond/cond_unary-1.c | 6 +++--
.../riscv/rvv/autovec/cond/cond_unary-2.c | 6 +++--
.../riscv/rvv/autovec/cond/cond_unary-3.c | 6 +++--
.../riscv/rvv/autovec/cond/cond_unary-4.c | 6 +++--
.../riscv/rvv/autovec/cond/cond_unary-5.c | 6 +++--
.../riscv/rvv/autovec/cond/cond_unary-6.c | 6 +++--
.../riscv/rvv/autovec/cond/cond_unary-7.c | 6 +++--
.../riscv/rvv/autovec/cond/cond_unary-8.c | 6 +++--
.../riscv/rvv/autovec/unop/abs-rv32gcv.c | 6 ++---
.../riscv/rvv/autovec/unop/abs-rv64gcv.c | 6 ++---
.../gcc.target/riscv/rvv/autovec/vls/abs-2.c | 2 +-
12 files changed, 47 insertions(+), 41 deletions(-)
diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index decfe2bf8cc8..4decaedbd826 100644
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -1073,29 +1073,19 @@
[(set_attr "type" "vialu")])
;;
---
-;; - [INT] ABS expansion to vmslt and vneg.
+;; - [INT] ABS expansion to vneg and vmax.
;;
---
-(define_insn_and_split "abs2"
+(define_expand "abs2"
[(set (match_operand:V_VLSI 0 "register_operand")
- (abs:V_VLSI
- (match_operand:V_VLSI 1 "register_operand")))]
- "TARGET_VECTOR && can_create_pseudo_p ()"
- "#"
- "&& 1"
- [(const_int 0)]
+(smax:V_VLSI
+ (match_dup 0)
+ (neg:V_VLSI
+ (match_operand:V_VLSI 1 "register_operand"]
+ "TARGET_VECTOR"
{
- rtx zero = gen_const_vec_duplicate (mode, GEN_INT (0));
- machine_mode mask_mode = riscv_vector::get_mask_mode (mode);
- rtx mask = gen_reg_rtx (mask_mode);
- riscv_vector::expand_vec_cmp (mask, LT, operands[1], zero);
-
- rtx ops[] = {operands[0], mask, operands[1], operands[1]};
- riscv_vector::emit_vlmax_insn (code_for_pred (NEG, mode),
- riscv_vector::UNARY_OP_TAMU, ops);
DONE;
-}
-[(set_attr "type" "vector")])
+})
;;
---
;; [FP] Unary operations
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-1.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-1.c
index 2233c6eeecb9..4866b221ca4a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-1.c
@@ -36,8 +36,10 @@
TEST_ALL (DEF_LOOP)
-/* NOTE: int abs operator is converted to vmslt + vneg.v */
-/* { dg-final { scan-assembler-times {\tvneg\.v\tv[0-9]+,v[0-9]+,v0\.t} 8 } }
*/
+/* NOTE: int abs operator is converted to vneg.v + vmax.vv */
+/* { dg-final { scan-assembler-times {\tvneg\.v\tv[0-9]+,v[0-9]+} 8 } } */
+/* { dg-final { scan-assembler-times {\tvmax\.vv\tv[0-9]+,v[0-9]+,v[0-9]+} 4 }
} */
+/* { dg-final { scan-assembler-times {\tvneg\.v\tv[0-9]+,v[0-9]+,v0\.t} 4 } }
*/
/* { dg-final { scan-assembler-times {\tvnot\.v\tv[0-9]+,v[0-9]+,v0\.t} 4 } }
*/
/* { dg-final { scan-assembler-times {\tvfabs\.v\tv[0-9]+,v[0-9]+,v0\.t} 3 } }
*/
/* { dg-final { scan-assembler-times {\tvfneg\.v\tv[0-9]+,v[0-9]+,v0\.t} 3 } }
*/
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-2.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-2.c
index 4886bff67d86..651df9f86461 100644
--- a/gcc/testsui
[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Use encoded nelts when calling repeating_sequence_p
https://gcc.gnu.org/g:3ee78b3342cbe83e3498fd0b355e57ff9a30966d
commit 3ee78b3342cbe83e3498fd0b355e57ff9a30966d
Author: Patrick O'Neill
Date: Mon Aug 19 12:19:33 2024 -0700
RISC-V: Use encoded nelts when calling repeating_sequence_p
repeating_sequence_p operates directly on the encoded pattern and does
not derive elements using the .elt() accessor. Passing in the length of
the unencoded vector can cause an out-of-bounds read of the encoded
pattern.
gcc/ChangeLog:
* config/riscv/riscv-v.cc
(rvv_builder::can_duplicate_repeating_sequence_p):
Use encoded_nelts when calling repeating_sequence_p.
(rvv_builder::is_repeating_sequence): Ditto.
(rvv_builder::repeating_sequence_use_merge_profitable_p): Ditto.
Signed-off-by: Patrick O'Neill
(cherry picked from commit 5dce17e17469161f413e1a5b723dca0e94be3fb6)
Diff:
---
gcc/config/riscv/riscv-v.cc | 10 +++---
1 file changed, 3 insertions(+), 7 deletions(-)
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 0db5c7591eff..c89603669e3a 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -502,9 +502,7 @@ rvv_builder::can_duplicate_repeating_sequence_p ()
|| GET_MODE_SIZE (m_new_inner_mode) > UNITS_PER_WORD
|| !get_vector_mode (m_new_inner_mode, new_size).exists (&m_new_mode))
return false;
- if (full_nelts ().is_constant ())
-return repeating_sequence_p (0, full_nelts ().to_constant (), npatterns
());
- return nelts_per_pattern () == 1;
+ return repeating_sequence_p (0, encoded_nelts (), npatterns ());
}
/* Return true if the vector is a simple sequence with one pattern and all
@@ -514,9 +512,7 @@ rvv_builder::is_repeating_sequence ()
{
if (npatterns () > 1)
return false;
- if (full_nelts ().is_constant ())
-return repeating_sequence_p (0, full_nelts ().to_constant (), 1);
- return nelts_per_pattern () == 1;
+ return repeating_sequence_p (0, encoded_nelts (), 1);
}
/* Return true if it is a repeating sequence that using
@@ -564,7 +560,7 @@ rvv_builder::repeating_sequence_use_merge_profitable_p ()
unsigned int nelts = full_nelts ().to_constant ();
- if (!repeating_sequence_p (0, nelts, npatterns ()))
+ if (!repeating_sequence_p (0, encoded_nelts (), npatterns ()))
return false;
unsigned int merge_cost = 1;
[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] Turn off late-combine for a few risc-v specific tests
https://gcc.gnu.org/g:ee54c9f75f443283801cc11eaec3d58ad85170b0
commit ee54c9f75f443283801cc11eaec3d58ad85170b0
Author: Jeff Law
Date: Sun Aug 25 07:06:45 2024 -0600
Turn off late-combine for a few risc-v specific tests
Just minor testsuite adjustments -- several of the shorten-memref tests are
slightly twiddled by the late-combine pass:
> Running /home/jlaw/test/gcc/gcc/testsuite/gcc.target/riscv/riscv.exp ...
> FAIL: gcc.target/riscv/shorten-memrefs-2.c -Os scan-assembler
store1a:\n(\t?\\.[^\n]*\n)*\taddi
> XPASS: gcc.target/riscv/shorten-memrefs-3.c -Os scan-assembler-not
load2a:\n.*addi[ \t]*[at][0-9],[at][0-9],[0-9]*
> FAIL: gcc.target/riscv/shorten-memrefs-5.c -Os scan-assembler
store1a:\n(\t?\\.[^\n]*\n)*\taddi
> FAIL: gcc.target/riscv/shorten-memrefs-8.c -Os scan-assembler
store:\n(\t?\\.[^\n]*\n)*\taddi\ta[0-7],a[0-7],1
This patch just turns off the late-combine pass for those tests. Locally
I'd
adjusted all the shorten-memref patches, but a quick re-rest shows that
only 4
tests seem affected right now.
Anyway, pushing to the trunk to slightly clean up our test results.
gcc/testsuite
* gcc.target/riscv/shorten-memrefs-2.c: Turn off late-combine.
* gcc.target/riscv/shorten-memrefs-3.c: Likewise.
* gcc.target/riscv/shorten-memrefs-5.c: Likewise.
* gcc.target/riscv/shorten-memrefs-8.c: Likewise.
(cherry picked from commit ab9c4bb54e817948f1a55edfb0f1f0481e4046df)
Diff:
---
gcc/testsuite/gcc.target/riscv/shorten-memrefs-2.c | 2 +-
gcc/testsuite/gcc.target/riscv/shorten-memrefs-3.c | 2 +-
gcc/testsuite/gcc.target/riscv/shorten-memrefs-5.c | 2 +-
gcc/testsuite/gcc.target/riscv/shorten-memrefs-8.c | 2 +-
4 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/gcc/testsuite/gcc.target/riscv/shorten-memrefs-2.c
b/gcc/testsuite/gcc.target/riscv/shorten-memrefs-2.c
index a9ddb797d06a..29ece481c261 100644
--- a/gcc/testsuite/gcc.target/riscv/shorten-memrefs-2.c
+++ b/gcc/testsuite/gcc.target/riscv/shorten-memrefs-2.c
@@ -1,4 +1,4 @@
-/* { dg-options "-march=rv32imc -mabi=ilp32" } */
+/* { dg-options "-march=rv32imc -mabi=ilp32 -fno-late-combine-instructions" }
*/
/* { dg-skip-if "" { *-*-* } { "*" } { "-Os" } } */
/* shorten_memrefs should rewrite these load/stores into a compressible
diff --git a/gcc/testsuite/gcc.target/riscv/shorten-memrefs-3.c
b/gcc/testsuite/gcc.target/riscv/shorten-memrefs-3.c
index 3d561124b818..273a68c373a1 100644
--- a/gcc/testsuite/gcc.target/riscv/shorten-memrefs-3.c
+++ b/gcc/testsuite/gcc.target/riscv/shorten-memrefs-3.c
@@ -1,4 +1,4 @@
-/* { dg-options "-march=rv32imc -mabi=ilp32" } */
+/* { dg-options "-march=rv32imc -mabi=ilp32 -fno-late-combine-instructions" }
*/
/* { dg-skip-if "" { *-*-* } { "*" } { "-Os" } } */
/* These loads cannot be compressed because only one compressed reg is
diff --git a/gcc/testsuite/gcc.target/riscv/shorten-memrefs-5.c
b/gcc/testsuite/gcc.target/riscv/shorten-memrefs-5.c
index 11e858ed6da0..f554105f91f1 100644
--- a/gcc/testsuite/gcc.target/riscv/shorten-memrefs-5.c
+++ b/gcc/testsuite/gcc.target/riscv/shorten-memrefs-5.c
@@ -1,4 +1,4 @@
-/* { dg-options "-march=rv64imc -mabi=lp64" } */
+/* { dg-options "-march=rv64imc -mabi=lp64 -fno-late-combine-instructions" } */
/* { dg-skip-if "" { *-*-* } { "*" } { "-Os" } } */
/* shorten_memrefs should rewrite these load/stores into a compressible
diff --git a/gcc/testsuite/gcc.target/riscv/shorten-memrefs-8.c
b/gcc/testsuite/gcc.target/riscv/shorten-memrefs-8.c
index 3ff6956b33e4..d533355409ca 100644
--- a/gcc/testsuite/gcc.target/riscv/shorten-memrefs-8.c
+++ b/gcc/testsuite/gcc.target/riscv/shorten-memrefs-8.c
@@ -1,4 +1,4 @@
-/* { dg-options "-march=rv32imc -mabi=ilp32" } */
+/* { dg-options "-march=rv32imc -mabi=ilp32 -fno-late-combine-instructions" }
*/
/* { dg-skip-if "" { *-*-* } { "*" } { "-Os" } } */
/* shorten_memrefs should use a correct base address*/
[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] optabs-query: Use opt_machine_mode for smallest_int_mode_for_size [PR115495].
https://gcc.gnu.org/g:0e8e9e768db6649899038cf4a0de2ad604cb4535
commit 0e8e9e768db6649899038cf4a0de2ad604cb4535
Author: Robin Dapp
Date: Tue Aug 20 14:02:09 2024 +0200
optabs-query: Use opt_machine_mode for smallest_int_mode_for_size
[PR115495].
In get_best_extraction_insn we use smallest_int_mode_for_size with
struct_bits as size argument. PR115495 has struct_bits = 256 and we
don't have a mode for that. This patch makes smallest_mode_for_size
and smallest_int_mode_for_size return opt modes so we can just skip
over the loop when there is no mode.
PR middle-end/115495
gcc/ChangeLog:
* cfgexpand.cc (expand_debug_expr): Require mode.
* combine.cc (make_extraction): Ditto.
* config/aarch64/aarch64.cc (aarch64_expand_cpymem): Ditto.
(aarch64_expand_setmem): Ditto.
* config/arc/arc.cc (arc_expand_cpymem): Ditto.
* config/arm/arm.cc (arm_expand_divmod_libfunc): Ditto.
* config/i386/i386.cc (ix86_get_mask_mode): Ditto.
* config/rs6000/predicates.md: Ditto.
* config/rs6000/rs6000.cc (vspltis_constant): Ditto.
* config/s390/s390.cc (s390_expand_insv): Ditto.
* config/sparc/sparc.cc (assign_int_registers): Ditto.
* coverage.cc (get_gcov_type): Ditto.
(get_gcov_unsigned_t): Ditto.
* dse.cc (find_shift_sequence): Ditto.
* expmed.cc (store_integral_bit_field): Ditto.
* expr.cc (convert_mode_scalar): Ditto.
(op_by_pieces_d::smallest_fixed_size_mode_for_size): Ditto.
(emit_block_move_via_oriented_loop): Ditto.
(copy_blkmode_to_reg): Ditto.
(store_field): Ditto.
* internal-fn.cc (expand_arith_overflow): Ditto.
* machmode.h (HAVE_MACHINE_MODES): Ditto.
(smallest_mode_for_size): Use opt_machine_mode.
(smallest_int_mode_for_size): Use opt_scalar_int_mode.
* optabs-query.cc (get_best_extraction_insn): Require mode.
* optabs.cc (expand_twoval_binop_libfunc): Ditto.
* stor-layout.cc (smallest_mode_for_size): Return
opt_machine_mode.
(layout_type): Require mode.
(initialize_sizetypes): Ditto.
* tree-ssa-loop-manip.cc (canonicalize_loop_ivs): Ditto.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/pr115495.c: New test.
gcc/ada/ChangeLog:
* gcc-interface/utils2.cc (fast_modulo_reduction): Require mode.
(nonbinary_modular_operation): Ditto.
(cherry picked from commit 96fe95bac67c7303dc811c04f5e99cc959a7182a)
Diff:
---
gcc/cfgexpand.cc | 2 +-
gcc/combine.cc| 2 +-
gcc/config/aarch64/aarch64.cc | 5 +++--
gcc/config/arc/arc.cc | 2 +-
gcc/config/arm/arm.cc | 2 +-
gcc/config/i386/i386.cc | 4 ++--
gcc/config/rs6000/predicates.md | 2 +-
gcc/config/rs6000/rs6000.cc | 2 +-
gcc/config/s390/s390.cc | 2 +-
gcc/config/sparc/sparc.cc | 2 +-
gcc/coverage.cc | 5 +++--
gcc/dse.cc| 3 ++-
gcc/expmed.cc | 3 ++-
gcc/expr.cc | 17 +
gcc/internal-fn.cc| 4 ++--
gcc/machmode.h| 10 +-
gcc/optabs-query.cc | 1 +
gcc/optabs.cc | 3 ++-
gcc/stor-layout.cc| 16 +---
gcc/testsuite/gcc.target/riscv/rvv/autovec/pr115495.c | 9 +
gcc/tree-ssa-loop-manip.cc| 2 +-
21 files changed, 58 insertions(+), 40 deletions(-)
diff --git a/gcc/cfgexpand.cc b/gcc/cfgexpand.cc
index eef565eddb5d..486145e9eaee 100644
--- a/gcc/cfgexpand.cc
+++ b/gcc/cfgexpand.cc
@@ -4840,7 +4840,7 @@ expand_debug_expr (tree exp)
if (maybe_gt (bitsize, MAX_BITSIZE_MODE_ANY_INT))
return NULL;
/* Bitfield. */
- mode1 = smallest_int_mode_for_size (bitsize);
+ mode1 = smallest_int_mode_for_size (bitsize).require ();
}
poly_int64 bytepos = bits_to_bytes_round_down (bitpos);
if (maybe_ne (bytepos, 0))
diff --git a/gcc/combine.cc b/gcc/combine.cc
index 60afe043578d..0304237d404a 100644
--- a/gcc/combine.cc
+++ b/gcc/combine.cc
@@ -7788,7 +7788,7 @@ make_extraction (machine_mode mode, rtx inner,
HOST_WIDE_INT pos,
{
/* Be care
[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [committed] Fix assembly scan for RISC-V VLS tests
https://gcc.gnu.org/g:d95274bbd89eca93a94670d4688fa4b829cd
commit d95274bbd89eca93a94670d4688fa4b829cd
Author: Jeff Law
Date: Sun Aug 25 07:16:50 2024 -0600
[committed] Fix assembly scan for RISC-V VLS tests
Surya's IRA patch from June slightly improves the code we generate for the
vls/calling-conventions tests on RISC-V. Specifically it removes an
unnecessary move from the instruction stream. This (of course) broke those
tests:
> Running /home/jlaw/test/gcc/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp ...
> FAIL: gcc.target/riscv/rvv/autovec/vls/calling-convention-1.c -O3
-ftree-vectorize -mrvv-vector-bits=scalable scan-assembler-times
mv\\s+s0,a0\\s+call\\s+memset\\s+mv\\s+a0,s0 3
> FAIL: gcc.target/riscv/rvv/autovec/vls/calling-convention-2.c -O3
-ftree-vectorize -mrvv-vector-bits=scalable scan-assembler-times
mv\\s+s0,a0\\s+call\\s+memset\\s+mv\\s+a0,s0 3
> FAIL: gcc.target/riscv/rvv/autovec/vls/calling-convention-3.c -O3
-ftree-vectorize -mrvv-vector-bits=scalable scan-assembler-times
mv\\s+s0,a0\\s+call\\s+memset\\s+mv\\s+a0,s0 3
> FAIL: gcc.target/riscv/rvv/autovec/vls/calling-convention-4.c -O3
-ftree-vectorize -mrvv-vector-bits=scalable scan-assembler-times
mv\\s+s0,a0\\s+call\\s+memset\\s+mv\\s+a0,s0 3
> FAIL: gcc.target/riscv/rvv/autovec/vls/calling-convention-5.c -O3
-ftree-vectorize -mrvv-vector-bits=scalable scan-assembler-times
mv\\s+s0,a0\\s+call\\s+memset\\s+mv\\s+a0,s0 3
> FAIL: gcc.target/riscv/rvv/autovec/vls/calling-convention-6.c -O3
-ftree-vectorize -mrvv-vector-bits=scalable scan-assembler-times
mv\\s+s0,a0\\s+call\\s+memset\\s+mv\\s+a0,s0 3
> FAIL: gcc.target/riscv/rvv/autovec/vls/calling-convention-7.c -O3
-ftree-vectorize -mrvv-vector-bits=scalable scan-assembler-times
mv\\s+s0,a0\\s+call\\s+memset\\s+mv\\s+a0,s0 3
This patch does the natural adjustment of those tests by dropping the moves
from the scan.
gcc/testsuite
* gcc.target/riscv/rvv/autovec/vls/calling-convention-1.c: Update
expected output.
* gcc.target/riscv/rvv/autovec/vls/calling-convention-2.c: Likewise.
* gcc.target/riscv/rvv/autovec/vls/calling-convention-3.c: Likewise.
* gcc.target/riscv/rvv/autovec/vls/calling-convention-4.c: Likewise.
* gcc.target/riscv/rvv/autovec/vls/calling-convention-5.c: Likewise.
* gcc.target/riscv/rvv/autovec/vls/calling-convention-6.c: Likewise.
* gcc.target/riscv/rvv/autovec/vls/calling-convention-7.c: Likewise.
(cherry picked from commit 4c3485897d3e28ecfbe911f21f83fa047ee8b54b)
Diff:
---
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-1.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-2.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-3.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-4.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-5.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-6.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-7.c | 2 +-
7 files changed, 7 insertions(+), 7 deletions(-)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-1.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-1.c
index 60c838eb21d2..82039f5ac4e3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-1.c
@@ -145,7 +145,7 @@ DEF_RET1_ARG9 (v4096qi)
// RET1_ARG0 tests
/* { dg-final { scan-assembler-times {li\s+a[0-1],\s*0} 9 } } */
-/* { dg-final { scan-assembler-times {mv\s+s0,a0\s+call\s+memset\s+mv\s+a0,s0}
3 } } */
+/* { dg-final { scan-assembler-times {call\s+memset} 3 } } */
// v1qi tests: return value (lbu) and function prologue (sb)
// 1 lbu per test, argnum sb's when args > 1
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-2.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-2.c
index b9922a64332d..af52b7039865 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-2.c
@@ -135,7 +135,7 @@ DEF_RET1_ARG9 (v2048hi)
// RET1_ARG0 tests
/* { dg-final { scan-assembler-times {li\s+a[0-1],\s*0} 8 } } */
-/* { dg-final { scan-assembler-times {mv\s+s0,a0\s+call\s+memset\s+mv\s+a0,s0}
3 } } */
+/* { dg-final { scan-assembler-times {call\s+memset} 3 } } */
// v1hi tests: return value (lhu) and function prologue (sh)
// 1 lhu per test, argnum sh's when args > 1
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-3.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-3.c
index 989d45de254d..01c5a1a1ba28 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv
[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] Disable late-combine in another RISC-V test
https://gcc.gnu.org/g:12fb83c7f94ad3a2b73a940f045ab6ec70f87d8b
commit 12fb83c7f94ad3a2b73a940f045ab6ec70f87d8b
Author: Jeff Law
Date: Sun Aug 25 07:24:56 2024 -0600
Disable late-combine in another RISC-V test
Another test where the output was slightly twiddled by late-combine in which
simply disabling late-combine seems to be the best option.
> Running /home/jlaw/test/gcc/gcc/testsuite/gcc.target/riscv/riscv.exp ...
> FAIL: gcc.target/riscv/cm_mv_rv32.c -Os check-function-bodies sum
Pushing to the trunk.
gcc/testsuite
* gcc.target/riscv/cm_mv_rv32.c: Disable late-combine.
(cherry picked from commit 70edccf88738ec204036e498a4a50c46e5e4f0c0)
Diff:
---
gcc/testsuite/gcc.target/riscv/cm_mv_rv32.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/testsuite/gcc.target/riscv/cm_mv_rv32.c
b/gcc/testsuite/gcc.target/riscv/cm_mv_rv32.c
index 2c1b3f9cabf9..e2369fc4d2d3 100644
--- a/gcc/testsuite/gcc.target/riscv/cm_mv_rv32.c
+++ b/gcc/testsuite/gcc.target/riscv/cm_mv_rv32.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options " -Os -march=rv32i_zca_zcmp -mabi=ilp32 " } */
+/* { dg-options " -Os -march=rv32i_zca_zcmp -mabi=ilp32
-fno-late-combine-instructions " } */
/* { dg-skip-if "" { *-*-* } {"-O0" "-O1" "-O2" "-Og" "-O3" "-Oz" "-flto"} } */
/* { dg-final { check-function-bodies "**" "" } } */
[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [PATCH] Re-add calling emit_clobber in lower-subreg.cc's resolve_simple_move.
https://gcc.gnu.org/g:76ed0a7caacfc924d5ba67fc1eabc6446a8d8207
commit 76ed0a7caacfc924d5ba67fc1eabc6446a8d8207
Author: Xianmiao Qu
Date: Sun Aug 25 11:22:21 2024 -0600
[PATCH] Re-add calling emit_clobber in lower-subreg.cc's
resolve_simple_move.
The previous patch:
https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=d8a6945c6ea22efa4d5e42fe1922d2b27953c8cd
aimed to eliminate redundant MOV instructions by removing calling
emit_clobber in lower-subreg.cc's resolve_simple_move.
First, I found that another patch address this issue:
https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=bdf2737cda53a83332db1a1a021653447b05a7e7
and even without removing calling emit_clobber,
the instruction generation is still as expected.
Second, removing the CLOBBER expression will have side effects.
When there is no CLOBBER expression and only SUBREG assignments exist,
according to the logic of the 'df_lr_bb_local_compute' function,
the register will be added to the basic block LR IN set.
This will cause the register's lifetime to span the entire function,
resulting in increased register pressure. Taking the newly added test case
'gcc/testsuite/gcc.target/riscv/pr43644.c' as an example,
removing the CLOBBER expression will lead to spill in some registers.
gcc/:
* lower-subreg.cc (resolve_simple_move): Re-add calling emit_clobber
immediately before moving a multi-word register by parts.
gcc/testsuite/:
* gcc.target/riscv/pr43644.c: New test case.
(cherry picked from commit dba20679f1bf138ab5e61ad131b887db42083174)
Diff:
---
gcc/lower-subreg.cc | 3 +++
gcc/testsuite/gcc.target/riscv/pr43644.c | 16
2 files changed, 19 insertions(+)
diff --git a/gcc/lower-subreg.cc b/gcc/lower-subreg.cc
index d1da94336e75..89608934c997 100644
--- a/gcc/lower-subreg.cc
+++ b/gcc/lower-subreg.cc
@@ -1101,6 +1101,9 @@ resolve_simple_move (rtx set, rtx_insn *insn)
{
unsigned int i;
+ if (REG_P (dest) && !HARD_REGISTER_NUM_P (REGNO (dest)))
+ emit_clobber (dest);
+
for (i = 0; i < words; ++i)
{
rtx t = simplify_gen_subreg_concatn (word_mode, dest,
diff --git a/gcc/testsuite/gcc.target/riscv/pr43644.c
b/gcc/testsuite/gcc.target/riscv/pr43644.c
new file mode 100644
index ..3b7ddb9e0ad5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/pr43644.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32imac -mabi=ilp32 -O2 -fdump-rtl-ira" } */
+
+double foo (double a)
+{
+ if (a < 0.0)
+return a + 1.0;
+ else if (a > 16.0)
+return a - 3.0;
+ else if (a < 300.0)
+return a - 30.0;
+ else
+return a;
+}
+
+/* { dg-final { scan-rtl-dump-not "memory is more profitable" "ira" } } */
[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Fix double mode under RV32 not utilize vf
https://gcc.gnu.org/g:93ef25c6f7366df397a985df569d12def715ee22 commit 93ef25c6f7366df397a985df569d12def715ee22 Author: demin.han Date: Sun Aug 25 15:53:58 2024 -0600 RISC-V: Fix double mode under RV32 not utilize vf Currently, some binops of vector vs double scalar under RV32 can't translated to vf but vfmv+vxx.vv. The cause is that vec_duplicate is also expanded to broadcast for double mode under RV32. last-combine can't process expanded broadcast. gcc/ChangeLog: * config/riscv/vector.md: Add !FLOAT_MODE_P constraint. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv-nofm.c: Fix test. * gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv-nofm.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv-nofm.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv-nofm.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv32gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fadd-1.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fadd-2.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fadd-3.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fadd-4.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-1.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-3.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-4.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-5.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-6.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fmax-1.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fmax-2.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fmax-3.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fmax-4.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fmin-1.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fmin-2.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fmin-3.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fmin-4.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-1.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-3.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-4.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-5.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-6.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fmul-1.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fmul-2.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fmul-3.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fmul-4.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fmul-5.c: Ditto. (cherry picked from commit 7f65c38ac1b18773d55c08d6ba920a798462b871) Diff: --- gcc/config/riscv/vector.md| 3 ++- .../gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv-nofm.c| 4 ++-- .../gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv-nofm.c| 4 ++-- .../gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv-nofm.c| 4 ++-- .../gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv-nofm.c| 6 +++--- .../gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv32gcv.c | 8 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-1.c | 4 ++-- gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-2.c | 4 ++-- gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-3.c | 4 ++-- gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-4.c | 4 ++-- gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-1.c | 4 ++-- gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-3.c | 4 ++-- gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-4.c | 4 ++-- gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-5.c | 4 ++-- gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-6.c | 4 ++-- gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-1.c | 4 ++-- gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-2.c | 4 ++-- gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-3.c | 4 ++-- gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-4.c | 4 ++-- gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-1.c | 4 ++-- gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-2.c | 4 ++-- gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-3.c | 4 ++-- gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-4.c | 4 ++-- gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-1.c | 4 ++-- gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-3.c | 4 ++-- gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_
[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for unsigned scalar .SAT_TRUNC form 4
https://gcc.gnu.org/g:a2432f0bc14acc8bfed1f72728f2b8bf9b2f9744
commit a2432f0bc14acc8bfed1f72728f2b8bf9b2f9744
Author: Pan Li
Date: Sun Aug 25 11:02:10 2024 +0800
RISC-V: Add testcases for unsigned scalar .SAT_TRUNC form 4
This patch would like to add test cases for the unsigned scalar quad and
oct .SAT_TRUNC form 4. Aka:
Form 4:
#define DEF_SAT_U_TRUNC_FMT_4(NT, WT) \
NT __attribute__((noinline)) \
sat_u_trunc_##WT##_to_##NT##_fmt_4 (WT x) \
{ \
bool not_overflow = x <= (WT)(NT)(-1); \
return ((NT)x) | (NT)((NT)not_overflow - 1); \
}
The below test is passed for this patch.
* The rv64gcv regression test.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/sat_arith.h: Add test helper macros.
* gcc.target/riscv/sat_u_trunc-19.c: New test.
* gcc.target/riscv/sat_u_trunc-20.c: New test.
* gcc.target/riscv/sat_u_trunc-21.c: New test.
* gcc.target/riscv/sat_u_trunc-22.c: New test.
* gcc.target/riscv/sat_u_trunc-23.c: New test.
* gcc.target/riscv/sat_u_trunc-24.c: New test.
* gcc.target/riscv/sat_u_trunc-run-19.c: New test.
* gcc.target/riscv/sat_u_trunc-run-20.c: New test.
* gcc.target/riscv/sat_u_trunc-run-21.c: New test.
* gcc.target/riscv/sat_u_trunc-run-22.c: New test.
* gcc.target/riscv/sat_u_trunc-run-23.c: New test.
* gcc.target/riscv/sat_u_trunc-run-24.c: New test.
Signed-off-by: Pan Li
(cherry picked from commit 5ab1e238aa23d1773429f8f28abfb6ed16f655f6)
Diff:
---
gcc/testsuite/gcc.target/riscv/sat_arith.h | 12
gcc/testsuite/gcc.target/riscv/sat_u_trunc-19.c | 17 +
gcc/testsuite/gcc.target/riscv/sat_u_trunc-20.c | 20
gcc/testsuite/gcc.target/riscv/sat_u_trunc-21.c | 19 +++
gcc/testsuite/gcc.target/riscv/sat_u_trunc-22.c | 17 +
gcc/testsuite/gcc.target/riscv/sat_u_trunc-23.c | 17 +
gcc/testsuite/gcc.target/riscv/sat_u_trunc-24.c | 20
gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-19.c | 16
gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-20.c | 16
gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-21.c | 16
gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-22.c | 16
gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-23.c | 16
gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-24.c | 16
13 files changed, 218 insertions(+)
diff --git a/gcc/testsuite/gcc.target/riscv/sat_arith.h
b/gcc/testsuite/gcc.target/riscv/sat_arith.h
index 91853b60f592..229e1f0a5cda 100644
--- a/gcc/testsuite/gcc.target/riscv/sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/sat_arith.h
@@ -245,6 +245,15 @@ sat_u_trunc_##WT##_to_##NT##_fmt_3 (WT x) \
}
#define DEF_SAT_U_TRUNC_FMT_3_WRAP(NT, WT) DEF_SAT_U_TRUNC_FMT_3(NT, WT)
+#define DEF_SAT_U_TRUNC_FMT_4(NT, WT) \
+NT __attribute__((noinline)) \
+sat_u_trunc_##WT##_to_##NT##_fmt_4 (WT x) \
+{ \
+ bool not_overflow = x <= (WT)(NT)(-1); \
+ return ((NT)x) | (NT)((NT)not_overflow - 1); \
+}
+#define DEF_SAT_U_TRUNC_FMT_4_WRAP(NT, WT) DEF_SAT_U_TRUNC_FMT_4(NT, WT)
+
#define RUN_SAT_U_TRUNC_FMT_1(NT, WT, x) sat_u_trunc_##WT##_to_##NT##_fmt_1 (x)
#define RUN_SAT_U_TRUNC_FMT_1_WRAP(NT, WT, x) RUN_SAT_U_TRUNC_FMT_1(NT, WT, x)
@@ -254,4 +263,7 @@ sat_u_trunc_##WT##_to_##NT##_fmt_3 (WT x) \
#define RUN_SAT_U_TRUNC_FMT_3(NT, WT, x) sat_u_trunc_##WT##_to_##NT##_fmt_3 (x)
#define RUN_SAT_U_TRUNC_FMT_3_WRAP(NT, WT, x) RUN_SAT_U_TRUNC_FMT_3(NT, WT, x)
+#define RUN_SAT_U_TRUNC_FMT_4(NT, WT, x) sat_u_trunc_##WT##_to_##NT##_fmt_4 (x)
+#define RUN_SAT_U_TRUNC_FMT_4_WRAP(NT, WT, x) RUN_SAT_U_TRUNC_FMT_4(NT, WT, x)
+
#endif
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_trunc-19.c
b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-19.c
new file mode 100644
index ..e61faffbbc6c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-19.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details
-fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_trunc_uint16_t_to_uint8_t_fmt_4:
+** sltiu\s+[atx][0-9]+,\s*a0,\s*255
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*0xff
+** ret
+*/
+DEF_SAT_U_TRUNC_FMT_4(uint8_t, uint16_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_trunc-20.c
b/gcc/testsuite/gc
[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for unsigned vector .SAT_TRUNC form 4
https://gcc.gnu.org/g:db1772fa10aecab5344bac705c60baaba71fd11c
commit db1772fa10aecab5344bac705c60baaba71fd11c
Author: Pan Li
Date: Sun Aug 25 14:15:40 2024 +0800
RISC-V: Add testcases for unsigned vector .SAT_TRUNC form 4
This patch would like to add test cases for the unsigned vector
.SAT_TRUNC form 4. Aka:
Form 4:
#define DEF_VEC_SAT_U_TRUNC_FMT_4(NT, WT) \
void __attribute__((noinline))\
vec_sat_u_trunc_##NT##_##WT##_fmt_4 (NT *out, WT *in, unsigned limit) \
{ \
unsigned i; \
for (i = 0; i < limit; i++) \
{ \
bool not_overflow = in[i] <= (WT)(NT)(-1); \
out[i] = ((NT)in[i]) | (NT)((NT)not_overflow - 1); \
} \
}
DEF_VEC_SAT_U_TRUNC_FMT_4 (uint32_t, uint64_t)
The below test is passed for this patch.
* The rv64gcv regression test.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/vec_sat_arith.h: Add test helper
macros.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-19.c: New test.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-20.c: New test.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-21.c: New test.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-22.c: New test.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-23.c: New test.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-24.c: New test.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-run-19.c: New
test.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-run-20.c: New
test.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-run-21.c: New
test.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-run-22.c: New
test.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-run-23.c: New
test.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-run-24.c: New
test.
Signed-off-by: Pan Li
(cherry picked from commit 8f2f7aabcef8d801af002a26885a97ccf9889099)
Diff:
---
.../riscv/rvv/autovec/unop/vec_sat_u_trunc-19.c| 19 ++
.../riscv/rvv/autovec/unop/vec_sat_u_trunc-20.c| 21
.../riscv/rvv/autovec/unop/vec_sat_u_trunc-21.c| 23 ++
.../riscv/rvv/autovec/unop/vec_sat_u_trunc-22.c| 19 ++
.../riscv/rvv/autovec/unop/vec_sat_u_trunc-23.c| 21
.../riscv/rvv/autovec/unop/vec_sat_u_trunc-24.c| 19 ++
.../rvv/autovec/unop/vec_sat_u_trunc-run-19.c | 16 +++
.../rvv/autovec/unop/vec_sat_u_trunc-run-20.c | 16 +++
.../rvv/autovec/unop/vec_sat_u_trunc-run-21.c | 16 +++
.../rvv/autovec/unop/vec_sat_u_trunc-run-22.c | 16 +++
.../rvv/autovec/unop/vec_sat_u_trunc-run-23.c | 16 +++
.../rvv/autovec/unop/vec_sat_u_trunc-run-24.c | 16 +++
.../gcc.target/riscv/rvv/autovec/vec_sat_arith.h | 18 +
13 files changed, 236 insertions(+)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-19.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-19.c
new file mode 100644
index ..a80cefe46ab0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-19.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-skip-if "" { *-*-* } { "-flto" } } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "../vec_sat_arith.h"
+
+/*
+** vec_sat_u_trunc_uint8_t_uint16_t_fmt_4:
+** ...
+** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*mf2,\s*ta,\s*ma
+** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
+** vse8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** ...
+*/
+DEF_VEC_SAT_U_TRUNC_FMT_4 (uint8_t, uint16_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-20.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-20.c
new file mode 100644
index ..9a4d261d052d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-20.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Support IMM for operand 0 of ussub pattern
https://gcc.gnu.org/g:ffb7ed746bee04052b62b2d4601bc9992acb40bc
commit ffb7ed746bee04052b62b2d4601bc9992acb40bc
Author: Pan Li
Date: Sat Aug 3 07:02:57 2024 +
RISC-V: Support IMM for operand 0 of ussub pattern
This patch would like to allow IMM for the operand 0 of ussub pattern.
Aka .SAT_SUB(1023, y) as the below example.
Form 1:
#define DEF_SAT_U_SUB_IMM_FMT_1(T, IMM) \
T __attribute__((noinline)) \
sat_u_sub_imm##IMM##_##T##_fmt_1 (T y) \
{ \
return (T)IMM >= y ? (T)IMM - y : 0; \
}
DEF_SAT_U_SUB_IMM_FMT_1(uint64_t, 1023)
Before this patch:
10 │ sat_u_sub_imm82_uint64_t_fmt_1:
11 │ li a5,82
12 │ bgtua0,a5,.L3
13 │ sub a0,a5,a0
14 │ ret
15 │ .L3:
16 │ li a0,0
17 │ ret
After this patch:
10 │ sat_u_sub_imm82_uint64_t_fmt_1:
11 │ li a5,82
12 │ sltua4,a5,a0
13 │ addia4,a4,-1
14 │ sub a0,a5,a0
15 │ and a0,a4,a0
16 │ ret
The below test suites are passed for this patch:
1. The rv64gcv fully regression test.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_gen_unsigned_xmode_reg): Add new
func impl to gen xmode rtx reg from operand rtx.
(riscv_expand_ussub): Gen xmode reg for operand 1.
* config/riscv/riscv.md: Allow const_int for operand 1.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/sat_arith.h: Add test helper macro.
* gcc.target/riscv/sat_u_sub_imm-1.c: New test.
* gcc.target/riscv/sat_u_sub_imm-1_1.c: New test.
* gcc.target/riscv/sat_u_sub_imm-1_2.c: New test.
* gcc.target/riscv/sat_u_sub_imm-2.c: New test.
* gcc.target/riscv/sat_u_sub_imm-2_1.c: New test.
* gcc.target/riscv/sat_u_sub_imm-2_2.c: New test.
* gcc.target/riscv/sat_u_sub_imm-3.c: New test.
* gcc.target/riscv/sat_u_sub_imm-3_1.c: New test.
* gcc.target/riscv/sat_u_sub_imm-3_2.c: New test.
* gcc.target/riscv/sat_u_sub_imm-4.c: New test.
* gcc.target/riscv/sat_u_sub_imm-run-1.c: New test.
* gcc.target/riscv/sat_u_sub_imm-run-2.c: New test.
* gcc.target/riscv/sat_u_sub_imm-run-3.c: New test.
* gcc.target/riscv/sat_u_sub_imm-run-4.c: New test.
Signed-off-by: Pan Li
(cherry picked from commit 17be00916e51835dcc47e30ed32fc892ee0c581d)
Diff:
---
gcc/config/riscv/riscv.cc | 46 +-
gcc/config/riscv/riscv.md | 2 +-
gcc/testsuite/gcc.target/riscv/sat_arith.h | 10
gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-1.c | 20
gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-1_1.c | 20
gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-1_2.c | 20
gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-2.c | 21
gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-2_1.c | 21
gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-2_2.c | 22 +
gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-3.c | 20
gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-3_1.c | 21
gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-3_2.c | 22 +
gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-4.c | 19
.../gcc.target/riscv/sat_u_sub_imm-run-1.c | 56 ++
.../gcc.target/riscv/sat_u_sub_imm-run-2.c | 56 ++
.../gcc.target/riscv/sat_u_sub_imm-run-3.c | 55 +
.../gcc.target/riscv/sat_u_sub_imm-run-4.c | 48 +++
17 files changed, 477 insertions(+), 2 deletions(-)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index d7f8a2174225..22a60f9ddd16 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -11907,6 +11907,50 @@ riscv_expand_usadd (rtx dest, rtx x, rtx y)
emit_move_insn (dest, gen_lowpart (mode, xmode_dest));
}
+/* Generate a REG rtx of Xmode from the given rtx and mode.
+ The rtx x can be REG (QI/HI/SI/DI) or const_int.
+ The machine_mode mode is the original mode from define pattern.
+
+ If rtx is REG, the gen_lowpart of Xmode will be returned.
+
+ If rtx is const_int, a new REG rtx will be created to hold the value of
+ const_int and then returned.
+
+ According to the gccint doc, the constants generated for modes with fewer
+ bits than in HOST_WIDE_INT must be sign extended to full width. Thus there
+ will be two cases here, take QImode as example.
+
+ For .SAT_SUB (127, y) in QImode, we have (const_int 127) and one simple
+ mov from const_int to the new REG rtx is good enough here.
+
+ For .SAT_SUB (254, y) in QImode, we have (const_int -2) after define_expand.
+ Aka 0xff
[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Move helper functions above expand_const_vector
https://gcc.gnu.org/g:9d19855517b95a0205c795becab4c67b0c9eac7e
commit 9d19855517b95a0205c795becab4c67b0c9eac7e
Author: Patrick O'Neill
Date: Mon Aug 19 12:40:14 2024 -0700
RISC-V: Move helper functions above expand_const_vector
These subroutines will be used in expand_const_vector in a future patch.
Relocate so expand_const_vector can use them.
gcc/ChangeLog:
* config/riscv/riscv-v.cc (expand_vector_init_insert_elems):
Relocate.
(expand_vector_init_trailing_same_elem): Ditto.
Signed-off-by: Patrick O'Neill
(cherry picked from commit 691f682fe24d07ff5854f1f53d81909320110c9c)
Diff:
---
gcc/config/riscv/riscv-v.cc | 132 ++--
1 file changed, 66 insertions(+), 66 deletions(-)
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index c89603669e3a..3753bd9842cf 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -1146,6 +1146,72 @@ expand_vec_series (rtx dest, rtx base, rtx step, rtx vid)
emit_move_insn (dest, result);
}
+/* Subroutine of riscv_vector_expand_vector_init.
+ Works as follows:
+ (a) Initialize TARGET by broadcasting element NELTS_REQD - 1 of BUILDER.
+ (b) Skip leading elements from BUILDER, which are the same as
+ element NELTS_REQD - 1.
+ (c) Insert earlier elements in reverse order in TARGET using vslide1down.
*/
+
+static void
+expand_vector_init_insert_elems (rtx target, const rvv_builder &builder,
+int nelts_reqd)
+{
+ machine_mode mode = GET_MODE (target);
+ rtx dup = expand_vector_broadcast (mode, builder.elt (0));
+ emit_move_insn (target, dup);
+ int ndups = builder.count_dups (0, nelts_reqd - 1, 1);
+ for (int i = ndups; i < nelts_reqd; i++)
+{
+ unsigned int unspec
+ = FLOAT_MODE_P (mode) ? UNSPEC_VFSLIDE1DOWN : UNSPEC_VSLIDE1DOWN;
+ insn_code icode = code_for_pred_slide (unspec, mode);
+ rtx ops[] = {target, target, builder.elt (i)};
+ emit_vlmax_insn (icode, BINARY_OP, ops);
+}
+}
+
+/* Subroutine of expand_vec_init to handle case
+ when all trailing elements of builder are same.
+ This works as follows:
+ (a) Use expand_insn interface to broadcast last vector element in TARGET.
+ (b) Insert remaining elements in TARGET using insr.
+
+ ??? The heuristic used is to do above if number of same trailing elements
+ is greater than leading_ndups, loosely based on
+ heuristic from mostly_zeros_p. May need fine-tuning. */
+
+static bool
+expand_vector_init_trailing_same_elem (rtx target,
+ const rtx_vector_builder &builder,
+ int nelts_reqd)
+{
+ int leading_ndups = builder.count_dups (0, nelts_reqd - 1, 1);
+ int trailing_ndups = builder.count_dups (nelts_reqd - 1, -1, -1);
+ machine_mode mode = GET_MODE (target);
+
+ if (trailing_ndups > leading_ndups)
+{
+ rtx dup = expand_vector_broadcast (mode, builder.elt (nelts_reqd - 1));
+ for (int i = nelts_reqd - trailing_ndups - 1; i >= 0; i--)
+ {
+ unsigned int unspec
+ = FLOAT_MODE_P (mode) ? UNSPEC_VFSLIDE1UP : UNSPEC_VSLIDE1UP;
+ insn_code icode = code_for_pred_slide (unspec, mode);
+ rtx tmp = gen_reg_rtx (mode);
+ rtx ops[] = {tmp, dup, builder.elt (i)};
+ emit_vlmax_insn (icode, BINARY_OP, ops);
+ /* slide1up need source and dest to be different REG. */
+ dup = tmp;
+ }
+
+ emit_move_insn (target, dup);
+ return true;
+}
+
+ return false;
+}
+
static void
expand_const_vector (rtx target, rtx src)
{
@@ -2342,31 +2408,6 @@ preferred_simd_mode (scalar_mode mode)
return word_mode;
}
-/* Subroutine of riscv_vector_expand_vector_init.
- Works as follows:
- (a) Initialize TARGET by broadcasting element NELTS_REQD - 1 of BUILDER.
- (b) Skip leading elements from BUILDER, which are the same as
- element NELTS_REQD - 1.
- (c) Insert earlier elements in reverse order in TARGET using vslide1down.
*/
-
-static void
-expand_vector_init_insert_elems (rtx target, const rvv_builder &builder,
-int nelts_reqd)
-{
- machine_mode mode = GET_MODE (target);
- rtx dup = expand_vector_broadcast (mode, builder.elt (0));
- emit_move_insn (target, dup);
- int ndups = builder.count_dups (0, nelts_reqd - 1, 1);
- for (int i = ndups; i < nelts_reqd; i++)
-{
- unsigned int unspec
- = FLOAT_MODE_P (mode) ? UNSPEC_VFSLIDE1DOWN : UNSPEC_VSLIDE1DOWN;
- insn_code icode = code_for_pred_slide (unspec, mode);
- rtx ops[] = {target, target, builder.elt (i)};
- emit_vlmax_insn (icode, BINARY_OP, ops);
-}
-}
-
/* Use merge approach to initialize the vector with repeating sequence.
v = {a, b, a, b, a, b, a, b}.
@@ -2491,47 +2532,6 @@ expand_vector_init_merge_combine_sequence (rtx target,
emit_vlmax_insn (icode, MERGE_OP, merge_
[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Support IMM for operand 1 of ussub pattern
https://gcc.gnu.org/g:a5bd5cc741a806106740fb10837dd6dacc630298
commit a5bd5cc741a806106740fb10837dd6dacc630298
Author: Pan Li
Date: Mon Aug 26 15:58:52 2024 +0800
RISC-V: Support IMM for operand 1 of ussub pattern
This patch would like to allow IMM for the operand 1 of ussub pattern.
Aka .SAT_SUB(x, 22) as the below example.
Form 2:
#define DEF_SAT_U_SUB_IMM_FMT_2(T, IMM) \
T __attribute__((noinline)) \
sat_u_sub_imm##IMM##_##T##_fmt_2 (T x) \
{ \
return x >= (T)IMM ? x - (T)IMM : 0; \
}
DEF_SAT_U_SUB_IMM_FMT_2(uint64_t, 1022)
It is almost the as support imm for operand 0 of ussub pattern, but
allow the second operand to be imm insted of the first operand.
The below test suites are passed for this patch:
1. The rv64gcv fully regression test.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_expand_ussub): Gen xmode for the
second operand, aka y in parameter.
* config/riscv/riscv.md (ussub3): Allow const_int for operand
2.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/sat_arith.h: Add test helper macros.
* gcc.target/riscv/sat_u_sub_imm-5.c: New test.
* gcc.target/riscv/sat_u_sub_imm-5_1.c: New test.
* gcc.target/riscv/sat_u_sub_imm-5_2.c: New test.
* gcc.target/riscv/sat_u_sub_imm-6.c: New test.
* gcc.target/riscv/sat_u_sub_imm-6_1.c: New test.
* gcc.target/riscv/sat_u_sub_imm-6_2.c: New test.
* gcc.target/riscv/sat_u_sub_imm-7.c: New test.
* gcc.target/riscv/sat_u_sub_imm-7_1.c: New test.
* gcc.target/riscv/sat_u_sub_imm-7_2.c: New test.
* gcc.target/riscv/sat_u_sub_imm-8.c: New test.
* gcc.target/riscv/sat_u_sub_imm-run-5.c: New test.
* gcc.target/riscv/sat_u_sub_imm-run-6.c: New test.
* gcc.target/riscv/sat_u_sub_imm-run-7.c: New test.
* gcc.target/riscv/sat_u_sub_imm-run-8.c: New test.
Signed-off-by: Pan Li
(cherry picked from commit a1062b0c07bb729cf6a1fff34929d22e5d5b633d)
Diff:
---
gcc/config/riscv/riscv.cc | 2 +-
gcc/config/riscv/riscv.md | 2 +-
gcc/testsuite/gcc.target/riscv/sat_arith.h | 9
gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-5.c | 19
gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-5_1.c | 19
gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-5_2.c | 19
gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-6.c | 20
gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-6_1.c | 21 +
gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-6_2.c | 22 +
gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-7.c | 19
gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-7_1.c | 21 +
gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-7_2.c | 22 +
gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-8.c | 18 +++
.../gcc.target/riscv/sat_u_sub_imm-run-5.c | 55 ++
.../gcc.target/riscv/sat_u_sub_imm-run-6.c | 55 ++
.../gcc.target/riscv/sat_u_sub_imm-run-7.c | 54 +
.../gcc.target/riscv/sat_u_sub_imm-run-8.c | 48 +++
17 files changed, 423 insertions(+), 2 deletions(-)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 22a60f9ddd16..76560c018bd8 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -11965,7 +11965,7 @@ riscv_expand_ussub (rtx dest, rtx x, rtx y)
{
machine_mode mode = GET_MODE (dest);
rtx xmode_x = riscv_gen_unsigned_xmode_reg (x, mode);
- rtx xmode_y = gen_lowpart (Xmode, y);
+ rtx xmode_y = riscv_gen_unsigned_xmode_reg (y, mode);
rtx xmode_lt = gen_reg_rtx (Xmode);
rtx xmode_minus = gen_reg_rtx (Xmode);
rtx xmode_dest = gen_reg_rtx (Xmode);
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index a94705a8e7cc..3289ed2155ad 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -4370,7 +4370,7 @@
(define_expand "ussub3"
[(match_operand:ANYI 0 "register_operand")
(match_operand:ANYI 1 "reg_or_int_operand")
- (match_operand:ANYI 2 "register_operand")]
+ (match_operand:ANYI 2 "reg_or_int_operand")]
""
{
riscv_expand_ussub (operands[0], operands[1], operands[2]);
diff --git a/gcc/testsuite/gcc.target/riscv/sat_arith.h
b/gcc/testsuite/gcc.target/riscv/sat_arith.h
index d3f7b5836c79..b05d973c4c6c 100644
--- a/gcc/testsuite/gcc.target/riscv/sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/sat_arith.h
@@ -208,6 +208,13 @@ sat_u_sub_imm##IMM##_##T##_fmt_1 (T y) \
return (T)IMM >= y ? (T)IMM - y : 0; \
}
+#define DEF_SAT_U_SUB_IMM_FMT_2(T, IMM) \
+T __attribute__((noinline)) \
+sat_u_sub_imm##IMM##_##T##_fmt_2 (T x) \
+{
[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Fix vid const vector expander for non-npatterns size steps
https://gcc.gnu.org/g:3d0ae86388b8c89133386e9ee2c97ac8c75bf80a
commit 3d0ae86388b8c89133386e9ee2c97ac8c75bf80a
Author: Patrick O'Neill
Date: Wed Aug 21 23:48:24 2024 -0700
RISC-V: Fix vid const vector expander for non-npatterns size steps
Prior to this patch the expander would emit vectors like:
{ 0, 0, 5, 5, 10, 10, ...}
as:
{ 0, 0, 2, 2, 4, 4, ...}
This patch sets the step size to the requested value.
gcc/ChangeLog:
* config/riscv/riscv-v.cc (expand_const_vector): Fix STEP size in
expander.
Signed-off-by: Patrick O'Neill
(cherry picked from commit c89038c7ae8bba7160ae2963647ce90171b5dd2c)
Diff:
---
gcc/config/riscv/riscv-v.cc | 48 +++--
1 file changed, 42 insertions(+), 6 deletions(-)
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 3753bd9842cf..43afddaed861 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -1378,25 +1378,61 @@ expand_const_vector (rtx target, rtx src)
/* Generate the variable-length vector following this rule:
{ a, a, a + step, a + step, a + step * 2, a + step * 2, ...}
E.g. { 0, 0, 8, 8, 16, 16, ... } */
- /* We want to create a pattern where value[ix] = floor (ix /
+
+ /* We want to create a pattern where value[idx] = floor (idx /
NPATTERNS). As NPATTERNS is always a power of two we can
-rewrite this as = ix & -NPATTERNS. */
+rewrite this as = idx & -NPATTERNS. */
/* Step 2: VID AND -NPATTERNS:
{ 0&-4, 1&-4, 2&-4, 3 &-4, 4 &-4, 5 &-4, 6 &-4, 7 &-4, ... }
*/
rtx imm
= gen_int_mode (-builder.npatterns (), builder.inner_mode ());
- rtx tmp = gen_reg_rtx (builder.mode ());
- rtx and_ops[] = {tmp, vid, imm};
+ rtx tmp1 = gen_reg_rtx (builder.mode ());
+ rtx and_ops[] = {tmp1, vid, imm};
icode = code_for_pred_scalar (AND, builder.mode ());
emit_vlmax_insn (icode, BINARY_OP, and_ops);
+
+ /* Step 3: Convert to step size 1. */
+ rtx tmp2 = gen_reg_rtx (builder.mode ());
+ /* log2 (npatterns) to get the shift amount to convert
+Eg. { 0, 0, 0, 0, 4, 4, ... }
+into { 0, 0, 0, 0, 1, 1, ... }. */
+ HOST_WIDE_INT shift_amt = exact_log2 (builder.npatterns ()) ;
+ rtx shift = gen_int_mode (shift_amt, builder.inner_mode ());
+ rtx shift_ops[] = {tmp2, tmp1, shift};
+ icode = code_for_pred_scalar (ASHIFTRT, builder.mode ());
+ emit_vlmax_insn (icode, BINARY_OP, shift_ops);
+
+ /* Step 4: Multiply to step size n. */
+ HOST_WIDE_INT step_size =
+ INTVAL (builder.elt (builder.npatterns ()))
+ - INTVAL (builder.elt (0));
+ rtx tmp3 = gen_reg_rtx (builder.mode ());
+ if (pow2p_hwi (step_size))
+ {
+ /* Power of 2 can be handled with a left shift. */
+ HOST_WIDE_INT shift = exact_log2 (step_size);
+ rtx shift_amount = gen_int_mode (shift, Pmode);
+ insn_code icode = code_for_pred_scalar (ASHIFT, mode);
+ rtx ops[] = {tmp3, tmp2, shift_amount};
+ emit_vlmax_insn (icode, BINARY_OP, ops);
+ }
+ else
+ {
+ rtx mult_amt = gen_int_mode (step_size, builder.inner_mode
());
+ insn_code icode = code_for_pred_scalar (MULT, builder.mode
());
+ rtx ops[] = {tmp3, tmp2, mult_amt};
+ emit_vlmax_insn (icode, BINARY_OP, ops);
+ }
+
+ /* Step 5: Add starting value to all elements. */
HOST_WIDE_INT init_val = INTVAL (builder.elt (0));
if (init_val == 0)
- emit_move_insn (target, tmp);
+ emit_move_insn (target, tmp3);
else
{
rtx dup = gen_const_vector_dup (builder.mode (), init_val);
- rtx add_ops[] = {target, tmp, dup};
+ rtx add_ops[] = {target, tmp3, dup};
icode = code_for_pred (PLUS, builder.mode ());
emit_vlmax_insn (icode, BINARY_OP, add_ops);
}
[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Reorder insn cost match order to match corresponding expander match order
https://gcc.gnu.org/g:77bdff2732045dfd049cb8ab91c948514f444fcb
commit 77bdff2732045dfd049cb8ab91c948514f444fcb
Author: Patrick O'Neill
Date: Tue Aug 20 11:38:20 2024 -0700
RISC-V: Reorder insn cost match order to match corresponding expander match
order
The corresponding expander (riscv-v.cc:expand_const_vector) matches
const_vec_duplicate_p before const_vec_series_p. Reorder to match this
behavior when calculating costs.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_const_insns): Relocate.
Signed-off-by: Patrick O'Neill
(cherry picked from commit ac1f3a8901344759dc7c247d3749c74a0bb524b0)
Diff:
---
gcc/config/riscv/riscv.cc | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 76560c018bd8..e5294619f23c 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -2142,15 +2142,6 @@ riscv_const_insns (rtx x, bool allow_new_pseudos)
...etc. */
if (riscv_v_ext_mode_p (GET_MODE (x)))
{
- /* const series vector. */
- rtx base, step;
- if (const_vec_series_p (x, &base, &step))
- {
- /* This is not accurate, we will need to adapt the COST
-* accurately according to BASE && STEP. */
- return 1;
- }
-
rtx elt;
if (const_vec_duplicate_p (x, &elt))
{
@@ -2186,6 +2177,15 @@ riscv_const_insns (rtx x, bool allow_new_pseudos)
return 1 + 4; /*vmv.v.x + memory access. */
}
}
+
+ /* const series vector. */
+ rtx base, step;
+ if (const_vec_series_p (x, &base, &step))
+ {
+ /* This cost is not accurate, we will need to adapt the COST
+ accurately according to BASE && STEP. */
+ return 1;
+ }
}
/* TODO: We may support more const vector in the future. */
[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Handle case when constant vector construction target rtx is not a register
https://gcc.gnu.org/g:d812473dad74924f641325e3548333d93fa65b41
commit d812473dad74924f641325e3548333d93fa65b41
Author: Patrick O'Neill
Date: Tue Aug 20 11:29:12 2024 -0700
RISC-V: Handle case when constant vector construction target rtx is not a
register
This manifests in RTL that is optimized away which causes runtime failures
in the testsuite. Update all patterns to use a temp result register if
required.
gcc/ChangeLog:
* config/riscv/riscv-v.cc (expand_const_vector): Use tmp register if
needed.
Signed-off-by: Patrick O'Neill
(cherry picked from commit a3dc5d2100a3d17a2d67805de6d0373847bca780)
Diff:
---
gcc/config/riscv/riscv-v.cc | 73 +
1 file changed, 41 insertions(+), 32 deletions(-)
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 43afddaed861..08eccd5a2cda 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -1216,26 +1216,29 @@ static void
expand_const_vector (rtx target, rtx src)
{
machine_mode mode = GET_MODE (target);
+ rtx result = register_operand (target, mode) ? target : gen_reg_rtx (mode);
if (GET_MODE_CLASS (mode) == MODE_VECTOR_BOOL)
{
rtx elt;
gcc_assert (
const_vec_duplicate_p (src, &elt)
&& (rtx_equal_p (elt, const0_rtx) || rtx_equal_p (elt, const1_rtx)));
- rtx ops[] = {target, src};
+ rtx ops[] = {result, src};
emit_vlmax_insn (code_for_pred_mov (mode), UNARY_MASK_OP, ops);
+
+ if (result != target)
+ emit_move_insn (target, result);
return;
}
rtx elt;
if (const_vec_duplicate_p (src, &elt))
{
- rtx tmp = register_operand (target, mode) ? target : gen_reg_rtx (mode);
/* Element in range -16 ~ 15 integer or 0.0 floating-point,
we use vmv.v.i instruction. */
if (satisfies_constraint_vi (src) || satisfies_constraint_Wc0 (src))
{
- rtx ops[] = {tmp, src};
+ rtx ops[] = {result, src};
emit_vlmax_insn (code_for_pred_mov (mode), UNARY_OP, ops);
}
else
@@ -1252,7 +1255,7 @@ expand_const_vector (rtx target, rtx src)
instruction (vsetvl a5, zero). */
if (lra_in_progress)
{
- rtx ops[] = {tmp, elt};
+ rtx ops[] = {result, elt};
emit_vlmax_insn (code_for_pred_broadcast (mode), UNARY_OP, ops);
}
else
@@ -1260,15 +1263,15 @@ expand_const_vector (rtx target, rtx src)
struct expand_operand ops[2];
enum insn_code icode = optab_handler (vec_duplicate_optab, mode);
gcc_assert (icode != CODE_FOR_nothing);
- create_output_operand (&ops[0], tmp, mode);
+ create_output_operand (&ops[0], result, mode);
create_input_operand (&ops[1], elt, GET_MODE_INNER (mode));
expand_insn (icode, 2, ops);
- tmp = ops[0].value;
+ result = ops[0].value;
}
}
- if (tmp != target)
- emit_move_insn (target, tmp);
+ if (result != target)
+ emit_move_insn (target, result);
return;
}
@@ -1276,7 +1279,10 @@ expand_const_vector (rtx target, rtx src)
rtx base, step;
if (const_vec_series_p (src, &base, &step))
{
- expand_vec_series (target, base, step);
+ expand_vec_series (result, base, step);
+
+ if (result != target)
+ emit_move_insn (target, result);
return;
}
@@ -1309,7 +1315,7 @@ expand_const_vector (rtx target, rtx src)
all element equal to 0x0706050403020100. */
rtx ele = builder.get_merged_repeating_sequence ();
rtx dup = expand_vector_broadcast (builder.new_mode (), ele);
- emit_move_insn (target, gen_lowpart (mode, dup));
+ emit_move_insn (result, gen_lowpart (mode, dup));
}
else
{
@@ -1338,8 +1344,8 @@ expand_const_vector (rtx target, rtx src)
emit_vlmax_insn (code_for_pred_scalar (AND, builder.int_mode ()),
BINARY_OP, and_ops);
- rtx tmp = gen_reg_rtx (builder.mode ());
- rtx dup_ops[] = {tmp, builder.elt (0)};
+ rtx tmp1 = gen_reg_rtx (builder.mode ());
+ rtx dup_ops[] = {tmp1, builder.elt (0)};
emit_vlmax_insn (code_for_pred_broadcast (builder.mode ()), UNARY_OP,
dup_ops);
for (unsigned int i = 1; i < builder.npatterns (); i++)
@@ -1351,12 +1357,12 @@ expand_const_vector (rtx target, rtx src)
/* Merge scalar to each i. */
rtx tmp2 = gen_reg_rtx (builder.mode ());
- rtx merge_ops[] = {tmp2, tmp, builder.elt (i), mask};
+ rtx merge_ops[] = {tmp2, tmp1, builder.elt (i), mask};
insn_code icode = code_for_pred_merge_scalar (builder.mode ());
emit_vlmax_insn (icode, MERGE_OP, merge_ops);
-
[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Emit costs for bool and stepped const vectors
https://gcc.gnu.org/g:1c7dfc57c1363ea7e387527a5919642308001b2f
commit 1c7dfc57c1363ea7e387527a5919642308001b2f
Author: Patrick O'Neill
Date: Tue Aug 20 11:51:50 2024 -0700
RISC-V: Emit costs for bool and stepped const vectors
These cases are handled in the expander
(riscv-v.cc:expand_const_vector). We need the vector builder to detect
these cases so extract that out into a new riscv-v.h header file.
gcc/ChangeLog:
* config/riscv/riscv-v.cc (class rvv_builder): Move to riscv-v.h.
* config/riscv/riscv.cc (riscv_const_insns): Emit placeholder costs
for
bool/stepped const vectors.
* config/riscv/riscv-v.h: New file.
Signed-off-by: Patrick O'Neill
(cherry picked from commit 771256bcb9ddc478dd0a8ecf929dfda5334f0ff3)
Diff:
---
gcc/config/riscv/riscv-v.cc | 53 +--
gcc/config/riscv/riscv-v.h | 88 +
gcc/config/riscv/riscv.cc | 42 ++
3 files changed, 131 insertions(+), 52 deletions(-)
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 08eccd5a2cda..76ef3f643643 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -51,6 +51,7 @@
#include "targhooks.h"
#include "predict.h"
#include "errors.h"
+#include "riscv-v.h"
using namespace riscv_vector;
@@ -436,58 +437,6 @@ emit_nonvlmax_insn (unsigned icode, unsigned insn_flags,
rtx *ops, rtx vl)
e.emit_insn ((enum insn_code) icode, ops);
}
-class rvv_builder : public rtx_vector_builder
-{
-public:
- rvv_builder () : rtx_vector_builder () {}
- rvv_builder (machine_mode mode, unsigned int npatterns,
- unsigned int nelts_per_pattern)
-: rtx_vector_builder (mode, npatterns, nelts_per_pattern)
- {
-m_inner_mode = GET_MODE_INNER (mode);
-m_inner_bits_size = GET_MODE_BITSIZE (m_inner_mode);
-m_inner_bytes_size = GET_MODE_SIZE (m_inner_mode);
-m_mask_mode = get_mask_mode (mode);
-
-gcc_assert (
- int_mode_for_size (inner_bits_size (), 0).exists (&m_inner_int_mode));
-m_int_mode
- = get_vector_mode (m_inner_int_mode, GET_MODE_NUNITS (mode)).require ();
- }
-
- bool can_duplicate_repeating_sequence_p ();
- bool is_repeating_sequence ();
- rtx get_merged_repeating_sequence ();
-
- bool repeating_sequence_use_merge_profitable_p ();
- bool combine_sequence_use_slideup_profitable_p ();
- bool combine_sequence_use_merge_profitable_p ();
- rtx get_merge_scalar_mask (unsigned int, machine_mode) const;
-
- bool single_step_npatterns_p () const;
- bool npatterns_all_equal_p () const;
- bool interleaved_stepped_npatterns_p () const;
- bool npatterns_vid_diff_repeated_p () const;
-
- machine_mode new_mode () const { return m_new_mode; }
- scalar_mode inner_mode () const { return m_inner_mode; }
- scalar_int_mode inner_int_mode () const { return m_inner_int_mode; }
- machine_mode mask_mode () const { return m_mask_mode; }
- machine_mode int_mode () const { return m_int_mode; }
- unsigned int inner_bits_size () const { return m_inner_bits_size; }
- unsigned int inner_bytes_size () const { return m_inner_bytes_size; }
-
-private:
- scalar_mode m_inner_mode;
- scalar_int_mode m_inner_int_mode;
- machine_mode m_new_mode;
- scalar_int_mode m_new_inner_mode;
- machine_mode m_mask_mode;
- machine_mode m_int_mode;
- unsigned int m_inner_bits_size;
- unsigned int m_inner_bytes_size;
-};
-
/* Return true if the vector duplicated by a super element which is the fusion
of consecutive elements.
diff --git a/gcc/config/riscv/riscv-v.h b/gcc/config/riscv/riscv-v.h
new file mode 100644
index ..4635b5415c78
--- /dev/null
+++ b/gcc/config/riscv/riscv-v.h
@@ -0,0 +1,88 @@
+/* Subroutines used for code generation for RISC-V 'V' Extension for
+ GNU compiler.
+ Copyright (C) 2022-2024 Free Software Foundation, Inc.
+ Contributed by Juzhe Zhong (juzhe.zh...@rivai.ai), RiVAI Technologies Ltd.
+
+ This file is part of GCC.
+
+ GCC is free software; you can redistribute it and/or modify it
+ under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ GCC is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with GCC; see the file COPYING3. If not see
+
[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Handle 0.0 floating point pattern costing to match const_vector expander
https://gcc.gnu.org/g:f815c8f308c29271702255ec5690b77896ce71f3
commit f815c8f308c29271702255ec5690b77896ce71f3
Author: Patrick O'Neill
Date: Tue Aug 20 12:01:22 2024 -0700
RISC-V: Handle 0.0 floating point pattern costing to match const_vector
expander
The comment previously here stated that the Wc0/Wc1 cases are handled by
the vi constraint but that is not true for the 0.0 Wc0 case.
gcc/ChangeLog:
* config/riscv/riscv-v.h (valid_vec_immediate_p): Add new helper.
* config/riscv/riscv-v.cc (valid_vec_immediate_p): Ditto.
(expand_const_vector): Use new helper.
* config/riscv/riscv.cc (riscv_const_insns): Handle 0.0
floating-point
case.
Signed-off-by: Patrick O'Neill
(cherry picked from commit 282bbc9381c563c746a43bf35e93d349188cc8e8)
Diff:
---
gcc/config/riscv/riscv-v.cc | 11 ++-
gcc/config/riscv/riscv-v.h | 2 ++
gcc/config/riscv/riscv.cc | 8 +++-
3 files changed, 15 insertions(+), 6 deletions(-)
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 76ef3f643643..8aaeaea29911 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -794,6 +794,15 @@ const_vec_all_in_range_p (rtx vec, poly_int64 minval,
poly_int64 maxval)
return true;
}
+/* Returns true if the vector's elements are all duplicates in
+ range -16 ~ 15 integer or 0.0 floating-point. */
+
+bool
+valid_vec_immediate_p (rtx x)
+{
+ return (satisfies_constraint_vi (x) || satisfies_constraint_Wc0 (x));
+}
+
/* Return a const vector of VAL. The VAL can be either const_int or
const_poly_int. */
@@ -1185,7 +1194,7 @@ expand_const_vector (rtx target, rtx src)
{
/* Element in range -16 ~ 15 integer or 0.0 floating-point,
we use vmv.v.i instruction. */
- if (satisfies_constraint_vi (src) || satisfies_constraint_Wc0 (src))
+ if (valid_vec_immediate_p (src))
{
rtx ops[] = {result, src};
emit_vlmax_insn (code_for_pred_mov (mode), UNARY_OP, ops);
diff --git a/gcc/config/riscv/riscv-v.h b/gcc/config/riscv/riscv-v.h
index 4635b5415c78..e7b095f094e6 100644
--- a/gcc/config/riscv/riscv-v.h
+++ b/gcc/config/riscv/riscv-v.h
@@ -83,6 +83,8 @@ private:
unsigned int m_inner_bytes_size;
};
+extern bool valid_vec_immediate_p(rtx);
+
} // namespace riscv_vector
#endif // GCC_RISCV_V_H
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index efa5d1853438..335ca5e6c89b 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -2158,11 +2158,9 @@ riscv_const_insns (rtx x, bool allow_new_pseudos)
if (maybe_gt (GET_MODE_SIZE (smode), UNITS_PER_WORD)
&& !immediate_operand (elt, Pmode))
return 0;
- /* Constants from -16 to 15 can be loaded with vmv.v.i.
- The Wc0, Wc1 constraints are already covered by the
- vi constraint so we do not need to check them here
- separately. */
- if (satisfies_constraint_vi (x))
+ /* Constants in range -16 ~ 15 integer or 0.0 floating-point
+ can be emitted using vmv.v.i. */
+ if (valid_vec_immediate_p (x))
return 1;
/* Any int/FP constants can always be broadcast from a
[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Allow non-duplicate bool patterns in expand_const_vector
https://gcc.gnu.org/g:a27d2ba5f655608dee585b6500bbdda17f488e91
commit a27d2ba5f655608dee585b6500bbdda17f488e91
Author: Patrick O'Neill
Date: Tue Aug 20 12:50:51 2024 -0700
RISC-V: Allow non-duplicate bool patterns in expand_const_vector
Currently we assert when encountering a non-duplicate boolean vector.
This patch allows non-duplicate vectors to fall through to the
gcc_unreachable and assert there.
This will be useful when adding a catch-all pattern to emit costs and
handle arbitary vectors.
gcc/ChangeLog:
* config/riscv/riscv-v.cc (expand_const_vector): Allow non-duplicate
to fall through other patterns before asserting.
Signed-off-by: Patrick O'Neill
(cherry picked from commit 1cd890279668bf94c93004bdbb757a1342931914)
Diff:
---
gcc/config/riscv/riscv-v.cc | 23 ---
1 file changed, 8 insertions(+), 15 deletions(-)
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 8aaeaea29911..9b6c3a21e2d3 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -1175,26 +1175,19 @@ expand_const_vector (rtx target, rtx src)
{
machine_mode mode = GET_MODE (target);
rtx result = register_operand (target, mode) ? target : gen_reg_rtx (mode);
- if (GET_MODE_CLASS (mode) == MODE_VECTOR_BOOL)
-{
- rtx elt;
- gcc_assert (
- const_vec_duplicate_p (src, &elt)
- && (rtx_equal_p (elt, const0_rtx) || rtx_equal_p (elt, const1_rtx)));
- rtx ops[] = {result, src};
- emit_vlmax_insn (code_for_pred_mov (mode), UNARY_MASK_OP, ops);
-
- if (result != target)
- emit_move_insn (target, result);
- return;
-}
-
rtx elt;
if (const_vec_duplicate_p (src, &elt))
{
+ if (GET_MODE_CLASS (mode) == MODE_VECTOR_BOOL)
+ {
+ gcc_assert (rtx_equal_p (elt, const0_rtx)
+ || rtx_equal_p (elt, const1_rtx));
+ rtx ops[] = {result, src};
+ emit_vlmax_insn (code_for_pred_mov (mode), UNARY_MASK_OP, ops);
+ }
/* Element in range -16 ~ 15 integer or 0.0 floating-point,
we use vmv.v.i instruction. */
- if (valid_vec_immediate_p (src))
+ else if (valid_vec_immediate_p (src))
{
rtx ops[] = {result, src};
emit_vlmax_insn (code_for_pred_mov (mode), UNARY_OP, ops);
[gcc r15-3236] Fix test failing on sparc
https://gcc.gnu.org/g:ffb00a0da44be946bcac45dd702e18555f564b2e
commit r15-3236-gffb00a0da44be946bcac45dd702e18555f564b2e
Author: Andi Kleen
Date: Tue Aug 27 16:45:26 2024 -0700
Fix test failing on sparc
SPARC does not support vectorizing conditions, which this test relies
on. Use vect_condition as effective target.
Committed as obvious.
PR testsuite/116500
gcc/testsuite/ChangeLog:
* gcc.dg/vect/vect-switch-ifcvt-1.c: Use vect_condition to
check if vectorizing conditions is supported for target.
Diff:
---
gcc/testsuite/gcc.dg/vect/vect-switch-ifcvt-1.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/testsuite/gcc.dg/vect/vect-switch-ifcvt-1.c
b/gcc/testsuite/gcc.dg/vect/vect-switch-ifcvt-1.c
index f5352ef8ed7a..2e3a9ae3c249 100644
--- a/gcc/testsuite/gcc.dg/vect/vect-switch-ifcvt-1.c
+++ b/gcc/testsuite/gcc.dg/vect/vect-switch-ifcvt-1.c
@@ -1,4 +1,4 @@
-/* { dg-require-effective-target vect_int } */
+/* { dg-require-effective-target vect_condition } */
#include "tree-vect.h"
extern void abort (void);
[gcc r15-3238] RISC-V: Add testcases for unsigned scalar .SAT_SUB IMM form 3
https://gcc.gnu.org/g:cb0b8b62223b485a058a56fc5c6345974ebaa230
commit r15-3238-gcb0b8b62223b485a058a56fc5c6345974ebaa230
Author: Pan Li
Date: Tue Aug 27 14:37:01 2024 +0800
RISC-V: Add testcases for unsigned scalar .SAT_SUB IMM form 3
This patch would like to add test cases for the unsigned scalar
.SAT_SUB IMM form 3. Aka:
Form 3:
#define DEF_SAT_U_SUB_IMM_FMT_3(T, IMM) \
T __attribute__((noinline)) \
sat_u_sub_imm##IMM##_##T##_fmt_3 (T y) \
{ \
return (T)IMM > y ? (T)IMM - y : 0; \
}
DEF_SAT_U_SUB_IMM_FMT_3(uint64_t, 23)
The below test is passed for this patch.
* The rv64gcv regression test.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/sat_arith.h: Add test helper macros.
* gcc.target/riscv/sat_u_sub_imm-10.c: New test.
* gcc.target/riscv/sat_u_sub_imm-10_1.c: New test.
* gcc.target/riscv/sat_u_sub_imm-10_2.c: New test.
* gcc.target/riscv/sat_u_sub_imm-11.c: New test.
* gcc.target/riscv/sat_u_sub_imm-11_1.c: New test.
* gcc.target/riscv/sat_u_sub_imm-11_2.c: New test.
* gcc.target/riscv/sat_u_sub_imm-12.c: New test.
* gcc.target/riscv/sat_u_sub_imm-9.c: New test.
* gcc.target/riscv/sat_u_sub_imm-9_1.c: New test.
* gcc.target/riscv/sat_u_sub_imm-9_2.c: New test.
* gcc.target/riscv/sat_u_sub_imm-run-10.c: New test.
* gcc.target/riscv/sat_u_sub_imm-run-11.c: New test.
* gcc.target/riscv/sat_u_sub_imm-run-12.c: New test.
* gcc.target/riscv/sat_u_sub_imm-run-9.c: New test.
Signed-off-by: Pan Li
Diff:
---
gcc/testsuite/gcc.target/riscv/sat_arith.h | 9
gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-10.c | 21
.../gcc.target/riscv/sat_u_sub_imm-10_1.c | 22 +
.../gcc.target/riscv/sat_u_sub_imm-10_2.c | 22 +
gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-11.c | 20
.../gcc.target/riscv/sat_u_sub_imm-11_1.c | 22 +
.../gcc.target/riscv/sat_u_sub_imm-11_2.c | 22 +
gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-12.c | 19
gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-9.c | 20
gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-9_1.c | 20
gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-9_2.c | 20
.../gcc.target/riscv/sat_u_sub_imm-run-10.c| 56 ++
.../gcc.target/riscv/sat_u_sub_imm-run-11.c| 55 +
.../gcc.target/riscv/sat_u_sub_imm-run-12.c| 48 +++
.../gcc.target/riscv/sat_u_sub_imm-run-9.c | 56 ++
15 files changed, 432 insertions(+)
diff --git a/gcc/testsuite/gcc.target/riscv/sat_arith.h
b/gcc/testsuite/gcc.target/riscv/sat_arith.h
index c8ff8320d824..b4339eb0dff9 100644
--- a/gcc/testsuite/gcc.target/riscv/sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/sat_arith.h
@@ -231,6 +231,13 @@ sat_u_sub_imm##IMM##_##T##_fmt_2 (T x) \
return x >= (T)IMM ? x - (T)IMM : 0; \
}
+#define DEF_SAT_U_SUB_IMM_FMT_3(T, IMM) \
+T __attribute__((noinline)) \
+sat_u_sub_imm##IMM##_##T##_fmt_3 (T y) \
+{ \
+ return (T)IMM > y ? (T)IMM - y : 0; \
+}
+
#define RUN_SAT_U_SUB_FMT_1(T, x, y) sat_u_sub_##T##_fmt_1(x, y)
#define RUN_SAT_U_SUB_FMT_2(T, x, y) sat_u_sub_##T##_fmt_2(x, y)
#define RUN_SAT_U_SUB_FMT_3(T, x, y) sat_u_sub_##T##_fmt_3(x, y)
@@ -248,6 +255,8 @@ sat_u_sub_imm##IMM##_##T##_fmt_2 (T x) \
if (sat_u_sub_imm##IMM##_##T##_fmt_1(y) != expect) __builtin_abort ()
#define RUN_SAT_U_SUB_IMM_FMT_2(T, x, IMM, expect) \
if (sat_u_sub_imm##IMM##_##T##_fmt_2(x) != expect) __builtin_abort ()
+#define RUN_SAT_U_SUB_IMM_FMT_3(T, IMM, y, expect) \
+ if (sat_u_sub_imm##IMM##_##T##_fmt_3(y) != expect) __builtin_abort ()
/**/
/* Saturation Truncate (unsigned and signed)
*/
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-10.c
b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-10.c
new file mode 100644
index ..db450d7cfbf8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-10.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details
-fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_imm6_uint16_t_fmt_3:
+** li\s+[atx][0-9]+,\s*6
+** sub\s+[atx][0-9]+,\s*[atx][0-9]+,\s*a0
+** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** addi\s+a0,\s*a0,\s*-1
+** and\s+a0,\s*a0,\s*[atx][0-9]+
+** slli\s+a0,\s*a0,\s*48
+** srli\s+a0,\s*a0,\s*48
+** ret
+*/
+
+DEF_SAT_U_SUB_IMM_FMT_3(uint16_t, 6)
+
+/* { d
[gcc r15-3239] RISC-V: Add testcases for unsigned scalar .SAT_SUB IMM form 4
https://gcc.gnu.org/g:3989e31d867b3505f847ecb6d870eacacfdf47bf
commit r15-3239-g3989e31d867b3505f847ecb6d870eacacfdf47bf
Author: Pan Li
Date: Tue Aug 27 15:14:40 2024 +0800
RISC-V: Add testcases for unsigned scalar .SAT_SUB IMM form 4
This patch would like to add test cases for the unsigned scalar
.SAT_SUB IMM form 4. Aka:
Form 4:
#define DEF_SAT_U_SUB_IMM_FMT_4(T, IMM) \
T __attribute__((noinline)) \
sat_u_sub_imm##IMM##_##T##_fmt_4 (T x) \
{ \
return x > (T)IMM ? x - (T)IMM : 0; \
}
DEF_SAT_U_SUB_IMM_FMT_4(uint64_t, 23)
The below test is passed for this patch.
* The rv64gcv regression test.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/sat_arith.h: Add test helper macros.
* gcc.target/riscv/sat_u_sub_imm-13.c: New test.
* gcc.target/riscv/sat_u_sub_imm-13_1.c: New test.
* gcc.target/riscv/sat_u_sub_imm-13_2.c: New test.
* gcc.target/riscv/sat_u_sub_imm-14.c: New test.
* gcc.target/riscv/sat_u_sub_imm-14_1.c: New test.
* gcc.target/riscv/sat_u_sub_imm-14_2.c: New test.
* gcc.target/riscv/sat_u_sub_imm-15.c: New test.
* gcc.target/riscv/sat_u_sub_imm-15_1.c: New test.
* gcc.target/riscv/sat_u_sub_imm-15_2.c: New test.
* gcc.target/riscv/sat_u_sub_imm-16.c: New test.
* gcc.target/riscv/sat_u_sub_imm-run-13.c: New test.
* gcc.target/riscv/sat_u_sub_imm-run-14.c: New test.
* gcc.target/riscv/sat_u_sub_imm-run-15.c: New test.
* gcc.target/riscv/sat_u_sub_imm-run-16.c: New test.
Signed-off-by: Pan Li
Diff:
---
gcc/testsuite/gcc.target/riscv/sat_arith.h | 9
gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-13.c | 19
.../gcc.target/riscv/sat_u_sub_imm-13_1.c | 19
.../gcc.target/riscv/sat_u_sub_imm-13_2.c | 19
gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-14.c | 20
.../gcc.target/riscv/sat_u_sub_imm-14_1.c | 21 +
.../gcc.target/riscv/sat_u_sub_imm-14_2.c | 22 +
gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-15.c | 19
.../gcc.target/riscv/sat_u_sub_imm-15_1.c | 21 +
.../gcc.target/riscv/sat_u_sub_imm-15_2.c | 22 +
gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-16.c | 18 +++
.../gcc.target/riscv/sat_u_sub_imm-run-13.c| 55 ++
.../gcc.target/riscv/sat_u_sub_imm-run-14.c| 55 ++
.../gcc.target/riscv/sat_u_sub_imm-run-15.c| 54 +
.../gcc.target/riscv/sat_u_sub_imm-run-16.c| 48 +++
15 files changed, 421 insertions(+)
diff --git a/gcc/testsuite/gcc.target/riscv/sat_arith.h
b/gcc/testsuite/gcc.target/riscv/sat_arith.h
index b4339eb0dff9..a899979904b9 100644
--- a/gcc/testsuite/gcc.target/riscv/sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/sat_arith.h
@@ -238,6 +238,13 @@ sat_u_sub_imm##IMM##_##T##_fmt_3 (T y) \
return (T)IMM > y ? (T)IMM - y : 0; \
}
+#define DEF_SAT_U_SUB_IMM_FMT_4(T, IMM) \
+T __attribute__((noinline)) \
+sat_u_sub_imm##IMM##_##T##_fmt_4 (T x) \
+{ \
+ return x > (T)IMM ? x - (T)IMM : 0; \
+}
+
#define RUN_SAT_U_SUB_FMT_1(T, x, y) sat_u_sub_##T##_fmt_1(x, y)
#define RUN_SAT_U_SUB_FMT_2(T, x, y) sat_u_sub_##T##_fmt_2(x, y)
#define RUN_SAT_U_SUB_FMT_3(T, x, y) sat_u_sub_##T##_fmt_3(x, y)
@@ -257,6 +264,8 @@ sat_u_sub_imm##IMM##_##T##_fmt_3 (T y) \
if (sat_u_sub_imm##IMM##_##T##_fmt_2(x) != expect) __builtin_abort ()
#define RUN_SAT_U_SUB_IMM_FMT_3(T, IMM, y, expect) \
if (sat_u_sub_imm##IMM##_##T##_fmt_3(y) != expect) __builtin_abort ()
+#define RUN_SAT_U_SUB_IMM_FMT_4(T, x, IMM, expect) \
+ if (sat_u_sub_imm##IMM##_##T##_fmt_4(x) != expect) __builtin_abort ()
/**/
/* Saturation Truncate (unsigned and signed)
*/
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-13.c
b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-13.c
new file mode 100644
index ..7dcbc3b1a126
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-13.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details
-fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_imm11_uint8_t_fmt_4:
+** addi\s+[atx][0-9]+,\s*a0,\s*-11
+** sltiu\s+a0,\s*[atx][0-9]+,\s*11
+** addi\s+a0,\s*a0,\s*-1
+** and\s+a0,\s*a0,\s*[atx][0-9]+
+** andi\s+a0,\s*a0,\s*0xff
+** ret
+*/
+
+DEF_SAT_U_SUB_IMM_FMT_4(uint8_t, 11)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git
[gcc r15-3240] Fix PR testsuite/116271, gcc.dg/vect/tsvc/vect-tsvc-s176.c fails
https://gcc.gnu.org/g:beb94f5979953969593a2387561cdbc8fedfaeb1
commit r15-3240-gbeb94f5979953969593a2387561cdbc8fedfaeb1
Author: Joern Rennecke
Date: Wed Aug 28 01:46:25 2024 +0100
Fix PR testsuite/116271, gcc.dg/vect/tsvc/vect-tsvc-s176.c fails
gcc/testsuite:
PR testsuite/116271
* gcc.dg/vect/tsvc/vect-tsvc-s176.c [TRUNCATE_TEST]: Make sure
that m stays the same as the loop bound of the middle loop.
* gcc.dg/vect/tsvc/tsvc.h (get_expected_result)
[TRUNCATE_TEST]:
Adjust expected value.
Diff:
---
gcc/testsuite/gcc.dg/vect/tsvc/tsvc.h | 2 +-
gcc/testsuite/gcc.dg/vect/tsvc/vect-tsvc-s176.c | 18 ++
2 files changed, 11 insertions(+), 9 deletions(-)
diff --git a/gcc/testsuite/gcc.dg/vect/tsvc/tsvc.h
b/gcc/testsuite/gcc.dg/vect/tsvc/tsvc.h
index cc02e4cacba1..4d295d1ec296 100644
--- a/gcc/testsuite/gcc.dg/vect/tsvc/tsvc.h
+++ b/gcc/testsuite/gcc.dg/vect/tsvc/tsvc.h
@@ -1727,7 +1727,7 @@ real_t get_expected_result(const char * name)
#ifndef TRUNCATE_TEST
return 32021.121094f;
#else /* TRUNCATE_TEST */
-return 32024.082031f;
+return 32023.751953f;
#endif /* TRUNCATE_TEST */
#endif /* iterations */
} else {
diff --git a/gcc/testsuite/gcc.dg/vect/tsvc/vect-tsvc-s176.c
b/gcc/testsuite/gcc.dg/vect/tsvc/vect-tsvc-s176.c
index 6e9580582d54..626692bcb81d 100644
--- a/gcc/testsuite/gcc.dg/vect/tsvc/vect-tsvc-s176.c
+++ b/gcc/testsuite/gcc.dg/vect/tsvc/vect-tsvc-s176.c
@@ -15,18 +15,20 @@ real_t s176(struct args_t * func_args)
initialise_arrays(__func__);
-int m = LEN_1D/2;
#ifdef TRUNCATE_TEST
-/* Do something equivalent to if (1) which the compiler is unlikely to
- figure out.
- FUNC_ARGS is in the caller's frame, so it shouldn't be between A and B.
- */
-if ((void *)func_args <= (void *)a || (void *)func_args >= (void *)b)
- m = 32;
+/* Reduce the iteration counts without changing what is a variable and
+ what is a constant expression.
+ 32000/25 == 640, i.e. it still has a nice power of two factor, but is
+ not a power of two itself, and still somewhat large-ish, so hopefully
+ this won't perturb the vectorizer decisions much. */
+#define M_CONST LEN_1D/50
+#else
+#define M_CONST LEN_1D/2
#endif
+int m = M_CONST;
for (int nl = 0; nl < 4*(10*iterations/LEN_1D); nl++) {
-for (int j = 0; j < (LEN_1D/2); j++) {
+for (int j = 0; j < (M_CONST); j++) {
for (int i = 0; i < m; i++) {
a[i] += b[i+m-j-1] * c[j];
}
[gcc r15-3241] Match: Support form 1 for scalar signed integer .SAT_ADD
https://gcc.gnu.org/g:fe5f652bab420eb372645281f7fe3e5aa1534d01
commit r15-3241-gfe5f652bab420eb372645281f7fe3e5aa1534d01
Author: Pan Li
Date: Mon Aug 26 10:11:38 2024 +0800
Match: Support form 1 for scalar signed integer .SAT_ADD
This patch would like to support the form 1 of the scalar signed
integer .SAT_ADD. Aka below example:
Form 1:
#define DEF_SAT_S_ADD_FMT_1(T, UT, MIN, MAX) \
T __attribute__((noinline)) \
sat_s_add_##T##_fmt_1 (T x, T y) \
{\
T sum = (UT)x + (UT)y; \
return (x ^ y) < 0 \
? sum\
: (sum ^ x) >= 0 \
? sum \
: x < 0 ? MIN : MAX; \
}
DEF_SAT_S_ADD_FMT_1(int64_t, uint64_t, INT64_MIN, INT64_MAX)
We can tell the difference before and after this patch if backend
implemented the ssadd3 pattern similar as below.
Before this patch:
4 │ __attribute__((noinline))
5 │ int64_t sat_s_add_int64_t_fmt_1 (int64_t x, int64_t y)
6 │ {
7 │ int64_t sum;
8 │ long unsigned int x.0_1;
9 │ long unsigned int y.1_2;
10 │ long unsigned int _3;
11 │ long int _4;
12 │ long int _5;
13 │ int64_t _6;
14 │ _Bool _11;
15 │ long int _12;
16 │ long int _13;
17 │ long int _14;
18 │ long int _16;
19 │ long int _17;
20 │
21 │ ;; basic block 2, loop depth 0
22 │ ;;pred: ENTRY
23 │ x.0_1 = (long unsigned int) x_7(D);
24 │ y.1_2 = (long unsigned int) y_8(D);
25 │ _3 = x.0_1 + y.1_2;
26 │ sum_9 = (int64_t) _3;
27 │ _4 = x_7(D) ^ y_8(D);
28 │ _5 = x_7(D) ^ sum_9;
29 │ _17 = ~_4;
30 │ _16 = _5 & _17;
31 │ if (_16 < 0)
32 │ goto ; [41.00%]
33 │ else
34 │ goto ; [59.00%]
35 │ ;;succ: 3
36 │ ;;4
37 │
38 │ ;; basic block 3, loop depth 0
39 │ ;;pred: 2
40 │ _11 = x_7(D) < 0;
41 │ _12 = (long int) _11;
42 │ _13 = -_12;
43 │ _14 = _13 ^ 9223372036854775807;
44 │ ;;succ: 4
45 │
46 │ ;; basic block 4, loop depth 0
47 │ ;;pred: 2
48 │ ;;3
49 │ # _6 = PHI
50 │ return _6;
51 │ ;;succ: EXIT
52 │
53 │ }
After this patch:
4 │ __attribute__((noinline))
5 │ int64_t sat_s_add_int64_t_fmt_1 (int64_t x, int64_t y)
6 │ {
7 │ int64_t _4;
8 │
9 │ ;; basic block 2, loop depth 0
10 │ ;;pred: ENTRY
11 │ _4 = .SAT_ADD (x_5(D), y_6(D)); [tail call]
12 │ return _4;
13 │ ;;succ: EXIT
14 │
15 │ }
The below test suites are passed for this patch.
* The rv64gcv fully regression test.
* The x86 bootstrap test.
* The x86 fully regression test.
gcc/ChangeLog:
* match.pd: Add the matching for signed .SAT_ADD.
* tree-ssa-math-opts.cc (gimple_signed_integer_sat_add): Add new
matching func decl.
(match_unsigned_saturation_add): Try signed .SAT_ADD and rename
to ...
(match_saturation_add): ... here.
(math_opts_dom_walker::after_dom_children): Update the above renamed
func from caller.
Signed-off-by: Pan Li
Diff:
---
gcc/match.pd | 15 +++
gcc/tree-ssa-math-opts.cc | 35 ++-
2 files changed, 45 insertions(+), 5 deletions(-)
diff --git a/gcc/match.pd b/gcc/match.pd
index 5ee60963c904..be211535a49f 100644
--- a/gcc/match.pd
+++ b/gcc/match.pd
@@ -3192,6 +3192,21 @@ DEFINE_INT_AND_FLOAT_ROUND_FN (RINT)
(if (INTEGRAL_TYPE_P (type) && TYPE_UNSIGNED (type)
&& types_match (type, @0) && int_fits_type_p (@1, type
+/* Signed saturation add, case 1:
+ T sum = (T)((UT)X + (UT)Y)
+ SAT_S_ADD = (X ^ sum) & !(X ^ Y) < 0 ? (-(T)(X < 0) ^ MAX) : sum;
+
+ The T and UT are type pair like T=int8_t, UT=uint8_t. */
+(match (signed_integer_sat_add @0 @1)
+ (cond^ (lt (bit_and:c (bit_xor:c @0 (nop_convert@2 (plus (nop_convert @0)
+ (nop_convert @1
+ (bit_not (bit_xor:c @0 @1)))
+ integer_zerop)
+ (bit_xor:c (negate (convert (lt @0 integer_zerop))) max_value)
+ @2)
+ (if (INTEGRAL_TYPE_P (type) && !TYPE_UNSIGNED (type)
+ && types_match (type, @0, @1
+
/* Unsigned saturation sub, case 1 (branch w
[gcc r15-3242] RISC-V: Add missing mode_idx for vrol and vror
https://gcc.gnu.org/g:3cde331e9590944819621bcde41ddbffd9bbf0ba
commit r15-3242-g3cde331e9590944819621bcde41ddbffd9bbf0ba
Author: Kito Cheng
Date: Tue Aug 27 21:27:02 2024 +0800
RISC-V: Add missing mode_idx for vrol and vror
We add pattern for vector rotate, but seems like we forgot adding
mode_idx which used in AVL propgation (riscv-avlprop.cc).
gcc/ChangeLog:
* config/riscv/vector.md (mode_idx): Add vrol and vror.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/rotr.c: New.
Diff:
---
gcc/config/riscv/vector.md| 2 +-
gcc/testsuite/gcc.target/riscv/rvv/autovec/rotr.c | 13 +
2 files changed, 14 insertions(+), 1 deletion(-)
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 666719330c69..d0677325ba1d 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -816,7 +816,7 @@
vfcmp,vfminmax,vfsgnj,vfclass,vfmerge,vfmov,\
vfcvtitof,vfncvtitof,vfncvtftoi,vfncvtftof,vmalu,vmiota,vmidx,\
vimovxv,vfmovfv,vslideup,vslidedown,vislide1up,vislide1down,vfslide1up,vfslide1down,\
-
vgather,vcompress,vmov,vnclip,vnshift,vandn,vcpop,vclz,vctz")
+
vgather,vcompress,vmov,vnclip,vnshift,vandn,vcpop,vclz,vctz,vrol,vror")
(const_int 0)
(eq_attr "type" "vimovvx,vfmovvf")
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/rotr.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/rotr.c
new file mode 100644
index ..055b28d1e787
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/rotr.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvbb -mabi=lp64d -fno-vect-cost-model
-mrvv-vector-bits=zvl" } */
+
+typedef int a;
+void *b;
+a c;
+void d() {
+ a e = c, f =0;
+ short *g = b;
+ for (; f < e; f++)
+*(g + f) = (255 & (*(g + f) >> 8)) | *(g + f) << 8;
+}
+
[gcc(refs/users/egallager/heads/master)] Merge branch 'gcc-mirror:master' into me/master
https://gcc.gnu.org/g:c271fdc52ebe8067451e52a75794076613ae23a2 commit c271fdc52ebe8067451e52a75794076613ae23a2 Merge: be2674c47243 184978cd74f9 Author: Eric Gallager Date: Mon Feb 5 18:49:21 2024 -0500 Merge branch 'gcc-mirror:master' into me/master Diff: ChangeLog | 12 + MAINTAINERS|6 +- contrib/ChangeLog |5 + contrib/test_installed |4 + contrib/unicode/gen_libstdcxx_unicode_data.py | 30 +- gcc/ChangeLog | 738 ++ gcc/DATESTAMP |2 +- gcc/analyzer/ChangeLog | 36 + gcc/analyzer/checker-event.cc | 59 +- gcc/analyzer/region-model.cc | 111 +- gcc/analyzer/state-purge.cc|9 + gcc/analyzer/supergraph.cc |4 + gcc/asan.h |7 +- gcc/builtins.cc|8 +- gcc/c-family/ChangeLog | 12 + gcc/c-family/c-opts.cc |5 + gcc/c-family/c-pch.cc | 23 +- gcc/c/ChangeLog| 25 + gcc/c/c-convert.cc |3 +- gcc/c/c-decl.cc|9 +- gcc/c/c-tree.h |3 +- gcc/c/c-typeck.cc | 36 +- gcc/common/config/riscv/riscv-common.cc| 14 + gcc/config/aarch64/aarch64-early-ra.cc | 28 +- gcc/config/aarch64/aarch64-ldpstp.md | 22 +- gcc/config/aarch64/aarch64-protos.h|2 +- gcc/config/aarch64/aarch64-simd.md | 11 +- gcc/config/aarch64/aarch64.cc | 20 +- gcc/config/arm/arm.cc |2 + gcc/config/avr/avr-mcus.def|8 +- gcc/config/avr/avr.cc | 7434 +++ gcc/config/darwin.h| 43 +- gcc/config/gcn/gcn.cc |6 +- gcc/config/gcn/gcn.h | 16 +- gcc/config/gcn/gcn.md | 17 +- gcc/config/i386/constraints.md |4 + gcc/config/i386/darwin.h |2 + gcc/config/i386/darwin32-biarch.h |3 + gcc/config/i386/darwin64-biarch.h |3 + gcc/config/i386/i386-expand.cc |2 +- gcc/config/i386/i386-features.cc | 26 + gcc/config/i386/i386.cc| 91 +- gcc/config/i386/i386.md|4 - gcc/config/loongarch/larchintrin.h | 16 +- gcc/config/loongarch/lasx.md | 16 - gcc/config/loongarch/loongarch-def.h |3 + gcc/config/loongarch/loongarch-opts.cc |2 - gcc/config/loongarch/loongarch-protos.h|1 + gcc/config/loongarch/loongarch.cc | 577 +- gcc/config/loongarch/loongarch.md | 125 +- gcc/config/loongarch/lsx.md| 11 - gcc/config/loongarch/predicates.md | 12 + gcc/config/loongarch/simd.md | 18 + gcc/config/mips/mips-msa.md| 18 +- gcc/config/pa/pa.cc| 215 +- gcc/config/pa/pa.md| 90 +- gcc/config/riscv/generic-ooo.md|2 +- gcc/config/riscv/generic.md|2 +- gcc/config/riscv/riscv-cores.def | 11 + gcc/config/riscv/riscv-opts.h |2 + gcc/config/riscv/riscv-v.cc| 12 +- gcc/config/riscv/riscv-vsetvl.cc | 248 +- gcc/config/riscv/riscv.cc | 151 +- gcc/config/riscv/riscv.h |5 +- gcc/config/riscv/riscv.md | 28 +- gcc/config/riscv/riscv.opt | 14 + gcc/config/riscv/sifive-7.md |2 +- gcc/config/riscv/sifive-p400.md| 174 + gcc/config/riscv/sifive-p600.md| 178 + gcc/config/riscv/thead.cc |3 +- gcc/config/rs6000/darwin.h |3 + gcc/config/sol2.h |2 +- gcc/config/sparc/sparc.h |7 + gcc/config/xtensa/constraints.md | 26 +- gcc/config/xtensa/predicates.md|7 +- gcc/config/xtensa/xtensa.cc| 46 +- gcc/config/xtensa/xtensa.md
[gcc(refs/users/egallager/heads/master)] Merge branch 'gcc-mirror:master' into me/master
https://gcc.gnu.org/g:acf3202147a77c67242e9638932ed7878cdee2f8 commit acf3202147a77c67242e9638932ed7878cdee2f8 Merge: f1b89f438575 4e3c8257304c Author: Eric Gallager Date: Sat Apr 6 20:18:13 2024 -0400 Merge branch 'gcc-mirror:master' into me/master Diff: ChangeLog | 30 + MAINTAINERS|7 +- Makefile.in| 33 + Makefile.tpl | 26 +- config/ChangeLog |5 + config/lcmessage.m4|4 +- contrib/ChangeLog | 24 + contrib/dg-extract-results.sh | 17 +- contrib/gcc_update |8 + contrib/test_mklog.py |2 +- contrib/unicode/gen_libstdcxx_unicode_data.py |6 +- gcc/ChangeLog | 2333 + gcc/DATESTAMP |2 +- gcc/ada/ChangeLog |6 + gcc/ada/exp_ch4.adb|6 +- gcc/analyzer/ChangeLog | 214 ++ gcc/analyzer/access-diagram.cc | 600 ++-- gcc/analyzer/access-diagram.h | 38 +- gcc/analyzer/analyzer-selftests.cc |1 + gcc/analyzer/analyzer-selftests.h |2 +- gcc/analyzer/analyzer.h| 11 +- gcc/analyzer/bounds-checking.cc| 148 +- gcc/analyzer/call-summary.cc | 13 + gcc/analyzer/constraint-manager.cc | 14 +- gcc/analyzer/diagnostic-manager.cc |2 +- gcc/analyzer/engine.cc |7 + gcc/analyzer/kf.cc | 157 +- gcc/analyzer/record-layout.cc |1 + gcc/analyzer/region-model-manager.cc | 164 +- gcc/analyzer/region-model-manager.h|7 +- gcc/analyzer/region-model.cc | 94 +- gcc/analyzer/region.cc | 67 +- gcc/analyzer/region.h |3 + gcc/analyzer/sm-malloc.cc | 31 + gcc/analyzer/sm-taint.cc | 58 +- gcc/analyzer/svalue.cc | 156 +- gcc/analyzer/svalue.h | 49 +- gcc/asan.cc| 40 +- gcc/auto-profile.cc|1 - gcc/bb-reorder.cc |6 +- gcc/btfout.cc | 30 +- gcc/builtins.cc| 14 +- gcc/c-family/ChangeLog | 42 + gcc/c-family/c-common.cc | 36 +- gcc/c-family/c-omp.cc | 51 +- gcc/c-family/c-pretty-print.cc |2 + gcc/c-family/c-warn.cc |1 - gcc/c-family/c.opt |4 + gcc/c-family/c.opt.urls| 352 +- gcc/c/ChangeLog| 23 + gcc/c/c-objc-common.cc | 23 + gcc/c/c-objc-common.h |3 + gcc/c/c-parser.cc | 68 +- gcc/c/c-tree.h |1 + gcc/cfganal.cc | 15 +- gcc/cfgloopmanip.cc|2 +- gcc/cgraph.h |6 + gcc/cgraphunit.cc |2 + gcc/collect2.cc|7 +- gcc/combine.cc | 28 +- gcc/common.opt | 11 +- gcc/common.opt.urls| 10 +- gcc/common/config/i386/cpuinfo.h | 16 + gcc/common/config/i386/i386-common.cc |6 +- gcc/common/config/i386/i386-cpuinfo.h |2 + gcc/common/config/riscv/riscv-common.cc| 139 +- gcc/config.gcc | 40 +- gcc/config/aarch64/aarch64-c.cc|4 +- gcc/config/aarch64/aarch64-cores.def |4 +- gcc/config/aarch64/aarch64-early-ra.cc | 20 +- gcc/config/aarch64/aarch64-feature-deps.h |3 + gcc/config/aarch64/aarch64-ldp-fusion.cc |2 +- gcc/config/aarch64/aarch64-option-extensions.def | 22 +- gcc/config/aarch64/aarch64-sme.md | 70 - gcc/config/aarch64/aarch64-sve-builtins-base.cc| 50 +- gcc/config/aarch64/aarch64-sve-builtins.cc | 16 + gcc/config/aarch64/aarch64-sve-bui
[gcc(refs/users/egallager/heads/master)] Merge branch 'gcc-mirror:master' into me/master
https://gcc.gnu.org/g:91913f4fdf0be9213eeb7cc787f91fdbf7b1ee38 commit 91913f4fdf0be9213eeb7cc787f91fdbf7b1ee38 Merge: acf3202147a7 b909daa5b673 Author: Eric Gallager Date: Mon Apr 22 18:22:16 2024 -0400 Merge branch 'gcc-mirror:master' into me/master Diff: ChangeLog |16 + config/ChangeLog | 9 + config/acx.m4 |10 + configure |80 + configure.ac |30 + contrib/ChangeLog |18 + contrib/check-params-in-docs.py|19 +- contrib/config-list.mk | 3 +- contrib/gcc-changelog/git_update_version.py| 3 +- gcc/ChangeLog | 959 ++ gcc/DATESTAMP | 2 +- gcc/ada/ChangeLog | 9 + .../doc/gnat_rm/implementation_defined_aspects.rst |12 + .../doc/gnat_rm/implementation_defined_pragmas.rst |18 + gcc/ada/gnat_rm.texi | 1649 +- gcc/ada/gnat_ugn.texi | 4 +- gcc/analyzer/ChangeLog |69 + gcc/analyzer/access-diagram.cc | 4 + gcc/analyzer/analyzer.opt | 2 +- gcc/analyzer/call-details.cc |33 +- gcc/analyzer/infinite-loop.cc |22 + gcc/analyzer/infinite-recursion.cc |13 + gcc/analyzer/program-state.cc | 4 +- gcc/analyzer/ranges.cc |15 + gcc/analyzer/ranges.h | 4 + gcc/analyzer/region-model.cc | 6 +- gcc/analyzer/region.cc | 2 +- gcc/analyzer/sm-taint.cc |15 +- gcc/analyzer/store.cc |20 +- gcc/asan.cc|29 +- gcc/attribs.cc | 7 +- gcc/btfout.cc | 141 +- gcc/c-family/ChangeLog |20 + gcc/c-family/c-common.cc | 1 + gcc/c-family/c.opt | 4 + gcc/c-family/c.opt.urls| 3 + gcc/c/ChangeLog|31 + gcc/c/c-decl.cc|53 +- gcc/c/c-typeck.cc | 4 +- gcc/combine.cc |27 +- gcc/common/config/i386/i386-common.cc | 2 +- gcc/config.gcc |23 +- gcc/config/aarch64/aarch64-arches.def | 2 +- gcc/config/aarch64/aarch64-c.cc| 6 +- gcc/config/aarch64/aarch64-gnu.h |68 + gcc/config/aarch64/aarch64-option-extensions.def |73 +- gcc/config/aarch64/aarch64-protos.h| 6 +- gcc/config/aarch64/aarch64-sve-builtins-base.cc| 2 +- gcc/config/aarch64/aarch64-sve-builtins.cc |88 +- gcc/config/aarch64/aarch64-sve-builtins.h |17 +- gcc/config/aarch64/aarch64.cc | 138 +- gcc/config/aarch64/aarch64.h | 3 +- gcc/config/aarch64/aarch64.md |23 +- gcc/config/aarch64/driver-aarch64.cc | 2 +- gcc/config/aarch64/t-aarch64-rtems |42 + gcc/config/avr/avr-mcus.def| 8 + gcc/config/avr/avr.cc |17 +- gcc/config/bpf/bpf-protos.h| 2 +- gcc/config/bpf/bpf.cc |54 +- gcc/config/bpf/bpf.md |56 +- gcc/config/bpf/constraints.md |20 + gcc/config/bpf/core-builtins.cc| 128 +- gcc/config/bpf/core-builtins.h | 2 + gcc/config/bpf/predicates.md | 7 +- gcc/config/darwin.h| 2 +- gcc/config/gcn/gcn.cc |14 +- gcc/config/gcn/gcn.opt |16 + gcc/config/gnu.h |16 + gcc/config/i386/gnu.h |11 - gcc/config/i386/i386-c.cc | 2 + gcc/config/i386/i386-options.cc| 2 +- gcc/config/i386/i386.md|46 +- gcc/config/i386/sse.md | 118 +- gcc/config/loongarch/loongarch-builtins.cc |25 +- gcc/config/loongarch/loongarch-def.cc |11 +- gcc/config/loongarch/loongarch-opt
[gcc(refs/users/egallager/heads/master)] Merge branch 'gcc-mirror:master' into me/master
https://gcc.gnu.org/g:68dbebb95d94b331d4d71a96b6187fc6f1e47a29 commit 68dbebb95d94b331d4d71a96b6187fc6f1e47a29 Merge: b7b360c08cee 24cb586cafd4 Author: Eric Gallager Date: Sun Jul 7 15:13:57 2024 -0400 Merge branch 'gcc-mirror:master' into me/master Diff: ChangeLog |64 + MAINTAINERS|13 +- Makefile.in| 3 + Makefile.tpl | 3 + configure | 154 + configure.ac |41 + fixincludes/ChangeLog |12 + fixincludes/fixincl.x |14 +- fixincludes/inclhack.def |13 +- fixincludes/tests/base/math.h |11 - gcc/ChangeLog | 3815 + gcc/DATESTAMP | 2 +- gcc/Makefile.in| 8 +- gcc/ada/ChangeLog | 1458 ++ gcc/ada/Makefile.rtl | 3 + gcc/ada/accessibility.adb |19 +- gcc/ada/ali.adb|11 +- gcc/ada/ali.ads| 6 + gcc/ada/aspects.ads| 116 +- gcc/ada/atree.ads |10 +- gcc/ada/bcheck.adb |10 +- gcc/ada/bindgen.adb|20 +- gcc/ada/checks.adb |42 +- gcc/ada/contracts.adb |46 +- gcc/ada/csets.adb |46 +- gcc/ada/csets.ads |14 +- gcc/ada/debug.adb |23 +- gcc/ada/doc/gnat_rm/gnat_language_extensions.rst | 107 +- gcc/ada/doc/gnat_rm/implementation_advice.rst |15 +- .../doc/gnat_rm/implementation_defined_aspects.rst |20 +- .../gnat_rm/implementation_defined_attributes.rst |30 - .../implementation_defined_characteristics.rst | 4 +- .../doc/gnat_rm/implementation_defined_pragmas.rst |59 +- ...ard_and_implementation_defined_restrictions.rst |10 +- .../building_executable_programs_with_gnat.rst |44 +- .../doc/gnat_ugn/the_gnat_compilation_model.rst| 4 + gcc/ada/einfo-utils.adb|33 +- gcc/ada/einfo-utils.ads| 1 + gcc/ada/einfo.ads |84 +- gcc/ada/errout.adb | 159 +- gcc/ada/erroutc.adb|71 +- gcc/ada/erroutc.ads|18 - gcc/ada/errutil.adb|34 +- gcc/ada/exp_aggr.adb | 163 +- gcc/ada/exp_atag.adb |41 +- gcc/ada/exp_atag.ads | 4 +- gcc/ada/exp_attr.adb |74 +- gcc/ada/exp_ch11.adb | 2 +- gcc/ada/exp_ch3.adb| 162 +- gcc/ada/exp_ch4.adb| 402 +- gcc/ada/exp_ch5.adb| 133 +- gcc/ada/exp_ch6.adb|69 +- gcc/ada/exp_ch7.adb| 288 +- gcc/ada/exp_ch9.adb| 272 +- gcc/ada/exp_disp.adb |59 +- gcc/ada/exp_put_image.adb |17 +- gcc/ada/exp_util.adb | 278 +- gcc/ada/exp_util.ads |61 +- gcc/ada/expander.ads | 6 +- gcc/ada/freeze.adb | 604 +- gcc/ada/freeze.ads |13 +- gcc/ada/gcc-interface/Make-lang.in |22 +- gcc/ada/gcc-interface/Makefile.in | 6 - gcc/ada/gcc-interface/cuintp.cc|66 +- gcc/ada/gcc-interface/decl.cc |63 +- gcc/ada/gcc-interface/gigi.h | 7 +- gcc/ada/gcc-interface/misc.cc |20 +- gcc/ada/gcc-interface/trans.cc |60 +- gcc/ada/gcc-interface/utils.cc | 144 +- gcc/ada/gcc-interface/utils2.cc| 228 +- gcc/ada/gen_il-fields.ads | 3 + gcc/ada/gen_il-gen-gen_entities.adb| 3 + gcc/ada/gen_il-gen-gen_nodes.adb | 3 +- gcc/ada/ghost.adb | 8 +- gcc/ada/gnat1drv.adb |22 +- gcc/ada/gnat_rm.tex
[gcc(refs/users/egallager/heads/CI)] Merge branch 'gcc-mirror:master' into me/CI
https://gcc.gnu.org/g:b2b3563188cb9e8a2e8116ba2f4b3495155c6809 commit b2b3563188cb9e8a2e8116ba2f4b3495155c6809 Merge: c64aef013f25 184978cd74f9 Author: Eric Gallager Date: Mon Feb 5 18:49:51 2024 -0500 Merge branch 'gcc-mirror:master' into me/CI Diff: ChangeLog | 12 + MAINTAINERS|6 +- contrib/ChangeLog |5 + contrib/test_installed |4 + contrib/unicode/gen_libstdcxx_unicode_data.py | 30 +- gcc/ChangeLog | 738 ++ gcc/DATESTAMP |2 +- gcc/analyzer/ChangeLog | 36 + gcc/analyzer/checker-event.cc | 59 +- gcc/analyzer/region-model.cc | 111 +- gcc/analyzer/state-purge.cc|9 + gcc/analyzer/supergraph.cc |4 + gcc/asan.h |7 +- gcc/builtins.cc|8 +- gcc/c-family/ChangeLog | 12 + gcc/c-family/c-opts.cc |5 + gcc/c-family/c-pch.cc | 23 +- gcc/c/ChangeLog| 25 + gcc/c/c-convert.cc |3 +- gcc/c/c-decl.cc|9 +- gcc/c/c-tree.h |3 +- gcc/c/c-typeck.cc | 36 +- gcc/common/config/riscv/riscv-common.cc| 14 + gcc/config/aarch64/aarch64-early-ra.cc | 28 +- gcc/config/aarch64/aarch64-ldpstp.md | 22 +- gcc/config/aarch64/aarch64-protos.h|2 +- gcc/config/aarch64/aarch64-simd.md | 11 +- gcc/config/aarch64/aarch64.cc | 20 +- gcc/config/arm/arm.cc |2 + gcc/config/avr/avr-mcus.def|8 +- gcc/config/avr/avr.cc | 7434 +++ gcc/config/darwin.h| 43 +- gcc/config/gcn/gcn.cc |6 +- gcc/config/gcn/gcn.h | 16 +- gcc/config/gcn/gcn.md | 17 +- gcc/config/i386/constraints.md |4 + gcc/config/i386/darwin.h |2 + gcc/config/i386/darwin32-biarch.h |3 + gcc/config/i386/darwin64-biarch.h |3 + gcc/config/i386/i386-expand.cc |2 +- gcc/config/i386/i386-features.cc | 26 + gcc/config/i386/i386.cc| 91 +- gcc/config/i386/i386.md|4 - gcc/config/loongarch/larchintrin.h | 16 +- gcc/config/loongarch/lasx.md | 16 - gcc/config/loongarch/loongarch-def.h |3 + gcc/config/loongarch/loongarch-opts.cc |2 - gcc/config/loongarch/loongarch-protos.h|1 + gcc/config/loongarch/loongarch.cc | 577 +- gcc/config/loongarch/loongarch.md | 125 +- gcc/config/loongarch/lsx.md| 11 - gcc/config/loongarch/predicates.md | 12 + gcc/config/loongarch/simd.md | 18 + gcc/config/mips/mips-msa.md| 18 +- gcc/config/pa/pa.cc| 215 +- gcc/config/pa/pa.md| 90 +- gcc/config/riscv/generic-ooo.md|2 +- gcc/config/riscv/generic.md|2 +- gcc/config/riscv/riscv-cores.def | 11 + gcc/config/riscv/riscv-opts.h |2 + gcc/config/riscv/riscv-v.cc| 12 +- gcc/config/riscv/riscv-vsetvl.cc | 248 +- gcc/config/riscv/riscv.cc | 151 +- gcc/config/riscv/riscv.h |5 +- gcc/config/riscv/riscv.md | 28 +- gcc/config/riscv/riscv.opt | 14 + gcc/config/riscv/sifive-7.md |2 +- gcc/config/riscv/sifive-p400.md| 174 + gcc/config/riscv/sifive-p600.md| 178 + gcc/config/riscv/thead.cc |3 +- gcc/config/rs6000/darwin.h |3 + gcc/config/sol2.h |2 +- gcc/config/sparc/sparc.h |7 + gcc/config/xtensa/constraints.md | 26 +- gcc/config/xtensa/predicates.md|7 +- gcc/config/xtensa/xtensa.cc| 46 +- gcc/config/xtensa/xtensa.md
[gcc(refs/users/egallager/heads/CI)] Merge branch 'gcc-mirror:master' into me/CI
https://gcc.gnu.org/g:90e8f13063ec5d3e9d422115900169e0545e65ca commit 90e8f13063ec5d3e9d422115900169e0545e65ca Merge: b2b3563188cb 39d989022dd0 Author: Eric Gallager Date: Mon Feb 12 16:16:49 2024 -0500 Merge branch 'gcc-mirror:master' into me/CI Diff: ChangeLog | 4 + MAINTAINERS| 2 + contrib/ChangeLog | 5 + gcc/ChangeLog | 410 + gcc/DATESTAMP | 2 +- gcc/Makefile.in| 7 + gcc/attribs.cc | 10 - gcc/c-family/ChangeLog | 20 + gcc/c-family/c-ada-spec.cc | 3 +- gcc/c-family/c-format.cc | 12 +- gcc/c-family/c-opts.cc | 5 + gcc/c-family/c.opt | 4 + gcc/c/ChangeLog| 19 + gcc/c/c-decl.cc| 4 +- gcc/c/c-typeck.cc | 12 +- gcc/cfgexpand.cc | 24 +- gcc/config/aarch64/aarch64-sys-regs.def| 85 +++ gcc/config/aarch64/aarch64.cc | 127 ++-- gcc/config/aarch64/aarch64.h | 20 + gcc/config/avr/avr-mcus.def| 4 +- gcc/config/avr/gen-avr-mmcu-specs.cc | 158 ++--- gcc/config/avr/specs.h | 7 +- gcc/config/i386/constraints.md | 36 +- gcc/config/i386/darwin.h | 3 +- gcc/config/i386/darwin32-biarch.h | 3 - gcc/config/i386/darwin64-biarch.h | 3 - gcc/config/i386/i386-features.cc | 42 +- gcc/config/i386/i386-protos.h | 1 - gcc/config/i386/i386.cc| 27 +- gcc/config/i386/i386.md| 129 ++-- gcc/config/i386/predicates.md | 65 ++ gcc/config/riscv/riscv-c.cc| 3 +- gcc/config/riscv/riscv-protos.h| 2 +- gcc/config/riscv/riscv-vector-builtins-shapes.cc | 17 +- gcc/config/riscv/riscv-vector-builtins.cc | 24 +- gcc/config/riscv/riscv-vsetvl.cc | 9 +- gcc/configure | 2 +- gcc/configure.ac | 2 +- gcc/cp/ChangeLog | 85 +++ gcc/cp/class.cc| 14 +- gcc/cp/constexpr.cc| 10 + gcc/cp/coroutines.cc | 4 +- gcc/cp/cp-tree.h | 3 +- gcc/cp/except.cc | 33 +- gcc/cp/method.cc | 7 +- gcc/cp/module.cc | 12 +- gcc/cp/parser.cc | 46 +- gcc/cp/pt.cc | 42 +- gcc/cp/semantics.cc| 7 +- gcc/cp/tree.cc | 5 +- gcc/d/d-builtins.cc| 31 +- gcc/d/d-codegen.cc | 15 +- gcc/d/decl.cc | 22 +- gcc/d/dmd/MERGE| 2 +- gcc/d/dmd/aggregate.d | 2 +- gcc/d/dmd/aggregate.h | 1 + gcc/d/dmd/astcodegen.d | 1 + gcc/d/dmd/astenums.d | 2 +- gcc/d/dmd/clone.d | 17 +- gcc/d/dmd/constfold.d | 2 +- gcc/d/dmd/dcast.d | 87 ++- gcc/d/dmd/declaration.d| 4 +- gcc/d/dmd/declaration.h| 2 - gcc/d/dmd/dinterpret.d | 2 +- gcc/d/dmd/dsymbol.h| 2 - gcc/d/dmd/dsymbolsem.d | 2 +- gcc/d/dmd/errors.h | 2 - gcc/d/dmd/expression.h | 10 +- gcc/d/dmd/expressionsem.d | 34 +- gcc/d/dmd/func.d | 11 +- gcc/d/dmd/hdrgen.h | 8 + gcc/d/dmd/init.h | 1 + gcc/d/dmd/mtype.d | 112 +--- gcc/d/dmd/mtype.h | 6 +- gcc/d/dmd/parse.d | 2 +- gcc/d/dmd/statement.h | 5 + gcc/d/dmd/template.h | 3 + gcc/d/dmd/typesem.d
[gcc(refs/users/egallager/heads/CI)] Merge branch 'gcc-mirror:master' into me/CI
https://gcc.gnu.org/g:407eabd4ac5221a29b0a024e07161cc61fecb7c7 commit 407eabd4ac5221a29b0a024e07161cc61fecb7c7 Merge: daab033be527 a28046e21530 Author: Eric Gallager Date: Sun Jul 7 16:23:30 2024 -0400 Merge branch 'gcc-mirror:master' into me/CI Diff: ChangeLog |64 + MAINTAINERS|13 +- Makefile.in| 3 + Makefile.tpl | 3 + configure | 154 + configure.ac |41 + fixincludes/ChangeLog |12 + fixincludes/fixincl.x |14 +- fixincludes/inclhack.def |13 +- fixincludes/tests/base/math.h |11 - gcc/ChangeLog | 3815 + gcc/DATESTAMP | 2 +- gcc/Makefile.in| 8 +- gcc/ada/ChangeLog | 1458 ++ gcc/ada/Makefile.rtl | 3 + gcc/ada/accessibility.adb |19 +- gcc/ada/ali.adb|11 +- gcc/ada/ali.ads| 6 + gcc/ada/aspects.ads| 116 +- gcc/ada/atree.ads |10 +- gcc/ada/bcheck.adb |10 +- gcc/ada/bindgen.adb|20 +- gcc/ada/checks.adb |42 +- gcc/ada/contracts.adb |46 +- gcc/ada/csets.adb |46 +- gcc/ada/csets.ads |14 +- gcc/ada/debug.adb |23 +- gcc/ada/doc/gnat_rm/gnat_language_extensions.rst | 107 +- gcc/ada/doc/gnat_rm/implementation_advice.rst |15 +- .../doc/gnat_rm/implementation_defined_aspects.rst |20 +- .../gnat_rm/implementation_defined_attributes.rst |30 - .../implementation_defined_characteristics.rst | 4 +- .../doc/gnat_rm/implementation_defined_pragmas.rst |59 +- ...ard_and_implementation_defined_restrictions.rst |10 +- .../building_executable_programs_with_gnat.rst |44 +- .../doc/gnat_ugn/the_gnat_compilation_model.rst| 4 + gcc/ada/einfo-utils.adb|33 +- gcc/ada/einfo-utils.ads| 1 + gcc/ada/einfo.ads |84 +- gcc/ada/errout.adb | 159 +- gcc/ada/erroutc.adb|71 +- gcc/ada/erroutc.ads|18 - gcc/ada/errutil.adb|34 +- gcc/ada/exp_aggr.adb | 163 +- gcc/ada/exp_atag.adb |41 +- gcc/ada/exp_atag.ads | 4 +- gcc/ada/exp_attr.adb |74 +- gcc/ada/exp_ch11.adb | 2 +- gcc/ada/exp_ch3.adb| 162 +- gcc/ada/exp_ch4.adb| 402 +- gcc/ada/exp_ch5.adb| 133 +- gcc/ada/exp_ch6.adb|69 +- gcc/ada/exp_ch7.adb| 288 +- gcc/ada/exp_ch9.adb| 272 +- gcc/ada/exp_disp.adb |59 +- gcc/ada/exp_put_image.adb |17 +- gcc/ada/exp_util.adb | 278 +- gcc/ada/exp_util.ads |61 +- gcc/ada/expander.ads | 6 +- gcc/ada/freeze.adb | 604 +- gcc/ada/freeze.ads |13 +- gcc/ada/gcc-interface/Make-lang.in |22 +- gcc/ada/gcc-interface/Makefile.in | 6 - gcc/ada/gcc-interface/cuintp.cc|66 +- gcc/ada/gcc-interface/decl.cc |63 +- gcc/ada/gcc-interface/gigi.h | 7 +- gcc/ada/gcc-interface/misc.cc |20 +- gcc/ada/gcc-interface/trans.cc |60 +- gcc/ada/gcc-interface/utils.cc | 144 +- gcc/ada/gcc-interface/utils2.cc| 228 +- gcc/ada/gen_il-fields.ads | 3 + gcc/ada/gen_il-gen-gen_entities.adb| 3 + gcc/ada/gen_il-gen-gen_nodes.adb | 3 +- gcc/ada/ghost.adb | 8 +- gcc/ada/gnat1drv.adb |22 +- gcc/ada/gnat_rm.texi
[gcc(refs/users/egallager/heads/CI)] Merge branch 'gcc-mirror:master' into me/CI
https://gcc.gnu.org/g:12281baa3f02521c9ded0c55b42e94a07b80f9b7 commit 12281baa3f02521c9ded0c55b42e94a07b80f9b7 Merge: a90e7b4b5280 4e3c8257304c Author: Eric Gallager Date: Sat Apr 6 20:19:19 2024 -0400 Merge branch 'gcc-mirror:master' into me/CI Diff: ChangeLog | 30 + MAINTAINERS|7 +- Makefile.in| 33 + Makefile.tpl | 26 +- config/ChangeLog |5 + config/lcmessage.m4|4 +- contrib/ChangeLog | 24 + contrib/dg-extract-results.sh | 17 +- contrib/gcc_update |8 + contrib/test_mklog.py |2 +- contrib/unicode/gen_libstdcxx_unicode_data.py |6 +- gcc/ChangeLog | 2333 + gcc/DATESTAMP |2 +- gcc/ada/ChangeLog |6 + gcc/ada/exp_ch4.adb|6 +- gcc/analyzer/ChangeLog | 214 ++ gcc/analyzer/access-diagram.cc | 600 ++-- gcc/analyzer/access-diagram.h | 38 +- gcc/analyzer/analyzer-selftests.cc |1 + gcc/analyzer/analyzer-selftests.h |2 +- gcc/analyzer/analyzer.h| 11 +- gcc/analyzer/bounds-checking.cc| 148 +- gcc/analyzer/call-summary.cc | 13 + gcc/analyzer/constraint-manager.cc | 14 +- gcc/analyzer/diagnostic-manager.cc |2 +- gcc/analyzer/engine.cc |7 + gcc/analyzer/kf.cc | 157 +- gcc/analyzer/record-layout.cc |1 + gcc/analyzer/region-model-manager.cc | 164 +- gcc/analyzer/region-model-manager.h|7 +- gcc/analyzer/region-model.cc | 94 +- gcc/analyzer/region.cc | 67 +- gcc/analyzer/region.h |3 + gcc/analyzer/sm-malloc.cc | 31 + gcc/analyzer/sm-taint.cc | 58 +- gcc/analyzer/svalue.cc | 156 +- gcc/analyzer/svalue.h | 49 +- gcc/asan.cc| 40 +- gcc/auto-profile.cc|1 - gcc/bb-reorder.cc |6 +- gcc/btfout.cc | 30 +- gcc/builtins.cc| 14 +- gcc/c-family/ChangeLog | 42 + gcc/c-family/c-common.cc | 36 +- gcc/c-family/c-omp.cc | 51 +- gcc/c-family/c-pretty-print.cc |2 + gcc/c-family/c-warn.cc |1 - gcc/c-family/c.opt |4 + gcc/c-family/c.opt.urls| 352 +- gcc/c/ChangeLog| 23 + gcc/c/c-objc-common.cc | 23 + gcc/c/c-objc-common.h |3 + gcc/c/c-parser.cc | 68 +- gcc/c/c-tree.h |1 + gcc/cfganal.cc | 15 +- gcc/cfgloopmanip.cc|2 +- gcc/cgraph.h |6 + gcc/cgraphunit.cc |2 + gcc/collect2.cc|7 +- gcc/combine.cc | 28 +- gcc/common.opt | 11 +- gcc/common.opt.urls| 10 +- gcc/common/config/i386/cpuinfo.h | 16 + gcc/common/config/i386/i386-common.cc |6 +- gcc/common/config/i386/i386-cpuinfo.h |2 + gcc/common/config/riscv/riscv-common.cc| 139 +- gcc/config.gcc | 40 +- gcc/config/aarch64/aarch64-c.cc|4 +- gcc/config/aarch64/aarch64-cores.def |4 +- gcc/config/aarch64/aarch64-early-ra.cc | 20 +- gcc/config/aarch64/aarch64-feature-deps.h |3 + gcc/config/aarch64/aarch64-ldp-fusion.cc |2 +- gcc/config/aarch64/aarch64-option-extensions.def | 22 +- gcc/config/aarch64/aarch64-sme.md | 70 - gcc/config/aarch64/aarch64-sve-builtins-base.cc| 50 +- gcc/config/aarch64/aarch64-sve-builtins.cc | 16 + gcc/config/aarch64/aarch64-sve-builtin
[gcc(refs/users/egallager/heads/CI)] Merge branch 'gcc-mirror:master' into me/CI
https://gcc.gnu.org/g:11b6e08fa680736f27e62d6507db446f46e013e6 commit 11b6e08fa680736f27e62d6507db446f46e013e6 Merge: 12281baa3f02 b909daa5b673 Author: Eric Gallager Date: Mon Apr 22 18:23:06 2024 -0400 Merge branch 'gcc-mirror:master' into me/CI Diff: ChangeLog |16 + config/ChangeLog | 9 + config/acx.m4 |10 + configure |80 + configure.ac |30 + contrib/ChangeLog |18 + contrib/check-params-in-docs.py|19 +- contrib/config-list.mk | 3 +- contrib/gcc-changelog/git_update_version.py| 3 +- gcc/ChangeLog | 959 ++ gcc/DATESTAMP | 2 +- gcc/ada/ChangeLog | 9 + .../doc/gnat_rm/implementation_defined_aspects.rst |12 + .../doc/gnat_rm/implementation_defined_pragmas.rst |18 + gcc/ada/gnat_rm.texi | 1649 +- gcc/ada/gnat_ugn.texi | 4 +- gcc/analyzer/ChangeLog |69 + gcc/analyzer/access-diagram.cc | 4 + gcc/analyzer/analyzer.opt | 2 +- gcc/analyzer/call-details.cc |33 +- gcc/analyzer/infinite-loop.cc |22 + gcc/analyzer/infinite-recursion.cc |13 + gcc/analyzer/program-state.cc | 4 +- gcc/analyzer/ranges.cc |15 + gcc/analyzer/ranges.h | 4 + gcc/analyzer/region-model.cc | 6 +- gcc/analyzer/region.cc | 2 +- gcc/analyzer/sm-taint.cc |15 +- gcc/analyzer/store.cc |20 +- gcc/asan.cc|29 +- gcc/attribs.cc | 7 +- gcc/btfout.cc | 141 +- gcc/c-family/ChangeLog |20 + gcc/c-family/c-common.cc | 1 + gcc/c-family/c.opt | 4 + gcc/c-family/c.opt.urls| 3 + gcc/c/ChangeLog|31 + gcc/c/c-decl.cc|53 +- gcc/c/c-typeck.cc | 4 +- gcc/combine.cc |27 +- gcc/common/config/i386/i386-common.cc | 2 +- gcc/config.gcc |23 +- gcc/config/aarch64/aarch64-arches.def | 2 +- gcc/config/aarch64/aarch64-c.cc| 6 +- gcc/config/aarch64/aarch64-gnu.h |68 + gcc/config/aarch64/aarch64-option-extensions.def |73 +- gcc/config/aarch64/aarch64-protos.h| 6 +- gcc/config/aarch64/aarch64-sve-builtins-base.cc| 2 +- gcc/config/aarch64/aarch64-sve-builtins.cc |88 +- gcc/config/aarch64/aarch64-sve-builtins.h |17 +- gcc/config/aarch64/aarch64.cc | 138 +- gcc/config/aarch64/aarch64.h | 3 +- gcc/config/aarch64/aarch64.md |23 +- gcc/config/aarch64/driver-aarch64.cc | 2 +- gcc/config/aarch64/t-aarch64-rtems |42 + gcc/config/avr/avr-mcus.def| 8 + gcc/config/avr/avr.cc |17 +- gcc/config/bpf/bpf-protos.h| 2 +- gcc/config/bpf/bpf.cc |54 +- gcc/config/bpf/bpf.md |56 +- gcc/config/bpf/constraints.md |20 + gcc/config/bpf/core-builtins.cc| 128 +- gcc/config/bpf/core-builtins.h | 2 + gcc/config/bpf/predicates.md | 7 +- gcc/config/darwin.h| 2 +- gcc/config/gcn/gcn.cc |14 +- gcc/config/gcn/gcn.opt |16 + gcc/config/gnu.h |16 + gcc/config/i386/gnu.h |11 - gcc/config/i386/i386-c.cc | 2 + gcc/config/i386/i386-options.cc| 2 +- gcc/config/i386/i386.md|46 +- gcc/config/i386/sse.md | 118 +- gcc/config/loongarch/loongarch-builtins.cc |25 +- gcc/config/loongarch/loongarch-def.cc |11 +- gcc/config/loongarch/loongarch-opts.cc
[gcc/egallager/heads/master] (1361 commits) Merge branch 'gcc-mirror:master' into me/master
The branch 'egallager/heads/master' was updated to point to:
2e9f317e1fd9... Merge branch 'gcc-mirror:master' into me/master
It previously pointed to:
68dbebb95d94... Merge branch 'gcc-mirror:master' into me/master
Diff:
Summary of changes (added commits):
---
2e9f317... Merge branch 'gcc-mirror:master' into me/master
3cde331... RISC-V: Add missing mode_idx for vrol and vror (*)
fe5f652... Match: Support form 1 for scalar signed integer .SAT_ADD (*)
beb94f5... Fix PR testsuite/116271, gcc.dg/vect/tsvc/vect-tsvc-s176.c (*)
3989e31... RISC-V: Add testcases for unsigned scalar .SAT_SUB IMM form (*)
cb0b8b6... RISC-V: Add testcases for unsigned scalar .SAT_SUB IMM form (*)
ef84d2f... Daily bump. (*)
ffb00a0... Fix test failing on sparc (*)
48032f2... Update gcc zh_CN.po (*)
ff0cba2... c++/coroutines: fix actor cases not being added to the curr (*)
a83e519... m68k: Accept ASHIFT like MULT in address operand (*)
02dff52... c++: Don't show constructor internal name in error message (*)
691f682... RISC-V: Move helper functions above expand_const_vector (*)
1cd8902... RISC-V: Allow non-duplicate bool patterns in expand_const_v (*)
282bbc9... RISC-V: Handle 0.0 floating point pattern costing to match (*)
771256b... RISC-V: Emit costs for bool and stepped const vectors (*)
a3dc5d2... RISC-V: Handle case when constant vector construction targe (*)
ac1f3a8... RISC-V: Reorder insn cost match order to match correspondin (*)
c89038c... RISC-V: Fix vid const vector expander for non-npatterns siz (*)
37c21d4... arm: Always use vmov.f64 instead of vmov.f32 with MVE (*)
ee98612... pr116174.c: Add the missing */ (*)
d6bb1e2... Extend check-function-bodies to allow label and directives (*)
e223ac9... LRA: Fix setup_sp_offset (*)
5427738... LRA: Don't use 0 as initialization for sp_offset (*)
359209b... final: go down ASHIFT in walk_alter_subreg (*)
75ef216... libstdc++: Do not use std::vector::reference default (*)
470a278... c++: Add most missing C++20 and C++23 names to cxxapi-data. (*)
ff4aa45... c++: Add correct copyright dates to output of gen-cxxapi-fi (*)
442e3cd... testsuite: Fix ending of comment in test cases (*)
2daf618... Un-XFAIL 'gcc.dg/signbit-5.c' for GCN (*)
708ee71... Handle arithmetic on eliminated address indices [PR116413] (*)
9db997e... lra: Don't apply eliminations to allocated registers [PR116 (*)
8d6d6c8... c++, coroutines: The frame pointer is used in the helpers [ (*)
172637c... tree-optimization/116460 - ICE with DCE in forwprop (*)
103127c... Fix another inline7.c test failure on sparc targets (*)
a1062b0... RISC-V: Support IMM for operand 1 of ussub pattern (*)
215ff99... c++/modules: Fix include translation for already-seen heade (*)
9860834... c++/modules: Clean up include translation [PR110980] (*)
9522fc8... MIPS: Include missing mips16.S in libgcc/lib1funcs.S (*)
5031df5... combine.cc (make_more_copies): Copy attributes from the ori (*)
5cca751... c++/coros: do not assume coros don't nest [PR113457] (*)
c73d7f3... coroutines: diagnose usage of alloca in coroutines (*)
92c5265... diagnostics: move output formats from diagnostic.{c,h} to t (*)
ac707d3... diagnostics: consolidate on_{begin,end}_diagnostic into on_ (*)
6a1c359... testsuite: add event IDs to multithreaded event plugin test (*)
aa3b950... testsuite: generalize support for Python tests for SARIF ou (*)
276cc43... pretty-print: fixes to selftests (*)
b835710... json.h: fix typo in comment (*)
26ee954... c++: Check template parameters in member class template spe (*)
cc372be... Remove an unneeded include that was added by mistake. (*)
eb63f95... Fix bootstap-errors due to enabling -gvariable-location-vie (*)
a8260eb... libcpp: deduplicate definition of padding size (*)
0ceeb99... tree-optimization/116460 - improve forwprop compile-time (*)
03b802e... Delay edge removal in forwprop (*)
d3e71b9... vect: Fix STMT_VINFO_DEF_TYPE check for odd/even widen mult (*)
3b78aa3... Match: Add int type fits check for .SAT_ADD imm operand (*)
53b86ca... expand: Use the correct mode for store flags for popcount [ (*)
b4ac2c2... i386: Add bf8 -> fp16 intrin (*)
576bd30... AVX10.2: Support compare instructions (*)
f6fe296... AVX10.2: Support vector copy instructions (*)
889f6dd... AVX10.2: Support minmax instructions (*)
3a97ce1... [PATCH 2/2] AVX10.2: Support saturating convert instruction (*)
e2c80d2... [PATCH 1/2] AVX10.2: Support saturating convert instruction (*)
5cb67dd... [PATCH 2/2] AVX10.2: Support BF16 instructions (*)
9023662... [PATCH 1/2] AVX10.2: Support BF16 instructions (*)
2a04611... AVX10.2: Support convert instructions (*)
af0a062... [PATCH 2/2] AVX10.2: Support media instructions (*)
8db80b2... [PATCH 1/2] AVX10.2: Support media instructions (*)
cba4566... i386: Refactor m512-check.h (*)
17be009... RISC-V: Support IMM for operand 0 of ussub pattern (*)
