date:20240821

[gcc r15-3062] Fortran: Fix ICE in sizeof(coarray) [PR77518]

2024-08-21 Thread Andre Vehreschild via Gcc-cvs

https://gcc.gnu.org/g:515730fd65a03c5f92f9ab6438d023aee8cfbecf

commit r15-3062-g515730fd65a03c5f92f9ab6438d023aee8cfbecf
Author: Andre Vehreschild 
Date:   Thu Jul 18 14:53:31 2024 +0200

Fortran: Fix ICE in sizeof(coarray) [PR77518]

Use se's class_container where present in sizeof().

PR fortran/77518

gcc/fortran/ChangeLog:

* trans-intrinsic.cc (gfc_conv_intrinsic_sizeof): Use
class_container of se when set.

gcc/testsuite/ChangeLog:

* gfortran.dg/coarray/sizeof_1.f90: New test.

Diff:
---
 gcc/fortran/trans-intrinsic.cc | 13 ++---
 gcc/testsuite/gfortran.dg/coarray/sizeof_1.f90 | 27 ++
 2 files changed, 37 insertions(+), 3 deletions(-)

diff --git a/gcc/fortran/trans-intrinsic.cc b/gcc/fortran/trans-intrinsic.cc
index fd2da4638252..0ecb04397783 100644
--- a/gcc/fortran/trans-intrinsic.cc
+++ b/gcc/fortran/trans-intrinsic.cc
@@ -8216,10 +8216,17 @@ gfc_conv_intrinsic_sizeof (gfc_se *se, gfc_expr *expr)
   else if (arg->rank > 0
   || (arg->rank == 0
   && arg->ref && arg->ref->type == REF_COMPONENT))
-   /* The scalarizer added an additional temp.  To get the class' vptr
-  one has to look at the original backend_decl.  */
-   byte_size = gfc_class_vtab_size_get (
+   {
+ /* The scalarizer added an additional temp.  To get the class' vptr
+one has to look at the original backend_decl.  */
+ if (argse.class_container)
+   byte_size = gfc_class_vtab_size_get (argse.class_container);
+ else if (DECL_LANG_SPECIFIC (arg->symtree->n.sym->backend_decl))
+   byte_size = gfc_class_vtab_size_get (
  GFC_DECL_SAVED_DESCRIPTOR (arg->symtree->n.sym->backend_decl));
+ else
+   gcc_unreachable ();
+   }
   else
gcc_unreachable ();
 }
diff --git a/gcc/testsuite/gfortran.dg/coarray/sizeof_1.f90 
b/gcc/testsuite/gfortran.dg/coarray/sizeof_1.f90
new file mode 100644
index ..b26f84164068
--- /dev/null
+++ b/gcc/testsuite/gfortran.dg/coarray/sizeof_1.f90
@@ -0,0 +1,27 @@
+!{ dg-do run }
+
+! Check that pr77518 is fixed.
+! Based on code by Gerhard Steinmetz  
+
+program coarray_sizeof_1
+  type t
+  end type
+  type t2
+integer :: v = 42
+  end type
+  type t3
+type(t2) :: s
+integer :: n = 1
+  end type
+
+  class(t), allocatable :: z[:]
+  class(t2), allocatable :: z2[:]
+  class(t3), allocatable :: z3[:]
+
+  if (sizeof(z) /= 0) stop 1
+  if (sizeof(z2) /= sizeof(integer)) stop 2
+  allocate(z3[*])
+  if (sizeof(z3) /= sizeof(z2) + sizeof(integer)) stop 3
+  if (sizeof(z3%s) /= sizeof(z2)) stop 4
+end
+

[gcc r15-3063] testsuite: i386: Fix g++.target/i386/pr116275-2.C on Solaris/x86

2024-08-21 Thread Rainer Orth via Gcc-cvs

https://gcc.gnu.org/g:cc8fc9850d1a4b614da104cfecd4c2368ee03c98

commit r15-3063-gcc8fc9850d1a4b614da104cfecd4c2368ee03c98
Author: Rainer Orth 
Date:   Wed Aug 21 10:04:07 2024 +0200

testsuite: i386: Fix g++.target/i386/pr116275-2.C on Solaris/x86

The new g++.target/i386/pr116275-2.C test FAILs on 32-bit Solaris/x86:

FAIL: g++.target/i386/pr116275-2.C   scan-assembler vpslld

This happens because Solaris defaults to -mstackrealign, disabling -mstv.

Fixed by disabling the former and enabling the latter.

Tested on i386-pc-solaris2.11 and x86_64-pc-linux-gnu.

2024-08-20  Rainer Orth  

gcc/testsuite:
* g++.target/i386/pr116275-2.C (dg-options): Add -mstv
-mno-stackrealign.

Diff:
---
 gcc/testsuite/g++.target/i386/pr116275-2.C | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/testsuite/g++.target/i386/pr116275-2.C 
b/gcc/testsuite/g++.target/i386/pr116275-2.C
index 98d3c19e59c8..9c571fda01f5 100644
--- a/gcc/testsuite/g++.target/i386/pr116275-2.C
+++ b/gcc/testsuite/g++.target/i386/pr116275-2.C
@@ -1,5 +1,5 @@
 /* { dg-do compile { target ia32 } } */
-/* { dg-options "-O2 -mavx -mno-avx512vl -std=c++11" } */
+/* { dg-options "-O2 -mavx -mno-avx512vl -mstv -mno-stackrealign -std=c++11" } 
*/
 
 struct SymbolDesc push_back(SymbolDesc);
 struct SymbolDesc {

[gcc r15-3064] c++, coroutines: Check for malformed functions before splitting.

2024-08-21 Thread Iain D Sandoe via Gcc-cvs

https://gcc.gnu.org/g:3949b7c0a87475692d1727086bdccb8133c53497

commit r15-3064-g3949b7c0a87475692d1727086bdccb8133c53497
Author: Iain Sandoe 
Date:   Wed Aug 14 13:30:30 2024 +0100

c++, coroutines: Check for malformed functions before splitting.

This performs the same basic check that is done by finish_function
to catch cases where the function is so badly malformed that we
do not have a consistent binding level.

gcc/cp/ChangeLog:

* coroutines.cc (split_coroutine_body_from_ramp): Check
that the binding level is as expected before attempting
to outline the function body.

Signed-off-by: Iain Sandoe 

Diff:
---
 gcc/cp/coroutines.cc | 8 +++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/gcc/cp/coroutines.cc b/gcc/cp/coroutines.cc
index f7791cbfb9a6..7af2a1885615 100644
--- a/gcc/cp/coroutines.cc
+++ b/gcc/cp/coroutines.cc
@@ -4553,10 +4553,16 @@ coro_rewrite_function_body (location_t fn_start, tree 
fnbody, tree orig,
 static tree
 split_coroutine_body_from_ramp (tree fndecl)
 {
-  tree body;
+  /* Sanity-check and punt if we have a nonsense tree because of earlier
+ parse errors, perhaps.  */
+  if (!current_binding_level
+  || current_binding_level->kind != sk_function_parms)
+return NULL_TREE;
+
   /* Once we've tied off the original user-authored body in fn_body.
  Start the replacement synthesized ramp body.  */
 
+  tree body;
   if (use_eh_spec_block (fndecl))
 {
   body = pop_stmt_list (TREE_OPERAND (current_eh_spec_block, 0));

[gcc r15-3065] libstdc++: Fix std::variant to reject array types [PR116381]

2024-08-21 Thread Jonathan Wakely via Libstdc++-cvs

https://gcc.gnu.org/g:1e10b3b8825ee398f077500af6ae1f5db180983a

commit r15-3065-g1e10b3b8825ee398f077500af6ae1f5db180983a
Author: Jonathan Wakely 
Date:   Tue Aug 20 16:52:22 2024 +0100

libstdc++: Fix std::variant to reject array types [PR116381]

libstdc++-v3/ChangeLog:

PR libstdc++/116381
* include/std/variant (variant): Fix conditions for
static_assert to match the spec.
* testsuite/20_util/variant/types_neg.cc: New test.

Diff:
---
 libstdc++-v3/include/std/variant|  6 ++
 libstdc++-v3/testsuite/20_util/variant/types_neg.cc | 17 +
 2 files changed, 19 insertions(+), 4 deletions(-)

diff --git a/libstdc++-v3/include/std/variant b/libstdc++-v3/include/std/variant
index 12108d07f0b1..5fb7770d8891 100644
--- a/libstdc++-v3/include/std/variant
+++ b/libstdc++-v3/include/std/variant
@@ -1457,10 +1457,8 @@ namespace __detail::__variant
 
   static_assert(sizeof...(_Types) > 0,
"variant must have at least one alternative");
-  static_assert(!(std::is_reference_v<_Types> || ...),
-   "variant must have no reference alternative");
-  static_assert(!(std::is_void_v<_Types> || ...),
-   "variant must have no void alternative");
+  static_assert(((std::is_object_v<_Types> && !is_array_v<_Types>) && ...),
+   "variant alternatives must be non-array object types");
 
   using _Base = __detail::__variant::_Variant_base<_Types...>;
 
diff --git a/libstdc++-v3/testsuite/20_util/variant/types_neg.cc 
b/libstdc++-v3/testsuite/20_util/variant/types_neg.cc
new file mode 100644
index ..5cd3d02154b6
--- /dev/null
+++ b/libstdc++-v3/testsuite/20_util/variant/types_neg.cc
@@ -0,0 +1,17 @@
+// { dg-do compile { target c++17 } }
+
+# include 
+
+std::variant<> v0; // { dg-error "here" }
+// { dg-error "must have at least one alternative" "" { target *-*-* } 0 }
+std::variant v1; // { dg-error "here" }
+std::variant v2; // { dg-error "here" }
+std::variant v3; // { dg-error "here" }
+std::variant v4; // { dg-error "here" }
+std::variant v5; // { dg-error "here" }
+std::variant v6; // { dg-error "here" }
+// { dg-error "must be non-array object types" "" { target *-*-* } 0 }
+
+// All of variant's base classes are instantiated before checking any
+// static_assert, so we get lots of errors before the expected errors above.
+// { dg-excess-errors "" }

[gcc r15-3066] Fix coarray rank for non-coarrays in derived types. [PR86468]

2024-08-21 Thread Andre Vehreschild via Gcc-cvs

https://gcc.gnu.org/g:723b30bee4e4fa3feba9ef03ce7dca95501e1555

commit r15-3066-g723b30bee4e4fa3feba9ef03ce7dca95501e1555
Author: Andre Vehreschild 
Date:   Fri Aug 16 15:07:39 2024 +0200

Fix coarray rank for non-coarrays in derived types. [PR86468]

The corank was propagated to array components in derived types.  Fix
this by setting a zero corank when the array component is not a pointer.
For pointer typed array components propagate the corank of the derived
type to allow associating the component to a coarray.

gcc/fortran/ChangeLog:

PR fortran/86468

* trans-intrinsic.cc (conv_intrinsic_move_alloc): Correct
comment.
* trans-types.cc (gfc_sym_type): Pass coarray rank, not false.
(gfc_get_derived_type): Only propagate  codimension for coarrays
and pointers to array components in derived typed coarrays.

gcc/testsuite/ChangeLog:

* gfortran.dg/coarray_lib_this_image_2.f90: Fix array rank in
tree dump scan.
* gfortran.dg/coarray_lib_token_4.f90: Same.
* gfortran.dg/coarray/move_alloc_2.f90: New test.

Diff:
---
 gcc/fortran/trans-intrinsic.cc |  2 +-
 gcc/fortran/trans-types.cc | 18 ---
 gcc/testsuite/gfortran.dg/coarray/move_alloc_2.f90 | 55 ++
 .../gfortran.dg/coarray_lib_this_image_2.f90   |  2 +-
 gcc/testsuite/gfortran.dg/coarray_lib_token_4.f90  |  4 +-
 5 files changed, 70 insertions(+), 11 deletions(-)

diff --git a/gcc/fortran/trans-intrinsic.cc b/gcc/fortran/trans-intrinsic.cc
index 0ecb04397783..0632e3e4d2fc 100644
--- a/gcc/fortran/trans-intrinsic.cc
+++ b/gcc/fortran/trans-intrinsic.cc
@@ -12906,7 +12906,7 @@ conv_intrinsic_move_alloc (gfc_code *code)
   gfc_add_expr_to_block (&block, tmp);
 }
 
-  /* Move the pointer and update the array descriptor data.  */
+  /* Copy the array descriptor data.  */
   gfc_add_modify_loc (input_location, &block, to_se.expr, from_se.expr);
 
   /* Set "from" to NULL.  */
diff --git a/gcc/fortran/trans-types.cc b/gcc/fortran/trans-types.cc
index bc582085f57f..38e18434f7c5 100644
--- a/gcc/fortran/trans-types.cc
+++ b/gcc/fortran/trans-types.cc
@@ -2386,7 +2386,7 @@ gfc_sym_type (gfc_symbol * sym, bool is_bind_c)
  else if (sym->attr.allocatable)
akind = GFC_ARRAY_ALLOCATABLE;
  type = gfc_build_array_type (type, sym->as, akind, restricted,
-  sym->attr.contiguous, false);
+  sym->attr.contiguous, sym->as->corank);
}
 }
   else
@@ -2909,12 +2909,16 @@ gfc_get_derived_type (gfc_symbol * derived, int codimen)
  else
akind = GFC_ARRAY_ALLOCATABLE;
  /* Pointers to arrays aren't actually pointer types.  The
-descriptors are separate, but the data is common.  */
- field_type = gfc_build_array_type (field_type, c->as, akind,
-!c->attr.target
-&& !c->attr.pointer,
-c->attr.contiguous,
-codimen);
+descriptors are separate, but the data is common.  Every
+array pointer in a coarray derived type needs to provide space
+for the coarray management, too.  Therefore treat coarrays
+and pointers to coarrays in derived types the same.  */
+ field_type = gfc_build_array_type
+   (
+ field_type, c->as, akind, !c->attr.target && !c->attr.pointer,
+ c->attr.contiguous,
+ c->attr.codimension || c->attr.pointer ? codimen : 0
+   );
}
  else
field_type = gfc_get_nodesc_array_type (field_type, c->as,
diff --git a/gcc/testsuite/gfortran.dg/coarray/move_alloc_2.f90 
b/gcc/testsuite/gfortran.dg/coarray/move_alloc_2.f90
new file mode 100644
index ..4a8e54ced6bf
--- /dev/null
+++ b/gcc/testsuite/gfortran.dg/coarray/move_alloc_2.f90
@@ -0,0 +1,55 @@
+!{ dg-do run }
+
+! Check gimplify with checking works. [PR86468]
+! This rather complicated code is needed to produce two "different"
+! types in the move_alloc.
+
+! Contributed by Juergen Reuter  
+
+module classes
+  implicit none
+  private
+  public :: wrapped_coarray
+  
+  type :: wrapped_point
+ integer, allocatable :: point(:)
+   contains
+ procedure :: add => wrapped_point_add
+  end type wrapped_point
+  
+  type :: wrapped_coarray
+ type(wrapped_point), allocatable :: caf(:)[:]
+  end type wrapped_coarray
+  
+contains
+  
+  subroutine wrapped_point_add(self, to_add)
+class(wrapped_point), intent(inout) :: self
+integer, intent(in) :: to_add
+integer, allocatable :: point(:)
+integer :: points_number
+

[gcc r15-3067] libstdc++: Check ios::uppercase for ios::fixed floating-point output [PR114862]

2024-08-21 Thread Jonathan Wakely via Libstdc++-cvs

https://gcc.gnu.org/g:878bb62cfc158b5324cc2b2476f92fb4237fd82a

commit r15-3067-g878bb62cfc158b5324cc2b2476f92fb4237fd82a
Author: Jonathan Wakely 
Date:   Wed May 8 10:03:20 2024 +0100

libstdc++: Check ios::uppercase for ios::fixed floating-point output 
[PR114862]

This is LWG 4084 which I filed recently. LWG seems to support making the
change, so that std::num_put can use the %F format for floating-point
numbers.

libstdc++-v3/ChangeLog:

PR libstdc++/114862
* src/c++98/locale_facets.cc (__num_base::_S_format_float):
Check uppercase flag for fixed format.
* testsuite/22_locale/num_put/put/char/lwg4084.cc: New test.

Diff:
---
 libstdc++-v3/src/c++98/locale_facets.cc| 13 +++---
 .../22_locale/num_put/put/char/lwg4084.cc  | 46 ++
 2 files changed, 54 insertions(+), 5 deletions(-)

diff --git a/libstdc++-v3/src/c++98/locale_facets.cc 
b/libstdc++-v3/src/c++98/locale_facets.cc
index fa469b1b8727..02f53fd5ec1c 100644
--- a/libstdc++-v3/src/c++98/locale_facets.cc
+++ b/libstdc++-v3/src/c++98/locale_facets.cc
@@ -84,17 +84,20 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
 
 if (__mod)
   *__fptr++ = __mod;
-// [22.2.2.2.2] Table 58
+// C++11 [facet.num.put.virtuals] Table 88
+// _GLIBCXX_RESOLVE_LIB_DEFECTS
+// 4084. std::fixed ignores std::uppercase
+bool __upper = __flags & ios_base::uppercase;
 if (__fltfield == ios_base::fixed)
-  *__fptr++ = 'f';
+  *__fptr++ = __upper ? 'F' : 'f';
 else if (__fltfield == ios_base::scientific)
-  *__fptr++ = (__flags & ios_base::uppercase) ? 'E' : 'e';
+  *__fptr++ = __upper ? 'E' : 'e';
 #if _GLIBCXX_USE_C99_STDIO
 else if (__fltfield == (ios_base::fixed | ios_base::scientific))
-  *__fptr++ = (__flags & ios_base::uppercase) ? 'A' : 'a';
+  *__fptr++ = __upper ? 'A' : 'a';
 #endif
 else
-  *__fptr++ = (__flags & ios_base::uppercase) ? 'G' : 'g';
+  *__fptr++ = __upper ? 'G' : 'g';
 *__fptr = '\0';
   }
 
diff --git a/libstdc++-v3/testsuite/22_locale/num_put/put/char/lwg4084.cc 
b/libstdc++-v3/testsuite/22_locale/num_put/put/char/lwg4084.cc
new file mode 100644
index ..b7c7da11f863
--- /dev/null
+++ b/libstdc++-v3/testsuite/22_locale/num_put/put/char/lwg4084.cc
@@ -0,0 +1,46 @@
+// { dg-do run }
+// LWG 4084. std::fixed ignores std::uppercase
+// PR libstdc++/114862 std::uppercase not applying to nan's and inf's
+
+#include 
+#include 
+#include 
+#include 
+
+void
+test_nan()
+{
+  std::ostringstream out;
+  double nan = std::numeric_limits::quiet_NaN();
+  out << std::fixed;
+  out << ' ' << nan << ' ' << -nan;
+  out << std::uppercase;
+  out << ' ' << nan << ' ' << -nan;
+  out << std::showpoint;
+  out << ' ' << nan << ' ' << -nan;
+  out << std::showpos;
+  out << ' ' << nan << ' ' << -nan;
+  VERIFY( out.str() == " nan -nan NAN -NAN NAN -NAN +NAN -NAN" );
+}
+
+void
+test_inf()
+{
+  std::ostringstream out;
+  double inf = std::numeric_limits::infinity();
+  out << std::fixed;
+  out << ' ' << inf << ' ' << -inf;
+  out << std::uppercase;
+  out << ' ' << inf << ' ' << -inf;
+  out << std::showpoint;
+  out << ' ' << inf << ' ' << -inf;
+  out << std::showpos;
+  out << ' ' << inf << ' ' << -inf;
+  VERIFY( out.str() == " inf -inf INF -INF INF -INF +INF -INF" );
+}
+
+int main()
+{
+  test_nan();
+  test_inf();
+}

[gcc r15-3068] libstdc++: Use strlen for std::char_traits::length [PR102958]

2024-08-21 Thread Jonathan Wakely via Libstdc++-cvs

https://gcc.gnu.org/g:fd7dabc116b9abc40ee6aa25bcc5d240b8cc516a

commit r15-3068-gfd7dabc116b9abc40ee6aa25bcc5d240b8cc516a
Author: Jonathan Wakely 
Date:   Tue Jan 9 16:19:20 2024 +

libstdc++: Use strlen for std::char_traits::length [PR102958]

libstdc++-v3/ChangeLog:

PR tree-optimization/102958
* include/bits/char_traits.h (char_traits::length): Use
strlen.

Diff:
---
 libstdc++-v3/include/bits/char_traits.h | 5 +
 1 file changed, 1 insertion(+), 4 deletions(-)

diff --git a/libstdc++-v3/include/bits/char_traits.h 
b/libstdc++-v3/include/bits/char_traits.h
index 3074e9bb77e2..ac3e43e34b96 100644
--- a/libstdc++-v3/include/bits/char_traits.h
+++ b/libstdc++-v3/include/bits/char_traits.h
@@ -651,10 +651,7 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
if (std::__is_constant_evaluated())
  return __gnu_cxx::char_traits::length(__s);
 #endif
-   size_t __i = 0;
-   while (!eq(__s[__i], char_type()))
- ++__i;
-   return __i;
+   return __builtin_strlen((const char*)__s);
   }
 
   static _GLIBCXX17_CONSTEXPR const char_type*

[gcc r15-3069] tree-optimization/116380 - bogus SSA update with loop distribution

2024-08-21 Thread Richard Biener via Gcc-cvs

https://gcc.gnu.org/g:af0d2d95a5f767d92bd64f959679fb4612247b0b

commit r15-3069-gaf0d2d95a5f767d92bd64f959679fb4612247b0b
Author: Richard Biener 
Date:   Wed Aug 21 13:56:40 2024 +0200

tree-optimization/116380 - bogus SSA update with loop distribution

When updating LC PHIs after copying loops we have to handle defs
defined outside of the loop appropriately (by not setting them to
NULL ...).  This mimics how we handle this in the SSA updating
code of the vectorizer.

PR tree-optimization/116380
* tree-loop-distribution.cc (copy_loop_before): Handle
out-of-loop defs appropriately.

* gcc.dg/torture/pr116380.c: New testcase.

Diff:
---
 gcc/testsuite/gcc.dg/torture/pr116380.c | 16 
 gcc/tree-loop-distribution.cc   |  3 +++
 2 files changed, 19 insertions(+)

diff --git a/gcc/testsuite/gcc.dg/torture/pr116380.c 
b/gcc/testsuite/gcc.dg/torture/pr116380.c
new file mode 100644
index ..5ffd99459d26
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/torture/pr116380.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-fno-tree-scev-cprop" } */
+
+int a[3], d[3], c;
+int f(int e, int b)
+{
+  for (; e < 3; e++)
+{
+  a[0] = 0;
+  if (b)
+   c = b;
+  d[e] = 0;
+  a[e] = 0;
+}
+  return e;
+}
diff --git a/gcc/tree-loop-distribution.cc b/gcc/tree-loop-distribution.cc
index f87393ee94d6..10f261a8769b 100644
--- a/gcc/tree-loop-distribution.cc
+++ b/gcc/tree-loop-distribution.cc
@@ -980,6 +980,9 @@ copy_loop_before (class loop *loop, bool 
redirect_lc_phi_defs)
  if (TREE_CODE (USE_FROM_PTR (use_p)) == SSA_NAME)
{
  tree new_def = get_current_def (USE_FROM_PTR (use_p));
+ if (!new_def)
+   /* Something defined outside of the loop.  */
+   continue;
  SET_USE (use_p, new_def);
}
}

[gcc r15-3070] sra: Avoid risking x87 magling binary representation of a replacement (PR 58416)

2024-08-21 Thread Martin Jambor via Gcc-cvs

https://gcc.gnu.org/g:f577959f420ae404f99f630dadc1c0370734d0da

commit r15-3070-gf577959f420ae404f99f630dadc1c0370734d0da
Author: Martin Jambor 
Date:   Wed Aug 21 14:49:11 2024 +0200

sra: Avoid risking x87 magling binary representation of a replacement (PR 
58416)

PR 58416 shows that storing non-floating point data to floating point
scalar registers can lead to miscompilations when the data is
normalized or otherwise processed upon loading to a register.  To
avoid that risk, this patch detects situations where we have multiple
types and a we decide to represent the data in a type with a mode that
is known to not be able to transfer actual bits reliably using the new
TARGET_MODE_CAN_TRANSFER_BITS hook.

gcc/ChangeLog:

2024-08-19  Martin Jambor  

PR target/58416
* tree-sra.cc (types_risk_mangled_binary_repr_p): New function.
(sort_and_splice_var_accesses): Use it.
(propagate_subaccesses_from_rhs): Likewise.

gcc/testsuite/ChangeLog:

2024-08-19  Martin Jambor  

PR target/58416
* gcc.dg/torture/pr58416.c: New test.

Diff:
---
 gcc/testsuite/gcc.dg/torture/pr58416.c | 32 
 gcc/tree-sra.cc| 28 +++-
 2 files changed, 59 insertions(+), 1 deletion(-)

diff --git a/gcc/testsuite/gcc.dg/torture/pr58416.c 
b/gcc/testsuite/gcc.dg/torture/pr58416.c
new file mode 100644
index ..0922b0e70890
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/torture/pr58416.c
@@ -0,0 +1,32 @@
+/* { dg-do run } */
+
+struct s {
+  char s[sizeof(long double)];
+};
+
+union u {
+  long double d;
+  struct s s;
+};
+
+int main()
+{
+  union u x = {0};
+#if __SIZEOF_LONG_DOUBLE__ == 16
+  x.s = (struct s){""};
+#elif __SIZEOF_LONG_DOUBLE__ == 12
+  x.s = (struct s){""};
+#elif __SIZEOF_LONG_DOUBLE__ == 8
+  x.s = (struct s){""};
+#elif __SIZEOF_LONG_DOUBLE__ == 4
+  x.s = (struct s){""};
+#endif
+
+  union u y = x;
+
+  for (unsigned char *p = (unsigned char *)&y + sizeof y;
+   p-- > (unsigned char *)&y;)
+if (*p != (unsigned char)'x')
+  __builtin_abort ();
+  return 0;
+}
diff --git a/gcc/tree-sra.cc b/gcc/tree-sra.cc
index 8040b0c56451..64e2f007d680 100644
--- a/gcc/tree-sra.cc
+++ b/gcc/tree-sra.cc
@@ -2335,6 +2335,19 @@ same_access_path_p (tree exp1, tree exp2)
   return true;
 }
 
+/* Return true when either T1 is a type that, when loaded into a register and
+   stored back to memory will yield the same bits or when both T1 and T2 are
+   compatible.  */
+
+static bool
+types_risk_mangled_binary_repr_p (tree t1, tree t2)
+{
+  if (mode_can_transfer_bits (TYPE_MODE (t1)))
+return false;
+
+  return !types_compatible_p (t1, t2);
+}
+
 /* Sort all accesses for the given variable, check for partial overlaps and
return NULL if there are any.  If there are none, pick a representative for
each combination of offset and size and create a linked list out of them.
@@ -2461,6 +2474,17 @@ sort_and_splice_var_accesses (tree var)
}
  unscalarizable_region = true;
}
+ else if (types_risk_mangled_binary_repr_p (access->type, ac2->type))
+   {
+ if (dump_file && (dump_flags & TDF_DETAILS))
+   {
+ fprintf (dump_file, "Cannot scalarize the following access "
+  "because data would be held in a mode which is not "
+  "guaranteed to preserve all bits.\n  ");
+ dump_access (dump_file, access, false);
+   }
+ unscalarizable_region = true;
+   }
 
  if (grp_same_access_path
  && !same_access_path_p (access->expr, ac2->expr))
@@ -3127,7 +3151,9 @@ propagate_subaccesses_from_rhs (struct access *lacc, 
struct access *racc)
  ret = true;
  subtree_mark_written_and_rhs_enqueue (lacc);
}
-  if (!lacc->first_child && !racc->first_child)
+  if (!lacc->first_child
+ && !racc->first_child
+ && !types_risk_mangled_binary_repr_p (racc->type, lacc->type))
{
  /* We are about to change the access type from aggregate to scalar,
 so we need to put the reverse flag onto the access, if any.  */

[gcc r13-8985] [testsuite] [arm] [vect] adjust mve-vshr test [PR113281]

2024-08-21 Thread Richard Ball via Gcc-cvs

https://gcc.gnu.org/g:3e5cf9f060f39a958edf4b817f632ee93e96d55c

commit r13-8985-g3e5cf9f060f39a958edf4b817f632ee93e96d55c
Author: Alexandre Oliva 
Date:   Wed Jun 26 02:08:18 2024 -0300

[testsuite] [arm] [vect] adjust mve-vshr test [PR113281]

The test was too optimistic, alas.  We used to vectorize shifts by
clamping the shift counts below the bit width of the types (e.g. at 15
for 16-bit vector elements), but (uint16_t)32768 >> (uint16_t)16 is
well defined (because of promotion to 32-bit int) and must yield 0,
not 1 (as before the fix).

Unfortunately, in the gimple model of vector units, such large shift
counts wouldn't be well-defined, so we won't vectorize such shifts any
more, unless we can tell they're in range or undefined.

So the test that expected the vectorization we no longer performed
needs to be adjusted.  Instead of nobbling the test, Richard Earnshaw
suggested annotating the test with the expected ranges so as to enable
the optimization, and Christophe Lyon suggested a further
simplification.

Co-Authored-By: Richard Earnshaw 

for  gcc/testsuite/ChangeLog

PR tree-optimization/113281
* gcc.target/arm/simd/mve-vshr.c: Add expected ranges.

(cherry picked from commit 54d2339c9f87f702e02e571a5460e11c19e1c02f)

Diff:
---
 gcc/testsuite/gcc.target/arm/simd/mve-vshr.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/gcc/testsuite/gcc.target/arm/simd/mve-vshr.c 
b/gcc/testsuite/gcc.target/arm/simd/mve-vshr.c
index 8c7adef9ed8f..03078de49c65 100644
--- a/gcc/testsuite/gcc.target/arm/simd/mve-vshr.c
+++ b/gcc/testsuite/gcc.target/arm/simd/mve-vshr.c
@@ -9,6 +9,8 @@
   void test_ ## NAME ##_ ## SIGN ## BITS ## x ## NB (TYPE##BITS##_t * 
__restrict__ dest, TYPE##BITS##_t *a, TYPE##BITS##_t *b) { \
 int i; \
 for (i=0; i= (unsigned)(BITS))  \
+   __builtin_unreachable();\
   dest[i] = a[i] OP b[i];  \
 }  \
 }

[gcc r12-10680] [testsuite] [arm] [vect] adjust mve-vshr test [PR113281]

2024-08-21 Thread Richard Ball via Gcc-cvs

https://gcc.gnu.org/g:881b54f56e77dc470d27e4746b90dc7819c2be81

commit r12-10680-g881b54f56e77dc470d27e4746b90dc7819c2be81
Author: Alexandre Oliva 
Date:   Wed Jun 26 02:08:18 2024 -0300

[testsuite] [arm] [vect] adjust mve-vshr test [PR113281]

The test was too optimistic, alas.  We used to vectorize shifts by
clamping the shift counts below the bit width of the types (e.g. at 15
for 16-bit vector elements), but (uint16_t)32768 >> (uint16_t)16 is
well defined (because of promotion to 32-bit int) and must yield 0,
not 1 (as before the fix).

Unfortunately, in the gimple model of vector units, such large shift
counts wouldn't be well-defined, so we won't vectorize such shifts any
more, unless we can tell they're in range or undefined.

So the test that expected the vectorization we no longer performed
needs to be adjusted.  Instead of nobbling the test, Richard Earnshaw
suggested annotating the test with the expected ranges so as to enable
the optimization, and Christophe Lyon suggested a further
simplification.

Co-Authored-By: Richard Earnshaw 

for  gcc/testsuite/ChangeLog

PR tree-optimization/113281
* gcc.target/arm/simd/mve-vshr.c: Add expected ranges.

(cherry picked from commit 54d2339c9f87f702e02e571a5460e11c19e1c02f)

Diff:
---
 gcc/testsuite/gcc.target/arm/simd/mve-vshr.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/gcc/testsuite/gcc.target/arm/simd/mve-vshr.c 
b/gcc/testsuite/gcc.target/arm/simd/mve-vshr.c
index 8c7adef9ed8f..03078de49c65 100644
--- a/gcc/testsuite/gcc.target/arm/simd/mve-vshr.c
+++ b/gcc/testsuite/gcc.target/arm/simd/mve-vshr.c
@@ -9,6 +9,8 @@
   void test_ ## NAME ##_ ## SIGN ## BITS ## x ## NB (TYPE##BITS##_t * 
__restrict__ dest, TYPE##BITS##_t *a, TYPE##BITS##_t *b) { \
 int i; \
 for (i=0; i= (unsigned)(BITS))  \
+   __builtin_unreachable();\
   dest[i] = a[i] OP b[i];  \
 }  \
 }

[gcc r15-3071] tree-optimization/116406 - ICE with int<->float punning prevention

2024-08-21 Thread Richard Biener via Gcc-cvs

https://gcc.gnu.org/g:893cef363c46fa879b47d2b042c19c98bcd2b5f8

commit r15-3071-g893cef363c46fa879b47d2b042c19c98bcd2b5f8
Author: Richard Biener 
Date:   Wed Aug 21 14:15:33 2024 +0200

tree-optimization/116406 - ICE with int<->float punning prevention

The following does away with the idea to use non-symmetrical
testing of mode_can_transfer_bits in hash-table equality testing.
It isn't feasible to always control query order to maintain
consistency.

PR tree-optimization/116406
* tree-ssa-sccvn.cc (vn_reference_eq): Never equate
float and int when the float mode cannot transfer bits.
Do not try to anticipate which is the mode we actually load
from.

* gcc.dg/tree-ssa/pr116406.c: New testcase.
* gcc.dg/tree-ssa/ssa-pre-30.c: On x86 dd -msse -mfpmath=sse.

Diff:
---
 gcc/testsuite/gcc.dg/tree-ssa/pr116406.c   | 21 +
 gcc/testsuite/gcc.dg/tree-ssa/ssa-pre-30.c |  1 +
 gcc/tree-ssa-sccvn.cc  |  3 ++-
 3 files changed, 24 insertions(+), 1 deletion(-)

diff --git a/gcc/testsuite/gcc.dg/tree-ssa/pr116406.c 
b/gcc/testsuite/gcc.dg/tree-ssa/pr116406.c
new file mode 100644
index ..6643c49218fe
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/tree-ssa/pr116406.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-Os -finstrument-functions-once" } */
+/* { dg-additional-options "-mfpmath=387" { target { x86_64-*-* i?86-*-* } } } 
*/
+
+typedef union {
+  float f32;
+  double f64;
+  long i64;
+} U;
+
+_Bool
+foo (int c, U u)
+{
+  switch (c)
+{
+case 1:
+  return u.f32 - u.f64;
+case 0:
+  return u.i64;
+}
+}
diff --git a/gcc/testsuite/gcc.dg/tree-ssa/ssa-pre-30.c 
b/gcc/testsuite/gcc.dg/tree-ssa/ssa-pre-30.c
index cf9317372d64..29dc18123380 100644
--- a/gcc/testsuite/gcc.dg/tree-ssa/ssa-pre-30.c
+++ b/gcc/testsuite/gcc.dg/tree-ssa/ssa-pre-30.c
@@ -1,6 +1,7 @@
 /* { dg-do compile } */
 /* { dg-require-effective-target int32 } */
 /* { dg-options "-O2 -fdump-tree-pre-details" } */
+/* { dg-additional-options "-msse -mfpmath=sse" { target { x86_64-*-* i?86-*-* 
} } } */
 
 int f;
 int g;
diff --git a/gcc/tree-ssa-sccvn.cc b/gcc/tree-ssa-sccvn.cc
index 4370d09d9d8c..abf7d38d15cb 100644
--- a/gcc/tree-ssa-sccvn.cc
+++ b/gcc/tree-ssa-sccvn.cc
@@ -838,7 +838,8 @@ vn_reference_eq (const_vn_reference_t const vr1, 
const_vn_reference_t const vr2)
return false;
 }
   else if (TYPE_MODE (vr1->type) != TYPE_MODE (vr2->type)
-  && !mode_can_transfer_bits (TYPE_MODE (vr1->type)))
+  && (!mode_can_transfer_bits (TYPE_MODE (vr1->type))
+  || !mode_can_transfer_bits (TYPE_MODE (vr2->type
 return false;
 
   i = 0;

[gcc r15-3072] aarch64: Implement popcountti2 pattern [PR113042]

2024-08-21 Thread Andrew Pinski via Gcc-cvs

https://gcc.gnu.org/g:4a5d6118c10dfa4f1ed28ab4875bb80f2b2dca9d

commit r15-3072-g4a5d6118c10dfa4f1ed28ab4875bb80f2b2dca9d
Author: Andrew Pinski 
Date:   Fri Aug 16 11:18:31 2024 -0700

aarch64: Implement popcountti2 pattern [PR113042]

When CSSC is not enabled, 128bit popcount can be implemented
just via the vector (v16qi) cnt instruction followed by a reduction,
like how the 64bit one is currently implemented instead of
splitting into 2 64bit popcount.

Changes since v1:
* v2: Make operand 0 be DImode instead of TImode and simplify.

Build and tested for aarch64-linux-gnu.

PR target/113042

gcc/ChangeLog:

* config/aarch64/aarch64.md (popcountti2): New define_expand.

gcc/testsuite/ChangeLog:

* gcc.target/aarch64/popcnt10.c: New test.
* gcc.target/aarch64/popcnt9.c: New test.

Signed-off-by: Andrew Pinski 

Diff:
---
 gcc/config/aarch64/aarch64.md   | 13 +
 gcc/testsuite/gcc.target/aarch64/popcnt10.c | 25 +
 gcc/testsuite/gcc.target/aarch64/popcnt9.c  | 25 +
 3 files changed, 63 insertions(+)

diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index 12dcc16529ad..c54b29cd64b9 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -5378,6 +5378,19 @@
 }
 })
 
+(define_expand "popcountti2"
+  [(match_operand:DI 0 "register_operand")
+   (match_operand:TI 1 "register_operand")]
+  "TARGET_SIMD && !TARGET_CSSC"
+{
+  rtx v = gen_reg_rtx (V16QImode);
+  rtx v1 = gen_reg_rtx (V16QImode);
+  emit_move_insn (v, gen_lowpart (V16QImode, operands[1]));
+  emit_insn (gen_popcountv16qi2 (v1, v));
+  emit_insn (gen_aarch64_zero_extenddi_reduc_plus_v16qi (operands[0], v1));
+  DONE;
+})
+
 (define_insn "clrsb2"
   [(set (match_operand:GPI 0 "register_operand" "=r")
 (clrsb:GPI (match_operand:GPI 1 "register_operand" "r")))]
diff --git a/gcc/testsuite/gcc.target/aarch64/popcnt10.c 
b/gcc/testsuite/gcc.target/aarch64/popcnt10.c
new file mode 100644
index ..4d01fc67022b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/popcnt10.c
@@ -0,0 +1,25 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -fdump-tree-optimized" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+/* PR target/113042 */
+
+#pragma GCC target "+cssc"
+
+/*
+** h128:
+** ldp x([0-9]+), x([0-9]+), \[x0\]
+** cnt x([0-9]+), x([0-9]+)
+** cnt x([0-9]+), x([0-9]+)
+** add w0, w([0-9]+), w([0-9]+)
+** ret
+*/
+
+
+unsigned h128 (const unsigned __int128 *a) {
+  return __builtin_popcountg (a[0]);
+}
+
+/* popcount with CSSC should be split into 2 sections. */
+/* { dg-final { scan-tree-dump-not "POPCOUNT " "optimized" } } */
+/* { dg-final { scan-tree-dump-times " __builtin_popcount" 2 "optimized" } } */
+
diff --git a/gcc/testsuite/gcc.target/aarch64/popcnt9.c 
b/gcc/testsuite/gcc.target/aarch64/popcnt9.c
new file mode 100644
index ..c778fc7f4206
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/popcnt9.c
@@ -0,0 +1,25 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -fdump-tree-optimized" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+/* PR target/113042 */
+
+#pragma GCC target "+nocssc"
+
+/*
+** h128:
+** ldr q([0-9]+), \[x0\]
+** cnt v([0-9]+).16b, v\1.16b
+** addvb([0-9]+), v\2.16b
+** fmovw0, s\3
+** ret
+*/
+
+
+unsigned h128 (const unsigned __int128 *a) {
+ return __builtin_popcountg (a[0]);
+}
+
+/* There should be only one POPCOUNT. */
+/* { dg-final { scan-tree-dump-times "POPCOUNT " 1 "optimized" } } */
+/* { dg-final { scan-tree-dump-not " __builtin_popcount"  "optimized" } } */
+

[gcc r15-3073] aarch64: Fix caller saves of VNx2QI [PR116238]

2024-08-21 Thread Richard Sandiford via Gcc-cvs

https://gcc.gnu.org/g:ec9d6d45191f639482344362d048294e74587ca3

commit r15-3073-gec9d6d45191f639482344362d048294e74587ca3
Author: Richard Sandiford 
Date:   Wed Aug 21 17:35:47 2024 +0100

aarch64: Fix caller saves of VNx2QI [PR116238]

The testcase contains a VNx2QImode pseudo that is live across a call
and that cannot be allocated a call-preserved register.  LRA quite
reasonably tried to save it before the call and restore it afterwards.
Unfortunately, the target told it to do that in SImode, even though
punning between SImode and VNx2QImode is disallowed by both
TARGET_CAN_CHANGE_MODE_CLASS and TARGET_MODES_TIEABLE_P.

The natural class to use for SImode is GENERAL_REGS, so this led
to an unsalvageable situation in which we had:

  (set (subreg:VNx2QI (reg:SI A) 0) (reg:VNx2QI B))

where A needed GENERAL_REGS and B needed FP_REGS.  We therefore ended
up in a reload loop.

The hooks above should ensure that this situation can never occur
for incoming subregs.  It only happened here because the target
explicitly forced it.

The decision to use SImode for modes smaller than 4 bytes dates
back to the beginning of the port, before 16-bit floating-point
modes existed.  I'm not sure whether promoting to SImode really
makes sense for any FPR, but that's a separate performance/QoI
discussion.  For now, this patch just disallows using SImode
when it is wrong for correctness reasons, since that should be
safer to backport.

gcc/
PR testsuite/116238
* config/aarch64/aarch64.cc (aarch64_hard_regno_caller_save_mode):
Only return SImode if we can convert to and from it.

gcc/testsuite/
PR testsuite/116238
* gcc.target/aarch64/sve/pr116238.c: New test.

Diff:
---
 gcc/config/aarch64/aarch64.cc   |  7 ---
 gcc/testsuite/gcc.target/aarch64/sve/pr116238.c | 13 +
 2 files changed, 17 insertions(+), 3 deletions(-)

diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc
index bfd7bcdef7cb..4e312c435769 100644
--- a/gcc/config/aarch64/aarch64.cc
+++ b/gcc/config/aarch64/aarch64.cc
@@ -2521,10 +2521,11 @@ aarch64_hard_regno_caller_save_mode (unsigned regno, 
unsigned,
  unnecessarily significant.  */
   if (PR_REGNUM_P (regno))
 return mode;
-  if (known_ge (GET_MODE_SIZE (mode), 4))
-return mode;
-  else
+  if (known_lt (GET_MODE_SIZE (mode), 4)
+  && REG_CAN_CHANGE_MODE_P (regno, mode, SImode)
+  && REG_CAN_CHANGE_MODE_P (regno, SImode, mode))
 return SImode;
+  return mode;
 }
 
 /* Return true if I's bits are consecutive ones from the MSB.  */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pr116238.c 
b/gcc/testsuite/gcc.target/aarch64/sve/pr116238.c
new file mode 100644
index ..fe66b198107f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve/pr116238.c
@@ -0,0 +1,13 @@
+/* { dg-additional-options "-O2 -msve-vector-bits=128" } */
+
+void foo();
+typedef unsigned char v2qi __attribute__((vector_size(2)));
+void f(v2qi *ptr)
+{
+  v2qi x = *ptr;
+  asm volatile ("" :: "w" (x));
+  asm volatile ("" ::: "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15");
+  foo();
+  asm volatile ("" :: "w" (x));
+  *ptr = x;
+}

[gcc r15-3074] [PR rtl-optimization/116437] Fix RTL checking issue in ext-dce

2024-08-21 Thread Jeff Law via Gcc-cvs

https://gcc.gnu.org/g:cdc9cd4afe8949276a0c50215eb7f23e2086044f

commit r15-3074-gcdc9cd4afe8949276a0c50215eb7f23e2086044f
Author: Jeff Law 
Date:   Wed Aug 21 16:52:23 2024 -0600

[PR rtl-optimization/116437] Fix RTL checking issue in ext-dce

Another RTL checking failure in ext-dce.  An easy one to fix this time.

When we optimize an extension we have to go back and cleanup with
SUBREG_PROMOTED state.  So we record the destination register into a bitmap 
as
we make changes, then later do a single pass over the IL fixing any 
associated
subreg expressions.

The optimization is changing the SET_SRC and largely ignores the 
destination.
The LHS could be a REG, SUBREG, or ZERO_EXTRACT.  If the LHS is a SUBREG or
ZERO_EXTRACT we can just strip them.

Bootstrapped and ran the testsuite with an RTL checking compiler and 
verified
no ext-dce RTL checking failures tripped.  Also bootstrapped and regression
tested x86_64 in the usual way.

Pushing to the trunk.

PR rtl-optimization/116437
gcc/
* ext-dce.cc (ext_dce_try_optimize_insn): Handle SUBREG and
ZERO_EXTRACT destinations.

Diff:
---
 gcc/ext-dce.cc | 7 ++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/gcc/ext-dce.cc b/gcc/ext-dce.cc
index eee9208f0d65..35c06469b82c 100644
--- a/gcc/ext-dce.cc
+++ b/gcc/ext-dce.cc
@@ -422,8 +422,13 @@ ext_dce_try_optimize_insn (rtx_insn *insn, rtx set)
 {
   int ok = validate_change (insn, &SET_SRC (set), new_pattern, false);
 
+  rtx x = SET_DEST (set);
+  while (SUBREG_P (x) || GET_CODE (x) == ZERO_EXTRACT)
+   x = XEXP (x, 0);
+
+  gcc_assert (REG_P (x));
   if (ok)
-   bitmap_set_bit (changed_pseudos, REGNO (SET_DEST (set)));
+   bitmap_set_bit (changed_pseudos, REGNO (x));
 
   if (dump_file)
{

[gcc r15-3075] RISC-V: Add testcases for unsigned vector .SAT_TRUNC form 2

2024-08-21 Thread Pan Li via Gcc-cvs

https://gcc.gnu.org/g:1e99e1ba79964f47f8850871d025209dfab73693

commit r15-3075-g1e99e1ba79964f47f8850871d025209dfab73693
Author: Pan Li 
Date:   Wed Aug 21 17:43:12 2024 +0800

RISC-V: Add testcases for unsigned vector .SAT_TRUNC form 2

This patch would like to add test cases for the unsigned vector
.SAT_TRUNC form 2.  Aka:

Form 2:
  #define DEF_VEC_SAT_U_TRUNC_FMT_2(NT, WT) \
  void __attribute__((noinline))\
  vec_sat_u_trunc_##NT##_##WT##_fmt_2 (NT *out, WT *in, unsigned limit) \
  { \
unsigned i; \
for (i = 0; i < limit; i++) \
  { \
WT max = (WT)(NT)-1;\
out[i] = in[i] > max ? (NT)max : (NT)in[i]; \
  } \
  }

DEF_VEC_SAT_U_TRUNC_FMT_2 (uint32_t, uint64_t)

The below test is passed for this patch.
* The rv64gcv regression test.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/vec_sat_arith.h: Add test helper 
macros.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-10.c: New test.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-11.c: New test.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-12.c: New test.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-7.c: New test.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-8.c: New test.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-9.c: New test.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-run-10.c: New 
test.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-run-11.c: New 
test.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-run-12.c: New 
test.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-run-7.c: New 
test.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-run-8.c: New 
test.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-run-9.c: New 
test.

Signed-off-by: Pan Li 

Diff:
---
 .../riscv/rvv/autovec/unop/vec_sat_u_trunc-10.c| 19 ++
 .../riscv/rvv/autovec/unop/vec_sat_u_trunc-11.c| 21 
 .../riscv/rvv/autovec/unop/vec_sat_u_trunc-12.c| 19 ++
 .../riscv/rvv/autovec/unop/vec_sat_u_trunc-7.c | 19 ++
 .../riscv/rvv/autovec/unop/vec_sat_u_trunc-8.c | 21 
 .../riscv/rvv/autovec/unop/vec_sat_u_trunc-9.c | 23 ++
 .../rvv/autovec/unop/vec_sat_u_trunc-run-10.c  | 16 +++
 .../rvv/autovec/unop/vec_sat_u_trunc-run-11.c  | 16 +++
 .../rvv/autovec/unop/vec_sat_u_trunc-run-12.c  | 16 +++
 .../riscv/rvv/autovec/unop/vec_sat_u_trunc-run-7.c | 16 +++
 .../riscv/rvv/autovec/unop/vec_sat_u_trunc-run-8.c | 16 +++
 .../riscv/rvv/autovec/unop/vec_sat_u_trunc-run-9.c | 16 +++
 .../gcc.target/riscv/rvv/autovec/vec_sat_arith.h   | 18 +
 13 files changed, 236 insertions(+)

diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-10.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-10.c
new file mode 100644
index ..f5084e503ebd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-10.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize 
-fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-skip-if "" { *-*-* } { "-flto" } } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "../vec_sat_arith.h"
+
+/*
+** vec_sat_u_trunc_uint16_t_uint32_t_fmt_2:
+** ...
+** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*mf2,\s*ta,\s*ma
+** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
+** vse16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** ...
+*/
+DEF_VEC_SAT_U_TRUNC_FMT_2 (uint16_t, uint32_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-11.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-11.c
new file mode 100644
index ..e2ab880a1aca
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-11.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize 
-fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-skip-if "" { *-*-* } { "-flto" } } */
+/* { dg-final {

[gcc r15-3076] RISC-V: Add testcases for unsigned vector .SAT_TRUNC form 3

2024-08-21 Thread Pan Li via Gcc-cvs

https://gcc.gnu.org/g:91f213908c0443b0249490b03b8046509f6e7e9d

commit r15-3076-g91f213908c0443b0249490b03b8046509f6e7e9d
Author: Pan Li 
Date:   Wed Aug 21 17:57:47 2024 +0800

RISC-V: Add testcases for unsigned vector .SAT_TRUNC form 3

This patch would like to add test cases for the unsigned vector
.SAT_TRUNC form 3.  Aka:

Form 3:
  #define DEF_VEC_SAT_U_TRUNC_FMT_3(NT, WT) \
  void __attribute__((noinline))\
  vec_sat_u_trunc_##NT##_##WT##_fmt_3 (NT *out, WT *in, unsigned limit) \
  { \
unsigned i; \
for (i = 0; i < limit; i++) \
  { \
WT max = (WT)(NT)-1;\
out[i] = in[i] <= max ? (NT)in[i] : (NT)max;\
  } \
  }

DEF_VEC_SAT_U_TRUNC_FMT_3 (uint32_t, uint64_t)

The below test is passed for this patch.
* The rv64gcv regression test.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/vec_sat_arith.h: Add test helper 
macros.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-13.c: New test.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-14.c: New test.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-15.c: New test.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-16.c: New test.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-17.c: New test.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-18.c: New test.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-run-13.c: New 
test.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-run-14.c: New 
test.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-run-15.c: New 
test.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-run-16.c: New 
test.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-run-17.c: New 
test.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-run-18.c: New 
test.

Signed-off-by: Pan Li 

Diff:
---
 .../riscv/rvv/autovec/unop/vec_sat_u_trunc-13.c| 19 ++
 .../riscv/rvv/autovec/unop/vec_sat_u_trunc-14.c| 21 
 .../riscv/rvv/autovec/unop/vec_sat_u_trunc-15.c| 23 ++
 .../riscv/rvv/autovec/unop/vec_sat_u_trunc-16.c| 19 ++
 .../riscv/rvv/autovec/unop/vec_sat_u_trunc-17.c| 21 
 .../riscv/rvv/autovec/unop/vec_sat_u_trunc-18.c| 19 ++
 .../rvv/autovec/unop/vec_sat_u_trunc-run-13.c  | 16 +++
 .../rvv/autovec/unop/vec_sat_u_trunc-run-14.c  | 16 +++
 .../rvv/autovec/unop/vec_sat_u_trunc-run-15.c  | 16 +++
 .../rvv/autovec/unop/vec_sat_u_trunc-run-16.c  | 16 +++
 .../rvv/autovec/unop/vec_sat_u_trunc-run-17.c  | 16 +++
 .../rvv/autovec/unop/vec_sat_u_trunc-run-18.c  | 16 +++
 .../gcc.target/riscv/rvv/autovec/vec_sat_arith.h   | 18 +
 13 files changed, 236 insertions(+)

diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-13.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-13.c
new file mode 100644
index ..49bdbdc36062
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-13.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize 
-fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-skip-if "" { *-*-* } { "-flto" } } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "../vec_sat_arith.h"
+
+/*
+** vec_sat_u_trunc_uint8_t_uint16_t_fmt_3:
+** ...
+** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*mf2,\s*ta,\s*ma
+** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
+** vse8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** ...
+*/
+DEF_VEC_SAT_U_TRUNC_FMT_3 (uint8_t, uint16_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" } } */
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-14.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-14.c
new file mode 100644
index ..3ff696edcfee
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-14.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize 
-fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-skip-if "" { *-*-* } { "-flto" } } */
+/* { dg-final

[gcc(refs/vendors/microsoft/heads/main)] Update xfail with new failures

2024-08-21 Thread Eugene Rozenfeld via Gcc-cvs

https://gcc.gnu.org/g:12a15e5a3f2f3fed01060d0e1a78e2b5586c1195

commit 12a15e5a3f2f3fed01060d0e1a78e2b5586c1195
Author: MS Automation 
Date:   Tue Aug 20 13:49:41 2024 +

Update xfail with new failures

Diff:
---
 .../testsuite-management/x86_64-pc-linux-gnu.xfail | 23 +-
 1 file changed, 22 insertions(+), 1 deletion(-)

diff --git a/contrib/testsuite-management/x86_64-pc-linux-gnu.xfail 
b/contrib/testsuite-management/x86_64-pc-linux-gnu.xfail
index fabb9ea1df0f..a6e4d9801a96 100644
--- a/contrib/testsuite-management/x86_64-pc-linux-gnu.xfail
+++ b/contrib/testsuite-management/x86_64-pc-linux-gnu.xfail
@@ -239,4 +239,25 @@ FAIL: gcc.dg/guality/vla-1.c -O2  -DPREVENT_OPTIMIZATION  
line 17 sizeof (a) ==
 FAIL: gcc.dg/guality/vla-1.c -O2 -flto -fno-use-linker-plugin 
-flto-partition=none  -DPREVENT_OPTIMIZATION line 17 sizeof (a) == 6
 FAIL: gcc.dg/guality/vla-1.c -O2 -flto -fuse-linker-plugin 
-fno-fat-lto-objects  -DPREVENT_OPTIMIZATION line 17 sizeof (a) == 6
 FAIL: gcc.dg/guality/vla-1.c -O3 -g  -DPREVENT_OPTIMIZATION  line 17 sizeof 
(a) == 6
-FAIL: gcc.dg/guality/vla-1.c -Os  -DPREVENT_OPTIMIZATION  line 17 sizeof (a) 
== 6
\ No newline at end of file
+FAIL: gcc.dg/guality/vla-1.c -Os  -DPREVENT_OPTIMIZATION  line 17 sizeof (a) 
== 6
+FAIL: gcc.dg/guality/loop-1.c -O2  -DPREVENT_OPTIMIZATION  line 20 i == 1
+FAIL: gcc.dg/guality/loop-1.c -O2 -flto -fno-use-linker-plugin 
-flto-partition=none  -DPREVENT_OPTIMIZATION line 20 i == 1
+FAIL: gcc.dg/guality/loop-1.c -O2 -flto -fuse-linker-plugin 
-fno-fat-lto-objects  -DPREVENT_OPTIMIZATION line 20 i == 1
+FAIL: gcc.dg/guality/loop-1.c -O3 -g  -DPREVENT_OPTIMIZATION  line 20 i == 1
+FAIL: gcc.target/i386/force-indirect-call-2.c scan-assembler-times 
(?:call|jmp)[ \\t]+\\*% 3
+FAIL: gcc.target/i386/pr101716.c scan-assembler leal[\\t ][^\\n]*eax
+FAIL: gcc.target/i386/pr101716.c scan-assembler-not movl[\\t ][^\\n]*eax
+FAIL: gcc.target/i386/pr101950-2.c scan-assembler-times \txor[ql]\t 2
+FAIL: gcc.target/i386/pr105493.c scan-tree-dump-times slp1 "  MEM 
 \\[[^]]*\\] = " 4
+FAIL: gcc.target/i386/pr91384.c scan-assembler-not testl
+FAIL: gcc.target/i386/stack-check-17.c scan-assembler-not pop
+FAIL: libgomp.oacc-c++/../libgomp.oacc-c-c++-common/acc_prof-kernels-1.c 
-DACC_DEVICE_TYPE_host=1 -DACC_MEM_SHARED=1 -foffload=disable  -O2   at line 
190 (test for warnings, line 185)
+FAIL: libgomp.oacc-c++/../libgomp.oacc-c-c++-common/acc_prof-kernels-1.c 
-DACC_DEVICE_TYPE_host=1 -DACC_MEM_SHARED=1 -foffload=disable  -O2   at line 
221 (test for warnings, line 214)
+FAIL: libgomp.oacc-c++/../libgomp.oacc-c-c++-common/acc_prof-kernels-1.c 
-DACC_DEVICE_TYPE_host=1 -DACC_MEM_SHARED=1 -foffload=disable  -O2   at line 
252 (test for warnings, line 245)
+FAIL: libgomp.oacc-c++/../libgomp.oacc-c-c++-common/acc_prof-kernels-1.c 
-DACC_DEVICE_TYPE_host=1 -DACC_MEM_SHARED=1 -foffload=disable  -O2  (test for 
excess errors)
+FAIL: libgomp.oacc-c/../libgomp.oacc-c-c++-common/acc_prof-kernels-1.c 
-DACC_DEVICE_TYPE_host=1 -DACC_MEM_SHARED=1 -foffload=disable  -O2   at line 
190 (test for warnings, line 185)
+FAIL: libgomp.oacc-c/../libgomp.oacc-c-c++-common/acc_prof-kernels-1.c 
-DACC_DEVICE_TYPE_host=1 -DACC_MEM_SHARED=1 -foffload=disable  -O2   at line 
221 (test for warnings, line 214)
+FAIL: libgomp.oacc-c/../libgomp.oacc-c-c++-common/acc_prof-kernels-1.c 
-DACC_DEVICE_TYPE_host=1 -DACC_MEM_SHARED=1 -foffload=disable  -O2   at line 
252 (test for warnings, line 245)
+FAIL: libgomp.oacc-c/../libgomp.oacc-c-c++-common/acc_prof-kernels-1.c 
-DACC_DEVICE_TYPE_host=1 -DACC_MEM_SHARED=1 -foffload=disable  -O2  (test for 
excess errors)
+XPASS: gcc.dg/ira-shrinkwrap-prep-1.c scan-rtl-dump ira "Split live-range of 
register"
+XPASS: gcc.dg/ira-shrinkwrap-prep-2.c scan-rtl-dump ira "Split live-range of 
register"
\ No newline at end of file

[gcc r15-3078] Align ix86_{move_max,store_max} with vectorizer.

2024-08-21 Thread hongtao Liu via Gcc-cvs

https://gcc.gnu.org/g:6ea25c041964bf63014fcf7bb68fb1f5a0a4e123

commit r15-3078-g6ea25c041964bf63014fcf7bb68fb1f5a0a4e123
Author: liuhongt 
Date:   Thu Aug 15 12:54:07 2024 +0800

Align ix86_{move_max,store_max} with vectorizer.

When none of mprefer-vector-width, avx256_optimal/avx128_optimal,
avx256_store_by_pieces/avx512_store_by_pieces is specified, GCC will
set ix86_{move_max,store_max} as max available vector length except
for AVX part.

  if (TARGET_AVX512F_P (opts->x_ix86_isa_flags)
  && TARGET_EVEX512_P (opts->x_ix86_isa_flags2))
opts->x_ix86_move_max = PVW_AVX512;
  else
opts->x_ix86_move_max = PVW_AVX128;

So for -mavx2, vectorizer will choose 256-bit for vectorization, but
128-bit is used for struct copy, there could be a potential STLF issue
due to this "misalign".

The patch fixes that.

gcc/ChangeLog:

* config/i386/i386-options.cc (ix86_option_override_internal):
set ix86_{move_max,store_max} to PVW_AVX256 when TARGET_AVX
instead of PVW_AVX128.

gcc/testsuite/ChangeLog:
* gcc.target/i386/pieces-memcpy-10.c: Add -mprefer-vector-width=128.
* gcc.target/i386/pieces-memcpy-6.c: Ditto.
* gcc.target/i386/pieces-memset-38.c: Ditto.
* gcc.target/i386/pieces-memset-40.c: Ditto.
* gcc.target/i386/pieces-memset-41.c: Ditto.
* gcc.target/i386/pieces-memset-42.c: Ditto.
* gcc.target/i386/pieces-memset-43.c: Ditto.
* gcc.target/i386/pieces-strcpy-2.c: Ditto.
* gcc.target/i386/pieces-memcpy-22.c: New test.
* gcc.target/i386/pieces-memset-51.c: New test.
* gcc.target/i386/pieces-strcpy-3.c: New test.

Diff:
---
 gcc/config/i386/i386-options.cc  |  6 ++
 gcc/testsuite/gcc.target/i386/pieces-memcpy-10.c |  2 +-
 gcc/testsuite/gcc.target/i386/pieces-memcpy-22.c | 12 
 gcc/testsuite/gcc.target/i386/pieces-memcpy-6.c  |  2 +-
 gcc/testsuite/gcc.target/i386/pieces-memset-38.c |  2 +-
 gcc/testsuite/gcc.target/i386/pieces-memset-40.c |  2 +-
 gcc/testsuite/gcc.target/i386/pieces-memset-41.c |  2 +-
 gcc/testsuite/gcc.target/i386/pieces-memset-42.c |  2 +-
 gcc/testsuite/gcc.target/i386/pieces-memset-43.c |  2 +-
 gcc/testsuite/gcc.target/i386/pieces-memset-51.c | 12 
 gcc/testsuite/gcc.target/i386/pieces-strcpy-2.c  |  2 +-
 gcc/testsuite/gcc.target/i386/pieces-strcpy-3.c  | 15 +++
 12 files changed, 53 insertions(+), 8 deletions(-)

diff --git a/gcc/config/i386/i386-options.cc b/gcc/config/i386/i386-options.cc
index f423455b3638..f79257cc7641 100644
--- a/gcc/config/i386/i386-options.cc
+++ b/gcc/config/i386/i386-options.cc
@@ -3023,6 +3023,9 @@ ix86_option_override_internal (bool main_args_p,
  if (TARGET_AVX512F_P (opts->x_ix86_isa_flags)
  && TARGET_EVEX512_P (opts->x_ix86_isa_flags2))
opts->x_ix86_move_max = PVW_AVX512;
+ /* Align with vectorizer to avoid potential STLF issue.  */
+ else if (TARGET_AVX_P (opts->x_ix86_isa_flags))
+   opts->x_ix86_move_max = PVW_AVX256;
  else
opts->x_ix86_move_max = PVW_AVX128;
}
@@ -3047,6 +3050,9 @@ ix86_option_override_internal (bool main_args_p,
  if (TARGET_AVX512F_P (opts->x_ix86_isa_flags)
  && TARGET_EVEX512_P (opts->x_ix86_isa_flags2))
opts->x_ix86_store_max = PVW_AVX512;
+ /* Align with vectorizer to avoid potential STLF issue.  */
+ else if (TARGET_AVX_P (opts->x_ix86_isa_flags))
+   opts->x_ix86_store_max = PVW_AVX256;
  else
opts->x_ix86_store_max = PVW_AVX128;
}
diff --git a/gcc/testsuite/gcc.target/i386/pieces-memcpy-10.c 
b/gcc/testsuite/gcc.target/i386/pieces-memcpy-10.c
index 5faee21f9b99..53ad0b3be443 100644
--- a/gcc/testsuite/gcc.target/i386/pieces-memcpy-10.c
+++ b/gcc/testsuite/gcc.target/i386/pieces-memcpy-10.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O2 -mno-avx2 -mavx -mtune=sandybridge" } */
+/* { dg-options "-O2 -mno-avx2 -mavx -mprefer-vector-width=128 
-mtune=sandybridge" } */
 
 extern char *dst, *src;
 
diff --git a/gcc/testsuite/gcc.target/i386/pieces-memcpy-22.c 
b/gcc/testsuite/gcc.target/i386/pieces-memcpy-22.c
new file mode 100644
index ..605b3623ffc5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pieces-memcpy-22.c
@@ -0,0 +1,12 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-O2 -mno-avx2 -mavx -mtune=generic" } */
+
+extern char *dst, *src;
+
+void
+foo (void)
+{
+  __builtin_memcpy (dst, src, 33);
+}
+
+/* { dg-final { scan-assembler-times "vmovdqu\[ \\t\]+\[^\n\]*%ymm" 2 } } */
diff --git a/gcc/testsuite/gcc.target/i386/pieces-memcpy-6.c 
b/gcc/testsuite/gcc.target

[gcc r14-10608] Align ix86_{move_max,store_max} with vectorizer.

2024-08-21 Thread hongtao Liu via Gcc-cvs

https://gcc.gnu.org/g:27dc1533b6dfc49f3912c524db51d6c372a5ac3d

commit r14-10608-g27dc1533b6dfc49f3912c524db51d6c372a5ac3d
Author: liuhongt 
Date:   Thu Aug 15 12:54:07 2024 +0800

Align ix86_{move_max,store_max} with vectorizer.

When none of mprefer-vector-width, avx256_optimal/avx128_optimal,
avx256_store_by_pieces/avx512_store_by_pieces is specified, GCC will
set ix86_{move_max,store_max} as max available vector length except
for AVX part.

  if (TARGET_AVX512F_P (opts->x_ix86_isa_flags)
  && TARGET_EVEX512_P (opts->x_ix86_isa_flags2))
opts->x_ix86_move_max = PVW_AVX512;
  else
opts->x_ix86_move_max = PVW_AVX128;

So for -mavx2, vectorizer will choose 256-bit for vectorization, but
128-bit is used for struct copy, there could be a potential STLF issue
due to this "misalign".

The patch fixes that.

gcc/ChangeLog:

* config/i386/i386-options.cc (ix86_option_override_internal):
set ix86_{move_max,store_max} to PVW_AVX256 when TARGET_AVX
instead of PVW_AVX128.

gcc/testsuite/ChangeLog:
* gcc.target/i386/pieces-memcpy-10.c: Add -mprefer-vector-width=128.
* gcc.target/i386/pieces-memcpy-6.c: Ditto.
* gcc.target/i386/pieces-memset-38.c: Ditto.
* gcc.target/i386/pieces-memset-40.c: Ditto.
* gcc.target/i386/pieces-memset-41.c: Ditto.
* gcc.target/i386/pieces-memset-42.c: Ditto.
* gcc.target/i386/pieces-memset-43.c: Ditto.
* gcc.target/i386/pieces-strcpy-2.c: Ditto.
* gcc.target/i386/pieces-memcpy-22.c: New test.
* gcc.target/i386/pieces-memset-51.c: New test.
* gcc.target/i386/pieces-strcpy-3.c: New test.

(cherry picked from commit 6ea25c041964bf63014fcf7bb68fb1f5a0a4e123)

Diff:
---
 gcc/config/i386/i386-options.cc  |  6 ++
 gcc/testsuite/gcc.target/i386/pieces-memcpy-10.c |  2 +-
 gcc/testsuite/gcc.target/i386/pieces-memcpy-22.c | 12 
 gcc/testsuite/gcc.target/i386/pieces-memcpy-6.c  |  2 +-
 gcc/testsuite/gcc.target/i386/pieces-memset-38.c |  2 +-
 gcc/testsuite/gcc.target/i386/pieces-memset-40.c |  2 +-
 gcc/testsuite/gcc.target/i386/pieces-memset-41.c |  2 +-
 gcc/testsuite/gcc.target/i386/pieces-memset-42.c |  2 +-
 gcc/testsuite/gcc.target/i386/pieces-memset-43.c |  2 +-
 gcc/testsuite/gcc.target/i386/pieces-memset-51.c | 12 
 gcc/testsuite/gcc.target/i386/pieces-strcpy-2.c  |  2 +-
 gcc/testsuite/gcc.target/i386/pieces-strcpy-3.c  | 15 +++
 12 files changed, 53 insertions(+), 8 deletions(-)

diff --git a/gcc/config/i386/i386-options.cc b/gcc/config/i386/i386-options.cc
index 6c212a8edeb9..f6c450cc871c 100644
--- a/gcc/config/i386/i386-options.cc
+++ b/gcc/config/i386/i386-options.cc
@@ -3062,6 +3062,9 @@ ix86_option_override_internal (bool main_args_p,
  if (TARGET_AVX512F_P (opts->x_ix86_isa_flags)
  && TARGET_EVEX512_P (opts->x_ix86_isa_flags2))
opts->x_ix86_move_max = PVW_AVX512;
+ /* Align with vectorizer to avoid potential STLF issue.  */
+ else if (TARGET_AVX_P (opts->x_ix86_isa_flags))
+   opts->x_ix86_move_max = PVW_AVX256;
  else
opts->x_ix86_move_max = PVW_AVX128;
}
@@ -3086,6 +3089,9 @@ ix86_option_override_internal (bool main_args_p,
  if (TARGET_AVX512F_P (opts->x_ix86_isa_flags)
  && TARGET_EVEX512_P (opts->x_ix86_isa_flags2))
opts->x_ix86_store_max = PVW_AVX512;
+ /* Align with vectorizer to avoid potential STLF issue.  */
+ else if (TARGET_AVX_P (opts->x_ix86_isa_flags))
+   opts->x_ix86_store_max = PVW_AVX256;
  else
opts->x_ix86_store_max = PVW_AVX128;
}
diff --git a/gcc/testsuite/gcc.target/i386/pieces-memcpy-10.c 
b/gcc/testsuite/gcc.target/i386/pieces-memcpy-10.c
index 5faee21f9b99..53ad0b3be443 100644
--- a/gcc/testsuite/gcc.target/i386/pieces-memcpy-10.c
+++ b/gcc/testsuite/gcc.target/i386/pieces-memcpy-10.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O2 -mno-avx2 -mavx -mtune=sandybridge" } */
+/* { dg-options "-O2 -mno-avx2 -mavx -mprefer-vector-width=128 
-mtune=sandybridge" } */
 
 extern char *dst, *src;
 
diff --git a/gcc/testsuite/gcc.target/i386/pieces-memcpy-22.c 
b/gcc/testsuite/gcc.target/i386/pieces-memcpy-22.c
new file mode 100644
index ..605b3623ffc5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pieces-memcpy-22.c
@@ -0,0 +1,12 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-O2 -mno-avx2 -mavx -mtune=generic" } */
+
+extern char *dst, *src;
+
+void
+foo (void)
+{
+  __builtin_memcpy (dst, src, 33);
+}
+
+/* { dg-final { scan-assembler-times "vmovdqu\[ \\t\]+\[^\n\]*%ymm" 2 } } */
diff --gi

[gcc r13-8987] Align ix86_{move_max,store_max} with vectorizer.

2024-08-21 Thread hongtao Liu via Gcc-cvs

https://gcc.gnu.org/g:aea374238cec1a1e53fb79575d2f998e16926999

commit r13-8987-gaea374238cec1a1e53fb79575d2f998e16926999
Author: liuhongt 
Date:   Thu Aug 15 12:54:07 2024 +0800

Align ix86_{move_max,store_max} with vectorizer.

When none of mprefer-vector-width, avx256_optimal/avx128_optimal,
avx256_store_by_pieces/avx512_store_by_pieces is specified, GCC will
set ix86_{move_max,store_max} as max available vector length except
for AVX part.

  if (TARGET_AVX512F_P (opts->x_ix86_isa_flags)
  && TARGET_EVEX512_P (opts->x_ix86_isa_flags2))
opts->x_ix86_move_max = PVW_AVX512;
  else
opts->x_ix86_move_max = PVW_AVX128;

So for -mavx2, vectorizer will choose 256-bit for vectorization, but
128-bit is used for struct copy, there could be a potential STLF issue
due to this "misalign".

The patch fixes that.

gcc/ChangeLog:

* config/i386/i386-options.cc (ix86_option_override_internal):
set ix86_{move_max,store_max} to PVW_AVX256 when TARGET_AVX
instead of PVW_AVX128.

gcc/testsuite/ChangeLog:
* gcc.target/i386/pieces-memcpy-10.c: Add -mprefer-vector-width=128.
* gcc.target/i386/pieces-memcpy-6.c: Ditto.
* gcc.target/i386/pieces-memset-38.c: Ditto.
* gcc.target/i386/pieces-memset-40.c: Ditto.
* gcc.target/i386/pieces-memset-41.c: Ditto.
* gcc.target/i386/pieces-memset-42.c: Ditto.
* gcc.target/i386/pieces-memset-43.c: Ditto.
* gcc.target/i386/pieces-strcpy-2.c: Ditto.
* gcc.target/i386/pieces-memcpy-22.c: New test.
* gcc.target/i386/pieces-memset-51.c: New test.
* gcc.target/i386/pieces-strcpy-3.c: New test.

(cherry picked from commit 6ea25c041964bf63014fcf7bb68fb1f5a0a4e123)

Diff:
---
 gcc/config/i386/i386-options.cc  |  6 ++
 gcc/testsuite/gcc.target/i386/pieces-memcpy-10.c |  2 +-
 gcc/testsuite/gcc.target/i386/pieces-memcpy-22.c | 12 
 gcc/testsuite/gcc.target/i386/pieces-memcpy-6.c  |  2 +-
 gcc/testsuite/gcc.target/i386/pieces-memset-38.c |  2 +-
 gcc/testsuite/gcc.target/i386/pieces-memset-40.c |  2 +-
 gcc/testsuite/gcc.target/i386/pieces-memset-41.c |  2 +-
 gcc/testsuite/gcc.target/i386/pieces-memset-42.c |  2 +-
 gcc/testsuite/gcc.target/i386/pieces-memset-43.c |  2 +-
 gcc/testsuite/gcc.target/i386/pieces-memset-51.c | 12 
 gcc/testsuite/gcc.target/i386/pieces-strcpy-2.c  |  2 +-
 gcc/testsuite/gcc.target/i386/pieces-strcpy-3.c  | 15 +++
 12 files changed, 53 insertions(+), 8 deletions(-)

diff --git a/gcc/config/i386/i386-options.cc b/gcc/config/i386/i386-options.cc
index a4cff4e615f0..1b3856a630a5 100644
--- a/gcc/config/i386/i386-options.cc
+++ b/gcc/config/i386/i386-options.cc
@@ -2840,6 +2840,9 @@ ix86_option_override_internal (bool main_args_p,
{
  if (TARGET_AVX512F_P (opts->x_ix86_isa_flags))
opts->x_ix86_move_max = PVW_AVX512;
+ /* Align with vectorizer to avoid potential STLF issue.  */
+ else if (TARGET_AVX_P (opts->x_ix86_isa_flags))
+   opts->x_ix86_move_max = PVW_AVX256;
  else
opts->x_ix86_move_max = PVW_AVX128;
}
@@ -2861,6 +2864,9 @@ ix86_option_override_internal (bool main_args_p,
{
  if (TARGET_AVX512F_P (opts->x_ix86_isa_flags))
opts->x_ix86_store_max = PVW_AVX512;
+ /* Align with vectorizer to avoid potential STLF issue.  */
+ else if (TARGET_AVX_P (opts->x_ix86_isa_flags))
+   opts->x_ix86_store_max = PVW_AVX256;
  else
opts->x_ix86_store_max = PVW_AVX128;
}
diff --git a/gcc/testsuite/gcc.target/i386/pieces-memcpy-10.c 
b/gcc/testsuite/gcc.target/i386/pieces-memcpy-10.c
index 5faee21f9b99..53ad0b3be443 100644
--- a/gcc/testsuite/gcc.target/i386/pieces-memcpy-10.c
+++ b/gcc/testsuite/gcc.target/i386/pieces-memcpy-10.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O2 -mno-avx2 -mavx -mtune=sandybridge" } */
+/* { dg-options "-O2 -mno-avx2 -mavx -mprefer-vector-width=128 
-mtune=sandybridge" } */
 
 extern char *dst, *src;
 
diff --git a/gcc/testsuite/gcc.target/i386/pieces-memcpy-22.c 
b/gcc/testsuite/gcc.target/i386/pieces-memcpy-22.c
new file mode 100644
index ..605b3623ffc5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pieces-memcpy-22.c
@@ -0,0 +1,12 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-O2 -mno-avx2 -mavx -mtune=generic" } */
+
+extern char *dst, *src;
+
+void
+foo (void)
+{
+  __builtin_memcpy (dst, src, 33);
+}
+
+/* { dg-final { scan-assembler-times "vmovdqu\[ \\t\]+\[^\n\]*%ymm" 2 } } */
diff --git a/gcc/testsuite/gcc.target/i386/pieces-memcpy-6.c 
b/gcc/testsuite/gcc.target/i386/pieces-memcpy-6.

[gcc r12-10682] Align ix86_{move_max,store_max} with vectorizer.

2024-08-21 Thread hongtao Liu via Gcc-cvs

https://gcc.gnu.org/g:b4bc34db3f2948e37ad55a09870635e88c54c7d3

commit r12-10682-gb4bc34db3f2948e37ad55a09870635e88c54c7d3
Author: liuhongt 
Date:   Thu Aug 15 12:54:07 2024 +0800

Align ix86_{move_max,store_max} with vectorizer.

When none of mprefer-vector-width, avx256_optimal/avx128_optimal,
avx256_store_by_pieces/avx512_store_by_pieces is specified, GCC will
set ix86_{move_max,store_max} as max available vector length except
for AVX part.

  if (TARGET_AVX512F_P (opts->x_ix86_isa_flags)
  && TARGET_EVEX512_P (opts->x_ix86_isa_flags2))
opts->x_ix86_move_max = PVW_AVX512;
  else
opts->x_ix86_move_max = PVW_AVX128;

So for -mavx2, vectorizer will choose 256-bit for vectorization, but
128-bit is used for struct copy, there could be a potential STLF issue
due to this "misalign".

The patch fixes that.

gcc/ChangeLog:

* config/i386/i386-options.cc (ix86_option_override_internal):
set ix86_{move_max,store_max} to PVW_AVX256 when TARGET_AVX
instead of PVW_AVX128.

gcc/testsuite/ChangeLog:
* gcc.target/i386/pieces-memcpy-10.c: Add -mprefer-vector-width=128.
* gcc.target/i386/pieces-memcpy-6.c: Ditto.
* gcc.target/i386/pieces-memset-38.c: Ditto.
* gcc.target/i386/pieces-memset-40.c: Ditto.
* gcc.target/i386/pieces-memset-41.c: Ditto.
* gcc.target/i386/pieces-memset-42.c: Ditto.
* gcc.target/i386/pieces-memset-43.c: Ditto.
* gcc.target/i386/pieces-strcpy-2.c: Ditto.
* gcc.target/i386/pieces-memcpy-22.c: New test.
* gcc.target/i386/pieces-memset-51.c: New test.
* gcc.target/i386/pieces-strcpy-3.c: New test.

(cherry picked from commit aea374238cec1a1e53fb79575d2f998e16926999)

Diff:
---
 gcc/config/i386/i386-options.cc  |  6 ++
 gcc/testsuite/gcc.target/i386/pieces-memcpy-10.c |  2 +-
 gcc/testsuite/gcc.target/i386/pieces-memcpy-22.c | 12 
 gcc/testsuite/gcc.target/i386/pieces-memcpy-6.c  |  2 +-
 gcc/testsuite/gcc.target/i386/pieces-memset-38.c |  2 +-
 gcc/testsuite/gcc.target/i386/pieces-memset-40.c |  2 +-
 gcc/testsuite/gcc.target/i386/pieces-memset-41.c |  2 +-
 gcc/testsuite/gcc.target/i386/pieces-memset-42.c |  2 +-
 gcc/testsuite/gcc.target/i386/pieces-memset-43.c |  2 +-
 gcc/testsuite/gcc.target/i386/pieces-memset-51.c | 12 
 gcc/testsuite/gcc.target/i386/pieces-strcpy-2.c  |  2 +-
 gcc/testsuite/gcc.target/i386/pieces-strcpy-3.c  | 15 +++
 12 files changed, 53 insertions(+), 8 deletions(-)

diff --git a/gcc/config/i386/i386-options.cc b/gcc/config/i386/i386-options.cc
index 318f6c614551..ad496ea5a8eb 100644
--- a/gcc/config/i386/i386-options.cc
+++ b/gcc/config/i386/i386-options.cc
@@ -2766,6 +2766,9 @@ ix86_option_override_internal (bool main_args_p,
{
  if (TARGET_AVX512F_P (opts->x_ix86_isa_flags))
opts->x_ix86_move_max = PVW_AVX512;
+ /* Align with vectorizer to avoid potential STLF issue.  */
+ else if (TARGET_AVX_P (opts->x_ix86_isa_flags))
+   opts->x_ix86_move_max = PVW_AVX256;
  else
opts->x_ix86_move_max = PVW_AVX128;
}
@@ -2787,6 +2790,9 @@ ix86_option_override_internal (bool main_args_p,
{
  if (TARGET_AVX512F_P (opts->x_ix86_isa_flags))
opts->x_ix86_store_max = PVW_AVX512;
+ /* Align with vectorizer to avoid potential STLF issue.  */
+ else if (TARGET_AVX_P (opts->x_ix86_isa_flags))
+   opts->x_ix86_store_max = PVW_AVX256;
  else
opts->x_ix86_store_max = PVW_AVX128;
}
diff --git a/gcc/testsuite/gcc.target/i386/pieces-memcpy-10.c 
b/gcc/testsuite/gcc.target/i386/pieces-memcpy-10.c
index 5faee21f9b99..53ad0b3be443 100644
--- a/gcc/testsuite/gcc.target/i386/pieces-memcpy-10.c
+++ b/gcc/testsuite/gcc.target/i386/pieces-memcpy-10.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O2 -mno-avx2 -mavx -mtune=sandybridge" } */
+/* { dg-options "-O2 -mno-avx2 -mavx -mprefer-vector-width=128 
-mtune=sandybridge" } */
 
 extern char *dst, *src;
 
diff --git a/gcc/testsuite/gcc.target/i386/pieces-memcpy-22.c 
b/gcc/testsuite/gcc.target/i386/pieces-memcpy-22.c
new file mode 100644
index ..605b3623ffc5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pieces-memcpy-22.c
@@ -0,0 +1,12 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-O2 -mno-avx2 -mavx -mtune=generic" } */
+
+extern char *dst, *src;
+
+void
+foo (void)
+{
+  __builtin_memcpy (dst, src, 33);
+}
+
+/* { dg-final { scan-assembler-times "vmovdqu\[ \\t\]+\[^\n\]*%ymm" 2 } } */
diff --git a/gcc/testsuite/gcc.target/i386/pieces-memcpy-6.c 
b/gcc/testsuite/gcc.target/i386/pieces-memcpy-6

[gcc r15-3079] Makefile.tpl: drop leftover intermodule cruft

2024-08-21 Thread Sam James via Gcc-cvs

https://gcc.gnu.org/g:d6a112afe7cd9ade0d06c3128d1f29b6454a7f5c

commit r15-3079-gd6a112afe7cd9ade0d06c3128d1f29b6454a7f5c
Author: Sam James 
Date:   Wed Aug 14 13:22:02 2024 +0100

Makefile.tpl: drop leftover intermodule cruft

intermodule supported was dropped in r0-103106-gde6ba7aee152a0 with some
remaining bits for Fortran removed in r14-1696-gecc96eb5d2a0e5.

Remove some small leftovers.

* Makefile.in: Regenerate.
* Makefile.tpl (STAGE1_CONFIGURE_FLAGS): Remove 
--disable-intermodule.

Diff:
---
 Makefile.in  | 11 ---
 Makefile.tpl | 11 ---
 2 files changed, 8 insertions(+), 14 deletions(-)

diff --git a/Makefile.in b/Makefile.in
index 34c5550beca2..a1a56bb5dd2c 100644
--- a/Makefile.in
+++ b/Makefile.in
@@ -610,14 +610,11 @@ STAGEautofeedback_CONFIGURE_FLAGS = 
$(STAGE_CONFIGURE_FLAGS)
 STAGE1_CFLAGS = @stage1_cflags@
 STAGE1_CHECKING = @stage1_checking@
 STAGE1_LANGUAGES = @stage1_languages@
-# * We force-disable intermodule optimizations, even if
-#   --enable-intermodule was passed, since the installed compiler
-#   probably can't handle them.  Luckily, autoconf always respects
-#   the last argument when conflicting --enable arguments are passed.
-# * Likewise, we force-disable coverage flags, since the installed
-#   compiler probably has never heard of them.
+# * We force-disable coverage flags, since the installed compiler probably
+#   has never heard of them. Luckily, autoconf always respects the last
+#   argument when conflicting --enable arguments are passed.
 # * We also disable -Wformat, since older GCCs don't understand newer %s.
-STAGE1_CONFIGURE_FLAGS = --disable-intermodule $(STAGE1_CHECKING) \
+STAGE1_CONFIGURE_FLAGS = $(STAGE1_CHECKING) \
  --disable-coverage --enable-languages="$(STAGE1_LANGUAGES)" \
  --disable-build-format-warnings
 
diff --git a/Makefile.tpl b/Makefile.tpl
index 8f4bf297918c..cbb3c6789dcf 100644
--- a/Makefile.tpl
+++ b/Makefile.tpl
@@ -533,14 +533,11 @@ STAGE[+id+]_CONFIGURE_FLAGS = $(STAGE_CONFIGURE_FLAGS)
 STAGE1_CFLAGS = @stage1_cflags@
 STAGE1_CHECKING = @stage1_checking@
 STAGE1_LANGUAGES = @stage1_languages@
-# * We force-disable intermodule optimizations, even if
-#   --enable-intermodule was passed, since the installed compiler
-#   probably can't handle them.  Luckily, autoconf always respects
-#   the last argument when conflicting --enable arguments are passed.
-# * Likewise, we force-disable coverage flags, since the installed
-#   compiler probably has never heard of them.
+# * We force-disable coverage flags, since the installed compiler probably
+#   has never heard of them. Luckily, autoconf always respects the last
+#   argument when conflicting --enable arguments are passed.
 # * We also disable -Wformat, since older GCCs don't understand newer %s.
-STAGE1_CONFIGURE_FLAGS = --disable-intermodule $(STAGE1_CHECKING) \
+STAGE1_CONFIGURE_FLAGS = $(STAGE1_CHECKING) \
  --disable-coverage --enable-languages="$(STAGE1_LANGUAGES)" \
  --disable-build-format-warnings

[gcc r15-3080] Makefile.tpl: fix whitespace in licence header

2024-08-21 Thread Sam James via Gcc-cvs

https://gcc.gnu.org/g:c1aba5e7e7da5f2bd75873d3853f1de85addc2ac

commit r15-3080-gc1aba5e7e7da5f2bd75873d3853f1de85addc2ac
Author: Sam James 
Date:   Wed Aug 14 13:25:01 2024 +0100

Makefile.tpl: fix whitespace in licence header

* Makefile.in: Regenerate.
* Makefile.tpl: Fix whitespace.

Signed-off-by: Sam James 

Diff:
---
 Makefile.in  | 4 ++--
 Makefile.tpl | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/Makefile.in b/Makefile.in
index a1a56bb5dd2c..966d60454960 100644
--- a/Makefile.in
+++ b/Makefile.in
@@ -10,12 +10,12 @@
 # it under the terms of the GNU General Public License as published by
 # the Free Software Foundation; either version 3 of the License, or
 # (at your option) any later version.
-# 
+#
 # This program is distributed in the hope that it will be useful,
 # but WITHOUT ANY WARRANTY; without even the implied warranty of
 # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 # GNU General Public License for more details.
-# 
+#
 # You should have received a copy of the GNU General Public License
 # along with this program; see the file COPYING3.  If not see
 # .
diff --git a/Makefile.tpl b/Makefile.tpl
index cbb3c6789dcf..da38dca697ad 100644
--- a/Makefile.tpl
+++ b/Makefile.tpl
@@ -13,12 +13,12 @@ in
 # it under the terms of the GNU General Public License as published by
 # the Free Software Foundation; either version 3 of the License, or
 # (at your option) any later version.
-# 
+#
 # This program is distributed in the hope that it will be useful,
 # but WITHOUT ANY WARRANTY; without even the implied warranty of
 # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 # GNU General Public License for more details.
-# 
+#
 # You should have received a copy of the GNU General Public License
 # along with this program; see the file COPYING3.  If not see
 # .

[gcc r15-3081] Dump aliases in -fcallgraph-info

2024-08-21 Thread Alexandre Oliva via Gcc-cvs

https://gcc.gnu.org/g:23496098bba769044ed352c0d7bdb317477c16ac

commit r15-3081-g23496098bba769044ed352c0d7bdb317477c16ac
Author: Alexandre Oliva 
Date:   Thu Aug 22 01:27:55 2024 -0300

Dump aliases in -fcallgraph-info

Dump ICF-unified decls, thunks, aliases and whatnot along with their
ultimate targets, with edges from the alias to the target.

Add support for dropping the source file's suffix when forming from
dump-base, so that auxiliary files can be scanned, such as the .ci
files generated by -fcallgraph-info, as in the testcase.


for  gcc/ChangeLog

* toplev.cc (dump_final_alias_vcg): New.
(dump_final_node_vcg): Dump aliases along with node.

for  gcc/testsuite/ChangeLog

* lib/scandump.exp (dump-base): Support {} in dump base suffix
to drop it.
* gcc.dg/callgraph-info-1.c: New.

Diff:
---
 gcc/testsuite/gcc.dg/callgraph-info-1.c |  7 +++
 gcc/testsuite/lib/scandump.exp  |  4 
 gcc/toplev.cc   | 37 +
 3 files changed, 48 insertions(+)

diff --git a/gcc/testsuite/gcc.dg/callgraph-info-1.c 
b/gcc/testsuite/gcc.dg/callgraph-info-1.c
new file mode 100644
index ..853ff9554eeb
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/callgraph-info-1.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-options "-fcallgraph-info" } */
+
+void f() {}
+void g() __attribute__ ((__alias__ ("f")));
+
+/* { dg-final { scan-dump-times "ci" "triangle" 1 "ci" {{}} } } */
diff --git a/gcc/testsuite/lib/scandump.exp b/gcc/testsuite/lib/scandump.exp
index 14536ae7379b..adf9886b61c9 100644
--- a/gcc/testsuite/lib/scandump.exp
+++ b/gcc/testsuite/lib/scandump.exp
@@ -37,6 +37,10 @@ proc dump-base { args } {
 # gcc-defs to base compilation dumps only on the source basename.
 set dumpbase $src
 if { [string length $dumpbase_suf] != 0 } {
+   # Accept {} as dump base suffix to drop the source suffix entirely.
+   if { "$dumpbase_suf" == "{}" } {
+   set dumpbase_suf ""
+   }
regsub {[.][^.]*$} $src $dumpbase_suf dumpbase
 }
 return $dumpbase
diff --git a/gcc/toplev.cc b/gcc/toplev.cc
index eee4805b504a..f308fb151083 100644
--- a/gcc/toplev.cc
+++ b/gcc/toplev.cc
@@ -914,6 +914,37 @@ dump_final_callee_vcg (FILE *f, location_t location, tree 
callee)
   fputs ("\" }\n", f);
 }
 
+/* Callback for cgraph_node::call_for_symbol_thunks_and_aliases to dump to F_ a
+   node and an edge from ALIAS->DECL to CURRENT_FUNCTION_DECL.  */
+
+static bool
+dump_final_alias_vcg (cgraph_node *alias, void *f_)
+{
+  FILE *f = (FILE *)f_;
+
+  if (alias->decl == current_function_decl)
+return false;
+
+  dump_final_node_vcg_start (f, alias->decl);
+  fputs ("\" shape : triangle }\n", f);
+
+  fputs ("edge: { sourcename: \"", f);
+  print_decl_identifier (f, alias->decl, PRINT_DECL_UNIQUE_NAME);
+  fputs ("\" targetname: \"", f);
+  print_decl_identifier (f, current_function_decl, PRINT_DECL_UNIQUE_NAME);
+  location_t location = DECL_SOURCE_LOCATION (alias->decl);
+  if (LOCATION_LOCUS (location) != UNKNOWN_LOCATION)
+{
+  expanded_location loc;
+  fputs ("\" label: \"", f);
+  loc = expand_location (location);
+  fprintf (f, "%s:%d:%d", loc.file, loc.line, loc.column);
+}
+  fputs ("\" }\n", f);
+
+  return false;
+}
+
 /* Dump final cgraph node in VCG format.  */
 
 static void
@@ -950,6 +981,12 @@ dump_final_node_vcg (FILE *f)
 dump_final_callee_vcg (f, c->location, c->decl);
   vec_free (cfun->su->callees);
   cfun->su->callees = NULL;
+
+  cgraph_node *node = cgraph_node::get (current_function_decl);
+  if (!node)
+return;
+  node->call_for_symbol_thunks_and_aliases (dump_final_alias_vcg, f,
+   true, false);
 }
 
 /* Output stack usage and callgraph info, as requested.  */

[gcc r13-8988] Fix testcase failure.

2024-08-21 Thread hongtao Liu via Gcc-cvs

https://gcc.gnu.org/g:ea9c508927ec032c6d67a24df59ffa429e4d3d95

commit r13-8988-gea9c508927ec032c6d67a24df59ffa429e4d3d95
Author: liuhongt 
Date:   Thu Aug 22 14:31:40 2024 +0800

Fix testcase failure.

gcc/testsuite/ChangeLog:

* gcc.target/i386/pieces-memcpy-10.c: Use -mmove-max=256 and
-mstore-max=256.
* gcc.target/i386/pieces-memcpy-6.c: Ditto.
* gcc.target/i386/pieces-memset-38.c: Ditto.
* gcc.target/i386/pieces-memset-40.c: Ditto.
* gcc.target/i386/pieces-memset-41.c: Ditto.
* gcc.target/i386/pieces-memset-42.c: Ditto.
* gcc.target/i386/pieces-memset-43.c: Ditto.
* gcc.target/i386/pieces-strcpy-2.c: Ditto.

Diff:
---
 gcc/testsuite/gcc.target/i386/pieces-memcpy-10.c | 2 +-
 gcc/testsuite/gcc.target/i386/pieces-memcpy-6.c  | 2 +-
 gcc/testsuite/gcc.target/i386/pieces-memset-38.c | 2 +-
 gcc/testsuite/gcc.target/i386/pieces-memset-40.c | 2 +-
 gcc/testsuite/gcc.target/i386/pieces-memset-41.c | 2 +-
 gcc/testsuite/gcc.target/i386/pieces-memset-42.c | 2 +-
 gcc/testsuite/gcc.target/i386/pieces-memset-43.c | 2 +-
 gcc/testsuite/gcc.target/i386/pieces-strcpy-2.c  | 2 +-
 8 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/gcc/testsuite/gcc.target/i386/pieces-memcpy-10.c 
b/gcc/testsuite/gcc.target/i386/pieces-memcpy-10.c
index 53ad0b3be443..78f92ac5197d 100644
--- a/gcc/testsuite/gcc.target/i386/pieces-memcpy-10.c
+++ b/gcc/testsuite/gcc.target/i386/pieces-memcpy-10.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O2 -mno-avx2 -mavx -mprefer-vector-width=128 
-mtune=sandybridge" } */
+/* { dg-options "-O2 -mno-avx2 -mavx -mmove-max=128 -mstore-max=128 
-mtune=sandybridge" } */
 
 extern char *dst, *src;
 
diff --git a/gcc/testsuite/gcc.target/i386/pieces-memcpy-6.c 
b/gcc/testsuite/gcc.target/i386/pieces-memcpy-6.c
index cfd2a86cf33b..57b74ae4b230 100644
--- a/gcc/testsuite/gcc.target/i386/pieces-memcpy-6.c
+++ b/gcc/testsuite/gcc.target/i386/pieces-memcpy-6.c
@@ -1,5 +1,5 @@
 /* { dg-do compile { target { ! ia32 } } } */
-/* { dg-options "-O2 -mno-avx2 -mavx -mprefer-vector-width=128 
-mtune=sandybridge" } */
+/* { dg-options "-O2 -mno-avx2 -mavx -mmove-max=128 -mstore-max=128 
-mtune=sandybridge" } */
 
 extern char *dst, *src;
 
diff --git a/gcc/testsuite/gcc.target/i386/pieces-memset-38.c 
b/gcc/testsuite/gcc.target/i386/pieces-memset-38.c
index ddd194debd57..d9443678735d 100644
--- a/gcc/testsuite/gcc.target/i386/pieces-memset-38.c
+++ b/gcc/testsuite/gcc.target/i386/pieces-memset-38.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O2 -mno-avx512f -mavx2 -mprefer-vector-width=128 
-mtune=sandybridge" } */
+/* { dg-options "-O2 -mno-avx512f -mavx2 -mmove-max=128 -mstore-max=128 
-mtune=sandybridge" } */
 
 extern char *dst;
 
diff --git a/gcc/testsuite/gcc.target/i386/pieces-memset-40.c 
b/gcc/testsuite/gcc.target/i386/pieces-memset-40.c
index 9c206465d465..8ad6ad7e494a 100644
--- a/gcc/testsuite/gcc.target/i386/pieces-memset-40.c
+++ b/gcc/testsuite/gcc.target/i386/pieces-memset-40.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O2 -mno-avx512f -mavx2 -mprefer-vector-width=128 
-mtune=sandybridge" } */
+/* { dg-options "-O2 -mno-avx512f -mavx2 -mmove-max=128 -mstore-max=128 
-mtune=sandybridge" } */
 
 extern char *dst;
 
diff --git a/gcc/testsuite/gcc.target/i386/pieces-memset-41.c 
b/gcc/testsuite/gcc.target/i386/pieces-memset-41.c
index b0756182e355..08fd6e9a9278 100644
--- a/gcc/testsuite/gcc.target/i386/pieces-memset-41.c
+++ b/gcc/testsuite/gcc.target/i386/pieces-memset-41.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O2 -mno-avx2 -mavx -mprefer-vector-width=128 
-mtune=sandybridge -mno-stackrealign" } */
+/* { dg-options "-O2 -mno-avx2 -mavx -mmove-max=128 -mstore-max=128 
-mtune=sandybridge -mno-stackrealign" } */
 
 extern char *dst;
 
diff --git a/gcc/testsuite/gcc.target/i386/pieces-memset-42.c 
b/gcc/testsuite/gcc.target/i386/pieces-memset-42.c
index 103da699ae52..6b73bb256af6 100644
--- a/gcc/testsuite/gcc.target/i386/pieces-memset-42.c
+++ b/gcc/testsuite/gcc.target/i386/pieces-memset-42.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O2 -mno-avx2 -mavx -mprefer-vector-width=128 
-mtune=sandybridge" } */
+/* { dg-options "-O2 -mno-avx2 -mavx -mmove-max=128 -mstore-max=128 
-mtune=sandybridge" } */
 
 extern char *dst;
 
diff --git a/gcc/testsuite/gcc.target/i386/pieces-memset-43.c 
b/gcc/testsuite/gcc.target/i386/pieces-memset-43.c
index f1494e176105..c6c7ff234dab 100644
--- a/gcc/testsuite/gcc.target/i386/pieces-memset-43.c
+++ b/gcc/testsuite/gcc.target/i386/pieces-memset-43.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O2 -mno-avx2 -mavx -mprefer-vector-width=128 
-mtune=sandybridge" } */
+/* { dg-options "-O2 -mno-avx2 -mavx -mmove-max=128 -mstore-max=128 
-mtune=sandybridge" } */
 
 extern char *dst;
 
diff --git a/gcc/testsuite/gcc.target/i386/pieces-strcpy-2.c 
b/

[gcc r15-3062] Fortran: Fix ICE in sizeof(coarray) [PR77518]

[gcc r15-3063] testsuite: i386: Fix g++.target/i386/pr116275-2.C on Solaris/x86

[gcc r15-3064] c++, coroutines: Check for malformed functions before splitting.

[gcc r15-3065] libstdc++: Fix std::variant to reject array types [PR116381]

[gcc r15-3066] Fix coarray rank for non-coarrays in derived types. [PR86468]

[gcc r15-3067] libstdc++: Check ios::uppercase for ios::fixed floating-point output [PR114862]

[gcc r15-3068] libstdc++: Use strlen for std::char_traits::length [PR102958]

[gcc r15-3069] tree-optimization/116380 - bogus SSA update with loop distribution

[gcc r15-3070] sra: Avoid risking x87 magling binary representation of a replacement (PR 58416)

[gcc r13-8985] [testsuite] [arm] [vect] adjust mve-vshr test [PR113281]

[gcc r12-10680] [testsuite] [arm] [vect] adjust mve-vshr test [PR113281]

[gcc r15-3071] tree-optimization/116406 - ICE with int<->float punning prevention

[gcc r15-3072] aarch64: Implement popcountti2 pattern [PR113042]

[gcc r15-3073] aarch64: Fix caller saves of VNx2QI [PR116238]

[gcc r15-3074] [PR rtl-optimization/116437] Fix RTL checking issue in ext-dce

[gcc r15-3075] RISC-V: Add testcases for unsigned vector .SAT_TRUNC form 2

[gcc r15-3076] RISC-V: Add testcases for unsigned vector .SAT_TRUNC form 3

[gcc(refs/vendors/microsoft/heads/main)] Update xfail with new failures

[gcc r15-3078] Align ix86_{move_max,store_max} with vectorizer.

[gcc r14-10608] Align ix86_{move_max,store_max} with vectorizer.

[gcc r13-8987] Align ix86_{move_max,store_max} with vectorizer.

[gcc r12-10682] Align ix86_{move_max,store_max} with vectorizer.

[gcc r15-3079] Makefile.tpl: drop leftover intermodule cruft

[gcc r15-3080] Makefile.tpl: fix whitespace in licence header

[gcc r15-3081] Dump aliases in -fcallgraph-info

[gcc r13-8988] Fix testcase failure.

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