[gcc(refs/users/meissner/heads/work176)] Add support for -mcpu=future
https://gcc.gnu.org/g:1a0f5719564e2e806b11c8584fcd2386ae0bf36a
commit 1a0f5719564e2e806b11c8584fcd2386ae0bf36a
Author: Michael Meissner
Date: Sat Aug 17 03:24:08 2024 -0400
Add support for -mcpu=future
This patch adds the support that can be used in developing GCC support for
future PowerPC processors.
2024-08-17 Michael Meissner
* config.gcc (powerpc*-*-*): Add support for --with-cpu=future.
* config/rs6000/aix71.h (ASM_CPU_SPEC): Add support for
-mcpu=future.
* config/rs6000/aix72.h (ASM_CPU_SPEC): Likewise.
* config/rs6000/aix73.h (ASM_CPU_SPEC): Likewise.
* config/rs6000/driver-rs6000.cc (asm_names): Likewise.
* config/rs6000/rs6000-arch.def: Add future cpu.
* config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): If
-mcpu=future, define _ARCH_FUTURE.
* config/rs6000/rs6000-cpus.def (FUTURE_MASKS_SERVER): New macro.
(future cpu): Define.
* config/rs6000/rs6000-opts.h (enum processor_type): Add
PROCESSOR_FUTURE.
* config/rs6000/rs6000-tables.opt: Regenerate.
* config/rs6000/rs6000.cc (power10_cost): Update comment.
(get_arch_flags): Add support for future processor.
(rs6000_option_override_internal): Likewise.
(rs6000_machine_from_flags): Likewise.
(rs6000_reassociation_width): Likewise.
(rs6000_adjust_cost): Likewise.
(rs6000_issue_rate): Likewise.
(rs6000_sched_reorder): Likewise.
(rs6000_sched_reorder2): Likewise.
(rs6000_register_move_cost): Likewise.
* config/rs6000/rs6000.h (ASM_CPU_SPEC): Likewise.
(TARGET_POWER11): New macro.
* config/rs6000/rs6000.md (cpu attribute): Likewise.
Diff:
---
gcc/config.gcc | 4 ++--
gcc/config/rs6000/aix71.h | 1 +
gcc/config/rs6000/aix72.h | 1 +
gcc/config/rs6000/aix73.h | 1 +
gcc/config/rs6000/driver-rs6000.cc | 2 ++
gcc/config/rs6000/rs6000-arch.def | 1 +
gcc/config/rs6000/rs6000-c.cc | 2 ++
gcc/config/rs6000/rs6000-cpus.def | 3 +++
gcc/config/rs6000/rs6000-opts.h | 1 +
gcc/config/rs6000/rs6000-tables.opt | 11 +++
gcc/config/rs6000/rs6000.cc | 34 ++
gcc/config/rs6000/rs6000.h | 2 ++
gcc/config/rs6000/rs6000.md | 2 +-
13 files changed, 50 insertions(+), 15 deletions(-)
diff --git a/gcc/config.gcc b/gcc/config.gcc
index a36dd1bcbc6..412ff100d54 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -533,7 +533,7 @@ powerpc*-*-*)
extra_headers="${extra_headers} ppu_intrinsics.h spu2vmx.h vec_types.h
si2vmx.h"
extra_headers="${extra_headers} amo.h"
case x$with_cpu in
-
xpowerpc64|xdefault64|x6[23]0|x970|xG5|xpower[3456789]|xpower1[01]|xpower6x|xrs64a|xcell|xa2|xe500mc64|xe5500|xe6500)
+
xpowerpc64|xdefault64|x6[23]0|x970|xG5|xpower[3456789]|xpower1[01]|xpower6x|xrs64a|xcell|xa2|xe500mc64|xe5500|xe6500|xfuture)
cpu_is_64bit=yes
;;
esac
@@ -5640,7 +5640,7 @@ case "${target}" in
tm_defines="${tm_defines} CONFIG_PPC405CR"
eval "with_$which=405"
;;
- "" | common | native \
+ "" | common | native | future \
| power[3456789] | power1[01] | power5+ | power6x \
| powerpc | powerpc64 | powerpc64le \
| rs64 \
diff --git a/gcc/config/rs6000/aix71.h b/gcc/config/rs6000/aix71.h
index 41037b3852d..570ddcc451d 100644
--- a/gcc/config/rs6000/aix71.h
+++ b/gcc/config/rs6000/aix71.h
@@ -79,6 +79,7 @@ do {
\
#undef ASM_CPU_SPEC
#define ASM_CPU_SPEC \
"%{mcpu=native: %(asm_cpu_native); \
+ mcpu=future: -mfuture; \
mcpu=power11: -mpwr11; \
mcpu=power10: -mpwr10; \
mcpu=power9: -mpwr9; \
diff --git a/gcc/config/rs6000/aix72.h b/gcc/config/rs6000/aix72.h
index fe59f8319b4..242ca94bd06 100644
--- a/gcc/config/rs6000/aix72.h
+++ b/gcc/config/rs6000/aix72.h
@@ -79,6 +79,7 @@ do {
\
#undef ASM_CPU_SPEC
#define ASM_CPU_SPEC \
"%{mcpu=native: %(asm_cpu_native); \
+ mcpu=future: -mfuture; \
mcpu=power11: -mpwr11; \
mcpu=power10: -mpwr10; \
mcpu=power9: -mpwr9; \
diff --git a/gcc/config/rs6000/aix73.h b/gcc/config/rs6000/aix73.h
index 1318b0b3662..2bd6b4bb3c4 100644
--- a/gcc/config/rs6000/aix73.h
+++ b/gcc/config/rs6000/aix73.h
@@ -79,6 +79,7 @@ do {
\
#undef ASM_CPU_SPEC
#define ASM_CPU_SPEC \
"%{mcpu=native: %(asm_cpu_native); \
+ mcpu=future: -mfuture; \
mcpu=power11: -mpwr11;
[gcc(refs/users/meissner/heads/work176)] Add -mcpu=future tuning support.
https://gcc.gnu.org/g:862273d6a23970f491a9dbab153e92f18110ad62 commit 862273d6a23970f491a9dbab153e92f18110ad62 Author: Michael Meissner Date: Sat Aug 17 03:24:57 2024 -0400 Add -mcpu=future tuning support. This patch makes -mtune=future use the same tuning decision as -mtune=power11. 2024-08-17 Michael Meissner gcc/ * config/rs6000/power10.md (all reservations): Add future as an alterntive to power10 and power11. Diff: --- gcc/config/rs6000/power10.md | 144 +-- 1 file changed, 72 insertions(+), 72 deletions(-) diff --git a/gcc/config/rs6000/power10.md b/gcc/config/rs6000/power10.md index 2310c460345..e42b057dc45 100644 --- a/gcc/config/rs6000/power10.md +++ b/gcc/config/rs6000/power10.md @@ -1,4 +1,4 @@ -;; Scheduling description for the IBM Power10 and Power11 processors. +;; Scheduling description for the IBM Power10, Power11, and Future processors. ;; Copyright (C) 2020-2024 Free Software Foundation, Inc. ;; ;; Contributed by Pat Haugen (pthau...@us.ibm.com). @@ -97,12 +97,12 @@ (eq_attr "update" "no") (eq_attr "size" "!128") (eq_attr "prefixed" "no") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_any_power10,LU_power10") (define_insn_reservation "power10-fused-load" 4 (and (eq_attr "type" "fused_load_cmpi,fused_addis_load,fused_load_load") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_even_power10,LU_power10") (define_insn_reservation "power10-prefixed-load" 4 @@ -110,13 +110,13 @@ (eq_attr "update" "no") (eq_attr "size" "!128") (eq_attr "prefixed" "yes") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_even_power10,LU_power10") (define_insn_reservation "power10-load-update" 4 (and (eq_attr "type" "load") (eq_attr "update" "yes") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_even_power10,LU_power10+SXU_power10") (define_insn_reservation "power10-fpload-double" 4 @@ -124,7 +124,7 @@ (eq_attr "update" "no") (eq_attr "size" "64") (eq_attr "prefixed" "no") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_any_power10,LU_power10") (define_insn_reservation "power10-prefixed-fpload-double" 4 @@ -132,14 +132,14 @@ (eq_attr "update" "no") (eq_attr "size" "64") (eq_attr "prefixed" "yes") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_even_power10,LU_power10") (define_insn_reservation "power10-fpload-update-double" 4 (and (eq_attr "type" "fpload") (eq_attr "update" "yes") (eq_attr "size" "64") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_even_power10,LU_power10+SXU_power10") ; SFmode loads are cracked and have additional 3 cycles over DFmode @@ -148,27 +148,27 @@ (and (eq_attr "type" "fpload") (eq_attr "update" "no") (eq_attr "size" "32") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_even_power10,LU_power10") (define_insn_reservation "power10-fpload-update-single" 7 (and (eq_attr "type" "fpload") (eq_attr "update" "yes") (eq_attr "size" "32") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_even_power10,LU_power10+SXU_power10") (define_insn_reservation "power10-vecload" 4 (and (eq_attr "type" "vecload") (eq_attr "size" "!256") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_any_power10,LU_power10") ; lxvp (define_insn_reservation "power10-vecload-pair" 4 (and (eq_attr "type" "vecload") (eq_attr "size" "256") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_even_power10,LU_power10+SXU_power10") ; Store Unit @@ -178,12 +178,12 @@ (eq_attr "prefixed" "no") (eq_attr "size" "!128") (eq_attr "size" "!256") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_any_power10,STU_power10") (define_insn_reservation "power10-fused-store" 0 (and (eq_attr "type" "fused_store_store") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_even_power10,STU_power10") (define_insn_reservation "power10-prefixed-store" 0 @@ -191,52 +191,52 @@ (eq_attr "prefixed" "yes") (eq_attr "size" "!128") (eq_attr "size" "!256") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_even_power10,STU_power10") ; Update forms have 2 cycle latency for updated
[gcc(refs/users/meissner/heads/work176)] Update ChangeLog.*
https://gcc.gnu.org/g:04913bc20cb2a9519f94631ccb3458c057b5c567 commit 04913bc20cb2a9519f94631ccb3458c057b5c567 Author: Michael Meissner Date: Sat Aug 17 05:40:54 2024 -0400 Update ChangeLog.* Diff: --- gcc/ChangeLog.meissner | 49 + 1 file changed, 49 insertions(+) diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner index 24abcad81cb..d1366c23650 100644 --- a/gcc/ChangeLog.meissner +++ b/gcc/ChangeLog.meissner @@ -1,3 +1,52 @@ + Branch work176, patch #21 + +Add -mcpu=future tuning support. + +This patch makes -mtune=future use the same tuning decision as -mtune=power11. + +2024-08-02 Michael Meissner + +gcc/ + + * config/rs6000/power10.md (all reservations): Add future as an + alterntive to power10 and power11. + + Branch work176, patch #20 + +Add support for -mcpu=future + +This patch adds the support that can be used in developing GCC support for +future PowerPC processors. + +2024-08-02 Michael Meissner + + * config.gcc (powerpc*-*-*): Add support for --with-cpu=future. + * config/rs6000/aix71.h (ASM_CPU_SPEC): Add support for -mcpu=future. + * config/rs6000/aix72.h (ASM_CPU_SPEC): Likewise. + * config/rs6000/aix73.h (ASM_CPU_SPEC): Likewise. + * config/rs6000/driver-rs6000.cc (asm_names): Likewise. + * config/rs6000/rs6000-arch.def: Add future cpu. + * config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): If + -mcpu=future, define _ARCH_FUTURE. + * config/rs6000/rs6000-cpus.def (FUTURE_MASKS_SERVER): New macro. + (future cpu): Define. + * config/rs6000/rs6000-opts.h (enum processor_type): Add + PROCESSOR_FUTURE. + * config/rs6000/rs6000-tables.opt: Regenerate. + * config/rs6000/rs6000.cc (power10_cost): Update comment. + (get_arch_flags): Add support for future processor. + (rs6000_option_override_internal): Likewise. + (rs6000_machine_from_flags): Likewise. + (rs6000_reassociation_width): Likewise. + (rs6000_adjust_cost): Likewise. + (rs6000_issue_rate): Likewise. + (rs6000_sched_reorder): Likewise. + (rs6000_sched_reorder2): Likewise. + (rs6000_register_move_cost): Likewise. + * config/rs6000/rs6000.h (ASM_CPU_SPEC): Likewise. + (TARGET_POWER11): New macro. + * config/rs6000/rs6000.md (cpu attribute): Likewise. + Branch work176, patch #9 Add support for -mcpu=future
[gcc r15-2963] AVR: target/116390 - Fix an avrtiny asm out template.
https://gcc.gnu.org/g:4065d163151b07b274241377e71dad028576db88
commit r15-2963-g4065d163151b07b274241377e71dad028576db88
Author: Georg-Johann Lay
Date: Sat Aug 17 12:49:42 2024 +0200
AVR: target/116390 - Fix an avrtiny asm out template.
PR target/116390
gcc/
* config/avr/avr.cc (avr_out_movsi_mr_r_reg_disp_tiny): Fix
output templates for the reg_base == reg_src and
reg_src == reg_base - 2 cases.
gcc/testsuite/
* gcc.target/avr/torture/pr116390.c: New test.
Diff:
---
gcc/config/avr/avr.cc | 30 +--
gcc/testsuite/gcc.target/avr/torture/pr116390.c | 71 +
2 files changed, 86 insertions(+), 15 deletions(-)
diff --git a/gcc/config/avr/avr.cc b/gcc/config/avr/avr.cc
index 8d59a6babed..8c19bcb34a6 100644
--- a/gcc/config/avr/avr.cc
+++ b/gcc/config/avr/avr.cc
@@ -5638,33 +5638,33 @@ avr_out_movsi_mr_r_reg_disp_tiny (rtx op[], int *l)
rtx src = op[1];
rtx base = XEXP (dest, 0);
int reg_base = REGNO (XEXP (base, 0));
- int reg_src =true_regnum (src);
+ int reg_src = true_regnum (src);
if (reg_base == reg_src)
{
*l = 11;
- return ("mov __tmp_reg__,%A2"CR_TAB
- "mov __zero_reg__,%B2" CR_TAB
+ return ("mov __tmp_reg__,%A1"CR_TAB
+ "mov __zero_reg__,%B1" CR_TAB
TINY_ADIW (%I0, %J0, %o0)CR_TAB
"st %b0+,__tmp_reg__"CR_TAB
"st %b0+,__zero_reg__" CR_TAB
- "st %b0+,%C2"CR_TAB
- "st %b0,%D2" CR_TAB
+ "st %b0+,%C1"CR_TAB
+ "st %b0,%D1" CR_TAB
"clr __zero_reg__" CR_TAB
TINY_SBIW (%I0, %J0, %o0+3));
}
else if (reg_src == reg_base - 2)
{
- *l = 11;
- return ("mov __tmp_reg__,%C2" CR_TAB
- "mov __zero_reg__,%D2"CR_TAB
- TINY_ADIW (%I0, %J0, %o0) CR_TAB
- "st %b0+,%A0" CR_TAB
- "st %b0+,%B0" CR_TAB
- "st %b0+,__tmp_reg__" CR_TAB
- "st %b0,__zero_reg__" CR_TAB
- "clr __zero_reg__"CR_TAB
- TINY_SBIW (%I0, %J0, %o0+3));
+ // This awkward case can occur when ext-dce turns zero-extend:SI(HI)
+ // into a paradoxical subreg, which register allocation may turn into
+ // something like *(R28:HI + 7) = R26:SI. There is actually no need
+ // to store the upper 2 bytes of R26:SI as they are unused rubbish.
+ // See PR116390.
+ *l = 6;
+ return (TINY_ADIW (%I0, %J0, %o0) CR_TAB
+ "st %b0+,%A1" CR_TAB
+ "st %b0,%B1" CR_TAB
+ TINY_SBIW (%I0, %J0, %o0+1));
}
*l = 8;
return (TINY_ADIW (%I0, %J0, %o0) CR_TAB
diff --git a/gcc/testsuite/gcc.target/avr/torture/pr116390.c
b/gcc/testsuite/gcc.target/avr/torture/pr116390.c
new file mode 100644
index 000..70c1ad62936
--- /dev/null
+++ b/gcc/testsuite/gcc.target/avr/torture/pr116390.c
@@ -0,0 +1,71 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99" } */
+
+typedef struct
+{
+int i;
+} MyStruct;
+
+void f_ic (int, char);
+void f_pi (char const *, int);
+void f_iic (int, int, char);
+
+const MyStruct *f_rms (void);
+
+char *f_rcp (void);
+int f_ri (void);
+
+void badFoo (void)
+{
+const MyStruct* ps = f_rms ();
+const char* pc = f_rcp ();
+
+unsigned n1 = f_rcp () - pc;
+
+if (n1)
+{
+long n2 = n1 - ps->i;
+if (n2 > 0)
+{
+if (f_ri ())
+n2 = n1;
+
+if (f_ri ())
+{
+f_iic (1, 2 * n2, ' ');
+}
+else
+f_pi (pc, n2);
+}
+if (ps->i > 0)
+{
+if (n2 >= 0)
+f_pi (pc + n2, ps->i);
+else
+{
+f_ic (n2, ' ');
+}
+}
+
+const int which = f_ri ();
+switch (which)
+{
+case 1:
+if (f_ri ())
+f_rcp ()[1] = ' ';
+break;
+
+case 2:
+f_pi (f_rcp (), 1);
+break;
+
+case 3:
+if (f_ri () && n1 < 0)
+f_ic (n1, ' ');
+else
+f_rcp ()[1] = ' ';
+break;
+
+}
+}
+}
[gcc r15-2964] doc: Tweak link to gm2 list archive
https://gcc.gnu.org/g:b9f08459c483086b956e7b3e396759fc42460b4c
commit r15-2964-gb9f08459c483086b956e7b3e396759fc42460b4c
Author: Gerald Pfeifer
Date: Sat Aug 17 13:26:36 2024 +0200
doc: Tweak link to gm2 list archive
Without the trailing slash we incur a "301 Moved Permanently".
gcc:
* doc/gm2.texi (Community): Tweak link to gm2 list archive.
Diff:
---
gcc/doc/gm2.texi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/doc/gm2.texi b/gcc/doc/gm2.texi
index bfc8dc71f23..40668f7f8c4 100644
--- a/gcc/doc/gm2.texi
+++ b/gcc/doc/gm2.texi
@@ -3015,7 +3015,7 @@ email to:
or by
@url{https://lists.nongnu.org/mailman/listinfo/gm2}.
The mailing list contents can be viewed
-@url{https://lists.gnu.org/archive/html/gm2}.
+@url{https://lists.gnu.org/archive/html/gm2/}.
@node Other languages, , Community, Using
@section Other languages for GCC
[gcc r15-2965] libstdc++: Tweak links to installation docs
https://gcc.gnu.org/g:16b92be67623f3bfa3b68dbdcf5fe7c060e91180 commit r15-2965-g16b92be67623f3bfa3b68dbdcf5fe7c060e91180 Author: Gerald Pfeifer Date: Sat Aug 17 13:47:09 2024 +0200 libstdc++: Tweak links to installation docs libstdc++v-3: * doc/xml/manual/prerequisites.xml: Tweak two links to installation docs. Fix grammar. * doc/html/manual/setup.html: Regenerate. Diff: --- libstdc++-v3/doc/html/manual/setup.html | 7 --- libstdc++-v3/doc/xml/manual/prerequisites.xml | 4 ++-- 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/libstdc++-v3/doc/html/manual/setup.html b/libstdc++-v3/doc/html/manual/setup.html index 1963cdf695a..78d2a00c50a 100644 --- a/libstdc++-v3/doc/html/manual/setup.html +++ b/libstdc++-v3/doc/html/manual/setup.html @@ -21,9 +21,10 @@ Prerequisites Because libstdc++ is part of GCC, the primary source for installation instructions is - http://gcc.gnu.org/install/"; target="_top">the GCC install page. - In particular, list of prerequisite software needed to build the library - http://gcc.gnu.org/install/prerequisites.html"; target="_top"> + https://gcc.gnu.org/install/"; target="_top">the GCC install page. + In particular, the list of prerequisite software needed to build + the library + https://gcc.gnu.org/install/prerequisites.html"; target="_top"> starts with those requirements. The same pages also list the tools you will need if you wish to modify the source. diff --git a/libstdc++-v3/doc/xml/manual/prerequisites.xml b/libstdc++-v3/doc/xml/manual/prerequisites.xml index a02d3795830..a3c6e732a77 100644 --- a/libstdc++-v3/doc/xml/manual/prerequisites.xml +++ b/libstdc++-v3/doc/xml/manual/prerequisites.xml @@ -14,9 +14,9 @@ Because libstdc++ is part of GCC, the primary source for installation instructions is - http://www.w3.org/1999/xlink"; xlink:href="http://gcc.gnu.org/install/";>the GCC install page. + http://www.w3.org/1999/xlink"; xlink:href="https://gcc.gnu.org/install/";>the GCC install page. In particular, list of prerequisite software needed to build the library - http://www.w3.org/1999/xlink"; xlink:href="http://gcc.gnu.org/install/prerequisites.html";> + http://www.w3.org/1999/xlink"; xlink:href="https://gcc.gnu.org/install/prerequisites.html";> starts with those requirements. The same pages also list the tools you will need if you wish to modify the source.
[gcc r15-2966] doc: Tweak PIM4 link
https://gcc.gnu.org/g:2af578434b21ac224d720808486ceeb023cd89c0
commit r15-2966-g2af578434b21ac224d720808486ceeb023cd89c0
Author: Gerald Pfeifer
Date: Sat Aug 17 14:04:31 2024 +0200
doc: Tweak PIM4 link
gcc:
* doc/gm2.texi (What is GNU Modula-2): Tweak PIM4 link.
Diff:
---
gcc/doc/gm2.texi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/doc/gm2.texi b/gcc/doc/gm2.texi
index 40668f7f8c4..b2e4aa2e9c0 100644
--- a/gcc/doc/gm2.texi
+++ b/gcc/doc/gm2.texi
@@ -108,7 +108,7 @@ PIM3: 'Programming in Modula-2', 3rd Corrected Edition,
Springer Verlag,
1985 (PIM3).
PIM4: 'Programming in Modula-2', 4th Edition, Springer Verlag, 1988
-(@uref{http://freepages.modula2.org/report4/modula-2.html, PIM4}).
+(@uref{https://freepages.modula2.org/report4/modula-2.html, PIM4}).
ISO: the ISO Modula-2 language as defined in 'ISO/IEC Information
technology - programming languages - part 1: Modula-2 Language,
[gcc r14-10597] AVR: target/116390 - Fix an avrtiny asm out template.
https://gcc.gnu.org/g:f3d9c120a1959c5b094001516c1e5cb4ba6f4080
commit r14-10597-gf3d9c120a1959c5b094001516c1e5cb4ba6f4080
Author: Georg-Johann Lay
Date: Sat Aug 17 12:49:42 2024 +0200
AVR: target/116390 - Fix an avrtiny asm out template.
PR target/116390
gcc/
* config/avr/avr.cc (avr_out_movsi_mr_r_reg_disp_tiny): Fix
output templates for the reg_base == reg_src and
reg_src == reg_base - 2 cases.
gcc/testsuite/
* gcc.target/avr/torture/pr116390.c: New test.
(cherry picked from commit 4065d163151b07b274241377e71dad028576db88)
Diff:
---
gcc/config/avr/avr.cc | 30 +--
gcc/testsuite/gcc.target/avr/torture/pr116390.c | 71 +
2 files changed, 86 insertions(+), 15 deletions(-)
diff --git a/gcc/config/avr/avr.cc b/gcc/config/avr/avr.cc
index 71929b28160..3c1a0bf707f 100644
--- a/gcc/config/avr/avr.cc
+++ b/gcc/config/avr/avr.cc
@@ -5501,33 +5501,33 @@ avr_out_movsi_mr_r_reg_disp_tiny (rtx op[], int *l)
rtx src = op[1];
rtx base = XEXP (dest, 0);
int reg_base = REGNO (XEXP (base, 0));
- int reg_src =true_regnum (src);
+ int reg_src = true_regnum (src);
if (reg_base == reg_src)
{
*l = 11;
- return ("mov __tmp_reg__,%A2"CR_TAB
- "mov __zero_reg__,%B2" CR_TAB
+ return ("mov __tmp_reg__,%A1"CR_TAB
+ "mov __zero_reg__,%B1" CR_TAB
TINY_ADIW (%I0, %J0, %o0)CR_TAB
"st %b0+,__tmp_reg__"CR_TAB
"st %b0+,__zero_reg__" CR_TAB
- "st %b0+,%C2"CR_TAB
- "st %b0,%D2" CR_TAB
+ "st %b0+,%C1"CR_TAB
+ "st %b0,%D1" CR_TAB
"clr __zero_reg__" CR_TAB
TINY_SBIW (%I0, %J0, %o0+3));
}
else if (reg_src == reg_base - 2)
{
- *l = 11;
- return ("mov __tmp_reg__,%C2" CR_TAB
- "mov __zero_reg__,%D2"CR_TAB
- TINY_ADIW (%I0, %J0, %o0) CR_TAB
- "st %b0+,%A0" CR_TAB
- "st %b0+,%B0" CR_TAB
- "st %b0+,__tmp_reg__" CR_TAB
- "st %b0,__zero_reg__" CR_TAB
- "clr __zero_reg__"CR_TAB
- TINY_SBIW (%I0, %J0, %o0+3));
+ // This awkward case can occur when ext-dce turns zero-extend:SI(HI)
+ // into a paradoxical subreg, which register allocation may turn into
+ // something like *(R28:HI + 7) = R26:SI. There is actually no need
+ // to store the upper 2 bytes of R26:SI as they are unused rubbish.
+ // See PR116390.
+ *l = 6;
+ return (TINY_ADIW (%I0, %J0, %o0) CR_TAB
+ "st %b0+,%A1" CR_TAB
+ "st %b0,%B1" CR_TAB
+ TINY_SBIW (%I0, %J0, %o0+1));
}
*l = 8;
return (TINY_ADIW (%I0, %J0, %o0) CR_TAB
diff --git a/gcc/testsuite/gcc.target/avr/torture/pr116390.c
b/gcc/testsuite/gcc.target/avr/torture/pr116390.c
new file mode 100644
index 000..70c1ad62936
--- /dev/null
+++ b/gcc/testsuite/gcc.target/avr/torture/pr116390.c
@@ -0,0 +1,71 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99" } */
+
+typedef struct
+{
+int i;
+} MyStruct;
+
+void f_ic (int, char);
+void f_pi (char const *, int);
+void f_iic (int, int, char);
+
+const MyStruct *f_rms (void);
+
+char *f_rcp (void);
+int f_ri (void);
+
+void badFoo (void)
+{
+const MyStruct* ps = f_rms ();
+const char* pc = f_rcp ();
+
+unsigned n1 = f_rcp () - pc;
+
+if (n1)
+{
+long n2 = n1 - ps->i;
+if (n2 > 0)
+{
+if (f_ri ())
+n2 = n1;
+
+if (f_ri ())
+{
+f_iic (1, 2 * n2, ' ');
+}
+else
+f_pi (pc, n2);
+}
+if (ps->i > 0)
+{
+if (n2 >= 0)
+f_pi (pc + n2, ps->i);
+else
+{
+f_ic (n2, ' ');
+}
+}
+
+const int which = f_ri ();
+switch (which)
+{
+case 1:
+if (f_ri ())
+f_rcp ()[1] = ' ';
+break;
+
+case 2:
+f_pi (f_rcp (), 1);
+break;
+
+case 3:
+if (f_ri () && n1 < 0)
+f_ic (n1, ' ');
+else
+f_rcp ()[1] = ' ';
+break;
+
+}
+}
+}
[gcc r15-2967] libstdc++: Update references to gcc.gnu.org/onlinedocs
https://gcc.gnu.org/g:e68ab0f16072af97f0898fa0a14e72fcda442775 commit r15-2967-ge68ab0f16072af97f0898fa0a14e72fcda442775 Author: Gerald Pfeifer Date: Sat Aug 17 15:21:21 2024 +0200 libstdc++: Update references to gcc.gnu.org/onlinedocs libstdc++-v3: * doc/xml/manual/abi.xml: Update reference to gcc.gnu.org/onlinedocs. * doc/xml/manual/concurrency_extensions.xml (interface): Ditto. * doc/xml/manual/extensions.xml: Ditto. * doc/xml/manual/parallel_mode.xml: Ditto. * doc/xml/manual/shared_ptr.xml: Ditto. * doc/xml/manual/using_exceptions.xml: Ditto. And change GNU GCC to GCC. * doc/html/manual/abi.html: Regenerate. * doc/html/manual/ext_concurrency_impl.html: Ditto. * doc/html/manual/ext_demangling.html: Ditto. * doc/html/manual/memory.html: Ditto. * doc/html/manual/parallel_mode_design.html: Ditto. * doc/html/manual/parallel_mode_using.html: Ditto. * doc/html/manual/using_exceptions.html: Ditto. Diff: --- libstdc++-v3/doc/html/manual/abi.html | 2 +- libstdc++-v3/doc/html/manual/ext_concurrency_impl.html | 4 ++-- libstdc++-v3/doc/html/manual/ext_demangling.html | 2 +- libstdc++-v3/doc/html/manual/memory.html | 2 +- libstdc++-v3/doc/html/manual/parallel_mode_design.html | 2 +- libstdc++-v3/doc/html/manual/parallel_mode_using.html | 2 +- libstdc++-v3/doc/html/manual/using_exceptions.html | 2 +- libstdc++-v3/doc/xml/manual/abi.xml| 2 +- libstdc++-v3/doc/xml/manual/concurrency_extensions.xml | 4 ++-- libstdc++-v3/doc/xml/manual/extensions.xml | 2 +- libstdc++-v3/doc/xml/manual/parallel_mode.xml | 4 ++-- libstdc++-v3/doc/xml/manual/shared_ptr.xml | 2 +- libstdc++-v3/doc/xml/manual/using_exceptions.xml | 4 ++-- 13 files changed, 17 insertions(+), 17 deletions(-) diff --git a/libstdc++-v3/doc/html/manual/abi.html b/libstdc++-v3/doc/html/manual/abi.html index 0eb6a12a501..8dab47dbb93 100644 --- a/libstdc++-v3/doc/html/manual/abi.html +++ b/libstdc++-v3/doc/html/manual/abi.html @@ -28,7 +28,7 @@ g++ command line options may change the ABI as a side-effect of use. Such flags include -fpack-struct and -fno-exceptions, but include others: see the complete - list in the GCC manual under the heading http://gcc.gnu.org/onlinedocs/gcc/Code-Gen-Options.html#Code%20Gen%20Options"; target="_top">Options + list in the GCC manual under the heading https://gcc.gnu.org/onlinedocs/gcc/Code-Gen-Options.html#Code%20Gen%20Options"; target="_top">Options for Code Generation Conventions. The configure options used when building a specific libstdc++ diff --git a/libstdc++-v3/doc/html/manual/ext_concurrency_impl.html b/libstdc++-v3/doc/html/manual/ext_concurrency_impl.html index 23b90f34572..669c07cf291 100644 --- a/libstdc++-v3/doc/html/manual/ext_concurrency_impl.html +++ b/libstdc++-v3/doc/html/manual/ext_concurrency_impl.html @@ -34,7 +34,7 @@ non-ancient x86 hardware, -march=native usually does t trick. For hosts without compiler intrinsics, but with capable hardware, hand-crafted assembly is selected. This is the case for the following hosts: crishppai386i486m48kmipssparcAnd for the rest, a simulated atomic lock via pthreads. - Detailed information about compiler intrinsics for atomic operations can be found in the GCC http://gcc.gnu.org/onlinedocs/gcc/_005f_005fatomic-Builtins.html"; target="_top"> documentation. +Detailed information about compiler intrinsics for atomic operations can be found in the GCC https://gcc.gnu.org/onlinedocs/gcc/_005f_005fatomic-Builtins.html"; target="_top"> documentation. More details on the library fallbacks from the porting section. Thread AbstractionA thin layer above IEEE 1003.1 (i.e. pthreads) is used to abstract the thread interface for GCC. This layer is called "gthread," and is @@ -44,7 +44,7 @@ a POSIX-like interface. the current host. In libstdc++ implementation files,is used to select the proper gthreads file. Within libstdc++ sources, all calls to underlying thread functionality -use this layer. More detail as to the specific interface can be found in the source http://gcc.gnu.org/onlinedocs/libstdc++/latest-doxygen/index.html"; target="_top">documentation. +use this layer. More detail as to the specific interface can be found in the source https://gcc.gnu.org/onlinedocs/libstdc++/latest-doxygen/index.html"; target="_top">documentation. By design, the gthread layer is interoperable with the types, functions, and usage found in the usual file, including pthread_t, pthread_once_t, pthread_create, diff --git a/libstdc++-v3/doc/html/manual/ext_demangling.html b/libstdc++-v3/doc/html/manual/ext_demangling.html index b5fb87b91c5..1eae99a1859 100644 --- a/libstdc++-v3/doc/html/manual/ext_demangling.html +++ b/libs
[gcc r15-2968] RISC-V: Add auto-vect pattern for vector rotate shift
https://gcc.gnu.org/g:54b228d80c54d32ab49cee6148cfd1364b2bc817
commit r15-2968-g54b228d80c54d32ab49cee6148cfd1364b2bc817
Author: Feng Wang
Date: Sat Aug 17 08:40:42 2024 -0600
RISC-V: Add auto-vect pattern for vector rotate shift
This patch add the vector rotate shift pattern for auto-vect.
With this patch, the scalar rotate shift can be automatically
vectorized into vector rotate shift.
gcc/ChangeLog:
* config/riscv/autovec.md (v3):
Add new define_expand pattern for vector rotate shift.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/binop/vrolr-1.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vrolr-run.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vrolr-template.h: New test.
Diff:
---
gcc/config/riscv/autovec.md| 16
.../gcc.target/riscv/rvv/autovec/binop/vrolr-1.c | 9 +++
.../gcc.target/riscv/rvv/autovec/binop/vrolr-run.c | 88 ++
.../riscv/rvv/autovec/binop/vrolr-template.h | 29 +++
4 files changed, 142 insertions(+)
diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index 0423d7bee13..decfe2bf8cc 100644
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -2764,3 +2764,19 @@
operands[2] = const0_rtx;
}
)
+
+;; -
+;; - vrol.vv vror.vv
+;; -
+(define_expand "v3"
+ [(set (match_operand:VI 0 "register_operand")
+ (bitmanip_rotate:VI
+ (match_operand:VI 1 "register_operand")
+ (match_operand:VI 2 "register_operand")))]
+ "TARGET_ZVBB || TARGET_ZVKB"
+ {
+riscv_vector::emit_vlmax_insn (code_for_pred_v (, mode),
+ riscv_vector::BINARY_OP, operands);
+DONE;
+ }
+)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrolr-1.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrolr-1.c
new file mode 100644
index 000..55dac27697c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrolr-1.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-add-options "riscv_v" } */
+/* { dg-add-options "riscv_zvbb" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model" } */
+
+#include "vrolr-template.h"
+
+/* { dg-final { scan-assembler-times {\tvrol\.vv} 4 } } */
+/* { dg-final { scan-assembler-times {\tvror\.vv} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrolr-run.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrolr-run.c
new file mode 100644
index 000..b659a0804f5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrolr-run.c
@@ -0,0 +1,88 @@
+/* { dg-do run } */
+/* { dg-require-effective-target "riscv_zvbb_ok" } */
+/* { dg-add-options "riscv_v" } */
+/* { dg-add-options "riscv_zvbb" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model" } */
+
+#include
+#include
+
+#include
+#include
+#include
+
+#define ARRAY_SIZE 512
+
+#define CIRCULAR_LEFT_SHIFT_ARRAY(arr, shifts, bit_size, size) \
+for (int i = 0; i < size; i++) { \
+(arr)[i] = (((arr)[i] << (shifts)[i]) | ((arr)[i] >> (bit_size -
(shifts)[i]))); \
+}
+
+#define CIRCULAR_RIGHT_SHIFT_ARRAY(arr, shifts, bit_size, size) \
+for (int i = 0; i < size; i++) { \
+(arr)[i] = (((arr)[i] >> (shifts)[i]) | ((arr)[i] << (bit_size -
(shifts)[i]))); \
+}
+
+void __attribute__((optimize("no-tree-vectorize"))) compare_results8(
+uint8_t *result_left, uint8_t *result_right,
+int bit_size, uint8_t *shift_values)
+{
+for (int i = 0; i < ARRAY_SIZE; i++) {
+assert(result_left[i] == (i << shift_values[i]) | (i >> (bit_size -
shift_values[i])));
+assert(result_right[i] == (i >> shift_values[i]) | (i << (bit_size -
shift_values[i])));
+}
+}
+
+void __attribute__((optimize("no-tree-vectorize"))) compare_results16(
+uint16_t *result_left, uint16_t *result_right,
+int bit_size, uint16_t *shift_values)
+{
+for (int i = 0; i < ARRAY_SIZE; i++) {
+assert(result_left[i] == (i << shift_values[i]) | (i >> (bit_size -
shift_values[i])));
+assert(result_right[i] == (i >> shift_values[i]) | (i << (bit_size -
shift_values[i])));
+}
+}
+
+void __attribute__((optimize("no-tree-vectorize"))) compare_results32(
+uint32_t *result_left, uint32_t *result_right,
+int bit_size, uint32_t *shift_values)
+{
+for (int i = 0; i < ARRAY_SIZE; i++) {
+assert(result_left[i] == (i << shift_values[i]) | (i >> (bit_size -
shift_values[i])));
+assert(result_right[i] == (i >> shift_values[i]) | (i << (bit_size -
shift_values[i])));
+}
+}
+
+void __attribute__((optimize("no-tree-vectorize"))) compare_results64(
+uint64_t *result_left, uint64_t *result_right,
+int bit_size, uint64_t *shift_values)
+{
+for (int i = 0; i
[gcc r15-2969] RISC-V: Bugfix incorrect operand for vwsll auto-vect
https://gcc.gnu.org/g:06ae7bc1345a31a5f23dc86b348a1bef59bb3cc1
commit r15-2969-g06ae7bc1345a31a5f23dc86b348a1bef59bb3cc1
Author: Pan Li
Date: Sat Aug 17 09:25:58 2024 -0600
RISC-V: Bugfix incorrect operand for vwsll auto-vect
This patch would like to fix one ICE when rv64gcv_zvbb for vwsll.
Consider below example.
void vwsll_vv_test (short *restrict dst, char *restrict a,
int *restrict b, int n)
{
for (int i = 0; i < n; i++)
dst[i] = a[i] << b[i];
}
It will hit the vwsll pattern with following operands.
operand 0 -> (reg:RVVMF2HI 146 [ vect__7.13 ])
operand 1 -> (reg:RVVMF4QI 165 [ vect_cst__33 ])
operand 2 -> (reg:RVVM1SI 171 [ vect_cst__36 ])
According to the ISA, operand 2 should be the same as operand 1.
Aka operand 2 should have RVVMF4QI mode as above. Thus, add
quad truncation for operand 2 before emit vwsll.
The below test suites are passed for this patch.
* The rv64gcv fully regression test.
PR target/116280
gcc/ChangeLog:
* config/riscv/autovec-opt.md: Add quad truncation to
align the mode requirement for vwsll.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/pr116280-1.c: New test.
* gcc.target/riscv/rvv/base/pr116280-2.c: New test.
Diff:
---
gcc/config/riscv/autovec-opt.md | 4
gcc/testsuite/gcc.target/riscv/rvv/base/pr116280-1.c | 14 ++
gcc/testsuite/gcc.target/riscv/rvv/base/pr116280-2.c | 10 ++
3 files changed, 28 insertions(+)
diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md
index d7a3cfd4602..4b33a145c17 100644
--- a/gcc/config/riscv/autovec-opt.md
+++ b/gcc/config/riscv/autovec-opt.md
@@ -1546,6 +1546,10 @@
"&& 1"
[(const_int 0)]
{
+rtx truncated = gen_reg_rtx (mode);
+emit_insn (gen_trunc2 (truncated, operands[2]));
+operands[2] = truncated;
+
insn_code icode = code_for_pred_vwsll (mode);
riscv_vector::emit_vlmax_insn (icode, riscv_vector::BINARY_OP, operands);
DONE;
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr116280-1.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/pr116280-1.c
new file mode 100644
index 000..8b8547e2c34
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr116280-1.c
@@ -0,0 +1,14 @@
+/* Test there is no ICE when compile. */
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvbb -mabi=lp64d -O3" } */
+
+short a;
+char b;
+
+void
+test (int e[][1][1], char f[][1][1][1][1]) {
+ for (int g; b;)
+for (;;)
+ for (int h; h < 4073709551572ULL; h += 18446744073709551612U)
+a = f[2][2][1][4073709551612][1] << e[1][1][g];
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr116280-2.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/pr116280-2.c
new file mode 100644
index 000..02f2de66eff
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr116280-2.c
@@ -0,0 +1,10 @@
+/* Test there is no ICE when compile. */
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvbb -mabi=lp64d -O3" } */
+
+void
+test (short *restrict dst, char *restrict a, int *restrict b, int n)
+{
+ for (int i = 0; i < n; i++)
+dst[i] = a[i] << b[i];
+}
[gcc r15-2970] RISC-V: Bugfix for RVV rounding intrinsic ICE in function checker
https://gcc.gnu.org/g:3f51684ac05f065a87c53d9506400cbe97af6b79
commit r15-2970-g3f51684ac05f065a87c53d9506400cbe97af6b79
Author: Jin Ma
Date: Sat Aug 17 09:29:11 2024 -0600
RISC-V: Bugfix for RVV rounding intrinsic ICE in function checker
When compiling an interface for rounding of type 'vfloat16*' without using
zvfh
or zvfhmin, it is not enough to use FLOAT_MODE_P because the type does not
support it. Although the subsequent riscv_validate_vector_type checks will
still fail and throw exceptions, I don't think we should have ICE here.
internal compiler error: in check, at
config/riscv/riscv-vector-builtins-shapes.cc:444
10 | return __riscv_vfadd_vv_f16m1_rm (vs2, vs1, 0, vl);
| ^~
0x4191794 internal_error(char const*, ...)
/iothome/jin.ma/code/master/gcc/gcc/diagnostic-global-context.cc:491
0x416ebf5 fancy_abort(char const*, int, char const*)
/iothome/jin.ma/code/master/gcc/gcc/diagnostic.cc:1772
0x220aae6
riscv_vector::build_frm_base::check(riscv_vector::function_checker&) const
/iothome/jin.ma/code/master/gcc/gcc/config/riscv/riscv-vector-builtins-shapes.cc:444
0x2205323 riscv_vector::function_checker::check()
/iothome/jin.ma/code/master/gcc/gcc/config/riscv/riscv-vector-builtins.cc:4414
gcc/ChangeLog:
* config/riscv/riscv-protos.h (riscv_vector_float_type_p): New.
* config/riscv/riscv-vector-builtins.cc
(function_instance::any_type_float_p):
Use riscv_vector_float_type_p instead of FLOAT_MODE_P for judgment.
* config/riscv/riscv.cc (riscv_vector_int_type_p): Change static to
extern.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/bug-9.c: New test.
Diff:
---
gcc/config/riscv/riscv-protos.h | 1 +
gcc/config/riscv/riscv-vector-builtins.cc | 4 ++--
gcc/config/riscv/riscv.cc | 5 -
gcc/testsuite/gcc.target/riscv/rvv/base/bug-9.c | 13 +
4 files changed, 20 insertions(+), 3 deletions(-)
diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
index 124ae2c073a..f8fc2874cbb 100644
--- a/gcc/config/riscv/riscv-protos.h
+++ b/gcc/config/riscv/riscv-protos.h
@@ -171,6 +171,7 @@ extern enum memmodel riscv_union_memmodels (enum memmodel,
enum memmodel);
extern bool riscv_reg_frame_related (rtx);
extern void riscv_split_sum_of_two_s12 (HOST_WIDE_INT, HOST_WIDE_INT *,
HOST_WIDE_INT *);
+extern bool riscv_vector_float_type_p (const_tree type);
/* Routines implemented in riscv-c.cc. */
void riscv_cpu_cpp_builtins (cpp_reader *);
diff --git a/gcc/config/riscv/riscv-vector-builtins.cc
b/gcc/config/riscv/riscv-vector-builtins.cc
index 9f707efa533..41730c483ee 100644
--- a/gcc/config/riscv/riscv-vector-builtins.cc
+++ b/gcc/config/riscv/riscv-vector-builtins.cc
@@ -3497,11 +3497,11 @@ function_instance::operator== (const function_instance
&other) const
bool
function_instance::any_type_float_p () const
{
- if (FLOAT_MODE_P (TYPE_MODE (get_return_type (
+ if (riscv_vector_float_type_p (get_return_type ()))
return true;
for (int i = 0; op_info->args[i].base_type != NUM_BASE_TYPES; ++i)
-if (FLOAT_MODE_P (TYPE_MODE (get_arg_type (i
+if (riscv_vector_float_type_p (get_arg_type (i)))
return true;
return false;
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 8b7123e043e..901983b4017 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -5898,9 +5898,12 @@ riscv_vector_int_type_p (const_tree type)
return strstr (name, "int") != NULL || strstr (name, "uint") != NULL;
}
-static bool
+bool
riscv_vector_float_type_p (const_tree type)
{
+ if (!riscv_vector_type_p (type))
+return false;
+
machine_mode mode = TYPE_MODE (type);
if (VECTOR_MODE_P (mode))
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/bug-9.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/bug-9.c
new file mode 100644
index 000..20ae9ebf6f2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/bug-9.c
@@ -0,0 +1,13 @@
+/* Test that we do not have ice when compile */
+/* { dg-do assemble } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O2" { target { rv64 } } } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O2" { target { rv32 } } } */
+
+#include
+
+vfloat16m1_t f0 (vfloat16m1_t vs2, vfloat16m1_t vs1, size_t vl)
+{
+ return __riscv_vfadd_vv_f16m1_rm (vs2, vs1, 0, vl);
+}
+
+/* { dg-error "return type 'vfloat16m1_t' requires the zvfhmin or zvfh ISA
extension" "" { target { "riscv*-*-*" } } 0 } */
[gcc r15-2971] [RISC-V][PR target/116282] Stabilize pattern conditions
https://gcc.gnu.org/g:7aed8dedeb9613925930447bf2457c3fd9972d91
commit r15-2971-g7aed8dedeb9613925930447bf2457c3fd9972d91
Author: Jeff Law
Date: Sat Aug 17 09:52:55 2024 -0600
[RISC-V][PR target/116282] Stabilize pattern conditions
So as expected the core problem with target/116282 is that the cost of
certain
constant synthesis cases varied depending on whether or not we're allowed to
generate new pseudos or not.
That in turn meant that in obscure cases an insn might change from
recognizable
to unrecognizable and triggers the observed failure.
So we need to keep the cost stable, at least when called from a pattern's
condition. So we pass another boolean down when necessary. I've tried to
keep
API fallout minimized.
Built and tested on rv32 in my tester. Let's see what pre-commit testing
has
to say though 🙂
Note this will also require a minor change to the in-flight constant
synthesis
work.
PR target/116282
gcc/
* config/riscv/riscv-protos.h (riscv_const_insns): Add new argument.
* config/riscv/riscv.cc (riscv_build_integer): Add new argument
ALLOW_NEW_PSEUDOS. Pass it down to recursive calls and check it
before using synthesis which allows new registers to be created.
(riscv_split_integer_cost): Pass new argument to
riscv_build_integer.
(riscv_integer_cost): Add ALLOW_NEW_PSEUDOS argument, pass it down
to
riscv_build_integer.
(riscv_legitimate_constant_p): Pass new argument to
riscv_const_insns.
(riscv_const_insns): New argment ALLOW_NEW_PSEUDOS. Pass it down to
riscv_integer_cost and riscv_const_insns.
(riscv_split_const_insns): Pass new argument to riscv_const_insns.
(riscv_move_integer, riscv_rtx_costs): Similarly.
* config/riscv/riscv.md (shadd with costly constant): Pass new
argument
to riscv_const_insns.
* config/riscv/bitmanip.md (and with costly constant): Pass new
argument
to riscv_const_insns.
gcc/testsuite/
* gcc.target/riscv/pr116282.c: New test.
Diff:
---
gcc/config/riscv/bitmanip.md | 2 +-
gcc/config/riscv/riscv-protos.h | 2 +-
gcc/config/riscv/riscv.cc | 66 +--
gcc/config/riscv/riscv.md | 16
gcc/testsuite/gcc.target/riscv/pr116282.c | 16
5 files changed, 71 insertions(+), 31 deletions(-)
diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md
index 6872ee56022..06ff698bfe7 100644
--- a/gcc/config/riscv/bitmanip.md
+++ b/gcc/config/riscv/bitmanip.md
@@ -1078,7 +1078,7 @@
&& TARGET_ZBA
&& !paradoxical_subreg_p (operands[1])
/* Only profitable if synthesis takes more than one insn. */
- && riscv_const_insns (operands[2]) != 1
+ && riscv_const_insns (operands[2], false) != 1
/* We need the upper half to be zero. */
&& (INTVAL (operands[2]) & HOST_WIDE_INT_C (0x)) == 0
/* And the the adjusted constant must either be something we can
diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
index f8fc2874cbb..926899ccad6 100644
--- a/gcc/config/riscv/riscv-protos.h
+++ b/gcc/config/riscv/riscv-protos.h
@@ -112,7 +112,7 @@ extern bool riscv_valid_base_register_p (rtx, machine_mode,
bool);
extern enum reg_class riscv_index_reg_class ();
extern int riscv_regno_ok_for_index_p (int);
extern int riscv_address_insns (rtx, machine_mode, bool);
-extern int riscv_const_insns (rtx);
+extern int riscv_const_insns (rtx, bool);
extern int riscv_split_const_insns (rtx);
extern int riscv_load_store_insns (rtx, rtx_insn *);
extern rtx riscv_emit_move (rtx, rtx);
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 901983b4017..c3877008d05 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -1074,11 +1074,16 @@ riscv_build_integer_1 (struct riscv_integer_op
codes[RISCV_MAX_INTEGER_OPS],
}
/* Fill CODES with a sequence of rtl operations to load VALUE.
- Return the number of operations needed. */
+ Return the number of operations needed.
+
+ ALLOW_NEW_PSEUDOS indicates if or caller wants to allow new pseudo
+ registers or not. This is needed for cases where the integer synthesis and
+ costing code are used in insn conditions, we can't have costing allow
+ recognition at some points and reject at others. */
static int
riscv_build_integer (struct riscv_integer_op *codes, HOST_WIDE_INT value,
-machine_mode mode)
+machine_mode mode, bool allow_new_pseudos)
{
int cost = riscv_build_integer_1 (codes, value, mode);
@@ -1129,7 +1134,8 @@ riscv_build_integer (struct riscv_integer_op *codes,
HOST_WIDE_INT value,
int alt_cost;
HOST_WIDE_INT nval = ~value;
- alt_cost = 1 + ri
[gcc r15-2972] RISC-V: Fix ICE for vector single-width integer multiply-add intrinsics
https://gcc.gnu.org/g:6d734ba485547329599f12bea63842a4fba8d72c commit r15-2972-g6d734ba485547329599f12bea63842a4fba8d72c Author: Jin Ma Date: Sat Aug 17 10:18:03 2024 -0600 RISC-V: Fix ICE for vector single-width integer multiply-add intrinsics When rs1 is the immediate 0, the following ICE occurs: error: unrecognizable insn: (insn 8 5 12 2 (set (reg:RVVM1DI 134 [ ]) (if_then_else:RVVM1DI (unspec:RVVMF64BI [ (const_vector:RVVMF64BI repeat [ (const_int 1 [0x1]) ]) (reg/v:DI 137 [ vl ]) (const_int 2 [0x2]) repeated x2 (const_int 0 [0]) (reg:SI 66 vl) (reg:SI 67 vtype) ] UNSPEC_VPREDICATE) (plus:RVVM1DI (mult:RVVM1DI (vec_duplicate:RVVM1DI (const_int 0 [0])) (reg/v:RVVM1DI 136 [ vs2 ])) (reg/v:RVVM1DI 135 [ vd ])) (reg/v:RVVM1DI 135 [ vd ]))) gcc/ChangeLog: * config/riscv/vector.md: Allow scalar operand to be 0. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/bug-7.c: New test. * gcc.target/riscv/rvv/base/bug-8.c: New test. Diff: --- gcc/config/riscv/vector.md | 80 - gcc/testsuite/gcc.target/riscv/rvv/base/bug-7.c | 26 gcc/testsuite/gcc.target/riscv/rvv/base/bug-8.c | 26 3 files changed, 92 insertions(+), 40 deletions(-) diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index aad34b3aa24..211bbc0bff0 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -5331,16 +5331,16 @@ (plus:V_VLSI (mult:V_VLSI (vec_duplicate:V_VLSI - (match_operand: 2 "register_operand" " r, r, r, r")) + (match_operand: 2 "reg_or_0_operand" " rJ, rJ, rJ, rJ")) (match_operand:V_VLSI 3 "register_operand" " 0, vr, 0, vr")) (match_operand:V_VLSI 4 "register_operand"" vr, vr, vr, vr")) (match_dup 3)))] "TARGET_VECTOR" "@ - vmadd.vx\t%0,%2,%4%p1 - vmv%m3r.v\t%0,%3\;vmadd.vx\t%0,%2,%4%p1 - vmadd.vx\t%0,%2,%4%p1 - vmv%m3r.v\t%0,%3\;vmadd.vx\t%0,%2,%4%p1" + vmadd.vx\t%0,%z2,%4%p1 + vmv%m3r.v\t%0,%3\;vmadd.vx\t%0,%z2,%4%p1 + vmadd.vx\t%0,%z2,%4%p1 + vmv%m3r.v\t%0,%3\;vmadd.vx\t%0,%z2,%4%p1" [(set_attr "type" "vimuladd") (set_attr "mode" "") (set_attr "merge_op_idx" "3") @@ -5363,16 +5363,16 @@ (plus:V_VLSI (mult:V_VLSI (vec_duplicate:V_VLSI - (match_operand: 2 "register_operand" " r, r, r, r")) + (match_operand: 2 "reg_or_0_operand" " rJ, rJ, rJ, rJ")) (match_operand:V_VLSI 3 "register_operand" " vr, vr, vr, vr")) (match_operand:V_VLSI 4 "register_operand"" 0, vr, 0, vr")) (match_dup 4)))] "TARGET_VECTOR" "@ - vmacc.vx\t%0,%2,%3%p1 - vmv%m4r.v\t%0,%4\;vmacc.vx\t%0,%2,%3%p1 - vmacc.vx\t%0,%2,%3%p1 - vmv%m4r.v\t%0,%4\;vmacc.vx\t%0,%2,%3%p1" + vmacc.vx\t%0,%z2,%3%p1 + vmv%m4r.v\t%0,%4\;vmacc.vx\t%0,%z2,%3%p1 + vmacc.vx\t%0,%z2,%3%p1 + vmv%m4r.v\t%0,%4\;vmacc.vx\t%0,%z2,%3%p1" [(set_attr "type" "vimuladd") (set_attr "mode" "") (set_attr "merge_op_idx" "4") @@ -5431,16 +5431,16 @@ (mult:V_VLSI_D (vec_duplicate:V_VLSI_D (sign_extend: - (match_operand: 2 "register_operand" " r, r, r, r"))) + (match_operand: 2 "reg_or_0_operand" " rJ, rJ, rJ, rJ"))) (match_operand:V_VLSI_D 3 "register_operand" " 0, vr, 0, vr")) (match_operand:V_VLSI_D 4 "register_operand" " vr, vr, vr, vr")) (match_dup 3)))] "TARGET_VECTOR && !TARGET_64BIT" "@ - vmadd.vx\t%0,%2,%4%p1 - vmv%m2r.v\t%0,%2\;vmadd.vx\t%0,%2,%4%p1 - vmadd.vx\t%0,%2,%4%p1 - vmv%m2r.v\t%0,%2\;vmadd.vx\t%0,%2,%4%p1" + vmadd.vx\t%0,%z2,%4%p1 + vmv%m2r.v\t%0,%z2\;vmadd.vx\t%0,%z2,%4%p1 + vmadd.vx\t%0,%z2,%4%p1 + vmv%m2r.v\t%0,%z2\;vmadd.vx\t%0,%z2,%4%p1" [(set_attr "type" "vimuladd") (set_attr "mode" "") (set_attr "merge_op_idx" "3") @@ -5464,16 +5464,16 @@ (mult:V_VLSI_D (vec_duplicate:V_VLSI_D (sign_extend: - (match_operand: 2 "register_operand" " r, r, r, r"))) + (match_operand: 2 "reg_or_0_operand" " rJ, rJ, rJ, rJ"))) (match_operand:V_VLSI_D 3 "register_operand" " vr, vr, vr, vr")) (match_operand:V_VLSI_D 4 "register_operand" " 0, vr, 0, vr")) (match_dup 4)))] "TARGET_VECTOR && !TARGET_64BIT" "@ - vmacc.vx\t%0,%2,%3%p1 - vmv%m4r.v\t%0,%4\;vmacc.vx\t%0
[gcc r15-2973] Adjust v850 rotate expander to allow more cases for V850E3V5
https://gcc.gnu.org/g:abfc140579682598cd178eb9d0b0160bbfafc633
commit r15-2973-gabfc140579682598cd178eb9d0b0160bbfafc633
Author: Jeff Law
Date: Sat Aug 17 10:30:48 2024 -0600
Adjust v850 rotate expander to allow more cases for V850E3V5
The recent if-conversion changes tripped a failure on the v850 port.
The core underlying issue is that while the if-conversion code tries to do
the
right thing with noce_can_force_operand to determine if it can force an
arbitrary operand into a register, it's not really a sufficient check.
Essentially for arithmetic codes, it checks the operands. If the operands
are
force-able and there's a code_to_optab mapping, then it returns true.
code_to_optab doesn't actually check anything other than the existence of a
mapping in the target. If the target pattern has restrictions enforced by
the
condition or it's an expander that is allowed to FAIL, then
noce_can_force_operand to be true, even though we may not be able to
directly
force the operand into a register.
This came up on the v850 when we had an operand that was a rotate by a
constant
number of bits (I don't remember the count, all that's important about it
was
the count was not 8 or 16).
The v850 port has this define_expand:
> (define_expand "rotlsi3"
> [(parallel [(set (match_operand:SI 0 "register_operand" "")
>(rotate:SI (match_operand:SI 1 "register_operand" "")
> (match_operand:SI 2 "const_int_operand"
"")))
> (clobber (reg:CC CC_REGNUM))])]
> "(TARGET_V850E_UP)"
> {
> if (INTVAL (operands[2]) != 16)
> FAIL;
> })
So the only rotate count allowed is 16 (there's a similar HI rotate with a
count of 8). AFAICT the rotate patterns are allowed to FAIL. So naturally the
expander fails and we get a testsuite regression:
> Tests that now fail, but worked before (4 tests):
>
> v850-sim/-mgcc-abi/-msoft-float/-mv850e3v5: gcc:
gcc.c-torture/execute/20100805-1.c -O3 -fomit-frame-pointer -funroll-loops
-fpeel-loops -ftracer -finline-functions (test for excess errors)
> v850-sim/-mgcc-abi/-msoft-float/-mv850e3v5: gcc:
gcc.c-torture/execute/20100805-1.c -O3 -fomit-frame-pointer -funroll-loops
-fpeel-loops -ftracer -finline-functions (test for excess errors)
> v850-sim/-msoft-float/-mv850e3v5: gcc: gcc.c-torture/execute/20100805-1.c
-O3 -fomit-frame-pointer -funroll-loops -fpeel-loops -ftracer
-finline-functions (test for excess errors)
> v850-sim/-mv850e3v5: gcc: gcc.c-torture/execute/20100805-1.c -O3
-fomit-frame-pointer -funroll-loops -fpeel-loops -ftracer -finline-functions
(test for excess errors)
This patch works around the problem by allowing the rotates in additional
cases, particularly for the V850E3V5+ variants which have a general rotate
capability. But let's be clear, this is just a workaround and I expect
we're
going to have to revisit the code to test if an operand can be forced into a
register.
gcc/
* config/v850/v850.md (rotlsi3): Allow more cases for V850E3V5+.
Diff:
---
gcc/config/v850/v850.md | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/gcc/config/v850/v850.md b/gcc/config/v850/v850.md
index f810a27fa2e..83cc9972673 100644
--- a/gcc/config/v850/v850.md
+++ b/gcc/config/v850/v850.md
@@ -1352,7 +1352,9 @@
(clobber (reg:CC CC_REGNUM))])]
"(TARGET_V850E_UP)"
{
-if (INTVAL (operands[2]) != 16)
+if (TARGET_V850E3V5_UP && e3v5_shift_operand (operands[2], SImode))
+ ;
+else if (INTVAL (operands[2]) != 16)
FAIL;
})
[gcc r15-2974] t-rtems: add rv32imf architecture to the RTEMS multilib for RISC-V
https://gcc.gnu.org/g:efcfd1d2ad8779b5c1b41b7f702516ca1da46925 commit r15-2974-gefcfd1d2ad8779b5c1b41b7f702516ca1da46925 Author: Kevin Kirspel Date: Sat Aug 17 14:37:18 2024 -0600 t-rtems: add rv32imf architecture to the RTEMS multilib for RISC-V The attach patch is specific to the RTEMS RISC-V architecture multilib which is controlled by the t-rtems file in the gcc/config/riscv/ directory. The patch file was created from the gcc-13.3.0 branch. It was successfully tested within RTEMS Source Builder. gcc/ * config/riscv/t-rtems: Add ilp32f multilib. Diff: --- gcc/config/riscv/t-rtems | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/gcc/config/riscv/t-rtems b/gcc/config/riscv/t-rtems index 19b12030895..f596e764f9d 100644 --- a/gcc/config/riscv/t-rtems +++ b/gcc/config/riscv/t-rtems @@ -1,8 +1,8 @@ MULTILIB_OPTIONS = MULTILIB_DIRNAMES = -MULTILIB_OPTIONS += march=rv32i/march=rv32iac/march=rv32im/march=rv32ima/march=rv32imac/march=rv32imaf/march=rv32imafc/march=rv32imafd/march=rv32imafdc/march=rv64ima/march=rv64imac/march=rv64imafd/march=rv64imafdc -MULTILIB_DIRNAMES += rv32i rv32iac rv32im rv32ima rv32imac rv32imaf rv32imafc rv32imafd rv32imafdc rv64ima rv64imac rv64imafd rv64imafdc +MULTILIB_OPTIONS += march=rv32i/march=rv32iac/march=rv32im/march=rv32imf/march=rv32ima/march=rv32imac/march=rv32imaf/march=rv32imafc/march=rv32imafd/march=rv32imafdc/march=rv64ima/march=rv64imac/march=rv64imafd/march=rv64imafdc +MULTILIB_DIRNAMES += rv32i rv32iac rv32im rv32imf rv32ima rv32imac rv32imaf rv32imafc rv32imafd rv32imafdc rv64ima rv64imac rv64imafd rv64imafdc MULTILIB_OPTIONS += mabi=ilp32/mabi=ilp32f/mabi=ilp32d/mabi=lp64/mabi=lp64d MULTILIB_DIRNAMES += ilp32 ilp32f ilp32d lp64 lp64d @@ -14,6 +14,7 @@ MULTILIB_REQUIRED = MULTILIB_REQUIRED += march=rv32i/mabi=ilp32 MULTILIB_REQUIRED += march=rv32iac/mabi=ilp32 MULTILIB_REQUIRED += march=rv32im/mabi=ilp32 +MULTILIB_REQUIRED += march=rv32imf/mabi=ilp32f MULTILIB_REQUIRED += march=rv32ima/mabi=ilp32 MULTILIB_REQUIRED += march=rv32imac/mabi=ilp32 MULTILIB_REQUIRED += march=rv32imaf/mabi=ilp32f
[gcc r15-2975] [committed] Avoid right shifting signed value on ext-dce.cc
https://gcc.gnu.org/g:61e179b1b363454926504fac13b554ad7f1b0f72 commit r15-2975-g61e179b1b363454926504fac13b554ad7f1b0f72 Author: Jeff Law Date: Sat Aug 17 15:10:38 2024 -0600 [committed] Avoid right shifting signed value on ext-dce.cc This is analogous to a prior patch to ext-dce which fixes propagation of sign bits, but this time for the saturating variants. I'd held off fixing those because I wanted the time to look at that code (since we don't have a testcase for it as far as I know). Not surprisingly, putting an abort on that path and running an x86 bootstrap and testsuite run, it never triggers. Of course not a lot of code tries to do saturating shifts. Anyway, bootstrapped and regression tested on x86_64. Pushing to the trunk. Thanks for everyone's patience. gcc/ * ext-dce.cc (carry_backpropagate): Cast mask to HOST_WIDE_INT before shifting. Diff: --- gcc/ext-dce.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gcc/ext-dce.cc b/gcc/ext-dce.cc index 97a66427118..017e2de000d 100644 --- a/gcc/ext-dce.cc +++ b/gcc/ext-dce.cc @@ -556,7 +556,7 @@ carry_backpropagate (unsigned HOST_WIDE_INT mask, enum rtx_code code, rtx x) >> (INTVAL (XEXP (x, 1)) + (XEXP (x, 1) != const0_rtx && code == SS_ASHIFT - | (mask >> INTVAL (XEXP (x, 1; + | ((HOST_WIDE_INT)mask >> INTVAL (XEXP (x, 1; } return mmask;
[gcc r15-2977] RISC-V: Add testcases for unsigned scalar .SAT_TRUNC form 2
https://gcc.gnu.org/g:6fbdbad97d451cc220a5654c8b97b9911485ef4a
commit r15-2977-g6fbdbad97d451cc220a5654c8b97b9911485ef4a
Author: Pan Li
Date: Sat Aug 17 18:04:00 2024 +0800
RISC-V: Add testcases for unsigned scalar .SAT_TRUNC form 2
This patch would like to add test cases for the unsigned scalar
.SAT_TRUNC form 2. Aka:
Form 2:
#define DEF_SAT_U_TRUC_FMT_2(NT, WT) \
NT __attribute__((noinline)) \
sat_u_truc_##WT##_to_##NT##_fmt_2 (WT x) \
{\
WT max = (WT)(NT)-1; \
return x > max ? (NT) max : (NT)x; \
}
DEF_SAT_U_TRUC_FMT_2 (uint32_t, uint64_t)
The below test is passed for this patch.
* The rv64gcv regression test.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/sat_arith.h: Add test helper macros.
* gcc.target/riscv/sat_u_trunc-7.c: New test.
* gcc.target/riscv/sat_u_trunc-8.c: New test.
* gcc.target/riscv/sat_u_trunc-9.c: New test.
* gcc.target/riscv/sat_u_trunc-run-7.c: New test.
* gcc.target/riscv/sat_u_trunc-run-8.c: New test.
* gcc.target/riscv/sat_u_trunc-run-9.c: New test.
Signed-off-by: Pan Li
Diff:
---
gcc/testsuite/gcc.target/riscv/sat_arith.h | 12
gcc/testsuite/gcc.target/riscv/sat_u_trunc-7.c | 17 +
gcc/testsuite/gcc.target/riscv/sat_u_trunc-8.c | 20
gcc/testsuite/gcc.target/riscv/sat_u_trunc-9.c | 19 +++
gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-7.c | 16
gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-8.c | 16
gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-9.c | 16
7 files changed, 116 insertions(+)
diff --git a/gcc/testsuite/gcc.target/riscv/sat_arith.h
b/gcc/testsuite/gcc.target/riscv/sat_arith.h
index 37e0a60f21b..576a4926d1f 100644
--- a/gcc/testsuite/gcc.target/riscv/sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/sat_arith.h
@@ -227,7 +227,19 @@ sat_u_truc_##WT##_to_##NT##_fmt_1 (WT x) \
}
#define DEF_SAT_U_TRUC_FMT_1_WRAP(NT, WT) DEF_SAT_U_TRUC_FMT_1(NT, WT)
+#define DEF_SAT_U_TRUC_FMT_2(NT, WT) \
+NT __attribute__((noinline)) \
+sat_u_truc_##WT##_to_##NT##_fmt_2 (WT x) \
+{\
+ WT max = (WT)(NT)-1; \
+ return x > max ? (NT) max : (NT)x; \
+}
+#define DEF_SAT_U_TRUC_FMT_2_WRAP(NT, WT) DEF_SAT_U_TRUC_FMT_2(NT, WT)
+
#define RUN_SAT_U_TRUC_FMT_1(NT, WT, x) sat_u_truc_##WT##_to_##NT##_fmt_1 (x)
#define RUN_SAT_U_TRUC_FMT_1_WRAP(NT, WT, x) RUN_SAT_U_TRUC_FMT_1(NT, WT, x)
+#define RUN_SAT_U_TRUC_FMT_2(NT, WT, x) sat_u_truc_##WT##_to_##NT##_fmt_2 (x)
+#define RUN_SAT_U_TRUC_FMT_2_WRAP(NT, WT, x) RUN_SAT_U_TRUC_FMT_2(NT, WT, x)
+
#endif
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_trunc-7.c
b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-7.c
new file mode 100644
index 000..95d513a15fb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-7.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details
-fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_truc_uint16_t_to_uint8_t_fmt_2:
+** sltiu\s+[atx][0-9]+,\s*a0,\s*255
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*0xff
+** ret
+*/
+DEF_SAT_U_TRUC_FMT_2(uint8_t, uint16_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_trunc-8.c
b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-8.c
new file mode 100644
index 000..f168912293d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-8.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details
-fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_truc_uint32_t_to_uint16_t_fmt_2:
+** li\s+[atx][0-9]+,\s*65536
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** sltu\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** slli\s+a0,\s*a0,\s*48
+** srli\s+a0,\s*a0,\s*48
+** ret
+*/
+DEF_SAT_U_TRUC_FMT_2(uint16_t, uint32_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_trunc-9.c
b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-9.c
new file mode 100644
index 000..d82363d6aef
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-9.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details
-fno
[gcc r15-2978] RISC-V: Add testcases for unsigned scalar .SAT_TRUNC form 3
https://gcc.gnu.org/g:8d0efcf5581abf2560701f4143a0c2ccb261d1f7
commit r15-2978-g8d0efcf5581abf2560701f4143a0c2ccb261d1f7
Author: Pan Li
Date: Sat Aug 17 19:27:11 2024 +0800
RISC-V: Add testcases for unsigned scalar .SAT_TRUNC form 3
This patch would like to add test cases for the unsigned scalar
.SAT_TRUNC form 3. Aka:
Form 3:
#define DEF_SAT_U_TRUC_FMT_3(NT, WT) \
NT __attribute__((noinline)) \
sat_u_truc_##WT##_to_##NT##_fmt_3 (WT x) \
{\
WT max = (WT)(NT)-1; \
return x <= max ? (NT)x : (NT) max;\
}
DEF_SAT_U_TRUC_FMT_3 (uint32_t, uint64_t)
The below test is passed for this patch.
* The rv64gcv regression test.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/sat_arith.h: Add test helper macros.
* gcc.target/riscv/sat_u_trunc-13.c: New test.
* gcc.target/riscv/sat_u_trunc-14.c: New test.
* gcc.target/riscv/sat_u_trunc-15.c: New test.
* gcc.target/riscv/sat_u_trunc-run-13.c: New test.
* gcc.target/riscv/sat_u_trunc-run-14.c: New test.
* gcc.target/riscv/sat_u_trunc-run-15.c: New test.
Signed-off-by: Pan Li
Diff:
---
gcc/testsuite/gcc.target/riscv/sat_arith.h | 12
gcc/testsuite/gcc.target/riscv/sat_u_trunc-13.c | 17 +
gcc/testsuite/gcc.target/riscv/sat_u_trunc-14.c | 20
gcc/testsuite/gcc.target/riscv/sat_u_trunc-15.c | 19 +++
gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-13.c | 16
gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-14.c | 16
gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-15.c | 16
7 files changed, 116 insertions(+)
diff --git a/gcc/testsuite/gcc.target/riscv/sat_arith.h
b/gcc/testsuite/gcc.target/riscv/sat_arith.h
index 576a4926d1f..cf055410fd1 100644
--- a/gcc/testsuite/gcc.target/riscv/sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/sat_arith.h
@@ -236,10 +236,22 @@ sat_u_truc_##WT##_to_##NT##_fmt_2 (WT x) \
}
#define DEF_SAT_U_TRUC_FMT_2_WRAP(NT, WT) DEF_SAT_U_TRUC_FMT_2(NT, WT)
+#define DEF_SAT_U_TRUC_FMT_3(NT, WT) \
+NT __attribute__((noinline)) \
+sat_u_truc_##WT##_to_##NT##_fmt_3 (WT x) \
+{\
+ WT max = (WT)(NT)-1; \
+ return x <= max ? (NT)x : (NT) max;\
+}
+#define DEF_SAT_U_TRUC_FMT_3_WRAP(NT, WT) DEF_SAT_U_TRUC_FMT_3(NT, WT)
+
#define RUN_SAT_U_TRUC_FMT_1(NT, WT, x) sat_u_truc_##WT##_to_##NT##_fmt_1 (x)
#define RUN_SAT_U_TRUC_FMT_1_WRAP(NT, WT, x) RUN_SAT_U_TRUC_FMT_1(NT, WT, x)
#define RUN_SAT_U_TRUC_FMT_2(NT, WT, x) sat_u_truc_##WT##_to_##NT##_fmt_2 (x)
#define RUN_SAT_U_TRUC_FMT_2_WRAP(NT, WT, x) RUN_SAT_U_TRUC_FMT_2(NT, WT, x)
+#define RUN_SAT_U_TRUC_FMT_3(NT, WT, x) sat_u_truc_##WT##_to_##NT##_fmt_3 (x)
+#define RUN_SAT_U_TRUC_FMT_3_WRAP(NT, WT, x) RUN_SAT_U_TRUC_FMT_3(NT, WT, x)
+
#endif
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_trunc-13.c
b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-13.c
new file mode 100644
index 000..58910793a80
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-13.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details
-fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_truc_uint16_t_to_uint8_t_fmt_3:
+** sltiu\s+[atx][0-9]+,\s*a0,\s*255
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*0xff
+** ret
+*/
+DEF_SAT_U_TRUC_FMT_3(uint8_t, uint16_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_trunc-14.c
b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-14.c
new file mode 100644
index 000..236ea1d45f7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-14.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details
-fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_truc_uint32_t_to_uint16_t_fmt_3:
+** li\s+[atx][0-9]+,\s*65536
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** sltu\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** slli\s+a0,\s*a0,\s*48
+** srli\s+a0,\s*a0,\s*48
+** ret
+*/
+DEF_SAT_U_TRUC_FMT_3(uint16_t, uint32_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_trunc-15.c
b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-15.c
new file mode 100644
index 000..33c3686c053
--- /de
[gcc r15-2979] RISC-V: Make sure high bits of usadd operands is clean for non-Xmode [PR116278]
https://gcc.gnu.org/g:e8f31f4f58f0fcf1716fc1d9ee003fbcdda600c3
commit r15-2979-ge8f31f4f58f0fcf1716fc1d9ee003fbcdda600c3
Author: Pan Li
Date: Fri Aug 9 10:26:32 2024 +0800
RISC-V: Make sure high bits of usadd operands is clean for non-Xmode
[PR116278]
For QI/HImode of .SAT_ADD, the operands may be sign-extended and the
high bits of Xmode may be all 1 which is not expected. For example as
below code.
signed char b[1];
unsigned short c;
signed char *d = b;
int main() {
b[0] = -40;
c = ({ (unsigned short)d[0] < 0xFFF6 ? (unsigned short)d[0] : 0xFFF6; })
+ 9;
__builtin_printf("%d\n", c);
}
After expanding we have:
;; _6 = .SAT_ADD (_3, 9);
(insn 8 7 9 (set (reg:DI 143)
(high:DI (symbol_ref:DI ("d") [flags 0x86] )))
(nil))
(insn 9 8 10 (set (reg/f:DI 142)
(mem/f/c:DI (lo_sum:DI (reg:DI 143)
(symbol_ref:DI ("d") [flags 0x86] )) [1 d+0 S8
A64]))
(nil))
(insn 10 9 11 (set (reg:HI 144 [ _3 ])
(sign_extend:HI (mem:QI (reg/f:DI 142) [0 *d.0_1+0 S1 A8])))
"test.c":7:10 -1
(nil))
The convert from signed char to unsigned short will have sign_extend rtl
as above. And finally become the lb insn as below:
lb a1,0(a5) // a1 is -40, aka 0xffd8
lui a0,0x1a
addia5,a1,9
sllia5,a5,0x30
srlia5,a5,0x30 // a5 is 65505
sltua1,a5,a1 // compare 65505 and 0xffd8 => TRUE
The sltu try to compare 65505 and 0xffd8 here, but we
actually want to compare 65505 and 65496 (0xffd8). Thus we need to
clean up the high bits to ensure this.
The below test suites are passed for this patch:
* The rv64gcv fully regression test.
PR target/116278
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_gen_zero_extend_rtx): Add new
func impl to zero extend rtx.
(riscv_expand_usadd): Leverage above func to cleanup operands 0
and remove the special handing for SImode in RV64.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/sat_u_add-11.c: Adjust asm check body.
* gcc.target/riscv/sat_u_add-15.c: Ditto.
* gcc.target/riscv/sat_u_add-19.c: Ditto.
* gcc.target/riscv/sat_u_add-23.c: Ditto.
* gcc.target/riscv/sat_u_add-3.c: Ditto.
* gcc.target/riscv/sat_u_add-7.c: Ditto.
* gcc.target/riscv/sat_u_add_imm-11.c: Ditto.
* gcc.target/riscv/sat_u_add_imm-15.c: Ditto.
* gcc.target/riscv/sat_u_add_imm-3.c: Ditto.
* gcc.target/riscv/sat_u_add_imm-7.c: Ditto.
* gcc.target/riscv/pr116278-run-1.c: New test.
* gcc.target/riscv/pr116278-run-2.c: New test.
Signed-off-by: Pan Li
Diff:
---
gcc/config/riscv/riscv.cc | 34 +++
gcc/testsuite/gcc.target/riscv/pr116278-run-1.c | 20 +
gcc/testsuite/gcc.target/riscv/pr116278-run-2.c | 20 +
gcc/testsuite/gcc.target/riscv/sat_u_add-11.c | 6 +++-
gcc/testsuite/gcc.target/riscv/sat_u_add-15.c | 6 +++-
gcc/testsuite/gcc.target/riscv/sat_u_add-19.c | 6 +++-
gcc/testsuite/gcc.target/riscv/sat_u_add-23.c | 6 +++-
gcc/testsuite/gcc.target/riscv/sat_u_add-3.c | 6 +++-
gcc/testsuite/gcc.target/riscv/sat_u_add-7.c | 6 +++-
gcc/testsuite/gcc.target/riscv/sat_u_add_imm-11.c | 6 +++-
gcc/testsuite/gcc.target/riscv/sat_u_add_imm-15.c | 6 +++-
gcc/testsuite/gcc.target/riscv/sat_u_add_imm-3.c | 6 +++-
gcc/testsuite/gcc.target/riscv/sat_u_add_imm-7.c | 6 +++-
13 files changed, 112 insertions(+), 22 deletions(-)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index c3877008d05..f266c45ed4d 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -11828,12 +11828,29 @@ riscv_get_raw_result_mode (int regno)
return default_get_reg_raw_mode (regno);
}
+/* Generate a new rtx of Xmode based on the rtx and mode in define pattern.
+ The rtx x will be zero extended to Xmode if the mode is HI/QImode, and
+ the new zero extended Xmode rtx will be returned.
+ Or the gen_lowpart rtx of Xmode will be returned. */
+
+static rtx
+riscv_gen_zero_extend_rtx (rtx x, machine_mode mode)
+{
+ if (mode == Xmode)
+return x;
+
+ rtx xmode_reg = gen_reg_rtx (Xmode);
+ riscv_emit_unary (ZERO_EXTEND, xmode_reg, x);
+
+ return xmode_reg;
+}
+
/* Implements the unsigned saturation add standard name usadd for int mode.
z = SAT_ADD(x, y).
=>
1. sum = x + y.
- 2. sum = truncate (sum) for QI and HI only.
+ 2. sum = truncate (sum) for non-Xmode.
3. lt = sum < x.
4. lt = -lt.
5. z = sum | lt. */
@@ -11844,22 +11861,15 @@ riscv_expand_usadd (rtx dest, rtx x, rtx y)
machine_mode mode = GET_MODE (dest);
rtx xmode_sum = gen_re
[gcc r15-2980] RISC-V: Implement the quad and oct .SAT_TRUNC for scalar
https://gcc.gnu.org/g:a183b255be8ec8f434c3c39f3f4e01d6bd5566f8
commit r15-2980-ga183b255be8ec8f434c3c39f3f4e01d6bd5566f8
Author: Pan Li
Date: Tue Jul 23 11:18:48 2024 +0800
RISC-V: Implement the quad and oct .SAT_TRUNC for scalar
This patch would like to implement the quad and oct .SAT_TRUNC pattern
in the riscv backend. Aka:
Form 1:
#define DEF_SAT_U_TRUC_FMT_1(NT, WT) \
NT __attribute__((noinline)) \
sat_u_truc_##WT##_to_##NT##_fmt_1 (WT x) \
{\
bool overflow = x > (WT)(NT)(-1); \
return ((NT)x) | (NT)-overflow;\
}
DEF_SAT_U_TRUC_FMT_1(uint16_t, uint64_t)
Before this patch:
4 │ __attribute__((noinline))
5 │ uint16_t sat_u_truc_uint64_t_to_uint16_t_fmt_1 (uint64_t x)
6 │ {
7 │ _Bool overflow;
8 │ short unsigned int _1;
9 │ short unsigned int _2;
10 │ short unsigned int _3;
11 │ uint16_t _6;
12 │
13 │ ;; basic block 2, loop depth 0
14 │ ;;pred: ENTRY
15 │ overflow_5 = x_4(D) > 65535;
16 │ _1 = (short unsigned int) x_4(D);
17 │ _2 = (short unsigned int) overflow_5;
18 │ _3 = -_2;
19 │ _6 = _1 | _3;
20 │ return _6;
21 │ ;;succ: EXIT
22 │
23 │ }
After this patch:
3 │
4 │ __attribute__((noinline))
5 │ uint16_t sat_u_truc_uint64_t_to_uint16_t_fmt_1 (uint64_t x)
6 │ {
7 │ uint16_t _6;
8 │
9 │ ;; basic block 2, loop depth 0
10 │ ;;pred: ENTRY
11 │ _6 = .SAT_TRUNC (x_4(D)); [tail call]
12 │ return _6;
13 │ ;;succ: EXIT
14 │
15 │ }
The below tests suites are passed for this patch
1. The rv64gcv fully regression test.
2. The rv64gcv build with glibc
gcc/ChangeLog:
* config/riscv/iterators.md (ANYI_QUAD_TRUNC): New iterator for
quad truncation.
(ANYI_OCT_TRUNC): New iterator for oct truncation.
(ANYI_QUAD_TRUNCATED): New attr for truncated quad modes.
(ANYI_OCT_TRUNCATED): New attr for truncated oct modes.
(anyi_quad_truncated): Ditto but for lower case.
(anyi_oct_truncated): Ditto but for lower case.
* config/riscv/riscv.md (ustrunc2):
Add new pattern for quad truncation.
(ustrunc2): Ditto but for oct.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-2.c: Adjust
the expand dump check times.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-3.c: Ditto.
* gcc.target/riscv/sat_arith_data.h: Add test helper macros.
* gcc.target/riscv/sat_u_trunc-4.c: New test.
* gcc.target/riscv/sat_u_trunc-5.c: New test.
* gcc.target/riscv/sat_u_trunc-6.c: New test.
* gcc.target/riscv/sat_u_trunc-run-4.c: New test.
* gcc.target/riscv/sat_u_trunc-run-5.c: New test.
* gcc.target/riscv/sat_u_trunc-run-6.c: New test.
Signed-off-by: Pan Li
Diff:
---
gcc/config/riscv/iterators.md | 20 +
gcc/config/riscv/riscv.md | 20 +
.../riscv/rvv/autovec/unop/vec_sat_u_trunc-2.c | 2 +-
.../riscv/rvv/autovec/unop/vec_sat_u_trunc-3.c | 2 +-
gcc/testsuite/gcc.target/riscv/sat_arith_data.h| 51 ++
gcc/testsuite/gcc.target/riscv/sat_u_trunc-4.c | 17
gcc/testsuite/gcc.target/riscv/sat_u_trunc-5.c | 17
gcc/testsuite/gcc.target/riscv/sat_u_trunc-6.c | 20 +
gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-4.c | 16 +++
gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-5.c | 16 +++
gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-6.c | 16 +++
11 files changed, 195 insertions(+), 2 deletions(-)
diff --git a/gcc/config/riscv/iterators.md b/gcc/config/riscv/iterators.md
index 0a669f560e3..2844cb02ff0 100644
--- a/gcc/config/riscv/iterators.md
+++ b/gcc/config/riscv/iterators.md
@@ -67,14 +67,34 @@
(define_mode_iterator ANYI_DOUBLE_TRUNC [HI SI (DI "TARGET_64BIT")])
+(define_mode_iterator ANYI_QUAD_TRUNC [SI (DI "TARGET_64BIT")])
+
+(define_mode_iterator ANYI_OCT_TRUNC [(DI "TARGET_64BIT")])
+
(define_mode_attr ANYI_DOUBLE_TRUNCATED [
(HI "QI") (SI "HI") (DI "SI")
])
+(define_mode_attr ANYI_QUAD_TRUNCATED [
+ (SI "QI") (DI "HI")
+])
+
+(define_mode_attr ANYI_OCT_TRUNCATED [
+ (DI "QI")
+])
+
(define_mode_attr anyi_double_truncated [
(HI "qi") (SI "hi") (DI "si")
])
+(define_mode_attr anyi_quad_truncated [
+ (SI "qi") (DI "hi")
+])
+
+(define_mode_attr anyi_oct_truncated [
+ (DI "qi")
+])
+
;; Iterator for hardware-supported floating-point modes.
(define_mode_iterato
