[gcc r15-2375] testsuite: Fix up consteval-prop21.C for 32-bit targets [PR115986]

[Jakub Jelinek via Gcc-cvs]

https://gcc.gnu.org/g:331f23540eec39fc1e665f573c4aac258bba6043

commit r15-2375-g331f23540eec39fc1e665f573c4aac258bba6043
Author: Jakub Jelinek 
Date:   Mon Jul 29 09:33:09 2024 +0200

testsuite: Fix up consteval-prop21.C for 32-bit targets [PR115986]

The test fails on 32-bit targets (which don't support __int128 type).
Using unsigned long long instead still ICEs before the fix and passes
after it on those targets.

2024-07-29  Jakub Jelinek  

PR c++/115986
* g++.dg/cpp2a/consteval-prop21.C (operator "" _c): Use
unsigned long long rather than __uint128_t for return type if int128
is unsupported.

Diff:
---
 gcc/testsuite/g++.dg/cpp2a/consteval-prop21.C | 8 +++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/gcc/testsuite/g++.dg/cpp2a/consteval-prop21.C 
b/gcc/testsuite/g++.dg/cpp2a/consteval-prop21.C
index debbda4f4259..36da1bd91f3a 100644
--- a/gcc/testsuite/g++.dg/cpp2a/consteval-prop21.C
+++ b/gcc/testsuite/g++.dg/cpp2a/consteval-prop21.C
@@ -5,7 +5,13 @@ template 
 constexpr int b(T) {
   return 0;
 }
-consteval __uint128_t operator"" _c(const char*) { return 0; }
+consteval
+#ifdef __SIZEOF_INT128__
+__uint128_t
+#else
+unsigned long long
+#endif
+operator"" _c(const char*) { return 0; }
 constexpr char e() {
   long f = true ? 0 : b(long(1));
   return b(f);

[gcc r14-10514] i386: Fix AVX512 intrin macro typo

[Haochen Jiang via Gcc-cvs]

https://gcc.gnu.org/g:affb2e8f87e3982ee82b72dc3c44486daefd22e3

commit r14-10514-gaffb2e8f87e3982ee82b72dc3c44486daefd22e3
Author: Haochen Jiang 
Date:   Thu Jul 25 16:12:20 2024 +0800

i386: Fix AVX512 intrin macro typo

There are several typo in AVX512 intrins macro define. Correct them to solve
errors when compiled with -O0.

gcc/ChangeLog:

* config/i386/avx512dqintrin.h
(_mm_mask_fpclass_ss_mask): Correct operand order.
(_mm_mask_fpclass_sd_mask): Ditto.
(_mm256_maskz_reduce_round_ss): Use 
__builtin_ia32_reducess_mask_round
instead of __builtin_ia32_reducesd_mask_round.
(_mm_reduce_round_sd): Use -1 as mask since it is non-mask.
(_mm_reduce_round_ss): Ditto.
* config/i386/avx512vlbwintrin.h
(_mm256_mask_alignr_epi8): Correct operand usage.
(_mm_mask_alignr_epi8): Ditto.
* config/i386/avx512vlintrin.h (_mm_mask_alignr_epi64): Ditto.

gcc/testsuite/ChangeLog:

* gcc.target/i386/avx512bw-vpalignr-1b.c: New test.
* gcc.target/i386/avx512dq-vfpclasssd-1b.c: Ditto.
* gcc.target/i386/avx512dq-vfpcla-1b.c: Ditto.
* gcc.target/i386/avx512dq-vreducesd-1b.c: Ditto.
* gcc.target/i386/avx512dq-vreducess-1b.c: Ditto.
* gcc.target/i386/avx512vl-valignq-1b.c: Ditto.

Diff:
---
 gcc/config/i386/avx512dqintrin.h   | 16 +---
 gcc/config/i386/avx512vlbwintrin.h |  4 ++--
 gcc/config/i386/avx512vlintrin.h   |  2 +-
 gcc/testsuite/gcc.target/i386/avx512bw-vpalignr-1b.c   | 18 ++
 gcc/testsuite/gcc.target/i386/avx512dq-vfpclasssd-1b.c | 14 ++
 gcc/testsuite/gcc.target/i386/avx512dq-vfpcla-1b.c | 14 ++
 gcc/testsuite/gcc.target/i386/avx512dq-vreducesd-1b.c  | 16 
 gcc/testsuite/gcc.target/i386/avx512dq-vreducess-1b.c  | 16 
 gcc/testsuite/gcc.target/i386/avx512vl-valignq-1b.c| 15 +++
 9 files changed, 105 insertions(+), 10 deletions(-)

diff --git a/gcc/config/i386/avx512dqintrin.h b/gcc/config/i386/avx512dqintrin.h
index 3beed7e649a9..d9890c6da1dc 100644
--- a/gcc/config/i386/avx512dqintrin.h
+++ b/gcc/config/i386/avx512dqintrin.h
@@ -572,11 +572,11 @@ _mm_mask_fpclass_sd_mask (__mmask8 __U, __m128d __A, 
const int __imm)
   ((__mmask8) __builtin_ia32_fpclasssd_mask ((__v2df) (__m128d) (X),   \
 (int) (C), (__mmask8) (-1))) \
 
-#define _mm_mask_fpclass_ss_mask(X, C, U)  \
+#define _mm_mask_fpclass_ss_mask(U, X, C)  \
   ((__mmask8) __builtin_ia32_fpcla_mask ((__v4sf) (__m128) (X),\
 (int) (C), (__mmask8) (U)))
 
-#define _mm_mask_fpclass_sd_mask(X, C, U)  \
+#define _mm_mask_fpclass_sd_mask(U, X, C)  \
   ((__mmask8) __builtin_ia32_fpclasssd_mask ((__v2df) (__m128d) (X),   \
 (int) (C), (__mmask8) (U)))
 #define _mm_reduce_sd(A, B, C) \
@@ -594,8 +594,9 @@ _mm_mask_fpclass_sd_mask (__mmask8 __U, __m128d __A, const 
int __imm)
 (__mmask8)(U)))
 
 #define _mm_reduce_round_sd(A, B, C, R)   \
-  ((__m128d) __builtin_ia32_reducesd_round ((__v2df)(__m128d)(A),  \
-(__v2df)(__m128d)(B), (int)(C), (__mmask8)(U), (int)(R)))
+  ((__m128d) __builtin_ia32_reducesd_mask_round ((__v2df)(__m128d)(A), \
+(__v2df)(__m128d)(B), (int)(C), (__v2df) _mm_avx512_setzero_pd (), \
+(__mmask8)(-1), (int)(R)))
 
 #define _mm_mask_reduce_round_sd(W, U, A, B, C, R)\
   ((__m128d) __builtin_ia32_reducesd_mask_round ((__v2df)(__m128d)(A), \
@@ -622,8 +623,9 @@ _mm_mask_fpclass_sd_mask (__mmask8 __U, __m128d __A, const 
int __imm)
 (__mmask8)(U)))
 
 #define _mm_reduce_round_ss(A, B, C, R)   \
-  ((__m128) __builtin_ia32_reducess_round ((__v4sf)(__m128)(A),   \
-(__v4sf)(__m128)(B), (int)(C), (__mmask8)(U), (int)(R)))
+  ((__m128) __builtin_ia32_reducess_mask_round ((__v4sf)(__m128)(A),   \
+(__v4sf)(__m128)(B), (int)(C), (__v4sf) _mm_avx512_setzero_ps (),  \
+(__mmask8)(-1), (int)(R)))
 
 #define _mm_mask_reduce_round_ss(W, U, A, B, C, R)\
   ((__m128) __builtin_ia32_reducess_mask_round ((__v4sf)(__m128)(A),   \
@@ -631,7 +633,7 @@ _mm_mask_fpclass_sd_mask (__mmask8 __U, __m128d __A, const 
int __imm)
 (__mmask8)(U), (int)(R)))
 
 #define _mm_maskz_reduce_round_ss(U, A, B, C, R)  \
-  ((__m128) __builtin_ia32_reducesd_mask_round ((__v4sf)(__m128)(A),   \
+  ((__m128) __builtin_ia32_reducess_mask_round ((__v4sf)(__m128)(A),   \
 (__v4sf)(__m128)(B), (int)(C), (__v4sf) _mm_avx512

[gcc r14-10515] Fix ICE with -fdump-tree-moref

[Jan Hubicka via Gcc-cvs]

https://gcc.gnu.org/g:98baaa17561ca299eefc98f469f4326e551604c9

commit r14-10515-g98baaa17561ca299eefc98f469f4326e551604c9
Author: Jan Hubicka 
Date:   Mon Jul 29 10:48:34 2024 +0200

Fix ICE with -fdump-tree-moref

gcc/ChangeLog:

PR ipa/116055
* ipa-modref.cc (analyze_function): Do not ICE when flags regress.

Diff:
---
 gcc/ipa-modref.cc | 7 ---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/gcc/ipa-modref.cc b/gcc/ipa-modref.cc
index 53a2e35133da..37221215a65b 100644
--- a/gcc/ipa-modref.cc
+++ b/gcc/ipa-modref.cc
@@ -3291,7 +3291,8 @@ analyze_function (bool ipa)
fprintf (dump_file, "  Flags for param %i improved:",
 (int)i);
  else
-   gcc_unreachable ();
+   fprintf (dump_file, "  Flags for param %i changed:",
+(int)i);
  dump_eaf_flags (dump_file, old_flags, false);
  fprintf (dump_file, " -> ");
  dump_eaf_flags (dump_file, new_flags, true);
@@ -3307,7 +3308,7 @@ analyze_function (bool ipa)
  || (summary->retslot_flags & EAF_UNUSED))
fprintf (dump_file, "  Flags for retslot improved:");
  else
-   gcc_unreachable ();
+   fprintf (dump_file, "  Flags for retslot changed:");
  dump_eaf_flags (dump_file, past_retslot_flags, false);
  fprintf (dump_file, " -> ");
  dump_eaf_flags (dump_file, summary->retslot_flags, true);
@@ -3322,7 +3323,7 @@ analyze_function (bool ipa)
  || (summary->static_chain_flags & EAF_UNUSED))
fprintf (dump_file, "  Flags for static chain improved:");
  else
-   gcc_unreachable ();
+   fprintf (dump_file, "  Flags for static chain changed:");
  dump_eaf_flags (dump_file, past_static_chain_flags, false);
  fprintf (dump_file, " -> ");
  dump_eaf_flags (dump_file, summary->static_chain_flags, true);

[gcc r15-2376] Fix ICE with -fdump-tree-moref

[Jan Hubicka via Gcc-cvs]

https://gcc.gnu.org/g:b3176b620ff29a06c90992ca3d29f3cffd459537

commit r15-2376-gb3176b620ff29a06c90992ca3d29f3cffd459537
Author: Jan Hubicka 
Date:   Mon Jul 29 10:49:49 2024 +0200

Fix ICE with -fdump-tree-moref

gcc/ChangeLog:

PR ipa/116055
* ipa-modref.cc (analyze_function): Do not ICE when flags regress.

Diff:
---
 gcc/ipa-modref.cc | 7 ---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/gcc/ipa-modref.cc b/gcc/ipa-modref.cc
index f6a758b5f427..59cfe91f987a 100644
--- a/gcc/ipa-modref.cc
+++ b/gcc/ipa-modref.cc
@@ -3297,7 +3297,8 @@ analyze_function (bool ipa)
fprintf (dump_file, "  Flags for param %i improved:",
 (int)i);
  else
-   gcc_unreachable ();
+   fprintf (dump_file, "  Flags for param %i changed:",
+(int)i);
  dump_eaf_flags (dump_file, old_flags, false);
  fprintf (dump_file, " -> ");
  dump_eaf_flags (dump_file, new_flags, true);
@@ -3313,7 +3314,7 @@ analyze_function (bool ipa)
  || (summary->retslot_flags & EAF_UNUSED))
fprintf (dump_file, "  Flags for retslot improved:");
  else
-   gcc_unreachable ();
+   fprintf (dump_file, "  Flags for retslot changed:");
  dump_eaf_flags (dump_file, past_retslot_flags, false);
  fprintf (dump_file, " -> ");
  dump_eaf_flags (dump_file, summary->retslot_flags, true);
@@ -3328,7 +3329,7 @@ analyze_function (bool ipa)
  || (summary->static_chain_flags & EAF_UNUSED))
fprintf (dump_file, "  Flags for static chain improved:");
  else
-   gcc_unreachable ();
+   fprintf (dump_file, "  Flags for static chain changed:");
  dump_eaf_flags (dump_file, past_static_chain_flags, false);
  fprintf (dump_file, " -> ");
  dump_eaf_flags (dump_file, summary->static_chain_flags, true);

[gcc r15-2377] libgomp: Fix declare target link with offset array-section mapping [PR116107]

[Tobias Burnus via Gcc-cvs]

https://gcc.gnu.org/g:14c47e7eb06e8b95913794f6059560fc2fa6de91

commit r15-2377-g14c47e7eb06e8b95913794f6059560fc2fa6de91
Author: Tobias Burnus 
Date:   Mon Jul 29 11:40:38 2024 +0200

libgomp: Fix declare target link with offset array-section mapping 
[PR116107]

Assume that 'int var[100]' is 'omp declare target link(var)'. When now
mapping an array section with offset such as 'map(to:var[20:10])',
the device-side link pointer has to store &[0] minus
the offset such that var[20] will access [0]. But
the offset calculation was missed such that the device-side 'var' pointed
to the first element of the mapped data - and var[20] points beyond at
some invalid memory.

PR middle-end/116107

libgomp/ChangeLog:

* target.c (gomp_map_vars_internal): Honor array mapping offsets
with declare-target 'link' variables.
* testsuite/libgomp.c-c++-common/target-link-2.c: New test.

Diff:
---
 libgomp/target.c   |  7 ++-
 .../testsuite/libgomp.c-c++-common/target-link-2.c | 59 ++
 2 files changed, 64 insertions(+), 2 deletions(-)

diff --git a/libgomp/target.c b/libgomp/target.c
index aa01c1367b98..efed6ad68ff4 100644
--- a/libgomp/target.c
+++ b/libgomp/target.c
@@ -1820,8 +1820,11 @@ gomp_map_vars_internal (struct gomp_device_descr 
*devicep,
if (k->aux && k->aux->link_key)
  {
/* Set link pointer on target to the device address of the
-  mapped object.  */
-   void *tgt_addr = (void *) (tgt->tgt_start + k->tgt_offset);
+  mapped object.  Also deal with offsets due to
+  array-section mapping.  */
+   void *tgt_addr = (void *) (tgt->tgt_start + k->tgt_offset
+  - (k->host_start
+ - 
k->aux->link_key->host_start));
/* We intentionally do not use coalescing here, as it's not
   data allocated by the current call to this function.  */
gomp_copy_host2dev (devicep, aq, (void *) n->tgt_offset,
diff --git a/libgomp/testsuite/libgomp.c-c++-common/target-link-2.c 
b/libgomp/testsuite/libgomp.c-c++-common/target-link-2.c
new file mode 100644
index ..15da1656ebf9
--- /dev/null
+++ b/libgomp/testsuite/libgomp.c-c++-common/target-link-2.c
@@ -0,0 +1,59 @@
+/* { dg-do run }  */
+/* PR middle-end/116107  */
+
+#include 
+
+int arr[15] = {1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};
+#pragma omp declare target link(arr)
+
+#pragma omp begin declare target
+void f(int *res)
+{
+  __builtin_memcpy (res, &arr[5], sizeof(int)*10);
+}
+
+void g(int *res)
+{
+  __builtin_memcpy (res, &arr[3], sizeof(int)*10);
+}
+#pragma omp end declare target
+
+int main()
+{
+  int res[10], res2;
+  for (int dev = 0; dev < omp_get_num_devices(); dev++)
+{
+  __builtin_memset (res, 0, sizeof (res));
+  res2 = 99;
+
+  #pragma omp target enter data map(arr[5:10]) device(dev)
+
+  #pragma omp target map(from: res) device(dev)
+   f (res);
+
+  #pragma omp target map(from: res2) device(dev)
+   res2 = arr[5];
+
+  if (res2 != 6)
+   __builtin_abort ();
+  for (int i = 0; i < 10; i++)
+   if (res[i] != 6 + i)
+ __builtin_abort ();
+
+  #pragma omp target exit data map(release:arr[5:10]) device(dev)
+
+  for (int i = 0; i < 15; i++)
+   arr[i] *= 10;
+  __builtin_memset (res, 0, sizeof (res));
+
+  #pragma omp target enter data map(arr[3:10]) device(dev)
+
+  #pragma omp target map(from: res) device(dev)
+   g (res);
+
+  for (int i = 0; i < 10; i++)
+   if (res[i] != (4 + i)*10)
+ __builtin_abort ();
+}
+  return 0;
+}

[gcc r15-2378] OpenMP/Fortran: Fix handling of 'declare target' with 'link' clause [PR115559]

[Tobias Burnus via Gcc-cvs]

https://gcc.gnu.org/g:29b1587e7d34667a1fd63071c1e4f5475cd71026

commit r15-2378-g29b1587e7d34667a1fd63071c1e4f5475cd71026
Author: Tobias Burnus 
Date:   Mon Jul 29 11:46:57 2024 +0200

OpenMP/Fortran: Fix handling of 'declare target' with 'link' clause 
[PR115559]

Contrary to a normal 'declare target', the 'declare target link' attribute
also needs to set node->offloadable and push the offload_vars in the front 
end.

Linked variables require that the data is mapped. For module variables, this
can happen anywhere. For variables in an external subprograms or the main
programm, this can only happen in the either that program itself or in an
internal subprogram. - Whether a variable is just normally mapped or linked 
then
becomes relevant if a device routine exists that can access that variable,
i.e. an internal procedure has then to be marked as declare target.

PR fortran/115559

gcc/fortran/ChangeLog:

* trans-common.cc (build_common_decl): Add 'omp declare target' and
'omp declare target link' variables to offload_vars.
* trans-decl.cc (add_attributes_to_decl): Likewise; update args and
call decl_attributes.
(get_proc_pointer_decl, gfc_get_extern_function_decl,
build_function_decl): Update calls.
(gfc_get_symbol_decl): Likewise; move after 'DECL_STATIC (t)=1'
to avoid errors with symtab_node::get_create.

libgomp/ChangeLog:

* testsuite/libgomp.fortran/declare-target-link.f90: New test.

Diff:
---
 gcc/fortran/trans-common.cc|  21 
 gcc/fortran/trans-decl.cc  |  81 +-
 .../libgomp.fortran/declare-target-link.f90| 116 +
 3 files changed, 192 insertions(+), 26 deletions(-)

diff --git a/gcc/fortran/trans-common.cc b/gcc/fortran/trans-common.cc
index 5f44e7bd663d..e714342c3c0b 100644
--- a/gcc/fortran/trans-common.cc
+++ b/gcc/fortran/trans-common.cc
@@ -98,6 +98,9 @@ along with GCC; see the file COPYING3.  If not see
 #include "coretypes.h"
 #include "tm.h"
 #include "tree.h"
+#include "cgraph.h"
+#include "context.h"
+#include "omp-offload.h"
 #include "gfortran.h"
 #include "trans.h"
 #include "stringpool.h"
@@ -497,6 +500,24 @@ build_common_decl (gfc_common_head *com, tree union_type, 
bool is_init)
  = tree_cons (get_identifier ("omp declare target"),
   omp_clauses, DECL_ATTRIBUTES (decl));
 
+  if (com->omp_declare_target_link || com->omp_declare_target)
+   {
+ /* Add to offload_vars; get_create does so for omp_declare_target,
+omp_declare_target_link requires manual work.  */
+ gcc_assert (symtab_node::get (decl) == 0);
+ symtab_node *node = symtab_node::get_create (decl);
+ if (node != NULL && com->omp_declare_target_link)
+   {
+ node->offloadable = 1;
+ if (ENABLE_OFFLOADING)
+   {
+ g->have_offload = true;
+ if (is_a  (node))
+   vec_safe_push (offload_vars, decl);
+   }
+   }
+   }
+
   /* Place the back end declaration for this common block in
  GLOBAL_BINDING_LEVEL.  */
   gfc_map_of_all_commons[identifier] = pushdecl_top_level (decl);
diff --git a/gcc/fortran/trans-decl.cc b/gcc/fortran/trans-decl.cc
index 82fa2bb61349..0fdc41b1784b 100644
--- a/gcc/fortran/trans-decl.cc
+++ b/gcc/fortran/trans-decl.cc
@@ -46,7 +46,9 @@ along with GCC; see the file COPYING3.  If not see
 #include "trans-stmt.h"
 #include "gomp-constants.h"
 #include "gimplify.h"
+#include "context.h"
 #include "omp-general.h"
+#include "omp-offload.h"
 #include "attr-fnspec.h"
 #include "tree-iterator.h"
 #include "dependency.h"
@@ -1472,19 +1474,18 @@ gfc_add_assign_aux_vars (gfc_symbol * sym)
 }
 
 
-static tree
-add_attributes_to_decl (symbol_attribute sym_attr, tree list)
+static void
+add_attributes_to_decl (tree *decl_p, const gfc_symbol *sym)
 {
   unsigned id;
-  tree attr;
+  tree list = NULL_TREE;
+  symbol_attribute sym_attr = sym->attr;
 
   for (id = 0; id < EXT_ATTR_NUM; id++)
 if (sym_attr.ext_attr & (1 << id) && ext_attr_list[id].middle_end_name)
   {
-   attr = build_tree_list (
-get_identifier (ext_attr_list[id].middle_end_name),
-NULL_TREE);
-   list = chainon (list, attr);
+   tree ident = get_identifier (ext_attr_list[id].middle_end_name);
+   list = tree_cons (ident, NULL_TREE, list);
   }
 
   tree clauses = NULL_TREE;
@@ -1547,6 +1548,7 @@ add_attributes_to_decl (symbol_attribute sym_attr, tree 
list)
   clauses = c;
 }
 
+  bool has_declare = true;
   if (sym_attr.omp_declare_target_link
   || sym_attr.oacc_declare_link)
 list = tree_cons (get_identifier ("omp declare target link"),
@@ -1558,12 +1560,45 @@ add_attributes_t

[gcc/devel/omp/gcc-14] (33 commits) Merge remote-tracking branch 'origin/releases/gcc-14' into

[Tobias Burnus via Gcc-cvs]

The branch 'devel/omp/gcc-14' was updated to point to:

 8ad1a509662a... Merge remote-tracking branch 'origin/releases/gcc-14' into 

It previously pointed to:

 b71fc8d1382b... Merge remote-tracking branch 'origin/releases/gcc-14' into 

Diff:

Summary of changes (added commits):
---

  8ad1a50... Merge remote-tracking branch 'origin/releases/gcc-14' into 
  9e05aff... OpenMP/Fortran: Fix handling of 'declare target' with 'link
  c9e52a1... libgomp: Fix declare target link with offset array-section 
  98baaa1... Fix ICE with -fdump-tree-moref (*)
  affb2e8... i386: Fix AVX512 intrin macro typo (*)
  b858a51... Daily bump. (*)
  c3eef3d... Daily bump. (*)
  8eae5b0... Daily bump. (*)
  92eb0ee... Daily bump. (*)
  a32aff1... Regenerate gcc.pot (*)
  a7f07e5... Daily bump. (*)
  181f40f... testsuite: Fix up pr116034.c test for big/pdp endian [PR116 (*)
  ab03866... RISC-V: Disable Zba optimization pattern if XTheadMemIdx is (*)
  ae2909a... Daily bump. (*)
  a544898... testsuite: Disable finite math only for test  [PR115826] (*)
  b41487a... libstdc++: Use [[maybe_unused]] attribute in src/c++23/prin (*)
  5fad887... libstdc++: Do not use isatty on avr [PR115482] (*)
  084768c... ssa: Fix up maybe_rewrite_mem_ref_base complex type handlin (*)
  81f356f... i386: Change prefetchi output template (*)
  109b389... [powerpc] [testsuite] reorder dg directives [PR106069] (*)
  066c789... c++/coroutines: correct passing *this to promise type [PR10 (*)
  50ff112... c++: xobj fn call without obj [PR115783] (*)
  dfae324... Daily bump. (*)
  9ddd5f8... Fix modref's iteraction with store merging (*)
  bd535b4... rs6000: Catch unsupported ABI errors when using -mrop-prote (*)
  35e5c2d... rs6000: Error on CPUs and ABIs that don't support the ROP p (*)
  e2d746e... rs6000: ROP - Emit hashst and hashchk insns on Power8 and l (*)
  33ebeb2... rs6000: Compute rop_hash_save_offset for non-Altivec compil (*)
  c33532c... rs6000: Update ELFv2 stack frame comment showing the correc (*)
  27ef3a0... Fix modref_eaf_analysis::analyze_ssa_name handling of value (*)
  f2e9808... Fix accounting of offsets in unadjusted_ptr_and_unit_offset (*)
  c5397d3... Compare loop bounds in ipa-icf (*)
  9a7d668... Reduce recursive inlining of always_inline functions (*)

(*) This commit already exists in another branch.
Because the reference `refs/heads/devel/omp/gcc-14' matches
your hooks.email-new-commits-only configuration,
no separate email is sent for this commit.

[gcc/devel/omp/gcc-14] libgomp: Fix declare target link with offset array-section mapping [PR116107]

[Tobias Burnus via Gcc-cvs]

https://gcc.gnu.org/g:c9e52a1a3d2c2970065c254a414bab76f798ce7d

commit c9e52a1a3d2c2970065c254a414bab76f798ce7d
Author: Tobias Burnus 
Date:   Mon Jul 29 12:50:56 2024 +0200

libgomp: Fix declare target link with offset array-section mapping 
[PR116107]

Assume that 'int var[100]' is 'omp declare target link(var)'. When now
mapping an array section with offset such as 'map(to:var[20:10])',
the device-side link pointer has to store &[0] minus
the offset such that var[20] will access [0]. But
the offset calculation was missed such that the device-side 'var' pointed
to the first element of the mapped data - and var[20] points beyond at
some invalid memory.

PR middle-end/116107

libgomp/ChangeLog:

* target.c (gomp_map_vars_internal): Honor array mapping offsets
with declare-target 'link' variables.
* testsuite/libgomp.c-c++-common/target-link-2.c: New test.

(cherry picked from commit 14c47e7eb06e8b95913794f6059560fc2fa6de91)

Diff:
---
 libgomp/ChangeLog  | 11 
 libgomp/target.c   |  7 ++-
 .../testsuite/libgomp.c-c++-common/target-link-2.c | 59 ++
 3 files changed, 75 insertions(+), 2 deletions(-)

diff --git a/libgomp/ChangeLog b/libgomp/ChangeLog
index 555f1f126f26..aaa2e8defe3e 100644
--- a/libgomp/ChangeLog
+++ b/libgomp/ChangeLog
@@ -1,3 +1,14 @@
+-- libgomp/ChangeLog -- 
+2024-07-29  Tobias Burnus  
+
+   Backported from master:
+   2024-07-29  Tobias Burnus  
+
+   PR middle-end/116107
+   * target.c (gomp_map_vars_internal): Honor array mapping offsets
+   with declare-target 'link' variables.
+   * testsuite/libgomp.c-c++-common/target-link-2.c: New test.
+
 2024-05-07  Jakub Jelinek  
 
Backported from master:
diff --git a/libgomp/target.c b/libgomp/target.c
index caa501c27acb..eb02d478e109 100644
--- a/libgomp/target.c
+++ b/libgomp/target.c
@@ -1892,8 +1892,11 @@ gomp_map_vars_internal (struct gomp_device_descr 
*devicep,
if (k->aux && k->aux->link_key)
  {
/* Set link pointer on target to the device address of the
-  mapped object.  */
-   void *tgt_addr = (void *) (tgt->tgt_start + k->tgt_offset);
+  mapped object.  Also deal with offsets due to
+  array-section mapping.  */
+   void *tgt_addr = (void *) (tgt->tgt_start + k->tgt_offset
+  - (k->host_start
+ - 
k->aux->link_key->host_start));
/* We intentionally do not use coalescing here, as it's not
   data allocated by the current call to this function.  */
gomp_copy_host2dev (devicep, aq, (void *) n->tgt_offset,
diff --git a/libgomp/testsuite/libgomp.c-c++-common/target-link-2.c 
b/libgomp/testsuite/libgomp.c-c++-common/target-link-2.c
new file mode 100644
index ..15da1656ebf9
--- /dev/null
+++ b/libgomp/testsuite/libgomp.c-c++-common/target-link-2.c
@@ -0,0 +1,59 @@
+/* { dg-do run }  */
+/* PR middle-end/116107  */
+
+#include 
+
+int arr[15] = {1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};
+#pragma omp declare target link(arr)
+
+#pragma omp begin declare target
+void f(int *res)
+{
+  __builtin_memcpy (res, &arr[5], sizeof(int)*10);
+}
+
+void g(int *res)
+{
+  __builtin_memcpy (res, &arr[3], sizeof(int)*10);
+}
+#pragma omp end declare target
+
+int main()
+{
+  int res[10], res2;
+  for (int dev = 0; dev < omp_get_num_devices(); dev++)
+{
+  __builtin_memset (res, 0, sizeof (res));
+  res2 = 99;
+
+  #pragma omp target enter data map(arr[5:10]) device(dev)
+
+  #pragma omp target map(from: res) device(dev)
+   f (res);
+
+  #pragma omp target map(from: res2) device(dev)
+   res2 = arr[5];
+
+  if (res2 != 6)
+   __builtin_abort ();
+  for (int i = 0; i < 10; i++)
+   if (res[i] != 6 + i)
+ __builtin_abort ();
+
+  #pragma omp target exit data map(release:arr[5:10]) device(dev)
+
+  for (int i = 0; i < 15; i++)
+   arr[i] *= 10;
+  __builtin_memset (res, 0, sizeof (res));
+
+  #pragma omp target enter data map(arr[3:10]) device(dev)
+
+  #pragma omp target map(from: res) device(dev)
+   g (res);
+
+  for (int i = 0; i < 10; i++)
+   if (res[i] != (4 + i)*10)
+ __builtin_abort ();
+}
+  return 0;
+}

[gcc/devel/omp/gcc-14] OpenMP/Fortran: Fix handling of 'declare target' with 'link' clause [PR115559]

[Tobias Burnus via Gcc-cvs]

https://gcc.gnu.org/g:9e05aff533d8c506aa6a99a1b9ac5c1743862af7

commit 9e05aff533d8c506aa6a99a1b9ac5c1743862af7
Author: Tobias Burnus 
Date:   Mon Jul 29 12:52:11 2024 +0200

OpenMP/Fortran: Fix handling of 'declare target' with 'link' clause 
[PR115559]

Contrary to a normal 'declare target', the 'declare target link' attribute
also needs to set node->offloadable and push the offload_vars in the front 
end.

Linked variables require that the data is mapped. For module variables, this
can happen anywhere. For variables in an external subprograms or the main
programm, this can only happen in the either that program itself or in an
internal subprogram. - Whether a variable is just normally mapped or linked 
then
becomes relevant if a device routine exists that can access that variable,
i.e. an internal procedure has then to be marked as declare target.

PR fortran/115559

gcc/fortran/ChangeLog:

* trans-common.cc (build_common_decl): Add 'omp declare target' and
'omp declare target link' variables to offload_vars.
* trans-decl.cc (add_attributes_to_decl): Likewise; update args and
call decl_attributes.
(get_proc_pointer_decl, gfc_get_extern_function_decl,
build_function_decl): Update calls.
(gfc_get_symbol_decl): Likewise; move after 'DECL_STATIC (t)=1'
to avoid errors with symtab_node::get_create.

libgomp/ChangeLog:

* testsuite/libgomp.fortran/declare-target-link.f90: New test.

(cherry picked from commit 29b1587e7d34667a1fd63071c1e4f5475cd71026)

Diff:
---
 gcc/fortran/ChangeLog.omp  |  15 +++
 gcc/fortran/trans-common.cc|  21 
 gcc/fortran/trans-decl.cc  |  81 +-
 libgomp/ChangeLog.omp  |   8 ++
 .../libgomp.fortran/declare-target-link.f90| 116 +
 5 files changed, 215 insertions(+), 26 deletions(-)

diff --git a/gcc/fortran/ChangeLog.omp b/gcc/fortran/ChangeLog.omp
index 917fad1de90a..31470f4852e4 100644
--- a/gcc/fortran/ChangeLog.omp
+++ b/gcc/fortran/ChangeLog.omp
@@ -1,3 +1,18 @@
+2024-07-29  Tobias Burnus  
+
+   Backported from master:
+   2024-07-29  Tobias Burnus  
+
+   PR fortran/115559
+   * trans-common.cc (build_common_decl): Add 'omp declare target' and
+   'omp declare target link' variables to offload_vars.
+   * trans-decl.cc (add_attributes_to_decl): Likewise; update args and
+   call decl_attributes.
+   (get_proc_pointer_decl, gfc_get_extern_function_decl,
+   build_function_decl): Update calls.
+   (gfc_get_symbol_decl): Likewise; move after 'DECL_STATIC (t)=1'
+   to avoid errors with symtab_node::get_create.
+
 2024-07-03  Thomas Schwinge  
 
* class.cc (generate_callback_wrapper) [GCC_NVPTX_H]: Disable.
diff --git a/gcc/fortran/trans-common.cc b/gcc/fortran/trans-common.cc
index 5f44e7bd663d..e714342c3c0b 100644
--- a/gcc/fortran/trans-common.cc
+++ b/gcc/fortran/trans-common.cc
@@ -98,6 +98,9 @@ along with GCC; see the file COPYING3.  If not see
 #include "coretypes.h"
 #include "tm.h"
 #include "tree.h"
+#include "cgraph.h"
+#include "context.h"
+#include "omp-offload.h"
 #include "gfortran.h"
 #include "trans.h"
 #include "stringpool.h"
@@ -497,6 +500,24 @@ build_common_decl (gfc_common_head *com, tree union_type, 
bool is_init)
  = tree_cons (get_identifier ("omp declare target"),
   omp_clauses, DECL_ATTRIBUTES (decl));
 
+  if (com->omp_declare_target_link || com->omp_declare_target)
+   {
+ /* Add to offload_vars; get_create does so for omp_declare_target,
+omp_declare_target_link requires manual work.  */
+ gcc_assert (symtab_node::get (decl) == 0);
+ symtab_node *node = symtab_node::get_create (decl);
+ if (node != NULL && com->omp_declare_target_link)
+   {
+ node->offloadable = 1;
+ if (ENABLE_OFFLOADING)
+   {
+ g->have_offload = true;
+ if (is_a  (node))
+   vec_safe_push (offload_vars, decl);
+   }
+   }
+   }
+
   /* Place the back end declaration for this common block in
  GLOBAL_BINDING_LEVEL.  */
   gfc_map_of_all_commons[identifier] = pushdecl_top_level (decl);
diff --git a/gcc/fortran/trans-decl.cc b/gcc/fortran/trans-decl.cc
index 643c93f36ee8..019e845bf9f0 100644
--- a/gcc/fortran/trans-decl.cc
+++ b/gcc/fortran/trans-decl.cc
@@ -46,7 +46,9 @@ along with GCC; see the file COPYING3.  If not see
 #include "trans-stmt.h"
 #include "gomp-constants.h"
 #include "gimplify.h"
+#include "context.h"
 #include "omp-general.h"
+#include "omp-offload.h"
 #include "attr-fnspec.h"
 #include "tree-iterator.h"
 
@@ -1450,19 +1452,18 @@ gfc_add_assign_aux_vars (gfc_symbol * sym)

[gcc/devel/omp/gcc-14] Merge remote-tracking branch 'origin/releases/gcc-14' into devel/omp/gcc-14

[Tobias Burnus via Gcc-cvs]

https://gcc.gnu.org/g:8ad1a509662a9af828600d053652d6d0f414027c

commit 8ad1a509662a9af828600d053652d6d0f414027c
Merge: 9e05aff533d8 98baaa17561c
Author: Tobias Burnus 
Date:   Mon Jul 29 12:52:36 2024 +0200

Merge remote-tracking branch 'origin/releases/gcc-14' into devel/omp/gcc-14

Merge up to commit r14-10515-g98baaa17561ca2 (29th July 2024)

Diff:

 gcc/ChangeLog  |  131 +
 gcc/DATESTAMP  |2 +-
 gcc/config/i386/avx512dqintrin.h   |   16 +-
 gcc/config/i386/avx512vlbwintrin.h |4 +-
 gcc/config/i386/avx512vlintrin.h   |2 +-
 gcc/config/i386/i386.md|2 +-
 gcc/config/riscv/bitmanip.md   |2 +-
 gcc/config/rs6000/rs6000-logue.cc  |   47 +-
 gcc/config/rs6000/rs6000.cc|   12 +
 gcc/config/rs6000/rs6000.md|6 +-
 gcc/cp/ChangeLog   |   21 +
 gcc/cp/call.cc |2 +-
 gcc/cp/coroutines.cc   |   18 +-
 gcc/ipa-icf-gimple.cc  |4 +
 gcc/ipa-inline.cc  |   79 +-
 gcc/ipa-modref.cc  |   16 +-
 gcc/ipa-prop.cc|4 +-
 gcc/po/ChangeLog   |4 +
 gcc/po/gcc.pot | 7713 ++--
 gcc/testsuite/ChangeLog|  132 +
 .../g++.dg/coroutines/pr104981-preview-this.C  |   34 +
 .../g++.dg/coroutines/pr115550-preview-this.C  |   47 +
 .../g++.dg/cpp23/explicit-obj-diagnostics11.C  |   48 +
 gcc/testsuite/g++.target/powerpc/pr106069.C|2 +-
 gcc/testsuite/gcc.c-torture/compile/pr115277.c |   28 +
 gcc/testsuite/gcc.c-torture/execute/pr114207.c |   23 +
 gcc/testsuite/gcc.c-torture/execute/pr115033.c |   35 +
 gcc/testsuite/gcc.c-torture/pr111613.c |   29 +
 gcc/testsuite/gcc.dg/pr116034.c|   23 +
 gcc/testsuite/gcc.dg/vect/tsvc/vect-tsvc-s1281.c   |3 +
 .../gcc.target/i386/avx512bw-vpalignr-1b.c |   18 +
 .../gcc.target/i386/avx512dq-vfpclasssd-1b.c   |   14 +
 .../gcc.target/i386/avx512dq-vfpcla-1b.c   |   14 +
 .../gcc.target/i386/avx512dq-vreducesd-1b.c|   16 +
 .../gcc.target/i386/avx512dq-vreducess-1b.c|   16 +
 .../gcc.target/i386/avx512vl-valignq-1b.c  |   15 +
 gcc/testsuite/gcc.target/i386/prefetchi-1.c|4 +-
 gcc/testsuite/gcc.target/powerpc/pr114759-2.c  |   17 +
 gcc/testsuite/gcc.target/powerpc/pr114759-3.c  |   21 +
 gcc/testsuite/gcc.target/powerpc/pr115389.c|   17 +
 gcc/testsuite/gcc.target/riscv/pr116035-1.c|   29 +
 gcc/testsuite/gcc.target/riscv/pr116035-2.c|   26 +
 gcc/testsuite/lib/target-supports.exp  |2 +-
 gcc/tree-ssa.cc|5 +-
 libstdc++-v3/ChangeLog |   17 +
 libstdc++-v3/src/c++23/print.cc|8 +-
 46 files changed, 4796 insertions(+), 3932 deletions(-)

[gcc r15-2379] Widening-Mul: Try .SAT_SUB for PLUS_EXPR when one op is IMM

[Pan Li via Gcc-cvs]

https://gcc.gnu.org/g:696d8b9bf3f0ea60da0c24361dc5fe559f97ab77

commit r15-2379-g696d8b9bf3f0ea60da0c24361dc5fe559f97ab77
Author: Pan Li 
Date:   Sat Jul 27 11:29:42 2024 +0800

Widening-Mul: Try .SAT_SUB for PLUS_EXPR when one op is IMM

After add the matching for .SAT_SUB when one op is IMM,  there
will be a new root PLUS_EXPR for the .SAT_SUB pattern.  For example,

Form 3:
  #define DEF_SAT_U_SUB_IMM_FMT_3(T, IMM) \
  T __attribute__((noinline)) \
  sat_u_sub_imm##IMM##_##T##_fmt_3 (T x)  \
  {   \
return x >= IMM ? x - IMM : 0;\
  }

DEF_SAT_U_SUB_IMM_FMT_3(uint64_t, 11)

And then we will have gimple before widening-mul as below.  Thus,  try
the .SAT_SUB for the PLUS_EXPR.

   4   │ __attribute__((noinline))
   5   │ uint64_t sat_u_sub_imm11_uint64_t_fmt_3 (uint64_t x)
   6   │ {
   7   │   long unsigned int _1;
   8   │   uint64_t _3;
   9   │
  10   │[local count: 1073741824]:
  11   │   _1 = MAX_EXPR ;
  12   │   _3 = _1 + 18446744073709551605;
  13   │   return _3;
  14   │
  15   │ }

The below test suites are passed for this patch.
1. The rv64gcv fully regression tests.
2. The x86 bootstrap tests.
3. The x86 fully regression tests.

gcc/ChangeLog:

* tree-ssa-math-opts.cc (math_opts_dom_walker::after_dom_children):
Try .SAT_SUB for PLUS_EXPR case.

Signed-off-by: Pan Li 

Diff:
---
 gcc/tree-ssa-math-opts.cc | 1 +
 1 file changed, 1 insertion(+)

diff --git a/gcc/tree-ssa-math-opts.cc b/gcc/tree-ssa-math-opts.cc
index ac86be8eb947..8d96a4c964b3 100644
--- a/gcc/tree-ssa-math-opts.cc
+++ b/gcc/tree-ssa-math-opts.cc
@@ -6129,6 +6129,7 @@ math_opts_dom_walker::after_dom_children (basic_block bb)
 
case PLUS_EXPR:
  match_unsigned_saturation_add (&gsi, as_a (stmt));
+ match_unsigned_saturation_sub (&gsi, as_a (stmt));
  /* fall-through  */
case MINUS_EXPR:
  if (!convert_plusminus_to_widen (&gsi, stmt, code))

[gcc r14-10516] c++: ICE with concept, local class, and lambda [PR115561]

[Jason Merrill via Gcc-cvs]

https://gcc.gnu.org/g:f30caf1bda8a0d086d0308e5024c2b4c43cbd6c0

commit r14-10516-gf30caf1bda8a0d086d0308e5024c2b4c43cbd6c0
Author: Jason Merrill 
Date:   Fri Jul 26 16:53:03 2024 -0400

c++: ICE with concept, local class, and lambda [PR115561]

Here when we want to synthesize methods for foo()::B maybe_push_to_top_level
calls push_function_context, which sets cfun to a dummy value; later
finish_call_expr tries to set something in
cp_function_chain (i.e. cfun->language), which isn't set.  Many places in
the compiler check cfun && cp_function_chain to avoid this problem; here we
also want to check !cp_unevaluated_operand, like set_flags_from_callee does.

PR c++/115561

gcc/cp/ChangeLog:

* semantics.cc (finish_call_expr): Check cp_unevaluated_operand.

gcc/testsuite/ChangeLog:

* g++.dg/cpp2a/concepts-lambda21.C: New test.

(cherry picked from commit 3129a2ed6a764c0687efaca9eba53dcf12d1d8a0)

Diff:
---
 gcc/cp/semantics.cc|  2 +-
 gcc/testsuite/g++.dg/cpp2a/concepts-lambda21.C | 69 ++
 2 files changed, 70 insertions(+), 1 deletion(-)

diff --git a/gcc/cp/semantics.cc b/gcc/cp/semantics.cc
index edb8947e4c2f..b5569066708e 100644
--- a/gcc/cp/semantics.cc
+++ b/gcc/cp/semantics.cc
@@ -2951,7 +2951,7 @@ finish_call_expr (tree fn, vec **args, bool 
disallow_virtual,
 -Wredundant-move warning.  */
  suppress_warning (result, OPT_Wpessimizing_move);
 
- if (cfun)
+ if (cfun && cp_function_chain && !cp_unevaluated_operand)
{
  bool abnormal = true;
  for (lkp_iterator iter (maybe_get_fns (fn)); iter; ++iter)
diff --git a/gcc/testsuite/g++.dg/cpp2a/concepts-lambda21.C 
b/gcc/testsuite/g++.dg/cpp2a/concepts-lambda21.C
new file mode 100644
index ..8d701cd4bbc4
--- /dev/null
+++ b/gcc/testsuite/g++.dg/cpp2a/concepts-lambda21.C
@@ -0,0 +1,69 @@
+// PR c++/115561
+// { dg-do compile { target c++20 } }
+
+template
+auto declval() noexcept -> _Tp&&;
+
+template
+struct enable_if
+{ };
+
+template
+struct enable_if
+{ using type = _Tp; };
+
+template
+using enable_if_t = typename enable_if<_Cond, _Tp>::type;
+
+template
+struct is_void
+{ static constexpr bool value = false;  };
+
+template
+using invoke_result_t =
+decltype(declval()(declval()...));
+
+template
+using iter_reference_t = decltype(*declval());
+
+struct iter_move_fn
+{
+template
+constexpr
+auto operator() (I &&i)  -> void;
+} iter_move;
+
+template
+using iter_rvalue_reference_t = decltype(iter_move(declval()));
+
+template
+concept same_as = true;
+
+template
+concept readable_concept_ =
+same_as, iter_rvalue_reference_t>;
+
+template
+concept indirectly_readable =
+readable_concept_>;
+
+template
+using indirect_result_t =
+enable_if_t,
+invoke_result_t>>;
+
+template
+concept transformable =
+   (!is_void>::value);
+
+template
+requires transformable
+constexpr void transform(I, Fun)
+{
+}
+
+void foo()
+{
+struct B {};
+(void) transform((B*)nullptr, [](B) {return 0; });
+}

[gcc r14-10518] c++: if consteval and consteval propagation [PR115583]

[Jason Merrill via Gcc-cvs]

https://gcc.gnu.org/g:9662299593c0b028e5008def72744732da429e9f

commit r14-10518-g9662299593c0b028e5008def72744732da429e9f
Author: Jason Merrill 
Date:   Sat Jul 27 16:40:02 2024 -0400

c++: if consteval and consteval propagation [PR115583]

During speculative constant folding of an if consteval, we take the false
branch, but the true branch is an immediate function context, so we don't
want to to cp_fold_immediate it.  So we could check IF_STMT_CONSTEVAL_P
here.  But beyond that, we don't want to do this inside a call, only when
first parsing a function.

PR c++/115583

gcc/cp/ChangeLog:

* constexpr.cc (cxx_eval_conditional_expression): Don't
cp_fold_immediate for if consteval.

gcc/testsuite/ChangeLog:

* g++.dg/cpp23/consteval-if13.C: New test.

(cherry picked from commit d5f1948640815a554d106542c2e91e4e117aa3bc)

Diff:
---
 gcc/cp/constexpr.cc |  7 +--
 gcc/testsuite/g++.dg/cpp23/consteval-if13.C | 17 +
 2 files changed, 22 insertions(+), 2 deletions(-)

diff --git a/gcc/cp/constexpr.cc b/gcc/cp/constexpr.cc
index 4e94113168bc..630c2190a8e4 100644
--- a/gcc/cp/constexpr.cc
+++ b/gcc/cp/constexpr.cc
@@ -3974,10 +3974,13 @@ cxx_eval_conditional_expression (const constexpr_ctx 
*ctx, tree t,
   if (TREE_CODE (t) == IF_STMT && !val)
 val = void_node;
 
-  /* P2564: a subexpression of a manifestly constant-evaluated expression
- or conversion is an immediate function context.  */
+  /* P2564: If we aren't in immediate function context (including a manifestly
+ constant-evaluated expression), check any uses of immediate functions in
+ the arm we're discarding.  But don't do this inside a call; we already
+ checked when parsing the function.  */
   if (ctx->manifestly_const_eval != mce_true
   && !in_immediate_context ()
+  && !ctx->call
   && cp_fold_immediate (&TREE_OPERAND (t, zero_p ? 1 : 2),
ctx->manifestly_const_eval))
 {
diff --git a/gcc/testsuite/g++.dg/cpp23/consteval-if13.C 
b/gcc/testsuite/g++.dg/cpp23/consteval-if13.C
new file mode 100644
index ..b98bbc33d133
--- /dev/null
+++ b/gcc/testsuite/g++.dg/cpp23/consteval-if13.C
@@ -0,0 +1,17 @@
+// PR c++/115583
+// { dg-do compile { target c++23 } }
+
+consteval int f(int i) {
+  return i;
+}
+const bool b = 0;
+constexpr int g(int i) {
+  if consteval {
+return f(i);
+  } else {
+return i;
+  }
+}
+int main() {
+  return g(1);
+}

[gcc r14-10517] c++: consteval propagation and templates [PR115986]

[Jason Merrill via Gcc-cvs]

https://gcc.gnu.org/g:56d5f8a60519f6c76df671e9f96acf995b0ffc6c

commit r14-10517-g56d5f8a60519f6c76df671e9f96acf995b0ffc6c
Author: Jason Merrill 
Date:   Fri Jul 26 17:20:18 2024 -0400

c++: consteval propagation and templates [PR115986]

Here the call to e() makes us decide to check d() for escalation at EOF, but
while checking it we try to fold_immediate 0_c, and get confused by the
template trees.  Let's not mess with escalation for function templates.

PR c++/115986

gcc/cp/ChangeLog:

* cp-gimplify.cc (remember_escalating_expr): Skip function
templates.

gcc/testsuite/ChangeLog:

* g++.dg/cpp2a/consteval-prop21.C: New test.

(cherry picked from commit a9e9f772c7488ac0c09dd92f28890bdab939771a)

Diff:
---
 gcc/cp/cp-gimplify.cc |  4 
 gcc/testsuite/g++.dg/cpp2a/consteval-prop21.C | 17 +
 2 files changed, 21 insertions(+)

diff --git a/gcc/cp/cp-gimplify.cc b/gcc/cp/cp-gimplify.cc
index 5cbdf0ea4989..7b52fc301d61 100644
--- a/gcc/cp/cp-gimplify.cc
+++ b/gcc/cp/cp-gimplify.cc
@@ -53,6 +53,10 @@ static GTY(()) hash_set *deferred_escalating_exprs;
 static void
 remember_escalating_expr (tree t)
 {
+  if (uses_template_parms (t))
+/* Templates don't escalate, and cp_fold_immediate can get confused by
+   other template trees in the function body (c++/115986).  */
+return;
   if (!deferred_escalating_exprs)
 deferred_escalating_exprs = hash_set::create_ggc (37);
   deferred_escalating_exprs->add (t);
diff --git a/gcc/testsuite/g++.dg/cpp2a/consteval-prop21.C 
b/gcc/testsuite/g++.dg/cpp2a/consteval-prop21.C
new file mode 100644
index ..debbda4f4259
--- /dev/null
+++ b/gcc/testsuite/g++.dg/cpp2a/consteval-prop21.C
@@ -0,0 +1,17 @@
+// PR c++/115986
+// { dg-do compile { target c++20 } }
+
+template 
+constexpr int b(T) {
+  return 0;
+}
+consteval __uint128_t operator"" _c(const char*) { return 0; }
+constexpr char e() {
+  long f = true ? 0 : b(long(1));
+  return b(f);
+}
+template 
+void d() {
+  0_c;
+  static_assert(e());
+}

[gcc r14-10519] testsuite: Fix up consteval-prop21.C for 32-bit targets [PR115986]

[Jason Merrill via Gcc-cvs]

https://gcc.gnu.org/g:61cb0c889e1f9a9f4ea5b22bbe089a906410374a

commit r14-10519-g61cb0c889e1f9a9f4ea5b22bbe089a906410374a
Author: Jakub Jelinek 
Date:   Mon Jul 29 09:33:09 2024 +0200

testsuite: Fix up consteval-prop21.C for 32-bit targets [PR115986]

The test fails on 32-bit targets (which don't support __int128 type).
Using unsigned long long instead still ICEs before the fix and passes
after it on those targets.

2024-07-29  Jakub Jelinek  

PR c++/115986
* g++.dg/cpp2a/consteval-prop21.C (operator "" _c): Use
unsigned long long rather than __uint128_t for return type if int128
is unsupported.

(cherry picked from commit 331f23540eec39fc1e665f573c4aac258bba6043)

Diff:
---
 gcc/testsuite/g++.dg/cpp2a/consteval-prop21.C | 8 +++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/gcc/testsuite/g++.dg/cpp2a/consteval-prop21.C 
b/gcc/testsuite/g++.dg/cpp2a/consteval-prop21.C
index debbda4f4259..36da1bd91f3a 100644
--- a/gcc/testsuite/g++.dg/cpp2a/consteval-prop21.C
+++ b/gcc/testsuite/g++.dg/cpp2a/consteval-prop21.C
@@ -5,7 +5,13 @@ template 
 constexpr int b(T) {
   return 0;
 }
-consteval __uint128_t operator"" _c(const char*) { return 0; }
+consteval
+#ifdef __SIZEOF_INT128__
+__uint128_t
+#else
+unsigned long long
+#endif
+operator"" _c(const char*) { return 0; }
 constexpr char e() {
   long f = true ? 0 : b(long(1));
   return b(f);

[gcc r14-10520] tree-optimization/116057 - wrong code with CCP and vector CTORs

[Richard Biener via Gcc-cvs]

https://gcc.gnu.org/g:a7f1b00ed69810ce7f000d385a60e148d0228d48

commit r14-10520-ga7f1b00ed69810ce7f000d385a60e148d0228d48
Author: Richard Biener 
Date:   Wed Jul 24 13:16:35 2024 +0200

tree-optimization/116057 - wrong code with CCP and vector CTORs

The following fixes an issue with CCPs likely_value when faced with
a vector CTOR containing undef SSA names and constants.  This should
be classified as CONSTANT and not UNDEFINED.

PR tree-optimization/116057
* tree-ssa-ccp.cc (likely_value): Also walk CTORs in stmt
operands to look for constants.

* gcc.dg/torture/pr116057.c: New testcase.

(cherry picked from commit 1ea551514b9c285d801ac5ab8d78b22483ff65af)

Diff:
---
 gcc/testsuite/gcc.dg/torture/pr116057.c | 20 
 gcc/tree-ssa-ccp.cc | 11 +++
 2 files changed, 31 insertions(+)

diff --git a/gcc/testsuite/gcc.dg/torture/pr116057.c 
b/gcc/testsuite/gcc.dg/torture/pr116057.c
new file mode 100644
index ..a7021c8e746e
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/torture/pr116057.c
@@ -0,0 +1,20 @@
+/* { dg-do run } */
+/* { dg-additional-options "-Wno-psabi" } */
+
+#define vect8 __attribute__((vector_size(8)))
+
+vect8 int __attribute__((noipa))
+f(int a)
+{
+  int b;
+  vect8 int t={1,1};
+  if(a) return t;
+  return (vect8 int){0, b};
+}
+
+int main ()
+{
+  if (f(0)[0] != 0)
+__builtin_abort ();
+  return 0;
+}
diff --git a/gcc/tree-ssa-ccp.cc b/gcc/tree-ssa-ccp.cc
index cc78ff20bb81..62f36367060e 100644
--- a/gcc/tree-ssa-ccp.cc
+++ b/gcc/tree-ssa-ccp.cc
@@ -762,6 +762,17 @@ likely_value (gimple *stmt)
continue;
   if (is_gimple_min_invariant (op))
has_constant_operand = true;
+  else if (TREE_CODE (op) == CONSTRUCTOR)
+   {
+ unsigned j;
+ tree val;
+ FOR_EACH_CONSTRUCTOR_VALUE (CONSTRUCTOR_ELTS (op), j, val)
+   if (CONSTANT_CLASS_P (val))
+ {
+   has_constant_operand = true;
+   break;
+ }
+   }
 }
 
   if (has_constant_operand)

[gcc r14-10521] c++: wrong error initializing empty class [PR115900]

[Jason Merrill via Gcc-cvs]

https://gcc.gnu.org/g:da7f0be91e2ae15342541546152a7a27a601c4b4

commit r14-10521-gda7f0be91e2ae15342541546152a7a27a601c4b4
Author: Marek Polacek 
Date:   Wed Jul 17 11:19:32 2024 -0400

c++: wrong error initializing empty class [PR115900]

In r14-409, we started handling empty bases first in cxx_fold_indirect_ref_1
so that we don't need to recurse and waste time.

This caused a bogus "modifying a const object" error.  I'm appending my
analysis from the PR, but basically, cxx_fold_indirect_ref now returns
a different object than before, and we mark the wrong thing as const,
but since we're initializing an empty object, we should avoid setting
the object constness.

~~
Pre-r14-409: we're evaluating the call to C::C(), which is in the body of
B::B(), which is the body of D::D(&d):

  C::C ((struct C *) this, NON_LVALUE_EXPR <0>)

It's a ctor so we get here:

 3118   /* Remember the object we are constructing or destructing.  */
 3119   tree new_obj = NULL_TREE;
 3120   if (DECL_CONSTRUCTOR_P (fun) || DECL_DESTRUCTOR_P (fun))
 3121 {
 3122   /* In a cdtor, it should be the first `this' argument.
 3123  At this point it has already been evaluated in the call
 3124  to cxx_bind_parameters_in_call.  */
 3125   new_obj = TREE_VEC_ELT (new_call.bindings, 0);

new_obj=(struct C *) &d.D.2656

 3126   new_obj = cxx_fold_indirect_ref (ctx, loc, DECL_CONTEXT (fun), 
new_obj);

new_obj=d.D.2656.D.2597

We proceed to evaluate the call, then we get here:

 3317   /* At this point, the object's constructor will have run, so
 3318  the object is no longer under construction, and its 
possible
 3319  'const' semantics now apply.  Make a note of this fact by
 3320  marking the CONSTRUCTOR TREE_READONLY.  */
 3321   if (new_obj && DECL_CONSTRUCTOR_P (fun))
 3322 cxx_set_object_constness (ctx, new_obj, 
/*readonly_p=*/true,
 3323   non_constant_p, overflow_p);

new_obj is still d.D.2656.D.2597, its type is "C", cxx_set_object_constness
doesn't set anything as const.  This is fine.

After r14-409: on line 3125, new_obj is (struct C *) &d.D.2656 as before,
but we go to cxx_fold_indirect_ref_1:

 5739   if (is_empty_class (type)
 5740   && CLASS_TYPE_P (optype)
 5741   && lookup_base (optype, type, ba_any, NULL, tf_none, off))
 5742 {
 5743   if (empty_base)
 5744 *empty_base = true;
 5745   return op;

type is C, which is an empty class; optype is "const D", and C is a base of 
D.
So we return the VAR_DECL 'd'.  Then we get to cxx_set_object_constness with
object=d, which is const, so we mark the constructor READONLY.

Then we're evaluating A::A() which has

  ((A*)this)->data = 0;

we evaluate the LHS to d.D.2656.a, for which the initializer is
{.D.2656={.a={.data=}}} which is TREE_READONLY and 'd' is const, so we think
we're modifying a const object and fail the constexpr evaluation.

PR c++/115900

gcc/cp/ChangeLog:

* constexpr.cc (cxx_eval_call_expression): Set new_obj to NULL_TREE
if cxx_fold_indirect_ref set empty_base to true.

gcc/testsuite/ChangeLog:

* g++.dg/cpp2a/constexpr-init23.C: New test.

(cherry picked from commit d890b04197fb0ddba4fbfb32f88e266fa27e02f3)

Diff:
---
 gcc/cp/constexpr.cc   | 14 ++
 gcc/testsuite/g++.dg/cpp2a/constexpr-init23.C | 22 ++
 2 files changed, 32 insertions(+), 4 deletions(-)

diff --git a/gcc/cp/constexpr.cc b/gcc/cp/constexpr.cc
index 630c2190a8e4..9b36f7628f36 100644
--- a/gcc/cp/constexpr.cc
+++ b/gcc/cp/constexpr.cc
@@ -3123,10 +3123,16 @@ cxx_eval_call_expression (const constexpr_ctx *ctx, 
tree t,
 At this point it has already been evaluated in the call
 to cxx_bind_parameters_in_call.  */
   new_obj = TREE_VEC_ELT (new_call.bindings, 0);
-  new_obj = cxx_fold_indirect_ref (ctx, loc, DECL_CONTEXT (fun), new_obj);
-
-  if (ctx->call && ctx->call->fundef
- && DECL_CONSTRUCTOR_P (ctx->call->fundef->decl))
+  bool empty_base = false;
+  new_obj = cxx_fold_indirect_ref (ctx, loc, DECL_CONTEXT (fun), new_obj,
+  &empty_base);
+  /* If we're initializing an empty class, don't set constness, because
+cxx_fold_indirect_ref will return the wrong object to set constness
+of.  */
+  if (empty_base)
+   new_obj = NULL_TREE;
+  else if (ctx->call && ctx->call->fundef
+  && DECL_CONSTRUCTOR_P (ctx->call->fundef->decl))
{
  tree cur_obj = TREE_VEC_ELT (ctx->call->bin

[gcc r15-2380] rs6000, add comment to VEC_IC definition

[Carl Love via Gcc-cvs]

https://gcc.gnu.org/g:b30eda6ad4877508bf0cb5dcc7cba3b18cd5265e

commit r15-2380-gb30eda6ad4877508bf0cb5dcc7cba3b18cd5265e
Author: Carl Love 
Date:   Mon Jul 29 11:17:14 2024 -0400

rs6000, add comment to VEC_IC definition

This patch adds a comment to the VEC_IC definition to clarify
the V1TI "TARGET_POWER10" mode that was added.

gcc/ChangeLog:
* config/rs6000/vector.md: Add comment for the VEC_IC
define_mode_iterator.

Diff:
---
 gcc/config/rs6000/vector.md | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/gcc/config/rs6000/vector.md b/gcc/config/rs6000/vector.md
index 0d3e0a24e118..524ba87d6d1d 100644
--- a/gcc/config/rs6000/vector.md
+++ b/gcc/config/rs6000/vector.md
@@ -26,7 +26,8 @@
 ;; Vector int modes
 (define_mode_iterator VEC_I [V16QI V8HI V4SI V2DI])
 
-;; Vector int modes for comparison, shift and rotation
+;; Vector int modes for comparison, shift and rotation.  ISA 3.1 adds the V1TI 
mode
+;; for the vector int128 type.
 (define_mode_iterator VEC_IC [V16QI V8HI V4SI V2DI (V1TI "TARGET_POWER10")])
 
 ;; 128-bit int modes

[gcc r15-2381] libgomp.texi: Update 'Device Information Routines' section

[Tobias Burnus via Gcc-cvs]

https://gcc.gnu.org/g:8d3325708c107d20d41f0bddb0ad161c18934561

commit r15-2381-g8d3325708c107d20d41f0bddb0ad161c18934561
Author: Tobias Burnus 
Date:   Mon Jul 29 17:43:42 2024 +0200

libgomp.texi: Update 'Device Information Routines' section

Update 'OpenMP Runtime Library Routines' by adding a note that invoking
inside a target region might invoke unspecified behavior. Additionally,
update omp_{get,set}_default_device for omp_{initial,invalid}_device
named constants.

libgomp/ChangeLog:

* libgomp.texi (OpenMP Runtime Library Routines): Add missing
title to some commented still undocumented items.
(Device Information Routines): Update.

Diff:
---
 libgomp/libgomp.texi | 48 +---
 1 file changed, 33 insertions(+), 15 deletions(-)

diff --git a/libgomp/libgomp.texi b/libgomp/libgomp.texi
index 50da248b74db..07cd75124b07 100644
--- a/libgomp/libgomp.texi
+++ b/libgomp/libgomp.texi
@@ -1208,11 +1208,11 @@ They have C linkage and do not throw exceptions.
 
 @menu
 * omp_get_proc_bind::   Whether threads may be moved between CPUs
-@c * omp_get_num_places:: 
-@c * omp_get_place_num_procs:: 
-@c * omp_get_place_proc_ids:: 
-@c * omp_get_place_num:: 
-@c * omp_get_partition_num_places:: 
+@c * omp_get_num_places::   Get the number of places available
+@c * omp_get_place_num_procs::  Get the number of processes associated with a 
place
+@c * omp_get_place_proc_ids::   Get number of processes associated with a place
+@c * omp_get_place_num::Get place number of the associated task
+@c * omp_get_partition_num_places:: Get number of places of innermost task
 @c * omp_get_partition_place_nums:: 
 @c * omp_set_affinity_format:: 
 @c * omp_get_affinity_format:: 
@@ -1627,8 +1627,12 @@ Returns the number of processors online on that device.
 @subsection @code{omp_set_default_device} -- Set the default device for target 
regions
 @table @asis
 @item @emph{Description}:
-Set the default device for target regions without device clause.  The argument
-shall be a nonnegative device number.
+Get the value of the @emph{default-device-var} ICV, which is used
+for target regions without a device clause.  The argument
+shall be a nonnegative device number, @code{omp_initial_device},
+or @code{omp_invalid_device}.
+
+The effect of running this routine in a @code{target} region is unspecified.
 
 @item @emph{C/C++}:
 @multitable @columnfractions .20 .80
@@ -1654,7 +1658,15 @@ shall be a nonnegative device number.
 @subsection @code{omp_get_default_device} -- Get the default device for target 
regions
 @table @asis
 @item @emph{Description}:
-Get the default device for target regions without device clause.
+Get the value of the @emph{default-device-var} ICV, which is used
+for target regions without a device clause. The value is either a
+nonnegative device number, @code{omp_initial_device} or
+@code{omp_invalid_device}. Note that for the host, the ICV can have two values
+and, hence, this routine might return either the value of the named constant
+@code{omp_initial_device} or the value returned by the
+@code{omp_get_initial_device} routine.
+
+The effect of running this routine in a @code{target} region is unspecified.
 
 @item @emph{C/C++}:
 @multitable @columnfractions .20 .80
@@ -1667,7 +1679,8 @@ Get the default device for target regions without device 
clause.
 @end multitable
 
 @item @emph{See also}:
-@ref{OMP_DEFAULT_DEVICE}, @ref{omp_set_default_device}
+@ref{OMP_DEFAULT_DEVICE}, @ref{omp_set_default_device},
+@ref{omp_get_initial_device}
 
 @item @emph{Reference}:
 @uref{https://www.openmp.org, OpenMP specification v4.5}, Section 3.2.30.
@@ -1681,6 +1694,8 @@ Get the default device for target regions without device 
clause.
 @item @emph{Description}:
 Returns the number of target devices.
 
+The effect of running this routine in a @code{target} region is unspecified.
+
 @item @emph{C/C++}:
 @multitable @columnfractions .20 .80
 @item @emph{Prototype}: @tab @code{int omp_get_num_devices(void);}
@@ -1702,9 +1717,9 @@ Returns the number of target devices.
 @table @asis
 @item @emph{Description}:
 This function returns a device number that represents the device that the
-current thread is executing on. For OpenMP 5.0, this must be equal to the
-value returned by the @code{omp_get_initial_device} function when called
-from the host.
+current thread is executing on. When called on the host, it returns
+the same value as returned by the @code{omp_get_initial_device} function
+as required since OpenMP 5.0.
 
 @item @emph{C/C++}
 @multitable @columnfractions .20 .80
@@ -1754,9 +1769,11 @@ their language-specific counterparts.
 @table @asis
 @item @emph{Description}:
 This function returns a device number that represents the host device.
-For OpenMP 5.1, this must be equal to the value returned by the
+Since OpenMP 5.1, this is equal to the value returned by the
 @code{omp_get_num_devices} function.

[gcc r15-2382] AVR: avr.cc - Fix a typo in a diagnostic.

[Georg-Johann Lay via Gcc-cvs]

https://gcc.gnu.org/g:3bc79863eb8483ab1a396e1d6131361a5195780f

commit r15-2382-g3bc79863eb8483ab1a396e1d6131361a5195780f
Author: Georg-Johann Lay 
Date:   Mon Jul 29 18:02:58 2024 +0200

AVR: avr.cc - Fix a typo in a diagnostic.

gcc/
* config/avr/avr.cc (avr_set_current_function): Fix typo in
error message.

Diff:
---
 gcc/config/avr/avr.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/config/avr/avr.cc b/gcc/config/avr/avr.cc
index dffb7e056bec..7229aac747bd 100644
--- a/gcc/config/avr/avr.cc
+++ b/gcc/config/avr/avr.cc
@@ -1540,7 +1540,7 @@ avr_set_current_function (tree decl)
{
  error_at (loc, "%qs function cannot have arguments", isr);
  if (TREE_CODE (TREE_TYPE (decl)) == METHOD_TYPE)
-   inform (loc, "method %qs has an inplicit % argument", name);
+   inform (loc, "method %qs has an implicit % argument", name);
}
 
   if (TREE_CODE (ret) != VOID_TYPE)

[gcc r15-2383] testsuite: make PR115277 test an execute one

[Sam James via Gcc-cvs]

https://gcc.gnu.org/g:ca255ca2760a5e6176031ea62a9c29c7bb92c212

commit r15-2383-gca255ca2760a5e6176031ea62a9c29c7bb92c212
Author: Sam James 
Date:   Mon Jul 29 16:47:09 2024 +0100

testsuite: make PR115277 test an execute one

PR middle-end/115277
* gcc.c-torture/compile/pr115277.c: Rename to...
* gcc.c-torture/execute/pr115277.c: ...this.

Diff:
---
 gcc/testsuite/gcc.c-torture/{compile => execute}/pr115277.c | 0
 1 file changed, 0 insertions(+), 0 deletions(-)

diff --git a/gcc/testsuite/gcc.c-torture/compile/pr115277.c 
b/gcc/testsuite/gcc.c-torture/execute/pr115277.c
similarity index 100%
rename from gcc/testsuite/gcc.c-torture/compile/pr115277.c
rename to gcc/testsuite/gcc.c-torture/execute/pr115277.c

[gcc r15-2384] Revert "PR116080: Fix tail call dejagnu checks"

[Andi Kleen via Gcc-cvs]

https://gcc.gnu.org/g:a7d6f7327e9211fbb4a800c06d00c4555dbffcec

commit r15-2384-ga7d6f7327e9211fbb4a800c06d00c4555dbffcec
Author: Andi Kleen 
Date:   Mon Jul 29 10:17:43 2024 -0700

Revert "PR116080: Fix tail call dejagnu checks"

This reverts commit ee41cd863b7c38ee3bc415ea7154954aa6facca3.

Diff:
---
 gcc/testsuite/g++.dg/musttail10.C |  2 +-
 gcc/testsuite/g++.dg/musttail6.C  |  2 +-
 gcc/testsuite/lib/target-supports.exp | 14 +++---
 3 files changed, 5 insertions(+), 13 deletions(-)

diff --git a/gcc/testsuite/g++.dg/musttail10.C 
b/gcc/testsuite/g++.dg/musttail10.C
index bd75affa2220..ff7fcc7d8755 100644
--- a/gcc/testsuite/g++.dg/musttail10.C
+++ b/gcc/testsuite/g++.dg/musttail10.C
@@ -8,7 +8,7 @@ double g() { [[gnu::musttail]] return f(); } /* { dg-error 
"cannot tail-cal
 
 template 
 __attribute__((noinline, noclone, noipa))
-T g1() { [[gnu::musttail]] return f(); } /* { dg-error "target is not able" 
"" { target { external_tail_call } } } */
+T g1() { [[gnu::musttail]] return f(); } /* { dg-error "target is not able" 
"" { target powerpc*-*-* } } */
 
 template 
 __attribute__((noinline, noclone, noipa))
diff --git a/gcc/testsuite/g++.dg/musttail6.C b/gcc/testsuite/g++.dg/musttail6.C
index 81f6d9f3ca77..5c6f69407ddb 100644
--- a/gcc/testsuite/g++.dg/musttail6.C
+++ b/gcc/testsuite/g++.dg/musttail6.C
@@ -1,6 +1,6 @@
 /* { dg-do compile { target { struct_tail_call } } } */
-/* { dg-require-effective-target external_tail_call } */
 /* A lot of architectures will not build this due to PR115606 and PR115607 */
+/* { dg-skip-if "powerpc does not support sibcall to templates" { powerpc*-*-* 
} } */
 /* { dg-options "-std=gnu++11" } */
 /* { dg-additional-options "-fdelayed-branch" { target sparc*-*-* } } */
 
diff --git a/gcc/testsuite/lib/target-supports.exp 
b/gcc/testsuite/lib/target-supports.exp
index 0a3946e82d4b..d368251ef9a4 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -12741,15 +12741,7 @@ proc check_effective_target_tail_call { } {
 return [check_no_messages_and_pattern tail_call ",SIBCALL" rtl-expand {
__attribute__((__noipa__)) void foo (void) { }
__attribute__((__noipa__)) void bar (void) { foo(); }
-} {-fdump-rtl-expand-all}] ;# The "SIBCALL" note requires a detailed dump.
-}
-
-# Return 1 if the target can perform tail-calls for externals
-proc check_effective_target_external_tail_call { } {
-return [check_no_messages_and_pattern tail_call ",SIBCALL" rtl-expand {
-   extern __attribute__((__noipa__)) void foo (void);
-   __attribute__((__noipa__)) void bar (void) { foo(); }
-} {-fdump-rtl-expand-all}] ;# The "SIBCALL" note requires a detailed dump.
+} {-O2 -fdump-rtl-expand-all}] ;# The "SIBCALL" note requires a detailed 
dump.
 }
 
 # Return 1 if the target can perform tail-call optimizations for structures
@@ -12759,9 +12751,9 @@ proc check_effective_target_struct_tail_call { } {
 return [check_no_messages_and_pattern tail_call ",SIBCALL" rtl-expand {
// C++
struct foo { int a, b; };
-   extern __attribute__((__noipa__)) struct foo foo (void);
+   __attribute__((__noipa__)) struct foo foo (void) { return {}; }
__attribute__((__noipa__)) struct foo bar (void) { return foo(); }
-} {-fdump-rtl-expand-all}] ;# The "SIBCALL" note requires a detailed dump.
+} {-O2 -fdump-rtl-expand-all}] ;# The "SIBCALL" note requires a detailed 
dump.
 }
 
 # Return 1 if the target's calling sequence or its ABI

[gcc r15-2385] gcc: xtensa: disable late-combine by default

[Max Filippov via Gcc-cvs]

https://gcc.gnu.org/g:9d5d6e61500411ea9043258e300d5b0f57e5c391

commit r15-2385-g9d5d6e61500411ea9043258e300d5b0f57e5c391
Author: Max Filippov 
Date:   Fri Jul 19 17:27:03 2024 -0700

gcc: xtensa: disable late-combine by default

gcc/
* config/xtensa/xtensa.cc (xtensa_option_override_after_change):
New function.
(TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE): Define as
xtensa_option_override_after_change.
(xtensa_option_override): Call
xtensa_option_override_after_change.

Diff:
---
 gcc/config/xtensa/xtensa.cc | 13 +
 1 file changed, 13 insertions(+)

diff --git a/gcc/config/xtensa/xtensa.cc b/gcc/config/xtensa/xtensa.cc
index d49d224466ad..10d964b51a96 100644
--- a/gcc/config/xtensa/xtensa.cc
+++ b/gcc/config/xtensa/xtensa.cc
@@ -114,6 +114,7 @@ struct GTY(()) machine_function
 };
 
 static void xtensa_option_override (void);
+static void xtensa_option_override_after_change (void);
 static enum internal_test map_test_to_internal_test (enum rtx_code);
 static rtx gen_int_relational (enum rtx_code, rtx, rtx);
 static rtx gen_float_relational (enum rtx_code, rtx, rtx);
@@ -303,6 +304,9 @@ static rtx xtensa_delegitimize_address (rtx);
 #undef TARGET_OPTION_OVERRIDE
 #define TARGET_OPTION_OVERRIDE xtensa_option_override
 
+#undef TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE
+#define TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE 
xtensa_option_override_after_change
+
 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA xtensa_output_addr_const_extra
 
@@ -2988,6 +2992,15 @@ xtensa_option_override (void)
  the define_insn_and_splits are fixed.  */
   if (!OPTION_SET_P (flag_late_combine_instructions))
 flag_late_combine_instructions = 0;
+
+  xtensa_option_override_after_change ();
+}
+
+static void
+xtensa_option_override_after_change (void)
+{
+  if (!OPTION_SET_P (flag_late_combine_instructions))
+flag_late_combine_instructions = 0;
 }
 
 /* Implement TARGET_HARD_REGNO_NREGS.  */

[gcc r15-2386] doc: Improve punctuation and grammar in -fdiagnostics-format docs

[Jonathan Wakely via Gcc-cvs]

https://gcc.gnu.org/g:dd2cc71e3898515a33970954d2bf7a4b67ea9790

commit r15-2386-gdd2cc71e3898515a33970954d2bf7a4b67ea9790
Author: Jonathan Wakely 
Date:   Fri Mar 15 12:58:56 2024 +

doc: Improve punctuation and grammar in -fdiagnostics-format docs

The hyphen can be misunderstood to mean "emitted to -" i.e. stdout.
Refer to both forms by name, rather than using "the former" for one and
referring to the other by name.

gcc/ChangeLog:

* doc/invoke.texi (Diagnostic Message Formatting Options):
Replace hyphen with a new sentence. Replace "the former" with
the actual value.

Diff:
---
 gcc/doc/invoke.texi | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index e495b1271fa7..86f9b5d1fe5e 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -5865,8 +5865,9 @@ named @file{@var{source}.sarif}, respectively.
 
 The @samp{json} format is a synonym for @samp{json-stderr}.
 The @samp{json-stderr} and @samp{json-file} formats are identical, apart from
-where the JSON is emitted to - with the former, the JSON is emitted to stderr,
-whereas with @samp{json-file} it is written to @file{@var{source}.gcc.json}.
+where the JSON is emitted to.  With @samp{json-stderr}, the JSON is emitted
+to stderr, whereas with @samp{json-file} it is written to
+@file{@var{source}.gcc.json}.
 
 The emitted JSON consists of a top-level JSON array containing JSON objects
 representing the diagnostics.

[gcc] Created branch 'meissner/heads/work174' in namespace 'refs/users'

[Michael Meissner via Gcc-cvs]

The branch 'meissner/heads/work174' was created in namespace 'refs/users' 
pointing to:

 dd2cc71e3898... doc: Improve punctuation and grammar in -fdiagnostics-forma

[gcc r15-2387] c++: generic lambda in default template argument [PR88313]

[Patrick Palka via Gcc-cvs]

https://gcc.gnu.org/g:72a7ab891ae0061841c4eb641ef6ab7719bf0369

commit r15-2387-g72a7ab891ae0061841c4eb641ef6ab7719bf0369
Author: Patrick Palka 
Date:   Mon Jul 29 16:37:19 2024 -0400

c++: generic lambda in default template argument [PR88313]

Here we're rejecting the generic lambda inside the default template
argument ultimately because auto_is_implicit_function_template_parm_p
doesn't get set during parsing of the lambda's parameter list, due
to the !processing_template_parmlist restriction.  But when parsing a
lambda parameter list we should always set that flag regardless of where
the lambda appears.  This patch makes sure of this via a local lambda_p
flag.

PR c++/88313

gcc/cp/ChangeLog:

* parser.cc (cp_parser_lambda_declarator_opt): Pass
lambda_p=true to cp_parser_parameter_declaration_clause.
(cp_parser_direct_declarator): Pass lambda_p=false to
to cp_parser_parameter_declaration_clause.
(cp_parser_parameter_declaration_clause): Add bool lambda_p
parameter.  Consider lambda_p instead of current_class_type
when setting parser->auto_is_implicit_function_template_parm_p.
Don't consider processing_template_parmlist.
(cp_parser_requirement_parameter_list): Pass lambda_p=false
to cp_parser_parameter_declaration_clause.

gcc/testsuite/ChangeLog:

* g++.dg/cpp2a/lambda-targ6.C: New test.

Reviewed-by: Jason Merrill 

Diff:
---
 gcc/cp/parser.cc  | 34 ++-
 gcc/testsuite/g++.dg/cpp2a/lambda-targ6.C | 15 ++
 2 files changed, 35 insertions(+), 14 deletions(-)

diff --git a/gcc/cp/parser.cc b/gcc/cp/parser.cc
index f79736c17ac6..e46cdfd20e19 100644
--- a/gcc/cp/parser.cc
+++ b/gcc/cp/parser.cc
@@ -2600,7 +2600,7 @@ static tree cp_parser_type_id_1
 static void cp_parser_type_specifier_seq
   (cp_parser *, cp_parser_flags, bool, bool, cp_decl_specifier_seq *);
 static tree cp_parser_parameter_declaration_clause
-  (cp_parser *, cp_parser_flags);
+  (cp_parser *, cp_parser_flags, bool);
 static tree cp_parser_parameter_declaration_list
   (cp_parser *, cp_parser_flags, auto_vec *);
 static cp_parameter_declarator *cp_parser_parameter_declaration
@@ -11889,7 +11889,7 @@ cp_parser_lambda_declarator_opt (cp_parser* parser, 
tree lambda_expr)
   /* Parse parameters.  */
   param_list
= cp_parser_parameter_declaration_clause
-   (parser, CP_PARSER_FLAGS_TYPENAME_OPTIONAL);
+   (parser, CP_PARSER_FLAGS_TYPENAME_OPTIONAL, /*lambda_p=*/true);
 
   /* Default arguments shall not be specified in the
 parameter-declaration-clause of a lambda-declarator.  */
@@ -24097,7 +24097,8 @@ cp_parser_direct_declarator (cp_parser* parser,
 
  /* Parse the parameter-declaration-clause.  */
  params
-   = cp_parser_parameter_declaration_clause (parser, flags);
+   = cp_parser_parameter_declaration_clause (parser, flags,
+ /*lambda_p=*/false);
  const location_t parens_end
= cp_lexer_peek_token (parser->lexer)->location;
 
@@ -25444,13 +25445,17 @@ function_being_declared_is_template_p (cp_parser* 
parser)
 
The parser flags FLAGS is used to control type-specifier parsing.
 
+   LAMBDA_P is true if this is the parameter-declaration-clause of
+   a lambda-declarator.
+
Returns a representation for the parameter declarations.  A return
value of NULL indicates a parameter-declaration-clause consisting
only of an ellipsis.  */
 
 static tree
 cp_parser_parameter_declaration_clause (cp_parser* parser,
-   cp_parser_flags flags)
+   cp_parser_flags flags,
+   bool lambda_p)
 {
   tree parameters;
   cp_token *token;
@@ -25459,15 +25464,15 @@ cp_parser_parameter_declaration_clause (cp_parser* 
parser,
   auto cleanup = make_temp_override
 (parser->auto_is_implicit_function_template_parm_p);
 
-  if (!processing_specialization
-  && !processing_template_parmlist
-  && !processing_explicit_instantiation
-  /* default_arg_ok_p tracks whether this is a parameter-clause for an
- actual function or a random abstract declarator.  */
-  && parser->default_arg_ok_p)
-if (!current_function_decl
-   || (current_class_type && LAMBDA_TYPE_P (current_class_type)))
-  parser->auto_is_implicit_function_template_parm_p = true;
+  if (lambda_p
+  || (!processing_specialization
+ && !processing_template_parmlist
+ && !processing_explicit_instantiation
+ /* default_arg_ok_p tracks whether this is a parameter-clause for an
+actual function or a random abstract declarator.  */
+ && parser->default_arg_ok_p
+  

[gcc(refs/users/meissner/heads/work174)] Add ChangeLog.meissner and REVISION.

[Michael Meissner via Libstdc++-cvs]

https://gcc.gnu.org/g:82a5c795fd715e4a04dca8b63e7de018cae33821

commit 82a5c795fd715e4a04dca8b63e7de018cae33821
Author: Michael Meissner 
Date:   Mon Jul 29 16:28:04 2024 -0400

Add ChangeLog.meissner and REVISION.

2024-07-29  Michael Meissner  

gcc/

* REVISION: New file for branch.
* ChangeLog.meissner: New file.

gcc/c-family/

* ChangeLog.meissner: New file.

gcc/c/

* ChangeLog.meissner: New file.

gcc/cp/

* ChangeLog.meissner: New file.

gcc/fortran/

* ChangeLog.meissner: New file.

gcc/testsuite/

* ChangeLog.meissner: New file.

libgcc/

* ChangeLog.meissner: New file.

Diff:
---
 gcc/ChangeLog.meissner   | 6 ++
 gcc/REVISION | 1 +
 gcc/c-family/ChangeLog.meissner  | 6 ++
 gcc/c/ChangeLog.meissner | 6 ++
 gcc/cp/ChangeLog.meissner| 6 ++
 gcc/fortran/ChangeLog.meissner   | 6 ++
 gcc/testsuite/ChangeLog.meissner | 6 ++
 libgcc/ChangeLog.meissner| 6 ++
 libstdc++-v3/ChangeLog.meissner  | 6 ++
 9 files changed, 49 insertions(+)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
new file mode 100644
index ..65c296e69433
--- /dev/null
+++ b/gcc/ChangeLog.meissner
@@ -0,0 +1,6 @@
+ Branch work174, baseline 
+
+2024-07-29   Michael Meissner  
+
+   Clone branch
+
diff --git a/gcc/REVISION b/gcc/REVISION
new file mode 100644
index ..413941b052d0
--- /dev/null
+++ b/gcc/REVISION
@@ -0,0 +1 @@
+work174 branch
diff --git a/gcc/c-family/ChangeLog.meissner b/gcc/c-family/ChangeLog.meissner
new file mode 100644
index ..65c296e69433
--- /dev/null
+++ b/gcc/c-family/ChangeLog.meissner
@@ -0,0 +1,6 @@
+ Branch work174, baseline 
+
+2024-07-29   Michael Meissner  
+
+   Clone branch
+
diff --git a/gcc/c/ChangeLog.meissner b/gcc/c/ChangeLog.meissner
new file mode 100644
index ..65c296e69433
--- /dev/null
+++ b/gcc/c/ChangeLog.meissner
@@ -0,0 +1,6 @@
+ Branch work174, baseline 
+
+2024-07-29   Michael Meissner  
+
+   Clone branch
+
diff --git a/gcc/cp/ChangeLog.meissner b/gcc/cp/ChangeLog.meissner
new file mode 100644
index ..65c296e69433
--- /dev/null
+++ b/gcc/cp/ChangeLog.meissner
@@ -0,0 +1,6 @@
+ Branch work174, baseline 
+
+2024-07-29   Michael Meissner  
+
+   Clone branch
+
diff --git a/gcc/fortran/ChangeLog.meissner b/gcc/fortran/ChangeLog.meissner
new file mode 100644
index ..65c296e69433
--- /dev/null
+++ b/gcc/fortran/ChangeLog.meissner
@@ -0,0 +1,6 @@
+ Branch work174, baseline 
+
+2024-07-29   Michael Meissner  
+
+   Clone branch
+
diff --git a/gcc/testsuite/ChangeLog.meissner b/gcc/testsuite/ChangeLog.meissner
new file mode 100644
index ..65c296e69433
--- /dev/null
+++ b/gcc/testsuite/ChangeLog.meissner
@@ -0,0 +1,6 @@
+ Branch work174, baseline 
+
+2024-07-29   Michael Meissner  
+
+   Clone branch
+
diff --git a/libgcc/ChangeLog.meissner b/libgcc/ChangeLog.meissner
new file mode 100644
index ..65c296e69433
--- /dev/null
+++ b/libgcc/ChangeLog.meissner
@@ -0,0 +1,6 @@
+ Branch work174, baseline 
+
+2024-07-29   Michael Meissner  
+
+   Clone branch
+
diff --git a/libstdc++-v3/ChangeLog.meissner b/libstdc++-v3/ChangeLog.meissner
new file mode 100644
index ..65c296e69433
--- /dev/null
+++ b/libstdc++-v3/ChangeLog.meissner
@@ -0,0 +1,6 @@
+ Branch work174, baseline 
+
+2024-07-29   Michael Meissner  
+
+   Clone branch
+

[gcc] Created branch 'meissner/heads/work174-dmf' in namespace 'refs/users'

[Michael Meissner via Gcc-cvs]

The branch 'meissner/heads/work174-dmf' was created in namespace 'refs/users' 
pointing to:

 82a5c795fd71... Add ChangeLog.meissner and REVISION.

[gcc(refs/users/meissner/heads/work174-dmf)] Add ChangeLog.dmf and update REVISION.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:ab0407a87efb9442e73afaec8490c0aa894da99f

commit ab0407a87efb9442e73afaec8490c0aa894da99f
Author: Michael Meissner 
Date:   Mon Jul 29 16:38:35 2024 -0400

Add ChangeLog.dmf and update REVISION.

2024-07-29  Michael Meissner  

gcc/

* ChangeLog.dmf: New file for branch.
* REVISION: Update.

Diff:
---
 gcc/ChangeLog.dmf | 6 ++
 gcc/REVISION  | 2 +-
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/gcc/ChangeLog.dmf b/gcc/ChangeLog.dmf
new file mode 100644
index ..8b10eface864
--- /dev/null
+++ b/gcc/ChangeLog.dmf
@@ -0,0 +1,6 @@
+ Branch work174-dmf, baseline 
+
+2024-07-29   Michael Meissner  
+
+   Clone branch
+
diff --git a/gcc/REVISION b/gcc/REVISION
index 413941b052d0..996d497cf07a 100644
--- a/gcc/REVISION
+++ b/gcc/REVISION
@@ -1 +1 @@
-work174 branch
+work174-dmf branch

[gcc] Created branch 'meissner/heads/work174-vpair' in namespace 'refs/users'

[Michael Meissner via Gcc-cvs]

The branch 'meissner/heads/work174-vpair' was created in namespace 'refs/users' 
pointing to:

 82a5c795fd71... Add ChangeLog.meissner and REVISION.

[gcc(refs/users/meissner/heads/work174-vpair)] Add ChangeLog.vpair and update REVISION.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:621dc107566d596088f3635b11648e0e23616b10

commit 621dc107566d596088f3635b11648e0e23616b10
Author: Michael Meissner 
Date:   Mon Jul 29 16:39:27 2024 -0400

Add ChangeLog.vpair and update REVISION.

2024-07-29  Michael Meissner  

gcc/

* ChangeLog.vpair: New file for branch.
* REVISION: Update.

Diff:
---
 gcc/ChangeLog.vpair | 6 ++
 gcc/REVISION| 2 +-
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/gcc/ChangeLog.vpair b/gcc/ChangeLog.vpair
new file mode 100644
index ..7867e637d8f4
--- /dev/null
+++ b/gcc/ChangeLog.vpair
@@ -0,0 +1,6 @@
+ Branch work174-vpair, baseline 
+
+2024-07-29   Michael Meissner  
+
+   Clone branch
+
diff --git a/gcc/REVISION b/gcc/REVISION
index 413941b052d0..5360dc97f7de 100644
--- a/gcc/REVISION
+++ b/gcc/REVISION
@@ -1 +1 @@
-work174 branch
+work174-vpair branch

[gcc] Created branch 'meissner/heads/work174-tar' in namespace 'refs/users'

[Michael Meissner via Gcc-cvs]

The branch 'meissner/heads/work174-tar' was created in namespace 'refs/users' 
pointing to:

 82a5c795fd71... Add ChangeLog.meissner and REVISION.

[gcc(refs/users/meissner/heads/work174-tar)] Add ChangeLog.tar and update REVISION.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:134e004f00358d070d87a40751adff56ceb2a76c

commit 134e004f00358d070d87a40751adff56ceb2a76c
Author: Michael Meissner 
Date:   Mon Jul 29 16:40:26 2024 -0400

Add ChangeLog.tar and update REVISION.

2024-07-29  Michael Meissner  

gcc/

* ChangeLog.tar: New file for branch.
* REVISION: Update.

Diff:
---
 gcc/ChangeLog.tar | 6 ++
 gcc/REVISION  | 2 +-
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/gcc/ChangeLog.tar b/gcc/ChangeLog.tar
new file mode 100644
index ..3433e69ba6b5
--- /dev/null
+++ b/gcc/ChangeLog.tar
@@ -0,0 +1,6 @@
+ Branch work174-tar, baseline 
+
+2024-07-29   Michael Meissner  
+
+   Clone branch
+
diff --git a/gcc/REVISION b/gcc/REVISION
index 413941b052d0..2c76bc5f8f6d 100644
--- a/gcc/REVISION
+++ b/gcc/REVISION
@@ -1 +1 @@
-work174 branch
+work174-tar branch

[gcc] Created branch 'meissner/heads/work174-bugs' in namespace 'refs/users'

[Michael Meissner via Gcc-cvs]

The branch 'meissner/heads/work174-bugs' was created in namespace 'refs/users' 
pointing to:

 82a5c795fd71... Add ChangeLog.meissner and REVISION.

[gcc(refs/users/meissner/heads/work174-bugs)] Add ChangeLog.bugs and update REVISION.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:eb5e56965437b34344b679e6b6dab6c5d934867c

commit eb5e56965437b34344b679e6b6dab6c5d934867c
Author: Michael Meissner 
Date:   Mon Jul 29 16:41:15 2024 -0400

Add ChangeLog.bugs and update REVISION.

2024-07-29  Michael Meissner  

gcc/

* ChangeLog.bugs: New file for branch.
* REVISION: Update.

Diff:
---
 gcc/ChangeLog.bugs | 6 ++
 gcc/REVISION   | 2 +-
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/gcc/ChangeLog.bugs b/gcc/ChangeLog.bugs
new file mode 100644
index ..13c3d901068f
--- /dev/null
+++ b/gcc/ChangeLog.bugs
@@ -0,0 +1,6 @@
+ Branch work174-bugs, baseline 
+
+2024-07-29   Michael Meissner  
+
+   Clone branch
+
diff --git a/gcc/REVISION b/gcc/REVISION
index 413941b052d0..06f7156b252a 100644
--- a/gcc/REVISION
+++ b/gcc/REVISION
@@ -1 +1 @@
-work174 branch
+work174-bugs branch

[gcc] Created branch 'meissner/heads/work174-test' in namespace 'refs/users'

[Michael Meissner via Gcc-cvs]

The branch 'meissner/heads/work174-test' was created in namespace 'refs/users' 
pointing to:

 82a5c795fd71... Add ChangeLog.meissner and REVISION.

[gcc(refs/users/meissner/heads/work174-test)] Add ChangeLog.test and update REVISION.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:6675d319eb77722cf6f288619243e0a4ba8970ce

commit 6675d319eb77722cf6f288619243e0a4ba8970ce
Author: Michael Meissner 
Date:   Mon Jul 29 16:42:06 2024 -0400

Add ChangeLog.test and update REVISION.

2024-07-29  Michael Meissner  

gcc/

* ChangeLog.test: New file for branch.
* REVISION: Update.

Diff:
---
 gcc/ChangeLog.test | 6 ++
 gcc/REVISION   | 2 +-
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/gcc/ChangeLog.test b/gcc/ChangeLog.test
new file mode 100644
index ..56e792180a72
--- /dev/null
+++ b/gcc/ChangeLog.test
@@ -0,0 +1,6 @@
+ Branch work174-test, baseline 
+
+2024-07-29   Michael Meissner  
+
+   Clone branch
+
diff --git a/gcc/REVISION b/gcc/REVISION
index 413941b052d0..e81b8c44fdcd 100644
--- a/gcc/REVISION
+++ b/gcc/REVISION
@@ -1 +1 @@
-work174 branch
+work174-test branch

[gcc] Created branch 'meissner/heads/work174-orig' in namespace 'refs/users'

[Michael Meissner via Gcc-cvs]

The branch 'meissner/heads/work174-orig' was created in namespace 'refs/users' 
pointing to:

 dd2cc71e3898... doc: Improve punctuation and grammar in -fdiagnostics-forma

[gcc(refs/users/meissner/heads/work174-orig)] Add REVISION.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:7e5ceefec53e912ced1017e06c9328e0ac6f4546

commit 7e5ceefec53e912ced1017e06c9328e0ac6f4546
Author: Michael Meissner 
Date:   Mon Jul 29 16:43:08 2024 -0400

Add REVISION.

2024-07-29  Michael Meissner  

gcc/

* REVISION: New file for branch.

Diff:
---
 gcc/REVISION | 1 +
 1 file changed, 1 insertion(+)

diff --git a/gcc/REVISION b/gcc/REVISION
new file mode 100644
index ..f83b29522d08
--- /dev/null
+++ b/gcc/REVISION
@@ -0,0 +1 @@
+work174-orig branch

[gcc r15-2388] testsuite: fix PR111613 test

[Sam James via Gcc-cvs]

https://gcc.gnu.org/g:5e5d7a88932b132437069f716160f8b20862890b

commit r15-2388-g5e5d7a88932b132437069f716160f8b20862890b
Author: Sam James 
Date:   Mon Jul 29 21:47:16 2024 +0100

testsuite: fix PR111613 test

PR ipa/111613
* gcc.c-torture/pr111613.c: Rename to..
* gcc.c-torture/execute/pr111613.c: ...this.

Diff:
---
 gcc/testsuite/gcc.c-torture/{ => execute}/pr111613.c | 0
 1 file changed, 0 insertions(+), 0 deletions(-)

diff --git a/gcc/testsuite/gcc.c-torture/pr111613.c 
b/gcc/testsuite/gcc.c-torture/execute/pr111613.c
similarity index 100%
rename from gcc/testsuite/gcc.c-torture/pr111613.c
rename to gcc/testsuite/gcc.c-torture/execute/pr111613.c

[gcc r15-2389] Polish libstdc++ 'dg-final' action 'file-io-diff'

[Thomas Schwinge via Gcc-cvs]

https://gcc.gnu.org/g:0544db1a4f8f250edb7f25eb0fa4dcfd569ec805

commit r15-2389-g0544db1a4f8f250edb7f25eb0fa4dcfd569ec805
Author: Thomas Schwinge 
Date:   Mon Jul 29 13:32:36 2024 +0200

Polish libstdc++ 'dg-final' action 'file-io-diff'

Follow-up to recent commit 515da03a838db05443ebcc4c543a405bed764188
"libstdc++: Add file-io-diff to replace @diff@ markup in I/O tests".

Currently, if a 'dg-final' action 'file-io-diff' passes, we print nothing
(should: 'PASS: [...]'), but if it fails, we just print: 'FAIL: files 
differ',
for example ('*.log' file):

[...]
FAIL: 27_io/basic_ostream/inserters_other/wchar_t/2.cc  -std=gnu++17 
(test for excess errors)
[...]
UNRESOLVED: 27_io/basic_ostream/inserters_other/wchar_t/2.cc  
-std=gnu++17 compilation failed to produce executable
diff: wostream_inserter_other_in.txt: No such file or directory
diff: wostream_inserter_other_out.txt: No such file or directory
FAIL: files differ
diff: wostream_inserter_other_in.txt: No such file or directory
diff: wostream_inserter_other_out.txt: No such file or directory

When later the '*.sum' files get sorted, these 'FAIL: files differ' 
instances
aren't grouped anymore with the other test cases' results, but they appear 
en
bloc, lexically sorted between ('e[...]' and 's[...]'), for example:

[...]
PASS: ext/vstring/types/23767.cc  -std=gnu++17 (test for excess errors)
FAIL: files differ
FAIL: files differ
FAIL: files differ
PASS: special_functions/01_assoc_laguerre/check_nan.cc  -std=gnu++17 
(test for excess errors)
[...]

Also, we shouldn't emit the actual 'diff' into the '*.sum' file, but just 
into
the '*.log* file, and there's no need for 'spawn'/'expect', as we're not
matching any specific messages.

libstdc++-v3/
* testsuite/lib/libstdc++.exp (file-io-diff): Polish.

Diff:
---
 libstdc++-v3/testsuite/lib/libstdc++.exp | 19 +++
 1 file changed, 11 insertions(+), 8 deletions(-)

diff --git a/libstdc++-v3/testsuite/lib/libstdc++.exp 
b/libstdc++-v3/testsuite/lib/libstdc++.exp
index c11e752ecfb1..18331c80bc27 100644
--- a/libstdc++-v3/testsuite/lib/libstdc++.exp
+++ b/libstdc++-v3/testsuite/lib/libstdc++.exp
@@ -1671,6 +1671,8 @@ if { [info exists env(GCC_RUNTEST_PARALLELIZE_DIR)] \
 
 }
 
+# Utility functions, invoked via dg-final.
+
 # Compare output file written by test to expected result.
 # With two arguments the comparison is done via 'diff arg1 arg2'.
 # With one argument the comparison is done via 'diff arg1.tst arg1.txt'.
@@ -1682,6 +1684,10 @@ proc file-io-diff { args } {
 if { $nargs > 2 } {
error "too many arguments to file-io-diff"
 }
+
+set testcase [testname-for-summary]
+set description "$testcase file-io-diff $args"
+
 if { $nargs == 1 } {
set file1 [lindex $args 0]
set file2 "${file1}.txt"
@@ -1691,14 +1697,11 @@ proc file-io-diff { args } {
set file2 [lindex $args 1]
 }
 
-spawn -noecho diff -u $file1 $file2
-expect {
-  -re ".+" {
-   set msg "files differ\n"
-   append msg $expect_out(0,string)
-   fail $msg
-   exp_continue
-  }
+if { [catch { exec diff -u $file1 $file2 } msg] } {
+   fail $description
+   verbose -log "'diff':\n$msg"
+} else {
+   pass $description
 }
 return
 }

[gcc r15-2390] [target/116104] Fix test guarding UINTVAL to extract shift count

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:5ab9a351247a551c47b0ab9d8e8b907223e7faf6

commit r15-2390-g5ab9a351247a551c47b0ab9d8e8b907223e7faf6
Author: Jeff Law 
Date:   Mon Jul 29 16:17:25 2024 -0600

[target/116104] Fix test guarding UINTVAL to extract shift count

Minor oversight in the ext-dce bits.  If the shift count is a constant 
vector,
then we shouldn't be extracting values with [U]INTVAL.  We guarded that test
with CONSTANT_P, when it should have been CONSTANT_INT_P.

Shows up on gcn, but I wouldn't be terribly surprised if it could be 
triggered
elsewhere.

Verified the testcase compiles on gcn.  Haven't done a libgcc build for gcn
though.  Also verified x86 bootstraps and regression tests cleanly.

Pushing to the trunk.

PR target/116104
gcc/
* ext-dce.cc (carry_backpropagate): Fix test guarding UINTVAL
extraction of shift count.

Diff:
---
 gcc/ext-dce.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/ext-dce.cc b/gcc/ext-dce.cc
index 14f163a01d63..f7b0eb114180 100644
--- a/gcc/ext-dce.cc
+++ b/gcc/ext-dce.cc
@@ -493,7 +493,7 @@ carry_backpropagate (unsigned HOST_WIDE_INT mask, enum 
rtx_code code, rtx x)
 /* We propagate for the shifted operand, but not the shift
count.  The count is handled specially.  */
 case ASHIFT:
-  if (CONSTANT_P (XEXP (x, 1))
+  if (CONST_INT_P (XEXP (x, 1))
  && known_lt (UINTVAL (XEXP (x, 1)), GET_MODE_BITSIZE (mode)))
return (HOST_WIDE_INT)mask >> INTVAL (XEXP (x, 1));
   return (2ULL << floor_log2 (mask)) - 1;

[gcc/aoliva/heads/testbase] (170 commits) [5/n][PR rtl-optimization/115877] Fix handling of input/out

[Alexandre Oliva via Gcc-cvs]

The branch 'aoliva/heads/testbase' was updated to point to:

 ad642d2c9506... [5/n][PR rtl-optimization/115877] Fix handling of input/out

It previously pointed to:

 bf8e80f9d164... [i386] adjust flag_omit_frame_pointer in a single function 

Diff:

Summary of changes (added commits):
---

  ad642d2... [5/n][PR rtl-optimization/115877] Fix handling of input/out (*)
  ad65caa... [powerpc] [testsuite] reorder dg directives [PR106069] (*)
  7c5a9bf... c++/coroutines: correct passing *this to promise type [PR10 (*)
  5d2115b... RISC-V: Implement the .SAT_TRUNC for scalar (*)
  d1b2554... Daily bump. (*)
  efcbe7b... Fix handling of ICF_NOVOPS in ipa-modref (*)
  6f81b7f... c++: Some cp-tree.def comment fixes (*)
  1407477... Fix modref's iteraction with store merging (*)
  05f0e9e... Add -mcpu=power11 support. (*)
  ab7c0ae... [4/n][PR rtl-optimization/115877] Correct SUBREG handling i (*)
  cf8ffc5... Fix modref_eaf_analysis::analyze_ssa_name handling of value (*)
  391f46f... Fix accounting of offsets in unadjusted_ptr_and_unit_offset (*)
  0d19fbc... Compare loop bounds in ipa-icf (*)
  34f33ea... rtl-ssa: Avoid using a stale splay tree root [PR116009] (*)
  e62988b... rtl-ssa: Add debug routines for def_splay_tree (*)
  ebde0cc... aarch64: Tighten aarch64_simd_mem_operand_p [PR115969] (*)
  88d1619... [NFC][PR rtl-optimization/115877] Avoid setting irrelevant  (*)
  a8e61cd... Fix hash of WIDEN_*_EXPR (*)
  1e32a8b... constify inchash (*)
  9d6... Fix Rejects allocatable coarray passed as a dummy argument  (*)
  0c5c0c9... AArch64: implement TARGET_VECTORIZE_CONDITIONAL_OPERATION_I (*)
  af792f0... middle-end: Implement conditonal store vectorizer pattern [ (*)
  913bab2... testsuite: powerpc: fix dg-do run typo (*)
  4ab19e4... RISC-V: Rearrange the test helper files for vector .SAT_* (*)
  3260665... Daily bump. (*)
  838999b... Fortran: Fix regression caused by r14-10477 [PR59104] (*)
  9d8ef27... [PR rtl-optimization/115877][2/n] Improve liveness computat (*)
  91e468b... [PR rtl-optimization/115877] Fix livein computation for ext (*)
  80c3733... gcc: stop adding -fno-common for checking builds (*)
  58b78cf... SH: Fix outage caused by recently added 2nd combine pass af (*)
  6d811c1... Daily bump. (*)
  1824caa... Require bitint575 for pr116003.c (*)
  4a46ba2... Revert "Add documentation for musttail attribute" (*)
  8805ad2... Revert "Add tests for C/C++ musttail attributes" (*)
  53660b1... Revert "C: Implement musttail attribute for returns" (*)
  ff6994e... Revert "C++: Support clang compatible [[musttail]] (PR83324 (*)
  493c555... Output CodeView function information (*)
  7357ba2... Add bitint to options for testcase (*)
  8e3fef3... doc: Remove documentation of two obsolete spec strings (*)
  e0d997e... Avoid undefined behaviour in build_option_suggestions (*)
  56f824c... Add documentation for musttail attribute (*)
  37c4703... Add tests for C/C++ musttail attributes (*)
  7db47f7... C: Implement musttail attribute for returns (*)
  59dd1d7... C++: Support clang compatible [[musttail]] (PR83324) (*)
  5c4c1fe... Add a musttail generic attribute to the c-attribs table (*)
  390c3e4... LoongArch: Organize the code related to split move and merg (*)
  8d6498f... Daily bump. (*)
  01c095a... Check for SSA_NAME not in the IL yet. (*)
  a95c191... libgomp: Document 'GOMP_teams4' (*)
  f911994... GCN: Honor OpenMP 5.1 'num_teams' lower bound (*)
  3850048... Rewrite usage comment at the top of 'gcc/passes.def' (*)
  348d890... Treat boolean vector elements as 0/-1 [PR115406] (*)
  ebdad26... arm: Update fp16-aapcs-[24].c after insn_propagation patch (*)
  2ee70c9... c++: xobj fn call without obj [PR115783] (*)
  9116490... AVR: Support new built-in function __builtin_avr_mask1. (*)
  8d6994f... libgomp: Remove bogus warnings from privatized-ref-2.f90. (*)
  c93be16... Fortran: character array constructor with >= 4 constant ele (*)
  b2f47a5... rs6000: Catch unsupported ABI errors when using -mrop-prote (*)
  58a9f3d... c++: add fixed testcase [PR109464] (*)
  8fbc386... bpf: create modifier for mem operand for xchg and cmpxchg (*)
  cea6473... c++: Add [dcl.init.aggr] examples to testsuite (*)
  a589d3b... Close GCC 11 branch (*)
  0f8261e... c++: Hash placeholder constraint in ctp_hasher (*)
  02cc849... Match: Only allow single use of MIN_EXPR for SAT_TRUNC form (*)
  e20ea6b... Daily bump. (*)
  9846b09... libatomic: Handle AVX+CX16 ZHAOXIN like Intel for 16b atomi (*)
  9690fb3... c++: implement DR1363 and DR1496 for __is_trivial [PR85723] (*)
  248e853... libbacktrace: use __has_attribute for fallthrough (*)
  6962835... rs6000: Fix .machine cpu selection w/ altivec [PR97367] (*)
  c192376... rs6000, update effective target for tests builtins-10*.c an (*)
  f7d01e0... libatomic: Improve cpuid usage in __libat_feat1_init (*)
  1e60a6a... eh: ICE with std::initializer_list and ASan [PR115865] (*)
  5080840... Do not use caller-saved registers for COMDAT fun

[gcc/aoliva/heads/testme] (171 commits) [libstdc++] [testsuite] avoid async.cc loss of precision [P

[Alexandre Oliva via Gcc-cvs]

The branch 'aoliva/heads/testme' was updated to point to:

 9d90ad447ba1... [libstdc++] [testsuite] avoid async.cc loss of precision [P

It previously pointed to:

 110c93a4411d... [strub] adjust all at-calls type variants at once

Diff:

!!! WARNING: THE FOLLOWING COMMITS ARE NO LONGER ACCESSIBLE (LOST):
---

  110c93a... [strub] adjust all at-calls type variants at once


Summary of changes (added commits):
---

  9d90ad4... [libstdc++] [testsuite] avoid async.cc loss of precision [P
  ad642d2... [5/n][PR rtl-optimization/115877] Fix handling of input/out (*)
  ad65caa... [powerpc] [testsuite] reorder dg directives [PR106069] (*)
  7c5a9bf... c++/coroutines: correct passing *this to promise type [PR10 (*)
  5d2115b... RISC-V: Implement the .SAT_TRUNC for scalar (*)
  d1b2554... Daily bump. (*)
  efcbe7b... Fix handling of ICF_NOVOPS in ipa-modref (*)
  6f81b7f... c++: Some cp-tree.def comment fixes (*)
  1407477... Fix modref's iteraction with store merging (*)
  05f0e9e... Add -mcpu=power11 support. (*)
  ab7c0ae... [4/n][PR rtl-optimization/115877] Correct SUBREG handling i (*)
  cf8ffc5... Fix modref_eaf_analysis::analyze_ssa_name handling of value (*)
  391f46f... Fix accounting of offsets in unadjusted_ptr_and_unit_offset (*)
  0d19fbc... Compare loop bounds in ipa-icf (*)
  34f33ea... rtl-ssa: Avoid using a stale splay tree root [PR116009] (*)
  e62988b... rtl-ssa: Add debug routines for def_splay_tree (*)
  ebde0cc... aarch64: Tighten aarch64_simd_mem_operand_p [PR115969] (*)
  88d1619... [NFC][PR rtl-optimization/115877] Avoid setting irrelevant  (*)
  a8e61cd... Fix hash of WIDEN_*_EXPR (*)
  1e32a8b... constify inchash (*)
  9d6... Fix Rejects allocatable coarray passed as a dummy argument  (*)
  0c5c0c9... AArch64: implement TARGET_VECTORIZE_CONDITIONAL_OPERATION_I (*)
  af792f0... middle-end: Implement conditonal store vectorizer pattern [ (*)
  913bab2... testsuite: powerpc: fix dg-do run typo (*)
  4ab19e4... RISC-V: Rearrange the test helper files for vector .SAT_* (*)
  3260665... Daily bump. (*)
  838999b... Fortran: Fix regression caused by r14-10477 [PR59104] (*)
  9d8ef27... [PR rtl-optimization/115877][2/n] Improve liveness computat (*)
  91e468b... [PR rtl-optimization/115877] Fix livein computation for ext (*)
  80c3733... gcc: stop adding -fno-common for checking builds (*)
  58b78cf... SH: Fix outage caused by recently added 2nd combine pass af (*)
  6d811c1... Daily bump. (*)
  1824caa... Require bitint575 for pr116003.c (*)
  4a46ba2... Revert "Add documentation for musttail attribute" (*)
  8805ad2... Revert "Add tests for C/C++ musttail attributes" (*)
  53660b1... Revert "C: Implement musttail attribute for returns" (*)
  ff6994e... Revert "C++: Support clang compatible [[musttail]] (PR83324 (*)
  493c555... Output CodeView function information (*)
  7357ba2... Add bitint to options for testcase (*)
  8e3fef3... doc: Remove documentation of two obsolete spec strings (*)
  e0d997e... Avoid undefined behaviour in build_option_suggestions (*)
  56f824c... Add documentation for musttail attribute (*)
  37c4703... Add tests for C/C++ musttail attributes (*)
  7db47f7... C: Implement musttail attribute for returns (*)
  59dd1d7... C++: Support clang compatible [[musttail]] (PR83324) (*)
  5c4c1fe... Add a musttail generic attribute to the c-attribs table (*)
  390c3e4... LoongArch: Organize the code related to split move and merg (*)
  8d6498f... Daily bump. (*)
  01c095a... Check for SSA_NAME not in the IL yet. (*)
  a95c191... libgomp: Document 'GOMP_teams4' (*)
  f911994... GCN: Honor OpenMP 5.1 'num_teams' lower bound (*)
  3850048... Rewrite usage comment at the top of 'gcc/passes.def' (*)
  348d890... Treat boolean vector elements as 0/-1 [PR115406] (*)
  ebdad26... arm: Update fp16-aapcs-[24].c after insn_propagation patch (*)
  2ee70c9... c++: xobj fn call without obj [PR115783] (*)
  9116490... AVR: Support new built-in function __builtin_avr_mask1. (*)
  8d6994f... libgomp: Remove bogus warnings from privatized-ref-2.f90. (*)
  c93be16... Fortran: character array constructor with >= 4 constant ele (*)
  b2f47a5... rs6000: Catch unsupported ABI errors when using -mrop-prote (*)
  58a9f3d... c++: add fixed testcase [PR109464] (*)
  8fbc386... bpf: create modifier for mem operand for xchg and cmpxchg (*)
  cea6473... c++: Add [dcl.init.aggr] examples to testsuite (*)
  a589d3b... Close GCC 11 branch (*)
  0f8261e... c++: Hash placeholder constraint in ctp_hasher (*)
  02cc849... Match: Only allow single use of MIN_EXPR for SAT_TRUNC form (*)
  e20ea6b... Daily bump. (*)
  9846b09... libatomic: Handle AVX+CX16 ZHAOXIN like Intel for 16b atomi (*)
  9690fb3... c++: implement DR1363 and DR1496 for __is_trivial [PR85723] (*)
  248e853... libbacktrace: use __has_attribute for fallthrough (*)
  6962835... rs6000: Fix .machine cpu selection w/ altivec [PR97367] (*)
  c192376... rs60

[gcc(refs/users/aoliva/heads/testme)] [libstdc++] [testsuite] avoid async.cc loss of precision [PR91486]

[Alexandre Oliva via Libstdc++-cvs]

https://gcc.gnu.org/g:9d90ad447ba1872c8606e1b33b4545ceb40ee0d0

commit 9d90ad447ba1872c8606e1b33b4545ceb40ee0d0
Author: Alexandre Oliva 
Date:   Mon Jul 29 19:48:52 2024 -0300

[libstdc++] [testsuite] avoid async.cc loss of precision [PR91486]

When we get to test_pr91486_wait_until(), we're about 10s past the
float_steady_clock epoch.  This is enough for the 1s delta for the
timeout to come out slightly lower when the futex-less wait_until
converts the deadline from float_steady_clock to __clock_t.  So we may
wake up a little too early, and end up looping one extra time to sleep
for e.g. another 954ns until we hit the deadline.

Each iteration calls float_steady_clock::now(), bumping the call_count
that we VERIFY() at the end of the subtest.  Since we expect at most 3
calls, and we're going to have at the very least 3 on futex-less
targets (one in the test proper, one before wait_until_impl to compute
the deadline, and one after wait_until_impl to check whether the
deadline was hit), any such imprecision that causes an extra iteration
will reach 5 and cause the test to fail.

Initializing the epoch in the beginning of the test makes such
spurious fails due to loss of precision far less likely.  I don't
suppose allowing for an extra couple of calls would be desirable.

While at that, I'm annotating unused status variables as such.


for  libstdc++-v3/ChangeLog

PR libstdc++/91486
* testsuite/30_threads/async/async.cc
(test_pr91486_wait_for): Mark status as unused.
(test_pr91486_wait_until): Likewise.  Initialize epoch later.

Diff:
---
 libstdc++-v3/testsuite/30_threads/async/async.cc | 19 ---
 1 file changed, 16 insertions(+), 3 deletions(-)

diff --git a/libstdc++-v3/testsuite/30_threads/async/async.cc 
b/libstdc++-v3/testsuite/30_threads/async/async.cc
index 3b157ed9c568..2474d318d7b1 100644
--- a/libstdc++-v3/testsuite/30_threads/async/async.cc
+++ b/libstdc++-v3/testsuite/30_threads/async/async.cc
@@ -173,7 +173,7 @@ void test_pr91486_wait_for()
 
   std::chrono::duration const wait_time = std::chrono::seconds(1);
   auto const start_steady = chrono::steady_clock::now();
-  auto status = f1.wait_for(wait_time);
+  auto status __attribute__ ((__unused__)) = f1.wait_for(wait_time);
   auto const elapsed_steady = chrono::steady_clock::now() - start_steady;
 
   VERIFY( elapsed_steady >= std::chrono::seconds(1) );
@@ -209,7 +209,7 @@ struct float_steady_clock
   }
 };
 
-chrono::steady_clock::time_point float_steady_clock::epoch = 
chrono::steady_clock::now();
+chrono::steady_clock::time_point float_steady_clock::epoch;
 int float_steady_clock::call_count = 0;
 
 void test_pr91486_wait_until()
@@ -218,6 +218,19 @@ void test_pr91486_wait_until()
   std::this_thread::sleep_for(std::chrono::seconds(1));
 });
 
+  // When we don't _GLIBCXX_HAVE_LINUX_FUTEX, we use
+  // condition_variables, whose wait_until converts times using
+  // deltas, and if too much time has elapsed since we set the epoch
+  // during program initialization, say if the other tests took over
+  // 8s and we're unlucky with the numbers, we may lose enough
+  // precision from the 1s delta that we don't sleep until the
+  // deadline, and then we may loop more times than expected.  Each
+  // iteration will recompute the wait time from deadline -
+  // float_steady_clock::now(), and each such computation will bump
+  // float_steady_clock::call_count, so the call_count check below
+  // will fail spuriously.  Setting the epoch just before running this
+  // test makes this failure mode far less likely.
+  float_steady_clock::epoch = chrono::steady_clock::now();
   float_steady_clock::time_point const now = float_steady_clock::now();
 
   std::chrono::duration const wait_time = std::chrono::seconds(1);
@@ -225,7 +238,7 @@ void test_pr91486_wait_until()
   VERIFY( expire > now );
 
   auto const start_steady = chrono::steady_clock::now();
-  auto status = f1.wait_until(expire);
+  auto status __attribute__ ((__unused__)) = f1.wait_until(expire);
   auto const elapsed_steady = chrono::steady_clock::now() - start_steady;
 
   // This checks that we didn't come back too soon

[gcc(refs/users/meissner/heads/work173)] Use old arch code for power4-power6.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:e4d2106c7ef57a460688cdc959a61901684ddd9d

commit e4d2106c7ef57a460688cdc959a61901684ddd9d
Author: Michael Meissner 
Date:   Mon Jul 29 19:36:22 2024 -0400

Use old arch code for power4-power6.

2024-07-29  Michael Meissner  

gcc/

* config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Use 
original
code for _ARCH_PWR* if older than power7.

Diff:
---
 gcc/config/rs6000/rs6000-c.cc | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc
index 2ffaee165885..f3081414721b 100644
--- a/gcc/config/rs6000/rs6000-c.cc
+++ b/gcc/config/rs6000/rs6000-c.cc
@@ -422,11 +422,11 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT 
flags,
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PPC64");
   if ((flags & OPTION_MASK_MFCRF) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR4");
-  if ((arch_flags & ARCH_MASK_POWER4) != 0)
+  if ((flags & OPTION_MASK_POPCNTB) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5");
-  if ((arch_flags & ARCH_MASK_POWER5) != 0)
+  if ((flags & OPTION_MASK_FPRND) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5X");
-  if ((arch_flags & ARCH_MASK_POWER6) != 0)
+  if ((flags & OPTION_MASK_CMPB) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR6");
   if ((arch_flags & ARCH_MASK_POWER7) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR7");

[gcc(refs/users/meissner/heads/work173)] Update ChangeLog.*

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:ad2f2d3a58313501940554940c19854c8f57bef9

commit ad2f2d3a58313501940554940c19854c8f57bef9
Author: Michael Meissner 
Date:   Mon Jul 29 19:37:55 2024 -0400

Update ChangeLog.*

Diff:
---
 gcc/ChangeLog.meissner | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index a08f187b26cf..27a75f8891e2 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,5 +1,16 @@
  Branch work173, patch #14 
 
+Use old arch code for power4-power6.
+
+2024-07-29  Michael Meissner  
+
+gcc/
+
+   * config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Use original
+   code for _ARCH_PWR* if older than power7.
+
+ Branch work173, patch #14 
+
 Do not allow -mvsx to boost processor to power7.
 
 2024-07-25  Michael Meissner  

[gcc r15-2391] xtensa: Make use of std::swap where appropriate

[Max Filippov via Gcc-cvs]

https://gcc.gnu.org/g:56c4979dd8be40681f2724861fc41ae6135e1e78

commit r15-2391-g56c4979dd8be40681f2724861fc41ae6135e1e78
Author: Takayuki 'January June' Suwa 
Date:   Sun Jul 14 20:03:13 2024 +0900

xtensa: Make use of std::swap where appropriate

No functional changes.

gcc/ChangeLog:

* config/xtensa/xtensa.cc
(gen_int_relational, gen_float_relational): Replace tempvar-based
value-swapping codes with std::swap.
* config/xtensa/xtensa.md (movdi_internal, movdf_internal):
Ditto.

Diff:
---
 gcc/config/xtensa/xtensa.cc | 12 ++--
 gcc/config/xtensa/xtensa.md | 10 --
 2 files changed, 6 insertions(+), 16 deletions(-)

diff --git a/gcc/config/xtensa/xtensa.cc b/gcc/config/xtensa/xtensa.cc
index 10d964b51a96..772150c7fa22 100644
--- a/gcc/config/xtensa/xtensa.cc
+++ b/gcc/config/xtensa/xtensa.cc
@@ -794,11 +794,7 @@ gen_int_relational (enum rtx_code test_code, /* relational 
test (EQ, etc) */
 
 }
   else if (p_info->reverse_regs)
-{
-  rtx temp = cmp0;
-  cmp0 = cmp1;
-  cmp1 = temp;
-}
+std::swap (cmp0, cmp1);
 
   return gen_rtx_fmt_ee (invert ? reverse_condition (p_info->test_code)
: p_info->test_code,
@@ -842,11 +838,7 @@ gen_float_relational (enum rtx_code test_code, /* 
relational test (EQ, etc) */
 }
 
   if (reverse_regs)
-{
-  rtx temp = cmp0;
-  cmp0 = cmp1;
-  cmp1 = temp;
-}
+std::swap (cmp0, cmp1);
 
   brtmp = gen_rtx_REG (CCmode, FPCC_REGNUM);
   emit_insn (gen_fn (brtmp, cmp0, cmp1));
diff --git a/gcc/config/xtensa/xtensa.md b/gcc/config/xtensa/xtensa.md
index 8709ef6d7a7d..0fcbb0b7bc37 100644
--- a/gcc/config/xtensa/xtensa.md
+++ b/gcc/config/xtensa/xtensa.md
@@ -1215,9 +1215,8 @@
   xtensa_split_operand_pair (operands, SImode);
   if (reg_overlap_mentioned_p (operands[0], operands[3]))
 {
-  rtx tmp;
-  tmp = operands[0], operands[0] = operands[1], operands[1] = tmp;
-  tmp = operands[2], operands[2] = operands[3], operands[3] = tmp;
+  std::swap (operands[0], operands[1]);
+  std::swap (operands[2], operands[3]);
 }
 })
 
@@ -1562,9 +1561,8 @@
   xtensa_split_operand_pair (operands, SFmode);
   if (reg_overlap_mentioned_p (operands[0], operands[3]))
 {
-  rtx tmp;
-  tmp = operands[0], operands[0] = operands[1], operands[1] = tmp;
-  tmp = operands[2], operands[2] = operands[3], operands[3] = tmp;
+  std::swap (operands[0], operands[1]);
+  std::swap (operands[2], operands[3]);
 }
 })

[gcc r15-2392] xtensa: Make use of scaled [U]FLOAT/TRUNC.S instructions

[Max Filippov via Gcc-cvs]

https://gcc.gnu.org/g:f9c7775f58798a051b57356ad321b758a2ee837d

commit r15-2392-gf9c7775f58798a051b57356ad321b758a2ee837d
Author: Takayuki 'January June' Suwa 
Date:   Sun Jul 14 20:04:15 2024 +0900

xtensa: Make use of scaled [U]FLOAT/TRUNC.S instructions

[U]FLOAT.S machine instruction in Xtensa ISA, which converts an integer to
a hardware single-precision FP register, has the ability to divide the
result by power of two (0 to 15th).

Similarly, [U]TRUNC.S instruction, which truncates single-precision FP to
integer, can multiply the source value by power of two in advance, but
neither of these currently uses this function (always specified with 0th
power of two, i.e. a scaling factor of 1).

This patch unleashes the scaling ability of the above instructions.

 /* example */
 float test0(int a) {
   return a / 2.f;
 }
 float test1(unsigned int a) {
   return a / 32768.f;
 }
 int test2(float a) {
   return a * 2;
 }
 unsigned int test3(float a) {
   return a * 32768;
 }

 ;; before
 test0:
movi.n  a9, 0x3f
float.s f0, a2, 0
sllia9, a9, 24
wfr f1, a9
mul.s   f0, f0, f1
rfr a2, f0
ret.n
 test1:
movi.n  a9, 7
ufloat.sf0, a2, 0
sllia9, a9, 27
wfr f1, a9
mul.s   f0, f0, f1
rfr a2, f0
ret.n
 test2:
wfr f1, a2
add.s   f0, f1, f1
trunc.s a2, f0, 0
ret.n
 test3:
movi.n  a9, 0x47
sllia9, a9, 24
wfr f1, a2
wfr f2, a9
mul.s   f0, f1, f2
utrunc.sa2, f0, 0
ret.n

 ;; after
 test0:
float.s f0, a2, 1
rfr a2, f0
ret.n
 test1:
ufloat.sf0, a2, 15
rfr a2, f0
ret.n
 test2:
wfr f0, a2
trunc.s a2, f0, 1
ret.n
 test3:
wfr f0, a2
utrunc.sa2, f0, 15
ret.n

gcc/ChangeLog:

* config/xtensa/predicates.md
(fix_scaling_operand, float_scaling_operand): New predicates.
* config/xtensa/xtensa.md
(any_fix/m_fix/s_fix, any_float/m_float/s_float):
New code iterators and their attributes.
(fix_truncsfsi2): Change from "fix_truncsfsi2".
(*fix_truncsfsi2_2x, *fix_truncsfsi2_scaled):
New insn definitions.
(floatsisf2): Change from "floatsisf2".
(*floatsisf2_scaled): New insn definition.

Diff:
---
 gcc/config/xtensa/predicates.md | 20 ++
 gcc/config/xtensa/xtensa.md | 58 -
 2 files changed, 66 insertions(+), 12 deletions(-)

diff --git a/gcc/config/xtensa/predicates.md b/gcc/config/xtensa/predicates.md
index 19b9f4cd7efe..e676fa4fb95c 100644
--- a/gcc/config/xtensa/predicates.md
+++ b/gcc/config/xtensa/predicates.md
@@ -159,6 +159,26 @@
   return real_equal (CONST_DOUBLE_REAL_VALUE (op), &dconst1);
 })
 
+(define_predicate "fix_scaling_operand"
+  (match_code "const_double")
+{
+  REAL_VALUE_TYPE r = *CONST_DOUBLE_REAL_VALUE (op);
+  int exp = REAL_EXP (&r) - 1;
+
+  SET_REAL_EXP (&r, 1);
+  return real_equal (&r, &dconst1) && IN_RANGE (exp, 2, 15);
+})
+
+(define_predicate "float_scaling_operand"
+  (match_code "const_double")
+{
+  REAL_VALUE_TYPE r = *CONST_DOUBLE_REAL_VALUE (op);
+  int exp = REAL_EXP (&r) - 1;
+
+  SET_REAL_EXP (&r, 1);
+  return real_equal (&r, &dconst1) && IN_RANGE (-exp, 1, 15);
+})
+
 (define_predicate "fpmem_offset_operand"
   (and (match_code "const_int")
(match_test "xtensa_mem_offset (INTVAL (op), SFmode)")))
diff --git a/gcc/config/xtensa/xtensa.md b/gcc/config/xtensa/xtensa.md
index 0fcbb0b7bc37..376d0f755446 100644
--- a/gcc/config/xtensa/xtensa.md
+++ b/gcc/config/xtensa/xtensa.md
@@ -91,6 +91,18 @@
 ;; the same template.
 (define_mode_iterator SHI [SI HI])
 
+;; This iterator and attribute allow signed/unsigned FP truncations to be
+;; generated from one template.
+(define_code_iterator any_fix [fix unsigned_fix])
+(define_code_attr m_fix [(fix "trunc") (unsigned_fix "utrunc")])
+(define_code_attr s_fix [(fix "") (unsigned_fix "uns")])
+
+;; This iterator and attribute allow signed/unsigned FP conversions to be
+;; generated from one template.
+(define_code_iterator any_float [float unsigned_float])
+(define_code_attr m_float [(float "float") (unsigned_float "ufloat")])
+(define_code_attr s_float [(float "") (unsigned_float "uns")])
+
 
 ;; Attributes.
 
@@ -1132,38 +1144,60 @@
 
 ;; Conversions.
 
-(define_insn "fix_truncsfsi2"
+(define_insn "fix_truncsfsi

[gcc(refs/users/meissner/heads/work173)] Use old arch code for power4-power6 part 2.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:85a5bf5709ae03cd14f54497fa26e49cab383b1c

commit 85a5bf5709ae03cd14f54497fa26e49cab383b1c
Author: Michael Meissner 
Date:   Mon Jul 29 20:30:42 2024 -0400

Use old arch code for power4-power6 part 2.

2024-07-29  Michael Meissner  

gcc/

* config/rs6000/rs6000.cc (report_architecture_mismatch): Use old 
code
for power6 options.

Diff:
---
 gcc/config/rs6000/rs6000.cc | 15 +++
 1 file changed, 7 insertions(+), 8 deletions(-)

diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 6f9f3cce5582..abc682683852 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -3943,7 +3943,7 @@ rs6000_option_override_internal (bool global_init_p)
   /* Disable VSX and Altivec silently if the user switched cpus to power7 in a
  target attribute or pragma which automatically enables both options,
  unless the altivec ABI was set.  This is set by default for 64-bit, but
- not for 32-bit.  Don't move this before the above code using ignore_masks,
+ not for 32-bit.  Don't move this before report_architecture_mismatch
  since it can reset the cleared VSX/ALTIVEC flag again.  */
   if (main_target_opt && !main_target_opt->x_rs6000_altivec_abi)
 {
@@ -25359,12 +25359,7 @@ report_architecture_mismatch (void)
 {
   OPTION_MASK_VSX | OPTION_MASK_POPCNTD,
   ARCH_MASK_POWER7,
-  "cpu=power7" },
-
-{
-  OPTION_MASK_DFP | OPTION_MASK_CMPB,
-  ARCH_MASK_POWER6,
-  "cpu=power6"
+  "cpu=power7"
 },
   };
 
@@ -25395,7 +25390,11 @@ report_architecture_mismatch (void)
 
   /* The following old options are used in multiple processors, so silently
  enable the appropriate ISA options as previous GCC revisions did.  */
-  if (TARGET_FPRND)
+  if (TARGET_DFP)
+rs6000_isa_flags |= (ISA_2_5_MASKS_SERVER & ~ignore_masks);
+  else if (TARGET_CMPB)
+rs6000_isa_flags |= (ISA_2_5_MASKS_EMBEDDED & ~ignore_masks);
+  else if (TARGET_FPRND)
 rs6000_isa_flags |= (ISA_2_4_MASKS & ~ignore_masks);
   else if (TARGET_POPCNTB)
 rs6000_isa_flags |= (ISA_2_2_MASKS & ~ignore_masks);

[gcc(refs/users/meissner/heads/work173)] Update ChangeLog.*

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:8932f6f9903b7b155780e12f4485660fb3fcb442

commit 8932f6f9903b7b155780e12f4485660fb3fcb442
Author: Michael Meissner 
Date:   Mon Jul 29 20:31:40 2024 -0400

Update ChangeLog.*

Diff:
---
 gcc/ChangeLog.meissner | 13 -
 1 file changed, 12 insertions(+), 1 deletion(-)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index 27a75f8891e2..7e64f74af706 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,4 +1,15 @@
- Branch work173, patch #14 
+ Branch work173, patch #16 
+
+Use old arch code for power4-power6 part 2.
+
+2024-07-29  Michael Meissner  
+
+gcc/
+
+   * config/rs6000/rs6000.cc (report_architecture_mismatch): Use old code
+   for power6 options.
+
+ Branch work173, patch #15 
 
 Use old arch code for power4-power6.

[gcc r15-2394] i386: Add non-optimize prefetchi intrins

[Haochen Jiang via Gcc-cvs]

https://gcc.gnu.org/g:b4524c4430ba9771265bd9fc31e69a3f35dfe117

commit r15-2394-gb4524c4430ba9771265bd9fc31e69a3f35dfe117
Author: Haochen Jiang 
Date:   Thu Jul 25 16:16:05 2024 +0800

i386: Add non-optimize prefetchi intrins

Under -O0, with the "newly" introduced intrins, the variable will be
transformed as mem instead of the origin symbol_ref. The compiler will
then treat the operand as invalid and turn the operation into nop, which
is not expected. Use macro for non-optimize to keep the variable as
symbol_ref just as how prefetch intrin does.

gcc/ChangeLog:

* config/i386/prfchiintrin.h
(_m_prefetchit0): Add macro for non-optimized option.
(_m_prefetchit1): Ditto.

gcc/testsuite/ChangeLog:

* gcc.target/i386/prefetchi-1b.c: New test.

Diff:
---
 gcc/config/i386/prfchiintrin.h   |  9 +
 gcc/testsuite/gcc.target/i386/prefetchi-1b.c | 26 ++
 2 files changed, 35 insertions(+)

diff --git a/gcc/config/i386/prfchiintrin.h b/gcc/config/i386/prfchiintrin.h
index dfca89c7d169..d6580e504c04 100644
--- a/gcc/config/i386/prfchiintrin.h
+++ b/gcc/config/i386/prfchiintrin.h
@@ -37,6 +37,7 @@
 #define __DISABLE_PREFETCHI__
 #endif /* __PREFETCHI__ */
 
+#ifdef __OPTIMIZE__
 extern __inline void
 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
 _m_prefetchit0 (void* __P)
@@ -50,6 +51,14 @@ _m_prefetchit1 (void* __P)
 {
   __builtin_ia32_prefetchi (__P, 2);
 }
+#else
+#define _m_prefetchit0(P)  \
+  __builtin_ia32_prefetchi(P, 3);
+
+#define _m_prefetchit1(P)  \
+  __builtin_ia32_prefetchi(P, 2);
+
+#endif
 
 #ifdef __DISABLE_PREFETCHI__
 #undef __DISABLE_PREFETCHI__
diff --git a/gcc/testsuite/gcc.target/i386/prefetchi-1b.c 
b/gcc/testsuite/gcc.target/i386/prefetchi-1b.c
new file mode 100644
index ..93139554d3cd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/prefetchi-1b.c
@@ -0,0 +1,26 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-mprefetchi -O0" } */
+/* { dg-final { scan-assembler-times "\[ \\t\]+prefetchit0\[ 
\\t\]+bar\\(%rip\\)" 1 } } */
+/* { dg-final { scan-assembler-times "\[ \\t\]+prefetchit1\[ 
\\t\]+bar\\(%rip\\)" 1 } } */
+
+#include 
+
+int
+bar (int a)
+{
+  return a + 1;
+}
+
+int
+foo1 (int b)
+{
+  _m_prefetchit0 (bar);
+  return bar (b) + 1;
+}
+
+int
+foo2 (int b)
+{
+  _m_prefetchit1 (bar);
+  return bar (b) + 1;
+}

[gcc r13-8952] i386: Add non-optimize prefetchi intrins

[Haochen Jiang via Gcc-cvs]

https://gcc.gnu.org/g:d80abba35edda7b508e29b723daebc0e475ddd87

commit r13-8952-gd80abba35edda7b508e29b723daebc0e475ddd87
Author: Haochen Jiang 
Date:   Thu Jul 25 16:16:05 2024 +0800

i386: Add non-optimize prefetchi intrins

Under -O0, with the "newly" introduced intrins, the variable will be
transformed as mem instead of the origin symbol_ref. The compiler will
then treat the operand as invalid and turn the operation into nop, which
is not expected. Use macro for non-optimize to keep the variable as
symbol_ref just as how prefetch intrin does.

gcc/ChangeLog:

* config/i386/prfchiintrin.h
(_m_prefetchit0): Add macro for non-optimized option.
(_m_prefetchit1): Ditto.

gcc/testsuite/ChangeLog:

* gcc.target/i386/prefetchi-1b.c: New test.

Diff:
---
 gcc/config/i386/prfchiintrin.h   |  9 +
 gcc/testsuite/gcc.target/i386/prefetchi-1b.c | 26 ++
 2 files changed, 35 insertions(+)

diff --git a/gcc/config/i386/prfchiintrin.h b/gcc/config/i386/prfchiintrin.h
index 382fc0795518..84cf27fe49c4 100644
--- a/gcc/config/i386/prfchiintrin.h
+++ b/gcc/config/i386/prfchiintrin.h
@@ -37,6 +37,7 @@
 #define __DISABLE_PREFETCHI__
 #endif /* __PREFETCHI__ */
 
+#ifdef __OPTIMIZE__
 extern __inline void
 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
 _m_prefetchit0 (void* __P)
@@ -50,6 +51,14 @@ _m_prefetchit1 (void* __P)
 {
   __builtin_ia32_prefetchi (__P, 2);
 }
+#else
+#define _m_prefetchit0(P)  \
+  __builtin_ia32_prefetchi(P, 3);
+
+#define _m_prefetchit1(P)  \
+  __builtin_ia32_prefetchi(P, 2);
+
+#endif
 
 #ifdef __DISABLE_PREFETCHI__
 #undef __DISABLE_PREFETCHI__
diff --git a/gcc/testsuite/gcc.target/i386/prefetchi-1b.c 
b/gcc/testsuite/gcc.target/i386/prefetchi-1b.c
new file mode 100644
index ..93139554d3cd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/prefetchi-1b.c
@@ -0,0 +1,26 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-mprefetchi -O0" } */
+/* { dg-final { scan-assembler-times "\[ \\t\]+prefetchit0\[ 
\\t\]+bar\\(%rip\\)" 1 } } */
+/* { dg-final { scan-assembler-times "\[ \\t\]+prefetchit1\[ 
\\t\]+bar\\(%rip\\)" 1 } } */
+
+#include 
+
+int
+bar (int a)
+{
+  return a + 1;
+}
+
+int
+foo1 (int b)
+{
+  _m_prefetchit0 (bar);
+  return bar (b) + 1;
+}
+
+int
+foo2 (int b)
+{
+  _m_prefetchit1 (bar);
+  return bar (b) + 1;
+}

[gcc r15-2395] Refine constraint "Bk" to define_special_memory_constraint.

[hongtao Liu via Gcc-cvs]

https://gcc.gnu.org/g:bc1fda00d5f20e2f3e77a50b2822562b6e0040b2

commit r15-2395-gbc1fda00d5f20e2f3e77a50b2822562b6e0040b2
Author: liuhongt 
Date:   Wed Jul 24 11:29:23 2024 +0800

Refine constraint "Bk" to define_special_memory_constraint.

For below pattern, RA may still allocate r162 as v/k register, try to
reload for address with leaq __libc_tsd_CTYPE_B@gottpoff(%rip), %rsi
which result a linker error.

(set (reg:DI 162)
 (mem/u/c:DI
   (const:DI (unspec:DI
 [(symbol_ref:DI ("a") [flags 0x60]  )]
 UNSPEC_GOTNTPOFF))

Quote from H.J for why linker issue an error.
>What do these do:
>
>leaq__libc_tsd_CTYPE_B@gottpoff(%rip), %rax
>vmovq   (%rax), %xmm0
>
>From x86-64 TLS psABI:
>
>The assembler generates for the x@gottpoff(%rip) expressions a R X86
>64 GOTTPOFF relocation for the symbol x which requests the linker to
>generate a GOT entry with a R X86 64 TPOFF64 relocation. The offset of
>the GOT entry relative to the end of the instruction is then used in
>the instruction. The R X86 64 TPOFF64 relocation is pro- cessed at
>program startup time by the dynamic linker by looking up the symbol x
>in the modules loaded at that point. The offset is written in the GOT
>entry and later loaded by the addq instruction.
>
>The above code sequence looks wrong to me.

gcc/ChangeLog:

PR target/116043
* config/i386/constraints.md (Bk): Refine to
define_special_memory_constraint.

gcc/testsuite/ChangeLog:

* gcc.target/i386/pr116043.c: New test.

Diff:
---
 gcc/config/i386/constraints.md   |  2 +-
 gcc/testsuite/gcc.target/i386/pr116043.c | 33 
 2 files changed, 34 insertions(+), 1 deletion(-)

diff --git a/gcc/config/i386/constraints.md b/gcc/config/i386/constraints.md
index 7508d7a58bd7..b760e7c221a1 100644
--- a/gcc/config/i386/constraints.md
+++ b/gcc/config/i386/constraints.md
@@ -187,7 +187,7 @@
   "@internal Vector memory operand."
   (match_operand 0 "vector_memory_operand"))
 
-(define_memory_constraint "Bk"
+(define_special_memory_constraint "Bk"
   "@internal TLS address that allows insn using non-integer registers."
   (and (match_operand 0 "memory_operand")
(not (match_test "ix86_gpr_tls_address_pattern_p (op)"
diff --git a/gcc/testsuite/gcc.target/i386/pr116043.c 
b/gcc/testsuite/gcc.target/i386/pr116043.c
new file mode 100644
index ..76553496c109
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr116043.c
@@ -0,0 +1,33 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512bf16 -O3" } */
+/* { dg-final { scan-assembler-not {(?n)lea.*@gottpoff} } } */
+
+extern __thread int a, c, i, j, k, l;
+int *b;
+struct d {
+  int e;
+} f, g;
+char *h;
+
+void m(struct d *n) {
+  b = &k;
+  for (; n->e; b++, n--) {
+i = b && a;
+if (i)
+  j = c;
+  }
+}
+
+char *o(struct d *n) {
+  for (; n->e;)
+return h;
+}
+
+int q() {
+  if (l)
+return 1;
+  int p = *o(&g);
+  m(&f);
+  m(&g);
+  l = p;
+}

[gcc(refs/users/meissner/heads/work174)] Add rs6000 architecture masks.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:e2263a8ee92635ffd1862a8b21036da2d848006c

commit e2263a8ee92635ffd1862a8b21036da2d848006c
Author: Michael Meissner 
Date:   Mon Jul 29 23:11:41 2024 -0400

Add rs6000 architecture masks.

This patch begins the journey to move architecture bits that are not user 
ISA
options from rs6000_isa_flags to a new targt variable rs6000_arch_flags.  
The
intention is to remove switches that are currently isa options, but the user
should not be using this particular option. For example, we want users to 
use
-mcpu=power10 and not just -mpower10.

2024-07-29  Michael Meissner  

gcc/

* config/rs6000/rs6000-arch.def: New file.
* config/rs6000/rs6000-opts.h: Use rs6000-arch.def to create the
architecture masks needed.
* config/rs6000/rs6000.cc (rs6000_print_isa_options): Add an
architecture flags argument, change all callers.
(get_arch_flag): New function.
(rs6000_debug_reg_global): Update rs6000_print_isa_options calls.
(rs6000_option_override_internal): Likewise.
(struct rs6000_arch_mask): New structure.
(rs6000_arch_masks): New table of architecutre masks and names.
(rs6000_function_specific_save): Save architecture flags.
(rs6000_function_specific_restore): Restore architecture flags.
(rs6000_function_specific_print): Update rs6000_print_isa_options 
calls.
(rs6000_print_options_internal): Add architecture flags options.
(rs6000_can_inline_p): Don't allow inling if the callee requires a 
newer
architecture than the caller.
* config/rs6000/rs6000.opt (rs6000_arch_flags): New target variable.
(x_rs6000_arch_flags): New save/restore field for rs6000_arch_flags.

Diff:
---
 gcc/config/rs6000/rs6000-arch.def |  47 
 gcc/config/rs6000/rs6000-opts.h   |  20 +
 gcc/config/rs6000/rs6000.cc   | 151 +-
 gcc/config/rs6000/rs6000.opt  |   8 ++
 4 files changed, 209 insertions(+), 17 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-arch.def 
b/gcc/config/rs6000/rs6000-arch.def
new file mode 100644
index ..6725736076da
--- /dev/null
+++ b/gcc/config/rs6000/rs6000-arch.def
@@ -0,0 +1,47 @@
+/* IBM RS/6000 CPU architecture features by processor type.
+   Copyright (C) 1991-2024 Free Software Foundation, Inc.
+   Contributed by Richard Kenner (ken...@vlsi1.ultra.nyu.edu)
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with GCC; see the file COPYING3.  If not see
+   .  */
+
+/* This file defines architecture features that are based on the -mcpu=
+   option, and not on user options that can be turned on or off.  The intention
+   is for newer processors (power7 and above) to not add new ISA bits for the
+   particular processor, but add these bits.  Otherwise we have to add a bunch
+   of hidden options, just so we have the proper ISA bits.
+
+   For example, in the past we added -mpower8-internal, so that on power8,
+   power9, and power10 would inherit the option, but we had to mark the option
+   generate a warning if the user actually used it.  These options have been
+   moved from the ISA flags to the arch flags.
+
+   To use this, define the macro ARCH_EXPAND which takes 2 arguments.  The
+   first argument is the processor name in upper case, and the second argument
+   is a text name for the processor.
+
+   The function get_arch_flags when passed a processor index number will set up
+   the appropriate architecture flags based on the actual processor
+   enumeration.  */
+
+ARCH_EXPAND(POWER4,  "power4")
+ARCH_EXPAND(POWER5,  "power5")
+ARCH_EXPAND(POWER6,  "power6")
+ARCH_EXPAND(POWER7,  "power7")
+ARCH_EXPAND(POWER8,  "power8")
+ARCH_EXPAND(POWER9,  "power9")
+ARCH_EXPAND(POWER10, "power10")
+ARCH_EXPAND(POWER11, "power11")
diff --git a/gcc/config/rs6000/rs6000-opts.h b/gcc/config/rs6000/rs6000-opts.h
index 88e357835a5c..9a52a1d4b147 100644
--- a/gcc/config/rs6000/rs6000-opts.h
+++ b/gcc/config/rs6000/rs6000-opts.h
@@ -71,6 +71,26 @@ enum processor_type
PROCESSOR_TITAN
 };
 
+/* Define an enumeration to number the architecture masks.  */
+#undef  ARCH_EXPAND
+#define ARCH_EXPAND(PROC, NAME)ARCH_ENUM_ ## PROC,
+
+enum {
+#include "rs6000-arch.def"
+  ARCH_ENUM_LAST
+};
+
+/* Create an architectur

[gcc(refs/users/meissner/heads/work174)] Set .machine from the architecture flags

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:b923b8d6ce508b1c05a8d64a285bf3511e1ebac5

commit b923b8d6ce508b1c05a8d64a285bf3511e1ebac5
Author: Michael Meissner 
Date:   Mon Jul 29 23:17:40 2024 -0400

Set .machine from the architecture flags

This patch switches the handling of .machine to use architecture masks if 
they
exist (power4 through power11).  All of the other PowerPCs will continue to 
use
the existing code for setting the .machine option.

2024-07-29  Michael Meissner  

gcc/

* config/rs6000/rs6000 (rs6000_machine_from_flags): Set .machine 
from
the architecture flags.

Diff:
---
 gcc/config/rs6000/rs6000.cc | 17 +
 1 file changed, 9 insertions(+), 8 deletions(-)

diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 0dda6dcc5a1a..ac2f4d769216 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -5965,27 +5965,28 @@ rs6000_machine_from_flags (void)
 return "ppc64";
 #endif
 
+  HOST_WIDE_INT arch_flags = rs6000_arch_flags;
   HOST_WIDE_INT flags = rs6000_isa_flags;
 
   /* Disable the flags that should never influence the .machine selection.  */
   flags &= ~(OPTION_MASK_PPC_GFXOPT | OPTION_MASK_PPC_GPOPT | OPTION_MASK_ISEL
 | OPTION_MASK_ALTIVEC);
 
-  if ((flags & (POWER11_MASKS_SERVER & ~ISA_3_1_MASKS_SERVER)) != 0)
+  if ((arch_flags & ARCH_MASK_POWER11) != 0)
 return "power11";
-  if ((flags & (ISA_3_1_MASKS_SERVER & ~ISA_3_0_MASKS_SERVER)) != 0)
+  if ((arch_flags & ARCH_MASK_POWER10) != 0)
 return "power10";
-  if ((flags & (ISA_3_0_MASKS_SERVER & ~ISA_2_7_MASKS_SERVER)) != 0)
+  if ((arch_flags & ARCH_MASK_POWER9) != 0)
 return "power9";
-  if ((flags & (ISA_2_7_MASKS_SERVER & ~ISA_2_6_MASKS_SERVER)) != 0)
+  if ((arch_flags & ARCH_MASK_POWER8) != 0)
 return "power8";
-  if ((flags & (ISA_2_6_MASKS_SERVER & ~ISA_2_5_MASKS_SERVER)) != 0)
+  if ((arch_flags & ARCH_MASK_POWER7) != 0)
 return "power7";
-  if ((flags & (ISA_2_5_MASKS_SERVER & ~ISA_2_4_MASKS)) != 0)
+  if ((arch_flags & ARCH_MASK_POWER6) != 0)
 return "power6";
-  if ((flags & (ISA_2_4_MASKS & ~ISA_2_1_MASKS)) != 0)
+  if ((arch_flags & ARCH_MASK_POWER5) != 0)
 return "power5";
-  if ((flags & ISA_2_1_MASKS) != 0)
+  if ((arch_flags & ARCH_MASK_POWER4) != 0)
 return "power4";
   if ((flags & OPTION_MASK_POWERPC64) != 0)
 return "ppc64";

[gcc(refs/users/meissner/heads/work174)] Make clone_targets use architecture flags.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:63ecac63bac6f2c1e7e151a4ff494f27b41b86e7

commit 63ecac63bac6f2c1e7e151a4ff494f27b41b86e7
Author: Michael Meissner 
Date:   Mon Jul 29 23:15:10 2024 -0400

Make clone_targets use architecture flags.

This patch expands on the previous patch and changes the target_clones 
support
to use an architecture mask instead of isa bits.

2024-07-29  Michael Meissner  

gcc/

* config/rs6000/rs6000.cc (struct clone_map): Switch to use 
architecture
flags instead of ISA flags for target_clone support.
(rs6000_clone_map): Likewise.
(rs6000_clone_priority): Likewise.

Diff:
---
 gcc/config/rs6000/rs6000.cc | 22 +++---
 1 file changed, 11 insertions(+), 11 deletions(-)

diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 83ae0157a9ec..0dda6dcc5a1a 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -251,17 +251,17 @@ enum {
 
 /* Map compiler ISA bits into HWCAP names.  */
 struct clone_map {
-  HOST_WIDE_INT isa_mask;  /* rs6000_isa mask */
+  HOST_WIDE_INT arch_mask; /* rs6000_arch_mask.  */
   const char *name;/* name to use in __builtin_cpu_supports.  */
 };
 
 static const struct clone_map rs6000_clone_map[CLONE_MAX] = {
-  { 0, "" },   /* Default options.  */
-  { OPTION_MASK_CMPB,  "arch_2_05" },  /* ISA 2.05 (power6).  */
-  { OPTION_MASK_POPCNTD,   "arch_2_06" },  /* ISA 2.06 (power7).  */
-  { OPTION_MASK_P8_VECTOR, "arch_2_07" },  /* ISA 2.07 (power8).  */
-  { OPTION_MASK_P9_VECTOR, "arch_3_00" },  /* ISA 3.0 (power9).  */
-  { OPTION_MASK_POWER10,   "arch_3_1" },   /* ISA 3.1 (power10).  */
+  { 0, "" },   /* Default options.  */
+  { ARCH_MASK_POWER6,  "arch_2_05" },  /* ISA 2.05 (power6).  */
+  { ARCH_MASK_POWER7,  "arch_2_06" },  /* ISA 2.06 (power7).  */
+  { ARCH_MASK_POWER8,  "arch_2_07" },  /* ISA 2.07 (power8).  */
+  { ARCH_MASK_POWER9,  "arch_3_00" },  /* ISA 3.0 (power9).  */
+  { ARCH_MASK_POWER10, "arch_3_1" },   /* ISA 3.1 (power10).  */
 };
 
 
@@ -25408,7 +25408,7 @@ static int
 rs6000_clone_priority (tree fndecl)
 {
   tree fn_opts = DECL_FUNCTION_SPECIFIC_TARGET (fndecl);
-  HOST_WIDE_INT isa_masks;
+  HOST_WIDE_INT arch_masks;
   int ret = CLONE_DEFAULT;
   tree attrs = lookup_attribute ("target", DECL_ATTRIBUTES (fndecl));
   const char *attrs_str = NULL;
@@ -25424,12 +25424,12 @@ rs6000_clone_priority (tree fndecl)
fn_opts = target_option_default_node;
 
   if (!fn_opts || !TREE_TARGET_OPTION (fn_opts))
-   isa_masks = rs6000_isa_flags;
+   arch_masks = rs6000_arch_flags;
   else
-   isa_masks = TREE_TARGET_OPTION (fn_opts)->x_rs6000_isa_flags;
+   arch_masks = TREE_TARGET_OPTION (fn_opts)->x_rs6000_arch_flags;
 
   for (ret = CLONE_MAX - 1; ret != 0; ret--)
-   if ((rs6000_clone_map[ret].isa_mask & isa_masks) != 0)
+   if ((rs6000_clone_map[ret].arch_mask & arch_masks) != 0)
  break;
 }

[gcc(refs/users/meissner/heads/work174)] Use architecture flags for defining _ARCH_PWR macros.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:66b25bd282d5ec1adb4a18ba206c893844c5807e

commit 66b25bd282d5ec1adb4a18ba206c893844c5807e
Author: Michael Meissner 
Date:   Mon Jul 29 23:28:39 2024 -0400

Use architecture flags for defining _ARCH_PWR macros.

For the newer architectures, this patch changes GCC to define the 
_ARCH_PWR
macros using the new architecture flags instead of relying on isa options 
like
-mpower10.

The -mpower8-internal, -mpower10, and -mpower11 options were removed.  The
-mpower11 option was removed completely, since it was just added in GCC 15. 
 The
other two options were marked as WarnRemoved, and the various ISA bits were
removed.

TARGET_POWER8 and TARGET_POWER10 were re-defined to use the architeture bits
instead of the ISA bits.

There are other internal isa bits that aren't removed with this patch 
because
the built-in function support uses those bits.

2024-07-29  Michael Meissner  

gcc/

* config/rs6000/rs6000-c.cc (rs6000_target_modify_macros) Add 
support to
use architecture flags instead of ISA flags for setting most of the
_ARCH_PWR* macros.
(rs6000_cpu_cpp_builtins): Likewise.
* config/rs6000/rs6000-cpus.def (ISA_2_7_MASKS_SERVER): Remove
OPTION_MASK_POWER8.
(ISA_3_1_MASKS_SERVER): Remove OPTION_MASK_POWER10.
(POWER11_MASKS_SERVER): Remove OPTION_MASK_POWER11.
(POWERPC_MASKS): Remove OPTION_MASK_POWER8, OPTION_MASK_POWER10, and
OPTION_MASK_POWER11.
* config/rs6000/rs6000-protos.h (rs6000_target_modify_macros): 
Update
declaration.
(rs6000_target_modify_macros_ptr): Likewise.
* config/rs6000/rs6000.cc (rs6000_target_modify_macros_ptr): 
Likewise.
(rs6000_option_override_internal): Use architecture flags instead 
of ISA
flags.
(rs6000_opt_masks): Remove -mpower10 and -mpower11 support.
(rs6000_pragma_target_parse): Use architecture flags as well as ISA
flags.
* config/rs6000/rs6000.h (TARGET_POWER8): New macro.
(TARGET_POWER10): Likewise.
* config/rs6000/rs6000.opt (-mpower8-internal): No longer make this 
an
ISA flag.
(-mpower10): Likewise.
(-mpower11): Likewise.

Diff:
---
 gcc/config/rs6000/rs6000-c.cc | 17 +
 gcc/config/rs6000/rs6000-cpus.def |  8 +---
 gcc/config/rs6000/rs6000-protos.h |  5 +++--
 gcc/config/rs6000/rs6000.cc   | 19 +++
 gcc/config/rs6000/rs6000.h|  6 ++
 gcc/config/rs6000/rs6000.opt  | 11 ++-
 6 files changed, 32 insertions(+), 34 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc
index 04882c396bfe..a8a6a956874f 100644
--- a/gcc/config/rs6000/rs6000-c.cc
+++ b/gcc/config/rs6000/rs6000-c.cc
@@ -338,7 +338,8 @@ rs6000_define_or_undefine_macro (bool define_p, const char 
*name)
#pragma GCC target, we need to adjust the macros dynamically.  */
 
 void
-rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags)
+rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags,
+HOST_WIDE_INT arch_flags)
 {
   if (TARGET_DEBUG_BUILTIN || TARGET_DEBUG_TARGET)
 fprintf (stderr,
@@ -411,7 +412,7 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT 
flags)
summary of the flags associated with particular cpu
definitions.  */
 
-  /* rs6000_isa_flags based options.  */
+  /* rs6000_isa_flags and rs6000_arch_flags based options.  */
   rs6000_define_or_undefine_macro (define_p, "_ARCH_PPC");
   if ((flags & OPTION_MASK_PPC_GPOPT) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PPCSQ");
@@ -427,15 +428,15 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT 
flags)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5X");
   if ((flags & OPTION_MASK_CMPB) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR6");
-  if ((flags & OPTION_MASK_POPCNTD) != 0)
+  if ((arch_flags & ARCH_MASK_POWER7) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR7");
-  if ((flags & OPTION_MASK_POWER8) != 0)
+  if ((arch_flags & ARCH_MASK_POWER8) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR8");
-  if ((flags & OPTION_MASK_MODULO) != 0)
+  if ((arch_flags & ARCH_MASK_POWER9) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR9");
-  if ((flags & OPTION_MASK_POWER10) != 0)
+  if ((arch_flags & ARCH_MASK_POWER10) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR10");
-  if ((flags & OPTION_MASK_POWER11) != 0)
+  if ((arch_flags & ARCH_MASK_POWER11) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR11");
   if ((flags & OPTION_MASK_SOFT_FLOAT) != 0)
 rs6000_define_or_undefine_macro (define_p, "_SOFT_FLOAT");
@@ -605,7 +606,7 @@ void
 rs6000_cpu_cp

[gcc(refs/users/meissner/heads/work174)] Do not allow -mvsx to boost processor to power7.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:062b226ae470e28d3e8f883dd6db1a4d0e301ac8

commit 062b226ae470e28d3e8f883dd6db1a4d0e301ac8
Author: Michael Meissner 
Date:   Mon Jul 29 23:35:12 2024 -0400

Do not allow -mvsx to boost processor to power7.

2024-07-29  Michael Meissner  

gcc/

* config/rs6000/rs6000.cc (report_architecture_mismatch): New 
function.
Report an error if the user used an option such as -mvsx when the
default processor would not allow the option.
(rs6000_option_override_internal): Move some ISA checking code into
report_architecture_mismatch.

Diff:
---
 gcc/config/rs6000/rs6000.cc | 129 +++-
 1 file changed, 79 insertions(+), 50 deletions(-)

diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 1bd045b8f037..19adc66cc801 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -1172,6 +1172,7 @@ const int INSN_NOT_AVAILABLE = -1;
 static void rs6000_print_isa_options (FILE *, int, const char *,
  HOST_WIDE_INT, HOST_WIDE_INT);
 static HOST_WIDE_INT rs6000_disable_incompatible_switches (void);
+static void report_architecture_mismatch (void);
 
 static enum rs6000_reg_type register_to_reg_type (rtx, bool *);
 static bool rs6000_secondary_reload_move (enum rs6000_reg_type,
@@ -3673,7 +3674,6 @@ rs6000_option_override_internal (bool global_init_p)
   bool ret = true;
 
   HOST_WIDE_INT set_masks;
-  HOST_WIDE_INT ignore_masks;
   int cpu_index = -1;
   int tune_index;
   struct cl_target_option *main_target_opt
@@ -3942,59 +3942,13 @@ rs6000_option_override_internal (bool global_init_p)
 dwarf_offset_size = POINTER_SIZE_UNITS;
 #endif
 
-  /* Handle explicit -mno-{altivec,vsx} and turn off all of
- the options that depend on those flags.  */
-  ignore_masks = rs6000_disable_incompatible_switches ();
-
-  /* For the newer switches (vsx, dfp, etc.) set some of the older options,
- unless the user explicitly used the -mno- to disable the code.  */
-  if (TARGET_P9_VECTOR || TARGET_MODULO || TARGET_P9_MISC)
-rs6000_isa_flags |= (ISA_3_0_MASKS_SERVER & ~ignore_masks);
-  else if (TARGET_P9_MINMAX)
-{
-  if (cpu_index >= 0)
-   {
- if (cpu_index == PROCESSOR_POWER9)
-   {
- /* legacy behavior: allow -mcpu=power9 with certain
-capabilities explicitly disabled.  */
- rs6000_isa_flags |= (ISA_3_0_MASKS_SERVER & ~ignore_masks);
-   }
- else
-   error ("power9 target option is incompatible with %<%s=%> "
-  "for  less than power9", "-mcpu");
-   }
-  else if ((ISA_3_0_MASKS_SERVER & rs6000_isa_flags_explicit)
-  != (ISA_3_0_MASKS_SERVER & rs6000_isa_flags
-  & rs6000_isa_flags_explicit))
-   /* Enforce that none of the ISA_3_0_MASKS_SERVER flags
-  were explicitly cleared.  */
-   error ("%qs incompatible with explicitly disabled options",
-  "-mpower9-minmax");
-  else
-   rs6000_isa_flags |= ISA_3_0_MASKS_SERVER;
-}
-  else if (TARGET_P8_VECTOR || TARGET_POWER8 || TARGET_CRYPTO)
-rs6000_isa_flags |= (ISA_2_7_MASKS_SERVER & ~ignore_masks);
-  else if (TARGET_VSX)
-rs6000_isa_flags |= (ISA_2_6_MASKS_SERVER & ~ignore_masks);
-  else if (TARGET_POPCNTD)
-rs6000_isa_flags |= (ISA_2_6_MASKS_EMBEDDED & ~ignore_masks);
-  else if (TARGET_DFP)
-rs6000_isa_flags |= (ISA_2_5_MASKS_SERVER & ~ignore_masks);
-  else if (TARGET_CMPB)
-rs6000_isa_flags |= (ISA_2_5_MASKS_EMBEDDED & ~ignore_masks);
-  else if (TARGET_FPRND)
-rs6000_isa_flags |= (ISA_2_4_MASKS & ~ignore_masks);
-  else if (TARGET_POPCNTB)
-rs6000_isa_flags |= (ISA_2_2_MASKS & ~ignore_masks);
-  else if (TARGET_ALTIVEC)
-rs6000_isa_flags |= (OPTION_MASK_PPC_GFXOPT & ~ignore_masks);
+  /* Report trying to use things like -mmodulo to imply -mcpu=power9.  */
+  report_architecture_mismatch ();
 
   /* Disable VSX and Altivec silently if the user switched cpus to power7 in a
  target attribute or pragma which automatically enables both options,
  unless the altivec ABI was set.  This is set by default for 64-bit, but
- not for 32-bit.  Don't move this before the above code using ignore_masks,
+ not for 32-bit.  Don't move this before report_architecture_mismatch
  since it can reset the cleared VSX/ALTIVEC flag again.  */
   if (main_target_opt && !main_target_opt->x_rs6000_altivec_abi)
 {
@@ -25385,6 +25339,81 @@ rs6000_disable_incompatible_switches (void)
   return ignore_masks;
 }
 
+/* In the past, we would boost up the ISA if you selected an -m option but
+   did not specify the correct -mcpu= option.  I.e. if you added -mvsx,
+   GCC implictly would assume that you were building for at least power7.  Now,
+   don't allow the -m option to boost up the ISA level.  But you can still
+   do -mcpu=power7 -mno-vsx or -mcp

[gcc(refs/users/meissner/heads/work174)] Update tests to work with architecture flags changes.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:b218260ad062bc65820475609bb69cee7dc6f7da

commit b218260ad062bc65820475609bb69cee7dc6f7da
Author: Michael Meissner 
Date:   Mon Jul 29 23:39:45 2024 -0400

Update tests to work with architecture flags changes.

Two tests used -mvsx to raise the processor level to at least power7.  These
tests were rewritten to add cpu=power7 support.

2024-07-29  Michael Meissner  

gcc/testsuite/

* gcc.target/powerpc/ppc-target-4.c: Rewrite the test to add 
cpu=power7
when we need to add VSX support.  Add test for adding cpu=power7 
no-vsx
to generate only Altivec instructions.
* gcc.target/powerpc/pr115688.c: Add cpu=power7 when requesting VSX
instructions.

Diff:
---
 gcc/testsuite/gcc.target/powerpc/ppc-target-4.c | 40 ++---
 gcc/testsuite/gcc.target/powerpc/pr115688.c |  3 +-
 2 files changed, 32 insertions(+), 11 deletions(-)

diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-target-4.c 
b/gcc/testsuite/gcc.target/powerpc/ppc-target-4.c
index db9ba500e0e1..42f5aa354d0a 100644
--- a/gcc/testsuite/gcc.target/powerpc/ppc-target-4.c
+++ b/gcc/testsuite/gcc.target/powerpc/ppc-target-4.c
@@ -1,8 +1,8 @@
 /* { dg-do compile { target { powerpc*-*-* } } } */
 /* { dg-skip-if "" { powerpc*-*-darwin* } } */
 /* { dg-require-effective-target powerpc_vsx_ok } */
-/* { dg-options "-O2 -ffast-math -mdejagnu-cpu=power5 -mno-altivec 
-mabi=altivec -fno-unroll-loops" } */
-/* { dg-final { scan-assembler-times "vaddfp" 1 } } */
+/* { dg-options "-O3 -ffast-math -mdejagnu-cpu=power5 -mno-altivec 
-mabi=altivec -fno-unroll-loops" } */
+/* { dg-final { scan-assembler-times "vaddfp" 2 } } */
 /* { dg-final { scan-assembler-times "xvaddsp" 1 } } */
 /* { dg-final { scan-assembler-times "fadds" 1 } } */
 
@@ -18,10 +18,6 @@
 #error "__VSX__ should not be defined."
 #endif
 
-#pragma GCC target("altivec,vsx")
-#include 
-#pragma GCC reset_options
-
 #pragma GCC push_options
 #pragma GCC target("altivec,no-vsx")
 
@@ -33,6 +29,7 @@
 #error "__VSX__ should not be defined."
 #endif
 
+/* Altivec build, generate vaddfp.  */
 void
 av_add (vector float *a, vector float *b, vector float *c)
 {
@@ -40,10 +37,11 @@ av_add (vector float *a, vector float *b, vector float *c)
   unsigned long n = SIZE / 4;
 
   for (i = 0; i < n; i++)
-a[i] = vec_add (b[i], c[i]);
+a[i] = b[i] + c[i];
 }
 
-#pragma GCC target("vsx")
+/* cpu=power7 must be used to enable VSX.  */
+#pragma GCC target("cpu=power7,vsx")
 
 #ifndef __ALTIVEC__
 #error "__ALTIVEC__ should be defined."
@@ -53,6 +51,7 @@ av_add (vector float *a, vector float *b, vector float *c)
 #error "__VSX__ should be defined."
 #endif
 
+/* VSX build on power7, generate xsaddsp.  */
 void
 vsx_add (vector float *a, vector float *b, vector float *c)
 {
@@ -60,11 +59,31 @@ vsx_add (vector float *a, vector float *b, vector float *c)
   unsigned long n = SIZE / 4;
 
   for (i = 0; i < n; i++)
-a[i] = vec_add (b[i], c[i]);
+a[i] = b[i] + c[i];
+}
+
+#pragma GCC target("cpu=power7,no-vsx")
+
+#ifndef __ALTIVEC__
+#error "__ALTIVEC__ should be defined."
+#endif
+
+#ifdef __VSX__
+#error "__VSX__ should not be defined."
+#endif
+
+/* Altivec build on power7 with no VSX, generate vaddfp.  */
+void
+av2_add (vector float *a, vector float *b, vector float *c)
+{
+  unsigned long i;
+  unsigned long n = SIZE / 4;
+
+  for (i = 0; i < n; i++)
+a[i] = b[i] + c[i];
 }
 
 #pragma GCC pop_options
-#pragma GCC target("no-vsx,no-altivec")
 
 #ifdef __ALTIVEC__
 #error "__ALTIVEC__ should not be defined."
@@ -74,6 +93,7 @@ vsx_add (vector float *a, vector float *b, vector float *c)
 #error "__VSX__ should not be defined."
 #endif
 
+/* Default power5 build, generate scalar fadds.  */
 void
 norm_add (float *a, float *b, float *c)
 {
diff --git a/gcc/testsuite/gcc.target/powerpc/pr115688.c 
b/gcc/testsuite/gcc.target/powerpc/pr115688.c
index 5222e66ef170..00c7c301436a 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr115688.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr115688.c
@@ -7,7 +7,8 @@
 
 /* Verify there is no ICE under 32 bit env.  */
 
-__attribute__((target("vsx")))
+/* cpu=power7 must be used to enable VSX.  */
+__attribute__((target("cpu=power7,vsx")))
 int test (void)
 {
   return 0;

[gcc(refs/users/meissner/heads/work174)] Update ChangeLog.*

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:cef4f3cb53faff4bc3b74ecd1dd4dd3d3d2106df

commit cef4f3cb53faff4bc3b74ecd1dd4dd3d3d2106df
Author: Michael Meissner 
Date:   Mon Jul 29 23:44:58 2024 -0400

Update ChangeLog.*

Diff:
---
 gcc/ChangeLog.meissner | 182 -
 1 file changed, 181 insertions(+), 1 deletion(-)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index 65c296e69433..58ffd411e22d 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,6 +1,186 @@
+ Branch work174, patch #6 
+
+Update tests to work with architecture flags changes.
+
+Two tests used -mvsx to raise the processor level to at least power7.  These
+tests were rewritten to add cpu=power7 support.
+
+2024-07-29  Michael Meissner  
+
+gcc/testsuite/
+
+   * gcc.target/powerpc/ppc-target-4.c: Rewrite the test to add cpu=power7
+   when we need to add VSX support.  Add test for adding cpu=power7 no-vsx
+   to generate only Altivec instructions.
+   * gcc.target/powerpc/pr115688.c: Add cpu=power7 when requesting VSX
+   instructions.
+
+ Branch work174, patch #5 
+
+Do not allow -mvsx to boost processor to power7.
+
+This patch restructures the code so that -mvsx for example will not silently
+convert the processor to power7.  The user must now use -mcpu=power7 or higher.
+This means if the user does -mvsx and the default processor does not have VSX
+support, it will be an error.
+
+2024-07-29  Michael Meissner  
+
+gcc/
+
+   * config/rs6000/rs6000.cc (report_architecture_mismatch): New function.
+   Report an error if the user used an option such as -mvsx when the
+   default processor would not allow the option.
+   (rs6000_option_override_internal): Move some ISA checking code into
+   report_architecture_mismatch.
+
+ Branch work174, patch #4 
+
+Use architecture flags for defining _ARCH_PWR macros.
+
+For the newer architectures, this patch changes GCC to define the _ARCH_PWR
+macros using the new architecture flags instead of relying on isa options like
+-mpower10.
+
+The -mpower8-internal, -mpower10, and -mpower11 options were removed.  The
+-mpower11 option was removed completely, since it was just added in GCC 15.  
The
+other two options were marked as WarnRemoved, and the various ISA bits were
+removed.
+
+TARGET_POWER8 and TARGET_POWER10 were re-defined to use the architeture bits
+instead of the ISA bits.
+
+There are other internal isa bits that aren't removed with this patch because
+the built-in function support uses those bits.
+
+2024-07-29  Michael Meissner  
+
+gcc/
+
+   * config/rs6000/rs6000-c.cc (rs6000_target_modify_macros) Add support to
+   use architecture flags instead of ISA flags for setting most of the
+   _ARCH_PWR* macros.
+   (rs6000_cpu_cpp_builtins): Likewise.
+   * config/rs6000/rs6000-cpus.def (ISA_2_7_MASKS_SERVER): Remove
+   OPTION_MASK_POWER8.
+   (ISA_3_1_MASKS_SERVER): Remove OPTION_MASK_POWER10.
+   (POWER11_MASKS_SERVER): Remove OPTION_MASK_POWER11.
+   (POWERPC_MASKS): Remove OPTION_MASK_POWER8, OPTION_MASK_POWER10, and
+   OPTION_MASK_POWER11.
+   * config/rs6000/rs6000-protos.h (rs6000_target_modify_macros): Update
+   declaration.
+   (rs6000_target_modify_macros_ptr): Likewise.
+   * config/rs6000/rs6000.cc (rs6000_target_modify_macros_ptr): Likewise.
+   (rs6000_option_override_internal): Use architecture flags instead of ISA
+   flags.
+   (rs6000_opt_masks): Remove -mpower10 and -mpower11 support.
+   (rs6000_pragma_target_parse): Use architecture flags as well as ISA
+   flags.
+   * config/rs6000/rs6000.h (TARGET_POWER8): New macro.
+   (TARGET_POWER10): Likewise.
+   * config/rs6000/rs6000.opt (-mpower8-internal): No longer make this an
+   ISA flag.
+   (-mpower10): Likewise.
+   (-mpower11): Likewise.
+
+ Branch work174, patch #3 
+
+Set .machine from the architecture flags
+
+This patch switches the handling of .machine to use architecture masks if they
+exist (power4 through power11).  All of the other PowerPCs will continue to use
+the existing code for setting the .machine option.
+
+2024-07-29  Michael Meissner  
+
+gcc/
+
+   * config/rs6000/rs6000 (rs6000_machine_from_flags): Set .machine from
+   the architecture flags.
+
+ Branch work174, patch #2 
+
+Make clone_targets use architecture flags.
+
+This patch expands on the previous patch and changes the target_clones support
+to use an architecture mask instead of isa bits.
+
+2024-07-29  Michael Meissner  
+
+gcc/
+
+   * config/rs6000/rs6000.cc (struct clone_map): Switch to use architecture
+   flags instead of ISA flags for target_clone support.
+   (rs6000_clone_map): Likewise.
+   (rs6000_clone_priority)

[gcc r15-2396] xtensa: Fix the regression introduce by r15-959-gbe9b3f4375e7

[Max Filippov via Gcc-cvs]

https://gcc.gnu.org/g:8ebb1d79ea16f37214c33d853061d3c9cf5e7f46

commit r15-2396-g8ebb1d79ea16f37214c33d853061d3c9cf5e7f46
Author: Takayuki 'January June' Suwa 
Date:   Sat Jul 20 05:35:33 2024 +0900

xtensa: Fix the regression introduce by r15-959-gbe9b3f4375e7

It is not wrong but also not optimal to specify that sibcalls require
register A0 in RTX generation pass, by misleading DFA into thinking it
is being used in function body.
It would be better to specify it in pro_and_epilogue as with 'return'
insn in order to avoid incorrect removing load that restores A0 in
subsequent passes, but since it is not possible to modify each sibcall
there, as a workaround we will preface it with a 'use' as before.

This patch effectively reverts commit r15-959-gbe9b3f4375e7

gcc/ChangeLog:

* config/xtensa/xtensa-protos.h (xtensa_expand_call):
Remove the third argument.
* config/xtensa/xtensa.cc (xtensa_expand_call):
Remove the third argument and the code that uses it.
* config/xtensa/xtensa.md (call, call_value, sibcall, 
sibcall_value):
Remove each Boolean constant specified in the third argument of
xtensa_expand_call.
(sibcall_epilogue): Add emitting '(use A0_REG)' after calling
xtensa_expand_epilogue.

Diff:
---
 gcc/config/xtensa/xtensa-protos.h |  2 +-
 gcc/config/xtensa/xtensa.cc   | 10 +-
 gcc/config/xtensa/xtensa.md   |  9 +
 3 files changed, 7 insertions(+), 14 deletions(-)

diff --git a/gcc/config/xtensa/xtensa-protos.h 
b/gcc/config/xtensa/xtensa-protos.h
index 8f645e87de96..3646ceaa0938 100644
--- a/gcc/config/xtensa/xtensa-protos.h
+++ b/gcc/config/xtensa/xtensa-protos.h
@@ -53,7 +53,7 @@ extern void xtensa_expand_atomic (enum rtx_code, rtx, rtx, 
rtx, bool);
 extern void xtensa_emit_loop_end (rtx_insn *, rtx *);
 extern char *xtensa_emit_branch (bool, rtx *);
 extern char *xtensa_emit_movcc (bool, bool, bool, rtx *);
-extern void xtensa_expand_call (int, rtx *, bool);
+extern void xtensa_expand_call (int, rtx *);
 extern char *xtensa_emit_call (int, rtx *);
 extern char *xtensa_emit_sibcall (int, rtx *);
 extern bool xtensa_tls_referenced_p (rtx);
diff --git a/gcc/config/xtensa/xtensa.cc b/gcc/config/xtensa/xtensa.cc
index 772150c7fa22..1ccd42bcda89 100644
--- a/gcc/config/xtensa/xtensa.cc
+++ b/gcc/config/xtensa/xtensa.cc
@@ -2297,7 +2297,7 @@ xtensa_emit_movcc (bool inverted, bool isfp, bool isbool, 
rtx *operands)
 
 
 void
-xtensa_expand_call (int callop, rtx *operands, bool sibcall_p)
+xtensa_expand_call (int callop, rtx *operands)
 {
   rtx call;
   rtx_insn *call_insn;
@@ -2339,14 +2339,6 @@ xtensa_expand_call (int callop, rtx *operands, bool 
sibcall_p)
   CALL_INSN_FUNCTION_USAGE (call_insn) =
gen_rtx_EXPR_LIST (Pmode, clob, CALL_INSN_FUNCTION_USAGE (call_insn));
 }
-  else if (sibcall_p)
-{
-  /* Sibling call requires a return address to the caller, similar to
-"return" insn.  */
-  rtx use = gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, A0_REG));
-  CALL_INSN_FUNCTION_USAGE (call_insn) =
-   gen_rtx_EXPR_LIST (Pmode, use, CALL_INSN_FUNCTION_USAGE (call_insn));
-}
 }
 
 
diff --git a/gcc/config/xtensa/xtensa.md b/gcc/config/xtensa/xtensa.md
index 376d0f755446..a3b99dc381de 100644
--- a/gcc/config/xtensa/xtensa.md
+++ b/gcc/config/xtensa/xtensa.md
@@ -2597,7 +2597,7 @@
 (match_operand 1 "" ""))]
   ""
 {
-  xtensa_expand_call (0, operands, false);
+  xtensa_expand_call (0, operands);
   DONE;
 })
 
@@ -2618,7 +2618,7 @@
  (match_operand 2 "" "")))]
   ""
 {
-  xtensa_expand_call (1, operands, false);
+  xtensa_expand_call (1, operands);
   DONE;
 })
 
@@ -2639,7 +2639,7 @@
 (match_operand 1 "" ""))]
   "!TARGET_WINDOWED_ABI"
 {
-  xtensa_expand_call (0, operands, true);
+  xtensa_expand_call (0, operands);
   DONE;
 })
 
@@ -2660,7 +2660,7 @@
  (match_operand 2 "" "")))]
   "!TARGET_WINDOWED_ABI"
 {
-  xtensa_expand_call (1, operands, true);
+  xtensa_expand_call (1, operands);
   DONE;
 })
 
@@ -2777,6 +2777,7 @@
   "!TARGET_WINDOWED_ABI"
 {
   xtensa_expand_epilogue ();
+  emit_use (gen_rtx_REG (SImode, A0_REG));
   DONE;
 })

[gcc r15-2397] xtensa: Fix suboptimal loading of pooled constant value into hardware single-precision FP register

[Max Filippov via Gcc-cvs]

https://gcc.gnu.org/g:fb7b82964f54192d0723a45c0657d2eb7c5ac97c

commit r15-2397-gfb7b82964f54192d0723a45c0657d2eb7c5ac97c
Author: Takayuki 'January June' Suwa 
Date:   Tue Jul 23 16:03:12 2024 +0900

xtensa: Fix suboptimal loading of pooled constant value into hardware 
single-precision FP register

We would like to implement the following to store a single-precision FP
constant in a hardware FP register:

- Load the bit-exact integer image of the pooled single-precision FP
  constant into an address (integer) register
- Then, assign from that address register to a hardware single-precision
  FP register

.literal_position
.literal.LC1, 0x3f80
...
l32ra9, .LC1
wfr f0, a9

However, it was emitted as follows:

- Load the address of the FP constant entry in litpool into an address
  register
- Then, dereference the address via that address register into a hardware
  single-precision FP register

.literal_position
.literal.LC1, 0x3f80
.literal.LC2, .LC1
...
l32ra9, .LC2
lsi f0, a9, 0

It is obviously inefficient to read the pool twice.

gcc/ChangeLog:

* config/xtensa/xtensa.md (movsf_internal):
Reorder alternative that corresponds to L32R machine instruction,
and prefix alternatives that correspond to LSI/SSI instructions
with the constraint character '^' so that they are disparaged by
reload/LRA.

Diff:
---
 gcc/config/xtensa/xtensa.md | 10 +-
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/gcc/config/xtensa/xtensa.md b/gcc/config/xtensa/xtensa.md
index a3b99dc381de..f19e1fd16b54 100644
--- a/gcc/config/xtensa/xtensa.md
+++ b/gcc/config/xtensa/xtensa.md
@@ -1453,8 +1453,8 @@
 })
 
 (define_insn "movsf_internal"
-  [(set (match_operand:SF 0 "nonimmed_operand" "=f,f,U,D,D,R,a,f,a,a,W,a,a,U")
-   (match_operand:SF 1 "move_operand" "f,U,f,d,R,d,r,r,f,Y,iF,T,U,r"))]
+  [(set (match_operand:SF 0 "nonimmed_operand" "=f,f,^U,D,a,D,R,a,f,a,a,W,a,U")
+   (match_operand:SF 1 "move_operand" "f,^U,f,d,T,R,d,r,r,f,Y,iF,U,r"))]
   "((register_operand (operands[0], SFmode)
  || register_operand (operands[1], SFmode))
 && !(FP_REG_P (xt_true_regnum (operands[0]))
@@ -1464,6 +1464,7 @@
%v1lsi\t%0, %1
%v0ssi\t%1, %0
mov.n\t%0, %1
+   %v1l32r\t%0, %1
%v1l32i.n\t%0, %1
%v0s32i.n\t%1, %0
mov\t%0, %1
@@ -1471,12 +1472,11 @@
rfr\t%0, %1
movi\t%0, %y1
const16\t%0, %t1\;const16\t%0, %b1
-   %v1l32r\t%0, %1
%v1l32i\t%0, %1
%v0s32i\t%1, %0"
-  [(set_attr "type"
"farith,fload,fstore,move,load,store,move,farith,farith,move,move,load,load,store")
+  [(set_attr "type"
"farith,fload,fstore,move,load,load,store,move,farith,farith,move,move,load,store")
(set_attr "mode""SF")
-   (set_attr "length"  "3,3,3,2,2,2,3,3,3,3,6,3,3,3")])
+   (set_attr "length"  "3,3,3,2,3,2,2,3,3,3,3,6,3,3")])
 
 (define_insn "*lsiu"
   [(set (match_operand:SF 0 "register_operand" "=f")

[gcc r15-2398] xtensa: Add missing speed cost for TYPE_FARITH in TARGET_INSN_COST

[Max Filippov via Gcc-cvs]

https://gcc.gnu.org/g:c1d35de0d94d43b9976aff44001dadd4dd42b7ae

commit r15-2398-gc1d35de0d94d43b9976aff44001dadd4dd42b7ae
Author: Takayuki 'January June' Suwa 
Date:   Wed Jul 24 06:07:06 2024 +0900

xtensa: Add missing speed cost for TYPE_FARITH in TARGET_INSN_COST

According to the implemented pipeline model, this cost can be assumed to be
1 clock cycle.

gcc/ChangeLog:

* config/xtensa/xtensa.cc (xtensa_insn_cost):
Add a case statement for TYPE_FARITH.

Diff:
---
 gcc/config/xtensa/xtensa.cc | 1 +
 1 file changed, 1 insertion(+)

diff --git a/gcc/config/xtensa/xtensa.cc b/gcc/config/xtensa/xtensa.cc
index 1ccd42bcda89..43b1332d42b3 100644
--- a/gcc/config/xtensa/xtensa.cc
+++ b/gcc/config/xtensa/xtensa.cc
@@ -4723,6 +4723,7 @@ xtensa_insn_cost (rtx_insn *insn, bool speed)
case TYPE_ARITH:
case TYPE_MULTI:
case TYPE_NOP:
+   case TYPE_FARITH:
case TYPE_FSTORE:
  return COSTS_N_INSNS (n);

[gcc r15-2399] RISC-V: Take Xmode instead of Pmode for ussub expanding

[Pan Li via Gcc-cvs]

https://gcc.gnu.org/g:85cff6e46d212240f9c15c2d7d614b6089be772a

commit r15-2399-g85cff6e46d212240f9c15c2d7d614b6089be772a
Author: Pan Li 
Date:   Tue Jul 30 13:56:40 2024 +0800

RISC-V: Take Xmode instead of Pmode for ussub expanding

The Pmode is designed for pointer,  thus leverage the Xmode instead
for the expanding of the ussub.

gcc/ChangeLog:

* config/riscv/riscv.cc (riscv_expand_ussub): Promote to Xmode
instead of Pmode.

Signed-off-by: Pan Li 

Diff:
---
 gcc/config/riscv/riscv.cc | 24 
 1 file changed, 12 insertions(+), 12 deletions(-)

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index a490b9598b04..8ece7859945c 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -11620,26 +11620,26 @@ void
 riscv_expand_ussub (rtx dest, rtx x, rtx y)
 {
   machine_mode mode = GET_MODE (dest);
-  rtx pmode_x = gen_lowpart (Pmode, x);
-  rtx pmode_y = gen_lowpart (Pmode, y);
-  rtx pmode_lt = gen_reg_rtx (Pmode);
-  rtx pmode_minus = gen_reg_rtx (Pmode);
-  rtx pmode_dest = gen_reg_rtx (Pmode);
+  rtx xmode_x = gen_lowpart (Xmode, x);
+  rtx xmode_y = gen_lowpart (Xmode, y);
+  rtx xmode_lt = gen_reg_rtx (Xmode);
+  rtx xmode_minus = gen_reg_rtx (Xmode);
+  rtx xmode_dest = gen_reg_rtx (Xmode);
 
   /* Step-1: minus = x - y  */
-  riscv_emit_binary (MINUS, pmode_minus, pmode_x, pmode_y);
+  riscv_emit_binary (MINUS, xmode_minus, xmode_x, xmode_y);
 
   /* Step-2: lt = x < y  */
-  riscv_emit_binary (LTU, pmode_lt, pmode_x, pmode_y);
+  riscv_emit_binary (LTU, xmode_lt, xmode_x, xmode_y);
 
   /* Step-3: lt = lt - 1 (lt + (-1))  */
-  riscv_emit_binary (PLUS, pmode_lt, pmode_lt, CONSTM1_RTX (Pmode));
+  riscv_emit_binary (PLUS, xmode_lt, xmode_lt, CONSTM1_RTX (Xmode));
 
-  /* Step-4: pmode_dest = minus & lt  */
-  riscv_emit_binary (AND, pmode_dest, pmode_lt, pmode_minus);
+  /* Step-4: xmode_dest = minus & lt  */
+  riscv_emit_binary (AND, xmode_dest, xmode_lt, xmode_minus);
 
-  /* Step-5: dest = pmode_dest  */
-  emit_move_insn (dest, gen_lowpart (mode, pmode_dest));
+  /* Step-5: dest = xmode_dest  */
+  emit_move_insn (dest, gen_lowpart (mode, xmode_dest));
 }
 
 /* Implement the unsigned saturation truncation for int mode.