[gcc r15-1962] Ensure function.end_line in source_info.lines

[J?rgen Kvalsvik via Gcc-cvs]

https://gcc.gnu.org/g:2b3fbac8e37384857cd594c0800fccd99e4d39a1

commit r15-1962-g2b3fbac8e37384857cd594c0800fccd99e4d39a1
Author: Jørgen Kvalsvik 
Date:   Wed Jul 10 18:47:27 2024 +0200

Ensure function.end_line in source_info.lines

Ensure that the function.end_line in the lines vector for the source
file, even if it is not explicitly touched by a basic block. This
ensures consistency with what you would expect. For example, this file
has sources[sum.cc].lines.size () == 23 and main.end_line == 2 without
adjusting sources.lines, which in this case is a no-op.

#:   17:int main ()
-:   18:{
#:   19:  sum (1, 2);
#:   20:  sum (1.1, 2);
#:   21:  sum (2.2, 2.3);
#:   22:}

This is a useful property when combined with selective reporting.

gcc/ChangeLog:

* gcov.cc (process_all_functions): Ensure fn.end_line is
included source[fn].lines.

Diff:
---
 gcc/gcov.cc | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/gcc/gcov.cc b/gcc/gcov.cc
index 2e4bd9d3c5da..7b4a075c5db6 100644
--- a/gcc/gcov.cc
+++ b/gcc/gcov.cc
@@ -1544,6 +1544,12 @@ process_all_functions (void)
}
}
 
+ /* Make sure to include the last line for this function even when it
+is not directly covered by a basic block, for example when } is on
+its own line.  */
+ if (sources[fn->src].lines.size () <= fn->end_line)
+   sources[fn->src].lines.resize (fn->end_line + 1);
+
  /* Allocate lines for group function, following start_line
 and end_line information of the function.  */
  if (fn->is_group)

[gcc r15-1963] Add function filtering to gcov

[J?rgen Kvalsvik via Gcc-cvs]

https://gcc.gnu.org/g:1e43ea7bb3598e3ee19119c54c69a7c4b8745d0f

commit r15-1963-g1e43ea7bb3598e3ee19119c54c69a7c4b8745d0f
Author: Jørgen Kvalsvik 
Date:   Fri Mar 29 13:01:37 2024 +0100

Add function filtering to gcov

Add the --include and --exclude flags to gcov to control what functions
to report on. This is meant to make gcov more practical as an when
writing test suites or performing other coverage experiments, which
tends to focus on a few functions at the time. This really shines in
combination with the -t/--stdout flag. With support for more expansive
metrics in gcov like modified condition/decision coverage (MC/DC) and
path coverage, output quickly gets overwhelming without filtering.

The approach is quite simple: filters are egrep regexes and are
evaluated left-to-right, and the last filter "wins", that is, if a
function matches an --include and a subsequent --exclude, it should not
be included in the output. All of the output machinery works on the
function table, so by optionally (not) adding function makes the even
the json output work as expected, and only minor changes are needed to
suppress the filtered-out functions.

Demo: math.c

int mul (int a, int b) {
return a * b;
}

int sub (int a, int b) {
return a - b;
}

int sum (int a, int b) {
return a + b;
}

Plain matches:

$ gcov -t math --include=sum
-:0:Source:math.c
-:0:Graph:math.gcno
-:0:Data:-
-:0:Runs:0
#:9:int sum (int a, int b) {
#:   10:return a + b;
-:   11:}

$ gcov -t math --include=mul
-:0:Source:math.c
-:0:Graph:math.gcno
-:0:Data:-
-:0:Runs:0
#:1:int mul (int a, int b) {
#:2:return a * b;
-:3:}

Regex match:

$ gcov -t math --include=su
-:0:Source:math.c
-:0:Graph:math.gcno
-:0:Data:-
-:0:Runs:0
#:5:int sub (int a, int b) {
#:6:return a - b;
-:7:}
#:9:int sum (int a, int b) {
#:   10:return a + b;
-:   11:}

And similar for exclude:

$ gcov -t math --exclude=sum
-:0:Source:math.c
-:0:Graph:math.gcno
-:0:Data:-
-:0:Runs:0
#:1:int mul (int a, int b) {
#:2:return a * b;
-:3:}
#:5:int sub (int a, int b) {
#:6:return a - b;
-:7:}

And json, for good measure:

$ gcov -t math --include=sum --json | jq ".files[].lines[]"
{
  "line_number": 9,
  "function_name": "sum",
  "count": 0,
  "unexecuted_block": true,
  "block_ids": [],
  "branches": [],
  "calls": []
}
{
  "line_number": 10,
  "function_name": "sum",
  "count": 0,
  "unexecuted_block": true,
  "block_ids": [
2
  ],
  "branches": [],
  "calls": []
}

Matching generally work well for mangled names, as the mangled names
also have the base symbol name in it. By default, functions are matched
by the mangled name, which means matching on base names always work as
expected. The -M flag makes the matching work on the demangled name
which is quite useful when you only want to report on specific
overloads and can use the full type names.

Why not just use grep? grep is not really sufficient as grep is very
line oriented, and the reports that benefit the most from filtering
often unpredictably span multiple lines based on the state of coverage.
For example, a condition coverage report for 3 terms/6 outcomes only
outputs 1 line when all conditions are covered, and 7 with no lines
covered.

gcc/ChangeLog:

* doc/gcov.texi: Add --include, --exclude, --match-on-demangled
documentation.
* gcov.cc (struct fnfilter): New.
(print_usage): Add --include, --exclude, -M,
--match-on-demangled.
(process_args): Likewise.
(release_structures): Release filters.
(read_graph_file): Only add function_infos matching filters.
(output_lines): Likewise.

gcc/testsuite/ChangeLog:

* lib/gcov.exp: Add filtering test function.
* g++.dg/gcov/gcov-19.C: New test.
* g++.dg/gcov/gcov-20.C: New test.
* g++.dg/gcov/gcov-21.C: New test.
* gcc.misc-tests/gcov-25.c: New test.
* gcc.misc-tests/gcov-26.c: New test.
* gcc.misc-tests/gcov-27.c: New test.
* gcc.misc-tests/gcov-28.c: 

[gcc r15-1964] Revert "fixincludes: skip stdio_stdarg_h on darwin"

[Iain D Sandoe via Gcc-cvs]

https://gcc.gnu.org/g:619f587f6852517889c216d4eb63728e9b062032

commit r15-1964-g619f587f6852517889c216d4eb63728e9b062032
Author: Iain Sandoe 
Date:   Thu Jul 11 07:19:51 2024 +0100

Revert "fixincludes: skip stdio_stdarg_h on darwin"

This reverts commit 7d454cae9d7df1f2936ad02d0742674a85396736.

The change breaks bootstrap on some x86_64 OS versions.

Diff:
---
 fixincludes/fixincl.x| 5 ++---
 fixincludes/inclhack.def | 1 -
 2 files changed, 2 insertions(+), 4 deletions(-)

diff --git a/fixincludes/fixincl.x b/fixincludes/fixincl.x
index bfacf9aa3ae9..9dc05ea17f10 100644
--- a/fixincludes/fixincl.x
+++ b/fixincludes/fixincl.x
@@ -2,11 +2,11 @@
  *
  * DO NOT EDIT THIS FILE   (fixincl.x)
  *
- * It has been AutoGen-ed  July 10, 2024 at 05:22:37 PM by AutoGen 5.18.16
+ * It has been AutoGen-ed  July 10, 2024 at 02:49:05 PM by AutoGen 5.18.16
  * From the definitionsinclhack.def
  * and the template file   fixincl
  */
-/* DO NOT SVN-MERGE THIS FILE, EITHER Wed Jul 10 17:22:37 CEST 2024
+/* DO NOT SVN-MERGE THIS FILE, EITHER Wed Jul 10 14:49:05 CEST 2024
  *
  * You must regenerate it.  Use the ./genfixes script.
  *
@@ -8975,7 +8975,6 @@ tSCC zStdio_Stdarg_HList[] =
  */
 tSCC* apzStdio_Stdarg_HMachs[] = {
 "*-*-solaris2.1[0-9]*",
-"*-*-darwin*",
 (const char*)NULL };
 
 /*
diff --git a/fixincludes/inclhack.def b/fixincludes/inclhack.def
index 69f751b4f27e..1ac8e335419e 100644
--- a/fixincludes/inclhack.def
+++ b/fixincludes/inclhack.def
@@ -4484,7 +4484,6 @@ fix = {
  * , which includes .
   */
 mach = '*-*-solaris2.1[0-9]*';
-mach = "*-*-darwin*";
 not_machine = true;
 
 c_fix = wrap;

[gcc r15-1965] Fortran: Fix rejecting class arrays of different ranks as storage association argument and add un/pa

[Andre Vehreschild via Gcc-cvs]

https://gcc.gnu.org/g:e4f2f46e015acb4c1b5605116a3ff0bb8c980372

commit r15-1965-ge4f2f46e015acb4c1b5605116a3ff0bb8c980372
Author: Andre Vehreschild 
Date:   Fri Jun 28 08:31:29 2024 +0200

Fortran: Fix rejecting class arrays of different ranks as storage 
association argument and add un/pack_class. [PR96992]

Removing the assert in trans-expr, lead to initial strides not set
which is now fixed.  When the array needs repacking, this is done for
class arrays now, too.

Packing class arrays was done using the regular internal pack
function in the past.  But that does not use the vptr's copy
function and breaks OOP paradigms (e.g. deep copy).  The new
un-/pack_class functions use the vptr's copy functionality to
implement OOP paradigms correctly.

PR fortran/96992

gcc/fortran/ChangeLog:

* trans-array.cc (gfc_trans_array_bounds): Set a starting
stride, when descriptor expects a variable for the stride.
(gfc_trans_dummy_array_bias): Allow storage association for
dummy class arrays, when they are not elemental.
(gfc_conv_array_parameter): Add more general class support
and packing for classes, too.
* trans-array.h (gfc_conv_array_parameter): Add lbound shift
for class arrays.
* trans-decl.cc (gfc_build_builtin_function_decls): Add decls
for internal_un-/pack_class.
* trans-expr.cc (gfc_reset_vptr): Allow supplying a type-tree
to generate the vtab from.
(gfc_class_set_vptr): Allow supplying a class-tree to take the
vptr from.
(class_array_data_assign): Rename to gfc_class_array_data_assign
and make usable from other compile units.
(gfc_class_array_data_assign): Renamed from class_array_data_
assign.
(gfc_conv_derived_to_class): Remove assert to
allow converting derived to class type arrays with assumed
rank.  Reduce code base and use gfc_conv_array_parameter also
for classes.
(gfc_conv_class_to_class): Use gfc_class_data_assign.
(gfc_conv_procedure_call): Adapt to new signature of
gfc_conv_derived_to_class.
* trans-io.cc (transfer_expr): Same.
* trans-stmt.cc (trans_associate_var): Same.
* trans.h (gfc_conv_derived_to_class): Signature changed.
(gfc_class_array_data_assign): Made public.
(gfor_fndecl_in_pack_class): Added declaration.
(gfor_fndecl_in_unpack_class): Same.

libgfortran/ChangeLog:

* Makefile.am: Add in_un-/pack_class.c to build.
* Makefile.in: Regenerated from Makefile.am.
* gfortran.map: Added new functions and bumped ABI.
* libgfortran.h (GFC_CLASS_T): Added for generating class
representation at runtime.
* runtime/in_pack_class.c: New file.
* runtime/in_unpack_class.c: New file.

gcc/testsuite/ChangeLog:

* gfortran.dg/class_dummy_11.f90: New test.

Diff:
---
 gcc/fortran/trans-array.cc   | 204 +-
 gcc/fortran/trans-array.h|   5 +-
 gcc/fortran/trans-decl.cc|  16 +-
 gcc/fortran/trans-expr.cc| 242 +--
 gcc/fortran/trans-io.cc  |   4 +-
 gcc/fortran/trans-stmt.cc|   6 +-
 gcc/fortran/trans.h  |   7 +-
 gcc/testsuite/gfortran.dg/class_dummy_11.f90 | 194 +
 libgfortran/Makefile.am  |   4 +-
 libgfortran/Makefile.in  |  13 +-
 libgfortran/gfortran.map |   6 +
 libgfortran/libgfortran.h|  23 +++
 libgfortran/runtime/in_pack_class.c  | 152 +
 libgfortran/runtime/in_unpack_class.c| 134 +++
 14 files changed, 824 insertions(+), 186 deletions(-)

diff --git a/gcc/fortran/trans-array.cc b/gcc/fortran/trans-array.cc
index c7d244689393..ed0ad5429e24 100644
--- a/gcc/fortran/trans-array.cc
+++ b/gcc/fortran/trans-array.cc
@@ -6803,6 +6803,9 @@ gfc_trans_array_bounds (tree type, gfc_symbol * sym, tree 
* poffset,
 
   size = gfc_index_one_node;
   offset = gfc_index_zero_node;
+  stride = GFC_TYPE_ARRAY_STRIDE (type, 0);
+  if (stride && VAR_P (stride))
+gfc_add_modify (pblock, stride, gfc_index_one_node);
   for (dim = 0; dim < as->rank; dim++)
 {
   /* Evaluate non-constant array bound expressions.
@@ -7148,7 +7151,9 @@ gfc_trans_dummy_array_bias (gfc_symbol * sym, tree 
tmpdesc,
   || (is_classarray && CLASS_DATA (sym)->attr.allocatable))
 return;
 
-  if (!is_classarray && sym->attr.dummy && gfc_is_nodesc_array (sym))
+  if ((!is_classarray
+   || (is_classarray && CLASS_DATA (sym)->as->type == AS_EXPLICIT

[gcc r15-1966] [MAINTAINERS] Update my email address and move to DCO.

[Kugan Vivekanandarajah via Gcc-cvs]

https://gcc.gnu.org/g:b38c8fdd82a5b9a550e6ee31502d39cfc3ad9fc8

commit r15-1966-gb38c8fdd82a5b9a550e6ee31502d39cfc3ad9fc8
Author: Kugan Vivekanandarajah 
Date:   Thu Jul 11 19:50:02 2024 +1000

[MAINTAINERS] Update my email address and move to DCO.

* MAINTAINERS: Update my email address.

Signed-off-by: Kugan Vivekanandarajah 

Diff:
---
 MAINTAINERS | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index 762b91256c41..d27640708c52 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -704,7 +704,7 @@ Alex Velenko

 Ilya Verbin
 Andre Vieira   
 Rasmus Villemoes   
-Kugan Vivekanandarajah 
+Kugan Vivekanandarajah 
 Marcel Vollweiler  
 Ville Voutilainen  
 Nenad Vukicevic
@@ -788,6 +788,7 @@ Fangrui Song

 Kyrylo Tkachov 
 Petter Tomner  
 Martin Uecker  
+Kugan Vivekanandarajah 
 Jonathan Wakely
 Alexander Westbrooks   
 Chung-Ju Wu

[gcc r15-1967] RISC-V: Add testcases for vector .SAT_SUB in zip benchmark

[Pan Li via Gcc-cvs]

https://gcc.gnu.org/g:b3c686416e88bf135def0e72d316713af01445a1

commit r15-1967-gb3c686416e88bf135def0e72d316713af01445a1
Author: Pan Li 
Date:   Thu Jul 11 15:54:32 2024 +0800

RISC-V: Add testcases for vector .SAT_SUB in zip benchmark

This patch would like to add the test cases for the vector .SAT_SUB in
the zip benchmark.  Aka:

Form in zip benchmark:
  #define DEF_VEC_SAT_U_SUB_ZIP(T1, T2) \
  void __attribute__((noinline))\
  vec_sat_u_sub_##T1##_##T2##_fmt_zip (T1 *x, T2 b, unsigned limit) \
  { \
T2 a;   \
T1 *p = x;  \
do {\
  a = *--p; \
  *p = (T1)(a >= b ? a - b : 0);\
} while (--limit);  \
  }

DEF_VEC_SAT_U_SUB_ZIP(uint8_t, uint16_t)

vec_sat_u_sub_uint16_t_uint32_t_fmt_zip:
  ...
  vsetvli   a4,zero,e32,m1,ta,ma
  vmv.v.x   v6,a1
  vsetvli   zero,zero,e16,mf2,ta,ma
  vid.v v2
  lia4,-1
  vnclipu.wiv6,v6,0   // .SAT_TRUNC
.L3:
  vle16.v   v3,0(a3)
  vrsub.vx  v5,v2,a6
  mva7,a4
  addw  a4,a4,t3
  vrgather.vv   v1,v3,v5
  vssubu.vv v1,v1,v6  // .SAT_SUB
  vrgather.vv   v3,v1,v5
  vse16.v   v3,0(a3)
  sub   a3,a3,t1
  bgtu  t4,a4,.L3

Passed the rv64gcv tests.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: Add test
helper macros.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_data.h: Add test
data for .SAT_SUB in zip benchmark.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_binary_vx.h: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_zip-run.c: New 
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_zip.c: New test.

Signed-off-by: Pan Li 

Diff:
---
 .../riscv/rvv/autovec/binop/vec_sat_arith.h| 18 +
 .../riscv/rvv/autovec/binop/vec_sat_binary_vx.h| 22 ++
 .../riscv/rvv/autovec/binop/vec_sat_data.h | 81 ++
 .../rvv/autovec/binop/vec_sat_u_sub_zip-run.c  | 16 +
 .../riscv/rvv/autovec/binop/vec_sat_u_sub_zip.c| 18 +
 5 files changed, 155 insertions(+)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h
index 10459807b2c4..416a1e49a47b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h
@@ -322,6 +322,19 @@ vec_sat_u_sub_##T##_fmt_10 (T *out, T *op_1, T *op_2, 
unsigned limit) \
 } \
 }
 
+#define DEF_VEC_SAT_U_SUB_ZIP(T1, T2) \
+void __attribute__((noinline))\
+vec_sat_u_sub_##T1##_##T2##_fmt_zip (T1 *x, T2 b, unsigned limit) \
+{ \
+  T2 a;   \
+  T1 *p = x;  \
+  do {\
+a = *--p; \
+*p = (T1)(a >= b ? a - b : 0);\
+  } while (--limit);  \
+}
+#define DEF_VEC_SAT_U_SUB_ZIP_WRAP(T1, T2) DEF_VEC_SAT_U_SUB_ZIP(T1, T2)
+
 #define RUN_VEC_SAT_U_SUB_FMT_1(T, out, op_1, op_2, N) \
   vec_sat_u_sub_##T##_fmt_1(out, op_1, op_2, N)
 
@@ -352,6 +365,11 @@ vec_sat_u_sub_##T##_fmt_10 (T *out, T *op_1, T *op_2, 
unsigned limit) \
 #define RUN_VEC_SAT_U_SUB_FMT_10(T, out, op_1, op_2, N) \
   vec_sat_u_sub_##T##_fmt_10(out, op_1, op_2, N)
 
+#define RUN_VEC_SAT_U_SUB_FMT_ZIP(T1, T2, x, b, N) \
+  vec_sat_u_sub_##T1##_##T2##_fmt_zip(x, b, N)
+#define RUN_VEC_SAT_U_SUB_FMT_ZIP_WRAP(T1, T2, x, b, N) \
+  RUN_VEC_SAT_U_SUB_FMT_ZIP(T1, T2, x, b, N) \
+
 
/**/
 /* Saturation Sub Truncated (Unsigned and Signed) 
*/
 
/**/
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_binary_vx.h 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_binary_vx.h
new file mode 100644
index ..d238c6392def
--- /dev/null
+++ b/gcc/testsuite/gcc.target/

[gcc r15-1968] c++/modules: Keep entity mapping info across duplicate_decls [PR99241]

[Nathaniel Shead via Gcc-cvs]

https://gcc.gnu.org/g:f04f9714fca40315360af109b9e5ca2305fd75db

commit r15-1968-gf04f9714fca40315360af109b9e5ca2305fd75db
Author: Nathaniel Shead 
Date:   Mon Jul 8 14:35:58 2024 +1000

c++/modules: Keep entity mapping info across duplicate_decls [PR99241]

When duplicate_decls finds a match with an existing imported
declaration, it clears DECL_LANG_SPECIFIC of the olddecl and replaces it
with the contents of newdecl; this clears DECL_MODULE_ENTITY_P causing
an ICE if the same declaration is imported again later.

This fixes the issue by ensuring that the flag is transferred to newdecl
before clearing so that it ends up on olddecl again.

For future-proofing we also do the same with DECL_MODULE_KEYED_DECLS_P,
though because we don't yet support textual redefinition merging we
can't yet test this works as intended.  I don't expect it's possible for
a new declaration already to have extra keyed decls mismatching that of
the old declaration though, so I don't do anything with 'keyed_map' at
this time.

PR c++/99241

gcc/cp/ChangeLog:

* decl.cc (duplicate_decls): Merge module entity information.

gcc/testsuite/ChangeLog:

* g++.dg/modules/pr99241_a.H: New test.
* g++.dg/modules/pr99241_b.H: New test.
* g++.dg/modules/pr99241_c.C: New test.

Signed-off-by: Nathaniel Shead 

Diff:
---
 gcc/cp/decl.cc   | 10 ++
 gcc/testsuite/g++.dg/modules/pr99241_a.H |  3 +++
 gcc/testsuite/g++.dg/modules/pr99241_b.H |  3 +++
 gcc/testsuite/g++.dg/modules/pr99241_c.C |  5 +
 4 files changed, 21 insertions(+)

diff --git a/gcc/cp/decl.cc b/gcc/cp/decl.cc
index d4c65a199329..edf4c155bf77 100644
--- a/gcc/cp/decl.cc
+++ b/gcc/cp/decl.cc
@@ -3139,6 +3139,16 @@ duplicate_decls (tree newdecl, tree olddecl, bool 
hiding, bool was_hidden)
   if (TREE_CODE (newdecl) == FIELD_DECL)
 DECL_PACKED (olddecl) = DECL_PACKED (newdecl);
 
+  /* Merge module entity mapping information.  */
+  if (DECL_LANG_SPECIFIC (olddecl)
+  && (DECL_MODULE_ENTITY_P (olddecl)
+ || DECL_MODULE_KEYED_DECLS_P (olddecl)))
+{
+  retrofit_lang_decl (newdecl);
+  DECL_MODULE_ENTITY_P (newdecl) = DECL_MODULE_ENTITY_P (olddecl);
+  DECL_MODULE_KEYED_DECLS_P (newdecl) = DECL_MODULE_KEYED_DECLS_P 
(olddecl);
+}
+
   /* The DECL_LANG_SPECIFIC information in OLDDECL will be replaced
  with that from NEWDECL below.  */
   if (DECL_LANG_SPECIFIC (olddecl))
diff --git a/gcc/testsuite/g++.dg/modules/pr99241_a.H 
b/gcc/testsuite/g++.dg/modules/pr99241_a.H
new file mode 100644
index ..c7031f08eb5d
--- /dev/null
+++ b/gcc/testsuite/g++.dg/modules/pr99241_a.H
@@ -0,0 +1,3 @@
+// { dg-additional-options "-fmodule-header" }
+// { dg-module-cmi {} }
+void terminate();
diff --git a/gcc/testsuite/g++.dg/modules/pr99241_b.H 
b/gcc/testsuite/g++.dg/modules/pr99241_b.H
new file mode 100644
index ..c7031f08eb5d
--- /dev/null
+++ b/gcc/testsuite/g++.dg/modules/pr99241_b.H
@@ -0,0 +1,3 @@
+// { dg-additional-options "-fmodule-header" }
+// { dg-module-cmi {} }
+void terminate();
diff --git a/gcc/testsuite/g++.dg/modules/pr99241_c.C 
b/gcc/testsuite/g++.dg/modules/pr99241_c.C
new file mode 100644
index ..7f2b1bb43eae
--- /dev/null
+++ b/gcc/testsuite/g++.dg/modules/pr99241_c.C
@@ -0,0 +1,5 @@
+// { dg-additional-options "-fmodules-ts -fno-module-lazy" }
+
+import "pr99241_a.H";
+void terminate();
+import "pr99241_b.H";

[gcc r15-1969] AVR: Tidy up subtract-and-zero_extend insns.

[Georg-Johann Lay via Gcc-cvs]

https://gcc.gnu.org/g:077f16b249346b560169cf89849779272327a2da

commit r15-1969-g077f16b249346b560169cf89849779272327a2da
Author: Georg-Johann Lay 
Date:   Thu Jul 11 13:08:19 2024 +0200

AVR: Tidy up subtract-and-zero_extend insns.

There are these insns that subtract and zero-extend where
the subtrahend is zero-extended to the mode of the minuend.
This patch uses one insn (and split) with mode iterators
instead of spelling out each variant individually.
This has the additional benefit that u32 - u24 is also supported,
which previously wasn't.

gcc/
* config/avr/avr-protos.h (avr_out_minus): New prototype.
* config/avr/avr.cc (avr_out_minus): New function.
* config/avr/avr.md (*sub3.zero_extend.)
(*sub3.zero_extend._split): New insns.
(*subpsi3_zero_extend.qi_split): Remove isns_and_split.
(*subpsi3_zero_extend.hi_split): Remove insn_and_split.
(*subhi3_zero_extend1_split): Remove insn_and_split.
(*subsi3_zero_extend_split): Remove insn_and_split.
(*subsi3_zero_extend.hi_split): Remove insn_and_split.
(*subpsi3_zero_extend.qi): Remove insn.
(*subpsi3_zero_extend.hi): Remove insn.
(*subhi3_zero_extend1): Remove insn.
(*subsi3_zero_extend): Remove insn.
(*subsi3_zero_extend.hi): Remove insn.
gcc/testsuite/
* gcc.target/avr/torture/sub-zerox.c: New test.

Diff:
---
 gcc/config/avr/avr-protos.h  |   1 +
 gcc/config/avr/avr.cc|  32 +-
 gcc/config/avr/avr.md| 122 +--
 gcc/testsuite/gcc.target/avr/torture/sub-zerox.c |  15 +++
 4 files changed, 73 insertions(+), 97 deletions(-)

diff --git a/gcc/config/avr/avr-protos.h b/gcc/config/avr/avr-protos.h
index dc23cfbf461c..6e02161759ca 100644
--- a/gcc/config/avr/avr-protos.h
+++ b/gcc/config/avr/avr-protos.h
@@ -95,6 +95,7 @@ extern void avr_output_addr_vec (rtx_insn*, rtx);
 extern const char *avr_out_sbxx_branch (rtx_insn *insn, rtx operands[]);
 extern const char* avr_out_bitop (rtx, rtx*, int*);
 extern const char* avr_out_plus (rtx, rtx*, int* =NULL, bool =true);
+extern const char* avr_out_minus (rtx*);
 extern const char* avr_out_round (rtx_insn *, rtx*, int* =NULL);
 extern const char* avr_out_addto_sp (rtx*, int*);
 extern const char* avr_out_xload (rtx_insn *, rtx*, int*);
diff --git a/gcc/config/avr/avr.cc b/gcc/config/avr/avr.cc
index d299fceb7824..4a7cbd0e7bc6 100644
--- a/gcc/config/avr/avr.cc
+++ b/gcc/config/avr/avr.cc
@@ -8843,6 +8843,36 @@ lshrsi3_out (rtx_insn *insn, rtx operands[], int *len)
 }
 
 
+/* Output subtraction of integer registers XOP[0] and XOP[2] and return ""
+
+  XOP[0] = XOP[0] - XOP[2]
+
+   where the mode of XOP[0] is in { HI, PSI, SI }, and the mode of
+   XOP[2] is in { QI, HI, PSI }.  When the mode of XOP[0] is larger
+   than the mode of XOP[2], then the latter is zero-extended on the fly.
+   The number of instructions will be the mode size of XOP[0].  */
+
+const char *
+avr_out_minus (rtx *xop)
+{
+  int n_bytes0 = GET_MODE_SIZE (GET_MODE (xop[0]));
+  int n_bytes2 = GET_MODE_SIZE (GET_MODE (xop[2]));
+
+  output_asm_insn ("sub %0,%2", xop);
+
+  for (int i = 1; i < n_bytes0; ++i)
+{
+  rtx op[2];
+  op[0] = all_regs_rtx[i + REGNO (xop[0])];
+  op[1] = (i < n_bytes2) ? all_regs_rtx[i + REGNO (xop[2])] : zero_reg_rtx;
+
+  output_asm_insn ("sbc %0,%1", op);
+}
+
+  return "";
+}
+
+
 /* Output addition of register XOP[0] and compile time constant XOP[2].
INSN is a single_set insn or an insn pattern.
CODE == PLUS:  perform addition by using ADD instructions or
@@ -12717,7 +12747,7 @@ avr_rtx_costs_1 (rtx x, machine_mode mode, int 
outer_code,
  *total = COSTS_N_INSNS (2);
  return true;
}
-  // *sub3_zero_extend1
+  // *sub3.zero_extend.
   if (REG_P (XEXP (x, 0))
  && GET_CODE (XEXP (x, 1)) == ZERO_EXTEND)
{
diff --git a/gcc/config/avr/avr.md b/gcc/config/avr/avr.md
index 2783b8c986f1..8c3e55a91ee0 100644
--- a/gcc/config/avr/avr.md
+++ b/gcc/config/avr/avr.md
@@ -2030,47 +2030,6 @@
   "sub %0,%2\;sbc %B0,%B2\;sbc %C0,%C2"
   [(set_attr "length" "3")])
 
-(define_insn_and_split "*subpsi3_zero_extend.qi_split"
-  [(set (match_operand:PSI 0 "register_operand"   "=r")
-(minus:PSI (match_operand:SI 1 "register_operand"  "0")
-   (zero_extend:PSI (match_operand:QI 2 "register_operand" 
"r"]
-  ""
-  "#"
-  "&& reload_completed"
-  [(parallel [(set (match_dup 0)
-   (minus:PSI (match_dup 1)
-  (zero_extend:PSI (match_dup 2
-  (clobber (reg:CC REG_CC))])])
-
-(define_insn "*subpsi3_zero_extend.qi"
-  [(set (match_operand:PSI 0 "register_operand"   "=r")
-(minus:PSI (ma

[gcc r14-10407] c++/modules: Keep entity mapping info across duplicate_decls [PR99241]

[Nathaniel Shead via Gcc-cvs]

https://gcc.gnu.org/g:08c2abffe0a903e8cf16b469813b7dd0fb41275a

commit r14-10407-g08c2abffe0a903e8cf16b469813b7dd0fb41275a
Author: Nathaniel Shead 
Date:   Mon Jul 8 14:35:58 2024 +1000

c++/modules: Keep entity mapping info across duplicate_decls [PR99241]

When duplicate_decls finds a match with an existing imported
declaration, it clears DECL_LANG_SPECIFIC of the olddecl and replaces it
with the contents of newdecl; this clears DECL_MODULE_ENTITY_P causing
an ICE if the same declaration is imported again later.

This fixes the issue by ensuring that the flag is transferred to newdecl
before clearing so that it ends up on olddecl again.

For future-proofing we also do the same with DECL_MODULE_KEYED_DECLS_P,
though because we don't yet support textual redefinition merging we
can't yet test this works as intended.  I don't expect it's possible for
a new declaration already to have extra keyed decls mismatching that of
the old declaration though, so I don't do anything with 'keyed_map' at
this time.

PR c++/99241

gcc/cp/ChangeLog:

* decl.cc (duplicate_decls): Merge module entity information.

gcc/testsuite/ChangeLog:

* g++.dg/modules/pr99241_a.H: New test.
* g++.dg/modules/pr99241_b.H: New test.
* g++.dg/modules/pr99241_c.C: New test.

Signed-off-by: Nathaniel Shead 
(cherry picked from commit f04f9714fca40315360af109b9e5ca2305fd75db)

Diff:
---
 gcc/cp/decl.cc   | 10 ++
 gcc/testsuite/g++.dg/modules/pr99241_a.H |  3 +++
 gcc/testsuite/g++.dg/modules/pr99241_b.H |  3 +++
 gcc/testsuite/g++.dg/modules/pr99241_c.C |  5 +
 4 files changed, 21 insertions(+)

diff --git a/gcc/cp/decl.cc b/gcc/cp/decl.cc
index 568b2becd4d0..ca00e9aea201 100644
--- a/gcc/cp/decl.cc
+++ b/gcc/cp/decl.cc
@@ -3120,6 +3120,16 @@ duplicate_decls (tree newdecl, tree olddecl, bool 
hiding, bool was_hidden)
   if (TREE_CODE (newdecl) == FIELD_DECL)
 DECL_PACKED (olddecl) = DECL_PACKED (newdecl);
 
+  /* Merge module entity mapping information.  */
+  if (DECL_LANG_SPECIFIC (olddecl)
+  && (DECL_MODULE_ENTITY_P (olddecl)
+ || DECL_MODULE_KEYED_DECLS_P (olddecl)))
+{
+  retrofit_lang_decl (newdecl);
+  DECL_MODULE_ENTITY_P (newdecl) = DECL_MODULE_ENTITY_P (olddecl);
+  DECL_MODULE_KEYED_DECLS_P (newdecl) = DECL_MODULE_KEYED_DECLS_P 
(olddecl);
+}
+
   /* The DECL_LANG_SPECIFIC information in OLDDECL will be replaced
  with that from NEWDECL below.  */
   if (DECL_LANG_SPECIFIC (olddecl))
diff --git a/gcc/testsuite/g++.dg/modules/pr99241_a.H 
b/gcc/testsuite/g++.dg/modules/pr99241_a.H
new file mode 100644
index ..c7031f08eb5d
--- /dev/null
+++ b/gcc/testsuite/g++.dg/modules/pr99241_a.H
@@ -0,0 +1,3 @@
+// { dg-additional-options "-fmodule-header" }
+// { dg-module-cmi {} }
+void terminate();
diff --git a/gcc/testsuite/g++.dg/modules/pr99241_b.H 
b/gcc/testsuite/g++.dg/modules/pr99241_b.H
new file mode 100644
index ..c7031f08eb5d
--- /dev/null
+++ b/gcc/testsuite/g++.dg/modules/pr99241_b.H
@@ -0,0 +1,3 @@
+// { dg-additional-options "-fmodule-header" }
+// { dg-module-cmi {} }
+void terminate();
diff --git a/gcc/testsuite/g++.dg/modules/pr99241_c.C 
b/gcc/testsuite/g++.dg/modules/pr99241_c.C
new file mode 100644
index ..7f2b1bb43eae
--- /dev/null
+++ b/gcc/testsuite/g++.dg/modules/pr99241_c.C
@@ -0,0 +1,5 @@
+// { dg-additional-options "-fmodules-ts -fno-module-lazy" }
+
+import "pr99241_a.H";
+void terminate();
+import "pr99241_b.H";

[gcc r15-1970] Fix gimplification of ordering comparisons of arrays of bytes

[Eric Botcazou via Gcc-cvs]

https://gcc.gnu.org/g:738711703db9f42490f06211a3e8fba07a84dbce

commit r15-1970-g738711703db9f42490f06211a3e8fba07a84dbce
Author: Eric Botcazou 
Date:   Thu Jul 11 10:49:13 2024 +0200

Fix gimplification of ordering comparisons of arrays of bytes

The Ada compiler now defers to the gimplifier for ordering comparisons of
arrays of bytes (Ada parlance for <, >, <= and >=) because the gimplifier
in turn defers to memcmp for them, which implements the required semantics.

However, the gimplifier has a special processing for aggregate types whose
mode is not BLKmode and this processing deviates from the memcmp semantics
when the target is little-endian.

gcc/
* gimplify.cc (gimplify_scalar_mode_aggregate_compare): Add support
for ordering comparisons.
(gimplify_expr) : Call 
gimplify_scalar_mode_aggregate_compare
only for integral scalar modes.

gcc/testsuite/
* gnat.dg/array42.adb, gnat.dg/array42_pkg.ads: New test.

Diff:
---
 gcc/gimplify.cc   | 48 +++
 gcc/testsuite/gnat.dg/array42.adb | 33 
 gcc/testsuite/gnat.dg/array42_pkg.ads | 25 ++
 3 files changed, 101 insertions(+), 5 deletions(-)

diff --git a/gcc/gimplify.cc b/gcc/gimplify.cc
index 5a9627c4acf6..02faaf7114cf 100644
--- a/gcc/gimplify.cc
+++ b/gcc/gimplify.cc
@@ -6728,18 +6728,56 @@ gimplify_variable_sized_compare (tree *expr_p)
 static enum gimplify_status
 gimplify_scalar_mode_aggregate_compare (tree *expr_p)
 {
-  location_t loc = EXPR_LOCATION (*expr_p);
+  const location_t loc = EXPR_LOCATION (*expr_p);
+  const enum tree_code code = TREE_CODE (*expr_p);
   tree op0 = TREE_OPERAND (*expr_p, 0);
   tree op1 = TREE_OPERAND (*expr_p, 1);
-
   tree type = TREE_TYPE (op0);
   tree scalar_type = lang_hooks.types.type_for_mode (TYPE_MODE (type), 1);
 
   op0 = fold_build1_loc (loc, VIEW_CONVERT_EXPR, scalar_type, op0);
   op1 = fold_build1_loc (loc, VIEW_CONVERT_EXPR, scalar_type, op1);
 
-  *expr_p
-= fold_build2_loc (loc, TREE_CODE (*expr_p), TREE_TYPE (*expr_p), op0, 
op1);
+  /* We need to perform ordering comparisons in memory order like memcmp and,
+ therefore, may need to byte-swap operands for little-endian targets.  */
+  if (code != EQ_EXPR && code != NE_EXPR)
+{
+  gcc_assert (BYTES_BIG_ENDIAN == WORDS_BIG_ENDIAN);
+  gcc_assert (TREE_CODE (scalar_type) == INTEGER_TYPE);
+  tree fndecl;
+
+  if (BYTES_BIG_ENDIAN)
+   fndecl = NULL_TREE;
+  else
+   switch (int_size_in_bytes (scalar_type))
+ {
+ case 1:
+   fndecl = NULL_TREE;
+   break;
+ case 2:
+   fndecl = builtin_decl_implicit (BUILT_IN_BSWAP16);
+   break;
+ case 4:
+   fndecl = builtin_decl_implicit (BUILT_IN_BSWAP32);
+   break;
+ case 8:
+   fndecl = builtin_decl_implicit (BUILT_IN_BSWAP64);
+   break;
+ case 16:
+   fndecl = builtin_decl_implicit (BUILT_IN_BSWAP128);
+   break;
+ default:
+   gcc_unreachable ();
+ }
+
+  if (fndecl)
+   {
+ op0 = build_call_expr_loc (loc, fndecl, 1, op0);
+ op1 = build_call_expr_loc (loc, fndecl, 1, op1);
+   }
+}
+
+  *expr_p = fold_build2_loc (loc, code, TREE_TYPE (*expr_p), op0, op1);
 
   return GS_OK;
 }
@@ -18825,7 +18863,7 @@ gimplify_expr (tree *expr_p, gimple_seq *pre_p, 
gimple_seq *post_p,
  else
goto expr_2;
}
- else if (TYPE_MODE (type) != BLKmode)
+ else if (SCALAR_INT_MODE_P (TYPE_MODE (type)))
ret = gimplify_scalar_mode_aggregate_compare (expr_p);
  else
ret = gimplify_variable_sized_compare (expr_p);
diff --git a/gcc/testsuite/gnat.dg/array42.adb 
b/gcc/testsuite/gnat.dg/array42.adb
new file mode 100644
index ..f47f9bb6b922
--- /dev/null
+++ b/gcc/testsuite/gnat.dg/array42.adb
@@ -0,0 +1,33 @@
+-- { dg-do run }
+
+with Array42_Pkg; use Array42_Pkg;
+
+procedure Array42 is
+
+  procedure Raise_Error_If_False (Test : Boolean; N : Positive) is
+  begin
+if not Test then
+  raise Program_Error with "Test" & N'Img & " fails";
+end if;
+  end;
+
+begin
+  Raise_Error_If_False (LT2  ("12", "21"), 1);
+  Raise_Error_If_False (LT4  ("1234", "4321"), 2);
+  Raise_Error_If_False (LT8  ("12345678", "87654321"), 3);
+  Raise_Error_If_False (LT8  ("12345678", "87654321"), 4);
+  Raise_Error_If_False (LT16 ("12345678ABCDEFGH", "HGFEDCBA87654321"), 5);
+
+  Raise_Error_If_False (LT5  ("12345", "54321"), 6);
+  Raise_Error_If_False (LE5  ("12345", "54321"), 7);
+  Raise_Error_If_False (not GT5  ("12345", "54321"), 8);
+  Raise_Error_If_False (not GE5  ("12345", "54321"), 9);
+
+  Raise_Error_If_False (LT45  ("1234", "12345"), 10);
+  Raise_Error_If_Fa

[gcc(refs/users/aoliva/heads/testme)] [libstdc++] [testsuite] xfail 128bit from_chars on all aarch64-*-*

[Alexandre Oliva via Gcc-cvs]

https://gcc.gnu.org/g:e7140d9f2a6451f8101e516b95a46261f7494c56

commit e7140d9f2a6451f8101e516b95a46261f7494c56
Author: Alexandre Oliva 
Date:   Thu Jul 11 09:03:27 2024 -0300

[libstdc++] [testsuite] xfail 128bit from_chars on all aarch64-*-*

Having observed failures of these two tests on yet another aarch64
operating system, and having concluded that the conditions that
trigger the problem ought to be present on all aarch64 targets, I'm
now matching any aarch64 target_os to enable the workaround.


for  libstdc++-v3/ChangeLog

* testsuite/20_util/from_chars/8.cc: Define SKIP_LONG_DOUBLE
on all aarch64-*-* targets.
* testsuite/20_util/to_chars/float128_c++23.cc: Xfail on all
aarch64-*-* targets.

Diff:
---
 libstdc++-v3/testsuite/20_util/from_chars/8.cc| 2 +-
 libstdc++-v3/testsuite/20_util/to_chars/float128_c++23.cc | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/libstdc++-v3/testsuite/20_util/from_chars/8.cc 
b/libstdc++-v3/testsuite/20_util/from_chars/8.cc
index bacad89943b5..e92b64349025 100644
--- a/libstdc++-v3/testsuite/20_util/from_chars/8.cc
+++ b/libstdc++-v3/testsuite/20_util/from_chars/8.cc
@@ -17,7 +17,7 @@
 
 // { dg-do run { target c++23 } }
 // { dg-add-options ieee }
-// { dg-additional-options "-DSKIP_LONG_DOUBLE" { target aarch64-*-vxworks* 
aarch64-*-rtems* } }
+// { dg-additional-options "-DSKIP_LONG_DOUBLE" { target aarch64-*-* } }
 
 #include 
 #include 
diff --git a/libstdc++-v3/testsuite/20_util/to_chars/float128_c++23.cc 
b/libstdc++-v3/testsuite/20_util/to_chars/float128_c++23.cc
index 6cb9cadcd204..840131c1e569 100644
--- a/libstdc++-v3/testsuite/20_util/to_chars/float128_c++23.cc
+++ b/libstdc++-v3/testsuite/20_util/to_chars/float128_c++23.cc
@@ -19,7 +19,7 @@
 // { dg-require-effective-target ieee_floats }
 // { dg-require-effective-target size32plus }
 // { dg-add-options ieee }
-// { dg-xfail-run-if "from_chars limited to double-precision" { 
aarch64-*-vxworks* aarch64-*-rtems* } }
+// { dg-xfail-run-if "from_chars limited to double-precision" { aarch64-*-* } }
 
 #include 
 #include 

[gcc(refs/users/aoliva/heads/testme)] [libstdc++] [testsuite] require dfprt on some tests

[Alexandre Oliva via Gcc-cvs]

https://gcc.gnu.org/g:35b8b9ad5a3db3089074fc7c9cd7b91b9fd5cedf

commit 35b8b9ad5a3db3089074fc7c9cd7b91b9fd5cedf
Author: Alexandre Oliva 
Date:   Thu Jul 11 09:04:02 2024 -0300

[libstdc++] [testsuite] require dfprt on some tests

On a target that doesn't enable decimal float components in libgcc
(because the libc doens't define all required FE_* macros), but whose
compiler supports _Decimal* types, the effective target requirement
dfp passes, but several tests won't link because the runtime support
they depend on is missing.  State their dfprt requirement.


for  libstdc++-v3/ChangeLog

* testsuite/decimal/binary-arith.cc: Require dfprt.
* testsuite/decimal/comparison.cc: Likewise.
* testsuite/decimal/compound-assignment-memfunc.cc: Likewise.
* testsuite/decimal/make-decimal.cc: Likewise.
* testsuite/decimal/pr54036-1.cc: Likewise.
* testsuite/decimal/pr54036-2.cc: Likewise.
* testsuite/decimal/pr54036-3.cc: Likewise.
* testsuite/decimal/unary-arith.cc: Likewise.

Diff:
---
 libstdc++-v3/testsuite/decimal/binary-arith.cc| 2 +-
 libstdc++-v3/testsuite/decimal/comparison.cc  | 2 +-
 libstdc++-v3/testsuite/decimal/compound-assignment-memfunc.cc | 2 +-
 libstdc++-v3/testsuite/decimal/compound-assignment.cc | 2 +-
 libstdc++-v3/testsuite/decimal/make-decimal.cc| 2 +-
 libstdc++-v3/testsuite/decimal/pr54036-1.cc   | 2 +-
 libstdc++-v3/testsuite/decimal/pr54036-2.cc   | 2 +-
 libstdc++-v3/testsuite/decimal/pr54036-3.cc   | 2 +-
 libstdc++-v3/testsuite/decimal/unary-arith.cc | 2 +-
 9 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/libstdc++-v3/testsuite/decimal/binary-arith.cc 
b/libstdc++-v3/testsuite/decimal/binary-arith.cc
index c10a8b6466cb..3eeed7ea9750 100644
--- a/libstdc++-v3/testsuite/decimal/binary-arith.cc
+++ b/libstdc++-v3/testsuite/decimal/binary-arith.cc
@@ -15,7 +15,7 @@
 // with this library; see the file COPYING3.  If not see
 // .
 
-// { dg-require-effective-target dfp }
+// { dg-require-effective-target dfprt }
 
 // ISO/IEC TR 24733  3.2.8  Binary arithmetic operators.
 
diff --git a/libstdc++-v3/testsuite/decimal/comparison.cc 
b/libstdc++-v3/testsuite/decimal/comparison.cc
index cf34c8d74bad..424dd8bd2665 100644
--- a/libstdc++-v3/testsuite/decimal/comparison.cc
+++ b/libstdc++-v3/testsuite/decimal/comparison.cc
@@ -15,7 +15,7 @@
 // with this library; see the file COPYING3.  If not see
 // .
 
-// { dg-require-effective-target dfp }
+// { dg-require-effective-target dfprt }
 
 // ISO/IEC TR 24733  3.2.9  Comparison operators.
 
diff --git a/libstdc++-v3/testsuite/decimal/compound-assignment-memfunc.cc 
b/libstdc++-v3/testsuite/decimal/compound-assignment-memfunc.cc
index 817d4bb10b1e..d520af9a68d4 100644
--- a/libstdc++-v3/testsuite/decimal/compound-assignment-memfunc.cc
+++ b/libstdc++-v3/testsuite/decimal/compound-assignment-memfunc.cc
@@ -15,7 +15,7 @@
 // with this library; see the file COPYING3.  If not see
 // .
 
-// { dg-require-effective-target dfp }
+// { dg-require-effective-target dfprt }
 
 // ISO/IEC TR 24733  3.2.2.6  Compound assignment (decimal32).
 // ISO/IEC TR 24733  3.2.3.6  Compound assignment (decimal64).
diff --git a/libstdc++-v3/testsuite/decimal/compound-assignment.cc 
b/libstdc++-v3/testsuite/decimal/compound-assignment.cc
index 2d3e32585698..5aa87e78a739 100644
--- a/libstdc++-v3/testsuite/decimal/compound-assignment.cc
+++ b/libstdc++-v3/testsuite/decimal/compound-assignment.cc
@@ -15,7 +15,7 @@
 // with this library; see the file COPYING3.  If not see
 // .
 
-// { dg-require-effective-target dfp }
+// { dg-require-effective-target dfprt }
 
 // ISO/IEC TR 24733  3.2.2.6  Compound assignment (decimal32).
 // ISO/IEC TR 24733  3.2.3.6  Compound assignment (decimal64).
diff --git a/libstdc++-v3/testsuite/decimal/make-decimal.cc 
b/libstdc++-v3/testsuite/decimal/make-decimal.cc
index aa75ac89d479..560196cb305e 100644
--- a/libstdc++-v3/testsuite/decimal/make-decimal.cc
+++ b/libstdc++-v3/testsuite/decimal/make-decimal.cc
@@ -15,7 +15,7 @@
 // with this library; see the file COPYING3.  If not see
 // .
 
-// { dg-require-effective-target dfp }
+// { dg-require-effective-target dfprt }
 // { dg-options "-Wno-pedantic" }
 
 // ISO/IEC TR 24733  3.2.5  Initialization from coefficient and exponent.
diff --git a/libstdc++-v3/testsuite/decimal/pr54036-1.cc 
b/libstdc++-v3/testsuite/decimal/pr54036-1.cc
index 508738701ca0..a07e4c351651 100644
--- a/libstdc++-v3/testsuite/decimal/pr54036-1.cc
+++ b/libstdc++-v3/testsuite/decimal/pr54036-1.cc
@@ -15,7 +15,7 @@
 // with this library; see the file COPYING3.  If not see
 // .
 
-/

[gcc(refs/users/aoliva/heads/testme)] [analyzer] [testsuite] avoid unexpected null dereference warning

[Alexandre Oliva via Gcc-cvs]

https://gcc.gnu.org/g:3b1df514951940298acd6b602f629027066af1c0

commit 3b1df514951940298acd6b602f629027066af1c0
Author: Alexandre Oliva 
Date:   Thu Jul 11 09:04:38 2024 -0300

[analyzer] [testsuite] avoid unexpected null dereference warning

The analyzer testsuite, on a customer's own operating system, reports
a potential NULL pointer dereference in flex-without-call-summaries.c.
I'm not sure why it shows up on that system, but not on others, but
the test is not meant to test for that warning, so I'm silencing it.


for  gcc/testsuite/ChangeLog

* c-c++-common/analyzer/flex-without-call-summaries.c: Disable
null dereference analyzer warnings.

Diff:
---
 gcc/testsuite/c-c++-common/analyzer/flex-without-call-summaries.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/gcc/testsuite/c-c++-common/analyzer/flex-without-call-summaries.c 
b/gcc/testsuite/c-c++-common/analyzer/flex-without-call-summaries.c
index c6ecb25d25d5..1aad2bc896b7 100644
--- a/gcc/testsuite/c-c++-common/analyzer/flex-without-call-summaries.c
+++ b/gcc/testsuite/c-c++-common/analyzer/flex-without-call-summaries.c
@@ -3,6 +3,7 @@
 
 /* { dg-additional-options "-fno-analyzer-call-summaries" } */
 
+/* { dg-additional-options "-Wno-analyzer-null-dereference" } */
 /* { dg-additional-options "-Wno-analyzer-too-complex" } */
 /* { dg-additional-options "-D_POSIX_SOURCE" } */

[gcc(refs/users/aoliva/heads/testme)] [libstdc++] [testsuite] avoid arbitrary errno codes

[Alexandre Oliva via Gcc-cvs]

https://gcc.gnu.org/g:2f1f926425b4e3cd5e7e48b86e03bb3613b5aa54

commit 2f1f926425b4e3cd5e7e48b86e03bb3613b5aa54
Author: Alexandre Oliva 
Date:   Thu Jul 11 09:04:11 2024 -0300

[libstdc++] [testsuite] avoid arbitrary errno codes

Passing an arbitrary error number to strerror* functions doesn't seem
to be portable; 19_diagnostics/system_error/cons-1.cc is hitting
runtime errors in the block that attempts to instantiate a
std:;system_error for error number 95.  The range of errno macros
defined on this target doesn't reach 95.

I'm changing the test to try to use a couple of select error codes,
falling back to a lower error number if neither are present.
Hopefully this doesn't change the nature of what is being tested for.


for  libstdc++-v3/ChangeLog

* testsuite/19_diagnostics/system_error/cons-1.cc: Use lower
error numbers, preferring some macro-defined ones.

Diff:
---
 .../testsuite/19_diagnostics/system_error/cons-1.cc| 14 --
 1 file changed, 12 insertions(+), 2 deletions(-)

diff --git a/libstdc++-v3/testsuite/19_diagnostics/system_error/cons-1.cc 
b/libstdc++-v3/testsuite/19_diagnostics/system_error/cons-1.cc
index 16aa960b2ee2..e227c6754241 100644
--- a/libstdc++-v3/testsuite/19_diagnostics/system_error/cons-1.cc
+++ b/libstdc++-v3/testsuite/19_diagnostics/system_error/cons-1.cc
@@ -37,8 +37,18 @@ int main()
 
   // 2
   {
-std::system_error err2(95, std::system_category(), s);
-VERIFY( err2.code() == std::error_code(95, std::system_category()) );
+int eno;
+#if defined EOPNOTSUPP
+eno = EOPNOTSUPP;
+#elif defined ENOSYS
+eno = ENOSYS;
+#else
+// strerror (used to combine with the given message) may fail if
+// the error number is out of range for the system.
+eno = 42;
+#endif
+std::system_error err2(eno, std::system_category(), s);
+VERIFY( err2.code() == std::error_code(eno, std::system_category()) );
 VERIFY( std::string((err2.what(), s)).find(s) != std::string::npos );
   }

[gcc r15-1971] Fix bootstrap broken by gcc-15-1965-ge4f2f46e015

[Andre Vehreschild via Gcc-cvs]

https://gcc.gnu.org/g:b9513c6746bfdbbb2f5e2a52bc3504236692beeb

commit r15-1971-gb9513c6746bfdbbb2f5e2a52bc3504236692beeb
Author: Andre Vehreschild 
Date:   Thu Jul 11 11:21:04 2024 +0200

Fix bootstrap broken by gcc-15-1965-ge4f2f46e015

gcc/fortran/ChangeLog:

* trans-array.cc (gfc_conv_array_parameter): Init variable to
NULL_TREE to fix bootstrap.

Diff:
---
 gcc/fortran/trans-array.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/fortran/trans-array.cc b/gcc/fortran/trans-array.cc
index ed0ad5429e24..140d933e45d4 100644
--- a/gcc/fortran/trans-array.cc
+++ b/gcc/fortran/trans-array.cc
@@ -8662,7 +8662,7 @@ gfc_conv_array_parameter (gfc_se *se, gfc_expr *expr, 
bool g77,
   tree stmt;
   tree parent = DECL_CONTEXT (current_function_decl);
   tree ctree;
-  tree pack_attr;
+  tree pack_attr = NULL_TREE; /* Set when packing class arrays.  */
   bool full_array_var;
   bool this_array_result;
   bool contiguous;

[gcc r15-1972] recog: Avoid validate_change shortcut for groups [PR115782]

[Richard Sandiford via Gcc-cvs]

https://gcc.gnu.org/g:44fc801e97a8dc626a4806ff4124439003420b20

commit r15-1972-g44fc801e97a8dc626a4806ff4124439003420b20
Author: Richard Sandiford 
Date:   Thu Jul 11 14:44:11 2024 +0100

recog: Avoid validate_change shortcut for groups [PR115782]

In this PR, due to the -f flags, we ended up with:

bb1:  r10=r10
...
bb2:  r10=r10
...
bb3:  ...=r10

with bb1->bb2 and bb1->bb3.

late-combine successfully combined the bb1->bb2 def-use and set
the insn code to NOOP_MOVE_INSN_CODE.  The bb1->bb3 combination
then failed for... reasons.  At this point, everything should have
been rewound to its original state.

However, substituting r10=r10 into r10=r10 gives r10=r10, and
validate_change had an early-out for no-op rtl changes.  This meant
that validate_change did not register a change for the bb2 insn and
so did not save its old insn code.  The NOOP_MOVE_INSN_CODE therefore
persisted even after the attempt had been rewound.

IMO it'd be too cumbersome and error-prone to expect all users of
validate_change to be aware of this possibility.  If code is using
validate_change with in_group=1, I think it has a reasonable expectation
that a change will be registered and that the insn code will be saved
(and restored on cancel).  This patch therefore limits the shortcut
to the !in_group case.

gcc/
PR rtl-optimization/115782
* recog.cc (validate_change_1): Suppress early exit for no-op
changes that are part of a group.

gcc/testsuite/
PR rtl-optimization/115782
* gcc.dg/pr115782.c: New test.

Diff:
---
 gcc/recog.cc|  7 ++-
 gcc/testsuite/gcc.dg/pr115782.c | 23 +++
 2 files changed, 29 insertions(+), 1 deletion(-)

diff --git a/gcc/recog.cc b/gcc/recog.cc
index 36507f3f57ce..7710c55b7452 100644
--- a/gcc/recog.cc
+++ b/gcc/recog.cc
@@ -230,7 +230,12 @@ validate_change_1 (rtx object, rtx *loc, rtx new_rtx, bool 
in_group,
   new_len = -1;
 }
 
-  if ((old == new_rtx || rtx_equal_p (old, new_rtx))
+  /* When a change is part of a group, callers expect to be able to change
+ INSN_CODE after making the change and have the code reset to its old
+ value by a later cancel_changes.  We therefore need to register group
+ changes even if they're no-ops.  */
+  if (!in_group
+  && (old == new_rtx || rtx_equal_p (old, new_rtx))
   && (new_len < 0 || XVECLEN (new_rtx, 0) == new_len))
 return true;
 
diff --git a/gcc/testsuite/gcc.dg/pr115782.c b/gcc/testsuite/gcc.dg/pr115782.c
new file mode 100644
index ..f4d11cc6d0f9
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/pr115782.c
@@ -0,0 +1,23 @@
+// { dg-require-effective-target lp64 }
+// { dg-options "-O2 -fno-guess-branch-probability -fgcse-sm 
-fno-expensive-optimizations -fno-gcse" }
+
+int printf(const char *, ...);
+int a, b, c, d, e, f, g, i, j, m, h;
+long k, l, n, o;
+int main() {
+  int p = e, r = i << a, q = r & b;
+  k = 4073709551613;
+  l = m = c = -(c >> j);
+  d = g ^ h ^ 4073709551613;
+  n = q - h;
+  o = ~d;
+  f = c * 4073709551613 / 409725 ^ r;
+  if ((n && m) || (q && j) || a)
+return 0;
+  d = o | p;
+  if (g)
+printf("0");
+  d = p;
+  c++;
+  return 0;
+}

[gcc(refs/users/matz/heads/x86-ssw)] Revert "Add target hook shrink_wrap.cleanup_components"

[Michael Matz via Gcc-cvs]

https://gcc.gnu.org/g:3b04b651551abc541c6ec21835d2e85a407bb1c4

commit 3b04b651551abc541c6ec21835d2e85a407bb1c4
Author: Michael Matz 
Date:   Thu Jul 11 15:16:57 2024 +0200

Revert "Add target hook shrink_wrap.cleanup_components"

This reverts commit 826dd85cb9f368608a9890046cd701f7530d7315.

I found a better way to solve the problem.

Diff:
---
 gcc/config/i386/i386.cc | 17 -
 gcc/doc/tm.texi |  8 
 gcc/doc/tm.texi.in  |  2 --
 gcc/shrink-wrap.cc  | 10 --
 gcc/target.def  | 10 --
 5 files changed, 47 deletions(-)

diff --git a/gcc/config/i386/i386.cc b/gcc/config/i386/i386.cc
index 36202b7dcb07..8c9505d53a75 100644
--- a/gcc/config/i386/i386.cc
+++ b/gcc/config/i386/i386.cc
@@ -10927,21 +10927,6 @@ ix86_disqualify_components (sbitmap components, edge 
e, sbitmap, bool)
 bitmap_clear_bit (components, SW_FRAME);
 }
 
-/* Implements TARGET_SHRINK_WRAP_CLEANUP_COMPONENTS.  The infrastructure
-   has removed some components (noted in REMOVED), this cleans out any
-   further components that can't be shrink wrapped separately
-   anymore.  */
-
-static void
-ix86_cleanup_components (sbitmap components, sbitmap removed)
-{
-  /* If separate shrink wrapping removed any register components
- then we must also removed SW_FRAME.  */
-  bitmap_clear_bit (removed, SW_FRAME);
-  if (!bitmap_empty_p (removed))
-bitmap_clear_bit (components, SW_FRAME);
-}
-
 /* Helper for frame allocation.  This resets cfun->machine->fs to
reflect the state at the first instruction before prologue (i.e.
the call just happened).  */
@@ -11122,8 +11107,6 @@ ix86_set_handled_components (sbitmap)
 #define TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB ix86_components_for_bb
 #undef TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS
 #define TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS ix86_disqualify_components
-#undef TARGET_SHRINK_WRAP_CLEANUP_COMPONENTS
-#define TARGET_SHRINK_WRAP_CLEANUP_COMPONENTS ix86_cleanup_components
 #undef TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS
 #define TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS 
ix86_emit_prologue_components
 #undef TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS
diff --git a/gcc/doc/tm.texi b/gcc/doc/tm.texi
index 201c8b9f94da..c8b8b126b242 100644
--- a/gcc/doc/tm.texi
+++ b/gcc/doc/tm.texi
@@ -5352,14 +5352,6 @@ components in @var{edge_components} that the target 
cannot handle on edge
 epilogue instead.
 @end deftypefn
 
-@deftypefn {Target Hook} void TARGET_SHRINK_WRAP_CLEANUP_COMPONENTS (sbitmap 
@var{components}, sbitmap @var{removed})
-This hook is called after the shrink wrapping infrastructure disqualified
-components for various reasons (e.g. because an unsplittable edge would
-have to be split).  If there are interdependencies between components the
-target can remove those from @var{components} whose dependencies are in
-@var{removed}.  If this hook would do nothing it doesn't need to be defined.
-@end deftypefn
-
 @deftypefn {Target Hook} void TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS 
(sbitmap)
 Emit prologue insns for the components indicated by the parameter.
 @end deftypefn
diff --git a/gcc/doc/tm.texi.in b/gcc/doc/tm.texi.in
index f23e6ff3e455..658e1e63371e 100644
--- a/gcc/doc/tm.texi.in
+++ b/gcc/doc/tm.texi.in
@@ -3787,8 +3787,6 @@ generic code.
 
 @hook TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS
 
-@hook TARGET_SHRINK_WRAP_CLEANUP_COMPONENTS
-
 @hook TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS
 
 @hook TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS
diff --git a/gcc/shrink-wrap.cc b/gcc/shrink-wrap.cc
index db5c1f24d11c..2bec492c2a57 100644
--- a/gcc/shrink-wrap.cc
+++ b/gcc/shrink-wrap.cc
@@ -1432,9 +1432,6 @@ disqualify_problematic_components (sbitmap components)
 {
   auto_sbitmap pro (SBITMAP_SIZE (components));
   auto_sbitmap epi (SBITMAP_SIZE (components));
-  auto_sbitmap old (SBITMAP_SIZE (components));
-
-  bitmap_copy (old, components);
 
   basic_block bb;
   FOR_EACH_BB_FN (bb, cfun)
@@ -1499,13 +1496,6 @@ disqualify_problematic_components (sbitmap components)
}
}
 }
-
-  /* If the target needs to know that we removed some components,
- tell it.  */
-  bitmap_and_compl (old, old, components);
-  if (targetm.shrink_wrap.cleanup_components
-  && !bitmap_empty_p (old))
-targetm.shrink_wrap.cleanup_components (components, old);
 }
 
 /* Place code for prologues and epilogues for COMPONENTS where we can put
diff --git a/gcc/target.def b/gcc/target.def
index ac26e8ed38d7..fdad7bbc93e2 100644
--- a/gcc/target.def
+++ b/gcc/target.def
@@ -6872,16 +6872,6 @@ epilogue instead.",
  void, (sbitmap components, edge e, sbitmap edge_components, bool is_prologue),
  NULL)
 
-DEFHOOK
-(cleanup_components,
- "This hook is called after the shrink wrapping infrastructure disqualified\n\
-components for various reasons (e.g. because an unsplittable edge would\n\
-have to be split).  If there are interdependencies between components the\n\
-target can remove those from @v

[gcc(refs/users/matz/heads/x86-ssw)] x86-ssw: Deal with deallocated frame in epilogue

[Michael Matz via Gcc-cvs]

https://gcc.gnu.org/g:fbf3ff6bc169639a2d55ab4ed5f962201ad6416e

commit fbf3ff6bc169639a2d55ab4ed5f962201ad6416e
Author: Michael Matz 
Date:   Thu Jul 11 15:21:05 2024 +0200

x86-ssw: Deal with deallocated frame in epilogue

When the frame is deallocated separately we need to adjust
frame_state.sp_offset to be correct before emitting the rest
of the standard epilogue.

Diff:
---
 gcc/config/i386/i386.cc | 5 +
 1 file changed, 5 insertions(+)

diff --git a/gcc/config/i386/i386.cc b/gcc/config/i386/i386.cc
index 8c9505d53a75..847c6116884b 100644
--- a/gcc/config/i386/i386.cc
+++ b/gcc/config/i386/i386.cc
@@ -9931,6 +9931,11 @@ ix86_expand_epilogue (int style)
   else
 restore_regs_via_mov = false;
 
+  /* If we've (de)allocated the frame separately, then that's done already,
+ and SP is in fact at a word offset.  */
+  if (m->frame_alloc_separately)
+m->fs.sp_offset = UNITS_PER_WORD;
+
   if (restore_regs_via_mov || frame.nsseregs)
 {
   /* Ensure that the entire register save area is addressable via

[gcc r15-1973] mve: Fix vsetq_lane for 64-bit elements with lane 1 [PR 115611]

[Andre Simoes Dias Vieira via Gcc-cvs]

https://gcc.gnu.org/g:7c11fdd2cc11a7058e9643b6abf27831970ad2c9

commit r15-1973-g7c11fdd2cc11a7058e9643b6abf27831970ad2c9
Author: Andre Vieira 
Date:   Thu Jul 11 15:38:45 2024 +0100

mve: Fix vsetq_lane for 64-bit elements with lane 1 [PR 115611]

This patch fixes the backend pattern that was printing the wrong input
scalar register pair when inserting into lane 1.

Added a new test to force float-abi=hard so we can use scan-assembler to 
check
correct codegen.

gcc/ChangeLog:

PR target/115611
* config/arm/mve.md (mve_vec_setv2di_internal): Fix printing of 
input
scalar register pair when lane = 1.

gcc/testsuite/ChangeLog:

* gcc.target/arm/mve/intrinsics/vsetq_lane_su64.c: New test.

Diff:
---
 gcc/config/arm/mve.md  |  2 +-
 .../arm/mve/intrinsics/vsetq_lane_su64.c   | 63 ++
 2 files changed, 64 insertions(+), 1 deletion(-)

diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
index 4b4d6298ffb1..706a45c7d665 100644
--- a/gcc/config/arm/mve.md
+++ b/gcc/config/arm/mve.md
@@ -6505,7 +6505,7 @@
   if (elt == 0)
return "vmov\t%e0, %Q1, %R1";
   else
-   return "vmov\t%f0, %J1, %K1";
+   return "vmov\t%f0, %Q1, %R1";
 }
  [(set_attr "type" "mve_move")])
 
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_su64.c 
b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_su64.c
new file mode 100644
index ..5aa3bc9a76a0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_su64.c
@@ -0,0 +1,63 @@
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-require-effective-target arm_hard_ok } */
+/* { dg-additional-options "-mfloat-abi=hard -O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "arm_mve.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**fn1:
+** vmovd0, r0, r1
+** bx  lr
+*/
+uint64x2_t
+fn1 (uint64_t a, uint64x2_t b)
+{
+  return vsetq_lane_u64 (a, b, 0);
+}
+
+/*
+**fn2:
+** vmovd1, r0, r1
+** bx  lr
+*/
+uint64x2_t
+fn2 (uint64_t a, uint64x2_t b)
+{
+  return vsetq_lane_u64 (a, b, 1);
+}
+
+/*
+**fn3:
+** vmovd0, r0, r1
+** bx  lr
+*/
+int64x2_t
+fn3 (int64_t a, int64x2_t b)
+{
+  return vsetq_lane_s64 (a, b, 0);
+}
+
+/*
+**fn4:
+** vmovd1, r0, r1
+** bx  lr
+*/
+int64x2_t
+fn4 (int64_t a, int64x2_t b)
+{
+  return vsetq_lane_s64 (a, b, 1);
+}
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
+

[gcc r15-1974] libstdc++: Disable expensive test for debug mode [PR108636]

[Jonathan Wakely via Libstdc++-cvs]

https://gcc.gnu.org/g:8dbc02ba43d9e89056f4ba21d664118377f7da40

commit r15-1974-g8dbc02ba43d9e89056f4ba21d664118377f7da40
Author: Jonathan Wakely 
Date:   Thu Jul 11 09:40:12 2024 +0100

libstdc++: Disable expensive test for debug mode [PR108636]

This test uses -fkeep-inline-functions and with debug mode enabled that
compiles much slower and times out if the system is under heavy load.

The original problem being tested is independent of debug mode, so just
require normal mode for the test.

libstdc++-v3/ChangeLog:

PR libstdc++/108636
* testsuite/27_io/filesystem/path/108636.cc: Require normal
mode.

Diff:
---
 libstdc++-v3/testsuite/27_io/filesystem/path/108636.cc | 1 +
 1 file changed, 1 insertion(+)

diff --git a/libstdc++-v3/testsuite/27_io/filesystem/path/108636.cc 
b/libstdc++-v3/testsuite/27_io/filesystem/path/108636.cc
index 73742df93b05..48435525d363 100644
--- a/libstdc++-v3/testsuite/27_io/filesystem/path/108636.cc
+++ b/libstdc++-v3/testsuite/27_io/filesystem/path/108636.cc
@@ -1,6 +1,7 @@
 // { dg-do link { target c++17 } }
 // { dg-options "-fkeep-inline-functions" }
 // { dg-require-filesystem-ts "" }
+// { dg-require-normal-mode "too slow with debug mode" }
 
 #include 
 int main()

[gcc r15-1975] Ranger: Mark a few classes as final

[Andrew Pinski via Gcc-cvs]

https://gcc.gnu.org/g:4e0aa05f67cf79729c2a8c20236de885f2e393d1

commit r15-1975-g4e0aa05f67cf79729c2a8c20236de885f2e393d1
Author: Andrew Pinski 
Date:   Fri Jun 21 21:07:26 2024 -0700

Ranger: Mark a few classes as final

I noticed there was a warning from clang about int_range's
dtor being marked as final saying the class cannot be inherited from.
So let's mark the few ranger classes as final for those which we know
will be final.

Bootstrapped and tested on x86_64-linux-gnu.

gcc/ChangeLog:

* value-range.h (class int_range): Mark as final.
(class prange): Likewise.
(class frange): Likewise.

Signed-off-by: Andrew Pinski 

Diff:
---
 gcc/value-range.h | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/gcc/value-range.h b/gcc/value-range.h
index 4a8d69f34084..334ea1bc338c 100644
--- a/gcc/value-range.h
+++ b/gcc/value-range.h
@@ -363,7 +363,7 @@ protected:
 // HARD_MAX_RANGES.  This new storage is freed upon destruction.
 
 template
-class int_range : public irange
+class int_range final : public irange
 {
 public:
   int_range ();
@@ -380,7 +380,7 @@ private:
   wide_int m_ranges[N*2];
 };
 
-class prange : public vrange
+class prange final : public vrange
 {
   friend class prange_storage;
   friend class vrange_printer;
@@ -523,7 +523,7 @@ nan_state::neg_p () const
 // The representation is a type with a couple of endpoints, unioned
 // with the set of { -NAN, +Nan }.
 
-class frange : public vrange
+class frange final : public vrange
 {
   friend class frange_storage;
   friend class vrange_printer;

[gcc r11-11570] mve: Fix vsetq_lane for 64-bit elements with lane 1 [PR 115611]

[Andre Simoes Dias Vieira via Gcc-cvs]

https://gcc.gnu.org/g:f75f9827cce522a58ae5d0bf47e2e1ea2704150a

commit r11-11570-gf75f9827cce522a58ae5d0bf47e2e1ea2704150a
Author: Andre Vieira 
Date:   Thu Jul 11 15:38:45 2024 +0100

mve: Fix vsetq_lane for 64-bit elements with lane 1 [PR 115611]

This patch fixes the backend pattern that was printing the wrong input
scalar register pair when inserting into lane 1.

Added a new test to force float-abi=hard so we can use scan-assembler to 
check
correct codegen.

gcc/ChangeLog:

PR target/115611
* config/arm/mve.md (mve_vec_setv2di_internal): Fix printing of 
input
scalar register pair when lane = 1.

gcc/testsuite/ChangeLog:

* gcc.target/arm/mve/intrinsics/vsetq_lane_su64.c: New test.

(cherry picked from commit 7c11fdd2cc11a7058e9643b6abf27831970ad2c9)

Diff:
---
 gcc/config/arm/mve.md  |  2 +-
 .../arm/mve/intrinsics/vsetq_lane_su64.c   | 63 ++
 2 files changed, 64 insertions(+), 1 deletion(-)

diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
index 1935813e4744..c5424973b667 100644
--- a/gcc/config/arm/mve.md
+++ b/gcc/config/arm/mve.md
@@ -10510,7 +10510,7 @@
   if (elt == 0)
return "vmov\t%e0, %Q1, %R1";
   else
-   return "vmov\t%f0, %J1, %K1";
+   return "vmov\t%f0, %Q1, %R1";
 }
  [(set_attr "type" "mve_move")])
 
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_su64.c 
b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_su64.c
new file mode 100644
index ..5aa3bc9a76a0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_su64.c
@@ -0,0 +1,63 @@
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-require-effective-target arm_hard_ok } */
+/* { dg-additional-options "-mfloat-abi=hard -O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "arm_mve.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**fn1:
+** vmovd0, r0, r1
+** bx  lr
+*/
+uint64x2_t
+fn1 (uint64_t a, uint64x2_t b)
+{
+  return vsetq_lane_u64 (a, b, 0);
+}
+
+/*
+**fn2:
+** vmovd1, r0, r1
+** bx  lr
+*/
+uint64x2_t
+fn2 (uint64_t a, uint64x2_t b)
+{
+  return vsetq_lane_u64 (a, b, 1);
+}
+
+/*
+**fn3:
+** vmovd0, r0, r1
+** bx  lr
+*/
+int64x2_t
+fn3 (int64_t a, int64x2_t b)
+{
+  return vsetq_lane_s64 (a, b, 0);
+}
+
+/*
+**fn4:
+** vmovd1, r0, r1
+** bx  lr
+*/
+int64x2_t
+fn4 (int64_t a, int64x2_t b)
+{
+  return vsetq_lane_s64 (a, b, 1);
+}
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
+

[gcc(refs/users/meissner/heads/work171-bugs)] Do not build IEEE 128-bit libgcc support if VSX is not available.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:aef0a6f0f0df4c1d91e133145540e0f7e7ff171c

commit aef0a6f0f0df4c1d91e133145540e0f7e7ff171c
Author: Michael Meissner 
Date:   Thu Jul 11 12:54:32 2024 -0400

Do not build IEEE 128-bit libgcc support if VSX is not available.

In the past, we would build libgcc and eable the float128 libraries by 
adding
-mvsx -mabi=altivec to build the support libraries.  However, this causes
problems if the default cpu is a 7450.

With this fix, in order to build the float128 support, the compiler must be
configured to default to at least power7 to enable using the VSX register 
set,
which is required for passing float128 values.

If somebody wanted to enable float128 on big endian systems, they would 
need to
use a compiler that defaults to at least power7.

2024-07-11  Michael Meissner  

libgcc/

PR target/115800
PR target/113652
* config.host (powerpc*-*-linux*): Do not enable the float128 
hardware
and float128 power10 hardware support unless the basic float128 
support
is added.
* configure.ac (powerpc*-*-linux*): Don't enable IEEE 128-bit on 
PowerPC
systems without VSX.
* configure: Regenerate.

Diff:
---
 libgcc/config.host  | 12 ++--
 libgcc/config/rs6000/t-float128 |  2 +-
 libgcc/configure| 17 +++--
 libgcc/configure.ac | 17 +++--
 4 files changed, 29 insertions(+), 19 deletions(-)

diff --git a/libgcc/config.host b/libgcc/config.host
index 9fae51d4ce7d..261b08859a4d 100644
--- a/libgcc/config.host
+++ b/libgcc/config.host
@@ -1292,14 +1292,14 @@ powerpc*-*-linux*)
 
if test $libgcc_cv_powerpc_float128 = yes; then
tmake_file="${tmake_file} rs6000/t-float128"
-   fi
 
-   if test $libgcc_cv_powerpc_float128_hw = yes; then
-   tmake_file="${tmake_file} rs6000/t-float128-hw"
-   fi
+   if test $libgcc_cv_powerpc_float128_hw = yes; then
+   tmake_file="${tmake_file} rs6000/t-float128-hw"
 
-   if test $libgcc_cv_powerpc_3_1_float128_hw = yes; then
-   tmake_file="${tmake_file} rs6000/t-float128-p10-hw"
+   if test $libgcc_cv_powerpc_3_1_float128_hw = yes; then
+   tmake_file="${tmake_file} 
rs6000/t-float128-p10-hw"
+   fi
+   fi
fi
 
extra_parts="$extra_parts ecrti.o ecrtn.o ncrti.o ncrtn.o"
diff --git a/libgcc/config/rs6000/t-float128 b/libgcc/config/rs6000/t-float128
index b09b5664af0e..2d93080f1174 100644
--- a/libgcc/config/rs6000/t-float128
+++ b/libgcc/config/rs6000/t-float128
@@ -74,7 +74,7 @@ fp128_includes= $(srcdir)/soft-fp/double.h \
  $(srcdir)/soft-fp/soft-fp.h
 
 # Build the emulator without ISA 3.0 hardware support.
-FP128_CFLAGS_SW = -Wno-type-limits -mvsx -mfloat128 \
+FP128_CFLAGS_SW = -Wno-type-limits -mfloat128 \
   -mno-float128-hardware -mno-gnu-attribute \
   -I$(srcdir)/soft-fp \
   -I$(srcdir)/config/rs6000 \
diff --git a/libgcc/configure b/libgcc/configure
index a69d314374a3..39193456929a 100755
--- a/libgcc/configure
+++ b/libgcc/configure
@@ -5180,13 +5180,18 @@ esac
 esac
 
 case ${host} in
-# At present, we cannot turn -mfloat128 on via #pragma GCC target, so just
-# check if we have VSX (ISA 2.06) support to build the software libraries, and
-# whether the assembler can handle xsaddqp for hardware support.  Also check if
-# a new glibc is being used so that __builtin_cpu_supports can be used.
+# Check if we can enable float128 support.  Some systems (big endian) do not
+# enable float128 by default, but they can enable it if -mfloat128 is used.
+# However, the compiler must be compiled using at least --with-cpu=power7 to
+# enable VSX support.  If we build a default big endian system without using
+# --with-cpu=power7, do not build the float128 libraries.  VSX support is
+# needed because float128 values are passed in VSX registers.
+#
+# Also check if a new glibc is being used so that __builtin_cpu_supports can be
+# used.
 powerpc*-*-linux*)
   saved_CFLAGS="$CFLAGS"
-  CFLAGS="$CFLAGS -mabi=altivec -mvsx -mfloat128"
+  CFLAGS="$CFLAGS -mfloat128"
   { $as_echo "$as_me:${as_lineno-$LINENO}: checking for PowerPC ISA 2.06 to 
build __float128 libraries" >&5
 $as_echo_n "checking for PowerPC ISA 2.06 to build __float128 libraries... " 
>&6; }
 if ${libgcc_cv_powerpc_float128+:} false; then :
@@ -5194,7 +5199,7 @@ if ${libgcc_cv_powerpc_float128+:} false; then :
 else
   cat confdefs.h - <<_ACEOF >conftest.$ac_ext
 /* end confdefs.h.  */
-vector double dadd (vector double a, vector double b) { return a + b; }
+__float128 f128_add (__float128 a, __float128 b) { return a+b; }
 _ACEOF
 if ac_fn_c_try_compile

[gcc(refs/users/meissner/heads/work171-bugs)] Update ChangeLog.*

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:caad5de45cf2142ddef06b3fd973dee64cba3121

commit caad5de45cf2142ddef06b3fd973dee64cba3121
Author: Michael Meissner 
Date:   Thu Jul 11 12:56:05 2024 -0400

Update ChangeLog.*

Diff:
---
 gcc/ChangeLog.bugs | 33 +++--
 1 file changed, 31 insertions(+), 2 deletions(-)

diff --git a/gcc/ChangeLog.bugs b/gcc/ChangeLog.bugs
index 1b4d99c0e5fb..738e612fc41a 100644
--- a/gcc/ChangeLog.bugs
+++ b/gcc/ChangeLog.bugs
@@ -1,8 +1,37 @@
  Branch work171-bugs, patch #301 
 
+Do not build IEEE 128-bit libgcc support if VSX is not available.
+
+In the past, we would build libgcc and eable the float128 libraries by adding
+-mvsx -mabi=altivec to build the support libraries.  However, this causes
+problems if the default cpu is a 7450.
+
+With this fix, in order to build the float128 support, the compiler must be
+configured to default to at least power7 to enable using the VSX register set,
+which is required for passing float128 values.
+
+If somebody wanted to enable float128 on big endian systems, they would need to
+use a compiler that defaults to at least power7.
+
+
+2024-07-11  Michael Meissner  
+
+libgcc/
+
+   PR target/115800
+   PR target/113652
+   * config.host (powerpc*-*-linux*): Do not enable the float128 hardware
+   and float128 power10 hardware support unless the basic float128 support
+   is added.
+   * configure.ac (powerpc*-*-linux*): Don't enable IEEE 128-bit on PowerPC
+   systems without VSX.
+   * configure: Regenerate.
+
+ Branch work171-bugs, patch #301 
+
 Do not build IEEE 128-bit libstdc++ support if VSX is not available.
 
-2024-07-03  Michael Meissner  
+2024-07-10  Michael Meissner  
 
 libstdc++-v3/
 
@@ -16,7 +45,7 @@ libstdc++-v3/
 
 Do not build IEEE 128-bit libgfortran support if VSX is not available.
 
-2024-07-03  Michael Meissner  
+2024-07-10  Michael Meissner  
 
 libgfortran/

[gcc r11-11571] libstdc++: Reverse arguments in constraint for std::optional's <=> [PR104606]

[Jonathan Wakely via Libstdc++-cvs]

https://gcc.gnu.org/g:1e0d60c6b097e9b0a96f7e763a10da11c412ef2c

commit r11-11571-g1e0d60c6b097e9b0a96f7e763a10da11c412ef2c
Author: Jonathan Wakely 
Date:   Wed Mar 27 21:51:13 2024 +

libstdc++: Reverse arguments in constraint for std::optional's <=> 
[PR104606]

This is a workaround for a possible compiler bug that causes constraint
recursion in the operator<=>(const optional&, const U&) overload.

libstdc++-v3/ChangeLog:

PR libstdc++/104606
* include/std/optional (operator<=>(const optional&, const U&)):
Reverse order of three_way_comparable_with template arguments.
* testsuite/20_util/optional/relops/104606.cc: New test.

(cherry picked from commit 7f65d8267fbfd19cf21a3dc71d27e989e75044a3)

Diff:
---
 libstdc++-v3/include/std/optional  |  2 +-
 .../testsuite/20_util/optional/relops/104606.cc| 18 ++
 2 files changed, 19 insertions(+), 1 deletion(-)

diff --git a/libstdc++-v3/include/std/optional 
b/libstdc++-v3/include/std/optional
index 449c27a80c46..b3fbd98c569a 100644
--- a/libstdc++-v3/include/std/optional
+++ b/libstdc++-v3/include/std/optional
@@ -1248,7 +1248,7 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
 
   template
 requires (!__is_optional_v<_Up>)
-  && three_way_comparable_with<_Tp, _Up>
+  && three_way_comparable_with<_Up, _Tp>
 constexpr compare_three_way_result_t<_Tp, _Up>
 operator<=>(const optional<_Tp>& __x, const _Up& __v)
 { return bool(__x) ? *__x <=> __v : strong_ordering::less; }
diff --git a/libstdc++-v3/testsuite/20_util/optional/relops/104606.cc 
b/libstdc++-v3/testsuite/20_util/optional/relops/104606.cc
new file mode 100644
index ..2b8df2452199
--- /dev/null
+++ b/libstdc++-v3/testsuite/20_util/optional/relops/104606.cc
@@ -0,0 +1,18 @@
+// { dg-do compile { target c++17 } }
+
+// Bug 104606 comparison operator resolution with std::optional and -std=c++20
+
+#include 
+#include 
+#include 
+
+struct Value : std::variant> { };
+
+struct Comparator {
+  template  bool operator<=(const T &) { return true; }
+};
+
+std::optional o;
+Comparator c;
+
+auto x = c <= o;

[gcc r12-10612] mve: Fix vsetq_lane for 64-bit elements with lane 1 [PR 115611]

[Andre Simoes Dias Vieira via Gcc-cvs]

https://gcc.gnu.org/g:a655c8d2098aff5235934263b065a389a9fcbbca

commit r12-10612-ga655c8d2098aff5235934263b065a389a9fcbbca
Author: Andre Vieira 
Date:   Thu Jul 11 15:38:45 2024 +0100

mve: Fix vsetq_lane for 64-bit elements with lane 1 [PR 115611]

This patch fixes the backend pattern that was printing the wrong input
scalar register pair when inserting into lane 1.

Added a new test to force float-abi=hard so we can use scan-assembler to 
check
correct codegen.

gcc/ChangeLog:

PR target/115611
* config/arm/mve.md (mve_vec_setv2di_internal): Fix printing of 
input
scalar register pair when lane = 1.

gcc/testsuite/ChangeLog:

* gcc.target/arm/mve/intrinsics/vsetq_lane_su64.c: New test.

(cherry picked from commit 7c11fdd2cc11a7058e9643b6abf27831970ad2c9)

Diff:
---
 gcc/config/arm/mve.md  |  2 +-
 .../arm/mve/intrinsics/vsetq_lane_su64.c   | 63 ++
 2 files changed, 64 insertions(+), 1 deletion(-)

diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
index 860d734b9a14..2de14013c43d 100644
--- a/gcc/config/arm/mve.md
+++ b/gcc/config/arm/mve.md
@@ -10159,7 +10159,7 @@
   if (elt == 0)
return "vmov\t%e0, %Q1, %R1";
   else
-   return "vmov\t%f0, %J1, %K1";
+   return "vmov\t%f0, %Q1, %R1";
 }
  [(set_attr "type" "mve_move")])
 
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_su64.c 
b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_su64.c
new file mode 100644
index ..5aa3bc9a76a0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_su64.c
@@ -0,0 +1,63 @@
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-require-effective-target arm_hard_ok } */
+/* { dg-additional-options "-mfloat-abi=hard -O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "arm_mve.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**fn1:
+** vmovd0, r0, r1
+** bx  lr
+*/
+uint64x2_t
+fn1 (uint64_t a, uint64x2_t b)
+{
+  return vsetq_lane_u64 (a, b, 0);
+}
+
+/*
+**fn2:
+** vmovd1, r0, r1
+** bx  lr
+*/
+uint64x2_t
+fn2 (uint64_t a, uint64x2_t b)
+{
+  return vsetq_lane_u64 (a, b, 1);
+}
+
+/*
+**fn3:
+** vmovd0, r0, r1
+** bx  lr
+*/
+int64x2_t
+fn3 (int64_t a, int64x2_t b)
+{
+  return vsetq_lane_s64 (a, b, 0);
+}
+
+/*
+**fn4:
+** vmovd1, r0, r1
+** bx  lr
+*/
+int64x2_t
+fn4 (int64_t a, int64x2_t b)
+{
+  return vsetq_lane_s64 (a, b, 1);
+}
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
+

[gcc r13-8905] mve: Fix vsetq_lane for 64-bit elements with lane 1 [PR 115611]

[Andre Simoes Dias Vieira via Gcc-cvs]

https://gcc.gnu.org/g:dd7b273f8dc03f28b0cd07c1a489d5200abaf790

commit r13-8905-gdd7b273f8dc03f28b0cd07c1a489d5200abaf790
Author: Andre Vieira 
Date:   Thu Jul 11 15:38:45 2024 +0100

mve: Fix vsetq_lane for 64-bit elements with lane 1 [PR 115611]

This patch fixes the backend pattern that was printing the wrong input
scalar register pair when inserting into lane 1.

Added a new test to force float-abi=hard so we can use scan-assembler to 
check
correct codegen.

gcc/ChangeLog:

PR target/115611
* config/arm/mve.md (mve_vec_setv2di_internal): Fix printing of 
input
scalar register pair when lane = 1.

gcc/testsuite/ChangeLog:

* gcc.target/arm/mve/intrinsics/vsetq_lane_su64.c: New test.

(cherry picked from commit 7c11fdd2cc11a7058e9643b6abf27831970ad2c9)

Diff:
---
 gcc/config/arm/mve.md  |  2 +-
 .../arm/mve/intrinsics/vsetq_lane_su64.c   | 63 ++
 2 files changed, 64 insertions(+), 1 deletion(-)

diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
index cf172f16c575..fd016c434616 100644
--- a/gcc/config/arm/mve.md
+++ b/gcc/config/arm/mve.md
@@ -10166,7 +10166,7 @@
   if (elt == 0)
return "vmov\t%e0, %Q1, %R1";
   else
-   return "vmov\t%f0, %J1, %K1";
+   return "vmov\t%f0, %Q1, %R1";
 }
  [(set_attr "type" "mve_move")])
 
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_su64.c 
b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_su64.c
new file mode 100644
index ..5aa3bc9a76a0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_su64.c
@@ -0,0 +1,63 @@
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-require-effective-target arm_hard_ok } */
+/* { dg-additional-options "-mfloat-abi=hard -O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "arm_mve.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**fn1:
+** vmovd0, r0, r1
+** bx  lr
+*/
+uint64x2_t
+fn1 (uint64_t a, uint64x2_t b)
+{
+  return vsetq_lane_u64 (a, b, 0);
+}
+
+/*
+**fn2:
+** vmovd1, r0, r1
+** bx  lr
+*/
+uint64x2_t
+fn2 (uint64_t a, uint64x2_t b)
+{
+  return vsetq_lane_u64 (a, b, 1);
+}
+
+/*
+**fn3:
+** vmovd0, r0, r1
+** bx  lr
+*/
+int64x2_t
+fn3 (int64_t a, int64x2_t b)
+{
+  return vsetq_lane_s64 (a, b, 0);
+}
+
+/*
+**fn4:
+** vmovd1, r0, r1
+** bx  lr
+*/
+int64x2_t
+fn4 (int64_t a, int64x2_t b)
+{
+  return vsetq_lane_s64 (a, b, 1);
+}
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
+

[gcc(refs/users/meissner/heads/work171-bugs)] Update ChangeLog.*

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:f4f8f4202017566975f1e2001875876f5cab4cbe

commit f4f8f4202017566975f1e2001875876f5cab4cbe
Author: Michael Meissner 
Date:   Thu Jul 11 13:01:57 2024 -0400

Update ChangeLog.*

Diff:
---
 gcc/ChangeLog.bugs | 1 +
 1 file changed, 1 insertion(+)

diff --git a/gcc/ChangeLog.bugs b/gcc/ChangeLog.bugs
index 738e612fc41a..a4a6b8aa0f70 100644
--- a/gcc/ChangeLog.bugs
+++ b/gcc/ChangeLog.bugs
@@ -23,6 +23,7 @@ libgcc/
* config.host (powerpc*-*-linux*): Do not enable the float128 hardware
and float128 power10 hardware support unless the basic float128 support
is added.
+   * config/rs6000/t-float128 (FP128_CFLAGS_SW): Do not add -mvsx.
* configure.ac (powerpc*-*-linux*): Don't enable IEEE 128-bit on PowerPC
systems without VSX.
* configure: Regenerate.

[gcc r14-10408] mve: Fix vsetq_lane for 64-bit elements with lane 1 [PR 115611]

[Andre Simoes Dias Vieira via Gcc-cvs]

https://gcc.gnu.org/g:b7a16ad1df8b00e084ef6bf0c23e5f8bdc5f419b

commit r14-10408-gb7a16ad1df8b00e084ef6bf0c23e5f8bdc5f419b
Author: Andre Vieira 
Date:   Thu Jul 11 15:38:45 2024 +0100

mve: Fix vsetq_lane for 64-bit elements with lane 1 [PR 115611]

This patch fixes the backend pattern that was printing the wrong input
scalar register pair when inserting into lane 1.

Added a new test to force float-abi=hard so we can use scan-assembler to 
check
correct codegen.

gcc/ChangeLog:

PR target/115611
* config/arm/mve.md (mve_vec_setv2di_internal): Fix printing of 
input
scalar register pair when lane = 1.

gcc/testsuite/ChangeLog:

* gcc.target/arm/mve/intrinsics/vsetq_lane_su64.c: New test.

(cherry picked from commit 7c11fdd2cc11a7058e9643b6abf27831970ad2c9)

Diff:
---
 gcc/config/arm/mve.md  |  2 +-
 .../arm/mve/intrinsics/vsetq_lane_su64.c   | 63 ++
 2 files changed, 64 insertions(+), 1 deletion(-)

diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
index 9fe51298cdc2..f45c555ef063 100644
--- a/gcc/config/arm/mve.md
+++ b/gcc/config/arm/mve.md
@@ -6505,7 +6505,7 @@
   if (elt == 0)
return "vmov\t%e0, %Q1, %R1";
   else
-   return "vmov\t%f0, %J1, %K1";
+   return "vmov\t%f0, %Q1, %R1";
 }
  [(set_attr "type" "mve_move")])
 
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_su64.c 
b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_su64.c
new file mode 100644
index ..5aa3bc9a76a0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_su64.c
@@ -0,0 +1,63 @@
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-require-effective-target arm_hard_ok } */
+/* { dg-additional-options "-mfloat-abi=hard -O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "arm_mve.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**fn1:
+** vmovd0, r0, r1
+** bx  lr
+*/
+uint64x2_t
+fn1 (uint64_t a, uint64x2_t b)
+{
+  return vsetq_lane_u64 (a, b, 0);
+}
+
+/*
+**fn2:
+** vmovd1, r0, r1
+** bx  lr
+*/
+uint64x2_t
+fn2 (uint64_t a, uint64x2_t b)
+{
+  return vsetq_lane_u64 (a, b, 1);
+}
+
+/*
+**fn3:
+** vmovd0, r0, r1
+** bx  lr
+*/
+int64x2_t
+fn3 (int64_t a, int64x2_t b)
+{
+  return vsetq_lane_s64 (a, b, 0);
+}
+
+/*
+**fn4:
+** vmovd1, r0, r1
+** bx  lr
+*/
+int64x2_t
+fn4 (int64_t a, int64x2_t b)
+{
+  return vsetq_lane_s64 (a, b, 1);
+}
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
+

[gcc r15-1976] [to-be-committed, RISC-V] Eliminate unnecessary sign extension after inlined str[n]cmp

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:74d8accaf88f83bfcab1150bf9be5140e7ac0e94

commit r15-1976-g74d8accaf88f83bfcab1150bf9be5140e7ac0e94
Author: Jeff Law 
Date:   Thu Jul 11 12:05:56 2024 -0600

[to-be-committed,RISC-V] Eliminate unnecessary sign extension after inlined 
str[n]cmp

This patch eliminates an unnecessary sign extension for scalar inlined
string comparisons on rv64.

Conceptually this is pretty simple.  Prove all the paths which "return"
a value from the inlined string comparison already have sign extended
values.

FINAL_LABEL is the point after the calculation of the return value.  So
if we have a jump to FINAL_LABEL, we must have a properly extended
result value at that point.

Second we're going to arrange in the .md part of the expander to use an
X mode temporary for the result.  After computing the result we will (if
necessary) extract the low part of the result using a SUBREG tagged with
the appropriate SUBREG_PROMOTED_* bits.

So with that background.

We find a jump to FINAL_LABEL in emit_strcmp_scalar_compare_byte.  Since
we know the result is X mode, we can just emit the subtraction of the
two chars in X mode and we'll have a properly sign extended result.

There's 4 jumps to final_label in emit_strcmp_scalar.

The first is just returning zero and needs trivial simplification to not
force the result into SImode.

The second is after calling strcmp in the library.  The ABI mandates
that value is sign extended, so there's nothing to do for that case.

The 3rd occurs after a call to
emit_strcmp_scalar_result_calculation_nonul.  If we dive into that
routine it needs simplificationq similar to what we did in
emit_strcmp_scalar_compare_byte

The 4th occurs after a call to emit_strcmp_scalar_result_calculation
which again needs trivial adjustment like we've done in the other routines.

Finally, at the end of expand_strcmp, just store the X mode result
sitting in SUB to RESULT.

The net of all that is we know every path has its result properly
extended to X mode.  Standard redundant extension removal will take care
of the rest.

We've been running this within Ventana for about 6 months, so naturally
it's been through various QA cycles, dhrystone, spec2017, etc.  It's
also been through a build/test cycle in my tester.  Waiting on results
from the pre-commit testing before moving forward.

gcc/
* config/riscv/riscv-string.cc
(emit_strcmp_scalar_compare_byte): Set RESULT directly rather
than using a new temporary.
(emit_strcmp_scalar_result_calculation_nonul): Likewise.
(emit_strcmp_scalar_result_calculation): Likewise.
(riscv_expand_strcmp_scalar): Use CONST0_RTX rather than
generating a new node.
(expand_strcmp): Copy directly from SUB to RESULT.
* config/riscv/riscv.md (cmpstrnsi, cmpstrsi): Pass an X
mode temporary to the expansion routines.  If necessary
extract low part of the word to store in final result location.

Diff:
---
 gcc/config/riscv/riscv-string.cc | 15 +--
 gcc/config/riscv/riscv.md| 28 
 2 files changed, 29 insertions(+), 14 deletions(-)

diff --git a/gcc/config/riscv/riscv-string.cc b/gcc/config/riscv/riscv-string.cc
index 257a514d2901..4736228e6f14 100644
--- a/gcc/config/riscv/riscv-string.cc
+++ b/gcc/config/riscv/riscv-string.cc
@@ -140,9 +140,7 @@ static void
 emit_strcmp_scalar_compare_byte (rtx result, rtx data1, rtx data2,
 rtx final_label)
 {
-  rtx tmp = gen_reg_rtx (Xmode);
-  do_sub3 (tmp, data1, data2);
-  emit_insn (gen_movsi (result, gen_lowpart (SImode, tmp)));
+  do_sub3 (result, data1, data2);
   emit_jump_insn (gen_jump (final_label));
   emit_barrier (); /* No fall-through.  */
 }
@@ -310,8 +308,7 @@ emit_strcmp_scalar_result_calculation_nonul (rtx result, 
rtx data1, rtx data2)
   rtx tmp = gen_reg_rtx (Xmode);
   emit_insn (gen_slt_3 (LTU, Xmode, Xmode, tmp, data1, data2));
   do_neg2 (tmp, tmp);
-  do_ior3 (tmp, tmp, const1_rtx);
-  emit_insn (gen_movsi (result, gen_lowpart (SImode, tmp)));
+  do_ior3 (result, tmp, const1_rtx);
 }
 
 /* strcmp-result calculation.
@@ -367,9 +364,7 @@ emit_strcmp_scalar_result_calculation (rtx result, rtx 
data1, rtx data2,
   unsigned int shiftr = (xlen - 1) * BITS_PER_UNIT;
   do_lshr3 (data1, data1, GEN_INT (shiftr));
   do_lshr3 (data2, data2, GEN_INT (shiftr));
-  rtx tmp = gen_reg_rtx (Xmode);
-  do_sub3 (tmp, data1, data2);
-  emit_insn (gen_movsi (result, gen_lowpart (SImode, tmp)));
+  do_sub3 (result, data1, data2);
 }
 
 /* Expand str(n)cmp using Zbb/TheadBb instructions.
@@ -444,7 +439,7 @@ riscv_expand_strcmp_scalar (rtx result, rtx src1, rtx src2,
   /* All compared and everything was equal.  */
   if (nc

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [RISC-V] add implied extension repeatly until stable

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:fe7b8250ee5190f31a622d99e394861f0688feef

commit fe7b8250ee5190f31a622d99e394861f0688feef
Author: Fei Gao 
Date:   Fri Jul 5 09:56:30 2024 +

[RISC-V] add implied extension repeatly until stable

Call handle_implied_ext repeatly until there's no
new subset added into the subset list.

gcc/ChangeLog:

* common/config/riscv/riscv-common.cc 
(riscv_subset_list::riscv_subset_list):
init m_subset_num to 0.
(riscv_subset_list::add): increase m_subset_num once a subset added.
(riscv_subset_list::finalize): call handle_implied_ext repeatly
until no change in m_subset_num.
* config/riscv/riscv-subset.h: add m_subset_num member.

Signed-off-by: Fei Gao 
(cherry picked from commit 682731d11f9c02b24358d1af1e2bf6fca0221ee7)

Diff:
---
 gcc/common/config/riscv/riscv-common.cc | 14 +++---
 gcc/config/riscv/riscv-subset.h |  3 +++
 2 files changed, 14 insertions(+), 3 deletions(-)

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index 16bdb3fd2259..b9bda3e110a2 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -569,7 +569,8 @@ riscv_subset_t::riscv_subset_t ()
 }
 
 riscv_subset_list::riscv_subset_list (const char *arch, location_t loc)
-  : m_arch (arch), m_loc (loc), m_head (NULL), m_tail (NULL), m_xlen (0)
+  : m_arch (arch), m_loc (loc), m_head (NULL), m_tail (NULL), m_xlen (0),
+m_subset_num (0)
 {
 }
 
@@ -815,6 +816,7 @@ riscv_subset_list::add (const char *subset, int 
major_version,
   return;
 }
 
+  m_subset_num++;
   riscv_subset_t *s = new riscv_subset_t ();
   riscv_subset_t *itr;
 
@@ -1597,9 +1599,15 @@ void
 riscv_subset_list::finalize ()
 {
   riscv_subset_t *subset;
+  unsigned pre_subset_num;
 
-  for (subset = m_head; subset != NULL; subset = subset->next)
-handle_implied_ext (subset->name.c_str ());
+  do
+{
+  pre_subset_num = m_subset_num;
+  for (subset = m_head; subset != NULL; subset = subset->next)
+   handle_implied_ext (subset->name.c_str ());
+}
+  while (pre_subset_num != m_subset_num);
 
   gcc_assert (check_implied_ext ());
 
diff --git a/gcc/config/riscv/riscv-subset.h b/gcc/config/riscv/riscv-subset.h
index fe7f54d8bc57..7dc196a20074 100644
--- a/gcc/config/riscv/riscv-subset.h
+++ b/gcc/config/riscv/riscv-subset.h
@@ -62,6 +62,9 @@ private:
   /* X-len of m_arch. */
   unsigned m_xlen;
 
+  /* Number of subsets. */
+  unsigned m_subset_num;
+
   riscv_subset_list (const char *, location_t);
 
   const char *parsing_subset_version (const char *, const char *, unsigned *,

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Implement .SAT_TRUNC for vector unsigned int

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:cbee085f82008a05b335754ea8b9764c3a78202c

commit cbee085f82008a05b335754ea8b9764c3a78202c
Author: Pan Li 
Date:   Fri Jul 5 09:02:47 2024 +0800

RISC-V: Implement .SAT_TRUNC for vector unsigned int

This patch would like to implement the .SAT_TRUNC for the RISC-V
backend.  With the help of the RVV Vector Narrowing Fixed-Point
Clip Instructions.  The below SEW(S) are supported:

* e64 => e32
* e64 => e16
* e64 => e8
* e32 => e16
* e32 => e8
* e16 => e8

Take below example to see the changes to asm.
Form 1:
  #define DEF_VEC_SAT_U_TRUNC_FMT_1(NT, WT) \
  void __attribute__((noinline))\
  vec_sat_u_trunc_##NT##_##WT##_fmt_1 (NT *out, WT *in, unsigned limit) \
  { \
unsigned i; \
for (i = 0; i < limit; i++) \
  { \
WT x = in[i];   \
bool overflow = x > (WT)(NT)(-1);   \
out[i] = ((NT)x) | (NT)-overflow;   \
  } \
  }

DEF_VEC_SAT_U_TRUNC_FMT_1 (uint32_t, uint64_t)

Before this patch:
.L3:
  vsetvli  a5,a2,e64,m1,ta,ma
  vle64.v  v1,0(a1)
  vmsgtu.vvv0,v1,v2
  vsetvli  zero,zero,e32,mf2,ta,ma
  vncvt.x.x.w  v1,v1
  vmerge.vim   v1,v1,-1,v0
  vse32.v  v1,0(a0)
  slli a4,a5,3
  add  a1,a1,a4
  slli a4,a5,2
  add  a0,a0,a4
  sub  a2,a2,a5
  bne  a2,zero,.L3

After this patch:
.L3:
  vsetvli  a5,a2,e32,mf2,ta,ma
  vle64.v  v1,0(a1)
  vnclipu.wi   v1,v1,0
  vse32.v  v1,0(a0)
  slli a4,a5,3
  add  a1,a1,a4
  slli a4,a5,2
  add  a0,a0,a4
  sub  a2,a2,a5
  bne  a2,zero,.L3

Passed the rv64gcv fully regression tests.

gcc/ChangeLog:

* config/riscv/autovec.md (ustrunc2): Add
new pattern for double truncation.
(ustrunc2): Ditto but for quad truncation.
(ustrunc2): Ditto but for oct truncation.
* config/riscv/riscv-protos.h (expand_vec_double_ustrunc): Add
new func decl to expand double vec ustrunc.
(expand_vec_quad_ustrunc): Ditto but for quad.
(expand_vec_oct_ustrunc): Ditto but for oct.
* config/riscv/riscv-v.cc (expand_vec_double_ustrunc): Add new
func impl to expand vector double ustrunc.
(expand_vec_quad_ustrunc): Ditto but for quad.
(expand_vec_oct_ustrunc): Ditto but for oct.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: Add helper
test macros.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_data.h: New test.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-1.c: New test.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-2.c: New test.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-3.c: New test.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-4.c: New test.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-5.c: New test.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-6.c: New test.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-run-1.c: New 
test.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-run-2.c: New 
test.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-run-3.c: New 
test.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-run-4.c: New 
test.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-run-5.c: New 
test.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-run-6.c: New 
test.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_unary_vv_run.h: New 
test.

Signed-off-by: Pan Li 
(cherry picked from commit dafd63d7c5cddce1e00803606e742d75927b1a1e)

Diff:
---
 gcc/config/riscv/autovec.md|  35 ++
 gcc/config/riscv/riscv-protos.h|   4 +
 gcc/config/riscv/riscv-v.cc|  46 +++
 .../riscv/rvv/autovec/binop/vec_sat_arith.h|  22 ++
 .../riscv/rvv/autovec/unop/vec_sat_data.h  | 394 +
 .../riscv/rvv/autovec/unop/vec_sat_u_trunc-1.c |  19 +
 .../riscv/rvv/autovec/unop/vec_sat_u_trunc-2.c |  21 ++
 .../riscv/rvv/autovec/unop/vec_sat_u_trunc-3.c |  23 ++
 .../riscv/rvv/autovec/unop/vec_sat_u_trunc-4.c 

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for unsigned vector .SAT_ADD IMM form 1

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:79aca63c26b3eee221c26ee62803fa19e5996502

commit 79aca63c26b3eee221c26ee62803fa19e5996502
Author: Pan Li 
Date:   Mon Jul 8 20:31:31 2024 +0800

RISC-V: Add testcases for unsigned vector .SAT_ADD IMM form 1

After the middle-end supported the vector mode of .SAT_ADD,  add more
testcases to ensure the correctness of RISC-V backend for form 1.  Aka:

Form 1:
  #define DEF_VEC_SAT_U_ADD_IMM_FMT_1(T, IMM)  \
  T __attribute__((noinline))  \
  vec_sat_u_add_imm##IMM##_##T##_fmt_1 (T *out, T *in, unsigned limit) \
  {\
unsigned i;\
for (i = 0; i < limit; i++)\
  out[i] = (T)(in[i] + IMM) >= in[i] ? (in[i] + IMM) : -1; \
  }

DEF_VEC_SAT_U_ADD_IMM_FMT_1 (uint64_t, 9)

Passed the fully rv64gcv regression tests.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: Add help
test macro.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_data.h: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-1.c: New 
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-2.c: New 
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-3.c: New 
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-4.c: New 
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-1.c: New 
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-2.c: New 
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-3.c: New 
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-4.c: New 
test.

Signed-off-by: Pan Li 
(cherry picked from commit 35b1096896a94a90d787f5ef402ba009dd4f0393)

Diff:
---
 .../riscv/rvv/autovec/binop/vec_sat_arith.h|  25 ++
 .../riscv/rvv/autovec/binop/vec_sat_data.h | 256 +
 .../riscv/rvv/autovec/binop/vec_sat_u_add_imm-1.c  |  14 ++
 .../riscv/rvv/autovec/binop/vec_sat_u_add_imm-2.c  |  14 ++
 .../riscv/rvv/autovec/binop/vec_sat_u_add_imm-3.c  |  14 ++
 .../riscv/rvv/autovec/binop/vec_sat_u_add_imm-4.c  |  14 ++
 .../rvv/autovec/binop/vec_sat_u_add_imm-run-1.c|  28 +++
 .../rvv/autovec/binop/vec_sat_u_add_imm-run-2.c|  28 +++
 .../rvv/autovec/binop/vec_sat_u_add_imm-run-3.c|  28 +++
 .../rvv/autovec/binop/vec_sat_u_add_imm-run-4.c|  28 +++
 10 files changed, 449 insertions(+)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h
index b55a589e019a..3733c8fd2c15 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h
@@ -4,6 +4,14 @@
 #include 
 #include 
 
+#define VALIDATE_RESULT(out, expect, N)  \
+  do \
+{\
+  for (unsigned i = 0; i < N; i++)   \
+if (out[i] != expect[i]) __builtin_abort (); \
+}\
+  while (false)
+
 
/**/
 /* Saturation Add (unsigned and signed)   
*/
 
/**/
@@ -139,6 +147,23 @@ vec_sat_u_add_##T##_fmt_8 (T *out, T *op_1, T *op_2, 
unsigned limit) \
 #define RUN_VEC_SAT_U_ADD_FMT_8(T, out, op_1, op_2, N) \
   vec_sat_u_add_##T##_fmt_8(out, op_1, op_2, N)
 
+#define DEF_VEC_SAT_U_ADD_IMM_FMT_1(T, IMM)  \
+T __attribute__((noinline))  \
+vec_sat_u_add_imm##IMM##_##T##_fmt_1 (T *out, T *in, unsigned limit) \
+{\
+  unsigned i;\
+  for (i = 0; i < limit; i++)\
+out[i] = (T)(in[i] + IMM) >= in[i] ? (in[i] + IMM) : -1; \
+}
+#define DEF_VEC_SAT_U_ADD_IMM_FMT_1_WRAP(T, IMM) \
+  DEF_VEC_SAT_U_ADD_IMM_FMT_1(T, IMM)
+
+#define RUN_VEC_SAT_U_ADD_IMM_FMT_1(T, out, op_1, expect, IMM, N) \
+  vec_sat_u_add_imm##IMM##_##T##_fmt_1(out, op_1, N); \
+  VALIDATE_RESULT (out, expect, N)
+#define RUN_VEC_SAT_U_ADD_IMM_FMT_1_WRAP(T, out, op_1, expect, IMM, N) \
+  RUN_VEC_SAT_U_ADD_IMM_FMT_1(T, out, op_1, expect, IMM, N)
+
 
/**/
 /* Saturation Sub (Unsigned and Signed)   
*/
 
/*

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [to-be-committed][RISC-V][V3] DCE analysis for extension elimination

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:d678469ed4f98cee0180ff6a9961920404e82a14

commit d678469ed4f98cee0180ff6a9961920404e82a14
Author: Jeff Law 
Date:   Mon Jul 8 17:06:55 2024 -0600

[to-be-committed][RISC-V][V3] DCE analysis for extension elimination

The pre-commit testing showed that making ext-dce only active at -O2 and 
above
would require minor edits to the tests.  In some cases we had specified -O1 
in
the test or specified no optimization level at all. Those need to be bumped 
to
-O2.   In one test we had one set of dg-options overriding another.

The other approach that could have been taken would be to drop the -On
argument, add an explicit -fext-dce and add dg-skip-if options.  I 
originally
thought that was going to be way to go, but the dg-skip-if aspect was going 
to
get ugly as things like interaction between unrolling, peeling and -ftracer
would have to be accounted for and would likely need semi-regular 
adjustment.

Changes since V2:
  Testsuite changes to deal with pass only being enabled at -O2 or
  higher.

--

Changes since V1:

  Check flag_ext_dce before running the new pass.  I'd forgotten that
  I had removed that part of the gate to facilitate more testing.
  Turn flag_ext_dce on at -O2 and above.
  Adjust one of the riscv tests to explicitly avoid vectors
  Adjust a few aarch64 tests
In tbz_2.c we remove an unnecessary extension which causes us to use
"x" registers instead of "w" registers.

In the pred_clobber tests we also remove an extension and that
ultimately causes a reg->reg copy to change locations.

--

This was actually ack'd late in the gcc-14 cycle, but I chose not to 
integrate
it given how late we were in the cycle.

The basic idea here is to track liveness of subobjects within a word and if 
we
find an extension where the bits set aren't actually used, then we convert 
the
extension into a subreg.  The subreg typically simplifies away.

I've seen this help a few routines in coremark, fix one bug in the testsuite
(pr111384) and fix a couple internally reported bugs in Ventana.

The original idea and code were from Joern; Jivan and I hacked it into 
usable
shape.  I've had this in my tester for ~8 months, so it's been through more
build/test cycles than I care to contemplate and nearly every architecture 
we
support.

But just in case, I'm going to wait for it to spin through the pre-commit CI
tester.  I'll find my old ChangeLog before committing.

gcc/
* Makefile.in (OBJS): Add ext-dce.o
* common.opt (ext-dce): Document new option.
* df-scan.cc (df_get_ext_block_use_set): Delete prototype and
make extern.
* df.h (df_get_exit_block_use_set): Prototype.
* ext-dce.cc: New file/pass.
* opts.cc (default_options_table): Handle ext-dce at -O2 or higher.
* passes.def: Add ext-dce before combine.
* tree-pass.h (make_pass_ext_dce): Prototype.

gcc/testsuite
* gcc.target/aarch64/sve/pred_clobber_1.c: Update expected output.
* gcc.target/aarch64/sve/pred_clobber_2.c: Likewise.
* gcc.target/aarch64/sve/pred_clobber_3.c: Likewise.
* gcc.target/aarch64/tbz_2.c: Likewise.
* gcc.target/riscv/core_bench_list.c: New test.
* gcc.target/riscv/core_init_matrix.c: New test.
* gcc.target/riscv/core_list_init.c: New test.
* gcc.target/riscv/matrix_add_const.c: New test.
* gcc.target/riscv/mem-extend.c: New test.
* gcc.target/riscv/pr111384.c: New test.

Co-authored-by: Jivan Hakobyan 
Co-authored-by: Joern Rennecke 

(cherry picked from commit 98914f9eba5f19d3eb93fbce8726b5264631cba0)

Diff:
---
 gcc/Makefile.in   |   1 +
 gcc/common.opt|   4 +
 gcc/df-scan.cc|   3 +-
 gcc/df.h  |   1 +
 gcc/ext-dce.cc| 943 ++
 gcc/opts.cc   |   1 +
 gcc/passes.def|   1 +
 gcc/testsuite/gcc.target/aarch64/tbz_2.c  |   6 +-
 gcc/testsuite/gcc.target/riscv/core_bench_list.c  |  15 +
 gcc/testsuite/gcc.target/riscv/core_init_matrix.c |  17 +
 gcc/testsuite/gcc.target/riscv/core_list_init.c   |  18 +
 gcc/testsuite/gcc.target/riscv/matrix_add_const.c |  13 +
 gcc/testsuite/gcc.target/riscv/mem-extend.c   |  14 +
 gcc/testsuite/gcc.target/riscv/pr111384.c |  11 +
 gcc/tree-pass.h   |   1 +
 15 files changed, 1044 insertions(+), 5 deletions(-)

diff --git a/gcc/Makefile.in b/gcc/Makefile.in
index a74761b7ab32..c070a38

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for unsigned vector .SAT_ADD IMM form 2

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:f3efae407d19273bf91c16e588ff63a80f0baf26

commit f3efae407d19273bf91c16e588ff63a80f0baf26
Author: Pan Li 
Date:   Mon Jul 8 21:58:59 2024 +0800

RISC-V: Add testcases for unsigned vector .SAT_ADD IMM form 2

After the middle-end supported the vector mode of .SAT_ADD,  add more
testcases to ensure the correctness of RISC-V backend for form 2.  Aka:

Form 2:
  #define DEF_VEC_SAT_U_ADD_IMM_FMT_2(T, IMM)  \
  T __attribute__((noinline))  \
  vec_sat_u_add_imm##IMM##_##T##_fmt_2 (T *out, T *in, unsigned limit) \
  {\
unsigned i;\
for (i = 0; i < limit; i++)\
  out[i] = (T)(in[i] + IMM) < in[i] ? -1 : (in[i] + IMM);  \
  }

DEF_VEC_SAT_U_ADD_IMM_FMT_2 (uint64_t, 9)

Passed the fully rv64gcv regression tests.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: Add help
test macro.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-5.c: New 
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-6.c: New 
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-7.c: New 
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-8.c: New 
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-5.c: New 
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-6.c: New 
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-7.c: New 
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-8.c: New 
test.

Signed-off-by: Pan Li 
(cherry picked from commit ecde8d50bea3573194f21277666f83463cbbe9c9)

Diff:
---
 .../riscv/rvv/autovec/binop/vec_sat_arith.h| 17 +
 .../riscv/rvv/autovec/binop/vec_sat_u_add_imm-5.c  | 14 +++
 .../riscv/rvv/autovec/binop/vec_sat_u_add_imm-6.c  | 14 +++
 .../riscv/rvv/autovec/binop/vec_sat_u_add_imm-7.c  | 14 +++
 .../riscv/rvv/autovec/binop/vec_sat_u_add_imm-8.c  | 14 +++
 .../rvv/autovec/binop/vec_sat_u_add_imm-run-5.c| 28 ++
 .../rvv/autovec/binop/vec_sat_u_add_imm-run-6.c| 28 ++
 .../rvv/autovec/binop/vec_sat_u_add_imm-run-7.c| 28 ++
 .../rvv/autovec/binop/vec_sat_u_add_imm-run-8.c| 28 ++
 9 files changed, 185 insertions(+)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h
index 3733c8fd2c15..10459807b2c4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h
@@ -158,12 +158,29 @@ vec_sat_u_add_imm##IMM##_##T##_fmt_1 (T *out, T *in, 
unsigned limit) \
 #define DEF_VEC_SAT_U_ADD_IMM_FMT_1_WRAP(T, IMM) \
   DEF_VEC_SAT_U_ADD_IMM_FMT_1(T, IMM)
 
+#define DEF_VEC_SAT_U_ADD_IMM_FMT_2(T, IMM)  \
+T __attribute__((noinline))  \
+vec_sat_u_add_imm##IMM##_##T##_fmt_2 (T *out, T *in, unsigned limit) \
+{\
+  unsigned i;\
+  for (i = 0; i < limit; i++)\
+out[i] = (T)(in[i] + IMM) < in[i] ? -1 : (in[i] + IMM);  \
+}
+#define DEF_VEC_SAT_U_ADD_IMM_FMT_2_WRAP(T, IMM) \
+  DEF_VEC_SAT_U_ADD_IMM_FMT_2(T, IMM)
+
 #define RUN_VEC_SAT_U_ADD_IMM_FMT_1(T, out, op_1, expect, IMM, N) \
   vec_sat_u_add_imm##IMM##_##T##_fmt_1(out, op_1, N); \
   VALIDATE_RESULT (out, expect, N)
 #define RUN_VEC_SAT_U_ADD_IMM_FMT_1_WRAP(T, out, op_1, expect, IMM, N) \
   RUN_VEC_SAT_U_ADD_IMM_FMT_1(T, out, op_1, expect, IMM, N)
 
+#define RUN_VEC_SAT_U_ADD_IMM_FMT_2(T, out, op_1, expect, IMM, N) \
+  vec_sat_u_add_imm##IMM##_##T##_fmt_2(out, op_1, N); \
+  VALIDATE_RESULT (out, expect, N)
+#define RUN_VEC_SAT_U_ADD_IMM_FMT_2_WRAP(T, out, op_1, expect, IMM, N) \
+  RUN_VEC_SAT_U_ADD_IMM_FMT_2(T, out, op_1, expect, IMM, N)
+
 
/**/
 /* Saturation Sub (Unsigned and Signed)   
*/
 
/**/
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-5.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-5.c
new file mode 100644
index ..d25fdcf78f38
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-5.c
@@ -0,0 +1,14 @@

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: testsuite: Properly gate LTO tests

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:6f195492e9798607b475c14934b0b77cf258a2a6

commit 6f195492e9798607b475c14934b0b77cf258a2a6
Author: Christoph Müllner 
Date:   Fri Jul 5 09:53:34 2024 +0200

RISC-V: testsuite: Properly gate LTO tests

There are two test cases with the following skip directive:
  dg-skip-if "" { *-*-* } { "-flto -fno-fat-lto-objects" }
This reads as: skip if both '-flto' and '-fno-fat-lto-objects'
are present.  This is not the case if only '-flto' is present.

Since both tests depend on instruction sequences (one does
check-function-bodies the other tests for an assembler error
message), they won't work reliably with fat LTO objects.

Let's change the skip line to gate the test on '-flto'
to avoid failing tests like this:

FAIL: gcc.target/riscv/interrupt-misaligned.c   -O2 -flto   
check-function-bodies interrupt
FAIL: gcc.target/riscv/interrupt-misaligned.c   -O2 -flto 
-flto-partition=none   check-function-bodies interrupt
FAIL: gcc.target/riscv/pr93202.c   -O2 -flto   (test for errors, line 10)
FAIL: gcc.target/riscv/pr93202.c   -O2 -flto   (test for errors, line 9)
FAIL: gcc.target/riscv/pr93202.c   -O2 -flto -flto-partition=none   (test 
for errors, line 10)
FAIL: gcc.target/riscv/pr93202.c   -O2 -flto -flto-partition=none   (test 
for errors, line 9)

gcc/testsuite/ChangeLog:

* gcc.target/riscv/interrupt-misaligned.c: Remove
"-fno-fat-lto-objects" from skip condition.
* gcc.target/riscv/pr93202.c: Likewise.

Signed-off-by: Christoph Müllner 
(cherry picked from commit 0717d50fc4ff983b79093bdef43b04e4584cc3cd)

Diff:
---
 gcc/testsuite/gcc.target/riscv/interrupt-misaligned.c | 2 +-
 gcc/testsuite/gcc.target/riscv/pr93202.c  | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/gcc/testsuite/gcc.target/riscv/interrupt-misaligned.c 
b/gcc/testsuite/gcc.target/riscv/interrupt-misaligned.c
index b5f8e6c2bbef..912f180e4d65 100644
--- a/gcc/testsuite/gcc.target/riscv/interrupt-misaligned.c
+++ b/gcc/testsuite/gcc.target/riscv/interrupt-misaligned.c
@@ -1,6 +1,6 @@
 /* { dg-do compile } */
 /* { dg-options "-O2 -march=rv64gc -mabi=lp64d -fno-schedule-insns 
-fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto -fno-fat-lto-objects" } } */
+/* { dg-skip-if "" { *-*-* } { "-flto" } } */
 
 /*  Make sure no stack offset are misaligned.
 **  interrupt:
diff --git a/gcc/testsuite/gcc.target/riscv/pr93202.c 
b/gcc/testsuite/gcc.target/riscv/pr93202.c
index 5501191ea52c..5de003fac421 100644
--- a/gcc/testsuite/gcc.target/riscv/pr93202.c
+++ b/gcc/testsuite/gcc.target/riscv/pr93202.c
@@ -1,7 +1,7 @@
 /* PR inline-asm/93202 */
 /* { dg-do compile { target fpic } } */
 /* { dg-options "-fpic" } */
-/* { dg-skip-if "" { *-*-* } { "-flto -fno-fat-lto-objects" } } */
+/* { dg-skip-if "" { *-*-* } { "-flto" } } */
 
 void
 foo (void)

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Deduplicate arch subset list processing

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:6b9226f62dd3a5425815a0b1ddf64215548b2669

commit 6b9226f62dd3a5425815a0b1ddf64215548b2669
Author: Christoph Müllner 
Date:   Fri Jul 5 01:09:46 2024 +0200

RISC-V: Deduplicate arch subset list processing

We have a code duplication in riscv_set_arch_by_subset_list() and
riscv_parse_arch_string(), where the latter function parses an ISA string
into a subset_list before doing the same as the former function.

riscv_parse_arch_string() is used to process command line options and
riscv_set_arch_by_subset_list() processes target attributes.
So, it is obvious that both functions should do the same.
Let's deduplicate the code to enforce this.

gcc/ChangeLog:

* common/config/riscv/riscv-common.cc 
(riscv_set_arch_by_subset_list):
Fix overlong line.
(riscv_parse_arch_string): Replace duplicated code by a call to
riscv_set_arch_by_subset_list.

Signed-off-by: Christoph Müllner 
(cherry picked from commit 85fa334fbcaa8e4b98ab197a8c9410dde87f0ae3)

Diff:
---
 gcc/common/config/riscv/riscv-common.cc | 32 ++--
 1 file changed, 6 insertions(+), 26 deletions(-)

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index b9bda3e110a2..dab2e7679653 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -1826,7 +1826,8 @@ riscv_set_arch_by_subset_list (riscv_subset_list 
*subset_list,
   else if (subset_list->xlen () == 64)
opts->x_target_flags |= MASK_64BIT;
 
-  for (arch_ext_flag_tab = &riscv_ext_flag_table[0]; 
arch_ext_flag_tab->ext;
+  for (arch_ext_flag_tab = &riscv_ext_flag_table[0];
+  arch_ext_flag_tab->ext;
   ++arch_ext_flag_tab)
{
  if (subset_list->lookup (arch_ext_flag_tab->ext))
@@ -1850,30 +1851,6 @@ riscv_parse_arch_string (const char *isa,
   if (!subset_list)
 return;
 
-  if (opts)
-{
-  const riscv_ext_flag_table_t *arch_ext_flag_tab;
-  /* Clean up target flags before we set.  */
-  for (arch_ext_flag_tab = &riscv_ext_flag_table[0];
-  arch_ext_flag_tab->ext;
-  ++arch_ext_flag_tab)
-   opts->*arch_ext_flag_tab->var_ref &= ~arch_ext_flag_tab->mask;
-
-  if (subset_list->xlen () == 32)
-   opts->x_target_flags &= ~MASK_64BIT;
-  else if (subset_list->xlen () == 64)
-   opts->x_target_flags |= MASK_64BIT;
-
-
-  for (arch_ext_flag_tab = &riscv_ext_flag_table[0];
-  arch_ext_flag_tab->ext;
-  ++arch_ext_flag_tab)
-   {
- if (subset_list->lookup (arch_ext_flag_tab->ext))
-   opts->*arch_ext_flag_tab->var_ref |= arch_ext_flag_tab->mask;
-   }
-}
-
   /* Avoid double delete if current_subset_list equals cmdline_subset_list.  */
   if (current_subset_list && current_subset_list != cmdline_subset_list)
 delete current_subset_list;
@@ -1881,7 +1858,10 @@ riscv_parse_arch_string (const char *isa,
   if (cmdline_subset_list)
 delete cmdline_subset_list;
 
-  current_subset_list = cmdline_subset_list = subset_list;
+  cmdline_subset_list = subset_list;
+  /* current_subset_list is set in the call below.  */
+
+  riscv_set_arch_by_subset_list (subset_list, opts);
 }
 
 /* Return the riscv_cpu_info entry for CPU, NULL if not found.  */

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Fix comment/naming in attribute parsing code

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:16d1d5b7db194fa7e0373bf78fccabdf8ef0d009

commit 16d1d5b7db194fa7e0373bf78fccabdf8ef0d009
Author: Christoph Müllner 
Date:   Fri Jul 5 04:58:07 2024 +0200

RISC-V: Fix comment/naming in attribute parsing code

Function target attributes have to be separated by semi-colons.
Let's fix the comment and variable naming to better explain what
the code does.

gcc/ChangeLog:

* config/riscv/riscv-target-attr.cc (riscv_process_target_attr):
Fix comments and variable names.

Signed-off-by: Christoph Müllner 
(cherry picked from commit 5ef0b7d2048a7142174ee3e8e021fc1a9c3e3334)

Diff:
---
 gcc/config/riscv/riscv-target-attr.cc | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/gcc/config/riscv/riscv-target-attr.cc 
b/gcc/config/riscv/riscv-target-attr.cc
index 19eb7b06d548..0bbe7df25d19 100644
--- a/gcc/config/riscv/riscv-target-attr.cc
+++ b/gcc/config/riscv/riscv-target-attr.cc
@@ -338,11 +338,11 @@ riscv_process_target_attr (tree fndecl, tree args, 
location_t loc,
   char *str_to_check = buf.get ();
   strcpy (str_to_check, TREE_STRING_POINTER (args));
 
-  /* Used to catch empty spaces between commas i.e.
+  /* Used to catch empty spaces between semi-colons i.e.
  attribute ((target ("attr1;;attr2"))).  */
-  unsigned int num_commas = num_occurences_in_str (';', str_to_check);
+  unsigned int num_semicolons = num_occurences_in_str (';', str_to_check);
 
-  /* Handle multiple target attributes separated by ','.  */
+  /* Handle multiple target attributes separated by ';'.  */
   char *token = strtok_r (str_to_check, ";", &str_to_check);
 
   riscv_target_attr_parser attr_parser (loc);
@@ -354,7 +354,7 @@ riscv_process_target_attr (tree fndecl, tree args, 
location_t loc,
   token = strtok_r (NULL, ";", &str_to_check);
 }
 
-  if (num_attrs != num_commas + 1)
+  if (num_attrs != num_semicolons + 1)
 {
   error_at (loc, "malformed % attribute",
TREE_STRING_POINTER (args));

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: fix zcmp popretz [PR113715]

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:4649bea8adb5b29d566dd4c63f68e56a877ebefc

commit 4649bea8adb5b29d566dd4c63f68e56a877ebefc
Author: Fei Gao 
Date:   Tue Jul 9 10:00:29 2024 +

RISC-V: fix zcmp popretz [PR113715]

No functional changes compared with V1, just spaces to table conversion
in testcases to pass check-function-bodies.

V1 passed regression locally but suprisingly failed in pre-commit CI, after
picking the patch from patchwork, I realize table got coverted to spaces
before sending the patch.

Root cause:

https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=b27d323a368033f0b37e93c57a57a35fd9997864
Commit above tries in targetm.gen_epilogue () to detect if
there's li a0,0 insn at the end of insn chain, if so, cm.popret
is replaced by cm.popretz and li a0,0 insn is deleted.

Insertion of the generated epilogue sequence
into the insn chain doesn't happen at this moment.
If later shrink-wrap decides NOT to insert the epilogue sequence at the end
of insn chain, then the li a0,0 insn has already been mistakeny removed.

Fix this issue by removing generation of cm.popretz in epilogue,
leaving the assignment to a0 and use insn with cm.popret.

That's likely going to result in some kind of code size regression,
but not a correctness regression.

Optimization can be done in future.

Signed-off-by: Fei Gao 

gcc/ChangeLog:
PR target/113715

* config/riscv/riscv.cc (riscv_zcmp_can_use_popretz): Removed.
(riscv_gen_multi_pop_insn): Remove generation of cm.popretz.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rv32e_zcmp.c: Adapt TC.
* gcc.target/riscv/rv32i_zcmp.c: Likewise.

(cherry picked from commit 7a345d0314f8cf0f15ca3664b1e4430d65764570)

Diff:
---
 gcc/config/riscv/riscv.cc   | 53 -
 gcc/testsuite/gcc.target/riscv/rv32e_zcmp.c |  3 +-
 gcc/testsuite/gcc.target/riscv/rv32i_zcmp.c |  3 +-
 3 files changed, 4 insertions(+), 55 deletions(-)

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 4acd643fd8d3..ce73c18f88f8 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -8167,52 +8167,6 @@ riscv_adjust_libcall_cfi_epilogue ()
   return dwarf;
 }
 
-/* return true if popretz pattern can be matched.
-   set (reg 10 a0) (const_int 0)
-   use (reg 10 a0)
-   NOTE_INSN_EPILOGUE_BEG  */
-static rtx_insn *
-riscv_zcmp_can_use_popretz (void)
-{
-  rtx_insn *insn = NULL, *use = NULL, *clear = NULL;
-
-  /* sequence stack for NOTE_INSN_EPILOGUE_BEG*/
-  struct sequence_stack *outer_seq = get_current_sequence ()->next;
-  if (!outer_seq)
-return NULL;
-  insn = outer_seq->first;
-  if (!insn || !NOTE_P (insn) || NOTE_KIND (insn) != NOTE_INSN_EPILOGUE_BEG)
-return NULL;
-
-  /* sequence stack for the insn before NOTE_INSN_EPILOGUE_BEG*/
-  outer_seq = outer_seq->next;
-  if (outer_seq)
-insn = outer_seq->last;
-
-  /* skip notes  */
-  while (insn && NOTE_P (insn))
-{
-  insn = PREV_INSN (insn);
-}
-  use = insn;
-
-  /* match use (reg 10 a0)  */
-  if (use == NULL || !INSN_P (use) || GET_CODE (PATTERN (use)) != USE
-  || !REG_P (XEXP (PATTERN (use), 0))
-  || REGNO (XEXP (PATTERN (use), 0)) != A0_REGNUM)
-return NULL;
-
-  /* match set (reg 10 a0) (const_int 0 [0])  */
-  clear = PREV_INSN (use);
-  if (clear != NULL && INSN_P (clear) && GET_CODE (PATTERN (clear)) == SET
-  && REG_P (SET_DEST (PATTERN (clear)))
-  && REGNO (SET_DEST (PATTERN (clear))) == A0_REGNUM
-  && SET_SRC (PATTERN (clear)) == const0_rtx)
-return clear;
-
-  return NULL;
-}
-
 static void
 riscv_gen_multi_pop_insn (bool use_multi_pop_normal, unsigned mask,
  unsigned multipop_size)
@@ -8223,13 +8177,6 @@ riscv_gen_multi_pop_insn (bool use_multi_pop_normal, 
unsigned mask,
   if (!use_multi_pop_normal)
 insn = emit_insn (
   riscv_gen_multi_push_pop_insn (POP_IDX, multipop_size, regs_count));
-  else if (rtx_insn *clear_a0_insn = riscv_zcmp_can_use_popretz ())
-{
-  delete_insn (NEXT_INSN (clear_a0_insn));
-  delete_insn (clear_a0_insn);
-  insn = emit_jump_insn (
-   riscv_gen_multi_push_pop_insn (POPRETZ_IDX, multipop_size, regs_count));
-}
   else
 insn = emit_jump_insn (
   riscv_gen_multi_push_pop_insn (POPRET_IDX, multipop_size, regs_count));
diff --git a/gcc/testsuite/gcc.target/riscv/rv32e_zcmp.c 
b/gcc/testsuite/gcc.target/riscv/rv32e_zcmp.c
index 50e443573ad9..0af4d7199f68 100644
--- a/gcc/testsuite/gcc.target/riscv/rv32e_zcmp.c
+++ b/gcc/testsuite/gcc.target/riscv/rv32e_zcmp.c
@@ -259,7 +259,8 @@ foo (void)
 **test_popretz:
 ** cm.push {ra}, -16
 ** callf1
-** cm.popretz  {ra}, 16
+** li  a0,0
+** cm.popret   {ra}, 16
 */
 long
 test_popretz ()
diff --git a/gcc/testsuite/gcc.target/riscv/rv32i_zcmp.c 
b/gcc/testsu

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add support for B standard extension

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:ac013ac6c759c6398db35fcc76265300375f5b37

commit ac013ac6c759c6398db35fcc76265300375f5b37
Author: Edwin Lu 
Date:   Wed Jul 10 09:44:48 2024 -0700

RISC-V: Add support for B standard extension

This patch adds support for recognizing the B standard extension to be the
collection of Zba, Zbb, Zbs extensions for consistency and conciseness
across toolchains

https://github.com/riscv/riscv-b/tags

gcc/ChangeLog:

* common/config/riscv/riscv-common.cc: Add imply rules for B 
extension
* config/riscv/arch-canonicalize: Ditto

Signed-off-by: Edwin Lu 
(cherry picked from commit 2a90c41a131080e5fdd2b5554fcdba5c654cb93f)

Diff:
---
 gcc/common/config/riscv/riscv-common.cc | 7 +++
 gcc/config/riscv/arch-canonicalize  | 1 +
 2 files changed, 8 insertions(+)

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index dab2e7679653..b0a16f5bd30f 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -84,6 +84,10 @@ static const riscv_implied_info_t riscv_implied_info[] =
 
   {"zabha", "zaamo"},
 
+  {"b", "zba"},
+  {"b", "zbb"},
+  {"b", "zbs"},
+
   {"zdinx", "zfinx"},
   {"zfinx", "zicsr"},
   {"zdinx", "zicsr"},
@@ -245,6 +249,8 @@ static const struct riscv_ext_version 
riscv_ext_version_table[] =
   {"c", ISA_SPEC_CLASS_20190608, 2, 0},
   {"c", ISA_SPEC_CLASS_2P2,  2, 0},
 
+  {"b",   ISA_SPEC_CLASS_NONE, 1, 0},
+
   {"h",   ISA_SPEC_CLASS_NONE, 1, 0},
 
   {"v",   ISA_SPEC_CLASS_NONE, 1, 0},
@@ -405,6 +411,7 @@ static const struct riscv_ext_version 
riscv_ext_version_table[] =
 static const struct riscv_ext_version riscv_combine_info[] =
 {
   {"a", ISA_SPEC_CLASS_20191213, 2, 1},
+  {"b",  ISA_SPEC_CLASS_NONE, 1, 0},
   {"zk",  ISA_SPEC_CLASS_NONE, 1, 0},
   {"zkn",  ISA_SPEC_CLASS_NONE, 1, 0},
   {"zks",  ISA_SPEC_CLASS_NONE, 1, 0},
diff --git a/gcc/config/riscv/arch-canonicalize 
b/gcc/config/riscv/arch-canonicalize
index 35a7fe4455a6..2ea514dd9869 100755
--- a/gcc/config/riscv/arch-canonicalize
+++ b/gcc/config/riscv/arch-canonicalize
@@ -45,6 +45,7 @@ IMPLIED_EXT = {
   "zabha" : ["zaamo"],
 
   "f" : ["zicsr"],
+  "b" : ["zba", "zbb", "zbs"],
   "zdinx" : ["zfinx", "zicsr"],
   "zfinx" : ["zicsr"],
   "zhinx" : ["zhinxmin", "zfinx", "zicsr"],

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Update testsuite to use b

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:6b32e85e97ef5f5654bb070172659f967c5ba50f

commit 6b32e85e97ef5f5654bb070172659f967c5ba50f
Author: Edwin Lu 
Date:   Wed Jul 3 17:17:27 2024 -0700

RISC-V: Update testsuite to use b

Update all instances of zba_zbb_zbs in the testsuite to use b instead

gcc/testsuite/ChangeLog:

* g++.target/riscv/redundant-bitmap-1.C: Use gcb instead of
zba_zbb_zbs
* g++.target/riscv/redundant-bitmap-2.C: Ditto
* g++.target/riscv/redundant-bitmap-3.C: Ditto
* g++.target/riscv/redundant-bitmap-4.C: Ditto
* gcc.target/riscv/shift-add-1.c: Ditto
* gcc.target/riscv/shift-add-2.c: Ditto
* gcc.target/riscv/synthesis-1.c: Ditto
* gcc.target/riscv/synthesis-2.c: Ditto
* gcc.target/riscv/synthesis-3.c: Ditto
* gcc.target/riscv/synthesis-4.c: Ditto
* gcc.target/riscv/synthesis-5.c: Ditto
* gcc.target/riscv/synthesis-6.c: Ditto
* gcc.target/riscv/synthesis-7.c: Ditto
* gcc.target/riscv/synthesis-8.c: Ditto
* gcc.target/riscv/zba_zbs_and-1.c: Ditto
* gcc.target/riscv/zbs-zext-3.c: Ditto
* lib/target-supports.exp: Add b to riscv_get_arch

Signed-off-by: Edwin Lu 
(cherry picked from commit 04df2a924bba38c271bfe4ed0e94af1877413818)

Diff:
---
 gcc/testsuite/g++.target/riscv/redundant-bitmap-1.C | 2 +-
 gcc/testsuite/g++.target/riscv/redundant-bitmap-2.C | 2 +-
 gcc/testsuite/g++.target/riscv/redundant-bitmap-3.C | 2 +-
 gcc/testsuite/g++.target/riscv/redundant-bitmap-4.C | 2 +-
 gcc/testsuite/gcc.target/riscv/shift-add-1.c| 2 +-
 gcc/testsuite/gcc.target/riscv/shift-add-2.c| 2 +-
 gcc/testsuite/gcc.target/riscv/synthesis-1.c| 2 +-
 gcc/testsuite/gcc.target/riscv/synthesis-2.c| 2 +-
 gcc/testsuite/gcc.target/riscv/synthesis-3.c| 2 +-
 gcc/testsuite/gcc.target/riscv/synthesis-4.c| 2 +-
 gcc/testsuite/gcc.target/riscv/synthesis-5.c| 2 +-
 gcc/testsuite/gcc.target/riscv/synthesis-6.c| 2 +-
 gcc/testsuite/gcc.target/riscv/synthesis-7.c| 2 +-
 gcc/testsuite/gcc.target/riscv/synthesis-8.c| 2 +-
 gcc/testsuite/gcc.target/riscv/zba_zbs_and-1.c  | 2 +-
 gcc/testsuite/gcc.target/riscv/zbs-zext-3.c | 4 ++--
 gcc/testsuite/lib/target-supports.exp   | 2 +-
 17 files changed, 18 insertions(+), 18 deletions(-)

diff --git a/gcc/testsuite/g++.target/riscv/redundant-bitmap-1.C 
b/gcc/testsuite/g++.target/riscv/redundant-bitmap-1.C
index 37066f10eeae..62bb2ab7b67d 100644
--- a/gcc/testsuite/g++.target/riscv/redundant-bitmap-1.C
+++ b/gcc/testsuite/g++.target/riscv/redundant-bitmap-1.C
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O2 -march=rv64gc_zba_zbb_zbs -mabi=lp64" } */
+/* { dg-options "-O2 -march=rv64gcb -mabi=lp64" } */
 
 void setBit(char &a, int b) {
 char c = 0x1UL << b;
diff --git a/gcc/testsuite/g++.target/riscv/redundant-bitmap-2.C 
b/gcc/testsuite/g++.target/riscv/redundant-bitmap-2.C
index 86acaba298fc..52204daecd11 100644
--- a/gcc/testsuite/g++.target/riscv/redundant-bitmap-2.C
+++ b/gcc/testsuite/g++.target/riscv/redundant-bitmap-2.C
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O2 -march=rv64gc_zba_zbb_zbs -mabi=lp64" } */
+/* { dg-options "-O2 -march=rv64gcb -mabi=lp64" } */
 
 void setBit(char &a, int b) {
 char c = 0x1UL << b;
diff --git a/gcc/testsuite/g++.target/riscv/redundant-bitmap-3.C 
b/gcc/testsuite/g++.target/riscv/redundant-bitmap-3.C
index 16bd7c1785e7..6745220f2f41 100644
--- a/gcc/testsuite/g++.target/riscv/redundant-bitmap-3.C
+++ b/gcc/testsuite/g++.target/riscv/redundant-bitmap-3.C
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O2 -march=rv64gc_zba_zbb_zbs -mabi=lp64" } */
+/* { dg-options "-O2 -march=rv64gcb -mabi=lp64" } */
 
 void setBit(char &a, int b) {
 char c = 0x1UL << b;
diff --git a/gcc/testsuite/g++.target/riscv/redundant-bitmap-4.C 
b/gcc/testsuite/g++.target/riscv/redundant-bitmap-4.C
index f664ee01a016..5e351fe457e9 100644
--- a/gcc/testsuite/g++.target/riscv/redundant-bitmap-4.C
+++ b/gcc/testsuite/g++.target/riscv/redundant-bitmap-4.C
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O2 -march=rv64gc_zba_zbb_zbs -mabi=lp64" } */
+/* { dg-options "-O2 -march=rv64gcb -mabi=lp64" } */
 
 void setBit(char &a, int b) {
 char c = 0x1UL << b;
diff --git a/gcc/testsuite/gcc.target/riscv/shift-add-1.c 
b/gcc/testsuite/gcc.target/riscv/shift-add-1.c
index d98875c32716..db84a51a2227 100644
--- a/gcc/testsuite/gcc.target/riscv/shift-add-1.c
+++ b/gcc/testsuite/gcc.target/riscv/shift-add-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gc_zba_zbb_zbs -mabi=lp64" } */
+/* { dg-options "-march=rv64gcb -mabi=lp64" } */
 /* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */
 
 int composeFromSurrogate(const unsigned short high) {
diff --git a/gcc/testsuite/gcc.

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: c implies zca, and conditionally zcf & zcd

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:b3586773824f09bf2bf16ce398d2f988428c0821

commit b3586773824f09bf2bf16ce398d2f988428c0821
Author: Fei Gao 
Date:   Wed Jul 10 10:12:02 2024 +

RISC-V: c implies zca, and conditionally zcf & zcd

According to Zc-1.0.4-3.pdf from

https://github.com/riscvarchive/riscv-code-size-reduction/releases/tag/v1.0.4-3
The rule is that:
- C always implies Zca
- C+F implies Zcf (RV32 only)
- C+D implies Zcd

Signed-off-by: Fei Gao 
gcc/ChangeLog:

* common/config/riscv/riscv-common.cc:
c implies zca, and conditionally zcf & zcd.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/attribute-15.c: adapt TC.
* gcc.target/riscv/attribute-16.c: likewise.
* gcc.target/riscv/attribute-17.c: likewise.
* gcc.target/riscv/attribute-18.c: likewise.
* gcc.target/riscv/pr110696.c: likewise.
* gcc.target/riscv/rvv/base/abi-callee-saved-1-zcmp.c: likewise.
* gcc.target/riscv/rvv/base/abi-callee-saved-2-zcmp.c: likewise.
* gcc.target/riscv/rvv/base/pr114352-1.c: likewise.
* gcc.target/riscv/rvv/base/pr114352-3.c: likewise.
* gcc.target/riscv/arch-39.c: New test.
* gcc.target/riscv/arch-40.c: New test.

(cherry picked from commit 36e5e409190e595638cec053ea034d20d5c74d6b)

Diff:
---
 gcc/common/config/riscv/riscv-common.cc  | 12 
 gcc/testsuite/gcc.target/riscv/arch-39.c |  7 +++
 gcc/testsuite/gcc.target/riscv/arch-40.c |  7 +++
 gcc/testsuite/gcc.target/riscv/attribute-15.c|  2 +-
 gcc/testsuite/gcc.target/riscv/attribute-16.c|  2 +-
 gcc/testsuite/gcc.target/riscv/attribute-17.c|  2 +-
 gcc/testsuite/gcc.target/riscv/attribute-18.c|  2 +-
 gcc/testsuite/gcc.target/riscv/pr110696.c|  2 +-
 .../gcc.target/riscv/rvv/base/abi-callee-saved-1-zcmp.c  |  2 +-
 .../gcc.target/riscv/rvv/base/abi-callee-saved-2-zcmp.c  |  2 +-
 gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-1.c |  4 ++--
 gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-3.c |  8 
 12 files changed, 39 insertions(+), 13 deletions(-)

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index b0a16f5bd30f..3c4178c19c99 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -82,6 +82,18 @@ static const riscv_implied_info_t riscv_implied_info[] =
   {"a", "zaamo"},
   {"a", "zalrsc"},
 
+  {"c", "zca"},
+  {"c", "zcf",
+   [] (const riscv_subset_list *subset_list) -> bool
+   {
+ return subset_list->xlen () == 32 && subset_list->lookup ("f");
+   }},
+  {"c", "zcd",
+   [] (const riscv_subset_list *subset_list) -> bool
+   {
+ return subset_list->lookup ("d");
+   }},
+
   {"zabha", "zaamo"},
 
   {"b", "zba"},
diff --git a/gcc/testsuite/gcc.target/riscv/arch-39.c 
b/gcc/testsuite/gcc.target/riscv/arch-39.c
new file mode 100644
index ..beeb81e44c50
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/arch-39.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64idc_zcmt -mabi=lp64d" } */
+int
+foo ()
+{}
+
+/* { dg-error "zcd conflicts with zcmt" "" { target *-*-* } 0 } */
diff --git a/gcc/testsuite/gcc.target/riscv/arch-40.c 
b/gcc/testsuite/gcc.target/riscv/arch-40.c
new file mode 100644
index ..eaefaf1d0d75
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/arch-40.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64idc_zcmp -mabi=lp64d" } */
+int
+foo ()
+{}
+
+/* { dg-error "zcd conflicts with zcmp" "" { target *-*-* } 0 } */
diff --git a/gcc/testsuite/gcc.target/riscv/attribute-15.c 
b/gcc/testsuite/gcc.target/riscv/attribute-15.c
index a2e394b6489b..ac6caaecd4f7 100644
--- a/gcc/testsuite/gcc.target/riscv/attribute-15.c
+++ b/gcc/testsuite/gcc.target/riscv/attribute-15.c
@@ -3,4 +3,4 @@
 int foo()
 {
 }
-/* { dg-final { scan-assembler ".attribute arch, 
\"rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0_zaamo1p0_zalrsc1p0\"" } } */
+/* { dg-final { scan-assembler ".attribute arch, 
\"rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zcf1p0\"" 
} } */
diff --git a/gcc/testsuite/gcc.target/riscv/attribute-16.c 
b/gcc/testsuite/gcc.target/riscv/attribute-16.c
index d2b18160cb5d..539e426ca976 100644
--- a/gcc/testsuite/gcc.target/riscv/attribute-16.c
+++ b/gcc/testsuite/gcc.target/riscv/attribute-16.c
@@ -3,4 +3,4 @@
 int foo()
 {
 }
-/* { dg-final { scan-assembler ".attribute arch, 
\"rv32i2p1_m2p0_a2p0_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0\"" 
} } */
+/* { dg-final { scan-assembler ".attribute arch, 
\"rv32i2p1_m2p0_a2p0_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zcf1p0\""
 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/attribute-17.c 
b/g

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for vector .SAT_SUB in zip benchmark

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:1726acdf1f7a3c3129a08fa571d750c5d09f8176

commit 1726acdf1f7a3c3129a08fa571d750c5d09f8176
Author: Pan Li 
Date:   Thu Jul 11 15:54:32 2024 +0800

RISC-V: Add testcases for vector .SAT_SUB in zip benchmark

This patch would like to add the test cases for the vector .SAT_SUB in
the zip benchmark.  Aka:

Form in zip benchmark:
  #define DEF_VEC_SAT_U_SUB_ZIP(T1, T2) \
  void __attribute__((noinline))\
  vec_sat_u_sub_##T1##_##T2##_fmt_zip (T1 *x, T2 b, unsigned limit) \
  { \
T2 a;   \
T1 *p = x;  \
do {\
  a = *--p; \
  *p = (T1)(a >= b ? a - b : 0);\
} while (--limit);  \
  }

DEF_VEC_SAT_U_SUB_ZIP(uint8_t, uint16_t)

vec_sat_u_sub_uint16_t_uint32_t_fmt_zip:
  ...
  vsetvli   a4,zero,e32,m1,ta,ma
  vmv.v.x   v6,a1
  vsetvli   zero,zero,e16,mf2,ta,ma
  vid.v v2
  lia4,-1
  vnclipu.wiv6,v6,0   // .SAT_TRUNC
.L3:
  vle16.v   v3,0(a3)
  vrsub.vx  v5,v2,a6
  mva7,a4
  addw  a4,a4,t3
  vrgather.vv   v1,v3,v5
  vssubu.vv v1,v1,v6  // .SAT_SUB
  vrgather.vv   v3,v1,v5
  vse16.v   v3,0(a3)
  sub   a3,a3,t1
  bgtu  t4,a4,.L3

Passed the rv64gcv tests.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: Add test
helper macros.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_data.h: Add test
data for .SAT_SUB in zip benchmark.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_binary_vx.h: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_zip-run.c: New 
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_zip.c: New test.

Signed-off-by: Pan Li 
(cherry picked from commit b3c686416e88bf135def0e72d316713af01445a1)

Diff:
---
 .../riscv/rvv/autovec/binop/vec_sat_arith.h| 18 +
 .../riscv/rvv/autovec/binop/vec_sat_binary_vx.h| 22 ++
 .../riscv/rvv/autovec/binop/vec_sat_data.h | 81 ++
 .../rvv/autovec/binop/vec_sat_u_sub_zip-run.c  | 16 +
 .../riscv/rvv/autovec/binop/vec_sat_u_sub_zip.c| 18 +
 5 files changed, 155 insertions(+)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h
index 10459807b2c4..416a1e49a47b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h
@@ -322,6 +322,19 @@ vec_sat_u_sub_##T##_fmt_10 (T *out, T *op_1, T *op_2, 
unsigned limit) \
 } \
 }
 
+#define DEF_VEC_SAT_U_SUB_ZIP(T1, T2) \
+void __attribute__((noinline))\
+vec_sat_u_sub_##T1##_##T2##_fmt_zip (T1 *x, T2 b, unsigned limit) \
+{ \
+  T2 a;   \
+  T1 *p = x;  \
+  do {\
+a = *--p; \
+*p = (T1)(a >= b ? a - b : 0);\
+  } while (--limit);  \
+}
+#define DEF_VEC_SAT_U_SUB_ZIP_WRAP(T1, T2) DEF_VEC_SAT_U_SUB_ZIP(T1, T2)
+
 #define RUN_VEC_SAT_U_SUB_FMT_1(T, out, op_1, op_2, N) \
   vec_sat_u_sub_##T##_fmt_1(out, op_1, op_2, N)
 
@@ -352,6 +365,11 @@ vec_sat_u_sub_##T##_fmt_10 (T *out, T *op_1, T *op_2, 
unsigned limit) \
 #define RUN_VEC_SAT_U_SUB_FMT_10(T, out, op_1, op_2, N) \
   vec_sat_u_sub_##T##_fmt_10(out, op_1, op_2, N)
 
+#define RUN_VEC_SAT_U_SUB_FMT_ZIP(T1, T2, x, b, N) \
+  vec_sat_u_sub_##T1##_##T2##_fmt_zip(x, b, N)
+#define RUN_VEC_SAT_U_SUB_FMT_ZIP_WRAP(T1, T2, x, b, N) \
+  RUN_VEC_SAT_U_SUB_FMT_ZIP(T1, T2, x, b, N) \
+
 
/**/
 /* Saturation Sub Truncated (Unsigned and Signed) 
*/
 
/**/
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_binary_vx.h 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_binary_vx.h
new file mode 100644
index 0

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [to-be-committed, RISC-V] Eliminate unnecessary sign extension after inlined str[n]cmp

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:e0bf7a4734598402720ed5b86285705c1791e457

commit e0bf7a4734598402720ed5b86285705c1791e457
Author: Jeff Law 
Date:   Thu Jul 11 12:05:56 2024 -0600

[to-be-committed,RISC-V] Eliminate unnecessary sign extension after inlined 
str[n]cmp

This patch eliminates an unnecessary sign extension for scalar inlined
string comparisons on rv64.

Conceptually this is pretty simple.  Prove all the paths which "return"
a value from the inlined string comparison already have sign extended
values.

FINAL_LABEL is the point after the calculation of the return value.  So
if we have a jump to FINAL_LABEL, we must have a properly extended
result value at that point.

Second we're going to arrange in the .md part of the expander to use an
X mode temporary for the result.  After computing the result we will (if
necessary) extract the low part of the result using a SUBREG tagged with
the appropriate SUBREG_PROMOTED_* bits.

So with that background.

We find a jump to FINAL_LABEL in emit_strcmp_scalar_compare_byte.  Since
we know the result is X mode, we can just emit the subtraction of the
two chars in X mode and we'll have a properly sign extended result.

There's 4 jumps to final_label in emit_strcmp_scalar.

The first is just returning zero and needs trivial simplification to not
force the result into SImode.

The second is after calling strcmp in the library.  The ABI mandates
that value is sign extended, so there's nothing to do for that case.

The 3rd occurs after a call to
emit_strcmp_scalar_result_calculation_nonul.  If we dive into that
routine it needs simplificationq similar to what we did in
emit_strcmp_scalar_compare_byte

The 4th occurs after a call to emit_strcmp_scalar_result_calculation
which again needs trivial adjustment like we've done in the other routines.

Finally, at the end of expand_strcmp, just store the X mode result
sitting in SUB to RESULT.

The net of all that is we know every path has its result properly
extended to X mode.  Standard redundant extension removal will take care
of the rest.

We've been running this within Ventana for about 6 months, so naturally
it's been through various QA cycles, dhrystone, spec2017, etc.  It's
also been through a build/test cycle in my tester.  Waiting on results
from the pre-commit testing before moving forward.

gcc/
* config/riscv/riscv-string.cc
(emit_strcmp_scalar_compare_byte): Set RESULT directly rather
than using a new temporary.
(emit_strcmp_scalar_result_calculation_nonul): Likewise.
(emit_strcmp_scalar_result_calculation): Likewise.
(riscv_expand_strcmp_scalar): Use CONST0_RTX rather than
generating a new node.
(expand_strcmp): Copy directly from SUB to RESULT.
* config/riscv/riscv.md (cmpstrnsi, cmpstrsi): Pass an X
mode temporary to the expansion routines.  If necessary
extract low part of the word to store in final result location.

(cherry picked from commit 74d8accaf88f83bfcab1150bf9be5140e7ac0e94)

Diff:
---
 gcc/config/riscv/riscv-string.cc | 15 +--
 gcc/config/riscv/riscv.md| 28 
 2 files changed, 29 insertions(+), 14 deletions(-)

diff --git a/gcc/config/riscv/riscv-string.cc b/gcc/config/riscv/riscv-string.cc
index 257a514d2901..4736228e6f14 100644
--- a/gcc/config/riscv/riscv-string.cc
+++ b/gcc/config/riscv/riscv-string.cc
@@ -140,9 +140,7 @@ static void
 emit_strcmp_scalar_compare_byte (rtx result, rtx data1, rtx data2,
 rtx final_label)
 {
-  rtx tmp = gen_reg_rtx (Xmode);
-  do_sub3 (tmp, data1, data2);
-  emit_insn (gen_movsi (result, gen_lowpart (SImode, tmp)));
+  do_sub3 (result, data1, data2);
   emit_jump_insn (gen_jump (final_label));
   emit_barrier (); /* No fall-through.  */
 }
@@ -310,8 +308,7 @@ emit_strcmp_scalar_result_calculation_nonul (rtx result, 
rtx data1, rtx data2)
   rtx tmp = gen_reg_rtx (Xmode);
   emit_insn (gen_slt_3 (LTU, Xmode, Xmode, tmp, data1, data2));
   do_neg2 (tmp, tmp);
-  do_ior3 (tmp, tmp, const1_rtx);
-  emit_insn (gen_movsi (result, gen_lowpart (SImode, tmp)));
+  do_ior3 (result, tmp, const1_rtx);
 }
 
 /* strcmp-result calculation.
@@ -367,9 +364,7 @@ emit_strcmp_scalar_result_calculation (rtx result, rtx 
data1, rtx data2,
   unsigned int shiftr = (xlen - 1) * BITS_PER_UNIT;
   do_lshr3 (data1, data1, GEN_INT (shiftr));
   do_lshr3 (data2, data2, GEN_INT (shiftr));
-  rtx tmp = gen_reg_rtx (Xmode);
-  do_sub3 (tmp, data1, data2);
-  emit_insn (gen_movsi (result, gen_lowpart (SImode, tmp)));
+  do_sub3 (result, data1, data2);
 }
 
 /* Expand str(n)cmp using Zbb/TheadBb instructions.
@@ -444,7 +439,7 @@ riscv_expand_strcmp_scalar (rtx result, rtx src1, 

[gcc r15-1977] libstdc++: Switch gcc.gnu.org links to https

[Gerald Pfeifer via Libstdc++-cvs]

https://gcc.gnu.org/g:26c9b095edf1ffa217f6cb2783b8ccfc5f4b1393

commit r15-1977-g26c9b095edf1ffa217f6cb2783b8ccfc5f4b1393
Author: Gerald Pfeifer 
Date:   Thu Jul 11 23:58:45 2024 +0200

libstdc++: Switch gcc.gnu.org links to https

libstdc++-v3:
* doc/xml/manual/using.xml: Switch gcc.gnu.org links to https.
* doc/html/manual/using_concurrency.html: Regenerate.
* doc/html/manual/using_dynamic_or_shared.html: Ditto.
* doc/html/manual/using_headers.html: Ditto.
* doc/html/manual/using_namespaces.html: Ditto.

Diff:
---
 libstdc++-v3/doc/html/manual/using_concurrency.html   |  2 +-
 libstdc++-v3/doc/html/manual/using_dynamic_or_shared.html |  4 ++--
 libstdc++-v3/doc/html/manual/using_headers.html   |  2 +-
 libstdc++-v3/doc/html/manual/using_namespaces.html|  2 +-
 libstdc++-v3/doc/xml/manual/using.xml | 10 +-
 5 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/libstdc++-v3/doc/html/manual/using_concurrency.html 
b/libstdc++-v3/doc/html/manual/using_concurrency.html
index e09fc5e15bcb..d21f15884949 100644
--- a/libstdc++-v3/doc/html/manual/using_concurrency.html
+++ b/libstdc++-v3/doc/html/manual/using_concurrency.html
@@ -62,7 +62,7 @@ gcc version 4.1.2 20070925 (Red Hat 4.1.2-33)
 and -march=native, although specifics vary
 depending on the host environment. See
 Command Options and
-http://gcc.gnu.org/onlinedocs/gcc/Option-Summary.html"; 
target="_top">Machine
+https://gcc.gnu.org/onlinedocs/gcc/Option-Summary.html"; 
target="_top">Machine
 Dependent Options.

   An implementation of the
diff --git a/libstdc++-v3/doc/html/manual/using_dynamic_or_shared.html 
b/libstdc++-v3/doc/html/manual/using_dynamic_or_shared.html
index f1e727800c28..a5a99ffef58c 100644
--- a/libstdc++-v3/doc/html/manual/using_dynamic_or_shared.html
+++ b/libstdc++-v3/doc/html/manual/using_dynamic_or_shared.html
@@ -75,10 +75,10 @@
   But how?
 
 A quick read of the relevant part of the GCC
-  manual, http://gcc.gnu.org/onlinedocs/gcc/Invoking-G_002b_002b.html#Invoking-G_002b_002b";
 target="_top">Compiling
+  manual, https://gcc.gnu.org/onlinedocs/gcc/Invoking-G_002b_002b.html#Invoking-G_002b_002b";
 target="_top">Compiling
   C++ Programs, specifies linking against a C++
   library. More details from the
-  GCC http://gcc.gnu.org/faq.html#rpath"; 
target="_top">FAQ,
+  GCC https://gcc.gnu.org/faq.html#rpath"; 
target="_top">FAQ,
   which states GCC does not, by default, 
specify a
   location so that the dynamic linker can find dynamic libraries at
   runtime.
diff --git a/libstdc++-v3/doc/html/manual/using_headers.html 
b/libstdc++-v3/doc/html/manual/using_headers.html
index a267e087a9d3..5f6698626541 100644
--- a/libstdc++-v3/doc/html/manual/using_headers.html
+++ b/libstdc++-v3/doc/html/manual/using_headers.html
@@ -186,5 +186,5 @@ g++ -Winvalid-pch -I. -include stdc++.h -H -g -O2 hello.cc 
-o test.exe
 ! ./stdc++.h.gch
 . /mnt/share/bld/H-x86-gcc.20071201/include/c++/4.3.0/iostream
 . /mnt/share/bld/H-x86-gcc.20071201include/c++/4.3.0/string
-The exclamation point to the left of the stdc++.h.gch listing means that the generated PCH file was 
used. Detailed information about creating precompiled header 
files can be found in the GCC http://gcc.gnu.org/onlinedocs/gcc/Precompiled-Headers.html"; 
target="_top">documentation.
+The exclamation point to the left of the stdc++.h.gch listing means that the generated PCH file was 
used. Detailed information about creating precompiled header 
files can be found in the GCC https://gcc.gnu.org/onlinedocs/gcc/Precompiled-Headers.html"; 
target="_top">documentation.
 Prev Up NextChapter 3. Using Home Macros
\ No newline at end of file
diff --git a/libstdc++-v3/doc/html/manual/using_namespaces.html 
b/libstdc++-v3/doc/html/manual/using_namespaces.html
index b036d6fa6ac6..1d0de6ca30db 100644
--- a/libstdc++-v3/doc/html/manual/using_namespaces.html
+++ b/libstdc++-v3/doc/html/manual/using_namespaces.html
@@ -13,7 +13,7 @@ and __gnu_pbds.
  The library uses a number of inline namespaces as 
implementation
 details that are not intended for users to refer to directly, these include
 std::__detail, std::__cxx11 and std::_V2.
- A complete list of implementation namespaces (including namespace 
contents) is available in the generated source http://gcc.gnu.org/onlinedocs/libstdc++/latest-doxygen/namespaces.html"; 
target="_top">documentation.
+A complete list of implementation namespaces (including namespace 
contents) is available in the generated source https://gcc.gnu.org/onlinedocs/libstdc++/latest-doxygen/namespaces.html"; 
target="_top">documentation.
 namespace 
std
   One standard requirement is that the library components are defined
   in namespace std::. Thus, in order to use 
these types or
diff --git a/libstdc++-v3/doc/xml/manual/using.xml 
b/lib

[gcc r15-1978] libbacktrace: remove trailing whitespace

[Ian Lance Taylor via Gcc-cvs]

https://gcc.gnu.org/g:02f7525e5e9e8d749c9ba2b9a925da4b202553ce

commit r15-1978-g02f7525e5e9e8d749c9ba2b9a925da4b202553ce
Author: Ian Lance Taylor 
Date:   Thu Jul 11 15:27:18 2024 -0700

libbacktrace: remove trailing whitespace

* dwarf.c: Remove trailing whitespace.
* macho.c: Likewise.

Diff:
---
 libbacktrace/dwarf.c | 4 ++--
 libbacktrace/macho.c | 1 -
 2 files changed, 2 insertions(+), 3 deletions(-)

diff --git a/libbacktrace/dwarf.c b/libbacktrace/dwarf.c
index ed0672964c24..cc36a0a2990d 100644
--- a/libbacktrace/dwarf.c
+++ b/libbacktrace/dwarf.c
@@ -1705,7 +1705,7 @@ add_ranges_from_ranges (
base = (uintptr_t) high;
   else
{
- if (!add_range (state, rdata, 
+ if (!add_range (state, rdata,
  (uintptr_t) low + base + base_address,
  (uintptr_t) high + base + base_address,
  error_callback, data, vec))
@@ -1904,7 +1904,7 @@ add_ranges (struct backtrace_state *state,
const struct dwarf_sections *dwarf_sections,
uintptr_t base_address, int is_bigendian,
struct unit *u, uintptr_t base, const struct pcrange *pcrange,
-   int (*add_range) (struct backtrace_state *state, void *rdata, 
+   int (*add_range) (struct backtrace_state *state, void *rdata,
  uintptr_t lowpc, uintptr_t highpc,
  backtrace_error_callback error_callback,
  void *data, void *vec),
diff --git a/libbacktrace/macho.c b/libbacktrace/macho.c
index b4856346ccc2..42f24721e6ac 100644
--- a/libbacktrace/macho.c
+++ b/libbacktrace/macho.c
@@ -674,7 +674,6 @@ macho_add_symtab (struct backtrace_state *state, int 
descriptor,
  struct macho_syminfo_data *p;
 
  p = backtrace_atomic_load_pointer (pp);
- 
  if (p == NULL)
break;

[gcc r15-1979] libbacktrace: suggest how to fix missing debug info

[Ian Lance Taylor via Gcc-cvs]

https://gcc.gnu.org/g:b96789abf8a51e8f70309799b5dfee36d4fb3da6

commit r15-1979-gb96789abf8a51e8f70309799b5dfee36d4fb3da6
Author: Ian Lance Taylor 
Date:   Thu Jul 11 15:39:07 2024 -0700

libbacktrace: suggest how to fix missing debug info

* elf.c (elf_nodebug): Suggest -g.
* macho.c (macho_nodebug): Suggest -g and dsymutil.
* pecoff.c (coff_nodebug): Suggest -g.

Diff:
---
 libbacktrace/elf.c| 2 +-
 libbacktrace/macho.c  | 2 +-
 libbacktrace/pecoff.c | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/libbacktrace/elf.c b/libbacktrace/elf.c
index 735f87525008..e6a66c0db905 100644
--- a/libbacktrace/elf.c
+++ b/libbacktrace/elf.c
@@ -589,7 +589,7 @@ elf_nodebug (struct backtrace_state *state, uintptr_t pc,
   return bdata.ret;
 }
 
-  error_callback (data, "no debug info in ELF executable", -1);
+  error_callback (data, "no debug info in ELF executable (make sure to compile 
with -g)", -1);
   return 0;
 }
 
diff --git a/libbacktrace/macho.c b/libbacktrace/macho.c
index 42f24721e6ac..5ceff05b29a5 100644
--- a/libbacktrace/macho.c
+++ b/libbacktrace/macho.c
@@ -324,7 +324,7 @@ macho_nodebug (struct backtrace_state *state 
ATTRIBUTE_UNUSED,
   backtrace_full_callback callback ATTRIBUTE_UNUSED,
   backtrace_error_callback error_callback, void *data)
 {
-  error_callback (data, "no debug info in Mach-O executable", -1);
+  error_callback (data, "no debug info in Mach-O executable (make sure to 
compile with -g; may need to run dsymutil)", -1);
   return 0;
 }
 
diff --git a/libbacktrace/pecoff.c b/libbacktrace/pecoff.c
index bbb59e26d7a6..e88e4d2b0383 100644
--- a/libbacktrace/pecoff.c
+++ b/libbacktrace/pecoff.c
@@ -240,7 +240,7 @@ coff_nodebug (struct backtrace_state *state 
ATTRIBUTE_UNUSED,
  backtrace_full_callback callback ATTRIBUTE_UNUSED,
  backtrace_error_callback error_callback, void *data)
 {
-  error_callback (data, "no debug info in PE/COFF executable", -1);
+  error_callback (data, "no debug info in PE/COFF executable (make sure to 
compile with -g)", -1);
   return 0;
 }

[gcc r15-1980] libstdc++: the specialization atomic_ref should use the primary template

[Jonathan Wakely via Libstdc++-cvs]

https://gcc.gnu.org/g:79d3f17b07884cc9486f5e6fb21beea97c153a55

commit r15-1980-g79d3f17b07884cc9486f5e6fb21beea97c153a55
Author: Damien Lebrun-Grandie 
Date:   Wed May 22 17:43:45 2024 -0400

libstdc++: the specialization atomic_ref should use the primary 
template

Per [atomics.ref.int] `bool` is excluded from the list of integral types
for which there is a specialization of the `atomic_ref` class template
and [Note 1] clearly states that `atomic_ref` "uses the primary
template" instead.

libstdc++-v3/ChangeLog:

* include/bits/atomic_base.h (__atomic_ref): Do not use integral
specialization for bool.

Signed-off-by: Damien Lebrun-Grandie 

Diff:
---
 libstdc++-v3/include/bits/atomic_base.h | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/libstdc++-v3/include/bits/atomic_base.h 
b/libstdc++-v3/include/bits/atomic_base.h
index 20901b7fc06f..1c2367b39b66 100644
--- a/libstdc++-v3/include/bits/atomic_base.h
+++ b/libstdc++-v3/include/bits/atomic_base.h
@@ -1478,7 +1478,8 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
 #undef _GLIBCXX20_INIT
 
   template, bool = is_floating_point_v<_Tp>>
+   bool = is_integral_v<_Tp> && !is_same_v<_Tp, bool>,
+   bool = is_floating_point_v<_Tp>>
 struct __atomic_ref;
 
   // base class for non-integral, non-floating-point, non-pointer types

[gcc r15-1981] libstdc++: Test that std::atomic_ref uses the primary template

[Jonathan Wakely via Libstdc++-cvs]

https://gcc.gnu.org/g:43763bd75f1d37189ba08657a322e91d240e8cf3

commit r15-1981-g43763bd75f1d37189ba08657a322e91d240e8cf3
Author: Jonathan Wakely 
Date:   Thu Jul 11 21:23:15 2024 +0100

libstdc++: Test that std::atomic_ref uses the primary template

The previous commit changed atomic_ref to not use the integral
specialization. This adds a test to verify that change. We can't
directly test that the primary template is used, but we can check that
the member functions of the integral specializations are not present.

libstdc++-v3/ChangeLog:

* testsuite/29_atomics/atomic_ref/bool.cc: New test.

Diff:
---
 libstdc++-v3/testsuite/29_atomics/atomic_ref/bool.cc | 15 +++
 1 file changed, 15 insertions(+)

diff --git a/libstdc++-v3/testsuite/29_atomics/atomic_ref/bool.cc 
b/libstdc++-v3/testsuite/29_atomics/atomic_ref/bool.cc
new file mode 100644
index ..4702932627e8
--- /dev/null
+++ b/libstdc++-v3/testsuite/29_atomics/atomic_ref/bool.cc
@@ -0,0 +1,15 @@
+// { dg-do compile { target c++20 } }
+
+#include 
+
+template concept has_and = requires (T& a) { a &= false; };
+template concept has_or = requires (T& a) { a |= false; };
+template concept has_xor = requires (T& a) { a ^= false; };
+template concept has_fetch_add = requires (T& a) { a.fetch_add(true); 
};
+template concept has_fetch_sub = requires (T& a) { a.fetch_sub(true); 
};
+
+static_assert( not has_and> );
+static_assert( not has_or> );
+static_assert( not has_xor> );
+static_assert( not has_fetch_add> );
+static_assert( not has_fetch_sub> );

[gcc r15-1982] libbacktrace: fix testsuite for clang

[Ian Lance Taylor via Gcc-cvs]

https://gcc.gnu.org/g:8f7c06df424fffa88422f83ba0a7c58576ae3d91

commit r15-1982-g8f7c06df424fffa88422f83ba0a7c58576ae3d91
Author: Ian Lance Taylor 
Date:   Thu Jul 11 16:07:06 2024 -0700

libbacktrace: fix testsuite for clang

* btest.c (test1, test3): Add optnone attribute.
* edtest.c (test1): Likewise.
* mtest.c (test1, test3): Likewise.
* configure.ac: Use -Wno-attributes and -Wno-unknown-attributes.
* configure: Regenerate.

Diff:
---
 libbacktrace/btest.c  | 4 ++--
 libbacktrace/configure| 3 ++-
 libbacktrace/configure.ac | 3 ++-
 libbacktrace/edtest.c | 2 +-
 libbacktrace/mtest.c  | 4 ++--
 5 files changed, 9 insertions(+), 7 deletions(-)

diff --git a/libbacktrace/btest.c b/libbacktrace/btest.c
index d9fc372d33d9..c4b2db2cce2f 100644
--- a/libbacktrace/btest.c
+++ b/libbacktrace/btest.c
@@ -49,7 +49,7 @@ POSSIBILITY OF SUCH DAMAGE.  */
 
 /* Test the backtrace function with non-inlined functions.  */
 
-static int test1 (void) __attribute__ ((noinline, noclone, unused));
+static int test1 (void) __attribute__ ((noinline, noclone, optnone, unused));
 static int f2 (int) __attribute__ ((noinline, noclone));
 static int f3 (int, int) __attribute__ ((noinline, noclone));
 
@@ -163,7 +163,7 @@ f13 (int f1line, int f2line)
 
 /* Test the backtrace_simple function with non-inlined functions.  */
 
-static int test3 (void) __attribute__ ((noinline, noclone, unused));
+static int test3 (void) __attribute__ ((noinline, noclone, optnone, unused));
 static int f22 (int) __attribute__ ((noinline, noclone));
 static int f23 (int, int) __attribute__ ((noinline, noclone));
 
diff --git a/libbacktrace/configure b/libbacktrace/configure
index ab94a85f45c1..fe0bb2083eb1 100755
--- a/libbacktrace/configure
+++ b/libbacktrace/configure
@@ -12384,7 +12384,8 @@ WARN_FLAGS=
 save_CFLAGS="$CFLAGS"
 for real_option in -W -Wall -Wwrite-strings -Wstrict-prototypes \
  -Wmissing-prototypes -Wold-style-definition \
- -Wmissing-format-attribute -Wcast-qual; do
+ -Wmissing-format-attribute -Wcast-qual \
+ -Wno-attributes -Wno-unknown-attributes; do
   # Do the check with the no- prefix removed since gcc silently
   # accepts any -Wno-* option on purpose
   case $real_option in
diff --git a/libbacktrace/configure.ac b/libbacktrace/configure.ac
index 59e9c415db8f..bfd7f35d2d2b 100644
--- a/libbacktrace/configure.ac
+++ b/libbacktrace/configure.ac
@@ -144,7 +144,8 @@ AC_SUBST(EXTRA_FLAGS)
 
 ACX_PROG_CC_WARNING_OPTS([-W -Wall -Wwrite-strings -Wstrict-prototypes \
  -Wmissing-prototypes -Wold-style-definition \
- -Wmissing-format-attribute -Wcast-qual],
+ -Wmissing-format-attribute -Wcast-qual \
+ -Wno-attributes -Wno-unknown-attributes],
  [WARN_FLAGS])
 
 AC_ARG_ENABLE([werror],
diff --git a/libbacktrace/edtest.c b/libbacktrace/edtest.c
index d99b8a602950..b644d93788cb 100644
--- a/libbacktrace/edtest.c
+++ b/libbacktrace/edtest.c
@@ -43,7 +43,7 @@ POSSIBILITY OF SUCH DAMAGE.  */
 
 #include "testlib.h"
 
-static int test1 (void) __attribute__ ((noinline, noclone, unused));
+static int test1 (void) __attribute__ ((noinline, noclone, optnone, unused));
 extern int f2 (int);
 extern int f3 (int, int);
 
diff --git a/libbacktrace/mtest.c b/libbacktrace/mtest.c
index 9afe70895148..f793391653dc 100644
--- a/libbacktrace/mtest.c
+++ b/libbacktrace/mtest.c
@@ -47,7 +47,7 @@ POSSIBILITY OF SUCH DAMAGE.  */
 
 #include "testlib.h"
 
-static int test1 (void) __attribute__ ((noinline, noclone, unused));
+static int test1 (void) __attribute__ ((noinline, noclone, optnone, unused));
 static int f2 (int) __attribute__ ((noinline, noclone));
 static int f3 (int, int) __attribute__ ((noinline, noclone));
 
@@ -211,7 +211,7 @@ f3 (int f1line __attribute__ ((unused)), int f2line 
__attribute__ ((unused)))
 
 /* Test the backtrace_simple function with non-inlined functions.  */
 
-static int test3 (void) __attribute__ ((noinline, noclone, unused));
+static int test3 (void) __attribute__ ((noinline, noclone, optnone, unused));
 static int f22 (int) __attribute__ ((noinline, noclone));
 static int f23 (int, int) __attribute__ ((noinline, noclone));

[gcc r15-1984] libbacktrace: correctly gather Mach-O symbol table

[Ian Lance Taylor via Gcc-cvs]

https://gcc.gnu.org/g:b870086904cfd480cf4297525ece00d169482ec7

commit r15-1984-gb870086904cfd480cf4297525ece00d169482ec7
Author: Ian Lance Taylor 
Date:   Thu Jul 11 17:50:18 2024 -0700

libbacktrace: correctly gather Mach-O symbol table

For PR libbacktrace/97082.
* macho.c (MACH_O_N_EXT): Don't define.
(MACH_O_N_UNDF): Define.
(macho_defined_symbol): Don't discard N_EXT symbols.  Do
discard N_UNDF symbols.

Diff:
---
 libbacktrace/macho.c | 14 --
 1 file changed, 8 insertions(+), 6 deletions(-)

diff --git a/libbacktrace/macho.c b/libbacktrace/macho.c
index 5ceff05b29a5..8f768f14a579 100644
--- a/libbacktrace/macho.c
+++ b/libbacktrace/macho.c
@@ -271,12 +271,14 @@ struct macho_nlist_64
 
 /* Value found in nlist n_type field.  */
 
-#define MACH_O_N_EXT   0x01/* Extern symbol */
+#define MACH_O_N_STAB  0xe0/* Stabs debugging symbol */
+#define MACH_O_N_TYPE  0x0e/* Mask for type bits */
+
+/* Values found after masking with MACH_O_N_TYPE.  */
+#define MACH_O_N_UNDF  0x00/* Undefined symbol */
 #define MACH_O_N_ABS   0x02/* Absolute symbol */
-#define MACH_O_N_SECT  0x0e/* Defined in section */
+#define MACH_O_N_SECT  0x0e/* Defined in section from n_sect field */
 
-#define MACH_O_N_TYPE  0x0e/* Mask for type bits */
-#define MACH_O_N_STAB  0xe0/* Stabs debugging symbol */
 
 /* Information we keep for a Mach-O symbol.  */
 
@@ -492,10 +494,10 @@ macho_defined_symbol (uint8_t type)
 {
   if ((type & MACH_O_N_STAB) != 0)
 return 0;
-  if ((type & MACH_O_N_EXT) != 0)
-return 0;
   switch (type & MACH_O_N_TYPE)
 {
+case MACH_O_N_UNDF:
+  return 0;
 case MACH_O_N_ABS:
   return 1;
 case MACH_O_N_SECT:

[gcc r15-1985] libbacktrace: don't fail if symbol size is unknown

[Ian Lance Taylor via Gcc-cvs]

https://gcc.gnu.org/g:d7318f4cf89c2a934fcd1f87d711081285fad242

commit r15-1985-gd7318f4cf89c2a934fcd1f87d711081285fad242
Author: Ian Lance Taylor 
Date:   Thu Jul 11 17:58:17 2024 -0700

libbacktrace: don't fail if symbol size is unknown

* btest.c (test5): Don't fail if symbol size is 0.
* mtest.c (test5): Likewise.

Diff:
---
 libbacktrace/btest.c | 2 +-
 libbacktrace/mtest.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/libbacktrace/btest.c b/libbacktrace/btest.c
index c4b2db2cce2f..3b603f643fa7 100644
--- a/libbacktrace/btest.c
+++ b/libbacktrace/btest.c
@@ -440,7 +440,7 @@ test5 (void)
   (unsigned long) (uintptr_t) &global);
  symdata.failed = 1;
}
-  else if (symdata.size != sizeof (global))
+  else if (symdata.size != sizeof (global) && symdata.size != 0)
{
  fprintf (stderr,
   "test5: unexpected syminfo size got %lx expected %lx\n",
diff --git a/libbacktrace/mtest.c b/libbacktrace/mtest.c
index f793391653dc..5ec43c7bbcea 100644
--- a/libbacktrace/mtest.c
+++ b/libbacktrace/mtest.c
@@ -373,7 +373,7 @@ test5 (void)
   (unsigned long) (uintptr_t) &global);
  symdata.failed = 1;
}
-  else if (symdata.size != sizeof (global))
+  else if (symdata.size != sizeof (global) && symdata.size != 0)
{
  fprintf (stderr,
   "test5: unexpected syminfo size got %lx expected %lx\n",

[gcc r15-1986] LoongArch: TFmode is not allowed to be stored in the float register.

[LuluCheng via Gcc-cvs]

https://gcc.gnu.org/g:abeb6c8a62758faa0719e818e6e8a7db15a6793b

commit r15-1986-gabeb6c8a62758faa0719e818e6e8a7db15a6793b
Author: Lulu Cheng 
Date:   Thu Jul 4 10:37:26 2024 +0800

LoongArch: TFmode is not allowed to be stored in the float register.

PR target/115752

gcc/ChangeLog:

* config/loongarch/loongarch.cc
(loongarch_hard_regno_mode_ok_uncached): Replace
UNITS_PER_FPVALUE with UNITS_PER_HWFPVALUE.
* config/loongarch/loongarch.h (UNITS_PER_FPVALUE): Delete.

gcc/testsuite/ChangeLog:

* gcc.target/loongarch/pr115752.c: New test.

Diff:
---
 gcc/config/loongarch/loongarch.cc | 2 +-
 gcc/config/loongarch/loongarch.h  | 7 ---
 gcc/testsuite/gcc.target/loongarch/pr115752.c | 8 
 3 files changed, 9 insertions(+), 8 deletions(-)

diff --git a/gcc/config/loongarch/loongarch.cc 
b/gcc/config/loongarch/loongarch.cc
index 27f3dbdfb1a0..5d894a36b4d4 100644
--- a/gcc/config/loongarch/loongarch.cc
+++ b/gcc/config/loongarch/loongarch.cc
@@ -6763,7 +6763,7 @@ loongarch_hard_regno_mode_ok_uncached (unsigned int 
regno, machine_mode mode)
   if (mclass == MODE_FLOAT
  || mclass == MODE_COMPLEX_FLOAT
  || mclass == MODE_VECTOR_FLOAT)
-   return size <= UNITS_PER_FPVALUE;
+   return size <= UNITS_PER_HWFPVALUE;
 
   /* Allow integer modes that fit into a single register.  We need
 to put integers into FPRs when using instructions like CVT
diff --git a/gcc/config/loongarch/loongarch.h b/gcc/config/loongarch/loongarch.h
index b9323aba3948..5efeae53be6b 100644
--- a/gcc/config/loongarch/loongarch.h
+++ b/gcc/config/loongarch/loongarch.h
@@ -146,13 +146,6 @@ along with GCC; see the file COPYING3.  If not see
 #define UNITS_PER_HWFPVALUE \
   (TARGET_SOFT_FLOAT ? 0 : UNITS_PER_FP_REG)
 
-/* The largest size of value that can be held in floating-point
-   registers.  */
-#define UNITS_PER_FPVALUE \
-  (TARGET_SOFT_FLOAT ? 0 \
-   : TARGET_SINGLE_FLOAT ? UNITS_PER_FP_REG \
-: LA_LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT)
-
 /* The number of bytes in a double.  */
 #define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT)
 
diff --git a/gcc/testsuite/gcc.target/loongarch/pr115752.c 
b/gcc/testsuite/gcc.target/loongarch/pr115752.c
new file mode 100644
index ..df4bae524f75
--- /dev/null
+++ b/gcc/testsuite/gcc.target/loongarch/pr115752.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+
+long double
+test (long double xx)
+{
+   __asm ("" :: "f"(xx)); /* { dg-error "inconsistent operand constraints in 
an 'asm'" } */
+   return xx + 1;
+}

[gcc r15-1987] LoongArch: Remove unreachable codes.

[LuluCheng via Gcc-cvs]

https://gcc.gnu.org/g:3bc1a86d534db98d2e7647b734a198098f51267f

commit r15-1987-g3bc1a86d534db98d2e7647b734a198098f51267f
Author: Lulu Cheng 
Date:   Thu Jul 4 15:00:40 2024 +0800

LoongArch: Remove unreachable codes.

gcc/ChangeLog:

* config/loongarch/loongarch.cc
(loongarch_split_move): Delete.
(loongarch_hard_regno_mode_ok_uncached): Likewise.
* config/loongarch/loongarch.md
(move_doubleword_fpr): Likewise.
(load_low): Likewise.
(load_high): Likewise.
(store_word): Likewise.
(movgr2frh): Likewise.
(movfrh2gr): Likewise.

Diff:
---
 gcc/config/loongarch/loongarch.cc |  47 +++-
 gcc/config/loongarch/loongarch.md | 109 --
 2 files changed, 8 insertions(+), 148 deletions(-)

diff --git a/gcc/config/loongarch/loongarch.cc 
b/gcc/config/loongarch/loongarch.cc
index 5d894a36b4d4..8eb47ff95c36 100644
--- a/gcc/config/loongarch/loongarch.cc
+++ b/gcc/config/loongarch/loongarch.cc
@@ -4462,42 +4462,13 @@ loongarch_split_move_p (rtx dest, rtx src)
 void
 loongarch_split_move (rtx dest, rtx src)
 {
-  rtx low_dest;
-
   gcc_checking_assert (loongarch_split_move_p (dest, src));
   if (LSX_SUPPORTED_MODE_P (GET_MODE (dest)))
 loongarch_split_128bit_move (dest, src);
   else if (LASX_SUPPORTED_MODE_P (GET_MODE (dest)))
 loongarch_split_256bit_move (dest, src);
-  else if (FP_REG_RTX_P (dest) || FP_REG_RTX_P (src))
-{
-  if (!TARGET_64BIT && GET_MODE (dest) == DImode)
-   emit_insn (gen_move_doubleword_fprdi (dest, src));
-  else if (!TARGET_64BIT && GET_MODE (dest) == DFmode)
-   emit_insn (gen_move_doubleword_fprdf (dest, src));
-  else if (TARGET_64BIT && GET_MODE (dest) == TFmode)
-   emit_insn (gen_move_doubleword_fprtf (dest, src));
-  else
-   gcc_unreachable ();
-}
   else
-{
-  /* The operation can be split into two normal moves.  Decide in
-which order to do them.  */
-  low_dest = loongarch_subword (dest, false);
-  if (REG_P (low_dest) && reg_overlap_mentioned_p (low_dest, src))
-   {
- loongarch_emit_move (loongarch_subword (dest, true),
-  loongarch_subword (src, true));
- loongarch_emit_move (low_dest, loongarch_subword (src, false));
-   }
-  else
-   {
- loongarch_emit_move (low_dest, loongarch_subword (src, false));
- loongarch_emit_move (loongarch_subword (dest, true),
-  loongarch_subword (src, true));
-   }
-}
+gcc_unreachable ();
 }
 
 /* Check if adding an integer constant value for a specific mode can be
@@ -6746,20 +6717,18 @@ loongarch_hard_regno_mode_ok_uncached (unsigned int 
regno, machine_mode mode)
   size = GET_MODE_SIZE (mode);
   mclass = GET_MODE_CLASS (mode);
 
-  if (GP_REG_P (regno) && !LSX_SUPPORTED_MODE_P (mode)
+  if (GP_REG_P (regno)
+  && !LSX_SUPPORTED_MODE_P (mode)
   && !LASX_SUPPORTED_MODE_P (mode))
 return ((regno - GP_REG_FIRST) & 1) == 0 || size <= UNITS_PER_WORD;
 
-  /* For LSX, allow TImode and 128-bit vector modes in all FPR.  */
-  if (FP_REG_P (regno) && LSX_SUPPORTED_MODE_P (mode))
-return true;
-
-  /* FIXED ME: For LASX, allow TImode and 256-bit vector modes in all FPR.  */
-  if (FP_REG_P (regno) && LASX_SUPPORTED_MODE_P (mode))
-return true;
-
   if (FP_REG_P (regno))
 {
+  /* Allow 128-bit or 256-bit vector modes in all FPR.  */
+  if (LSX_SUPPORTED_MODE_P (mode)
+ || LASX_SUPPORTED_MODE_P (mode))
+   return true;
+
   if (mclass == MODE_FLOAT
  || mclass == MODE_COMPLEX_FLOAT
  || mclass == MODE_VECTOR_FLOAT)
diff --git a/gcc/config/loongarch/loongarch.md 
b/gcc/config/loongarch/loongarch.md
index 25c1d323ba0f..21890a2d94ba 100644
--- a/gcc/config/loongarch/loongarch.md
+++ b/gcc/config/loongarch/loongarch.md
@@ -400,9 +400,6 @@
 ;; 64-bit modes for which we provide move patterns.
 (define_mode_iterator MOVE64 [DI DF])
 
-;; 128-bit modes for which we provide move patterns on 64-bit targets.
-(define_mode_iterator MOVE128 [TI TF])
-
 ;; Iterator for sub-32-bit integer modes.
 (define_mode_iterator SHORT [QI HI])
 
@@ -421,12 +418,6 @@
 (define_mode_iterator ANYFI [(SI "TARGET_HARD_FLOAT")
 (DI "TARGET_DOUBLE_FLOAT")])
 
-;; A mode for which moves involving FPRs may need to be split.
-(define_mode_iterator SPLITF
-  [(DF "!TARGET_64BIT && TARGET_DOUBLE_FLOAT")
-   (DI "!TARGET_64BIT && TARGET_DOUBLE_FLOAT")
-   (TF "TARGET_64BIT && TARGET_DOUBLE_FLOAT")])
-
 ;; A mode for anything with 32 bits or more, and able to be loaded with
 ;; the same addressing mode as ld.w.
 (define_mode_iterator LD_AT_LEAST_32_BIT [GPR ANYF])
@@ -2421,41 +2412,6 @@
   [(set_attr "move_type" "move,load,store")
(set_attr "mode" "DF")])
 
-;; Emit a doubleword move in which exactly one of the operands is
-;; a floating-point

[gcc r15-1988] libbacktrace: avoid infinite recursion

[Ian Lance Taylor via Gcc-cvs]

https://gcc.gnu.org/g:bf406a53693ef664b7ee0c77c4940a71a83866c5

commit r15-1988-gbf406a53693ef664b7ee0c77c4940a71a83866c5
Author: Ian Lance Taylor 
Date:   Thu Jul 11 19:29:04 2024 -0700

libbacktrace: avoid infinite recursion

We could get an infinite recursion in an odd case in which a
.gnu_debugdata section was added to a debug file, and mini_debuginfo
was put into the debug file, and the debug file was put into a
/usr/lib/debug directory to be found by build ID.  This combination
doesn't really make sense but we shouldn't get an infinite recursion.

* elf.c (elf_add): Don't use .gnu_debugdata if we are already
reading a debuginfo file.
* Makefile.am (m2test_*): New test targets.
(CHECK_PROGRAMS): Add m2test.
(MAKETESTS): Add m2test_minidebug2.
(%_minidebug2): New pattern.
(CLEANFILES): Remove minidebug2 files.
* Makefile.in: Regenerate.

Diff:
---
 libbacktrace/Makefile.am |  36 -
 libbacktrace/Makefile.in | 137 +--
 libbacktrace/elf.c   |   3 +-
 3 files changed, 134 insertions(+), 42 deletions(-)

diff --git a/libbacktrace/Makefile.am b/libbacktrace/Makefile.am
index bed42c293295..8215cfd9bd5b 100644
--- a/libbacktrace/Makefile.am
+++ b/libbacktrace/Makefile.am
@@ -594,6 +594,39 @@ MAKETESTS += mtest_minidebug
$(OBJCOPY) --add-section .gnu_debugdata=$<.mdbg.xz $<.strip
mv $<.strip $@
 
+if HAVE_ELF
+if HAVE_BUILDID
+if HAVE_OBJCOPY_DEBUGLINK
+
+m2test_SOURCES = $(mtest_SOURCES)
+m2test_CFLAGS = $(libbacktrace_TEST_CFLAGS) -O
+m2test_LDFLAGS = -Wl,--build-id $(libbacktrace_testing_ldflags)
+m2test_LDADD = libbacktrace_elf_for_test.la
+
+check_PROGRAMS += m2test
+MAKETESTS += m2test_minidebug2
+
+# minidebug2 is like minidebug but also adds the gnu_debugdata section
+# to the debug file, and uses a build ID file.  There is no reason to do
+# this but it was causing an infinite recursion.
+%_minidebug2: %
+   $(NM) -D $< -P --defined-only | $(AWK) '{ print $$1 }' | sort > 
$<.dsyms2
+   $(NM) $< -P --defined-only | $(AWK) '{ if ($$2 == "T" || $$2 == "t" || 
$$2 == "D") print $$1 }' | sort > $<.fsyms2
+   $(COMM) -13 $<.dsyms2 $<.fsyms2 > $<.keepsyms2
+   $(OBJCOPY) --only-keep-debug $< $<.dbg2
+   $(OBJCOPY) -S --remove-section .gdb_index --remove-section .comment 
--keep-symbols=$<.keepsyms2 $<.dbg2 $<.mdbg2
+   $(OBJCOPY) --strip-all --remove-section ..comment $< $<.strip2
+   rm -f $<.mdbg2.xz
+   $(XZ) $<.mdbg2
+   $(OBJCOPY) --add-section .gnu_debugdata=$<.mdbg2.xz $<.dbg2
+   $(OBJCOPY) --add-section .gnu_debugdata=$<.mdbg2.xz $<.strip2
+   $(SHELL) ./install-debuginfo-for-buildid.sh $(TEST_BUILD_ID_DIR) $<.dbg2
+   mv $<.strip2 $@
+
+endif HAVE_OBJCOPY_DEBUGLINK
+endif HAVE_BUILDID
+endif HAVE_ELF
+
 endif HAVE_MINIDEBUG
 
 endif NATIVE
@@ -629,7 +662,8 @@ TESTS += $(MAKETESTS) $(BUILDTESTS)
 CLEANFILES = \
$(MAKETESTS) $(BUILDTESTS) *.debug elf_for_test.c edtest2_build.c \
gen_edtest2_build \
-   *.dsyms *.fsyms *.keepsyms *.dbg *.mdbg *.mdbg.xz *.strip
+   *.dsyms *.fsyms *.keepsyms *.dbg *.mdbg *.mdbg.xz *.strip \
+   *.dsyms2 *.fsyms2 *.keepsyms2 *.dbg2 *.mdbg2 *.mdbg2.xz *.strip2
 
 clean-local:
-rm -rf usr
diff --git a/libbacktrace/Makefile.in b/libbacktrace/Makefile.in
index 0260ca81798b..7241e70002dd 100644
--- a/libbacktrace/Makefile.in
+++ b/libbacktrace/Makefile.in
@@ -121,8 +121,8 @@ build_triplet = @build@
 host_triplet = @host@
 target_triplet = @target@
 check_PROGRAMS = $(am__EXEEXT_1) $(am__EXEEXT_2) $(am__EXEEXT_3) \
-   $(am__EXEEXT_16)
-TESTS = $(am__append_4) $(MAKETESTS) $(am__EXEEXT_16)
+   $(am__EXEEXT_4) $(am__EXEEXT_17)
+TESTS = $(am__append_4) $(MAKETESTS) $(am__EXEEXT_17)
 @HAVE_ELF_TRUE@@HAVE_OBJCOPY_DEBUGLINK_TRUE@@NATIVE_TRUE@am__append_1 = 
libbacktrace_elf_for_test.la
 @NATIVE_TRUE@am__append_2 = test_elf_32 test_elf_64 test_macho \
 @NATIVE_TRUE@  test_xcoff_32 test_xcoff_64 test_pecoff \
@@ -163,9 +163,11 @@ TESTS = $(am__append_4) $(MAKETESTS) $(am__EXEEXT_16)
 @NATIVE_TRUE@am__append_28 = mtest
 @NATIVE_TRUE@@USE_DSYMUTIL_TRUE@am__append_29 = mtest.dSYM
 @HAVE_MINIDEBUG_TRUE@@NATIVE_TRUE@am__append_30 = mtest_minidebug
-@HAVE_ELF_TRUE@@HAVE_LIBLZMA_TRUE@am__append_31 = -llzma
-@HAVE_ELF_TRUE@@HAVE_LIBLZMA_TRUE@am__append_32 = -llzma
-@HAVE_ELF_TRUE@am__append_33 = xztest xztest_alloc
+@HAVE_BUILDID_TRUE@@HAVE_ELF_TRUE@@HAVE_MINIDEBUG_TRUE@@HAVE_OBJCOPY_DEBUGLINK_TRUE@@NATIVE_TRUE@am__append_31
 = m2test
+@HAVE_BUILDID_TRUE@@HAVE_ELF_TRUE@@HAVE_MINIDEBUG_TRUE@@HAVE_OBJCOPY_DEBUGLINK_TRUE@@NATIVE_TRUE@am__append_32
 = m2test_minidebug2
+@HAVE_ELF_TRUE@@HAVE_LIBLZMA_TRUE@am__append_33 = -llzma
+@HAVE_ELF_TRUE@@HAVE_LIBLZMA_TRUE@am__append_34 = -llzma
+@HAVE_ELF_TRUE@am__append_35 = xztest xztest_alloc
 subdir = .
 ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
 am__aclocal_m4_deps 

[gcc r15-1989] [committed] Fix m68k bootstrap segfault with late-combine

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:a91c51c187a78e4164bc4039ebdb543848e379d2

commit r15-1989-ga91c51c187a78e4164bc4039ebdb543848e379d2
Author: Jeff Law 
Date:   Thu Jul 11 21:37:34 2024 -0600

[committed] Fix m68k bootstrap segfault with late-combine

So the m68k port has failed to bootstrap since the introduction of
late-combine.  My suspicion has been this is a backend problem.  Sure enough
after bisecting things down (thank goodness for the debug counter!) I'm 
happy
to report m68k (after this patch) has moved into its stage3 build for the 
first
time in a month.

Basically late-combine propagated an address calculation to its use points,
generating this insn (dwarf2out.c, I forget what function):

> (insn 653 652 655 (parallel [
> (set (mem/j:DI (plus:SI (plus:SI (reg/f:SI 9 %a1 [orig:64 _67 
] [64])
> (reg:SI 0 %d0 [321]))
> (const_int 20 [0x14])) [0 
slot_204->dw_attr_val.v.val_unsigned+0 S8 A16])
> (sign_extend:DI (mem/c:SI (plus:SI (reg/f:SI 14 %a6)
> (const_int -28 [0xffe4])) [870 
%sfp+-28 S4 A16])))
> (clobber (reg:SI 0 %d0))
> ]) "../../../gcc/gcc/dwarf2out.cc":24961:23 93 {extendsidi2}
>  (expr_list:REG_DEAD (reg/f:SI 9 %a1 [orig:64 _67 ] [64])
> (expr_list:REG_DEAD (reg:SI 0 %d0 [321])
> (expr_list:REG_UNUSED (reg:SI 0 %d0)
> (nil)
Note how the output uses d0 in the address calculation and the clobber uses 
d0.

It matches this insn in the md file:

> (define_insn "extendsidi2"
>   [(set (match_operand:DI 0 "nonimmediate_operand" "=d,o,o,<")
> (sign_extend:DI
>  (match_operand:SI 1 "nonimmediate_src_operand" "rm,rm,r,rm")))
>(clobber (match_scratch:SI 2 "=X,&d,&d,&d"))]
>   ""
> {
>   if (which_alternative == 0)
> /* Handle alternative 0.  */
> {
>   if (TARGET_68020 || TARGET_COLDFIRE)
> return "move%.l %1,%R0\;smi %0\;extb%.l %0";
>   else
> return "move%.l %1,%R0\;smi %0\;ext%.w %0\;ext%.l %0";
> }
>
>   /* Handle alternatives 1, 2 and 3.  We don't need to adjust address by 4
>  in alternative 3 because autodecrement will do that for us.  */
>   operands[3] = adjust_address (operands[0], SImode,
> which_alternative == 3 ? 0 : 4);
>   operands[0] = adjust_address (operands[0], SImode, 0);
>
>   if (TARGET_68020 || TARGET_COLDFIRE)
> return "move%.l %1,%3\;smi %2\;extb%.l %2\;move%.l %2,%0";
>   else
> return "move%.l %1,%3\;smi %2\;ext%.w %2\;ext%.l %2\;move%.l %2,%0";
> }
>   [(set_attr "ok_for_coldfire" "yes,no,yes,yes")])
Note the smi/ext instruction pair in the case for alternatives 1..3.  Those
clobber the scratch register before we're done consuming inputs.  The 
scratch
register really needs to be marked as an earlyclobber.

That fixes the bootstrap problem, but a cursory review of m68k.md is not
encouraging.  I will not be surprised at all if there's more of this kind of
problem lurking.

But happy to at least have m68k bootstrapping again.   It's failing the
comparison test, but definitely progress.

* config/m68k/m68k.md (extendsidi2): Add missing early clobbers.

Diff:
---
 gcc/config/m68k/m68k.md | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/config/m68k/m68k.md b/gcc/config/m68k/m68k.md
index 037978db40c0..e5c252888448 100644
--- a/gcc/config/m68k/m68k.md
+++ b/gcc/config/m68k/m68k.md
@@ -1887,7 +1887,7 @@
   [(set (match_operand:DI 0 "nonimmediate_operand" "=d,o,o,<")
(sign_extend:DI
 (match_operand:SI 1 "nonimmediate_src_operand" "rm,rm,r,rm")))
-   (clobber (match_scratch:SI 2 "=X,d,d,d"))]
+   (clobber (match_scratch:SI 2 "=X,&d,&d,&d"))]
   ""
 {
   if (which_alternative == 0)

[gcc r15-1990] tree-optimization/115867 - ICE with simdcall vectorization in masked loop

[Richard Biener via Gcc-cvs]

https://gcc.gnu.org/g:4f4478f0f31263997bfdc4159f90e58dd79b38f9

commit r15-1990-g4f4478f0f31263997bfdc4159f90e58dd79b38f9
Author: Richard Biener 
Date:   Thu Jul 11 10:18:55 2024 +0200

tree-optimization/115867 - ICE with simdcall vectorization in masked loop

When only a loop mask is to be supplied for the inbranch arg to a
simd function we fail to handle integer mode masks correctly.  We
need to guess the number of elements represented by it.  This assumes
that excess arguments are all for masks, I wasn't able to create
a simdclone with more than one integer mode mask argument.

The gcc.dg/vect/vect-simd-clone-20.c exercises this with -mavx512vl

PR tree-optimization/115867
* tree-vect-stmts.cc (vectorizable_simd_clone_call): Properly
guess the number of mask elements for integer mode masks.

Diff:
---
 gcc/tree-vect-stmts.cc | 7 ++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/gcc/tree-vect-stmts.cc b/gcc/tree-vect-stmts.cc
index fdcda0d2abae..2e4d500d1f26 100644
--- a/gcc/tree-vect-stmts.cc
+++ b/gcc/tree-vect-stmts.cc
@@ -4748,7 +4748,12 @@ vectorizable_simd_clone_call (vec_info *vinfo, 
stmt_vec_info stmt_info,
  SIMD_CLONE_ARG_TYPE_MASK);
 
  tree masktype = bestn->simdclone->args[mask_i].vector_type;
- callee_nelements = TYPE_VECTOR_SUBPARTS (masktype);
+ if (SCALAR_INT_MODE_P (bestn->simdclone->mask_mode))
+   /* Guess the number of lanes represented by masktype.  */
+   callee_nelements = exact_div (bestn->simdclone->simdlen,
+ bestn->simdclone->nargs - nargs);
+ else
+   callee_nelements = TYPE_VECTOR_SUBPARTS (masktype);
  o = vector_unroll_factor (nunits, callee_nelements);
  for (m = j * o; m < (j + 1) * o; m++)
{

[gcc r15-1991] rs6000: Remove vcond{,u} expanders

[Kewen Lin via Gcc-cvs]

https://gcc.gnu.org/g:f7e4000397842671fe7e5c0473f1fa62707e1db9

commit r15-1991-gf7e4000397842671fe7e5c0473f1fa62707e1db9
Author: Kewen Lin 
Date:   Fri Jul 12 01:32:57 2024 -0500

rs6000: Remove vcond{,u} expanders

As PR114189 shows, middle-end will obsolete vcond, vcondu
and vcondeq optabs soon.  This patch is to remove all
vcond{,u} expanders in rs6000 port and adjust the function
rs6000_emit_vector_cond_expr which is called by those
expanders as static.

PR target/115659

gcc/ChangeLog:

* config/rs6000/rs6000-protos.h (rs6000_emit_vector_cond_expr): 
Remove.
* config/rs6000/rs6000.cc (rs6000_emit_vector_cond_expr): Add static
qualifier as it is only called by rs6000_emit_swsqrt now.
* config/rs6000/vector.md (vcond): Remove.
(vcond): Remove.
(vcondv4sfv4si): Likewise.
(vcondv4siv4sf): Likewise.
(vcondv2dfv2di): Likewise.
(vcondv2div2df): Likewise.
(vcondu): Likewise.
(vconduv4sfv4si): Likewise.
(vconduv2dfv2di): Likewise.

Diff:
---
 gcc/config/rs6000/rs6000-protos.h |   1 -
 gcc/config/rs6000/rs6000.cc   |   2 +-
 gcc/config/rs6000/vector.md   | 160 --
 3 files changed, 1 insertion(+), 162 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-protos.h 
b/gcc/config/rs6000/rs6000-protos.h
index 09a57a806faf..b40557a85577 100644
--- a/gcc/config/rs6000/rs6000-protos.h
+++ b/gcc/config/rs6000/rs6000-protos.h
@@ -126,7 +126,6 @@ extern void rs6000_emit_dot_insn (rtx dst, rtx src, int 
dot, rtx ccreg);
 extern bool rs6000_emit_set_const (rtx, rtx);
 extern bool rs6000_emit_cmove (rtx, rtx, rtx, rtx);
 extern bool rs6000_emit_int_cmove (rtx, rtx, rtx, rtx);
-extern int rs6000_emit_vector_cond_expr (rtx, rtx, rtx, rtx, rtx, rtx);
 extern void rs6000_emit_minmax (rtx, enum rtx_code, rtx, rtx);
 extern void rs6000_expand_atomic_compare_and_swap (rtx op[]);
 extern rtx swap_endian_selector_for_mode (machine_mode mode);
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 2cbea6ea2d7c..195f2af9062e 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -16149,7 +16149,7 @@ rs6000_emit_vector_compare (enum rtx_code rcode,
OP_FALSE are two VEC_COND_EXPR operands.  CC_OP0 and CC_OP1 are the two
operands for the relation operation COND.  */
 
-int
+static int
 rs6000_emit_vector_cond_expr (rtx dest, rtx op_true, rtx op_false,
  rtx cond, rtx cc_op0, rtx cc_op1)
 {
diff --git a/gcc/config/rs6000/vector.md b/gcc/config/rs6000/vector.md
index 59489e068399..0d3e0a24e118 100644
--- a/gcc/config/rs6000/vector.md
+++ b/gcc/config/rs6000/vector.md
@@ -331,166 +331,6 @@
 })
 
 
-;; Vector comparisons
-(define_expand "vcond"
-  [(set (match_operand:VEC_F 0 "vfloat_operand")
-   (if_then_else:VEC_F
-(match_operator 3 "comparison_operator"
-[(match_operand:VEC_F 4 "vfloat_operand")
- (match_operand:VEC_F 5 "vfloat_operand")])
-(match_operand:VEC_F 1 "vfloat_operand")
-(match_operand:VEC_F 2 "vfloat_operand")))]
-  "VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)"
-{
-  if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
-   operands[3], operands[4], operands[5]))
-DONE;
-  else
-gcc_unreachable ();
-})
-
-(define_expand "vcond"
-  [(set (match_operand:VEC_I 0 "vint_operand")
-   (if_then_else:VEC_I
-(match_operator 3 "comparison_operator"
-[(match_operand:VEC_I 4 "vint_operand")
- (match_operand:VEC_I 5 "vint_operand")])
-(match_operand:VEC_I 1 "vector_int_reg_or_same_bit")
-(match_operand:VEC_I 2 "vector_int_reg_or_same_bit")))]
-  "VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)"
-{
-  if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
-   operands[3], operands[4], operands[5]))
-DONE;
-  else
-gcc_unreachable ();
-})
-
-(define_expand "vcondv4sfv4si"
-  [(set (match_operand:V4SF 0 "vfloat_operand")
-   (if_then_else:V4SF
-(match_operator 3 "comparison_operator"
-[(match_operand:V4SI 4 "vint_operand")
- (match_operand:V4SI 5 "vint_operand")])
-(match_operand:V4SF 1 "vfloat_operand")
-(match_operand:V4SF 2 "vfloat_operand")))]
-  "VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)
-   && VECTOR_UNIT_ALTIVEC_P (V4SImode)"
-{
-  if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
-   operands[3], operands[4], operands[5]))
-DONE;
-  else
-gcc_unreachable ();
-})
-
-(define_expand "vcondv4siv4sf"
-  [(set (match_operand:V4SI 0 "vint_operand")
-   (if_then_else:V4SI
-(match_operator 3 "comparison_operator"
-

[gcc r14-10410] Fortran: Fix ICEs due to comp calls in initialization exprs [PR103312]

[Paul Thomas via Gcc-cvs]

https://gcc.gnu.org/g:29b2e1cdb6f182d3f519a4b96cdc98032a10f81d

commit r14-10410-g29b2e1cdb6f182d3f519a4b96cdc98032a10f81d
Author: Paul Thomas 
Date:   Thu May 23 07:59:46 2024 +0100

Fortran: Fix ICEs due to comp calls in initialization exprs [PR103312]

2024-05-23  Paul Thomas  

gcc/fortran
PR fortran/103312
* dependency.cc (gfc_dep_compare_expr): Handle component call
expressions. Return -2 as default and return 0 if compared with
a function expression that is from an interface body and has
the same name.
* expr.cc (gfc_reduce_init_expr): If the expression is a comp
call do not attempt to reduce, defer to resolution and return
false.
* trans-types.cc (gfc_get_dtype_rank_type,
gfc_get_nodesc_array_type): Fix whitespace.

gcc/testsuite/
PR fortran/103312
* gfortran.dg/pr103312.f90: New test.

(cherry picked from commit 2ce90517ed75c4af9fc0616f2670cf6dfcfa8a91)

Diff:
---
 gcc/fortran/dependency.cc  | 32 +
 gcc/fortran/expr.cc|  5 ++
 gcc/fortran/trans-types.cc |  4 +-
 gcc/testsuite/gfortran.dg/pr103312.f90 | 87 ++
 4 files changed, 126 insertions(+), 2 deletions(-)

diff --git a/gcc/fortran/dependency.cc b/gcc/fortran/dependency.cc
index fb4d94de6413..bafe8cbc5bc3 100644
--- a/gcc/fortran/dependency.cc
+++ b/gcc/fortran/dependency.cc
@@ -440,6 +440,38 @@ gfc_dep_compare_expr (gfc_expr *e1, gfc_expr *e2)
return mpz_sgn (e2->value.op.op2->value.integer);
 }
 
+
+  if (e1->expr_type == EXPR_COMPCALL)
+{
+  /* This will have emerged from interface.cc(gfc_check_typebound_override)
+via gfc_check_result_characteristics. It is possible that other
+variants exist that are 'equal' but play it safe for now by setting
+the relationship as 'indeterminate'.  */
+  if (e2->expr_type == EXPR_FUNCTION && e2->ref)
+   {
+ gfc_ref *ref = e2->ref;
+ gfc_symbol *s = NULL;
+
+ if (e1->value.compcall.tbp->u.specific)
+   s = e1->value.compcall.tbp->u.specific->n.sym;
+
+ /* Check if the proc ptr points to an interface declaration and the
+names are the same; ie. the overriden proc. of an abstract type.
+The checking of the arguments will already have been done.  */
+ for (; ref && s; ref = ref->next)
+   if (!ref->next && ref->type == REF_COMPONENT
+   && ref->u.c.component->attr.proc_pointer
+   && ref->u.c.component->ts.interface
+   && ref->u.c.component->ts.interface->attr.if_source
+   == IFSRC_IFBODY
+   && !strcmp (s->name, ref->u.c.component->name))
+ return 0;
+   }
+
+  /* Assume as default that TKR checking is sufficient.  */
+ return -2;
+  }
+
   if (e1->expr_type != e2->expr_type)
 return -3;
 
diff --git a/gcc/fortran/expr.cc b/gcc/fortran/expr.cc
index 50e32a7a3b75..9ce0b950b617 100644
--- a/gcc/fortran/expr.cc
+++ b/gcc/fortran/expr.cc
@@ -3201,6 +3201,11 @@ gfc_reduce_init_expr (gfc_expr *expr)
 {
   bool t;
 
+  /* It is far too early to resolve a class compcall. Punt to resolution.  */
+  if (expr && expr->expr_type == EXPR_COMPCALL
+  && expr->symtree->n.sym->ts.type == BT_CLASS)
+return false;
+
   gfc_init_expr_flag = true;
   t = gfc_resolve_expr (expr);
   if (t)
diff --git a/gcc/fortran/trans-types.cc b/gcc/fortran/trans-types.cc
index 676014e9b984..8466c595e065 100644
--- a/gcc/fortran/trans-types.cc
+++ b/gcc/fortran/trans-types.cc
@@ -1591,7 +1591,7 @@ gfc_get_dtype_rank_type (int rank, tree etype)
   size = size_in_bytes (etype);
   break;
 }
-  
+
   gcc_assert (size);
 
   STRIP_NOPS (size);
@@ -1740,7 +1740,7 @@ gfc_get_nodesc_array_type (tree etype, gfc_array_spec * 
as, gfc_packed packed,
tmp = gfc_conv_mpz_to_tree (expr->value.integer,
gfc_index_integer_kind);
   else
-   tmp = NULL_TREE;
+   tmp = NULL_TREE;
   GFC_TYPE_ARRAY_LBOUND (type, n) = tmp;
 
   expr = as->upper[n];
diff --git a/gcc/testsuite/gfortran.dg/pr103312.f90 
b/gcc/testsuite/gfortran.dg/pr103312.f90
new file mode 100644
index ..deacc70bf5df
--- /dev/null
+++ b/gcc/testsuite/gfortran.dg/pr103312.f90
@@ -0,0 +1,87 @@
+! { dg-do run }
+!
+! Test the fix for pr103312, in which the use of a component call in
+! initialization expressions, eg. character(this%size()), caused ICEs.
+!
+! Contributed by Arseny Solokha  
+!
+module example
+
+  type, abstract :: foo
+integer :: i
+  contains
+procedure(foo_size), deferred :: size
+procedure(foo_func), deferred :: func
+  end type
+
+  interface
+function foo_func (this) result (string)
+  import :: foo
+  class(foo) :: this
+  character(

[gcc r13-8907] Fortran: Fix ICEs due to comp calls in initialization exprs [PR103312]

[Paul Thomas via Gcc-cvs]

https://gcc.gnu.org/g:1b22831d3c74a1b3e72dab840e2818e495ecd567

commit r13-8907-g1b22831d3c74a1b3e72dab840e2818e495ecd567
Author: Paul Thomas 
Date:   Thu May 23 07:59:46 2024 +0100

Fortran: Fix ICEs due to comp calls in initialization exprs [PR103312]

2024-05-23  Paul Thomas  

gcc/fortran
PR fortran/103312
* dependency.cc (gfc_dep_compare_expr): Handle component call
expressions. Return -2 as default and return 0 if compared with
a function expression that is from an interface body and has
the same name.
* expr.cc (gfc_reduce_init_expr): If the expression is a comp
call do not attempt to reduce, defer to resolution and return
false.
* trans-types.cc (gfc_get_dtype_rank_type,
gfc_get_nodesc_array_type): Fix whitespace.

gcc/testsuite/
PR fortran/103312
* gfortran.dg/pr103312.f90: New test.

(cherry picked from commit 2ce90517ed75c4af9fc0616f2670cf6dfcfa8a91)

Diff:
---
 gcc/fortran/dependency.cc  | 32 +
 gcc/fortran/expr.cc|  5 ++
 gcc/fortran/trans-types.cc |  4 +-
 gcc/testsuite/gfortran.dg/pr103312.f90 | 87 ++
 4 files changed, 126 insertions(+), 2 deletions(-)

diff --git a/gcc/fortran/dependency.cc b/gcc/fortran/dependency.cc
index 9117825ee6e8..f928099e9e2f 100644
--- a/gcc/fortran/dependency.cc
+++ b/gcc/fortran/dependency.cc
@@ -440,6 +440,38 @@ gfc_dep_compare_expr (gfc_expr *e1, gfc_expr *e2)
return mpz_sgn (e2->value.op.op2->value.integer);
 }
 
+
+  if (e1->expr_type == EXPR_COMPCALL)
+{
+  /* This will have emerged from interface.cc(gfc_check_typebound_override)
+via gfc_check_result_characteristics. It is possible that other
+variants exist that are 'equal' but play it safe for now by setting
+the relationship as 'indeterminate'.  */
+  if (e2->expr_type == EXPR_FUNCTION && e2->ref)
+   {
+ gfc_ref *ref = e2->ref;
+ gfc_symbol *s = NULL;
+
+ if (e1->value.compcall.tbp->u.specific)
+   s = e1->value.compcall.tbp->u.specific->n.sym;
+
+ /* Check if the proc ptr points to an interface declaration and the
+names are the same; ie. the overriden proc. of an abstract type.
+The checking of the arguments will already have been done.  */
+ for (; ref && s; ref = ref->next)
+   if (!ref->next && ref->type == REF_COMPONENT
+   && ref->u.c.component->attr.proc_pointer
+   && ref->u.c.component->ts.interface
+   && ref->u.c.component->ts.interface->attr.if_source
+   == IFSRC_IFBODY
+   && !strcmp (s->name, ref->u.c.component->name))
+ return 0;
+   }
+
+  /* Assume as default that TKR checking is sufficient.  */
+ return -2;
+  }
+
   if (e1->expr_type != e2->expr_type)
 return -3;
 
diff --git a/gcc/fortran/expr.cc b/gcc/fortran/expr.cc
index 4a9b29c7e9d5..90d2daa08642 100644
--- a/gcc/fortran/expr.cc
+++ b/gcc/fortran/expr.cc
@@ -3188,6 +3188,11 @@ gfc_reduce_init_expr (gfc_expr *expr)
 {
   bool t;
 
+  /* It is far too early to resolve a class compcall. Punt to resolution.  */
+  if (expr && expr->expr_type == EXPR_COMPCALL
+  && expr->symtree->n.sym->ts.type == BT_CLASS)
+return false;
+
   gfc_init_expr_flag = true;
   t = gfc_resolve_expr (expr);
   if (t)
diff --git a/gcc/fortran/trans-types.cc b/gcc/fortran/trans-types.cc
index b2a3000da1fe..0c59ab3f5b57 100644
--- a/gcc/fortran/trans-types.cc
+++ b/gcc/fortran/trans-types.cc
@@ -1591,7 +1591,7 @@ gfc_get_dtype_rank_type (int rank, tree etype)
   size = size_in_bytes (etype);
   break;
 }
-  
+
   gcc_assert (size);
 
   STRIP_NOPS (size);
@@ -1736,7 +1736,7 @@ gfc_get_nodesc_array_type (tree etype, gfc_array_spec * 
as, gfc_packed packed,
tmp = gfc_conv_mpz_to_tree (expr->value.integer,
gfc_index_integer_kind);
   else
-   tmp = NULL_TREE;
+   tmp = NULL_TREE;
   GFC_TYPE_ARRAY_LBOUND (type, n) = tmp;
 
   expr = as->upper[n];
diff --git a/gcc/testsuite/gfortran.dg/pr103312.f90 
b/gcc/testsuite/gfortran.dg/pr103312.f90
new file mode 100644
index ..deacc70bf5df
--- /dev/null
+++ b/gcc/testsuite/gfortran.dg/pr103312.f90
@@ -0,0 +1,87 @@
+! { dg-do run }
+!
+! Test the fix for pr103312, in which the use of a component call in
+! initialization expressions, eg. character(this%size()), caused ICEs.
+!
+! Contributed by Arseny Solokha  
+!
+module example
+
+  type, abstract :: foo
+integer :: i
+  contains
+procedure(foo_size), deferred :: size
+procedure(foo_func), deferred :: func
+  end type
+
+  interface
+function foo_func (this) result (string)
+  import :: foo
+  class(foo) :: this
+  character(t