[gcc r15-1838] Aarch64: Add test for non-commutative SIMD intrinsic
https://gcc.gnu.org/g:14c6793885c11c892ac90d5046979ab20de1b0b1
commit r15-1838-g14c6793885c11c892ac90d5046979ab20de1b0b1
Author: Alfie Richards
Date: Thu Jul 4 09:07:57 2024 +0200
Aarch64: Add test for non-commutative SIMD intrinsic
This adds a test for non-commutative SIMD NEON intrinsics.
Specifically addp is non-commutative and has a bug in the current
big-endian implementation.
gcc/testsuite/ChangeLog:
* gcc.target/aarch64/vector_intrinsics_asm.c: New test.
Diff:
---
.../gcc.target/aarch64/vector_intrinsics_asm.c | 371 +
1 file changed, 371 insertions(+)
diff --git a/gcc/testsuite/gcc.target/aarch64/vector_intrinsics_asm.c
b/gcc/testsuite/gcc.target/aarch64/vector_intrinsics_asm.c
new file mode 100644
index 000..b7d5620abab
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/vector_intrinsics_asm.c
@@ -0,0 +1,371 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" "" { xfail be } } } */
+
+#include "arm_neon.h"
+
+// SIGNED VADD INTRINSICS
+
+/*
+**test_vadd_s8:
+** addpv0\.8b, v0\.8b, v1\.8b
+** ret
+*/
+int8x8_t test_vadd_s8(int8x8_t v1, int8x8_t v2) {
+ int8x8_t v3 = vpadd_s8(v1, v2);
+ return v3;
+}
+
+/*
+**test_vadd_s16:
+**addp v0\.4h, v0\.4h, v1\.4h
+**ret
+*/
+int16x4_t test_vadd_s16(int16x4_t v1, int16x4_t v2) {
+ int16x4_t v3 = vpadd_s16(v1, v2);
+ return v3;
+}
+
+/*
+**test_vadd_s32:
+** addpv0\.2s, v0\.2s, v1\.2s
+** ret
+*/
+int32x2_t test_vadd_s32(int32x2_t v1, int32x2_t v2) {
+ int32x2_t v3 = vpadd_s32(v1, v2);
+ return v3;
+}
+
+/*
+**test_vaddq_s8:
+**...
+** addpv0\.16b, v0\.16b, v1\.16b
+** ret
+*/
+int8x16_t test_vaddq_s8(int8x16_t v1, int8x16_t v2) {
+ int8x16_t v3 = vpaddq_s8(v1, v2);
+ return v3;
+}
+
+/*
+**test_vaddq_s16:
+**...
+** addpv0\.8h, v0\.8h, v1\.8h
+** ret
+*/
+int16x8_t test_vaddq_s16(int16x8_t v1, int16x8_t v2) {
+ int16x8_t v3 = vpaddq_s16(v1, v2);
+ return v3;
+}
+
+/*
+**test_vaddq_s32:
+**...
+** addpv0\.4s, v0\.4s, v1\.4s
+** ret
+*/
+int32x4_t test_vaddq_s32(int32x4_t v1, int32x4_t v2) {
+ int32x4_t v3 = vpaddq_s32(v1, v2);
+ return v3;
+}
+
+/*
+**test_vaddq_s64:
+**...
+** addpv0\.2d, v0\.2d, v1\.2d
+** ret
+*/
+int64x2_t test_vaddq_s64(int64x2_t v1, int64x2_t v2) {
+ int64x2_t v3 = vpaddq_s64(v1, v2);
+ return v3;
+}
+
+/*
+**test_vaddd_s64:
+**...
+** addp(d[0-9]+), v0\.2d
+** fmovx0, \1
+** ret
+*/
+int64_t test_vaddd_s64(int64x2_t v1) {
+ int64_t v2 = vpaddd_s64(v1);
+ return v2;
+}
+
+/*
+**test_vaddl_s8:
+**...
+** saddlp v0\.4h, v0\.8b
+** ret
+*/
+int16x4_t test_vaddl_s8(int8x8_t v1) {
+ int16x4_t v2 = vpaddl_s8(v1);
+ return v2;
+}
+
+/*
+**test_vaddlq_s8:
+**...
+** saddlp v0\.8h, v0\.16b
+** ret
+*/
+int16x8_t test_vaddlq_s8(int8x16_t v1) {
+ int16x8_t v2 = vpaddlq_s8(v1);
+ return v2;
+}
+/*
+**test_vaddl_s16:
+**...
+** saddlp v0\.2s, v0\.4h
+** ret
+*/
+int32x2_t test_vaddl_s16(int16x4_t v1) {
+ int32x2_t v2 = vpaddl_s16(v1);
+ return v2;
+}
+
+/*
+**test_vaddlq_s16:
+**...
+** saddlp v0\.4s, v0\.8h
+** ret
+*/
+int32x4_t test_vaddlq_s16(int16x8_t v1) {
+ int32x4_t v2 = vpaddlq_s16(v1);
+ return v2;
+}
+
+/*
+**test_vaddl_s32:
+**...
+** saddlp v0\.1d, v0\.2s
+** ret
+*/
+int64x1_t test_vaddl_s32(int32x2_t v1) {
+ int64x1_t v2 = vpaddl_s32(v1);
+ return v2;
+}
+
+/*
+**test_vaddlq_s32:
+**...
+** saddlp v0\.2d, v0\.4s
+** ret
+*/
+int64x2_t test_vaddlq_s32(int32x4_t v1) {
+ int64x2_t v2 = vpaddlq_s32(v1);
+ return v2;
+}
+
+// UNSIGNED VADD INTRINSICS
+
+/*
+**test_vadd_u8:
+**...
+** addpv0\.8b, v0\.8b, v1\.8b
+** ret
+*/
+uint8x8_t test_vadd_u8(uint8x8_t v1, uint8x8_t v2) {
+ uint8x8_t v3 = vpadd_u8(v1, v2);
+ return v3;
+}
+
+/*
+**test_vadd_u16:
+**...
+** addpv0\.4h, v0\.4h, v1\.4h
+** ret
+*/
+uint16x4_t test_vadd_u16(uint16x4_t v1, uint16x4_t v2) {
+ uint16x4_t v3 = vpadd_u16(v1, v2);
+ return v3;
+}
+
+/*
+**test_vadd_u32:
+**...
+** addpv0\.2s, v0\.2s, v1\.2s
+** ret
+*/
+uint32x2_t test_vadd_u32(uint32x2_t v1, uint32x2_t v2) {
+ uint32x2_t v3 = vpadd_u32(v1, v2);
+ return v3;
+}
+
+/*
+**test_vaddq_u8:
+**...
+** addpv0\.16b, v0\.16b, v1\.16b
+** ret
+*/
+uint8x16_t test_vaddq_u8(uint8x16_t v1, uint8x16_t v2) {
+ uint8x16_t v3 = vpaddq_u8(v1, v2);
+ return v3;
+}
+
+/*
+**test_vaddq_u16:
+**...
+** addpv0\.8h, v0\.8h, v1\.8h
+** ret
+*/
+uint16x8_t test_vaddq_u16(uint16x8_t v1, uint16x8_t v2) {
+ uint16x8_t v3 = vpaddq_u16(v1, v2);
+ return v3;
+}
+
+/*
+**test_vaddq_u32:
+**...
+** addpv0\.4s, v0\.4s, v1\.4s
+** ret
+*/
+uint32x4_t test_vaddq_u32(uint32x4_t v1, uint32x4_t v2) {
+ uint32x4_t v3 = vpaddq_u32(v1, v2);
+ return v3;
+}
+
+/*
+**test_vaddq_u64:
+**...
+** addpv0\.2d, v0\.2d, v1\.2d
+** ret
+*/
+uint64x2_t test_vaddq_u64(uint64x2_t v1, uint64x2_t v2) {
+ uint6
[gcc r15-1839] Aarch64, bugfix: Fix NEON bigendian addp intrinsic [PR114890]
https://gcc.gnu.org/g:11049cdf204bc96bc407e5dd44ed3b8a492f405a
commit r15-1839-g11049cdf204bc96bc407e5dd44ed3b8a492f405a
Author: Alfie Richards
Date: Thu Jul 4 09:09:19 2024 +0200
Aarch64, bugfix: Fix NEON bigendian addp intrinsic [PR114890]
This change removes code that switches the operands in bigendian mode
erroneously.
This fixes the related test also.
gcc/ChangeLog:
PR target/114890
* config/aarch64/aarch64-simd.md: Remove bigendian operand swap.
gcc/testsuite/ChangeLog:
PR target/114890
* gcc.target/aarch64/vector_intrinsics_asm.c: Remove xfail.
Diff:
---
gcc/config/aarch64/aarch64-simd.md | 2 --
gcc/testsuite/gcc.target/aarch64/vector_intrinsics_asm.c | 2 +-
2 files changed, 1 insertion(+), 3 deletions(-)
diff --git a/gcc/config/aarch64/aarch64-simd.md
b/gcc/config/aarch64/aarch64-simd.md
index fd0c5e612b5..fd10039f9a2 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -7379,8 +7379,6 @@
nunits /= 2;
rtx par_even = aarch64_gen_stepped_int_parallel (nunits, 0, 2);
rtx par_odd = aarch64_gen_stepped_int_parallel (nunits, 1, 2);
-if (BYTES_BIG_ENDIAN)
- std::swap (operands[1], operands[2]);
emit_insn (gen_aarch64_addp_insn (operands[0], operands[1],
operands[2], par_even, par_odd));
DONE;
diff --git a/gcc/testsuite/gcc.target/aarch64/vector_intrinsics_asm.c
b/gcc/testsuite/gcc.target/aarch64/vector_intrinsics_asm.c
index b7d5620abab..e3dcd0830c8 100644
--- a/gcc/testsuite/gcc.target/aarch64/vector_intrinsics_asm.c
+++ b/gcc/testsuite/gcc.target/aarch64/vector_intrinsics_asm.c
@@ -1,6 +1,6 @@
/* { dg-do compile } */
/* { dg-options "-O2" } */
-/* { dg-final { check-function-bodies "**" "" "" { xfail be } } } */
+/* { dg-final { check-function-bodies "**" "" "" } } */
#include "arm_neon.h"
[gcc r15-1840] arm: Use LDMIA/STMIA for thumb1 DI/DF loads/stores
https://gcc.gnu.org/g:236d6fef2479654b3011f8208e1bd7f078700109
commit r15-1840-g236d6fef2479654b3011f8208e1bd7f078700109
Author: Siarhei Volkau
Date: Thu Jun 20 10:24:31 2024 +0300
arm: Use LDMIA/STMIA for thumb1 DI/DF loads/stores
If the address register is dead after load/store operation it looks
beneficial to use LDMIA/STMIA instead of pair of LDR/STR instructions,
at least if optimizing for size.
gcc/ChangeLog:
* config/arm/arm.cc (thumb_load_double_from_address): Emit ldmia
when address reg rewritten by load.
* config/arm/thumb1.md (peephole2 to rewrite DI/DF load): New.
(peephole2 to rewrite DI/DF store): New.
* config/arm/iterators.md (DIDF): New.
gcc/testsuite:
* gcc.target/arm/thumb1-load-store-64bit.c: Add new test.
Signed-off-by: Siarhei Volkau
Diff:
---
gcc/config/arm/arm.cc | 10 ++
gcc/config/arm/iterators.md| 3 ++
gcc/config/arm/thumb1.md | 37 +-
.../gcc.target/arm/thumb1-load-store-64bit.c | 16 ++
4 files changed, 58 insertions(+), 8 deletions(-)
diff --git a/gcc/config/arm/arm.cc b/gcc/config/arm/arm.cc
index 6dab65f493b..bb9c7c3b5c4 100644
--- a/gcc/config/arm/arm.cc
+++ b/gcc/config/arm/arm.cc
@@ -28374,15 +28374,11 @@ thumb_load_double_from_address (rtx *operands)
switch (GET_CODE (addr))
{
case REG:
- operands[2] = adjust_address (operands[1], SImode, 4);
-
- if (REGNO (operands[0]) == REGNO (addr))
- {
- output_asm_insn ("ldr\t%H0, %2", operands);
- output_asm_insn ("ldr\t%0, %1", operands);
- }
+ if (reg_overlap_mentioned_p (addr, operands[0]))
+ output_asm_insn ("ldmia\t%m1, {%0, %H0}", operands);
else
{
+ operands[2] = adjust_address (operands[1], SImode, 4);
output_asm_insn ("ldr\t%0, %1", operands);
output_asm_insn ("ldr\t%H0, %2", operands);
}
diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md
index 987602da1bf..b9ff01cb104 100644
--- a/gcc/config/arm/iterators.md
+++ b/gcc/config/arm/iterators.md
@@ -50,6 +50,9 @@
;; A list of the 32bit and 64bit integer modes
(define_mode_iterator SIDI [SI DI])
+;; A list of the 64bit modes for thumb1.
+(define_mode_iterator DIDF [DI DF])
+
;; A list of atomic compare and swap success return modes
(define_mode_iterator CCSI [(CC_Z "TARGET_32BIT") (SI "TARGET_THUMB1")])
diff --git a/gcc/config/arm/thumb1.md b/gcc/config/arm/thumb1.md
index d7074b43f60..b4d7c6ea981 100644
--- a/gcc/config/arm/thumb1.md
+++ b/gcc/config/arm/thumb1.md
@@ -655,6 +655,42 @@
(set_attr "pool_range" "*,*,*,*,*,*,1018,*,*")]
)
+
+;; match patterns usable by ldmia/stmia
+(define_peephole2
+ [(set (match_operand:DIDF 0 "low_register_operand" "")
+ (match_operand:DIDF 1 "memory_operand" ""))]
+ "TARGET_THUMB1
+ && low_register_operand (XEXP (operands[1], 0), SImode)
+ && !reg_overlap_mentioned_p (XEXP (operands[1], 0), operands[0])
+ && peep2_reg_dead_p (1, XEXP (operands[1], 0))"
+ [(set (match_dup 0)
+ (match_dup 1))]
+ {
+operands[1] = change_address (operands[1], VOIDmode,
+ gen_rtx_POST_INC (SImode,
+ XEXP (operands[1], 0)));
+ }
+)
+
+(define_peephole2
+ [(set (match_operand:DIDF 0 "memory_operand" "")
+ (match_operand:DIDF 1 "low_register_operand" ""))]
+ "TARGET_THUMB1
+ && low_register_operand (XEXP (operands[0], 0), SImode)
+ && peep2_reg_dead_p (1, XEXP (operands[0], 0))
+ /* The low register in the transfer list may overlap the address,
+ but the second cannot. */
+ && REGNO (XEXP (operands[0], 0)) != (REGNO (operands[1]) + 1)"
+ [(set (match_dup 0)
+ (match_dup 1))]
+ {
+operands[0] = change_address (operands[0], VOIDmode,
+ gen_rtx_POST_INC (SImode,
+ XEXP (operands[0], 0)));
+ }
+)
+
(define_insn "*thumb1_movsi_insn"
[(set (match_operand:SI 0 "nonimmediate_operand" "=l,l,r,l,l,l,>,l, l,
m,*l*h*k")
(match_operand:SI 1 "general_operand" "l, I,j,J,K,>,l,i,
mi,l,*l*h*k"))]
@@ -2055,4 +2091,3 @@
(set_attr "conds" "clob")
(set_attr "type" "multiple")]
)
-
diff --git a/gcc/testsuite/gcc.target/arm/thumb1-load-store-64bit.c
b/gcc/testsuite/gcc.target/arm/thumb1-load-store-64bit.c
new file mode 100644
index 000..167fa9ec876
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/thumb1-load-store-64bit.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-mthumb -Os" } */
+/* { dg-require-effective-target arm_thumb1_ok } */
+
+void copy_df(double *dst, const double *src)
+{
+*dst = *src;
+}
+
+void copy_di(unsigned long long *dst, const unsigned long long *src)
+{
+*dst = *src;
+}
+
+/* { dg-final
[gcc r15-1841] c++ frontend: check for missing condition for novector [PR115623]
https://gcc.gnu.org/g:84acbfbecbdbc3fb2a395bd97e338b2b26fad374
commit r15-1841-g84acbfbecbdbc3fb2a395bd97e338b2b26fad374
Author: Tamar Christina
Date: Thu Jul 4 11:01:55 2024 +0100
c++ frontend: check for missing condition for novector [PR115623]
It looks like I forgot to check in the C++ frontend if a condition exist
for the
loop being adorned with novector. This causes a segfault because cond isn't
expected to be null.
This fixes it by issuing ignoring the pragma when there's no loop condition
the same way we do in the C frontend.
gcc/cp/ChangeLog:
PR c++/115623
* semantics.cc (finish_for_cond): Add check for C++ cond.
gcc/testsuite/ChangeLog:
PR c++/115623
* g++.dg/vect/vect-novector-pragma_2.cc: New test.
Diff:
---
gcc/cp/semantics.cc | 2 +-
gcc/testsuite/g++.dg/vect/vect-novector-pragma_2.cc | 10 ++
2 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/gcc/cp/semantics.cc b/gcc/cp/semantics.cc
index 12d79bdbb3f..cd3df13772d 100644
--- a/gcc/cp/semantics.cc
+++ b/gcc/cp/semantics.cc
@@ -1510,7 +1510,7 @@ finish_for_cond (tree cond, tree for_stmt, bool ivdep,
tree unroll,
build_int_cst (integer_type_node,
annot_expr_unroll_kind),
unroll);
- if (novector && cond != error_mark_node)
+ if (novector && cond && cond != error_mark_node)
FOR_COND (for_stmt) = build3 (ANNOTATE_EXPR,
TREE_TYPE (FOR_COND (for_stmt)),
FOR_COND (for_stmt),
diff --git a/gcc/testsuite/g++.dg/vect/vect-novector-pragma_2.cc
b/gcc/testsuite/g++.dg/vect/vect-novector-pragma_2.cc
new file mode 100644
index 000..d2a8eee8d71
--- /dev/null
+++ b/gcc/testsuite/g++.dg/vect/vect-novector-pragma_2.cc
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+
+void f (char *a, int i)
+{
+#pragma GCC novector
+ for (;;i++)
+a[i] *= 2;
+}
+
+
[gcc r14-10378] c++ frontend: check for missing condition for novector [PR115623]
https://gcc.gnu.org/g:1742b699c31e3ac4dadbedb6036ee2498b569259
commit r14-10378-g1742b699c31e3ac4dadbedb6036ee2498b569259
Author: Tamar Christina
Date: Thu Jul 4 11:01:55 2024 +0100
c++ frontend: check for missing condition for novector [PR115623]
It looks like I forgot to check in the C++ frontend if a condition exist
for the
loop being adorned with novector. This causes a segfault because cond isn't
expected to be null.
This fixes it by issuing ignoring the pragma when there's no loop condition
the same way we do in the C frontend.
gcc/cp/ChangeLog:
PR c++/115623
* semantics.cc (finish_for_cond): Add check for C++ cond.
gcc/testsuite/ChangeLog:
PR c++/115623
* g++.dg/vect/vect-novector-pragma_2.cc: New test.
(cherry picked from commit 84acbfbecbdbc3fb2a395bd97e338b2b26fad374)
Diff:
---
gcc/cp/semantics.cc | 2 +-
gcc/testsuite/g++.dg/vect/vect-novector-pragma_2.cc | 10 ++
2 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/gcc/cp/semantics.cc b/gcc/cp/semantics.cc
index b18fc7c61be..ec741c0b203 100644
--- a/gcc/cp/semantics.cc
+++ b/gcc/cp/semantics.cc
@@ -1501,7 +1501,7 @@ finish_for_cond (tree cond, tree for_stmt, bool ivdep,
tree unroll,
build_int_cst (integer_type_node,
annot_expr_unroll_kind),
unroll);
- if (novector && cond != error_mark_node)
+ if (novector && cond && cond != error_mark_node)
FOR_COND (for_stmt) = build3 (ANNOTATE_EXPR,
TREE_TYPE (FOR_COND (for_stmt)),
FOR_COND (for_stmt),
diff --git a/gcc/testsuite/g++.dg/vect/vect-novector-pragma_2.cc
b/gcc/testsuite/g++.dg/vect/vect-novector-pragma_2.cc
new file mode 100644
index 000..d2a8eee8d71
--- /dev/null
+++ b/gcc/testsuite/g++.dg/vect/vect-novector-pragma_2.cc
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+
+void f (char *a, int i)
+{
+#pragma GCC novector
+ for (;;i++)
+a[i] *= 2;
+}
+
+
[gcc r15-1842] testsuite: Update test for PR115537 to use SVE .
https://gcc.gnu.org/g:adcfb4fb8fb20a911c795312ff5f5284dba05275
commit r15-1842-gadcfb4fb8fb20a911c795312ff5f5284dba05275
Author: Tamar Christina
Date: Thu Jul 4 11:19:20 2024 +0100
testsuite: Update test for PR115537 to use SVE .
The PR was about SVE codegen, the testcase accidentally used neoverse-n1
instead of neoverse-v1 as was the original report.
This updates the tool options.
gcc/testsuite/ChangeLog:
PR tree-optimization/115537
* gcc.dg/vect/pr115537.c: Update flag from neoverse-n1 to
neoverse-v1.
Diff:
---
gcc/testsuite/gcc.dg/vect/pr115537.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/testsuite/gcc.dg/vect/pr115537.c
b/gcc/testsuite/gcc.dg/vect/pr115537.c
index 99ed467feb8..9f7347a5f2a 100644
--- a/gcc/testsuite/gcc.dg/vect/pr115537.c
+++ b/gcc/testsuite/gcc.dg/vect/pr115537.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-mcpu=neoverse-n1" { target aarch64*-*-* } } */
+/* { dg-additional-options "-mcpu=neoverse-v1" { target aarch64*-*-* } } */
char *a;
int b;
[gcc r14-10379] aarch64: PR target/115457 Implement missing __ARM_FEATURE_BF16 macro
https://gcc.gnu.org/g:1a97c8ed42562ceabb00c9c516435541909c134b
commit r14-10379-g1a97c8ed42562ceabb00c9c516435541909c134b
Author: Kyrylo Tkachov
Date: Thu Jun 27 16:10:41 2024 +0530
aarch64: PR target/115457 Implement missing __ARM_FEATURE_BF16 macro
The ACLE asks the user to test for __ARM_FEATURE_BF16 before using the
header but GCC doesn't set this up.
LLVM does, so this is an inconsistency between the compilers.
This patch enables that macro for TARGET_BF16_FP.
Bootstrapped and tested on aarch64-none-linux-gnu.
gcc/
PR target/115457
* config/aarch64/aarch64-c.cc (aarch64_update_cpp_builtins):
Define __ARM_FEATURE_BF16 for TARGET_BF16_FP.
gcc/testsuite/
PR target/115457
* gcc.target/aarch64/acle/bf16_feature.c: New test.
Signed-off-by: Kyrylo Tkachov
(cherry picked from commit c10942134fa759843ac1ed1424b86fcb8e6368ba)
Diff:
---
gcc/config/aarch64/aarch64-c.cc | 2 ++
gcc/testsuite/gcc.target/aarch64/acle/bf16_feature.c | 10 ++
2 files changed, 12 insertions(+)
diff --git a/gcc/config/aarch64/aarch64-c.cc b/gcc/config/aarch64/aarch64-c.cc
index d042e5fbd8c..f5d70339e4e 100644
--- a/gcc/config/aarch64/aarch64-c.cc
+++ b/gcc/config/aarch64/aarch64-c.cc
@@ -252,6 +252,8 @@ aarch64_update_cpp_builtins (cpp_reader *pfile)
"__ARM_FEATURE_BF16_VECTOR_ARITHMETIC", pfile);
aarch64_def_or_undef (TARGET_BF16_FP,
"__ARM_FEATURE_BF16_SCALAR_ARITHMETIC", pfile);
+ aarch64_def_or_undef (TARGET_BF16_FP,
+ "__ARM_FEATURE_BF16", pfile);
aarch64_def_or_undef (TARGET_LS64,
"__ARM_FEATURE_LS64", pfile);
aarch64_def_or_undef (AARCH64_ISA_RCPC, "__ARM_FEATURE_RCPC", pfile);
diff --git a/gcc/testsuite/gcc.target/aarch64/acle/bf16_feature.c
b/gcc/testsuite/gcc.target/aarch64/acle/bf16_feature.c
new file mode 100644
index 000..96584b4b988
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/acle/bf16_feature.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+
+#pragma GCC target "+bf16"
+#ifndef __ARM_FEATURE_BF16
+#error "__ARM_FEATURE_BF16 is not defined but should be!"
+#endif
+
+void
+foo (void) {}
+
[gcc r14-10380] aarch64: PR target/115475 Implement missing __ARM_FEATURE_SVE_BF16 macro
https://gcc.gnu.org/g:dc63b5dbe60da076f46cb3bcb10f0f84cfd7fb7d
commit r14-10380-gdc63b5dbe60da076f46cb3bcb10f0f84cfd7fb7d
Author: Kyrylo Tkachov
Date: Fri Jun 28 13:22:37 2024 +0530
aarch64: PR target/115475 Implement missing __ARM_FEATURE_SVE_BF16 macro
The ACLE requires __ARM_FEATURE_SVE_BF16 to be enabled when SVE and BF16
and the associated intrinsics are available.
GCC does support the required intrinsics for TARGET_SVE_BF16 so define
this macro too.
Bootstrapped and tested on aarch64-none-linux-gnu.
gcc/
PR target/115475
* config/aarch64/aarch64-c.cc (aarch64_update_cpp_builtins):
Define __ARM_FEATURE_SVE_BF16 for TARGET_SVE_BF16.
gcc/testsuite/
PR target/115475
* gcc.target/aarch64/acle/bf16_sve_feature.c: New test.
Signed-off-by: Kyrylo Tkachov
(cherry picked from commit 6492c7130d6ae9992298fc3d072e2589d1131376)
Diff:
---
gcc/config/aarch64/aarch64-c.cc | 3 +++
gcc/testsuite/gcc.target/aarch64/acle/bf16_sve_feature.c | 10 ++
2 files changed, 13 insertions(+)
diff --git a/gcc/config/aarch64/aarch64-c.cc b/gcc/config/aarch64/aarch64-c.cc
index f5d70339e4e..2aff097dd33 100644
--- a/gcc/config/aarch64/aarch64-c.cc
+++ b/gcc/config/aarch64/aarch64-c.cc
@@ -254,6 +254,9 @@ aarch64_update_cpp_builtins (cpp_reader *pfile)
"__ARM_FEATURE_BF16_SCALAR_ARITHMETIC", pfile);
aarch64_def_or_undef (TARGET_BF16_FP,
"__ARM_FEATURE_BF16", pfile);
+ aarch64_def_or_undef (TARGET_SVE_BF16,
+ "__ARM_FEATURE_SVE_BF16", pfile);
+
aarch64_def_or_undef (TARGET_LS64,
"__ARM_FEATURE_LS64", pfile);
aarch64_def_or_undef (AARCH64_ISA_RCPC, "__ARM_FEATURE_RCPC", pfile);
diff --git a/gcc/testsuite/gcc.target/aarch64/acle/bf16_sve_feature.c
b/gcc/testsuite/gcc.target/aarch64/acle/bf16_sve_feature.c
new file mode 100644
index 000..cb3ddac71a3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/acle/bf16_sve_feature.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+
+#pragma GCC target "+sve+bf16"
+#ifndef __ARM_FEATURE_SVE_BF16
+#error "__ARM_FEATURE_SVE_BF16 is not defined but should be!"
+#endif
+
+void
+foo (void) {}
+
[gcc r13-8890] aarch64: PR target/115457 Implement missing __ARM_FEATURE_BF16 macro
https://gcc.gnu.org/g:7785289f8d1f6350a3f48232ce578009b0e23534
commit r13-8890-g7785289f8d1f6350a3f48232ce578009b0e23534
Author: Kyrylo Tkachov
Date: Thu Jun 27 16:10:41 2024 +0530
aarch64: PR target/115457 Implement missing __ARM_FEATURE_BF16 macro
The ACLE asks the user to test for __ARM_FEATURE_BF16 before using the
header but GCC doesn't set this up.
LLVM does, so this is an inconsistency between the compilers.
This patch enables that macro for TARGET_BF16_FP.
Bootstrapped and tested on aarch64-none-linux-gnu.
gcc/
PR target/115457
* config/aarch64/aarch64-c.cc (aarch64_update_cpp_builtins):
Define __ARM_FEATURE_BF16 for TARGET_BF16_FP.
gcc/testsuite/
PR target/115457
* gcc.target/aarch64/acle/bf16_feature.c: New test.
Signed-off-by: Kyrylo Tkachov
(cherry picked from commit c10942134fa759843ac1ed1424b86fcb8e6368ba)
Diff:
---
gcc/config/aarch64/aarch64-c.cc | 2 ++
gcc/testsuite/gcc.target/aarch64/acle/bf16_feature.c | 10 ++
2 files changed, 12 insertions(+)
diff --git a/gcc/config/aarch64/aarch64-c.cc b/gcc/config/aarch64/aarch64-c.cc
index 6c5331a7625..51709d6044e 100644
--- a/gcc/config/aarch64/aarch64-c.cc
+++ b/gcc/config/aarch64/aarch64-c.cc
@@ -202,6 +202,8 @@ aarch64_update_cpp_builtins (cpp_reader *pfile)
"__ARM_FEATURE_BF16_VECTOR_ARITHMETIC", pfile);
aarch64_def_or_undef (TARGET_BF16_FP,
"__ARM_FEATURE_BF16_SCALAR_ARITHMETIC", pfile);
+ aarch64_def_or_undef (TARGET_BF16_FP,
+ "__ARM_FEATURE_BF16", pfile);
aarch64_def_or_undef (TARGET_LS64,
"__ARM_FEATURE_LS64", pfile);
aarch64_def_or_undef (AARCH64_ISA_RCPC, "__ARM_FEATURE_RCPC", pfile);
diff --git a/gcc/testsuite/gcc.target/aarch64/acle/bf16_feature.c
b/gcc/testsuite/gcc.target/aarch64/acle/bf16_feature.c
new file mode 100644
index 000..96584b4b988
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/acle/bf16_feature.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+
+#pragma GCC target "+bf16"
+#ifndef __ARM_FEATURE_BF16
+#error "__ARM_FEATURE_BF16 is not defined but should be!"
+#endif
+
+void
+foo (void) {}
+
[gcc r13-8891] aarch64: PR target/115475 Implement missing __ARM_FEATURE_SVE_BF16 macro
https://gcc.gnu.org/g:40d54856c1189ab6125d3eeb064df25082dd0e50
commit r13-8891-g40d54856c1189ab6125d3eeb064df25082dd0e50
Author: Kyrylo Tkachov
Date: Fri Jun 28 13:22:37 2024 +0530
aarch64: PR target/115475 Implement missing __ARM_FEATURE_SVE_BF16 macro
The ACLE requires __ARM_FEATURE_SVE_BF16 to be enabled when SVE and BF16
and the associated intrinsics are available.
GCC does support the required intrinsics for TARGET_SVE_BF16 so define
this macro too.
Bootstrapped and tested on aarch64-none-linux-gnu.
gcc/
PR target/115475
* config/aarch64/aarch64-c.cc (aarch64_update_cpp_builtins):
Define __ARM_FEATURE_SVE_BF16 for TARGET_SVE_BF16.
gcc/testsuite/
PR target/115475
* gcc.target/aarch64/acle/bf16_sve_feature.c: New test.
Signed-off-by: Kyrylo Tkachov
(cherry picked from commit 6492c7130d6ae9992298fc3d072e2589d1131376)
Diff:
---
gcc/config/aarch64/aarch64-c.cc | 3 +++
gcc/testsuite/gcc.target/aarch64/acle/bf16_sve_feature.c | 10 ++
2 files changed, 13 insertions(+)
diff --git a/gcc/config/aarch64/aarch64-c.cc b/gcc/config/aarch64/aarch64-c.cc
index 51709d6044e..6ddfcc7ce3e 100644
--- a/gcc/config/aarch64/aarch64-c.cc
+++ b/gcc/config/aarch64/aarch64-c.cc
@@ -204,6 +204,9 @@ aarch64_update_cpp_builtins (cpp_reader *pfile)
"__ARM_FEATURE_BF16_SCALAR_ARITHMETIC", pfile);
aarch64_def_or_undef (TARGET_BF16_FP,
"__ARM_FEATURE_BF16", pfile);
+ aarch64_def_or_undef (TARGET_SVE_BF16,
+ "__ARM_FEATURE_SVE_BF16", pfile);
+
aarch64_def_or_undef (TARGET_LS64,
"__ARM_FEATURE_LS64", pfile);
aarch64_def_or_undef (AARCH64_ISA_RCPC, "__ARM_FEATURE_RCPC", pfile);
diff --git a/gcc/testsuite/gcc.target/aarch64/acle/bf16_sve_feature.c
b/gcc/testsuite/gcc.target/aarch64/acle/bf16_sve_feature.c
new file mode 100644
index 000..cb3ddac71a3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/acle/bf16_sve_feature.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+
+#pragma GCC target "+sve+bf16"
+#ifndef __ARM_FEATURE_SVE_BF16
+#error "__ARM_FEATURE_SVE_BF16 is not defined but should be!"
+#endif
+
+void
+foo (void) {}
+
[gcc r12-10599] aarch64: PR target/115457 Implement missing __ARM_FEATURE_BF16 macro
https://gcc.gnu.org/g:ebf561429ee4fbd125aa51ee985e32f1cfd4daed
commit r12-10599-gebf561429ee4fbd125aa51ee985e32f1cfd4daed
Author: Kyrylo Tkachov
Date: Thu Jun 27 16:10:41 2024 +0530
aarch64: PR target/115457 Implement missing __ARM_FEATURE_BF16 macro
The ACLE asks the user to test for __ARM_FEATURE_BF16 before using the
header but GCC doesn't set this up.
LLVM does, so this is an inconsistency between the compilers.
This patch enables that macro for TARGET_BF16_FP.
Bootstrapped and tested on aarch64-none-linux-gnu.
gcc/
PR target/115457
* config/aarch64/aarch64-c.cc (aarch64_update_cpp_builtins):
Define __ARM_FEATURE_BF16 for TARGET_BF16_FP.
gcc/testsuite/
PR target/115457
* gcc.target/aarch64/acle/bf16_feature.c: New test.
Signed-off-by: Kyrylo Tkachov
(cherry picked from commit c10942134fa759843ac1ed1424b86fcb8e6368ba)
Diff:
---
gcc/config/aarch64/aarch64-c.cc | 2 ++
gcc/testsuite/gcc.target/aarch64/acle/bf16_feature.c | 10 ++
2 files changed, 12 insertions(+)
diff --git a/gcc/config/aarch64/aarch64-c.cc b/gcc/config/aarch64/aarch64-c.cc
index a4c407724a7..b31b967c140 100644
--- a/gcc/config/aarch64/aarch64-c.cc
+++ b/gcc/config/aarch64/aarch64-c.cc
@@ -200,6 +200,8 @@ aarch64_update_cpp_builtins (cpp_reader *pfile)
"__ARM_FEATURE_BF16_VECTOR_ARITHMETIC", pfile);
aarch64_def_or_undef (TARGET_BF16_FP,
"__ARM_FEATURE_BF16_SCALAR_ARITHMETIC", pfile);
+ aarch64_def_or_undef (TARGET_BF16_FP,
+ "__ARM_FEATURE_BF16", pfile);
aarch64_def_or_undef (TARGET_LS64,
"__ARM_FEATURE_LS64", pfile);
aarch64_def_or_undef (AARCH64_ISA_RCPC, "__ARM_FEATURE_RCPC", pfile);
diff --git a/gcc/testsuite/gcc.target/aarch64/acle/bf16_feature.c
b/gcc/testsuite/gcc.target/aarch64/acle/bf16_feature.c
new file mode 100644
index 000..96584b4b988
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/acle/bf16_feature.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+
+#pragma GCC target "+bf16"
+#ifndef __ARM_FEATURE_BF16
+#error "__ARM_FEATURE_BF16 is not defined but should be!"
+#endif
+
+void
+foo (void) {}
+
[gcc r12-10600] aarch64: PR target/115475 Implement missing __ARM_FEATURE_SVE_BF16 macro
https://gcc.gnu.org/g:cdeb7ce83f71d1527626975e70d294ef55535d03
commit r12-10600-gcdeb7ce83f71d1527626975e70d294ef55535d03
Author: Kyrylo Tkachov
Date: Fri Jun 28 13:22:37 2024 +0530
aarch64: PR target/115475 Implement missing __ARM_FEATURE_SVE_BF16 macro
The ACLE requires __ARM_FEATURE_SVE_BF16 to be enabled when SVE and BF16
and the associated intrinsics are available.
GCC does support the required intrinsics for TARGET_SVE_BF16 so define
this macro too.
Bootstrapped and tested on aarch64-none-linux-gnu.
gcc/
PR target/115475
* config/aarch64/aarch64-c.cc (aarch64_update_cpp_builtins):
Define __ARM_FEATURE_SVE_BF16 for TARGET_SVE_BF16.
gcc/testsuite/
PR target/115475
* gcc.target/aarch64/acle/bf16_sve_feature.c: New test.
Signed-off-by: Kyrylo Tkachov
(cherry picked from commit 6492c7130d6ae9992298fc3d072e2589d1131376)
Diff:
---
gcc/config/aarch64/aarch64-c.cc | 3 +++
gcc/testsuite/gcc.target/aarch64/acle/bf16_sve_feature.c | 10 ++
2 files changed, 13 insertions(+)
diff --git a/gcc/config/aarch64/aarch64-c.cc b/gcc/config/aarch64/aarch64-c.cc
index b31b967c140..e024d410dc7 100644
--- a/gcc/config/aarch64/aarch64-c.cc
+++ b/gcc/config/aarch64/aarch64-c.cc
@@ -202,6 +202,9 @@ aarch64_update_cpp_builtins (cpp_reader *pfile)
"__ARM_FEATURE_BF16_SCALAR_ARITHMETIC", pfile);
aarch64_def_or_undef (TARGET_BF16_FP,
"__ARM_FEATURE_BF16", pfile);
+ aarch64_def_or_undef (TARGET_SVE_BF16,
+ "__ARM_FEATURE_SVE_BF16", pfile);
+
aarch64_def_or_undef (TARGET_LS64,
"__ARM_FEATURE_LS64", pfile);
aarch64_def_or_undef (AARCH64_ISA_RCPC, "__ARM_FEATURE_RCPC", pfile);
diff --git a/gcc/testsuite/gcc.target/aarch64/acle/bf16_sve_feature.c
b/gcc/testsuite/gcc.target/aarch64/acle/bf16_sve_feature.c
new file mode 100644
index 000..cb3ddac71a3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/acle/bf16_sve_feature.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+
+#pragma GCC target "+sve+bf16"
+#ifndef __ARM_FEATURE_SVE_BF16
+#error "__ARM_FEATURE_SVE_BF16 is not defined but should be!"
+#endif
+
+void
+foo (void) {}
+
[gcc r15-1843] Skip 30_threads/future/members/poll.cc on hppa*-*-linux*
https://gcc.gnu.org/g:46ffda9bf19abeed95e9d758ed5e776ee221ee9e
commit r15-1843-g46ffda9bf19abeed95e9d758ed5e776ee221ee9e
Author: John David Anglin
Date: Thu Jul 4 09:16:18 2024 -0400
Skip 30_threads/future/members/poll.cc on hppa*-*-linux*
hppa*-*-linux* lacks high resolution timer support. Timer resolution
ranges from 1 to 10ms. As a result, a large number of iterations are
needed for the wait_for_0 and ready loops. This causes the
wait_until_sys_epoch and wait_until_steady_epoch loops to timeout.
There the loop wait time is determined by the timer resolution.
2024-07-04 John David Anglin
libstdc++-v3/ChangeLog:
PR libstdc++/98678
* testsuite/30_threads/future/members/poll.cc: Skip on
hppa*-*-linux*.
Diff:
---
libstdc++-v3/testsuite/30_threads/future/members/poll.cc | 1 +
1 file changed, 1 insertion(+)
diff --git a/libstdc++-v3/testsuite/30_threads/future/members/poll.cc
b/libstdc++-v3/testsuite/30_threads/future/members/poll.cc
index 4fa282bd87f..2bdbe7a48ce 100644
--- a/libstdc++-v3/testsuite/30_threads/future/members/poll.cc
+++ b/libstdc++-v3/testsuite/30_threads/future/members/poll.cc
@@ -19,6 +19,7 @@
// { dg-do run { target c++11 } }
// { dg-additional-options "-pthread" { target pthread } }
// { dg-require-gthreads "" }
+// { dg-skip-if "no high resolution timer support" { hppa*-*-linux* } }
#include
#include
[gcc(refs/vendors/ibm/heads/gcc-14-branch)] ibm: Merge up to top of releases/gcc-14
https://gcc.gnu.org/g:a9332cff81c899769b2aa6e744087f1a080cf010 commit a9332cff81c899769b2aa6e744087f1a080cf010 Merge: 96b284e64a7 0f71e52717b Author: Peter Bergner Date: Wed Jul 3 22:27:59 2024 -0500 ibm: Merge up to top of releases/gcc-14 2024-07-03 Peter Bergner Merge up to releases/gcc-14 0f71e52717b20c41c168b57245a8c12bdaa017e3 Diff: gcc/ChangeLog | 271 + gcc/ChangeLog.ibm | 4 + gcc/DATESTAMP | 2 +- gcc/c-family/ChangeLog | 25 ++ gcc/c-family/c-opts.cc | 2 +- gcc/c-family/c-warn.cc | 13 +- gcc/c-family/c.opt | 2 +- gcc/c/ChangeLog| 22 ++ gcc/c/c-decl.cc| 38 ++- gcc/c/c-parser.cc | 4 +- gcc/config/aarch64/aarch64-cores.def | 2 + gcc/config/aarch64/aarch64-ldp-fusion.cc | 4 +- gcc/config/aarch64/aarch64-tune.md | 2 +- gcc/config/avr/avr.cc | 35 ++- gcc/config/avr/avr.md | 18 +- gcc/config/pa/pa.md| 18 -- gcc/config/pa/pa32-linux.h | 5 + gcc/config/riscv/riscv-target-attr.cc | 6 +- gcc/config/rs6000/altivec.md | 222 - gcc/config/rs6000/rs6000-logue.cc | 7 +- gcc/config/rs6000/rs6000.cc| 24 +- gcc/config/rs6000/rs6000.md| 15 ++ gcc/config/rs6000/vsx.md | 28 ++- gcc/config/s390/s390.cc| 49 +++- gcc/config/s390/vx-builtins.md | 2 +- gcc/config/sparc/linux64.h | 2 +- gcc/configure | 2 + gcc/configure.ac | 2 + gcc/cp/ChangeLog | 78 ++ gcc/cp/call.cc | 3 +- gcc/cp/decl2.cc| 7 +- gcc/cp/parser.cc | 10 +- gcc/cp/pt.cc | 6 +- gcc/cp/semantics.cc| 8 - gcc/cp/typeck.cc | 10 +- gcc/doc/invoke.texi| 4 +- gcc/fortran/ChangeLog | 31 +++ gcc/fortran/trans-array.cc | 20 +- gcc/fortran/trans-decl.cc | 4 +- gcc/fortran/trans-stmt.cc | 5 +- gcc/gimple-lower-bitint.cc | 5 +- gcc/opts-common.cc | 6 +- gcc/testsuite/ChangeLog| 247 +++ gcc/testsuite/c-c++-common/Warray-compare-3.c | 13 + gcc/testsuite/g++.dg/cpp1y/decltype-auto8.C| 22 ++ gcc/testsuite/g++.dg/cpp1z/pr115440.C | 8 + gcc/testsuite/g++.dg/cpp23/ext-floating18.C| 26 ++ .../g++.dg/cpp2a/class-deduction-alias22.C | 14 ++ gcc/testsuite/g++.dg/cpp2a/concepts-requires38.C | 14 ++ gcc/testsuite/g++.dg/overload/error7.C | 10 + gcc/testsuite/g++.dg/pch/pr115312.C| 2 + gcc/testsuite/g++.dg/pch/pr115312.Hs | 1 + gcc/testsuite/g++.dg/template/array37.C| 14 ++ gcc/testsuite/g++.dg/template/linkage5.C | 14 ++ gcc/testsuite/g++.dg/torture/vshuf-mem.C | 27 ++ gcc/testsuite/g++.dg/vect/pr115278.cc | 38 +++ gcc/testsuite/g++.target/powerpc/pr106069.C| 119 + gcc/testsuite/gcc.dg/bitint-107.c | 16 ++ gcc/testsuite/gcc.dg/pr114574-1.c | 6 +- gcc/testsuite/gcc.dg/pr114574-2.c | 6 +- gcc/testsuite/gcc.dg/pr114930.c| 9 + gcc/testsuite/gcc.dg/pr115502.c| 9 + .../gcc.target/avr/torture/pr88236-pr115726.c | 115 + gcc/testsuite/gcc.target/avr/torture/pr98762.c | 19 ++ gcc/testsuite/gcc.target/i386/pr115508.c | 15 ++ gcc/testsuite/gcc.target/powerpc/pr106069-1.c | 39 +++ gcc/testsuite/gcc.target/powerpc/pr106069-2.c | 37 +++ gcc/testsuite/gcc.target/powerpc/pr114846.c| 20 ++ gcc/testsuite/gcc.target/powerpc/pr115355.c| 37 +++ .../gcc.target/riscv/rvv/vsetvl/pr115214.c | 52 gcc/testsuite/gcc.target/s390/ccor.c | 4 +- .../gcc.target/s390/ifcvt-one-insn-bool.c | 2 +- .../gfortran.dg/allocate_with_source_33.f90| 69 ++ gcc/testsuite/gfortran.dg/bind_c_char_11.f90 | 45 gcc/testsuite/gfortran.dg/opti
[gcc/ibm/heads/gcc-14-branch] (70 commits) ibm: Merge up to top of releases/gcc-14
The branch 'ibm/heads/gcc-14-branch' was updated to point to: a9332cff81c... ibm: Merge up to top of releases/gcc-14 It previously pointed to: 96b284e64a7... ibm: Create the ibm/gcc-14-branch Diff: Summary of changes (added commits): --- a9332cf... ibm: Merge up to top of releases/gcc-14 0f71e52... Daily bump. (*) 6e1fb1f... Revert "Delete MALLOC_ABI_ALIGNMENT define from pa32-linux. (*) acde9f8... hppa: Fix ICE caused by mismatched predicate and constraint (*) 3389a23... preprocessor: Create the parser before handling command-lin (*) 5574450... AVR: target/98762 - Handle partial clobber in movqi output. (*) 052f78d... rs6000: Fix wrong RTL patterns for vector merge high/low sh (*) 0e495e8... rs6000: Fix wrong RTL patterns for vector merge high/low ch (*) 88bfbab... Daily bump. (*) 8eb4695... aarch64: Fix typo in aarch64-ldp-fusion.cc:combine_reg_note (*) 5db1392... Daily bump. (*) 7249b3c... AVR: target/88236, target/115726 - Fix __memx code generati (*) 37bbd2c... c: Fix ICE related to incomplete structures in C23 [PR11493 (*) 78bd4b1... Daily bump. (*) 603b344... Fortran: fix ALLOCATE with SOURCE of deferred character len (*) 9f14748... Fortran: fix passing of optional dummy as actual to optiona (*) b31e190... Fortran: fix for CHARACTER(len=*) dummies with bind(C) [PR1 (*) 4fe3fff... Daily bump. (*) 47cbc76... Daily bump. (*) e6b115b... c++: decltype of capture proxy of ref [PR115504] (*) a00a8d4... c++: alias CTAD and copy deduction guide [PR115198] (*) 33a9c4d... c++: using non-dep array var of unknown bound [PR115358] (*) d5e352a... libstdc++: Fix std::format for chrono::duration with unsign (*) ef8b60d... rs6000: Fix wrong RTL patterns for vector merge high/low wo (*) 15d304d... Daily bump. (*) a8b77a6... libstdc++: Replace viewcvs links in docs with cgit links (*) b70af0b... [libstdc++] [testsuite] defer to check_vect_support* [PR115 (*) c2878a9... aarch64: Add support for -mcpu=grace (*) 6e6f10c... tree-ssa-pre.c/115214(ICE in find_or_generate_expression, a (*) f9cc628... Daily bump. (*) 532357b... Daily bump. (*) f91d9b3... libstdc++: Remove confusing text from status tables for rel (*) b383719... Fix PR c/115587, uninitialized variable in c_parser_omp_loo (*) 4bf93fc... SPARC: fix internal error with -mv8plus on 64-bit Linux (*) b7157f3... c-family: Add Warning property to Wnrvo option [PR115624] (*) faf5994... Daily bump. (*) 2b5e8f9... rs6000: Don't clobber return value when eh_return called [P (*) 1a2329d... Daily bump. (*) 1735b86... Daily bump. (*) 70d9d92... Daily bump. (*) 9421f02... AArch64: Fix cpu features initialization [PR115342] (*) a851931... libstdc++: Fix test on x86_64 and non-simd targets (*) a16f47f... Build: Set gcc_cv_as_mips_explicit_relocs if gcc_cv_as_mips (*) 272e8c9... tree-optimization/115278 - fix DSE in if-conversion wrt vol (*) 65e2586... tree-optimization/115508 - fix ICE with SLP scheduling and (*) 85d32e6... Avoid SLP_REPRESENTATIVE access for VEC_PERM in SLP schedul (*) 30fca2c... Daily bump. (*) e77f314... libstdc++: Fix find_last_set(simd_mask) to ignore padding b (*) d26fa1c... vshuf-mem.C: Make -march=z14 depend on s390_vxe (*) b4e4997... testsuite: Add -Wno-psabi to vshuf-mem.C test (*) 166c9f9... IBM Z: Fix ICE in expand_perm_as_replicate (*) f79e909... bitint: Fix up lowering of COMPLEX_EXPR [PR115544] (*) 74a58c3... diagnostics: Fix add_misspelling_candidates [PR115440] (*) 946f26e... Daily bump. (*) 6f6103c... Daily bump. (*) 789f055... Daily bump. (*) 9226487... c-family: Fix -Warray-compare warning ICE [PR115290] (*) 5be6d9d... c++: Fix up floating point conversion rank comparison for _ (*) 20cda2e... c++: undeclared identifier in requires-clause [PR99678] (*) 4df8640... c++: ICE w/ ambig and non-strictly-viable cands [PR115239] (*) 9583f78... c++: visibility wrt concept-id as targ [PR115283] (*) 0ed63e3... s390: testsuite: Fix ifcvt-one-insn-bool.c (*) 8f124e6... s390: Implement TARGET_NOCE_CONVERSION_PROFITABLE_P [PR1095 (*) 13a09f3... Daily bump. (*) a4f8e9e... Daily bump. (*) 3fe255f... riscv: Allocate enough space to strcpy() string (*) 6b2fc15... Daily bump. (*) 75251f5... libstdc++: Fix declaration of posix_memalign for freestandi (*) b740c09... Daily bump. (*) 8bd6e40... Daily bump. (*) (*) This commit already exists in another branch. Because the reference `refs/vendors/ibm/heads/gcc-14-branch' matches your hooks.email-new-commits-only configuration, no separate email is sent for this commit.
[gcc/ibm/heads/gcc-13-branch] (83 commits) ibm: Merge up to top of releases/gcc-13
The branch 'ibm/heads/gcc-13-branch' was updated to point to:
b7341a9059d... ibm: Merge up to top of releases/gcc-13
It previously pointed to:
c3db5f495a1... ibm: Merge up to top of releases/gcc-13
Diff:
Summary of changes (added commits):
---
b7341a9... ibm: Merge up to top of releases/gcc-13
a26c560... Daily bump. (*)
ecd6ebe... hppa: Fix ICE caused by mismatched predicate and constraint (*)
ba9fef4... AVR: target/98762 - Handle partial clobber in movqi output. (*)
bab38d9... rs6000: Fix wrong RTL patterns for vector merge high/low sh (*)
ffdd377... rs6000: Fix wrong RTL patterns for vector merge high/low ch (*)
2dd3934... Daily bump. (*)
b4abe8f... Daily bump. (*)
743575b... AVR: target/88236, target/115726 - Fix __memx code generati (*)
461c846... Daily bump. (*)
5a4ea0b... Daily bump. (*)
ae1f6eb... Daily bump. (*)
84cae12... libstdc++: Replace viewcvs links in docs with cgit links (*)
4b64a10... libstdc++: Fix std::format for chrono::duration with unsign (*)
361bfce... rs6000: Fix wrong RTL patterns for vector merge high/low wo (*)
e65b1a1... Daily bump. (*)
5aa9ed0... AArch64: Fix strict-align cpymem/setmem [PR103100] (*)
c93a9bb... aarch64: Fix +nocrypto handling (*)
3de1c49... [libstdc++] [testsuite] defer to check_vect_support* [PR115 (*)
952ea32... Add support for -mcpu=grace (*)
d081007... Daily bump. (*)
563aa24... Daily bump. (*)
bc6e4bd... libstdc++: Remove confusing text from status tables for rel (*)
2cb5a44... Daily bump. (*)
dd54ed4... rs6000: Don't clobber return value when eh_return called [P (*)
db36cf4... Daily bump. (*)
464c4af... Daily bump. (*)
df9c225... Daily bump. (*)
c335e34... libstdc++: Fix test on x86_64 and non-simd targets (*)
fbd088a... libstdc++: Fix find_last_set(simd_mask) to ignore padding b (*)
701de95... Daily bump. (*)
e216eb1... diagnostics: Fix add_misspelling_candidates [PR115440] (*)
abde654... Daily bump. (*)
0530884... Fortran: fix ALLOCATE with SOURCE=, zero-length character [ (*)
41ea263... Daily bump. (*)
3ff2339... Daily bump. (*)
be14e6c... c-family: Fix -Warray-compare warning ICE [PR115290] (*)
6d0a0c5... c++: Fix up floating point conversion rank comparison for _ (*)
a62db39... Daily bump. (*)
663be6b... Daily bump. (*)
072e71f... Daily bump. (*)
24dbdd2... libstdc++: Fix declaration of posix_memalign for freestandi (*)
7da2f89... Daily bump. (*)
341342d... Daily bump. (*)
113a104... arm: Add .type and .size to __gnu_cmse_nonsecure_call [PR11 (*)
dfab685... testsuite: Fix expand-return CMSE test for Armv8.1-M [PR115 (*)
bf3ffb4... arm: Zero/Sign extends for CMSE security on Armv8-M.baselin (*)
3f5d0ca... Daily bump. (*)
6eb0e93... Fix building JIT with musl libc [PR115442] (*)
ef21690... libstdc++: Fix simd conversion for -fno-signed-char f (*)
0efc270... libstdc++: Avoid MMX return types from __builtin_shufflevec (*)
26113c2... libstdc++: Use __builtin_shufflevector for simd split and c (*)
7813d94... c: Fix up pointer types to may_alias structures [PR114493] (*)
865d60a... fold-const: Fix up CLZ handling in tree_call_nonnegative_wa (*)
f9db8b0... builtins: Force SAVE_EXPR for __builtin_{add,sub,mul}_overf (*)
308ca60... invoke.texi: Clarify -march=lujiazui (*)
50b5019... rs6000: Fix up PCH in --enable-host-pie builds [PR115324] (*)
8deaab6... combine: Fix up simplify_compare_const [PR115092] (*)
f2ef3ac... Daily bump. (*)
ef494b1... Fix crash on access-to-incomplete type (*)
02025fb... Add testcase for PR ada/114398 (*)
e54d909... ada: Storage_Error in indirect call to function returning l (*)
7067b7e... Daily bump. (*)
cd8dc16... Daily bump. (*)
e11fb72... Daily bump. (*)
e4f85ea... Disable FMADD in chains for Zen4 and generic (*)
3cf6c1f... Daily bump. (*)
c0f2293... Daily bump. (*)
16fe81c... Daily bump. (*)
38360ba... Daily bump. (*)
ed06ca8... alpha: Fix invalid RTX in divmodsi insn patterns [PR115297] (*)
218246b... Daily bump. (*)
6634ff0... Daily bump. (*)
c57d73f... AVR: tree-optimization/115307 - Work around isinf bloat fro (*)
b45d728... AVR: target/115317 - Make isinf(-Inf) return -1. (*)
3687dcf... libstdc++: Replace link to gcc-4.3.2 docs in manual [PR1152 (*)
acdf0f7... Daily bump. (*)
2602b71... vect: Tighten vect_determine_precisions_from_range [PR11328 (*)
0836216... vect: Fix access size alignment assumption [PR115192] (*)
173f876... i386: Fix ix86_option override after change [PR 113719] (*)
d0fb9d2... Daily bump. (*)
3be8fa7... MIPS16: Mark $2/$3 as clobbered if GP is used (*)
2618cda... Daily bump. (*)
(*) This commit already exists in another branch.
Because the reference `refs/vendors/ibm/heads/gcc-13-branch' matches
your hooks.email-new-commits-only configuration,
no separate email is sent for this commit.
[gcc(refs/vendors/ibm/heads/gcc-13-branch)] ibm: Merge up to top of releases/gcc-13
https://gcc.gnu.org/g:b7341a9059d7a4ff8fcbffd7b968209a732d0163 commit b7341a9059d7a4ff8fcbffd7b968209a732d0163 Merge: c3db5f495a1 a26c560d3f6 Author: Peter Bergner Date: Wed Jul 3 22:36:49 2024 -0500 ibm: Merge up to top of releases/gcc-13 2024-07-03 Peter Bergner Merge up to releases/gcc-13 a26c560d3f679d5237dd5191869e845740b94759 Diff: gcc/ChangeLog | 333 + gcc/ChangeLog.ibm | 4 + gcc/DATESTAMP | 2 +- gcc/ada/ChangeLog | 13 + gcc/ada/exp_ch6.adb| 11 +- gcc/ada/exp_util.adb | 6 + gcc/ada/sem_ch6.adb| 12 +- gcc/builtins.cc| 16 +- gcc/c-family/ChangeLog | 10 + gcc/c-family/c-warn.cc | 13 +- gcc/c/ChangeLog| 10 + gcc/c/c-decl.cc| 15 + gcc/combine.cc | 6 +- gcc/common/config/aarch64/aarch64-common.cc| 35 ++- gcc/config/aarch64/aarch64-c.cc| 2 +- gcc/config/aarch64/aarch64-cores.def | 2 + gcc/config/aarch64/aarch64-tune.md | 2 +- gcc/config/aarch64/aarch64.cc | 52 ++-- gcc/config/aarch64/aarch64.h | 10 +- gcc/config/aarch64/aarch64.md | 4 +- gcc/config/alpha/alpha.md | 21 +- gcc/config/alpha/constraints.md| 2 +- gcc/config/arm/arm.cc | 76 - gcc/config/avr/avr.cc | 35 ++- gcc/config/avr/avr.md | 34 ++- gcc/config/i386/i386-options.cc| 10 +- gcc/config/i386/x86-tune.def | 2 +- gcc/config/mips/mips.cc| 11 +- gcc/config/pa/pa.md| 18 -- gcc/config/rs6000/altivec.md | 222 ++ gcc/config/rs6000/rs6000-builtin.cc| 2 +- gcc/config/rs6000/rs6000-c.cc | 62 ++-- gcc/config/rs6000/rs6000-gen-builtins.cc | 72 ++--- gcc/config/rs6000/rs6000-logue.cc | 7 +- gcc/config/rs6000/rs6000.cc| 24 +- gcc/config/rs6000/rs6000.md| 15 + gcc/config/rs6000/vsx.md | 28 +- gcc/cp/ChangeLog | 11 + gcc/cp/typeck.cc | 3 + gcc/doc/invoke.texi| 10 +- gcc/fold-const.cc | 18 +- gcc/fortran/ChangeLog | 10 + gcc/fortran/trans-stmt.cc | 3 +- gcc/jit/ChangeLog | 9 + gcc/jit/jit-recording.cc | 1 + gcc/opts-common.cc | 6 +- gcc/testsuite/ChangeLog| 188 gcc/testsuite/c-c++-common/Warray-compare-3.c | 13 + gcc/testsuite/g++.dg/cpp1z/pr115440.C | 8 + gcc/testsuite/g++.dg/cpp23/ext-floating18.C| 26 ++ gcc/testsuite/g++.target/powerpc/pr106069.C| 119 gcc/testsuite/gcc.c-torture/execute/pr108789.c | 39 +++ gcc/testsuite/gcc.dg/pr114493-1.c | 19 ++ gcc/testsuite/gcc.dg/pr114493-2.c | 26 ++ gcc/testsuite/gcc.dg/pr114902.c| 23 ++ gcc/testsuite/gcc.dg/pr115092.c| 16 + gcc/testsuite/gcc.dg/vect/pr113281-1.c | 17 ++ gcc/testsuite/gcc.dg/vect/pr113281-2.c | 50 gcc/testsuite/gcc.dg/vect/pr113281-3.c | 39 +++ gcc/testsuite/gcc.dg/vect/pr113281-4.c | 55 gcc/testsuite/gcc.dg/vect/pr113281-5.c | 66 gcc/testsuite/gcc.dg/vect/pr115192.c | 28 ++ gcc/testsuite/gcc.target/aarch64/options_set_27.c | 9 + gcc/testsuite/gcc.target/aarch64/options_set_4.c | 2 +- gcc/testsuite/gcc.target/alpha/pr115297.c | 13 + gcc/testsuite/gcc.target/arm/cmse/extend-return.c | 62 +++- .../gcc.target/avr/torture/pr115307-isinf.c| 21 ++ .../gcc.target/avr/torture/pr115317-isinf.c| 55 .../gcc.target/avr/torture/pr88236-pr115726.c | 115 +++ gcc/testsuite/gcc.target/avr/torture/pr98762.c | 19 ++ gcc/testsuite/gcc.target/powerpc/pr106069-1.c | 39 +++ gcc/testsuite/gcc.target/powerpc/pr106069-2.c | 37 +++ gcc/testsuite/gcc.target/powerpc/pr114846.c| 20 ++ gcc/testsuite/gcc.target/powerpc/pr115355.c| 37 +++ .../gfortran.dg/allocate_with_source_32.f9
[gcc(refs/users/mikael/heads/non_lvalue_match.pd_v01)] match: Simplify double not and double negate to a non_lvalue
https://gcc.gnu.org/g:540cb6b0dd2a9ece734e927d520a9ca15e8afff8
commit 540cb6b0dd2a9ece734e927d520a9ca15e8afff8
Author: Mikael Morin
Date: Thu Jul 4 12:59:34 2024 +0200
match: Simplify double not and double negate to a non_lvalue
gcc/ChangeLog:
* match.pd: Add a NON_LVALUE_EXPR wrapper around the simplification
of doubled unary operators NEGATE_EXPR and BIT_NOT_EXPR.
gcc/testsuite/ChangeLog:
* gfortran.dg/non_lvalue_1.f90: New test.
Diff:
---
gcc/match.pd | 4 ++--
gcc/testsuite/gfortran.dg/non_lvalue_1.f90 | 21 +
2 files changed, 23 insertions(+), 2 deletions(-)
diff --git a/gcc/match.pd b/gcc/match.pd
index 4edfa2ae2c9..d0859545ada 100644
--- a/gcc/match.pd
+++ b/gcc/match.pd
@@ -2294,7 +2294,7 @@ DEFINE_INT_AND_FLOAT_ROUND_FN (RINT)
/* ~~x -> x */
(simplify
(bit_not (bit_not @0))
- @0)
+ (non_lvalue @0))
/* zero_one_valued_p will match when a value is known to be either
0 or 1 including constants 0 or 1.
@@ -3674,7 +3674,7 @@ DEFINE_INT_AND_FLOAT_ROUND_FN (RINT)
(negate (nop_convert? (negate @1)))
(if (!TYPE_OVERFLOW_SANITIZED (type)
&& !TYPE_OVERFLOW_SANITIZED (TREE_TYPE (@1)))
- (view_convert @1)))
+ (non_lvalue (view_convert @1
/* We can't reassociate floating-point unless -fassociative-math
or fixed-point plus or minus because of saturation to +-Inf. */
diff --git a/gcc/testsuite/gfortran.dg/non_lvalue_1.f90
b/gcc/testsuite/gfortran.dg/non_lvalue_1.f90
new file mode 100644
index 000..ac52b272094
--- /dev/null
+++ b/gcc/testsuite/gfortran.dg/non_lvalue_1.f90
@@ -0,0 +1,21 @@
+! { dg-do compile }
+! { dg-additional-options "-fdump-tree-original" }
+!
+! Check the generation of NON_LVALUE_EXPR trees in cases where a unary
operator expression
+! simplifies to a data reference.
+
+! A NON_LVALUE_EXPR is generated for a double negation that simplifies to a
data reference. */
+function f1 (f1_arg1)
+ integer, value :: f1_arg1
+ integer :: f1
+ f1 = -(-f1_arg1)
+end function
+! { dg-final { scan-tree-dump "__result_f1 = NON_LVALUE_EXPR ;"
"original" } }
+
+! A NON_LVALUE_EXPR is generated for a double complement that simplifies to a
data reference. */
+function f2 (f2_arg1)
+ integer, value :: f2_arg1
+ integer :: f2
+ f2 = not(not(f2_arg1))
+end function
+! { dg-final { scan-tree-dump "__result_f2 = NON_LVALUE_EXPR ;"
"original" } }
[gcc] Created branch 'mikael/heads/non_lvalue_match.pd_v01' in namespace 'refs/users'
The branch 'mikael/heads/non_lvalue_match.pd_v01' was created in namespace 'refs/users' pointing to: b3cc0b4da1b... match: Unwrap non-lvalue as unary or binary operand
[gcc(refs/users/mikael/heads/non_lvalue_match.pd_v01)] match: Unwrap non-lvalue as unary or binary operand
https://gcc.gnu.org/g:b3cc0b4da1b94e3b3c2895011ab8d19d1268c34b
commit b3cc0b4da1b94e3b3c2895011ab8d19d1268c34b
Author: Mikael Morin
Date: Thu Jul 4 15:24:36 2024 +0200
match: Unwrap non-lvalue as unary or binary operand
gcc/ChangeLog:
* match.pd: Unwrap NON_LVALUE_EXPR trees when they are used as
operand of a unary or binary operator.
gcc/testsuite/ChangeLog:
* gfortran.dg/non_lvalue_2.f90: New test.
Diff:
---
gcc/match.pd | 12
gcc/testsuite/gfortran.dg/non_lvalue_2.f90 | 44 ++
2 files changed, 56 insertions(+)
diff --git a/gcc/match.pd b/gcc/match.pd
index d0859545ada..513df562fd7 100644
--- a/gcc/match.pd
+++ b/gcc/match.pd
@@ -280,6 +280,18 @@ DEFINE_INT_AND_FLOAT_ROUND_FN (RINT)
(outer_op @0 @2)
@3))
+/* Remove superfluous NON_LVALUE_EXPR in unary operators. */
+(for op (UNCOND_UNARY)
+ (simplify (op (non_lvalue @0))
+ (op @0)))
+
+/* Remove superfluous NON_LVALUE_EXPR in binary operators. */
+(for op (UNCOND_BINARY tcc_comparison)
+ (simplify (op (non_lvalue @0) @1)
+ (op @0 @1))
+ (simplify (op @0 (non_lvalue @1))
+ (op @0 @1)))
+
/* Simplify x - x.
This is unsafe for certain floats even in non-IEEE formats.
In IEEE, it is unsafe because it does wrong for NaNs.
diff --git a/gcc/testsuite/gfortran.dg/non_lvalue_2.f90
b/gcc/testsuite/gfortran.dg/non_lvalue_2.f90
new file mode 100644
index 000..8c3197eab1f
--- /dev/null
+++ b/gcc/testsuite/gfortran.dg/non_lvalue_2.f90
@@ -0,0 +1,44 @@
+! { dg-do compile }
+! { dg-additional-options "-fdump-tree-original" }
+!
+! Check the removal of NON_LVALUE_EXPR if they are used in a non-lvalue context
+
+! The NON_LVALUE_EXPR is dropped if it's part (left operand) of a bigger
expression
+function f1 (f1_arg1, f1_arg2)
+ integer, value :: f1_arg1, f1_arg2
+ integer :: f1
+ f1 = (f1_arg1 + 0) + f1_arg2
+end function
+! { dg-final { scan-tree-dump "__result_f1 = f1_arg1 \\+ f1_arg2;" "original"
} }
+
+! The NON_LVALUE_EXPR is dropped if it's part (right operand) of a bigger
expression
+function f2 (f2_arg1, f2_arg2)
+ integer, value :: f2_arg1, f2_arg2
+ integer :: f2
+ f2 = f2_arg1 + (f2_arg2 + 0)
+end function
+! { dg-final { scan-tree-dump "__result_f2 = f2_arg1 \\+ f2_arg2;" "original"
} }
+
+! The NON_LVALUE_EXPR is dropped if it's part (left operand) of a binary
logical operator
+function f3 (f3_arg1)
+ integer, value :: f3_arg1
+ logical :: f3
+ f3 = (f3_arg1 + 0) > 0
+end function
+! { dg-final { scan-tree-dump "__result_f3 = f3_arg1 > 0;" "original" } }
+
+! The NON_LVALUE_EXPR is dropped if it's part (right operand) of a binary
logical operator
+function f4 (f4_arg1, f4_arg2)
+ integer, value :: f4_arg1, f4_arg2
+ logical :: f4
+ f4 = f4_arg1 > (f4_arg2 + 0)
+end function
+! { dg-final { scan-tree-dump "__result_f4 = f4_arg1 > f4_arg2;" "original" } }
+
+! The NON_LVALUE_EXPR is dropped if it's part of a unary operator
+function f5 (f5_arg1)
+ integer, value :: f5_arg1
+ integer :: f5
+ f5 = -(not(not(f5_arg1)))
+end function
+! { dg-final { scan-tree-dump "__result_f5 = -f5_arg1;" "original" } }
[gcc r15-1844] [committed][RISC-V] Fix test expectations after recent late-combine changes
https://gcc.gnu.org/g:b611f3969249967d7f098c6adfcf5f701192a2d0
commit r15-1844-gb611f3969249967d7f098c6adfcf5f701192a2d0
Author: Jeff Law
Date: Thu Jul 4 09:25:20 2024 -0600
[committed][RISC-V] Fix test expectations after recent late-combine changes
With the recent DCE related adjustment to late-combine the
rvv/base/vcreate.c
test no longer has those undesirable vmvNr statements.
It's a bit unclear why this wasn't written as a scan-assembler-not and
xfailed
given the comment says we don't want to see vmvNr insructions. I must have
missed that during review.
This patch adjusts the test to expect no vmvNr statements and if they're
ever
re-introduced, we'll get a nice unexpected failure.
gcc/testsuite
* gcc.target/riscv/rvv/base/vcreate.c: Update expected output.
Diff:
---
gcc/testsuite/gcc.target/riscv/rvv/base/vcreate.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vcreate.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/vcreate.c
index 01006de7c81..1c7c154637e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/vcreate.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vcreate.c
@@ -256,6 +256,6 @@ test_vcreate_v_i64m2x4 (vint64m2_t v0, vint64m2_t v1,
vint64m2_t v2,
}
// Ideally with O3, should find 0 instances of any vmvnr.v PR113913
-/* { dg-final { scan-assembler-times {vmv1r.v\s+v[0-9]+,\s*v[0-9]+} 72 } } */
-/* { dg-final { scan-assembler-times {vmv2r.v\s+v[0-9]+,\s*v[0-9]+} 36 } } */
-/* { dg-final { scan-assembler-times {vmv4r.v\s+v[0-9]+,\s*v[0-9]+} 16 } } */
+/* { dg-final { scan-assembler-not {vmv1r.v\s+v[0-9]+,\s*v[0-9]+} } } */
+/* { dg-final { scan-assembler-not {vmv2r.v\s+v[0-9]+,\s*v[0-9]+} } } */
+/* { dg-final { scan-assembler-not {vmv4r.v\s+v[0-9]+,\s*v[0-9]+} } } */
[gcc r15-1845] analyzer: handle at -O0 [PR115724]
https://gcc.gnu.org/g:a6fdb1a2a2906103afd70fa68cf7c45e896b8fbb
commit r15-1845-ga6fdb1a2a2906103afd70fa68cf7c45e896b8fbb
Author: David Malcolm
Date: Thu Jul 4 14:44:51 2024 -0400
analyzer: handle at -O0 [PR115724]
At -O0, glibc's:
__extern_always_inline void
error (int __status, int __errnum, const char *__format, ...)
{
if (__builtin_constant_p (__status) && __status != 0)
__error_noreturn (__status, __errnum, __format, __builtin_va_arg_pack
());
else
__error_alias (__status, __errnum, __format, __builtin_va_arg_pack ());
}
becomes just:
__extern_always_inline void
error (int __status, int __errnum, const char *__format, ...)
{
if (0)
__error_noreturn (__status, __errnum, __format, __builtin_va_arg_pack
());
else
__error_alias (__status, __errnum, __format, __builtin_va_arg_pack ());
}
and thus calls to "error" are calls to "__error_alias" by the
time -fanalyzer "sees" them.
Handle them with more special-casing in kf.cc.
gcc/analyzer/ChangeLog:
PR analyzer/115724
* kf.cc (register_known_functions): Add __error_alias and
__error_at_line_alias.
gcc/testsuite/ChangeLog:
PR analyzer/115724
* c-c++-common/analyzer/error-pr115724.c: New test.
Signed-off-by: David Malcolm
Diff:
---
gcc/analyzer/kf.cc | 4 +
.../c-c++-common/analyzer/error-pr115724.c | 86 ++
2 files changed, 90 insertions(+)
diff --git a/gcc/analyzer/kf.cc b/gcc/analyzer/kf.cc
index 4213b89ac9f..5c3a71fbb49 100644
--- a/gcc/analyzer/kf.cc
+++ b/gcc/analyzer/kf.cc
@@ -2325,6 +2325,10 @@ register_known_functions (known_function_manager &kfm,
kfm.add ("__errno_location", make_unique ());
kfm.add ("error", make_unique (3));
kfm.add ("error_at_line", make_unique (5));
+/* Variants of "error" and "error_at_line" seen by the
+ analyzer at -O0 (PR analyzer/115724). */
+kfm.add ("__error_alias", make_unique (3));
+kfm.add ("__error_at_line_alias", make_unique (5));
}
/* Other implementations of C standard library. */
diff --git a/gcc/testsuite/c-c++-common/analyzer/error-pr115724.c
b/gcc/testsuite/c-c++-common/analyzer/error-pr115724.c
new file mode 100644
index 000..ae606ad89d6
--- /dev/null
+++ b/gcc/testsuite/c-c++-common/analyzer/error-pr115724.c
@@ -0,0 +1,86 @@
+/* Verify that the analyzer handles the no-optimization case in
+ glibc's when error,error_at_line calls become
+ __error_alias and __error_at_line_alias. */
+
+typedef __SIZE_TYPE__ size_t;
+#define EXIT_FAILURE 1
+#define __extern_always_inline extern inline __attribute__
((__always_inline__)) __attribute__ ((__gnu_inline__))
+
+int errno;
+
+/* Adapted from glibc's bits/error.h. */
+
+extern void __error_alias (int __status, int __errnum,
+ const char *__format, ...)
+ __attribute__ ((__format__ (__printf__, 3, 4)));
+extern void __error_noreturn (int __status, int __errnum,
+ const char *__format, ...)
+ __attribute__ ((__noreturn__, __format__ (__printf__, 3, 4)));
+
+/* If we know the function will never return make sure the compiler
+ realizes that, too. */
+__extern_always_inline void
+error (int __status, int __errnum, const char *__format, ...)
+{
+ if (__builtin_constant_p (__status) && __status != 0)
+__error_noreturn (__status, __errnum, __format, __builtin_va_arg_pack ());
+ else
+__error_alias (__status, __errnum, __format, __builtin_va_arg_pack ());
+}
+
+extern void __error_at_line_alias (int __status, int __errnum,
+ const char *__fname,
+ unsigned int __line,
+ const char *__format, ...)
+ __attribute__ ((__format__ (__printf__, 5, 6)));
+extern void __error_at_line_noreturn (int __status, int __errnum,
+ const char *__fname,
+ unsigned int __line,
+ const char *__format,
+ ...)
+ __attribute__ ((__noreturn__, __format__ (__printf__, 5, 6)));
+
+/* If we know the function will never return make sure the compiler
+ realizes that, too. */
+__extern_always_inline void
+error_at_line (int __status, int __errnum, const char *__fname,
+ unsigned int __line, const char *__format, ...)
+{
+ if (__builtin_constant_p (__status) && __status != 0)
+__error_at_line_noreturn (__status, __errnum, __fname, __line, __format,
+ __builtin_va_arg_pack ());
+ else
+__error_at_line_alias (__status, __errnum, __fname, __line,
+ __format, __builtin_va_arg_pack ());
+}
+
+
+struct list {
+size_t size;
+void (*destroy)(void *data);
+
gcc-cvs@gcc.gnu.org
https://gcc.gnu.org/g:f8c130cdf531653e5c041d247729851419bc7bde commit r15-1846-gf8c130cdf531653e5c041d247729851419bc7bde Author: David Malcolm Date: Thu Jul 4 14:44:51 2024 -0400 analyzer: convert sm_context * to sm_context & These are never nullptr and never change, so use a reference rather than a pointer. No functional change intended. gcc/analyzer/ChangeLog: * diagnostic-manager.cc (diagnostic_manager::add_events_for_eedge): Pass sm_ctxt by reference. * engine.cc (impl_region_model_context::on_condition): Likewise. (impl_region_model_context::on_bounded_ranges): Likewise. (impl_region_model_context::on_phi): Likewise. (exploded_node::on_stmt): Likewise. * sm-fd.cc: Update all uses of sm_context * to sm_context &. * sm-file.cc: Likewise. * sm-malloc.cc: Likewise. * sm-pattern-test.cc: Likewise. * sm-sensitive.cc: Likewise. * sm-signal.cc: Likewise. * sm-taint.cc: Likewise. * sm.h: Likewise. * varargs.cc: Likewise. gcc/testsuite/ChangeLog: * gcc.dg/plugin/analyzer_gil_plugin.c: Update all uses of sm_context * to sm_context &. Signed-off-by: David Malcolm Diff: --- gcc/analyzer/diagnostic-manager.cc| 2 +- gcc/analyzer/engine.cc| 8 +- gcc/analyzer/sm-fd.cc | 318 +++--- gcc/analyzer/sm-file.cc | 38 +-- gcc/analyzer/sm-malloc.cc | 194 ++--- gcc/analyzer/sm-pattern-test.cc | 14 +- gcc/analyzer/sm-sensitive.cc | 22 +- gcc/analyzer/sm-signal.cc | 20 +- gcc/analyzer/sm-taint.cc | 122 - gcc/analyzer/sm.h | 8 +- gcc/analyzer/varargs.cc | 54 ++-- gcc/testsuite/gcc.dg/plugin/analyzer_gil_plugin.c | 46 ++-- 12 files changed, 419 insertions(+), 427 deletions(-) diff --git a/gcc/analyzer/diagnostic-manager.cc b/gcc/analyzer/diagnostic-manager.cc index 20e793d72c1..fe943ac61c9 100644 --- a/gcc/analyzer/diagnostic-manager.cc +++ b/gcc/analyzer/diagnostic-manager.cc @@ -2239,7 +2239,7 @@ diagnostic_manager::add_events_for_eedge (const path_builder &pb, &iter_point, emission_path, pb.get_ext_state ()); - sm.on_stmt (&sm_ctxt, dst_point.get_supernode (), stmt); + sm.on_stmt (sm_ctxt, dst_point.get_supernode (), stmt); // TODO: what about phi nodes? } } diff --git a/gcc/analyzer/engine.cc b/gcc/analyzer/engine.cc index f5fad5b2e47..c9f204b13e7 100644 --- a/gcc/analyzer/engine.cc +++ b/gcc/analyzer/engine.cc @@ -969,7 +969,7 @@ impl_region_model_context::on_condition (const svalue *lhs, m_old_state->m_checker_states[sm_idx], m_new_state->m_checker_states[sm_idx], m_path_ctxt); - sm.on_condition (&sm_ctxt, + sm.on_condition (sm_ctxt, (m_enode_for_diag ? m_enode_for_diag->get_supernode () : NULL), @@ -996,7 +996,7 @@ impl_region_model_context::on_bounded_ranges (const svalue &sval, m_old_state->m_checker_states[sm_idx], m_new_state->m_checker_states[sm_idx], m_path_ctxt); - sm.on_bounded_ranges (&sm_ctxt, + sm.on_bounded_ranges (sm_ctxt, (m_enode_for_diag ? m_enode_for_diag->get_supernode () : NULL), @@ -1037,7 +1037,7 @@ impl_region_model_context::on_phi (const gphi *phi, tree rhs) m_old_state->m_checker_states[sm_idx], m_new_state->m_checker_states[sm_idx], m_path_ctxt); - sm.on_phi (&sm_ctxt, m_enode_for_diag->get_supernode (), phi, rhs); + sm.on_phi (sm_ctxt, m_enode_for_diag->get_supernode (), phi, rhs); } } @@ -1559,7 +1559,7 @@ exploded_node::on_stmt (exploded_graph &eg, unknown_side_effects); /* Allow the state_machine to handle the stmt. */ - if (sm.on_stmt (&sm_ctxt, snode, stmt)) + if (sm.on_stmt (sm_ctxt, snode, stmt)) unknown_side_effects = false; } diff --git a/gcc/analyzer/sm-fd.cc b/gcc/analyzer/sm-fd.cc index ded20576fd1..3396b1d1122 100644 --- a/gcc/analyzer/sm-fd.cc +++ b/gcc/analyzer/sm-fd.cc @@ -119,
[gcc r15-1848] Support group size of three in SLP store permute lowering
https://gcc.gnu.org/g:7eb8b65780d9dc3e266056383279b00d5e152bea
commit r15-1848-g7eb8b65780d9dc3e266056383279b00d5e152bea
Author: Richard Biener
Date: Wed Jul 3 13:50:59 2024 +0200
Support group size of three in SLP store permute lowering
The following implements the group-size three scheme from
vect_permute_store_chain in SLP grouped store permute lowering
and extends it to power-of-two multiples of group size three.
The scheme goes from vectors A, B and C to
{ A[0], B[0], C[0], A[1], B[1], C[1], ... } by first producing
{ A[0], B[0], X, A[1], B[1], X, ... } (with X random but chosen
to A[n]) and then permuting in C[n] in the appropriate places.
The extension goes as to replace vector elements with a
power-of-two number of lanes and you'd get pairwise interleaving
until the final three input permutes happen.
The last permute step could be seen as extending C to { C[0], C[0],
C[0], ... } and then performing a blend.
VLA archs will want to use store-lanes here I guess, I'm not sure
if the three vector interleave operation is also available with
a register source and destination and thus available for a shuffle.
* tree-vect-slp.cc (vect_build_slp_instance): Special case
three input permute with the same number of lanes in store
permute lowering.
* gcc.dg/vect/slp-53.c: New testcase.
* gcc.dg/vect/slp-54.c: New testcase.
Diff:
---
gcc/testsuite/gcc.dg/vect/slp-53.c | 15 +
gcc/testsuite/gcc.dg/vect/slp-54.c | 18 +++
gcc/tree-vect-slp.cc | 65 +-
3 files changed, 97 insertions(+), 1 deletion(-)
diff --git a/gcc/testsuite/gcc.dg/vect/slp-53.c
b/gcc/testsuite/gcc.dg/vect/slp-53.c
new file mode 100644
index 000..d8cd5f85b3c
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/vect/slp-53.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+
+void foo (int * __restrict x, int *y)
+{
+ x = __builtin_assume_aligned (x, __BIGGEST_ALIGNMENT__);
+ y = __builtin_assume_aligned (y, __BIGGEST_ALIGNMENT__);
+ for (int i = 0; i < 1024; ++i)
+{
+ x[3*i+0] = y[2*i+0] * 7 + 5;
+ x[3*i+1] = y[2*i+1] * 2;
+ x[3*i+2] = y[2*i+0] + 3;
+}
+}
+
+/* { dg-final { scan-tree-dump "vectorizing stmts using SLP" "vect" { target {
vect_int && vect_int_mult } xfail vect_load_lanes } } } */
diff --git a/gcc/testsuite/gcc.dg/vect/slp-54.c
b/gcc/testsuite/gcc.dg/vect/slp-54.c
new file mode 100644
index 000..ab66b349d1f
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/vect/slp-54.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+
+void foo (int * __restrict x, int *y)
+{
+ x = __builtin_assume_aligned (x, __BIGGEST_ALIGNMENT__);
+ y = __builtin_assume_aligned (y, __BIGGEST_ALIGNMENT__);
+ for (int i = 0; i < 1024; ++i)
+{
+ x[6*i+0] = y[4*i+0] * 7 + 5;
+ x[6*i+1] = y[4*i+1] * 2;
+ x[6*i+2] = y[4*i+2] + 3;
+ x[6*i+3] = y[4*i+3] * 7 + 5;
+ x[6*i+4] = y[4*i+0] * 2;
+ x[6*i+5] = y[4*i+3] + 3;
+}
+}
+
+/* { dg-final { scan-tree-dump "vectorizing stmts using SLP" "vect" { target {
vect_int && vect_int_mult } xfail riscv*-*-* } } } */
diff --git a/gcc/tree-vect-slp.cc b/gcc/tree-vect-slp.cc
index a8bb08ea7be..d0a8531fd3b 100644
--- a/gcc/tree-vect-slp.cc
+++ b/gcc/tree-vect-slp.cc
@@ -3697,6 +3697,69 @@ vect_build_slp_instance (vec_info *vinfo,
most two vector inputs to produce a single vector output. */
while (SLP_TREE_CHILDREN (perm).length () > 2)
{
+ /* When we have three equal sized groups left the pairwise
+reduction does not result in a scheme that avoids using
+three vectors. Instead merge the first two groups
+to the final size with do-not-care elements (chosen
+from the first group) and then merge with the third.
+ { A0, B0, x, A1, B1, x, ... }
+ -> { A0, B0, C0, A1, B1, C1, ... }
+This handles group size of three (and at least
+power-of-two multiples of that). */
+ if (SLP_TREE_CHILDREN (perm).length () == 3
+ && (SLP_TREE_LANES (SLP_TREE_CHILDREN (perm)[0])
+ == SLP_TREE_LANES (SLP_TREE_CHILDREN (perm)[1]))
+ && (SLP_TREE_LANES (SLP_TREE_CHILDREN (perm)[0])
+ == SLP_TREE_LANES (SLP_TREE_CHILDREN (perm)[2])))
+ {
+ int ai = 0;
+ int bi = 1;
+ slp_tree a = SLP_TREE_CHILDREN (perm)[ai];
+ slp_tree b = SLP_TREE_CHILDREN (perm)[bi];
+ unsigned n = SLP_TREE_LANES (perm);
+
+ slp_tree permab
+ = vect_create_new_slp_node (2, VEC_PERM_EXPR);
+ SLP_TREE_LANES (
