[gcc r14-10366] c: Fix ICE related to incomplete structures in C23 [PR114930]
https://gcc.gnu.org/g:37bbd2c1667c70387f5fa6b52f461d57a204229d
commit r14-10366-g37bbd2c1667c70387f5fa6b52f461d57a204229d
Author: Jakub Jelinek
Date: Tue Jun 25 08:35:56 2024 +0200
c: Fix ICE related to incomplete structures in C23 [PR114930]
Here is a version of the c_update_type_canonical fixes which passed
bootstrap/regtest.
The non-trivial part is the handling of the case when
build_qualified_type (TYPE_CANONICAL (t), TYPE_QUALS (x))
returns a type with NULL TYPE_CANONICAL. That should happen only
if TYPE_CANONICAL (t) == t, because otherwise c_update_type_canonical should
have been already called on the other type. c, the returned type, is
usually x
and in that case it should have TYPE_CANONICAL set to itself, or worst
for whatever reason x is not the right canonical type (say it has attributes
or whatever disqualifies it from check_qualified_type). In that case
either it finds some pre-existing type from the variant chain of t which
is later in the chain and we haven't processed it yet (but then
get_qualified_type moves it right after t in:
/* Put the found variant at the head of the variant list so
frequently searched variants get found faster. The C++ FE
benefits greatly from this. */
tree t = *tp;
*tp = TYPE_NEXT_VARIANT (t);
TYPE_NEXT_VARIANT (t) = TYPE_NEXT_VARIANT (mv);
TYPE_NEXT_VARIANT (mv) = t;
return t;
optimization), or creates a fresh new type using build_variant_type_copy,
which again places the new type right after t:
/* Add the new type to the chain of variants of TYPE. */
TYPE_NEXT_VARIANT (t) = TYPE_NEXT_VARIANT (m);
TYPE_NEXT_VARIANT (m) = t;
TYPE_MAIN_VARIANT (t) = m;
At this point we want to make c its own canonical type (i.e. TYPE_CANONICAL
(c) = c;), but also need to process pointers to it and only then return back
to processing x. Processing the whole chain from c again could be costly,
we could have hundreds of types in the chain already processed, and while
the loop would just quickly skip them
for (tree x = t, l = NULL_TREE; x; l = x, x = TYPE_NEXT_VARIANT (x))
{
if (x != t && TYPE_STRUCTURAL_EQUALITY_P (x))
...
else if (x != t)
continue;
it feels costly. So, this patch instead moves c from right after t
to right before x in the chain (that shouldn't change anything, because
clearly build_qualified_type didn't find any matches in the chain before
x) and continues processing the c at that position, so should handle the
x that encountered this in the next iteration.
We could avoid some of the moving in the chain if we processed the chain
twice, once deal only with x != t && TYPE_STRUCTURAL_EQUALITY_P (x)
&& TYPE_CANONICAL (t) == t && check_qualified_type (t, x, TYPE_QUALS (x))
types (in that case set TYPE_CANONICAL (x) = x) and once the rest. There
is still the theoretical case where build_qualified_type would return
a new type and in that case we are back to the moving the type around and
needing to handle it though.
2024-06-25 Jakub Jelinek
Martin Uecker
PR c/114930
PR c/115502
gcc/c/
* c-decl.cc (c_update_type_canonical): Assert t is main variant
with 0 TYPE_QUALS. Simplify and don't use check_qualified_type.
Deal with the case where build_qualified_type returns
TYPE_STRUCTURAL_EQUALITY_P type.
gcc/testsuite/
* gcc.dg/pr114574-1.c: Require lto effective target.
* gcc.dg/pr114574-2.c: Likewise.
* gcc.dg/pr114930.c: New test.
* gcc.dg/pr115502.c: New test.
(cherry picked from commit 777cc6a01d1cf783a36d0fa67ab20f0312f35d7a)
Diff:
---
gcc/c/c-decl.cc | 38 +++---
gcc/testsuite/gcc.dg/pr114574-1.c | 6 +++---
gcc/testsuite/gcc.dg/pr114574-2.c | 6 +++---
gcc/testsuite/gcc.dg/pr114930.c | 9 +
gcc/testsuite/gcc.dg/pr115502.c | 9 +
5 files changed, 55 insertions(+), 13 deletions(-)
diff --git a/gcc/c/c-decl.cc b/gcc/c/c-decl.cc
index e63dab49589..0e52f217618 100644
--- a/gcc/c/c-decl.cc
+++ b/gcc/c/c-decl.cc
@@ -9363,18 +9363,42 @@ is_flexible_array_member_p (bool is_last_field,
static void
c_update_type_canonical (tree t)
{
- for (tree x = TYPE_MAIN_VARIANT (t); x; x = TYPE_NEXT_VARIANT (x))
+ gcc_checking_assert (TYPE_MAIN_VARIANT (t) == t && !TYPE_QUALS (t));
+ for (tree x = t, l = NULL_TREE; x; l = x, x = TYPE_NEXT_VARIANT (x))
{
if (x != t && TYPE_STRUCTURAL_EQUALITY_P (x))
{
- if (TYPE_QUALS (x) == TYPE_QUALS (t))
+ if (!TYPE_QUALS (x))
TYPE_CANONICAL (x) = TYPE_CANONICAL (t);
- else if (TYPE_CANONICAL (t) != t
- || check_q
[gcc r15-1744] [MAINTAINERS] Update my email address
https://gcc.gnu.org/g:382e2123c402edb6123f0c4669fa298d4140edd8 commit r15-1744-g382e2123c402edb6123f0c4669fa298d4140edd8 Author: Claudiu Zissulescu Date: Mon Jul 1 10:49:29 2024 +0300 [MAINTAINERS] Update my email address Update my email address. ChangeLog: * MAINTAINERS: Update claziss email address. Signed-off-by: Claudiu Zissulescu Diff: --- MAINTAINERS | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index 41319595bb5..ddeea7b497f 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -56,7 +56,7 @@ aarch64 port Kyrylo Tkachov alpha port Richard Henderson amdgcn portJulian Brown amdgcn portAndrew Stubbs -arc port Claudiu Zissulescu +arc port Claudiu Zissulescu arm port Nick Clifton arm port Richard Earnshaw arm port Ramana Radhakrishnan @@ -267,7 +267,6 @@ check in changes outside of the parts of the compiler they maintain. Reviewers -arc port Claudiu Zissulescu callgraph Martin Jambor C front endMarek Polacek CTF, BTF Indu Bhagat
[gcc/redhat/heads/gcc-14-branch] (37 commits) Merge commit 'r14-10366-g37bbd2c1667c70387f5fa6b52f461d57a2
The branch 'redhat/heads/gcc-14-branch' was updated to point to: 6eada54ba86... Merge commit 'r14-10366-g37bbd2c1667c70387f5fa6b52f461d57a2 It previously pointed to: 640bb0fa76a... Merge commit 'r14-10330-gd26fa1c73b2c0f7fd2d412ce7b4e84e0f7 Diff: Summary of changes (added commits): --- 6eada54... Merge commit 'r14-10366-g37bbd2c1667c70387f5fa6b52f461d57a2 37bbd2c... c: Fix ICE related to incomplete structures in C23 [PR11493 (*) 78bd4b1... Daily bump. (*) 603b344... Fortran: fix ALLOCATE with SOURCE of deferred character len (*) 9f14748... Fortran: fix passing of optional dummy as actual to optiona (*) b31e190... Fortran: fix for CHARACTER(len=*) dummies with bind(C) [PR1 (*) 4fe3fff... Daily bump. (*) 47cbc76... Daily bump. (*) e6b115b... c++: decltype of capture proxy of ref [PR115504] (*) a00a8d4... c++: alias CTAD and copy deduction guide [PR115198] (*) 33a9c4d... c++: using non-dep array var of unknown bound [PR115358] (*) d5e352a... libstdc++: Fix std::format for chrono::duration with unsign (*) ef8b60d... rs6000: Fix wrong RTL patterns for vector merge high/low wo (*) 15d304d... Daily bump. (*) a8b77a6... libstdc++: Replace viewcvs links in docs with cgit links (*) b70af0b... [libstdc++] [testsuite] defer to check_vect_support* [PR115 (*) c2878a9... aarch64: Add support for -mcpu=grace (*) 6e6f10c... tree-ssa-pre.c/115214(ICE in find_or_generate_expression, a (*) f9cc628... Daily bump. (*) 532357b... Daily bump. (*) f91d9b3... libstdc++: Remove confusing text from status tables for rel (*) b383719... Fix PR c/115587, uninitialized variable in c_parser_omp_loo (*) 4bf93fc... SPARC: fix internal error with -mv8plus on 64-bit Linux (*) b7157f3... c-family: Add Warning property to Wnrvo option [PR115624] (*) faf5994... Daily bump. (*) 2b5e8f9... rs6000: Don't clobber return value when eh_return called [P (*) 1a2329d... Daily bump. (*) 1735b86... Daily bump. (*) 70d9d92... Daily bump. (*) 9421f02... AArch64: Fix cpu features initialization [PR115342] (*) a851931... libstdc++: Fix test on x86_64 and non-simd targets (*) a16f47f... Build: Set gcc_cv_as_mips_explicit_relocs if gcc_cv_as_mips (*) 272e8c9... tree-optimization/115278 - fix DSE in if-conversion wrt vol (*) 65e2586... tree-optimization/115508 - fix ICE with SLP scheduling and (*) 85d32e6... Avoid SLP_REPRESENTATIVE access for VEC_PERM in SLP schedul (*) 30fca2c... Daily bump. (*) e77f314... libstdc++: Fix find_last_set(simd_mask) to ignore padding b (*) (*) This commit already exists in another branch. Because the reference `refs/vendors/redhat/heads/gcc-14-branch' matches your hooks.email-new-commits-only configuration, no separate email is sent for this commit.
[gcc(refs/vendors/redhat/heads/gcc-14-branch)] Merge commit 'r14-10366-g37bbd2c1667c70387f5fa6b52f461d57a204229d' into redhat/gcc-14-branch
https://gcc.gnu.org/g:6eada54ba865eeb9aabfcfbc106c3fbff7abe98a commit 6eada54ba865eeb9aabfcfbc106c3fbff7abe98a Merge: 640bb0fa76a 37bbd2c1667 Author: Jakub Jelinek Date: Mon Jul 1 10:20:55 2024 +0200 Merge commit 'r14-10366-g37bbd2c1667c70387f5fa6b52f461d57a204229d' into redhat/gcc-14-branch Diff: gcc/ChangeLog | 134 +++ gcc/DATESTAMP | 2 +- gcc/c-family/ChangeLog | 8 + gcc/c-family/c.opt | 2 +- gcc/c/ChangeLog| 9 + gcc/c/c-decl.cc| 38 - gcc/c/c-parser.cc | 4 +- gcc/config/aarch64/aarch64-cores.def | 2 + gcc/config/aarch64/aarch64-tune.md | 2 +- gcc/config/rs6000/altivec.md | 80 ++--- gcc/config/rs6000/rs6000-logue.cc | 7 +- gcc/config/rs6000/rs6000.cc| 8 +- gcc/config/rs6000/rs6000.md| 15 ++ gcc/config/rs6000/vsx.md | 28 ++-- gcc/config/sparc/linux64.h | 2 +- gcc/configure | 2 + gcc/configure.ac | 2 + gcc/cp/ChangeLog | 39 + gcc/cp/decl2.cc| 2 + gcc/cp/parser.cc | 8 +- gcc/cp/pt.cc | 6 +- gcc/cp/semantics.cc| 8 - gcc/cp/typeck.cc | 7 - gcc/doc/invoke.texi| 4 +- gcc/fortran/ChangeLog | 31 gcc/fortran/trans-array.cc | 20 ++- gcc/fortran/trans-decl.cc | 4 +- gcc/fortran/trans-stmt.cc | 5 +- gcc/testsuite/ChangeLog| 125 ++ gcc/testsuite/g++.dg/cpp1y/decltype-auto8.C| 22 +++ .../g++.dg/cpp2a/class-deduction-alias22.C | 14 ++ gcc/testsuite/g++.dg/template/array37.C| 14 ++ gcc/testsuite/g++.dg/vect/pr115278.cc | 38 + gcc/testsuite/g++.target/powerpc/pr106069.C| 119 ++ gcc/testsuite/gcc.dg/pr114574-1.c | 6 +- gcc/testsuite/gcc.dg/pr114574-2.c | 6 +- gcc/testsuite/gcc.dg/pr114930.c| 9 + gcc/testsuite/gcc.dg/pr115502.c| 9 + gcc/testsuite/gcc.target/i386/pr115508.c | 15 ++ gcc/testsuite/gcc.target/powerpc/pr114846.c| 20 +++ gcc/testsuite/gcc.target/powerpc/pr115355.c| 37 + .../gcc.target/riscv/rvv/vsetvl/pr115214.c | 52 ++ .../gfortran.dg/allocate_with_source_33.f90| 69 gcc/testsuite/gfortran.dg/bind_c_char_11.f90 | 45 + gcc/testsuite/gfortran.dg/optional_absent_12.f90 | 30 gcc/tree-if-conv.cc| 4 +- gcc/tree-ssa-pre.cc| 10 +- gcc/tree-vect-slp.cc | 29 ++-- libgcc/ChangeLog | 13 ++ libgcc/config/aarch64/cpuinfo.c| 181 + libstdc++-v3/ChangeLog | 65 libstdc++-v3/doc/html/faq.html | 2 +- libstdc++-v3/doc/html/manual/memory.html | 10 +- .../doc/html/manual/mt_allocator_impl.html | 6 +- libstdc++-v3/doc/html/manual/status.html | 16 +- libstdc++-v3/doc/xml/faq.xml | 2 +- libstdc++-v3/doc/xml/manual/allocator.xml | 10 +- libstdc++-v3/doc/xml/manual/mt_allocator.xml | 6 +- libstdc++-v3/doc/xml/manual/status_cxx1998.xml | 2 +- libstdc++-v3/doc/xml/manual/status_cxx2011.xml | 2 +- libstdc++-v3/doc/xml/manual/status_cxx2014.xml | 2 +- libstdc++-v3/doc/xml/manual/status_cxx2017.xml | 2 +- libstdc++-v3/doc/xml/manual/status_cxx2020.xml | 2 +- libstdc++-v3/doc/xml/manual/status_cxx2023.xml | 2 +- libstdc++-v3/doc/xml/manual/status_cxxtr1.xml | 2 +- libstdc++-v3/doc/xml/manual/status_cxxtr24733.xml | 2 +- libstdc++-v3/include/bits/chrono_io.h | 5 +- libstdc++-v3/include/experimental/bits/simd_x86.h | 26 +-- libstdc++-v3/testsuite/20_util/duration/io.cc | 6 + .../experimental/simd/pr115454_find_last_set.cc| 50 ++ 70 files changed, 1301 insertions(+), 265 deletions(-)
[gcc r15-1745] tree-optimization/115723 - ICE with .COND_ADD reduction
https://gcc.gnu.org/g:286cda3461d6f5ce7d911d3f26bd4975ea7ea11d
commit r15-1745-g286cda3461d6f5ce7d911d3f26bd4975ea7ea11d
Author: Richard Biener
Date: Mon Jul 1 10:06:55 2024 +0200
tree-optimization/115723 - ICE with .COND_ADD reduction
The following fixes an ICE with a .COND_ADD discovered as reduction
even though its else value isn't the reduction chain link but a
constant. This would be wrong-code with --disable-checking I think.
PR tree-optimization/115723
* tree-vect-loop.cc (check_reduction_path): For a .COND_ADD
verify the else value also refers to the reduction chain op.
* gcc.dg/vect/pr115723.c: New testcase.
Diff:
---
gcc/testsuite/gcc.dg/vect/pr115723.c | 25 +
gcc/tree-vect-loop.cc| 12
2 files changed, 33 insertions(+), 4 deletions(-)
diff --git a/gcc/testsuite/gcc.dg/vect/pr115723.c
b/gcc/testsuite/gcc.dg/vect/pr115723.c
new file mode 100644
index 000..b98b29d4870
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/vect/pr115723.c
@@ -0,0 +1,25 @@
+/* { dg-additional-options "-ffast-math -fno-unsafe-math-optimizations" } */
+
+#include "tree-vect.h"
+
+double __attribute__((noipa))
+foo (double *x, double *y, int n)
+{
+ double res = 0.;
+ for (int i = 0; i < n; ++i)
+if (y[i] > 0.)
+ res += x[i];
+else
+ res = 64.;
+ return res;
+}
+
+double y[16] = { 1., 1., 1., 1., 0., 1., 1., 1.,
+ 1., 1., 1., 1., 1., 1., 1., 1. };
+int main ()
+{
+ check_vect ();
+ if (foo (y, y, 16) != 64. + 11.)
+abort ();
+ return 0;
+}
diff --git a/gcc/tree-vect-loop.cc b/gcc/tree-vect-loop.cc
index 3095ff5ab6b..a64b5082bd1 100644
--- a/gcc/tree-vect-loop.cc
+++ b/gcc/tree-vect-loop.cc
@@ -4163,15 +4163,19 @@ pop:
FOR_EACH_IMM_USE_STMT (op_use_stmt, imm_iter, op.ops[opi])
{
- /* In case of a COND_OP (mask, op1, op2, op1) reduction we might have
- op1 twice (once as definition, once as else) in the same operation.
- Allow this. */
+ /* In case of a COND_OP (mask, op1, op2, op1) reduction we should
+have op1 twice (once as definition, once as else) in the same
+operation. Enforce this. */
if (cond_fn_p && op_use_stmt == use_stmt)
{
gcall *call = as_a (use_stmt);
unsigned else_pos
= internal_fn_else_index (internal_fn (op.code));
-
+ if (gimple_call_arg (call, else_pos) != op.ops[opi])
+ {
+ fail = true;
+ break;
+ }
for (unsigned int j = 0; j < gimple_call_num_args (call); ++j)
{
if (j == else_pos)
[gcc r15-1746] libffi: Fix 32-bit SPARC structure passing [PR115681]
https://gcc.gnu.org/g:61aa380bad45fb070379f259f7abc5e5f50c9009
commit r15-1746-g61aa380bad45fb070379f259f7abc5e5f50c9009
Author: Rainer Orth
Date: Mon Jul 1 11:20:15 2024 +0200
libffi: Fix 32-bit SPARC structure passing [PR115681]
The libffi.closures/single_entry_structs2.c test FAILs on 32-bit SPARC:
FAIL: libffi.closures/single_entry_structs2.c -W -Wall -Wno-psabi -O0
execution test
The issue has been reported, analyzed and fixed upstream:
Several tests FAIL on 32-bit Solaris/SPARC
https://github.com/libffi/libffi/issues/841
Therefore this patch imports the fix into the GCC tree.
Tested on sparc-sun-solaris2.11.
2024-07-01 Rainer Orth
libffi:
PR libffi/115681
* src/sparc/ffi.c (ffi_call_int): Copy structure arguments to
maintain call-by-value semantics.
Diff:
---
libffi/src/sparc/ffi.c | 16
1 file changed, 16 insertions(+)
diff --git a/libffi/src/sparc/ffi.c b/libffi/src/sparc/ffi.c
index 9e406d0af67..cf819ee6738 100644
--- a/libffi/src/sparc/ffi.c
+++ b/libffi/src/sparc/ffi.c
@@ -286,6 +286,8 @@ ffi_call_int (ffi_cif *cif, void (*fn)(void), void *rvalue,
void **avalue, void *closure)
{
size_t bytes = cif->bytes;
+ size_t i, nargs = cif->nargs;
+ ffi_type **arg_types = cif->arg_types;
FFI_ASSERT (cif->abi == FFI_V8);
@@ -295,6 +297,20 @@ ffi_call_int (ffi_cif *cif, void (*fn)(void), void *rvalue,
&& (cif->flags & SPARC_FLAG_RET_MASK) == SPARC_RET_STRUCT)
bytes += FFI_ALIGN (cif->rtype->size, 8);
+ /* If we have any structure arguments, make a copy so we are passing
+ by value. */
+ for (i = 0; i < nargs; i++)
+{
+ ffi_type *at = arg_types[i];
+ int size = at->size;
+ if (at->type == FFI_TYPE_STRUCT)
+{
+ char *argcopy = alloca (size);
+ memcpy (argcopy, avalue[i], size);
+ avalue[i] = argcopy;
+}
+}
+
ffi_call_v8(cif, fn, rvalue, avalue, -bytes, closure);
}
[gcc r15-1747] libgomp: change alloc-pinned tests failure mode
https://gcc.gnu.org/g:90efaebf95c93244f6b1eda5cb8724e52047cecd
commit r15-1747-g90efaebf95c93244f6b1eda5cb8724e52047cecd
Author: Andrew Stubbs
Date: Wed Jun 12 08:43:53 2024 +
libgomp: change alloc-pinned tests failure mode
The feature doesn't work on non-Linux hosts, at present, so skip the tests
entirely.
On Linux systems that have insufficient lockable memory configured we still
need to fail or else the feature won't be getting tested when we think it
is,
but now there's a message to explain why.
libgomp/ChangeLog:
* testsuite/libgomp.c/alloc-pinned-1.c: Change dg-xfail-run-if to
dg-skip-if.
Correct spelling mistake.
Abort on insufficient lockable memory.
Use #error on non-linux hosts.
* testsuite/libgomp.c/alloc-pinned-2.c: Likewise.
Diff:
---
libgomp/testsuite/libgomp.c/alloc-pinned-1.c | 20 ++--
libgomp/testsuite/libgomp.c/alloc-pinned-2.c | 20 ++--
2 files changed, 12 insertions(+), 28 deletions(-)
diff --git a/libgomp/testsuite/libgomp.c/alloc-pinned-1.c
b/libgomp/testsuite/libgomp.c/alloc-pinned-1.c
index 4185accf2e6..672f2453a78 100644
--- a/libgomp/testsuite/libgomp.c/alloc-pinned-1.c
+++ b/libgomp/testsuite/libgomp.c/alloc-pinned-1.c
@@ -1,6 +1,6 @@
/* { dg-do run } */
-/* { dg-xfail-run-if "Pinning not implemented on this host" { ! *-*-linux-gnu
} } */
+/* { dg-skip-if "Pinning not implemented on this host" { ! *-*-linux-gnu* } }
*/
/* Test that pinned memory works. */
@@ -19,7 +19,10 @@
struct rlimit limit; \
if (getrlimit (RLIMIT_MEMLOCK, &limit) \
|| limit.rlim_cur <= SIZE) \
-fprintf (stderr, "unsufficient lockable memory; please increase
ulimit\n"); \
+{ \
+ fprintf (stderr, "insufficient lockable memory; please increase
ulimit\n"); \
+ abort (); \
+} \
}
int
@@ -44,18 +47,7 @@ get_pinned_mem ()
abort ();
}
#else
-#define PAGE_SIZE 1024 /* unknown */
-#define CHECK_SIZE(SIZE) { \
- fprintf (stderr, "OS unsupported\n"); \
- abort (); \
- }
-#define EXPECT_OMP_NULL_ALLOCATOR
-
-int
-get_pinned_mem ()
-{
- return 0;
-}
+#error "OS unsupported"
#endif
static void
diff --git a/libgomp/testsuite/libgomp.c/alloc-pinned-2.c
b/libgomp/testsuite/libgomp.c/alloc-pinned-2.c
index 0b9c11d0315..b6d1d83fb6f 100644
--- a/libgomp/testsuite/libgomp.c/alloc-pinned-2.c
+++ b/libgomp/testsuite/libgomp.c/alloc-pinned-2.c
@@ -1,6 +1,6 @@
/* { dg-do run } */
-/* { dg-xfail-run-if "Pinning not implemented on this host" { ! *-*-linux-gnu
} } */
+/* { dg-skip-if "Pinning not implemented on this host" { ! *-*-linux-gnu* } }
*/
/* Test that pinned memory works (pool_size code path). */
@@ -19,7 +19,10 @@
struct rlimit limit; \
if (getrlimit (RLIMIT_MEMLOCK, &limit) \
|| limit.rlim_cur <= SIZE) \
-fprintf (stderr, "unsufficient lockable memory; please increase
ulimit\n"); \
+{ \
+ fprintf (stderr, "insufficient lockable memory; please increase
ulimit\n"); \
+ abort (); \
+} \
}
int
@@ -44,18 +47,7 @@ get_pinned_mem ()
abort ();
}
#else
-#define PAGE_SIZE 1024 /* unknown */
-#define CHECK_SIZE(SIZE) { \
- fprintf (stderr, "OS unsupported\n"); \
- abort (); \
- }
-#define EXPECT_OMP_NULL_ALLOCATOR
-
-int
-get_pinned_mem ()
-{
- return 0;
-}
+#error "OS unsupported"
#endif
static void
[gcc r15-1748] libgomp, openmp: Add ompx_gnu_pinned_mem_alloc
https://gcc.gnu.org/g:64001441ec99b80e457188ce50bb6c59c757d3c6
commit r15-1748-g64001441ec99b80e457188ce50bb6c59c757d3c6
Author: Andrew Stubbs
Date: Wed Jun 12 11:09:33 2024 +
libgomp, openmp: Add ompx_gnu_pinned_mem_alloc
This creates a new predefined allocator as a shortcut for using pinned
memory with OpenMP. This is not in the OpenMP standard so it uses the
"ompx"
namespace and an independent enum baseline of 200 (selected to not clash
with
other known implementations).
The allocator is equivalent to using a custom allocator with the pinned
trait and the null fallback trait. One motivation for having this feature
is
for use by the (planned) -foffload-memory=pinned feature.
gcc/fortran/ChangeLog:
* openmp.cc (is_predefined_allocator): Update valid ranges to
incorporate ompx_gnu_pinned_mem_alloc.
libgomp/ChangeLog:
* allocator.c (ompx_gnu_min_predefined_alloc): New.
(ompx_gnu_max_predefined_alloc): New.
(predefined_alloc_mapping): Rename to ...
(predefined_omp_alloc_mapping): ... this.
(predefined_ompx_gnu_alloc_mapping): New.
(_Static_assert): Adjust for the new name, and add a new assert for
the
new table.
(predefined_allocator_p): New.
(predefined_alloc_mapping): New.
(omp_aligned_alloc): Support ompx_gnu_pinned_mem_alloc.
Use predefined_allocator_p and predefined_alloc_mapping.
(omp_free): Likewise.
(omp_alligned_calloc): Likewise.
(omp_realloc): Likewise.
* env.c (parse_allocator): Add ompx_gnu_pinned_mem_alloc.
* libgomp.texi: Document ompx_gnu_pinned_mem_alloc.
* omp.h.in (omp_allocator_handle_t): Add ompx_gnu_pinned_mem_alloc.
* omp_lib.f90.in: Add ompx_gnu_pinned_mem_alloc.
* omp_lib.h.in: Add ompx_gnu_pinned_mem_alloc.
* testsuite/libgomp.c/alloc-pinned-5.c: New test.
* testsuite/libgomp.c/alloc-pinned-6.c: New test.
* testsuite/libgomp.fortran/alloc-pinned-1.f90: New test.
gcc/testsuite/ChangeLog:
* gfortran.dg/gomp/allocate-pinned-1.f90: New test.
Co-Authored-By: Thomas Schwinge
Diff:
---
gcc/fortran/openmp.cc | 11 +-
.../gfortran.dg/gomp/allocate-pinned-1.f90 | 16 +++
libgomp/allocator.c| 115 +++--
libgomp/env.c | 1 +
libgomp/libgomp.texi | 7 +-
libgomp/omp.h.in | 1 +
libgomp/omp_lib.f90.in | 2 +
libgomp/omp_lib.h.in | 2 +
libgomp/testsuite/libgomp.c/alloc-pinned-5.c | 100 ++
libgomp/testsuite/libgomp.c/alloc-pinned-6.c | 102 ++
.../testsuite/libgomp.fortran/alloc-pinned-1.f90 | 16 +++
11 files changed, 336 insertions(+), 37 deletions(-)
diff --git a/gcc/fortran/openmp.cc b/gcc/fortran/openmp.cc
index 9b30a108560..333f0c7fe7f 100644
--- a/gcc/fortran/openmp.cc
+++ b/gcc/fortran/openmp.cc
@@ -7423,8 +7423,9 @@ resolve_omp_udr_clause (gfc_omp_namelist *n,
gfc_namespace *ns,
}
/* Assume that a constant expression in the range 1 (omp_default_mem_alloc)
- to 8 (omp_thread_mem_alloc) range is fine. The original symbol name is
- already lost during matching via gfc_match_expr. */
+ to 8 (omp_thread_mem_alloc) range, or 200 (ompx_gnu_pinned_mem_alloc) is
+ fine. The original symbol name is already lost during matching via
+ gfc_match_expr. */
static bool
is_predefined_allocator (gfc_expr *expr)
{
@@ -7433,8 +7434,10 @@ is_predefined_allocator (gfc_expr *expr)
&& expr->ts.type == BT_INTEGER
&& expr->ts.kind == gfc_c_intptr_kind
&& expr->expr_type == EXPR_CONSTANT
- && mpz_sgn (expr->value.integer) > 0
- && mpz_cmp_si (expr->value.integer, 8) <= 0);
+ && ((mpz_sgn (expr->value.integer) > 0
+ && mpz_cmp_si (expr->value.integer, 8) <= 0)
+ || (mpz_cmp_si (expr->value.integer, 200) >= 0
+ && mpz_cmp_si (expr->value.integer, 200) <= 0)));
}
/* Resolve declarative ALLOCATE statement. Note: Common block vars only appear
diff --git a/gcc/testsuite/gfortran.dg/gomp/allocate-pinned-1.f90
b/gcc/testsuite/gfortran.dg/gomp/allocate-pinned-1.f90
new file mode 100644
index 000..0e6619b7853
--- /dev/null
+++ b/gcc/testsuite/gfortran.dg/gomp/allocate-pinned-1.f90
@@ -0,0 +1,16 @@
+! Test that the ompx_gnu_pinned_mem_alloc is accepted by the parser
+
+module m
+use iso_c_binding
+integer, parameter :: omp_allocator_handle_kind = c_intptr_t
+integer (kind=omp_allocator_handle_kind), &
+ parameter :: ompx_gnu_pinned_mem_alloc = 200
+end
+
+subroutine f ()
+
[gcc r15-1749] testsuite/52641 - Adjust some test cases to less capable platforms.
https://gcc.gnu.org/g:90c558ef740d0b98892b6a7811c278eda8adeea3
commit r15-1749-g90c558ef740d0b98892b6a7811c278eda8adeea3
Author: Georg-Johann Lay
Date: Mon Jul 1 12:10:50 2024 +0200
testsuite/52641 - Adjust some test cases to less capable platforms.
PR testsuite/52641
gcc/testsuite/
* gcc.dg/analyzer/pr109577.c: Use __SIZE_TYPE__ instead of
"unsigned long".
* gcc.dg/analyzer/pr93032-mztools-signed-char.c: Requires int32plus.
* gcc.dg/analyzer/pr93032-mztools-unsigned-char.c: Requires
int32plus.
* gcc.dg/analyzer/putenv-1.c: Skip on avr.
* gcc.dg/torture/type-generic-1.c: Skip on avr.
Diff:
---
gcc/testsuite/gcc.dg/analyzer/pr109577.c | 8
gcc/testsuite/gcc.dg/analyzer/pr93032-mztools-signed-char.c | 1 +
gcc/testsuite/gcc.dg/analyzer/pr93032-mztools-unsigned-char.c | 1 +
gcc/testsuite/gcc.dg/analyzer/putenv-1.c | 1 +
gcc/testsuite/gcc.dg/torture/type-generic-1.c | 1 +
5 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/gcc/testsuite/gcc.dg/analyzer/pr109577.c
b/gcc/testsuite/gcc.dg/analyzer/pr109577.c
index 74d1629f3c7..18417818b54 100644
--- a/gcc/testsuite/gcc.dg/analyzer/pr109577.c
+++ b/gcc/testsuite/gcc.dg/analyzer/pr109577.c
@@ -2,18 +2,18 @@
Therefore this test has been duplicated as
c-c++-common/analyzer/pr109577-noexcept.c */
-void *malloc (unsigned long);
+void *malloc (__SIZE_TYPE__);
double *
-unsafe (unsigned long n)
+unsafe (__SIZE_TYPE__ n)
{
return (double *) malloc (n * sizeof (double));
}
double *
-safer (unsigned long n)
+safer (__SIZE_TYPE__ n)
{
- unsigned long nbytes;
+ __SIZE_TYPE__ nbytes;
if (__builtin_mul_overflow (n, sizeof (double), &nbytes))
return 0;
return (double *) malloc (nbytes); /* Exceptions enabled cause a leak here.
*/
diff --git a/gcc/testsuite/gcc.dg/analyzer/pr93032-mztools-signed-char.c
b/gcc/testsuite/gcc.dg/analyzer/pr93032-mztools-signed-char.c
index 45599e228b8..7a7320fca2b 100644
--- a/gcc/testsuite/gcc.dg/analyzer/pr93032-mztools-signed-char.c
+++ b/gcc/testsuite/gcc.dg/analyzer/pr93032-mztools-signed-char.c
@@ -5,6 +5,7 @@
/* { dg-do "compile" } */
/* { dg-additional-options "-fsigned-char" } */
+/* { dg-require-effective-target int32plus } */
/* TODO (PR analyzer/112528): remove need for this. */
/* { dg-additional-options "--param analyzer-max-enodes-per-program-point=40
--param analyzer-bb-explosion-factor=10" } */
diff --git a/gcc/testsuite/gcc.dg/analyzer/pr93032-mztools-unsigned-char.c
b/gcc/testsuite/gcc.dg/analyzer/pr93032-mztools-unsigned-char.c
index a59fc49c2b3..10832757127 100644
--- a/gcc/testsuite/gcc.dg/analyzer/pr93032-mztools-unsigned-char.c
+++ b/gcc/testsuite/gcc.dg/analyzer/pr93032-mztools-unsigned-char.c
@@ -5,6 +5,7 @@
/* { dg-do "compile" } */
/* { dg-additional-options "-funsigned-char" } */
+/* { dg-require-effective-target int32plus } */
/* TODO (PR analyzer/112528): remove need for this. */
/* { dg-additional-options "--param analyzer-max-enodes-per-program-point=40
--param analyzer-bb-explosion-factor=10" } */
diff --git a/gcc/testsuite/gcc.dg/analyzer/putenv-1.c
b/gcc/testsuite/gcc.dg/analyzer/putenv-1.c
index 5c4e08c68df..2be52f05033 100644
--- a/gcc/testsuite/gcc.dg/analyzer/putenv-1.c
+++ b/gcc/testsuite/gcc.dg/analyzer/putenv-1.c
@@ -1,5 +1,6 @@
/* { dg-additional-options "-Wno-analyzer-null-argument" } */
/* { dg-require-effective-target alloca } */
+/* { dg-skip-if "has no putenv" { "avr-*-*" } } */
#include
#include
diff --git a/gcc/testsuite/gcc.dg/torture/type-generic-1.c
b/gcc/testsuite/gcc.dg/torture/type-generic-1.c
index b2aacd933f8..1dd0534a5fb 100644
--- a/gcc/testsuite/gcc.dg/torture/type-generic-1.c
+++ b/gcc/testsuite/gcc.dg/torture/type-generic-1.c
@@ -4,6 +4,7 @@
/* { dg-do run } */
/* { dg-require-effective-target inf } */
/* { dg-skip-if "No subnormal support" { csky-*-* } { "-mhard-float" } } */
+/* { dg-skip-if "Not fully IEEE" { "avr-*-*" } } */
/* { dg-options "-DUNSAFE" { target tic6x*-*-* visium-*-* nvptx-*-* } } */
/* { dg-add-options ieee } */
[gcc r15-1750] AVR: target/88236, target/115726 - Fix __memx code generation.
https://gcc.gnu.org/g:3d23abd3dd9c8c226ea302203b214b346f4fe8d7
commit r15-1750-g3d23abd3dd9c8c226ea302203b214b346f4fe8d7
Author: Georg-Johann Lay
Date: Mon Jul 1 12:31:01 2024 +0200
AVR: target/88236, target/115726 - Fix __memx code generation.
PR target/88236
PR target/115726
gcc/
* config/avr/avr.md (mov) [avr_mem_memx_p]: Expand in such a
way that the destination does not overlap with any hard register
clobbered / used by xload8qi_A resp. xload_A.
* config/avr/avr.cc (avr_out_xload): Avoid early-clobber
situation for Z by executing just one load when the output register
overlaps with Z.
gcc/testsuite/
* gcc.target/avr/torture/pr88236-pr115726.c: New test.
Diff:
---
gcc/config/avr/avr.cc | 8 +-
gcc/config/avr/avr.md | 18 +++-
.../gcc.target/avr/torture/pr88236-pr115726.c | 115 +
3 files changed, 138 insertions(+), 3 deletions(-)
diff --git a/gcc/config/avr/avr.cc b/gcc/config/avr/avr.cc
index 61c325f2497..a110af62cd5 100644
--- a/gcc/config/avr/avr.cc
+++ b/gcc/config/avr/avr.cc
@@ -4686,7 +4686,13 @@ avr_out_xload (rtx_insn * /*insn*/, rtx *op, int *plen)
xop[2] = lpm_addr_reg_rtx;
xop[3] = AVR_HAVE_LPMX ? op[0] : lpm_reg_rtx;
- avr_asm_len (AVR_HAVE_LPMX ? "lpm %3,%a2" : "lpm", xop, plen, -1);
+ if (plen)
+*plen = 0;
+
+ if (reg_overlap_mentioned_p (xop[3], lpm_addr_reg_rtx))
+avr_asm_len ("sbrs %1,7", xop, plen, 1);
+
+ avr_asm_len (AVR_HAVE_LPMX ? "lpm %3,%a2" : "lpm", xop, plen, 1);
avr_asm_len ("sbrc %1,7" CR_TAB
"ld %3,%a2", xop, plen, 2);
diff --git a/gcc/config/avr/avr.md b/gcc/config/avr/avr.md
index 75d35d5e14b..dabf4c0fc5a 100644
--- a/gcc/config/avr/avr.md
+++ b/gcc/config/avr/avr.md
@@ -735,12 +735,26 @@
if (!REG_P (addr))
src = replace_equiv_address (src, copy_to_mode_reg (PSImode, addr));
+rtx dest2 = reg_overlap_mentioned_p (dest, lpm_addr_reg_rtx)
+ ? gen_reg_rtx (mode)
+ : dest;
+
if (!avr_xload_libgcc_p (mode))
// No here because gen_xload8_A only iterates over ALL1.
// insn-emit does not depend on the mode, it's all about operands.
- emit_insn (gen_xload8qi_A (dest, src));
+ emit_insn (gen_xload8qi_A (dest2, src));
else
- emit_insn (gen_xload_A (dest, src));
+ {
+rtx reg_22 = gen_rtx_REG (mode, REG_22);
+if (reg_overlap_mentioned_p (dest2, reg_22)
+|| reg_overlap_mentioned_p (dest2, all_regs_rtx[REG_21]))
+ dest2 = gen_reg_rtx (mode);
+
+emit_insn (gen_xload_A (dest2, src));
+ }
+
+if (dest2 != dest)
+ emit_move_insn (dest, dest2);
DONE;
}
diff --git a/gcc/testsuite/gcc.target/avr/torture/pr88236-pr115726.c
b/gcc/testsuite/gcc.target/avr/torture/pr88236-pr115726.c
new file mode 100644
index 000..9fd5fd3b5f5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/avr/torture/pr88236-pr115726.c
@@ -0,0 +1,115 @@
+/* { dg-do run { target { ! avr_tiny } } } */
+/* { dg-additional-options "-std=gnu99" } */
+
+const __flash char fvals8[] = { 1, 2, 3 };
+char rvals8[] = { 0, 2, 4 };
+
+const __flash int fvals16[] = { 1, 2, 3 };
+int rvals16[] = { 0, 2, 4 };
+
+__attribute__((noinline, noclone))
+char xload8_r30 (const __memx char *pc)
+{
+ register char c __asm ("r30");
+ c = *pc;
+ __asm (";;" : "+r" (c));
+ return c;
+}
+
+__attribute__((noinline, noclone))
+int xload16_r30 (const __memx int *pc)
+{
+ register int c __asm ("r30");
+ c = *pc;
+ __asm (";;" : "+r" (c));
+ return c;
+}
+
+__attribute__((noinline, noclone))
+char xload8_r22 (const __memx char *pc)
+{
+ register char c __asm ("r22");
+ c = *pc;
+ __asm (";;" : "+r" (c));
+ return c;
+}
+
+__attribute__((noinline, noclone))
+int xload16_r22 (const __memx int *pc)
+{
+ register int c __asm ("r22");
+ c = *pc;
+ __asm (";;" : "+r" (c));
+ return c;
+}
+
+__attribute__((noinline, noclone))
+int xload16_r20 (const __memx int *pc)
+{
+ register int c __asm ("r20");
+ c = *pc;
+ __asm (";;" : "+r" (c));
+ return c;
+}
+
+void test8 (void)
+{
+ char c;
+ for (int i = 0; i < 3; ++i)
+{
+ c = xload8_r30 (fvals8 + i);
+ if (c != 1 + i)
+ __builtin_exit (__LINE__);
+
+ c = xload8_r22 (fvals8 + i);
+ if (c != 1 + i)
+ __builtin_exit (__LINE__);
+
+ c = xload8_r30 (rvals8 + i);
+ if (c != 2 * i)
+ __builtin_exit (__LINE__);
+
+ c = xload8_r22 (rvals8 + i);
+ if (c != 2 * i)
+ __builtin_exit (__LINE__);
+}
+}
+
+void test16 (void)
+{
+ int c;
+ for (int i = 0; i < 3; ++i)
+{
+ c = xload16_r30 (fvals16 + i);
+ if (c != 1 + i)
+ __builtin_exit (__LINE__);
+
+ c = xload16_r22 (fvals16 + i);
+ if (c != 1 + i)
+ __builtin_exit (__LI
[gcc r15-1751] i386: Additional peephole2 to use lea in round-up integer division.
https://gcc.gnu.org/g:142b5263b18be96e5d9ce406ad2c1b6ab35c190f
commit r15-1751-g142b5263b18be96e5d9ce406ad2c1b6ab35c190f
Author: Roger Sayle
Date: Mon Jul 1 12:18:26 2024 +0100
i386: Additional peephole2 to use lea in round-up integer division.
A common idiom for implementing an integer division that rounds upwards is
to write (x + y - 1) / y. Conveniently on x86, the two additions to form
the numerator can be performed by a single lea instruction, and indeed gcc
currently generates a lea when both x and y are both registers.
int foo(int x, int y) {
return (x+y-1)/y;
}
generates with -O2:
foo:leal-1(%rsi,%rdi), %eax // 4 bytes
cltd
idivl %esi
ret
Oddly, however, if x is a memory, gcc currently uses two instructions:
int m;
int bar(int y) {
return (m+y-1)/y;
}
generates:
foo:movlm(%rip), %eax
addl%edi, %eax // 2 bytes
subl$1, %eax// 3 bytes
cltd
idivl %edi
ret
This discrepancy is caused by the late decision (in peephole2) to split
an addition with a memory operand, into a load followed by a reg-reg
addition. This patch improves this situation by adding a peephole2
to recognize consecutive additions and transform them into lea if
profitable.
My first attempt at fixing this was to use a define_insn_and_split:
(define_insn_and_split "*lea3_reg_mem_imm"
[(set (match_operand:SWI48 0 "register_operand")
(plus:SWI48 (plus:SWI48 (match_operand:SWI48 1 "register_operand")
(match_operand:SWI48 2 "memory_operand"))
(match_operand:SWI48 3 "x86_64_immediate_operand")))]
"ix86_pre_reload_split ()"
"#"
"&& 1"
[(set (match_dup 4) (match_dup 2))
(set (match_dup 0) (plus:SWI48 (plus:SWI48 (match_dup 1) (match_dup 4))
(match_dup 3)))]
"operands[4] = gen_reg_rtx (mode);")
using combine to combine instructions. Unfortunately, this approach
interferes with (reload's) subtle balance of deciding when to use/avoid lea,
which can be observed as a code size regression in CSiBE. The peephole2
approach (proposed here) uniformly improves CSiBE results.
2024-07-01 Roger Sayle
gcc/ChangeLog
* config/i386/i386.md (peephole2): Transform two consecutive
additions into a 3-component lea if !TARGET_AVOID_LEA_FOR_ADDR.
gcc/testsuite/ChangeLog
* gcc.target/i386/lea-3.c: New test case.
Diff:
---
gcc/config/i386/i386.md | 15 +++
gcc/testsuite/gcc.target/i386/lea-3.c | 13 +
2 files changed, 28 insertions(+)
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 59a889da304..0b6f6e75072 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -6332,6 +6332,21 @@
"TARGET_APX_NF && reload_completed"
[(set (match_dup 0) (ashift:SWI48 (match_dup 0) (match_dup 1)))]
"operands[1] = GEN_INT (exact_log2 (INTVAL (operands[1])));")
+
+;; The peephole2 pass may expose consecutive additions suitable for lea.
+(define_peephole2
+ [(parallel [(set (match_operand:SWI48 0 "register_operand")
+ (plus:SWI48 (match_dup 0)
+ (match_operand 1 "register_operand")))
+ (clobber (reg:CC FLAGS_REG))])
+ (parallel [(set (match_dup 0)
+ (plus:SWI48 (match_dup 0)
+ (match_operand 2 "x86_64_immediate_operand")))
+ (clobber (reg:CC FLAGS_REG))])]
+ "!TARGET_AVOID_LEA_FOR_ADDR || optimize_function_for_size_p (cfun)"
+ [(set (match_dup 0) (plus:SWI48 (plus:SWI48 (match_dup 0)
+ (match_dup 1))
+ (match_dup 2)))])
;; Add instructions
diff --git a/gcc/testsuite/gcc.target/i386/lea-3.c
b/gcc/testsuite/gcc.target/i386/lea-3.c
new file mode 100644
index 000..84e66b00fc2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/lea-3.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+int m;
+
+int foo(int y)
+{
+ return (m+y-1)/y;
+}
+
+/* { dg-final { scan-assembler "leal" } } */
+/* { dg-final { scan-assembler-not "addl" } } */
+/* { dg-final { scan-assembler-not "subl" } } */
[gcc r15-1752] testsuite: Fix -m32 gcc.target/i386/pr102464-vrndscaleph.c on RedHat.
https://gcc.gnu.org/g:589865a8e4f6bd26c622ea0ee0a38565a0d42e80
commit r15-1752-g589865a8e4f6bd26c622ea0ee0a38565a0d42e80
Author: Roger Sayle
Date: Mon Jul 1 12:21:20 2024 +0100
testsuite: Fix -m32 gcc.target/i386/pr102464-vrndscaleph.c on RedHat.
This patch fixes the 4 FAILs of gcc.target/i386/pr192464-vrndscaleph.c
with --target_board='unix{-m32}' on RedHat 7.x. The issue is that this
AVX512 test includes the system math.h, and on older systems this provides
inline versions of floor, ceil and rint (for the 387). The work around
is to define __NO_MATH_INLINES before #include (or alternatively
use __builtin_floor, __builtin_ceil, etc.).
2024-07-01 Roger Sayle
gcc/testsuite/ChangeLog
PR middle-end/102464
* gcc.target/i386/pr102464-vrndscaleph.c: Define __NO_MATH_INLINES
to resovle FAILs with -m32 on older RedHat systems.
Diff:
---
gcc/testsuite/gcc.target/i386/pr102464-vrndscaleph.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/gcc/testsuite/gcc.target/i386/pr102464-vrndscaleph.c
b/gcc/testsuite/gcc.target/i386/pr102464-vrndscaleph.c
index a76d9e7e376..9eb8124e3f5 100644
--- a/gcc/testsuite/gcc.target/i386/pr102464-vrndscaleph.c
+++ b/gcc/testsuite/gcc.target/i386/pr102464-vrndscaleph.c
@@ -1,6 +1,9 @@
/* PR target/102464. */
/* { dg-do compile } */
/* { dg-options "-Ofast -mavx512fp16 -mavx512vl -mprefer-vector-width=512" } */
+#ifndef __NO_MATH_INLINES
+#define __NO_MATH_INLINES
+#endif
#include
void
foo (_Float16* __restrict a, _Float16* b)
[gcc r14-10367] AVR: target/88236, target/115726 - Fix __memx code generation.
https://gcc.gnu.org/g:7249b3cdc16ae85bcfeb63510b6e5cb7f4a43adb
commit r14-10367-g7249b3cdc16ae85bcfeb63510b6e5cb7f4a43adb
Author: Georg-Johann Lay
Date: Mon Jul 1 12:31:01 2024 +0200
AVR: target/88236, target/115726 - Fix __memx code generation.
PR target/88236
PR target/115726
gcc/
* config/avr/avr.md (mov) [avr_mem_memx_p]: Expand in such a
way that the destination does not overlap with any hard register
clobbered / used by xload8qi_A resp. xload_A.
* config/avr/avr.cc (avr_out_xload): Avoid early-clobber
situation for Z by executing just one load when the output register
overlaps with Z.
gcc/testsuite/
* gcc.target/avr/torture/pr88236-pr115726.c: New test.
(cherry picked from commit 3d23abd3dd9c8c226ea302203b214b346f4fe8d7)
Diff:
---
gcc/config/avr/avr.cc | 8 +-
gcc/config/avr/avr.md | 18 +++-
.../gcc.target/avr/torture/pr88236-pr115726.c | 115 +
3 files changed, 138 insertions(+), 3 deletions(-)
diff --git a/gcc/config/avr/avr.cc b/gcc/config/avr/avr.cc
index 74924ab0565..e516c19322c 100644
--- a/gcc/config/avr/avr.cc
+++ b/gcc/config/avr/avr.cc
@@ -4686,7 +4686,13 @@ avr_out_xload (rtx_insn * /*insn*/, rtx *op, int *plen)
xop[2] = lpm_addr_reg_rtx;
xop[3] = AVR_HAVE_LPMX ? op[0] : lpm_reg_rtx;
- avr_asm_len (AVR_HAVE_LPMX ? "lpm %3,%a2" : "lpm", xop, plen, -1);
+ if (plen)
+*plen = 0;
+
+ if (reg_overlap_mentioned_p (xop[3], lpm_addr_reg_rtx))
+avr_asm_len ("sbrs %1,7", xop, plen, 1);
+
+ avr_asm_len (AVR_HAVE_LPMX ? "lpm %3,%a2" : "lpm", xop, plen, 1);
avr_asm_len ("sbrc %1,7" CR_TAB
"ld %3,%a2", xop, plen, 2);
diff --git a/gcc/config/avr/avr.md b/gcc/config/avr/avr.md
index 75d35d5e14b..dabf4c0fc5a 100644
--- a/gcc/config/avr/avr.md
+++ b/gcc/config/avr/avr.md
@@ -735,12 +735,26 @@
if (!REG_P (addr))
src = replace_equiv_address (src, copy_to_mode_reg (PSImode, addr));
+rtx dest2 = reg_overlap_mentioned_p (dest, lpm_addr_reg_rtx)
+ ? gen_reg_rtx (mode)
+ : dest;
+
if (!avr_xload_libgcc_p (mode))
// No here because gen_xload8_A only iterates over ALL1.
// insn-emit does not depend on the mode, it's all about operands.
- emit_insn (gen_xload8qi_A (dest, src));
+ emit_insn (gen_xload8qi_A (dest2, src));
else
- emit_insn (gen_xload_A (dest, src));
+ {
+rtx reg_22 = gen_rtx_REG (mode, REG_22);
+if (reg_overlap_mentioned_p (dest2, reg_22)
+|| reg_overlap_mentioned_p (dest2, all_regs_rtx[REG_21]))
+ dest2 = gen_reg_rtx (mode);
+
+emit_insn (gen_xload_A (dest2, src));
+ }
+
+if (dest2 != dest)
+ emit_move_insn (dest, dest2);
DONE;
}
diff --git a/gcc/testsuite/gcc.target/avr/torture/pr88236-pr115726.c
b/gcc/testsuite/gcc.target/avr/torture/pr88236-pr115726.c
new file mode 100644
index 000..9fd5fd3b5f5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/avr/torture/pr88236-pr115726.c
@@ -0,0 +1,115 @@
+/* { dg-do run { target { ! avr_tiny } } } */
+/* { dg-additional-options "-std=gnu99" } */
+
+const __flash char fvals8[] = { 1, 2, 3 };
+char rvals8[] = { 0, 2, 4 };
+
+const __flash int fvals16[] = { 1, 2, 3 };
+int rvals16[] = { 0, 2, 4 };
+
+__attribute__((noinline, noclone))
+char xload8_r30 (const __memx char *pc)
+{
+ register char c __asm ("r30");
+ c = *pc;
+ __asm (";;" : "+r" (c));
+ return c;
+}
+
+__attribute__((noinline, noclone))
+int xload16_r30 (const __memx int *pc)
+{
+ register int c __asm ("r30");
+ c = *pc;
+ __asm (";;" : "+r" (c));
+ return c;
+}
+
+__attribute__((noinline, noclone))
+char xload8_r22 (const __memx char *pc)
+{
+ register char c __asm ("r22");
+ c = *pc;
+ __asm (";;" : "+r" (c));
+ return c;
+}
+
+__attribute__((noinline, noclone))
+int xload16_r22 (const __memx int *pc)
+{
+ register int c __asm ("r22");
+ c = *pc;
+ __asm (";;" : "+r" (c));
+ return c;
+}
+
+__attribute__((noinline, noclone))
+int xload16_r20 (const __memx int *pc)
+{
+ register int c __asm ("r20");
+ c = *pc;
+ __asm (";;" : "+r" (c));
+ return c;
+}
+
+void test8 (void)
+{
+ char c;
+ for (int i = 0; i < 3; ++i)
+{
+ c = xload8_r30 (fvals8 + i);
+ if (c != 1 + i)
+ __builtin_exit (__LINE__);
+
+ c = xload8_r22 (fvals8 + i);
+ if (c != 1 + i)
+ __builtin_exit (__LINE__);
+
+ c = xload8_r30 (rvals8 + i);
+ if (c != 2 * i)
+ __builtin_exit (__LINE__);
+
+ c = xload8_r22 (rvals8 + i);
+ if (c != 2 * i)
+ __builtin_exit (__LINE__);
+}
+}
+
+void test16 (void)
+{
+ int c;
+ for (int i = 0; i < 3; ++i)
+{
+ c = xload16_r30 (fvals16 + i);
+ if (c != 1 + i)
+ __builtin_exit (__LINE__);
+
+ c =
[gcc r13-8882] AVR: target/88236, target/115726 - Fix __memx code generation.
https://gcc.gnu.org/g:743575bfc6cfb3520047bddf969f880455d581b1
commit r13-8882-g743575bfc6cfb3520047bddf969f880455d581b1
Author: Georg-Johann Lay
Date: Mon Jul 1 12:31:01 2024 +0200
AVR: target/88236, target/115726 - Fix __memx code generation.
PR target/88236
PR target/115726
gcc/
* config/avr/avr.md (mov) [avr_mem_memx_p]: Expand in such a
way that the destination does not overlap with any hard register
clobbered / used by xload8qi_A resp. xload_A.
* config/avr/avr.cc (avr_out_xload): Avoid early-clobber
situation for Z by executing just one load when the output register
overlaps with Z.
gcc/testsuite/
* gcc.target/avr/torture/pr88236-pr115726.c: New test.
(cherry picked from commit 3d23abd3dd9c8c226ea302203b214b346f4fe8d7)
Diff:
---
gcc/config/avr/avr.cc | 8 +-
gcc/config/avr/avr.md | 18 +++-
.../gcc.target/avr/torture/pr88236-pr115726.c | 115 +
3 files changed, 138 insertions(+), 3 deletions(-)
diff --git a/gcc/config/avr/avr.cc b/gcc/config/avr/avr.cc
index a5c628134b4..36ad0f23162 100644
--- a/gcc/config/avr/avr.cc
+++ b/gcc/config/avr/avr.cc
@@ -4093,7 +4093,13 @@ avr_out_xload (rtx_insn *insn ATTRIBUTE_UNUSED, rtx *op,
int *plen)
xop[2] = lpm_addr_reg_rtx;
xop[3] = AVR_HAVE_LPMX ? op[0] : lpm_reg_rtx;
- avr_asm_len (AVR_HAVE_LPMX ? "lpm %3,%a2" : "lpm", xop, plen, -1);
+ if (plen)
+*plen = 0;
+
+ if (reg_overlap_mentioned_p (xop[3], lpm_addr_reg_rtx))
+avr_asm_len ("sbrs %1,7", xop, plen, 1);
+
+ avr_asm_len (AVR_HAVE_LPMX ? "lpm %3,%a2" : "lpm", xop, plen, 1);
avr_asm_len ("sbrc %1,7" CR_TAB
"ld %3,%a2", xop, plen, 2);
diff --git a/gcc/config/avr/avr.md b/gcc/config/avr/avr.md
index 46f7812cea2..c8b5ccaf098 100644
--- a/gcc/config/avr/avr.md
+++ b/gcc/config/avr/avr.md
@@ -718,12 +718,26 @@
if (!REG_P (addr))
src = replace_equiv_address (src, copy_to_mode_reg (PSImode, addr));
+rtx dest2 = reg_overlap_mentioned_p (dest, lpm_addr_reg_rtx)
+ ? gen_reg_rtx (mode)
+ : dest;
+
if (!avr_xload_libgcc_p (mode))
/* ; No here because gen_xload8_A only iterates over
ALL1.
; insn-emit does not depend on the mode, it's all about operands.
*/
- emit_insn (gen_xload8qi_A (dest, src));
+ emit_insn (gen_xload8qi_A (dest2, src));
else
- emit_insn (gen_xload_A (dest, src));
+ {
+rtx reg_22 = gen_rtx_REG (mode, 22);
+if (reg_overlap_mentioned_p (dest2, reg_22)
+|| reg_overlap_mentioned_p (dest2, all_regs_rtx[21]))
+ dest2 = gen_reg_rtx (mode);
+
+emit_insn (gen_xload_A (dest2, src));
+ }
+
+if (dest2 != dest)
+ emit_move_insn (dest, dest2);
DONE;
}
diff --git a/gcc/testsuite/gcc.target/avr/torture/pr88236-pr115726.c
b/gcc/testsuite/gcc.target/avr/torture/pr88236-pr115726.c
new file mode 100644
index 000..9fd5fd3b5f5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/avr/torture/pr88236-pr115726.c
@@ -0,0 +1,115 @@
+/* { dg-do run { target { ! avr_tiny } } } */
+/* { dg-additional-options "-std=gnu99" } */
+
+const __flash char fvals8[] = { 1, 2, 3 };
+char rvals8[] = { 0, 2, 4 };
+
+const __flash int fvals16[] = { 1, 2, 3 };
+int rvals16[] = { 0, 2, 4 };
+
+__attribute__((noinline, noclone))
+char xload8_r30 (const __memx char *pc)
+{
+ register char c __asm ("r30");
+ c = *pc;
+ __asm (";;" : "+r" (c));
+ return c;
+}
+
+__attribute__((noinline, noclone))
+int xload16_r30 (const __memx int *pc)
+{
+ register int c __asm ("r30");
+ c = *pc;
+ __asm (";;" : "+r" (c));
+ return c;
+}
+
+__attribute__((noinline, noclone))
+char xload8_r22 (const __memx char *pc)
+{
+ register char c __asm ("r22");
+ c = *pc;
+ __asm (";;" : "+r" (c));
+ return c;
+}
+
+__attribute__((noinline, noclone))
+int xload16_r22 (const __memx int *pc)
+{
+ register int c __asm ("r22");
+ c = *pc;
+ __asm (";;" : "+r" (c));
+ return c;
+}
+
+__attribute__((noinline, noclone))
+int xload16_r20 (const __memx int *pc)
+{
+ register int c __asm ("r20");
+ c = *pc;
+ __asm (";;" : "+r" (c));
+ return c;
+}
+
+void test8 (void)
+{
+ char c;
+ for (int i = 0; i < 3; ++i)
+{
+ c = xload8_r30 (fvals8 + i);
+ if (c != 1 + i)
+ __builtin_exit (__LINE__);
+
+ c = xload8_r22 (fvals8 + i);
+ if (c != 1 + i)
+ __builtin_exit (__LINE__);
+
+ c = xload8_r30 (rvals8 + i);
+ if (c != 2 * i)
+ __builtin_exit (__LINE__);
+
+ c = xload8_r22 (rvals8 + i);
+ if (c != 2 * i)
+ __builtin_exit (__LINE__);
+}
+}
+
+void test16 (void)
+{
+ int c;
+ for (int i = 0; i < 3; ++i)
+{
+ c = xload16_r30 (fvals16 + i);
+ if (c != 1 + i)
+ __builtin_exit (__LINE__
[gcc r12-10591] AVR: target/88236, target/115726 - Fix __memx code generation.
https://gcc.gnu.org/g:53305588cfbf74604bafcc27902e1eded5677ae6
commit r12-10591-g53305588cfbf74604bafcc27902e1eded5677ae6
Author: Georg-Johann Lay
Date: Mon Jul 1 12:31:01 2024 +0200
AVR: target/88236, target/115726 - Fix __memx code generation.
PR target/88236
PR target/115726
gcc/
* config/avr/avr.md (mov) [avr_mem_memx_p]: Expand in such a
way that the destination does not overlap with any hard register
clobbered / used by xload8qi_A resp. xload_A.
* config/avr/avr.cc (avr_out_xload): Avoid early-clobber
situation for Z by executing just one load when the output register
overlaps with Z.
gcc/testsuite/
* gcc.target/avr/torture/pr88236-pr115726.c: New test.
(cherry picked from commit 3d23abd3dd9c8c226ea302203b214b346f4fe8d7)
Diff:
---
gcc/config/avr/avr.cc | 8 +-
gcc/config/avr/avr.md | 18 +++-
.../gcc.target/avr/torture/pr88236-pr115726.c | 115 +
3 files changed, 138 insertions(+), 3 deletions(-)
diff --git a/gcc/config/avr/avr.cc b/gcc/config/avr/avr.cc
index bc15017c61c..ee033d3204d 100644
--- a/gcc/config/avr/avr.cc
+++ b/gcc/config/avr/avr.cc
@@ -4071,7 +4071,13 @@ avr_out_xload (rtx_insn *insn ATTRIBUTE_UNUSED, rtx *op,
int *plen)
xop[2] = lpm_addr_reg_rtx;
xop[3] = AVR_HAVE_LPMX ? op[0] : lpm_reg_rtx;
- avr_asm_len (AVR_HAVE_LPMX ? "lpm %3,%a2" : "lpm", xop, plen, -1);
+ if (plen)
+*plen = 0;
+
+ if (reg_overlap_mentioned_p (xop[3], lpm_addr_reg_rtx))
+avr_asm_len ("sbrs %1,7", xop, plen, 1);
+
+ avr_asm_len (AVR_HAVE_LPMX ? "lpm %3,%a2" : "lpm", xop, plen, 1);
avr_asm_len ("sbrc %1,7" CR_TAB
"ld %3,%a2", xop, plen, 2);
diff --git a/gcc/config/avr/avr.md b/gcc/config/avr/avr.md
index de029476908..f76249340b8 100644
--- a/gcc/config/avr/avr.md
+++ b/gcc/config/avr/avr.md
@@ -715,12 +715,26 @@
if (!REG_P (addr))
src = replace_equiv_address (src, copy_to_mode_reg (PSImode, addr));
+rtx dest2 = reg_overlap_mentioned_p (dest, lpm_addr_reg_rtx)
+ ? gen_reg_rtx (mode)
+ : dest;
+
if (!avr_xload_libgcc_p (mode))
/* ; No here because gen_xload8_A only iterates over
ALL1.
; insn-emit does not depend on the mode, it's all about operands.
*/
- emit_insn (gen_xload8qi_A (dest, src));
+ emit_insn (gen_xload8qi_A (dest2, src));
else
- emit_insn (gen_xload_A (dest, src));
+ {
+rtx reg_22 = gen_rtx_REG (mode, 22);
+if (reg_overlap_mentioned_p (dest2, reg_22)
+|| reg_overlap_mentioned_p (dest2, all_regs_rtx[21]))
+ dest2 = gen_reg_rtx (mode);
+
+emit_insn (gen_xload_A (dest2, src));
+ }
+
+if (dest2 != dest)
+ emit_move_insn (dest, dest2);
DONE;
}
diff --git a/gcc/testsuite/gcc.target/avr/torture/pr88236-pr115726.c
b/gcc/testsuite/gcc.target/avr/torture/pr88236-pr115726.c
new file mode 100644
index 000..9fd5fd3b5f5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/avr/torture/pr88236-pr115726.c
@@ -0,0 +1,115 @@
+/* { dg-do run { target { ! avr_tiny } } } */
+/* { dg-additional-options "-std=gnu99" } */
+
+const __flash char fvals8[] = { 1, 2, 3 };
+char rvals8[] = { 0, 2, 4 };
+
+const __flash int fvals16[] = { 1, 2, 3 };
+int rvals16[] = { 0, 2, 4 };
+
+__attribute__((noinline, noclone))
+char xload8_r30 (const __memx char *pc)
+{
+ register char c __asm ("r30");
+ c = *pc;
+ __asm (";;" : "+r" (c));
+ return c;
+}
+
+__attribute__((noinline, noclone))
+int xload16_r30 (const __memx int *pc)
+{
+ register int c __asm ("r30");
+ c = *pc;
+ __asm (";;" : "+r" (c));
+ return c;
+}
+
+__attribute__((noinline, noclone))
+char xload8_r22 (const __memx char *pc)
+{
+ register char c __asm ("r22");
+ c = *pc;
+ __asm (";;" : "+r" (c));
+ return c;
+}
+
+__attribute__((noinline, noclone))
+int xload16_r22 (const __memx int *pc)
+{
+ register int c __asm ("r22");
+ c = *pc;
+ __asm (";;" : "+r" (c));
+ return c;
+}
+
+__attribute__((noinline, noclone))
+int xload16_r20 (const __memx int *pc)
+{
+ register int c __asm ("r20");
+ c = *pc;
+ __asm (";;" : "+r" (c));
+ return c;
+}
+
+void test8 (void)
+{
+ char c;
+ for (int i = 0; i < 3; ++i)
+{
+ c = xload8_r30 (fvals8 + i);
+ if (c != 1 + i)
+ __builtin_exit (__LINE__);
+
+ c = xload8_r22 (fvals8 + i);
+ if (c != 1 + i)
+ __builtin_exit (__LINE__);
+
+ c = xload8_r30 (rvals8 + i);
+ if (c != 2 * i)
+ __builtin_exit (__LINE__);
+
+ c = xload8_r22 (rvals8 + i);
+ if (c != 2 * i)
+ __builtin_exit (__LINE__);
+}
+}
+
+void test16 (void)
+{
+ int c;
+ for (int i = 0; i < 3; ++i)
+{
+ c = xload16_r30 (fvals16 + i);
+ if (c != 1 + i)
+ __builtin_exit (__LINE_
[gcc r15-1753] RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM form 1
https://gcc.gnu.org/g:ed213b384fdca9375c3ec53c2a0eae134fb98612
commit r15-1753-ged213b384fdca9375c3ec53c2a0eae134fb98612
Author: Pan Li
Date: Sun Jun 30 16:03:41 2024 +0800
RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM form 1
This patch would like to add test cases for the unsigned scalar
.SAT_ADD IMM form 1. Aka:
Form 1:
#define DEF_SAT_U_ADD_IMM_FMT_1(T) \
T __attribute__((noinline)) \
sat_u_add_imm_##T##_fmt_1 (T x) \
{\
return (T)(x + 9) >= x ? (x + 9) : -1; \
}
DEF_SAT_U_ADD_IMM_FMT_1(uint64_t)
The below test is passed for this patch.
* The rv64gcv regression test.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/sat_arith.h: Add helper test macro.
* gcc.target/riscv/sat_u_add_imm-1.c: New test.
* gcc.target/riscv/sat_u_add_imm-2.c: New test.
* gcc.target/riscv/sat_u_add_imm-3.c: New test.
* gcc.target/riscv/sat_u_add_imm-4.c: New test.
* gcc.target/riscv/sat_u_add_imm-run-1.c: New test.
* gcc.target/riscv/sat_u_add_imm-run-2.c: New test.
* gcc.target/riscv/sat_u_add_imm-run-3.c: New test.
* gcc.target/riscv/sat_u_add_imm-run-4.c: New test.
Signed-off-by: Pan Li
Diff:
---
gcc/testsuite/gcc.target/riscv/sat_arith.h | 10 +
gcc/testsuite/gcc.target/riscv/sat_u_add_imm-1.c | 19 +
gcc/testsuite/gcc.target/riscv/sat_u_add_imm-2.c | 21 ++
gcc/testsuite/gcc.target/riscv/sat_u_add_imm-3.c | 18 +
gcc/testsuite/gcc.target/riscv/sat_u_add_imm-4.c | 17
.../gcc.target/riscv/sat_u_add_imm-run-1.c | 46 ++
.../gcc.target/riscv/sat_u_add_imm-run-2.c | 46 ++
.../gcc.target/riscv/sat_u_add_imm-run-3.c | 46 ++
.../gcc.target/riscv/sat_u_add_imm-run-4.c | 46 ++
9 files changed, 269 insertions(+)
diff --git a/gcc/testsuite/gcc.target/riscv/sat_arith.h
b/gcc/testsuite/gcc.target/riscv/sat_arith.h
index 0c2e44af718..4ec4ec36cc1 100644
--- a/gcc/testsuite/gcc.target/riscv/sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/sat_arith.h
@@ -60,6 +60,16 @@ sat_u_add_##T##_fmt_6 (T x, T y)\
#define RUN_SAT_U_ADD_FMT_5(T, x, y) sat_u_add_##T##_fmt_5(x, y)
#define RUN_SAT_U_ADD_FMT_6(T, x, y) sat_u_add_##T##_fmt_6(x, y)
+#define DEF_SAT_U_ADD_IMM_FMT_1(T, IMM) \
+T __attribute__((noinline)) \
+sat_u_add_imm##IMM##_##T##_fmt_1 (T x) \
+{\
+ return (T)(x + IMM) >= x ? (x + IMM) : -1; \
+}
+
+#define RUN_SAT_U_ADD_IMM_FMT_1(T, x, IMM, expect) \
+ if (sat_u_add_imm##IMM##_##T##_fmt_1(x) != expect) __builtin_abort ()
+
/**/
/* Saturation Sub (Unsigned and Signed)
*/
/**/
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-1.c
b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-1.c
new file mode 100644
index 000..14e9b7595a8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-1.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details
-fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_add_imm9_uint8_t_fmt_1:
+** addi\s+[atx][0-9]+,\s*a0,\s*9
+** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*0xff
+** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** neg\s+[atx][0-9]+,\s*[atx][0-9]+
+** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** andi\s+a0,\s*a0,\s*0xff
+** ret
+*/
+DEF_SAT_U_ADD_IMM_FMT_1(uint8_t, 9)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-2.c
b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-2.c
new file mode 100644
index 000..c1a3c6ff21d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-2.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details
-fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_add_imm3_uint16_t_fmt_1:
+** addi\s+[atx][0-9]+,\s*a0,\s*3
+** slli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*48
+** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*48
+** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** neg\s+[atx][0-9]+,\s*[atx][0-9]+
+** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** slli\s+a0,\s*a0,\s*48
+** srli\s+a0,\s*a0,\s*48
+** ret
+*/
+DEF_SAT_U_ADD_IMM_FMT_1(uint16_t, 3)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
diff --git a/gcc/testsui
[gcc r15-1754] RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM form 2
https://gcc.gnu.org/g:bff0d025aff8efaa5d991fcd13dd9876b115dc94
commit r15-1754-gbff0d025aff8efaa5d991fcd13dd9876b115dc94
Author: Pan Li
Date: Sun Jun 30 16:14:38 2024 +0800
RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM form 2
This patch would like to add test cases for the unsigned scalar
.SAT_ADD IMM form 2. Aka:
Form 2:
#define DEF_SAT_U_ADD_IMM_FMT_2(T) \
T __attribute__((noinline)) \
sat_u_add_imm_##T##_fmt_1 (T x) \
{ \
return (T)(x + 9) < x ? -1 : (x + 9); \
}
DEF_SAT_U_ADD_IMM_FMT_2(uint64_t)
The below test is passed for this patch.
* The rv64gcv regression test.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/sat_arith.h: Add helper test macro.
* gcc.target/riscv/sat_u_add_imm-5.c: New test.
* gcc.target/riscv/sat_u_add_imm-6.c: New test.
* gcc.target/riscv/sat_u_add_imm-7.c: New test.
* gcc.target/riscv/sat_u_add_imm-8.c: New test.
* gcc.target/riscv/sat_u_add_imm-run-5.c: New test.
* gcc.target/riscv/sat_u_add_imm-run-6.c: New test.
* gcc.target/riscv/sat_u_add_imm-run-7.c: New test.
* gcc.target/riscv/sat_u_add_imm-run-8.c: New test.
Signed-off-by: Pan Li
Diff:
---
gcc/testsuite/gcc.target/riscv/sat_arith.h | 10 +
gcc/testsuite/gcc.target/riscv/sat_u_add_imm-5.c | 19 +
gcc/testsuite/gcc.target/riscv/sat_u_add_imm-6.c | 21 ++
gcc/testsuite/gcc.target/riscv/sat_u_add_imm-7.c | 18 +
gcc/testsuite/gcc.target/riscv/sat_u_add_imm-8.c | 17
.../gcc.target/riscv/sat_u_add_imm-run-5.c | 46 ++
.../gcc.target/riscv/sat_u_add_imm-run-6.c | 46 ++
.../gcc.target/riscv/sat_u_add_imm-run-7.c | 46 ++
.../gcc.target/riscv/sat_u_add_imm-run-8.c | 46 ++
9 files changed, 269 insertions(+)
diff --git a/gcc/testsuite/gcc.target/riscv/sat_arith.h
b/gcc/testsuite/gcc.target/riscv/sat_arith.h
index 4ec4ec36cc1..d94f0fd602c 100644
--- a/gcc/testsuite/gcc.target/riscv/sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/sat_arith.h
@@ -67,9 +67,19 @@ sat_u_add_imm##IMM##_##T##_fmt_1 (T x) \
return (T)(x + IMM) >= x ? (x + IMM) : -1; \
}
+#define DEF_SAT_U_ADD_IMM_FMT_2(T, IMM) \
+T __attribute__((noinline)) \
+sat_u_add_imm##IMM##_##T##_fmt_2 (T x) \
+{ \
+ return (T)(x + IMM) < x ? -1 : (x + IMM); \
+}
+
#define RUN_SAT_U_ADD_IMM_FMT_1(T, x, IMM, expect) \
if (sat_u_add_imm##IMM##_##T##_fmt_1(x) != expect) __builtin_abort ()
+#define RUN_SAT_U_ADD_IMM_FMT_2(T, x, IMM, expect) \
+ if (sat_u_add_imm##IMM##_##T##_fmt_2(x) != expect) __builtin_abort ()
+
/**/
/* Saturation Sub (Unsigned and Signed)
*/
/**/
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-5.c
b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-5.c
new file mode 100644
index 000..19b502db6c9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-5.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details
-fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_add_imm9_uint8_t_fmt_2:
+** addi\s+[atx][0-9]+,\s*a0,\s*9
+** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*0xff
+** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** neg\s+[atx][0-9]+,\s*[atx][0-9]+
+** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** andi\s+a0,\s*a0,\s*0xff
+** ret
+*/
+DEF_SAT_U_ADD_IMM_FMT_2(uint8_t, 9)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-6.c
b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-6.c
new file mode 100644
index 000..0317370b67e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-6.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details
-fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_add_imm3_uint16_t_fmt_2:
+** addi\s+[atx][0-9]+,\s*a0,\s*3
+** slli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*48
+** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*48
+** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** neg\s+[atx][0-9]+,\s*[atx][0-9]+
+** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** slli\s+a0,\s*a0,\s*48
+** srli\s+a0,\s*a0,\s*48
+** ret
+*/
+DEF_SAT_U_ADD_IMM_FMT_2(uint16_t, 3)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD "
[gcc r15-1755] RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM form 3
https://gcc.gnu.org/g:6d98e88f61f9b2e6864775ce390e9ce0a1359624
commit r15-1755-g6d98e88f61f9b2e6864775ce390e9ce0a1359624
Author: Pan Li
Date: Sun Jun 30 16:41:16 2024 +0800
RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM form 3
This patch would like to add test cases for the unsigned scalar
.SAT_ADD IMM form 3. Aka:
Form 3:
#define DEF_SAT_U_ADD_IMM_FMT_3(T) \
T __attribute__((noinline)) \
sat_u_add_imm_##T##_fmt_3 (T x) \
{\
T ret; \
return __builtin_add_overflow (x, 8, &ret) ? -1 : ret; \
}
DEF_SAT_U_ADD_IMM_FMT_3(uint64_t)
The below test is passed for this patch.
* The rv64gcv regression test.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/sat_arith.h: Add helper test macro.
* gcc.target/riscv/sat_u_add_imm-10.c: New test.
* gcc.target/riscv/sat_u_add_imm-11.c: New test.
* gcc.target/riscv/sat_u_add_imm-12.c: New test.
* gcc.target/riscv/sat_u_add_imm-9.c: New test.
* gcc.target/riscv/sat_u_add_imm-run-10.c: New test.
* gcc.target/riscv/sat_u_add_imm-run-11.c: New test.
* gcc.target/riscv/sat_u_add_imm-run-12.c: New test.
* gcc.target/riscv/sat_u_add_imm-run-9.c: New test.
Signed-off-by: Pan Li
Diff:
---
gcc/testsuite/gcc.target/riscv/sat_arith.h | 11 ++
gcc/testsuite/gcc.target/riscv/sat_u_add_imm-10.c | 21 ++
gcc/testsuite/gcc.target/riscv/sat_u_add_imm-11.c | 18 +
gcc/testsuite/gcc.target/riscv/sat_u_add_imm-12.c | 17
gcc/testsuite/gcc.target/riscv/sat_u_add_imm-9.c | 19 +
.../gcc.target/riscv/sat_u_add_imm-run-10.c| 46 ++
.../gcc.target/riscv/sat_u_add_imm-run-11.c| 46 ++
.../gcc.target/riscv/sat_u_add_imm-run-12.c| 46 ++
.../gcc.target/riscv/sat_u_add_imm-run-9.c | 46 ++
9 files changed, 270 insertions(+)
diff --git a/gcc/testsuite/gcc.target/riscv/sat_arith.h
b/gcc/testsuite/gcc.target/riscv/sat_arith.h
index d94f0fd602c..83b294db476 100644
--- a/gcc/testsuite/gcc.target/riscv/sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/sat_arith.h
@@ -74,12 +74,23 @@ sat_u_add_imm##IMM##_##T##_fmt_2 (T x) \
return (T)(x + IMM) < x ? -1 : (x + IMM); \
}
+#define DEF_SAT_U_ADD_IMM_FMT_3(T, IMM)\
+T __attribute__((noinline))\
+sat_u_add_imm##IMM##_##T##_fmt_3 (T x) \
+{ \
+ T ret; \
+ return __builtin_add_overflow (x, IMM, &ret) ? -1 : ret; \
+}
+
#define RUN_SAT_U_ADD_IMM_FMT_1(T, x, IMM, expect) \
if (sat_u_add_imm##IMM##_##T##_fmt_1(x) != expect) __builtin_abort ()
#define RUN_SAT_U_ADD_IMM_FMT_2(T, x, IMM, expect) \
if (sat_u_add_imm##IMM##_##T##_fmt_2(x) != expect) __builtin_abort ()
+#define RUN_SAT_U_ADD_IMM_FMT_3(T, x, IMM, expect) \
+ if (sat_u_add_imm##IMM##_##T##_fmt_3(x) != expect) __builtin_abort ()
+
/**/
/* Saturation Sub (Unsigned and Signed)
*/
/**/
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-10.c
b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-10.c
new file mode 100644
index 000..24cdd267cca
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-10.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details
-fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_add_imm3_uint16_t_fmt_3:
+** addi\s+[atx][0-9]+,\s*a0,\s*3
+** slli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*48
+** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*48
+** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** neg\s+[atx][0-9]+,\s*[atx][0-9]+
+** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** slli\s+a0,\s*a0,\s*48
+** srli\s+a0,\s*a0,\s*48
+** ret
+*/
+DEF_SAT_U_ADD_IMM_FMT_3(uint16_t, 3)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-11.c
b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-11.c
new file mode 100644
index 000..f30e2405a0d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-11.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details
-fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "
[gcc r15-1756] RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM form 4
https://gcc.gnu.org/g:7a65ab6b5f38d3018ffd456f278a9fd885487a27
commit r15-1756-g7a65ab6b5f38d3018ffd456f278a9fd885487a27
Author: Pan Li
Date: Sun Jun 30 16:48:19 2024 +0800
RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM form 4
This patch would like to add test cases for the unsigned scalar
.SAT_ADD IMM form 4. Aka:
Form 4:
#define DEF_SAT_U_ADD_IMM_FMT_4(T)\
T __attribute__((noinline)) \
sat_u_add_imm_##T##_fmt_4 (T x) \
{ \
T ret; \
return __builtin_add_overflow (x, 9, &ret) == 0 ? ret : -1; \
}
DEF_SAT_U_ADD_IMM_FMT_4(uint64_t)
The below test is passed for this patch.
* The rv64gcv regression test.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/sat_arith.h: Add helper test macro.
* gcc.target/riscv/sat_u_add_imm-13.c: New test.
* gcc.target/riscv/sat_u_add_imm-14.c: New test.
* gcc.target/riscv/sat_u_add_imm-15.c: New test.
* gcc.target/riscv/sat_u_add_imm-16.c: New test.
* gcc.target/riscv/sat_u_add_imm-run-13.c: New test.
* gcc.target/riscv/sat_u_add_imm-run-14.c: New test.
* gcc.target/riscv/sat_u_add_imm-run-15.c: New test.
* gcc.target/riscv/sat_u_add_imm-run-16.c: New test.
Signed-off-by: Pan Li
Diff:
---
gcc/testsuite/gcc.target/riscv/sat_arith.h | 11 ++
gcc/testsuite/gcc.target/riscv/sat_u_add_imm-13.c | 19 +
gcc/testsuite/gcc.target/riscv/sat_u_add_imm-14.c | 21 ++
gcc/testsuite/gcc.target/riscv/sat_u_add_imm-15.c | 18 +
gcc/testsuite/gcc.target/riscv/sat_u_add_imm-16.c | 17
.../gcc.target/riscv/sat_u_add_imm-run-13.c| 46 ++
.../gcc.target/riscv/sat_u_add_imm-run-14.c| 46 ++
.../gcc.target/riscv/sat_u_add_imm-run-15.c| 46 ++
.../gcc.target/riscv/sat_u_add_imm-run-16.c| 46 ++
9 files changed, 270 insertions(+)
diff --git a/gcc/testsuite/gcc.target/riscv/sat_arith.h
b/gcc/testsuite/gcc.target/riscv/sat_arith.h
index 83b294db476..75442c94dc1 100644
--- a/gcc/testsuite/gcc.target/riscv/sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/sat_arith.h
@@ -82,6 +82,14 @@ sat_u_add_imm##IMM##_##T##_fmt_3 (T x) \
return __builtin_add_overflow (x, IMM, &ret) ? -1 : ret; \
}
+#define DEF_SAT_U_ADD_IMM_FMT_4(T, IMM) \
+T __attribute__((noinline)) \
+sat_u_add_imm##IMM##_##T##_fmt_4 (T x) \
+{ \
+ T ret;\
+ return __builtin_add_overflow (x, IMM, &ret) == 0 ? ret : -1; \
+}
+
#define RUN_SAT_U_ADD_IMM_FMT_1(T, x, IMM, expect) \
if (sat_u_add_imm##IMM##_##T##_fmt_1(x) != expect) __builtin_abort ()
@@ -91,6 +99,9 @@ sat_u_add_imm##IMM##_##T##_fmt_3 (T x) \
#define RUN_SAT_U_ADD_IMM_FMT_3(T, x, IMM, expect) \
if (sat_u_add_imm##IMM##_##T##_fmt_3(x) != expect) __builtin_abort ()
+#define RUN_SAT_U_ADD_IMM_FMT_4(T, x, IMM, expect) \
+ if (sat_u_add_imm##IMM##_##T##_fmt_4(x) != expect) __builtin_abort ()
+
/**/
/* Saturation Sub (Unsigned and Signed)
*/
/**/
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-13.c
b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-13.c
new file mode 100644
index 000..a3b2679233c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-13.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details
-fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_add_imm9_uint8_t_fmt_4:
+** addi\s+[atx][0-9]+,\s*a0,\s*9
+** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*0xff
+** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** neg\s+[atx][0-9]+,\s*[atx][0-9]+
+** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** andi\s+a0,\s*a0,\s*0xff
+** ret
+*/
+DEF_SAT_U_ADD_IMM_FMT_4(uint8_t, 9)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-14.c
b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-14.c
new file mode 100644
index 000..968534b74da
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-14.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-e
[gcc r15-1757] Preserve SSA info for more propagated copy
https://gcc.gnu.org/g:4d24159a1fcb15e1e28f46aa418de5e1ae384ff5 commit r15-1757-g4d24159a1fcb15e1e28f46aa418de5e1ae384ff5 Author: Richard Biener Date: Sun Jun 30 11:37:12 2024 +0200 Preserve SSA info for more propagated copy Besides VN and copy-prop also CCP and VRP as well as forwprop propagate out copies and thus it's worthwhile to try to preserve range and points-to info there when possible. Note that this also fixes the testcase from PR115701 but that's because we do not actually intersect info but only copy info when there was no info present. * tree-ssa-forwprop.cc (fwprop_set_lattice_val): Preserve SSA info. * tree-ssa-propagate.cc (substitute_and_fold_dom_walker::before_dom_children): Likewise. Diff: --- gcc/tree-ssa-forwprop.cc | 4 gcc/tree-ssa-propagate.cc | 8 2 files changed, 12 insertions(+) diff --git a/gcc/tree-ssa-forwprop.cc b/gcc/tree-ssa-forwprop.cc index abf71f0d3a0..44a6b5d39aa 100644 --- a/gcc/tree-ssa-forwprop.cc +++ b/gcc/tree-ssa-forwprop.cc @@ -207,6 +207,10 @@ fwprop_set_lattice_val (tree name, tree val) lattice.quick_grow_cleared (num_ssa_names); } lattice[SSA_NAME_VERSION (name)] = val; + /* As this now constitutes a copy duplicate points-to +and range info appropriately. */ + if (TREE_CODE (val) == SSA_NAME) + maybe_duplicate_ssa_info_at_copy (name, val); } } diff --git a/gcc/tree-ssa-propagate.cc b/gcc/tree-ssa-propagate.cc index a34c7618b55..d96d0a9fe19 100644 --- a/gcc/tree-ssa-propagate.cc +++ b/gcc/tree-ssa-propagate.cc @@ -789,6 +789,10 @@ substitute_and_fold_dom_walker::before_dom_children (basic_block bb) fprintf (dump_file, "\n"); } bitmap_set_bit (dceworklist, SSA_NAME_VERSION (res)); + /* As this now constitutes a copy duplicate points-to +and range info appropriately. */ + if (TREE_CODE (sprime) == SSA_NAME) + maybe_duplicate_ssa_info_at_copy (res, sprime); continue; } } @@ -831,6 +835,10 @@ substitute_and_fold_dom_walker::before_dom_children (basic_block bb) fprintf (dump_file, "\n"); } bitmap_set_bit (dceworklist, SSA_NAME_VERSION (lhs)); + /* As this now constitutes a copy duplicate points-to +and range info appropriately. */ + if (TREE_CODE (sprime) == SSA_NAME) + maybe_duplicate_ssa_info_at_copy (lhs, sprime); continue; } }
[gcc r15-1758] c++: DR2627, Bit-fields and narrowing conversions [PR94058]
https://gcc.gnu.org/g:52d71b6b1f0f465a6cf064f61b22fc99453ec132
commit r15-1758-g52d71b6b1f0f465a6cf064f61b22fc99453ec132
Author: Marek Polacek
Date: Fri Jun 28 17:51:19 2024 -0400
c++: DR2627, Bit-fields and narrowing conversions [PR94058]
This DR (https://cplusplus.github.io/CWG/issues/2627.html) says that
even if we are converting from an integer type or unscoped enumeration type
to an integer type that cannot represent all the values of the original
type, it's not narrowing if "the source is a bit-field whose width w is
less than that of its type (or, for an enumeration type, its underlying
type) and the target type can represent all the values of a hypothetical
extended integer type with width w and with the same signedness as the
original type".
DR 2627
PR c++/94058
PR c++/104392
gcc/cp/ChangeLog:
* typeck2.cc (check_narrowing): Don't warn if the conversion isn't
narrowing as per DR 2627.
gcc/testsuite/ChangeLog:
* g++.dg/DRs/dr2627.C: New test.
* g++.dg/cpp0x/Wnarrowing22.C: New test.
* g++.dg/cpp2a/spaceship-narrowing1.C: New test.
* g++.dg/cpp2a/spaceship-narrowing2.C: New test.
Diff:
---
gcc/cp/typeck2.cc | 12 ++
gcc/testsuite/g++.dg/DRs/dr2627.C | 13 ++
gcc/testsuite/g++.dg/cpp0x/Wnarrowing22.C | 49 +++
gcc/testsuite/g++.dg/cpp2a/spaceship-narrowing1.C | 34
gcc/testsuite/g++.dg/cpp2a/spaceship-narrowing2.C | 26
5 files changed, 134 insertions(+)
diff --git a/gcc/cp/typeck2.cc b/gcc/cp/typeck2.cc
index 7782f38da43..30a6fbe95c9 100644
--- a/gcc/cp/typeck2.cc
+++ b/gcc/cp/typeck2.cc
@@ -1012,6 +1012,18 @@ check_narrowing (tree type, tree init, tsubst_flags_t
complain,
if (TREE_CODE (ftype) == ENUMERAL_TYPE)
/* Check for narrowing based on the values of the enumeration. */
ftype = ENUM_UNDERLYING_TYPE (ftype);
+ /* Undo convert_bitfield_to_declared_type (STRIP_NOPS isn't enough). */
+ tree op = init;
+ while (CONVERT_EXPR_P (op))
+ op = TREE_OPERAND (op, 0);
+ /* Core 2627 says that we shouldn't warn when "the source is a bit-field
+whose width w is less than that of its type (or, for an enumeration
+type, its underlying type) and the target type can represent all the
+values of a hypothetical extended integer type with width w and with
+the same signedness as the original type". */
+ if (is_bitfield_expr_with_lowered_type (op)
+ && TYPE_PRECISION (TREE_TYPE (op)) < TYPE_PRECISION (ftype))
+ ftype = TREE_TYPE (op);
if ((tree_int_cst_lt (TYPE_MAX_VALUE (type),
TYPE_MAX_VALUE (ftype))
|| tree_int_cst_lt (TYPE_MIN_VALUE (ftype),
diff --git a/gcc/testsuite/g++.dg/DRs/dr2627.C
b/gcc/testsuite/g++.dg/DRs/dr2627.C
new file mode 100644
index 000..fe7f28613ca
--- /dev/null
+++ b/gcc/testsuite/g++.dg/DRs/dr2627.C
@@ -0,0 +1,13 @@
+// DR 2627 - Bit-fields and narrowing conversions
+// { dg-do compile { target c++20 } }
+
+#include
+
+struct C {
+ long long i : 8;
+};
+
+void f() {
+ C x{1}, y{2};
+ x.i <=> y.i;
+}
diff --git a/gcc/testsuite/g++.dg/cpp0x/Wnarrowing22.C
b/gcc/testsuite/g++.dg/cpp0x/Wnarrowing22.C
new file mode 100644
index 000..dd30451a7cc
--- /dev/null
+++ b/gcc/testsuite/g++.dg/cpp0x/Wnarrowing22.C
@@ -0,0 +1,49 @@
+// DR 2627 - Bit-fields and narrowing conversions
+// PR c++/94058
+// { dg-do compile { target c++11 } }
+// { dg-options "-Wno-error=narrowing" }
+
+using int64_t = __INT64_TYPE__;
+using int32_t = __INT32_TYPE__;
+
+struct A {
+ int64_t i1 : __CHAR_BIT__;
+ int64_t i2 : sizeof (int32_t) * __CHAR_BIT__ - 1;
+ int64_t i3 : sizeof (int32_t) * __CHAR_BIT__;
+ int64_t i4 : sizeof (int32_t) * __CHAR_BIT__ + 1;
+ int64_t i5 : sizeof (int64_t) * __CHAR_BIT__ - 1;
+ int64_t i6 : sizeof (int64_t) * __CHAR_BIT__;
+} a;
+
+int32_t i1{a.i1};
+int32_t i2{a.i2};
+int32_t i3{a.i3};
+int32_t i4{a.i4}; // { dg-warning "narrowing conversion" }
+int32_t i5{a.i5}; // { dg-warning "narrowing conversion" }
+int32_t i6{a.i6}; // { dg-warning "narrowing conversion" }
+
+struct B {
+ bool b1 : sizeof (bool) * __CHAR_BIT__;
+ bool b2 : sizeof (bool);
+} b;
+
+signed char b1{b.b1};
+signed char b2{b.b2};
+
+enum E : int64_t { E1 };
+
+struct C {
+ E e1 : __CHAR_BIT__;
+ E e2 : sizeof (int32_t) * __CHAR_BIT__ - 1;
+ E e3 : sizeof (int32_t) * __CHAR_BIT__;
+ E e4 : sizeof (int32_t) * __CHAR_BIT__ + 1;
+ E e5 : sizeof (int64_t) * __CHAR_BIT__ - 1;
+ E e6 : sizeof (int64_t) * __CHAR_BIT__;
+} c;
+
+int32_t e1{c.e1};
+int32_t e2{c.e2};
+int32_t e3{c.e3};
+int32_t e4{c.e4}; // { dg-warning "narrowing conversion" }
+int32_t e5{c.e5}; // { dg-warning "narrowing conversion" }
+int32_t e6{c.e6}; // { dg-warning "narrowing conversion
[gcc r15-1759] c++: unresolved overload with comma op [PR115430]
https://gcc.gnu.org/g:c847dcf94499da62e5a28921b404e6e561645d99
commit r15-1759-gc847dcf94499da62e5a28921b404e6e561645d99
Author: Marek Polacek
Date: Tue Jun 25 17:42:01 2024 -0400
c++: unresolved overload with comma op [PR115430]
This works:
template
int Func(T);
typedef int (*funcptrtype)(int);
funcptrtype fp0 = &Func;
but this doesn't:
funcptrtype fp2 = (0, &Func);
because we only call resolve_nondeduced_context on the LHS (via
convert_to_void) but not on the RHS, so cp_build_compound_expr's
type_unknown_p check issues an error.
PR c++/115430
gcc/cp/ChangeLog:
* typeck.cc (cp_build_compound_expr): Call
resolve_nondeduced_context
on RHS.
gcc/testsuite/ChangeLog:
* g++.dg/cpp0x/noexcept41.C: Remove dg-error.
* g++.dg/overload/addr3.C: New test.
Diff:
---
gcc/cp/typeck.cc| 4 +++-
gcc/testsuite/g++.dg/cpp0x/noexcept41.C | 2 +-
gcc/testsuite/g++.dg/overload/addr3.C | 24
3 files changed, 28 insertions(+), 2 deletions(-)
diff --git a/gcc/cp/typeck.cc b/gcc/cp/typeck.cc
index 50f48768a95..55ee867d329 100644
--- a/gcc/cp/typeck.cc
+++ b/gcc/cp/typeck.cc
@@ -8157,6 +8157,8 @@ cp_build_compound_expr (tree lhs, tree rhs,
tsubst_flags_t complain)
return rhs;
}
+ rhs = resolve_nondeduced_context (rhs, complain);
+
if (type_unknown_p (rhs))
{
if (complain & tf_error)
@@ -8164,7 +8166,7 @@ cp_build_compound_expr (tree lhs, tree rhs,
tsubst_flags_t complain)
"no context to resolve type of %qE", rhs);
return error_mark_node;
}
-
+
tree ret = build2 (COMPOUND_EXPR, TREE_TYPE (rhs), lhs, rhs);
if (eptype)
ret = build1 (EXCESS_PRECISION_EXPR, eptype, ret);
diff --git a/gcc/testsuite/g++.dg/cpp0x/noexcept41.C
b/gcc/testsuite/g++.dg/cpp0x/noexcept41.C
index 4cd3d8d7854..7c65cebb618 100644
--- a/gcc/testsuite/g++.dg/cpp0x/noexcept41.C
+++ b/gcc/testsuite/g++.dg/cpp0x/noexcept41.C
@@ -9,4 +9,4 @@ template struct a {
};
template auto f(d &&, c &&) -> decltype(declval);
struct e {};
-static_assert((e{}, declval>),""); // { dg-error "no context to resolve
type" }
+static_assert((e{}, declval>),"");
diff --git a/gcc/testsuite/g++.dg/overload/addr3.C
b/gcc/testsuite/g++.dg/overload/addr3.C
new file mode 100644
index 000..b203326de32
--- /dev/null
+++ b/gcc/testsuite/g++.dg/overload/addr3.C
@@ -0,0 +1,24 @@
+// PR c++/115430
+// { dg-do compile }
+
+template
+int Func(T);
+typedef int (*funcptrtype)(int);
+funcptrtype fp0 = &Func;
+funcptrtype fp1 = +&Func;
+funcptrtype fp2 = (0, &Func);
+funcptrtype fp3 = (0, +&Func);
+funcptrtype fp4 = (0, 1, &Func);
+
+template
+void
+g ()
+{
+ funcptrtype fp5 = (0, &Func);
+}
+
+void
+f ()
+{
+ g();
+}
[gcc r15-1760] testsuite: fix spaceship-narrowing1.C
https://gcc.gnu.org/g:cb39f7df8d1c16cc2763952a9cc0c828ba88b4d7
commit r15-1760-gcb39f7df8d1c16cc2763952a9cc0c828ba88b4d7
Author: Marek Polacek
Date: Mon Jul 1 18:12:31 2024 -0400
testsuite: fix spaceship-narrowing1.C
I made sure that Wnarrowing22.C works fine on ILP32, but apparently
I didn't verify that spaceship-narrowing1.C works there as well. :(
gcc/testsuite/ChangeLog:
* g++.dg/cpp2a/spaceship-narrowing1.C: Use __INT64_TYPE__.
Diff:
---
gcc/testsuite/g++.dg/cpp2a/spaceship-narrowing1.C | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/testsuite/g++.dg/cpp2a/spaceship-narrowing1.C
b/gcc/testsuite/g++.dg/cpp2a/spaceship-narrowing1.C
index 7769f950bed..9f2ff3ceae4 100644
--- a/gcc/testsuite/g++.dg/cpp2a/spaceship-narrowing1.C
+++ b/gcc/testsuite/g++.dg/cpp2a/spaceship-narrowing1.C
@@ -16,7 +16,7 @@ constexpr strong_ordering strong_ordering::greater = 1;
}
struct A {
- long i : 48;
+ __INT64_TYPE__ i : 48;
auto operator <=> (const A&) const = default;
};
[gcc r15-1761] c++: ICE with computed gotos [PR115469]
https://gcc.gnu.org/g:c90e785bb6fde02cc009f296332a1469fcc1261a
commit r15-1761-gc90e785bb6fde02cc009f296332a1469fcc1261a
Author: Marek Polacek
Date: Wed Jun 26 17:55:21 2024 -0400
c++: ICE with computed gotos [PR115469]
This is a low-prio crash on invalid code where we ICE on a VAR_DECL
with erroneous type. I thought I'd try to avoid putting such decls
into ->names and ->names_in_scope but that sounds riskier than the
following cleanup.
PR c++/115469
gcc/cp/ChangeLog:
* decl.cc (automatic_var_with_nontrivial_dtor_p): New.
(poplevel_named_label_1): Use it.
(check_goto_1): Likewise.
gcc/testsuite/ChangeLog:
* g++.dg/ext/label17.C: New test.
Diff:
---
gcc/cp/decl.cc | 20
gcc/testsuite/g++.dg/ext/label17.C | 18 ++
2 files changed, 34 insertions(+), 4 deletions(-)
diff --git a/gcc/cp/decl.cc b/gcc/cp/decl.cc
index 03deb1493a4..c7457fae7b0 100644
--- a/gcc/cp/decl.cc
+++ b/gcc/cp/decl.cc
@@ -514,6 +514,20 @@ level_for_consteval_if (cp_binding_level *b)
&& IF_STMT_CONSTEVAL_P (b->this_entity));
}
+/* True if T is a non-static VAR_DECL that has a non-trivial destructor.
+ See [stmt.dcl]/2. */
+
+static bool
+automatic_var_with_nontrivial_dtor_p (const_tree t)
+{
+ if (error_operand_p (t))
+return false;
+
+ return (VAR_P (t)
+ && decl_storage_duration (CONST_CAST_TREE (t)) == dk_auto
+ && TYPE_HAS_NONTRIVIAL_DESTRUCTOR (TREE_TYPE (t)));
+}
+
/* Update data for defined and undefined labels when leaving a scope. */
int
@@ -575,8 +589,7 @@ poplevel_named_label_1 (named_label_entry **slot,
cp_binding_level *bl)
if (bl->kind == sk_catch)
vec_safe_push (cg, get_identifier ("catch"));
for (tree d = use->names_in_scope; d; d = DECL_CHAIN (d))
- if (TREE_CODE (d) == VAR_DECL && !TREE_STATIC (d)
- && TYPE_HAS_NONTRIVIAL_DESTRUCTOR (TREE_TYPE (d)))
+ if (automatic_var_with_nontrivial_dtor_p (d))
vec_safe_push (cg, d);
}
@@ -4003,8 +4016,7 @@ check_goto_1 (named_label_entry *ent, bool computed)
tree end = b == level ? names : NULL_TREE;
for (tree d = b->names; d != end; d = DECL_CHAIN (d))
{
- if (TREE_CODE (d) == VAR_DECL && !TREE_STATIC (d)
- && TYPE_HAS_NONTRIVIAL_DESTRUCTOR (TREE_TYPE (d)))
+ if (automatic_var_with_nontrivial_dtor_p (d))
{
if (!identified)
{
diff --git a/gcc/testsuite/g++.dg/ext/label17.C
b/gcc/testsuite/g++.dg/ext/label17.C
new file mode 100644
index 000..076ef1f798e
--- /dev/null
+++ b/gcc/testsuite/g++.dg/ext/label17.C
@@ -0,0 +1,18 @@
+// PR c++/115469
+// { dg-do compile { target indirect_jumps } }
+// { dg-options "" }
+
+void
+fn1 ()
+{
+ b = &&c;// { dg-error "not declared|not defined" }
+ goto *0;
+}
+
+void
+fn2 ()
+{
+c:
+ b = &&c; // { dg-error "not declared" }
+ goto *0;
+}
[gcc/aoliva/heads/testme] (3 commits) UI_To_gnu: cope with per-target precision limits
The branch 'aoliva/heads/testme' was updated to point to: 18cdf562ea2... UI_To_gnu: cope with per-target precision limits It previously pointed to: 03263dba590... [dwarf] get_debug_type of qualified_type Diff: !!! WARNING: THE FOLLOWING COMMITS ARE NO LONGER ACCESSIBLE (LOST): --- 03263db... [dwarf] get_debug_type of qualified_type Summary of changes (added commits): --- 18cdf56... UI_To_gnu: cope with per-target precision limits f216931... Introduce general caching of sized type 0a9b788... [dwarf] get_debug_type of TYPE_NAME to compare with qualifi
[gcc(refs/users/aoliva/heads/testme)] Introduce general caching of sized type
https://gcc.gnu.org/g:f216931275ed5b4244964ede0739e8c7e3cdd624
commit f216931275ed5b4244964ede0739e8c7e3cdd624
Author: Alexandre Oliva
Date: Mon Jul 1 22:17:10 2024 -0300
Introduce general caching of sized type
The simplified form of caching, in TYPE_DEBUG_TYPE, didn't work on
big-endian targets, so introduce general caching for sized integral
types, modeled after caching of packable types.
for gcc/ada/ChangeLog
* gcc-interface/utils.cc (sized_type_hash): New struct.
(sized_type_hasher): New struct.
(sized_type_hash_table): New variable.
(init_gnat_utils): Allocate it.
(destroy_gnat_utils): Release it.
(sized_type_hasher::equal): New.
(hash_sized_type): New.
(canonicalize_sized_type): New.
(make_type_from_size): Use it, instead of
TYPE_DEBUG_TYPE-based caching.
Diff:
---
gcc/ada/gcc-interface/utils.cc | 124 ++---
1 file changed, 103 insertions(+), 21 deletions(-)
diff --git a/gcc/ada/gcc-interface/utils.cc b/gcc/ada/gcc-interface/utils.cc
index b46e035e1d4..66e3192ea4f 100644
--- a/gcc/ada/gcc-interface/utils.cc
+++ b/gcc/ada/gcc-interface/utils.cc
@@ -364,6 +364,26 @@ struct pad_type_hasher : ggc_cache_ptr_hash
static GTY ((cache)) hash_table *pad_type_hash_table;
+struct GTY((for_user)) sized_type_hash
+{
+ hashval_t hash;
+ tree type;
+};
+
+struct sized_type_hasher : ggc_cache_ptr_hash
+{
+ static inline hashval_t hash (sized_type_hash *t) { return t->hash; }
+ static bool equal (sized_type_hash *a, sized_type_hash *b);
+
+ static int
+ keep_cache_entry (sized_type_hash *&t)
+ {
+return ggc_marked_p (t->type);
+ }
+};
+
+static GTY ((cache)) hash_table *sized_type_hash_table;
+
static tree merge_sizes (tree, tree, tree, bool, bool);
static tree fold_bit_position (const_tree);
static tree compute_related_constant (tree, tree);
@@ -421,6 +441,9 @@ init_gnat_utils (void)
/* Initialize the hash table of padded types. */
pad_type_hash_table = hash_table::create_ggc (512);
+
+ /* Initialize the hash table of sized types. */
+ sized_type_hash_table = hash_table::create_ggc (512);
}
/* Destroy data structures of the utils.cc module. */
@@ -443,6 +466,10 @@ destroy_gnat_utils (void)
/* Destroy the hash table of padded types. */
pad_type_hash_table->empty ();
pad_type_hash_table = NULL;
+
+ /* Destroy the hash table of sized types. */
+ sized_type_hash_table->empty ();
+ sized_type_hash_table = NULL;
}
/* GNAT_ENTITY is a GNAT tree node for an entity. Associate GNU_DECL, a GCC
@@ -1350,6 +1377,79 @@ type_unsigned_for_rm (tree type)
return false;
}
+/* Return true iff the sized types are equivalent. */
+
+bool
+sized_type_hasher::equal (sized_type_hash *t1, sized_type_hash *t2)
+{
+ tree type1, type2;
+
+ if (t1->hash != t2->hash)
+return false;
+
+ type1 = t1->type;
+ type2 = t2->type;
+
+ /* We consider sized types equivalent if they have the same name,
+ size, alignment, RM size, and biasing. The range is not expected
+ to vary across different-sized versions of the same base
+ type. */
+ bool res
+= (TYPE_NAME (type1) == TYPE_NAME (type2)
+ && TYPE_SIZE (type1) == TYPE_SIZE (type2)
+ && TYPE_ALIGN (type1) == TYPE_ALIGN (type2)
+ && TYPE_RM_SIZE (type1) == TYPE_RM_SIZE (type2)
+ && (TYPE_BIASED_REPRESENTATION_P (type1)
+ == TYPE_BIASED_REPRESENTATION_P (type2)));
+
+ gcc_assert (!res
+ || (TYPE_RM_MIN_VALUE (type1) == TYPE_RM_MIN_VALUE (type2)
+ && TYPE_RM_MAX_VALUE (type1) == TYPE_RM_MAX_VALUE (type2)));
+
+ return res;
+}
+
+/* Compute the hash value for the sized TYPE. */
+
+static hashval_t
+hash_sized_type (tree type)
+{
+ hashval_t hashcode;
+
+ hashcode = iterative_hash_expr (TYPE_NAME (type), 0);
+ hashcode = iterative_hash_expr (TYPE_SIZE (type), hashcode);
+ hashcode = iterative_hash_hashval_t (TYPE_ALIGN (type), hashcode);
+ hashcode = iterative_hash_expr (TYPE_RM_SIZE (type), hashcode);
+ hashcode
+= iterative_hash_hashval_t (TYPE_BIASED_REPRESENTATION_P (type), hashcode);
+
+ return hashcode;
+}
+
+/* Look up the sized TYPE in the hash table and return its canonical version
+ if it exists; otherwise, insert it into the hash table. */
+
+static tree
+canonicalize_sized_type (tree type)
+{
+ const hashval_t hashcode = hash_sized_type (type);
+ struct sized_type_hash in, *h, **slot;
+
+ in.hash = hashcode;
+ in.type = type;
+ slot = sized_type_hash_table->find_slot_with_hash (&in, hashcode, INSERT);
+ h = *slot;
+ if (!h)
+{
+ h = ggc_alloc ();
+ h->hash = hashcode;
+ h->type = type;
+ *slot = h;
+}
+
+ return h->type;
+}
+
/* Given a type TYPE, return a new type whose size is appropriate for SIZE.
If TYPE is the best type, return it. Otherwise, make a new type. We
only support new inte
[gcc(refs/users/aoliva/heads/testme)] [dwarf] get_debug_type of TYPE_NAME to compare with qualified_type
https://gcc.gnu.org/g:0a9b788f27514fe72c539de8a58f6d6cb6e2e97f
commit 0a9b788f27514fe72c539de8a58f6d6cb6e2e97f
Author: Alexandre Oliva
Date: Fri Jun 28 08:13:52 2024 -0300
[dwarf] get_debug_type of TYPE_NAME to compare with qualified_type
When we choose the narrower/packed variant of a type as the main debug
info type, we fail to output its name if we fail to follow
debug type for the TYPE_NAME decl type in modified_type_die.
for gcc/ChangeLog
* dwarf2out.cc (modified_type_die): Follow name's debug type.
Diff:
---
gcc/dwarf2out.cc | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/gcc/dwarf2out.cc b/gcc/dwarf2out.cc
index f463435e446..5ce1a3e6f66 100644
--- a/gcc/dwarf2out.cc
+++ b/gcc/dwarf2out.cc
@@ -14051,8 +14051,11 @@ modified_type_die (tree type, int cv_quals, bool
reverse,
&& (qualified_type == TYPE_MAIN_VARIANT (type)
|| (cv_quals == TYPE_UNQUALIFIED)))
|| (TREE_CODE (name) == TYPE_DECL
- && TREE_TYPE (name) == qualified_type
- && DECL_NAME (name
+ && DECL_NAME (name)
+ && (TREE_TYPE (name) == qualified_type
+ || (lang_hooks.types.get_debug_type
+ && (lang_hooks.types.get_debug_type (TREE_TYPE (name))
+ == qualified_type))
{
if (TREE_CODE (name) == TYPE_DECL)
/* Could just call add_name_and_src_coords_attributes here,
[gcc(refs/users/aoliva/heads/testme)] UI_To_gnu: cope with per-target precision limits
https://gcc.gnu.org/g:18cdf562ea2ae6b43df502e5ebb043f40d531884
commit 18cdf562ea2ae6b43df502e5ebb043f40d531884
Author: Alexandre Oliva
Date: Mon Jul 1 22:17:45 2024 -0300
UI_To_gnu: cope with per-target precision limits
Avoid exceeding the maximum precision for wide ints, and for available
int modes, when selecting a type to represent very wide constants,
falling back to 0/0 for unrepresentable fractions.
for gcc/ada/ChangeLog
* gcc-interface/cuintp.cc (UI_To_gnu): Don't exceed available
integral mode widths. Fail if the constant exceeds the
representable numbers.
* gcc-interface/decl.cc (gnat_to_gnu_entity): Recognize the
failure mode and fall back to an indeterminate fraction.
Diff:
---
gcc/ada/gcc-interface/cuintp.cc | 40
gcc/ada/gcc-interface/decl.cc | 4
2 files changed, 32 insertions(+), 12 deletions(-)
diff --git a/gcc/ada/gcc-interface/cuintp.cc b/gcc/ada/gcc-interface/cuintp.cc
index ad345096282..6a03131144b 100644
--- a/gcc/ada/gcc-interface/cuintp.cc
+++ b/gcc/ada/gcc-interface/cuintp.cc
@@ -69,7 +69,8 @@ build_cst_from_int (tree type, HOST_WIDE_INT low)
depending on whether TYPE is an integral or real type. Overflow is tested
by the constant-folding used to build the node. TYPE is the GCC type of
the resulting node. If TYPE is NULL, an unsigned integer type wide enough
- to hold the entire constant is selected. */
+ to hold the entire constant is selected, and if no such type exists,
+ return NULL_TREE. */
tree
UI_To_gnu (Uint Input, tree type)
@@ -79,7 +80,7 @@ UI_To_gnu (Uint Input, tree type)
any such possible value for intermediate computations and then rely on a
conversion back to TYPE to perform the bias adjustment when need be. */
tree comp_type
-= (!type ? gnat_type_for_size (32, 0)
+= (!type ? gnat_type_for_size (32, 1)
: (TREE_CODE (type) == INTEGER_TYPE
&& TYPE_BIASED_REPRESENTATION_P (type))
? get_base_type (type) : type);
@@ -96,6 +97,10 @@ UI_To_gnu (Uint Input, tree type)
tree gnu_base;
gcc_assert (Length > 0);
+ /* The extension of unsigned types we use to try to fit the
+constant only works if we're dealing with nonnegative
+constants, but that's what we expect when !TYPE. */
+ gcc_assert (type || First >= 0);
/* The computations we perform below always require a type at least as
large as an integer not to overflow. FP types are always fine, but
@@ -104,9 +109,6 @@ UI_To_gnu (Uint Input, tree type)
convert the final result back to the incoming type later on. */
if (!SCALAR_FLOAT_TYPE_P (comp_type) && TYPE_PRECISION (comp_type) < 32)
comp_type = gnat_type_for_size (32, 0);
- else if (!type && TYPE_UNSIGNED (comp_type))
- /* Choose a signed type, so that we can detect overflow. */
- comp_type = make_signed_type (TYPE_PRECISION (comp_type));
gnu_base = build_cst_from_int (comp_type, Base);
@@ -114,24 +116,38 @@ UI_To_gnu (Uint Input, tree type)
for (Idx++, Length--; Length; Idx++, Length--)
for (;;)
{
- tree next_ret = fold_build2 (code, comp_type,
-fold_build2 (MULT_EXPR, comp_type,
- gnu_ret, gnu_base),
-build_cst_from_int
-(comp_type, (*Udigits_Ptr)[Idx]));
+ tree elt, scaled, next_ret;
+ elt = build_cst_from_int (comp_type, (*Udigits_Ptr)[Idx]);
+ if (!type)
+ {
+ scaled = int_const_binop (MULT_EXPR, gnu_ret, gnu_base, -1);
+ next_ret = int_const_binop (code, scaled, elt, -1);
+ }
+ else
+ {
+ scaled = fold_build2 (MULT_EXPR, comp_type, gnu_ret, gnu_base);
+ next_ret = fold_build2 (code, comp_type, scaled, elt);
+ }
if (!TREE_OVERFLOW (next_ret) || type)
{
gnu_ret = next_ret;
break;
}
- comp_type = make_signed_type (TYPE_PRECISION (comp_type) * 2);
+ opt_scalar_int_mode wider_mode
+ = GET_MODE_WIDER_MODE (SCALAR_INT_TYPE_MODE
+(comp_type)).require ();
+ if (!wider_mode.exists ())
+ /* Signal that we couldn't represent the value. */
+ return NULL_TREE;
+ comp_type = make_unsigned_type (GET_MODE_BITSIZE
+ (wider_mode.require ()));
gnu_base = convert (comp_type, gnu_base);
gnu_ret = convert (comp_type, gnu_ret);
}
}
if (!type)
-type = make_unsigned_type (TYPE_PRECISION (comp_type));
+type = comp_type;
gnu_ret = c
[gcc/meissner/heads/work169] (395 commits) Merge commit 'refs/users/meissner/heads/work169' of git+ssh
The branch 'meissner/heads/work169' was updated to point to:
bdebf88289c... Merge commit 'refs/users/meissner/heads/work169' of git+ssh
It previously pointed to:
99d2f9ee130... Add -mcpu=power11 tests.
Diff:
Summary of changes (added commits):
---
bdebf88... Merge commit 'refs/users/meissner/heads/work169' of git+ssh
31521f0... Add -mcpu=power11 tests.
0ee3bfb... Revert changes
2127f93... Update ChangeLog.*
5f1ab41... Add -mcpu=future tuning support.
c0b1d92... Add -mcpu=future support.
9a4a196... Update ChangeLog.*
66fd189... Add -mcpu=power11 tests.
bb44308... Add -mcpu=power11 tuning support.
beb2652... Add -mcpu=power11 support.
43f9e5a... Add ChangeLog.meissner and REVISION.
0b4fd67... Daily bump. (*)
c90e785... c++: ICE with computed gotos [PR115469] (*)
cb39f7d... testsuite: fix spaceship-narrowing1.C (*)
c847dcf... c++: unresolved overload with comma op [PR115430] (*)
52d71b6... c++: DR2627, Bit-fields and narrowing conversions [PR94058] (*)
4d24159... Preserve SSA info for more propagated copy (*)
7a65ab6... RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM form (*)
6d98e88... RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM form (*)
bff0d02... RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM form (*)
ed213b3... RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM form (*)
589865a... testsuite: Fix -m32 gcc.target/i386/pr102464-vrndscaleph.c (*)
142b526... i386: Additional peephole2 to use lea in round-up integer d (*)
3d23abd... AVR: target/88236, target/115726 - Fix __memx code generati (*)
90c558e... testsuite/52641 - Adjust some test cases to less capable pl (*)
6400144... libgomp, openmp: Add ompx_gnu_pinned_mem_alloc (*)
90efaeb... libgomp: change alloc-pinned tests failure mode (*)
61aa380... libffi: Fix 32-bit SPARC structure passing [PR115681] (*)
286cda3... tree-optimization/115723 - ICE with .COND_ADD reduction (*)
382e212... [MAINTAINERS] Update my email address (*)
543a5b9... tree-optimization/115694 - ICE with complex store rewrite (*)
55f80c6... Remove vcond{,u,eq} expanders since they will be obso (*)
2ccdd0f... Optimize a < 0 ? -1 : 0 to (signed)a >> 31. (*)
e94e6ee... Adjust testcase for the regressed testcases after obsolete (*)
3cb2040... Add more splitter for mskmov with avx512 comparison. (*)
09737d9... Match IEEE min/max with UNSPEC_IEEE_{MIN,MAX}. (*)
b06a108... Lower AVX512 kmask comparison back to AVX2 comparison when (*)
2e2dfa0... Add more splitters to match (unspec [op1 op2 (gt op3 constm (*)
e62ea4f... Enable flate-combine. (*)
8e1fa10... Extend lshifrtsi3_1_zext to ?k alternative. (*)
5e1a9f4... Define mask as extern instead of uninitialized local variab (*)
76075bf... Daily bump. (*)
30ad2fa... hppa: Fix ICE caused by mismatched predicate and constraint (*)
b77f17c... tree-optimization/115701 - fix maybe_duplicate_ssa_info_at_ (*)
b5c64b4... tree-optimization/115701 - factor out maybe_duplicate_ssa_i (*)
b443d71... Harden SLP reduction support wrt STMT_VINFO_REDUC_IDX (*)
3aa004f... vect: Determine input vectype for multiple lane-reducing op (*)
1ff5f8f... vect: Fix shift-by-induction for single-lane slp (*)
1bcfed4... Daily bump. (*)
69bc5fb... [PR115565] cse: Don't use a valid regno for non-register in (*)
42946aa... [to-be-committed,RISC-V,V4] movmem for RISCV with V extensi (*)
7682d11... Fortran: fix ALLOCATE with SOURCE of deferred character len (*)
21e3565... Match: Support imm form for unsigned scalar .SAT_ADD (*)
45e74d5... jit: Fix Darwin bootstrap after r15-1699. (*)
9fbbad9... [committed] Fix mcore-elf regression after recent IRA chang (*)
614fd0f... Daily bump. (*)
50073ff... c++: bad 'this' conversion for nullary memfn [PR106760] (*)
52370c8... libstdc++: Define __glibcxx_assert_fail for non-verbose bui (*)
fab60ea... libstdc++: Extend std::equal memcmp optimization to std::by (*)
03d3aeb... libstdc++: Do not use C++11 alignof in C++98 mode [PR104395 (*)
ac8c61b... libstdc++: Simplify class templates (*)
5612541... ssa_lazy_cache takes an optional bitmap_obstack pointer. (*)
7419b4f... i386: Cleanup tmp variable usage in ix86_expand_move (*)
86451e1... Use move-aware auto_vec in map (*)
ff6e8b7... tree-optimization/115652 - more fixing of the fix (*)
c4b7b62... i386: Fix regression after refactoring legitimize_pe_coff_s (*)
e9aa979... Remove unused hybrid_* operators in range-ops. (*)
0192341... tree-optimization/115640 - outer loop vect with inner SLP p (*)
ef0b302... amdgcn: Fix RDNA V32 permutations [PR115640] (*)
aa3599a... Add gfc_class_set_vptr. (*)
3f8ce76... Use gfc_reset_vptr more consistently. (*)
07e9159... i386: Handle sign_extend like zero_extend in *concatditi3_[ (*)
5938cf0... i386: Some additional AVX512 ternlog refinements. (*)
4fda39e... Daily bump. (*)
445c62e... libgccjit: Add ability to get the alignment of a type (*)
da
[gcc(refs/users/meissner/heads/work169)] Add ChangeLog.meissner and REVISION.
https://gcc.gnu.org/g:43f9e5a74e3d10d3154ff3faf4cff1273867c356 commit 43f9e5a74e3d10d3154ff3faf4cff1273867c356 Author: Michael Meissner Date: Mon Jun 17 11:42:43 2024 -0400 Add ChangeLog.meissner and REVISION. 2024-06-17 Michael Meissner gcc/ * REVISION: New file for branch. * ChangeLog.meissner: New file. gcc/c-family/ * ChangeLog.meissner: New file. gcc/c/ * ChangeLog.meissner: New file. gcc/cp/ * ChangeLog.meissner: New file. gcc/fortran/ * ChangeLog.meissner: New file. gcc/testsuite/ * ChangeLog.meissner: New file. libgcc/ * ChangeLog.meissner: New file. Diff: --- gcc/ChangeLog.meissner | 6 ++ gcc/REVISION | 1 + gcc/c-family/ChangeLog.meissner | 6 ++ gcc/c/ChangeLog.meissner | 6 ++ gcc/cp/ChangeLog.meissner| 6 ++ gcc/fortran/ChangeLog.meissner | 6 ++ gcc/testsuite/ChangeLog.meissner | 6 ++ libgcc/ChangeLog.meissner| 6 ++ libstdc++-v3/ChangeLog.meissner | 6 ++ 9 files changed, 49 insertions(+) diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner new file mode 100644 index 000..ef7eaa6f006 --- /dev/null +++ b/gcc/ChangeLog.meissner @@ -0,0 +1,6 @@ + Branch work169, baseline + +2024-06-17 Michael Meissner + + Clone branch + diff --git a/gcc/REVISION b/gcc/REVISION new file mode 100644 index 000..ac3c7025be6 --- /dev/null +++ b/gcc/REVISION @@ -0,0 +1 @@ +work169 branch diff --git a/gcc/c-family/ChangeLog.meissner b/gcc/c-family/ChangeLog.meissner new file mode 100644 index 000..ef7eaa6f006 --- /dev/null +++ b/gcc/c-family/ChangeLog.meissner @@ -0,0 +1,6 @@ + Branch work169, baseline + +2024-06-17 Michael Meissner + + Clone branch + diff --git a/gcc/c/ChangeLog.meissner b/gcc/c/ChangeLog.meissner new file mode 100644 index 000..ef7eaa6f006 --- /dev/null +++ b/gcc/c/ChangeLog.meissner @@ -0,0 +1,6 @@ + Branch work169, baseline + +2024-06-17 Michael Meissner + + Clone branch + diff --git a/gcc/cp/ChangeLog.meissner b/gcc/cp/ChangeLog.meissner new file mode 100644 index 000..ef7eaa6f006 --- /dev/null +++ b/gcc/cp/ChangeLog.meissner @@ -0,0 +1,6 @@ + Branch work169, baseline + +2024-06-17 Michael Meissner + + Clone branch + diff --git a/gcc/fortran/ChangeLog.meissner b/gcc/fortran/ChangeLog.meissner new file mode 100644 index 000..ef7eaa6f006 --- /dev/null +++ b/gcc/fortran/ChangeLog.meissner @@ -0,0 +1,6 @@ + Branch work169, baseline + +2024-06-17 Michael Meissner + + Clone branch + diff --git a/gcc/testsuite/ChangeLog.meissner b/gcc/testsuite/ChangeLog.meissner new file mode 100644 index 000..ef7eaa6f006 --- /dev/null +++ b/gcc/testsuite/ChangeLog.meissner @@ -0,0 +1,6 @@ + Branch work169, baseline + +2024-06-17 Michael Meissner + + Clone branch + diff --git a/libgcc/ChangeLog.meissner b/libgcc/ChangeLog.meissner new file mode 100644 index 000..ef7eaa6f006 --- /dev/null +++ b/libgcc/ChangeLog.meissner @@ -0,0 +1,6 @@ + Branch work169, baseline + +2024-06-17 Michael Meissner + + Clone branch + diff --git a/libstdc++-v3/ChangeLog.meissner b/libstdc++-v3/ChangeLog.meissner new file mode 100644 index 000..ef7eaa6f006 --- /dev/null +++ b/libstdc++-v3/ChangeLog.meissner @@ -0,0 +1,6 @@ + Branch work169, baseline + +2024-06-17 Michael Meissner + + Clone branch +
[gcc(refs/users/meissner/heads/work169)] Add -mcpu=power11 support.
https://gcc.gnu.org/g:beb26520a2540b54ab5b47f04735152d58cef712
commit beb26520a2540b54ab5b47f04735152d58cef712
Author: Michael Meissner
Date: Mon Jun 17 14:40:40 2024 -0400
Add -mcpu=power11 support.
This patch adds the power11 option to the -mcpu= and -mtune= switches.
This patch treats the power11 like a power10 in terms of costs and
reassociation
width.
This patch issues a ".machine power11" to the assembly file if you use
-mcpu=power11.
This patch defines _ARCH_PWR11 if the user uses -mcpu=power11.
This patch allows GCC to be configured with the --with-cpu=power11 and
--with-tune=power11 options.
This patch passes -mpwr11 to the assembler if the user uses -mcpu=power11.
This patch adds support for using "power11" in the __builtin_cpu_is built-in
function.
2024-06-17 Michael Meissner
gcc/
* config.gcc (rs6000*-*-*, powerpc*-*-*): Add support for power11.
* config/rs6000/aix71.h (ASM_CPU_SPEC): Add support for
-mcpu=power11.
* config/rs6000/aix72.h (ASM_CPU_SPEC): Likewise.
* config/rs6000/aix73.h (ASM_CPU_SPEC): Likewise.
* config/rs6000/driver-rs6000.cc (asm_names): Likewise.
* config/rs6000/ppc-auxv.h (PPC_PLATFORM_POWER11): New define.
* config/rs6000/rs6000-builtin.cc (cpu_is_info): Add power11.
* config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Define
_ARCH_PWR11 if -mcpu=power11.
* config/rs6000/rs6000-cpus.def (ISA_POWER11_MASKS_SERVER): New
define.
(POWERPC_MASKS): Add power11 isa bit.
(power11 cpu): Add power11 definition.
* config/rs6000/rs6000-opts.h (PROCESSOR_POWER11): Add power11
processor.
* config/rs6000/rs6000-string.cc (expand_compare_loop): Likewise.
* config/rs6000/rs6000-tables.opt: Regenerate.
* config/rs6000/rs6000.cc (rs6000_option_override_internal): Add
power11
support.
(rs6000_machine_from_flags): Likewise.
(rs6000_reassociation_width): Likewise.
(rs6000_adjust_cost): Likewise.
(rs6000_issue_rate): Likewise.
(rs6000_sched_reorder): Likewise.
(rs6000_sched_reorder2): Likewise.
(rs6000_register_move_cost): Likewise.
(rs6000_opt_masks): Likewise.
* config/rs6000/rs6000.h (ASM_CPU_SPEC): Likewise.
* config/rs6000/rs6000.md (cpu attribute): Add power11.
* config/rs6000/rs6000.opt (-mpower11): Add internal power11 ISA
flag.
* doc/invoke.texi (RS/6000 and PowerPC Options): Document
-mcpu=power11.
Diff:
---
gcc/config.gcc | 6 --
gcc/config/rs6000/aix71.h | 1 +
gcc/config/rs6000/aix72.h | 1 +
gcc/config/rs6000/aix73.h | 1 +
gcc/config/rs6000/driver-rs6000.cc | 2 ++
gcc/config/rs6000/ppc-auxv.h| 3 +--
gcc/config/rs6000/rs6000-builtin.cc | 1 +
gcc/config/rs6000/rs6000-c.cc | 2 ++
gcc/config/rs6000/rs6000-cpus.def | 5 +
gcc/config/rs6000/rs6000-opts.h | 3 ++-
gcc/config/rs6000/rs6000-string.cc | 1 +
gcc/config/rs6000/rs6000-tables.opt | 3 +++
gcc/config/rs6000/rs6000.cc | 32
gcc/config/rs6000/rs6000.h | 1 +
gcc/config/rs6000/rs6000.md | 2 +-
gcc/config/rs6000/rs6000.opt| 3 +++
gcc/doc/invoke.texi | 5 +++--
17 files changed, 56 insertions(+), 16 deletions(-)
diff --git a/gcc/config.gcc b/gcc/config.gcc
index bc45615741b..7c283f59e36 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -533,7 +533,9 @@ powerpc*-*-*)
extra_headers="${extra_headers} ppu_intrinsics.h spu2vmx.h vec_types.h
si2vmx.h"
extra_headers="${extra_headers} amo.h"
case x$with_cpu in
-
xpowerpc64|xdefault64|x6[23]0|x970|xG5|xpower[3456789]|xpower10|xpower6x|xrs64a|xcell|xa2|xe500mc64|xe5500|xe6500)
+ xpowerpc64 | xdefault64 | x6[23]0 | x970 | xG5 | xpower[3456789] \
+ | xpower1[01] | xpower6x | xrs64a | xcell | xa2 | xe500mc64 \
+ | xe5500 | xe6500)
cpu_is_64bit=yes
;;
esac
@@ -5641,7 +5643,7 @@ case "${target}" in
eval "with_$which=405"
;;
"" | common | native \
- | power[3456789] | power10 | power5+ | power6x \
+ | power[3456789] | power1[01] | power5+ | power6x \
| powerpc | powerpc64 | powerpc64le \
| rs64 \
| 401 | 403 | 405 | 405fp | 440 | 440fp | 464 | 464fp \
diff --git a/gcc/config/rs6000/aix71.h b/gcc/config/rs6000/aix71.h
index 24bc301e37d..41037b3852d 100644
--- a/gcc/config/rs6000/aix71.h
+++ b/gcc/config/rs6000/aix71.h
@@ -79,6 +79,7 @@ do {
[gcc(refs/users/meissner/heads/work169)] Add -mcpu=power11 tuning support.
https://gcc.gnu.org/g:bb44308a9852b37c9591ef266eebd5e6736fe9e1 commit bb44308a9852b37c9591ef266eebd5e6736fe9e1 Author: Michael Meissner Date: Mon Jun 17 14:41:20 2024 -0400 Add -mcpu=power11 tuning support. This patch makes -mtune=power11 use the same tuning decisions as -mtune=power10. 2024-06-17 Michael Meissner gcc/ * config/rs6000/power10.md (all reservations): Add power11 as an alternative to power10. Diff: --- gcc/config/rs6000/power10.md | 144 +-- 1 file changed, 72 insertions(+), 72 deletions(-) diff --git a/gcc/config/rs6000/power10.md b/gcc/config/rs6000/power10.md index fcc2199ab29..90312643858 100644 --- a/gcc/config/rs6000/power10.md +++ b/gcc/config/rs6000/power10.md @@ -1,4 +1,4 @@ -;; Scheduling description for the IBM POWER10 processor. +;; Scheduling description for the IBM POWER10 and POWER11 processors. ;; Copyright (C) 2020-2024 Free Software Foundation, Inc. ;; ;; Contributed by Pat Haugen (pthau...@us.ibm.com). @@ -97,12 +97,12 @@ (eq_attr "update" "no") (eq_attr "size" "!128") (eq_attr "prefixed" "no") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_any_power10,LU_power10") (define_insn_reservation "power10-fused-load" 4 (and (eq_attr "type" "fused_load_cmpi,fused_addis_load,fused_load_load") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_even_power10,LU_power10") (define_insn_reservation "power10-prefixed-load" 4 @@ -110,13 +110,13 @@ (eq_attr "update" "no") (eq_attr "size" "!128") (eq_attr "prefixed" "yes") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_even_power10,LU_power10") (define_insn_reservation "power10-load-update" 4 (and (eq_attr "type" "load") (eq_attr "update" "yes") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_even_power10,LU_power10+SXU_power10") (define_insn_reservation "power10-fpload-double" 4 @@ -124,7 +124,7 @@ (eq_attr "update" "no") (eq_attr "size" "64") (eq_attr "prefixed" "no") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_any_power10,LU_power10") (define_insn_reservation "power10-prefixed-fpload-double" 4 @@ -132,14 +132,14 @@ (eq_attr "update" "no") (eq_attr "size" "64") (eq_attr "prefixed" "yes") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_even_power10,LU_power10") (define_insn_reservation "power10-fpload-update-double" 4 (and (eq_attr "type" "fpload") (eq_attr "update" "yes") (eq_attr "size" "64") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_even_power10,LU_power10+SXU_power10") ; SFmode loads are cracked and have additional 3 cycles over DFmode @@ -148,27 +148,27 @@ (and (eq_attr "type" "fpload") (eq_attr "update" "no") (eq_attr "size" "32") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_even_power10,LU_power10") (define_insn_reservation "power10-fpload-update-single" 7 (and (eq_attr "type" "fpload") (eq_attr "update" "yes") (eq_attr "size" "32") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_even_power10,LU_power10+SXU_power10") (define_insn_reservation "power10-vecload" 4 (and (eq_attr "type" "vecload") (eq_attr "size" "!256") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_any_power10,LU_power10") ; lxvp (define_insn_reservation "power10-vecload-pair" 4 (and (eq_attr "type" "vecload") (eq_attr "size" "256") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_even_power10,LU_power10+SXU_power10") ; Store Unit @@ -178,12 +178,12 @@ (eq_attr "prefixed" "no") (eq_attr "size" "!128") (eq_attr "size" "!256") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_any_power10,STU_power10") (define_insn_reservation "power10-fused-store" 0 (and (eq_attr "type" "fused_store_store") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_even_power10,STU_power10") (define_insn_reservation "power10-prefixed-store" 0 @@ -191,52 +191,52 @@ (eq_attr "prefixed" "yes") (eq_attr "size" "!128") (eq_attr "size" "!256") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_even_power10,STU_power10") ; Update forms have 2 cycle latency for updated addr reg (define_insn_reservation "power10-store-update" 2 (and (eq_attr "type" "store,fpstore") (eq_attr "update" "yes") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_any_power10,STU_pow
[gcc(refs/users/meissner/heads/work169)] Add -mcpu=power11 tests.
https://gcc.gnu.org/g:66fd1891540b71266d794a4e5a17845443bf84f8
commit 66fd1891540b71266d794a4e5a17845443bf84f8
Author: Michael Meissner
Date: Mon Jun 17 14:50:47 2024 -0400
Add -mcpu=power11 tests.
This patch adds some simple tests for -mcpu=power11 support. In order to
run
these tests, you need an assembler that supports the appropriate option for
supporting the Power11 processor (-mpower11 under Linux or -mpwr11 under
AIX).
2024-06-17 Michael Meissner
gcc/testsuite/
* gcc.target/powerpc/power11-1.c: New test.
* gcc.target/powerpc/power11-2.c: Likewise.
* gcc.target/powerpc/power11-3.c: Likewise.
* lib/target-supports.exp (check_effective_target_power11_ok): Add
new
effective target.
Diff:
---
gcc/testsuite/gcc.target/powerpc/power11-1.c | 13 +
gcc/testsuite/gcc.target/powerpc/power11-2.c | 21 +
gcc/testsuite/gcc.target/powerpc/power11-3.c | 11 +++
gcc/testsuite/lib/target-supports.exp| 17 +
4 files changed, 62 insertions(+)
diff --git a/gcc/testsuite/gcc.target/powerpc/power11-1.c
b/gcc/testsuite/gcc.target/powerpc/power11-1.c
new file mode 100644
index 000..2dd0f64ead1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/power11-1.c
@@ -0,0 +1,13 @@
+/* { dg-do assemble { target powerpc*-*-* } } */
+/* { dg-require-effective-target power11_ok } */
+/* { dg-options "-mdejagnu-cpu=power11 -O2" } */
+
+/* Basic check to see if the compiler supports -mcpu=power11. */
+
+#ifndef _ARCH_PWR11
+#error "-mcpu=power11 is not supported"
+#endif
+
+void foo (void)
+{
+}
diff --git a/gcc/testsuite/gcc.target/powerpc/power11-2.c
b/gcc/testsuite/gcc.target/powerpc/power11-2.c
new file mode 100644
index 000..625031e9146
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/power11-2.c
@@ -0,0 +1,21 @@
+/* { dg-do assemble { target powerpc*-*-* } } */
+/* { dg-require-effective-target power11_ok } */
+/* { dg-require-effective-target target_clone } */
+/* { dg-options "-O2" } */
+
+/* Check if we can set the power11 target via a target attribute. */
+
+__attribute__((__target__("cpu=power9")))
+void foo_p9 (void)
+{
+}
+
+__attribute__((__target__("cpu=power10")))
+void foo_p10 (void)
+{
+}
+
+__attribute__((__target__("cpu=power11")))
+void foo_p11 (void)
+{
+}
diff --git a/gcc/testsuite/gcc.target/powerpc/power11-3.c
b/gcc/testsuite/gcc.target/powerpc/power11-3.c
new file mode 100644
index 000..b0f245eea03
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/power11-3.c
@@ -0,0 +1,11 @@
+/* { dg-do assemble { target powerpc*-*-* } } */
+/* { dg-require-effective-target power11_ok } */
+/* { dg-require-effective-target target_clone } */
+/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
+
+/* Check if we can set the power11 target via a target_clones attribute. */
+
+__attribute__((__target_clones__("cpu=power11,cpu=power9,default")))
+void foo (void)
+{
+}
diff --git a/gcc/testsuite/lib/target-supports.exp
b/gcc/testsuite/lib/target-supports.exp
index b7df6150bcb..da384da766d 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -7217,6 +7217,23 @@ proc check_effective_target_power10_ok { } {
}
}
+# Return 1 if this is a PowerPC target supporting -mcpu=power11.
+
+proc check_effective_target_power11_ok { } {
+if { ([istarget powerpc*-*-*]) } {
+ return [check_no_compiler_messages power11_ok object {
+ int main (void) {
+ #ifndef _ARCH_PWR11
+ #error "-mcpu=power11 is not supported"
+ #endif
+ return 0;
+ }
+ } "-mcpu=power11"]
+} else {
+ return 0
+}
+}
+
# Return 1 if this is a PowerPC target supporting -mfloat128 via either
# software emulation on power7/power8 systems or hardware support on power9.
[gcc(refs/users/meissner/heads/work169)] Update ChangeLog.*
https://gcc.gnu.org/g:9a4a196007b2c491848c4f84cc3a8a93d4067524 commit 9a4a196007b2c491848c4f84cc3a8a93d4067524 Author: Michael Meissner Date: Mon Jun 17 16:12:24 2024 -0400 Update ChangeLog.* Diff: --- gcc/ChangeLog.meissner | 121 - 1 file changed, 120 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner index ef7eaa6f006..df288b5cdf3 100644 --- a/gcc/ChangeLog.meissner +++ b/gcc/ChangeLog.meissner @@ -1,6 +1,125 @@ + Branch work169, patch #3 + +Add -mcpu=power11 tests. + +This patch adds some simple tests for -mcpu=power11 support. In order to run +these tests, you need an assembler that supports the appropriate option for +supporting the Power11 processor (-mpower11 under Linux or -mpwr11 under AIX). + +2024-06-03 Michael Meissner + +gcc/testsuite/ + + * gcc.target/powerpc/power11-1.c: New test. + * gcc.target/powerpc/power11-2.c: Likewise. + * gcc.target/powerpc/power11-3.c: Likewise. + * lib/target-supports.exp (check_effective_target_power11_ok): Add new + effective target. + + Branch work169, patch #2 + +Add -mcpu=power11 tuning support. + +This patch makes -mtune=power11 use the same tuning decisions as -mtune=power10. + +2024-06-03 Michael Meissner + +gcc/ + + * config/rs6000/power10.md (all reservations): Add power11 as an + alternative to power10. + + Branch work169, patch #1 + +Add -mcpu=power11 support. + +This patch adds the power11 option to the -mcpu= and -mtune= switches. + +This patch treats the power11 like a power10 in terms of costs and reassociation +width. + +This patch issues a ".machine power11" to the assembly file if you use +-mcpu=power11. + +This patch defines _ARCH_PWR11 if the user uses -mcpu=power11. + +This patch allows GCC to be configured with the --with-cpu=power11 and +--with-tune=power11 options. + +This patch passes -mpwr11 to the assembler if the user uses -mcpu=power11. + +This patch adds support for using "power11" in the __builtin_cpu_is built-in +function. + +2024-06-03 Michael Meissner + +gcc/ + + * config.gcc (rs6000*-*-*, powerpc*-*-*): Add support for power11. + * config/rs6000/aix71.h (ASM_CPU_SPEC): Add support for -mcpu=power11. + * config/rs6000/aix72.h (ASM_CPU_SPEC): Likewise. + * config/rs6000/aix73.h (ASM_CPU_SPEC): Likewise. + * config/rs6000/driver-rs6000.cc (asm_names): Likewise. + * config/rs6000/ppc-auxv.h (PPC_PLATFORM_POWER11): New define. + * config/rs6000/rs6000-builtin.cc (cpu_is_info): Add power11. + * config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Define + _ARCH_PWR11 if -mcpu=power11. + * config/rs6000/rs6000-cpus.def (ISA_POWER11_MASKS_SERVER): New define. + (POWERPC_MASKS): Add power11 isa bit. + (power11 cpu): Add power11 definition. + * config/rs6000/rs6000-opts.h (PROCESSOR_POWER11): Add power11 processor. + * config/rs6000/rs6000-string.cc (expand_compare_loop): Likewise. + * config/rs6000/rs6000-tables.opt: Regenerate. + * config/rs6000/rs6000.cc (rs6000_option_override_internal): Add power11 + support. + (rs6000_machine_from_flags): Likewise. + (rs6000_reassociation_width): Likewise. + (rs6000_adjust_cost): Likewise. + (rs6000_issue_rate): Likewise. + (rs6000_sched_reorder): Likewise. + (rs6000_sched_reorder2): Likewise. + (rs6000_register_move_cost): Likewise. + (rs6000_opt_masks): Likewise. + * config/rs6000/rs6000.h (ASM_CPU_SPEC): Likewise. + * config/rs6000/rs6000.md (cpu attribute): Add power11. + * config/rs6000/rs6000.opt (-mpower11): Add internal power11 ISA flag. + * doc/invoke.texi (RS/6000 and PowerPC Options): Document -mcpu=power11. + Branch work169, baseline +Add ChangeLog.meissner and REVISION. + +2024-06-03 Michael Meissner + +gcc/ + + * REVISION: New file for branch. + * ChangeLog.meissner: New file. + +gcc/c-family/ + + * ChangeLog.meissner: New file. + +gcc/c/ + + * ChangeLog.meissner: New file. + +gcc/cp/ + + * ChangeLog.meissner: New file. + +gcc/fortran/ + + * ChangeLog.meissner: New file. + +gcc/testsuite/ + + * ChangeLog.meissner: New file. + +libgcc/ + + * ChangeLog.meissner: New file. + 2024-06-17 Michael Meissner Clone branch -
[gcc(refs/users/meissner/heads/work169)] Add -mcpu=future support.
https://gcc.gnu.org/g:c0b1d926cc374c8308bcd1f3f38ed629940cf6aa
commit c0b1d926cc374c8308bcd1f3f38ed629940cf6aa
Author: Michael Meissner
Date: Mon Jun 17 16:13:39 2024 -0400
Add -mcpu=future support.
This patch adds the future option to the -mcpu= and -mtune= switches.
This patch treats the future like a power11 in terms of costs and
reassociation
width.
This patch issues a ".machine future" to the assembly file if you use
-mcpu=power11.
This patch defines _ARCH_PWR_FUTURE if the user uses -mcpu=future.
This patch allows GCC to be configured with the --with-cpu=future and
--with-tune=future options.
This patch passes -mfuture to the assembler if the user uses -mcpu=future.
2024-06-17 Michael Meissner
gcc/
* config.gcc (rs6000*-*-*, powerpc*-*-*): Add support for power11.
* config/rs6000/aix71.h (ASM_CPU_SPEC): Add support for
-mcpu=power11.
* config/rs6000/aix72.h (ASM_CPU_SPEC): Likewise.
* config/rs6000/aix73.h (ASM_CPU_SPEC): Likewise.
* config/rs6000/driver-rs6000.cc (asm_names): Likewise.
* config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Define
_ARCH_PWR_FUTURE if -mcpu=future.
* config/rs6000/rs6000-cpus.def (ISA_FUTURE_MASKS_SERVER): New
define.
(POWERPC_MASKS): Add future isa bit.
(power11 cpu): Add future definition.
* config/rs6000/rs6000-opts.h (PROCESSOR_FUTURE): Add future
processor.
* config/rs6000/rs6000-string.cc (expand_compare_loop): Likewise.
* config/rs6000/rs6000-tables.opt: Regenerate.
* config/rs6000/rs6000.cc (rs6000_option_override_internal): Add
future
support.
(rs6000_machine_from_flags): Likewise.
(rs6000_reassociation_width): Likewise.
(rs6000_adjust_cost): Likewise.
(rs6000_issue_rate): Likewise.
(rs6000_sched_reorder): Likewise.
(rs6000_sched_reorder2): Likewise.
(rs6000_register_move_cost): Likewise.
(rs6000_opt_masks): Likewise.
* config/rs6000/rs6000.h (ASM_CPU_SPEC): Likewise.
* config/rs6000/rs6000.md (cpu attribute): Add future.
* config/rs6000/rs6000.opt (-mpower11): Add internal future ISA
flag.
* doc/invoke.texi (RS/6000 and PowerPC Options): Document
-mcpu=future.
Diff:
---
gcc/config.gcc | 4 ++--
gcc/config/rs6000/aix71.h | 1 +
gcc/config/rs6000/aix72.h | 1 +
gcc/config/rs6000/aix73.h | 1 +
gcc/config/rs6000/driver-rs6000.cc | 2 ++
gcc/config/rs6000/rs6000-c.cc | 2 ++
gcc/config/rs6000/rs6000-cpus.def | 5 +
gcc/config/rs6000/rs6000-opts.h | 3 ++-
gcc/config/rs6000/rs6000-string.cc | 1 +
gcc/config/rs6000/rs6000-tables.opt | 3 +++
gcc/config/rs6000/rs6000.cc | 30 ++
gcc/config/rs6000/rs6000.h | 1 +
gcc/config/rs6000/rs6000.md | 2 +-
gcc/config/rs6000/rs6000.opt| 3 +++
gcc/doc/invoke.texi | 2 +-
15 files changed, 48 insertions(+), 13 deletions(-)
diff --git a/gcc/config.gcc b/gcc/config.gcc
index 7c283f59e36..fe59f33370c 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -534,7 +534,7 @@ powerpc*-*-*)
extra_headers="${extra_headers} amo.h"
case x$with_cpu in
xpowerpc64 | xdefault64 | x6[23]0 | x970 | xG5 | xpower[3456789] \
- | xpower1[01] | xpower6x | xrs64a | xcell | xa2 | xe500mc64 \
+ | xpower1[01] | xfuture | xpower6x | xrs64a | xcell | xa2 |
xe500mc64 \
| xe5500 | xe6500)
cpu_is_64bit=yes
;;
@@ -5643,7 +5643,7 @@ case "${target}" in
eval "with_$which=405"
;;
"" | common | native \
- | power[3456789] | power1[01] | power5+ | power6x \
+ | power[3456789] | power1[01] | power5+ | power6x |
future \
| powerpc | powerpc64 | powerpc64le \
| rs64 \
| 401 | 403 | 405 | 405fp | 440 | 440fp | 464 | 464fp \
diff --git a/gcc/config/rs6000/aix71.h b/gcc/config/rs6000/aix71.h
index 41037b3852d..570ddcc451d 100644
--- a/gcc/config/rs6000/aix71.h
+++ b/gcc/config/rs6000/aix71.h
@@ -79,6 +79,7 @@ do {
\
#undef ASM_CPU_SPEC
#define ASM_CPU_SPEC \
"%{mcpu=native: %(asm_cpu_native); \
+ mcpu=future: -mfuture; \
mcpu=power11: -mpwr11; \
mcpu=power10: -mpwr10; \
mcpu=power9: -mpwr9; \
diff --git a/gcc/config/rs6000/aix72.h b/gcc/config/rs6000/aix72.h
index fe59f8319b4..242ca94bd06 100644
--- a/gcc/config/rs6000/aix72.h
+++ b/gcc/config/rs6000/aix72.h
@@ -79,6 +79,7 @@ do {
[gcc(refs/users/meissner/heads/work169)] Add -mcpu=future tuning support.
https://gcc.gnu.org/g:5f1ab419ab4a1357ab6458b72d5c74a04d26503a commit 5f1ab419ab4a1357ab6458b72d5c74a04d26503a Author: Michael Meissner Date: Mon Jun 17 16:14:22 2024 -0400 Add -mcpu=future tuning support. This patch makes -mtune=future use the same tuning decision as -mtune=power11. 2024-06-17 Michael Meissner gcc/ * config/rs6000/power10.md (all reservations): Add future as an alterntive to power10 and power11. Diff: --- gcc/config/rs6000/power10.md | 145 ++- 1 file changed, 73 insertions(+), 72 deletions(-) diff --git a/gcc/config/rs6000/power10.md b/gcc/config/rs6000/power10.md index 90312643858..1ec1bef0726 100644 --- a/gcc/config/rs6000/power10.md +++ b/gcc/config/rs6000/power10.md @@ -1,4 +1,5 @@ -;; Scheduling description for the IBM POWER10 and POWER11 processors. +;; Scheduling description for the IBM POWER10 and POWER11 processors as well as +;; potential future processors. ;; Copyright (C) 2020-2024 Free Software Foundation, Inc. ;; ;; Contributed by Pat Haugen (pthau...@us.ibm.com). @@ -97,12 +98,12 @@ (eq_attr "update" "no") (eq_attr "size" "!128") (eq_attr "prefixed" "no") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_any_power10,LU_power10") (define_insn_reservation "power10-fused-load" 4 (and (eq_attr "type" "fused_load_cmpi,fused_addis_load,fused_load_load") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_even_power10,LU_power10") (define_insn_reservation "power10-prefixed-load" 4 @@ -110,13 +111,13 @@ (eq_attr "update" "no") (eq_attr "size" "!128") (eq_attr "prefixed" "yes") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_even_power10,LU_power10") (define_insn_reservation "power10-load-update" 4 (and (eq_attr "type" "load") (eq_attr "update" "yes") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_even_power10,LU_power10+SXU_power10") (define_insn_reservation "power10-fpload-double" 4 @@ -124,7 +125,7 @@ (eq_attr "update" "no") (eq_attr "size" "64") (eq_attr "prefixed" "no") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_any_power10,LU_power10") (define_insn_reservation "power10-prefixed-fpload-double" 4 @@ -132,14 +133,14 @@ (eq_attr "update" "no") (eq_attr "size" "64") (eq_attr "prefixed" "yes") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_even_power10,LU_power10") (define_insn_reservation "power10-fpload-update-double" 4 (and (eq_attr "type" "fpload") (eq_attr "update" "yes") (eq_attr "size" "64") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_even_power10,LU_power10+SXU_power10") ; SFmode loads are cracked and have additional 3 cycles over DFmode @@ -148,27 +149,27 @@ (and (eq_attr "type" "fpload") (eq_attr "update" "no") (eq_attr "size" "32") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_even_power10,LU_power10") (define_insn_reservation "power10-fpload-update-single" 7 (and (eq_attr "type" "fpload") (eq_attr "update" "yes") (eq_attr "size" "32") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_even_power10,LU_power10+SXU_power10") (define_insn_reservation "power10-vecload" 4 (and (eq_attr "type" "vecload") (eq_attr "size" "!256") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_any_power10,LU_power10") ; lxvp (define_insn_reservation "power10-vecload-pair" 4 (and (eq_attr "type" "vecload") (eq_attr "size" "256") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_even_power10,LU_power10+SXU_power10") ; Store Unit @@ -178,12 +179,12 @@ (eq_attr "prefixed" "no") (eq_attr "size" "!128") (eq_attr "size" "!256") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_any_power10,STU_power10") (define_insn_reservation "power10-fused-store" 0 (and (eq_attr "type" "fused_store_store") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_even_power10,STU_power10") (define_insn_reservation "power10-prefixed-store" 0 @@ -191,52 +192,52 @@ (eq_attr "prefixed" "yes") (eq_attr "size" "!128") (eq_attr "size" "!256") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_even_power10,STU_power10") ; Update form
[gcc(refs/users/meissner/heads/work169)] Revert changes
https://gcc.gnu.org/g:0ee3bfbccf44fed620d341576fc107b18661ff42
commit 0ee3bfbccf44fed620d341576fc107b18661ff42
Author: Michael Meissner
Date: Mon Jun 17 17:40:04 2024 -0400
Revert changes
Diff:
---
gcc/testsuite/gcc.target/powerpc/power11-1.c | 13 -
gcc/testsuite/gcc.target/powerpc/power11-2.c | 21 -
gcc/testsuite/gcc.target/powerpc/power11-3.c | 11 ---
gcc/testsuite/lib/target-supports.exp| 17 -
4 files changed, 62 deletions(-)
diff --git a/gcc/testsuite/gcc.target/powerpc/power11-1.c
b/gcc/testsuite/gcc.target/powerpc/power11-1.c
deleted file mode 100644
index 2dd0f64ead1..000
--- a/gcc/testsuite/gcc.target/powerpc/power11-1.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* { dg-do assemble { target powerpc*-*-* } } */
-/* { dg-require-effective-target power11_ok } */
-/* { dg-options "-mdejagnu-cpu=power11 -O2" } */
-
-/* Basic check to see if the compiler supports -mcpu=power11. */
-
-#ifndef _ARCH_PWR11
-#error "-mcpu=power11 is not supported"
-#endif
-
-void foo (void)
-{
-}
diff --git a/gcc/testsuite/gcc.target/powerpc/power11-2.c
b/gcc/testsuite/gcc.target/powerpc/power11-2.c
deleted file mode 100644
index 625031e9146..000
--- a/gcc/testsuite/gcc.target/powerpc/power11-2.c
+++ /dev/null
@@ -1,21 +0,0 @@
-/* { dg-do assemble { target powerpc*-*-* } } */
-/* { dg-require-effective-target power11_ok } */
-/* { dg-require-effective-target target_clone } */
-/* { dg-options "-O2" } */
-
-/* Check if we can set the power11 target via a target attribute. */
-
-__attribute__((__target__("cpu=power9")))
-void foo_p9 (void)
-{
-}
-
-__attribute__((__target__("cpu=power10")))
-void foo_p10 (void)
-{
-}
-
-__attribute__((__target__("cpu=power11")))
-void foo_p11 (void)
-{
-}
diff --git a/gcc/testsuite/gcc.target/powerpc/power11-3.c
b/gcc/testsuite/gcc.target/powerpc/power11-3.c
deleted file mode 100644
index b0f245eea03..000
--- a/gcc/testsuite/gcc.target/powerpc/power11-3.c
+++ /dev/null
@@ -1,11 +0,0 @@
-/* { dg-do assemble { target powerpc*-*-* } } */
-/* { dg-require-effective-target power11_ok } */
-/* { dg-require-effective-target target_clone } */
-/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
-
-/* Check if we can set the power11 target via a target_clones attribute. */
-
-__attribute__((__target_clones__("cpu=power11,cpu=power9,default")))
-void foo (void)
-{
-}
diff --git a/gcc/testsuite/lib/target-supports.exp
b/gcc/testsuite/lib/target-supports.exp
index da384da766d..b7df6150bcb 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -7217,23 +7217,6 @@ proc check_effective_target_power10_ok { } {
}
}
-# Return 1 if this is a PowerPC target supporting -mcpu=power11.
-
-proc check_effective_target_power11_ok { } {
-if { ([istarget powerpc*-*-*]) } {
- return [check_no_compiler_messages power11_ok object {
- int main (void) {
- #ifndef _ARCH_PWR11
- #error "-mcpu=power11 is not supported"
- #endif
- return 0;
- }
- } "-mcpu=power11"]
-} else {
- return 0
-}
-}
-
# Return 1 if this is a PowerPC target supporting -mfloat128 via either
# software emulation on power7/power8 systems or hardware support on power9.
[gcc(refs/users/meissner/heads/work169)] Update ChangeLog.*
https://gcc.gnu.org/g:2127f93fa4820bda10e6b33d1ff3089f62c3b68b commit 2127f93fa4820bda10e6b33d1ff3089f62c3b68b Author: Michael Meissner Date: Mon Jun 17 16:16:20 2024 -0400 Update ChangeLog.* Diff: --- gcc/ChangeLog.meissner | 72 +++--- 1 file changed, 68 insertions(+), 4 deletions(-) diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner index df288b5cdf3..9e0d3f523da 100644 --- a/gcc/ChangeLog.meissner +++ b/gcc/ChangeLog.meissner @@ -1,3 +1,67 @@ + Branch work169, patch #11 + +Add -mcpu=future tuning support. + +This patch makes -mtune=future use the same tuning decision as -mtune=power11. + +2024-06-17 Michael Meissner + +gcc/ + + * config/rs6000/power10.md (all reservations): Add future as an + alterntive to power10 and power11. + + Branch work169, patch #10 + +Add -mcpu=future support. + +This patch adds the future option to the -mcpu= and -mtune= switches. + +This patch treats the future like a power11 in terms of costs and reassociation +width. + +This patch issues a ".machine future" to the assembly file if you use +-mcpu=power11. + +This patch defines _ARCH_PWR_FUTURE if the user uses -mcpu=future. + +This patch allows GCC to be configured with the --with-cpu=future and +--with-tune=future options. + +This patch passes -mfuture to the assembler if the user uses -mcpu=future. + +2024-06-17 Michael Meissner + +gcc/ + + * config.gcc (rs6000*-*-*, powerpc*-*-*): Add support for power11. + * config/rs6000/aix71.h (ASM_CPU_SPEC): Add support for -mcpu=power11. + * config/rs6000/aix72.h (ASM_CPU_SPEC): Likewise. + * config/rs6000/aix73.h (ASM_CPU_SPEC): Likewise. + * config/rs6000/driver-rs6000.cc (asm_names): Likewise. + * config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Define + _ARCH_PWR_FUTURE if -mcpu=future. + * config/rs6000/rs6000-cpus.def (ISA_FUTURE_MASKS_SERVER): New define. + (POWERPC_MASKS): Add future isa bit. + (power11 cpu): Add future definition. + * config/rs6000/rs6000-opts.h (PROCESSOR_FUTURE): Add future processor. + * config/rs6000/rs6000-string.cc (expand_compare_loop): Likewise. + * config/rs6000/rs6000-tables.opt: Regenerate. + * config/rs6000/rs6000.cc (rs6000_option_override_internal): Add future + support. + (rs6000_machine_from_flags): Likewise. + (rs6000_reassociation_width): Likewise. + (rs6000_adjust_cost): Likewise. + (rs6000_issue_rate): Likewise. + (rs6000_sched_reorder): Likewise. + (rs6000_sched_reorder2): Likewise. + (rs6000_register_move_cost): Likewise. + (rs6000_opt_masks): Likewise. + * config/rs6000/rs6000.h (ASM_CPU_SPEC): Likewise. + * config/rs6000/rs6000.md (cpu attribute): Add future. + * config/rs6000/rs6000.opt (-mpower11): Add internal future ISA flag. + * doc/invoke.texi (RS/6000 and PowerPC Options): Document -mcpu=future. + Branch work169, patch #3 Add -mcpu=power11 tests. @@ -6,7 +70,7 @@ This patch adds some simple tests for -mcpu=power11 support. In order to run these tests, you need an assembler that supports the appropriate option for supporting the Power11 processor (-mpower11 under Linux or -mpwr11 under AIX). -2024-06-03 Michael Meissner +2024-06-17 Michael Meissner gcc/testsuite/ @@ -22,7 +86,7 @@ Add -mcpu=power11 tuning support. This patch makes -mtune=power11 use the same tuning decisions as -mtune=power10. -2024-06-03 Michael Meissner +2024-06-17 Michael Meissner gcc/ @@ -51,7 +115,7 @@ This patch passes -mpwr11 to the assembler if the user uses -mcpu=power11. This patch adds support for using "power11" in the __builtin_cpu_is built-in function. -2024-06-03 Michael Meissner +2024-06-17 Michael Meissner gcc/ @@ -89,7 +153,7 @@ gcc/ Add ChangeLog.meissner and REVISION. -2024-06-03 Michael Meissner +2024-06-17 Michael Meissner gcc/
[gcc(refs/users/meissner/heads/work169)] Add -mcpu=power11 tests.
https://gcc.gnu.org/g:31521f0f9515f91a40fb730bd229db65b9d03b7a
commit 31521f0f9515f91a40fb730bd229db65b9d03b7a
Author: Michael Meissner
Date: Mon Jun 17 17:41:34 2024 -0400
Add -mcpu=power11 tests.
This patch adds some simple tests for -mcpu=power11 support. In order to
run
these tests, you need an assembler that supports the appropriate option for
supporting the Power11 processor (-mpower11 under Linux or -mpwr11 under
AIX).
2024-06-17 Michael Meissner
gcc/testsuite/
* gcc.target/powerpc/power11-1.c: New test.
* gcc.target/powerpc/power11-2.c: Likewise.
* gcc.target/powerpc/power11-3.c: Likewise.
* lib/target-supports.exp (check_effective_target_power11_ok): Add
new
effective target.
Diff:
---
gcc/testsuite/gcc.target/powerpc/power11-1.c | 13 +
gcc/testsuite/gcc.target/powerpc/power11-2.c | 20
gcc/testsuite/gcc.target/powerpc/power11-3.c | 10 ++
gcc/testsuite/lib/target-supports.exp| 17 +
4 files changed, 60 insertions(+)
diff --git a/gcc/testsuite/gcc.target/powerpc/power11-1.c
b/gcc/testsuite/gcc.target/powerpc/power11-1.c
new file mode 100644
index 000..2dd0f64ead1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/power11-1.c
@@ -0,0 +1,13 @@
+/* { dg-do assemble { target powerpc*-*-* } } */
+/* { dg-require-effective-target power11_ok } */
+/* { dg-options "-mdejagnu-cpu=power11 -O2" } */
+
+/* Basic check to see if the compiler supports -mcpu=power11. */
+
+#ifndef _ARCH_PWR11
+#error "-mcpu=power11 is not supported"
+#endif
+
+void foo (void)
+{
+}
diff --git a/gcc/testsuite/gcc.target/powerpc/power11-2.c
b/gcc/testsuite/gcc.target/powerpc/power11-2.c
new file mode 100644
index 000..6537e22e1a6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/power11-2.c
@@ -0,0 +1,20 @@
+/* { dg-do assemble { target powerpc*-*-* } } */
+/* { dg-require-effective-target power11_ok } */
+/* { dg-options "-O2" } */
+
+/* Check if we can set the power11 target via a target attribute. */
+
+__attribute__((__target__("cpu=power9")))
+void foo_p9 (void)
+{
+}
+
+__attribute__((__target__("cpu=power10")))
+void foo_p10 (void)
+{
+}
+
+__attribute__((__target__("cpu=power11")))
+void foo_p11 (void)
+{
+}
diff --git a/gcc/testsuite/gcc.target/powerpc/power11-3.c
b/gcc/testsuite/gcc.target/powerpc/power11-3.c
new file mode 100644
index 000..89b13c857d9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/power11-3.c
@@ -0,0 +1,10 @@
+/* { dg-do assemble { target powerpc*-*-* } } */
+/* { dg-require-effective-target power11_ok } */
+/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
+
+/* Check if we can set the power11 target via a target_clones attribute. */
+
+__attribute__((__target_clones__("cpu=power11,cpu=power9,default")))
+void foo (void)
+{
+}
diff --git a/gcc/testsuite/lib/target-supports.exp
b/gcc/testsuite/lib/target-supports.exp
index b7df6150bcb..da384da766d 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -7217,6 +7217,23 @@ proc check_effective_target_power10_ok { } {
}
}
+# Return 1 if this is a PowerPC target supporting -mcpu=power11.
+
+proc check_effective_target_power11_ok { } {
+if { ([istarget powerpc*-*-*]) } {
+ return [check_no_compiler_messages power11_ok object {
+ int main (void) {
+ #ifndef _ARCH_PWR11
+ #error "-mcpu=power11 is not supported"
+ #endif
+ return 0;
+ }
+ } "-mcpu=power11"]
+} else {
+ return 0
+}
+}
+
# Return 1 if this is a PowerPC target supporting -mfloat128 via either
# software emulation on power7/power8 systems or hardware support on power9.
[gcc(refs/users/meissner/heads/work169)] Merge commit 'refs/users/meissner/heads/work169' of git+ssh://gcc.gnu.org/git/gcc into me/work169
https://gcc.gnu.org/g:bdebf88289c3b371b5cc7b0ec9481d2efcbfaa31 commit bdebf88289c3b371b5cc7b0ec9481d2efcbfaa31 Merge: 31521f0f951 99d2f9ee130 Author: Michael Meissner Date: Mon Jul 1 22:31:57 2024 -0400 Merge commit 'refs/users/meissner/heads/work169' of git+ssh://gcc.gnu.org/git/gcc into me/work169 Diff:
[gcc/meissner/heads/work171] (52 commits) Merge commit 'refs/users/meissner/heads/work171' of git+ssh
The branch 'meissner/heads/work171' was updated to point to:
1f0d0b5085c... Merge commit 'refs/users/meissner/heads/work171' of git+ssh
It previously pointed to:
f1cbe164c77... Add ChangeLog.meissner and REVISION.
Diff:
Summary of changes (added commits):
---
1f0d0b5... Merge commit 'refs/users/meissner/heads/work171' of git+ssh
f41f2d6... Add ChangeLog.meissner and REVISION.
0b4fd67... Daily bump. (*)
c90e785... c++: ICE with computed gotos [PR115469] (*)
cb39f7d... testsuite: fix spaceship-narrowing1.C (*)
c847dcf... c++: unresolved overload with comma op [PR115430] (*)
52d71b6... c++: DR2627, Bit-fields and narrowing conversions [PR94058] (*)
4d24159... Preserve SSA info for more propagated copy (*)
7a65ab6... RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM form (*)
6d98e88... RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM form (*)
bff0d02... RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM form (*)
ed213b3... RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM form (*)
589865a... testsuite: Fix -m32 gcc.target/i386/pr102464-vrndscaleph.c (*)
142b526... i386: Additional peephole2 to use lea in round-up integer d (*)
3d23abd... AVR: target/88236, target/115726 - Fix __memx code generati (*)
90c558e... testsuite/52641 - Adjust some test cases to less capable pl (*)
6400144... libgomp, openmp: Add ompx_gnu_pinned_mem_alloc (*)
90efaeb... libgomp: change alloc-pinned tests failure mode (*)
61aa380... libffi: Fix 32-bit SPARC structure passing [PR115681] (*)
286cda3... tree-optimization/115723 - ICE with .COND_ADD reduction (*)
382e212... [MAINTAINERS] Update my email address (*)
543a5b9... tree-optimization/115694 - ICE with complex store rewrite (*)
55f80c6... Remove vcond{,u,eq} expanders since they will be obso (*)
2ccdd0f... Optimize a < 0 ? -1 : 0 to (signed)a >> 31. (*)
e94e6ee... Adjust testcase for the regressed testcases after obsolete (*)
3cb2040... Add more splitter for mskmov with avx512 comparison. (*)
09737d9... Match IEEE min/max with UNSPEC_IEEE_{MIN,MAX}. (*)
b06a108... Lower AVX512 kmask comparison back to AVX2 comparison when (*)
2e2dfa0... Add more splitters to match (unspec [op1 op2 (gt op3 constm (*)
e62ea4f... Enable flate-combine. (*)
8e1fa10... Extend lshifrtsi3_1_zext to ?k alternative. (*)
5e1a9f4... Define mask as extern instead of uninitialized local variab (*)
76075bf... Daily bump. (*)
30ad2fa... hppa: Fix ICE caused by mismatched predicate and constraint (*)
b77f17c... tree-optimization/115701 - fix maybe_duplicate_ssa_info_at_ (*)
b5c64b4... tree-optimization/115701 - factor out maybe_duplicate_ssa_i (*)
b443d71... Harden SLP reduction support wrt STMT_VINFO_REDUC_IDX (*)
3aa004f... vect: Determine input vectype for multiple lane-reducing op (*)
1ff5f8f... vect: Fix shift-by-induction for single-lane slp (*)
1bcfed4... Daily bump. (*)
69bc5fb... [PR115565] cse: Don't use a valid regno for non-register in (*)
42946aa... [to-be-committed,RISC-V,V4] movmem for RISCV with V extensi (*)
7682d11... Fortran: fix ALLOCATE with SOURCE of deferred character len (*)
21e3565... Match: Support imm form for unsigned scalar .SAT_ADD (*)
45e74d5... jit: Fix Darwin bootstrap after r15-1699. (*)
9fbbad9... [committed] Fix mcore-elf regression after recent IRA chang (*)
614fd0f... Daily bump. (*)
50073ff... c++: bad 'this' conversion for nullary memfn [PR106760] (*)
52370c8... libstdc++: Define __glibcxx_assert_fail for non-verbose bui (*)
fab60ea... libstdc++: Extend std::equal memcmp optimization to std::by (*)
03d3aeb... libstdc++: Do not use C++11 alignof in C++98 mode [PR104395 (*)
ac8c61b... libstdc++: Simplify class templates (*)
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Because the reference `refs/users/meissner/heads/work171' matches
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[gcc(refs/users/meissner/heads/work171)] Add ChangeLog.meissner and REVISION.
https://gcc.gnu.org/g:f41f2d6f9205bf5b665057b6731744872f56e783 commit f41f2d6f9205bf5b665057b6731744872f56e783 Author: Michael Meissner Date: Fri Jun 28 15:03:42 2024 -0400 Add ChangeLog.meissner and REVISION. 2024-06-28 Michael Meissner gcc/ * REVISION: New file for branch. * ChangeLog.meissner: New file. gcc/c-family/ * ChangeLog.meissner: New file. gcc/c/ * ChangeLog.meissner: New file. gcc/cp/ * ChangeLog.meissner: New file. gcc/fortran/ * ChangeLog.meissner: New file. gcc/testsuite/ * ChangeLog.meissner: New file. libgcc/ * ChangeLog.meissner: New file. Diff: --- gcc/ChangeLog.meissner | 6 ++ gcc/REVISION | 1 + gcc/c-family/ChangeLog.meissner | 6 ++ gcc/c/ChangeLog.meissner | 6 ++ gcc/cp/ChangeLog.meissner| 6 ++ gcc/fortran/ChangeLog.meissner | 6 ++ gcc/testsuite/ChangeLog.meissner | 6 ++ libgcc/ChangeLog.meissner| 6 ++ libstdc++-v3/ChangeLog.meissner | 6 ++ 9 files changed, 49 insertions(+) diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner new file mode 100644 index 000..1418e34ed1c --- /dev/null +++ b/gcc/ChangeLog.meissner @@ -0,0 +1,6 @@ + Branch work171, baseline + +2024-06-28 Michael Meissner + + Clone branch + diff --git a/gcc/REVISION b/gcc/REVISION new file mode 100644 index 000..060d0f9e831 --- /dev/null +++ b/gcc/REVISION @@ -0,0 +1 @@ +work171 branch diff --git a/gcc/c-family/ChangeLog.meissner b/gcc/c-family/ChangeLog.meissner new file mode 100644 index 000..1418e34ed1c --- /dev/null +++ b/gcc/c-family/ChangeLog.meissner @@ -0,0 +1,6 @@ + Branch work171, baseline + +2024-06-28 Michael Meissner + + Clone branch + diff --git a/gcc/c/ChangeLog.meissner b/gcc/c/ChangeLog.meissner new file mode 100644 index 000..1418e34ed1c --- /dev/null +++ b/gcc/c/ChangeLog.meissner @@ -0,0 +1,6 @@ + Branch work171, baseline + +2024-06-28 Michael Meissner + + Clone branch + diff --git a/gcc/cp/ChangeLog.meissner b/gcc/cp/ChangeLog.meissner new file mode 100644 index 000..1418e34ed1c --- /dev/null +++ b/gcc/cp/ChangeLog.meissner @@ -0,0 +1,6 @@ + Branch work171, baseline + +2024-06-28 Michael Meissner + + Clone branch + diff --git a/gcc/fortran/ChangeLog.meissner b/gcc/fortran/ChangeLog.meissner new file mode 100644 index 000..1418e34ed1c --- /dev/null +++ b/gcc/fortran/ChangeLog.meissner @@ -0,0 +1,6 @@ + Branch work171, baseline + +2024-06-28 Michael Meissner + + Clone branch + diff --git a/gcc/testsuite/ChangeLog.meissner b/gcc/testsuite/ChangeLog.meissner new file mode 100644 index 000..1418e34ed1c --- /dev/null +++ b/gcc/testsuite/ChangeLog.meissner @@ -0,0 +1,6 @@ + Branch work171, baseline + +2024-06-28 Michael Meissner + + Clone branch + diff --git a/libgcc/ChangeLog.meissner b/libgcc/ChangeLog.meissner new file mode 100644 index 000..1418e34ed1c --- /dev/null +++ b/libgcc/ChangeLog.meissner @@ -0,0 +1,6 @@ + Branch work171, baseline + +2024-06-28 Michael Meissner + + Clone branch + diff --git a/libstdc++-v3/ChangeLog.meissner b/libstdc++-v3/ChangeLog.meissner new file mode 100644 index 000..1418e34ed1c --- /dev/null +++ b/libstdc++-v3/ChangeLog.meissner @@ -0,0 +1,6 @@ + Branch work171, baseline + +2024-06-28 Michael Meissner + + Clone branch +
[gcc(refs/users/meissner/heads/work171)] Merge commit 'refs/users/meissner/heads/work171' of git+ssh://gcc.gnu.org/git/gcc into me/work171
https://gcc.gnu.org/g:1f0d0b5085caebb5dd5a67105ffec43053985c65 commit 1f0d0b5085caebb5dd5a67105ffec43053985c65 Merge: f41f2d6f920 f1cbe164c77 Author: Michael Meissner Date: Mon Jul 1 22:43:49 2024 -0400 Merge commit 'refs/users/meissner/heads/work171' of git+ssh://gcc.gnu.org/git/gcc into me/work171 Diff:
[gcc/meissner/heads/work171-bugs] (54 commits) Merge commit 'refs/users/meissner/heads/work171-bugs' of gi
The branch 'meissner/heads/work171-bugs' was updated to point to:
eea8d7b482a... Merge commit 'refs/users/meissner/heads/work171-bugs' of gi
It previously pointed to:
ceb9a2dcf78... Add ChangeLog.bugs and update REVISION.
Diff:
Summary of changes (added commits):
---
eea8d7b... Merge commit 'refs/users/meissner/heads/work171-bugs' of gi
831077e... Add ChangeLog.bugs and update REVISION.
1f0d0b5... Merge commit 'refs/users/meissner/heads/work171' of git+ssh (*)
f41f2d6... Add ChangeLog.meissner and REVISION. (*)
0b4fd67... Daily bump. (*)
c90e785... c++: ICE with computed gotos [PR115469] (*)
cb39f7d... testsuite: fix spaceship-narrowing1.C (*)
c847dcf... c++: unresolved overload with comma op [PR115430] (*)
52d71b6... c++: DR2627, Bit-fields and narrowing conversions [PR94058] (*)
4d24159... Preserve SSA info for more propagated copy (*)
7a65ab6... RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM form (*)
6d98e88... RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM form (*)
bff0d02... RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM form (*)
ed213b3... RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM form (*)
589865a... testsuite: Fix -m32 gcc.target/i386/pr102464-vrndscaleph.c (*)
142b526... i386: Additional peephole2 to use lea in round-up integer d (*)
3d23abd... AVR: target/88236, target/115726 - Fix __memx code generati (*)
90c558e... testsuite/52641 - Adjust some test cases to less capable pl (*)
6400144... libgomp, openmp: Add ompx_gnu_pinned_mem_alloc (*)
90efaeb... libgomp: change alloc-pinned tests failure mode (*)
61aa380... libffi: Fix 32-bit SPARC structure passing [PR115681] (*)
286cda3... tree-optimization/115723 - ICE with .COND_ADD reduction (*)
382e212... [MAINTAINERS] Update my email address (*)
543a5b9... tree-optimization/115694 - ICE with complex store rewrite (*)
55f80c6... Remove vcond{,u,eq} expanders since they will be obso (*)
2ccdd0f... Optimize a < 0 ? -1 : 0 to (signed)a >> 31. (*)
e94e6ee... Adjust testcase for the regressed testcases after obsolete (*)
3cb2040... Add more splitter for mskmov with avx512 comparison. (*)
09737d9... Match IEEE min/max with UNSPEC_IEEE_{MIN,MAX}. (*)
b06a108... Lower AVX512 kmask comparison back to AVX2 comparison when (*)
2e2dfa0... Add more splitters to match (unspec [op1 op2 (gt op3 constm (*)
e62ea4f... Enable flate-combine. (*)
8e1fa10... Extend lshifrtsi3_1_zext to ?k alternative. (*)
5e1a9f4... Define mask as extern instead of uninitialized local variab (*)
76075bf... Daily bump. (*)
30ad2fa... hppa: Fix ICE caused by mismatched predicate and constraint (*)
b77f17c... tree-optimization/115701 - fix maybe_duplicate_ssa_info_at_ (*)
b5c64b4... tree-optimization/115701 - factor out maybe_duplicate_ssa_i (*)
b443d71... Harden SLP reduction support wrt STMT_VINFO_REDUC_IDX (*)
3aa004f... vect: Determine input vectype for multiple lane-reducing op (*)
1ff5f8f... vect: Fix shift-by-induction for single-lane slp (*)
1bcfed4... Daily bump. (*)
69bc5fb... [PR115565] cse: Don't use a valid regno for non-register in (*)
42946aa... [to-be-committed,RISC-V,V4] movmem for RISCV with V extensi (*)
7682d11... Fortran: fix ALLOCATE with SOURCE of deferred character len (*)
21e3565... Match: Support imm form for unsigned scalar .SAT_ADD (*)
45e74d5... jit: Fix Darwin bootstrap after r15-1699. (*)
9fbbad9... [committed] Fix mcore-elf regression after recent IRA chang (*)
614fd0f... Daily bump. (*)
50073ff... c++: bad 'this' conversion for nullary memfn [PR106760] (*)
52370c8... libstdc++: Define __glibcxx_assert_fail for non-verbose bui (*)
fab60ea... libstdc++: Extend std::equal memcmp optimization to std::by (*)
03d3aeb... libstdc++: Do not use C++11 alignof in C++98 mode [PR104395 (*)
ac8c61b... libstdc++: Simplify class templates (*)
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[gcc(refs/users/meissner/heads/work171-bugs)] Add ChangeLog.bugs and update REVISION.
https://gcc.gnu.org/g:831077e7d37500ded357a23cd544d38adbea2fcb commit 831077e7d37500ded357a23cd544d38adbea2fcb Author: Michael Meissner Date: Fri Jun 28 15:07:19 2024 -0400 Add ChangeLog.bugs and update REVISION. 2024-06-28 Michael Meissner gcc/ * ChangeLog.bugs: New file for branch. * REVISION: Update. Diff: --- gcc/ChangeLog.bugs | 6 ++ gcc/REVISION | 2 +- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog.bugs b/gcc/ChangeLog.bugs new file mode 100644 index 000..d2c5d2ab118 --- /dev/null +++ b/gcc/ChangeLog.bugs @@ -0,0 +1,6 @@ + Branch work171-bugs, baseline + +2024-06-28 Michael Meissner + + Clone branch + diff --git a/gcc/REVISION b/gcc/REVISION index 060d0f9e831..7a2e248f4d4 100644 --- a/gcc/REVISION +++ b/gcc/REVISION @@ -1 +1 @@ -work171 branch +work171-bugs branch
[gcc(refs/users/meissner/heads/work171-bugs)] Merge commit 'refs/users/meissner/heads/work171-bugs' of git+ssh://gcc.gnu.org/git/gcc into me/work1
https://gcc.gnu.org/g:eea8d7b482a3867978c174cc37c8faa314d9cea1 commit eea8d7b482a3867978c174cc37c8faa314d9cea1 Merge: 831077e7d37 ceb9a2dcf78 Author: Michael Meissner Date: Mon Jul 1 22:45:16 2024 -0400 Merge commit 'refs/users/meissner/heads/work171-bugs' of git+ssh://gcc.gnu.org/git/gcc into me/work171-bugs Diff:
[gcc/meissner/heads/work171-dmf] (54 commits) Merge commit 'refs/users/meissner/heads/work171-dmf' of git
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306ab5def69... Merge commit 'refs/users/meissner/heads/work171-dmf' of git
It previously pointed to:
c6be350c861... Add ChangeLog.dmf and update REVISION.
Diff:
Summary of changes (added commits):
---
306ab5d... Merge commit 'refs/users/meissner/heads/work171-dmf' of git
2631e7c... Add ChangeLog.dmf and update REVISION.
1f0d0b5... Merge commit 'refs/users/meissner/heads/work171' of git+ssh (*)
f41f2d6... Add ChangeLog.meissner and REVISION. (*)
0b4fd67... Daily bump. (*)
c90e785... c++: ICE with computed gotos [PR115469] (*)
cb39f7d... testsuite: fix spaceship-narrowing1.C (*)
c847dcf... c++: unresolved overload with comma op [PR115430] (*)
52d71b6... c++: DR2627, Bit-fields and narrowing conversions [PR94058] (*)
4d24159... Preserve SSA info for more propagated copy (*)
7a65ab6... RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM form (*)
6d98e88... RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM form (*)
bff0d02... RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM form (*)
ed213b3... RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM form (*)
589865a... testsuite: Fix -m32 gcc.target/i386/pr102464-vrndscaleph.c (*)
142b526... i386: Additional peephole2 to use lea in round-up integer d (*)
3d23abd... AVR: target/88236, target/115726 - Fix __memx code generati (*)
90c558e... testsuite/52641 - Adjust some test cases to less capable pl (*)
6400144... libgomp, openmp: Add ompx_gnu_pinned_mem_alloc (*)
90efaeb... libgomp: change alloc-pinned tests failure mode (*)
61aa380... libffi: Fix 32-bit SPARC structure passing [PR115681] (*)
286cda3... tree-optimization/115723 - ICE with .COND_ADD reduction (*)
382e212... [MAINTAINERS] Update my email address (*)
543a5b9... tree-optimization/115694 - ICE with complex store rewrite (*)
55f80c6... Remove vcond{,u,eq} expanders since they will be obso (*)
2ccdd0f... Optimize a < 0 ? -1 : 0 to (signed)a >> 31. (*)
e94e6ee... Adjust testcase for the regressed testcases after obsolete (*)
3cb2040... Add more splitter for mskmov with avx512 comparison. (*)
09737d9... Match IEEE min/max with UNSPEC_IEEE_{MIN,MAX}. (*)
b06a108... Lower AVX512 kmask comparison back to AVX2 comparison when (*)
2e2dfa0... Add more splitters to match (unspec [op1 op2 (gt op3 constm (*)
e62ea4f... Enable flate-combine. (*)
8e1fa10... Extend lshifrtsi3_1_zext to ?k alternative. (*)
5e1a9f4... Define mask as extern instead of uninitialized local variab (*)
76075bf... Daily bump. (*)
30ad2fa... hppa: Fix ICE caused by mismatched predicate and constraint (*)
b77f17c... tree-optimization/115701 - fix maybe_duplicate_ssa_info_at_ (*)
b5c64b4... tree-optimization/115701 - factor out maybe_duplicate_ssa_i (*)
b443d71... Harden SLP reduction support wrt STMT_VINFO_REDUC_IDX (*)
3aa004f... vect: Determine input vectype for multiple lane-reducing op (*)
1ff5f8f... vect: Fix shift-by-induction for single-lane slp (*)
1bcfed4... Daily bump. (*)
69bc5fb... [PR115565] cse: Don't use a valid regno for non-register in (*)
42946aa... [to-be-committed,RISC-V,V4] movmem for RISCV with V extensi (*)
7682d11... Fortran: fix ALLOCATE with SOURCE of deferred character len (*)
21e3565... Match: Support imm form for unsigned scalar .SAT_ADD (*)
45e74d5... jit: Fix Darwin bootstrap after r15-1699. (*)
9fbbad9... [committed] Fix mcore-elf regression after recent IRA chang (*)
614fd0f... Daily bump. (*)
50073ff... c++: bad 'this' conversion for nullary memfn [PR106760] (*)
52370c8... libstdc++: Define __glibcxx_assert_fail for non-verbose bui (*)
fab60ea... libstdc++: Extend std::equal memcmp optimization to std::by (*)
03d3aeb... libstdc++: Do not use C++11 alignof in C++98 mode [PR104395 (*)
ac8c61b... libstdc++: Simplify class templates (*)
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Because the reference `refs/users/meissner/heads/work171-dmf' matches
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[gcc(refs/users/meissner/heads/work171-dmf)] Add ChangeLog.dmf and update REVISION.
https://gcc.gnu.org/g:2631e7cf01dcb82e2ccd68f1fe11995e8ecc255d commit 2631e7cf01dcb82e2ccd68f1fe11995e8ecc255d Author: Michael Meissner Date: Fri Jun 28 15:04:38 2024 -0400 Add ChangeLog.dmf and update REVISION. 2024-06-28 Michael Meissner gcc/ * ChangeLog.dmf: New file for branch. * REVISION: Update. Diff: --- gcc/ChangeLog.dmf | 6 ++ gcc/REVISION | 2 +- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog.dmf b/gcc/ChangeLog.dmf new file mode 100644 index 000..bf4edca66c7 --- /dev/null +++ b/gcc/ChangeLog.dmf @@ -0,0 +1,6 @@ + Branch work171-dmf, baseline + +2024-06-28 Michael Meissner + + Clone branch + diff --git a/gcc/REVISION b/gcc/REVISION index 060d0f9e831..e8fb95125d2 100644 --- a/gcc/REVISION +++ b/gcc/REVISION @@ -1 +1 @@ -work171 branch +work171-dmf branch
[gcc(refs/users/meissner/heads/work171-dmf)] Merge commit 'refs/users/meissner/heads/work171-dmf' of git+ssh://gcc.gnu.org/git/gcc into me/work17
https://gcc.gnu.org/g:306ab5def69b4560ff5682d7063b8c472c0e2355 commit 306ab5def69b4560ff5682d7063b8c472c0e2355 Merge: 2631e7cf01d c6be350c861 Author: Michael Meissner Date: Mon Jul 1 22:47:07 2024 -0400 Merge commit 'refs/users/meissner/heads/work171-dmf' of git+ssh://gcc.gnu.org/git/gcc into me/work171-dmf Diff:
[gcc/meissner/heads/work171-tar] (54 commits) Merge commit 'refs/users/meissner/heads/work171-tar' of git
The branch 'meissner/heads/work171-tar' was updated to point to:
c70c1d9fef8... Merge commit 'refs/users/meissner/heads/work171-tar' of git
It previously pointed to:
96bcf7509f8... Add ChangeLog.tar and update REVISION.
Diff:
Summary of changes (added commits):
---
c70c1d9... Merge commit 'refs/users/meissner/heads/work171-tar' of git
1fc2e4c... Add ChangeLog.tar and update REVISION.
1f0d0b5... Merge commit 'refs/users/meissner/heads/work171' of git+ssh (*)
f41f2d6... Add ChangeLog.meissner and REVISION. (*)
0b4fd67... Daily bump. (*)
c90e785... c++: ICE with computed gotos [PR115469] (*)
cb39f7d... testsuite: fix spaceship-narrowing1.C (*)
c847dcf... c++: unresolved overload with comma op [PR115430] (*)
52d71b6... c++: DR2627, Bit-fields and narrowing conversions [PR94058] (*)
4d24159... Preserve SSA info for more propagated copy (*)
7a65ab6... RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM form (*)
6d98e88... RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM form (*)
bff0d02... RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM form (*)
ed213b3... RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM form (*)
589865a... testsuite: Fix -m32 gcc.target/i386/pr102464-vrndscaleph.c (*)
142b526... i386: Additional peephole2 to use lea in round-up integer d (*)
3d23abd... AVR: target/88236, target/115726 - Fix __memx code generati (*)
90c558e... testsuite/52641 - Adjust some test cases to less capable pl (*)
6400144... libgomp, openmp: Add ompx_gnu_pinned_mem_alloc (*)
90efaeb... libgomp: change alloc-pinned tests failure mode (*)
61aa380... libffi: Fix 32-bit SPARC structure passing [PR115681] (*)
286cda3... tree-optimization/115723 - ICE with .COND_ADD reduction (*)
382e212... [MAINTAINERS] Update my email address (*)
543a5b9... tree-optimization/115694 - ICE with complex store rewrite (*)
55f80c6... Remove vcond{,u,eq} expanders since they will be obso (*)
2ccdd0f... Optimize a < 0 ? -1 : 0 to (signed)a >> 31. (*)
e94e6ee... Adjust testcase for the regressed testcases after obsolete (*)
3cb2040... Add more splitter for mskmov with avx512 comparison. (*)
09737d9... Match IEEE min/max with UNSPEC_IEEE_{MIN,MAX}. (*)
b06a108... Lower AVX512 kmask comparison back to AVX2 comparison when (*)
2e2dfa0... Add more splitters to match (unspec [op1 op2 (gt op3 constm (*)
e62ea4f... Enable flate-combine. (*)
8e1fa10... Extend lshifrtsi3_1_zext to ?k alternative. (*)
5e1a9f4... Define mask as extern instead of uninitialized local variab (*)
76075bf... Daily bump. (*)
30ad2fa... hppa: Fix ICE caused by mismatched predicate and constraint (*)
b77f17c... tree-optimization/115701 - fix maybe_duplicate_ssa_info_at_ (*)
b5c64b4... tree-optimization/115701 - factor out maybe_duplicate_ssa_i (*)
b443d71... Harden SLP reduction support wrt STMT_VINFO_REDUC_IDX (*)
3aa004f... vect: Determine input vectype for multiple lane-reducing op (*)
1ff5f8f... vect: Fix shift-by-induction for single-lane slp (*)
1bcfed4... Daily bump. (*)
69bc5fb... [PR115565] cse: Don't use a valid regno for non-register in (*)
42946aa... [to-be-committed,RISC-V,V4] movmem for RISCV with V extensi (*)
7682d11... Fortran: fix ALLOCATE with SOURCE of deferred character len (*)
21e3565... Match: Support imm form for unsigned scalar .SAT_ADD (*)
45e74d5... jit: Fix Darwin bootstrap after r15-1699. (*)
9fbbad9... [committed] Fix mcore-elf regression after recent IRA chang (*)
614fd0f... Daily bump. (*)
50073ff... c++: bad 'this' conversion for nullary memfn [PR106760] (*)
52370c8... libstdc++: Define __glibcxx_assert_fail for non-verbose bui (*)
fab60ea... libstdc++: Extend std::equal memcmp optimization to std::by (*)
03d3aeb... libstdc++: Do not use C++11 alignof in C++98 mode [PR104395 (*)
ac8c61b... libstdc++: Simplify class templates (*)
(*) This commit already exists in another branch.
Because the reference `refs/users/meissner/heads/work171-tar' matches
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no separate email is sent for this commit.
[gcc(refs/users/meissner/heads/work171-tar)] Add ChangeLog.tar and update REVISION.
https://gcc.gnu.org/g:1fc2e4c688f9ccb7fe9fb97afc51bfe81f48733e commit 1fc2e4c688f9ccb7fe9fb97afc51bfe81f48733e Author: Michael Meissner Date: Fri Jun 28 15:06:24 2024 -0400 Add ChangeLog.tar and update REVISION. 2024-06-28 Michael Meissner gcc/ * ChangeLog.tar: New file for branch. * REVISION: Update. Diff: --- gcc/ChangeLog.tar | 6 ++ gcc/REVISION | 2 +- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog.tar b/gcc/ChangeLog.tar new file mode 100644 index 000..dbdff04e2fa --- /dev/null +++ b/gcc/ChangeLog.tar @@ -0,0 +1,6 @@ + Branch work171-tar, baseline + +2024-06-28 Michael Meissner + + Clone branch + diff --git a/gcc/REVISION b/gcc/REVISION index 060d0f9e831..da2e6621959 100644 --- a/gcc/REVISION +++ b/gcc/REVISION @@ -1 +1 @@ -work171 branch +work171-tar branch
[gcc(refs/users/meissner/heads/work171-tar)] Merge commit 'refs/users/meissner/heads/work171-tar' of git+ssh://gcc.gnu.org/git/gcc into me/work17
https://gcc.gnu.org/g:c70c1d9fef8896fd351273141cc4167d485d8bd6 commit c70c1d9fef8896fd351273141cc4167d485d8bd6 Merge: 1fc2e4c688f 96bcf7509f8 Author: Michael Meissner Date: Mon Jul 1 22:48:33 2024 -0400 Merge commit 'refs/users/meissner/heads/work171-tar' of git+ssh://gcc.gnu.org/git/gcc into me/work171-tar Diff:
[gcc/meissner/heads/work171-test] (54 commits) Merge commit 'refs/users/meissner/heads/work171-test' of gi
The branch 'meissner/heads/work171-test' was updated to point to:
610c6e705cf... Merge commit 'refs/users/meissner/heads/work171-test' of gi
It previously pointed to:
1e4c7929c90... Add ChangeLog.test and update REVISION.
Diff:
Summary of changes (added commits):
---
610c6e7... Merge commit 'refs/users/meissner/heads/work171-test' of gi
acb280b... Add ChangeLog.test and update REVISION.
1f0d0b5... Merge commit 'refs/users/meissner/heads/work171' of git+ssh (*)
f41f2d6... Add ChangeLog.meissner and REVISION. (*)
0b4fd67... Daily bump. (*)
c90e785... c++: ICE with computed gotos [PR115469] (*)
cb39f7d... testsuite: fix spaceship-narrowing1.C (*)
c847dcf... c++: unresolved overload with comma op [PR115430] (*)
52d71b6... c++: DR2627, Bit-fields and narrowing conversions [PR94058] (*)
4d24159... Preserve SSA info for more propagated copy (*)
7a65ab6... RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM form (*)
6d98e88... RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM form (*)
bff0d02... RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM form (*)
ed213b3... RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM form (*)
589865a... testsuite: Fix -m32 gcc.target/i386/pr102464-vrndscaleph.c (*)
142b526... i386: Additional peephole2 to use lea in round-up integer d (*)
3d23abd... AVR: target/88236, target/115726 - Fix __memx code generati (*)
90c558e... testsuite/52641 - Adjust some test cases to less capable pl (*)
6400144... libgomp, openmp: Add ompx_gnu_pinned_mem_alloc (*)
90efaeb... libgomp: change alloc-pinned tests failure mode (*)
61aa380... libffi: Fix 32-bit SPARC structure passing [PR115681] (*)
286cda3... tree-optimization/115723 - ICE with .COND_ADD reduction (*)
382e212... [MAINTAINERS] Update my email address (*)
543a5b9... tree-optimization/115694 - ICE with complex store rewrite (*)
55f80c6... Remove vcond{,u,eq} expanders since they will be obso (*)
2ccdd0f... Optimize a < 0 ? -1 : 0 to (signed)a >> 31. (*)
e94e6ee... Adjust testcase for the regressed testcases after obsolete (*)
3cb2040... Add more splitter for mskmov with avx512 comparison. (*)
09737d9... Match IEEE min/max with UNSPEC_IEEE_{MIN,MAX}. (*)
b06a108... Lower AVX512 kmask comparison back to AVX2 comparison when (*)
2e2dfa0... Add more splitters to match (unspec [op1 op2 (gt op3 constm (*)
e62ea4f... Enable flate-combine. (*)
8e1fa10... Extend lshifrtsi3_1_zext to ?k alternative. (*)
5e1a9f4... Define mask as extern instead of uninitialized local variab (*)
76075bf... Daily bump. (*)
30ad2fa... hppa: Fix ICE caused by mismatched predicate and constraint (*)
b77f17c... tree-optimization/115701 - fix maybe_duplicate_ssa_info_at_ (*)
b5c64b4... tree-optimization/115701 - factor out maybe_duplicate_ssa_i (*)
b443d71... Harden SLP reduction support wrt STMT_VINFO_REDUC_IDX (*)
3aa004f... vect: Determine input vectype for multiple lane-reducing op (*)
1ff5f8f... vect: Fix shift-by-induction for single-lane slp (*)
1bcfed4... Daily bump. (*)
69bc5fb... [PR115565] cse: Don't use a valid regno for non-register in (*)
42946aa... [to-be-committed,RISC-V,V4] movmem for RISCV with V extensi (*)
7682d11... Fortran: fix ALLOCATE with SOURCE of deferred character len (*)
21e3565... Match: Support imm form for unsigned scalar .SAT_ADD (*)
45e74d5... jit: Fix Darwin bootstrap after r15-1699. (*)
9fbbad9... [committed] Fix mcore-elf regression after recent IRA chang (*)
614fd0f... Daily bump. (*)
50073ff... c++: bad 'this' conversion for nullary memfn [PR106760] (*)
52370c8... libstdc++: Define __glibcxx_assert_fail for non-verbose bui (*)
fab60ea... libstdc++: Extend std::equal memcmp optimization to std::by (*)
03d3aeb... libstdc++: Do not use C++11 alignof in C++98 mode [PR104395 (*)
ac8c61b... libstdc++: Simplify class templates (*)
(*) This commit already exists in another branch.
Because the reference `refs/users/meissner/heads/work171-test' matches
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[gcc(refs/users/meissner/heads/work171-test)] Add ChangeLog.test and update REVISION.
https://gcc.gnu.org/g:acb280b2ed53fb9f7884ced5f35766ef13ea1c55 commit acb280b2ed53fb9f7884ced5f35766ef13ea1c55 Author: Michael Meissner Date: Fri Jun 28 15:08:09 2024 -0400 Add ChangeLog.test and update REVISION. 2024-06-28 Michael Meissner gcc/ * ChangeLog.test: New file for branch. * REVISION: Update. Diff: --- gcc/ChangeLog.test | 6 ++ gcc/REVISION | 2 +- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog.test b/gcc/ChangeLog.test new file mode 100644 index 000..c2893a28120 --- /dev/null +++ b/gcc/ChangeLog.test @@ -0,0 +1,6 @@ + Branch work171-test, baseline + +2024-06-28 Michael Meissner + + Clone branch + diff --git a/gcc/REVISION b/gcc/REVISION index 060d0f9e831..78d94f8c4ae 100644 --- a/gcc/REVISION +++ b/gcc/REVISION @@ -1 +1 @@ -work171 branch +work171-test branch
[gcc(refs/users/meissner/heads/work171-test)] Merge commit 'refs/users/meissner/heads/work171-test' of git+ssh://gcc.gnu.org/git/gcc into me/work1
https://gcc.gnu.org/g:610c6e705cf9debd3b16ec9bb43a95f1d410f7c1 commit 610c6e705cf9debd3b16ec9bb43a95f1d410f7c1 Merge: acb280b2ed5 1e4c7929c90 Author: Michael Meissner Date: Mon Jul 1 22:49:53 2024 -0400 Merge commit 'refs/users/meissner/heads/work171-test' of git+ssh://gcc.gnu.org/git/gcc into me/work171-test Diff:
[gcc(refs/users/meissner/heads/work171-vpair)] Merge commit 'refs/users/meissner/heads/work171-vpair' of git+ssh://gcc.gnu.org/git/gcc into me/work
https://gcc.gnu.org/g:08f8a254f512f85ffa98b2deece0d940fea35306 commit 08f8a254f512f85ffa98b2deece0d940fea35306 Merge: 6cde2ecc0bf a22705ca2c0 Author: Michael Meissner Date: Mon Jul 1 22:51:18 2024 -0400 Merge commit 'refs/users/meissner/heads/work171-vpair' of git+ssh://gcc.gnu.org/git/gcc into me/work171-vpair Diff:
[gcc/meissner/heads/work171-vpair] (54 commits) Merge commit 'refs/users/meissner/heads/work171-vpair' of g
The branch 'meissner/heads/work171-vpair' was updated to point to:
08f8a254f51... Merge commit 'refs/users/meissner/heads/work171-vpair' of g
It previously pointed to:
a22705ca2c0... Add ChangeLog.vpair and update REVISION.
Diff:
Summary of changes (added commits):
---
08f8a25... Merge commit 'refs/users/meissner/heads/work171-vpair' of g
6cde2ec... Add ChangeLog.vpair and update REVISION.
1f0d0b5... Merge commit 'refs/users/meissner/heads/work171' of git+ssh (*)
f41f2d6... Add ChangeLog.meissner and REVISION. (*)
0b4fd67... Daily bump. (*)
c90e785... c++: ICE with computed gotos [PR115469] (*)
cb39f7d... testsuite: fix spaceship-narrowing1.C (*)
c847dcf... c++: unresolved overload with comma op [PR115430] (*)
52d71b6... c++: DR2627, Bit-fields and narrowing conversions [PR94058] (*)
4d24159... Preserve SSA info for more propagated copy (*)
7a65ab6... RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM form (*)
6d98e88... RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM form (*)
bff0d02... RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM form (*)
ed213b3... RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM form (*)
589865a... testsuite: Fix -m32 gcc.target/i386/pr102464-vrndscaleph.c (*)
142b526... i386: Additional peephole2 to use lea in round-up integer d (*)
3d23abd... AVR: target/88236, target/115726 - Fix __memx code generati (*)
90c558e... testsuite/52641 - Adjust some test cases to less capable pl (*)
6400144... libgomp, openmp: Add ompx_gnu_pinned_mem_alloc (*)
90efaeb... libgomp: change alloc-pinned tests failure mode (*)
61aa380... libffi: Fix 32-bit SPARC structure passing [PR115681] (*)
286cda3... tree-optimization/115723 - ICE with .COND_ADD reduction (*)
382e212... [MAINTAINERS] Update my email address (*)
543a5b9... tree-optimization/115694 - ICE with complex store rewrite (*)
55f80c6... Remove vcond{,u,eq} expanders since they will be obso (*)
2ccdd0f... Optimize a < 0 ? -1 : 0 to (signed)a >> 31. (*)
e94e6ee... Adjust testcase for the regressed testcases after obsolete (*)
3cb2040... Add more splitter for mskmov with avx512 comparison. (*)
09737d9... Match IEEE min/max with UNSPEC_IEEE_{MIN,MAX}. (*)
b06a108... Lower AVX512 kmask comparison back to AVX2 comparison when (*)
2e2dfa0... Add more splitters to match (unspec [op1 op2 (gt op3 constm (*)
e62ea4f... Enable flate-combine. (*)
8e1fa10... Extend lshifrtsi3_1_zext to ?k alternative. (*)
5e1a9f4... Define mask as extern instead of uninitialized local variab (*)
76075bf... Daily bump. (*)
30ad2fa... hppa: Fix ICE caused by mismatched predicate and constraint (*)
b77f17c... tree-optimization/115701 - fix maybe_duplicate_ssa_info_at_ (*)
b5c64b4... tree-optimization/115701 - factor out maybe_duplicate_ssa_i (*)
b443d71... Harden SLP reduction support wrt STMT_VINFO_REDUC_IDX (*)
3aa004f... vect: Determine input vectype for multiple lane-reducing op (*)
1ff5f8f... vect: Fix shift-by-induction for single-lane slp (*)
1bcfed4... Daily bump. (*)
69bc5fb... [PR115565] cse: Don't use a valid regno for non-register in (*)
42946aa... [to-be-committed,RISC-V,V4] movmem for RISCV with V extensi (*)
7682d11... Fortran: fix ALLOCATE with SOURCE of deferred character len (*)
21e3565... Match: Support imm form for unsigned scalar .SAT_ADD (*)
45e74d5... jit: Fix Darwin bootstrap after r15-1699. (*)
9fbbad9... [committed] Fix mcore-elf regression after recent IRA chang (*)
614fd0f... Daily bump. (*)
50073ff... c++: bad 'this' conversion for nullary memfn [PR106760] (*)
52370c8... libstdc++: Define __glibcxx_assert_fail for non-verbose bui (*)
fab60ea... libstdc++: Extend std::equal memcmp optimization to std::by (*)
03d3aeb... libstdc++: Do not use C++11 alignof in C++98 mode [PR104395 (*)
ac8c61b... libstdc++: Simplify class templates (*)
(*) This commit already exists in another branch.
Because the reference `refs/users/meissner/heads/work171-vpair' matches
your hooks.email-new-commits-only configuration,
no separate email is sent for this commit.
[gcc(refs/users/meissner/heads/work171-vpair)] Add ChangeLog.vpair and update REVISION.
https://gcc.gnu.org/g:6cde2ecc0bf2a276811bfbab7db67a60a972bfd7 commit 6cde2ecc0bf2a276811bfbab7db67a60a972bfd7 Author: Michael Meissner Date: Fri Jun 28 15:05:36 2024 -0400 Add ChangeLog.vpair and update REVISION. 2024-06-28 Michael Meissner gcc/ * ChangeLog.vpair: New file for branch. * REVISION: Update. Diff: --- gcc/ChangeLog.vpair | 6 ++ gcc/REVISION| 2 +- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog.vpair b/gcc/ChangeLog.vpair new file mode 100644 index 000..eb6dd427796 --- /dev/null +++ b/gcc/ChangeLog.vpair @@ -0,0 +1,6 @@ + Branch work171-vpair, baseline + +2024-06-28 Michael Meissner + + Clone branch + diff --git a/gcc/REVISION b/gcc/REVISION index 060d0f9e831..6cef7066a80 100644 --- a/gcc/REVISION +++ b/gcc/REVISION @@ -1 +1 @@ -work171 branch +work171-vpair branch
[gcc/meissner/heads/work171-orig] (52 commits) Merge commit 'refs/users/meissner/heads/work171-orig' of gi
The branch 'meissner/heads/work171-orig' was updated to point to:
f745ee5a0dd... Merge commit 'refs/users/meissner/heads/work171-orig' of gi
It previously pointed to:
547ef5be3d3... Add REVISION.
Diff:
Summary of changes (added commits):
---
f745ee5... Merge commit 'refs/users/meissner/heads/work171-orig' of gi
ebaf415... Add REVISION.
0b4fd67... Daily bump. (*)
c90e785... c++: ICE with computed gotos [PR115469] (*)
cb39f7d... testsuite: fix spaceship-narrowing1.C (*)
c847dcf... c++: unresolved overload with comma op [PR115430] (*)
52d71b6... c++: DR2627, Bit-fields and narrowing conversions [PR94058] (*)
4d24159... Preserve SSA info for more propagated copy (*)
7a65ab6... RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM form (*)
6d98e88... RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM form (*)
bff0d02... RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM form (*)
ed213b3... RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM form (*)
589865a... testsuite: Fix -m32 gcc.target/i386/pr102464-vrndscaleph.c (*)
142b526... i386: Additional peephole2 to use lea in round-up integer d (*)
3d23abd... AVR: target/88236, target/115726 - Fix __memx code generati (*)
90c558e... testsuite/52641 - Adjust some test cases to less capable pl (*)
6400144... libgomp, openmp: Add ompx_gnu_pinned_mem_alloc (*)
90efaeb... libgomp: change alloc-pinned tests failure mode (*)
61aa380... libffi: Fix 32-bit SPARC structure passing [PR115681] (*)
286cda3... tree-optimization/115723 - ICE with .COND_ADD reduction (*)
382e212... [MAINTAINERS] Update my email address (*)
543a5b9... tree-optimization/115694 - ICE with complex store rewrite (*)
55f80c6... Remove vcond{,u,eq} expanders since they will be obso (*)
2ccdd0f... Optimize a < 0 ? -1 : 0 to (signed)a >> 31. (*)
e94e6ee... Adjust testcase for the regressed testcases after obsolete (*)
3cb2040... Add more splitter for mskmov with avx512 comparison. (*)
09737d9... Match IEEE min/max with UNSPEC_IEEE_{MIN,MAX}. (*)
b06a108... Lower AVX512 kmask comparison back to AVX2 comparison when (*)
2e2dfa0... Add more splitters to match (unspec [op1 op2 (gt op3 constm (*)
e62ea4f... Enable flate-combine. (*)
8e1fa10... Extend lshifrtsi3_1_zext to ?k alternative. (*)
5e1a9f4... Define mask as extern instead of uninitialized local variab (*)
76075bf... Daily bump. (*)
30ad2fa... hppa: Fix ICE caused by mismatched predicate and constraint (*)
b77f17c... tree-optimization/115701 - fix maybe_duplicate_ssa_info_at_ (*)
b5c64b4... tree-optimization/115701 - factor out maybe_duplicate_ssa_i (*)
b443d71... Harden SLP reduction support wrt STMT_VINFO_REDUC_IDX (*)
3aa004f... vect: Determine input vectype for multiple lane-reducing op (*)
1ff5f8f... vect: Fix shift-by-induction for single-lane slp (*)
1bcfed4... Daily bump. (*)
69bc5fb... [PR115565] cse: Don't use a valid regno for non-register in (*)
42946aa... [to-be-committed,RISC-V,V4] movmem for RISCV with V extensi (*)
7682d11... Fortran: fix ALLOCATE with SOURCE of deferred character len (*)
21e3565... Match: Support imm form for unsigned scalar .SAT_ADD (*)
45e74d5... jit: Fix Darwin bootstrap after r15-1699. (*)
9fbbad9... [committed] Fix mcore-elf regression after recent IRA chang (*)
614fd0f... Daily bump. (*)
50073ff... c++: bad 'this' conversion for nullary memfn [PR106760] (*)
52370c8... libstdc++: Define __glibcxx_assert_fail for non-verbose bui (*)
fab60ea... libstdc++: Extend std::equal memcmp optimization to std::by (*)
03d3aeb... libstdc++: Do not use C++11 alignof in C++98 mode [PR104395 (*)
ac8c61b... libstdc++: Simplify class templates (*)
(*) This commit already exists in another branch.
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no separate email is sent for this commit.
[gcc(refs/users/meissner/heads/work171-orig)] Add REVISION.
https://gcc.gnu.org/g:ebaf415b9e1d41e2707903d06fac29f79e765e77 commit ebaf415b9e1d41e2707903d06fac29f79e765e77 Author: Michael Meissner Date: Fri Jun 28 15:09:42 2024 -0400 Add REVISION. 2024-06-28 Michael Meissner gcc/ * REVISION: New file for branch. Diff: --- gcc/REVISION | 1 + 1 file changed, 1 insertion(+) diff --git a/gcc/REVISION b/gcc/REVISION new file mode 100644 index 000..546b088ed52 --- /dev/null +++ b/gcc/REVISION @@ -0,0 +1 @@ +work171-orig branch
[gcc(refs/users/meissner/heads/work171-orig)] Merge commit 'refs/users/meissner/heads/work171-orig' of git+ssh://gcc.gnu.org/git/gcc into me/work1
https://gcc.gnu.org/g:f745ee5a0dde7a43b384dcd9bfac7b9a74c8826c commit f745ee5a0dde7a43b384dcd9bfac7b9a74c8826c Merge: ebaf415b9e1 547ef5be3d3 Author: Michael Meissner Date: Mon Jul 1 23:00:18 2024 -0400 Merge commit 'refs/users/meissner/heads/work171-orig' of git+ssh://gcc.gnu.org/git/gcc into me/work171-orig Diff:
