[gcc r15-1394] c23: Fix for redeclared enumerator initialized with different type [PR115109]

[Martin Uecker via Gcc-cvs]

https://gcc.gnu.org/g:c9b96a68860bfdee49d40b4a844af7c5ef69cd12

commit r15-1394-gc9b96a68860bfdee49d40b4a844af7c5ef69cd12
Author: Martin Uecker 
Date:   Sat May 18 22:00:04 2024 +0200

c23: Fix for redeclared enumerator initialized with different type 
[PR115109]

c23 specifies that the type of a redeclared enumerator is the one of the
previous declaration.  Convert initializers with different type accordingly
and emit an error when the value does not fit.

2024-06-01 Martin Uecker  

PR c/115109

gcc/c/
* c-decl.cc (build_enumerator): When redeclaring an
enumerator convert value to previous type.  For redeclared
enumerators use underlying type for computing the next value.

gcc/testsuite/
* gcc.dg/pr115109.c: New test.
* gcc.dg/c23-tag-enum-6.c: New test.
* gcc.dg/c23-tag-enum-7.c: New test.

Diff:
---
 gcc/c/c-decl.cc   | 29 ++---
 gcc/testsuite/gcc.dg/c23-tag-enum-6.c | 20 +
 gcc/testsuite/gcc.dg/c23-tag-enum-7.c | 41 +++
 gcc/testsuite/gcc.dg/pr115109.c   |  8 +++
 4 files changed, 95 insertions(+), 3 deletions(-)

diff --git a/gcc/c/c-decl.cc b/gcc/c/c-decl.cc
index 6c09eb731284..01326570e2b2 100644
--- a/gcc/c/c-decl.cc
+++ b/gcc/c/c-decl.cc
@@ -10277,6 +10277,7 @@ build_enumerator (location_t decl_loc, location_t loc,
  struct c_enum_contents *the_enum, tree name, tree value)
 {
   tree decl;
+  tree old_decl;
 
   /* Validate and default VALUE.  */
 
@@ -10336,6 +10337,23 @@ build_enumerator (location_t decl_loc, location_t loc,
 definition.  */
   value = convert (the_enum->enum_type, value);
 }
+  else if (flag_isoc23
+  && (old_decl = lookup_name_in_scope (name, current_scope))
+  && old_decl != error_mark_node
+  && TREE_TYPE (old_decl)
+  && TREE_TYPE (TREE_TYPE (old_decl))
+  && TREE_CODE (old_decl) == CONST_DECL)
+{
+  /* Enumeration constants in a redeclaration have the previous type.  */
+  tree previous_type = TREE_TYPE (DECL_INITIAL (old_decl));
+  if (!int_fits_type_p (value, previous_type))
+   {
+ error_at (loc, "value of redeclared enumerator outside the range "
+"of %qT", previous_type);
+ locate_old_decl (old_decl);
+   }
+  value = convert (previous_type, value);
+}
   else
 {
   /* Even though the underlying type of an enum is unspecified, the
@@ -10402,9 +10420,14 @@ build_enumerator (location_t decl_loc, location_t loc,
 false);
 }
   else
-the_enum->enum_next_value
-  = build_binary_op (EXPR_LOC_OR_LOC (value, input_location),
-PLUS_EXPR, value, integer_one_node, false);
+{
+  /* In a redeclaration the type can already be the enumeral type.  */
+  if (TREE_CODE (TREE_TYPE (value)) == ENUMERAL_TYPE)
+   value = convert (ENUM_UNDERLYING_TYPE (TREE_TYPE (value)), value);
+  the_enum->enum_next_value
+   = build_binary_op (EXPR_LOC_OR_LOC (value, input_location),
+  PLUS_EXPR, value, integer_one_node, false);
+}
   the_enum->enum_overflow = tree_int_cst_lt (the_enum->enum_next_value, value);
   if (the_enum->enum_overflow
   && !ENUM_FIXED_UNDERLYING_TYPE_P (the_enum->enum_type))
diff --git a/gcc/testsuite/gcc.dg/c23-tag-enum-6.c 
b/gcc/testsuite/gcc.dg/c23-tag-enum-6.c
new file mode 100644
index ..29aef7ee3fdf
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/c23-tag-enum-6.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-options "-std=c23 -fno-short-enums" } */
+
+#include 
+
+enum E : int { a = 1, b = 2 };
+enum E : int { b = _Generic(a, enum E: 2), a = 1 };
+
+enum H { x = 1 };
+enum H { x = 2UL + UINT_MAX }; /* { dg-error "outside the range" } */
+
+enum K : int { z = 1 };
+enum K : int { z = 2UL + UINT_MAX };   /* { dg-error "outside the range" } */
+
+enum F { A = 0, B = UINT_MAX };
+enum F { B = UINT_MAX, A };/* { dg-error "outside the range" } */
+
+enum G : unsigned int { C = 0, D = UINT_MAX };
+enum G : unsigned int { D = UINT_MAX, C }; /* { dg-error 
"overflow" } */
+
diff --git a/gcc/testsuite/gcc.dg/c23-tag-enum-7.c 
b/gcc/testsuite/gcc.dg/c23-tag-enum-7.c
new file mode 100644
index ..d4c787c8f716
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/c23-tag-enum-7.c
@@ -0,0 +1,41 @@
+/* { dg-do compile }
+ * { dg-options "-std=c23 -fno-short-enums" } */
+
+#include 
+
+// enumerators are all representable in int
+enum E { a = 1UL, b = _Generic(a, int: 2) };
+static_assert(_Generic(a, int: 1));
+static_assert(_Generic(b, int: 1));
+enum E { a = 1UL, b = _Generic(a, int: 2) };
+static_assert(_Generic(a, int: 1));
+static_assert(_Generic(b, int: 1));
+
+// enumerators are not representable in int
+enum H { c = 1UL << (UINT_WIDTH + 1)

[gcc r15-1395] Make force_subreg emit nothing on failure

[Richard Sandiford via Gcc-cvs]

https://gcc.gnu.org/g:01044471ea39f9be4803c583ef2a946abc657f99

commit r15-1395-g01044471ea39f9be4803c583ef2a946abc657f99
Author: Richard Sandiford 
Date:   Tue Jun 18 12:22:30 2024 +0100

Make force_subreg emit nothing on failure

While adding more uses of force_subreg, I realised that it should
be more careful to emit no instructions on failure.  This kind of
failure should be very rare, so I don't think it's a case worth
optimising for.

gcc/
* explow.cc (force_subreg): Emit no instructions on failure.

Diff:
---
 gcc/explow.cc | 6 +-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/gcc/explow.cc b/gcc/explow.cc
index f6843398c4b0..bd93c8780649 100644
--- a/gcc/explow.cc
+++ b/gcc/explow.cc
@@ -756,8 +756,12 @@ force_subreg (machine_mode outermode, rtx op,
   if (x)
 return x;
 
+  auto *start = get_last_insn ();
   op = copy_to_mode_reg (innermode, op);
-  return simplify_gen_subreg (outermode, op, innermode, byte);
+  rtx res = simplify_gen_subreg (outermode, op, innermode, byte);
+  if (!res)
+delete_insns_since (start);
+  return res;
 }
 
 /* If X is a memory ref, copy its contents to a new temp reg and return

[gcc r15-1396] aarch64: Use force_subreg in more places

[Richard Sandiford via Gcc-cvs]

https://gcc.gnu.org/g:1474a8eead4ab390e59ee014befa8c40346679f4

commit r15-1396-g1474a8eead4ab390e59ee014befa8c40346679f4
Author: Richard Sandiford 
Date:   Tue Jun 18 12:22:30 2024 +0100

aarch64: Use force_subreg in more places

This patch makes the aarch64 code use force_subreg instead of
simplify_gen_subreg in more places.  The criteria were:

(1) The code is obviously specific to expand (where new pseudos
can be created).

(2) The value is obviously an rvalue rather than an lvalue.

(3) The offset wasn't a simple lowpart or highpart calculation;
a later patch will deal with those.

gcc/
* config/aarch64/aarch64-builtins.cc (aarch64_expand_fcmla_builtin):
Use force_subreg instead of simplify_gen_subreg.
* config/aarch64/aarch64-simd.md (ctz2): Likewise.
* config/aarch64/aarch64-sve-builtins-base.cc
(svget_impl::expand): Likewise.
(svget_neonq_impl::expand): Likewise.
* config/aarch64/aarch64-sve-builtins-functions.h
(multireg_permute::expand): Likewise.

Diff:
---
 gcc/config/aarch64/aarch64-builtins.cc  | 4 ++--
 gcc/config/aarch64/aarch64-simd.md  | 4 ++--
 gcc/config/aarch64/aarch64-sve-builtins-base.cc | 8 +++-
 gcc/config/aarch64/aarch64-sve-builtins-functions.h | 6 +++---
 4 files changed, 10 insertions(+), 12 deletions(-)

diff --git a/gcc/config/aarch64/aarch64-builtins.cc 
b/gcc/config/aarch64/aarch64-builtins.cc
index d589e59defc2..7d827cbc2ac0 100644
--- a/gcc/config/aarch64/aarch64-builtins.cc
+++ b/gcc/config/aarch64/aarch64-builtins.cc
@@ -2592,12 +2592,12 @@ aarch64_expand_fcmla_builtin (tree exp, rtx target, int 
fcode)
   rtx temp2 = gen_reg_rtx (DImode);
   temp1 = simplify_gen_subreg (d->mode, op2, quadmode,
   subreg_lowpart_offset (d->mode, quadmode));
-  temp1 = simplify_gen_subreg (V2DImode, temp1, d->mode, 0);
+  temp1 = force_subreg (V2DImode, temp1, d->mode, 0);
   if (BYTES_BIG_ENDIAN)
emit_insn (gen_aarch64_get_lanev2di (temp2, temp1, const0_rtx));
   else
emit_insn (gen_aarch64_get_lanev2di (temp2, temp1, const1_rtx));
-  op2 = simplify_gen_subreg (d->mode, temp2, GET_MODE (temp2), 0);
+  op2 = force_subreg (d->mode, temp2, GET_MODE (temp2), 0);
 
   /* And recalculate the index.  */
   lane -= nunits / 4;
diff --git a/gcc/config/aarch64/aarch64-simd.md 
b/gcc/config/aarch64/aarch64-simd.md
index 0bb39091a385..01b084d8ccb5 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -389,8 +389,8 @@
   "TARGET_SIMD"
   {
  emit_insn (gen_bswap2 (operands[0], operands[1]));
- rtx op0_castsi2qi = simplify_gen_subreg(mode, operands[0],
-mode, 0);
+ rtx op0_castsi2qi = force_subreg (mode, operands[0],
+  mode, 0);
  emit_insn (gen_aarch64_rbit (op0_castsi2qi, op0_castsi2qi));
  emit_insn (gen_clz2 (operands[0], operands[0]));
  DONE;
diff --git a/gcc/config/aarch64/aarch64-sve-builtins-base.cc 
b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
index 823d60040f9a..999320371247 100644
--- a/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+++ b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
@@ -1121,9 +1121,8 @@ public:
   expand (function_expander &e) const override
   {
 /* Fold the access into a subreg rvalue.  */
-return simplify_gen_subreg (e.vector_mode (0), e.args[0],
-   GET_MODE (e.args[0]),
-   INTVAL (e.args[1]) * BYTES_PER_SVE_VECTOR);
+return force_subreg (e.vector_mode (0), e.args[0], GET_MODE (e.args[0]),
+INTVAL (e.args[1]) * BYTES_PER_SVE_VECTOR);
   }
 };
 
@@ -1157,8 +1156,7 @@ public:
e.add_fixed_operand (indices);
return e.generate_insn (icode);
   }
-return simplify_gen_subreg (e.result_mode (), e.args[0],
-   GET_MODE (e.args[0]), 0);
+return force_subreg (e.result_mode (), e.args[0], GET_MODE (e.args[0]), 0);
   }
 };
 
diff --git a/gcc/config/aarch64/aarch64-sve-builtins-functions.h 
b/gcc/config/aarch64/aarch64-sve-builtins-functions.h
index 3b8e575e98e7..7d06a57ff834 100644
--- a/gcc/config/aarch64/aarch64-sve-builtins-functions.h
+++ b/gcc/config/aarch64/aarch64-sve-builtins-functions.h
@@ -639,9 +639,9 @@ public:
   {
machine_mode elt_mode = e.vector_mode (0);
rtx arg = e.args[0];
-   e.args[0] = simplify_gen_subreg (elt_mode, arg, GET_MODE (arg), 0);
-   e.args.safe_push (simplify_gen_subreg (elt_mode, arg, GET_MODE (arg),
-  GET_MODE_SIZE (elt_mode)));
+   e.args[0] = force_subreg (elt_mode, arg, GET_MODE (arg), 0);
+   e.args.safe_push (force_subreg (elt_mode, arg, GET_MODE (arg),
+

[gcc r15-1397] Make more use of force_subreg

[Richard Sandiford via Gcc-cvs]

https://gcc.gnu.org/g:d4047da6a070175aae7121c739d1cad6b08ff4b2

commit r15-1397-gd4047da6a070175aae7121c739d1cad6b08ff4b2
Author: Richard Sandiford 
Date:   Tue Jun 18 12:22:30 2024 +0100

Make more use of force_subreg

This patch makes target-independent code use force_subreg instead
of simplify_gen_subreg in some places.  The criteria were:

(1) The code is obviously specific to expand (where new pseudos
can be created), or at least would be invalid to call when
!can_create_pseudo_p () and temporaries are needed.

(2) The value is obviously an rvalue rather than an lvalue.

(3) The offset wasn't a simple lowpart or highpart calculation;
a later patch will deal with those.

Doing this should reduce the likelihood of bugs like PR115464
occuring in other situations.

gcc/
* expmed.cc (store_bit_field_using_insv): Use force_subreg
instead of simplify_gen_subreg.
(store_bit_field_1): Likewise.
(extract_bit_field_as_subreg): Likewise.
(extract_integral_bit_field): Likewise.
(emit_store_flag_1): Likewise.
* expr.cc (convert_move): Likewise.
(convert_modes): Likewise.
(emit_group_load_1): Likewise.
(emit_group_store): Likewise.
(expand_assignment): Likewise.

Diff:
---
 gcc/expmed.cc | 22 --
 gcc/expr.cc   | 27 ---
 2 files changed, 20 insertions(+), 29 deletions(-)

diff --git a/gcc/expmed.cc b/gcc/expmed.cc
index 9ba01695f538..1f68e7be721d 100644
--- a/gcc/expmed.cc
+++ b/gcc/expmed.cc
@@ -695,13 +695,7 @@ store_bit_field_using_insv (const extraction_insn *insv, 
rtx op0,
 if we must narrow it, be sure we do it correctly.  */
 
  if (GET_MODE_SIZE (value_mode) < GET_MODE_SIZE (op_mode))
-   {
- tmp = simplify_subreg (op_mode, value1, value_mode, 0);
- if (! tmp)
-   tmp = simplify_gen_subreg (op_mode,
-  force_reg (value_mode, value1),
-  value_mode, 0);
-   }
+   tmp = force_subreg (op_mode, value1, value_mode, 0);
  else
{
  if (targetm.mode_rep_extended (op_mode, value_mode) != UNKNOWN)
@@ -806,7 +800,7 @@ store_bit_field_1 (rtx str_rtx, poly_uint64 bitsize, 
poly_uint64 bitnum,
   if (known_eq (bitnum, 0U)
  && known_eq (bitsize, GET_MODE_BITSIZE (GET_MODE (op0
{
- sub = simplify_gen_subreg (GET_MODE (op0), value, fieldmode, 0);
+ sub = force_subreg (GET_MODE (op0), value, fieldmode, 0);
  if (sub)
{
  if (reverse)
@@ -1633,7 +1627,7 @@ extract_bit_field_as_subreg (machine_mode mode, rtx op0,
   && known_eq (bitsize, GET_MODE_BITSIZE (mode))
   && lowpart_bit_field_p (bitnum, bitsize, op0_mode)
   && TRULY_NOOP_TRUNCATION_MODES_P (mode, op0_mode))
-return simplify_gen_subreg (mode, op0, op0_mode, bytenum);
+return force_subreg (mode, op0, op0_mode, bytenum);
   return NULL_RTX;
 }
 
@@ -2000,11 +1994,11 @@ extract_integral_bit_field (rtx op0, 
opt_scalar_int_mode op0_mode,
  return convert_extracted_bit_field (target, mode, tmode, unsignedp);
}
   /* If OP0 is a hard register, copy it to a pseudo before calling
-simplify_gen_subreg.  */
+force_subreg.  */
   if (REG_P (op0) && HARD_REGISTER_P (op0))
op0 = copy_to_reg (op0);
-  op0 = simplify_gen_subreg (word_mode, op0, op0_mode.require (),
-bitnum / BITS_PER_WORD * UNITS_PER_WORD);
+  op0 = force_subreg (word_mode, op0, op0_mode.require (),
+ bitnum / BITS_PER_WORD * UNITS_PER_WORD);
   op0_mode = word_mode;
   bitnum %= BITS_PER_WORD;
 }
@@ -5774,8 +5768,8 @@ emit_store_flag_1 (rtx target, enum rtx_code code, rtx 
op0, rtx op1,
 
  /* Do a logical OR or AND of the two words and compare the
 result.  */
- op00 = simplify_gen_subreg (word_mode, op0, int_mode, 0);
- op01 = simplify_gen_subreg (word_mode, op0, int_mode, UNITS_PER_WORD);
+ op00 = force_subreg (word_mode, op0, int_mode, 0);
+ op01 = force_subreg (word_mode, op0, int_mode, UNITS_PER_WORD);
  tem = expand_binop (word_mode,
  op1 == const0_rtx ? ior_optab : and_optab,
  op00, op01, NULL_RTX, unsignedp,
diff --git a/gcc/expr.cc b/gcc/expr.cc
index 9cecc1758f5c..31a7346e33f0 100644
--- a/gcc/expr.cc
+++ b/gcc/expr.cc
@@ -301,7 +301,7 @@ convert_move (rtx to, rtx from, int unsignedp)
GET_MODE_BITSIZE (to_mode)));
 
   if (VECTOR_MODE_P (to_mode))
-   from = simplify_gen_subreg (to_mode, from, GET_MODE (from), 0);
+   from = force_subreg (to_mode, from, GET_MODE (from), 0);
   else
   

[gcc r15-1398] Add force_lowpart_subreg

[Richard Sandiford via Gcc-cvs]

https://gcc.gnu.org/g:5f40d1c0cc6ce91ef28d326b8707b3f05e6f239c

commit r15-1398-g5f40d1c0cc6ce91ef28d326b8707b3f05e6f239c
Author: Richard Sandiford 
Date:   Tue Jun 18 12:22:31 2024 +0100

Add force_lowpart_subreg

optabs had a local function called lowpart_subreg_maybe_copy
that is very similar to the lowpart version of force_subreg.
This patch adds a force_lowpart_subreg wrapper around
force_subreg and uses it in optabs.cc.

The only difference between the old and new functions is that
the old one asserted success while the new one doesn't.
It's common not to assert elsewhere when taking subregs;
normally a null result is enough.

Later patches will make more use of the new function.

gcc/
* explow.h (force_lowpart_subreg): Declare.
* explow.cc (force_lowpart_subreg): New function.
* optabs.cc (lowpart_subreg_maybe_copy): Delete.
(expand_absneg_bit): Use force_lowpart_subreg instead of
lowpart_subreg_maybe_copy.
(expand_copysign_bit): Likewise.

Diff:
---
 gcc/explow.cc | 14 ++
 gcc/explow.h  |  1 +
 gcc/optabs.cc | 24 ++--
 3 files changed, 17 insertions(+), 22 deletions(-)

diff --git a/gcc/explow.cc b/gcc/explow.cc
index bd93c8780649..2a91cf76ea62 100644
--- a/gcc/explow.cc
+++ b/gcc/explow.cc
@@ -764,6 +764,20 @@ force_subreg (machine_mode outermode, rtx op,
   return res;
 }
 
+/* Try to return an rvalue expression for the OUTERMODE lowpart of OP,
+   which has mode INNERMODE.  Allow OP to be forced into a new register
+   if necessary.
+
+   Return null on failure.  */
+
+rtx
+force_lowpart_subreg (machine_mode outermode, rtx op,
+ machine_mode innermode)
+{
+  auto byte = subreg_lowpart_offset (outermode, innermode);
+  return force_subreg (outermode, op, innermode, byte);
+}
+
 /* If X is a memory ref, copy its contents to a new temp reg and return
that reg.  Otherwise, return X.  */
 
diff --git a/gcc/explow.h b/gcc/explow.h
index cbd1fcb7eb34..dd654649b068 100644
--- a/gcc/explow.h
+++ b/gcc/explow.h
@@ -43,6 +43,7 @@ extern rtx copy_to_suggested_reg (rtx, rtx, machine_mode);
 extern rtx force_reg (machine_mode, rtx);
 
 extern rtx force_subreg (machine_mode, rtx, machine_mode, poly_uint64);
+extern rtx force_lowpart_subreg (machine_mode, rtx, machine_mode);
 
 /* Return given rtx, copied into a new temp reg if it was in memory.  */
 extern rtx force_not_mem (rtx);
diff --git a/gcc/optabs.cc b/gcc/optabs.cc
index c54d275b8b7a..d569742beea9 100644
--- a/gcc/optabs.cc
+++ b/gcc/optabs.cc
@@ -3096,26 +3096,6 @@ expand_ffs (scalar_int_mode mode, rtx op0, rtx target)
   return 0;
 }
 
-/* Extract the OMODE lowpart from VAL, which has IMODE.  Under certain
-   conditions, VAL may already be a SUBREG against which we cannot generate
-   a further SUBREG.  In this case, we expect forcing the value into a
-   register will work around the situation.  */
-
-static rtx
-lowpart_subreg_maybe_copy (machine_mode omode, rtx val,
-  machine_mode imode)
-{
-  rtx ret;
-  ret = lowpart_subreg (omode, val, imode);
-  if (ret == NULL)
-{
-  val = force_reg (imode, val);
-  ret = lowpart_subreg (omode, val, imode);
-  gcc_assert (ret != NULL);
-}
-  return ret;
-}
-
 /* Expand a floating point absolute value or negation operation via a
logical operation on the sign bit.  */
 
@@ -3204,7 +3184,7 @@ expand_absneg_bit (enum rtx_code code, scalar_float_mode 
mode,
   gen_lowpart (imode, op0),
   immed_wide_int_const (mask, imode),
   gen_lowpart (imode, target), 1, OPTAB_LIB_WIDEN);
-  target = lowpart_subreg_maybe_copy (mode, temp, imode);
+  target = force_lowpart_subreg (mode, temp, imode);
 
   set_dst_reg_note (get_last_insn (), REG_EQUAL,
gen_rtx_fmt_e (code, mode, copy_rtx (op0)),
@@ -4043,7 +4023,7 @@ expand_copysign_bit (scalar_float_mode mode, rtx op0, rtx 
op1, rtx target,
 
   temp = expand_binop (imode, ior_optab, op0, op1,
   gen_lowpart (imode, target), 1, OPTAB_LIB_WIDEN);
-  target = lowpart_subreg_maybe_copy (mode, temp, imode);
+  target = force_lowpart_subreg (mode, temp, imode);
 }
 
   return target;

[gcc r15-1399] aarch64: Add some uses of force_lowpart_subreg

[Richard Sandiford via Gcc-cvs]

https://gcc.gnu.org/g:6bd4fbae45d11795a9a6f54b866308d4d7134def

commit r15-1399-g6bd4fbae45d11795a9a6f54b866308d4d7134def
Author: Richard Sandiford 
Date:   Tue Jun 18 12:22:31 2024 +0100

aarch64: Add some uses of force_lowpart_subreg

This patch makes more use of force_lowpart_subreg, similarly
to the recent patch for force_subreg.  The criteria were:

(1) The code is obviously specific to expand (where new pseudos
can be created).

(2) The value is obviously an rvalue rather than an lvalue.

gcc/
PR target/115464
* config/aarch64/aarch64-builtins.cc (aarch64_expand_fcmla_builtin)
(aarch64_expand_rwsr_builtin): Use force_lowpart_subreg instead of
simplify_gen_subreg and lowpart_subreg.
* config/aarch64/aarch64-sve-builtins-base.cc
(svset_neonq_impl::expand): Likewise.
* config/aarch64/aarch64-sve-builtins-sme.cc
(add_load_store_slice_operand): Likewise.
* config/aarch64/aarch64.cc (aarch64_sve_reinterpret): Likewise.
(aarch64_addti_scratch_regs, aarch64_subvti_scratch_regs): Likewise.

gcc/testsuite/
PR target/115464
* gcc.target/aarch64/sve/acle/general/pr115464_2.c: New test.

Diff:
---
 gcc/config/aarch64/aarch64-builtins.cc | 11 +--
 gcc/config/aarch64/aarch64-sve-builtins-base.cc|  2 +-
 gcc/config/aarch64/aarch64-sve-builtins-sme.cc |  2 +-
 gcc/config/aarch64/aarch64.cc  | 14 +-
 .../gcc.target/aarch64/sve/acle/general/pr115464_2.c   | 11 +++
 5 files changed, 23 insertions(+), 17 deletions(-)

diff --git a/gcc/config/aarch64/aarch64-builtins.cc 
b/gcc/config/aarch64/aarch64-builtins.cc
index 7d827cbc2ac0..30669f8aa182 100644
--- a/gcc/config/aarch64/aarch64-builtins.cc
+++ b/gcc/config/aarch64/aarch64-builtins.cc
@@ -2579,8 +2579,7 @@ aarch64_expand_fcmla_builtin (tree exp, rtx target, int 
fcode)
   int lane = INTVAL (lane_idx);
 
   if (lane < nunits / 4)
-op2 = simplify_gen_subreg (d->mode, op2, quadmode,
-  subreg_lowpart_offset (d->mode, quadmode));
+op2 = force_lowpart_subreg (d->mode, op2, quadmode);
   else
 {
   /* Select the upper 64 bits, either a V2SF or V4HF, this however
@@ -2590,8 +2589,7 @@ aarch64_expand_fcmla_builtin (tree exp, rtx target, int 
fcode)
 gen_highpart_mode generates code that isn't optimal.  */
   rtx temp1 = gen_reg_rtx (d->mode);
   rtx temp2 = gen_reg_rtx (DImode);
-  temp1 = simplify_gen_subreg (d->mode, op2, quadmode,
-  subreg_lowpart_offset (d->mode, quadmode));
+  temp1 = force_lowpart_subreg (d->mode, op2, quadmode);
   temp1 = force_subreg (V2DImode, temp1, d->mode, 0);
   if (BYTES_BIG_ENDIAN)
emit_insn (gen_aarch64_get_lanev2di (temp2, temp1, const0_rtx));
@@ -2836,7 +2834,7 @@ aarch64_expand_rwsr_builtin (tree exp, rtx target, int 
fcode)
case AARCH64_WSR64:
case AARCH64_WSRF64:
case AARCH64_WSR128:
- subreg = lowpart_subreg (sysreg_mode, input_val, mode);
+ subreg = force_lowpart_subreg (sysreg_mode, input_val, mode);
  break;
case AARCH64_WSRF:
  subreg = gen_lowpart_SUBREG (SImode, input_val);
@@ -2871,7 +2869,8 @@ aarch64_expand_rwsr_builtin (tree exp, rtx target, int 
fcode)
 case AARCH64_RSR64:
 case AARCH64_RSRF64:
 case AARCH64_RSR128:
-  return lowpart_subreg (TYPE_MODE (TREE_TYPE (exp)), target, sysreg_mode);
+  return force_lowpart_subreg (TYPE_MODE (TREE_TYPE (exp)),
+  target, sysreg_mode);
 case AARCH64_RSRF:
   subreg = gen_lowpart_SUBREG (SImode, target);
   return gen_lowpart_SUBREG (SFmode, subreg);
diff --git a/gcc/config/aarch64/aarch64-sve-builtins-base.cc 
b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
index 999320371247..aa26370d397f 100644
--- a/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+++ b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
@@ -1183,7 +1183,7 @@ public:
 if (BYTES_BIG_ENDIAN)
   return e.use_exact_insn (code_for_aarch64_sve_set_neonq (mode));
 insn_code icode = code_for_vcond_mask (mode, mode);
-e.args[1] = lowpart_subreg (mode, e.args[1], GET_MODE (e.args[1]));
+e.args[1] = force_lowpart_subreg (mode, e.args[1], GET_MODE (e.args[1]));
 e.add_output_operand (icode);
 e.add_input_operand (icode, e.args[1]);
 e.add_input_operand (icode, e.args[0]);
diff --git a/gcc/config/aarch64/aarch64-sve-builtins-sme.cc 
b/gcc/config/aarch64/aarch64-sve-builtins-sme.cc
index f4c91bcbb95d..b66b35ae60b7 100644
--- a/gcc/config/aarch64/aarch64-sve-builtins-sme.cc
+++ b/gcc/config/aarch64/aarch64-sve-builtins-sme.cc
@@ -112,7 +112,7 @@ add_load_store_slice_operand (function_expander &e, 
insn_code icode,
   rtx base = e.args[argno];
   if (e.mode_suffix_

[gcc r15-1401] Add force_highpart_subreg

[Richard Sandiford via Gcc-cvs]

https://gcc.gnu.org/g:e0700fbe35286d31fe64782b255c8d2caec673dc

commit r15-1401-ge0700fbe35286d31fe64782b255c8d2caec673dc
Author: Richard Sandiford 
Date:   Tue Jun 18 12:22:32 2024 +0100

Add force_highpart_subreg

This patch adds a force_highpart_subreg to go along with the
recently added force_lowpart_subreg.

gcc/
* explow.h (force_highpart_subreg): Declare.
* explow.cc (force_highpart_subreg): New function.
* builtins.cc (expand_builtin_issignaling): Use it.
* expmed.cc (emit_store_flag_1): Likewise.

Diff:
---
 gcc/builtins.cc | 15 ---
 gcc/explow.cc   | 14 ++
 gcc/explow.h|  1 +
 gcc/expmed.cc   |  4 +---
 4 files changed, 20 insertions(+), 14 deletions(-)

diff --git a/gcc/builtins.cc b/gcc/builtins.cc
index bde517b639e8..d467d1697b45 100644
--- a/gcc/builtins.cc
+++ b/gcc/builtins.cc
@@ -2835,9 +2835,7 @@ expand_builtin_issignaling (tree exp, rtx target)
 it is, working on the DImode high part is usually better.  */
  if (!MEM_P (temp))
{
- if (rtx t = simplify_gen_subreg (imode, temp, fmode,
-  subreg_highpart_offset (imode,
-  fmode)))
+ if (rtx t = force_highpart_subreg (imode, temp, fmode))
hi = t;
  else
{
@@ -2845,9 +2843,7 @@ expand_builtin_issignaling (tree exp, rtx target)
  if (int_mode_for_mode (fmode).exists (&imode2))
{
  rtx temp2 = gen_lowpart (imode2, temp);
- poly_uint64 off = subreg_highpart_offset (imode, imode2);
- if (rtx t = simplify_gen_subreg (imode, temp2,
-  imode2, off))
+ if (rtx t = force_highpart_subreg (imode, temp2, imode2))
hi = t;
}
}
@@ -2938,8 +2934,7 @@ expand_builtin_issignaling (tree exp, rtx target)
   it is, working on DImode parts is usually better.  */
if (!MEM_P (temp))
  {
-   hi = simplify_gen_subreg (imode, temp, fmode,
- subreg_highpart_offset (imode, fmode));
+   hi = force_highpart_subreg (imode, temp, fmode);
lo = force_lowpart_subreg (imode, temp, fmode);
if (!hi || !lo)
  {
@@ -2947,9 +2942,7 @@ expand_builtin_issignaling (tree exp, rtx target)
if (int_mode_for_mode (fmode).exists (&imode2))
  {
rtx temp2 = gen_lowpart (imode2, temp);
-   hi = simplify_gen_subreg (imode, temp2, imode2,
- subreg_highpart_offset (imode,
- imode2));
+   hi = force_highpart_subreg (imode, temp2, imode2);
lo = force_lowpart_subreg (imode, temp2, imode2);
  }
  }
diff --git a/gcc/explow.cc b/gcc/explow.cc
index 2a91cf76ea62..b4a0df89bc36 100644
--- a/gcc/explow.cc
+++ b/gcc/explow.cc
@@ -778,6 +778,20 @@ force_lowpart_subreg (machine_mode outermode, rtx op,
   return force_subreg (outermode, op, innermode, byte);
 }
 
+/* Try to return an rvalue expression for the OUTERMODE highpart of OP,
+   which has mode INNERMODE.  Allow OP to be forced into a new register
+   if necessary.
+
+   Return null on failure.  */
+
+rtx
+force_highpart_subreg (machine_mode outermode, rtx op,
+  machine_mode innermode)
+{
+  auto byte = subreg_highpart_offset (outermode, innermode);
+  return force_subreg (outermode, op, innermode, byte);
+}
+
 /* If X is a memory ref, copy its contents to a new temp reg and return
that reg.  Otherwise, return X.  */
 
diff --git a/gcc/explow.h b/gcc/explow.h
index dd654649b068..de89e9e2933e 100644
--- a/gcc/explow.h
+++ b/gcc/explow.h
@@ -44,6 +44,7 @@ extern rtx force_reg (machine_mode, rtx);
 
 extern rtx force_subreg (machine_mode, rtx, machine_mode, poly_uint64);
 extern rtx force_lowpart_subreg (machine_mode, rtx, machine_mode);
+extern rtx force_highpart_subreg (machine_mode, rtx, machine_mode);
 
 /* Return given rtx, copied into a new temp reg if it was in memory.  */
 extern rtx force_not_mem (rtx);
diff --git a/gcc/expmed.cc b/gcc/expmed.cc
index 1f68e7be721d..3b9475f5aa0b 100644
--- a/gcc/expmed.cc
+++ b/gcc/expmed.cc
@@ -5784,9 +5784,7 @@ emit_store_flag_1 (rtx target, enum rtx_code code, rtx 
op0, rtx op1,
  rtx op0h;
 
  /* If testing the sign bit, can just test on high word.  */
- op0h = simplify_gen_subreg (word_mode, op0, int_mode,
- subreg_highpart_offset (word_mode,
- int_mode));
+ op0h = force_highpart_su

[gcc r15-1402] aarch64: Add some uses of force_highpart_subreg

[Richard Sandiford via Gcc-cvs]

https://gcc.gnu.org/g:c67a9a9c8e934234b640a613b0ae3c15e7fa9733

commit r15-1402-gc67a9a9c8e934234b640a613b0ae3c15e7fa9733
Author: Richard Sandiford 
Date:   Tue Jun 18 12:22:33 2024 +0100

aarch64: Add some uses of force_highpart_subreg

This patch adds uses of force_highpart_subreg to places that
already use force_lowpart_subreg.

gcc/
* config/aarch64/aarch64.cc (aarch64_addti_scratch_regs): Use
force_highpart_subreg instead of gen_highpart and 
simplify_gen_subreg.
(aarch64_subvti_scratch_regs): Likewise.

Diff:
---
 gcc/config/aarch64/aarch64.cc | 17 -
 1 file changed, 4 insertions(+), 13 deletions(-)

diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc
index c952a7cdefec..026f8627a893 100644
--- a/gcc/config/aarch64/aarch64.cc
+++ b/gcc/config/aarch64/aarch64.cc
@@ -26873,19 +26873,12 @@ aarch64_addti_scratch_regs (rtx op1, rtx op2, rtx 
*low_dest,
   *low_in1 = force_lowpart_subreg (DImode, op1, TImode);
   *low_in2 = force_lowpart_subreg (DImode, op2, TImode);
   *high_dest = gen_reg_rtx (DImode);
-  *high_in1 = gen_highpart (DImode, op1);
-  *high_in2 = simplify_gen_subreg (DImode, op2, TImode,
-  subreg_highpart_offset (DImode, TImode));
+  *high_in1 = force_highpart_subreg (DImode, op1, TImode);
+  *high_in2 = force_highpart_subreg (DImode, op2, TImode);
 }
 
 /* Generate DImode scratch registers for 128-bit (TImode) subtraction.
 
-   This function differs from 'arch64_addti_scratch_regs' in that
-   OP1 can be an immediate constant (zero). We must call
-   subreg_highpart_offset with DImode and TImode arguments, otherwise
-   VOIDmode will be used for the const_int which generates an internal
-   error from subreg_size_highpart_offset which does not expect a size of zero.
-
OP1 represents the TImode destination operand 1
OP2 represents the TImode destination operand 2
LOW_DEST represents the low half (DImode) of TImode operand 0
@@ -26907,10 +26900,8 @@ aarch64_subvti_scratch_regs (rtx op1, rtx op2, rtx 
*low_dest,
   *low_in2 = force_lowpart_subreg (DImode, op2, TImode);
   *high_dest = gen_reg_rtx (DImode);
 
-  *high_in1 = simplify_gen_subreg (DImode, op1, TImode,
-  subreg_highpart_offset (DImode, TImode));
-  *high_in2 = simplify_gen_subreg (DImode, op2, TImode,
-  subreg_highpart_offset (DImode, TImode));
+  *high_in1 = force_highpart_subreg (DImode, op1, TImode);
+  *high_in2 = force_highpart_subreg (DImode, op2, TImode);
 }
 
 /* Generate RTL for 128-bit (TImode) subtraction with overflow.

[gcc r15-1400] Make more use of force_lowpart_subreg

[Richard Sandiford via Gcc-cvs]

https://gcc.gnu.org/g:a573ed4367ee685fb1bc50b79239b8b4b69872ee

commit r15-1400-ga573ed4367ee685fb1bc50b79239b8b4b69872ee
Author: Richard Sandiford 
Date:   Tue Jun 18 12:22:32 2024 +0100

Make more use of force_lowpart_subreg

This patch makes target-independent code use force_lowpart_subreg
instead of simplify_gen_subreg and lowpart_subreg in some places.
The criteria were:

(1) The code is obviously specific to expand (where new pseudos
can be created), or at least would be invalid to call when
!can_create_pseudo_p () and temporaries are needed.

(2) The value is obviously an rvalue rather than an lvalue.

Doing this should reduce the likelihood of bugs like PR115464
occuring in other situations.

gcc/
* builtins.cc (expand_builtin_issignaling): Use force_lowpart_subreg
instead of simplify_gen_subreg and lowpart_subreg.
* expr.cc (convert_mode_scalar, expand_expr_real_2): Likewise.
* optabs.cc (expand_doubleword_mod): Likewise.

Diff:
---
 gcc/builtins.cc |  7 ++-
 gcc/expr.cc | 17 +
 gcc/optabs.cc   |  2 +-
 3 files changed, 12 insertions(+), 14 deletions(-)

diff --git a/gcc/builtins.cc b/gcc/builtins.cc
index 5b5307c67b8c..bde517b639e8 100644
--- a/gcc/builtins.cc
+++ b/gcc/builtins.cc
@@ -2940,8 +2940,7 @@ expand_builtin_issignaling (tree exp, rtx target)
  {
hi = simplify_gen_subreg (imode, temp, fmode,
  subreg_highpart_offset (imode, fmode));
-   lo = simplify_gen_subreg (imode, temp, fmode,
- subreg_lowpart_offset (imode, fmode));
+   lo = force_lowpart_subreg (imode, temp, fmode);
if (!hi || !lo)
  {
scalar_int_mode imode2;
@@ -2951,9 +2950,7 @@ expand_builtin_issignaling (tree exp, rtx target)
hi = simplify_gen_subreg (imode, temp2, imode2,
  subreg_highpart_offset (imode,
  imode2));
-   lo = simplify_gen_subreg (imode, temp2, imode2,
- subreg_lowpart_offset (imode,
-imode2));
+   lo = force_lowpart_subreg (imode, temp2, imode2);
  }
  }
if (!hi || !lo)
diff --git a/gcc/expr.cc b/gcc/expr.cc
index 31a7346e33f0..ffbac5136923 100644
--- a/gcc/expr.cc
+++ b/gcc/expr.cc
@@ -423,7 +423,8 @@ convert_mode_scalar (rtx to, rtx from, int unsignedp)
0).exists (&toi_mode))
{
  start_sequence ();
- rtx fromi = lowpart_subreg (fromi_mode, from, from_mode);
+ rtx fromi = force_lowpart_subreg (fromi_mode, from,
+   from_mode);
  rtx tof = NULL_RTX;
  if (fromi)
{
@@ -443,7 +444,7 @@ convert_mode_scalar (rtx to, rtx from, int unsignedp)
  NULL_RTX, 1);
  if (toi)
{
- tof = lowpart_subreg (to_mode, toi, toi_mode);
+ tof = force_lowpart_subreg (to_mode, toi, toi_mode);
  if (tof)
emit_move_insn (to, tof);
}
@@ -475,7 +476,7 @@ convert_mode_scalar (rtx to, rtx from, int unsignedp)
0).exists (&toi_mode))
{
  start_sequence ();
- rtx fromi = lowpart_subreg (fromi_mode, from, from_mode);
+ rtx fromi = force_lowpart_subreg (fromi_mode, from, from_mode);
  rtx tof = NULL_RTX;
  do
{
@@ -510,11 +511,11 @@ convert_mode_scalar (rtx to, rtx from, int unsignedp)
  temp4, shift, NULL_RTX, 1);
  if (!temp5)
break;
- rtx temp6 = lowpart_subreg (toi_mode, temp5, fromi_mode);
+ rtx temp6 = force_lowpart_subreg (toi_mode, temp5,
+   fromi_mode);
  if (!temp6)
break;
- tof = lowpart_subreg (to_mode, force_reg (toi_mode, temp6),
-   toi_mode);
+ tof = force_lowpart_subreg (to_mode, temp6, toi_mode);
  if (tof)
emit_move_insn (to, tof);
}
@@ -9784,9 +9785,9 @@ expand_expr_real_2 (const_sepops ops, rtx target, 
machine_mode tmode,
inner_mode = TYPE_MODE (inner_type);
 
  if (modifier == EXPAND_INITIALIZER)
-   op0 = lowpart_subreg (mode, op0, inner_mode);
+

[gcc r15-1403] [MAINTAINERS] Update my email address

[Kyrylo Tkachov via Gcc-cvs]

https://gcc.gnu.org/g:5f6b42969d598139640e60daf1d0b9bdfcaa9f73

commit r15-1403-g5f6b42969d598139640e60daf1d0b9bdfcaa9f73
Author: Kyrylo Tkachov 
Date:   Tue Jun 18 14:00:54 2024 +0200

[MAINTAINERS] Update my email address

Pushing to trunk.

* MAINTAINERS (aarch64 port): Update my email address.
(DCO section): Likewise.

Signed-off-by: Kyrylo Tkachov 

Diff:
---
 MAINTAINERS | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index 6444e6ea2f1a..8b6fa16f79a9 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -52,7 +52,7 @@ docs, and the testsuite related to that.
 aarch64 port   Richard Earnshaw
 aarch64 port   Richard Sandiford   
 aarch64 port   Marcus Shawcroft
-aarch64 port   Kyrylo Tkachov  
+aarch64 port   Kyrylo Tkachov  
 alpha port Richard Henderson   
 amdgcn portJulian Brown
 amdgcn portAndrew Stubbs   
@@ -784,7 +784,7 @@ Nathaniel Shead 

 Nathan Sidwell 
 Edward Smith-Rowland   
 Fangrui Song   
-Kyrylo Tkachov 
+Kyrylo Tkachov 
 Petter Tomner  
 Martin Uecker  
 Jonathan Wakely

[gcc r15-1404] analyzer: Fix g++ 4.8 bootstrap without using std::move to return std::unique_ptr

[Jonathan Wakely via Gcc-cvs]

https://gcc.gnu.org/g:d8c8ab7de71218eb6ddbe5822f1acdcd8726323d

commit r15-1404-gd8c8ab7de71218eb6ddbe5822f1acdcd8726323d
Author: Jonathan Wakely 
Date:   Fri Jun 14 13:57:10 2024 +0100

analyzer: Fix g++ 4.8 bootstrap without using std::move to return 
std::unique_ptr

Revert the changes in r15--ge22b7f741ab54f and fix bootstrap with
GCC 4.8 a different way. The original problem is not related to C++17
guaranteed copy elision, it's related to Core DR 1579 [1], which was
part of C++14 but only implemented in G++ as a C++11 DR with
r5-1576-gfb682f9458c6cf (so GCC 4.8 doesn't implement it).

The original fix causes -Wredundant-move warnings with GCC trunk.

[1] https://cplusplus.github.io/CWG/issues/1579.html

gcc/analyzer/ChangeLog
* constraint-manager.cc (equiv_class::make_dump_widget): Change
return type to match return value and do not use std::move on
return value.
(bounded_ranges_constraint::make_dump_widget): Likewise.
(constraint_manager::make_dump_widget): Likewise.
* constraint-manager.h (equiv_class::make_dump_widget): Change
return type.
(bounded_ranges_constraint::make_dump_widget): Likewise.
(constraint_manager::make_dump_widget): Likewise.
* program-state.cc (sm_state_map::make_dump_widget): Likewise.
(program_state::make_dump_widget): Likewise.
* program-state.h (sm_state_map::make_dump_widget): Likewise.
(program_state::make_dump_widget): Likewise.
* region-model.cc (region_to_value_map::make_dump_widget): Likewise.
(region_model::make_dump_widget): Likewise.
* region-model.h (region_to_value_map::make_dump_widget): Likewise.
(region_model::make_dump_widget): Likewise.
* region.cc (region::make_dump_widget): Likewise.
* region.h (region::make_dump_widget): Likewise.
* store.cc (binding_cluster::make_dump_widget): Likewise.
(store::make_dump_widget): Likewise.
* store.h (binding_cluster::make_dump_widget): Likewise.
(store::make_dump_widget): Likewise.
* svalue.cc (svalue::make_dump_widget): Likewise.
* svalue.h (svalue::make_dump_widget): Likewise.

Diff:
---
 gcc/analyzer/constraint-manager.cc | 12 ++--
 gcc/analyzer/constraint-manager.h  |  6 +++---
 gcc/analyzer/program-state.cc  |  8 
 gcc/analyzer/program-state.h   |  4 ++--
 gcc/analyzer/region-model.cc   |  8 
 gcc/analyzer/region-model.h|  4 ++--
 gcc/analyzer/region.cc |  4 ++--
 gcc/analyzer/region.h  |  2 +-
 gcc/analyzer/store.cc  |  8 
 gcc/analyzer/store.h   |  4 ++--
 gcc/analyzer/svalue.cc |  4 ++--
 gcc/analyzer/svalue.h  |  2 +-
 12 files changed, 33 insertions(+), 33 deletions(-)

diff --git a/gcc/analyzer/constraint-manager.cc 
b/gcc/analyzer/constraint-manager.cc
index a9d58c9cdcf5..29539060ebdd 100644
--- a/gcc/analyzer/constraint-manager.cc
+++ b/gcc/analyzer/constraint-manager.cc
@@ -1146,7 +1146,7 @@ equiv_class::to_json () const
   return ec_obj;
 }
 
-std::unique_ptr
+std::unique_ptr
 equiv_class::make_dump_widget (const text_art::dump_widget_info &dwi,
   unsigned id) const
 {
@@ -1176,7 +1176,7 @@ equiv_class::make_dump_widget (const 
text_art::dump_widget_info &dwi,
   ec_widget->add_child (tree_widget::make (dwi, &pp));
 }
 
-  return std::move (ec_widget);
+  return ec_widget;
 }
 
 /* Generate a hash value for this equiv_class.
@@ -1491,7 +1491,7 @@ bounded_ranges_constraint::to_json () const
   return con_obj;
 }
 
-std::unique_ptr
+std::unique_ptr
 bounded_ranges_constraint::
 make_dump_widget (const text_art::dump_widget_info &dwi) const
 {
@@ -1500,7 +1500,7 @@ make_dump_widget (const text_art::dump_widget_info &dwi) 
const
 (tree_widget::from_fmt (dwi, nullptr,
"ec%i bounded ranges", m_ec_id.as_int ()));
   m_ranges->add_to_dump_widget (*brc_widget.get (), dwi);
-  return std::move (brc_widget);
+  return brc_widget;
 }
 
 bool
@@ -1829,7 +1829,7 @@ constraint_manager::to_json () const
   return cm_obj;
 }
 
-std::unique_ptr
+std::unique_ptr
 constraint_manager::make_dump_widget (const text_art::dump_widget_info &dwi) 
const
 {
   using text_art::tree_widget;
@@ -1853,7 +1853,7 @@ constraint_manager::make_dump_widget (const 
text_art::dump_widget_info &dwi) con
   if (cm_widget->get_num_children () == 0)
 return nullptr;
 
-  return std::move (cm_widget);
+  return cm_widget;
 }
 
 /* Attempt to add the constraint LHS OP RHS to this constraint_manager.
diff --git a/gcc/analyzer/constraint-manager.h 
b/gcc/analyzer/constraint-manager.h
index 31556aebc7a1..81e9c7ec035c 100644
--- a/gcc/analyzer/constraint-manager.h
+++ b/gcc/analyzer/constraint-manager.h
@@ -273,7 

[gcc r15-1405] libstdc++: Fix outdated comment about standard integer types

[Jonathan Wakely via Libstdc++-cvs]

https://gcc.gnu.org/g:89c26a99102d2cc00455333795d81d6426be7057

commit r15-1405-g89c26a99102d2cc00455333795d81d6426be7057
Author: Jonathan Wakely 
Date:   Tue Jun 18 13:05:39 2024 +0100

libstdc++: Fix outdated comment about standard integer types

The long long and unsigned long long types have been standard since
C++11, so are not extensions. There are also the char8_t, char16_t and
char32_t types. Just refer to the standard integer types, without saying
how many there are.

libstdc++-v3/ChangeLog:

* include/bits/cpp_type_traits.h: Fix outdated comment about the
number of standard integer types.

Diff:
---
 libstdc++-v3/include/bits/cpp_type_traits.h | 6 ++
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/libstdc++-v3/include/bits/cpp_type_traits.h 
b/libstdc++-v3/include/bits/cpp_type_traits.h
index 679eee99b904..6834dee55570 100644
--- a/libstdc++-v3/include/bits/cpp_type_traits.h
+++ b/libstdc++-v3/include/bits/cpp_type_traits.h
@@ -130,10 +130,8 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
   typedef __false_type __type;
 };
 
-  // Thirteen specializations (yes there are eleven standard integer
-  // types; long long and unsigned long long are
-  // supported as extensions).  Up to four target-specific __int
-  // types are supported as well.
+  // Explicit specializations for the standard integer types.
+  // Up to four target-specific __int types are supported as well.
   template<>
 struct __is_integer
 {

[gcc r15-1406] [to-be-committed, RISC-V] Improve bset generation when bit position is limited

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:a78e2c3a00d8b147b44416f7a843c9df61f04531

commit r15-1406-ga78e2c3a00d8b147b44416f7a843c9df61f04531
Author: Jeff Law 
Date:   Tue Jun 18 06:40:40 2024 -0600

[to-be-committed,RISC-V] Improve bset generation when bit position is 
limited

  So more work in the ongoing effort to make better use of the Zbs
extension.  This time we're trying to exploit knowledge of the shift
count/bit position to allow us to use a bset instruction.

Consider this expression in SImode

  (1 << (pos & 0xf)

None of the resulting values will have bit 31 set.  So if there's an
explicit zero or sign extension to DI we can drop that explicit
extension and generate a simple bset with x0 as the input value.

Or another example (which I think came from spec at some point and IIRC
was the primary motivation for this patch):

(1 << (7-(pos) % 8))

Before this change they'd generate something like this respectively:

 li  a5,1
 andia0,a0,15
 sllwa0,a5,a0

 li  a5,7
 andna0,a5,a0
 li  a5,1
 sllwa0,a5,a0

After this change they generate:

 andia0,a0,15# 9 [c=4 l=4]  *anddi3/1
 bseta0,x0,a0# 17[c=8 l=4]  *bsetdi_2

 li  a5,7# 27[c=4 l=4]  *movdi_64bit/1
 andna0,a5,a0# 28[c=4 l=4]  and_notdi3
 bseta0,x0,a0# 19[c=8 l=4]  *bsetdi_2

We achieve this with simple define_splits which target the bsetdi_2
pattern I recently added.  Much better than the original implementation
I did a few months back :-)  I've got a bclr/binv variant from a few
months back as well, but it needs to be updated to the simpler
implementation found here.

Just ran this through my tester.  Will wait for the precommit CI to
render its verdict before moving forward.

gcc/
* config/riscv/bitmanip.md (bset splitters): New patterns for
generating bset when bit position is limited.

Diff:
---
 gcc/config/riscv/bitmanip.md   | 36 ++
 gcc/testsuite/gcc.target/riscv/zbs-ext-2.c | 24 
 2 files changed, 60 insertions(+)

diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md
index 094bc2acf1c7..ae5e7e510c0e 100644
--- a/gcc/config/riscv/bitmanip.md
+++ b/gcc/config/riscv/bitmanip.md
@@ -609,6 +609,42 @@
   "bset\t%0,x0,%1"
   [(set_attr "type" "bitmanip")])
 
+;; These two splitters take advantage of the limited range of the
+;; shift constant.  With the limited range we know the SImode sign
+;; bit is never set, thus we can treat this as zero extending and
+;; generate the bsetdi_2 pattern.
+(define_split
+  [(set (match_operand:DI 0 "register_operand")
+   (any_extend:DI
+(ashift:SI (const_int 1)
+   (subreg:QI
+ (and:DI (not:DI (match_operand:DI 1 "register_operand"))
+ (match_operand 2 "const_int_operand")) 0
+   (clobber (match_operand:DI 3 "register_operand"))]
+  "TARGET_64BIT
+   && TARGET_ZBS
+   && (TARGET_ZBB || TARGET_ZBKB)
+   && (INTVAL (operands[2]) & 0x1f) != 0x1f"
+   [(set (match_dup 0) (and:DI (not:DI (match_dup 1)) (match_dup 2)))
+(set (match_dup 0) (zero_extend:DI (ashift:SI
+  (const_int 1)
+  (subreg:QI (match_dup 0) 0])
+
+(define_split
+  [(set (match_operand:DI 0 "register_operand")
+   (any_extend:DI
+(ashift:SI (const_int 1)
+   (subreg:QI
+ (and:DI (match_operand:DI 1 "register_operand")
+ (match_operand 2 "const_int_operand")) 0]
+  "TARGET_64BIT
+   && TARGET_ZBS
+   && (INTVAL (operands[2]) & 0x1f) != 0x1f"
+   [(set (match_dup 0) (and:DI (match_dup 1) (match_dup 2)))
+(set (match_dup 0) (zero_extend:DI (ashift:SI
+  (const_int 1)
+  (subreg:QI (match_dup 0) 0])
+
 (define_insn "*bset_1_mask"
   [(set (match_operand:X 0 "register_operand" "=r")
(ashift:X (const_int 1)
diff --git a/gcc/testsuite/gcc.target/riscv/zbs-ext-2.c 
b/gcc/testsuite/gcc.target/riscv/zbs-ext-2.c
new file mode 100644
index ..301bc9d89c4e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zbs-ext-2.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zbb_zbs -mabi=lp64" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */
+
+
+typedef unsigned int uint32_t;
+uint32_t foo(uint32_t pos)
+{
+return (1 << (7-(pos) % 8));
+}
+
+typedef unsigned int uint32_t;
+uint32_t foo2(uint32_t pos)
+{
+return (1 << (pos & 0xf));
+}
+
+/* { dg-final { scan-assembler-not "sll\t" } } */
+/* { dg-final { scan-assemble

[gcc r15-1407] tree-optimization/115537 - ICE with SLP condition reduction vectorization

[Richard Biener via Gcc-cvs]

https://gcc.gnu.org/g:7f9be55a4630134a237219af9cc8143e02080380

commit r15-1407-g7f9be55a4630134a237219af9cc8143e02080380
Author: Richard Biener 
Date:   Tue Jun 18 14:00:52 2024 +0200

tree-optimization/115537 - ICE with SLP condition reduction vectorization

The condition rejecting "multiple-type" SLP condition reduction lacks
handling EXTRACT_LAST reductions.

PR tree-optimization/115537
* tree-vect-loop.cc (vectorizable_reduction): Also reject
SLP condition reductions of EXTRACT_LAST kind when multiple
statement copies are involved.

* gcc.dg/vect/pr115537.c: New testcase.

Diff:
---
 gcc/testsuite/gcc.dg/vect/pr115537.c | 19 +++
 gcc/tree-vect-loop.cc|  5 +++--
 2 files changed, 22 insertions(+), 2 deletions(-)

diff --git a/gcc/testsuite/gcc.dg/vect/pr115537.c 
b/gcc/testsuite/gcc.dg/vect/pr115537.c
new file mode 100644
index ..99ed467feb88
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/vect/pr115537.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-mcpu=neoverse-n1" { target aarch64*-*-* } } */
+
+char *a;
+int b;
+void c()
+{
+  int d = 0, e = 0, f;
+  for (; f; ++f)
+if (a[f] == 5)
+  ;
+else if (a[f])
+  e = 1;
+else
+  d = 1;
+  if (d)
+if (e)
+  b = 0;
+}
diff --git a/gcc/tree-vect-loop.cc b/gcc/tree-vect-loop.cc
index 7c79e9da1060..eeb75c09e91a 100644
--- a/gcc/tree-vect-loop.cc
+++ b/gcc/tree-vect-loop.cc
@@ -8083,13 +8083,14 @@ vectorizable_reduction (loop_vec_info loop_vinfo,
 
   if ((reduction_type == COND_REDUCTION
|| reduction_type == INTEGER_INDUC_COND_REDUCTION
-   || reduction_type == CONST_COND_REDUCTION)
+   || reduction_type == CONST_COND_REDUCTION
+   || reduction_type == EXTRACT_LAST_REDUCTION)
   && slp_node
   && SLP_TREE_NUMBER_OF_VEC_STMTS (slp_node) > 1)
 {
   if (dump_enabled_p ())
dump_printf_loc (MSG_MISSED_OPTIMIZATION, vect_location,
-"multiple types in condition reduction reduction.\n");
+"multiple types in condition reduction.\n");
   return false;
 }

[gcc r15-1408] Match: Support form 11 for the unsigned scalar .SAT_SUB

[Pan Li via Gcc-cvs]

https://gcc.gnu.org/g:9b109826e0b0473572395f5837b455d57fa5a93c

commit r15-1408-g9b109826e0b0473572395f5837b455d57fa5a93c
Author: Pan Li 
Date:   Mon Jun 17 14:56:42 2024 +0800

Match: Support form 11 for the unsigned scalar .SAT_SUB

We missed one match pattern for the unsigned scalar .SAT_SUB,  aka
form 11.

Form 11:
  #define SAT_SUB_U_11(T) \
  T sat_sub_u_11_##T (T x, T y) \
  { \
T ret; \
bool overflow = __builtin_sub_overflow (x, y, &ret); \
return overflow ? 0 : ret; \
  }

Thus,  add above form 11 to the match pattern 
gimple_unsigned_integer_sat_sub.

The below test suites are passed for this patch:
1. The rv64gcv fully regression test with newlib.
2. The rv64gcv build with glibc.
3. The x86 bootstrap test.
4. The x86 fully regression test.

gcc/ChangeLog:

* match.pd: Add form 11 match pattern for .SAT_SUB.

Signed-off-by: Pan Li 

Diff:
---
 gcc/match.pd | 9 -
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/gcc/match.pd b/gcc/match.pd
index 99968d316eda..5c330a43ed01 100644
--- a/gcc/match.pd
+++ b/gcc/match.pd
@@ -3186,13 +3186,20 @@ DEFINE_INT_AND_FLOAT_ROUND_FN (RINT)
  (if (INTEGRAL_TYPE_P (type) && TYPE_UNSIGNED (type)
   && types_match (type, @0, @1
 
-/* Unsigned saturation sub, case 7 (branch with .SUB_OVERFLOW).  */
+/* Unsigned saturation sub, case 7 (branch eq with .SUB_OVERFLOW).  */
 (match (unsigned_integer_sat_sub @0 @1)
  (cond^ (eq (imagpart (IFN_SUB_OVERFLOW@2 @0 @1)) integer_zerop)
   (realpart @2) integer_zerop)
  (if (INTEGRAL_TYPE_P (type) && TYPE_UNSIGNED (type)
   && types_match (type, @0, @1
 
+/* Unsigned saturation sub, case 8 (branch ne with .SUB_OVERFLOW).  */
+(match (unsigned_integer_sat_sub @0 @1)
+ (cond^ (ne (imagpart (IFN_SUB_OVERFLOW@2 @0 @1)) integer_zerop)
+   integer_zerop (realpart @2))
+ (if (INTEGRAL_TYPE_P (type) && TYPE_UNSIGNED (type)
+  && types_match (type, @0, @1
+
 /* x >  y  &&  x != XXX_MIN  -->  x > y
x >  y  &&  x == XXX_MIN  -->  false . */
 (for eqne (eq ne)

[gcc r15-1409] Match: Support forms 7 and 8 for the unsigned .SAT_ADD

[Pan Li via Gcc-cvs]

https://gcc.gnu.org/g:e4f938936867d8799775d1455e67bd3fb8711afd

commit r15-1409-ge4f938936867d8799775d1455e67bd3fb8711afd
Author: Pan Li 
Date:   Mon Jun 17 09:31:33 2024 +0800

Match: Support forms 7 and 8 for the unsigned .SAT_ADD

When investigate the vectorization of .SAT_ADD,  we notice there
are additional 2 forms,  aka form 7 and 8 for .SAT_ADD.

Form 7:
  #define DEF_SAT_U_ADD_FMT_7(T)  \
  T __attribute__((noinline)) \
  sat_u_add_##T##_fmt_7 (T x, T y)\
  {   \
return x > (T)(x + y) ? -1 : (x + y); \
  }

Form 8:
  #define DEF_SAT_U_ADD_FMT_8(T)   \
  T __attribute__((noinline))  \
  sat_u_add_##T##_fmt_8 (T x, T y) \
  {\
return x <= (T)(x + y) ? (x + y) : -1; \
  }

Thus,  add above 2 forms to the match gimple_unsigned_integer_sat_add,
and then the vectorizer can try to recog the pattern like form 7 and
form 8.

The below test suites are passed for this patch:
1. The rv64gcv fully regression test with newlib.
2. The rv64gcv build with glibc.
3. The x86 bootstrap test.
4. The x86 fully regression test.

gcc/ChangeLog:

* match.pd: Add form 7 and 8 for the unsigned .SAT_ADD match.

Signed-off-by: Pan Li 

Diff:
---
 gcc/match.pd | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/gcc/match.pd b/gcc/match.pd
index 5c330a43ed01..3d0689c9312d 100644
--- a/gcc/match.pd
+++ b/gcc/match.pd
@@ -3144,6 +3144,16 @@ DEFINE_INT_AND_FLOAT_ROUND_FN (RINT)
  (cond^ (ne (imagpart (IFN_ADD_OVERFLOW:c @0 @1)) integer_zerop)
   integer_minus_onep (usadd_left_part_2 @0 @1)))
 
+/* Unsigned saturation add, case 7 (branch with le):
+   SAT_ADD = x <= (X + Y) ? (X + Y) : -1.  */
+(match (unsigned_integer_sat_add @0 @1)
+ (cond^ (le @0 (usadd_left_part_1@2 @0 @1)) @2 integer_minus_onep))
+
+/* Unsigned saturation add, case 8 (branch with gt):
+   SAT_ADD = x > (X + Y) ? -1 : (X + Y).  */
+(match (unsigned_integer_sat_add @0 @1)
+ (cond^ (gt @0 (usadd_left_part_1@2 @0 @1)) integer_minus_onep @2))
+
 /* Unsigned saturation sub, case 1 (branch with gt):
SAT_U_SUB = X > Y ? X - Y : 0  */
 (match (unsigned_integer_sat_sub @0 @1)

[gcc r15-1413] diagnostics: eliminate diagnostic_context::m_make_json_for_path

[David Malcolm via Gcc-cvs]

https://gcc.gnu.org/g:d3878c85f331c7a378245b636d5d230735b87347

commit r15-1413-gd3878c85f331c7a378245b636d5d230735b87347
Author: David Malcolm 
Date:   Tue Jun 18 10:59:55 2024 -0400

diagnostics: eliminate diagnostic_context::m_make_json_for_path

Now that the path-handling code for json_output_format no longer
needs "tree", and thus can be in OBJS-libcommon we can move it
from tree-diagnostic-path.cc to diagnostic-format-json.cc where it
should have been all along.

No functional change intended.

gcc/ChangeLog:
* diagnostic-format-json.cc: Include "diagnostic-path.h" and
"logical-location.h".
(make_json_for_path): Move tree-diagnostic-path.cc's
default_tree_make_json_for_path here, renaming it and making it
static.
(json_output_format::on_end_diagnostic): Replace call of
m_context's m_make_json_for_path callback with a direct call to
make_json_for_path.
* diagnostic.h (diagnostic_context::m_make_json_for_path): Drop
field.
* tree-diagnostic-path.cc: Drop include of "json.h".
(default_tree_make_json_for_path): Rename to make_json_for_path
and move to diagnostic-format-json.cc.
* tree-diagnostic.cc (tree_diagnostics_defaults): Drop
initialization of m_make_json_for_path.
* tree-diagnostic.h (default_tree_make_json_for): Delete decl.

Signed-off-by: David Malcolm 

Diff:
---
 gcc/diagnostic-format-json.cc | 37 ++---
 gcc/diagnostic.h  |  2 --
 gcc/tree-diagnostic-path.cc   | 32 
 gcc/tree-diagnostic.cc|  1 -
 gcc/tree-diagnostic.h |  2 --
 5 files changed, 34 insertions(+), 40 deletions(-)

diff --git a/gcc/diagnostic-format-json.cc b/gcc/diagnostic-format-json.cc
index 0782ae831eba..2bdc2c13d37b 100644
--- a/gcc/diagnostic-format-json.cc
+++ b/gcc/diagnostic-format-json.cc
@@ -25,8 +25,10 @@ along with GCC; see the file COPYING3.  If not see
 #include "diagnostic.h"
 #include "selftest-diagnostic.h"
 #include "diagnostic-metadata.h"
+#include "diagnostic-path.h"
 #include "json.h"
 #include "selftest.h"
+#include "logical-location.h"
 
 /* Subclass of diagnostic_output_format for JSON output.  */
 
@@ -187,6 +189,36 @@ json_from_metadata (const diagnostic_metadata *metadata)
   return metadata_obj;
 }
 
+/* Make a JSON value for PATH.  */
+
+static json::value *
+make_json_for_path (diagnostic_context *context,
+   const diagnostic_path *path)
+{
+  json::array *path_array = new json::array ();
+  for (unsigned i = 0; i < path->num_events (); i++)
+{
+  const diagnostic_event &event = path->get_event (i);
+
+  json::object *event_obj = new json::object ();
+  if (event.get_location ())
+   event_obj->set ("location",
+   json_from_expanded_location (context,
+event.get_location ()));
+  label_text event_text (event.get_desc (false));
+  event_obj->set_string ("description", event_text.get ());
+  if (const logical_location *logical_loc = event.get_logical_location ())
+   {
+ label_text name (logical_loc->get_name_for_path_output ());
+ event_obj->set_string ("function", name.get ());
+   }
+  event_obj->set_integer ("depth", event.get_stack_depth ());
+  path_array->append (event_obj);
+}
+  return path_array;
+}
+
+
 /* Implementation of "on_end_diagnostic" vfunc for JSON output.
Generate a JSON object for DIAGNOSTIC, and store for output
within current diagnostic group.  */
@@ -291,10 +323,9 @@ json_output_format::on_end_diagnostic (const 
diagnostic_info &diagnostic,
 }
 
   const diagnostic_path *path = richloc->get_path ();
-  if (path && m_context.m_make_json_for_path)
+  if (path)
 {
-  json::value *path_value
-   = m_context.m_make_json_for_path (&m_context, path);
+  json::value *path_value = make_json_for_path (&m_context, path);
   diag_obj->set ("path", path_value);
 }
 
diff --git a/gcc/diagnostic.h b/gcc/diagnostic.h
index 9a9571bb76d4..ff2aa3dd9a32 100644
--- a/gcc/diagnostic.h
+++ b/gcc/diagnostic.h
@@ -713,8 +713,6 @@ private:
 
 public:
   void (*m_print_path) (diagnostic_context *, const diagnostic_path *);
-  json::value *(*m_make_json_for_path) (diagnostic_context *,
-   const diagnostic_path *);
 
   /* Auxiliary data for client.  */
   void *m_client_aux_data;
diff --git a/gcc/tree-diagnostic-path.cc b/gcc/tree-diagnostic-path.cc
index 39a85d330153..40b197d971cf 100644
--- a/gcc/tree-diagnostic-path.cc
+++ b/gcc/tree-diagnostic-path.cc
@@ -30,7 +30,6 @@ along with GCC; see the file COPYING3.  If not see
 #include "tree-diagnostic.h"
 #include "intl.h"
 #include "diagnostic-path.h"
-#include "json.h"
 #include "gcc-rich-location.h"

[gcc r15-1414] diagnostics: introduce diagnostic-macro-unwinding.h/cc

[David Malcolm via Gcc-cvs]

https://gcc.gnu.org/g:bdcfe7f7f50ec64b45581a175d1eca41c74a3dfe

commit r15-1414-gbdcfe7f7f50ec64b45581a175d1eca41c74a3dfe
Author: David Malcolm 
Date:   Tue Jun 18 10:59:56 2024 -0400

diagnostics: introduce diagnostic-macro-unwinding.h/cc

Eliminate a dependency on "tree" from the code used by
diagnostic_path handling.

No functional change intended.

gcc/ChangeLog:
* Makefile.in (OBJS): Add diagnostic-macro-unwinding.o.

gcc/c-family/ChangeLog:
* c-opts.cc: Replace include of "tree-diagnostic.h" with
"diagnostic-macro-unwinding.h".

gcc/ChangeLog:
* diagnostic-macro-unwinding.cc: New file, with material taken
from tree-diagnostic.cc.
* diagnostic-macro-unwinding.h: New file, with material taken
from tree-diagnostic.h.
* tree-diagnostic-path.cc: Repalce include of "tree-diagnostic.h"
with "diagnostic-macro-unwinding.h".
* tree-diagnostic.cc (struct loc_map_pair): Move to
diagnostic-macro-unwinding.cc.
(maybe_unwind_expanded_macro_loc): Likewise.
(virt_loc_aware_diagnostic_finalizer): Likewise.
* tree-diagnostic.h (virt_loc_aware_diagnostic_finalizer): Move
decl to diagnostic-macro-unwinding.h.
(maybe_unwind_expanded_macro_loc): Likewise.

Signed-off-by: David Malcolm 

Diff:
---
 gcc/Makefile.in   |   1 +
 gcc/c-family/c-opts.cc|   2 +-
 gcc/diagnostic-macro-unwinding.cc | 221 ++
 gcc/diagnostic-macro-unwinding.h  |  29 +
 gcc/tree-diagnostic-path.cc   |   2 +-
 gcc/tree-diagnostic.cc| 195 -
 gcc/tree-diagnostic.h |   5 -
 7 files changed, 253 insertions(+), 202 deletions(-)

diff --git a/gcc/Makefile.in b/gcc/Makefile.in
index a2799b8d8262..e701d9fb0829 100644
--- a/gcc/Makefile.in
+++ b/gcc/Makefile.in
@@ -1826,6 +1826,7 @@ OBJS = \
 OBJS-libcommon = diagnostic-spec.o diagnostic.o diagnostic-color.o \
diagnostic-format-json.o \
diagnostic-format-sarif.o \
+   diagnostic-macro-unwinding.o \
diagnostic-show-locus.o \
edit-context.o \
pretty-print.o intl.o \
diff --git a/gcc/c-family/c-opts.cc b/gcc/c-family/c-opts.cc
index faaf9ee63509..33114f13c8db 100644
--- a/gcc/c-family/c-opts.cc
+++ b/gcc/c-family/c-opts.cc
@@ -32,7 +32,7 @@ along with GCC; see the file COPYING3.  If not see
 #include "flags.h"
 #include "toplev.h"
 #include "langhooks.h"
-#include "tree-diagnostic.h" /* for virt_loc_aware_diagnostic_finalizer */
+#include "diagnostic-macro-unwinding.h" /* for 
virt_loc_aware_diagnostic_finalizer */
 #include "intl.h"
 #include "cppdefault.h"
 #include "incpath.h"
diff --git a/gcc/diagnostic-macro-unwinding.cc 
b/gcc/diagnostic-macro-unwinding.cc
new file mode 100644
index ..3056d8c8afb1
--- /dev/null
+++ b/gcc/diagnostic-macro-unwinding.cc
@@ -0,0 +1,221 @@
+/* Code for unwinding macro expansions in diagnostics.
+   Copyright (C) 1999-2024 Free Software Foundation, Inc.
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify it under
+the terms of the GNU General Public License as published by the Free
+Software Foundation; either version 3, or (at your option) any later
+version.
+
+GCC is distributed in the hope that it will be useful, but WITHOUT ANY
+WARRANTY; without even the implied warranty of MERCHANTABILITY or
+FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+for more details.
+
+You should have received a copy of the GNU General Public License
+along with GCC; see the file COPYING3.  If not see
+.  */
+
+#include "config.h"
+#include "system.h"
+#include "coretypes.h"
+#include "tree.h"
+#include "diagnostic.h"
+#include "diagnostic-macro-unwinding.h"
+#include "intl.h"
+
+/* This is a pair made of a location and the line map it originated
+   from.  It's used in the maybe_unwind_expanded_macro_loc function
+   below.  */
+struct loc_map_pair
+{
+  const line_map_macro *map;
+  location_t where;
+};
+
+
+/* Unwind the different macro expansions that lead to the token which
+   location is WHERE and emit diagnostics showing the resulting
+   unwound macro expansion trace.  Let's look at an example to see how
+   the trace looks like.  Suppose we have this piece of code,
+   artificially annotated with the line numbers to increase
+   legibility:
+
+$ cat -n test.c
+  1#define OPERATE(OPRD1, OPRT, OPRD2) \
+  2  OPRD1 OPRT OPRD2;
+  3
+  4#define SHIFTL(A,B) \
+  5  OPERATE (A,<<,B)
+  6
+  7#define MULT(A) \
+  8  SHIFTL (A,1)
+  9
+ 10void
+ 11g ()
+ 12{
+ 13  MULT (1.0);// 1.0 << 1; <-- so this is an error.
+ 14}
+
+   Here is the diagnostic that we want the compiler to gener

[gcc r15-1416] diagnostics: rename tree-diagnostic-path.cc to diagnostic-path.cc

[David Malcolm via Gcc-cvs]

https://gcc.gnu.org/g:524cdf4dab610e6e53b3b033eacbdb1a03687cc7

commit r15-1416-g524cdf4dab610e6e53b3b033eacbdb1a03687cc7
Author: David Malcolm 
Date:   Tue Jun 18 10:59:56 2024 -0400

diagnostics: rename tree-diagnostic-path.cc to diagnostic-path.cc

Now that nothing in tree-diagnostic-path.cc uses "tree", this patch
renames it to diagnostic-path.cc and moves it from OBJS to
OBJS-libcommon.

No functional change intended.

gcc/ChangeLog:
* Makefile.in (OBJS): Move selftest-diagnostic-path.o,
selftest-logical-location.o, and tree-diagnostic-path.o to...
(OBJS-libcommon): ...here, renaming tree-diagnostic-path.o to
diagnostic-path.o.
* tree-diagnostic-path.cc: Rename to...
* diagnostic-path.cc: ...this.  Drop include of "tree.h".
(tree_diagnostic_path_cc_tests): Rename to...
(diagnostic_path_cc_tests): ...this.
* selftest-run-tests.cc (selftest::run_tests): Update for above
renaming.
* selftest.h (tree_diagnostic_path_cc_tests): Rename decl to...
(diagnostic_path_cc_tests): ...this.

Signed-off-by: David Malcolm 

Diff:
---
 gcc/Makefile.in | 6 +++---
 gcc/{tree-diagnostic-path.cc => diagnostic-path.cc} | 3 +--
 gcc/selftest-run-tests.cc   | 2 +-
 gcc/selftest.h  | 2 +-
 4 files changed, 6 insertions(+), 7 deletions(-)

diff --git a/gcc/Makefile.in b/gcc/Makefile.in
index e701d9fb0829..638ea6b2307b 100644
--- a/gcc/Makefile.in
+++ b/gcc/Makefile.in
@@ -1700,8 +1700,6 @@ OBJS = \
ubsan.o \
sanopt.o \
sancov.o \
-   selftest-diagnostic-path.o \
-   selftest-logical-location.o \
simple-diagnostic-path.o \
tree-call-cdce.o \
tree-cfg.o \
@@ -1712,7 +1710,6 @@ OBJS = \
tree-dfa.o \
tree-diagnostic.o \
tree-diagnostic-client-data-hooks.o \
-   tree-diagnostic-path.o \
tree-dump.o \
tree-eh.o \
tree-emutls.o \
@@ -1827,6 +1824,7 @@ OBJS-libcommon = diagnostic-spec.o diagnostic.o 
diagnostic-color.o \
diagnostic-format-json.o \
diagnostic-format-sarif.o \
diagnostic-macro-unwinding.o \
+   diagnostic-path.o \
diagnostic-show-locus.o \
edit-context.o \
pretty-print.o intl.o \
@@ -1834,6 +1832,8 @@ OBJS-libcommon = diagnostic-spec.o diagnostic.o 
diagnostic-color.o \
sbitmap.o \
vec.o input.o hash-table.o ggc-none.o memory-block.o \
selftest.o selftest-diagnostic.o sort.o \
+   selftest-diagnostic-path.o \
+   selftest-logical-location.o \
text-art/box-drawing.o \
text-art/canvas.o \
text-art/ruler.o \
diff --git a/gcc/tree-diagnostic-path.cc b/gcc/diagnostic-path.cc
similarity index 99%
rename from gcc/tree-diagnostic-path.cc
rename to gcc/diagnostic-path.cc
index 35f8ea2b8b62..882dc1c5805f 100644
--- a/gcc/tree-diagnostic-path.cc
+++ b/gcc/diagnostic-path.cc
@@ -25,7 +25,6 @@ along with GCC; see the file COPYING3.  If not see
 #define INCLUDE_VECTOR
 #include "system.h"
 #include "coretypes.h"
-#include "tree.h"
 #include "diagnostic.h"
 #include "diagnostic-macro-unwinding.h"
 #include "intl.h"
@@ -2199,7 +2198,7 @@ control_flow_tests (const line_table_case &case_)
 /* Run all of the selftests within this file.  */
 
 void
-tree_diagnostic_path_cc_tests ()
+diagnostic_path_cc_tests ()
 {
   /* In a few places we use the global dc's printer to determine
  colorization so ensure this off during the tests.  */
diff --git a/gcc/selftest-run-tests.cc b/gcc/selftest-run-tests.cc
index 3275db38ba92..e6779206c470 100644
--- a/gcc/selftest-run-tests.cc
+++ b/gcc/selftest-run-tests.cc
@@ -102,7 +102,7 @@ selftest::run_tests ()
   spellcheck_cc_tests ();
   spellcheck_tree_cc_tests ();
   tree_cfg_cc_tests ();
-  tree_diagnostic_path_cc_tests ();
+  diagnostic_path_cc_tests ();
   simple_diagnostic_path_cc_tests ();
   attribs_cc_tests ();
 
diff --git a/gcc/selftest.h b/gcc/selftest.h
index 2d1aa91607e3..dcb1463ed906 100644
--- a/gcc/selftest.h
+++ b/gcc/selftest.h
@@ -222,6 +222,7 @@ extern void cgraph_cc_tests ();
 extern void convert_cc_tests ();
 extern void diagnostic_color_cc_tests ();
 extern void diagnostic_format_json_cc_tests ();
+extern void diagnostic_path_cc_tests ();
 extern void diagnostic_show_locus_cc_tests ();
 extern void digraph_cc_tests ();
 extern void dumpfile_cc_tests ();
@@ -259,7 +260,6 @@ extern void sreal_cc_tests ();
 extern void store_merging_cc_tests ();
 extern void tree_cc_tests ();
 extern void tree_cfg_cc_tests ();
-extern void tree_diagnostic_path_cc_tests ();
 extern void tristate_cc_tests ();
 extern void typed_splay_tree_cc_tests ();
 extern void vec_cc_tests ();

[gcc r15-1410] diagnostics: move simple_diagnostic_{path, thread, event} to their own .h/cc

[David Malcolm via Gcc-cvs]

https://gcc.gnu.org/g:f89f9c7ae7190c700d1b3727a3fd66e90cfb90ac

commit r15-1410-gf89f9c7ae7190c700d1b3727a3fd66e90cfb90ac
Author: David Malcolm 
Date:   Tue Jun 18 10:59:54 2024 -0400

diagnostics: move simple_diagnostic_{path,thread,event} to their own .h/cc

As work towards eliminating the dependency on "tree" from
path-printing, move these classes to a new simple-diagnostic-path.h/cc.

No functional change intended.

gcc/analyzer/ChangeLog:
* checker-path.h: Include "simple-diagnostic-path.h".

gcc/ChangeLog:
* Makefile.in (OBJS): Add simple-diagnostic-path.o.
* diagnostic-path.h (class simple_diagnostic_event): Move to
simple-diagnostic-path.h.
(class simple_diagnostic_thread): Likewise.
(class simple_diagnostic_path): Likewise.
* diagnostic.cc (simple_diagnostic_path::simple_diagnostic_path):
Move to simple-diagnostic-path.cc.
(simple_diagnostic_path::num_events): Likewise.
(simple_diagnostic_path::get_event): Likewise.
(simple_diagnostic_path::num_threads): Likewise.
(simple_diagnostic_path::get_thread): Likewise.
(simple_diagnostic_path::add_thread): Likewise.
(simple_diagnostic_path::add_event): Likewise.
(simple_diagnostic_path::add_thread_event): Likewise.
(simple_diagnostic_path::connect_to_next_event): Likewise.
(simple_diagnostic_event::simple_diagnostic_event): Likewise.
(simple_diagnostic_event::~simple_diagnostic_event): Likewise.
* selftest-run-tests.cc (selftest::run_tests): Call
selftest::simple_diagnostic_path_cc_tests.
* selftest.h (selftest::simple_diagnostic_path_cc_tests): New
decl.
* simple-diagnostic-path.cc: New file, from the above material.
* simple-diagnostic-path.h: New file, from the above material
from diagnostic-path.h.
* tree-diagnostic-path.cc: Include "simple-diagnostic-path.h".

gcc/testsuite/ChangeLog
* gcc.dg/plugin/diagnostic_plugin_test_paths.c: Include
"simple-diagnostic-path.h".

Signed-off-by: David Malcolm 

Diff:
---
 gcc/Makefile.in|   1 +
 gcc/analyzer/checker-path.h|   1 +
 gcc/diagnostic-path.h  | 104 +-
 gcc/diagnostic.cc  | 149 --
 gcc/selftest-run-tests.cc  |   1 +
 gcc/selftest.h |   1 +
 gcc/simple-diagnostic-path.cc  | 228 +
 gcc/simple-diagnostic-path.h   | 130 
 .../gcc.dg/plugin/diagnostic_plugin_test_paths.c   |   1 +
 gcc/tree-diagnostic-path.cc|   1 +
 10 files changed, 366 insertions(+), 251 deletions(-)

diff --git a/gcc/Makefile.in b/gcc/Makefile.in
index f5adb647d3fb..35f259da858d 100644
--- a/gcc/Makefile.in
+++ b/gcc/Makefile.in
@@ -1700,6 +1700,7 @@ OBJS = \
ubsan.o \
sanopt.o \
sancov.o \
+   simple-diagnostic-path.o \
tree-call-cdce.o \
tree-cfg.o \
tree-cfgcleanup.o \
diff --git a/gcc/analyzer/checker-path.h b/gcc/analyzer/checker-path.h
index 6b3e8a34fe56..162ebb3f0d83 100644
--- a/gcc/analyzer/checker-path.h
+++ b/gcc/analyzer/checker-path.h
@@ -22,6 +22,7 @@ along with GCC; see the file COPYING3.  If not see
 #define GCC_ANALYZER_CHECKER_PATH_H
 
 #include "analyzer/checker-event.h"
+#include "simple-diagnostic-path.h"
 
 namespace ana {
 
diff --git a/gcc/diagnostic-path.h b/gcc/diagnostic-path.h
index 938bd583a3da..958eb725322a 100644
--- a/gcc/diagnostic-path.h
+++ b/gcc/diagnostic-path.h
@@ -201,108 +201,8 @@ private:
   bool get_first_event_in_a_function (unsigned *out_idx) const;
 };
 
-/* Concrete subclasses.  */
-
-/* A simple implementation of diagnostic_event.  */
-
-class simple_diagnostic_event : public diagnostic_event
-{
- public:
-  simple_diagnostic_event (location_t loc, tree fndecl, int depth,
-  const char *desc,
-  diagnostic_thread_id_t thread_id = 0);
-  ~simple_diagnostic_event ();
-
-  location_t get_location () const final override { return m_loc; }
-  tree get_fndecl () const final override { return m_fndecl; }
-  int get_stack_depth () const final override { return m_depth; }
-  label_text get_desc (bool) const final override
-  {
-return label_text::borrow (m_desc);
-  }
-  const logical_location *get_logical_location () const final override
-  {
-return NULL;
-  }
-  meaning get_meaning () const final override
-  {
-return meaning ();
-  }
-  bool connect_to_next_event_p () const final override
-  {
-return m_connected_to_next_event;
-  }
-  diagnostic_thread_id_t get_thread_id () const final override
-  {
-ret

[gcc r15-1411] diagnostics: eliminate "tree" from diagnostic_{event, path}

[David Malcolm via Gcc-cvs]

https://gcc.gnu.org/g:d0334e7798c4be9f6eac5fd9b6273a0ea31b1360

commit r15-1411-gd0334e7798c4be9f6eac5fd9b6273a0ea31b1360
Author: David Malcolm 
Date:   Tue Jun 18 10:59:54 2024 -0400

diagnostics: eliminate "tree" from diagnostic_{event,path}

This patch eliminates the use of "tree" from diagnostic_{event,path} in
favor of const logical_location *.

No functional change intended.

gcc/analyzer/ChangeLog:
* checker-event.h (checker_event::fndecl): Drop "final" and
"override", converting from a vfunc implementation to a plain
accessor.
* checker-path.cc (checker_path::same_function_p): New.
* checker-path.h (checker_path::same_function_p): New decl.

gcc/ChangeLog:
* diagnostic.cc: Include "logical-location.h".
(diagnostic_path::get_first_event_in_a_function): Fix typo in
leading comment.  Rewrite to use logical_location rather than
tree.  Drop test on stack depth.
(diagnostic_path::interprocedural_p): Rewrite to use
logical_location rather than tree.
(logical_location::function_p): New.
* diagnostic-path.h (diagnostic_event::get_fndecl): Eliminate
vfunc.
(diagnostic_path::same_function_p): New pure virtual func.
* logical-location.h (logical_location::get_name_for_path_output):
New pure virtual func.
* simple-diagnostic-path.cc
(simple_diagnostic_path::same_function_p): New.
(simple_diagnostic_event::simple_diagnostic_event): Initialize
m_logical_loc.
* simple-diagnostic-path.h: Include "tree-logical-location.h".
(simple_diagnostic_event::get_fndecl): Convert from a vfunc
implementation to an accessor.
(simple_diagnostic_event::get_logical_location): Use
m_logical_loc.
(simple_diagnostic_event::m_logical_loc): New field.
(simple_diagnostic_path::same_function_p): New decl.
* tree-diagnostic-path.cc: Move pragma disabling -Wformat-diag to
cover the whole file.
(can_consolidate_events): Add params "path", "ev1_idx", and
"ev2_idx".  Rewrite to use diagnostic_path::same_function_p rather
than tree.
(per_thread_summary::per_thread_summary): Add "path" param
(per_thread_summary::m_path): New field.
(event_range::event_range): Update for conversion of m_fndecl to
m_logical_loc.
(event_range::maybe_add_event): Rename param "idx" to
"new_ev_idx".  Update call to can_consolidate_events to pass in
"m_path", "m_start_idx", and "new_ev_idx".
(event_range::m_fndecl): Replace with...
(event_range::m_logical_loc): ...this.
(path_summary::get_or_create_events_for_thread_id): Pass "path" to
per_thread_summary ctor.
(per_thread_summary::interprocedural_p): Rewrite to use
diagnostic_path::same_function_p rather than tree.
(print_fndecl): Delete.
(thread_event_printer::print_swimlane_for_event_range): Update for
conversion from tree to logical_location.
(default_tree_diagnostic_path_printer): Likewise.
(default_tree_make_json_for_path): Likewise.
* tree-logical-location.cc: Include "intl.h".
(compiler_logical_location::get_name_for_tree_for_path_output):
New.
(tree_logical_location::get_name_for_path_output): New.
(current_fndecl_logical_location::get_name_for_path_output): New.
* tree-logical-location.h
(compiler_logical_location::get_name_for_tree_for_path_output):
New decl.
(tree_logical_location::get_name_for_path_output): New decl.
(current_fndecl_logical_location::get_name_for_path_output): New
decl.

Signed-off-by: David Malcolm 

Diff:
---
 gcc/analyzer/checker-event.h  |   2 +-
 gcc/analyzer/checker-path.cc  |   8 
 gcc/analyzer/checker-path.h   |   4 ++
 gcc/diagnostic-path.h |  10 ++--
 gcc/diagnostic.cc |  47 +++
 gcc/logical-location.h|   5 ++
 gcc/simple-diagnostic-path.cc |  11 -
 gcc/simple-diagnostic-path.h  |  13 +-
 gcc/tree-diagnostic-path.cc   | 103 --
 gcc/tree-logical-location.cc  |  25 ++
 gcc/tree-logical-location.h   |   3 ++
 11 files changed, 161 insertions(+), 70 deletions(-)

diff --git a/gcc/analyzer/checker-event.h b/gcc/analyzer/checker-event.h
index d0935aca9853..4343641f441c 100644
--- a/gcc/analyzer/checker-event.h
+++ b/gcc/analyzer/checker-event.h
@@ -91,7 +91,6 @@ public:
   /* Implementation of diagnostic_event.  */
 
   location_t get_location () const final override { return m_loc; }
-  tree get_fndecl () c

[gcc r15-1412] diagnostics: remove tree usage from tree-diagnostic-path.cc

[David Malcolm via Gcc-cvs]

https://gcc.gnu.org/g:164ac58fabc6430eed45dda7500dfba64be2bd87

commit r15-1412-g164ac58fabc6430eed45dda7500dfba64be2bd87
Author: David Malcolm 
Date:   Tue Jun 18 10:59:55 2024 -0400

diagnostics: remove tree usage from tree-diagnostic-path.cc

No functional change intended.

gcc/ChangeLog:
* Makefile.in (OBJS): Add selftest-diagnostic-path.o and
selftest-logical-location.o.
* logical-location.h: Include "label-text.h".
(class logical_location): Update leading comment.
* selftest-diagnostic-path.cc: New file, adapted from
simple-diagnostic-path.cc and from material in
tree-diagnostic-path.cc.
* selftest-diagnostic-path.h: New file, adapted from
simple-diagnostic-path.h and from material in
tree-diagnostic-path.cc.
* selftest-logical-location.cc: New file.
* selftest-logical-location.h: New file.
* tree-diagnostic-path.cc: Remove includes of "tree-pretty-print.h",
"langhooks.h", and "simple-diagnostic-path.h".  Add include of
"selftest-diagnostic-path.h".
(class test_diagnostic_path): Delete, in favor of new
implementation in selftest-diagnostic-path.{h,cc}, which is
directly derived from diagnostic_path, rather than from
simple_diagnostic_path.
(selftest::test_intraprocedural_path): Eliminate tree usage,
via change to test_diagnostic_path, using strings rather than
function_decls for identifying functions in the test.
(selftest::test_interprocedural_path_1): Likewise.
(selftest::test_interprocedural_path_2): Likewise.
(selftest::test_recursion): Likewise.
(selftest::test_control_flow_1): Likewise.
(selftest::test_control_flow_2): Likewise.
(selftest::test_control_flow_3): Likewise.
(selftest::assert_cfg_edge_path_streq): Likewise.
(selftest::test_control_flow_5): Likewise.
(selftest::test_control_flow_6): Likewise.

Signed-off-by: David Malcolm 

Diff:
---
 gcc/Makefile.in  |   2 +
 gcc/logical-location.h   |   5 +-
 gcc/selftest-diagnostic-path.cc  | 233 +++
 gcc/selftest-diagnostic-path.h   | 163 +++
 gcc/selftest-logical-location.cc |  71 
 gcc/selftest-logical-location.h  |  58 ++
 gcc/tree-diagnostic-path.cc  | 161 ---
 7 files changed, 580 insertions(+), 113 deletions(-)

diff --git a/gcc/Makefile.in b/gcc/Makefile.in
index 35f259da858d..a2799b8d8262 100644
--- a/gcc/Makefile.in
+++ b/gcc/Makefile.in
@@ -1700,6 +1700,8 @@ OBJS = \
ubsan.o \
sanopt.o \
sancov.o \
+   selftest-diagnostic-path.o \
+   selftest-logical-location.o \
simple-diagnostic-path.o \
tree-call-cdce.o \
tree-cfg.o \
diff --git a/gcc/logical-location.h b/gcc/logical-location.h
index c3b72081135b..bba210877862 100644
--- a/gcc/logical-location.h
+++ b/gcc/logical-location.h
@@ -21,6 +21,8 @@ along with GCC; see the file COPYING3.  If not see
 #ifndef GCC_LOGICAL_LOCATION_H
 #define GCC_LOGICAL_LOCATION_H
 
+#include "label-text.h"
+
 /* An enum for discriminating between different kinds of logical location
for a diagnostic.
 
@@ -46,7 +48,8 @@ enum logical_location_kind
- "within function 'foo'", or
- "within method 'bar'",
but *without* requiring knowledge of trees
-   (see tree-logical-location.h for subclasses relating to trees).  */
+   (see tree-logical-location.h for concrete subclasses relating to trees,
+   and selftest-logical-location.h for a concrete subclass for selftests).  */
 
 class logical_location
 {
diff --git a/gcc/selftest-diagnostic-path.cc b/gcc/selftest-diagnostic-path.cc
new file mode 100644
index ..6d21f2e55999
--- /dev/null
+++ b/gcc/selftest-diagnostic-path.cc
@@ -0,0 +1,233 @@
+/* Concrete classes for selftests involving diagnostic paths.
+   Copyright (C) 2019-2024 Free Software Foundation, Inc.
+   Contributed by David Malcolm 
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify it under
+the terms of the GNU General Public License as published by the Free
+Software Foundation; either version 3, or (at your option) any later
+version.
+
+GCC is distributed in the hope that it will be useful, but WITHOUT ANY
+WARRANTY; without even the implied warranty of MERCHANTABILITY or
+FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+for more details.
+
+You should have received a copy of the GNU General Public License
+along with GCC; see the file COPYING3.  If not see
+.  */
+
+
+#include "config.h"
+#define INCLUDE_VECTOR
+#include "system.h"
+#include "coretypes.h"
+#include "version.h"
+#include "demangle.h"
+#inc

[gcc r15-1415] diagnostics: eliminate diagnostic_context::m_print_path callback

[David Malcolm via Gcc-cvs]

https://gcc.gnu.org/g:c371d7bdbe69201b4c91179ff6f3e2237e0e7fbe

commit r15-1415-gc371d7bdbe69201b4c91179ff6f3e2237e0e7fbe
Author: David Malcolm 
Date:   Tue Jun 18 10:59:56 2024 -0400

diagnostics: eliminate diagnostic_context::m_print_path callback

No functional change intended.

gcc/ChangeLog:
* diagnostic-format-json.cc (diagnostic_output_format_init_json):
Replace clearing of diagnostic_context::m_print_path callback with
setting the path format to DPF_NONE.
* diagnostic-format-sarif.cc
(diagnostic_output_format_init_sarif): Likewise.
* diagnostic.cc (diagnostic_context::show_any_path): Replace call
to diagnostic_context::m_print_path callback with a direct call to
diagnostic_context::print_path.
* diagnostic.h (diagnostic_context::print_path): New decl.
(diagnostic_context::m_print_path): Delete callback.
* tree-diagnostic-path.cc (default_tree_diagnostic_path_printer):
Convert to...
(diagnostic_context::print_path): ...this.
* tree-diagnostic.cc (tree_diagnostics_defaults): Delete
initialization of m_print_path.
* tree-diagnostic.h (default_tree_diagnostic_path_printer): Delete
decl.

Signed-off-by: David Malcolm 

Diff:
---
 gcc/diagnostic-format-json.cc  |  4 ++--
 gcc/diagnostic-format-sarif.cc |  4 +++-
 gcc/diagnostic.cc  |  3 +--
 gcc/diagnostic.h   |  4 ++--
 gcc/tree-diagnostic-path.cc| 23 +++
 gcc/tree-diagnostic.cc |  1 -
 gcc/tree-diagnostic.h  |  3 ---
 7 files changed, 19 insertions(+), 23 deletions(-)

diff --git a/gcc/diagnostic-format-json.cc b/gcc/diagnostic-format-json.cc
index 2bdc2c13d37b..ec03ac15aeba 100644
--- a/gcc/diagnostic-format-json.cc
+++ b/gcc/diagnostic-format-json.cc
@@ -395,8 +395,8 @@ private:
 static void
 diagnostic_output_format_init_json (diagnostic_context *context)
 {
-  /* Override callbacks.  */
-  context->m_print_path = nullptr; /* handled in json_end_diagnostic.  */
+  /* Suppress normal textual path output.  */
+  context->set_path_format (DPF_NONE);
 
   /* The metadata is handled in JSON format, rather than as text.  */
   context->set_show_cwe (false);
diff --git a/gcc/diagnostic-format-sarif.cc b/gcc/diagnostic-format-sarif.cc
index 79116f051bc1..5f438dd38a88 100644
--- a/gcc/diagnostic-format-sarif.cc
+++ b/gcc/diagnostic-format-sarif.cc
@@ -1991,8 +1991,10 @@ private:
 static void
 diagnostic_output_format_init_sarif (diagnostic_context *context)
 {
+  /* Suppress normal textual path output.  */
+  context->set_path_format (DPF_NONE);
+
   /* Override callbacks.  */
-  context->m_print_path = nullptr; /* handled in sarif_end_diagnostic.  */
   context->set_ice_handler_callback (sarif_ice_handler);
 
   /* The metadata is handled in SARIF format, rather than as text.  */
diff --git a/gcc/diagnostic.cc b/gcc/diagnostic.cc
index 844eb8e10482..471135f16dec 100644
--- a/gcc/diagnostic.cc
+++ b/gcc/diagnostic.cc
@@ -915,8 +915,7 @@ diagnostic_context::show_any_path (const diagnostic_info 
&diagnostic)
   if (!path)
 return;
 
-  if (m_print_path)
-m_print_path (this, path);
+  print_path (path);
 }
 
 /* class diagnostic_event.  */
diff --git a/gcc/diagnostic.h b/gcc/diagnostic.h
index ff2aa3dd9a32..c6846525da31 100644
--- a/gcc/diagnostic.h
+++ b/gcc/diagnostic.h
@@ -583,6 +583,8 @@ private:
   pretty_printer *pp,
   diagnostic_source_effect_info *effect_info);
 
+  void print_path (const diagnostic_path *path);
+
   /* Data members.
  Ideally, all of these would be private and have "m_" prefixes.  */
 
@@ -712,8 +714,6 @@ private:
   urlifier *m_urlifier;
 
 public:
-  void (*m_print_path) (diagnostic_context *, const diagnostic_path *);
-
   /* Auxiliary data for client.  */
   void *m_client_aux_data;
 
diff --git a/gcc/tree-diagnostic-path.cc b/gcc/tree-diagnostic-path.cc
index adaaf30b84fd..35f8ea2b8b62 100644
--- a/gcc/tree-diagnostic-path.cc
+++ b/gcc/tree-diagnostic-path.cc
@@ -884,17 +884,16 @@ print_path_summary_as_text (const path_summary *ps, 
diagnostic_context *dc,
 
 } /* end of anonymous namespace for path-printing code.  */
 
-/* Print PATH to CONTEXT, according to CONTEXT's path_format.  */
+/* Print PATH according to this context's path_format.  */
 
 void
-default_tree_diagnostic_path_printer (diagnostic_context *context,
- const diagnostic_path *path)
+diagnostic_context::print_path (const diagnostic_path *path)
 {
   gcc_assert (path);
 
   const unsigned num_events = path->num_events ();
 
-  switch (context->get_path_format ())
+  switch (get_path_format ())
 {
 case DPF_NONE:
   /* Do nothing.  */
@@ -909,7 +908,7 @@ default_tree_diagnostic_path_printer (diagnostic_context 
*context,
label_text event_text (event.get_desc (false));

[gcc r15-1417] aarch64: make thunderxt88p1 an alias of thunderxt88

[Andrew Pinski via Gcc-cvs]

https://gcc.gnu.org/g:79ab7245bea102f2c4ec38bd4b3ba03e7828617f

commit r15-1417-g79ab7245bea102f2c4ec38bd4b3ba03e7828617f
Author: Andrew Pinski 
Date:   Mon Jun 17 13:26:54 2024 -0700

aarch64: make thunderxt88p1 an alias of thunderxt88

Since r7-6575-g71aba51d6460ff, thunderxt88 has been the same as 
thunderxt88p1 so let's make
them a true alias and remove the odd variant handling and moves it below 
thunderxt88.

Bootstrapped and tested on aarch64-linux-gnu with no regressions.

gcc/ChangeLog:

* config/aarch64/aarch64-cores.def (thunderxt88p1): Make an alias 
of thunderxt88 and
move below thunderxt88.
* config/aarch64/aarch64-tune.md: Regenerate.

Signed-off-by: Andrew Pinski 

Diff:
---
 gcc/config/aarch64/aarch64-cores.def | 5 ++---
 gcc/config/aarch64/aarch64-tune.md   | 2 +-
 2 files changed, 3 insertions(+), 4 deletions(-)

diff --git a/gcc/config/aarch64/aarch64-cores.def 
b/gcc/config/aarch64/aarch64-cores.def
index be60929e4000..06a8213811ca 100644
--- a/gcc/config/aarch64/aarch64-cores.def
+++ b/gcc/config/aarch64/aarch64-cores.def
@@ -58,10 +58,9 @@ AARCH64_CORE("cortex-a73",  cortexa73, cortexa57, V8A,  
(CRC), cortexa73, 0x41,
 
 /* Cavium ('C') cores. */
 AARCH64_CORE("thunderx",  thunderx,  thunderx,  V8A,  (CRC, CRYPTO), 
thunderx,  0x43, 0x0a0, -1)
-/* Do not swap around "thunderxt88p1" and "thunderxt88",
-   this order is required to handle variant correctly. */
-AARCH64_CORE("thunderxt88p1", thunderxt88p1, thunderx,  V8A,  (CRC, CRYPTO),   
thunderxt88,  0x43, 0x0a1, 0)
 AARCH64_CORE("thunderxt88",   thunderxt88,   thunderx,  V8A,  (CRC, CRYPTO), 
thunderxt88,  0x43, 0x0a1, -1)
+/* "thunderxt88p1 is just an alias for thunderxt88 now. */
+AARCH64_CORE("thunderxt88p1", thunderxt88p1, thunderx,  V8A,  (CRC, CRYPTO), 
thunderxt88,  0x43, 0x0a1, -1)
 
 /* OcteonTX is the official name for T81/T83. */
 AARCH64_CORE("octeontx",  octeontx,  thunderx,  V8A,  (CRC, CRYPTO), 
thunderx,  0x43, 0x0a0, -1)
diff --git a/gcc/config/aarch64/aarch64-tune.md 
b/gcc/config/aarch64/aarch64-tune.md
index ba940f1c8901..9b1f32a0330a 100644
--- a/gcc/config/aarch64/aarch64-tune.md
+++ b/gcc/config/aarch64/aarch64-tune.md
@@ -1,5 +1,5 @@
 ;; -*- buffer-read-only: t -*-
 ;; Generated automatically by gentune.sh from aarch64-cores.def
 (define_attr "tune"
-   
"cortexa34,cortexa35,cortexa53,cortexa57,cortexa72,cortexa73,thunderx,thunderxt88p1,thunderxt88,octeontx,octeontxt81,octeontxt83,thunderxt81,thunderxt83,ampere1,ampere1a,ampere1b,emag,xgene1,falkor,qdf24xx,exynosm1,phecda,thunderx2t99p1,vulcan,thunderx2t99,cortexa55,cortexa75,cortexa76,cortexa76ae,cortexa77,cortexa78,cortexa78ae,cortexa78c,cortexa65,cortexa65ae,cortexx1,cortexx1c,neoversen1,ares,neoversee1,octeontx2,octeontx2t98,octeontx2t96,octeontx2t93,octeontx2f95,octeontx2f95n,octeontx2f95mm,a64fx,tsv110,thunderx3t110,neoversev1,zeus,neoverse512tvb,saphira,oryon1,cortexa57cortexa53,cortexa72cortexa53,cortexa73cortexa35,cortexa73cortexa53,cortexa75cortexa55,cortexa76cortexa55,cortexr82,cortexa510,cortexa520,cortexa710,cortexa715,cortexa720,cortexx2,cortexx3,cortexx4,neoversen2,cobalt100,neoversev2,demeter,generic,generic_armv8_a,generic_armv9_a"
+   
"cortexa34,cortexa35,cortexa53,cortexa57,cortexa72,cortexa73,thunderx,thunderxt88,thunderxt88p1,octeontx,octeontxt81,octeontxt83,thunderxt81,thunderxt83,ampere1,ampere1a,ampere1b,emag,xgene1,falkor,qdf24xx,exynosm1,phecda,thunderx2t99p1,vulcan,thunderx2t99,cortexa55,cortexa75,cortexa76,cortexa76ae,cortexa77,cortexa78,cortexa78ae,cortexa78c,cortexa65,cortexa65ae,cortexx1,cortexx1c,neoversen1,ares,neoversee1,octeontx2,octeontx2t98,octeontx2t96,octeontx2t93,octeontx2f95,octeontx2f95n,octeontx2f95mm,a64fx,tsv110,thunderx3t110,neoversev1,zeus,neoverse512tvb,saphira,oryon1,cortexa57cortexa53,cortexa72cortexa53,cortexa73cortexa35,cortexa73cortexa53,cortexa75cortexa55,cortexa76cortexa55,cortexr82,cortexa510,cortexa520,cortexa710,cortexa715,cortexa720,cortexx2,cortexx3,cortexx4,neoversen2,cobalt100,neoversev2,demeter,generic,generic_armv8_a,generic_armv9_a"
(const (symbol_ref "((enum attr_tune) aarch64_tune)")))

[gcc r15-1418] aarch64: Add comment about thunderxt81/t83 being aliases

[Andrew Pinski via Gcc-cvs]

https://gcc.gnu.org/g:adadb5c7ba0922ea77bb9ca695f398de67c11c49

commit r15-1418-gadadb5c7ba0922ea77bb9ca695f398de67c11c49
Author: Andrew Pinski 
Date:   Mon Jun 17 14:20:10 2024 -0700

aarch64: Add comment about thunderxt81/t83 being aliases

Since these were already aliases just make it clear on that.

gcc/ChangeLog:

* config/aarch64/aarch64-cores.def: Add comment
saying thunderxt81/t83 are aliases of octeontx81/83.

Signed-off-by: Andrew Pinski 

Diff:
---
 gcc/config/aarch64/aarch64-cores.def | 1 +
 1 file changed, 1 insertion(+)

diff --git a/gcc/config/aarch64/aarch64-cores.def 
b/gcc/config/aarch64/aarch64-cores.def
index 06a8213811ca..0e05e81761cb 100644
--- a/gcc/config/aarch64/aarch64-cores.def
+++ b/gcc/config/aarch64/aarch64-cores.def
@@ -67,6 +67,7 @@ AARCH64_CORE("octeontx",  octeontx,  thunderx,  V8A,  
(CRC, CRYPTO), thu
 AARCH64_CORE("octeontx81",octeontxt81,   thunderx,  V8A,  (CRC, CRYPTO), 
thunderx,  0x43, 0x0a2, -1)
 AARCH64_CORE("octeontx83",octeontxt83,   thunderx,  V8A,  (CRC, CRYPTO), 
thunderx,  0x43, 0x0a3, -1)
 
+/* thunderxt81/83 are aliases for octeontxt81/83. */
 AARCH64_CORE("thunderxt81",   thunderxt81,   thunderx,  V8A,  (CRC, CRYPTO), 
thunderx,  0x43, 0x0a2, -1)
 AARCH64_CORE("thunderxt83",   thunderxt83,   thunderx,  V8A,  (CRC, CRYPTO), 
thunderx,  0x43, 0x0a3, -1)

[gcc(refs/users/meissner/heads/work169-bugs)] Revert changes

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:1ffb92e1bd8f9ae1c091ba7782916be67861f7e9

commit 1ffb92e1bd8f9ae1c091ba7782916be67861f7e9
Author: Michael Meissner 
Date:   Tue Jun 18 12:15:15 2024 -0400

Revert changes

Diff:
---
 gcc/config/rs6000/rs6000.cc  | 13 +
 libgcc/config.host   | 14 ++
 libgcc/configure | 19 ++-
 libgcc/configure.ac  | 19 ++-
 libgfortran/configure|  7 ++-
 libgfortran/configure.ac |  3 ---
 libgfortran/kinds-override.h |  2 +-
 7 files changed, 22 insertions(+), 55 deletions(-)

diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index ea36e651b446..c5c4191127e4 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -4146,8 +4146,7 @@ rs6000_option_override_internal (bool global_init_p)
  the keyword as well as the type.  */
   TARGET_FLOAT128_TYPE = TARGET_FLOAT128_ENABLE_TYPE && TARGET_VSX;
 
-  /* IEEE 128-bit floating point requires VSX support.  Disable IEEE 128-bit on
- legacy 32-bit LE systems.  */
+  /* IEEE 128-bit floating point requires VSX support.  */
   if (TARGET_FLOAT128_KEYWORD)
 {
   if (!TARGET_VSX)
@@ -4155,16 +4154,6 @@ rs6000_option_override_internal (bool global_init_p)
  if ((rs6000_isa_flags_explicit & OPTION_MASK_FLOAT128_KEYWORD) != 0)
error ("%qs requires VSX support", "-mfloat128");
 
- TARGET_FLOAT128_TYPE = 0;
- rs6000_isa_flags &= ~(OPTION_MASK_FLOAT128_KEYWORD
-   | OPTION_MASK_FLOAT128_HW);
-   }
-  else if (!TARGET_POWERPC64 && !BYTES_BIG_ENDIAN)
-   {
- if ((rs6000_isa_flags_explicit & OPTION_MASK_FLOAT128_KEYWORD) != 0)
-   error ("%qs requires 64-bit support on little endian systems",
-  "-mfloat128");
-
  TARGET_FLOAT128_TYPE = 0;
  rs6000_isa_flags &= ~(OPTION_MASK_FLOAT128_KEYWORD
| OPTION_MASK_FLOAT128_HW);
diff --git a/libgcc/config.host b/libgcc/config.host
index 9e3b21e98fdd..9fae51d4ce7d 100644
--- a/libgcc/config.host
+++ b/libgcc/config.host
@@ -1290,18 +1290,16 @@ powerpc*-*-linux*)
;;
esac
 
-   # If the compiler is not configured for IEEE 128-bit, do not include the
-   # power9 and power10 hardware support libraries
if test $libgcc_cv_powerpc_float128 = yes; then
tmake_file="${tmake_file} rs6000/t-float128"
+   fi
 
-   if test $libgcc_cv_powerpc_float128_hw = yes; then
-   tmake_file="${tmake_file} rs6000/t-float128-hw"
+   if test $libgcc_cv_powerpc_float128_hw = yes; then
+   tmake_file="${tmake_file} rs6000/t-float128-hw"
+   fi
 
-   if test $libgcc_cv_powerpc_3_1_float128_hw = yes; then
-   tmake_file="${tmake_file} 
rs6000/t-float128-p10-hw"
-   fi
-   fi
+   if test $libgcc_cv_powerpc_3_1_float128_hw = yes; then
+   tmake_file="${tmake_file} rs6000/t-float128-p10-hw"
fi
 
extra_parts="$extra_parts ecrti.o ecrtn.o ncrti.o ncrtn.o"
diff --git a/libgcc/configure b/libgcc/configure
index 7ac132b71693..a69d314374a3 100755
--- a/libgcc/configure
+++ b/libgcc/configure
@@ -5180,14 +5180,13 @@ esac
 esac
 
 case ${host} in
-# Determine if the system can support VSX, which is needed to support
-# __float128.  Little endian 32-bit cannot be supported, since those systems do
-# not support VSX.  All of the little endian 64-bit systems require VSX support
-# (power8 and above).  With big endian, the default might not include VSX, but
-# we can build the libgcc __float128 support with VSX enabled.
+# At present, we cannot turn -mfloat128 on via #pragma GCC target, so just
+# check if we have VSX (ISA 2.06) support to build the software libraries, and
+# whether the assembler can handle xsaddqp for hardware support.  Also check if
+# a new glibc is being used so that __builtin_cpu_supports can be used.
 powerpc*-*-linux*)
   saved_CFLAGS="$CFLAGS"
-  CFLAGS="$CFLAGS -mabi=altivec -mfloat128"
+  CFLAGS="$CFLAGS -mabi=altivec -mvsx -mfloat128"
   { $as_echo "$as_me:${as_lineno-$LINENO}: checking for PowerPC ISA 2.06 to 
build __float128 libraries" >&5
 $as_echo_n "checking for PowerPC ISA 2.06 to build __float128 libraries... " 
>&6; }
 if ${libgcc_cv_powerpc_float128+:} false; then :
@@ -5195,13 +5194,7 @@ if ${libgcc_cv_powerpc_float128+:} false; then :
 else
   cat confdefs.h - <<_ACEOF >conftest.$ac_ext
 /* end confdefs.h.  */
-#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ && !defined(_ARCH_PPC64)
-#error "32-bit little endian does not support VSX for __float128"
-#endif
-#if !defined(__ARCH_PWR8)
-#pragma GCC target ("cpu=power8")
-#endif
-vector double dadd (vector double a, vector double b) { return a + b; }
+vector double dadd (vector double a, vector double b) { return a + b; }
 _ACEOF
 if ac_fn_c

[gcc(refs/users/meissner/heads/work169-bugs)] Do not build IEEE 128-bit support for little endian power5.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:398a67d35afbf08b3598e38087ca93fa8d26447f

commit 398a67d35afbf08b3598e38087ca93fa8d26447f
Author: Michael Meissner 
Date:   Tue Jun 18 13:26:03 2024 -0400

Do not build IEEE 128-bit support for little endian power5.

2024-06-18  Michael Meissner  

libgfortran/

* configure.ac (powerpc64le*-linux*): Check to see that the compiler
uses VSX before enabling IEEE 128-bit support.
* configure: Regenerate.
* kinds-override.h: Do not enable IEEE 128-bit floating point 
support on
little endian PowerPC that does not have VSX support.
* libgfortran.h (POWER_IEEE128): Add check for __VSX__.

libstdc++-v3/

* configure.ac (powerpc*-*-linux*): Skip IEEE 128-bit on little 
endian
PowerPC systems without VSX.
* configure: Regenerate.
* numeric_traits.h: Don't enable IEEE 128-bit on PowerPC systems 
without
VSX.

Diff:
---
 libgfortran/configure |  7 +++-
 libgfortran/configure.ac  |  3 ++
 libgfortran/kinds-override.h  |  2 +-
 libgfortran/libgfortran.h |  2 +-
 libstdc++-v3/configure| 68 ++-
 libstdc++-v3/configure.ac | 58 --
 libstdc++-v3/include/ext/numeric_traits.h |  2 +-
 7 files changed, 96 insertions(+), 46 deletions(-)

diff --git a/libgfortran/configure b/libgfortran/configure
index 11a1bc5f0708..2708e5c7eca4 100755
--- a/libgfortran/configure
+++ b/libgfortran/configure
@@ -5981,6 +5981,9 @@ if test "x$GCC" = "xyes"; then
 #if __SIZEOF_LONG_DOUBLE__ != 16
   #error long double is double
   #endif
+  #if !defined(__VSX__)
+  #error VSX is not available
+  #endif
 int
 main ()
 {
@@ -12847,7 +12850,7 @@ else
   lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
   lt_status=$lt_dlunknown
   cat > conftest.$ac_ext <<_LT_EOF
-#line 12850 "configure"
+#line 12853 "configure"
 #include "confdefs.h"
 
 #if HAVE_DLFCN_H
@@ -12953,7 +12956,7 @@ else
   lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
   lt_status=$lt_dlunknown
   cat > conftest.$ac_ext <<_LT_EOF
-#line 12956 "configure"
+#line 12959 "configure"
 #include "confdefs.h"
 
 #if HAVE_DLFCN_H
diff --git a/libgfortran/configure.ac b/libgfortran/configure.ac
index cca1ea0ea970..cfaeb9717ab8 100644
--- a/libgfortran/configure.ac
+++ b/libgfortran/configure.ac
@@ -148,6 +148,9 @@ if test "x$GCC" = "xyes"; then
   AC_PREPROC_IFELSE(
 [AC_LANG_PROGRAM([[#if __SIZEOF_LONG_DOUBLE__ != 16
   #error long double is double
+  #endif
+  #if !defined(__VSX__)
+  #error VSX is not available
   #endif]],
  [[(void) 0;]])],
 [AM_FCFLAGS="$AM_FCFLAGS -mabi=ibmlongdouble -mno-gnu-attribute";
diff --git a/libgfortran/kinds-override.h b/libgfortran/kinds-override.h
index f6b4956c5caa..51f440e53232 100644
--- a/libgfortran/kinds-override.h
+++ b/libgfortran/kinds-override.h
@@ -30,7 +30,7 @@ see the files COPYING3 and COPYING.RUNTIME respectively.  If 
not, see
 #endif
 
 /* Keep these conditions on one line so grep can filter it out.  */
-#if defined(__powerpc64__)  && __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__  && 
__SIZEOF_LONG_DOUBLE__ == 16
+#if defined(__powerpc64__)  && __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__  && 
__SIZEOF_LONG_DOUBLE__ == 16 && defined(__VSX__)
 typedef _Float128 GFC_REAL_17;
 typedef _Complex _Float128 GFC_COMPLEX_17;
 #define HAVE_GFC_REAL_17
diff --git a/libgfortran/libgfortran.h b/libgfortran/libgfortran.h
index 5c59ec26e16c..236603352435 100644
--- a/libgfortran/libgfortran.h
+++ b/libgfortran/libgfortran.h
@@ -104,7 +104,7 @@ typedef off_t gfc_offset;
 #endif
 
 #if defined(__powerpc64__) && __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ \
-&& defined __GLIBC_PREREQ
+&& defined __GLIBC_PREREQ && defined(__VSX__)
 #if __GLIBC_PREREQ (2, 32)
 #define POWER_IEEE128 1
 #endif
diff --git a/libstdc++-v3/configure b/libstdc++-v3/configure
index 5645e991af7a..706dcbefe11a 100755
--- a/libstdc++-v3/configure
+++ b/libstdc++-v3/configure
@@ -51355,8 +51355,31 @@ $as_echo "#define _GLIBCXX_LONG_DOUBLE_COMPAT 1" 
>>confdefs.h
 case "$target" in
   powerpc*-*-linux*)
LONG_DOUBLE_COMPAT_FLAGS="$LONG_DOUBLE_COMPAT_FLAGS -mno-gnu-attribute"
-# Check for IEEE128 support in libm:
-{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for __frexpieee128 
in -lm" >&5
+   # Eliminate little endian systems without VSX
+   cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+int
+main ()
+{
+
+ #if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ && !defined(__VSX__)
+ #error "IEEE 128

[gcc(refs/users/meissner/heads/work169-bugs)] Update ChangeLog.*

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:5411b60bd85b40db1e8fd7086e5531afc7caf0ec

commit 5411b60bd85b40db1e8fd7086e5531afc7caf0ec
Author: Michael Meissner 
Date:   Tue Jun 18 13:27:54 2024 -0400

Update ChangeLog.*

Diff:
---
 gcc/ChangeLog.bugs | 26 --
 1 file changed, 12 insertions(+), 14 deletions(-)

diff --git a/gcc/ChangeLog.bugs b/gcc/ChangeLog.bugs
index 4bd3e28874b9..449f44ce3fa8 100644
--- a/gcc/ChangeLog.bugs
+++ b/gcc/ChangeLog.bugs
@@ -1,22 +1,9 @@
- Branch work169-bugs, patch #401 
+ Branch work169-bugs, patch #402 
 
 Do not build IEEE 128-bit support for little endian power5.
 
 2024-06-18  Michael Meissner  
 
-gcc/
-
-   * config/rs6000/rs6000.cc (rs6000_option_override_internal): Do not
-   allow IEEE 128-bit on little endian 32-bit systems.
-
-libgcc/
-
-   * config.host (powerpc*-linux*): Do not enable ieee 128-bit hardware
-   support unless ieee 128-bit basic support is provided.
-   * configure.ac (powerpc*-linux*): Disable building libgcc on legacy
-   32-bit little endian systems which will never support VSX.
-   * configure: Regenerate.
-
 libgfortran/
 
* configure.ac (powerpc64le*-linux*): Check to see that the compiler
@@ -24,6 +11,17 @@ libgfortran/
* configure: Regenerate.
* kinds-override.h: Do not enable IEEE 128-bit floating point support on
little endian PowerPC that does not have VSX support.
+   * libgfortran.h (POWER_IEEE128): Add check for __VSX__.
+
+libstdc++-v3/
+
+   * configure.ac (powerpc*-*-linux*): Skip IEEE 128-bit on little endian
+   PowerPC systems without VSX.
+   * configure: Regenerate.
+   * numeric_traits.h: Don't enable IEEE 128-bit on PowerPC systems without
+   VSX.
+
+ Branch work169-bugs, patch #401 was reverted 

 
  Branch work169-bugs, patch #400 was reverted 

[gcc r15-1419] [committed] [RISC-V] Fix wrong patch application

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:cbf7245c8b305fe997a535051a4fec379a429243

commit r15-1419-gcbf7245c8b305fe997a535051a4fec379a429243
Author: Jeff Law 
Date:   Tue Jun 18 12:10:57 2024 -0600

[committed] [RISC-V] Fix wrong patch application

Applied the wrong patch which didn't have the final testsuite adjustment to
skip -Os on the new test.  Fixed thusly.

Pushed to the trunk.

gcc/testsuite
* gcc.target/riscv/zbs-ext-2.c: Do not run for -Os.

Diff:
---
 gcc/testsuite/gcc.target/riscv/zbs-ext-2.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/testsuite/gcc.target/riscv/zbs-ext-2.c 
b/gcc/testsuite/gcc.target/riscv/zbs-ext-2.c
index 301bc9d89c4e..690dd722bce9 100644
--- a/gcc/testsuite/gcc.target/riscv/zbs-ext-2.c
+++ b/gcc/testsuite/gcc.target/riscv/zbs-ext-2.c
@@ -1,6 +1,6 @@
 /* { dg-do compile } */
 /* { dg-options "-march=rv64gc_zbb_zbs -mabi=lp64" } */
-/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" } } */
 
 
 typedef unsigned int uint32_t;

[gcc(refs/users/meissner/heads/work169-bugs)] Revert changes

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:0e66a6400cf99e965e679362eac65483f938b138

commit 0e66a6400cf99e965e679362eac65483f938b138
Author: Michael Meissner 
Date:   Tue Jun 18 14:27:18 2024 -0400

Revert changes

Diff:
---
 libgfortran/configure |  7 +---
 libgfortran/configure.ac  |  3 --
 libgfortran/kinds-override.h  |  2 +-
 libgfortran/libgfortran.h |  2 +-
 libstdc++-v3/configure| 68 +--
 libstdc++-v3/configure.ac | 58 ++
 libstdc++-v3/include/ext/numeric_traits.h |  2 +-
 7 files changed, 46 insertions(+), 96 deletions(-)

diff --git a/libgfortran/configure b/libgfortran/configure
index 2708e5c7eca4..11a1bc5f0708 100755
--- a/libgfortran/configure
+++ b/libgfortran/configure
@@ -5981,9 +5981,6 @@ if test "x$GCC" = "xyes"; then
 #if __SIZEOF_LONG_DOUBLE__ != 16
   #error long double is double
   #endif
-  #if !defined(__VSX__)
-  #error VSX is not available
-  #endif
 int
 main ()
 {
@@ -12850,7 +12847,7 @@ else
   lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
   lt_status=$lt_dlunknown
   cat > conftest.$ac_ext <<_LT_EOF
-#line 12853 "configure"
+#line 12850 "configure"
 #include "confdefs.h"
 
 #if HAVE_DLFCN_H
@@ -12956,7 +12953,7 @@ else
   lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
   lt_status=$lt_dlunknown
   cat > conftest.$ac_ext <<_LT_EOF
-#line 12959 "configure"
+#line 12956 "configure"
 #include "confdefs.h"
 
 #if HAVE_DLFCN_H
diff --git a/libgfortran/configure.ac b/libgfortran/configure.ac
index cfaeb9717ab8..cca1ea0ea970 100644
--- a/libgfortran/configure.ac
+++ b/libgfortran/configure.ac
@@ -148,9 +148,6 @@ if test "x$GCC" = "xyes"; then
   AC_PREPROC_IFELSE(
 [AC_LANG_PROGRAM([[#if __SIZEOF_LONG_DOUBLE__ != 16
   #error long double is double
-  #endif
-  #if !defined(__VSX__)
-  #error VSX is not available
   #endif]],
  [[(void) 0;]])],
 [AM_FCFLAGS="$AM_FCFLAGS -mabi=ibmlongdouble -mno-gnu-attribute";
diff --git a/libgfortran/kinds-override.h b/libgfortran/kinds-override.h
index 51f440e53232..f6b4956c5caa 100644
--- a/libgfortran/kinds-override.h
+++ b/libgfortran/kinds-override.h
@@ -30,7 +30,7 @@ see the files COPYING3 and COPYING.RUNTIME respectively.  If 
not, see
 #endif
 
 /* Keep these conditions on one line so grep can filter it out.  */
-#if defined(__powerpc64__)  && __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__  && 
__SIZEOF_LONG_DOUBLE__ == 16 && defined(__VSX__)
+#if defined(__powerpc64__)  && __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__  && 
__SIZEOF_LONG_DOUBLE__ == 16
 typedef _Float128 GFC_REAL_17;
 typedef _Complex _Float128 GFC_COMPLEX_17;
 #define HAVE_GFC_REAL_17
diff --git a/libgfortran/libgfortran.h b/libgfortran/libgfortran.h
index 236603352435..5c59ec26e16c 100644
--- a/libgfortran/libgfortran.h
+++ b/libgfortran/libgfortran.h
@@ -104,7 +104,7 @@ typedef off_t gfc_offset;
 #endif
 
 #if defined(__powerpc64__) && __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ \
-&& defined __GLIBC_PREREQ && defined(__VSX__)
+&& defined __GLIBC_PREREQ
 #if __GLIBC_PREREQ (2, 32)
 #define POWER_IEEE128 1
 #endif
diff --git a/libstdc++-v3/configure b/libstdc++-v3/configure
index 706dcbefe11a..5645e991af7a 100755
--- a/libstdc++-v3/configure
+++ b/libstdc++-v3/configure
@@ -51355,31 +51355,8 @@ $as_echo "#define _GLIBCXX_LONG_DOUBLE_COMPAT 1" 
>>confdefs.h
 case "$target" in
   powerpc*-*-linux*)
LONG_DOUBLE_COMPAT_FLAGS="$LONG_DOUBLE_COMPAT_FLAGS -mno-gnu-attribute"
-   # Eliminate little endian systems without VSX
-   cat confdefs.h - <<_ACEOF >conftest.$ac_ext
-/* end confdefs.h.  */
-
-int
-main ()
-{
-
- #if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ && !defined(__VSX__)
- #error "IEEE 128-bit cannot be supported on non-VSX little endian 
systems"
- #endif
-
-  ;
-  return 0;
-}
-_ACEOF
-if ac_fn_c_try_compile "$LINENO"; then :
-  ac_ieee128_possible=yes
-else
-  ac_ieee128_possible=no
-fi
-rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
-   if test $ac_ieee128_possible = yes; then
-  # Check for IEEE128 support in libm:
-  { $as_echo "$as_me:${as_lineno-$LINENO}: checking for __frexpieee128 
in -lm" >&5
+# Check for IEEE128 support in libm:
+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for __frexpieee128 
in -lm" >&5
 $as_echo_n "checking for __frexpieee128 in -lm... " >&6; }
 if ${ac_cv_lib_m___frexpieee128+:} false; then :
   $as_echo_n "(cached) " >&6
@@ -51424,18 +51401,18 @@ else
   ac_ldbl_ieee128_in_libc=no
 fi
 
-  if test $ac_ldbl_ieee128_in_libc = yes; then
-# Determine which long double format is the compiler's defaul

[gcc(refs/users/meissner/heads/work169-bugs)] Do not build IEEE 128-bit support if VSX is not available.

[Michael Meissner via Libstdc++-cvs]

https://gcc.gnu.org/g:bf53eea91a2c76e9fdd21fbb20e1d3528073c826

commit bf53eea91a2c76e9fdd21fbb20e1d3528073c826
Author: Michael Meissner 
Date:   Tue Jun 18 14:34:52 2024 -0400

Do not build IEEE 128-bit support if VSX is not available.

2024-06-18  Michael Meissner  

libgfortran/

* configure.ac (powerpc64le*-linux*): Check to see that the compiler
uses VSX before enabling IEEE 128-bit support.
* configure: Regenerate.
* kinds-override.h (GFC_REAL_17): Add check for __VSX__.
* libgfortran.h (POWER_IEEE128): Likewise.

libstdc++-v3/

* configure.ac (powerpc*-*-linux*): Don't enable IEEE 128-bit on 
PowerPC
systems without VSX.
* configure: Regenerate.
* numeric_traits.h: Don't enable IEEE 128-bit on PowerPC systems 
without
VSX.

Diff:
---
 libgfortran/configure |  7 +++-
 libgfortran/configure.ac  |  3 ++
 libgfortran/kinds-override.h  |  2 +-
 libgfortran/libgfortran.h |  2 +-
 libstdc++-v3/configure| 68 ++-
 libstdc++-v3/configure.ac | 58 --
 libstdc++-v3/include/ext/numeric_traits.h |  2 +-
 7 files changed, 96 insertions(+), 46 deletions(-)

diff --git a/libgfortran/configure b/libgfortran/configure
index 11a1bc5f0708..2708e5c7eca4 100755
--- a/libgfortran/configure
+++ b/libgfortran/configure
@@ -5981,6 +5981,9 @@ if test "x$GCC" = "xyes"; then
 #if __SIZEOF_LONG_DOUBLE__ != 16
   #error long double is double
   #endif
+  #if !defined(__VSX__)
+  #error VSX is not available
+  #endif
 int
 main ()
 {
@@ -12847,7 +12850,7 @@ else
   lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
   lt_status=$lt_dlunknown
   cat > conftest.$ac_ext <<_LT_EOF
-#line 12850 "configure"
+#line 12853 "configure"
 #include "confdefs.h"
 
 #if HAVE_DLFCN_H
@@ -12953,7 +12956,7 @@ else
   lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
   lt_status=$lt_dlunknown
   cat > conftest.$ac_ext <<_LT_EOF
-#line 12956 "configure"
+#line 12959 "configure"
 #include "confdefs.h"
 
 #if HAVE_DLFCN_H
diff --git a/libgfortran/configure.ac b/libgfortran/configure.ac
index cca1ea0ea970..cfaeb9717ab8 100644
--- a/libgfortran/configure.ac
+++ b/libgfortran/configure.ac
@@ -148,6 +148,9 @@ if test "x$GCC" = "xyes"; then
   AC_PREPROC_IFELSE(
 [AC_LANG_PROGRAM([[#if __SIZEOF_LONG_DOUBLE__ != 16
   #error long double is double
+  #endif
+  #if !defined(__VSX__)
+  #error VSX is not available
   #endif]],
  [[(void) 0;]])],
 [AM_FCFLAGS="$AM_FCFLAGS -mabi=ibmlongdouble -mno-gnu-attribute";
diff --git a/libgfortran/kinds-override.h b/libgfortran/kinds-override.h
index f6b4956c5caa..51f440e53232 100644
--- a/libgfortran/kinds-override.h
+++ b/libgfortran/kinds-override.h
@@ -30,7 +30,7 @@ see the files COPYING3 and COPYING.RUNTIME respectively.  If 
not, see
 #endif
 
 /* Keep these conditions on one line so grep can filter it out.  */
-#if defined(__powerpc64__)  && __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__  && 
__SIZEOF_LONG_DOUBLE__ == 16
+#if defined(__powerpc64__)  && __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__  && 
__SIZEOF_LONG_DOUBLE__ == 16 && defined(__VSX__)
 typedef _Float128 GFC_REAL_17;
 typedef _Complex _Float128 GFC_COMPLEX_17;
 #define HAVE_GFC_REAL_17
diff --git a/libgfortran/libgfortran.h b/libgfortran/libgfortran.h
index 5c59ec26e16c..236603352435 100644
--- a/libgfortran/libgfortran.h
+++ b/libgfortran/libgfortran.h
@@ -104,7 +104,7 @@ typedef off_t gfc_offset;
 #endif
 
 #if defined(__powerpc64__) && __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ \
-&& defined __GLIBC_PREREQ
+&& defined __GLIBC_PREREQ && defined(__VSX__)
 #if __GLIBC_PREREQ (2, 32)
 #define POWER_IEEE128 1
 #endif
diff --git a/libstdc++-v3/configure b/libstdc++-v3/configure
index 5645e991af7a..daab67f9deea 100755
--- a/libstdc++-v3/configure
+++ b/libstdc++-v3/configure
@@ -51355,8 +51355,31 @@ $as_echo "#define _GLIBCXX_LONG_DOUBLE_COMPAT 1" 
>>confdefs.h
 case "$target" in
   powerpc*-*-linux*)
LONG_DOUBLE_COMPAT_FLAGS="$LONG_DOUBLE_COMPAT_FLAGS -mno-gnu-attribute"
-# Check for IEEE128 support in libm:
-{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for __frexpieee128 
in -lm" >&5
+   # Eliminate little endian systems without VSX
+   cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+int
+main ()
+{
+
+ #ifndef __VSX__
+ #error "IEEE 128-bit needs VSX"
+ #endif
+
+  ;
+  return 0;
+}
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  ac_ieee128_possible=yes
+else
+  ac_ieee128_p

[gcc(refs/users/meissner/heads/work169-bugs)] Update ChangeLog.*

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:1bc45f0d5b2495275ce6acd45cb11669f09defcf

commit 1bc45f0d5b2495275ce6acd45cb11669f09defcf
Author: Michael Meissner 
Date:   Tue Jun 18 14:36:17 2024 -0400

Update ChangeLog.*

Diff:
---
 gcc/ChangeLog.bugs | 15 +++
 1 file changed, 7 insertions(+), 8 deletions(-)

diff --git a/gcc/ChangeLog.bugs b/gcc/ChangeLog.bugs
index 449f44ce3fa8..e52a70168c3a 100644
--- a/gcc/ChangeLog.bugs
+++ b/gcc/ChangeLog.bugs
@@ -1,6 +1,6 @@
- Branch work169-bugs, patch #402 
+ Branch work169-bugs, patch #403 
 
-Do not build IEEE 128-bit support for little endian power5.
+Do not build IEEE 128-bit support if VSX is not available.
 
 2024-06-18  Michael Meissner  
 
@@ -9,20 +9,19 @@ libgfortran/
* configure.ac (powerpc64le*-linux*): Check to see that the compiler
uses VSX before enabling IEEE 128-bit support.
* configure: Regenerate.
-   * kinds-override.h: Do not enable IEEE 128-bit floating point support on
-   little endian PowerPC that does not have VSX support.
-   * libgfortran.h (POWER_IEEE128): Add check for __VSX__.
+   * kinds-override.h (GFC_REAL_17): Add check for __VSX__.
+   * libgfortran.h (POWER_IEEE128): Likewise.
 
 libstdc++-v3/
 
-   * configure.ac (powerpc*-*-linux*): Skip IEEE 128-bit on little endian
-   PowerPC systems without VSX.
+   * configure.ac (powerpc*-*-linux*): Don't enable IEEE 128-bit on PowerPC
+   systems without VSX.
* configure: Regenerate.
* numeric_traits.h: Don't enable IEEE 128-bit on PowerPC systems without
VSX.
 
+ Branch work169-bugs, patch #402 was reverted 

  Branch work169-bugs, patch #401 was reverted 

-
  Branch work169-bugs, patch #400 was reverted 

 
  Branch work169-bugs, patch #11 (work169 branch) 

[gcc r15-1420] RISC-V: Fix vwsll combine on rv32 targets

[Edwin Lu via Gcc-cvs]

https://gcc.gnu.org/g:6638ba17eadc0f450faa3d8c2f77afe7fdb20614

commit r15-1420-g6638ba17eadc0f450faa3d8c2f77afe7fdb20614
Author: Edwin Lu 
Date:   Tue Jun 11 13:50:02 2024 -0700

RISC-V: Fix vwsll combine on rv32 targets

On rv32 targets, vwsll_zext1_scalar_ would trigger an ice in
maybe_legitimize_instruction when zero extending a uint32 to uint64 due
to a mismatch between the input operand's mode (DI) and the expanded insn
operand's mode (Pmode == SI). Ensure that mode of the operands match

gcc/ChangeLog:

* config/riscv/autovec-opt.md: Fix mode mismatch

Signed-off-by: Edwin Lu 
Co-authored-by: Robin Dapp 

Diff:
---
 gcc/config/riscv/autovec-opt.md | 6 ++
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md
index 6a2eabbd8544..d7a3cfd4602b 100644
--- a/gcc/config/riscv/autovec-opt.md
+++ b/gcc/config/riscv/autovec-opt.md
@@ -1517,8 +1517,7 @@
   "&& 1"
   [(const_int 0)]
   {
-if (GET_CODE (operands[2]) == SUBREG)
-  operands[2] = SUBREG_REG (operands[2]);
+operands[2] = gen_lowpart (Pmode, operands[2]);
 insn_code icode = code_for_pred_vwsll_scalar (mode);
 riscv_vector::emit_vlmax_insn (icode, riscv_vector::BINARY_OP, operands);
 DONE;
@@ -1584,8 +1583,7 @@
   "&& 1"
   [(const_int 0)]
   {
-if (GET_CODE (operands[2]) == SUBREG)
-  operands[2] = SUBREG_REG (operands[2]);
+operands[2] = gen_lowpart (Pmode, operands[2]);
 insn_code icode = code_for_pred_vwsll_scalar (mode);
 riscv_vector::emit_vlmax_insn (icode, riscv_vector::BINARY_OP, operands);
 DONE;

[gcc r15-1421] RISC-V: Move mode assertion out of conditional branch in emit_insn

[Edwin Lu via Gcc-cvs]

https://gcc.gnu.org/g:ffe5141f30655e1889c8d0471a4f60fa4d64d1b0

commit r15-1421-gffe5141f30655e1889c8d0471a4f60fa4d64d1b0
Author: Edwin Lu 
Date:   Fri Jun 14 09:46:01 2024 -0700

RISC-V: Move mode assertion out of conditional branch in emit_insn

When emitting insns, we have an early assertion to ensure the input
operand's mode and the expanded operand's mode are the same; however, it
does not perform this check if the pattern does not have an explicit
machine mode specifying the operand. In this scenario, it will always
assume that mode = Pmode to correctly satisfy the
maybe_legitimize_operand check, however, there may be problems when
working in 32 bit environments.

Make the assert unconditional and replace it with an internal error for
more descriptive logging

gcc/ChangeLog:

* config/riscv/riscv-v.cc: Move assert out of conditional block

Signed-off-by: Edwin Lu 
Co-authored-by: Robin Dapp 

Diff:
---
 gcc/config/riscv/riscv-v.cc | 25 +++--
 1 file changed, 19 insertions(+), 6 deletions(-)

diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 8911f5783c88..5306711c1b73 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -50,6 +50,7 @@
 #include "rtx-vector-builder.h"
 #include "targhooks.h"
 #include "predict.h"
+#include "errors.h"
 
 using namespace riscv_vector;
 
@@ -290,11 +291,17 @@ public:
   always Pmode.  */
if (mode == VOIDmode)
  mode = Pmode;
-   else
- /* Early assertion ensures same mode since maybe_legitimize_operand
-will check this.  */
- gcc_assert (GET_MODE (ops[opno]) == VOIDmode
- || GET_MODE (ops[opno]) == mode);
+
+   /* Early assertion ensures same mode since maybe_legitimize_operand
+  will check this.  */
+   machine_mode required_mode = GET_MODE (ops[opno]);
+   if (required_mode != VOIDmode && required_mode != mode)
+ internal_error ("expected mode %s for operand %d of "
+ "insn %s but got mode %s.\n",
+ GET_MODE_NAME (mode),
+ opno,
+ insn_data[(int) icode].name,
+ GET_MODE_NAME (required_mode));
 
add_input_operand (ops[opno], mode);
   }
@@ -346,7 +353,13 @@ public:
 else if (m_insn_flags & VXRM_RDN_P)
   add_rounding_mode_operand (VXRM_RDN);
 
-gcc_assert (insn_data[(int) icode].n_operands == m_opno);
+
+if (insn_data[(int) icode].n_operands != m_opno)
+  internal_error ("invalid number of operands for insn %s, "
+ "expected %d but got %d.\n",
+ insn_data[(int) icode].name,
+ insn_data[(int) icode].n_operands, m_opno);
+
 expand (icode, any_mem_p);
   }

[gcc r15-1423] [MAINTAINERS] Update my email address and move to DCO.

[Ramana Radhakrishnan via Gcc-cvs]

https://gcc.gnu.org/g:17d0982f425dbdeb528b70d141e70b006f6b9df6

commit r15-1423-g17d0982f425dbdeb528b70d141e70b006f6b9df6
Author: Ramana Radhakrishnan 
Date:   Wed Jun 19 06:48:57 2024 +0530

[MAINTAINERS] Update my email address and move to DCO.

Signed-off-by: Ramana Radhakrishnan  

* MAINTAINERS: Update my email address.

Diff:
---
 MAINTAINERS | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index 8b6fa16f79a9..41319595bb5c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -59,7 +59,7 @@ amdgcn port   Andrew Stubbs   

 arc port   Claudiu Zissulescu  
 arm port   Nick Clifton
 arm port   Richard Earnshaw
-arm port   Ramana Radhakrishnan
+arm port   Ramana Radhakrishnan
 avr port   Denis Chertykov 
 bfin port  Jie Zhang   
 bpf port   Jose E. Marchesi
@@ -776,6 +776,7 @@ Immad Mir   

 Gaius Mulley   
 Andrew Pinski  
 Siddhesh Poyarekar 
+Ramana Radhakrishnan   
 Navid Rahimi   
 Rishi Raj  

 Trevor Saunders

[gcc r15-1424] RISC-V: Add testcases for unsigned .SAT_SUB scalar form 11

[Pan Li via Gcc-cvs]

https://gcc.gnu.org/g:6315c000c027948fd49d9f5a55aa83808b21b85a

commit r15-1424-g6315c000c027948fd49d9f5a55aa83808b21b85a
Author: Pan Li 
Date:   Tue Jun 18 16:14:23 2024 +0800

RISC-V: Add testcases for unsigned .SAT_SUB scalar form 11

After the middle-end support the form 11 of unsigned SAT_SUB and
the RISC-V backend implement the SAT_SUB for vector mode, add
more test case to cover the form 11.

Form 11:
  #define DEF_SAT_U_SUB_FMT_11(T)\
  T __attribute__((noinline))\
  sat_u_sub_##T##_fmt_11 (T x, T y)  \
  {  \
T ret;   \
bool overflow = __builtin_sub_overflow (x, y, &ret); \
return overflow ? 0 : ret;   \
  }

Passed the rv64gcv regression tests.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/sat_arith.h: Add helper
macro for testing.
* gcc.target/riscv/sat_u_sub-41.c: New test.
* gcc.target/riscv/sat_u_sub-42.c: New test.
* gcc.target/riscv/sat_u_sub-43.c: New test.
* gcc.target/riscv/sat_u_sub-44.c: New test.
* gcc.target/riscv/sat_u_sub-run-41.c: New test.
* gcc.target/riscv/sat_u_sub-run-42.c: New test.
* gcc.target/riscv/sat_u_sub-run-43.c: New test.
* gcc.target/riscv/sat_u_sub-run-44.c: New test.

Signed-off-by: Pan Li 

Diff:
---
 gcc/testsuite/gcc.target/riscv/sat_arith.h| 11 ++
 gcc/testsuite/gcc.target/riscv/sat_u_sub-41.c | 18 
 gcc/testsuite/gcc.target/riscv/sat_u_sub-42.c | 19 +
 gcc/testsuite/gcc.target/riscv/sat_u_sub-43.c | 18 
 gcc/testsuite/gcc.target/riscv/sat_u_sub-44.c | 17 +++
 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-41.c | 25 +++
 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-42.c | 25 +++
 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-43.c | 25 +++
 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-44.c | 25 +++
 9 files changed, 183 insertions(+)

diff --git a/gcc/testsuite/gcc.target/riscv/sat_arith.h 
b/gcc/testsuite/gcc.target/riscv/sat_arith.h
index 0f94c5ff087b..ab7289a69476 100644
--- a/gcc/testsuite/gcc.target/riscv/sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/sat_arith.h
@@ -2,6 +2,7 @@
 #define HAVE_SAT_ARITH
 
 #include 
+#include 
 
 
/**/
 /* Saturation Add (unsigned and signed)   
*/
@@ -140,6 +141,15 @@ sat_u_sub_##T##_fmt_10 (T x, T y)   \
   return !overflow ? ret : 0;   \
 }
 
+#define DEF_SAT_U_SUB_FMT_11(T)\
+T __attribute__((noinline))\
+sat_u_sub_##T##_fmt_11 (T x, T y)  \
+{  \
+  T ret;   \
+  bool overflow = __builtin_sub_overflow (x, y, &ret); \
+  return overflow ? 0 : ret;   \
+}
+
 #define RUN_SAT_U_SUB_FMT_1(T, x, y) sat_u_sub_##T##_fmt_1(x, y)
 #define RUN_SAT_U_SUB_FMT_2(T, x, y) sat_u_sub_##T##_fmt_2(x, y)
 #define RUN_SAT_U_SUB_FMT_3(T, x, y) sat_u_sub_##T##_fmt_3(x, y)
@@ -150,5 +160,6 @@ sat_u_sub_##T##_fmt_10 (T x, T y)   \
 #define RUN_SAT_U_SUB_FMT_8(T, x, y) sat_u_sub_##T##_fmt_8(x, y)
 #define RUN_SAT_U_SUB_FMT_9(T, x, y) sat_u_sub_##T##_fmt_9(x, y)
 #define RUN_SAT_U_SUB_FMT_10(T, x, y) sat_u_sub_##T##_fmt_10(x, y)
+#define RUN_SAT_U_SUB_FMT_11(T, x, y) sat_u_sub_##T##_fmt_11(x, y)
 
 #endif
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-41.c 
b/gcc/testsuite/gcc.target/riscv/sat_u_sub-41.c
new file mode 100644
index ..dd13f94e40f2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-41.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details 
-fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint8_t_fmt_11:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*a0,\s*[atx][0-9]+
+** andi\s+a0,\s*a0,\s*0xff
+** ret
+*/
+DEF_SAT_U_SUB_FMT_11(uint8_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-42.c 
b/gcc/testsuite/gcc.target/riscv/sat_u_sub-42.c
new file mode 100644
index ..3ed4195b18b2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-42.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rt

[gcc r15-1425] RISC-V: Add testcases for unsigned .SAT_SUB scalar form 12

[Pan Li via Gcc-cvs]

https://gcc.gnu.org/g:61655f5c95186960f637c26130f08098e5407516

commit r15-1425-g61655f5c95186960f637c26130f08098e5407516
Author: Pan Li 
Date:   Tue Jun 18 16:22:59 2024 +0800

RISC-V: Add testcases for unsigned .SAT_SUB scalar form 12

After the middle-end support the form 12 of unsigned SAT_SUB and
the RISC-V backend implement the SAT_SUB for vector mode, add
more test case to cover the form 12.

Form 12:
  #define DEF_SAT_U_SUB_FMT_12(T)\
  T __attribute__((noinline))\
  sat_u_sub_##T##_fmt_12 (T x, T y)  \
  {  \
T ret;   \
bool overflow = __builtin_sub_overflow (x, y, &ret); \
return !overflow ? ret : 0;  \
  }

Passed the rv64gcv regression tests.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/sat_arith.h: Add helper macro for
testing.
* gcc.target/riscv/sat_u_sub-45.c: New test.
* gcc.target/riscv/sat_u_sub-46.c: New test.
* gcc.target/riscv/sat_u_sub-47.c: New test.
* gcc.target/riscv/sat_u_sub-48.c: New test.
* gcc.target/riscv/sat_u_sub-run-45.c: New test.
* gcc.target/riscv/sat_u_sub-run-46.c: New test.
* gcc.target/riscv/sat_u_sub-run-47.c: New test.
* gcc.target/riscv/sat_u_sub-run-48.c: New test.

Signed-off-by: Pan Li 

Diff:
---
 gcc/testsuite/gcc.target/riscv/sat_arith.h| 10 +
 gcc/testsuite/gcc.target/riscv/sat_u_sub-45.c | 18 
 gcc/testsuite/gcc.target/riscv/sat_u_sub-46.c | 19 +
 gcc/testsuite/gcc.target/riscv/sat_u_sub-47.c | 18 
 gcc/testsuite/gcc.target/riscv/sat_u_sub-48.c | 17 +++
 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-45.c | 25 +++
 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-46.c | 25 +++
 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-47.c | 25 +++
 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-48.c | 25 +++
 9 files changed, 182 insertions(+)

diff --git a/gcc/testsuite/gcc.target/riscv/sat_arith.h 
b/gcc/testsuite/gcc.target/riscv/sat_arith.h
index ab7289a69476..0c2e44af7189 100644
--- a/gcc/testsuite/gcc.target/riscv/sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/sat_arith.h
@@ -150,6 +150,15 @@ sat_u_sub_##T##_fmt_11 (T x, T y)  \
   return overflow ? 0 : ret;   \
 }
 
+#define DEF_SAT_U_SUB_FMT_12(T)\
+T __attribute__((noinline))\
+sat_u_sub_##T##_fmt_12 (T x, T y)  \
+{  \
+  T ret;   \
+  bool overflow = __builtin_sub_overflow (x, y, &ret); \
+  return !overflow ? ret : 0;  \
+}
+
 #define RUN_SAT_U_SUB_FMT_1(T, x, y) sat_u_sub_##T##_fmt_1(x, y)
 #define RUN_SAT_U_SUB_FMT_2(T, x, y) sat_u_sub_##T##_fmt_2(x, y)
 #define RUN_SAT_U_SUB_FMT_3(T, x, y) sat_u_sub_##T##_fmt_3(x, y)
@@ -161,5 +170,6 @@ sat_u_sub_##T##_fmt_11 (T x, T y)  \
 #define RUN_SAT_U_SUB_FMT_9(T, x, y) sat_u_sub_##T##_fmt_9(x, y)
 #define RUN_SAT_U_SUB_FMT_10(T, x, y) sat_u_sub_##T##_fmt_10(x, y)
 #define RUN_SAT_U_SUB_FMT_11(T, x, y) sat_u_sub_##T##_fmt_11(x, y)
+#define RUN_SAT_U_SUB_FMT_12(T, x, y) sat_u_sub_##T##_fmt_12(x, y)
 
 #endif
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-45.c 
b/gcc/testsuite/gcc.target/riscv/sat_u_sub-45.c
new file mode 100644
index ..1aad8961e29d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-45.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details 
-fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint8_t_fmt_12:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*a0,\s*[atx][0-9]+
+** andi\s+a0,\s*a0,\s*0xff
+** ret
+*/
+DEF_SAT_U_SUB_FMT_12(uint8_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-46.c 
b/gcc/testsuite/gcc.target/riscv/sat_u_sub-46.c
new file mode 100644
index ..d184043f6f83
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-46.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details 
-fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint16_t_fmt_12:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sl

[gcc r15-1426] RISC-V: Add testcases for unsigned .SAT_ADD vector form 2

[Pan Li via Gcc-cvs]

https://gcc.gnu.org/g:a84945e521e5687cdc46fc1f963d64d0b7f26cdd

commit r15-1426-ga84945e521e5687cdc46fc1f963d64d0b7f26cdd
Author: Pan Li 
Date:   Mon Jun 17 14:39:10 2024 +0800

RISC-V: Add testcases for unsigned .SAT_ADD vector form 2

After the middle-end support the form 2 of unsigned SAT_ADD and
the RISC-V backend implement the .SAT_ADD for vector mode, add
more test case to cover the form 2.

Form 2:
  #define DEF_VEC_SAT_U_ADD_FMT_2(T)   \
  void __attribute__((noinline))   \
  vec_sat_u_add_##T##_fmt_2 (T *out, T *op_1, T *op_2, unsigned limit) \
  {\
unsigned i;\
for (i = 0; i < limit; i++)\
  {\
T x = op_1[i]; \
T y = op_2[i]; \
out[i] = (T)(x + y) >= x ? (x + y) : -1;   \
  }\
  }

Passed the rv64gcv regression tests.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: Add helper
macro for testing.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-5.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-6.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-7.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-8.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-5.c: New 
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-6.c: New 
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-7.c: New 
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-8.c: New 
test.

Signed-off-by: Pan Li 

Diff:
---
 .../riscv/rvv/autovec/binop/vec_sat_arith.h| 16 +
 .../riscv/rvv/autovec/binop/vec_sat_u_add-5.c  | 19 ++
 .../riscv/rvv/autovec/binop/vec_sat_u_add-6.c  | 20 ++
 .../riscv/rvv/autovec/binop/vec_sat_u_add-7.c  | 20 ++
 .../riscv/rvv/autovec/binop/vec_sat_u_add-8.c  | 20 ++
 .../riscv/rvv/autovec/binop/vec_sat_u_add-run-5.c  | 75 ++
 .../riscv/rvv/autovec/binop/vec_sat_u_add-run-6.c  | 75 ++
 .../riscv/rvv/autovec/binop/vec_sat_u_add-run-7.c  | 75 ++
 .../riscv/rvv/autovec/binop/vec_sat_u_add-run-8.c  | 75 ++
 9 files changed, 395 insertions(+)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h
index 450f0fbbc72c..57b1bce4bd2c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h
@@ -19,9 +19,25 @@ vec_sat_u_add_##T##_fmt_1 (T *out, T *op_1, T *op_2, 
unsigned limit) \
 }\
 }
 
+#define DEF_VEC_SAT_U_ADD_FMT_2(T)   \
+void __attribute__((noinline))   \
+vec_sat_u_add_##T##_fmt_2 (T *out, T *op_1, T *op_2, unsigned limit) \
+{\
+  unsigned i;\
+  for (i = 0; i < limit; i++)\
+{\
+  T x = op_1[i]; \
+  T y = op_2[i]; \
+  out[i] = (T)(x + y) >= x ? (x + y) : -1;   \
+}\
+}
+
 #define RUN_VEC_SAT_U_ADD_FMT_1(T, out, op_1, op_2, N) \
   vec_sat_u_add_##T##_fmt_1(out, op_1, op_2, N)
 
+#define RUN_VEC_SAT_U_ADD_FMT_2(T, out, op_1, op_2, N) \
+  vec_sat_u_add_##T##_fmt_2(out, op_1, op_2, N)
+
 
/**/
 /* Saturation Sub (Unsigned and Signed)   
*/
 
/**/
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-5.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-5.c
new file mode 100644
index ..a46a3c592c24
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-5.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-ve

[gcc r15-1427] RISC-V: Add testcases for unsigned .SAT_ADD vector form 3

[Pan Li via Gcc-cvs]

https://gcc.gnu.org/g:1bdcac7aefdd2a170112e2c78e8e769f7caad0a2

commit r15-1427-g1bdcac7aefdd2a170112e2c78e8e769f7caad0a2
Author: Pan Li 
Date:   Mon Jun 17 14:53:12 2024 +0800

RISC-V: Add testcases for unsigned .SAT_ADD vector form 3

After the middle-end support the form 3 of unsigned SAT_ADD and
the RISC-V backend implement the .SAT_ADD for vector mode, add
more test case to cover the form 3.

Form 3:
  #define DEF_VEC_SAT_U_ADD_FMT_3(T)   \
  void __attribute__((noinline))   \
  vec_sat_u_add_##T##_fmt_3 (T *out, T *op_1, T *op_2, unsigned limit) \
  {\
unsigned i;\
for (i = 0; i < limit; i++)\
  {\
T x = op_1[i]; \
T y = op_2[i]; \
T ret; \
T overflow = __builtin_add_overflow (x, y, &ret);  \
out[i] = (T)(-overflow) | ret; \
  }\
  }

Passed the rv64gcv regression tests.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: Add helper
macro for testing.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-10.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-11.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-12.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-9.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-10.c: New 
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-11.c: New 
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-12.c: New 
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-9.c: New 
test.

Signed-off-by: Pan Li 

Diff:
---
 .../riscv/rvv/autovec/binop/vec_sat_arith.h| 18 ++
 .../riscv/rvv/autovec/binop/vec_sat_u_add-10.c | 20 ++
 .../riscv/rvv/autovec/binop/vec_sat_u_add-11.c | 20 ++
 .../riscv/rvv/autovec/binop/vec_sat_u_add-12.c | 20 ++
 .../riscv/rvv/autovec/binop/vec_sat_u_add-9.c  | 19 ++
 .../riscv/rvv/autovec/binop/vec_sat_u_add-run-10.c | 75 ++
 .../riscv/rvv/autovec/binop/vec_sat_u_add-run-11.c | 75 ++
 .../riscv/rvv/autovec/binop/vec_sat_u_add-run-12.c | 75 ++
 .../riscv/rvv/autovec/binop/vec_sat_u_add-run-9.c  | 75 ++
 9 files changed, 397 insertions(+)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h
index 57b1bce4bd2c..76f393fffbd1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h
@@ -32,12 +32,30 @@ vec_sat_u_add_##T##_fmt_2 (T *out, T *op_1, T *op_2, 
unsigned limit) \
 }\
 }
 
+#define DEF_VEC_SAT_U_ADD_FMT_3(T)   \
+void __attribute__((noinline))   \
+vec_sat_u_add_##T##_fmt_3 (T *out, T *op_1, T *op_2, unsigned limit) \
+{\
+  unsigned i;\
+  for (i = 0; i < limit; i++)\
+{\
+  T x = op_1[i]; \
+  T y = op_2[i]; \
+  T ret; \
+  T overflow = __builtin_add_overflow (x, y, &ret);  \
+  out[i] = (T)(-overflow) | ret; \
+}\
+}
+
 #define RUN_VEC_SAT_U_ADD_FMT_1(T, out, op_1, op_2, N) \
   vec_sat_u_add_##T##_fmt_1(out, op_1, op_2, N)
 
 #define RUN_VEC_SAT_U_ADD_FMT_2(T, out, op_1, op_2, N) \
   vec_sat_u_add_##T##_fmt_2(out, op_1, op_2, N)
 
+#define RUN_VEC_SAT_U_ADD_FMT_3(T, out, op_1, op_2, N) \
+  vec_sat_u_add_##T##_fmt_3(out, op_1, op_2, N)
+
 
/**/
 /* Saturation Sub (Unsigned and Signed)   
*/
 
/

[gcc r15-1428] RISC-V: Add testcases for unsigned .SAT_ADD vector form 4

[Pan Li via Gcc-cvs]

https://gcc.gnu.org/g:24ae0a0a3dea27d8c81f2f102d637cf09424b4b9

commit r15-1428-g24ae0a0a3dea27d8c81f2f102d637cf09424b4b9
Author: Pan Li 
Date:   Mon Jun 17 16:09:13 2024 +0800

RISC-V: Add testcases for unsigned .SAT_ADD vector form 4

After the middle-end support the form 4 of unsigned SAT_ADD and
the RISC-V backend implement the .SAT_ADD for vector mode, add
more test case to cover the form 4.

Form 4:
  #define DEF_VEC_SAT_U_ADD_FMT_4(T)   \
  void __attribute__((noinline))   \
  vec_sat_u_add_##T##_fmt_4 (T *out, T *op_1, T *op_2, unsigned limit) \
  {\
unsigned i;\
for (i = 0; i < limit; i++)\
  {\
T x = op_1[i]; \
T y = op_2[i]; \
T ret; \
out[i] = __builtin_add_overflow (x, y, &ret) ? -1 : ret;   \
  }\
  }

Passed the rv64gcv regression tests.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: Add helper
macro for testing.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-13.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-14.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-15.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-16.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-13.c: New 
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-14.c: New 
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-15.c: New 
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-16.c: New 
test.

Signed-off-by: Pan Li 

Diff:
---
 .../riscv/rvv/autovec/binop/vec_sat_arith.h| 17 +
 .../riscv/rvv/autovec/binop/vec_sat_u_add-13.c | 19 ++
 .../riscv/rvv/autovec/binop/vec_sat_u_add-14.c | 20 ++
 .../riscv/rvv/autovec/binop/vec_sat_u_add-15.c | 20 ++
 .../riscv/rvv/autovec/binop/vec_sat_u_add-16.c | 20 ++
 .../riscv/rvv/autovec/binop/vec_sat_u_add-run-13.c | 75 ++
 .../riscv/rvv/autovec/binop/vec_sat_u_add-run-14.c | 75 ++
 .../riscv/rvv/autovec/binop/vec_sat_u_add-run-15.c | 75 ++
 .../riscv/rvv/autovec/binop/vec_sat_u_add-run-16.c | 75 ++
 9 files changed, 396 insertions(+)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h
index 76f393fffbd1..e00769e35b60 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h
@@ -47,6 +47,20 @@ vec_sat_u_add_##T##_fmt_3 (T *out, T *op_1, T *op_2, 
unsigned limit) \
 }\
 }
 
+#define DEF_VEC_SAT_U_ADD_FMT_4(T)   \
+void __attribute__((noinline))   \
+vec_sat_u_add_##T##_fmt_4 (T *out, T *op_1, T *op_2, unsigned limit) \
+{\
+  unsigned i;\
+  for (i = 0; i < limit; i++)\
+{\
+  T x = op_1[i]; \
+  T y = op_2[i]; \
+  T ret; \
+  out[i] = __builtin_add_overflow (x, y, &ret) ? -1 : ret;   \
+}\
+}
+
 #define RUN_VEC_SAT_U_ADD_FMT_1(T, out, op_1, op_2, N) \
   vec_sat_u_add_##T##_fmt_1(out, op_1, op_2, N)
 
@@ -56,6 +70,9 @@ vec_sat_u_add_##T##_fmt_3 (T *out, T *op_1, T *op_2, unsigned 
limit) \
 #define RUN_VEC_SAT_U_ADD_FMT_3(T, out, op_1, op_2, N) \
   vec_sat_u_add_##T##_fmt_3(out, op_1, op_2, N)
 
+#define RUN_VEC_SAT_U_ADD_FMT_4(T, out, op_1, op_2, N) \
+  vec_sat_u_add_##T##_fmt_4(out, op_1, op_2, N)
+
 
/**/
 /* Saturation Sub (Unsigned and Signed)   
*/
 
/**/
diff --git 
a/gcc/testsuite/gcc.tar

[gcc r15-1429] RISC-V: Add testcases for unsigned .SAT_ADD vector form 5

[Pan Li via Gcc-cvs]

https://gcc.gnu.org/g:1daf54aa7818519b5a1dcc441c8b235d15a8726e

commit r15-1429-g1daf54aa7818519b5a1dcc441c8b235d15a8726e
Author: Pan Li 
Date:   Mon Jun 17 16:31:26 2024 +0800

RISC-V: Add testcases for unsigned .SAT_ADD vector form 5

After the middle-end support the form 5 of unsigned SAT_ADD and
the RISC-V backend implement the .SAT_ADD for vector mode, add
more test case to cover the form 5.

Form 5:
  #define DEF_VEC_SAT_U_ADD_FMT_5(T)   \
  void __attribute__((noinline))   \
  vec_sat_u_add_##T##_fmt_5 (T *out, T *op_1, T *op_2, unsigned limit) \
  {\
unsigned i;\
for (i = 0; i < limit; i++)\
  {\
T x = op_1[i]; \
T y = op_2[i]; \
T ret; \
out[i] = __builtin_add_overflow (x, y, &ret) == 0 ? ret : -1;  \
  }\
  }

Passed the rv64gcv regression tests.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: Add helper
macro for testing.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-17.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-18.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-19.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-20.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-17.c: New 
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-18.c: New 
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-19.c: New 
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-20.c: New 
test.

Signed-off-by: Pan Li 

Diff:
---
 .../riscv/rvv/autovec/binop/vec_sat_arith.h| 17 +
 .../riscv/rvv/autovec/binop/vec_sat_u_add-17.c | 19 ++
 .../riscv/rvv/autovec/binop/vec_sat_u_add-18.c | 20 ++
 .../riscv/rvv/autovec/binop/vec_sat_u_add-19.c | 20 ++
 .../riscv/rvv/autovec/binop/vec_sat_u_add-20.c | 20 ++
 .../riscv/rvv/autovec/binop/vec_sat_u_add-run-17.c | 75 ++
 .../riscv/rvv/autovec/binop/vec_sat_u_add-run-18.c | 75 ++
 .../riscv/rvv/autovec/binop/vec_sat_u_add-run-19.c | 75 ++
 .../riscv/rvv/autovec/binop/vec_sat_u_add-run-20.c | 75 ++
 9 files changed, 396 insertions(+)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h
index e00769e35b60..1f2ee31577dc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h
@@ -61,6 +61,20 @@ vec_sat_u_add_##T##_fmt_4 (T *out, T *op_1, T *op_2, 
unsigned limit) \
 }\
 }
 
+#define DEF_VEC_SAT_U_ADD_FMT_5(T)   \
+void __attribute__((noinline))   \
+vec_sat_u_add_##T##_fmt_5 (T *out, T *op_1, T *op_2, unsigned limit) \
+{\
+  unsigned i;\
+  for (i = 0; i < limit; i++)\
+{\
+  T x = op_1[i]; \
+  T y = op_2[i]; \
+  T ret; \
+  out[i] = __builtin_add_overflow (x, y, &ret) == 0 ? ret : -1;  \
+}\
+}
+
 #define RUN_VEC_SAT_U_ADD_FMT_1(T, out, op_1, op_2, N) \
   vec_sat_u_add_##T##_fmt_1(out, op_1, op_2, N)
 
@@ -73,6 +87,9 @@ vec_sat_u_add_##T##_fmt_4 (T *out, T *op_1, T *op_2, unsigned 
limit) \
 #define RUN_VEC_SAT_U_ADD_FMT_4(T, out, op_1, op_2, N) \
   vec_sat_u_add_##T##_fmt_4(out, op_1, op_2, N)
 
+#define RUN_VEC_SAT_U_ADD_FMT_5(T, out, op_1, op_2, N) \
+  vec_sat_u_add_##T##_fmt_5(out, op_1, op_2, N)
+
 
/**/
 /* Saturation Sub (Unsigned and Signed)   
*/
 
/**/
diff --git 
a/gcc/testsuite/gcc.tar

[gcc r15-1430] RISC-V: Add testcases for unsigned .SAT_ADD vector form 6

[Pan Li via Gcc-cvs]

https://gcc.gnu.org/g:748b9f0a37c448cbe8585cfa8c1b380b4975ba9d

commit r15-1430-g748b9f0a37c448cbe8585cfa8c1b380b4975ba9d
Author: Pan Li 
Date:   Mon Jun 17 22:10:31 2024 +0800

RISC-V: Add testcases for unsigned .SAT_ADD vector form 6

After the middle-end support the form 6 of unsigned SAT_ADD and
the RISC-V backend implement the .SAT_ADD for vector mode, add
more test case to cover the form 6.

Form 6:
  #define DEF_VEC_SAT_U_ADD_FMT_6(T)   \
  void __attribute__((noinline))   \
  vec_sat_u_add_##T##_fmt_6 (T *out, T *op_1, T *op_2, unsigned limit) \
  {\
unsigned i;\
for (i = 0; i < limit; i++)\
  {\
T x = op_1[i]; \
T y = op_2[i]; \
out[i] = x <= (T)(x + y) ? (x + y) : -1;   \
  }\
  }

Passed the rv64gcv regression tests.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: Add helper
macro for testing.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-21.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-22.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-23.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-24.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-21.c: New 
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-22.c: New 
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-23.c: New 
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-24.c: New 
test.

Signed-off-by: Pan Li 

Diff:
---
 .../riscv/rvv/autovec/binop/vec_sat_arith.h| 16 +
 .../riscv/rvv/autovec/binop/vec_sat_u_add-21.c | 19 ++
 .../riscv/rvv/autovec/binop/vec_sat_u_add-22.c | 20 ++
 .../riscv/rvv/autovec/binop/vec_sat_u_add-23.c | 20 ++
 .../riscv/rvv/autovec/binop/vec_sat_u_add-24.c | 20 ++
 .../riscv/rvv/autovec/binop/vec_sat_u_add-run-21.c | 75 ++
 .../riscv/rvv/autovec/binop/vec_sat_u_add-run-22.c | 75 ++
 .../riscv/rvv/autovec/binop/vec_sat_u_add-run-23.c | 75 ++
 .../riscv/rvv/autovec/binop/vec_sat_u_add-run-24.c | 75 ++
 9 files changed, 395 insertions(+)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h
index 1f2ee31577dc..0f08822cbeb7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h
@@ -75,6 +75,19 @@ vec_sat_u_add_##T##_fmt_5 (T *out, T *op_1, T *op_2, 
unsigned limit) \
 }\
 }
 
+#define DEF_VEC_SAT_U_ADD_FMT_6(T)   \
+void __attribute__((noinline))   \
+vec_sat_u_add_##T##_fmt_6 (T *out, T *op_1, T *op_2, unsigned limit) \
+{\
+  unsigned i;\
+  for (i = 0; i < limit; i++)\
+{\
+  T x = op_1[i]; \
+  T y = op_2[i]; \
+  out[i] = x <= (T)(x + y) ? (x + y) : -1;   \
+}\
+}
+
 #define RUN_VEC_SAT_U_ADD_FMT_1(T, out, op_1, op_2, N) \
   vec_sat_u_add_##T##_fmt_1(out, op_1, op_2, N)
 
@@ -90,6 +103,9 @@ vec_sat_u_add_##T##_fmt_5 (T *out, T *op_1, T *op_2, 
unsigned limit) \
 #define RUN_VEC_SAT_U_ADD_FMT_5(T, out, op_1, op_2, N) \
   vec_sat_u_add_##T##_fmt_5(out, op_1, op_2, N)
 
+#define RUN_VEC_SAT_U_ADD_FMT_6(T, out, op_1, op_2, N) \
+  vec_sat_u_add_##T##_fmt_6(out, op_1, op_2, N)
+
 
/**/
 /* Saturation Sub (Unsigned and Signed)   
*/
 
/**/
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-21.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-21.c
new file mode 100644
index 000

[gcc r15-1431] RISC-V: Add testcases for unsigned .SAT_ADD vector form 7

[Pan Li via Gcc-cvs]

https://gcc.gnu.org/g:ed94699eefc7cc8ac8fd79a6d8d81bf05d5a79ff

commit r15-1431-ged94699eefc7cc8ac8fd79a6d8d81bf05d5a79ff
Author: Pan Li 
Date:   Mon Jun 17 22:19:54 2024 +0800

RISC-V: Add testcases for unsigned .SAT_ADD vector form 7

After the middle-end support the form 7 of unsigned SAT_ADD and
the RISC-V backend implement the .SAT_ADD for vector mode, add
more test case to cover the form 7.

Form 7:
  #define DEF_VEC_SAT_U_ADD_FMT_7(T)   \
  void __attribute__((noinline))   \
  vec_sat_u_add_##T##_fmt_7 (T *out, T *op_1, T *op_2, unsigned limit) \
  {\
unsigned i;\
for (i = 0; i < limit; i++)\
  {\
T x = op_1[i]; \
T y = op_2[i]; \
out[i] = (T)(x + y) < x ? -1 : (x + y);\
  }\
  }

Passed the rv64gcv regression tests.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: Add helper
macro for testing.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-25.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-26.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-27.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-28.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-25.c: New 
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-26.c: New 
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-27.c: New 
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-28.c: New 
test.

Signed-off-by: Pan Li 

Diff:
---
 .../riscv/rvv/autovec/binop/vec_sat_arith.h| 16 +
 .../riscv/rvv/autovec/binop/vec_sat_u_add-25.c | 19 ++
 .../riscv/rvv/autovec/binop/vec_sat_u_add-26.c | 20 ++
 .../riscv/rvv/autovec/binop/vec_sat_u_add-27.c | 20 ++
 .../riscv/rvv/autovec/binop/vec_sat_u_add-28.c | 20 ++
 .../riscv/rvv/autovec/binop/vec_sat_u_add-run-25.c | 75 ++
 .../riscv/rvv/autovec/binop/vec_sat_u_add-run-26.c | 75 ++
 .../riscv/rvv/autovec/binop/vec_sat_u_add-run-27.c | 75 ++
 .../riscv/rvv/autovec/binop/vec_sat_u_add-run-28.c | 75 ++
 9 files changed, 395 insertions(+)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h
index 0f08822cbeb7..46fae4555be4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h
@@ -88,6 +88,19 @@ vec_sat_u_add_##T##_fmt_6 (T *out, T *op_1, T *op_2, 
unsigned limit) \
 }\
 }
 
+#define DEF_VEC_SAT_U_ADD_FMT_7(T)   \
+void __attribute__((noinline))   \
+vec_sat_u_add_##T##_fmt_7 (T *out, T *op_1, T *op_2, unsigned limit) \
+{\
+  unsigned i;\
+  for (i = 0; i < limit; i++)\
+{\
+  T x = op_1[i]; \
+  T y = op_2[i]; \
+  out[i] = (T)(x + y) < x ? -1 : (x + y);\
+}\
+}
+
 #define RUN_VEC_SAT_U_ADD_FMT_1(T, out, op_1, op_2, N) \
   vec_sat_u_add_##T##_fmt_1(out, op_1, op_2, N)
 
@@ -106,6 +119,9 @@ vec_sat_u_add_##T##_fmt_6 (T *out, T *op_1, T *op_2, 
unsigned limit) \
 #define RUN_VEC_SAT_U_ADD_FMT_6(T, out, op_1, op_2, N) \
   vec_sat_u_add_##T##_fmt_6(out, op_1, op_2, N)
 
+#define RUN_VEC_SAT_U_ADD_FMT_7(T, out, op_1, op_2, N) \
+  vec_sat_u_add_##T##_fmt_7(out, op_1, op_2, N)
+
 
/**/
 /* Saturation Sub (Unsigned and Signed)   
*/
 
/**/
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-25.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-25.c
new file mode 100644
index 00

[gcc r15-1432] RISC-V: Add testcases for unsigned .SAT_ADD vector form 8

[Pan Li via Gcc-cvs]

https://gcc.gnu.org/g:eb549f13fcde079a7bbe27e5ba3d5e80abbffba1

commit r15-1432-geb549f13fcde079a7bbe27e5ba3d5e80abbffba1
Author: Pan Li 
Date:   Mon Jun 17 22:31:27 2024 +0800

RISC-V: Add testcases for unsigned .SAT_ADD vector form 8

After the middle-end support the form 8 of unsigned SAT_ADD and
the RISC-V backend implement the .SAT_ADD for vector mode, add
more test case to cover the form 8.

Form 8:
  #define DEF_VEC_SAT_U_ADD_FMT_8(T)   \
  void __attribute__((noinline))   \
  vec_sat_u_add_##T##_fmt_8 (T *out, T *op_1, T *op_2, unsigned limit) \
  {\
unsigned i;\
for (i = 0; i < limit; i++)\
  {\
T x = op_1[i]; \
T y = op_2[i]; \
out[i] = x > (T)(x + y) ? -1 : (x + y);\
  }\
  }

Passed the rv64gcv regression tests.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: Add helper
macro for testing.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-29.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-30.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-31.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-32.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-29.c: New 
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-30.c: New 
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-31.c: New 
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-32.c: New 
test.

Signed-off-by: Pan Li 

Diff:
---
 .../riscv/rvv/autovec/binop/vec_sat_arith.h| 16 +
 .../riscv/rvv/autovec/binop/vec_sat_u_add-29.c | 19 ++
 .../riscv/rvv/autovec/binop/vec_sat_u_add-30.c | 20 ++
 .../riscv/rvv/autovec/binop/vec_sat_u_add-31.c | 20 ++
 .../riscv/rvv/autovec/binop/vec_sat_u_add-32.c | 20 ++
 .../riscv/rvv/autovec/binop/vec_sat_u_add-run-29.c | 75 ++
 .../riscv/rvv/autovec/binop/vec_sat_u_add-run-30.c | 75 ++
 .../riscv/rvv/autovec/binop/vec_sat_u_add-run-31.c | 75 ++
 .../riscv/rvv/autovec/binop/vec_sat_u_add-run-32.c | 75 ++
 9 files changed, 395 insertions(+)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h
index 46fae4555be4..443f88261ba0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h
@@ -101,6 +101,19 @@ vec_sat_u_add_##T##_fmt_7 (T *out, T *op_1, T *op_2, 
unsigned limit) \
 }\
 }
 
+#define DEF_VEC_SAT_U_ADD_FMT_8(T)   \
+void __attribute__((noinline))   \
+vec_sat_u_add_##T##_fmt_8 (T *out, T *op_1, T *op_2, unsigned limit) \
+{\
+  unsigned i;\
+  for (i = 0; i < limit; i++)\
+{\
+  T x = op_1[i]; \
+  T y = op_2[i]; \
+  out[i] = x > (T)(x + y) ? -1 : (x + y);\
+}\
+}
+
 #define RUN_VEC_SAT_U_ADD_FMT_1(T, out, op_1, op_2, N) \
   vec_sat_u_add_##T##_fmt_1(out, op_1, op_2, N)
 
@@ -122,6 +135,9 @@ vec_sat_u_add_##T##_fmt_7 (T *out, T *op_1, T *op_2, 
unsigned limit) \
 #define RUN_VEC_SAT_U_ADD_FMT_7(T, out, op_1, op_2, N) \
   vec_sat_u_add_##T##_fmt_7(out, op_1, op_2, N)
 
+#define RUN_VEC_SAT_U_ADD_FMT_8(T, out, op_1, op_2, N) \
+  vec_sat_u_add_##T##_fmt_8(out, op_1, op_2, N)
+
 
/**/
 /* Saturation Sub (Unsigned and Signed)   
*/
 
/**/
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-29.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-29.c
new file mode 100644
index