[Bug rtl-optimization/65067] regression on accessing volatile bit field

2015-02-25 Thread tony.liu at arm dot com
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65067

Tony Liu  changed:

   What|Removed |Added

 CC||tony.liu at arm dot com

--- Comment #5 from Tony Liu  ---
(In reply to Bernd Edlinger from comment #4)
> this does not happen with 4.9.0,
> but I can confirm this behavior with current trunk.

Yes. This does not happen before the revision 216989, which is committed after
4.9.2 release. 
And I think Richard's suggestion is the right way to fix this bug. I'll try my
best to implement the patch.


[Bug rtl-optimization/65067] regression on accessing volatile bit field

2015-03-03 Thread tony.liu at arm dot com
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65067

--- Comment #7 from Tony Liu  ---
(In reply to Bernd Edlinger from comment #6)
> Ok, I think I understand now, what is wrong.
> 
> r216989 did just cause the strict-alignment code path to be executed,
> which was not the case before.
> 
> Actually the extract_bit_field code is also wrong, but the combine pass
> replaces the two instruction sequence and/shift with ubfx, but for the
> store_bit_field the generated code is way too complex for the combine pass.
> 
> 
> So, this would by my first idea, how to fix it:
> 
> 
> Index: expmed.c
> ===
> --- expmed.c  (revision 221087)
> +++ expmed.c  (working copy)
> @@ -1080,6 +1080,15 @@ store_fixed_bit_field_1 (rtx op0, unsigned HOST_WI
>mode = GET_MODE (op0);
>gcc_assert (SCALAR_INT_MODE_P (mode));
>  
> +  if (MEM_P (op0) && bitsize < GET_MODE_BITSIZE (mode))
> +{
> +  temp = copy_to_reg (op0);
> +  store_bit_field_1 (temp, bitsize, bitnum, 0, 0,
> +  mode, value, true);
> +  emit_move_insn (op0, temp);
> +  return;
> +}
> +
>/* Note that bitsize + bitnum can be greater than GET_MODE_BITSIZE (mode)
>   for invalid input, such as f5 from gcc.dg/pr48335-2.c.  */
>  
> @@ -1852,6 +1861,14 @@ extract_fixed_bit_field_1 (machine_mode tmode, rtx
>machine_mode mode = GET_MODE (op0);
>gcc_assert (SCALAR_INT_MODE_P (mode));
>  
> +  if (MEM_P (op0) && bitsize < GET_MODE_BITSIZE (mode))
> +{
> +  op0 = copy_to_reg (op0);
> +  return extract_bit_field_1 (op0, bitsize, bitnum,
> +   unsignedp, target,
> +   mode, tmode, true);
> +}
> +
>/* Note that bitsize + bitnum can be greater than GET_MODE_BITSIZE (mode)
>   for invalid input, such as extract equivalent of f5 from
>   gcc.dg/pr48335-2.c.  */

I've checked your patch on trunk, it works and also passes the regression tests
for target Cortex-M3. It will be very appreciated if you could commit this
patch to trunk. Thank you very much.

[Bug rtl-optimization/65067] regression on accessing volatile bit field

2015-03-04 Thread tony.liu at arm dot com
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65067

--- Comment #9 from Tony Liu  ---
(In reply to Bernd Edlinger from comment #8)
> Created attachment 34955 [details]
> Proposed Fix
> 
> Well, I noticed that the first version of this patch caused
> a small but measurable decrease of code quality on x86_64,
> so I moved the patch to the if (strict_volatile_bitfield_p block,
> and used some code transformations to simplify the resulting code
> a bit.
> 
> I will post this new version for review, after a full boot-strap
> and successful regression-test on my ARM target.

I've tested for target Cortex-M3, no regression.