[Bug target/51819] New: [4.7 Regression ]Neon wrong code generation, Error: unsupported alignment for instruction -- `vst1.32 {d2[0]},[r0:64]'

[thejes.k at gmail dot com]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=51819

 Bug #: 51819
   Summary: [4.7 Regression ]Neon wrong code generation, Error:
unsupported alignment for instruction -- `vst1.32
{d2[0]},[r0:64]'
Classification: Unclassified
   Product: gcc
   Version: 4.7.0
Status: UNCONFIRMED
  Severity: normal
  Priority: P3
 Component: target
AssignedTo: unassig...@gcc.gnu.org
ReportedBy: theje...@gmail.com
Target: arm


With the gcc,
xgcc (4.7.0 20111217 (experimental) 

I tried to compile the code "gcc/testsuite/gcc.dg/vect/vect-double-reduc-6.c"
with neon options as shown below,

Command Line:

$ gcc-4.7-20111217/host-i686-pc-linux-gnu/gcc/xgcc
-B./gcc-4.7-20111217/host-i686-pc-linux-gnu/gcc vect-double-reduc-6.c
-ftree-vectorize -fno-vect-cost-model -ffast-math -O2 -funroll-loops
-fdump-tree-vect-details  -lm  -march=armv7-a -mthumb -mfpu=neon
-mfloat-abi=softfp  -o ./vect-double-reduc-6.exe 

/tmp/ccsaDvPz.s: Assembler messages: 
/tmp/ccsaDvPz.s:132: Error: unsupported alignment for instruction -- `vst1.32
{d2[0]},[r0:64]' 

I could not reproduce this issue with gcc-4.5-20111215 or  gcc-4.6-20111216 .
It seems this issue is caused by the revision 172314
http://gcc.gnu.org/ml/gcc-patches/2011-03/msg01996.html.

This patch is not merged to gcc 4.5 or 4.6 also.

[Bug target/51819] [4.7 Regression] Neon wrong code generation, Error: unsupported alignment for instruction -- `vst1.32 {d2[0]},[r0:64]'

[thejes.k at gmail dot com]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=51819

--- Comment #2 from Thejes Kuttian  2012-01-13 
05:32:48 UTC ---
(In reply to comment #1)
> Completely untested but I think this is the correct fix for this problem. 
> 
> 
> 
> 
> diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
> index 4c310d4..31f03cc 100644
> --- a/gcc/config/arm/arm.c
> +++ b/gcc/config/arm/arm.c
> @@ -17720,7 +17720,7 @@ arm_print_operand (FILE *stream, rtx x, int code)
>   align_bits = 256;
> else if ((memsize == 8 || memsize == 16) && (align % 16) == 0)
>   align_bits = 128;
> -   else if ((align % 8) == 0)
> +   else if ((memsize >= 8) && (align % 8) == 0)
>   align_bits = 64;
> else
>   align_bits = 0;

Confirmed. This patch fixes the issue for me .