[Bug middle-end/50629] [4.7 Regression] FAIL: gcc.c-torture/execute/vect-shuffle-2.c with ICE on ARM

[tema at gcc dot gnu.org]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=50629

Artem Shinkarov  changed:

   What|Removed |Added

 CC||tema at gcc dot gnu.org

--- Comment #1 from Artem Shinkarov  2011-10-10 
11:41:58 UTC ---
These tests are not in the repository anymore.  Please update your sources and
see if the bunch of tests gcc.c.torture/execute/vshuff-* bring any failures.

Thanks,
Artem.

[Bug middle-end/50704] FAIL: gcc.target/i386/warn-vect-op-1.c

[tema at gcc dot gnu.org]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=50704

Artem Shinkarov  changed:

   What|Removed |Added

 CC||tema at gcc dot gnu.org

--- Comment #2 from Artem Shinkarov  2011-10-12 
16:56:59 UTC ---
Ah! It happens because the underlying architecture is 32-bit.  We should run
these tests only on 64-bit architectures to get the correct warnings.  So I'll
add /* { dg-require-effective-target lp64 } */ option.

By the way, is it a correct option to disable running the test on 32-bit archs?


Artem.

[Bug middle-end/50704] FAIL: gcc.target/i386/warn-vect-op-1.c

[tema at gcc dot gnu.org]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=50704

--- Comment #5 from Artem Shinkarov  2011-10-12 
17:03:46 UTC ---
(In reply to comment #4)
> (In reply to comment #3)
> > (In reply to comment #2)
> > > Ah! It happens because the underlying architecture is 32-bit.  We should 
> > > run
> > > these tests only on 64-bit architectures to get the correct warnings.  So 
> > > I'll
> > > add /* { dg-require-effective-target lp64 } */ option.
> > >
> > > By the way, is it a correct option to disable running the test on 32-bit 
> > > archs?
> > > 
> > > 
> > 
> > X86 supports ia32, x32 and lp64.  I think you want to run it for x32 and
> > lp32.
> 
> I meant "x32 and lp64".

So if I want to run the test only on 64-bit architectures, then lp64 is the
correct choice in dg-require-effective-target?

Artem.

[Bug middle-end/50704] FAIL: gcc.target/i386/warn-vect-op-1.c

[tema at gcc dot gnu.org]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=50704

--- Comment #7 from Artem Shinkarov  2011-10-12 
17:45:14 UTC ---
(In reply to comment #6)
> (In reply to comment #5)
> > 
> > So if I want to run the test only on 64-bit architectures, then lp64 is the
> > correct choice in dg-require-effective-target?
> > 
> > Artem.
> 
> x32 also has 64bit registers. You should use
> 
> /* { dg-do compile { target { ! { ia32 } } } } */

I need to make sure that UNITS_PER_WORD is 8 on the architecture I am running
the test.  Is it the case for x32?

Thanks,
Artem.

[Bug middle-end/50716] New: Segmentation fault caused by misaligned vector access

[tema at gcc dot gnu.org]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=50716

 Bug #: 50716
   Summary: Segmentation fault caused by misaligned vector access
Classification: Unclassified
   Product: gcc
   Version: 4.7.0
Status: UNCONFIRMED
  Severity: normal
  Priority: P3
 Component: middle-end
AssignedTo: unassig...@gcc.gnu.org
ReportedBy: t...@gcc.gnu.org


The following code segfaults on i386 + sse targets:

typedef int vec __attribute__((vector_size(16)));
int main ()
{
 int * arr = __builtin_malloc (1024);
 vec *p = (vec *) &arr[1];
 *p = (vec){1, 2, 3, 4};
 return *(char *)p;
}

The problem is that *p = (vec){1,2,3,4} produces aligned move instead of
unaligned.  Most likely this could be reproduced on any target with SIMD
extensions, where aligned move differs from unaligned.

[Bug middle-end/50704] FAIL: gcc.target/i386/warn-vect-op-1.c

[tema at gcc dot gnu.org]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=50704

--- Comment #9 from Artem Shinkarov  2011-10-14 
15:39:56 UTC ---
The problem should be fixed with 179991.  Anyone running 32-bit architectures,
please confirm.